From natebegeman at mac.com Mon Jun 14 00:17:23 2010 From: natebegeman at mac.com (Nate Begeman) Date: Mon, 14 Jun 2010 05:17:23 -0000 Subject: [llvm-commits] [llvm] r105929 - /llvm/trunk/utils/TableGen/NeonEmitter.cpp Message-ID: <20100614051723.DAD232A6C12C@llvm.org> Author: sampo Date: Mon Jun 14 00:17:23 2010 New Revision: 105929 URL: http://llvm.org/viewvc/llvm-project?rev=105929&view=rev Log: Add the last of the SemaChecking-gen code. Modified: llvm/trunk/utils/TableGen/NeonEmitter.cpp Modified: llvm/trunk/utils/TableGen/NeonEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/NeonEmitter.cpp?rev=105929&r1=105928&r2=105929&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/NeonEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/NeonEmitter.cpp Mon Jun 14 00:17:23 2010 @@ -946,6 +946,28 @@ OS << "#endif /* __ARM_NEON_H */\n"; } +static unsigned RangeFromType(StringRef typestr) { + // base type to get the type string for. + bool quad = false, dummy = false; + char type = ClassifyType(typestr, quad, dummy, dummy); + + switch (type) { + case 'c': + return (8 << quad) - 1; + case 'h': + case 's': + return (4 << quad) - 1; + case 'f': + case 'i': + return (2 << quad) - 1; + case 'l': + return (1 << quad) - 1; + default: + throw "unhandled type!"; + break; + } +} + /// runHeader - generate one of three different tables which are used by clang /// to support ARM NEON codegen. By default, this will produce the contents of /// BuiltinsARM.def's NEON section. You may also enable the genSemaTypes or @@ -1020,11 +1042,32 @@ } if (genSemaRange) { - if (Proto.find('s') == std::string::npos) + std::string namestr, shiftstr, rangestr; + + // Builtins which are overloaded by type will need to have their upper + // bound computed at Sema time based on the type constant. + if (Proto.find('s') == std::string::npos) { ck = ClassB; + if (R->getValueAsBit("isShift")) { + shiftstr = ", true"; + + // Right shifts have an 'r' in the name, left shifts do not. + if (name.find('r') != std::string::npos) + rangestr = "l = 1; "; + } + rangestr += "u = RFT(TV" + shiftstr + ")"; + } else { + rangestr = "u = " + utostr(RangeFromType(TypeVec[ti])); + } + // Make sure cases appear only once. + namestr = MangleName(name, TypeVec[ti], ck); + if (EmittedMap.count(namestr)) + continue; + EmittedMap[namestr] = OpNone; OS << "case ARM::BI__builtin_neon_" - << MangleName(name, TypeVec[ti], ck) << "\n"; + << MangleName(name, TypeVec[ti], ck) << ": i = " << Proto.find('i')-1 + << "; " << rangestr << "; break;\n"; continue; } From clattner at apple.com Mon Jun 14 00:50:38 2010 From: clattner at apple.com (Chris Lattner) Date: Sun, 13 Jun 2010 22:50:38 -0700 Subject: [llvm-commits] [patch] Implement a pass to instrument function entry and exit In-Reply-To: <87wru2k1kk.fsf@mit.edu> References: <87zkz9q6ta.fsf@mit.edu> <7E610534-74CD-4454-8494-3E49CC0EC7A9@apple.com> <87wru2k1kk.fsf@mit.edu> Message-ID: On Jun 13, 2010, at 3:30 PM, Nelson Elhage wrote: >> >> However, backing up a little bit, I'm not sure I understand this from the GCC man page: >> >> "This instrumentation is also done for functions expanded inline in other functions." >> >> Does that mean that *all* source-level function (that don't have the >> no_instrument_function attribute) get instrumented, even if they get >> inlined etc? > > That's correct. > > (As of GCC 4, there is a complication, which is that as of GCC 4, > inlined functions call __cyg_profile_* with the address and caller of > the function _they were inlined into_, instead of passing the address of > the non-inlined version of the function. (See > http://gcc.gnu.org/bugzilla/show_bug.cgi?id=23296). I'm not sure whether > we want to duplicate the GCC behavior, which I and at least two others > find confusing (http://gcc.gnu.org/bugzilla/show_bug.cgi?id=28205), or > do something else. But in any case, yes, all source-level functions get > instrumented). Yeah, that sounds like a bug. >> If so, then I think this entire thing can be handled in the Clang IR >> generation routines, not needing LLVM IR attributes and not needing an >> LLVM IR pass. >> >> What do you think? > > What do you see as the advantage to handling this from clang, instead of > as an LLVM IR pass? My intuition would be that making this an IR pass is > desirable because you might want to instrument code generated by > something other than clang, but I don't yet have a strong feel for the > overall architecture and where the clang/LLVM split is. My main aim is to reduce complexity in LLVM IR. Adding another attribute just for this would introduce complexity that doesn't seem essential to the task of describing the program. Because of that, if possible, I'd prefer to handle this in clang directly. Thanks again for working on this! -Chris From clattner at apple.com Mon Jun 14 00:54:09 2010 From: clattner at apple.com (Chris Lattner) Date: Sun, 13 Jun 2010 22:54:09 -0700 Subject: [llvm-commits] [llvm] r105303 - /llvm/trunk/lib/Target/X86/README-X86-64.txt In-Reply-To: References: <20100602001036.832CB312800A@llvm.org> <4012A8C4-CE99-4592-8E65-B0C77127763D@apple.com> Message-ID: <8EF849BD-AADA-411D-991B-6526110EC198@apple.com> On Jun 12, 2010, at 6:46 PM, Eli Friedman wrote: >>> -It jumps over the movaps that do not need to be stored. Hard to see this being >>> -significant as it added 5 instruciton (including a indirect branch) to avoid >>> -executing 0 to 8 stores in the function prologue. >>> - >>> -Perhaps we can optimize for the common case where no XMM registers are used for >>> -parameter passing. i.e. is %al == 0 jump over all stores. Or in the case of a >>> -leaf function where we can determine that no XMM input parameter is need, avoid >>> -emitting the stores at all. > > We have a jump over the stores if %al == 0. I guess we don't try to > detect the case where no floats are passed to va_arg, but that's > practically impossible without large changes to the way we lower > va_arg to IR. GCC does an indirect jump to get exactly the number of restores needed, llvm always does 0 or all of them. I don't know of this is really important or not. Incidentally, GCC does a very nice optimization when it can tell that all the va_args calls are of non-vector/fp types and when the a va_list doesn't escape from a function: it doesn't save the fp/vector registers. It seems that the llvm optimizer could determine this and capture the classes of va_arg'd stuff in an extra argument to llvm.vastart or something. This is a pretty big win in stuff like this: void test(int x, ...) { } GCC compiles this to an empty function, we... don't. IIRC, the original justification for this was in functions like libc's "open". >>> -For problem 4, the parameter 'd' would be moved to the front of the parameter >>> -list so it will be passed in register: >>> - void %test(int %d, >>> - long %undef1, long %undef2, long %undef3, long %undef4, >>> - long %undef5, long %undef6, >>> - long %s.i, byte %s.j, long %s.d); >>> - > > I'm pretty sure argument passing on x86-64 works. :) And we have a > bug on adding an ABI-lowering library to LLVM. Ah ok. We still do many things that are terrible for code quality, but if this was about correctness, I'm all for removing it. Thanks Eli! -Chris From echristo at apple.com Mon Jun 14 01:03:16 2010 From: echristo at apple.com (Eric Christopher) Date: Mon, 14 Jun 2010 06:03:16 -0000 Subject: [llvm-commits] [llvm] r105932 - in /llvm/trunk/examples/Kaleidoscope: Chapter4/toy.cpp Chapter5/toy.cpp Chapter6/toy.cpp Chapter7/toy.cpp Message-ID: <20100614060317.0C89E2A6C12C@llvm.org> Author: echristo Date: Mon Jun 14 01:03:16 2010 New Revision: 105932 URL: http://llvm.org/viewvc/llvm-project?rev=105932&view=rev Log: Make kaleidoscope use fp add/sub/mul. Patch by Patrick Flannery! Modified: llvm/trunk/examples/Kaleidoscope/Chapter4/toy.cpp llvm/trunk/examples/Kaleidoscope/Chapter5/toy.cpp llvm/trunk/examples/Kaleidoscope/Chapter6/toy.cpp llvm/trunk/examples/Kaleidoscope/Chapter7/toy.cpp Modified: llvm/trunk/examples/Kaleidoscope/Chapter4/toy.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/Kaleidoscope/Chapter4/toy.cpp?rev=105932&r1=105931&r2=105932&view=diff ============================================================================== --- llvm/trunk/examples/Kaleidoscope/Chapter4/toy.cpp (original) +++ llvm/trunk/examples/Kaleidoscope/Chapter4/toy.cpp Mon Jun 14 01:03:16 2010 @@ -374,9 +374,9 @@ if (L == 0 || R == 0) return 0; switch (Op) { - case '+': return Builder.CreateAdd(L, R, "addtmp"); - case '-': return Builder.CreateSub(L, R, "subtmp"); - case '*': return Builder.CreateMul(L, R, "multmp"); + case '+': return Builder.CreateFAdd(L, R, "addtmp"); + case '-': return Builder.CreateFSub(L, R, "subtmp"); + case '*': return Builder.CreateFMul(L, R, "multmp"); case '<': L = Builder.CreateFCmpULT(L, R, "cmptmp"); // Convert bool 0/1 to double 0.0 or 1.0 Modified: llvm/trunk/examples/Kaleidoscope/Chapter5/toy.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/Kaleidoscope/Chapter5/toy.cpp?rev=105932&r1=105931&r2=105932&view=diff ============================================================================== --- llvm/trunk/examples/Kaleidoscope/Chapter5/toy.cpp (original) +++ llvm/trunk/examples/Kaleidoscope/Chapter5/toy.cpp Mon Jun 14 01:03:16 2010 @@ -475,9 +475,9 @@ if (L == 0 || R == 0) return 0; switch (Op) { - case '+': return Builder.CreateAdd(L, R, "addtmp"); - case '-': return Builder.CreateSub(L, R, "subtmp"); - case '*': return Builder.CreateMul(L, R, "multmp"); + case '+': return Builder.CreateFAdd(L, R, "addtmp"); + case '-': return Builder.CreateFSub(L, R, "subtmp"); + case '*': return Builder.CreateFMul(L, R, "multmp"); case '<': L = Builder.CreateFCmpULT(L, R, "cmptmp"); // Convert bool 0/1 to double 0.0 or 1.0 Modified: llvm/trunk/examples/Kaleidoscope/Chapter6/toy.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/Kaleidoscope/Chapter6/toy.cpp?rev=105932&r1=105931&r2=105932&view=diff ============================================================================== --- llvm/trunk/examples/Kaleidoscope/Chapter6/toy.cpp (original) +++ llvm/trunk/examples/Kaleidoscope/Chapter6/toy.cpp Mon Jun 14 01:03:16 2010 @@ -571,9 +571,9 @@ if (L == 0 || R == 0) return 0; switch (Op) { - case '+': return Builder.CreateAdd(L, R, "addtmp"); - case '-': return Builder.CreateSub(L, R, "subtmp"); - case '*': return Builder.CreateMul(L, R, "multmp"); + case '+': return Builder.CreateFAdd(L, R, "addtmp"); + case '-': return Builder.CreateFSub(L, R, "subtmp"); + case '*': return Builder.CreateFMul(L, R, "multmp"); case '<': L = Builder.CreateFCmpULT(L, R, "cmptmp"); // Convert bool 0/1 to double 0.0 or 1.0 Modified: llvm/trunk/examples/Kaleidoscope/Chapter7/toy.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/Kaleidoscope/Chapter7/toy.cpp?rev=105932&r1=105931&r2=105932&view=diff ============================================================================== --- llvm/trunk/examples/Kaleidoscope/Chapter7/toy.cpp (original) +++ llvm/trunk/examples/Kaleidoscope/Chapter7/toy.cpp Mon Jun 14 01:03:16 2010 @@ -667,9 +667,9 @@ if (L == 0 || R == 0) return 0; switch (Op) { - case '+': return Builder.CreateAdd(L, R, "addtmp"); - case '-': return Builder.CreateSub(L, R, "subtmp"); - case '*': return Builder.CreateMul(L, R, "multmp"); + case '+': return Builder.CreateFAdd(L, R, "addtmp"); + case '-': return Builder.CreateFSub(L, R, "subtmp"); + case '*': return Builder.CreateFMul(L, R, "multmp"); case '<': L = Builder.CreateFCmpULT(L, R, "cmptmp"); // Convert bool 0/1 to double 0.0 or 1.0 From echristo at apple.com Mon Jun 14 01:09:39 2010 From: echristo at apple.com (Eric Christopher) Date: Mon, 14 Jun 2010 06:09:39 -0000 Subject: [llvm-commits] [llvm] r105933 - in /llvm/trunk/docs/tutorial: LangImpl3.html LangImpl4.html LangImpl5.html LangImpl6.html LangImpl7.html Message-ID: <20100614060940.1990D2A6C12C@llvm.org> Author: echristo Date: Mon Jun 14 01:09:39 2010 New Revision: 105933 URL: http://llvm.org/viewvc/llvm-project?rev=105933&view=rev Log: Update html tutorial docs to match api changes. Modified: llvm/trunk/docs/tutorial/LangImpl3.html llvm/trunk/docs/tutorial/LangImpl4.html llvm/trunk/docs/tutorial/LangImpl5.html llvm/trunk/docs/tutorial/LangImpl6.html llvm/trunk/docs/tutorial/LangImpl7.html Modified: llvm/trunk/docs/tutorial/LangImpl3.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/tutorial/LangImpl3.html?rev=105933&r1=105932&r2=105933&view=diff ============================================================================== --- llvm/trunk/docs/tutorial/LangImpl3.html (original) +++ llvm/trunk/docs/tutorial/LangImpl3.html Mon Jun 14 01:09:39 2010 @@ -200,9 +200,9 @@ if (L == 0 || R == 0) return 0; switch (Op) { - case '+': return Builder.CreateAdd(L, R, "addtmp"); - case '-': return Builder.CreateSub(L, R, "subtmp"); - case '*': return Builder.CreateMul(L, R, "multmp"); + case '+': return Builder.CreateFAdd(L, R, "addtmp"); + case '-': return Builder.CreateFSub(L, R, "subtmp"); + case '*': return Builder.CreateFMul(L, R, "multmp"); case '<': L = Builder.CreateFCmpULT(L, R, "cmptmp"); // Convert bool 0/1 to double 0.0 or 1.0 Modified: llvm/trunk/docs/tutorial/LangImpl4.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/tutorial/LangImpl4.html?rev=105933&r1=105932&r2=105933&view=diff ============================================================================== --- llvm/trunk/docs/tutorial/LangImpl4.html (original) +++ llvm/trunk/docs/tutorial/LangImpl4.html Mon Jun 14 01:09:39 2010 @@ -876,9 +876,9 @@ if (L == 0 || R == 0) return 0; switch (Op) { - case '+': return Builder.CreateAdd(L, R, "addtmp"); - case '-': return Builder.CreateSub(L, R, "subtmp"); - case '*': return Builder.CreateMul(L, R, "multmp"); + case '+': return Builder.CreateFAdd(L, R, "addtmp"); + case '-': return Builder.CreateFSub(L, R, "subtmp"); + case '*': return Builder.CreateFMul(L, R, "multmp"); case '<': L = Builder.CreateFCmpULT(L, R, "cmptmp"); // Convert bool 0/1 to double 0.0 or 1.0 Modified: llvm/trunk/docs/tutorial/LangImpl5.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/tutorial/LangImpl5.html?rev=105933&r1=105932&r2=105933&view=diff ============================================================================== --- llvm/trunk/docs/tutorial/LangImpl5.html (original) +++ llvm/trunk/docs/tutorial/LangImpl5.html Mon Jun 14 01:09:39 2010 @@ -1377,9 +1377,9 @@ if (L == 0 || R == 0) return 0; switch (Op) { - case '+': return Builder.CreateAdd(L, R, "addtmp"); - case '-': return Builder.CreateSub(L, R, "subtmp"); - case '*': return Builder.CreateMul(L, R, "multmp"); + case '+': return Builder.CreateFAdd(L, R, "addtmp"); + case '-': return Builder.CreateFSub(L, R, "subtmp"); + case '*': return Builder.CreateFMul(L, R, "multmp"); case '<': L = Builder.CreateFCmpULT(L, R, "cmptmp"); // Convert bool 0/1 to double 0.0 or 1.0 Modified: llvm/trunk/docs/tutorial/LangImpl6.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/tutorial/LangImpl6.html?rev=105933&r1=105932&r2=105933&view=diff ============================================================================== --- llvm/trunk/docs/tutorial/LangImpl6.html (original) +++ llvm/trunk/docs/tutorial/LangImpl6.html Mon Jun 14 01:09:39 2010 @@ -277,9 +277,9 @@ if (L == 0 || R == 0) return 0; switch (Op) { - case '+': return Builder.CreateAdd(L, R, "addtmp"); - case '-': return Builder.CreateSub(L, R, "subtmp"); - case '*': return Builder.CreateMul(L, R, "multmp"); + case '+': return Builder.CreateFAdd(L, R, "addtmp"); + case '-': return Builder.CreateFSub(L, R, "subtmp"); + case '*': return Builder.CreateFMul(L, R, "multmp"); case '<': L = Builder.CreateFCmpULT(L, R, "cmptmp"); // Convert bool 0/1 to double 0.0 or 1.0 @@ -1392,9 +1392,9 @@ if (L == 0 || R == 0) return 0; switch (Op) { - case '+': return Builder.CreateAdd(L, R, "addtmp"); - case '-': return Builder.CreateSub(L, R, "subtmp"); - case '*': return Builder.CreateMul(L, R, "multmp"); + case '+': return Builder.CreateFAdd(L, R, "addtmp"); + case '-': return Builder.CreateFSub(L, R, "subtmp"); + case '*': return Builder.CreateFMul(L, R, "multmp"); case '<': L = Builder.CreateFCmpULT(L, R, "cmptmp"); // Convert bool 0/1 to double 0.0 or 1.0 Modified: llvm/trunk/docs/tutorial/LangImpl7.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/tutorial/LangImpl7.html?rev=105933&r1=105932&r2=105933&view=diff ============================================================================== --- llvm/trunk/docs/tutorial/LangImpl7.html (original) +++ llvm/trunk/docs/tutorial/LangImpl7.html Mon Jun 14 01:09:39 2010 @@ -1672,9 +1672,9 @@ if (L == 0 || R == 0) return 0; switch (Op) { - case '+': return Builder.CreateAdd(L, R, "addtmp"); - case '-': return Builder.CreateSub(L, R, "subtmp"); - case '*': return Builder.CreateMul(L, R, "multmp"); + case '+': return Builder.CreateFAdd(L, R, "addtmp"); + case '-': return Builder.CreateFSub(L, R, "subtmp"); + case '*': return Builder.CreateFMul(L, R, "multmp"); case '<': L = Builder.CreateFCmpULT(L, R, "cmptmp"); // Convert bool 0/1 to double 0.0 or 1.0 From eli.friedman at gmail.com Mon Jun 14 02:03:30 2010 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 14 Jun 2010 07:03:30 -0000 Subject: [llvm-commits] [llvm] r105934 - /llvm/trunk/lib/Target/X86/README-X86-64.txt Message-ID: <20100614070330.75A652A6C12C@llvm.org> Author: efriedma Date: Mon Jun 14 02:03:30 2010 New Revision: 105934 URL: http://llvm.org/viewvc/llvm-project?rev=105934&view=rev Log: Add back some possible optimizations for va_arg, with wording that makes it more clear what exactly is missing. Modified: llvm/trunk/lib/Target/X86/README-X86-64.txt Modified: llvm/trunk/lib/Target/X86/README-X86-64.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/README-X86-64.txt?rev=105934&r1=105933&r2=105934&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/README-X86-64.txt (original) +++ llvm/trunk/lib/Target/X86/README-X86-64.txt Mon Jun 14 02:03:30 2010 @@ -240,3 +240,34 @@ expensive addressing mode. //===---------------------------------------------------------------------===// + +Consider the following (contrived testcase, but contains common factors): + +#include +int test(int x, ...) { + int sum, i; + va_list l; + va_start(l, x); + for (i = 0; i < x; i++) + sum += va_arg(l, int); + va_end(l); + return sum; +} + +Testcase given in C because fixing it will likely involve changing the IR +generated for it. The primary issue with the result is that it doesn't do any +of the optimizations which are possible if we know the address of a va_list +in the current function is never taken: +1. We shouldn't spill the XMM registers because we only call va_arg with "int". +2. It would be nice if we could scalarrepl the va_list. +3. Probably overkill, but it'd be cool if we could peel off the first five +iterations of the loop. + +Other optimizations involving functions which use va_arg on floats which don't +have the address of a va_list taken: +1. Conversely to the above, we shouldn't spill general registers if we only + call va_arg on "double". +2. If we know nothing more than 64 bits wide is read from the XMM registers, + we can change the spilling code to reduce the amount of stack used by half. + +//===---------------------------------------------------------------------===// From eli.friedman at gmail.com Mon Jun 14 02:11:09 2010 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 14 Jun 2010 00:11:09 -0700 Subject: [llvm-commits] [llvm] r105303 - /llvm/trunk/lib/Target/X86/README-X86-64.txt In-Reply-To: <8EF849BD-AADA-411D-991B-6526110EC198@apple.com> References: <20100602001036.832CB312800A@llvm.org> <4012A8C4-CE99-4592-8E65-B0C77127763D@apple.com> <8EF849BD-AADA-411D-991B-6526110EC198@apple.com> Message-ID: On Sun, Jun 13, 2010 at 10:54 PM, Chris Lattner wrote: > > On Jun 12, 2010, at 6:46 PM, Eli Friedman wrote: > >>>> -It jumps over the movaps that do not need to be stored. Hard to see this being >>>> -significant as it added 5 instruciton (including a indirect branch) to avoid >>>> -executing 0 to 8 stores in the function prologue. >>>> - >>>> -Perhaps we can optimize for the common case where no XMM registers are used for >>>> -parameter passing. i.e. is %al == 0 jump over all stores. Or in the case of a >>>> -leaf function where we can determine that no XMM input parameter is need, avoid >>>> -emitting the stores at all. >> >> We have a jump over the stores if %al == 0. ?I guess we don't try to >> detect the case where no floats are passed to va_arg, but that's >> practically impossible without large changes to the way we lower >> va_arg to IR. > > GCC does an indirect jump to get exactly the number of restores needed, llvm always does 0 or all of them. ?I don't know of this is really important or not. > > Incidentally, GCC does a very nice optimization when it can tell that all the va_args calls are of non-vector/fp types and when the a va_list doesn't escape from a function: it doesn't save the fp/vector registers. > > It seems that the llvm optimizer could determine this and capture the classes of va_arg'd stuff in an extra argument to llvm.vastart or something. ?This is a pretty big win in stuff like this: > > void test(int x, ...) { > } > > GCC compiles this to an empty function, we... don't. ?IIRC, the original justification for this was in functions like libc's "open". Added some va_arg optimization stuff in r105934; I don't think the old entry was very clear, so I rewrote it from scratch. >>>> -For problem 4, the parameter 'd' would be moved to the front of the parameter >>>> -list so it will be passed in register: >>>> - ? ?void %test(int %d, >>>> - ? ? ? ? ? ? ? long %undef1, long %undef2, long %undef3, long %undef4, >>>> - ? ? ? ? ? ? ? long %undef5, long %undef6, >>>> - ? ? ? ? ? ? ? long %s.i, byte %s.j, long %s.d); >>>> - >> >> I'm pretty sure argument passing on x86-64 works. :) ?And we have a >> bug on adding an ABI-lowering library to LLVM. > > Ah ok. ?We still do many things that are terrible for code quality, but if this was about correctness, I'm all for removing it. ?Thanks Eli! Hmm, all I can find is http://llvm.org/bugs/show_bug.cgi?id=6194 and a README entry; are there code-quality issues for anything other than structs with floats in XMM registers? -Eli From dimitry at andric.com Mon Jun 14 06:21:46 2010 From: dimitry at andric.com (Dimitry Andric) Date: Mon, 14 Jun 2010 13:21:46 +0200 Subject: [llvm-commits] [llvm] r105786 - in /llvm/trunk/include/llvm: ADT/DenseMap.h ADT/SmallVector.h ADT/ilist.h Use.h In-Reply-To: <20100610101358.943472A6C12C@llvm.org> References: <20100610101358.943472A6C12C@llvm.org> Message-ID: <4C1610CA.7020609@andric.com> On 2010-06-10 12:13, Duncan Sands wrote: > Author: baldrick > Date: Thu Jun 10 05:13:58 2010 > New Revision: 105786 > > URL: http://llvm.org/viewvc/llvm-project?rev=105786&view=rev > Log: > Add includes to get ptrdiff_t. This is needed by gcc-4.6 which has > done some more header trimming, resulting in cstdef being included > by less header files. Compiling on my FreeBSD box with gcc 4.6.0 20100605 gave an additional complaint about NULL not being defined in ARMConstantPoolValue.h, and another few about ptrdiff_t in clang. These are all fixed by the attached patches; please review. -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: gcc46-llvm-fixes.diff Url: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100614/5b4a6d55/attachment.pl -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: gcc46-clang-fixes.diff Url: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100614/5b4a6d55/attachment-0001.pl From vputkine at cs.hut.fi Mon Jun 14 09:56:34 2010 From: vputkine at cs.hut.fi (Visa Putkinen) Date: Mon, 14 Jun 2010 17:56:34 +0300 Subject: [llvm-commits] Buggy SelectionDAG binop vector widening In-Reply-To: <13CA807A-F47C-42F4-ABB4-58EB544226D9@apple.com> References: <20100603132756.GA30866@cc.hut.fi> <86CAA4FC-4CE3-4E7E-B0A4-58DE974B9176@apple.com> <20100608092644.GB30866@cc.hut.fi> <097373B3-998A-4F32-8688-AF7CB8271F35@apple.com> <4C0F3563.1040702@free.fr> <13CA807A-F47C-42F4-ABB4-58EB544226D9@apple.com> Message-ID: <20100614145634.GE30776@cc.hut.fi> Hi! Sorry for the long delay. On Wed, Jun 09, 2010 at 11:25:20PM -0700, Mon Ping Wang wrote: > All the occurrences in widening should use isTypeLegal should be updated to use isTypeSynthesizable but I can do that update if you prefer after this patch is in. I replaced all isTypeLegals with isTypeSynthesizable in LegalizeVectorTypes.cpp to spare you the trouble. > Looking at the changes, it overall looks good. The code now separates the code that breaks the vector into synthesizable types with where it recombines it. I think we can simplify the code during the recombine step > while (true) { > bool wrongTypeInConcatOps = false; > for (Idx = ConcatEnd - 1; Idx >= 0; Idx--) { > if (ConcatOps[Idx].getValueType() != MaxVT) { > wrongTypeInConcatOps = true; > break; > } > } > if(!wrongTypeInConcatOps) > break; > ... > } > > When we split the vector into synthesizable types, we go form largest to smallest. If the last piece is the list of operations we want to concatenate is MaxVT, I believe every other piece must be MaxVT so we don't need the loop. I think we can get rid of the for loop and we can move the condition into the while. A very good observation! I didn't like the clumsy for loop either, so good riddance. I implemented your suggestion and it does work: with the patch (against r105937) llc produces correct code from 'fdiv %a, %b' for x86-64 for vector lengths 1-32. The updated patch is attached. Two DejaGNU test cases are also included in the patch. -- Visa Putkinen // vputkine at cs.hut.fi -------------- next part -------------- A non-text attachment was scrubbed... Name: vector-binop-widen.patch Type: text/x-diff Size: 10529 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100614/c415f97e/attachment.bin From clattner at apple.com Mon Jun 14 10:59:48 2010 From: clattner at apple.com (Chris Lattner) Date: Mon, 14 Jun 2010 08:59:48 -0700 Subject: [llvm-commits] [llvm] r105303 - /llvm/trunk/lib/Target/X86/README-X86-64.txt In-Reply-To: References: <20100602001036.832CB312800A@llvm.org> <4012A8C4-CE99-4592-8E65-B0C77127763D@apple.com> <8EF849BD-AADA-411D-991B-6526110EC198@apple.com> Message-ID: <2664E4B7-9A05-431D-BA9A-33FA13E66922@apple.com> On Jun 14, 2010, at 12:11 AM, Eli Friedman wrote: >> >> GCC compiles this to an empty function, we... don't. IIRC, the original justification for this was in functions like libc's "open". > > Added some va_arg optimization stuff in r105934; I don't think the old > entry was very clear, so I rewrote it from scratch. Thanks! >>>>> -For problem 4, the parameter 'd' would be moved to the front of the parameter >>>>> -list so it will be passed in register: >>>>> - void %test(int %d, >>>>> - long %undef1, long %undef2, long %undef3, long %undef4, >>>>> - long %undef5, long %undef6, >>>>> - long %s.i, byte %s.j, long %s.d); >>>>> - >>> >>> I'm pretty sure argument passing on x86-64 works. :) And we have a >>> bug on adding an ABI-lowering library to LLVM. >> >> Ah ok. We still do many things that are terrible for code quality, but if this was about correctness, I'm all for removing it. Thanks Eli! > > Hmm, all I can find is http://llvm.org/bugs/show_bug.cgi?id=6194 and a > README entry; are there code-quality issues for anything other than > structs with floats in XMM registers? The biggest ones are that clang (for example) compiles these functions into gross IR: struct foo { float a, b, c, d }; struct StringRef { char *X; long len; }; struct foo test1(float a) { struct foo r; r.a = r.b = r.c = r.d = a; return r; } void test2a(struct StringRef X); void test2(struct StringRef *X) { test2a(*X); } $ clang t.c -S -o - -emit-llvm -O target triple = "x86_64-apple-darwin10.0.0" %0 = type { double, double } %1 = type { i64, i64 } %struct.StringRef = type { i8*, i64 } define %0 @test1(float %a) nounwind readnone ssp { entry: %tmp29 = bitcast float %a to i32 ; [#uses=1] %tmp30 = zext i32 %tmp29 to i128 ; [#uses=4] %tmp25 = shl i128 %tmp30, 32 ; [#uses=1] %ins27 = or i128 %tmp25, %tmp30 ; [#uses=1] %tmp19 = shl i128 %tmp30, 64 ; [#uses=1] %tmp15 = shl i128 %tmp30, 96 ; [#uses=1] %ins = or i128 %tmp19, %tmp15 ; [#uses=1] %tmp34 = trunc i128 %ins27 to i64 ; [#uses=1] %tmp35 = bitcast i64 %tmp34 to double ; [#uses=1] %tmp36 = insertvalue %0 undef, double %tmp35, 0 ; <%0> [#uses=1] %tmp37 = lshr i128 %ins, 64 ; [#uses=1] %tmp38 = trunc i128 %tmp37 to i64 ; [#uses=1] %tmp39 = bitcast i64 %tmp38 to double ; [#uses=1] %tmp40 = insertvalue %0 %tmp36, double %tmp39, 1 ; <%0> [#uses=1] ret %0 %tmp40 } define void @test2(%struct.StringRef* nocapture %X) nounwind ssp { entry: %0 = bitcast %struct.StringRef* %X to i128* ; [#uses=1] %srcval = load i128* %0, align 8 ; [#uses=2] %tmp3 = trunc i128 %srcval to i64 ; [#uses=1] %tmp4 = insertvalue %1 undef, i64 %tmp3, 0 ; <%1> [#uses=1] %tmp5 = lshr i128 %srcval, 64 ; [#uses=1] %tmp6 = trunc i128 %tmp5 to i64 ; [#uses=1] %tmp7 = insertvalue %1 %tmp4, i64 %tmp6, 1 ; <%1> [#uses=1] tail call void @test2a(%1 %tmp7) nounwind noredzone ret void } declare void @test2a(%1) The former should compile into something that returns two <4 x float>'s and insertelement 'a' into the low two elements of each. This would give us a few shuffles instead of this gross code: _test1: ## @test1 ## BB#0: ## %entry movd %xmm0, %eax movq %rax, %rcx shlq $32, %rcx addq %rax, %rcx movd %rcx, %xmm0 movapd %xmm0, %xmm1 ret test2 should pass around stringref as {i8*, i64} not an {i64,i64}. The gyrations it goes through makes the inliner's life harder. -Chris From bob.wilson at apple.com Mon Jun 14 12:56:25 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Mon, 14 Jun 2010 17:56:25 -0000 Subject: [llvm-commits] [llvm] r105938 - /llvm/trunk/utils/buildit/build_llvm Message-ID: <20100614175625.D2E6F2A6C12C@llvm.org> Author: bwilson Date: Mon Jun 14 12:56:25 2010 New Revision: 105938 URL: http://llvm.org/viewvc/llvm-project?rev=105938&view=rev Log: Honor the SDKROOT setting when building llvm. Radar 7894069. Modified: llvm/trunk/utils/buildit/build_llvm Modified: llvm/trunk/utils/buildit/build_llvm URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/buildit/build_llvm?rev=105938&r1=105937&r2=105938&view=diff ============================================================================== --- llvm/trunk/utils/buildit/build_llvm (original) +++ llvm/trunk/utils/buildit/build_llvm Mon Jun 14 12:56:25 2010 @@ -66,7 +66,6 @@ DEVELOPER_DIR="${DEVELOPER_DIR-Developer}" if [ "$ARM_HOSTED_BUILD" = yes ]; then DT_HOME="$DEST_DIR/usr" - HOST_SDKROOT=$SDKROOT else DT_HOME="$DEST_DIR/$DEVELOPER_DIR/usr" fi @@ -195,7 +194,7 @@ fi make $JOBS_FLAG $OPTIMIZE_OPTS UNIVERSAL=1 UNIVERSAL_ARCH="$HOSTS" \ - UNIVERSAL_SDK_PATH=$HOST_SDKROOT \ + UNIVERSAL_SDK_PATH=$SDKROOT \ NO_RUNTIME_LIBS=1 \ DISABLE_EDIS=1 \ LLVM_SUBMIT_VERSION=$LLVM_SUBMIT_VERSION \ From stuart at apple.com Mon Jun 14 13:27:41 2010 From: stuart at apple.com (Stuart Hastings) Date: Mon, 14 Jun 2010 18:27:41 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r105941 - /llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/block-bad-ivar-access.C Message-ID: <20100614182741.402972A6C12C@llvm.org> Author: stuart Date: Mon Jun 14 13:27:41 2010 New Revision: 105941 URL: http://llvm.org/viewvc/llvm-project?rev=105941&view=rev Log: Commit a mislaid test case for Radar 7901648. Added: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/block-bad-ivar-access.C Added: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/block-bad-ivar-access.C URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/block-bad-ivar-access.C?rev=105941&view=auto ============================================================================== --- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/block-bad-ivar-access.C (added) +++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/block-bad-ivar-access.C Mon Jun 14 13:27:41 2010 @@ -0,0 +1,25 @@ +/* APPLE LOCAL file 7901648 */ +/* { dg-do compile } */ +/* { dg-options "-mmacosx-version-min=10.5 -ObjC++ -fblocks" } */ + + + at interface Foo { + int x; + int y; +} + at end + +void fee(int); + + at implementation Foo ++ (int)method { + ^{ x = 1; /* { dg-error "instance variable \\'x\\' accessed in class method" } */ + /* { dg-error "was not declared" "" { target *-*-* } 16 } */ + x = + y+1; /* { dg-error "instance variable \\'y\\' accessed in class method" } */ + /* { dg-error "was not declared" "" { target *-*-* } 19 } */ + fee(x); + return x; }; +} + at end + From sabre at nondot.org Mon Jun 14 13:28:34 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 14 Jun 2010 18:28:34 -0000 Subject: [llvm-commits] [llvm] r105942 - /llvm/trunk/lib/CodeGen/LiveVariables.cpp Message-ID: <20100614182834.29F072A6C12C@llvm.org> Author: lattner Date: Mon Jun 14 13:28:34 2010 New Revision: 105942 URL: http://llvm.org/viewvc/llvm-project?rev=105942&view=rev Log: fix a -Wbool-conversions warning from clang. Modified: llvm/trunk/lib/CodeGen/LiveVariables.cpp Modified: llvm/trunk/lib/CodeGen/LiveVariables.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveVariables.cpp?rev=105942&r1=105941&r2=105942&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveVariables.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveVariables.cpp Mon Jun 14 13:28:34 2010 @@ -286,7 +286,7 @@ MachineInstr *LastDef = PhysRegDef[Reg]; MachineInstr *LastUse = PhysRegUse[Reg]; if (!LastDef && !LastUse) - return false; + return 0; MachineInstr *LastRefOrPartRef = LastUse ? LastUse : LastDef; unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef]; From sabre at nondot.org Mon Jun 14 13:28:58 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 14 Jun 2010 18:28:58 -0000 Subject: [llvm-commits] [llvm] r105943 - /llvm/trunk/lib/Target/CBackend/CBackend.cpp Message-ID: <20100614182858.18FC42A6C12C@llvm.org> Author: lattner Date: Mon Jun 14 13:28:57 2010 New Revision: 105943 URL: http://llvm.org/viewvc/llvm-project?rev=105943&view=rev Log: fix a -Wbool-conversions warning from clang. Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=105943&r1=105942&r2=105943&view=diff ============================================================================== --- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original) +++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Mon Jun 14 13:28:57 2010 @@ -264,7 +264,7 @@ // static const AllocaInst *isDirectAlloca(const Value *V) { const AllocaInst *AI = dyn_cast(V); - if (!AI) return false; + if (!AI) return 0; if (AI->isArrayAllocation()) return 0; // FIXME: we can also inline fixed size array allocas! if (AI->getParent() != &AI->getParent()->getParent()->getEntryBlock()) From bob.wilson at apple.com Mon Jun 14 13:29:23 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Mon, 14 Jun 2010 18:29:23 -0000 Subject: [llvm-commits] [llvm] r105944 - /llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Message-ID: <20100614182924.08B9E2A6C12C@llvm.org> Author: bwilson Date: Mon Jun 14 13:29:23 2010 New Revision: 105944 URL: http://llvm.org/viewvc/llvm-project?rev=105944&view=rev Log: Fix a comment typo. Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=105944&r1=105943&r2=105944&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Mon Jun 14 13:29:23 2010 @@ -455,7 +455,7 @@ virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0; /// getSubRegIndex - For a given register pair, return the sub-register index - /// if the are second register is a sub-register of the first. Return zero + /// if the second register is a sub-register of the first. Return zero /// otherwise. virtual unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const = 0; From stuart at apple.com Mon Jun 14 13:31:33 2010 From: stuart at apple.com (Stuart Hastings) Date: Mon, 14 Jun 2010 18:31:33 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r105945 - /llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/block-bad-ivar-access.c Message-ID: <20100614183133.A845F2A6C12C@llvm.org> Author: stuart Date: Mon Jun 14 13:31:33 2010 New Revision: 105945 URL: http://llvm.org/viewvc/llvm-project?rev=105945&view=rev Log: Commit a mislaid test case for Radar 7901648. Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/block-bad-ivar-access.c Added: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/block-bad-ivar-access.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/block-bad-ivar-access.c?rev=105945&view=auto ============================================================================== --- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/block-bad-ivar-access.c (added) +++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/block-bad-ivar-access.c Mon Jun 14 13:31:33 2010 @@ -0,0 +1,23 @@ +/* APPLE LOCAL file 7901648 */ +/* { dg-do compile } */ +/* { dg-options "-mmacosx-version-min=10.5 -ObjC -fblocks" } */ + + + at interface Foo { + int x; + int y; +} + at end + +void fee(int); + + at implementation Foo ++ (int)method { + ^{ x = 1; /* { dg-error "instance variable \\'x\\' accessed in class method" } */ + x = /* { dg-error "instance variable \\'x\\' accessed in class method" } */ + y+1; /* { dg-error "instance variable \\'y\\' accessed in class method" } */ + fee(x); /* { dg-error "instance variable \\'x\\' accessed in class method" } */ + return x; }; /* { dg-error "instance variable \\'x\\' accessed in class method" } */ +} + at end + From stuart at apple.com Mon Jun 14 13:36:56 2010 From: stuart at apple.com (Stuart Hastings) Date: Mon, 14 Jun 2010 18:36:56 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r105948 - /llvm-gcc-4.2/trunk/gcc/gimplify.c Message-ID: <20100614183656.70DD72A6C12C@llvm.org> Author: stuart Date: Mon Jun 14 13:36:56 2010 New Revision: 105948 URL: http://llvm.org/viewvc/llvm-project?rev=105948&view=rev Log: Gimplify the type here, in case a SAVE_EXPR lurks within. Radar 8004649. Modified: llvm-gcc-4.2/trunk/gcc/gimplify.c Modified: llvm-gcc-4.2/trunk/gcc/gimplify.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/gimplify.c?rev=105948&r1=105947&r2=105948&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/gimplify.c (original) +++ llvm-gcc-4.2/trunk/gcc/gimplify.c Mon Jun 14 13:36:56 2010 @@ -5531,8 +5531,11 @@ #ifdef ENABLE_LLVM /* Handle the LLVM "ARRAY_REF with pointer base" extension by treating pointer-based ARRAY_REFs as binary expressions. */ - if (TREE_CODE (TREE_TYPE (TREE_OPERAND (*expr_p, 0))) != ARRAY_TYPE) + if (TREE_CODE (TREE_TYPE (TREE_OPERAND (*expr_p, 0))) != ARRAY_TYPE) { + /* LLVM LOCAL 8004649 */ + gimplify_type_sizes (TREE_TYPE (*expr_p), expr_p); goto expr_2; + } #endif /* LLVM LOCAL end */ From stuart at apple.com Mon Jun 14 13:37:05 2010 From: stuart at apple.com (Stuart Hastings) Date: Mon, 14 Jun 2010 18:37:05 -0000 Subject: [llvm-commits] [llvm] r105949 - /llvm/trunk/test/FrontendC/2010-06-11-SaveExpr.c Message-ID: <20100614183705.1D2CF2A6C12C@llvm.org> Author: stuart Date: Mon Jun 14 13:37:04 2010 New Revision: 105949 URL: http://llvm.org/viewvc/llvm-project?rev=105949&view=rev Log: Test case for Radar 8004649. Added: llvm/trunk/test/FrontendC/2010-06-11-SaveExpr.c Added: llvm/trunk/test/FrontendC/2010-06-11-SaveExpr.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/2010-06-11-SaveExpr.c?rev=105949&view=auto ============================================================================== --- llvm/trunk/test/FrontendC/2010-06-11-SaveExpr.c (added) +++ llvm/trunk/test/FrontendC/2010-06-11-SaveExpr.c Mon Jun 14 13:37:04 2010 @@ -0,0 +1,8 @@ +// RUN: %llvmgcc -S %s +// Test case by Eric Postpischil! +void foo(void) +{ + char a[1]; + int t = 1; + ((char (*)[t]) a)[0][0] = 0; +} From espindola at google.com Mon Jun 14 14:28:00 2010 From: espindola at google.com (Rafael Espindola) Date: Mon, 14 Jun 2010 15:28:00 -0400 Subject: [llvm-commits] [patch] Small fixes to the gold plugin Message-ID: The attached patch has two small fixes to the gold plugin. First, it moves two checks out of the per file loop. I assume this was broken in the recent changes. Right now the plugin will produce no output if any file was fully unused. The second fix is a special case for _start. We need this for the uncommon situation that a full program is LLVM IL (including the crt* files). In this case the resolution of nothing is LDPR_PREVAILING_DEF and we drop all symbols. Cheers, -- Rafael ?vila de Esp?ndola -------------- next part -------------- A non-text attachment was scrubbed... Name: gold-plugin.patch Type: text/x-patch Size: 1263 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100614/428b24b7/attachment.bin From sabre at nondot.org Mon Jun 14 14:45:43 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 14 Jun 2010 19:45:43 -0000 Subject: [llvm-commits] [llvm] r105950 - in /llvm/trunk: lib/Transforms/Scalar/JumpThreading.cpp test/Transforms/JumpThreading/crash.ll Message-ID: <20100614194543.60A362A6C12C@llvm.org> Author: lattner Date: Mon Jun 14 14:45:43 2010 New Revision: 105950 URL: http://llvm.org/viewvc/llvm-project?rev=105950&view=rev Log: jump threading can't split a critical edge from an indirectbr. This fixes PR7356. Modified: llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp llvm/trunk/test/Transforms/JumpThreading/crash.ll Modified: llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp?rev=105950&r1=105949&r2=105950&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Mon Jun 14 14:45:43 2010 @@ -870,9 +870,14 @@ // Add all the unavailable predecessors to the PredsToSplit list. for (pred_iterator PI = pred_begin(LoadBB), PE = pred_end(LoadBB); - PI != PE; ++PI) + PI != PE; ++PI) { + // If the predecessor is an indirect goto, we can't split the edge. + if (isa((*PI)->getTerminator())) + return false; + if (!AvailablePredSet.count(*PI)) PredsToSplit.push_back(*PI); + } // Split them out to their own block. UnavailablePred = Modified: llvm/trunk/test/Transforms/JumpThreading/crash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/JumpThreading/crash.ll?rev=105950&r1=105949&r2=105950&view=diff ============================================================================== --- llvm/trunk/test/Transforms/JumpThreading/crash.ll (original) +++ llvm/trunk/test/Transforms/JumpThreading/crash.ll Mon Jun 14 14:45:43 2010 @@ -341,3 +341,25 @@ ret void } + + +; PR7356 +define i32 @test13(i32* %P, i8* %Ptr) { +entry: + indirectbr i8* %Ptr, [label %BrBlock, label %B2] + +B2: + store i32 4, i32 *%P + br label %BrBlock + +BrBlock: + %L = load i32* %P + %C = icmp eq i32 %L, 42 + br i1 %C, label %T, label %F + +T: + ret i32 123 +F: + ret i32 1422 +} + From sabre at nondot.org Mon Jun 14 15:07:34 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 14 Jun 2010 20:07:34 -0000 Subject: [llvm-commits] [llvm] r105952 - /llvm/trunk/test/CodeGen/X86/hidden-vis-pic.ll Message-ID: <20100614200734.A31DA2A6C12C@llvm.org> Author: lattner Date: Mon Jun 14 15:07:34 2010 New Revision: 105952 URL: http://llvm.org/viewvc/llvm-project?rev=105952&view=rev Log: rename test Added: llvm/trunk/test/CodeGen/X86/hidden-vis-pic.ll - copied unchanged from r105940, llvm/trunk/test/CodeGen/X86/hidden-vis-5.ll From sabre at nondot.org Mon Jun 14 15:07:44 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 14 Jun 2010 20:07:44 -0000 Subject: [llvm-commits] [llvm] r105953 - /llvm/trunk/test/CodeGen/X86/hidden-vis-5.ll Message-ID: <20100614200744.11FA22A6C12C@llvm.org> Author: lattner Date: Mon Jun 14 15:07:43 2010 New Revision: 105953 URL: http://llvm.org/viewvc/llvm-project?rev=105953&view=rev Log: remove old test. Removed: llvm/trunk/test/CodeGen/X86/hidden-vis-5.ll Removed: llvm/trunk/test/CodeGen/X86/hidden-vis-5.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/hidden-vis-5.ll?rev=105952&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/hidden-vis-5.ll (original) +++ llvm/trunk/test/CodeGen/X86/hidden-vis-5.ll (removed) @@ -1,30 +0,0 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin9 -relocation-model=pic -disable-fp-elim -unwind-tables | FileCheck %s -; - - at .str = private constant [12 x i8] c"hello world\00", align 1 ; <[12 x i8]*> [#uses=1] - -define hidden void @func() nounwind ssp { -entry: - %0 = call i32 @puts(i8* getelementptr inbounds ([12 x i8]* @.str, i64 0, i64 0)) nounwind ; [#uses=0] - br label %return - -return: ; preds = %entry - ret void -} - -declare i32 @puts(i8*) - -define hidden i32 @main() nounwind ssp { -entry: - %retval = alloca i32 ; [#uses=1] - %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] - call void @func() nounwind - br label %return - -return: ; preds = %entry - %retval1 = load i32* %retval ; [#uses=1] - ret i32 %retval1 -} - -; CHECK: .private_extern _func.eh -; CHECK: .private_extern _main.eh From sabre at nondot.org Mon Jun 14 15:11:56 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 14 Jun 2010 20:11:56 -0000 Subject: [llvm-commits] [llvm] r105954 - in /llvm/trunk: lib/Target/X86/X86Subtarget.cpp test/CodeGen/X86/hidden-vis-pic.ll Message-ID: <20100614201156.B365A2A6C12C@llvm.org> Author: lattner Date: Mon Jun 14 15:11:56 2010 New Revision: 105954 URL: http://llvm.org/viewvc/llvm-project?rev=105954&view=rev Log: fix a nasty bug where we were not treating available_externally symbols as declarations in the X86 backend. This would manifest on darwin x86-32 as errors like this with -fvisibility=hidden: symbol '__ZNSbIcED1Ev' can not be undefined in a subtraction expression This fixes PR7353. Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp llvm/trunk/test/CodeGen/X86/hidden-vis-pic.ll Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=105954&r1=105953&r2=105954&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original) +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Mon Jun 14 15:11:56 2010 @@ -53,9 +53,12 @@ if (GV->hasDLLImportLinkage()) return X86II::MO_DLLIMPORT; - // Materializable GVs (in JIT lazy compilation mode) do not require an - // extra load from stub. - bool isDecl = GV->isDeclaration() && !GV->isMaterializable(); + // Determine whether this is a reference to a definition or a declaration. + // Materializable GVs (in JIT lazy compilation mode) do not require an extra + // load from stub. + bool isDecl = GV->hasAvailableExternallyLinkage(); + if (GV->isDeclaration() && !GV->isMaterializable()) + isDecl = true; // X86-64 in PIC mode. if (isPICStyleRIPRel()) { Modified: llvm/trunk/test/CodeGen/X86/hidden-vis-pic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/hidden-vis-pic.ll?rev=105954&r1=105953&r2=105954&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/hidden-vis-pic.ll (original) +++ llvm/trunk/test/CodeGen/X86/hidden-vis-pic.ll Mon Jun 14 15:11:56 2010 @@ -1,4 +1,27 @@ ; RUN: llc < %s -mtriple=i386-apple-darwin9 -relocation-model=pic -disable-fp-elim -unwind-tables | FileCheck %s + + + +; PR7353 + +define available_externally hidden +void @_ZNSbIcED1Ev() nounwind readnone ssp align 2 { +entry: + ret void +} + +define void()* @test1() nounwind { +entry: + ret void()* @_ZNSbIcED1Ev +} + +; This must use movl of the stub, not an lea, since the function isn't being +; emitted here. +; CHECK: movl L__ZNSbIcED1Ev$non_lazy_ptr-L1$pb( + + + + ; @.str = private constant [12 x i8] c"hello world\00", align 1 ; <[12 x i8]*> [#uses=1] @@ -28,3 +51,5 @@ ; CHECK: .private_extern _func.eh ; CHECK: .private_extern _main.eh + + From nlewycky at google.com Mon Jun 14 15:16:12 2010 From: nlewycky at google.com (Nick Lewycky) Date: Mon, 14 Jun 2010 13:16:12 -0700 Subject: [llvm-commits] [patch] Small fixes to the gold plugin In-Reply-To: References: Message-ID: On 14 June 2010 12:28, Rafael Espindola wrote: > The attached patch has two small fixes to the gold plugin. First, it > moves two checks out of the per file loop. I assume this was broken in > the recent changes. Right now the plugin will produce no output if any > file was fully unused. > Right. I even remember noticing that at one point, but got distracted. Please commit the second hunk of your patch. Thanks. The second fix is a special case for _start. We need this for the > uncommon situation that a full program is LLVM IL (including the crt* > files). In this case the resolution of nothing is LDPR_PREVAILING_DEF > and we drop all symbols. > Uh, no. This fix belongs in the gold linker since _start is a special case in the operating system and will apply to all forms of dead global elimination (including garbage collection inside the linker) and across all plugins. If gold is ported to a different operating system where _start isn't special but another symbol is, the plugins shouldn't all need to change. Gold should treat _start as though it were referenced by native code. Does that sound sensible? Nick -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100614/6ada068a/attachment.html From evan.cheng at apple.com Mon Jun 14 15:18:40 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 14 Jun 2010 20:18:40 -0000 Subject: [llvm-commits] [llvm] r105955 - /llvm/trunk/lib/CodeGen/SimpleHazardRecognizer.h Message-ID: <20100614201840.344DE2A6C12D@llvm.org> Author: evancheng Date: Mon Jun 14 15:18:40 2010 New Revision: 105955 URL: http://llvm.org/viewvc/llvm-project?rev=105955&view=rev Log: Avoid uncessary array copying. Modified: llvm/trunk/lib/CodeGen/SimpleHazardRecognizer.h Modified: llvm/trunk/lib/CodeGen/SimpleHazardRecognizer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleHazardRecognizer.h?rev=105955&r1=105954&r2=105955&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SimpleHazardRecognizer.h (original) +++ llvm/trunk/lib/CodeGen/SimpleHazardRecognizer.h Mon Jun 14 15:18:40 2010 @@ -35,6 +35,10 @@ /// instructions. Class Window[8]; + /// Pos - Current position pointing into Window. + /// + unsigned Pos; + /// getClass - Classify the given SUnit. Class getClass(const SUnit *SU) { const MachineInstr *MI = SU->getInstr(); @@ -49,8 +53,11 @@ /// Step - Rotate the existing entries in Window and insert the /// given class value in position as the most recent. void Step(Class C) { - std::copy(Window+1, array_endof(Window), Window); - Window[array_lengthof(Window)-1] = C; + Window[Pos] = C; + if (Pos == 0) + Pos = array_lengthof(Window)-1; + else + --Pos; } public: @@ -62,18 +69,23 @@ Class C = getClass(SU); if (C == Other) return NoHazard; + unsigned Score = 0; - for (unsigned i = 0; i != array_lengthof(Window); ++i) - if (Window[i] == C) - Score += i + 1; - if (Score > array_lengthof(Window) * 2) - return Hazard; + for (unsigned i = array_lengthof(Window); i != 0; --i) { + unsigned RealPos = (Pos + (i-1)) % array_lengthof(Window); + if (Window[RealPos] == C) { + Score += i; + if (Score > array_lengthof(Window) * 2) + return Hazard; + } + } return NoHazard; } virtual void Reset() { for (unsigned i = 0; i != array_lengthof(Window); ++i) Window[i] = Other; + Pos = array_lengthof(Window)-1; } virtual void EmitInstruction(SUnit *SU) { From sabre at nondot.org Mon Jun 14 15:19:03 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 14 Jun 2010 20:19:03 -0000 Subject: [llvm-commits] [llvm] r105956 - /llvm/trunk/test/CodeGen/X86/hidden-vis-pic.ll Message-ID: <20100614201903.C02E02A6C12D@llvm.org> Author: lattner Date: Mon Jun 14 15:19:03 2010 New Revision: 105956 URL: http://llvm.org/viewvc/llvm-project?rev=105956&view=rev Log: apparently lots of dupes. Modified: llvm/trunk/test/CodeGen/X86/hidden-vis-pic.ll Modified: llvm/trunk/test/CodeGen/X86/hidden-vis-pic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/hidden-vis-pic.ll?rev=105956&r1=105955&r2=105956&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/hidden-vis-pic.ll (original) +++ llvm/trunk/test/CodeGen/X86/hidden-vis-pic.ll Mon Jun 14 15:19:03 2010 @@ -2,7 +2,7 @@ -; PR7353 +; PR7353 PR7334 rdar://8072315 rdar://8018308 define available_externally hidden void @_ZNSbIcED1Ev() nounwind readnone ssp align 2 { From evan.cheng at apple.com Mon Jun 14 16:06:53 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 14 Jun 2010 21:06:53 -0000 Subject: [llvm-commits] [llvm] r105959 - in /llvm/trunk: include/llvm/CodeGen/PostRAHazardRecognizer.h lib/CodeGen/ExactHazardRecognizer.cpp lib/CodeGen/ExactHazardRecognizer.h lib/CodeGen/PostRAHazardRecognizer.cpp lib/CodeGen/PostRASchedulerList.cpp lib/CodeGen/SimpleHazardRecognizer.h lib/CodeGen/TargetInstrInfoImpl.cpp Message-ID: <20100614210653.A1D332A6C12C@llvm.org> Author: evancheng Date: Mon Jun 14 16:06:53 2010 New Revision: 105959 URL: http://llvm.org/viewvc/llvm-project?rev=105959&view=rev Log: - Do away with SimpleHazardRecognizer.h. It's not used and offers little value. - Rename ExactHazardRecognizer to PostRAHazardRecognizer and move its header to include to allow targets to extend it. Added: llvm/trunk/include/llvm/CodeGen/PostRAHazardRecognizer.h llvm/trunk/lib/CodeGen/PostRAHazardRecognizer.cpp - copied, changed from r105940, llvm/trunk/lib/CodeGen/ExactHazardRecognizer.cpp Removed: llvm/trunk/lib/CodeGen/ExactHazardRecognizer.cpp llvm/trunk/lib/CodeGen/ExactHazardRecognizer.h llvm/trunk/lib/CodeGen/SimpleHazardRecognizer.h Modified: llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp Added: llvm/trunk/include/llvm/CodeGen/PostRAHazardRecognizer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/PostRAHazardRecognizer.h?rev=105959&view=auto ============================================================================== --- llvm/trunk/include/llvm/CodeGen/PostRAHazardRecognizer.h (added) +++ llvm/trunk/include/llvm/CodeGen/PostRAHazardRecognizer.h Mon Jun 14 16:06:53 2010 @@ -0,0 +1,93 @@ +//=- llvm/CodeGen/PostRAHazardRecognizer.h - Scheduling Support -*- C++ -*-=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements the PostRAHazardRecognizer class, which +// implements hazard-avoidance heuristics for scheduling, based on the +// scheduling itineraries specified for the target. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CODEGEN_EXACTHAZARDRECOGNIZER_H +#define LLVM_CODEGEN_EXACTHAZARDRECOGNIZER_H + +#include "llvm/CodeGen/ScheduleHazardRecognizer.h" +#include "llvm/System/DataTypes.h" + +#include +#include + +namespace llvm { + +class InstrItineraryData; +class SUnit; + +class PostRAHazardRecognizer : public ScheduleHazardRecognizer { + // ScoreBoard to track function unit usage. ScoreBoard[0] is a + // mask of the FUs in use in the cycle currently being + // schedule. ScoreBoard[1] is a mask for the next cycle. The + // ScoreBoard is used as a circular buffer with the current cycle + // indicated by Head. + class ScoreBoard { + unsigned *Data; + + // The maximum number of cycles monitored by the Scoreboard. This + // value is determined based on the target itineraries to ensure + // that all hazards can be tracked. + size_t Depth; + // Indices into the Scoreboard that represent the current cycle. + size_t Head; + public: + ScoreBoard():Data(NULL), Depth(0), Head(0) { } + ~ScoreBoard() { + delete[] Data; + } + + size_t getDepth() const { return Depth; } + unsigned& operator[](size_t idx) const { + assert(Depth && "ScoreBoard was not initialized properly!"); + + return Data[(Head + idx) % Depth]; + } + + void reset(size_t d = 1) { + if (Data == NULL) { + Depth = d; + Data = new unsigned[Depth]; + } + + memset(Data, 0, Depth * sizeof(Data[0])); + Head = 0; + } + + void advance() { + Head = (Head + 1) % Depth; + } + + // Print the scoreboard. + void dump() const; + }; + + // Itinerary data for the target. + const InstrItineraryData &ItinData; + + ScoreBoard ReservedScoreboard; + ScoreBoard RequiredScoreboard; + +public: + PostRAHazardRecognizer(const InstrItineraryData &ItinData); + + virtual HazardType getHazardType(SUnit *SU); + virtual void Reset(); + virtual void EmitInstruction(SUnit *SU); + virtual void AdvanceCycle(); +}; + +} + +#endif Removed: llvm/trunk/lib/CodeGen/ExactHazardRecognizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ExactHazardRecognizer.cpp?rev=105958&view=auto ============================================================================== --- llvm/trunk/lib/CodeGen/ExactHazardRecognizer.cpp (original) +++ llvm/trunk/lib/CodeGen/ExactHazardRecognizer.cpp (removed) @@ -1,180 +0,0 @@ -//===----- ExactHazardRecognizer.cpp - hazard recognizer -------- ---------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This implements a hazard recognizer using the instructions itineraries -// defined for the current target. -// -//===----------------------------------------------------------------------===// - -#define DEBUG_TYPE "post-RA-sched" -#include "ExactHazardRecognizer.h" -#include "llvm/CodeGen/ScheduleHazardRecognizer.h" -#include "llvm/Support/Debug.h" -#include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/raw_ostream.h" -#include "llvm/Target/TargetInstrItineraries.h" - -using namespace llvm; - -ExactHazardRecognizer:: -ExactHazardRecognizer(const InstrItineraryData &LItinData) : - ScheduleHazardRecognizer(), ItinData(LItinData) -{ - // Determine the maximum depth of any itinerary. This determines the - // depth of the scoreboard. We always make the scoreboard at least 1 - // cycle deep to avoid dealing with the boundary condition. - unsigned ScoreboardDepth = 1; - if (!ItinData.isEmpty()) { - for (unsigned idx = 0; ; ++idx) { - if (ItinData.isEndMarker(idx)) - break; - - const InstrStage *IS = ItinData.beginStage(idx); - const InstrStage *E = ItinData.endStage(idx); - unsigned ItinDepth = 0; - for (; IS != E; ++IS) - ItinDepth += IS->getCycles(); - - ScoreboardDepth = std::max(ScoreboardDepth, ItinDepth); - } - } - - ReservedScoreboard.reset(ScoreboardDepth); - RequiredScoreboard.reset(ScoreboardDepth); - - DEBUG(dbgs() << "Using exact hazard recognizer: ScoreboardDepth = " - << ScoreboardDepth << '\n'); -} - -void ExactHazardRecognizer::Reset() { - RequiredScoreboard.reset(); - ReservedScoreboard.reset(); -} - -void ExactHazardRecognizer::ScoreBoard::dump() const { - dbgs() << "Scoreboard:\n"; - - unsigned last = Depth - 1; - while ((last > 0) && ((*this)[last] == 0)) - last--; - - for (unsigned i = 0; i <= last; i++) { - unsigned FUs = (*this)[i]; - dbgs() << "\t"; - for (int j = 31; j >= 0; j--) - dbgs() << ((FUs & (1 << j)) ? '1' : '0'); - dbgs() << '\n'; - } -} - -ExactHazardRecognizer::HazardType ExactHazardRecognizer::getHazardType(SUnit *SU) { - if (ItinData.isEmpty()) - return NoHazard; - - unsigned cycle = 0; - - // Use the itinerary for the underlying instruction to check for - // free FU's in the scoreboard at the appropriate future cycles. - unsigned idx = SU->getInstr()->getDesc().getSchedClass(); - for (const InstrStage *IS = ItinData.beginStage(idx), - *E = ItinData.endStage(idx); IS != E; ++IS) { - // We must find one of the stage's units free for every cycle the - // stage is occupied. FIXME it would be more accurate to find the - // same unit free in all the cycles. - for (unsigned int i = 0; i < IS->getCycles(); ++i) { - assert(((cycle + i) < RequiredScoreboard.getDepth()) && - "Scoreboard depth exceeded!"); - - unsigned freeUnits = IS->getUnits(); - switch (IS->getReservationKind()) { - default: - assert(0 && "Invalid FU reservation"); - case InstrStage::Required: - // Required FUs conflict with both reserved and required ones - freeUnits &= ~ReservedScoreboard[cycle + i]; - // FALLTHROUGH - case InstrStage::Reserved: - // Reserved FUs can conflict only with required ones. - freeUnits &= ~RequiredScoreboard[cycle + i]; - break; - } - - if (!freeUnits) { - DEBUG(dbgs() << "*** Hazard in cycle " << (cycle + i) << ", "); - DEBUG(dbgs() << "SU(" << SU->NodeNum << "): "); - DEBUG(SU->getInstr()->dump()); - return Hazard; - } - } - - // Advance the cycle to the next stage. - cycle += IS->getNextCycles(); - } - - return NoHazard; -} - -void ExactHazardRecognizer::EmitInstruction(SUnit *SU) { - if (ItinData.isEmpty()) - return; - - unsigned cycle = 0; - - // Use the itinerary for the underlying instruction to reserve FU's - // in the scoreboard at the appropriate future cycles. - unsigned idx = SU->getInstr()->getDesc().getSchedClass(); - for (const InstrStage *IS = ItinData.beginStage(idx), - *E = ItinData.endStage(idx); IS != E; ++IS) { - // We must reserve one of the stage's units for every cycle the - // stage is occupied. FIXME it would be more accurate to reserve - // the same unit free in all the cycles. - for (unsigned int i = 0; i < IS->getCycles(); ++i) { - assert(((cycle + i) < RequiredScoreboard.getDepth()) && - "Scoreboard depth exceeded!"); - - unsigned freeUnits = IS->getUnits(); - switch (IS->getReservationKind()) { - default: - assert(0 && "Invalid FU reservation"); - case InstrStage::Required: - // Required FUs conflict with both reserved and required ones - freeUnits &= ~ReservedScoreboard[cycle + i]; - // FALLTHROUGH - case InstrStage::Reserved: - // Reserved FUs can conflict only with required ones. - freeUnits &= ~RequiredScoreboard[cycle + i]; - break; - } - - // reduce to a single unit - unsigned freeUnit = 0; - do { - freeUnit = freeUnits; - freeUnits = freeUnit & (freeUnit - 1); - } while (freeUnits); - - assert(freeUnit && "No function unit available!"); - if (IS->getReservationKind() == InstrStage::Required) - RequiredScoreboard[cycle + i] |= freeUnit; - else - ReservedScoreboard[cycle + i] |= freeUnit; - } - - // Advance the cycle to the next stage. - cycle += IS->getNextCycles(); - } - - DEBUG(ReservedScoreboard.dump()); - DEBUG(RequiredScoreboard.dump()); -} - -void ExactHazardRecognizer::AdvanceCycle() { - ReservedScoreboard[0] = 0; ReservedScoreboard.advance(); - RequiredScoreboard[0] = 0; RequiredScoreboard.advance(); -} Removed: llvm/trunk/lib/CodeGen/ExactHazardRecognizer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ExactHazardRecognizer.h?rev=105958&view=auto ============================================================================== --- llvm/trunk/lib/CodeGen/ExactHazardRecognizer.h (original) +++ llvm/trunk/lib/CodeGen/ExactHazardRecognizer.h (removed) @@ -1,86 +0,0 @@ -//=- llvm/CodeGen/ExactHazardRecognizer.h - Scheduling Support -*- C++ -*-=// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file implements the ExactHazardRecognizer class, which -// implements hazard-avoidance heuristics for scheduling, based on the -// scheduling itineraries specified for the target. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_CODEGEN_EXACTHAZARDRECOGNIZER_H -#define LLVM_CODEGEN_EXACTHAZARDRECOGNIZER_H - -#include "llvm/CodeGen/ScheduleHazardRecognizer.h" -#include "llvm/CodeGen/ScheduleDAG.h" -#include "llvm/Target/TargetInstrItineraries.h" - -namespace llvm { - class ExactHazardRecognizer : public ScheduleHazardRecognizer { - // ScoreBoard to track function unit usage. ScoreBoard[0] is a - // mask of the FUs in use in the cycle currently being - // schedule. ScoreBoard[1] is a mask for the next cycle. The - // ScoreBoard is used as a circular buffer with the current cycle - // indicated by Head. - class ScoreBoard { - unsigned *Data; - - // The maximum number of cycles monitored by the Scoreboard. This - // value is determined based on the target itineraries to ensure - // that all hazards can be tracked. - size_t Depth; - // Indices into the Scoreboard that represent the current cycle. - size_t Head; - public: - ScoreBoard():Data(NULL), Depth(0), Head(0) { } - ~ScoreBoard() { - delete[] Data; - } - - size_t getDepth() const { return Depth; } - unsigned& operator[](size_t idx) const { - assert(Depth && "ScoreBoard was not initialized properly!"); - - return Data[(Head + idx) % Depth]; - } - - void reset(size_t d = 1) { - if (Data == NULL) { - Depth = d; - Data = new unsigned[Depth]; - } - - memset(Data, 0, Depth * sizeof(Data[0])); - Head = 0; - } - - void advance() { - Head = (Head + 1) % Depth; - } - - // Print the scoreboard. - void dump() const; - }; - - // Itinerary data for the target. - const InstrItineraryData &ItinData; - - ScoreBoard ReservedScoreboard; - ScoreBoard RequiredScoreboard; - - public: - ExactHazardRecognizer(const InstrItineraryData &ItinData); - - virtual HazardType getHazardType(SUnit *SU); - virtual void Reset(); - virtual void EmitInstruction(SUnit *SU); - virtual void AdvanceCycle(); - }; -} - -#endif Copied: llvm/trunk/lib/CodeGen/PostRAHazardRecognizer.cpp (from r105940, llvm/trunk/lib/CodeGen/ExactHazardRecognizer.cpp) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PostRAHazardRecognizer.cpp?p2=llvm/trunk/lib/CodeGen/PostRAHazardRecognizer.cpp&p1=llvm/trunk/lib/CodeGen/ExactHazardRecognizer.cpp&r1=105940&r2=105959&rev=105959&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ExactHazardRecognizer.cpp (original) +++ llvm/trunk/lib/CodeGen/PostRAHazardRecognizer.cpp Mon Jun 14 16:06:53 2010 @@ -1,4 +1,4 @@ -//===----- ExactHazardRecognizer.cpp - hazard recognizer -------- ---------===// +//===----- PostRAHazardRecognizer.cpp - hazard recognizer -------- ---------===// // // The LLVM Compiler Infrastructure // @@ -13,8 +13,8 @@ //===----------------------------------------------------------------------===// #define DEBUG_TYPE "post-RA-sched" -#include "ExactHazardRecognizer.h" -#include "llvm/CodeGen/ScheduleHazardRecognizer.h" +#include "llvm/CodeGen/PostRAHazardRecognizer.h" +#include "llvm/CodeGen/ScheduleDAG.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" @@ -22,10 +22,9 @@ using namespace llvm; -ExactHazardRecognizer:: -ExactHazardRecognizer(const InstrItineraryData &LItinData) : - ScheduleHazardRecognizer(), ItinData(LItinData) -{ +PostRAHazardRecognizer:: +PostRAHazardRecognizer(const InstrItineraryData &LItinData) : + ScheduleHazardRecognizer(), ItinData(LItinData) { // Determine the maximum depth of any itinerary. This determines the // depth of the scoreboard. We always make the scoreboard at least 1 // cycle deep to avoid dealing with the boundary condition. @@ -48,16 +47,16 @@ ReservedScoreboard.reset(ScoreboardDepth); RequiredScoreboard.reset(ScoreboardDepth); - DEBUG(dbgs() << "Using exact hazard recognizer: ScoreboardDepth = " + DEBUG(dbgs() << "Using post-ra hazard recognizer: ScoreboardDepth = " << ScoreboardDepth << '\n'); } -void ExactHazardRecognizer::Reset() { +void PostRAHazardRecognizer::Reset() { RequiredScoreboard.reset(); ReservedScoreboard.reset(); } -void ExactHazardRecognizer::ScoreBoard::dump() const { +void PostRAHazardRecognizer::ScoreBoard::dump() const { dbgs() << "Scoreboard:\n"; unsigned last = Depth - 1; @@ -73,7 +72,8 @@ } } -ExactHazardRecognizer::HazardType ExactHazardRecognizer::getHazardType(SUnit *SU) { +PostRAHazardRecognizer::HazardType +PostRAHazardRecognizer::getHazardType(SUnit *SU) { if (ItinData.isEmpty()) return NoHazard; @@ -120,7 +120,7 @@ return NoHazard; } -void ExactHazardRecognizer::EmitInstruction(SUnit *SU) { +void PostRAHazardRecognizer::EmitInstruction(SUnit *SU) { if (ItinData.isEmpty()) return; @@ -174,7 +174,7 @@ DEBUG(RequiredScoreboard.dump()); } -void ExactHazardRecognizer::AdvanceCycle() { +void PostRAHazardRecognizer::AdvanceCycle() { ReservedScoreboard[0] = 0; ReservedScoreboard.advance(); RequiredScoreboard[0] = 0; RequiredScoreboard.advance(); } Modified: llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp?rev=105959&r1=105958&r2=105959&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp (original) +++ llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp Mon Jun 14 16:06:53 2010 @@ -22,8 +22,6 @@ #include "AntiDepBreaker.h" #include "AggressiveAntiDepBreaker.h" #include "CriticalAntiDepBreaker.h" -#include "ExactHazardRecognizer.h" -#include "SimpleHazardRecognizer.h" #include "ScheduleDAGInstrs.h" #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/LatencyPriorityQueue.h" @@ -65,10 +63,6 @@ cl::desc("Break post-RA scheduling anti-dependencies: " "\"critical\", \"all\", or \"none\""), cl::init("none"), cl::Hidden); -static cl::opt -EnablePostRAHazardAvoidance("avoid-hazards", - cl::desc("Enable exact hazard avoidance"), - cl::init(true), cl::Hidden); // If DebugDiv > 0 then only schedule MBB with (ID % DebugDiv) == DebugMod static cl::opt @@ -680,15 +674,6 @@ ScheduleNodeTopDown(FoundSUnit, CurCycle); HazardRec->EmitInstruction(FoundSUnit); CycleHasInsts = true; - - // If we are using the target-specific hazards, then don't - // advance the cycle time just because we schedule a node. If - // the target allows it we can schedule multiple nodes in the - // same cycle. - if (!EnablePostRAHazardAvoidance) { - if (FoundSUnit->Latency) // Don't increment CurCycle for pseudo-ops! - ++CurCycle; - } } else { if (CycleHasInsts) { DEBUG(dbgs() << "*** Finished cycle " << CurCycle << '\n'); @@ -719,16 +704,6 @@ #endif } -// Default implementation of CreateTargetPostRAHazardRecognizer. This should -// be in TargetInstrInfoImpl.cpp except it reference local command line -// option EnablePostRAHazardAvoidance -ScheduleHazardRecognizer *TargetInstrInfoImpl:: -CreateTargetPostRAHazardRecognizer(const InstrItineraryData &II) const { - if (EnablePostRAHazardAvoidance) - return (ScheduleHazardRecognizer *)new ExactHazardRecognizer(II); - return (ScheduleHazardRecognizer *)new SimpleHazardRecognizer(); -} - //===----------------------------------------------------------------------===// // Public Constructor Functions //===----------------------------------------------------------------------===// Removed: llvm/trunk/lib/CodeGen/SimpleHazardRecognizer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleHazardRecognizer.h?rev=105958&view=auto ============================================================================== --- llvm/trunk/lib/CodeGen/SimpleHazardRecognizer.h (original) +++ llvm/trunk/lib/CodeGen/SimpleHazardRecognizer.h (removed) @@ -1,101 +0,0 @@ -//=- llvm/CodeGen/SimpleHazardRecognizer.h - Scheduling Support -*- C++ -*-=// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file implements the SimpleHazardRecognizer class, which -// implements hazard-avoidance heuristics for scheduling, based on the -// scheduling itineraries specified for the target. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_CODEGEN_SIMPLEHAZARDRECOGNIZER_H -#define LLVM_CODEGEN_SIMPLEHAZARDRECOGNIZER_H - -#include "llvm/CodeGen/ScheduleHazardRecognizer.h" -#include "llvm/CodeGen/ScheduleDAG.h" -#include "llvm/Target/TargetMachine.h" -#include "llvm/Target/TargetInstrInfo.h" - -namespace llvm { - /// SimpleHazardRecognizer - A *very* simple hazard recognizer. It uses - /// a coarse classification and attempts to avoid that instructions of - /// a given class aren't grouped too densely together. - class SimpleHazardRecognizer : public ScheduleHazardRecognizer { - /// Class - A simple classification for SUnits. - enum Class { - Other, Load, Store - }; - - /// Window - The Class values of the most recently issued - /// instructions. - Class Window[8]; - - /// Pos - Current position pointing into Window. - /// - unsigned Pos; - - /// getClass - Classify the given SUnit. - Class getClass(const SUnit *SU) { - const MachineInstr *MI = SU->getInstr(); - const TargetInstrDesc &TID = MI->getDesc(); - if (TID.mayLoad()) - return Load; - if (TID.mayStore()) - return Store; - return Other; - } - - /// Step - Rotate the existing entries in Window and insert the - /// given class value in position as the most recent. - void Step(Class C) { - Window[Pos] = C; - if (Pos == 0) - Pos = array_lengthof(Window)-1; - else - --Pos; - } - - public: - SimpleHazardRecognizer() : Window() { - Reset(); - } - - virtual HazardType getHazardType(SUnit *SU) { - Class C = getClass(SU); - if (C == Other) - return NoHazard; - - unsigned Score = 0; - for (unsigned i = array_lengthof(Window); i != 0; --i) { - unsigned RealPos = (Pos + (i-1)) % array_lengthof(Window); - if (Window[RealPos] == C) { - Score += i; - if (Score > array_lengthof(Window) * 2) - return Hazard; - } - } - return NoHazard; - } - - virtual void Reset() { - for (unsigned i = 0; i != array_lengthof(Window); ++i) - Window[i] = Other; - Pos = array_lengthof(Window)-1; - } - - virtual void EmitInstruction(SUnit *SU) { - Step(getClass(SU)); - } - - virtual void AdvanceCycle() { - Step(Other); - } - }; -} - -#endif Modified: llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp?rev=105959&r1=105958&r2=105959&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp (original) +++ llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp Mon Jun 14 16:06:53 2010 @@ -21,6 +21,7 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineMemOperand.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/PostRAHazardRecognizer.h" #include "llvm/CodeGen/PseudoSourceValue.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" @@ -314,3 +315,9 @@ // Everything checked out. return true; } + +// Default implementation of CreateTargetPostRAHazardRecognizer. +ScheduleHazardRecognizer *TargetInstrInfoImpl:: +CreateTargetPostRAHazardRecognizer(const InstrItineraryData &II) const { + return (ScheduleHazardRecognizer *)new PostRAHazardRecognizer(II); +} From espindola at google.com Mon Jun 14 16:18:19 2010 From: espindola at google.com (Rafael Espindola) Date: Mon, 14 Jun 2010 17:18:19 -0400 Subject: [llvm-commits] [patch] Small fixes to the gold plugin In-Reply-To: References: Message-ID: >> The second fix is a special case for _start. We need this for the >> uncommon situation that a full program is LLVM IL (including the crt* >> files). In this case the resolution of nothing is LDPR_PREVAILING_DEF >> and we drop all symbols. > > Uh, no. This fix belongs in the gold linker since _start is a special case > in the operating system and will apply to all forms of dead global > elimination (including garbage collection inside the linker) and across all > plugins. If gold is ported to a different operating system where _start > isn't special but another symbol is, the plugins shouldn't all need to > change. > Gold should treat _start as though it were referenced by native code. Does > that sound sensible? Yes. I was not sure if we should count the runtime reference to it, but it makes sense. It is similar to what gold tells us when producing shared libraries. I will commit the other part and try to fix this in gold. > Nick > Thanks, -- Rafael ?vila de Esp?ndola From rafael.espindola at gmail.com Mon Jun 14 16:20:52 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Mon, 14 Jun 2010 21:20:52 -0000 Subject: [llvm-commits] [llvm] r105962 - /llvm/trunk/tools/gold/gold-plugin.cpp Message-ID: <20100614212052.3B9492A6C12C@llvm.org> Author: rafael Date: Mon Jun 14 16:20:52 2010 New Revision: 105962 URL: http://llvm.org/viewvc/llvm-project?rev=105962&view=rev Log: Don't produce output only if *all* files are unused. Modified: llvm/trunk/tools/gold/gold-plugin.cpp Modified: llvm/trunk/tools/gold/gold-plugin.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/gold/gold-plugin.cpp?rev=105962&r1=105961&r2=105962&view=diff ============================================================================== --- llvm/trunk/tools/gold/gold-plugin.cpp (original) +++ llvm/trunk/tools/gold/gold-plugin.cpp Mon Jun 14 16:20:52 2010 @@ -368,15 +368,15 @@ api_file << I->syms[i].name << "\n"; } } + } - if (options::generate_api_file) - api_file.close(); + if (options::generate_api_file) + api_file.close(); - if (!anySymbolsPreserved) { - // This entire file is unnecessary! - lto_codegen_dispose(cg); - return LDPS_OK; - } + if (!anySymbolsPreserved) { + // All of the IL is unnecessary! + lto_codegen_dispose(cg); + return LDPS_OK; } lto_codegen_set_pic_model(cg, output_type); From grosbach at apple.com Mon Jun 14 16:30:33 2010 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 14 Jun 2010 21:30:33 -0000 Subject: [llvm-commits] [llvm] r105965 - /llvm/trunk/lib/CodeGen/IfConversion.cpp Message-ID: <20100614213033.22D0A2A6C12C@llvm.org> Author: grosbach Date: Mon Jun 14 16:30:32 2010 New Revision: 105965 URL: http://llvm.org/viewvc/llvm-project?rev=105965&view=rev Log: More dbg_value cleanup so the presence of debug info doesn't affect code-gen. Make sure to skip the dbg_value instructions when moving dups out of the diamond. rdar://7797940 Modified: llvm/trunk/lib/CodeGen/IfConversion.cpp Modified: llvm/trunk/lib/CodeGen/IfConversion.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/IfConversion.cpp?rev=105965&r1=105964&r2=105965&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/IfConversion.cpp (original) +++ llvm/trunk/lib/CodeGen/IfConversion.cpp Mon Jun 14 16:30:32 2010 @@ -1091,6 +1091,13 @@ // Remove the duplicated instructions at the beginnings of both paths. MachineBasicBlock::iterator DI1 = BBI1->BB->begin(); MachineBasicBlock::iterator DI2 = BBI2->BB->begin(); + MachineBasicBlock::iterator DIE1 = BBI1->BB->end(); + MachineBasicBlock::iterator DIE2 = BBI2->BB->end(); + // Skip dbg_value instructions + while (DI1 != DIE1 && DI1->isDebugValue()) + ++DI1; + while (DI2 != DIE2 && DI2->isDebugValue()) + ++DI2; BBI1->NonPredSize -= NumDups1; BBI2->NonPredSize -= NumDups1; while (NumDups1 != 0) { @@ -1104,8 +1111,15 @@ // Predicate the 'true' block after removing its branch. BBI1->NonPredSize -= TII->RemoveBranch(*BBI1->BB); DI1 = BBI1->BB->end(); - for (unsigned i = 0; i != NumDups2; ++i) + for (unsigned i = 0; i != NumDups2; ) { + // NumDups2 only counted non-dbg_value instructions, so this won't + // run off the head of the list. + assert (DI1 != BBI1->BB->begin()); --DI1; + // skip dbg_value instructions + if (!DI1->isDebugValue()) + ++i; + } BBI1->BB->erase(DI1, BBI1->BB->end()); PredicateBlock(*BBI1, BBI1->BB->end(), *Cond1); @@ -1113,8 +1127,13 @@ BBI2->NonPredSize -= TII->RemoveBranch(*BBI2->BB); DI2 = BBI2->BB->end(); while (NumDups2 != 0) { + // NumDups2 only counted non-dbg_value instructions, so this won't + // run off the head of the list. + assert (DI2 != BBI2->BB->begin()); --DI2; - --NumDups2; + // skip dbg_value instructions + if (!DI2->isDebugValue()) + --NumDups2; } PredicateBlock(*BBI2, DI2, *Cond2); From bob.wilson at apple.com Mon Jun 14 17:19:58 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Mon, 14 Jun 2010 22:19:58 -0000 Subject: [llvm-commits] [llvm] r105969 - in /llvm/trunk/lib/Target/ARM: ARMISelLowering.cpp ARMISelLowering.h ARMInstrNEON.td Message-ID: <20100614221958.2E3EC2A6C12E@llvm.org> Author: bwilson Date: Mon Jun 14 17:19:57 2010 New Revision: 105969 URL: http://llvm.org/viewvc/llvm-project?rev=105969&view=rev Log: Rename functions referring to VMOV immediates to refer to NEON "modified immediate" operands. These functions have so far only been used for VMOV but they also apply to other NEON instructions with modified immediate operands. No functional changes. Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.h llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=105969&r1=105968&r2=105969&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Mon Jun 14 17:19:57 2010 @@ -2758,13 +2758,15 @@ return Result; } -/// isVMOVSplat - Check if the specified splat value corresponds to an immediate -/// VMOV instruction. If so, return either the constant being splatted or the -/// encoded value, depending on the DoEncode parameter. The format of the -/// encoded value is: bit12=Op, bits11-8=Cmode, bits7-0=Immediate. -static SDValue isVMOVSplat(uint64_t SplatBits, uint64_t SplatUndef, - unsigned SplatBitSize, SelectionDAG &DAG, - bool DoEncode) { +/// isNEONModifiedImm - Check if the specified splat value corresponds to a +/// valid vector constant for a NEON instruction with a "modified immediate" +/// operand (e.g., VMOV). If so, return either the constant being +/// splatted or the encoded value, depending on the DoEncode parameter. The +/// format of the encoded value is: bit12=Op, bits11-8=Cmode, +/// bits7-0=Immediate. +static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef, + unsigned SplatBitSize, SelectionDAG &DAG, + bool DoEncode) { unsigned Op, Cmode, Imm; EVT VT; @@ -2885,11 +2887,12 @@ return DAG.getTargetConstant(SplatBits, VT); } -/// getVMOVImm - If this is a build_vector of constants which can be -/// formed by using a VMOV instruction of the specified element size, -/// return the constant being splatted. The ByteSize field indicates the -/// number of bytes of each element [1248]. -SDValue ARM::getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { + +/// getNEONModImm - If this is a valid vector constant for a NEON instruction +/// with a "modified immediate" operand (e.g., VMOV) of the specified element +/// size, return the encoded value for that immediate. The ByteSize field +/// indicates the number of bytes of each element [1248]. +SDValue ARM::getNEONModImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { BuildVectorSDNode *BVN = dyn_cast(N); APInt SplatBits, SplatUndef; unsigned SplatBitSize; @@ -2901,8 +2904,8 @@ if (SplatBitSize > ByteSize * 8) return SDValue(); - return isVMOVSplat(SplatBits.getZExtValue(), SplatUndef.getZExtValue(), - SplatBitSize, DAG, true); + return isNEONModifiedImm(SplatBits.getZExtValue(), SplatUndef.getZExtValue(), + SplatBitSize, DAG, true); } static bool isVEXTMask(const SmallVectorImpl &M, EVT VT, @@ -3142,9 +3145,10 @@ bool HasAnyUndefs; if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { if (SplatBitSize <= 64) { - SDValue Val = isVMOVSplat(SplatBits.getZExtValue(), - SplatUndef.getZExtValue(), SplatBitSize, DAG, - false); + // Check if an immediate VMOV works. + SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(), + SplatUndef.getZExtValue(), + SplatBitSize, DAG, false); if (Val.getNode()) return BuildSplat(Val, VT, DAG, dl); } Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=105969&r1=105968&r2=105969&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Mon Jun 14 17:19:57 2010 @@ -150,11 +150,11 @@ /// Define some predicates that are used for node matching. namespace ARM { - /// getVMOVImm - If this is a build_vector of constants which can be - /// formed by using a VMOV instruction of the specified element size, - /// return the constant being splatted. The ByteSize field indicates the - /// number of bytes of each element [1248]. - SDValue getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); + /// getNEONModImm - If this is a valid vector constant for a NEON + /// instruction with a "modified immediate" operand (e.g., VMOV) of the + /// specified element size, return the encoded value for that immediate. + /// The ByteSize field indicates the number of bytes of each element [1248]. + SDValue getNEONModImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); /// getVFPf32Imm / getVFPf64Imm - If the given fp immediate can be /// materialized with a VMOV.f32 / VMOV.f64 (i.e. fconsts / fconstd) Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=105969&r1=105968&r2=105969&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Jun 14 17:19:57 2010 @@ -2820,34 +2820,34 @@ // VMOV_get_imm8 xform function: convert build_vector to VMOV.i8 imm. def VMOV_get_imm8 : SDNodeXForm; def vmovImm8 : PatLeaf<(build_vector), [{ - return ARM::getVMOVImm(N, 1, *CurDAG).getNode() != 0; + return ARM::getNEONModImm(N, 1, *CurDAG).getNode() != 0; }], VMOV_get_imm8>; // VMOV_get_imm16 xform function: convert build_vector to VMOV.i16 imm. def VMOV_get_imm16 : SDNodeXForm; def vmovImm16 : PatLeaf<(build_vector), [{ - return ARM::getVMOVImm(N, 2, *CurDAG).getNode() != 0; + return ARM::getNEONModImm(N, 2, *CurDAG).getNode() != 0; }], VMOV_get_imm16>; // VMOV_get_imm32 xform function: convert build_vector to VMOV.i32 imm. def VMOV_get_imm32 : SDNodeXForm; def vmovImm32 : PatLeaf<(build_vector), [{ - return ARM::getVMOVImm(N, 4, *CurDAG).getNode() != 0; + return ARM::getNEONModImm(N, 4, *CurDAG).getNode() != 0; }], VMOV_get_imm32>; // VMOV_get_imm64 xform function: convert build_vector to VMOV.i64 imm. def VMOV_get_imm64 : SDNodeXForm; def vmovImm64 : PatLeaf<(build_vector), [{ - return ARM::getVMOVImm(N, 8, *CurDAG).getNode() != 0; + return ARM::getNEONModImm(N, 8, *CurDAG).getNode() != 0; }], VMOV_get_imm64>; // Note: Some of the cmode bits in the following VMOV instructions need to From sabre at nondot.org Mon Jun 14 17:33:34 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 14 Jun 2010 22:33:34 -0000 Subject: [llvm-commits] [llvm] r105970 - /llvm/trunk/utils/TableGen/DAGISelMatcherEmitter.cpp Message-ID: <20100614223334.B14152A6C12C@llvm.org> Author: lattner Date: Mon Jun 14 17:33:34 2010 New Revision: 105970 URL: http://llvm.org/viewvc/llvm-project?rev=105970&view=rev Log: generate better code in CheckComplexPattern Modified: llvm/trunk/utils/TableGen/DAGISelMatcherEmitter.cpp Modified: llvm/trunk/utils/TableGen/DAGISelMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelMatcherEmitter.cpp?rev=105970&r1=105969&r2=105970&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/DAGISelMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/DAGISelMatcherEmitter.cpp Mon Jun 14 17:33:34 2010 @@ -635,6 +635,7 @@ if (!ComplexPatterns.empty()) { OS << "bool CheckComplexPattern(SDNode *Root, SDValue N,\n"; OS << " unsigned PatternNo, SmallVectorImpl &Result) {\n"; + OS << " unsigned NextRes = Result.size();\n"; OS << " switch (PatternNo) {\n"; OS << " default: assert(0 && \"Invalid pattern # in table?\");\n"; for (unsigned i = 0, e = ComplexPatterns.size(); i != e; ++i) { @@ -645,12 +646,12 @@ ++NumOps; // Get the chained node too. OS << " case " << i << ":\n"; - OS << " Result.resize(Result.size()+" << NumOps << ");\n"; + OS << " Result.resize(NextRes+" << NumOps << ");\n"; OS << " return " << P.getSelectFunc(); OS << "(Root, N"; for (unsigned i = 0; i != NumOps; ++i) - OS << ", Result[Result.size()-" << (NumOps-i) << ']'; + OS << ", Result[NextRes+" << i << ']'; OS << ");\n"; } OS << " }\n"; From rideau3 at gmail.com Mon Jun 14 17:44:26 2010 From: rideau3 at gmail.com (Sean Hunt) Date: Mon, 14 Jun 2010 22:44:26 -0000 Subject: [llvm-commits] [llvm] r105971 - /llvm/trunk/include/llvm/CodeGen/PostRAHazardRecognizer.h Message-ID: <20100614224426.C22582A6C12C@llvm.org> Author: coppro Date: Mon Jun 14 17:44:26 2010 New Revision: 105971 URL: http://llvm.org/viewvc/llvm-project?rev=105971&view=rev Log: Add missing include to unbreak the build. Modified: llvm/trunk/include/llvm/CodeGen/PostRAHazardRecognizer.h Modified: llvm/trunk/include/llvm/CodeGen/PostRAHazardRecognizer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/PostRAHazardRecognizer.h?rev=105971&r1=105970&r2=105971&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/PostRAHazardRecognizer.h (original) +++ llvm/trunk/include/llvm/CodeGen/PostRAHazardRecognizer.h Mon Jun 14 17:44:26 2010 @@ -20,6 +20,7 @@ #include "llvm/System/DataTypes.h" #include +#include #include namespace llvm { From daniel at zuster.org Mon Jun 14 18:07:39 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 14 Jun 2010 23:07:39 -0000 Subject: [llvm-commits] [zorg] r105972 - /zorg/trunk/lnt/lnt/db/perfdbsummary.py Message-ID: <20100614230739.D6C8A2A6C12C@llvm.org> Author: ddunbar Date: Mon Jun 14 18:07:39 2010 New Revision: 105972 URL: http://llvm.org/viewvc/llvm-project?rev=105972&view=rev Log: LNT/simple: Tweak status map to use .status markers whenever they are present for any test in the suite. Modified: zorg/trunk/lnt/lnt/db/perfdbsummary.py Modified: zorg/trunk/lnt/lnt/db/perfdbsummary.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/db/perfdbsummary.py?rev=105972&r1=105971&r2=105972&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/db/perfdbsummary.py (original) +++ zorg/trunk/lnt/lnt/db/perfdbsummary.py Mon Jun 14 18:07:39 2010 @@ -49,7 +49,8 @@ test_names = set() parameter_sets = set() test_map = {} - test_status_map = {} + has_status_markers = False + has_success_markers = False for t in tests: name = t.name.split('.', 1)[1] @@ -62,15 +63,26 @@ if name.endswith('.success'): test_name = name.rsplit('.', 1)[0] - test_status_map[test_name] = (name, False) + has_success_markers = True elif name.endswith('.status'): test_name = name.rsplit('.', 1)[0] - test_status_map[test_name] = (name, True) + has_status_markers = True else: test_name = name test_names.add(test_name) + # Compute the test status info. + test_status_map = {} + if has_status_markers: + for test_name in test_names: + marker_name = '%s.status' % test_name + test_status_map[test_name] = (marker_name, True) + elif has_success_markers: + for test_name in test_names: + marker_name = '%s.success' % test_name + test_status_map[test_name] = (marker_name, False) + # Order the test names. test_names = list(test_names) test_names.sort() From daniel at zuster.org Mon Jun 14 18:07:48 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 14 Jun 2010 23:07:48 -0000 Subject: [llvm-commits] [zorg] r105973 - /zorg/trunk/lnt/lnt/viewer/simple.ptl Message-ID: <20100614230748.1CE6B2A6C12C@llvm.org> Author: ddunbar Date: Mon Jun 14 18:07:47 2010 New Revision: 105973 URL: http://llvm.org/viewvc/llvm-project?rev=105973&view=rev Log: LNT/simple: Add optional delta, std. dev., and MAD display. Modified: zorg/trunk/lnt/lnt/viewer/simple.ptl Modified: zorg/trunk/lnt/lnt/viewer/simple.ptl URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/viewer/simple.ptl?rev=105973&r1=105972&r2=105973&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/viewer/simple.ptl (original) +++ zorg/trunk/lnt/lnt/viewer/simple.ptl Mon Jun 14 18:07:47 2010 @@ -4,6 +4,7 @@ Nightly Test UI instance for actual nightly test data. """ +import math import sys import time @@ -19,6 +20,9 @@ from PerfDB import Machine, Run, RunInfo, Test +def mean(l): + return sum(l)/len(l) + def median(l): l = list(l) l.sort() @@ -30,6 +34,12 @@ med = median(l) return median([abs(x - med) for x in l]) +def standard_deviation(l): + m = mean(l) + means_sqrd = sum([(v - m)**2 for v in l]) / len(l) + rms = math.sqrt(means_sqrd) + return rms + class SimpleRunUI(Directory): _q_exports = ["", "graph"] @@ -72,7 +82,7 @@ # Get the run summary which has run ordering information. run_summary = perfdbsummary.SimpleSuiteRunSummary.get_summary(db, self.tag) - + # Find previous run to compare to. if compareTo is None: id = run_summary.get_previous_run_on_machine(run.id) @@ -213,7 +223,8 @@ addPopupJS=True, addFormCSS=True) self.show_run_page(db, run, run_summary, compare_to, - lambda: self._q_index_body(db, run, compare_to)) + lambda: self._q_index_body(db, run, run_summary, + compare_to)) def graph [html] (self): request = quixote.get_request() @@ -467,7 +478,7 @@ self.show_run_page(db, run, run_summary, compare_to, graph_body) - def _q_index_body [html] (self, db, run, compare_to): + def _q_index_body [html] (self, db, run, run_summary, compare_to): # Find the tests. The simple UI maps all tests that start with # 'simple.'. # @@ -478,14 +489,34 @@ if compare_to: prev_id = compare_to.id - interesting_runs = (run.id, prev_id) + interesting_runs = [run.id, prev_id] else: prev_id = None - interesting_runs = (run.id,) + interesting_runs = [run.id] # Load the test suite summary. ts_summary = perfdbsummary.get_simple_suite_summary(db, self.tag) + cur_id = run.id + previous_runs = [] + + request = quixote.get_request() + show_delta = bool(request.form.get('show_delta')) + show_stddev = bool(request.form.get('show_stddev')) + show_mad = bool(request.form.get('show_mad')) + + if show_stddev or show_mad: + for i in range(5): + cur_id = run_summary.get_previous_run_on_machine(cur_id) + if not cur_id: + break + + previous_runs.append(cur_id) + if cur_id not in interesting_runs: + interesting_runs.append(cur_id) + + interesting_runs = tuple(set(interesting_runs + previous_runs)) + # Load the run sample data. q = db.session.query(Sample.value, Sample.run_id, Sample.test_id) q = q.filter(Sample.run_id.in_(interesting_runs)) @@ -522,7 +553,10 @@ run_cell_value = "-" if run_values: - run_cell_value = "%.4f" % min(run_values) + run_value = min(run_values) + run_cell_value = "%.4f" % run_value + else: + run_value = None cell_color = None if run_failed: @@ -542,14 +576,44 @@ """ %snan') Util.PctCell(pct, delta=True).render() else: """-""" + prev_value = None + + if show_delta: + if prev_value is not None and run_value is not None: + """%.4f""" % (run_value - prev_value) + else: + """-""" + + if show_stddev: + previous_values = [v for run_id in previous_runs + for v in sample_map.get((run_id, + test.id), ())] + if previous_values: + sd_value = standard_deviation(previous_values) + sd_cell_value = "%.4f" % sd_value + else: + sd_cell_value = "-" + """ + %s%sParameter Sets @@ -582,17 +646,34 @@ """

Tests

""" + pset_cols = 2 + show_delta + show_stddev + show_mad """
+ - """ + """ + for i in range(len(ts_summary.parameter_sets)): + """ + """ % (pset_cols, i) + """ + """ for i in range(len(ts_summary.parameter_sets)): """ - - """ % (i, i) + + """ % i + if show_delta: + """ + """ + if show_stddev: + """ + """ + if show_mad: + """ + """ """ - """ + + """ for name in ts_summary.test_names: """ From daniel at zuster.org Mon Jun 14 18:07:55 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 14 Jun 2010 23:07:55 -0000 Subject: [llvm-commits] [zorg] r105974 - in /zorg/trunk/lnt/lnt/tests: misc/ misc/GetSourceVersion nt.py Message-ID: <20100614230755.C5C0D2A6C12C@llvm.org> Author: ddunbar Date: Mon Jun 14 18:07:55 2010 New Revision: 105974 URL: http://llvm.org/viewvc/llvm-project?rev=105974&view=rev Log: LNT/nt: Add local copy of GetSourceVersion, so we don't depend on any particular LLVM revision. Added: zorg/trunk/lnt/lnt/tests/misc/ zorg/trunk/lnt/lnt/tests/misc/GetSourceVersion (with props) Modified: zorg/trunk/lnt/lnt/tests/nt.py Added: zorg/trunk/lnt/lnt/tests/misc/GetSourceVersion URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/tests/misc/GetSourceVersion?rev=105974&view=auto ============================================================================== --- zorg/trunk/lnt/lnt/tests/misc/GetSourceVersion (added) +++ zorg/trunk/lnt/lnt/tests/misc/GetSourceVersion Mon Jun 14 18:07:55 2010 @@ -0,0 +1,27 @@ +#!/bin/sh + +usage() { + echo "usage: $0 " + echo " Prints the source control revision of the given source directory," + echo " the exact format of the revision string depends on the source " + echo " control system. If the source control system isn't known, the output" + echo " is empty and the exit code is 1." + exit 1 +} + +if [ $# != 1 ] || [ ! -d $1 ]; then + usage; +fi + +cd $1 +if [ -d .svn ]; then + svnversion +elif [ -d .git/svn ]; then + git svn info | grep 'Revision:' | cut -d: -f2- +elif [ -d .git ]; then + git log -1 --pretty=format:%H +else + exit 1; +fi + +exit 0 Propchange: zorg/trunk/lnt/lnt/tests/misc/GetSourceVersion ------------------------------------------------------------------------------ svn:executable = * Modified: zorg/trunk/lnt/lnt/tests/nt.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/tests/nt.py?rev=105974&r1=105973&r2=105974&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/tests/nt.py (original) +++ zorg/trunk/lnt/lnt/tests/nt.py Mon Jun 14 18:07:55 2010 @@ -13,6 +13,10 @@ from lnt.testing.util.commands import note, warning, error, fatal from lnt.testing.util.commands import capture, which +# FIXME: Add util command for this. +kGetSourceVersionPath = os.path.join(os.path.dirname(__file__), + 'misc', 'GetSourceVersion') + def timestamp(): return datetime.utcnow().strftime('%Y-%m-%d %H:%M:%S') @@ -370,14 +374,10 @@ # FIXME: Hack, use better method of getting versions. Ideally, from binaries # so we are more likely to be accurate. - run_info['llvm_revision'] = capture([os.path.join(opts.llvm_src_root, - 'utils', - 'GetSourceVersion'), + run_info['llvm_revision'] = capture([kGetSourceVersionPath, opts.llvm_src_root], include_stderr=True).strip() - run_info['test_suite_revision'] = capture([os.path.join(opts.llvm_src_root, - 'utils', - 'GetSourceVersion'), + run_info['test_suite_revision'] = capture([kGetSourceVersionPath, opts.test_suite_root], include_stderr=True).strip() run_info.update(public_make_variables) From daniel at zuster.org Mon Jun 14 18:41:37 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 14 Jun 2010 23:41:37 -0000 Subject: [llvm-commits] [zorg] r105976 - in /zorg/trunk/lnt/lnt: testing/util/rcs.py tests/misc/GetSourceVersion tests/nt.py Message-ID: <20100614234137.407E72A6C12C@llvm.org> Author: ddunbar Date: Mon Jun 14 18:41:37 2010 New Revision: 105976 URL: http://llvm.org/viewvc/llvm-project?rev=105976&view=rev Log: LNT/nt: Add (hackish) lnt.testing.util.rcs.get_source_version, instead of being lazy. Added: zorg/trunk/lnt/lnt/testing/util/rcs.py Removed: zorg/trunk/lnt/lnt/tests/misc/GetSourceVersion Modified: zorg/trunk/lnt/lnt/tests/nt.py Added: zorg/trunk/lnt/lnt/testing/util/rcs.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/testing/util/rcs.py?rev=105976&view=auto ============================================================================== --- zorg/trunk/lnt/lnt/testing/util/rcs.py (added) +++ zorg/trunk/lnt/lnt/testing/util/rcs.py Mon Jun 14 18:41:37 2010 @@ -0,0 +1,24 @@ +import os +from lnt.testing.util import commands + +def get_source_version(path): + """get_source_version(path) -> str or None + + Given the path to a revision controlled source tree, return a revision + number, hash, etc. which identifies the source version. + """ + + if os.path.exists(os.path.join(path, ".svn")): + return commands.capture(['/bin/sh', '-c', + 'cd "%s" && svnversion' % path]).strip() + elif os.path.exists(os.path.join(path, ".git", "svn")): + res = commands.capture(['/bin/sh', '-c', + 'cd "%s" && git svn info' % path]).strip() + for ln in res.split("\n"): + if ln.startswith("Revision:"): + return ln.split(':',1)[1].strip() + elif os.path.exists(os.path.join(path, ".git")): + return commands.capture(['/bin/sh', '-c', + ('cd "%s" && ' + 'git log -1 --pretty=format:%%H') % path] + ).strip() Removed: zorg/trunk/lnt/lnt/tests/misc/GetSourceVersion URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/tests/misc/GetSourceVersion?rev=105975&view=auto ============================================================================== --- zorg/trunk/lnt/lnt/tests/misc/GetSourceVersion (original) +++ zorg/trunk/lnt/lnt/tests/misc/GetSourceVersion (removed) @@ -1,27 +0,0 @@ -#!/bin/sh - -usage() { - echo "usage: $0 " - echo " Prints the source control revision of the given source directory," - echo " the exact format of the revision string depends on the source " - echo " control system. If the source control system isn't known, the output" - echo " is empty and the exit code is 1." - exit 1 -} - -if [ $# != 1 ] || [ ! -d $1 ]; then - usage; -fi - -cd $1 -if [ -d .svn ]; then - svnversion -elif [ -d .git/svn ]; then - git svn info | grep 'Revision:' | cut -d: -f2- -elif [ -d .git ]; then - git log -1 --pretty=format:%H -else - exit 1; -fi - -exit 0 Modified: zorg/trunk/lnt/lnt/tests/nt.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/tests/nt.py?rev=105976&r1=105975&r2=105976&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/tests/nt.py (original) +++ zorg/trunk/lnt/lnt/tests/nt.py Mon Jun 14 18:41:37 2010 @@ -12,10 +12,7 @@ from lnt.testing.util.commands import note, warning, error, fatal from lnt.testing.util.commands import capture, which - -# FIXME: Add util command for this. -kGetSourceVersionPath = os.path.join(os.path.dirname(__file__), - 'misc', 'GetSourceVersion') +from lnt.testing.util.rcs import get_source_version def timestamp(): return datetime.utcnow().strftime('%Y-%m-%d %H:%M:%S') @@ -374,12 +371,8 @@ # FIXME: Hack, use better method of getting versions. Ideally, from binaries # so we are more likely to be accurate. - run_info['llvm_revision'] = capture([kGetSourceVersionPath, - opts.llvm_src_root], - include_stderr=True).strip() - run_info['test_suite_revision'] = capture([kGetSourceVersionPath, - opts.test_suite_root], - include_stderr=True).strip() + run_info['llvm_revision'] = get_source_version(opts.llvm_src_root) + run_info['test_suite_revision'] = get_source_version(opts.test_suite_root) run_info.update(public_make_variables) # Set the run order from the user, if given. From daniel at zuster.org Mon Jun 14 19:16:39 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Tue, 15 Jun 2010 00:16:39 -0000 Subject: [llvm-commits] [zorg] r105979 - /zorg/trunk/lnt/lnt/tests/nt.py Message-ID: <20100615001639.5C1F82A6C12C@llvm.org> Author: ddunbar Date: Mon Jun 14 19:16:39 2010 New Revision: 105979 URL: http://llvm.org/viewvc/llvm-project?rev=105979&view=rev Log: LNT/nt: Always pass the cxx_under_test to the LLVM test makefiles, since it may be used to link even when we aren't testing C++ code. Also, fall back to the cc_under_test if the cxx_under_test doesn't exist, to support testing old Clang revisions before clang++ materialized. Modified: zorg/trunk/lnt/lnt/tests/nt.py Modified: zorg/trunk/lnt/lnt/tests/nt.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/tests/nt.py?rev=105979&r1=105978&r2=105979&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/tests/nt.py (original) +++ zorg/trunk/lnt/lnt/tests/nt.py Mon Jun 14 19:16:39 2010 @@ -45,7 +45,9 @@ # Set the make variables to use. make_variables = { 'TARGET_CC' : opts.cc_reference, + 'TARGET_CXX' : opts.cxx_reference, 'TARGET_LLVMGCC' : opts.cc_under_test, + 'TARGET_LLVMGXX' : opts.cxx_under_test, 'TARGET_FLAGS' : ' '.join(target_flags), 'TARGET_LLCFLAGS' : ' '.join(target_llcflags), 'ENABLE_OPTIMIZED' : '1', @@ -61,11 +63,7 @@ make_variables['LLC_OPTFLAGS'] = opts.optimize_option # Set test selection variables. - make_variables['TARGET_CXX'] = opts.cxx_reference - if opts.test_cxx: - make_variables['TARGET_LLVMGXX'] = opts.cxx_under_test - else: - make_variables['TARGET_LLVMGXX'] = 'false' + if not opts.test_cxx: make_variables['DISABLE_CXX'] = '1' if not opts.test_cbe: make_variables['DISABLE_CBE'] = '1' @@ -639,6 +637,18 @@ if opts.test_cxx and opts.cxx_under_test is None: parser.error('--cxx is required') + # Always set cxx_under_test, since it may be used as the linker even + # when not testing C++ code. + if opts.cxx_under_test is None: + opts.cxx_under_test = opts.cc_under_test + + # FIXME: As a hack to allow sampling old Clang revisions, if we are + # given a C++ compiler that doesn't exist, reset it to just use the + # given C compiler. + if not os.path.exists(opts.cxx_under_test): + warning("invalid cxx_under_test, falling back to cc_under_test") + opts.cxx_under_test = opts.cc_under_test + if opts.llvm_src_root is None: parser.error('--llvm-src is required') if opts.llvm_obj_root is None: From gkistanova at gmail.com Mon Jun 14 19:19:58 2010 From: gkistanova at gmail.com (Galina Kistanova) Date: Tue, 15 Jun 2010 00:19:58 -0000 Subject: [llvm-commits] [zorg] r105980 - /zorg/trunk/buildbot/osuosl/master/config/builders.py Message-ID: <20100615001958.DCAD82A6C12C@llvm.org> Author: gkistanova Date: Mon Jun 14 19:19:58 2010 New Revision: 105980 URL: http://llvm.org/viewvc/llvm-project?rev=105980&view=rev Log: Added new buildbot builder to build on x86_64-apple-darwin10 of cross llvm-gcc for i686-pc-linux-gnu Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=105980&r1=105979&r2=105980&view=diff ============================================================================== --- zorg/trunk/buildbot/osuosl/master/config/builders.py (original) +++ zorg/trunk/buildbot/osuosl/master/config/builders.py Mon Jun 14 19:19:58 2010 @@ -407,6 +407,45 @@ 'haltOnFailure' : True },]), 'category' : 'llvm-gcc' }, + {'name' : "llvm-gcc-x86_64-darwin10-cross-i686-linux", + 'slavenames': [ "kistanova1" ], + 'builddir' : "llvm-gcc-x86_64-darwin10-cross-i686-linux", + 'factory' : ScriptedBuilder.getScriptedBuildFactory( + source_code = [SVN(name='svn-llvm', + mode='update', baseURL='http://llvm.org/svn/llvm-project/llvm/', + defaultBranch='trunk', + workdir="llvm.src"), + SVN(name='svn-llvm-gcc', + mode='update', baseURL='http://llvm.org/svn/llvm-project/llvm-gcc-4.2/', + defaultBranch='trunk', + workdir="llvm-gcc.src"),], + launcher = 'llvm-gcc.src/extras/buildbot-launcher', + build_script = 'llvm-gcc.src/extras/build-x-4-linux', + extra_args = [], + build_steps = [{'name' : 'clean', + 'description' : 'clean', + 'haltOnFailure' : True }, + {'name' : 'copy_cross_tools', + 'description' : 'copy cross-tools', + 'haltOnFailure' : True }, + {'name' : 'configure_llvm', + 'description' : 'configure llvm', + 'haltOnFailure' : True }, + {'name' : 'make_llvm', + 'description' : 'make llvm', + 'extra_args' : ['-j8'], # Extra step-specific properties + 'haltOnFailure' : True }, + {'name' : 'configure_llvmgcc', + 'description' : 'configure llvm-gcc', + 'haltOnFailure' : True }, + {'name' : 'make_llvmgcc', + 'description' : 'make llvm-gcc', + 'haltOnFailure' : True }, + {'name' : 'install_llvmgcc', + 'description' : 'install llvm-gcc', + 'haltOnFailure' : True },]), + 'category' : 'llvm-gcc' }, + {'name' : "clang-i686-linux-selfhost-rel", 'slavenames' : ["osu8"], 'builddir' : "clang-i686-linux-selfhost-rel", From gkistanova at gmail.com Mon Jun 14 19:40:24 2010 From: gkistanova at gmail.com (Galina Kistanova) Date: Tue, 15 Jun 2010 00:40:24 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r105981 - /llvm-gcc-4.2/trunk/extras/build-x-4-linux Message-ID: <20100615004024.264BF2A6C12C@llvm.org> Author: gkistanova Date: Mon Jun 14 19:40:23 2010 New Revision: 105981 URL: http://llvm.org/viewvc/llvm-project?rev=105981&view=rev Log: Added build script for build on x86_64-apple-darwin10 of cross llvm-gcc for i686-pc-linux-gnu Added: llvm-gcc-4.2/trunk/extras/build-x-4-linux (with props) Added: llvm-gcc-4.2/trunk/extras/build-x-4-linux URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/extras/build-x-4-linux?rev=105981&view=auto ============================================================================== --- llvm-gcc-4.2/trunk/extras/build-x-4-linux (added) +++ llvm-gcc-4.2/trunk/extras/build-x-4-linux Mon Jun 14 19:40:23 2010 @@ -0,0 +1,207 @@ +#!/bin/bash + +set -e # Terminate script at the first line that fails. +set -o pipefail # Return the first non-zero pipe command error. +set -x # Print commands as they are executed + +# This script performs an automated build on x86_64-apple-darwin10 of +# cross llvm-gcc for i686-pc-linux-gnu. It assumes the valid native +# compiler for x86_64-apple-darwin10 is in place and available as well as +# cross libraries and headers for i686-pc-linux-gnu. + +# --build=x86_64-apple-darwin10 +# --host=x86_64-apple-darwin10 +# --target=i686-pc-linux-gnu + +# The usage: +# Run this build from the build from the build root directory as +# build-x-4-linux [] [] + +# Expected project tree structure: +# +# +-- ${LLVM_src} +# +-- ${LLVM_GCC_src} +# +-- ${LLVM_obj} +# +-- ${LLVM_GCC_obj} +# +-- ${INSTALL} + +LLVM_src=llvm.src # The LLVM source code root directory name. +LLVM_GCC_src=llvm-gcc.src # The LLVM-GCC source code root directory name. +LLVM_obj=llvm.obj # The LLVM build root directory name. +LLVM_GCC_obj=llvm-gcc.obj # The LLVM-GCC build root directory name. +INSTALL=install # Where the result will be installed. + +# CFLAGS and CXXFLAGS must not be set during the building of cross-tools. +unset CFLAGS +unset CXXFLAGS + +BUILD_ROOT=$PWD # Where build happens. +PRIVATE_INSTALL=${BUILD_ROOT}/${INSTALL} # Where the result will be installed. + +#------------------------------------------------------------------------------ +# Define build steps, parse and validate input parameters +#------------------------------------------------------------------------------ + +# This script supports the following steps: +do_clean=no # Clean up the build directory. +do_copy_cross_tools=no # Copy cross-tools. +do_configure_llvm=no # Configure LLVM. +do_make_llvm=no # Make LLVM. +do_test_llvm=no # Test LLVM. +do_configure_llvmgcc=no # Configure LLVM-GCC. +do_make_llvmgcc=no # Make LLVM-GCC. +do_install_llvmgcc=no # Install LLVM-GCC. +do_all=no # Runs all steps at once when requested. + +# Set step parameter +if (( $# == 0 )) ; then + do_all=yes +fi +# else +if (( ! $# == 0 )) ; then + # First check that the parameter actually defines a step. + case $1 in + clean | \ + copy_cross_tools | \ + configure_llvm | \ + make_llvm | \ + test_llvm | \ + configure_llvmgcc | \ + make_llvmgcc | \ + install_llvmgcc | \ + all) + eval do_$1=yes # Set the flag for the requested step . + shift # Remove it since is is ours and already precessed. + ;; + + *) + # Not our parameter. Pass it as is. + esac +fi + +# Set all steps if do_all requested +if [ "$do_all" == "yes" ] ; then + # Set all steps to yes + do_clean=yes + do_copy_cross_tools=yes + do_configure_llvm=yes + do_make_llvm=yes + do_test_llvm=yes + do_configure_llvmgcc=yes + do_make_llvmgcc=yes + do_install_llvmgcc=yes +fi + +#------------------------------------------------------------------------------ +# Step: Clean up. +#------------------------------------------------------------------------------ +if [ "$do_clean" == "yes" ] ; then + + # Remove everything from where we will be installing the result. + rm -rf ${PRIVATE_INSTALL} + mkdir -p ${PRIVATE_INSTALL} + chmod a+rx ${PRIVATE_INSTALL} + +fi + +#------------------------------------------------------------------------------ +# Step: Copy cross-tools. +#------------------------------------------------------------------------------ +if [ "$do_copy_cross_tools" == "yes" ] ; then + + # We need a local copy of binutils, system libraries and headers, + # since we will be installing there. + cp -RL /cross-tools/ ${PRIVATE_INSTALL} + +fi + +#------------------------------------------------------------------------------ +# Step: Configure LLVM. +#------------------------------------------------------------------------------ +if [ "$do_configure_llvm" == "yes" ] ; then + + # Remove previously build files if any. + rm -rf ${BUILD_ROOT}/${LLVM_obj} + mkdir -p ${BUILD_ROOT}/${LLVM_obj} + chmod a+rx ${BUILD_ROOT}/${LLVM_obj} + cd ${BUILD_ROOT}/${LLVM_obj} + + ../${LLVM_src}/configure --prefix=${PRIVATE_INSTALL} \ + --build=x86_64-apple-darwin10 --host=x86_64-apple-darwin10 \ + --target=i686-pc-linux-gnu \ + --enable-optimize \ + $@ # Extra args if any + +fi + +#------------------------------------------------------------------------------ +# Step: Make LLVM. +#------------------------------------------------------------------------------ +if [ "$do_make_llvm" == "yes" ] ; then + + cd ${BUILD_ROOT}/${LLVM_obj} + # NOTE: Do not build with ENABLE_OPTIMIZED=1 - some test fail after it. + nice -n 20 make VERBOSE=1 \ + $@ # Extra args if any, like -j16 for example. + +fi + +#------------------------------------------------------------------------------ +# Step: Test LLVM. +#------------------------------------------------------------------------------ +if [ "$do_test_llvm" == "yes" ] ; then + + cd ${BUILD_ROOT}/${LLVM_obj} + make check-lit VERBOSE=1 \ + $@ # Extra args if any, like -j16 for example. + +fi + +#------------------------------------------------------------------------------ +# Step: Configure LLVM-GCC. +#------------------------------------------------------------------------------ +if [ "$do_configure_llvmgcc" == "yes" ] ; then + + # Remove previously build files if any. + rm -rf ${BUILD_ROOT}/${LLVM_GCC_obj} + mkdir -p ${BUILD_ROOT}/${LLVM_GCC_obj} + chmod a+rx ${BUILD_ROOT}/${LLVM_GCC_obj} + cd ${BUILD_ROOT}/${LLVM_GCC_obj} + +# TODO: check the next comment +# We want this cross-compiler to have prefix of the target platform +# instead of llvm-, so we would not rename it later to get used as a cross. + + ../${LLVM_GCC_src}/configure --prefix=${PRIVATE_INSTALL} \ + --build=x86_64-apple-darwin10 --host=x86_64-apple-darwin10 \ + --target=i686-pc-linux-gnu \ + --with-local-prefix=/tools \ + --program-prefix=llvm- \ + --enable-llvm=${BUILD_ROOT}/${LLVM_obj} \ + --enable-languages=c,c++ \ + --disable-multilib --disable-nls \ + $@ # Extra args if any +fi + +#------------------------------------------------------------------------------ +# Step: Make LLVM-GCC. +#------------------------------------------------------------------------------ +if [ "$do_make_llvmgcc" == "yes" ] ; then + + cd ${BUILD_ROOT}/${LLVM_GCC_obj} + # NOTE: Do not build in parallel! It doesn't build. + nice -n 20 make \ + $@ # Extra args if any + +fi + +#------------------------------------------------------------------------------ +# Step: Install LLVM-GCC. +#------------------------------------------------------------------------------ +if [ "$do_install_llvmgcc" == "yes" ] ; then + + cd ${BUILD_ROOT}/${LLVM_GCC_obj} + nice -n 20 make install \ + $@ # Extra args if any + +fi Propchange: llvm-gcc-4.2/trunk/extras/build-x-4-linux ------------------------------------------------------------------------------ svn:executable = * From grosbach at apple.com Mon Jun 14 19:41:09 2010 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 15 Jun 2010 00:41:09 -0000 Subject: [llvm-commits] [llvm] r105982 - /llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Message-ID: <20100615004109.EAE372A6C12C@llvm.org> Author: grosbach Date: Mon Jun 14 19:41:09 2010 New Revision: 105982 URL: http://llvm.org/viewvc/llvm-project?rev=105982&view=rev Log: Make sure to skip dbg_value instructions when finding an insertion point for the combined load/store instruction. rdar://7797940 Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=105982&r1=105981&r2=105982&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Mon Jun 14 19:41:09 2010 @@ -1491,7 +1491,8 @@ } else { // This is the new location for the loads / stores. MachineBasicBlock::iterator InsertPos = isLd ? FirstOp : LastOp; - while (InsertPos != MBB->end() && MemOps.count(InsertPos)) + while (InsertPos != MBB->end() + && (MemOps.count(InsertPos) || InsertPos->isDebugValue())) ++InsertPos; // If we are moving a pair of loads / stores, see if it makes sense From nelhage at nelhage.com Mon Jun 14 20:25:43 2010 From: nelhage at nelhage.com (Nelson Elhage) Date: Mon, 14 Jun 2010 21:25:43 -0400 Subject: [llvm-commits] [patch] X86FastISel can't handle loads through %fs or %gs Message-ID: <87r5k9dr3c.fsf@mit.edu> A non-text attachment was scrubbed... Name: x86-fast-isel-fs-load.diff Type: text/x-diff Size: 994 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100614/a6af1725/attachment.bin From bigcheesegs at gmail.com Mon Jun 14 21:10:48 2010 From: bigcheesegs at gmail.com (Michael Spencer) Date: Mon, 14 Jun 2010 22:10:48 -0400 Subject: [llvm-commits] [llvm] r105959 - in /llvm/trunk: include/llvm/CodeGen/PostRAHazardRecognizer.h lib/CodeGen/ExactHazardRecognizer.cpp lib/CodeGen/ExactHazardRecognizer.h lib/CodeGen/PostRAHazardRecognizer.cpp lib/CodeGen/PostRASchedulerList.cpp lib Message-ID: On Mon, Jun 14, 2010 at 5:06 PM, Evan Cheng wrote: > ? ?llvm/trunk/lib/CodeGen/PostRAHazardRecognizer.cpp > ? ? ?- copied, changed from r105940, llvm/trunk/lib/CodeGen/ExactHazardRecognizer.cpp This breaks the build with MSVC for me. CMake reports that lib/CodeGen/PostRAHazardRecognizer.cpp was not found in lib/CodeGen/CMakeLists.txt - Michael Spencer From dalej at apple.com Mon Jun 14 22:13:49 2010 From: dalej at apple.com (Dale Johannesen) Date: Tue, 15 Jun 2010 03:13:49 -0000 Subject: [llvm-commits] [llvm] r105986 - /llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Message-ID: <20100615031350.0154E2A6C12C@llvm.org> Author: johannes Date: Mon Jun 14 22:13:49 2010 New Revision: 105986 URL: http://llvm.org/viewvc/llvm-project?rev=105986&view=rev Log: The form of BuildMI used for TAILJMPr was changing the register containing the target address, an input, into an output. I don't think this actually broke anything on x86 (it does on ARM), but it's wrong. Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=105986&r1=105985&r2=105986&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Mon Jun 14 22:13:49 2010 @@ -1279,9 +1279,11 @@ for (unsigned i = 0; i != 5; ++i) MIB.addOperand(MBBI->getOperand(i)); } else if (RetOpcode == X86::TCRETURNri64) { - BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64), JumpTarget.getReg()); + BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64)). + addReg(JumpTarget.getReg(), JumpTarget.getTargetFlags()); } else { - BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr), JumpTarget.getReg()); + BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr)). + addReg(JumpTarget.getReg(), JumpTarget.getTargetFlags()); } MachineInstr *NewMI = prior(MBBI); From kremenek at apple.com Mon Jun 14 23:08:14 2010 From: kremenek at apple.com (Ted Kremenek) Date: Tue, 15 Jun 2010 04:08:14 -0000 Subject: [llvm-commits] [llvm] r105987 - /llvm/trunk/lib/CodeGen/CMakeLists.txt Message-ID: <20100615040814.F20622A6C12C@llvm.org> Author: kremenek Date: Mon Jun 14 23:08:14 2010 New Revision: 105987 URL: http://llvm.org/viewvc/llvm-project?rev=105987&view=rev Log: Update CMake build. Modified: llvm/trunk/lib/CodeGen/CMakeLists.txt Modified: llvm/trunk/lib/CodeGen/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CMakeLists.txt?rev=105987&r1=105986&r2=105987&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CMakeLists.txt (original) +++ llvm/trunk/lib/CodeGen/CMakeLists.txt Mon Jun 14 23:08:14 2010 @@ -1,6 +1,6 @@ add_llvm_library(LLVMCodeGen - Analysis.cpp AggressiveAntiDepBreaker.cpp + Analysis.cpp BranchFolding.cpp CalcSpillWeights.cpp CodePlacementOpt.cpp @@ -9,7 +9,6 @@ DwarfEHPrepare.cpp ELFCodeEmitter.cpp ELFWriter.cpp - ExactHazardRecognizer.cpp GCMetadata.cpp GCMetadataPrinter.cpp GCStrategy.cpp @@ -45,6 +44,7 @@ OptimizePHIs.cpp PHIElimination.cpp Passes.cpp + PostRAHazardRecognizer.cpp PostRASchedulerList.cpp PreAllocSplitting.cpp ProcessImplicitDefs.cpp From nicholas at mxc.ca Mon Jun 14 23:42:59 2010 From: nicholas at mxc.ca (Nick Lewycky) Date: Mon, 14 Jun 2010 21:42:59 -0700 Subject: [llvm-commits] [patch] Small fixes to the gold plugin In-Reply-To: References: Message-ID: <4C1704D3.8070600@mxc.ca> Rafael Espindola wrote: >>> The second fix is a special case for _start. We need this for the >>> uncommon situation that a full program is LLVM IL (including the crt* >>> files). In this case the resolution of nothing is LDPR_PREVAILING_DEF >>> and we drop all symbols. >> >> Uh, no. This fix belongs in the gold linker since _start is a special case >> in the operating system and will apply to all forms of dead global >> elimination (including garbage collection inside the linker) and across all >> plugins. If gold is ported to a different operating system where _start >> isn't special but another symbol is, the plugins shouldn't all need to >> change. >> Gold should treat _start as though it were referenced by native code. Does >> that sound sensible? > > Yes. I was not sure if we should count the runtime reference to it, > but it makes sense. It is similar to what gold tells us when producing > shared libraries. I will commit the other part and try to fix this in > gold. Thanks! Nick >> Nick >> > > Thanks, From nicholas at mxc.ca Mon Jun 14 23:44:22 2010 From: nicholas at mxc.ca (Nick Lewycky) Date: Mon, 14 Jun 2010 21:44:22 -0700 Subject: [llvm-commits] [llvm] r85419 - /llvm/trunk/tools/gold/gold-plugin.cpp In-Reply-To: <200910281855.n9SItt4r014991@zion.cs.uiuc.edu> References: <200910281855.n9SItt4r014991@zion.cs.uiuc.edu> Message-ID: <4C170526.5000805@mxc.ca> Viktor Kutuzov wrote: > Author: vkutuzov > Date: Wed Oct 28 13:55:55 2009 > New Revision: 85419 > > URL: http://llvm.org/viewvc/llvm-project?rev=85419&view=rev > Log: > Fix to pass options from Gold plugin to LTO codegen > > Modified: > llvm/trunk/tools/gold/gold-plugin.cpp > > Modified: llvm/trunk/tools/gold/gold-plugin.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/gold/gold-plugin.cpp?rev=85419&r1=85418&r2=85419&view=diff > > ============================================================================== > --- llvm/trunk/tools/gold/gold-plugin.cpp (original) > +++ llvm/trunk/tools/gold/gold-plugin.cpp Wed Oct 28 13:55:55 2009 > @@ -46,9 +46,6 @@ > int api_version = 0; > int gold_version = 0; > > - bool generate_api_file = false; > - const char *as_path = NULL; > - > struct claimed_file { > lto_module_t M; > void *handle; > @@ -60,6 +57,37 @@ > std::vector Cleanup; > } > > +namespace options { > + bool generate_api_file = false; > + const char *as_path = NULL; > + // Additional options to pass into the code generator. > + // Note: This array will contain all plugin options which are not claimed > + // as plugin exclusive to pass to the code generator. > + // For example, "generate-api-file" and "as"options are for the plugin > + // use only and will not be passed. > + std::vector extra; > + > + void process_plugin_option(const char* opt) > + { > + if (opt == NULL) > + return; > + > + if (strcmp("generate-api-file", opt) == 0) { > + generate_api_file = true; > + } else if (strncmp("as=", opt, 3) == 0) { > + if (as_path) { > + (*message)(LDPL_WARNING, "Path to as specified twice. " > + "Discarding %s", opt); > + } else { > + as_path = strdup(opt + 3); > + } > + } else { > + // Save this option to pass to the code generator. > + extra.push_back(std::string(opt)); > + } I don't like this at all. We shouldn't just pass an option through because we don't know what it is. This needs to test for some sort of prefix. > + } > +} > + > ld_plugin_status claim_file_hook(const ld_plugin_input_file *file, > int *claimed); > ld_plugin_status all_symbols_read_hook(void); > @@ -103,18 +131,7 @@ > //output_type = LTO_CODEGEN_PIC_MODEL_DYNAMIC_NO_PIC; > break; > case LDPT_OPTION: > - if (strcmp("generate-api-file", tv->tv_u.tv_string) == 0) { > - generate_api_file = true; > - } else if (strncmp("as=", tv->tv_u.tv_string, 3) == 0) { > - if (as_path) { > - (*message)(LDPL_WARNING, "Path to as specified twice. " > - "Discarding %s", tv->tv_u.tv_string); > - } else { > - as_path = strdup(tv->tv_u.tv_string + 3); > - } > - } else { > - (*message)(LDPL_WARNING, "Ignoring flag %s", tv->tv_u.tv_string); > - } > + options::process_plugin_option(tv->tv_u.tv_string); > break; > case LDPT_REGISTER_CLAIM_FILE_HOOK: { > ld_plugin_register_claim_file callback; > @@ -307,7 +324,7 @@ > lto_codegen_add_module(cg, I->M); > > std::ofstream api_file; > - if (generate_api_file) { > + if (options::generate_api_file) { > api_file.open("apifile.txt", std::ofstream::out | std::ofstream::trunc); > if (!api_file.is_open()) { > (*message)(LDPL_FATAL, "Unable to open apifile.txt for writing."); > @@ -329,13 +346,13 @@ > lto_codegen_add_must_preserve_symbol(cg, I->syms[i].name); > anySymbolsPreserved = true; > > - if (generate_api_file) > + if (options::generate_api_file) > api_file<< I->syms[i].name<< "\n"; > } > } > } > > - if (generate_api_file) > + if (options::generate_api_file) > api_file.close(); > > if (!anySymbolsPreserved) { > @@ -347,10 +364,17 @@ > > lto_codegen_set_pic_model(cg, output_type); > lto_codegen_set_debug_model(cg, LTO_DEBUG_MODEL_DWARF); > - if (as_path) { > - sys::Path p = sys::Program::FindProgramByName(as_path); > + if (options::as_path) { > + sys::Path p = sys::Program::FindProgramByName(options::as_path); > lto_codegen_set_assembler_path(cg, p.c_str()); > } > + // Pass through extra options to the code generator. > + if (!options::extra.empty()) { > + for (std::vector::iterator it = options::extra.begin(); > + it != options::extra.end(); ++it) { This violates the LLVM coding style. http://llvm.org/docs/CodingStandards.html#ll_end Nick > + lto_codegen_debug_options(cg, (*it).c_str()); > + } > + } > > size_t bufsize = 0; > const char *buffer = static_cast(lto_codegen_compile(cg, > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From dalej at apple.com Mon Jun 14 23:55:07 2010 From: dalej at apple.com (Dale Johannesen) Date: Tue, 15 Jun 2010 04:55:07 -0000 Subject: [llvm-commits] [llvm] r105988 - /llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Message-ID: <20100615045507.0BAE52A6C12C@llvm.org> Author: johannes Date: Mon Jun 14 23:55:06 2010 New Revision: 105988 URL: http://llvm.org/viewvc/llvm-project?rev=105988&view=rev Log: Revert 105986; looks like I'd better try bootstrapping. Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=105988&r1=105987&r2=105988&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Mon Jun 14 23:55:06 2010 @@ -1279,11 +1279,9 @@ for (unsigned i = 0; i != 5; ++i) MIB.addOperand(MBBI->getOperand(i)); } else if (RetOpcode == X86::TCRETURNri64) { - BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64)). - addReg(JumpTarget.getReg(), JumpTarget.getTargetFlags()); + BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64), JumpTarget.getReg()); } else { - BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr)). - addReg(JumpTarget.getReg(), JumpTarget.getTargetFlags()); + BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr), JumpTarget.getReg()); } MachineInstr *NewMI = prior(MBBI); From daniel at zuster.org Tue Jun 15 00:34:25 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Tue, 15 Jun 2010 05:34:25 -0000 Subject: [llvm-commits] [zorg] r105989 - /zorg/trunk/lnt/lnt/tests/nt.py Message-ID: <20100615053425.9ECD42A6C12C@llvm.org> Author: ddunbar Date: Tue Jun 15 00:34:25 2010 New Revision: 105989 URL: http://llvm.org/viewvc/llvm-project?rev=105989&view=rev Log: LNT/nt: Add --no-machdep-info, which avoids putting stuff like the hostname in the machine info. Useful when wanting to report results from a group of machines and have the results shared. Modified: zorg/trunk/lnt/lnt/tests/nt.py Modified: zorg/trunk/lnt/lnt/tests/nt.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/tests/nt.py?rev=105989&r1=105988&r2=105989&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/tests/nt.py (original) +++ zorg/trunk/lnt/lnt/tests/nt.py Tue Jun 15 00:34:25 2010 @@ -346,27 +346,33 @@ # Collect the machine and run info. # - # FIXME: Support no-machdep-info. - # # FIXME: Import full range of data that the Clang tests are using? machine_info = {} - machine_info['uname'] = capture(["uname","-a"], - include_stderr=True).strip() machine_info['hardware'] = capture(["uname","-m"], include_stderr=True).strip() machine_info['os'] = capture(["uname","-sr"], include_stderr=True).strip() - machine_info['name'] = capture(["uname","-n"], include_stderr=True).strip() if opts.cc_reference is not None: machine_info['gcc_version'] = capture( [opts.cc_reference, '--version'], include_stderr=True).split('\n')[0] - machine = lnt.testing.Machine(nick, machine_info) # FIXME: We aren't getting the LLCBETA options. run_info = {} run_info['tag'] = test_namespace run_info.update(cc_info) + # Add machine dependent info. + if opts.use_machdep_info: + machdep_info = machine_info + else: + machdep_info = run_info + + machdep_info['uname'] = capture(["uname","-a"], include_stderr=True).strip() + machdep_info['name'] = capture(["uname","-n"], include_stderr=True).strip() + + # Create the machine entry. + machine = lnt.testing.Machine(nick, machine_info) + # FIXME: Hack, use better method of getting versions. Ideally, from binaries # so we are more likely to be accurate. run_info['llvm_revision'] = get_source_version(opts.llvm_src_root) @@ -599,7 +605,11 @@ group.add_option("", "--no-auto-name", dest="auto_name", help="Don't automatically derive submission name", action="store_false", default=True) - parser.add_option("", "--run-order", dest="run_order", metavar="STR", + group.add_option("", "--no-machdep-info", dest="use_machdep_info", + help=("Don't put machine (instance) dependent " + "variables with machine info"), + action="store_false", default=True) + group.add_option("", "--run-order", dest="run_order", metavar="STR", help="String to use to identify and order this run", action="store", type=str, default=None) parser.add_option_group(group) From bob.wilson at apple.com Tue Jun 15 00:51:27 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 15 Jun 2010 05:51:27 -0000 Subject: [llvm-commits] [llvm] r105990 - /llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Message-ID: <20100615055127.914AD2A6C12C@llvm.org> Author: bwilson Date: Tue Jun 15 00:51:27 2010 New Revision: 105990 URL: http://llvm.org/viewvc/llvm-project?rev=105990&view=rev Log: VMOVQQ and VMOVQQQQ are pseudo instructions and not predicable. Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=105990&r1=105989&r2=105990&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Jun 15 00:51:27 2010 @@ -759,7 +759,10 @@ else return false; - AddDefaultPred(BuildMI(MBB, I, DL, get(Opc), DestReg).addReg(SrcReg)); + MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); + MIB.addReg(SrcReg); + if (Opc != ARM::VMOVQQ && Opc != ARM::VMOVQQQQ) + AddDefaultPred(MIB); } return true; From bob.wilson at apple.com Tue Jun 15 00:56:32 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 15 Jun 2010 05:56:32 -0000 Subject: [llvm-commits] [llvm] r105991 - in /llvm/trunk: lib/CodeGen/TwoAddressInstructionPass.cpp test/CodeGen/ARM/2009-11-01-NeonMoves.ll Message-ID: <20100615055632.16CD22A6C12C@llvm.org> Author: bwilson Date: Tue Jun 15 00:56:31 2010 New Revision: 105991 URL: http://llvm.org/viewvc/llvm-project?rev=105991&view=rev Log: Generalize the pre-coalescing of extract_subregs feeding reg_sequences, replacing the overly conservative checks that I had introduced recently to deal with correctness issues. This makes a pretty noticable difference in our testcases where reg_sequences are used. I've updated one test to check that we no longer emit the unnecessary subreg moves. Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp llvm/trunk/test/CodeGen/ARM/2009-11-01-NeonMoves.ll Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=105991&r1=105990&r2=105991&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original) +++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Tue Jun 15 00:56:31 2010 @@ -33,6 +33,7 @@ #include "llvm/CodeGen/LiveVariables.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/Analysis/AliasAnalysis.h" #include "llvm/Target/TargetRegisterInfo.h" @@ -1183,11 +1184,8 @@ UI = MRI->use_nodbg_begin(SrcReg), UE = MRI->use_nodbg_end(); UI != UE; ++UI) { MachineInstr *UseMI = &*UI; - // FIXME: For now require that the destination subregs match the subregs - // being extracted. if (!UseMI->isExtractSubreg() || UseMI->getOperand(0).getReg() != DstReg || - UseMI->getOperand(0).getSubReg() != UseMI->getOperand(2).getImm() || UseMI->getOperand(1).getSubReg() != 0) { CanCoalesce = false; break; @@ -1198,40 +1196,92 @@ if (!CanCoalesce || SubIndices.size() < 2) continue; - // FIXME: For now require that the src and dst registers are in the - // same regclass. - if (MRI->getRegClass(SrcReg) != MRI->getRegClass(DstReg)) + std::sort(SubIndices.begin(), SubIndices.end()); + unsigned NewSrcSubIdx = 0; + if (!TRI->canCombineSubRegIndices(MRI->getRegClass(SrcReg), SubIndices, + NewSrcSubIdx)) continue; + // Now that we know that all the uses are extract_subregs and that those + // subregs can somehow be combined, scan all the extract_subregs again to + // make sure the subregs are in the right order and can be composed. + // Also keep track of the destination subregisters so we can make sure + // that those can be combined. + SubIndices.clear(); + MachineInstr *SomeMI = 0; + CanCoalesce = true; + for (MachineRegisterInfo::use_nodbg_iterator + UI = MRI->use_nodbg_begin(SrcReg), + UE = MRI->use_nodbg_end(); UI != UE; ++UI) { + MachineInstr *UseMI = &*UI; + assert(UseMI->isExtractSubreg()); + unsigned DstSubIdx = UseMI->getOperand(0).getSubReg(); + unsigned SrcSubIdx = UseMI->getOperand(2).getImm(); + assert(DstSubIdx != 0 && "missing subreg from RegSequence elimination"); + if (TRI->composeSubRegIndices(NewSrcSubIdx, DstSubIdx) != SrcSubIdx) { + CanCoalesce = false; + break; + } + SubIndices.push_back(DstSubIdx); + // Keep track of one of the uses. + SomeMI = UseMI; + } + if (!CanCoalesce) + continue; + + // Check that the destination subregisters can also be combined. std::sort(SubIndices.begin(), SubIndices.end()); - unsigned NewSubIdx = 0; - if (TRI->canCombineSubRegIndices(MRI->getRegClass(SrcReg), SubIndices, - NewSubIdx)) { - bool Proceed = true; - if (NewSubIdx) - for (MachineRegisterInfo::reg_nodbg_iterator - RI = MRI->reg_nodbg_begin(SrcReg), RE = MRI->reg_nodbg_end(); - RI != RE; ) { - MachineOperand &MO = RI.getOperand(); - ++RI; - // FIXME: If the sub-registers do not combine to the whole - // super-register, i.e. NewSubIdx != 0, and any of the use has a - // sub-register index, then abort the coalescing attempt. - if (MO.getSubReg()) { - Proceed = false; - break; - } - } - if (Proceed) - for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(SrcReg), - RE = MRI->reg_end(); RI != RE; ) { - MachineOperand &MO = RI.getOperand(); - ++RI; - MO.setReg(DstReg); - if (NewSubIdx) - MO.setSubReg(NewSubIdx); - } + unsigned NewDstSubIdx = 0; + if (!TRI->canCombineSubRegIndices(MRI->getRegClass(DstReg), SubIndices, + NewDstSubIdx)) + continue; + + // If neither source nor destination can be combined to the full register, + // just give up. This could be improved if it ever matters. + if (NewSrcSubIdx != 0 && NewDstSubIdx != 0) + continue; + + // Insert a copy or an extract to replace the original extracts. + MachineBasicBlock::iterator InsertLoc = SomeMI; + if (NewSrcSubIdx) { + // Insert an extract subreg. + BuildMI(*SomeMI->getParent(), InsertLoc, SomeMI->getDebugLoc(), + TII->get(TargetOpcode::EXTRACT_SUBREG), DstReg) + .addReg(SrcReg).addImm(NewSrcSubIdx); + } else if (NewDstSubIdx) { + // Do a subreg insertion. + BuildMI(*SomeMI->getParent(), InsertLoc, SomeMI->getDebugLoc(), + TII->get(TargetOpcode::INSERT_SUBREG), DstReg) + .addReg(DstReg).addReg(SrcReg).addImm(NewDstSubIdx); + } else { + // Insert a copy. + bool Emitted = + TII->copyRegToReg(*SomeMI->getParent(), InsertLoc, DstReg, SrcReg, + MRI->getRegClass(DstReg), MRI->getRegClass(SrcReg), + SomeMI->getDebugLoc()); + (void)Emitted; + } + MachineBasicBlock::iterator CopyMI = prior(InsertLoc); + + // Remove all the old extract instructions. + for (MachineRegisterInfo::use_nodbg_iterator + UI = MRI->use_nodbg_begin(SrcReg), + UE = MRI->use_nodbg_end(); UI != UE; ) { + MachineInstr *UseMI = &*UI; + ++UI; + if (UseMI == CopyMI) + continue; + assert(UseMI->isExtractSubreg()); + // Move any kills to the new copy or extract instruction. + if (UseMI->getOperand(1).isKill()) { + MachineOperand *KillMO = CopyMI->findRegisterUseOperand(SrcReg); + KillMO->setIsKill(); + if (LV) + // Update live variables + LV->replaceKillInstruction(SrcReg, UseMI, &*CopyMI); } + UseMI->eraseFromParent(); + } } } Modified: llvm/trunk/test/CodeGen/ARM/2009-11-01-NeonMoves.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-11-01-NeonMoves.ll?rev=105991&r1=105990&r2=105991&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-11-01-NeonMoves.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2009-11-01-NeonMoves.ll Tue Jun 15 00:56:31 2010 @@ -11,11 +11,11 @@ %0 = getelementptr inbounds %foo* %quat_addr, i32 0, i32 0 ; <<4 x float>*> [#uses=1] store <4 x float> %quat.0, <4 x float>* %0 %1 = call arm_aapcs_vfpcc <4 x float> @quux(%foo* %quat_addr) nounwind ; <<4 x float>> [#uses=3] -;CHECK: vmov.f32 -;CHECK: vmov.f32 %2 = fmul <4 x float> %1, %1 ; <<4 x float>> [#uses=2] %3 = shufflevector <4 x float> %2, <4 x float> undef, <2 x i32> ; <<2 x float>> [#uses=1] %4 = shufflevector <4 x float> %2, <4 x float> undef, <2 x i32> ; <<2 x float>> [#uses=1] +;CHECK-NOT: vmov +;CHECK: vpadd %5 = call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> %3, <2 x float> %4) nounwind ; <<2 x float>> [#uses=2] %6 = call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> %5, <2 x float> %5) nounwind ; <<2 x float>> [#uses=2] %7 = shufflevector <2 x float> %6, <2 x float> %6, <4 x i32> ; <<4 x float>> [#uses=2] From dimitry at andric.com Tue Jun 15 09:43:44 2010 From: dimitry at andric.com (Dimitry Andric) Date: Tue, 15 Jun 2010 16:43:44 +0200 Subject: [llvm-commits] [LLVMbugs] [Bug 7322] ms vcpp build warnings In-Reply-To: <20100614203927.C1E7A2A6C12C@llvm.org> References: <20100614203927.C1E7A2A6C12C@llvm.org> Message-ID: <4C1791A0.9030604@andric.com> On 2010-06-14 22:39, bugzilla-daemon at llvm.org wrote: > --- Comment #1 from Chris Lattner 2010-06-14 15:39:27 CDT --- > there are a bunch of build warnings with MSVC. If you're interested in helping > with this, please send patches to llvm-commits, thanks! What I see quite often with VC++ is this warning: .\NeonEmitter.cpp(529) : warning C4804: '<<' : unsafe use of type 'bool' in operation which comes from bool variables used as shift count, e.g: bool dummy, quad = false; ... b = Duplicate(nElts << quad, typestr, "b"); I'm not sure if this is unnecessarily paranoid of VC++, as the standard seems to imply it should be no problem, if I read it correctly: [conv.prom] 4. An rvalue of type bool can be converted to an rvalue of type int, with false becoming zero and true becoming one. and [conv.integral]: 4. If the destination type is bool, see 4.12. If the source type is bool, the value false is converted to zero and the value true is converted to one. In short, is it worthwhile to appease VC++ here, by using an int or unsigned instead, or should we just stash in a pragma to disable this particular warning? From daniel at zuster.org Tue Jun 15 09:50:42 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Tue, 15 Jun 2010 14:50:42 -0000 Subject: [llvm-commits] [llvm] r105994 - /llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.h Message-ID: <20100615145042.CE7C92A6C12C@llvm.org> Author: ddunbar Date: Tue Jun 15 09:50:42 2010 New Revision: 105994 URL: http://llvm.org/viewvc/llvm-project?rev=105994&view=rev Log: Add include to get ptrdiff_t, for gcc-4.6; patch by Dimitry Andric. Modified: llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.h Modified: llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.h?rev=105994&r1=105993&r2=105994&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.h (original) +++ llvm/trunk/lib/Target/ARM/ARMConstantPoolValue.h Tue Jun 15 09:50:42 2010 @@ -15,6 +15,7 @@ #define LLVM_TARGET_ARM_CONSTANTPOOLVALUE_H #include "llvm/CodeGen/MachineConstantPool.h" +#include namespace llvm { From daniel at zuster.org Tue Jun 15 09:58:25 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Tue, 15 Jun 2010 07:58:25 -0700 Subject: [llvm-commits] [cfe-commits] [llvm] r105786 - in /llvm/trunk/include/llvm: ADT/DenseMap.h ADT/SmallVector.h ADT/ilist.h Use.h In-Reply-To: <4C1610CA.7020609@andric.com> References: <20100610101358.943472A6C12C@llvm.org> <4C1610CA.7020609@andric.com> Message-ID: On Mon, Jun 14, 2010 at 4:21 AM, Dimitry Andric wrote: > On 2010-06-10 12:13, Duncan Sands wrote: >> Author: baldrick >> Date: Thu Jun 10 05:13:58 2010 >> New Revision: 105786 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=105786&view=rev >> Log: >> Add includes to get ptrdiff_t. ?This is needed by gcc-4.6 which has >> done some more header trimming, resulting in cstdef being included >> by less header files. > > Compiling on my FreeBSD box with gcc 4.6.0 20100605 gave an additional > complaint about NULL not being defined in ARMConstantPoolValue.h, and > another few about ptrdiff_t in clang. ?These are all fixed by the > attached patches; please review. Applied in r105994 and r105995, thanks! - Daniel > > _______________________________________________ > cfe-commits mailing list > cfe-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/cfe-commits > > From stoklund at 2pi.dk Tue Jun 15 11:04:22 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 15 Jun 2010 16:04:22 -0000 Subject: [llvm-commits] [llvm] r105997 - in /llvm/trunk: include/llvm/CodeGen/RegisterCoalescer.h lib/CodeGen/RegisterCoalescer.cpp lib/CodeGen/SimpleRegisterCoalescing.cpp lib/CodeGen/SimpleRegisterCoalescing.h test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll Message-ID: <20100615160422.2ACB92A6C12C@llvm.org> Author: stoklund Date: Tue Jun 15 11:04:21 2010 New Revision: 105997 URL: http://llvm.org/viewvc/llvm-project?rev=105997&view=rev Log: Add CoalescerPair helper class. Given a copy instruction, CoalescerPair can determine which registers to coalesce in order to eliminate the copy. It deals with all the subreg fun to determine a tuple (DstReg, SrcReg, SubIdx) such that: - SrcReg is a virtual register that will disappear after coalescing. - DstReg is a virtual or physical register whose live range will be extended. - SubIdx is 0 when DstReg is a physical register. - SrcReg can be joined with DstReg:SubIdx. CoalescerPair::isCoalescable() determines if another copy instruction is compatible with the same tuple. This fixes some NEON miscompilations where shuffles are getting coalesced as if they were copies. The CoalescerPair class will replace a lot of the spaghetti logic in JoinCopy later. Added: llvm/trunk/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll Modified: llvm/trunk/include/llvm/CodeGen/RegisterCoalescer.h llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h Modified: llvm/trunk/include/llvm/CodeGen/RegisterCoalescer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/RegisterCoalescer.h?rev=105997&r1=105996&r2=105997&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/RegisterCoalescer.h (original) +++ llvm/trunk/include/llvm/CodeGen/RegisterCoalescer.h Tue Jun 15 11:04:21 2010 @@ -25,6 +25,9 @@ class RegallocQuery; class AnalysisUsage; class MachineInstr; + class TargetRegisterInfo; + class TargetRegisterClass; + class TargetInstrInfo; /// An abstract interface for register coalescers. Coalescers must /// implement this interface to be part of the coalescer analysis @@ -141,6 +144,87 @@ return true; } }; + + + /// CoalescerPair - A helper class for register coalescers. When deciding if + /// two registers can be coalesced, CoalescerPair can determine if a copy + /// instruction would become an identity copy after coalescing. + class CoalescerPair { + const TargetInstrInfo &tii_; + const TargetRegisterInfo &tri_; + + /// dstReg_ - The register that will be left after coalescing. It can be a + /// virtual or physical register. + unsigned dstReg_; + + /// srcReg_ - the virtual register that will be coalesced into dstReg. + unsigned srcReg_; + + /// subReg_ - The subregister index of srcReg in dstReg_. It is possible the + /// coalesce srcReg_ into a subreg of the larger dstReg_ when dstReg_ is a + /// virtual register. + unsigned subIdx_; + + /// partial_ - True when the original copy was a partial subregister copy. + bool partial_; + + /// flipped_ - True when DstReg and SrcReg are reversed from the oriignal copy + /// instruction. + bool flipped_; + + /// newRC_ - The register class of the coalesced register, or NULL if dstReg_ + /// is a physreg. + const TargetRegisterClass *newRC_; + + /// compose - Compose subreg indices a and b, either may be 0. + unsigned compose(unsigned, unsigned) const; + + /// isMoveInstr - Return true if MI is a move or subreg instruction. + bool isMoveInstr(const MachineInstr *MI, unsigned &Src, unsigned &Dst, + unsigned &SrcSub, unsigned &DstSub) const; + + public: + CoalescerPair(const TargetInstrInfo &tii, const TargetRegisterInfo &tri) + : tii_(tii), tri_(tri), dstReg_(0), srcReg_(0), subIdx_(0), + partial_(false), flipped_(false), newRC_(0) {} + + /// setRegisters - set registers to match the copy instruction MI. Return + /// false if MI is not a coalescable copy instruction. + bool setRegisters(const MachineInstr*); + + /// flip - Swap srcReg_ and dstReg_. Return false if swapping is impossible + /// because dstReg_ is a physical register, or subIdx_ is set. + bool flip(); + + /// isCoalescable - Return true if MI is a copy instruction that will become + /// an identity copy after coalescing. + bool isCoalescable(const MachineInstr*) const; + + /// isPhys - Return true if DstReg is a physical register. + bool isPhys() const { return !newRC_; } + + /// isPartial - Return true if the original copy instruction did not copy the + /// full register, but was a subreg operation. + bool isPartial() const { return partial_; } + + /// isFlipped - Return true when getSrcReg is the register being defined by + /// the original copy instruction. + bool isFlipped() const { return flipped_; } + + /// getDstReg - Return the register (virtual or physical) that will remain + /// after coalescing. + unsigned getDstReg() const { return dstReg_; } + + /// getSrcReg - Return the virtual register that will be coalesced away. + unsigned getSrcReg() const { return srcReg_; } + + /// getSubIdx - Return the subregister index in DstReg that SrcReg will be + /// coalesced into, or 0. + unsigned getSubIdx() const { return subIdx_; } + + /// getNewRC - Return the register class of the coalesced register. + const TargetRegisterClass *getNewRC() const { return newRC_; } + }; } // Because of the way .a files work, we must force the SimpleRC Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp?rev=105997&r1=105996&r2=105997&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp (original) +++ llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp Tue Jun 15 11:04:21 2010 @@ -16,6 +16,8 @@ #include "llvm/CodeGen/RegisterCoalescer.h" #include "llvm/CodeGen/LiveIntervalAnalysis.h" #include "llvm/CodeGen/MachineInstr.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Pass.h" @@ -33,6 +35,151 @@ // RegisterCoalescer::~RegisterCoalescer() {} +unsigned CoalescerPair::compose(unsigned a, unsigned b) const { + if (!a) return b; + if (!b) return a; + return tri_.composeSubRegIndices(a, b); +} + +bool CoalescerPair::isMoveInstr(const MachineInstr *MI, + unsigned &Src, unsigned &Dst, + unsigned &SrcSub, unsigned &DstSub) const { + if (MI->isExtractSubreg()) { + Dst = MI->getOperand(0).getReg(); + DstSub = MI->getOperand(0).getSubReg(); + Src = MI->getOperand(1).getReg(); + SrcSub = compose(MI->getOperand(1).getSubReg(), MI->getOperand(2).getImm()); + } else if (MI->isInsertSubreg() || MI->isSubregToReg()) { + Dst = MI->getOperand(0).getReg(); + DstSub = compose(MI->getOperand(0).getSubReg(), MI->getOperand(3).getImm()); + Src = MI->getOperand(2).getReg(); + SrcSub = MI->getOperand(2).getSubReg(); + } else if (!tii_.isMoveInstr(*MI, Src, Dst, SrcSub, DstSub)) { + return false; + } + return true; +} + +bool CoalescerPair::setRegisters(const MachineInstr *MI) { + srcReg_ = dstReg_ = subIdx_ = 0; + newRC_ = 0; + flipped_ = false; + + unsigned Src, Dst, SrcSub, DstSub; + if (!isMoveInstr(MI, Src, Dst, SrcSub, DstSub)) + return false; + partial_ = SrcSub || DstSub; + + // If one register is a physreg, it must be Dst. + if (TargetRegisterInfo::isPhysicalRegister(Src)) { + if (TargetRegisterInfo::isPhysicalRegister(Dst)) + return false; + std::swap(Src, Dst); + std::swap(SrcSub, DstSub); + flipped_ = true; + } + + const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); + + if (TargetRegisterInfo::isPhysicalRegister(Dst)) { + // Eliminate DstSub on a physreg. + if (DstSub) { + Dst = tri_.getSubReg(Dst, DstSub); + if (!Dst) return false; + DstSub = 0; + } + + // Eliminate SrcSub by picking a corresponding Dst superregister. + if (SrcSub) { + Dst = tri_.getMatchingSuperReg(Dst, SrcSub, MRI.getRegClass(Src)); + if (!Dst) return false; + SrcSub = 0; + } else if (!MRI.getRegClass(Src)->contains(Dst)) { + return false; + } + } else { + // Both registers are virtual. + + // Identical sub to sub. + if (SrcSub == DstSub) + SrcSub = DstSub = 0; + else if (SrcSub && DstSub) + return false; // FIXME: Qreg:ssub_3 + Dreg:ssub_1 => QReg:dsub_1 + Dreg. + + // There can be no SrcSub. + if (SrcSub) { + std::swap(Src, Dst); + DstSub = SrcSub; + SrcSub = 0; + assert(!flipped_ && "Unexpected flip"); + flipped_ = true; + } + + // Find the new register class. + const TargetRegisterClass *SrcRC = MRI.getRegClass(Src); + const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); + if (DstSub) + newRC_ = tri_.getMatchingSuperRegClass(DstRC, SrcRC, DstSub); + else + newRC_ = getCommonSubClass(DstRC, SrcRC); + if (!newRC_) + return false; + } + // Check our invariants + assert(TargetRegisterInfo::isVirtualRegister(Src) && "Src must be virtual"); + assert(!(TargetRegisterInfo::isPhysicalRegister(Dst) && DstSub) && + "Cannot have a physical SubIdx"); + srcReg_ = Src; + dstReg_ = Dst; + subIdx_ = DstSub; + return true; +} + +bool CoalescerPair::flip() { + if (subIdx_ || TargetRegisterInfo::isPhysicalRegister(dstReg_)) + return false; + std::swap(srcReg_, dstReg_); + flipped_ = !flipped_; + return true; +} + +bool CoalescerPair::isCoalescable(const MachineInstr *MI) const { + if (!MI) + return false; + unsigned Src, Dst, SrcSub, DstSub; + if (!isMoveInstr(MI, Src, Dst, SrcSub, DstSub)) + return false; + + // Find the virtual register that is srcReg_. + if (Dst == srcReg_) { + std::swap(Src, Dst); + std::swap(SrcSub, DstSub); + } else if (Src != srcReg_) { + return false; + } + + // Now check that Dst matches dstReg_. + if (TargetRegisterInfo::isPhysicalRegister(dstReg_)) { + if (!TargetRegisterInfo::isPhysicalRegister(Dst)) + return false; + assert(!subIdx_ && "Inconsistent CoalescerPair state."); + // DstSub could be set for a physreg from INSERT_SUBREG. + if (DstSub) + Dst = tri_.getSubReg(Dst, DstSub); + // Full copy of Src. + if (!SrcSub) + return dstReg_ == Dst; + // This is a partial register copy. Check that the parts match. + return tri_.getSubReg(dstReg_, SrcSub) == Dst; + } else { + // dstReg_ is virtual. + if (dstReg_ != Dst) + return false; + // Registers match, do the subregisters line up? + return compose(subIdx_, SrcSub) == DstSub; + } +} + // Because of the way .a files work, we must force the SimpleRC // implementation to be pulled in if the RegisterCoalescer classes are // pulled in. Otherwise we run the risk of RegisterCoalescer being Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=105997&r1=105996&r2=105997&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original) +++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Tue Jun 15 11:04:21 2010 @@ -1395,6 +1395,12 @@ return false; // Not coalescable. } + CoalescerPair CP(*tii_, *tri_); + if (!CP.setRegisters(CopyMI)) { + DEBUG(dbgs() << "\tNot coalescable.\n"); + return false; + } + bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg); bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg); @@ -1722,7 +1728,7 @@ DEBUG(dbgs() << "\tNot profitable!\n"); return false; } - } else if (!JoinIntervals(DstInt, SrcInt, Swapped)) { + } else if (!JoinIntervals(DstInt, SrcInt, Swapped, CP)) { // Coalescing failed. // If definition of source is defined by trivial computation, try @@ -1919,33 +1925,13 @@ return std::find(V.begin(), V.end(), Val) != V.end(); } -static bool isValNoDefMove(const MachineInstr *MI, unsigned DR, unsigned SR, - const TargetInstrInfo *TII, - const TargetRegisterInfo *TRI) { - unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx; - if (TII->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) - ; - else if (MI->isExtractSubreg()) { - DstReg = MI->getOperand(0).getReg(); - SrcReg = MI->getOperand(1).getReg(); - } else if (MI->isSubregToReg() || - MI->isInsertSubreg()) { - DstReg = MI->getOperand(0).getReg(); - SrcReg = MI->getOperand(2).getReg(); - } else - return false; - return (SrcReg == SR || TRI->isSuperRegister(SR, SrcReg)) && - (DstReg == DR || TRI->isSuperRegister(DR, DstReg)); -} - /// RangeIsDefinedByCopyFromReg - Return true if the specified live range of /// the specified live interval is defined by a copy from the specified /// register. -bool SimpleRegisterCoalescing::RangeIsDefinedByCopyFromReg(LiveInterval &li, - LiveRange *LR, - unsigned Reg) { - unsigned SrcReg = li_->getVNInfoSourceReg(LR->valno); - if (SrcReg == Reg) +bool SimpleRegisterCoalescing::RangeIsDefinedByCopy(LiveInterval &li, + LiveRange *LR, + CoalescerPair &CP) { + if (CP.isCoalescable(LR->valno->getCopy())) return true; // FIXME: Do isPHIDef and isDefAccurate both need to be tested? if ((LR->valno->isPHIDef() || !LR->valno->isDefAccurate()) && @@ -1954,7 +1940,7 @@ // It's a sub-register live interval, we may not have precise information. // Re-compute it. MachineInstr *DefMI = li_->getInstructionFromIndex(LR->start); - if (DefMI && isValNoDefMove(DefMI, li.reg, Reg, tii_, tri_)) { + if (CP.isCoalescable(DefMI)) { // Cache computed info. LR->valno->def = LR->start; LR->valno->setCopy(DefMI); @@ -1986,7 +1972,8 @@ /// value number and that the RHS is not defined by a copy from this /// interval. This returns false if the intervals are not joinable, or it /// joins them and returns true. -bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){ +bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS, + CoalescerPair &CP) { assert(RHS.containsOneValue()); // Some number (potentially more than one) value numbers in the current @@ -2028,7 +2015,7 @@ if (LHSIt->valno->hasRedefByEC()) return false; // Copy from the RHS? - if (!RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg)) + if (!RangeIsDefinedByCopy(LHS, LHSIt, CP)) return false; // Nope, bail out. if (ValueLiveAt(LHSIt, LHS.end(), RHSIt->valno->def)) @@ -2072,7 +2059,7 @@ return false; // Otherwise, if this is a copy from the RHS, mark it as being merged // in. - if (RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg)) { + if (RangeIsDefinedByCopy(LHS, LHSIt, CP)) { if (ValueLiveAt(LHSIt, LHS.end(), RHSIt->valno->def)) // Here is an interesting situation: // BB1: @@ -2171,7 +2158,7 @@ /// below to update aliases. bool SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS, - bool &Swapped) { + bool &Swapped, CoalescerPair &CP) { // Compute the final value assignment, assuming that the live ranges can be // coalesced. SmallVector LHSValNoAssignments; @@ -2252,7 +2239,7 @@ // faster checks to see if the live ranges are coalescable. This joiner // can't swap the LHS/RHS intervals though. if (!TargetRegisterInfo::isPhysicalRegister(RHS.reg)) { - return SimpleJoin(LHS, RHS); + return SimpleJoin(LHS, RHS, CP); } else { RHSValNoInfo = RHSValNoInfo0; } @@ -2318,7 +2305,7 @@ // DstReg is known to be a register in the LHS interval. If the src is // from the RHS interval, we can use its value #. - if (li_->getVNInfoSourceReg(VNI) != RHS.reg) + if (!CP.isCoalescable(VNI->getCopy())) continue; // Figure out the value # from the RHS. @@ -2337,7 +2324,7 @@ // DstReg is known to be a register in the RHS interval. If the src is // from the LHS interval, we can use its value #. - if (li_->getVNInfoSourceReg(VNI) != LHS.reg) + if (!CP.isCoalescable(VNI->getCopy())) continue; // Figure out the value # from the LHS. Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h?rev=105997&r1=105996&r2=105997&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h (original) +++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h Tue Jun 15 11:04:21 2010 @@ -111,14 +111,15 @@ /// physreg, this method always canonicalizes DestInt to be it. The output /// "SrcInt" will not have been modified, so we can use this information /// below to update aliases. - bool JoinIntervals(LiveInterval &LHS, LiveInterval &RHS, bool &Swapped); + bool JoinIntervals(LiveInterval &LHS, LiveInterval &RHS, bool &Swapped, + CoalescerPair &CP); /// SimpleJoin - Attempt to join the specified interval into this one. The /// caller of this method must guarantee that the RHS only contains a single /// value number and that the RHS is not defined by a copy from this /// interval. This returns false if the intervals are not joinable, or it /// joins them and returns true. - bool SimpleJoin(LiveInterval &LHS, LiveInterval &RHS); + bool SimpleJoin(LiveInterval &LHS, LiveInterval &RHS, CoalescerPair &CP); /// Return true if the two specified registers belong to different register /// classes. The registers may be either phys or virt regs. @@ -210,11 +211,10 @@ bool ValueLiveAt(LiveInterval::iterator LRItr, LiveInterval::iterator LREnd, SlotIndex defPoint) const; - /// RangeIsDefinedByCopyFromReg - Return true if the specified live range of - /// the specified live interval is defined by a copy from the specified - /// register. - bool RangeIsDefinedByCopyFromReg(LiveInterval &li, LiveRange *LR, - unsigned Reg); + /// RangeIsDefinedByCopy - Return true if the specified live range of the + /// specified live interval is defined by a coalescable copy. + bool RangeIsDefinedByCopy(LiveInterval &li, LiveRange *LR, + CoalescerPair &CP); /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and /// update the subregister number if it is not zero. If DstReg is a Added: llvm/trunk/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll?rev=105997&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll (added) +++ llvm/trunk/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll Tue Jun 15 11:04:21 2010 @@ -0,0 +1,41 @@ +; RUN: llc < %s -O3 -relocation-model=pic -mattr=+thumb2 -mcpu=cortex-a8 | FileCheck %s +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32" +target triple = "thumbv7-apple-darwin10" + +; This is a case where the coalescer was too eager. These two copies were +; considered equivalent and coalescable: +; +; 140 %reg1038:dsub_0 = VMOVD %reg1047:dsub_0, pred:14, pred:%reg0 +; 148 %reg1038:dsub_1 = VMOVD %reg1047:dsub_0, pred:14, pred:%reg0 +; +; Only one can be coalesced. + + at .str = private constant [7 x i8] c"%g %g\0A\00", align 4 ; <[7 x i8]*> [#uses=1] + +define arm_apcscc i32 @main(i32 %argc, i8** nocapture %Argv) nounwind { +entry: + %0 = icmp eq i32 %argc, 2123 ; [#uses=1] + %U.0 = select i1 %0, double 3.282190e+01, double 8.731834e+02 ; [#uses=2] + %1 = icmp eq i32 %argc, 5123 ; [#uses=1] + %V.0.ph = select i1 %1, double 7.779980e+01, double 0x409CCB9C779A6B51 ; [#uses=1] + %2 = insertelement <2 x double> undef, double %U.0, i32 0 ; <<2 x double>> [#uses=2] + %3 = insertelement <2 x double> %2, double %U.0, i32 1 ; <<2 x double>> [#uses=2] + %4 = insertelement <2 x double> %2, double %V.0.ph, i32 1 ; <<2 x double>> [#uses=2] +; Constant pool load followed by add. +; Then clobber the loaded register, not the sum. +; CHECK: vldr.64 [[LDR:d.]] +; CHECK: vadd.f64 [[ADD:d.]], [[LDR]], [[LDR]] +; CHECK: vmov.f64 [[LDR]] + %5 = fadd <2 x double> %3, %3 ; <<2 x double>> [#uses=2] + %6 = fadd <2 x double> %4, %4 ; <<2 x double>> [#uses=2] + %tmp7 = extractelement <2 x double> %5, i32 0 ; [#uses=1] + %tmp5 = extractelement <2 x double> %5, i32 1 ; [#uses=1] +; CHECK: printf + %7 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([7 x i8]* @.str, i32 0, i32 0), double %tmp7, double %tmp5) nounwind ; [#uses=0] + %tmp3 = extractelement <2 x double> %6, i32 0 ; [#uses=1] + %tmp1 = extractelement <2 x double> %6, i32 1 ; [#uses=1] + %8 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([7 x i8]* @.str, i32 0, i32 0), double %tmp3, double %tmp1) nounwind ; [#uses=0] + ret i32 0 +} + +declare arm_apcscc i32 @printf(i8* nocapture, ...) nounwind From stoklund at 2pi.dk Tue Jun 15 11:20:57 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 15 Jun 2010 16:20:57 -0000 Subject: [llvm-commits] [llvm] r105998 - in /llvm/trunk: lib/CodeGen/RegAllocFast.cpp test/CodeGen/X86/2010-06-15-FastAllocEarlyCLobber.ll Message-ID: <20100615162057.93F212A6C12C@llvm.org> Author: stoklund Date: Tue Jun 15 11:20:57 2010 New Revision: 105998 URL: http://llvm.org/viewvc/llvm-project?rev=105998&view=rev Log: Avoid processing early clobbers twice in RegAllocFast. Early clobbers defining a virtual register were first alocated to a physreg and then processed as a physreg EC, spilling the virtreg. This fixes PR7382. Added: llvm/trunk/test/CodeGen/X86/2010-06-15-FastAllocEarlyCLobber.ll Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=105998&r1=105997&r2=105998&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocFast.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp Tue Jun 15 11:20:57 2010 @@ -708,7 +708,8 @@ if (MO.isUse()) { usePhysReg(MO); } else if (MO.isEarlyClobber()) { - definePhysReg(MI, Reg, MO.isDead() ? regFree : regReserved); + definePhysReg(MI, Reg, (MO.isImplicit() || MO.isDead()) ? + regFree : regReserved); PhysECs.push_back(Reg); } } @@ -731,8 +732,11 @@ // Note: defineVirtReg may invalidate MO. LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, 0); unsigned PhysReg = LRI->second.PhysReg; - setPhysReg(MI, i, PhysReg); + if (setPhysReg(MI, i, PhysReg)) + VirtDead.push_back(Reg); PhysECs.push_back(PhysReg); + // Don't attempt coalescing when earlyclobbers are present. + CopyDst = 0; } } @@ -767,7 +771,8 @@ // Allocate defs and collect dead defs. for (unsigned i = 0; i != DefOpEnd; ++i) { MachineOperand &MO = MI->getOperand(i); - if (!MO.isReg() || !MO.isDef() || !MO.getReg()) continue; + if (!MO.isReg() || !MO.isDef() || !MO.getReg() || MO.isEarlyClobber()) + continue; unsigned Reg = MO.getReg(); if (TargetRegisterInfo::isPhysicalRegister(Reg)) { Added: llvm/trunk/test/CodeGen/X86/2010-06-15-FastAllocEarlyCLobber.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-06-15-FastAllocEarlyCLobber.ll?rev=105998&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2010-06-15-FastAllocEarlyCLobber.ll (added) +++ llvm/trunk/test/CodeGen/X86/2010-06-15-FastAllocEarlyCLobber.ll Tue Jun 15 11:20:57 2010 @@ -0,0 +1,29 @@ +; RUN: llc -regalloc=fast < %s | FileCheck %s +; PR7382 +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" + + at .str = private constant [23 x i8] c"This should be -1: %d\0A\00" ; <[23 x i8]*> [#uses=1] + +define i32 @main() { +entry: + %retval = alloca i32, align 4 ; [#uses=3] + %v = alloca i32, align 4 ; [#uses=3] + store i32 0, i32* %retval + %zero = load i32* %retval +; The earlyclobber register EC0 should not be spilled before the inline asm. +; Yes, check-not can refer to FileCheck variables defined in the future. +; CHECK-NOT: [[EC0]]{{.*}}(%rsp) +; CHECK: bsr {{[^,]*}}, [[EC0:%...]] + %0 = call i32 asm "bsr $1, $0\0A\09cmovz $2, $0", "=&r,ro,r,~{cc},~{dirflag},~{fpsr},~{flags}"(i32 %zero, i32 -1) nounwind, !srcloc !0 ; [#uses=1] + store i32 %0, i32* %v + %tmp = load i32* %v ; [#uses=1] + %call1 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([23 x i8]* @.str, i32 0, i32 0), i32 %tmp) ; [#uses=0] + store i32 0, i32* %retval + %1 = load i32* %retval ; [#uses=1] + ret i32 %0 +} + +declare i32 @printf(i8*, ...) + +!0 = metadata !{i32 191} From daniel at zuster.org Tue Jun 15 11:23:39 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Tue, 15 Jun 2010 16:23:39 -0000 Subject: [llvm-commits] [test-suite] r105999 - in /test-suite/trunk/SingleSource/UnitTests/Threads: tls.c tls.reference_output Message-ID: <20100615162339.C75BD2A6C12D@llvm.org> Author: ddunbar Date: Tue Jun 15 11:23:39 2010 New Revision: 105999 URL: http://llvm.org/viewvc/llvm-project?rev=105999&view=rev Log: Add SingleSource/UnitTests/Threads/tls reference output. Added: test-suite/trunk/SingleSource/UnitTests/Threads/tls.reference_output Modified: test-suite/trunk/SingleSource/UnitTests/Threads/tls.c Modified: test-suite/trunk/SingleSource/UnitTests/Threads/tls.c URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/Threads/tls.c?rev=105999&r1=105998&r2=105999&view=diff ============================================================================== --- test-suite/trunk/SingleSource/UnitTests/Threads/tls.c (original) +++ test-suite/trunk/SingleSource/UnitTests/Threads/tls.c Tue Jun 15 11:23:39 2010 @@ -13,9 +13,9 @@ intptr_t ret; pthread_create(&t, NULL, f, NULL); pthread_join(t, (void **) &ret); - printf("Thread 1: %" PRIdPTR "\n",ret); + printf("Thread 1: %d\n", (int) ret); pthread_create(&t, NULL, f, NULL); pthread_join(t, (void **) &ret); - printf("Thread 2: %" PRIdPTR "\n",ret); + printf("Thread 2: %d\n", (int) ret); return 0; } Added: test-suite/trunk/SingleSource/UnitTests/Threads/tls.reference_output URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/Threads/tls.reference_output?rev=105999&view=auto ============================================================================== --- test-suite/trunk/SingleSource/UnitTests/Threads/tls.reference_output (added) +++ test-suite/trunk/SingleSource/UnitTests/Threads/tls.reference_output Tue Jun 15 11:23:39 2010 @@ -0,0 +1,3 @@ +Thread 1: 2 +Thread 2: 2 +exit 0 From bob.wilson at apple.com Tue Jun 15 12:27:54 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 15 Jun 2010 17:27:54 -0000 Subject: [llvm-commits] [llvm] r106004 - /llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Message-ID: <20100615172754.880542A6C12C@llvm.org> Author: bwilson Date: Tue Jun 15 12:27:54 2010 New Revision: 106004 URL: http://llvm.org/viewvc/llvm-project?rev=106004&view=rev Log: Add some missing checks for the case where the extract_subregs are combined to an insert_subreg, i.e., where the destination register is larger than the source. We need to check that the subregs can be composed for that case in a symmetrical way to the case when the destination is smaller. Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=106004&r1=106003&r2=106004&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original) +++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Tue Jun 15 12:27:54 2010 @@ -1179,7 +1179,7 @@ // If there are no other uses than extract_subreg which feed into // the reg_sequence, then we might be able to coalesce them. bool CanCoalesce = true; - SmallVector SubIndices; + SmallVector SrcSubIndices, DstSubIndices; for (MachineRegisterInfo::use_nodbg_iterator UI = MRI->use_nodbg_begin(SrcReg), UE = MRI->use_nodbg_end(); UI != UE; ++UI) { @@ -1190,24 +1190,35 @@ CanCoalesce = false; break; } - SubIndices.push_back(UseMI->getOperand(2).getImm()); + SrcSubIndices.push_back(UseMI->getOperand(2).getImm()); + DstSubIndices.push_back(UseMI->getOperand(0).getSubReg()); } - if (!CanCoalesce || SubIndices.size() < 2) + if (!CanCoalesce || SrcSubIndices.size() < 2) continue; - std::sort(SubIndices.begin(), SubIndices.end()); + // Check that the source subregisters can be combined. + std::sort(SrcSubIndices.begin(), SrcSubIndices.end()); unsigned NewSrcSubIdx = 0; - if (!TRI->canCombineSubRegIndices(MRI->getRegClass(SrcReg), SubIndices, + if (!TRI->canCombineSubRegIndices(MRI->getRegClass(SrcReg), SrcSubIndices, NewSrcSubIdx)) continue; + // Check that the destination subregisters can also be combined. + std::sort(DstSubIndices.begin(), DstSubIndices.end()); + unsigned NewDstSubIdx = 0; + if (!TRI->canCombineSubRegIndices(MRI->getRegClass(DstReg), DstSubIndices, + NewDstSubIdx)) + continue; + + // If neither source nor destination can be combined to the full register, + // just give up. This could be improved if it ever matters. + if (NewSrcSubIdx != 0 && NewDstSubIdx != 0) + continue; + // Now that we know that all the uses are extract_subregs and that those // subregs can somehow be combined, scan all the extract_subregs again to // make sure the subregs are in the right order and can be composed. - // Also keep track of the destination subregisters so we can make sure - // that those can be combined. - SubIndices.clear(); MachineInstr *SomeMI = 0; CanCoalesce = true; for (MachineRegisterInfo::use_nodbg_iterator @@ -1218,29 +1229,19 @@ unsigned DstSubIdx = UseMI->getOperand(0).getSubReg(); unsigned SrcSubIdx = UseMI->getOperand(2).getImm(); assert(DstSubIdx != 0 && "missing subreg from RegSequence elimination"); - if (TRI->composeSubRegIndices(NewSrcSubIdx, DstSubIdx) != SrcSubIdx) { + if ((NewDstSubIdx == 0 && + TRI->composeSubRegIndices(NewSrcSubIdx, DstSubIdx) != SrcSubIdx) || + (NewSrcSubIdx == 0 && + TRI->composeSubRegIndices(NewDstSubIdx, SrcSubIdx) != DstSubIdx)) { CanCoalesce = false; break; } - SubIndices.push_back(DstSubIdx); // Keep track of one of the uses. SomeMI = UseMI; } if (!CanCoalesce) continue; - // Check that the destination subregisters can also be combined. - std::sort(SubIndices.begin(), SubIndices.end()); - unsigned NewDstSubIdx = 0; - if (!TRI->canCombineSubRegIndices(MRI->getRegClass(DstReg), SubIndices, - NewDstSubIdx)) - continue; - - // If neither source nor destination can be combined to the full register, - // just give up. This could be improved if it ever matters. - if (NewSrcSubIdx != 0 && NewDstSubIdx != 0) - continue; - // Insert a copy or an extract to replace the original extracts. MachineBasicBlock::iterator InsertLoc = SomeMI; if (NewSrcSubIdx) { From stuart at apple.com Tue Jun 15 12:38:04 2010 From: stuart at apple.com (Stuart Hastings) Date: Tue, 15 Jun 2010 17:38:04 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r106005 - /llvm-gcc-4.2/trunk/gcc/gimplify.c Message-ID: <20100615173804.70EDC2A6C12C@llvm.org> Author: stuart Date: Tue Jun 15 12:38:04 2010 New Revision: 106005 URL: http://llvm.org/viewvc/llvm-project?rev=106005&view=rev Log: Thinko. Thanks to Dale for pointing this out. Followup to Radar 8004649. Modified: llvm-gcc-4.2/trunk/gcc/gimplify.c Modified: llvm-gcc-4.2/trunk/gcc/gimplify.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/gimplify.c?rev=106005&r1=106004&r2=106005&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/gimplify.c (original) +++ llvm-gcc-4.2/trunk/gcc/gimplify.c Tue Jun 15 12:38:04 2010 @@ -5533,7 +5533,7 @@ pointer-based ARRAY_REFs as binary expressions. */ if (TREE_CODE (TREE_TYPE (TREE_OPERAND (*expr_p, 0))) != ARRAY_TYPE) { /* LLVM LOCAL 8004649 */ - gimplify_type_sizes (TREE_TYPE (*expr_p), expr_p); + gimplify_type_sizes (TREE_TYPE (*expr_p), pre_p); goto expr_2; } #endif From criswell at uiuc.edu Tue Jun 15 12:40:30 2010 From: criswell at uiuc.edu (John Criswell) Date: Tue, 15 Jun 2010 17:40:30 -0000 Subject: [llvm-commits] [www-pubs] r106006 - in /www-pubs/trunk: 2010-04-EUROSYS-Returnless.html 2010-05-Oakland-HyperSafe.html pubs.js Message-ID: <20100615174030.297BA2A6C12C@llvm.org> Author: criswell Date: Tue Jun 15 12:40:29 2010 New Revision: 106006 URL: http://llvm.org/viewvc/llvm-project?rev=106006&view=rev Log: Added Xuxian Jiang's Eurosys and Oakland papers. Both use LLVM. Added: www-pubs/trunk/2010-04-EUROSYS-Returnless.html www-pubs/trunk/2010-05-Oakland-HyperSafe.html Modified: www-pubs/trunk/pubs.js Added: www-pubs/trunk/2010-04-EUROSYS-Returnless.html URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/2010-04-EUROSYS-Returnless.html?rev=106006&view=auto ============================================================================== --- www-pubs/trunk/2010-04-EUROSYS-Returnless.html (added) +++ www-pubs/trunk/2010-04-EUROSYS-Returnless.html Tue Jun 15 12:40:29 2010 @@ -0,0 +1,72 @@ + + + + + + Defeating Return-Oriented Rootkits with "Return-Less" Kernels + + + +
+ Defeating Return-Oriented Rootkits with "Return-Less" Kernels +
+
+ Jinku Li, Zhi Wang, Xuxian Jiang, Michael Grace, and Sina Bahram +
+ +

Abstract:

+
+

+Targeting the operating system (OS) kernel, kernel rootkits pose a formidable +threat to computer systems and their users. Recent efforts have made +significant progress in blocking them from injecting malicious code into the OS +kernel for execution. Unfortunately, they cannot block the emerging so-called +return-oriented rootkits (RORs). Without the need of injecting their own +malicious code, these rootkits can discover and chain together "return-oriented +gadgets" (that consist of only legitimate kernel code) for rootkit computation. +

+ +

+In this paper, we propose a compiler-based approach to defeat these +return-oriented rootkits. Our approach recognizes the hallmark of +return-oriented rootkits, i.e., the ret instruction, and accordingly aims to +completely remove them in a running OS kernel. Specifically, one key technique +named return indirection is to replace the return address in a stack frame into +a return index and disallow a ROR from using their own return addresses to +locate and assemble return-oriented gadgets. Further, to prevent legitimate +instructions that happen to contain return opcodes from being misused,we also +propose two other techniques, register allocation and peephole optimization, to +avoid introducing them in the first place. We have developed a LLVM-based +prototype and used it to generate a return-less FreeBSD kernel. Our evaluation +results indicate that the proposed approach is generic, effective, and can be +implemented on commodity hardware with a low performance overhead. +

+
+ +

Published:

+
+ "Defeating Return-Oriented Rootkits with "Return-Less" Kernels" +
+ Jinku Li, Zhi Wang, Xuxian Jiang, Michael Grace, and Sina Bahram +
+ +Proc. of the 5th ACM European Conference on Computer Systems +, Paris, France, April 2010. +
+

Download:

+

Paper:

+ + + +
+ Valid CSS! + Valid HTML 4.01! + + + Added: www-pubs/trunk/2010-05-Oakland-HyperSafe.html URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/2010-05-Oakland-HyperSafe.html?rev=106006&view=auto ============================================================================== --- www-pubs/trunk/2010-05-Oakland-HyperSafe.html (added) +++ www-pubs/trunk/2010-05-Oakland-HyperSafe.html Tue Jun 15 12:40:29 2010 @@ -0,0 +1,77 @@ + + + + + + HyperSafe: A Lightweight Approach to Provide Lifetime Hypervisor Control-Flow Integrity + + + +
+ HyperSafe: A Lightweight Approach to Provide Lifetime Hypervisor Control-Flow Integrity +
+
+ Zhi Wang and Xuxian Jiang +
+ +

Abstract:

+
+

+Virtualization is being widely adopted in today???s +computing systems. Its unique security advantages in isolating +and introspecting commodity OSes as virtual machines (VMs) +have enabled a wide spectrum of applications. However, a com- +mon, fundamental assumption is the presence of a trustworthy +hypervisor. Unfortunately, the large code base of commodity +hypervisors and recent successful hypervisor attacks (e.g., VM +escape) seriously question the validity of this assumption. +In this paper, we present HyperSafe, a lightweight approach +that endows existing Type-I bare-metal hypervisors with a +unique self-protection capability to provide lifetime control- +???ow integrity. Speci???cally, we propose two key techniques. The +???rst one ??? non-bypassable memory lockdown ??? reliably protects +the hypervisor???s code and static data from being compromised +even in the presence of exploitable memory corruption bugs +(e.g., buffer over???ows), therefore successfully providing hyper- +visor code integrity. The second one ??? restricted pointer indexing +??? introduces one layer of indirection to convert the control data +into pointer indexes. These pointer indexes are restricted such +that the corresponding call/return targets strictly follow the +hypervisor control ???ow graph, hence expanding protection to +control-???ow integrity. We have built a prototype and used it to +protect two open-source Type-I hypervisors: BitVisor and Xen. +The experimental results with synthetic hypervisor exploits +and benchmarking programs show HyperSafe can reliably +enable the hypervisor self-protection and provide the integrity +guarantee with a small performance overhead. +

+
+ +

Published:

+
+ "HyperSafe: A Lightweight Approach to Provide Lifetime Hypervisor Control-Flow Integrity" +
+ Zhi Wang and Xuxian Jiang +
+ +Proceedings of the Thirty First IEEE Symposium on Security & Privacy (Oakland +2010), + Oakland, CA, May 2010. +
+

Download:

+

Paper:

+ + + +
+ Valid CSS! + Valid HTML 4.01! + + + Modified: www-pubs/trunk/pubs.js URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/pubs.js?rev=106006&r1=106005&r2=106006&view=diff ============================================================================== --- www-pubs/trunk/pubs.js (original) +++ www-pubs/trunk/pubs.js Tue Jun 15 12:40:29 2010 @@ -1,6 +1,12 @@ // The array should be sorted reverse-chronologically, and will be displayed on // the page in the order listed. var PUBS = [ + {url: "2010-05-Oakland-HyperSafe.html", + title: "HyperSafe: A Lightweight Approach to Provide Lifetime Hypervisor Control-Flow Integrity", + published: "IEEE Symposium on Security & Privacy 2010", + author: " Zhi Wang and Xuxian Jiang", + month: 5, + year: 2010}, {url: "2010-05-01-ClangBSD.html", title: "ClangBSD", published: "BSDcan 2010", @@ -21,6 +27,13 @@ location: "Paris, France", month: 4, year: 2010}, + {url: "2010-04-EUROSYS-Returnless.html", + title: "Defeating Return-Oriented Rootkits with "Return-Less" Kernels", + published: "Proc. of the 5th ACM European Conference on Computer Systems (EuroSys'10)", + author: "Jinku Li, Zhi Wang, Xuxian Jiang, Michael Grace, and Sina Bahram", + location: "Paris, France", + month: 4, + year: 2010}, {url: "2010-04-EUROSYS-RevNIC.html", title: "Reverse Engineering of Binary Device Drivers with RevNIC", published: "Proc. of the 5th ACM European Conference on Computer Systems (EuroSys'10)", From criswell at uiuc.edu Tue Jun 15 12:42:00 2010 From: criswell at uiuc.edu (John Criswell) Date: Tue, 15 Jun 2010 17:42:00 -0000 Subject: [llvm-commits] [www-pubs] r106007 - /www-pubs/trunk/pubs.js Message-ID: <20100615174200.BD7B02A6C12C@llvm.org> Author: criswell Date: Tue Jun 15 12:42:00 2010 New Revision: 106007 URL: http://llvm.org/viewvc/llvm-project?rev=106007&view=rev Log: Fix quoting problem. Modified: www-pubs/trunk/pubs.js Modified: www-pubs/trunk/pubs.js URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/pubs.js?rev=106007&r1=106006&r2=106007&view=diff ============================================================================== --- www-pubs/trunk/pubs.js (original) +++ www-pubs/trunk/pubs.js Tue Jun 15 12:42:00 2010 @@ -28,7 +28,7 @@ month: 4, year: 2010}, {url: "2010-04-EUROSYS-Returnless.html", - title: "Defeating Return-Oriented Rootkits with "Return-Less" Kernels", + title: "Defeating Return-Oriented Rootkits with \"Return-Less\" Kernels", published: "Proc. of the 5th ACM European Conference on Computer Systems (EuroSys'10)", author: "Jinku Li, Zhi Wang, Xuxian Jiang, Michael Grace, and Sina Bahram", location: "Paris, France", From daniel at zuster.org Tue Jun 15 12:47:24 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Tue, 15 Jun 2010 17:47:24 -0000 Subject: [llvm-commits] [llvm] r106009 - /llvm/trunk/examples/ExceptionDemo/ExceptionDemo.cpp Message-ID: <20100615174724.A93152A6C12C@llvm.org> Author: ddunbar Date: Tue Jun 15 12:47:24 2010 New Revision: 106009 URL: http://llvm.org/viewvc/llvm-project?rev=106009&view=rev Log: Remove stray semi-colon. Modified: llvm/trunk/examples/ExceptionDemo/ExceptionDemo.cpp Modified: llvm/trunk/examples/ExceptionDemo/ExceptionDemo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/ExceptionDemo/ExceptionDemo.cpp?rev=106009&r1=106008&r2=106009&view=diff ============================================================================== --- llvm/trunk/examples/ExceptionDemo/ExceptionDemo.cpp (original) +++ llvm/trunk/examples/ExceptionDemo/ExceptionDemo.cpp Tue Jun 15 12:47:24 2010 @@ -1574,7 +1574,7 @@ )); } - ~OurCppRunException (void) throw () {}; + ~OurCppRunException (void) throw () {} }; From criswell at uiuc.edu Tue Jun 15 13:09:28 2010 From: criswell at uiuc.edu (John Criswell) Date: Tue, 15 Jun 2010 18:09:28 -0000 Subject: [llvm-commits] [www-pubs] r106013 - in /www-pubs/trunk: 2010-06-ISMM-CETS.html pubs.js Message-ID: <20100615180928.27FA12A6C12C@llvm.org> Author: criswell Date: Tue Jun 15 13:09:27 2010 New Revision: 106013 URL: http://llvm.org/viewvc/llvm-project?rev=106013&view=rev Log: Added CETS paper from ISMM 2010. Added: www-pubs/trunk/2010-06-ISMM-CETS.html Modified: www-pubs/trunk/pubs.js Added: www-pubs/trunk/2010-06-ISMM-CETS.html URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/2010-06-ISMM-CETS.html?rev=106013&view=auto ============================================================================== --- www-pubs/trunk/2010-06-ISMM-CETS.html (added) +++ www-pubs/trunk/2010-06-ISMM-CETS.html Tue Jun 15 13:09:27 2010 @@ -0,0 +1,65 @@ + + + + + + CETS: Compiler Enforced Temporal Safety for C + + + +
+ CETS: Compiler Enforced Temporal Safety for C +
+
+ Santosh Nagarakatte, Jianzhou Zhao, Milo M K Martin and Steve Zdancewic +
+ +

Abstract:

+
+

+Temporal memory safety errors, such as dangling pointer dereferences and double +frees, are a prevalent source of software bugs in unmanaged languages such as +C. Existing schemes that attempt to retrofit temporal safety for such languages +have high runtime overheads and/or are incomplete, thereby limiting their +effectiveness as debugging aids. This paper presents CETS, a compile-time +transformation for detecting all violations of temporal safety in C programs. +Inspired by existing approaches, CETS maintains a unique identifier with each +object, associates this metadata with the pointers in a disjoint metadata space +to retain memory layout compatibility, and checks that the object is still +allocated on pointer dereferences. A formal proof shows that this is sufficient +to provide temporal safety even in the presence of arbitrary casts if the +program contains no spatial safety violations. Our CETS prototype employs both +temporal check removal optimizations and traditional compiler optimizations to +achieve a runtime overhead of just 48% on average. When combined with a +spatial-checking system, the average overall overhead is 116% for complete +memory safety. +

+
+ +

Published:

+
+ "CETS: Compiler Enforced Temporal Safety for C" +
+ Santosh Nagarakatte, Jianzhou Zhao, Milo M K Martin and Steve Zdancewic. +
+ +Proceedings of the International Conference on Memory Management, + Toronto, Canada, June 2010. +
+

Download:

+

Paper:

+ + + +
+ Valid CSS! + Valid HTML 4.01! + + + Modified: www-pubs/trunk/pubs.js URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/pubs.js?rev=106013&r1=106012&r2=106013&view=diff ============================================================================== --- www-pubs/trunk/pubs.js (original) +++ www-pubs/trunk/pubs.js Tue Jun 15 13:09:27 2010 @@ -1,10 +1,16 @@ // The array should be sorted reverse-chronologically, and will be displayed on // the page in the order listed. var PUBS = [ + {url: "2010-06-ISMM-CETS.html", + title: "CETS: Compiler Enforced Temporal Safety for C", + published: "International Conference on Memory Management 2010", + author: "Santosh Nagarakatte, Jianzhou Zhao, Milo M K Martin and Steve Zdancewic", + month: 6, + year: 2010}, {url: "2010-05-Oakland-HyperSafe.html", title: "HyperSafe: A Lightweight Approach to Provide Lifetime Hypervisor Control-Flow Integrity", published: "IEEE Symposium on Security & Privacy 2010", - author: " Zhi Wang and Xuxian Jiang", + author: "Zhi Wang and Xuxian Jiang", month: 5, year: 2010}, {url: "2010-05-01-ClangBSD.html", From criswell at uiuc.edu Tue Jun 15 13:12:59 2010 From: criswell at uiuc.edu (John Criswell) Date: Tue, 15 Jun 2010 18:12:59 -0000 Subject: [llvm-commits] [www-pubs] r106014 - /www-pubs/trunk/index.html Message-ID: <20100615181259.9A6B02A6C131@llvm.org> Author: criswell Date: Tue Jun 15 13:12:59 2010 New Revision: 106014 URL: http://llvm.org/viewvc/llvm-project?rev=106014&view=rev Log: Fixed some punctuation errors; improved wording (I think). Modified: www-pubs/trunk/index.html Modified: www-pubs/trunk/index.html URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/index.html?rev=106014&r1=106013&r2=106014&view=diff ============================================================================== --- www-pubs/trunk/index.html (original) +++ www-pubs/trunk/index.html Tue Jun 15 13:12:59 2010 @@ -2,7 +2,7 @@
LLVM Related Publications

Here are some of the publications that use or build on LLVM. This list - generally lags behind publication, if you have a paper for this + generally lags behind publication; if you have a paper for this list, please email Chris or commit it directly to the llvm-pubs SVN module if you have llvm.org commit access.

From espindola at google.com Tue Jun 15 13:17:16 2010 From: espindola at google.com (Rafael Espindola) Date: Tue, 15 Jun 2010 14:17:16 -0400 Subject: [llvm-commits] [patch] Remove arm_aapcscc from some tests Message-ID: Discussing PR7357 over IRC, Nick suggested that the best fix would be to change simplify-libcalls to not modify calls with non-default calling conventions. This looks reasonable, but to do that we have to change the default ARM calling convention to the default (.i.e "") :-) The attached patch is a first step in that direction. It just updates the tests to use "" instead of arm_aapcscc. I will do the same with arm_apcscc and then change llvm-gcc and clang to use "" for the default. Cheers, -- Rafael ?vila de Esp?ndola -------------- next part -------------- A non-text attachment was scrubbed... Name: aapcs.patch Type: text/x-patch Size: 9467 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100615/fefdbaf2/attachment.bin From bob.wilson at apple.com Tue Jun 15 13:19:27 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 15 Jun 2010 18:19:27 -0000 Subject: [llvm-commits] [llvm] r106015 - /llvm/trunk/lib/CodeGen/IfConversion.cpp Message-ID: <20100615181927.972C12A6C12F@llvm.org> Author: bwilson Date: Tue Jun 15 13:19:27 2010 New Revision: 106015 URL: http://llvm.org/viewvc/llvm-project?rev=106015&view=rev Log: Fix a comment typo. Modified: llvm/trunk/lib/CodeGen/IfConversion.cpp Modified: llvm/trunk/lib/CodeGen/IfConversion.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/IfConversion.cpp?rev=106015&r1=106014&r2=106015&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/IfConversion.cpp (original) +++ llvm/trunk/lib/CodeGen/IfConversion.cpp Tue Jun 15 13:19:27 2010 @@ -115,7 +115,7 @@ BB(0), TrueBB(0), FalseBB(0) {} }; - /// IfcvtToken - Record information about pending if-conversions to attemp: + /// IfcvtToken - Record information about pending if-conversions to attempt: /// BBI - Corresponding BBInfo. /// Kind - Type of block. See IfcvtKind. /// NeedSubsumption - True if the to-be-predicated BB has already been From bob.wilson at apple.com Tue Jun 15 13:34:19 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 15 Jun 2010 18:34:19 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r106018 - /llvm-gcc-4.2/trunk/GNUmakefile Message-ID: <20100615183419.51A272A6C12E@llvm.org> Author: bwilson Date: Tue Jun 15 13:34:19 2010 New Revision: 106018 URL: http://llvm.org/viewvc/llvm-project?rev=106018&view=rev Log: Strip out gcc/testsuite from llvm-gcc submissions. There's no reason to submit the testsuite files and this will save disk space and speed up the submission process. Modified: llvm-gcc-4.2/trunk/GNUmakefile Modified: llvm-gcc-4.2/trunk/GNUmakefile URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/GNUmakefile?rev=106018&r1=106017&r2=106018&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/GNUmakefile (original) +++ llvm-gcc-4.2/trunk/GNUmakefile Tue Jun 15 13:34:19 2010 @@ -147,6 +147,7 @@ -type f -a -name .DS_Store -o \ -name \*~ -o -name .\#\* \) \ -exec rm -rf {} \; + rm -rf "$(SRCROOT)/gcc/testsuite" rm -rf "$(SRCROOT)/llvmCore/test" ####################################################################### From bob.wilson at apple.com Tue Jun 15 13:44:00 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 15 Jun 2010 11:44:00 -0700 Subject: [llvm-commits] [patch] Remove arm_aapcscc from some tests In-Reply-To: References: Message-ID: <250924C5-EF3C-4CB0-BD7C-7F42F9B1D27D@apple.com> On Jun 15, 2010, at 11:17 AM, Rafael Espindola wrote: > Discussing PR7357 over IRC, Nick suggested that the best fix would be > to change simplify-libcalls to not modify calls with non-default > calling conventions. This looks reasonable, but to do that we have to > change the default ARM calling convention to the default (.i.e "") :-) > > The attached patch is a first step in that direction. It just updates > the tests to use "" instead of arm_aapcscc. I will do the same with > arm_apcscc and then change llvm-gcc and clang to use "" for the > default. This isn't really necessary, is it? It's still OK to explicitly specify the calling convention, right? Are you just trying to get better test coverage for using the default ABI? What's the default ABI for "-mtriple=armv6-elf" or "-march=arm"? It isn't obvious to me whether those should use APCS or AAPCS, so maybe it is better to explicitly specify the CC in those cases. From espindola at google.com Tue Jun 15 13:48:19 2010 From: espindola at google.com (Rafael Espindola) Date: Tue, 15 Jun 2010 14:48:19 -0400 Subject: [llvm-commits] [patch] Remove arm_aapcscc from some tests In-Reply-To: <250924C5-EF3C-4CB0-BD7C-7F42F9B1D27D@apple.com> References: <250924C5-EF3C-4CB0-BD7C-7F42F9B1D27D@apple.com> Message-ID: > This isn't really necessary, is it? ?It's still OK to explicitly specify the calling convention, right? ?Are you just trying to get better test coverage for using the default ABI? Correct. Since I intend to switch the FE, it is better if most tests have the same structure as the output of the FE. > What's the default ABI for "-mtriple=armv6-elf" or "-march=arm"? ?It isn't obvious to me whether those should use APCS or AAPCS, so maybe it is better to explicitly specify the CC in those cases. None of those tests was checking anything specific about the ABI. For tests that do, it is probably better to pass a more complete mtriple, no? Cheers, -- Rafael ?vila de Esp?ndola From stoklund at 2pi.dk Tue Jun 15 13:49:14 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 15 Jun 2010 18:49:14 -0000 Subject: [llvm-commits] [llvm] r106021 - /llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Message-ID: <20100615184915.060552A6C12C@llvm.org> Author: stoklund Date: Tue Jun 15 13:49:14 2010 New Revision: 106021 URL: http://llvm.org/viewvc/llvm-project?rev=106021&view=rev Log: Fix an exotic bug that only showed up in an internal test case. SimpleRegisterCoalescing::JoinIntervals() uses CoalescerPair to determine if a copy is coalescable, and in very rare cases it can return true where LHS is not live - the coalescable copy can come from an alias of the physreg in LHS. Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=106021&r1=106020&r2=106021&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original) +++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Tue Jun 15 13:49:14 2010 @@ -2310,7 +2310,8 @@ // Figure out the value # from the RHS. LiveRange *lr = RHS.getLiveRangeContaining(VNI->def.getPrevSlot()); - assert(lr && "Cannot find live range"); + // The copy could be to an aliased physreg. + if (!lr) continue; LHSValsDefinedFromRHS[VNI] = lr->valno; } @@ -2329,7 +2330,8 @@ // Figure out the value # from the LHS. LiveRange *lr = LHS.getLiveRangeContaining(VNI->def.getPrevSlot()); - assert(lr && "Cannot find live range"); + // The copy could be to an aliased physreg. + if (!lr) continue; RHSValsDefinedFromLHS[VNI] = lr->valno; } From benny.kra at googlemail.com Tue Jun 15 13:50:59 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Tue, 15 Jun 2010 20:50:59 +0200 Subject: [llvm-commits] [PATCH] simplify-libcalls: fold strstr(a, b) == a -> strncmp(a, b, strlen(b)) == 0 Message-ID: <59C54A68-7761-44D2-B994-BA352C2B79C5@gmail.com> This seems to be a common idiom to check the prefix of a string (lldb uses it) and it triggers O(n*m) behavior in most libc implementations. strncmp brings it down to O(m). I'm not sure if simplify-libcalls is the right place for this. The code basically works around the pass's infrastructure (skipping statistics etc.) -------------- next part -------------- A non-text attachment was scrubbed... Name: strstr.patch Type: application/octet-stream Size: 5132 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100615/a0bd392c/attachment.obj From grosbach at apple.com Tue Jun 15 13:53:34 2010 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 15 Jun 2010 18:53:34 -0000 Subject: [llvm-commits] [llvm] r106024 - /llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Message-ID: <20100615185334.9B7002A6C12C@llvm.org> Author: grosbach Date: Tue Jun 15 13:53:34 2010 New Revision: 106024 URL: http://llvm.org/viewvc/llvm-project?rev=106024&view=rev Log: fix naming Modified: llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Modified: llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp?rev=106024&r1=106023&r2=106024&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp (original) +++ llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Tue Jun 15 13:53:34 2010 @@ -71,7 +71,7 @@ void insertCallSiteStore(Instruction *I, int Number, Value *CallSite); void markInvokeCallSite(InvokeInst *II, int InvokeNo, Value *CallSite, SwitchInst *CatchSwitch); - void splitLiveRangesLiveAcrossInvokes(SmallVector &Invokes); + void splitLiveRangesAcrossInvokes(SmallVector &Invokes); bool insertSjLjEHSupport(Function &F); }; } // end anonymous namespace @@ -182,7 +182,7 @@ /// FIXME: Move this function to a common utility file (Local.cpp?) so /// both SjLj and LowerInvoke can use it. void SjLjEHPass:: -splitLiveRangesLiveAcrossInvokes(SmallVector &Invokes) { +splitLiveRangesAcrossInvokes(SmallVector &Invokes) { // First step, split all critical edges from invoke instructions. for (unsigned i = 0, e = Invokes.size(); i != e; ++i) { InvokeInst *II = Invokes[i]; @@ -364,7 +364,7 @@ // we spill into a stack location, guaranteeing that there is nothing live // across the unwind edge. This process also splits all critical edges // coming out of invoke's. - splitLiveRangesLiveAcrossInvokes(Invokes); + splitLiveRangesAcrossInvokes(Invokes); BasicBlock *EntryBB = F.begin(); // Create an alloca for the incoming jump buffer ptr and the new jump buffer From bob.wilson at apple.com Tue Jun 15 13:57:15 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 15 Jun 2010 18:57:15 -0000 Subject: [llvm-commits] [llvm] r106027 - /llvm/trunk/lib/CodeGen/IfConversion.cpp Message-ID: <20100615185715.B011C2A6C12C@llvm.org> Author: bwilson Date: Tue Jun 15 13:57:15 2010 New Revision: 106027 URL: http://llvm.org/viewvc/llvm-project?rev=106027&view=rev Log: IfConversion's AnalyzeBlocks method always returns false; clean it up. Modified: llvm/trunk/lib/CodeGen/IfConversion.cpp Modified: llvm/trunk/lib/CodeGen/IfConversion.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/IfConversion.cpp?rev=106027&r1=106026&r2=106027&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/IfConversion.cpp (original) +++ llvm/trunk/lib/CodeGen/IfConversion.cpp Tue Jun 15 13:57:15 2010 @@ -167,8 +167,7 @@ std::vector &Tokens); bool FeasibilityAnalysis(BBInfo &BBI, SmallVectorImpl &Cond, bool isTriangle = false, bool RevBranch = false); - bool AnalyzeBlocks(MachineFunction &MF, - std::vector &Tokens); + void AnalyzeBlocks(MachineFunction &MF, std::vector &Tokens); void InvalidatePreds(MachineBasicBlock *BB); void RemoveExtraEdges(BBInfo &BBI); bool IfConvertSimple(BBInfo &BBI, IfcvtKind Kind); @@ -253,7 +252,8 @@ while (IfCvtLimit == -1 || (int)NumIfCvts < IfCvtLimit) { // Do an initial analysis for each basic block and find all the potential // candidates to perform if-conversion. - bool Change = AnalyzeBlocks(MF, Tokens); + bool Change = false; + AnalyzeBlocks(MF, Tokens); while (!Tokens.empty()) { IfcvtToken *Token = Tokens.back(); Tokens.pop_back(); @@ -802,11 +802,9 @@ } /// AnalyzeBlocks - Analyze all blocks and find entries for all if-conversion -/// candidates. It returns true if any CFG restructuring is done to expose more -/// if-conversion opportunities. -bool IfConverter::AnalyzeBlocks(MachineFunction &MF, +/// candidates. +void IfConverter::AnalyzeBlocks(MachineFunction &MF, std::vector &Tokens) { - bool Change = false; std::set Visited; for (unsigned i = 0, e = Roots.size(); i != e; ++i) { for (idf_ext_iterator I=idf_ext_begin(Roots[i],Visited), @@ -818,8 +816,6 @@ // Sort to favor more complex ifcvt scheme. std::stable_sort(Tokens.begin(), Tokens.end(), IfcvtTokenCmp); - - return Change; } /// canFallThroughTo - Returns true either if ToBB is the next block after BB or From sabre at nondot.org Tue Jun 15 13:59:43 2010 From: sabre at nondot.org (Chris Lattner) Date: Tue, 15 Jun 2010 18:59:43 -0000 Subject: [llvm-commits] [llvm] r106028 - /llvm/trunk/include/llvm/ADT/SmallVector.h Message-ID: <20100615185943.A21032A6C12C@llvm.org> Author: lattner Date: Tue Jun 15 13:59:43 2010 New Revision: 106028 URL: http://llvm.org/viewvc/llvm-project?rev=106028&view=rev Log: disable SmallVectorImpl's copy constructor. This prevents a class of base class slicing bugs reported on irc Modified: llvm/trunk/include/llvm/ADT/SmallVector.h Modified: llvm/trunk/include/llvm/ADT/SmallVector.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/SmallVector.h?rev=106028&r1=106027&r2=106028&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/SmallVector.h (original) +++ llvm/trunk/include/llvm/ADT/SmallVector.h Tue Jun 15 13:59:43 2010 @@ -269,6 +269,8 @@ template class SmallVectorImpl : public SmallVectorTemplateBase::value> { typedef SmallVectorTemplateBase::value > SuperClass; + + SmallVectorImpl(const SmallVectorImpl&); // DISABLED. public: typedef typename SuperClass::iterator iterator; typedef typename SuperClass::size_type size_type; From bob.wilson at apple.com Tue Jun 15 14:01:36 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 15 Jun 2010 12:01:36 -0700 Subject: [llvm-commits] [patch] Remove arm_aapcscc from some tests In-Reply-To: References: <250924C5-EF3C-4CB0-BD7C-7F42F9B1D27D@apple.com> Message-ID: <9601F397-5FAC-469F-A704-EF38972AE22E@apple.com> On Jun 15, 2010, at 11:48 AM, Rafael Espindola wrote: >> This isn't really necessary, is it? It's still OK to explicitly specify the calling convention, right? Are you just trying to get better test coverage for using the default ABI? > > Correct. Since I intend to switch the FE, it is better if most tests > have the same structure as the output of the FE. > >> What's the default ABI for "-mtriple=armv6-elf" or "-march=arm"? It isn't obvious to me whether those should use APCS or AAPCS, so maybe it is better to explicitly specify the CC in those cases. > > None of those tests was checking anything specific about the ABI. For > tests that do, it is probably better to pass a more complete mtriple, > no? I guess so. I don't have any objections to your change as long as it doesn't break the tests. From clattner at apple.com Tue Jun 15 14:03:46 2010 From: clattner at apple.com (Chris Lattner) Date: Tue, 15 Jun 2010 12:03:46 -0700 Subject: [llvm-commits] [PATCH] simplify-libcalls: fold strstr(a, b) == a -> strncmp(a, b, strlen(b)) == 0 In-Reply-To: <59C54A68-7761-44D2-B994-BA352C2B79C5@gmail.com> References: <59C54A68-7761-44D2-B994-BA352C2B79C5@gmail.com> Message-ID: <010C4722-CDD7-4C57-A170-FD9EAC525277@apple.com> On Jun 15, 2010, at 11:50 AM, Benjamin Kramer wrote: > This seems to be a common idiom to check the prefix of a string (lldb uses it) and it triggers O(n*m) behavior in most libc implementations. strncmp brings it down to O(m). > > I'm not sure if simplify-libcalls is the right place for this. The code basically works around the pass's infrastructure (skipping statistics etc.) This looks great to me. As a micro-micro-optimization, you could check to see if 'a' has a known length. If so, you could use strlen(a) instead since using strlen(a) or strlen(b) both work. -Chris From rafael.espindola at gmail.com Tue Jun 15 14:04:30 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Tue, 15 Jun 2010 19:04:30 -0000 Subject: [llvm-commits] [llvm] r106029 - in /llvm/trunk/test: CodeGen/ARM/ CodeGen/Thumb2/ Transforms/ScalarRepl/ Message-ID: <20100615190430.2F4C32A6C12C@llvm.org> Author: rafael Date: Tue Jun 15 14:04:29 2010 New Revision: 106029 URL: http://llvm.org/viewvc/llvm-project?rev=106029&view=rev Log: Remove the arm_aapcscc marker from the tests. It is the default for the linux targets. Modified: llvm/trunk/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll llvm/trunk/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll llvm/trunk/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll llvm/trunk/test/CodeGen/ARM/2009-08-15-RegScavengerAssert.ll llvm/trunk/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll llvm/trunk/test/CodeGen/ARM/2009-10-27-double-align.ll llvm/trunk/test/CodeGen/ARM/arm-frameaddr.ll llvm/trunk/test/CodeGen/ARM/armv4.ll llvm/trunk/test/CodeGen/Thumb2/2009-08-04-CoalescerAssert.ll llvm/trunk/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll llvm/trunk/test/CodeGen/Thumb2/2009-08-08-ScavengerAssert.ll llvm/trunk/test/Transforms/ScalarRepl/memcpy-align.ll Modified: llvm/trunk/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll?rev=106029&r1=106028&r2=106029&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll Tue Jun 15 14:04:29 2010 @@ -4,7 +4,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64" target triple = "armv6-elf" -define arm_aapcscc i32 @file_read_actor(i32* nocapture %desc, i32* %page, i32 %offset, i32 %size) nounwind optsize { +define i32 @file_read_actor(i32* nocapture %desc, i32* %page, i32 %offset, i32 %size) nounwind optsize { entry: br i1 undef, label %fault_in_pages_writeable.exit, label %bb5.i @@ -26,8 +26,8 @@ unreachable bb3: ; preds = %fault_in_pages_writeable.exit - %1 = tail call arm_aapcscc i32 @__copy_to_user(i8* undef, i8* undef, i32 undef) nounwind ; [#uses=0] + %1 = tail call i32 @__copy_to_user(i8* undef, i8* undef, i32 undef) nounwind ; [#uses=0] unreachable } -declare arm_aapcscc i32 @__copy_to_user(i8*, i8*, i32) +declare i32 @__copy_to_user(i8*, i8*, i32) Modified: llvm/trunk/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll?rev=106029&r1=106028&r2=106029&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll Tue Jun 15 14:04:29 2010 @@ -1,7 +1,7 @@ ; RUN: llc < %s -mtriple=armv6-elf ; PR4528 -define arm_aapcscc i32 @file_read_actor(i32 %desc, i32 %page, i32 %offset, i32 %size) nounwind optsize { +define i32 @file_read_actor(i32 %desc, i32 %page, i32 %offset, i32 %size) nounwind optsize { entry: br i1 undef, label %fault_in_pages_writeable.exit, label %bb5.i @@ -18,8 +18,8 @@ unreachable bb3: ; preds = %fault_in_pages_writeable.exit - %2 = tail call arm_aapcscc i32 @__copy_to_user(i8* undef, i8* undef, i32 undef) nounwind ; [#uses=0] + %2 = tail call i32 @__copy_to_user(i8* undef, i8* undef, i32 undef) nounwind ; [#uses=0] unreachable } -declare arm_aapcscc i32 @__copy_to_user(i8*, i8*, i32) +declare i32 @__copy_to_user(i8*, i8*, i32) Modified: llvm/trunk/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll?rev=106029&r1=106028&r2=106029&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll Tue Jun 15 14:04:29 2010 @@ -6,7 +6,7 @@ %struct.device_dma_parameters = type { i32, i32 } %struct.iovec = type { i8*, i32 } -define arm_aapcscc i32 @generic_segment_checks(%struct.iovec* nocapture %iov, i32* nocapture %nr_segs, i32* nocapture %count, i32 %access_flags) nounwind optsize { +define i32 @generic_segment_checks(%struct.iovec* nocapture %iov, i32* nocapture %nr_segs, i32* nocapture %count, i32 %access_flags) nounwind optsize { entry: br label %bb8 Modified: llvm/trunk/test/CodeGen/ARM/2009-08-15-RegScavengerAssert.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-08-15-RegScavengerAssert.ll?rev=106029&r1=106028&r2=106029&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-08-15-RegScavengerAssert.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2009-08-15-RegScavengerAssert.ll Tue Jun 15 14:04:29 2010 @@ -1,10 +1,10 @@ ; RUN: llc < %s -march=arm ; PR4716 -define arm_aapcscc void @_start() nounwind naked { +define void @_start() nounwind naked { entry: - tail call arm_aapcscc void @exit(i32 undef) noreturn nounwind + tail call void @exit(i32 undef) noreturn nounwind unreachable } -declare arm_aapcscc void @exit(i32) noreturn nounwind +declare void @exit(i32) noreturn nounwind Modified: llvm/trunk/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll?rev=106029&r1=106028&r2=106029&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll Tue Jun 15 14:04:29 2010 @@ -3,7 +3,7 @@ %0 = type { double, double } -define arm_aapcscc void @foo(%0* noalias nocapture sret %agg.result, double %x.0, double %y.0) nounwind { +define void @foo(%0* noalias nocapture sret %agg.result, double %x.0, double %y.0) nounwind { ; CHECK: foo: ; CHECK: bl __adddf3 ; CHECK-NOT: strd Modified: llvm/trunk/test/CodeGen/ARM/2009-10-27-double-align.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-10-27-double-align.ll?rev=106029&r1=106028&r2=106029&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-10-27-double-align.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2009-10-27-double-align.ll Tue Jun 15 14:04:29 2010 @@ -2,13 +2,13 @@ @.str = private constant [1 x i8] zeroinitializer, align 1 -define arm_aapcscc void @g() { +define void @g() { entry: ;CHECK: [sp, #8] ;CHECK: [sp, #12] ;CHECK: [sp] - tail call arm_aapcscc void (i8*, ...)* @f(i8* getelementptr ([1 x i8]* @.str, i32 0, i32 0), i32 1, double 2.000000e+00, i32 3, double 4.000000e+00) + tail call void (i8*, ...)* @f(i8* getelementptr ([1 x i8]* @.str, i32 0, i32 0), i32 1, double 2.000000e+00, i32 3, double 4.000000e+00) ret void } -declare arm_aapcscc void @f(i8*, ...) +declare void @f(i8*, ...) Modified: llvm/trunk/test/CodeGen/ARM/arm-frameaddr.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/arm-frameaddr.ll?rev=106029&r1=106028&r2=106029&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/arm-frameaddr.ll (original) +++ llvm/trunk/test/CodeGen/ARM/arm-frameaddr.ll Tue Jun 15 14:04:29 2010 @@ -3,7 +3,7 @@ ; PR4344 ; PR4416 -define arm_aapcscc i8* @t() nounwind { +define i8* @t() nounwind { entry: ; DARWIN: t: ; DARWIN: mov r0, r7 Modified: llvm/trunk/test/CodeGen/ARM/armv4.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/armv4.ll?rev=106029&r1=106028&r2=106029&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/armv4.ll (original) +++ llvm/trunk/test/CodeGen/ARM/armv4.ll Tue Jun 15 14:04:29 2010 @@ -5,7 +5,7 @@ ; RUN: llc < %s -mtriple=armv4-unknown-eabi | FileCheck %s -check-prefix=ARM ; RUN: llc < %s -mtriple=armv4t-unknown-eabi | FileCheck %s -check-prefix=THUMB -define arm_aapcscc i32 @test(i32 %a) nounwind readnone { +define i32 @test(i32 %a) nounwind readnone { entry: ; ARM: mov pc ; THUMB: bx Modified: llvm/trunk/test/CodeGen/Thumb2/2009-08-04-CoalescerAssert.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-08-04-CoalescerAssert.ll?rev=106029&r1=106028&r2=106029&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2009-08-04-CoalescerAssert.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2009-08-04-CoalescerAssert.ll Tue Jun 15 14:04:29 2010 @@ -5,7 +5,7 @@ %struct._IO_marker = type { %struct._IO_marker*, %struct.FILE*, i32 } @.str2 = external constant [30 x i8], align 1 ; <[30 x i8]*> [#uses=1] -define arm_aapcscc i32 @__mf_heuristic_check(i32 %ptr, i32 %ptr_high) nounwind { +define i32 @__mf_heuristic_check(i32 %ptr, i32 %ptr_high) nounwind { entry: br i1 undef, label %bb1, label %bb @@ -17,7 +17,7 @@ bb2: ; preds = %bb1 %0 = call i8* @llvm.frameaddress(i32 0) ; [#uses=1] - %1 = call arm_aapcscc i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* noalias undef, i8* noalias getelementptr ([30 x i8]* @.str2, i32 0, i32 0), i8* %0, i8* null) nounwind ; [#uses=0] + %1 = call i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* noalias undef, i8* noalias getelementptr ([30 x i8]* @.str2, i32 0, i32 0), i8* %0, i8* null) nounwind ; [#uses=0] unreachable bb9: ; preds = %bb1 @@ -26,4 +26,4 @@ declare i8* @llvm.frameaddress(i32) nounwind readnone -declare arm_aapcscc i32 @fprintf(%struct.FILE* noalias nocapture, i8* noalias nocapture, ...) nounwind +declare i32 @fprintf(%struct.FILE* noalias nocapture, i8* noalias nocapture, ...) nounwind Modified: llvm/trunk/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll?rev=106029&r1=106028&r2=106029&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll Tue Jun 15 14:04:29 2010 @@ -2,12 +2,12 @@ ; PR4659 ; PR4682 -define hidden arm_aapcscc i32 @__gcov_execlp(i8* %path, i8* %arg, ...) nounwind { +define hidden i32 @__gcov_execlp(i8* %path, i8* %arg, ...) nounwind { entry: ; CHECK: __gcov_execlp: ; CHECK: mov sp, r7 ; CHECK: sub sp, #4 - call arm_aapcscc void @__gcov_flush() nounwind + call void @__gcov_flush() nounwind br i1 undef, label %bb5, label %bb bb: ; preds = %bb, %entry @@ -15,10 +15,10 @@ bb5: ; preds = %bb, %entry %0 = alloca i8*, i32 undef, align 4 ; [#uses=1] - %1 = call arm_aapcscc i32 @execvp(i8* %path, i8** %0) nounwind ; [#uses=1] + %1 = call i32 @execvp(i8* %path, i8** %0) nounwind ; [#uses=1] ret i32 %1 } -declare hidden arm_aapcscc void @__gcov_flush() +declare hidden void @__gcov_flush() -declare arm_aapcscc i32 @execvp(i8*, i8**) nounwind +declare i32 @execvp(i8*, i8**) nounwind Modified: llvm/trunk/test/CodeGen/Thumb2/2009-08-08-ScavengerAssert.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-08-08-ScavengerAssert.ll?rev=106029&r1=106028&r2=106029&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2009-08-08-ScavengerAssert.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2009-08-08-ScavengerAssert.ll Tue Jun 15 14:04:29 2010 @@ -3,7 +3,7 @@ @g_d = external global double ; [#uses=1] -define arm_aapcscc void @foo(float %yIncr) { +define void @foo(float %yIncr) { entry: br i1 undef, label %bb, label %bb4 Modified: llvm/trunk/test/Transforms/ScalarRepl/memcpy-align.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ScalarRepl/memcpy-align.ll?rev=106029&r1=106028&r2=106029&view=diff ============================================================================== --- llvm/trunk/test/Transforms/ScalarRepl/memcpy-align.ll (original) +++ llvm/trunk/test/Transforms/ScalarRepl/memcpy-align.ll Tue Jun 15 14:04:29 2010 @@ -9,7 +9,7 @@ @c = external global %0 ; <%0*> [#uses=1] -define arm_aapcscc void @good() nounwind { +define void @good() nounwind { entry: %x0 = alloca %struct.anon, align 4 ; <%struct.anon*> [#uses=2] %tmp = bitcast %struct.anon* %x0 to i8* ; [#uses=1] From bob.wilson at apple.com Tue Jun 15 14:05:35 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 15 Jun 2010 19:05:35 -0000 Subject: [llvm-commits] [llvm] r106030 - in /llvm/trunk/lib/Target/ARM: ARMISelLowering.cpp ARMISelLowering.h ARMInstrNEON.td Message-ID: <20100615190535.5867A2A6C12C@llvm.org> Author: bwilson Date: Tue Jun 15 14:05:35 2010 New Revision: 106030 URL: http://llvm.org/viewvc/llvm-project?rev=106030&view=rev Log: Add basic support for NEON modified immediates besides VMOV. Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.h llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=106030&r1=106029&r2=106030&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Jun 15 14:05:35 2010 @@ -2766,10 +2766,18 @@ /// bits7-0=Immediate. static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef, unsigned SplatBitSize, SelectionDAG &DAG, - bool DoEncode) { + bool isVMOV, bool DoEncode) { unsigned Op, Cmode, Imm; EVT VT; + // SplatBitSize is set to the smallest size that splats the vector, so a + // zero vector will always have SplatBitSize == 8. However, NEON modified + // immediate instructions others than VMOV do not support the 8-bit encoding + // of a zero vector, and the default encoding of zero is supposed to be the + // 32-bit version. + if (SplatBits == 0) + SplatBitSize = 32; + Op = 0; switch (SplatBitSize) { case 8: @@ -2855,6 +2863,8 @@ case 64: { // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff. + if (!isVMOV) + return SDValue(); uint64_t BitMask = 0xff; uint64_t Val = 0; unsigned ImmMask = 1; @@ -2892,7 +2902,8 @@ /// with a "modified immediate" operand (e.g., VMOV) of the specified element /// size, return the encoded value for that immediate. The ByteSize field /// indicates the number of bytes of each element [1248]. -SDValue ARM::getNEONModImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { +SDValue ARM::getNEONModImm(SDNode *N, unsigned ByteSize, bool isVMOV, + SelectionDAG &DAG) { BuildVectorSDNode *BVN = dyn_cast(N); APInt SplatBits, SplatUndef; unsigned SplatBitSize; @@ -2905,7 +2916,7 @@ return SDValue(); return isNEONModifiedImm(SplatBits.getZExtValue(), SplatUndef.getZExtValue(), - SplatBitSize, DAG, true); + SplatBitSize, DAG, isVMOV, true); } static bool isVEXTMask(const SmallVectorImpl &M, EVT VT, @@ -3148,7 +3159,7 @@ // Check if an immediate VMOV works. SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(), SplatUndef.getZExtValue(), - SplatBitSize, DAG, false); + SplatBitSize, DAG, true, false); if (Val.getNode()) return BuildSplat(Val, VT, DAG, dl); } Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=106030&r1=106029&r2=106030&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Tue Jun 15 14:05:35 2010 @@ -154,7 +154,8 @@ /// instruction with a "modified immediate" operand (e.g., VMOV) of the /// specified element size, return the encoded value for that immediate. /// The ByteSize field indicates the number of bytes of each element [1248]. - SDValue getNEONModImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); + SDValue getNEONModImm(SDNode *N, unsigned ByteSize, bool isVMOV, + SelectionDAG &DAG); /// getVFPf32Imm / getVFPf64Imm - If the given fp immediate can be /// materialized with a VMOV.f32 / VMOV.f64 (i.e. fconsts / fconstd) Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=106030&r1=106029&r2=106030&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Jun 15 14:05:35 2010 @@ -2820,34 +2820,34 @@ // VMOV_get_imm8 xform function: convert build_vector to VMOV.i8 imm. def VMOV_get_imm8 : SDNodeXForm; def vmovImm8 : PatLeaf<(build_vector), [{ - return ARM::getNEONModImm(N, 1, *CurDAG).getNode() != 0; + return ARM::getNEONModImm(N, 1, true, *CurDAG).getNode() != 0; }], VMOV_get_imm8>; // VMOV_get_imm16 xform function: convert build_vector to VMOV.i16 imm. def VMOV_get_imm16 : SDNodeXForm; def vmovImm16 : PatLeaf<(build_vector), [{ - return ARM::getNEONModImm(N, 2, *CurDAG).getNode() != 0; + return ARM::getNEONModImm(N, 2, true, *CurDAG).getNode() != 0; }], VMOV_get_imm16>; // VMOV_get_imm32 xform function: convert build_vector to VMOV.i32 imm. def VMOV_get_imm32 : SDNodeXForm; def vmovImm32 : PatLeaf<(build_vector), [{ - return ARM::getNEONModImm(N, 4, *CurDAG).getNode() != 0; + return ARM::getNEONModImm(N, 4, true, *CurDAG).getNode() != 0; }], VMOV_get_imm32>; // VMOV_get_imm64 xform function: convert build_vector to VMOV.i64 imm. def VMOV_get_imm64 : SDNodeXForm; def vmovImm64 : PatLeaf<(build_vector), [{ - return ARM::getNEONModImm(N, 8, *CurDAG).getNode() != 0; + return ARM::getNEONModImm(N, 8, true, *CurDAG).getNode() != 0; }], VMOV_get_imm64>; // Note: Some of the cmode bits in the following VMOV instructions need to From clattner at apple.com Tue Jun 15 14:05:48 2010 From: clattner at apple.com (Chris Lattner) Date: Tue, 15 Jun 2010 12:05:48 -0700 Subject: [llvm-commits] [LLVMbugs] [Bug 7322] ms vcpp build warnings In-Reply-To: <4C1791A0.9030604@andric.com> References: <20100614203927.C1E7A2A6C12C@llvm.org> <4C1791A0.9030604@andric.com> Message-ID: <9B2F24FF-14A8-4EC2-B462-429E45E8C8EC@apple.com> Nate, can you change these to use "nElts << (int)quad" or something? -Chris On Jun 15, 2010, at 7:43 AM, Dimitry Andric wrote: > On 2010-06-14 22:39, bugzilla-daemon at llvm.org wrote: >> --- Comment #1 from Chris Lattner 2010-06-14 15:39:27 CDT --- >> there are a bunch of build warnings with MSVC. If you're interested in helping >> with this, please send patches to llvm-commits, thanks! > > What I see quite often with VC++ is this warning: > > .\NeonEmitter.cpp(529) : warning C4804: '<<' : unsafe use of type 'bool' in operation > > which comes from bool variables used as shift count, e.g: > > bool dummy, quad = false; > ... > b = Duplicate(nElts << quad, typestr, "b"); > > I'm not sure if this is unnecessarily paranoid of VC++, as the standard > seems to imply it should be no problem, if I read it correctly: > > [conv.prom] > 4. An rvalue of type bool can be converted to an rvalue of type int, > with false becoming zero and true becoming one. > > and [conv.integral]: > > 4. If the destination type is bool, see 4.12. If the source type is > bool, the value false is converted to zero and the value true is > converted to one. > > In short, is it worthwhile to appease VC++ here, by using an int or > unsigned instead, or should we just stash in a pragma to disable this > particular warning? > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From sabre at nondot.org Tue Jun 15 14:08:40 2010 From: sabre at nondot.org (Chris Lattner) Date: Tue, 15 Jun 2010 19:08:40 -0000 Subject: [llvm-commits] [llvm] r106031 - in /llvm/trunk: lib/Target/X86/X86FastISel.cpp test/CodeGen/X86/2010-06-14-fast-isel-fs-load.ll Message-ID: <20100615190840.79F812A6C12C@llvm.org> Author: lattner Date: Tue Jun 15 14:08:40 2010 New Revision: 106031 URL: http://llvm.org/viewvc/llvm-project?rev=106031&view=rev Log: fix fastisel to handle GS and FS relative pointers. Patch by Nelson Elhage! Added: llvm/trunk/test/CodeGen/X86/2010-06-14-fast-isel-fs-load.ll Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=106031&r1=106030&r2=106031&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Tue Jun 15 14:08:40 2010 @@ -349,6 +349,11 @@ U = C; } + if (const PointerType *Ty = dyn_cast(V->getType())) + if (Ty->getAddressSpace() > 255) + // Fast instruction selection doesn't support pointers through %fs or %gs + return false; + switch (Opcode) { default: break; case Instruction::BitCast: Added: llvm/trunk/test/CodeGen/X86/2010-06-14-fast-isel-fs-load.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-06-14-fast-isel-fs-load.ll?rev=106031&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2010-06-14-fast-isel-fs-load.ll (added) +++ llvm/trunk/test/CodeGen/X86/2010-06-14-fast-isel-fs-load.ll Tue Jun 15 14:08:40 2010 @@ -0,0 +1,6 @@ +; RUN: llc -fast-isel -march=x86 < %s | grep %fs: + +define i32 @test1(i32 addrspace(257)* %arg) nounwind { + %tmp = load i32 addrspace(257)* %arg + ret i32 %tmp +} From clattner at apple.com Tue Jun 15 14:09:00 2010 From: clattner at apple.com (Chris Lattner) Date: Tue, 15 Jun 2010 12:09:00 -0700 Subject: [llvm-commits] [patch] X86FastISel can't handle loads through %fs or %gs In-Reply-To: <87r5k9dr3c.fsf@mit.edu> References: <87r5k9dr3c.fsf@mit.edu> Message-ID: <7359BE5B-636C-4841-9402-D3D2F30B5AD0@apple.com> On Jun 14, 2010, at 6:25 PM, Nelson Elhage wrote: > This patch causes X86FastIsel to bail out on loads through %fs or %gs > (i.e. address spaces > 255), which lets us fall back to regular isel and > correctly compile loads through those segment registers at -O0. > > The addrspace(256) -> %GS feature is still buggy (See PR3966), but this > seems like a strict improvement, and I expect that feature is used > rarely enough that the performance cost of going through regular > instruction selection is probably acceptable. Looks great, applied in r106031! -Chris From clattner at apple.com Tue Jun 15 14:11:28 2010 From: clattner at apple.com (Chris Lattner) Date: Tue, 15 Jun 2010 12:11:28 -0700 Subject: [llvm-commits] [llvm] r105519 - in /llvm/trunk: docs/TableGenFundamentals.html test/TableGen/DefmInsideMultiClass.td utils/TableGen/TGParser.cpp utils/TableGen/TGParser.h In-Reply-To: <20100605021152.9A96E312800A@llvm.org> References: <20100605021152.9A96E312800A@llvm.org> Message-ID: On Jun 4, 2010, at 7:11 PM, Bruno Cardoso Lopes wrote: > Author: bruno > Date: Fri Jun 4 21:11:52 2010 > New Revision: 105519 > > URL: http://llvm.org/viewvc/llvm-project?rev=105519&view=rev > Log: > Teach tablegen to support 'defm' inside multiclasses. Very nice Bruno! -Chris From daniel at zuster.org Tue Jun 15 14:20:28 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Tue, 15 Jun 2010 19:20:28 -0000 Subject: [llvm-commits] [llvm] r106032 - /llvm/trunk/lib/Support/FileUtilities.cpp Message-ID: <20100615192028.6ABA02A6C12C@llvm.org> Author: ddunbar Date: Tue Jun 15 14:20:28 2010 New Revision: 106032 URL: http://llvm.org/viewvc/llvm-project?rev=106032&view=rev Log: fpcmp: Fix a possible infinite loop when comparing something like: 1..19 ok to 1..20 o k (yes, the odd space is necessary). Modified: llvm/trunk/lib/Support/FileUtilities.cpp Modified: llvm/trunk/lib/Support/FileUtilities.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/FileUtilities.cpp?rev=106032&r1=106031&r2=106032&view=diff ============================================================================== --- llvm/trunk/lib/Support/FileUtilities.cpp (original) +++ llvm/trunk/lib/Support/FileUtilities.cpp Tue Jun 15 14:20:28 2010 @@ -51,7 +51,15 @@ if (!isNumberChar(*Pos)) return Pos; // Otherwise, return to the start of the number. + bool HasPeriod = false; while (Pos > FirstChar && isNumberChar(Pos[-1])) { + // Backup over at most one period. + if (Pos[-1] == '.') { + if (HasPeriod) + break; + HasPeriod = true; + } + --Pos; if (Pos > FirstChar && isSignedChar(Pos[0]) && !isExponentChar(Pos[-1])) break; From daniel at zuster.org Tue Jun 15 14:20:30 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Tue, 15 Jun 2010 19:20:30 -0000 Subject: [llvm-commits] [llvm] r106033 - /llvm/trunk/lib/Support/FileUtilities.cpp Message-ID: <20100615192030.A37AB2A6C12D@llvm.org> Author: ddunbar Date: Tue Jun 15 14:20:30 2010 New Revision: 106033 URL: http://llvm.org/viewvc/llvm-project?rev=106033&view=rev Log: fpcmp: Fix bug where fpcmp wouldn't early exit when files obviously differ and no tolerance is set. Modified: llvm/trunk/lib/Support/FileUtilities.cpp Modified: llvm/trunk/lib/Support/FileUtilities.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/FileUtilities.cpp?rev=106033&r1=106032&r2=106033&view=diff ============================================================================== --- llvm/trunk/lib/Support/FileUtilities.cpp (original) +++ llvm/trunk/lib/Support/FileUtilities.cpp Tue Jun 15 14:20:30 2010 @@ -212,16 +212,16 @@ const char *F1P = File1Start; const char *F2P = File2Start; - if (A_size == B_size) { - // Are the buffers identical? Common case: Handle this efficiently. - if (std::memcmp(File1Start, File2Start, A_size) == 0) - return 0; - - if (AbsTol == 0 && RelTol == 0) { - if (Error) - *Error = "Files differ without tolerance allowance"; - return 1; // Files different! - } + // Are the buffers identical? Common case: Handle this efficiently. + if (A_size == B_size && + std::memcmp(File1Start, File2Start, A_size) == 0) + return 0; + + // Otherwise, we are done a tolerances are set. + if (AbsTol == 0 && RelTol == 0) { + if (Error) + *Error = "Files differ without tolerance allowance"; + return 1; // Files different! } bool CompareFailed = false; From espindola at google.com Tue Jun 15 14:30:14 2010 From: espindola at google.com (Rafael Espindola) Date: Tue, 15 Jun 2010 15:30:14 -0400 Subject: [llvm-commits] [patch] Remove arm_aapcscc from some tests In-Reply-To: <9601F397-5FAC-469F-A704-EF38972AE22E@apple.com> References: <250924C5-EF3C-4CB0-BD7C-7F42F9B1D27D@apple.com> <9601F397-5FAC-469F-A704-EF38972AE22E@apple.com> Message-ID: > I guess so. ?I don't have any objections to your change as long as it doesn't break the tests. The equivalent patch for apcs is attached. Is it OK? Cheers, -- Rafael ?vila de Esp?ndola -------------- next part -------------- A non-text attachment was scrubbed... Name: apcs.patch.gz Type: application/x-gzip Size: 24668 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100615/ee60674b/attachment.gz From nbegeman at apple.com Tue Jun 15 14:45:58 2010 From: nbegeman at apple.com (nate begeman) Date: Tue, 15 Jun 2010 12:45:58 -0700 Subject: [llvm-commits] [LLVMbugs] [Bug 7322] ms vcpp build warnings In-Reply-To: <9B2F24FF-14A8-4EC2-B462-429E45E8C8EC@apple.com> References: <20100614203927.C1E7A2A6C12C@llvm.org> <4C1791A0.9030604@andric.com> <9B2F24FF-14A8-4EC2-B462-429E45E8C8EC@apple.com> Message-ID: Sure, sorry, I seemed to recall shifts implicitly promoting to int, but maybe that's in C and not C++, will cast. Nate On Jun 15, 2010, at 12:05 PM, Chris Lattner wrote: > Nate, can you change these to use "nElts << (int)quad" or something? > > -Chris > > On Jun 15, 2010, at 7:43 AM, Dimitry Andric wrote: > >> On 2010-06-14 22:39, bugzilla-daemon at llvm.org wrote: >>> --- Comment #1 from Chris Lattner 2010-06-14 15:39:27 CDT --- >>> there are a bunch of build warnings with MSVC. If you're interested in helping >>> with this, please send patches to llvm-commits, thanks! >> >> What I see quite often with VC++ is this warning: >> >> .\NeonEmitter.cpp(529) : warning C4804: '<<' : unsafe use of type 'bool' in operation >> >> which comes from bool variables used as shift count, e.g: >> >> bool dummy, quad = false; >> ... >> b = Duplicate(nElts << quad, typestr, "b"); >> >> I'm not sure if this is unnecessarily paranoid of VC++, as the standard >> seems to imply it should be no problem, if I read it correctly: >> >> [conv.prom] >> 4. An rvalue of type bool can be converted to an rvalue of type int, >> with false becoming zero and true becoming one. >> >> and [conv.integral]: >> >> 4. If the destination type is bool, see 4.12. If the source type is >> bool, the value false is converted to zero and the value true is >> converted to one. >> >> In short, is it worthwhile to appease VC++ here, by using an int or >> unsigned instead, or should we just stash in a pragma to disable this >> particular warning? >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From daniel at zuster.org Tue Jun 15 15:01:10 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Tue, 15 Jun 2010 20:01:10 -0000 Subject: [llvm-commits] [test-suite] r106035 - /test-suite/trunk/Makefile.programs Message-ID: <20100615200110.BE9FD2A6C12C@llvm.org> Author: ddunbar Date: Tue Jun 15 15:01:10 2010 New Revision: 106035 URL: http://llvm.org/viewvc/llvm-project?rev=106035&view=rev Log: Run DiffOutput/fpcmp under RunToolSafely, to allow testing old revisions which unfortunately hit the fpcmp infinite loop when testing with Clang. Modified: test-suite/trunk/Makefile.programs Modified: test-suite/trunk/Makefile.programs URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/Makefile.programs?rev=106035&r1=106034&r2=106035&view=diff ============================================================================== --- test-suite/trunk/Makefile.programs (original) +++ test-suite/trunk/Makefile.programs Tue Jun 15 15:01:10 2010 @@ -64,7 +64,12 @@ endif # DIFFPROG - The program used to diff the output -DIFFPROG := $(PROGDIR)/DiffOutput.sh "$(LLVMTOOLCURRENT)/fpcmp $(TOLERANCEOPT)" +# +# We run this under RunToolSafely because 'fpcmp' at one point would infinite +# loop on some inputs, which blocks testing some historical revisions. We can +# remove this once we build our own test tools. +DIFFPROG := $(PROGDIR)/RunToolSafely.sh 60 \ + $(PROGDIR)/DiffOutput.sh "$(LLVMTOOLCURRENT)/fpcmp $(TOLERANCEOPT)" # RUNTIMELIMIT - The number of seconds we should wait before certain events # timeout. This is overridable on the commandline or in tests makefiles. From bob.wilson at apple.com Tue Jun 15 15:10:27 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 15 Jun 2010 13:10:27 -0700 Subject: [llvm-commits] [patch] Remove arm_aapcscc from some tests In-Reply-To: References: <250924C5-EF3C-4CB0-BD7C-7F42F9B1D27D@apple.com> <9601F397-5FAC-469F-A704-EF38972AE22E@apple.com> Message-ID: <7BDDBF70-72CC-4A74-A676-568E4D35E8B9@apple.com> On Jun 15, 2010, at 12:30 PM, Rafael Espindola wrote: >> I guess so. I don't have any objections to your change as long as it doesn't break the tests. > > The equivalent patch for apcs is attached. Is it OK? I'm OK with it as long as the default ABI for non-Linux targets is APCS. I took a quick look at it seems like that is true; AAPCS is only the default if the triple includes "eabi". Otherwise, you're potentially changing the behavior of a lot of tests. Even if those tests are not directly related to testing the ABI, there may be differences that affect what the tests do. In light of that, I recommend you take another look at the test changes you made to remove "arm_aapcscc". There were fewer of them, so it shouldn't be too hard. Since you removed the ABI specifier, it would be a good idea to change those tests to use a target triple that defaults to AAPCS so that those tests continue testing what they were doing before. From espindola at google.com Tue Jun 15 15:25:08 2010 From: espindola at google.com (Rafael Espindola) Date: Tue, 15 Jun 2010 16:25:08 -0400 Subject: [llvm-commits] [patch] Update llvm-gcc to produce "" for the default calling convention on ARM Message-ID: With the attached patch llvm-gcc produces "" as the calling convention by default. I manually checked that arm_aapcs_vfpcc is produced when -mfloat-abi=hard is used. Cheers, -- Rafael ?vila de Esp?ndola -------------- next part -------------- A non-text attachment was scrubbed... Name: llvm-gcc-cc.patch Type: text/x-patch Size: 1683 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100615/e1685333/attachment.bin From wangmp at apple.com Tue Jun 15 15:29:05 2010 From: wangmp at apple.com (Mon P Wang) Date: Tue, 15 Jun 2010 20:29:05 -0000 Subject: [llvm-commits] [llvm] r106038 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp test/CodeGen/Generic/v-binop-widen.ll test/CodeGen/Generic/v-binop-widen2.ll Message-ID: <20100615202905.4C9A42A6C12C@llvm.org> Author: wangmp Date: Tue Jun 15 15:29:05 2010 New Revision: 106038 URL: http://llvm.org/viewvc/llvm-project?rev=106038&view=rev Log: Fixed vector widening of binary instructions that can trap. Patch by Visa Putkinen! Added: llvm/trunk/test/CodeGen/Generic/v-binop-widen.ll llvm/trunk/test/CodeGen/Generic/v-binop-widen2.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=106038&r1=106037&r2=106038&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Tue Jun 15 15:29:05 2010 @@ -1271,7 +1271,7 @@ EVT WidenEltVT = WidenVT.getVectorElementType(); EVT VT = WidenVT; unsigned NumElts = VT.getVectorNumElements(); - while (!TLI.isTypeLegal(VT) && NumElts != 1) { + while (!TLI.isTypeSynthesizable(VT) && NumElts != 1) { NumElts = NumElts / 2; VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts); } @@ -1286,13 +1286,20 @@ return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements()); } else { // Since the operation can trap, apply operation on the original vector. + EVT MaxVT = VT; SDValue InOp1 = GetWidenedVector(N->getOperand(0)); SDValue InOp2 = GetWidenedVector(N->getOperand(1)); unsigned CurNumElts = N->getValueType(0).getVectorNumElements(); SmallVector ConcatOps(CurNumElts); unsigned ConcatEnd = 0; // Current ConcatOps index. - unsigned Idx = 0; // Current Idx into input vectors. + int Idx = 0; // Current Idx into input vectors. + + // NumElts := greatest synthesizable vector size (at most WidenVT) + // while (orig. vector has unhandled elements) { + // take munches of size NumElts from the beginning and add to ConcatOps + // NumElts := next smaller supported vector size or 1 + // } while (CurNumElts != 0) { while (CurNumElts >= NumElts) { SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1, @@ -1303,26 +1310,21 @@ Idx += NumElts; CurNumElts -= NumElts; } - EVT PrevVecVT = VT; do { NumElts = NumElts / 2; VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts); - } while (!TLI.isTypeLegal(VT) && NumElts != 1); + } while (!TLI.isTypeSynthesizable(VT) && NumElts != 1); if (NumElts == 1) { - // Since we are using concat vector, build a vector from the scalar ops. - SDValue VecOp = DAG.getUNDEF(PrevVecVT); for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) { SDValue EOp1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, InOp1, DAG.getIntPtrConstant(Idx)); SDValue EOp2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, InOp2, DAG.getIntPtrConstant(Idx)); - VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, PrevVecVT, VecOp, - DAG.getNode(Opcode, dl, WidenEltVT, EOp1, EOp2), - DAG.getIntPtrConstant(i)); + ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT, + EOp1, EOp2); } CurNumElts = 0; - ConcatOps[ConcatEnd++] = VecOp; } } @@ -1333,23 +1335,65 @@ return ConcatOps[0]; } - // Rebuild vector to one with the widen type - Idx = ConcatEnd - 1; - while (Idx != 0) { + // while (Some element of ConcatOps is not of type MaxVT) { + // From the end of ConcatOps, collect elements of the same type and put + // them into an op of the next larger supported type + // } + while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) { + Idx = ConcatEnd - 1; VT = ConcatOps[Idx--].getValueType(); - while (Idx != 0 && ConcatOps[Idx].getValueType() == VT) - --Idx; - if (Idx != 0) { - VT = ConcatOps[Idx].getValueType(); - ConcatOps[Idx+1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, - &ConcatOps[Idx+1], ConcatEnd - Idx - 1); + while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT) + Idx--; + + int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1; + EVT NextVT; + do { + NextSize *= 2; + NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize); + } while (!TLI.isTypeSynthesizable(NextVT)); + + if (!VT.isVector()) { + // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT + SDValue VecOp = DAG.getUNDEF(NextVT); + unsigned NumToInsert = ConcatEnd - Idx - 1; + for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) { + VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, + ConcatOps[OpIdx], DAG.getIntPtrConstant(i)); + } + ConcatOps[Idx+1] = VecOp; ConcatEnd = Idx + 2; + } + else { + // Vector type, create a CONCAT_VECTORS of type NextVT + SDValue undefVec = DAG.getUNDEF(VT); + unsigned OpsToConcat = NextSize/VT.getVectorNumElements(); + SmallVector SubConcatOps(OpsToConcat); + unsigned RealVals = ConcatEnd - Idx - 1; + unsigned SubConcatEnd = 0; + unsigned SubConcatIdx = Idx + 1; + while (SubConcatEnd < RealVals) + SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx]; + while (SubConcatEnd < OpsToConcat) + SubConcatOps[SubConcatEnd++] = undefVec; + ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl, + NextVT, &SubConcatOps[0], + OpsToConcat); + ConcatEnd = SubConcatIdx + 1; } } + + // Check to see if we have a single operation with the widen type. + if (ConcatEnd == 1) { + VT = ConcatOps[0].getValueType(); + if (VT == WidenVT) + return ConcatOps[0]; + } - unsigned NumOps = WidenVT.getVectorNumElements()/VT.getVectorNumElements(); + // add undefs of size MaxVT until ConcatOps grows to length of WidenVT + unsigned NumOps = + WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements(); if (NumOps != ConcatEnd ) { - SDValue UndefVal = DAG.getUNDEF(VT); + SDValue UndefVal = DAG.getUNDEF(MaxVT); for (unsigned j = ConcatEnd; j < NumOps; ++j) ConcatOps[j] = UndefVal; } @@ -1379,7 +1423,7 @@ return DAG.getNode(Opcode, dl, WidenVT, InOp); } - if (TLI.isTypeLegal(InWidenVT)) { + if (TLI.isTypeSynthesizable(InWidenVT)) { // Because the result and the input are different vector types, widening // the result could create a legal type but widening the input might make // it an illegal type that might lead to repeatedly splitting the input @@ -1521,7 +1565,7 @@ NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts); } - if (TLI.isTypeLegal(NewInVT)) { + if (TLI.isTypeSynthesizable(NewInVT)) { // Because the result and the input are different vector types, widening // the result could create a legal type but widening the input might make // it an illegal type that might lead to repeatedly splitting the input @@ -1662,7 +1706,7 @@ SatOp, CvtCode); } - if (TLI.isTypeLegal(InWidenVT)) { + if (TLI.isTypeSynthesizable(InWidenVT)) { // Because the result and the input are different vector types, widening // the result could create a legal type but widening the input might make // it an illegal type that might lead to repeatedly splitting the input @@ -1988,7 +2032,7 @@ if (InWidenSize % Size == 0 && !VT.isVector()) { unsigned NewNumElts = InWidenSize / Size; EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts); - if (TLI.isTypeLegal(NewVT)) { + if (TLI.isTypeSynthesizable(NewVT)) { SDValue BitOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, InOp); return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp, DAG.getIntPtrConstant(0)); @@ -2086,7 +2130,7 @@ unsigned MemVTWidth = MemVT.getSizeInBits(); if (MemVT.getSizeInBits() <= WidenEltWidth) break; - if (TLI.isTypeLegal(MemVT) && (WidenWidth % MemVTWidth) == 0 && + if (TLI.isTypeSynthesizable(MemVT) && (WidenWidth % MemVTWidth) == 0 && (MemVTWidth <= Width || (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) { RetVT = MemVT; @@ -2100,7 +2144,7 @@ VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) { EVT MemVT = (MVT::SimpleValueType) VT; unsigned MemVTWidth = MemVT.getSizeInBits(); - if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() && + if (TLI.isTypeSynthesizable(MemVT) && WidenEltVT == MemVT.getVectorElementType() && (WidenWidth % MemVTWidth) == 0 && (MemVTWidth <= Width || (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) { Added: llvm/trunk/test/CodeGen/Generic/v-binop-widen.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/v-binop-widen.ll?rev=106038&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Generic/v-binop-widen.ll (added) +++ llvm/trunk/test/CodeGen/Generic/v-binop-widen.ll Tue Jun 15 15:29:05 2010 @@ -0,0 +1,8 @@ +; RUN: llc -march=x86 %s + +%vec = type <9 x float> +define %vec @vecdiv( %vec %p1, %vec %p2) +{ + %result = fdiv %vec %p1, %p2 + ret %vec %result +} Added: llvm/trunk/test/CodeGen/Generic/v-binop-widen2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/v-binop-widen2.ll?rev=106038&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Generic/v-binop-widen2.ll (added) +++ llvm/trunk/test/CodeGen/Generic/v-binop-widen2.ll Tue Jun 15 15:29:05 2010 @@ -0,0 +1,37 @@ +; RUN: llvm-as < %s | lli + +%vec = type <6 x float> + +define %vec @vecdiv( %vec %p1, %vec %p2) +{ + %result = fdiv %vec %p1, %p2 + ret %vec %result +} + + at a = constant %vec < float 2.0, float 4.0, float 8.0, float 16.0, float 32.0, float 64.0 > + at b = constant %vec < float 2.0, float 2.0, float 2.0, float 2.0, float 2.0, float 2.0 > + +; Expected result: < 1.0, 2.0, 4.0, ..., 2.0^(n-1) > +; main() returns 0 if the result is expected and 1 otherwise +define i32 @main() nounwind { +entry: + %avec = load %vec* @a + %bvec = load %vec* @b + + %res = call %vec @vecdiv(%vec %avec, %vec %bvec) + br label %loop +loop: + %idx = phi i32 [0, %entry], [%nextInd, %looptail] + %expected = phi float [1.0, %entry], [%nextExpected, %looptail] + %elem = extractelement %vec %res, i32 %idx + %expcmp = fcmp oeq float %elem, %expected + br i1 %expcmp, label %looptail, label %return +looptail: + %nextExpected = fmul float %expected, 2.0 + %nextInd = add i32 %idx, 1 + %cmp = icmp slt i32 %nextInd, 6 + br i1 %cmp, label %loop, label %return +return: + %retval = phi i32 [0, %looptail], [1, %loop] + ret i32 %retval +} From monping at apple.com Tue Jun 15 15:30:09 2010 From: monping at apple.com (Mon Ping Wang) Date: Tue, 15 Jun 2010 13:30:09 -0700 Subject: [llvm-commits] Buggy SelectionDAG binop vector widening In-Reply-To: <20100614145634.GE30776@cc.hut.fi> References: <20100603132756.GA30866@cc.hut.fi> <86CAA4FC-4CE3-4E7E-B0A4-58DE974B9176@apple.com> <20100608092644.GB30866@cc.hut.fi> <097373B3-998A-4F32-8688-AF7CB8271F35@apple.com> <4C0F3563.1040702@free.fr> <13CA807A-F47C-42F4-ABB4-58EB544226D9@apple.com> <20100614145634.GE30776@cc.hut.fi> Message-ID: Thanks for the patch. Applied in r106038. -- Mon Ping On Jun 14, 2010, at 7:56 AM, Visa Putkinen wrote: > Hi! > > Sorry for the long delay. > > On Wed, Jun 09, 2010 at 11:25:20PM -0700, Mon Ping Wang wrote: >> All the occurrences in widening should use isTypeLegal should be updated to use isTypeSynthesizable but I can do that update if you prefer after this patch is in. > > I replaced all isTypeLegals with isTypeSynthesizable in > LegalizeVectorTypes.cpp to spare you the trouble. > >> Looking at the changes, it overall looks good. The code now separates the code that breaks the vector into synthesizable types with where it recombines it. I think we can simplify the code during the recombine step >> while (true) { >> bool wrongTypeInConcatOps = false; >> for (Idx = ConcatEnd - 1; Idx >= 0; Idx--) { >> if (ConcatOps[Idx].getValueType() != MaxVT) { >> wrongTypeInConcatOps = true; >> break; >> } >> } >> if(!wrongTypeInConcatOps) >> break; >> ... >> } >> >> When we split the vector into synthesizable types, we go form largest to smallest. If the last piece is the list of operations we want to concatenate is MaxVT, I believe every other piece must be MaxVT so we don't need the loop. I think we can get rid of the for loop and we can move the condition into the while. > > A very good observation! I didn't like the clumsy for loop either, so > good riddance. I implemented your suggestion and it does work: with the > patch (against r105937) llc produces correct code from > 'fdiv %a, %b' for x86-64 for vector lengths 1-32. The > updated patch is attached. > > Two DejaGNU test cases are also included in the patch. > > -- > Visa Putkinen // vputkine at cs.hut.fi > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From rafael.espindola at gmail.com Tue Jun 15 15:42:00 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Tue, 15 Jun 2010 20:42:00 -0000 Subject: [llvm-commits] [llvm] r106041 - in /llvm/trunk/test/CodeGen/ARM: 2009-08-04-RegScavengerAssert-2.ll 2009-08-04-RegScavengerAssert.ll 2009-08-15-RegScavenger-EarlyClobber.ll 2009-08-15-RegScavengerAssert.ll Message-ID: <20100615204200.B40CD2A6C12C@llvm.org> Author: rafael Date: Tue Jun 15 15:42:00 2010 New Revision: 106041 URL: http://llvm.org/viewvc/llvm-project?rev=106041&view=rev Log: Set the mtriple in some tests so that they use AAPCS. Modified: llvm/trunk/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll llvm/trunk/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll llvm/trunk/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll llvm/trunk/test/CodeGen/ARM/2009-08-15-RegScavengerAssert.ll Modified: llvm/trunk/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll?rev=106041&r1=106040&r2=106041&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll Tue Jun 15 15:42:00 2010 @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=armv6-elf +; RUN: llc < %s -mtriple=arm-linux-gnueabi ; PR4528 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64" Modified: llvm/trunk/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll?rev=106041&r1=106040&r2=106041&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll Tue Jun 15 15:42:00 2010 @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=armv6-elf +; RUN: llc < %s -mtriple=arm-linux-gnueabi ; PR4528 define i32 @file_read_actor(i32 %desc, i32 %page, i32 %offset, i32 %size) nounwind optsize { Modified: llvm/trunk/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll?rev=106041&r1=106040&r2=106041&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll Tue Jun 15 15:42:00 2010 @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm +; RUN: llc < %s -mtriple=arm-linux-gnueabi ; PR4528 ; Inline asm is allowed to contain operands "=&r", "0". Modified: llvm/trunk/test/CodeGen/ARM/2009-08-15-RegScavengerAssert.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-08-15-RegScavengerAssert.ll?rev=106041&r1=106040&r2=106041&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-08-15-RegScavengerAssert.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2009-08-15-RegScavengerAssert.ll Tue Jun 15 15:42:00 2010 @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm +; RUN: llc < %s -mtriple=arm-linux-gnueabi ; PR4716 define void @_start() nounwind naked { From bob.wilson at apple.com Tue Jun 15 15:44:09 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 15 Jun 2010 13:44:09 -0700 Subject: [llvm-commits] [llvm] r106029 - in /llvm/trunk/test: CodeGen/ARM/ CodeGen/Thumb2/ Transforms/ScalarRepl/ In-Reply-To: <20100615190430.2F4C32A6C12C@llvm.org> References: <20100615190430.2F4C32A6C12C@llvm.org> Message-ID: <1E956E78-3033-4947-AEEC-D4344DE897B0@apple.com> I think I mentioned this in another message, but this is changing the behavior of at least some of these tests. For example, the first one has a target triple of "armv6-elf", which as far as I can tell, has a default ABI of APCS. So you've changed that test to use APCS instead of AAPCS. Unless you think there's a problem with the tests, it would be better to avoid random changes that may prevent them from testing what they were intended to test. On Jun 15, 2010, at 12:04 PM, Rafael Espindola wrote: > Author: rafael > Date: Tue Jun 15 14:04:29 2010 > New Revision: 106029 > > URL: http://llvm.org/viewvc/llvm-project?rev=106029&view=rev > Log: > Remove the arm_aapcscc marker from the tests. It is the default > for the linux targets. > > Modified: > llvm/trunk/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll > llvm/trunk/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll > llvm/trunk/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll > llvm/trunk/test/CodeGen/ARM/2009-08-15-RegScavengerAssert.ll > llvm/trunk/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll > llvm/trunk/test/CodeGen/ARM/2009-10-27-double-align.ll > llvm/trunk/test/CodeGen/ARM/arm-frameaddr.ll > llvm/trunk/test/CodeGen/ARM/armv4.ll > llvm/trunk/test/CodeGen/Thumb2/2009-08-04-CoalescerAssert.ll > llvm/trunk/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll > llvm/trunk/test/CodeGen/Thumb2/2009-08-08-ScavengerAssert.ll > llvm/trunk/test/Transforms/ScalarRepl/memcpy-align.ll > > Modified: llvm/trunk/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll?rev=106029&r1=106028&r2=106029&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll (original) > +++ llvm/trunk/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll Tue Jun 15 14:04:29 2010 > @@ -4,7 +4,7 @@ > target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64" > target triple = "armv6-elf" > > -define arm_aapcscc i32 @file_read_actor(i32* nocapture %desc, i32* %page, i32 %offset, i32 %size) nounwind optsize { > +define i32 @file_read_actor(i32* nocapture %desc, i32* %page, i32 %offset, i32 %size) nounwind optsize { > entry: > br i1 undef, label %fault_in_pages_writeable.exit, label %bb5.i > > @@ -26,8 +26,8 @@ > unreachable > > bb3: ; preds = %fault_in_pages_writeable.exit > - %1 = tail call arm_aapcscc i32 @__copy_to_user(i8* undef, i8* undef, i32 undef) nounwind ; [#uses=0] > + %1 = tail call i32 @__copy_to_user(i8* undef, i8* undef, i32 undef) nounwind ; [#uses=0] > unreachable > } > > -declare arm_aapcscc i32 @__copy_to_user(i8*, i8*, i32) > +declare i32 @__copy_to_user(i8*, i8*, i32) > > Modified: llvm/trunk/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll?rev=106029&r1=106028&r2=106029&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll (original) > +++ llvm/trunk/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll Tue Jun 15 14:04:29 2010 > @@ -1,7 +1,7 @@ > ; RUN: llc < %s -mtriple=armv6-elf > ; PR4528 > > -define arm_aapcscc i32 @file_read_actor(i32 %desc, i32 %page, i32 %offset, i32 %size) nounwind optsize { > +define i32 @file_read_actor(i32 %desc, i32 %page, i32 %offset, i32 %size) nounwind optsize { > entry: > br i1 undef, label %fault_in_pages_writeable.exit, label %bb5.i > > @@ -18,8 +18,8 @@ > unreachable > > bb3: ; preds = %fault_in_pages_writeable.exit > - %2 = tail call arm_aapcscc i32 @__copy_to_user(i8* undef, i8* undef, i32 undef) nounwind ; [#uses=0] > + %2 = tail call i32 @__copy_to_user(i8* undef, i8* undef, i32 undef) nounwind ; [#uses=0] > unreachable > } > > -declare arm_aapcscc i32 @__copy_to_user(i8*, i8*, i32) > +declare i32 @__copy_to_user(i8*, i8*, i32) > > Modified: llvm/trunk/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll?rev=106029&r1=106028&r2=106029&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll (original) > +++ llvm/trunk/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll Tue Jun 15 14:04:29 2010 > @@ -6,7 +6,7 @@ > %struct.device_dma_parameters = type { i32, i32 } > %struct.iovec = type { i8*, i32 } > > -define arm_aapcscc i32 @generic_segment_checks(%struct.iovec* nocapture %iov, i32* nocapture %nr_segs, i32* nocapture %count, i32 %access_flags) nounwind optsize { > +define i32 @generic_segment_checks(%struct.iovec* nocapture %iov, i32* nocapture %nr_segs, i32* nocapture %count, i32 %access_flags) nounwind optsize { > entry: > br label %bb8 > > > Modified: llvm/trunk/test/CodeGen/ARM/2009-08-15-RegScavengerAssert.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-08-15-RegScavengerAssert.ll?rev=106029&r1=106028&r2=106029&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/ARM/2009-08-15-RegScavengerAssert.ll (original) > +++ llvm/trunk/test/CodeGen/ARM/2009-08-15-RegScavengerAssert.ll Tue Jun 15 14:04:29 2010 > @@ -1,10 +1,10 @@ > ; RUN: llc < %s -march=arm > ; PR4716 > > -define arm_aapcscc void @_start() nounwind naked { > +define void @_start() nounwind naked { > entry: > - tail call arm_aapcscc void @exit(i32 undef) noreturn nounwind > + tail call void @exit(i32 undef) noreturn nounwind > unreachable > } > > -declare arm_aapcscc void @exit(i32) noreturn nounwind > +declare void @exit(i32) noreturn nounwind > > Modified: llvm/trunk/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll?rev=106029&r1=106028&r2=106029&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll (original) > +++ llvm/trunk/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll Tue Jun 15 14:04:29 2010 > @@ -3,7 +3,7 @@ > > %0 = type { double, double } > > -define arm_aapcscc void @foo(%0* noalias nocapture sret %agg.result, double %x.0, double %y.0) nounwind { > +define void @foo(%0* noalias nocapture sret %agg.result, double %x.0, double %y.0) nounwind { > ; CHECK: foo: > ; CHECK: bl __adddf3 > ; CHECK-NOT: strd > > Modified: llvm/trunk/test/CodeGen/ARM/2009-10-27-double-align.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-10-27-double-align.ll?rev=106029&r1=106028&r2=106029&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/ARM/2009-10-27-double-align.ll (original) > +++ llvm/trunk/test/CodeGen/ARM/2009-10-27-double-align.ll Tue Jun 15 14:04:29 2010 > @@ -2,13 +2,13 @@ > > @.str = private constant [1 x i8] zeroinitializer, align 1 > > -define arm_aapcscc void @g() { > +define void @g() { > entry: > ;CHECK: [sp, #8] > ;CHECK: [sp, #12] > ;CHECK: [sp] > - tail call arm_aapcscc void (i8*, ...)* @f(i8* getelementptr ([1 x i8]* @.str, i32 0, i32 0), i32 1, double 2.000000e+00, i32 3, double 4.000000e+00) > + tail call void (i8*, ...)* @f(i8* getelementptr ([1 x i8]* @.str, i32 0, i32 0), i32 1, double 2.000000e+00, i32 3, double 4.000000e+00) > ret void > } > > -declare arm_aapcscc void @f(i8*, ...) > +declare void @f(i8*, ...) > > Modified: llvm/trunk/test/CodeGen/ARM/arm-frameaddr.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/arm-frameaddr.ll?rev=106029&r1=106028&r2=106029&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/ARM/arm-frameaddr.ll (original) > +++ llvm/trunk/test/CodeGen/ARM/arm-frameaddr.ll Tue Jun 15 14:04:29 2010 > @@ -3,7 +3,7 @@ > ; PR4344 > ; PR4416 > > -define arm_aapcscc i8* @t() nounwind { > +define i8* @t() nounwind { > entry: > ; DARWIN: t: > ; DARWIN: mov r0, r7 > > Modified: llvm/trunk/test/CodeGen/ARM/armv4.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/armv4.ll?rev=106029&r1=106028&r2=106029&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/ARM/armv4.ll (original) > +++ llvm/trunk/test/CodeGen/ARM/armv4.ll Tue Jun 15 14:04:29 2010 > @@ -5,7 +5,7 @@ > ; RUN: llc < %s -mtriple=armv4-unknown-eabi | FileCheck %s -check-prefix=ARM > ; RUN: llc < %s -mtriple=armv4t-unknown-eabi | FileCheck %s -check-prefix=THUMB > > -define arm_aapcscc i32 @test(i32 %a) nounwind readnone { > +define i32 @test(i32 %a) nounwind readnone { > entry: > ; ARM: mov pc > ; THUMB: bx > > Modified: llvm/trunk/test/CodeGen/Thumb2/2009-08-04-CoalescerAssert.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-08-04-CoalescerAssert.ll?rev=106029&r1=106028&r2=106029&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/Thumb2/2009-08-04-CoalescerAssert.ll (original) > +++ llvm/trunk/test/CodeGen/Thumb2/2009-08-04-CoalescerAssert.ll Tue Jun 15 14:04:29 2010 > @@ -5,7 +5,7 @@ > %struct._IO_marker = type { %struct._IO_marker*, %struct.FILE*, i32 } > @.str2 = external constant [30 x i8], align 1 ; <[30 x i8]*> [#uses=1] > > -define arm_aapcscc i32 @__mf_heuristic_check(i32 %ptr, i32 %ptr_high) nounwind { > +define i32 @__mf_heuristic_check(i32 %ptr, i32 %ptr_high) nounwind { > entry: > br i1 undef, label %bb1, label %bb > > @@ -17,7 +17,7 @@ > > bb2: ; preds = %bb1 > %0 = call i8* @llvm.frameaddress(i32 0) ; [#uses=1] > - %1 = call arm_aapcscc i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* noalias undef, i8* noalias getelementptr ([30 x i8]* @.str2, i32 0, i32 0), i8* %0, i8* null) nounwind ; [#uses=0] > + %1 = call i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* noalias undef, i8* noalias getelementptr ([30 x i8]* @.str2, i32 0, i32 0), i8* %0, i8* null) nounwind ; [#uses=0] > unreachable > > bb9: ; preds = %bb1 > @@ -26,4 +26,4 @@ > > declare i8* @llvm.frameaddress(i32) nounwind readnone > > -declare arm_aapcscc i32 @fprintf(%struct.FILE* noalias nocapture, i8* noalias nocapture, ...) nounwind > +declare i32 @fprintf(%struct.FILE* noalias nocapture, i8* noalias nocapture, ...) nounwind > > Modified: llvm/trunk/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll?rev=106029&r1=106028&r2=106029&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll (original) > +++ llvm/trunk/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll Tue Jun 15 14:04:29 2010 > @@ -2,12 +2,12 @@ > ; PR4659 > ; PR4682 > > -define hidden arm_aapcscc i32 @__gcov_execlp(i8* %path, i8* %arg, ...) nounwind { > +define hidden i32 @__gcov_execlp(i8* %path, i8* %arg, ...) nounwind { > entry: > ; CHECK: __gcov_execlp: > ; CHECK: mov sp, r7 > ; CHECK: sub sp, #4 > - call arm_aapcscc void @__gcov_flush() nounwind > + call void @__gcov_flush() nounwind > br i1 undef, label %bb5, label %bb > > bb: ; preds = %bb, %entry > @@ -15,10 +15,10 @@ > > bb5: ; preds = %bb, %entry > %0 = alloca i8*, i32 undef, align 4 ; [#uses=1] > - %1 = call arm_aapcscc i32 @execvp(i8* %path, i8** %0) nounwind ; [#uses=1] > + %1 = call i32 @execvp(i8* %path, i8** %0) nounwind ; [#uses=1] > ret i32 %1 > } > > -declare hidden arm_aapcscc void @__gcov_flush() > +declare hidden void @__gcov_flush() > > -declare arm_aapcscc i32 @execvp(i8*, i8**) nounwind > +declare i32 @execvp(i8*, i8**) nounwind > > Modified: llvm/trunk/test/CodeGen/Thumb2/2009-08-08-ScavengerAssert.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-08-08-ScavengerAssert.ll?rev=106029&r1=106028&r2=106029&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/Thumb2/2009-08-08-ScavengerAssert.ll (original) > +++ llvm/trunk/test/CodeGen/Thumb2/2009-08-08-ScavengerAssert.ll Tue Jun 15 14:04:29 2010 > @@ -3,7 +3,7 @@ > > @g_d = external global double ; [#uses=1] > > -define arm_aapcscc void @foo(float %yIncr) { > +define void @foo(float %yIncr) { > entry: > br i1 undef, label %bb, label %bb4 > > > Modified: llvm/trunk/test/Transforms/ScalarRepl/memcpy-align.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ScalarRepl/memcpy-align.ll?rev=106029&r1=106028&r2=106029&view=diff > ============================================================================== > --- llvm/trunk/test/Transforms/ScalarRepl/memcpy-align.ll (original) > +++ llvm/trunk/test/Transforms/ScalarRepl/memcpy-align.ll Tue Jun 15 14:04:29 2010 > @@ -9,7 +9,7 @@ > > @c = external global %0 ; <%0*> [#uses=1] > > -define arm_aapcscc void @good() nounwind { > +define void @good() nounwind { > entry: > %x0 = alloca %struct.anon, align 4 ; <%struct.anon*> [#uses=2] > %tmp = bitcast %struct.anon* %x0 to i8* ; [#uses=1] > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From bob.wilson at apple.com Tue Jun 15 15:45:36 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 15 Jun 2010 13:45:36 -0700 Subject: [llvm-commits] [llvm] r106029 - in /llvm/trunk/test: CodeGen/ARM/ CodeGen/Thumb2/ Transforms/ScalarRepl/ In-Reply-To: <1E956E78-3033-4947-AEEC-D4344DE897B0@apple.com> References: <20100615190430.2F4C32A6C12C@llvm.org> <1E956E78-3033-4947-AEEC-D4344DE897B0@apple.com> Message-ID: <4AE6647A-9079-4E2B-916A-55EC728F5733@apple.com> Nevermind. I see you already fixed that. On Jun 15, 2010, at 1:44 PM, Bob Wilson wrote: > I think I mentioned this in another message, but this is changing the behavior of at least some of these tests. For example, the first one has a target triple of "armv6-elf", which as far as I can tell, has a default ABI of APCS. So you've changed that test to use APCS instead of AAPCS. > > Unless you think there's a problem with the tests, it would be better to avoid random changes that may prevent them from testing what they were intended to test. > > On Jun 15, 2010, at 12:04 PM, Rafael Espindola wrote: > >> Author: rafael >> Date: Tue Jun 15 14:04:29 2010 >> New Revision: 106029 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=106029&view=rev >> Log: >> Remove the arm_aapcscc marker from the tests. It is the default >> for the linux targets. >> >> Modified: >> llvm/trunk/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll >> llvm/trunk/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll >> llvm/trunk/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll >> llvm/trunk/test/CodeGen/ARM/2009-08-15-RegScavengerAssert.ll >> llvm/trunk/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll >> llvm/trunk/test/CodeGen/ARM/2009-10-27-double-align.ll >> llvm/trunk/test/CodeGen/ARM/arm-frameaddr.ll >> llvm/trunk/test/CodeGen/ARM/armv4.ll >> llvm/trunk/test/CodeGen/Thumb2/2009-08-04-CoalescerAssert.ll >> llvm/trunk/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll >> llvm/trunk/test/CodeGen/Thumb2/2009-08-08-ScavengerAssert.ll >> llvm/trunk/test/Transforms/ScalarRepl/memcpy-align.ll >> >> Modified: llvm/trunk/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll?rev=106029&r1=106028&r2=106029&view=diff >> ============================================================================== >> --- llvm/trunk/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll (original) >> +++ llvm/trunk/test/CodeGen/ARM/2009-08-04-RegScavengerAssert-2.ll Tue Jun 15 14:04:29 2010 >> @@ -4,7 +4,7 @@ >> target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64" >> target triple = "armv6-elf" >> >> -define arm_aapcscc i32 @file_read_actor(i32* nocapture %desc, i32* %page, i32 %offset, i32 %size) nounwind optsize { >> +define i32 @file_read_actor(i32* nocapture %desc, i32* %page, i32 %offset, i32 %size) nounwind optsize { >> entry: >> br i1 undef, label %fault_in_pages_writeable.exit, label %bb5.i >> >> @@ -26,8 +26,8 @@ >> unreachable >> >> bb3: ; preds = %fault_in_pages_writeable.exit >> - %1 = tail call arm_aapcscc i32 @__copy_to_user(i8* undef, i8* undef, i32 undef) nounwind ; [#uses=0] >> + %1 = tail call i32 @__copy_to_user(i8* undef, i8* undef, i32 undef) nounwind ; [#uses=0] >> unreachable >> } >> >> -declare arm_aapcscc i32 @__copy_to_user(i8*, i8*, i32) >> +declare i32 @__copy_to_user(i8*, i8*, i32) >> >> Modified: llvm/trunk/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll?rev=106029&r1=106028&r2=106029&view=diff >> ============================================================================== >> --- llvm/trunk/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll (original) >> +++ llvm/trunk/test/CodeGen/ARM/2009-08-04-RegScavengerAssert.ll Tue Jun 15 14:04:29 2010 >> @@ -1,7 +1,7 @@ >> ; RUN: llc < %s -mtriple=armv6-elf >> ; PR4528 >> >> -define arm_aapcscc i32 @file_read_actor(i32 %desc, i32 %page, i32 %offset, i32 %size) nounwind optsize { >> +define i32 @file_read_actor(i32 %desc, i32 %page, i32 %offset, i32 %size) nounwind optsize { >> entry: >> br i1 undef, label %fault_in_pages_writeable.exit, label %bb5.i >> >> @@ -18,8 +18,8 @@ >> unreachable >> >> bb3: ; preds = %fault_in_pages_writeable.exit >> - %2 = tail call arm_aapcscc i32 @__copy_to_user(i8* undef, i8* undef, i32 undef) nounwind ; [#uses=0] >> + %2 = tail call i32 @__copy_to_user(i8* undef, i8* undef, i32 undef) nounwind ; [#uses=0] >> unreachable >> } >> >> -declare arm_aapcscc i32 @__copy_to_user(i8*, i8*, i32) >> +declare i32 @__copy_to_user(i8*, i8*, i32) >> >> Modified: llvm/trunk/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll?rev=106029&r1=106028&r2=106029&view=diff >> ============================================================================== >> --- llvm/trunk/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll (original) >> +++ llvm/trunk/test/CodeGen/ARM/2009-08-15-RegScavenger-EarlyClobber.ll Tue Jun 15 14:04:29 2010 >> @@ -6,7 +6,7 @@ >> %struct.device_dma_parameters = type { i32, i32 } >> %struct.iovec = type { i8*, i32 } >> >> -define arm_aapcscc i32 @generic_segment_checks(%struct.iovec* nocapture %iov, i32* nocapture %nr_segs, i32* nocapture %count, i32 %access_flags) nounwind optsize { >> +define i32 @generic_segment_checks(%struct.iovec* nocapture %iov, i32* nocapture %nr_segs, i32* nocapture %count, i32 %access_flags) nounwind optsize { >> entry: >> br label %bb8 >> >> >> Modified: llvm/trunk/test/CodeGen/ARM/2009-08-15-RegScavengerAssert.ll >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-08-15-RegScavengerAssert.ll?rev=106029&r1=106028&r2=106029&view=diff >> ============================================================================== >> --- llvm/trunk/test/CodeGen/ARM/2009-08-15-RegScavengerAssert.ll (original) >> +++ llvm/trunk/test/CodeGen/ARM/2009-08-15-RegScavengerAssert.ll Tue Jun 15 14:04:29 2010 >> @@ -1,10 +1,10 @@ >> ; RUN: llc < %s -march=arm >> ; PR4716 >> >> -define arm_aapcscc void @_start() nounwind naked { >> +define void @_start() nounwind naked { >> entry: >> - tail call arm_aapcscc void @exit(i32 undef) noreturn nounwind >> + tail call void @exit(i32 undef) noreturn nounwind >> unreachable >> } >> >> -declare arm_aapcscc void @exit(i32) noreturn nounwind >> +declare void @exit(i32) noreturn nounwind >> >> Modified: llvm/trunk/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll?rev=106029&r1=106028&r2=106029&view=diff >> ============================================================================== >> --- llvm/trunk/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll (original) >> +++ llvm/trunk/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll Tue Jun 15 14:04:29 2010 >> @@ -3,7 +3,7 @@ >> >> %0 = type { double, double } >> >> -define arm_aapcscc void @foo(%0* noalias nocapture sret %agg.result, double %x.0, double %y.0) nounwind { >> +define void @foo(%0* noalias nocapture sret %agg.result, double %x.0, double %y.0) nounwind { >> ; CHECK: foo: >> ; CHECK: bl __adddf3 >> ; CHECK-NOT: strd >> >> Modified: llvm/trunk/test/CodeGen/ARM/2009-10-27-double-align.ll >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-10-27-double-align.ll?rev=106029&r1=106028&r2=106029&view=diff >> ============================================================================== >> --- llvm/trunk/test/CodeGen/ARM/2009-10-27-double-align.ll (original) >> +++ llvm/trunk/test/CodeGen/ARM/2009-10-27-double-align.ll Tue Jun 15 14:04:29 2010 >> @@ -2,13 +2,13 @@ >> >> @.str = private constant [1 x i8] zeroinitializer, align 1 >> >> -define arm_aapcscc void @g() { >> +define void @g() { >> entry: >> ;CHECK: [sp, #8] >> ;CHECK: [sp, #12] >> ;CHECK: [sp] >> - tail call arm_aapcscc void (i8*, ...)* @f(i8* getelementptr ([1 x i8]* @.str, i32 0, i32 0), i32 1, double 2.000000e+00, i32 3, double 4.000000e+00) >> + tail call void (i8*, ...)* @f(i8* getelementptr ([1 x i8]* @.str, i32 0, i32 0), i32 1, double 2.000000e+00, i32 3, double 4.000000e+00) >> ret void >> } >> >> -declare arm_aapcscc void @f(i8*, ...) >> +declare void @f(i8*, ...) >> >> Modified: llvm/trunk/test/CodeGen/ARM/arm-frameaddr.ll >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/arm-frameaddr.ll?rev=106029&r1=106028&r2=106029&view=diff >> ============================================================================== >> --- llvm/trunk/test/CodeGen/ARM/arm-frameaddr.ll (original) >> +++ llvm/trunk/test/CodeGen/ARM/arm-frameaddr.ll Tue Jun 15 14:04:29 2010 >> @@ -3,7 +3,7 @@ >> ; PR4344 >> ; PR4416 >> >> -define arm_aapcscc i8* @t() nounwind { >> +define i8* @t() nounwind { >> entry: >> ; DARWIN: t: >> ; DARWIN: mov r0, r7 >> >> Modified: llvm/trunk/test/CodeGen/ARM/armv4.ll >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/armv4.ll?rev=106029&r1=106028&r2=106029&view=diff >> ============================================================================== >> --- llvm/trunk/test/CodeGen/ARM/armv4.ll (original) >> +++ llvm/trunk/test/CodeGen/ARM/armv4.ll Tue Jun 15 14:04:29 2010 >> @@ -5,7 +5,7 @@ >> ; RUN: llc < %s -mtriple=armv4-unknown-eabi | FileCheck %s -check-prefix=ARM >> ; RUN: llc < %s -mtriple=armv4t-unknown-eabi | FileCheck %s -check-prefix=THUMB >> >> -define arm_aapcscc i32 @test(i32 %a) nounwind readnone { >> +define i32 @test(i32 %a) nounwind readnone { >> entry: >> ; ARM: mov pc >> ; THUMB: bx >> >> Modified: llvm/trunk/test/CodeGen/Thumb2/2009-08-04-CoalescerAssert.ll >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-08-04-CoalescerAssert.ll?rev=106029&r1=106028&r2=106029&view=diff >> ============================================================================== >> --- llvm/trunk/test/CodeGen/Thumb2/2009-08-04-CoalescerAssert.ll (original) >> +++ llvm/trunk/test/CodeGen/Thumb2/2009-08-04-CoalescerAssert.ll Tue Jun 15 14:04:29 2010 >> @@ -5,7 +5,7 @@ >> %struct._IO_marker = type { %struct._IO_marker*, %struct.FILE*, i32 } >> @.str2 = external constant [30 x i8], align 1 ; <[30 x i8]*> [#uses=1] >> >> -define arm_aapcscc i32 @__mf_heuristic_check(i32 %ptr, i32 %ptr_high) nounwind { >> +define i32 @__mf_heuristic_check(i32 %ptr, i32 %ptr_high) nounwind { >> entry: >> br i1 undef, label %bb1, label %bb >> >> @@ -17,7 +17,7 @@ >> >> bb2: ; preds = %bb1 >> %0 = call i8* @llvm.frameaddress(i32 0) ; [#uses=1] >> - %1 = call arm_aapcscc i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* noalias undef, i8* noalias getelementptr ([30 x i8]* @.str2, i32 0, i32 0), i8* %0, i8* null) nounwind ; [#uses=0] >> + %1 = call i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* noalias undef, i8* noalias getelementptr ([30 x i8]* @.str2, i32 0, i32 0), i8* %0, i8* null) nounwind ; [#uses=0] >> unreachable >> >> bb9: ; preds = %bb1 >> @@ -26,4 +26,4 @@ >> >> declare i8* @llvm.frameaddress(i32) nounwind readnone >> >> -declare arm_aapcscc i32 @fprintf(%struct.FILE* noalias nocapture, i8* noalias nocapture, ...) nounwind >> +declare i32 @fprintf(%struct.FILE* noalias nocapture, i8* noalias nocapture, ...) nounwind >> >> Modified: llvm/trunk/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll?rev=106029&r1=106028&r2=106029&view=diff >> ============================================================================== >> --- llvm/trunk/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll (original) >> +++ llvm/trunk/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll Tue Jun 15 14:04:29 2010 >> @@ -2,12 +2,12 @@ >> ; PR4659 >> ; PR4682 >> >> -define hidden arm_aapcscc i32 @__gcov_execlp(i8* %path, i8* %arg, ...) nounwind { >> +define hidden i32 @__gcov_execlp(i8* %path, i8* %arg, ...) nounwind { >> entry: >> ; CHECK: __gcov_execlp: >> ; CHECK: mov sp, r7 >> ; CHECK: sub sp, #4 >> - call arm_aapcscc void @__gcov_flush() nounwind >> + call void @__gcov_flush() nounwind >> br i1 undef, label %bb5, label %bb >> >> bb: ; preds = %bb, %entry >> @@ -15,10 +15,10 @@ >> >> bb5: ; preds = %bb, %entry >> %0 = alloca i8*, i32 undef, align 4 ; [#uses=1] >> - %1 = call arm_aapcscc i32 @execvp(i8* %path, i8** %0) nounwind ; [#uses=1] >> + %1 = call i32 @execvp(i8* %path, i8** %0) nounwind ; [#uses=1] >> ret i32 %1 >> } >> >> -declare hidden arm_aapcscc void @__gcov_flush() >> +declare hidden void @__gcov_flush() >> >> -declare arm_aapcscc i32 @execvp(i8*, i8**) nounwind >> +declare i32 @execvp(i8*, i8**) nounwind >> >> Modified: llvm/trunk/test/CodeGen/Thumb2/2009-08-08-ScavengerAssert.ll >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-08-08-ScavengerAssert.ll?rev=106029&r1=106028&r2=106029&view=diff >> ============================================================================== >> --- llvm/trunk/test/CodeGen/Thumb2/2009-08-08-ScavengerAssert.ll (original) >> +++ llvm/trunk/test/CodeGen/Thumb2/2009-08-08-ScavengerAssert.ll Tue Jun 15 14:04:29 2010 >> @@ -3,7 +3,7 @@ >> >> @g_d = external global double ; [#uses=1] >> >> -define arm_aapcscc void @foo(float %yIncr) { >> +define void @foo(float %yIncr) { >> entry: >> br i1 undef, label %bb, label %bb4 >> >> >> Modified: llvm/trunk/test/Transforms/ScalarRepl/memcpy-align.ll >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ScalarRepl/memcpy-align.ll?rev=106029&r1=106028&r2=106029&view=diff >> ============================================================================== >> --- llvm/trunk/test/Transforms/ScalarRepl/memcpy-align.ll (original) >> +++ llvm/trunk/test/Transforms/ScalarRepl/memcpy-align.ll Tue Jun 15 14:04:29 2010 >> @@ -9,7 +9,7 @@ >> >> @c = external global %0 ; <%0*> [#uses=1] >> >> -define arm_aapcscc void @good() nounwind { >> +define void @good() nounwind { >> entry: >> %x0 = alloca %struct.anon, align 4 ; <%struct.anon*> [#uses=2] >> %tmp = bitcast %struct.anon* %x0 to i8* ; [#uses=1] >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From criswell at uiuc.edu Tue Jun 15 15:53:10 2010 From: criswell at uiuc.edu (John Criswell) Date: Tue, 15 Jun 2010 20:53:10 -0000 Subject: [llvm-commits] [poolalloc] r106042 - in /poolalloc/trunk: lib/PoolAllocate/TransformFunctionBody.cpp test/Makefile Message-ID: <20100615205310.600732A6C12C@llvm.org> Author: criswell Date: Tue Jun 15 15:53:10 2010 New Revision: 106042 URL: http://llvm.org/viewvc/llvm-project?rev=106042&view=rev Log: Added initial support for handling calls to the malloc() and free() functions. The malloc and free instructions don't exist anymore. Modified: poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp poolalloc/trunk/test/Makefile Modified: poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp?rev=106042&r1=106041&r2=106042&view=diff ============================================================================== --- poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp (original) +++ poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp Tue Jun 15 15:53:10 2010 @@ -73,11 +73,13 @@ void visitInstruction(Instruction &I); //void visitMallocInst(MallocInst &MI); void visitAllocaInst(AllocaInst &MI); + void visitMallocCall(CallSite & CS); void visitCallocCall(CallSite CS); void visitReallocCall(CallSite CS); void visitMemAlignCall(CallSite CS); void visitStrdupCall(CallSite CS); //void visitFreeInst(FreeInst &FI); + void visitFreeCall(CallSite &CS); void visitCallSite(CallSite &CS); void visitCallInst(CallInst &CI) { CallSite CS(&CI); @@ -277,12 +279,35 @@ return; } - -Instruction *FuncTransform::InsertPoolFreeInstr(Value *Arg, Instruction *Where){ +// +// Method: InsertPoolFreeInstr() +// +// Description: +// Insert a call to poolfree() at the specified point to free the specified +// value. +// +// Inputs: +// Arg - The value that should be freed by the call to poolfree(). +// Where - The instruction before which the poolfree() call should be +// inserted. +// +// Return value: +// NULL - No call to poolfree() was inserted. +// Otherwise, a pointer to the call instruction that calls poolfree() will be +// returned. +// +Instruction * +FuncTransform::InsertPoolFreeInstr (Value *Arg, Instruction *Where){ + // + // Attempt to get the pool handle of the specified value. If there is no + // pool handle, then just return NULL. + // Value *PH = getPoolHandle(Arg); // Get the pool handle for this DSNode... if (PH == 0 || isa(PH)) return 0; - // Insert a cast and a call to poolfree... + // + // Cast the pointer to be freed to a void pointer type if necessary. + // Value *Casted = Arg; if (Arg->getType() != PointerType::getUnqual(Type::getInt8Ty(Arg->getContext()))) { Casted = CastInst::CreatePointerCast(Arg, PointerType::getUnqual(Type::getInt8Ty(Arg->getContext())), @@ -290,6 +315,9 @@ G->getScalarMap()[Casted] = G->getScalarMap()[Arg]; } + // + // Insert a call to poolfree() + // Value* Opts[2] = {PH, Casted}; CallInst *FreeI = CallInst::Create(PAInfo.PoolFree, Opts, Opts + 2, "", Where); AddPoolUse(*FreeI, PH, PoolFrees); @@ -315,6 +343,53 @@ } #endif +void +FuncTransform::visitFreeCall (CallSite & CS) { + // + // Replace the call to the free() function with a call to poolfree(). + // + Instruction * InsertPt = CS.getInstruction(); + if (Instruction *I = InsertPoolFreeInstr (CS.getArgument(0), InsertPt)) { + // Delete the now obsolete free instruction... + InsertPt->getParent()->getInstList().erase(InsertPt); + + // Update the NewToOldValueMap if this is a clone + if (!FI.NewToOldValueMap.empty()) { + std::map::iterator II = + FI.NewToOldValueMap.find(InsertPt); + assert(II != FI.NewToOldValueMap.end() && + "free call not found in clone?"); + FI.NewToOldValueMap.insert(std::make_pair(I, II->second)); + FI.NewToOldValueMap.erase(II); + } + } +} + +void +FuncTransform::visitMallocCall(CallSite &CS) { + // + // Get the instruction to which the call site refers + // + Instruction * MI = CS.getInstruction(); + + // + // Get the pool handle for the node that this contributes to... + // + Value *PH = getPoolHandle(MI); + if (PH == 0 || isa(PH)) return; + + // + // Find the size of the allocation. + // + Value *AllocSize = CS.getArgument(0); + + // + // Transform the allocation site to use poolalloc(). + // + TransformAllocationInstr(MI, AllocSize); +} + + void FuncTransform::visitCallocCall(CallSite CS) { TargetData& TD = PAInfo.getAnalysis(); const Type* Int8Type = Type::getInt8Ty(CS.getInstruction()->getContext()); @@ -570,7 +645,13 @@ // If this function is one of the memory manipulating functions built into // libc, emulate it with pool calls as appropriate. if (CF && CF->isDeclaration()) { - if (CF->getName() == "calloc") { + if (CF->getName() == "free") { + visitFreeCall(CS); + return; + } else if (CF->getName() == "malloc") { + visitMallocCall(CS); + return; + } else if (CF->getName() == "calloc") { visitCallocCall(CS); return; } else if (CF->getName() == "realloc") { Modified: poolalloc/trunk/test/Makefile URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/Makefile?rev=106042&r1=106041&r2=106042&view=diff ============================================================================== --- poolalloc/trunk/test/Makefile (original) +++ poolalloc/trunk/test/Makefile Tue Jun 15 15:53:10 2010 @@ -37,13 +37,15 @@ NORMAL_PROBLEM_SIZE_DIRS := \ - MultiSource/Benchmarks/Olden/bisort \ - #MultiSource/Benchmarks/Olden/bh \ + External/SPEC/CINT2000/175.vpr \ #External/SPEC/CINT2000 \ + #External/SPEC/CINT2000/181.mcf \ + #External/SPEC/CINT2000/186.crafty \ + #MultiSource/Benchmarks/Olden \ + #MultiSource/Benchmarks/Olden/bh \ #External/FPGrowth \ #External/Namd \ #External/Povray \ - #MultiSource/Benchmarks/Olden \ #MultiSource/Benchmarks/SciMark2-C/scimark2 \ #External/SPEC/CINT2000/164.gzip \ #External/SPEC/CINT2000/175.vpr \ From bob.wilson at apple.com Tue Jun 15 15:55:08 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 15 Jun 2010 13:55:08 -0700 Subject: [llvm-commits] [patch] Remove arm_aapcscc from some tests In-Reply-To: References: Message-ID: <6BE997EF-5C55-46FB-B555-110D511CD8AB@apple.com> On Jun 15, 2010, at 11:17 AM, Rafael Espindola wrote: > Discussing PR7357 over IRC, Nick suggested that the best fix would be > to change simplify-libcalls to not modify calls with non-default > calling conventions. This looks reasonable, but to do that we have to > change the default ARM calling convention to the default (.i.e "") :-) > > The attached patch is a first step in that direction. It just updates > the tests to use "" instead of arm_aapcscc. I will do the same with > arm_apcscc and then change llvm-gcc and clang to use "" for the > default. Replying to a discussion on IRC.... Anton says that non-linux targets, e.g., bare-metal targets, should also use the AAPCS ABI. That conflicts with both llvm-gcc and the llvm backend. llvm-gcc defines ARM_DEFAULT_ABI to ARM_ABI_APCS. That is overridden in linux-eabi.h and bpabi.h but neither of those are used for bare-metal targets. The llvm backend defaults TargetABI to ARM_ABI_APCS, and that is overridden in ARMSubtarget.cpp only when the target triple contains the string "eabi". So, unless I'm totally missing something, bare-metal targets are currently defaulting to APCS. From clattner at apple.com Tue Jun 15 15:56:15 2010 From: clattner at apple.com (Chris Lattner) Date: Tue, 15 Jun 2010 13:56:15 -0700 Subject: [llvm-commits] [LLVMbugs] [Bug 7322] ms vcpp build warnings In-Reply-To: References: <20100614203927.C1E7A2A6C12C@llvm.org> <4C1791A0.9030604@andric.com> <9B2F24FF-14A8-4EC2-B462-429E45E8C8EC@apple.com> Message-ID: On Jun 15, 2010, at 12:45 PM, nate begeman wrote: > Sure, sorry, I seemed to recall shifts implicitly promoting to int, but maybe that's in C and not C++, will cast. They do promote to int, it just causes warnings with some compilers. -Chris > > Nate > > On Jun 15, 2010, at 12:05 PM, Chris Lattner wrote: > >> Nate, can you change these to use "nElts << (int)quad" or something? >> >> -Chris >> >> On Jun 15, 2010, at 7:43 AM, Dimitry Andric wrote: >> >>> On 2010-06-14 22:39, bugzilla-daemon at llvm.org wrote: >>>> --- Comment #1 from Chris Lattner 2010-06-14 15:39:27 CDT --- >>>> there are a bunch of build warnings with MSVC. If you're interested in helping >>>> with this, please send patches to llvm-commits, thanks! >>> >>> What I see quite often with VC++ is this warning: >>> >>> .\NeonEmitter.cpp(529) : warning C4804: '<<' : unsafe use of type 'bool' in operation >>> >>> which comes from bool variables used as shift count, e.g: >>> >>> bool dummy, quad = false; >>> ... >>> b = Duplicate(nElts << quad, typestr, "b"); >>> >>> I'm not sure if this is unnecessarily paranoid of VC++, as the standard >>> seems to imply it should be no problem, if I read it correctly: >>> >>> [conv.prom] >>> 4. An rvalue of type bool can be converted to an rvalue of type int, >>> with false becoming zero and true becoming one. >>> >>> and [conv.integral]: >>> >>> 4. If the destination type is bool, see 4.12. If the source type is >>> bool, the value false is converted to zero and the value true is >>> converted to one. >>> >>> In short, is it worthwhile to appease VC++ here, by using an int or >>> unsigned instead, or should we just stash in a pragma to disable this >>> particular warning? >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> > From bob.wilson at apple.com Tue Jun 15 15:57:23 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 15 Jun 2010 13:57:23 -0700 Subject: [llvm-commits] [patch] Update llvm-gcc to produce "" for the default calling convention on ARM In-Reply-To: References: Message-ID: <76A0798C-9AB8-43E8-99C1-7AFE618CEBEB@apple.com> On Jun 15, 2010, at 1:25 PM, Rafael Espindola wrote: > With the attached patch llvm-gcc produces "" as the calling convention > by default. I manually checked that arm_aapcs_vfpcc is produced when > -mfloat-abi=hard is used. As far as I understand this, you want to change llvm-gcc and clang to set the CC to "" when it matches the backend's default for the target. This patch seems insufficient. You'll need to check to see what the current target is set to and compare the current ABI against the default for that target. From stoklund at 2pi.dk Tue Jun 15 16:16:35 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 15 Jun 2010 21:16:35 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r106044 - /llvm-gcc-4.2/trunk/gcc/llvm-linker-hack.cpp Message-ID: <20100615211635.E31272A6C12C@llvm.org> Author: stoklund Date: Tue Jun 15 16:16:35 2010 New Revision: 106044 URL: http://llvm.org/viewvc/llvm-project?rev=106044&view=rev Log: Don't pull in register allocator factory functions. They are no longer called directly. Modified: llvm-gcc-4.2/trunk/gcc/llvm-linker-hack.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-linker-hack.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-linker-hack.cpp?rev=106044&r1=106043&r2=106044&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-linker-hack.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-linker-hack.cpp Tue Jun 15 16:16:35 2010 @@ -59,8 +59,6 @@ llvm::createCFGSimplificationPass(); llvm::createDefaultScheduler(NULL, llvm::CodeGenOpt::Default); - llvm::createLinearScanRegisterAllocator(); - llvm::createLocalRegisterAllocator(); llvm::createGVNPass(); llvm::createLoopRotatePass(); From rjmccall at apple.com Tue Jun 15 16:23:45 2010 From: rjmccall at apple.com (John McCall) Date: Tue, 15 Jun 2010 14:23:45 -0700 Subject: [llvm-commits] [PATCH] simplify-libcalls: fold strstr(a, b) == a -> strncmp(a, b, strlen(b)) == 0 In-Reply-To: <010C4722-CDD7-4C57-A170-FD9EAC525277@apple.com> References: <59C54A68-7761-44D2-B994-BA352C2B79C5@gmail.com> <010C4722-CDD7-4C57-A170-FD9EAC525277@apple.com> Message-ID: <0E9318E6-45EE-4F8D-B5E9-41FD619E60F6@apple.com> On Jun 15, 2010, at 12:03 PM, Chris Lattner wrote: > > On Jun 15, 2010, at 11:50 AM, Benjamin Kramer wrote: > >> This seems to be a common idiom to check the prefix of a string (lldb uses it) and it triggers O(n*m) behavior in most libc implementations. strncmp brings it down to O(m). >> >> I'm not sure if simplify-libcalls is the right place for this. The code basically works around the pass's infrastructure (skipping statistics etc.) > > This looks great to me. As a micro-micro-optimization, you could check to see if 'a' has a known length. If so, you could use strlen(a) instead since using strlen(a) or strlen(b) both work. It needs to be strlen(b). strstr("foo", "food") != "foo". John. From benny.kra at googlemail.com Tue Jun 15 16:34:25 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Tue, 15 Jun 2010 21:34:25 -0000 Subject: [llvm-commits] [llvm] r106047 - in /llvm/trunk: include/llvm/Transforms/Utils/BuildLibCalls.h lib/Transforms/Scalar/SimplifyLibCalls.cpp lib/Transforms/Utils/BuildLibCalls.cpp test/Transforms/SimplifyLibCalls/StrStr.ll Message-ID: <20100615213425.ABB272A6C12C@llvm.org> Author: d0k Date: Tue Jun 15 16:34:25 2010 New Revision: 106047 URL: http://llvm.org/viewvc/llvm-project?rev=106047&view=rev Log: simplify-libcalls: fold strstr(a, b) == a -> strncmp(a, b, strlen(b)) == 0 Modified: llvm/trunk/include/llvm/Transforms/Utils/BuildLibCalls.h llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp llvm/trunk/test/Transforms/SimplifyLibCalls/StrStr.ll Modified: llvm/trunk/include/llvm/Transforms/Utils/BuildLibCalls.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/Utils/BuildLibCalls.h?rev=106047&r1=106046&r2=106047&view=diff ============================================================================== --- llvm/trunk/include/llvm/Transforms/Utils/BuildLibCalls.h (original) +++ llvm/trunk/include/llvm/Transforms/Utils/BuildLibCalls.h Tue Jun 15 16:34:25 2010 @@ -34,6 +34,10 @@ /// and the return value has 'i8*' type. Value *EmitStrChr(Value *Ptr, char C, IRBuilder<> &B, const TargetData *TD); + /// EmitStrNCmp - Emit a call to the strncmp function to the builder. + Value *EmitStrNCmp(Value *Ptr1, Value *Ptr2, Value *Len, IRBuilder<> &B, + const TargetData *TD); + /// EmitStrCpy - Emit a call to the strcpy function to the builder, for the /// specified pointer arguments. Value *EmitStrCpy(Value *Dst, Value *Src, IRBuilder<> &B, Modified: llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp?rev=106047&r1=106046&r2=106047&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Tue Jun 15 16:34:25 2010 @@ -92,6 +92,20 @@ return true; } +/// IsOnlyUsedInEqualityComparison - Return true if it is only used in equality +/// comparisons with With. +static bool IsOnlyUsedInEqualityComparison(Value *V, Value *With) { + for (Value::use_iterator UI = V->use_begin(), E = V->use_end(); + UI != E; ++UI) { + if (ICmpInst *IC = dyn_cast(*UI)) + if (IC->isEquality() && IC->getOperand(1) == With) + continue; + // Unknown instruction. + return false; + } + return true; +} + //===----------------------------------------------------------------------===// // String and Memory LibCall Optimizations //===----------------------------------------------------------------------===// @@ -503,6 +517,23 @@ if (CI->getOperand(1) == CI->getOperand(2)) return B.CreateBitCast(CI->getOperand(1), CI->getType()); + // fold strstr(a, b) == a -> strncmp(a, b, strlen(b)) == 0 + if (TD && IsOnlyUsedInEqualityComparison(CI, CI->getOperand(1))) { + Value *StrLen = EmitStrLen(CI->getOperand(2), B, TD); + Value *StrNCmp = EmitStrNCmp(CI->getOperand(1), CI->getOperand(2), + StrLen, B, TD); + for (Value::use_iterator UI = CI->use_begin(), UE = CI->use_end(); + UI != UE; ) { + ICmpInst *Old = cast(UI++); + Value *Cmp = B.CreateICmp(Old->getPredicate(), StrNCmp, + ConstantInt::getNullValue(StrNCmp->getType()), + "cmp"); + Old->replaceAllUsesWith(Cmp); + Old->eraseFromParent(); + } + return CI; + } + // See if either input string is a constant string. std::string SearchStr, ToFindStr; bool HasStr1 = GetConstantStringInfo(CI->getOperand(1), SearchStr); Modified: llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp?rev=106047&r1=106046&r2=106047&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp Tue Jun 15 16:34:25 2010 @@ -69,6 +69,31 @@ return CI; } +/// EmitStrNCmp - Emit a call to the strncmp function to the builder. +Value *llvm::EmitStrNCmp(Value *Ptr1, Value *Ptr2, Value *Len, + IRBuilder<> &B, const TargetData *TD) { + Module *M = B.GetInsertBlock()->getParent()->getParent(); + AttributeWithIndex AWI[3]; + AWI[0] = AttributeWithIndex::get(1, Attribute::NoCapture); + AWI[1] = AttributeWithIndex::get(2, Attribute::NoCapture); + AWI[2] = AttributeWithIndex::get(~0u, Attribute::ReadOnly | + Attribute::NoUnwind); + + LLVMContext &Context = B.GetInsertBlock()->getContext(); + Value *StrNCmp = M->getOrInsertFunction("strncmp", AttrListPtr::get(AWI, 3), + B.getInt32Ty(), + B.getInt8PtrTy(), + B.getInt8PtrTy(), + TD->getIntPtrType(Context), NULL); + CallInst *CI = B.CreateCall3(StrNCmp, CastToCStr(Ptr1, B), + CastToCStr(Ptr2, B), Len, "strncmp"); + + if (const Function *F = dyn_cast(StrNCmp->stripPointerCasts())) + CI->setCallingConv(F->getCallingConv()); + + return CI; +} + /// EmitStrCpy - Emit a call to the strcpy function to the builder, for the /// specified pointer arguments. Value *llvm::EmitStrCpy(Value *Dst, Value *Src, IRBuilder<> &B, Modified: llvm/trunk/test/Transforms/SimplifyLibCalls/StrStr.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyLibCalls/StrStr.ll?rev=106047&r1=106046&r2=106047&view=diff ============================================================================== --- llvm/trunk/test/Transforms/SimplifyLibCalls/StrStr.ll (original) +++ llvm/trunk/test/Transforms/SimplifyLibCalls/StrStr.ll Tue Jun 15 16:34:25 2010 @@ -46,3 +46,15 @@ ; CHECK: @test4 ; CHECK: ret i8* %P } + +define i1 @test5(i8* %P, i8* %Q) nounwind readonly { +entry: + %call = tail call i8* @strstr(i8* %P, i8* %Q) nounwind ; [#uses=1] + %cmp = icmp eq i8* %call, %P + ret i1 %cmp +; CHECK: @test5 +; CHECK: [[LEN:%[a-z]+]] = call {{i[0-9]+}} @strlen(i8* %Q) +; CHECK: [[NCMP:%[a-z]+]] = call {{i[0-9]+}} @strncmp(i8* %P, i8* %Q, {{i[0-9]+}} [[LEN]]) +; CHECK: icmp eq {{i[0-9]+}} [[NCMP]], 0 +; CHECK: ret i1 +} From sabre at nondot.org Tue Jun 15 16:35:22 2010 From: sabre at nondot.org (Chris Lattner) Date: Tue, 15 Jun 2010 21:35:22 -0000 Subject: [llvm-commits] [llvm] r106048 - /llvm/trunk/Makefile.rules Message-ID: <20100615213522.ED0F82A6C12C@llvm.org> Author: lattner Date: Tue Jun 15 16:35:22 2010 New Revision: 106048 URL: http://llvm.org/viewvc/llvm-project?rev=106048&view=rev Log: fix PR7380: use 'test' instead of shell builtins. This improves portability to Solaris 10, which apparently doesn't support [ foo -ot bar ] Modified: llvm/trunk/Makefile.rules Modified: llvm/trunk/Makefile.rules URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=106048&r1=106047&r2=106048&view=diff ============================================================================== --- llvm/trunk/Makefile.rules (original) +++ llvm/trunk/Makefile.rules Tue Jun 15 16:35:22 2010 @@ -808,7 +808,7 @@ $(RecursiveTargets):: $(Verb) for dir in $(DIRS); do \ if ([ ! -f $$dir/Makefile ] || \ - [ $$dir/Makefile -ot $(PROJ_SRC_DIR)/$$dir/Makefile ]); then \ + test $$dir/Makefile -ot $(PROJ_SRC_DIR)/$$dir/Makefile ); then \ $(MKDIR) $$dir; \ $(CP) $(PROJ_SRC_DIR)/$$dir/Makefile $$dir/Makefile; \ fi; \ @@ -831,7 +831,7 @@ $(RecursiveTargets):: $(Verb) for dir in $(EXPERIMENTAL_DIRS); do \ if ([ ! -f $$dir/Makefile ] || \ - [ $$dir/Makefile -ot $(PROJ_SRC_DIR)/$$dir/Makefile ]); then \ + test $$dir/Makefile -ot $(PROJ_SRC_DIR)/$$dir/Makefile ); then \ $(MKDIR) $$dir; \ $(CP) $(PROJ_SRC_DIR)/$$dir/Makefile $$dir/Makefile; \ fi; \ @@ -866,8 +866,8 @@ $(ParallelTargets) : $(Verb) if ([ ! -f $(@D)/Makefile ] || \ - [ $(@D)/Makefile -ot \ - $(PROJ_SRC_DIR)/$(@D)/Makefile ]); then \ + test $(@D)/Makefile -ot \ + $(PROJ_SRC_DIR)/$(@D)/Makefile ); then \ $(MKDIR) $(@D); \ $(CP) $(PROJ_SRC_DIR)/$(@D)/Makefile $(@D)/Makefile; \ fi; \ @@ -887,7 +887,7 @@ $(Verb) for dir in $(OPTIONAL_DIRS); do \ if [ -d $(PROJ_SRC_DIR)/$$dir ]; then\ if ([ ! -f $$dir/Makefile ] || \ - [ $$dir/Makefile -ot $(PROJ_SRC_DIR)/$$dir/Makefile ]); then \ + test $$dir/Makefile -ot $(PROJ_SRC_DIR)/$$dir/Makefile ); then \ $(MKDIR) $$dir; \ $(CP) $(PROJ_SRC_DIR)/$$dir/Makefile $$dir/Makefile; \ fi; \ From dalej at apple.com Tue Jun 15 16:36:43 2010 From: dalej at apple.com (Dale Johannesen) Date: Tue, 15 Jun 2010 21:36:43 -0000 Subject: [llvm-commits] [llvm] r106049 - /llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Message-ID: <20100615213643.F20B22A6C12C@llvm.org> Author: johannes Date: Tue Jun 15 16:36:43 2010 New Revision: 106049 URL: http://llvm.org/viewvc/llvm-project?rev=106049&view=rev Log: Reapply 105986 with fix for bug pointed out by Jakob: flag argument to addReg is not the same format as flags attached to MachineOperand, although both have the same info. I don't think this actually mattered; the bootstrap failure did not reproduce on the next run anyway. Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=106049&r1=106048&r2=106049&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Tue Jun 15 16:36:43 2010 @@ -1279,9 +1279,11 @@ for (unsigned i = 0; i != 5; ++i) MIB.addOperand(MBBI->getOperand(i)); } else if (RetOpcode == X86::TCRETURNri64) { - BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64), JumpTarget.getReg()); + BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64)). + addReg(JumpTarget.getReg(), RegState::Kill); } else { - BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr), JumpTarget.getReg()); + BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr)). + addReg(JumpTarget.getReg(), RegState::Kill); } MachineInstr *NewMI = prior(MBBI); From clattner at apple.com Tue Jun 15 16:43:35 2010 From: clattner at apple.com (Chris Lattner) Date: Tue, 15 Jun 2010 14:43:35 -0700 Subject: [llvm-commits] [PATCH] simplify-libcalls: fold strstr(a, b) == a -> strncmp(a, b, strlen(b)) == 0 In-Reply-To: <0E9318E6-45EE-4F8D-B5E9-41FD619E60F6@apple.com> References: <59C54A68-7761-44D2-B994-BA352C2B79C5@gmail.com> <010C4722-CDD7-4C57-A170-FD9EAC525277@apple.com> <0E9318E6-45EE-4F8D-B5E9-41FD619E60F6@apple.com> Message-ID: <15D2722D-478D-43A7-99D6-66838F9C1E22@apple.com> On Jun 15, 2010, at 2:23 PM, John McCall wrote: > > On Jun 15, 2010, at 12:03 PM, Chris Lattner wrote: > >> >> On Jun 15, 2010, at 11:50 AM, Benjamin Kramer wrote: >> >>> This seems to be a common idiom to check the prefix of a string (lldb uses it) and it triggers O(n*m) behavior in most libc implementations. strncmp brings it down to O(m). >>> >>> I'm not sure if simplify-libcalls is the right place for this. The code basically works around the pass's infrastructure (skipping statistics etc.) >> >> This looks great to me. As a micro-micro-optimization, you could check to see if 'a' has a known length. If so, you could use strlen(a) instead since using strlen(a) or strlen(b) both work. > > It needs to be strlen(b). strstr("foo", "food") != "foo". Yep, he corrected me on irc. :) From benny.kra at googlemail.com Tue Jun 15 16:48:11 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Tue, 15 Jun 2010 23:48:11 +0200 Subject: [llvm-commits] [PATCH] simplify-libcalls: fold strstr(a, b) == a -> strncmp(a, b, strlen(b)) == 0 In-Reply-To: <15D2722D-478D-43A7-99D6-66838F9C1E22@apple.com> References: <59C54A68-7761-44D2-B994-BA352C2B79C5@gmail.com> <010C4722-CDD7-4C57-A170-FD9EAC525277@apple.com> <0E9318E6-45EE-4F8D-B5E9-41FD619E60F6@apple.com> <15D2722D-478D-43A7-99D6-66838F9C1E22@apple.com> Message-ID: On 15.06.2010, at 23:43, Chris Lattner wrote: > > On Jun 15, 2010, at 2:23 PM, John McCall wrote: > >> >> On Jun 15, 2010, at 12:03 PM, Chris Lattner wrote: >> >>> >>> On Jun 15, 2010, at 11:50 AM, Benjamin Kramer wrote: >>> >>>> This seems to be a common idiom to check the prefix of a string (lldb uses it) and it triggers O(n*m) behavior in most libc implementations. strncmp brings it down to O(m). >>>> >>>> I'm not sure if simplify-libcalls is the right place for this. The code basically works around the pass's infrastructure (skipping statistics etc.) >>> >>> This looks great to me. As a micro-micro-optimization, you could check to see if 'a' has a known length. If so, you could use strlen(a) instead since using strlen(a) or strlen(b) both work. >> >> It needs to be strlen(b). strstr("foo", "food") != "foo". > > Yep, he corrected me on irc. :) ? and landed the patch with some minor tweaks in r106047. From espindola at google.com Tue Jun 15 16:50:45 2010 From: espindola at google.com (Rafael Espindola) Date: Tue, 15 Jun 2010 17:50:45 -0400 Subject: [llvm-commits] [patch] Update llvm-gcc to produce "" for the default calling convention on ARM In-Reply-To: <76A0798C-9AB8-43E8-99C1-7AFE618CEBEB@apple.com> References: <76A0798C-9AB8-43E8-99C1-7AFE618CEBEB@apple.com> Message-ID: > As far as I understand this, you want to change llvm-gcc and clang to set the CC to "" when it matches the backend's default for the target. ?This patch seems insufficient. ?You'll need to check to see what the current target is set to and compare the current ABI against the default for that target. An updated patch is attached. With it and a gcc configured for arm-none-linux-gnueabi I get: *) no -mabi -> "" *) -mabi=aapcs -> "" *) -mcpu=cortex-a8 -> arm_apcscc *) -mfloat-abi=hard -> arm_aapcs_vfpcc Is it OK? Cheers, -- Rafael ?vila de Esp?ndola -------------- next part -------------- A non-text attachment was scrubbed... Name: llvm-gcc-cc.patch Type: text/x-patch Size: 1912 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100615/08ce618c/attachment.bin From stoklund at 2pi.dk Tue Jun 15 16:58:33 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 15 Jun 2010 21:58:33 -0000 Subject: [llvm-commits] [llvm] r106051 - in /llvm/trunk: docs/ include/llvm/CodeGen/ lib/CodeGen/ test/CodeGen/ARM/ test/CodeGen/Generic/ test/CodeGen/PowerPC/ test/CodeGen/Thumb/ test/CodeGen/X86/ Message-ID: <20100615215833.ED6BC2A6C12C@llvm.org> Author: stoklund Date: Tue Jun 15 16:58:33 2010 New Revision: 106051 URL: http://llvm.org/viewvc/llvm-project?rev=106051&view=rev Log: Remove the local register allocator. Please use the fast allocator instead. Removed: llvm/trunk/lib/CodeGen/RegAllocLocal.cpp llvm/trunk/test/CodeGen/X86/local-liveness.ll Modified: llvm/trunk/docs/CodeGenerator.html llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h llvm/trunk/include/llvm/CodeGen/Passes.h llvm/trunk/lib/CodeGen/CMakeLists.txt llvm/trunk/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll llvm/trunk/test/CodeGen/ARM/2008-02-29-RegAllocLocal.ll llvm/trunk/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll llvm/trunk/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll llvm/trunk/test/CodeGen/Generic/2006-09-02-LocalAllocCrash.ll llvm/trunk/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll llvm/trunk/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll llvm/trunk/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll llvm/trunk/test/CodeGen/PowerPC/2008-02-09-LocalRegAllocAssert.ll llvm/trunk/test/CodeGen/PowerPC/cr_spilling.ll llvm/trunk/test/CodeGen/Thumb/2010-01-15-local-alloc-spill-physical.ll llvm/trunk/test/CodeGen/X86/2008-01-16-FPStackifierAssert.ll llvm/trunk/test/CodeGen/X86/2008-02-22-LocalRegAllocBug.ll llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll llvm/trunk/test/CodeGen/X86/2008-05-28-LocalRegAllocBug.ll llvm/trunk/test/CodeGen/X86/2008-09-17-inline-asm-1.ll llvm/trunk/test/CodeGen/X86/2008-09-18-inline-asm-2.ll llvm/trunk/test/CodeGen/X86/2009-01-29-LocalRegAllocBug.ll llvm/trunk/test/CodeGen/X86/2009-04-14-IllegalRegs.ll llvm/trunk/test/CodeGen/X86/2009-04-24.ll llvm/trunk/test/CodeGen/X86/2010-04-30-LocalAlloc-LandingPad.ll llvm/trunk/test/CodeGen/X86/2010-05-05-LocalAllocEarlyClobber.ll llvm/trunk/test/CodeGen/X86/2010-05-06-LocalInlineAsmClobber.ll llvm/trunk/test/CodeGen/X86/fp-stack-O0-crash.ll llvm/trunk/test/CodeGen/X86/liveness-local-regalloc.ll llvm/trunk/test/CodeGen/X86/phys-reg-local-regalloc.ll Modified: llvm/trunk/docs/CodeGenerator.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CodeGenerator.html?rev=106051&r1=106050&r2=106051&view=diff ============================================================================== --- llvm/trunk/docs/CodeGenerator.html (original) +++ llvm/trunk/docs/CodeGenerator.html Tue Jun 15 16:58:33 2010 @@ -1594,22 +1594,22 @@ different register allocators:

    -
  • Simple — This is a very simple implementation that does not - keep values in registers across instructions. This register allocator - immediately spills every value right after it is computed, and reloads all - used operands from memory to temporary registers before each - instruction.
    • - -
  • Local — This register allocator is an improvement on the - Simple implementation. It allocates registers on a basic block - level, attempting to keep values in registers and reusing registers as - appropriate.
    • -
  • Linear Scan — The default allocator. This is the well-know linear scan register allocator. Whereas the Simple and Local algorithms use a direct mapping implementation technique, the Linear Scan implementation uses a spiller in order to place load and stores.
    • + +
  • Fast — This register allocator is the default for debug + builds. It allocates registers on a basic block level, attempting to keep + values in registers and reusing registers as appropriate.
    • + +
  • PBQP — A Partitioned Boolean Quadratic Programming (PBQP) + based register allocator. This allocator works by constructing a PBQP + problem representing the register allocation problem under consideration, + solving this using a PBQP solver, and mapping the solution back to a + register assignment.
    • +

The type of register allocator used in llc can be chosen with the @@ -1617,9 +1617,9 @@ 

-$ llc -regalloc=simple file.bc -o sp.s;
-$ llc -regalloc=local file.bc -o lc.s;
 $ llc -regalloc=linearscan file.bc -o ln.s;
+$ llc -regalloc=fast file.bc -o fa.s;
+$ llc -regalloc=pbqp file.bc -o pbqp.s;
Modified: llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h?rev=106051&r1=106050&r2=106051&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h (original) +++ llvm/trunk/include/llvm/CodeGen/LinkAllCodegenComponents.h Tue Jun 15 16:58:33 2010 @@ -33,7 +33,6 @@ (void) llvm::createDeadMachineInstructionElimPass(); - (void) llvm::createLocalRegisterAllocator(); (void) llvm::createFastRegisterAllocator(); (void) llvm::createLinearScanRegisterAllocator(); (void) llvm::createPBQPRegisterAllocator(); Modified: llvm/trunk/include/llvm/CodeGen/Passes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/Passes.h?rev=106051&r1=106050&r2=106051&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/Passes.h (original) +++ llvm/trunk/include/llvm/CodeGen/Passes.h Tue Jun 15 16:58:33 2010 @@ -90,12 +90,6 @@ /// FunctionPass *createRegisterAllocator(CodeGenOpt::Level OptLevel); - /// LocalRegisterAllocation Pass - This pass register allocates the input code - /// a basic block at a time, yielding code better than the simple register - /// allocator, but not as good as a global allocator. - /// - FunctionPass *createLocalRegisterAllocator(); - /// FastRegisterAllocation Pass - This pass register allocates as fast as /// possible. It is best suited for debug code where live ranges are short. /// Modified: llvm/trunk/lib/CodeGen/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CMakeLists.txt?rev=106051&r1=106050&r2=106051&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CMakeLists.txt (original) +++ llvm/trunk/lib/CodeGen/CMakeLists.txt Tue Jun 15 16:58:33 2010 @@ -52,7 +52,6 @@ PseudoSourceValue.cpp RegAllocFast.cpp RegAllocLinearScan.cpp - RegAllocLocal.cpp RegAllocPBQP.cpp RegisterCoalescer.cpp RegisterScavenging.cpp Removed: llvm/trunk/lib/CodeGen/RegAllocLocal.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLocal.cpp?rev=106050&view=auto ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocLocal.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocLocal.cpp (removed) @@ -1,1254 +0,0 @@ -//===-- RegAllocLocal.cpp - A BasicBlock generic register allocator -------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This register allocator allocates registers to a basic block at a time, -// attempting to keep values in registers and reusing registers as appropriate. -// -//===----------------------------------------------------------------------===// - -#define DEBUG_TYPE "regalloc" -#include "llvm/BasicBlock.h" -#include "llvm/CodeGen/MachineFunctionPass.h" -#include "llvm/CodeGen/MachineInstr.h" -#include "llvm/CodeGen/MachineFrameInfo.h" -#include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/CodeGen/Passes.h" -#include "llvm/CodeGen/RegAllocRegistry.h" -#include "llvm/Target/TargetInstrInfo.h" -#include "llvm/Target/TargetMachine.h" -#include "llvm/Support/CommandLine.h" -#include "llvm/Support/Debug.h" -#include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/raw_ostream.h" -#include "llvm/ADT/DenseMap.h" -#include "llvm/ADT/IndexedMap.h" -#include "llvm/ADT/SmallSet.h" -#include "llvm/ADT/SmallVector.h" -#include "llvm/ADT/Statistic.h" -#include "llvm/ADT/STLExtras.h" -#include -using namespace llvm; - -STATISTIC(NumStores, "Number of stores added"); -STATISTIC(NumLoads , "Number of loads added"); -STATISTIC(NumCopies, "Number of copies coalesced"); - -static RegisterRegAlloc - localRegAlloc("local", "local register allocator", - createLocalRegisterAllocator); - -namespace { - class RALocal : public MachineFunctionPass { - public: - static char ID; - RALocal() : MachineFunctionPass(&ID), StackSlotForVirtReg(-1) {} - private: - const TargetMachine *TM; - MachineFunction *MF; - MachineRegisterInfo *MRI; - const TargetRegisterInfo *TRI; - const TargetInstrInfo *TII; - - // StackSlotForVirtReg - Maps virtual regs to the frame index where these - // values are spilled. - IndexedMap StackSlotForVirtReg; - - // Virt2PhysRegMap - This map contains entries for each virtual register - // that is currently available in a physical register. - IndexedMap Virt2PhysRegMap; - - unsigned &getVirt2PhysRegMapSlot(unsigned VirtReg) { - return Virt2PhysRegMap[VirtReg]; - } - - // PhysRegsUsed - This array is effectively a map, containing entries for - // each physical register that currently has a value (ie, it is in - // Virt2PhysRegMap). The value mapped to is the virtual register - // corresponding to the physical register (the inverse of the - // Virt2PhysRegMap), or 0. The value is set to 0 if this register is pinned - // because it is used by a future instruction, and to -2 if it is not - // allocatable. If the entry for a physical register is -1, then the - // physical register is "not in the map". - // - std::vector PhysRegsUsed; - - // PhysRegsUseOrder - This contains a list of the physical registers that - // currently have a virtual register value in them. This list provides an - // ordering of registers, imposing a reallocation order. This list is only - // used if all registers are allocated and we have to spill one, in which - // case we spill the least recently used register. Entries at the front of - // the list are the least recently used registers, entries at the back are - // the most recently used. - // - std::vector PhysRegsUseOrder; - - // Virt2LastUseMap - This maps each virtual register to its last use - // (MachineInstr*, operand index pair). - IndexedMap, VirtReg2IndexFunctor> - Virt2LastUseMap; - - std::pair& getVirtRegLastUse(unsigned Reg) { - assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!"); - return Virt2LastUseMap[Reg]; - } - - // VirtRegModified - This bitset contains information about which virtual - // registers need to be spilled back to memory when their registers are - // scavenged. If a virtual register has simply been rematerialized, there - // is no reason to spill it to memory when we need the register back. - // - BitVector VirtRegModified; - - // UsedInMultipleBlocks - Tracks whether a particular register is used in - // more than one block. - BitVector UsedInMultipleBlocks; - - void markVirtRegModified(unsigned Reg, bool Val = true) { - assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!"); - Reg -= TargetRegisterInfo::FirstVirtualRegister; - if (Val) - VirtRegModified.set(Reg); - else - VirtRegModified.reset(Reg); - } - - bool isVirtRegModified(unsigned Reg) const { - assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!"); - assert(Reg - TargetRegisterInfo::FirstVirtualRegister < - VirtRegModified.size() && "Illegal virtual register!"); - return VirtRegModified[Reg - TargetRegisterInfo::FirstVirtualRegister]; - } - - void AddToPhysRegsUseOrder(unsigned Reg) { - std::vector::iterator It = - std::find(PhysRegsUseOrder.begin(), PhysRegsUseOrder.end(), Reg); - if (It != PhysRegsUseOrder.end()) - PhysRegsUseOrder.erase(It); - PhysRegsUseOrder.push_back(Reg); - } - - void MarkPhysRegRecentlyUsed(unsigned Reg) { - if (PhysRegsUseOrder.empty() || - PhysRegsUseOrder.back() == Reg) return; // Already most recently used - - for (unsigned i = PhysRegsUseOrder.size(); i != 0; --i) { - unsigned RegMatch = PhysRegsUseOrder[i-1]; // remove from middle - if (!areRegsEqual(Reg, RegMatch)) continue; - - PhysRegsUseOrder.erase(PhysRegsUseOrder.begin()+i-1); - // Add it to the end of the list - PhysRegsUseOrder.push_back(RegMatch); - if (RegMatch == Reg) - return; // Found an exact match, exit early - } - } - - public: - virtual const char *getPassName() const { - return "Local Register Allocator"; - } - - virtual void getAnalysisUsage(AnalysisUsage &AU) const { - AU.setPreservesCFG(); - AU.addRequiredID(PHIEliminationID); - AU.addRequiredID(TwoAddressInstructionPassID); - MachineFunctionPass::getAnalysisUsage(AU); - } - - private: - /// runOnMachineFunction - Register allocate the whole function - bool runOnMachineFunction(MachineFunction &Fn); - - /// AllocateBasicBlock - Register allocate the specified basic block. - void AllocateBasicBlock(MachineBasicBlock &MBB); - - - /// areRegsEqual - This method returns true if the specified registers are - /// related to each other. To do this, it checks to see if they are equal - /// or if the first register is in the alias set of the second register. - /// - bool areRegsEqual(unsigned R1, unsigned R2) const { - if (R1 == R2) return true; - for (const unsigned *AliasSet = TRI->getAliasSet(R2); - *AliasSet; ++AliasSet) { - if (*AliasSet == R1) return true; - } - return false; - } - - /// getStackSpaceFor - This returns the frame index of the specified virtual - /// register on the stack, allocating space if necessary. - int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC); - - /// removePhysReg - This method marks the specified physical register as no - /// longer being in use. - /// - void removePhysReg(unsigned PhysReg); - - void storeVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, - unsigned VirtReg, unsigned PhysReg, bool isKill); - - /// spillVirtReg - This method spills the value specified by PhysReg into - /// the virtual register slot specified by VirtReg. It then updates the RA - /// data structures to indicate the fact that PhysReg is now available. - /// - void spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, - unsigned VirtReg, unsigned PhysReg); - - /// spillPhysReg - This method spills the specified physical register into - /// the virtual register slot associated with it. If OnlyVirtRegs is set to - /// true, then the request is ignored if the physical register does not - /// contain a virtual register. - /// - void spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I, - unsigned PhysReg, bool OnlyVirtRegs = false); - - /// assignVirtToPhysReg - This method updates local state so that we know - /// that PhysReg is the proper container for VirtReg now. The physical - /// register must not be used for anything else when this is called. - /// - void assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg); - - /// isPhysRegAvailable - Return true if the specified physical register is - /// free and available for use. This also includes checking to see if - /// aliased registers are all free... - /// - bool isPhysRegAvailable(unsigned PhysReg) const; - - /// getFreeReg - Look to see if there is a free register available in the - /// specified register class. If not, return 0. - /// - unsigned getFreeReg(const TargetRegisterClass *RC); - - /// getReg - Find a physical register to hold the specified virtual - /// register. If all compatible physical registers are used, this method - /// spills the last used virtual register to the stack, and uses that - /// register. If NoFree is true, that means the caller knows there isn't - /// a free register, do not call getFreeReg(). - unsigned getReg(MachineBasicBlock &MBB, MachineInstr *MI, - unsigned VirtReg, bool NoFree = false); - - /// reloadVirtReg - This method transforms the specified virtual - /// register use to refer to a physical register. This method may do this - /// in one of several ways: if the register is available in a physical - /// register already, it uses that physical register. If the value is not - /// in a physical register, and if there are physical registers available, - /// it loads it into a register: PhysReg if that is an available physical - /// register, otherwise any physical register of the right class. - /// If register pressure is high, and it is possible, it tries to fold the - /// load of the virtual register into the instruction itself. It avoids - /// doing this if register pressure is low to improve the chance that - /// subsequent instructions can use the reloaded value. This method - /// returns the modified instruction. - /// - MachineInstr *reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI, - unsigned OpNum, SmallSet &RRegs, - unsigned PhysReg); - - /// ComputeLocalLiveness - Computes liveness of registers within a basic - /// block, setting the killed/dead flags as appropriate. - void ComputeLocalLiveness(MachineBasicBlock& MBB); - - void reloadPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I, - unsigned PhysReg); - }; - char RALocal::ID = 0; -} - -/// getStackSpaceFor - This allocates space for the specified virtual register -/// to be held on the stack. -int RALocal::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) { - // Find the location Reg would belong... - int SS = StackSlotForVirtReg[VirtReg]; - if (SS != -1) - return SS; // Already has space allocated? - - // Allocate a new stack object for this spill location... - int FrameIdx = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(), - RC->getAlignment()); - - // Assign the slot. - StackSlotForVirtReg[VirtReg] = FrameIdx; - return FrameIdx; -} - - -/// removePhysReg - This method marks the specified physical register as no -/// longer being in use. -/// -void RALocal::removePhysReg(unsigned PhysReg) { - PhysRegsUsed[PhysReg] = -1; // PhyReg no longer used - - std::vector::iterator It = - std::find(PhysRegsUseOrder.begin(), PhysRegsUseOrder.end(), PhysReg); - if (It != PhysRegsUseOrder.end()) - PhysRegsUseOrder.erase(It); -} - -/// storeVirtReg - Store a virtual register to its assigned stack slot. -void RALocal::storeVirtReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - unsigned VirtReg, unsigned PhysReg, - bool isKill) { - const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg); - int FrameIndex = getStackSpaceFor(VirtReg, RC); - DEBUG(dbgs() << " to stack slot #" << FrameIndex); - TII->storeRegToStackSlot(MBB, I, PhysReg, isKill, FrameIndex, RC, TRI); - ++NumStores; // Update statistics - - // Mark the spill instruction as last use if we're not killing the register. - if (!isKill) { - MachineInstr *Spill = llvm::prior(I); - int OpNum = Spill->findRegisterUseOperandIdx(PhysReg); - if (OpNum < 0) - getVirtRegLastUse(VirtReg) = std::make_pair((MachineInstr*)0, 0); - else - getVirtRegLastUse(VirtReg) = std::make_pair(Spill, OpNum); - } -} - -/// spillVirtReg - This method spills the value specified by PhysReg into the -/// virtual register slot specified by VirtReg. It then updates the RA data -/// structures to indicate the fact that PhysReg is now available. -/// -void RALocal::spillVirtReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - unsigned VirtReg, unsigned PhysReg) { - assert(VirtReg && "Spilling a physical register is illegal!" - " Must not have appropriate kill for the register or use exists beyond" - " the intended one."); - DEBUG(dbgs() << " Spilling register " << TRI->getName(PhysReg) - << " containing %reg" << VirtReg); - - if (!isVirtRegModified(VirtReg)) { - DEBUG(dbgs() << " which has not been modified, so no store necessary!"); - std::pair &LastUse = getVirtRegLastUse(VirtReg); - if (LastUse.first) - LastUse.first->getOperand(LastUse.second).setIsKill(); - } else { - // Otherwise, there is a virtual register corresponding to this physical - // register. We only need to spill it into its stack slot if it has been - // modified. - // If the instruction reads the register that's spilled, (e.g. this can - // happen if it is a move to a physical register), then the spill - // instruction is not a kill. - bool isKill = !(I != MBB.end() && I->readsRegister(PhysReg)); - storeVirtReg(MBB, I, VirtReg, PhysReg, isKill); - } - - getVirt2PhysRegMapSlot(VirtReg) = 0; // VirtReg no longer available - - DEBUG(dbgs() << '\n'); - removePhysReg(PhysReg); -} - - -/// spillPhysReg - This method spills the specified physical register into the -/// virtual register slot associated with it. If OnlyVirtRegs is set to true, -/// then the request is ignored if the physical register does not contain a -/// virtual register. -/// -void RALocal::spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I, - unsigned PhysReg, bool OnlyVirtRegs) { - if (PhysRegsUsed[PhysReg] != -1) { // Only spill it if it's used! - assert(PhysRegsUsed[PhysReg] != -2 && "Non allocable reg used!"); - if (PhysRegsUsed[PhysReg] || !OnlyVirtRegs) - spillVirtReg(MBB, I, PhysRegsUsed[PhysReg], PhysReg); - return; - } - - // If the selected register aliases any other registers, we must make - // sure that one of the aliases isn't alive. - for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg); - *AliasSet; ++AliasSet) { - if (PhysRegsUsed[*AliasSet] == -1 || // Spill aliased register. - PhysRegsUsed[*AliasSet] == -2) // If allocatable. - continue; - - if (PhysRegsUsed[*AliasSet]) - spillVirtReg(MBB, I, PhysRegsUsed[*AliasSet], *AliasSet); - } -} - - -/// assignVirtToPhysReg - This method updates local state so that we know -/// that PhysReg is the proper container for VirtReg now. The physical -/// register must not be used for anything else when this is called. -/// -void RALocal::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) { - assert(PhysRegsUsed[PhysReg] == -1 && "Phys reg already assigned!"); - // Update information to note the fact that this register was just used, and - // it holds VirtReg. - PhysRegsUsed[PhysReg] = VirtReg; - getVirt2PhysRegMapSlot(VirtReg) = PhysReg; - AddToPhysRegsUseOrder(PhysReg); // New use of PhysReg -} - - -/// isPhysRegAvailable - Return true if the specified physical register is free -/// and available for use. This also includes checking to see if aliased -/// registers are all free... -/// -bool RALocal::isPhysRegAvailable(unsigned PhysReg) const { - if (PhysRegsUsed[PhysReg] != -1) return false; - - // If the selected register aliases any other allocated registers, it is - // not free! - for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg); - *AliasSet; ++AliasSet) - if (PhysRegsUsed[*AliasSet] >= 0) // Aliased register in use? - return false; // Can't use this reg then. - return true; -} - - -/// getFreeReg - Look to see if there is a free register available in the -/// specified register class. If not, return 0. -/// -unsigned RALocal::getFreeReg(const TargetRegisterClass *RC) { - // Get iterators defining the range of registers that are valid to allocate in - // this class, which also specifies the preferred allocation order. - TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF); - TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF); - - for (; RI != RE; ++RI) - if (isPhysRegAvailable(*RI)) { // Is reg unused? - assert(*RI != 0 && "Cannot use register!"); - return *RI; // Found an unused register! - } - return 0; -} - - -/// getReg - Find a physical register to hold the specified virtual -/// register. If all compatible physical registers are used, this method spills -/// the last used virtual register to the stack, and uses that register. -/// -unsigned RALocal::getReg(MachineBasicBlock &MBB, MachineInstr *I, - unsigned VirtReg, bool NoFree) { - const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg); - - // First check to see if we have a free register of the requested type... - unsigned PhysReg = NoFree ? 0 : getFreeReg(RC); - - if (PhysReg != 0) { - // Assign the register. - assignVirtToPhysReg(VirtReg, PhysReg); - return PhysReg; - } - - // If we didn't find an unused register, scavenge one now! - assert(!PhysRegsUseOrder.empty() && "No allocated registers??"); - - // Loop over all of the preallocated registers from the least recently used - // to the most recently used. When we find one that is capable of holding - // our register, use it. - for (unsigned i = 0; PhysReg == 0; ++i) { - assert(i != PhysRegsUseOrder.size() && - "Couldn't find a register of the appropriate class!"); - - unsigned R = PhysRegsUseOrder[i]; - - // We can only use this register if it holds a virtual register (ie, it - // can be spilled). Do not use it if it is an explicitly allocated - // physical register! - assert(PhysRegsUsed[R] != -1 && - "PhysReg in PhysRegsUseOrder, but is not allocated?"); - if (PhysRegsUsed[R] && PhysRegsUsed[R] != -2) { - // If the current register is compatible, use it. - if (RC->contains(R)) { - PhysReg = R; - break; - } - - // If one of the registers aliased to the current register is - // compatible, use it. - for (const unsigned *AliasIt = TRI->getAliasSet(R); - *AliasIt; ++AliasIt) { - if (!RC->contains(*AliasIt)) continue; - - // If this is pinned down for some reason, don't use it. For - // example, if CL is pinned, and we run across CH, don't use - // CH as justification for using scavenging ECX (which will - // fail). - if (PhysRegsUsed[*AliasIt] == 0) continue; - - // Make sure the register is allocatable. Don't allocate SIL on - // x86-32. - if (PhysRegsUsed[*AliasIt] == -2) continue; - - PhysReg = *AliasIt; // Take an aliased register - break; - } - } - } - - assert(PhysReg && "Physical register not assigned!?!?"); - - // At this point PhysRegsUseOrder[i] is the least recently used register of - // compatible register class. Spill it to memory and reap its remains. - spillPhysReg(MBB, I, PhysReg); - - // Now that we know which register we need to assign this to, do it now! - assignVirtToPhysReg(VirtReg, PhysReg); - return PhysReg; -} - - -/// reloadVirtReg - This method transforms the specified virtual -/// register use to refer to a physical register. This method may do this in -/// one of several ways: if the register is available in a physical register -/// already, it uses that physical register. If the value is not in a physical -/// register, and if there are physical registers available, it loads it into a -/// register: PhysReg if that is an available physical register, otherwise any -/// register. If register pressure is high, and it is possible, it tries to -/// fold the load of the virtual register into the instruction itself. It -/// avoids doing this if register pressure is low to improve the chance that -/// subsequent instructions can use the reloaded value. This method returns -/// the modified instruction. -/// -MachineInstr *RALocal::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI, - unsigned OpNum, - SmallSet &ReloadedRegs, - unsigned PhysReg) { - unsigned VirtReg = MI->getOperand(OpNum).getReg(); - unsigned SubIdx = MI->getOperand(OpNum).getSubReg(); - - // If the virtual register is already available, just update the instruction - // and return. - if (unsigned PR = getVirt2PhysRegMapSlot(VirtReg)) { - if (SubIdx) { - PR = TRI->getSubReg(PR, SubIdx); - MI->getOperand(OpNum).setSubReg(0); - } - MI->getOperand(OpNum).setReg(PR); // Assign the input register - if (!MI->isDebugValue()) { - // Do not do these for DBG_VALUE as they can affect codegen. - MarkPhysRegRecentlyUsed(PR); // Already have this value available! - getVirtRegLastUse(VirtReg) = std::make_pair(MI, OpNum); - } - return MI; - } - - // Otherwise, we need to fold it into the current instruction, or reload it. - // If we have registers available to hold the value, use them. - const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg); - // If we already have a PhysReg (this happens when the instruction is a - // reg-to-reg copy with a PhysReg destination) use that. - if (!PhysReg || !TargetRegisterInfo::isPhysicalRegister(PhysReg) || - !isPhysRegAvailable(PhysReg)) - PhysReg = getFreeReg(RC); - int FrameIndex = getStackSpaceFor(VirtReg, RC); - - if (PhysReg) { // Register is available, allocate it! - assignVirtToPhysReg(VirtReg, PhysReg); - } else { // No registers available. - // Force some poor hapless value out of the register file to - // make room for the new register, and reload it. - PhysReg = getReg(MBB, MI, VirtReg, true); - } - - markVirtRegModified(VirtReg, false); // Note that this reg was just reloaded - - DEBUG(dbgs() << " Reloading %reg" << VirtReg << " into " - << TRI->getName(PhysReg) << "\n"); - - // Add move instruction(s) - TII->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC, TRI); - ++NumLoads; // Update statistics - - MF->getRegInfo().setPhysRegUsed(PhysReg); - // Assign the input register. - if (SubIdx) { - MI->getOperand(OpNum).setSubReg(0); - MI->getOperand(OpNum).setReg(TRI->getSubReg(PhysReg, SubIdx)); - } else - MI->getOperand(OpNum).setReg(PhysReg); // Assign the input register - getVirtRegLastUse(VirtReg) = std::make_pair(MI, OpNum); - - if (!ReloadedRegs.insert(PhysReg)) { - std::string msg; - raw_string_ostream Msg(msg); - Msg << "Ran out of registers during register allocation!"; - if (MI->isInlineAsm()) { - Msg << "\nPlease check your inline asm statement for invalid " - << "constraints:\n"; - MI->print(Msg, TM); - } - report_fatal_error(Msg.str()); - } - for (const unsigned *SubRegs = TRI->getSubRegisters(PhysReg); - *SubRegs; ++SubRegs) { - if (ReloadedRegs.insert(*SubRegs)) continue; - - std::string msg; - raw_string_ostream Msg(msg); - Msg << "Ran out of registers during register allocation!"; - if (MI->isInlineAsm()) { - Msg << "\nPlease check your inline asm statement for invalid " - << "constraints:\n"; - MI->print(Msg, TM); - } - report_fatal_error(Msg.str()); - } - - return MI; -} - -/// isReadModWriteImplicitKill - True if this is an implicit kill for a -/// read/mod/write register, i.e. update partial register. -static bool isReadModWriteImplicitKill(MachineInstr *MI, unsigned Reg) { - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { - MachineOperand &MO = MI->getOperand(i); - if (MO.isReg() && MO.getReg() == Reg && MO.isImplicit() && - MO.isDef() && !MO.isDead()) - return true; - } - return false; -} - -/// isReadModWriteImplicitDef - True if this is an implicit def for a -/// read/mod/write register, i.e. update partial register. -static bool isReadModWriteImplicitDef(MachineInstr *MI, unsigned Reg) { - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { - MachineOperand &MO = MI->getOperand(i); - if (MO.isReg() && MO.getReg() == Reg && MO.isImplicit() && - !MO.isDef() && MO.isKill()) - return true; - } - return false; -} - -// precedes - Helper function to determine with MachineInstr A -// precedes MachineInstr B within the same MBB. -static bool precedes(MachineBasicBlock::iterator A, - MachineBasicBlock::iterator B) { - if (A == B) - return false; - - MachineBasicBlock::iterator I = A->getParent()->begin(); - while (I != A->getParent()->end()) { - if (I == A) - return true; - else if (I == B) - return false; - - ++I; - } - - return false; -} - -/// ComputeLocalLiveness - Computes liveness of registers within a basic -/// block, setting the killed/dead flags as appropriate. -void RALocal::ComputeLocalLiveness(MachineBasicBlock& MBB) { - // Keep track of the most recently seen previous use or def of each reg, - // so that we can update them with dead/kill markers. - DenseMap > LastUseDef; - for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); - I != E; ++I) { - if (I->isDebugValue()) - continue; - - for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) { - MachineOperand &MO = I->getOperand(i); - // Uses don't trigger any flags, but we need to save - // them for later. Also, we have to process these - // _before_ processing the defs, since an instr - // uses regs before it defs them. - if (!MO.isReg() || !MO.getReg() || !MO.isUse()) - continue; - - // Ignore helpful kill flags from earlier passes. - MO.setIsKill(false); - - LastUseDef[MO.getReg()] = std::make_pair(I, i); - - if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) continue; - - const unsigned *Aliases = TRI->getAliasSet(MO.getReg()); - if (Aliases == 0) - continue; - - while (*Aliases) { - DenseMap >::iterator - alias = LastUseDef.find(*Aliases); - - if (alias != LastUseDef.end() && alias->second.first != I) - LastUseDef[*Aliases] = std::make_pair(I, i); - - ++Aliases; - } - } - - for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) { - MachineOperand &MO = I->getOperand(i); - // Defs others than 2-addr redefs _do_ trigger flag changes: - // - A def followed by a def is dead - // - A use followed by a def is a kill - if (!MO.isReg() || !MO.getReg() || !MO.isDef()) continue; - - unsigned SubIdx = MO.getSubReg(); - DenseMap >::iterator - last = LastUseDef.find(MO.getReg()); - if (last != LastUseDef.end()) { - // Check if this is a two address instruction. If so, then - // the def does not kill the use. - if (last->second.first == I && I->isRegTiedToUseOperand(i)) - continue; - - MachineOperand &lastUD = - last->second.first->getOperand(last->second.second); - if (SubIdx && lastUD.getSubReg() != SubIdx) - // Partial re-def, the last def is not dead. - // %reg1024:5 = - // %reg1024:6 = - // or - // %reg1024:5 = op %reg1024, 5 - continue; - - if (lastUD.isDef()) - lastUD.setIsDead(true); - else - lastUD.setIsKill(true); - } - - LastUseDef[MO.getReg()] = std::make_pair(I, i); - } - } - - // Live-out (of the function) registers contain return values of the function, - // so we need to make sure they are alive at return time. - MachineBasicBlock::iterator Ret = MBB.getFirstTerminator(); - bool BBEndsInReturn = (Ret != MBB.end() && Ret->getDesc().isReturn()); - - if (BBEndsInReturn) - for (MachineRegisterInfo::liveout_iterator - I = MF->getRegInfo().liveout_begin(), - E = MF->getRegInfo().liveout_end(); I != E; ++I) - if (!Ret->readsRegister(*I)) { - Ret->addOperand(MachineOperand::CreateReg(*I, false, true)); - LastUseDef[*I] = std::make_pair(Ret, Ret->getNumOperands()-1); - } - - // Finally, loop over the final use/def of each reg - // in the block and determine if it is dead. - for (DenseMap >::iterator - I = LastUseDef.begin(), E = LastUseDef.end(); I != E; ++I) { - MachineInstr *MI = I->second.first; - unsigned idx = I->second.second; - MachineOperand &MO = MI->getOperand(idx); - - bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(MO.getReg()); - - // A crude approximation of "live-out" calculation - bool usedOutsideBlock = isPhysReg ? false : - UsedInMultipleBlocks.test(MO.getReg() - - TargetRegisterInfo::FirstVirtualRegister); - - // If the machine BB ends in a return instruction, then the value isn't used - // outside of the BB. - if (!isPhysReg && (!usedOutsideBlock || BBEndsInReturn)) { - // DBG_VALUE complicates this: if the only refs of a register outside - // this block are DBG_VALUE, we can't keep the reg live just for that, - // as it will cause the reg to be spilled at the end of this block when - // it wouldn't have been otherwise. Nullify the DBG_VALUEs when that - // happens. - bool UsedByDebugValueOnly = false; - for (MachineRegisterInfo::reg_iterator UI = MRI->reg_begin(MO.getReg()), - UE = MRI->reg_end(); UI != UE; ++UI) { - // Two cases: - // - used in another block - // - used in the same block before it is defined (loop) - if (UI->getParent() == &MBB && - !(MO.isDef() && UI.getOperand().isUse() && precedes(&*UI, MI))) - continue; - - if (UI->isDebugValue()) { - UsedByDebugValueOnly = true; - continue; - } - - // A non-DBG_VALUE use means we can leave DBG_VALUE uses alone. - UsedInMultipleBlocks.set(MO.getReg() - - TargetRegisterInfo::FirstVirtualRegister); - usedOutsideBlock = true; - UsedByDebugValueOnly = false; - break; - } - - if (UsedByDebugValueOnly) - for (MachineRegisterInfo::reg_iterator UI = MRI->reg_begin(MO.getReg()), - UE = MRI->reg_end(); UI != UE; ++UI) - if (UI->isDebugValue() && - (UI->getParent() != &MBB || - (MO.isDef() && precedes(&*UI, MI)))) - UI.getOperand().setReg(0U); - } - - // Physical registers and those that are not live-out of the block are - // killed/dead at their last use/def within this block. - if (isPhysReg || !usedOutsideBlock || BBEndsInReturn) { - if (MO.isUse()) { - // Don't mark uses that are tied to defs as kills. - if (!MI->isRegTiedToDefOperand(idx)) - MO.setIsKill(true); - } else { - MO.setIsDead(true); - } - } - } -} - -void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) { - // loop over each instruction - MachineBasicBlock::iterator MII = MBB.begin(); - - DEBUG({ - const BasicBlock *LBB = MBB.getBasicBlock(); - if (LBB) - dbgs() << "\nStarting RegAlloc of BB: " << LBB->getName(); - }); - - // Add live-in registers as active. - for (MachineBasicBlock::livein_iterator I = MBB.livein_begin(), - E = MBB.livein_end(); I != E; ++I) { - unsigned Reg = *I; - MF->getRegInfo().setPhysRegUsed(Reg); - PhysRegsUsed[Reg] = 0; // It is free and reserved now - AddToPhysRegsUseOrder(Reg); - for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); - *SubRegs; ++SubRegs) { - if (PhysRegsUsed[*SubRegs] == -2) continue; - - AddToPhysRegsUseOrder(*SubRegs); - PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now - MF->getRegInfo().setPhysRegUsed(*SubRegs); - } - } - - ComputeLocalLiveness(MBB); - - // Otherwise, sequentially allocate each instruction in the MBB. - while (MII != MBB.end()) { - MachineInstr *MI = MII++; - const TargetInstrDesc &TID = MI->getDesc(); - DEBUG({ - dbgs() << "\nStarting RegAlloc of: " << *MI; - dbgs() << " Regs have values: "; - for (unsigned i = 0; i != TRI->getNumRegs(); ++i) - if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2) { - if (PhysRegsUsed[i] && isVirtRegModified(PhysRegsUsed[i])) - dbgs() << "*"; - dbgs() << "[" << TRI->getName(i) - << ",%reg" << PhysRegsUsed[i] << "] "; - } - dbgs() << '\n'; - }); - - // Determine whether this is a copy instruction. The cases where the - // source or destination are phys regs are handled specially. - unsigned SrcCopyReg, DstCopyReg, SrcCopySubReg, DstCopySubReg; - unsigned SrcCopyPhysReg = 0U; - bool isCopy = TII->isMoveInstr(*MI, SrcCopyReg, DstCopyReg, - SrcCopySubReg, DstCopySubReg) && - SrcCopySubReg == DstCopySubReg; - if (isCopy && TargetRegisterInfo::isVirtualRegister(SrcCopyReg)) - SrcCopyPhysReg = getVirt2PhysRegMapSlot(SrcCopyReg); - - // Loop over the implicit uses, making sure that they are at the head of the - // use order list, so they don't get reallocated. - if (TID.ImplicitUses) { - for (const unsigned *ImplicitUses = TID.ImplicitUses; - *ImplicitUses; ++ImplicitUses) - MarkPhysRegRecentlyUsed(*ImplicitUses); - } - - SmallVector Kills; - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { - MachineOperand &MO = MI->getOperand(i); - if (!MO.isReg() || !MO.isKill()) continue; - - if (!MO.isImplicit()) - Kills.push_back(MO.getReg()); - else if (!isReadModWriteImplicitKill(MI, MO.getReg())) - // These are extra physical register kills when a sub-register - // is defined (def of a sub-register is a read/mod/write of the - // larger registers). Ignore. - Kills.push_back(MO.getReg()); - } - - // If any physical regs are earlyclobber, spill any value they might - // have in them, then mark them unallocatable. - // If any virtual regs are earlyclobber, allocate them now (before - // freeing inputs that are killed). - if (MI->isInlineAsm()) { - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { - MachineOperand &MO = MI->getOperand(i); - if (!MO.isReg() || !MO.isDef() || !MO.isEarlyClobber() || - !MO.getReg()) - continue; - - if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) { - unsigned DestVirtReg = MO.getReg(); - unsigned DestPhysReg; - - // If DestVirtReg already has a value, use it. - if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg))) - DestPhysReg = getReg(MBB, MI, DestVirtReg); - MF->getRegInfo().setPhysRegUsed(DestPhysReg); - markVirtRegModified(DestVirtReg); - getVirtRegLastUse(DestVirtReg) = - std::make_pair((MachineInstr*)0, 0); - DEBUG(dbgs() << " Assigning " << TRI->getName(DestPhysReg) - << " to %reg" << DestVirtReg << "\n"); - if (unsigned DestSubIdx = MO.getSubReg()) { - MO.setSubReg(0); - DestPhysReg = TRI->getSubReg(DestPhysReg, DestSubIdx); - } - MO.setReg(DestPhysReg); // Assign the earlyclobber register - } else { - unsigned Reg = MO.getReg(); - if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP. - // These are extra physical register defs when a sub-register - // is defined (def of a sub-register is a read/mod/write of the - // larger registers). Ignore. - if (isReadModWriteImplicitDef(MI, MO.getReg())) continue; - - MF->getRegInfo().setPhysRegUsed(Reg); - spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in reg - PhysRegsUsed[Reg] = 0; // It is free and reserved now - AddToPhysRegsUseOrder(Reg); - - for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); - *SubRegs; ++SubRegs) { - if (PhysRegsUsed[*SubRegs] == -2) continue; - MF->getRegInfo().setPhysRegUsed(*SubRegs); - PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now - AddToPhysRegsUseOrder(*SubRegs); - } - } - } - } - - // If a DBG_VALUE says something is located in a spilled register, - // change the DBG_VALUE to be undef, which prevents the register - // from being reloaded here. Doing that would change the generated - // code, unless another use immediately follows this instruction. - if (MI->isDebugValue() && - MI->getNumOperands()==3 && MI->getOperand(0).isReg()) { - unsigned VirtReg = MI->getOperand(0).getReg(); - if (VirtReg && TargetRegisterInfo::isVirtualRegister(VirtReg) && - !getVirt2PhysRegMapSlot(VirtReg)) - MI->getOperand(0).setReg(0U); - } - - // Get the used operands into registers. This has the potential to spill - // incoming values if we are out of registers. Note that we completely - // ignore physical register uses here. We assume that if an explicit - // physical register is referenced by the instruction, that it is guaranteed - // to be live-in, or the input is badly hosed. - // - SmallSet ReloadedRegs; - for (unsigned i = 0; i != MI->getNumOperands(); ++i) { - MachineOperand &MO = MI->getOperand(i); - // here we are looking for only used operands (never def&use) - if (MO.isReg() && !MO.isDef() && MO.getReg() && !MO.isImplicit() && - TargetRegisterInfo::isVirtualRegister(MO.getReg())) - MI = reloadVirtReg(MBB, MI, i, ReloadedRegs, - isCopy ? DstCopyReg : 0); - } - - // If this instruction is the last user of this register, kill the - // value, freeing the register being used, so it doesn't need to be - // spilled to memory. - // - for (unsigned i = 0, e = Kills.size(); i != e; ++i) { - unsigned VirtReg = Kills[i]; - unsigned PhysReg = VirtReg; - if (TargetRegisterInfo::isVirtualRegister(VirtReg)) { - // If the virtual register was never materialized into a register, it - // might not be in the map, but it won't hurt to zero it out anyway. - unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg); - PhysReg = PhysRegSlot; - PhysRegSlot = 0; - } else if (PhysRegsUsed[PhysReg] == -2) { - // Unallocatable register dead, ignore. - continue; - } else { - assert((!PhysRegsUsed[PhysReg] || PhysRegsUsed[PhysReg] == -1) && - "Silently clearing a virtual register?"); - } - - if (!PhysReg) continue; - - DEBUG(dbgs() << " Last use of " << TRI->getName(PhysReg) - << "[%reg" << VirtReg <<"], removing it from live set\n"); - removePhysReg(PhysReg); - for (const unsigned *SubRegs = TRI->getSubRegisters(PhysReg); - *SubRegs; ++SubRegs) { - if (PhysRegsUsed[*SubRegs] != -2) { - DEBUG(dbgs() << " Last use of " - << TRI->getName(*SubRegs) << "[%reg" << VirtReg - <<"], removing it from live set\n"); - removePhysReg(*SubRegs); - } - } - } - - // Loop over all of the operands of the instruction, spilling registers that - // are defined, and marking explicit destinations in the PhysRegsUsed map. - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { - MachineOperand &MO = MI->getOperand(i); - if (!MO.isReg() || !MO.isDef() || MO.isImplicit() || !MO.getReg() || - MO.isEarlyClobber() || - !TargetRegisterInfo::isPhysicalRegister(MO.getReg())) - continue; - - unsigned Reg = MO.getReg(); - if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP. - // These are extra physical register defs when a sub-register - // is defined (def of a sub-register is a read/mod/write of the - // larger registers). Ignore. - if (isReadModWriteImplicitDef(MI, MO.getReg())) continue; - - MF->getRegInfo().setPhysRegUsed(Reg); - spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in reg - PhysRegsUsed[Reg] = 0; // It is free and reserved now - AddToPhysRegsUseOrder(Reg); - - for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); - *SubRegs; ++SubRegs) { - if (PhysRegsUsed[*SubRegs] == -2) continue; - - MF->getRegInfo().setPhysRegUsed(*SubRegs); - PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now - AddToPhysRegsUseOrder(*SubRegs); - } - } - - // Loop over the implicit defs, spilling them as well. - if (TID.ImplicitDefs) { - for (const unsigned *ImplicitDefs = TID.ImplicitDefs; - *ImplicitDefs; ++ImplicitDefs) { - unsigned Reg = *ImplicitDefs; - if (PhysRegsUsed[Reg] != -2) { - spillPhysReg(MBB, MI, Reg, true); - AddToPhysRegsUseOrder(Reg); - PhysRegsUsed[Reg] = 0; // It is free and reserved now - } - MF->getRegInfo().setPhysRegUsed(Reg); - for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); - *SubRegs; ++SubRegs) { - if (PhysRegsUsed[*SubRegs] == -2) continue; - - AddToPhysRegsUseOrder(*SubRegs); - PhysRegsUsed[*SubRegs] = 0; // It is free and reserved now - MF->getRegInfo().setPhysRegUsed(*SubRegs); - } - } - } - - SmallVector DeadDefs; - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { - MachineOperand &MO = MI->getOperand(i); - if (MO.isReg() && MO.isDead()) - DeadDefs.push_back(MO.getReg()); - } - - // Okay, we have allocated all of the source operands and spilled any values - // that would be destroyed by defs of this instruction. Loop over the - // explicit defs and assign them to a register, spilling incoming values if - // we need to scavenge a register. - // - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { - MachineOperand &MO = MI->getOperand(i); - if (!MO.isReg() || !MO.isDef() || !MO.getReg() || - MO.isEarlyClobber() || - !TargetRegisterInfo::isVirtualRegister(MO.getReg())) - continue; - - unsigned DestVirtReg = MO.getReg(); - unsigned DestPhysReg; - - // If DestVirtReg already has a value, use it. - if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg))) { - // If this is a copy try to reuse the input as the output; - // that will make the copy go away. - // If this is a copy, the source reg is a phys reg, and - // that reg is available, use that phys reg for DestPhysReg. - // If this is a copy, the source reg is a virtual reg, and - // the phys reg that was assigned to that virtual reg is now - // available, use that phys reg for DestPhysReg. (If it's now - // available that means this was the last use of the source.) - if (isCopy && - TargetRegisterInfo::isPhysicalRegister(SrcCopyReg) && - isPhysRegAvailable(SrcCopyReg)) { - DestPhysReg = SrcCopyReg; - assignVirtToPhysReg(DestVirtReg, DestPhysReg); - } else if (isCopy && - TargetRegisterInfo::isVirtualRegister(SrcCopyReg) && - SrcCopyPhysReg && isPhysRegAvailable(SrcCopyPhysReg) && - MF->getRegInfo().getRegClass(DestVirtReg)-> - contains(SrcCopyPhysReg)) { - DestPhysReg = SrcCopyPhysReg; - assignVirtToPhysReg(DestVirtReg, DestPhysReg); - } else - DestPhysReg = getReg(MBB, MI, DestVirtReg); - } - MF->getRegInfo().setPhysRegUsed(DestPhysReg); - markVirtRegModified(DestVirtReg); - getVirtRegLastUse(DestVirtReg) = std::make_pair((MachineInstr*)0, 0); - DEBUG(dbgs() << " Assigning " << TRI->getName(DestPhysReg) - << " to %reg" << DestVirtReg << "\n"); - - if (unsigned DestSubIdx = MO.getSubReg()) { - MO.setSubReg(0); - DestPhysReg = TRI->getSubReg(DestPhysReg, DestSubIdx); - } - MO.setReg(DestPhysReg); // Assign the output register - } - - // If this instruction defines any registers that are immediately dead, - // kill them now. - // - for (unsigned i = 0, e = DeadDefs.size(); i != e; ++i) { - unsigned VirtReg = DeadDefs[i]; - unsigned PhysReg = VirtReg; - if (TargetRegisterInfo::isVirtualRegister(VirtReg)) { - unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg); - PhysReg = PhysRegSlot; - assert(PhysReg != 0); - PhysRegSlot = 0; - } else if (PhysRegsUsed[PhysReg] == -2) { - // Unallocatable register dead, ignore. - continue; - } else if (!PhysReg) - continue; - - DEBUG(dbgs() << " Register " << TRI->getName(PhysReg) - << " [%reg" << VirtReg - << "] is never used, removing it from live set\n"); - removePhysReg(PhysReg); - for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg); - *AliasSet; ++AliasSet) { - if (PhysRegsUsed[*AliasSet] != -2) { - DEBUG(dbgs() << " Register " << TRI->getName(*AliasSet) - << " [%reg" << *AliasSet - << "] is never used, removing it from live set\n"); - removePhysReg(*AliasSet); - } - } - } - - // If this instruction is a call, make sure there are no dirty registers. The - // call might throw an exception, and the landing pad expects to find all - // registers in stack slots. - if (TID.isCall()) - for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) { - if (PhysRegsUsed[i] <= 0) continue; - unsigned VirtReg = PhysRegsUsed[i]; - if (!isVirtRegModified(VirtReg)) continue; - DEBUG(dbgs() << " Storing dirty %reg" << VirtReg); - storeVirtReg(MBB, MI, VirtReg, i, false); - markVirtRegModified(VirtReg, false); - DEBUG(dbgs() << " because the call might throw\n"); - } - - // Finally, if this is a noop copy instruction, zap it. (Except that if - // the copy is dead, it must be kept to avoid messing up liveness info for - // the register scavenger. See pr4100.) - if (TII->isMoveInstr(*MI, SrcCopyReg, DstCopyReg, - SrcCopySubReg, DstCopySubReg) && - SrcCopyReg == DstCopyReg && SrcCopySubReg == DstCopySubReg && - DeadDefs.empty()) { - ++NumCopies; - MBB.erase(MI); - } - } - - MachineBasicBlock::iterator MI = MBB.getFirstTerminator(); - - // Spill all physical registers holding virtual registers now. - for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) - if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2) { - if (unsigned VirtReg = PhysRegsUsed[i]) - spillVirtReg(MBB, MI, VirtReg, i); - else - removePhysReg(i); - } - -#if 0 - // This checking code is very expensive. - bool AllOk = true; - for (unsigned i = TargetRegisterInfo::FirstVirtualRegister, - e = MF->getRegInfo().getLastVirtReg(); i <= e; ++i) - if (unsigned PR = Virt2PhysRegMap[i]) { - cerr << "Register still mapped: " << i << " -> " << PR << "\n"; - AllOk = false; - } - assert(AllOk && "Virtual registers still in phys regs?"); -#endif - - // Clear any physical register which appear live at the end of the basic - // block, but which do not hold any virtual registers. e.g., the stack - // pointer. - PhysRegsUseOrder.clear(); -} - -/// runOnMachineFunction - Register allocate the whole function -/// -bool RALocal::runOnMachineFunction(MachineFunction &Fn) { - DEBUG(dbgs() << "Machine Function\n"); - MF = &Fn; - MRI = &Fn.getRegInfo(); - TM = &Fn.getTarget(); - TRI = TM->getRegisterInfo(); - TII = TM->getInstrInfo(); - - PhysRegsUsed.assign(TRI->getNumRegs(), -1); - - // At various places we want to efficiently check to see whether a register - // is allocatable. To handle this, we mark all unallocatable registers as - // being pinned down, permanently. - { - BitVector Allocable = TRI->getAllocatableSet(Fn); - for (unsigned i = 0, e = Allocable.size(); i != e; ++i) - if (!Allocable[i]) - PhysRegsUsed[i] = -2; // Mark the reg unallocable. - } - - // initialize the virtual->physical register map to have a 'null' - // mapping for all virtual registers - unsigned LastVirtReg = MF->getRegInfo().getLastVirtReg(); - StackSlotForVirtReg.grow(LastVirtReg); - Virt2PhysRegMap.grow(LastVirtReg); - Virt2LastUseMap.grow(LastVirtReg); - VirtRegModified.resize(LastVirtReg+1 - - TargetRegisterInfo::FirstVirtualRegister); - UsedInMultipleBlocks.resize(LastVirtReg+1 - - TargetRegisterInfo::FirstVirtualRegister); - - // Loop over all of the basic blocks, eliminating virtual register references - for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end(); - MBB != MBBe; ++MBB) - AllocateBasicBlock(*MBB); - - StackSlotForVirtReg.clear(); - PhysRegsUsed.clear(); - VirtRegModified.clear(); - UsedInMultipleBlocks.clear(); - Virt2PhysRegMap.clear(); - Virt2LastUseMap.clear(); - return true; -} - -FunctionPass *llvm::createLocalRegisterAllocator() { - return new RALocal(); -} Modified: llvm/trunk/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll?rev=106051&r1=106050&r2=106051&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2008-02-04-LocalRegAllocBug.ll Tue Jun 15 16:58:33 2010 @@ -1,4 +1,3 @@ -; RUN: llc < %s -mtriple=arm-linux-gnueabi -regalloc=local ; RUN: llc < %s -mtriple=arm-linux-gnueabi -regalloc=fast ; PR1925 Modified: llvm/trunk/test/CodeGen/ARM/2008-02-29-RegAllocLocal.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2008-02-29-RegAllocLocal.ll?rev=106051&r1=106050&r2=106051&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2008-02-29-RegAllocLocal.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2008-02-29-RegAllocLocal.ll Tue Jun 15 16:58:33 2010 @@ -1,4 +1,3 @@ -; RUN: llc < %s -mtriple=arm-apple-darwin -regalloc=local ; RUN: llc < %s -mtriple=arm-apple-darwin -regalloc=fast ; PR1925 Modified: llvm/trunk/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll?rev=106051&r1=106050&r2=106051&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll Tue Jun 15 16:58:33 2010 @@ -1,4 +1,3 @@ -; RUN: llc < %s -mtriple=armv5-unknown-linux-gnueabi -O0 -regalloc=local ; RUN: llc < %s -mtriple=armv5-unknown-linux-gnueabi -O0 -regalloc=fast ; PR4100 @.str = external constant [30 x i8] ; <[30 x i8]*> [#uses=1] Modified: llvm/trunk/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll?rev=106051&r1=106050&r2=106051&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll Tue Jun 15 16:58:33 2010 @@ -1,4 +1,3 @@ -; RUN: llc < %s -O0 -verify-machineinstrs -regalloc=local ; RUN: llc < %s -O0 -verify-machineinstrs -regalloc=fast ; rdar://problem/7948106 ;; This test would spill %R4 before the call to zz, but it forgot to move the Modified: llvm/trunk/test/CodeGen/Generic/2006-09-02-LocalAllocCrash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2006-09-02-LocalAllocCrash.ll?rev=106051&r1=106050&r2=106051&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Generic/2006-09-02-LocalAllocCrash.ll (original) +++ llvm/trunk/test/CodeGen/Generic/2006-09-02-LocalAllocCrash.ll Tue Jun 15 16:58:33 2010 @@ -1,4 +1,3 @@ -; RUN: llc < %s -regalloc=local ; RUN: llc < %s -regalloc=fast %struct.CHESS_POSITION = type { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32, i32, i8, i8, [64 x i8], i8, i8, i8, i8, i8 } Modified: llvm/trunk/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll?rev=106051&r1=106050&r2=106051&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll (original) +++ llvm/trunk/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll Tue Jun 15 16:58:33 2010 @@ -1,5 +1,4 @@ ; RUN: llc < %s | FileCheck %s -; RUN: llc < %s -regalloc=local | FileCheck %s ; RUN: llc < %s -regalloc=fast | FileCheck %s ; The first argument of subfc must not be the same as any other register. Modified: llvm/trunk/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll?rev=106051&r1=106050&r2=106051&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll (original) +++ llvm/trunk/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert.ll Tue Jun 15 16:58:33 2010 @@ -1,4 +1,3 @@ -; RUN: llc < %s -mtriple=powerpc64-apple-darwin9 -regalloc=local -relocation-model=pic ; RUN: llc < %s -mtriple=powerpc64-apple-darwin9 -regalloc=fast -relocation-model=pic %struct.NSError = type opaque Modified: llvm/trunk/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll?rev=106051&r1=106050&r2=106051&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll (original) +++ llvm/trunk/test/CodeGen/PowerPC/2007-10-21-LocalRegAllocAssert2.ll Tue Jun 15 16:58:33 2010 @@ -1,4 +1,3 @@ -; RUN: llc < %s -mtriple=powerpc64-apple-darwin9 -regalloc=local -relocation-model=pic ; RUN: llc < %s -mtriple=powerpc64-apple-darwin9 -regalloc=fast -relocation-model=pic %struct.NSError = type opaque Modified: llvm/trunk/test/CodeGen/PowerPC/2008-02-09-LocalRegAllocAssert.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2008-02-09-LocalRegAllocAssert.ll?rev=106051&r1=106050&r2=106051&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/2008-02-09-LocalRegAllocAssert.ll (original) +++ llvm/trunk/test/CodeGen/PowerPC/2008-02-09-LocalRegAllocAssert.ll Tue Jun 15 16:58:33 2010 @@ -1,4 +1,3 @@ -; RUN: llc < %s -mtriple=powerpc-apple-darwin -regalloc=local ; RUN: llc < %s -mtriple=powerpc-apple-darwin -regalloc=fast define i32 @bork(i64 %foo, i64 %bar) { Modified: llvm/trunk/test/CodeGen/PowerPC/cr_spilling.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/cr_spilling.ll?rev=106051&r1=106050&r2=106051&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/cr_spilling.ll (original) +++ llvm/trunk/test/CodeGen/PowerPC/cr_spilling.ll Tue Jun 15 16:58:33 2010 @@ -1,4 +1,3 @@ -; RUN: llc < %s -march=ppc32 -regalloc=local -O0 -relocation-model=pic -o - ; RUN: llc < %s -march=ppc32 -regalloc=fast -O0 -relocation-model=pic -o - ; PR1638 Modified: llvm/trunk/test/CodeGen/Thumb/2010-01-15-local-alloc-spill-physical.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/2010-01-15-local-alloc-spill-physical.ll?rev=106051&r1=106050&r2=106051&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/2010-01-15-local-alloc-spill-physical.ll (original) +++ llvm/trunk/test/CodeGen/Thumb/2010-01-15-local-alloc-spill-physical.ll Tue Jun 15 16:58:33 2010 @@ -1,4 +1,3 @@ -; RUN: llc < %s -regalloc=local -relocation-model=pic | FileCheck %s ; RUN: llc < %s -regalloc=fast -relocation-model=pic | FileCheck %s target triple = "thumbv6-apple-darwin10" Modified: llvm/trunk/test/CodeGen/X86/2008-01-16-FPStackifierAssert.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-01-16-FPStackifierAssert.ll?rev=106051&r1=106050&r2=106051&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2008-01-16-FPStackifierAssert.ll (original) +++ llvm/trunk/test/CodeGen/X86/2008-01-16-FPStackifierAssert.ll Tue Jun 15 16:58:33 2010 @@ -1,4 +1,3 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 -regalloc=local ; RUN: llc < %s -march=x86 -mattr=+sse2 -regalloc=fast define void @SolveCubic(double %a, double %b, double %c, double %d, i32* %solutions, double* %x) { Modified: llvm/trunk/test/CodeGen/X86/2008-02-22-LocalRegAllocBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-02-22-LocalRegAllocBug.ll?rev=106051&r1=106050&r2=106051&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2008-02-22-LocalRegAllocBug.ll (original) +++ llvm/trunk/test/CodeGen/X86/2008-02-22-LocalRegAllocBug.ll Tue Jun 15 16:58:33 2010 @@ -1,4 +1,3 @@ -; RUN: llc < %s -regalloc=local -march=x86 -mattr=+mmx | grep esi ; RUN: llc < %s -regalloc=fast -march=x86 -mattr=+mmx | grep esi ; PR2082 ; Local register allocator was refusing to use ESI, EDI, and EBP so it ran out of Modified: llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll?rev=106051&r1=106050&r2=106051&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll (original) +++ llvm/trunk/test/CodeGen/X86/2008-04-15-LiveVariableBug.ll Tue Jun 15 16:58:33 2010 @@ -1,5 +1,4 @@ ; RUN: llc < %s -mtriple=x86_64-apple-darwin -; RUN: llc < %s -mtriple=x86_64-apple-darwin -relocation-model=pic -disable-fp-elim -O0 -regalloc=local ; RUN: llc < %s -mtriple=x86_64-apple-darwin -relocation-model=pic -disable-fp-elim -O0 -regalloc=fast ; PR5534 Modified: llvm/trunk/test/CodeGen/X86/2008-05-28-LocalRegAllocBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-05-28-LocalRegAllocBug.ll?rev=106051&r1=106050&r2=106051&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2008-05-28-LocalRegAllocBug.ll (original) +++ llvm/trunk/test/CodeGen/X86/2008-05-28-LocalRegAllocBug.ll Tue Jun 15 16:58:33 2010 @@ -1,4 +1,3 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin -regalloc=local ; RUN: llc < %s -mtriple=i386-apple-darwin -regalloc=fast @_ZTVN10Evaluation10GridOutputILi3EEE = external constant [5 x i32 (...)*] ; <[5 x i32 (...)*]*> [#uses=1] Modified: llvm/trunk/test/CodeGen/X86/2008-09-17-inline-asm-1.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-09-17-inline-asm-1.ll?rev=106051&r1=106050&r2=106051&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2008-09-17-inline-asm-1.ll (original) +++ llvm/trunk/test/CodeGen/X86/2008-09-17-inline-asm-1.ll Tue Jun 15 16:58:33 2010 @@ -1,5 +1,4 @@ ; RUN: llc < %s -march=x86 | FileCheck %s -; RUN: llc < %s -march=x86 -regalloc=local | FileCheck %s ; RUN: llc < %s -march=x86 -regalloc=fast | FileCheck %s ; %0 must not be put in EAX or EDX. Modified: llvm/trunk/test/CodeGen/X86/2008-09-18-inline-asm-2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-09-18-inline-asm-2.ll?rev=106051&r1=106050&r2=106051&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2008-09-18-inline-asm-2.ll (original) +++ llvm/trunk/test/CodeGen/X86/2008-09-18-inline-asm-2.ll Tue Jun 15 16:58:33 2010 @@ -1,5 +1,4 @@ ; RUN: llc < %s -march=x86 | grep "#%ebp %esi %edi 8(%edx) %eax (%ebx)" -; RUN: llc < %s -march=x86 -regalloc=local | grep "#%edi %ebp %edx 8(%ebx) %eax (%esi)" ; RUN: llc < %s -march=x86 -regalloc=fast | grep "#%edi %ebp %edx 8(%ebx) %eax (%esi)" ; The 1st, 2nd, 3rd and 5th registers above must all be different. The registers Modified: llvm/trunk/test/CodeGen/X86/2009-01-29-LocalRegAllocBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-01-29-LocalRegAllocBug.ll?rev=106051&r1=106050&r2=106051&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2009-01-29-LocalRegAllocBug.ll (original) +++ llvm/trunk/test/CodeGen/X86/2009-01-29-LocalRegAllocBug.ll Tue Jun 15 16:58:33 2010 @@ -1,4 +1,3 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin9.6 -regalloc=local -disable-fp-elim ; RUN: llc < %s -mtriple=i386-apple-darwin9.6 -regalloc=fast -disable-fp-elim ; rdar://6538384 Modified: llvm/trunk/test/CodeGen/X86/2009-04-14-IllegalRegs.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-04-14-IllegalRegs.ll?rev=106051&r1=106050&r2=106051&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2009-04-14-IllegalRegs.ll (original) +++ llvm/trunk/test/CodeGen/X86/2009-04-14-IllegalRegs.ll Tue Jun 15 16:58:33 2010 @@ -1,4 +1,3 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin -O0 -regalloc=local | not grep sil ; RUN: llc < %s -mtriple=i386-apple-darwin -O0 -regalloc=fast | not grep sil ; rdar://6787136 Modified: llvm/trunk/test/CodeGen/X86/2009-04-24.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-04-24.ll?rev=106051&r1=106050&r2=106051&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2009-04-24.ll (original) +++ llvm/trunk/test/CodeGen/X86/2009-04-24.ll Tue Jun 15 16:58:33 2010 @@ -1,6 +1,4 @@ -; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu -regalloc=local -relocation-model=pic > %t -; RUN: grep {leal.*TLSGD.*___tls_get_addr} %t -; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu -regalloc=local -relocation-model=pic > %t2 +; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu -regalloc=fast -relocation-model=pic > %t2 ; RUN: grep {leaq.*TLSGD.*__tls_get_addr} %t2 ; PR4004 Modified: llvm/trunk/test/CodeGen/X86/2010-04-30-LocalAlloc-LandingPad.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-04-30-LocalAlloc-LandingPad.ll?rev=106051&r1=106050&r2=106051&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2010-04-30-LocalAlloc-LandingPad.ll (original) +++ llvm/trunk/test/CodeGen/X86/2010-04-30-LocalAlloc-LandingPad.ll Tue Jun 15 16:58:33 2010 @@ -1,4 +1,3 @@ -; RUN: llc < %s -O0 -regalloc=local -relocation-model=pic -disable-fp-elim | FileCheck %s ; RUN: llc < %s -O0 -regalloc=fast -relocation-model=pic -disable-fp-elim | FileCheck %s target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32" target triple = "i386-apple-darwin10.0.0" Modified: llvm/trunk/test/CodeGen/X86/2010-05-05-LocalAllocEarlyClobber.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-05-05-LocalAllocEarlyClobber.ll?rev=106051&r1=106050&r2=106051&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2010-05-05-LocalAllocEarlyClobber.ll (original) +++ llvm/trunk/test/CodeGen/X86/2010-05-05-LocalAllocEarlyClobber.ll Tue Jun 15 16:58:33 2010 @@ -1,4 +1,3 @@ -; RUN-XFAIL: llc < %s -O0 -regalloc=local | FileCheck %s ; RUN: llc < %s -O0 -regalloc=fast | FileCheck %s ; PR6520 Modified: llvm/trunk/test/CodeGen/X86/2010-05-06-LocalInlineAsmClobber.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-05-06-LocalInlineAsmClobber.ll?rev=106051&r1=106050&r2=106051&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2010-05-06-LocalInlineAsmClobber.ll (original) +++ llvm/trunk/test/CodeGen/X86/2010-05-06-LocalInlineAsmClobber.ll Tue Jun 15 16:58:33 2010 @@ -1,4 +1,3 @@ -; RUN: llc -regalloc=local %s -o %t ; RUN: llc -regalloc=fast %s -o %t ; PR7066 Modified: llvm/trunk/test/CodeGen/X86/fp-stack-O0-crash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fp-stack-O0-crash.ll?rev=106051&r1=106050&r2=106051&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/fp-stack-O0-crash.ll (original) +++ llvm/trunk/test/CodeGen/X86/fp-stack-O0-crash.ll Tue Jun 15 16:58:33 2010 @@ -1,4 +1,3 @@ -; RUN: llc %s -O0 -fast-isel -regalloc=local -o - ; RUN: llc %s -O0 -fast-isel -regalloc=fast -o - ; PR4767 Modified: llvm/trunk/test/CodeGen/X86/liveness-local-regalloc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/liveness-local-regalloc.ll?rev=106051&r1=106050&r2=106051&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/liveness-local-regalloc.ll (original) +++ llvm/trunk/test/CodeGen/X86/liveness-local-regalloc.ll Tue Jun 15 16:58:33 2010 @@ -1,4 +1,3 @@ -; RUN: llc < %s -O3 -regalloc=local -mtriple=x86_64-apple-darwin10 ; RUN: llc < %s -O3 -regalloc=fast -mtriple=x86_64-apple-darwin10 ; Removed: llvm/trunk/test/CodeGen/X86/local-liveness.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/local-liveness.ll?rev=106050&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/local-liveness.ll (original) +++ llvm/trunk/test/CodeGen/X86/local-liveness.ll (removed) @@ -1,31 +0,0 @@ -; RUN: llc < %s -march=x86 -regalloc=local | grep {subl %eax, %edx} - -; Local regalloc shouldn't assume that both the uses of the -; sub instruction are kills, because one of them is tied -; to an output. Previously, it was allocating both inputs -; in the same register. - -define i32 @func_3() nounwind { -entry: - %retval = alloca i32 ; [#uses=2] - %g_323 = alloca i8 ; [#uses=2] - %p_5 = alloca i64, align 8 ; [#uses=2] - %0 = alloca i32 ; [#uses=2] - %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] - store i64 0, i64* %p_5, align 8 - store i8 1, i8* %g_323, align 1 - %1 = load i8* %g_323, align 1 ; [#uses=1] - %2 = sext i8 %1 to i64 ; [#uses=1] - %3 = load i64* %p_5, align 8 ; [#uses=1] - %4 = sub i64 %3, %2 ; [#uses=1] - %5 = icmp sge i64 %4, 0 ; [#uses=1] - %6 = zext i1 %5 to i32 ; [#uses=1] - store i32 %6, i32* %0, align 4 - %7 = load i32* %0, align 4 ; [#uses=1] - store i32 %7, i32* %retval, align 4 - br label %return - -return: ; preds = %entry - %retval1 = load i32* %retval ; [#uses=1] - ret i32 %retval1 -} Modified: llvm/trunk/test/CodeGen/X86/phys-reg-local-regalloc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/phys-reg-local-regalloc.ll?rev=106051&r1=106050&r2=106051&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/phys-reg-local-regalloc.ll (original) +++ llvm/trunk/test/CodeGen/X86/phys-reg-local-regalloc.ll Tue Jun 15 16:58:33 2010 @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=x86 -mtriple=i386-apple-darwin9 -regalloc=local | FileCheck %s -; RUN: llc -O0 < %s -march=x86 -mtriple=i386-apple-darwin9 -regalloc=local | FileCheck %s +; RUN: llc < %s -march=x86 -mtriple=i386-apple-darwin9 -regalloc=fast | FileCheck %s +; RUN: llc -O0 < %s -march=x86 -mtriple=i386-apple-darwin9 -regalloc=fast | FileCheck %s ; CHECKed instructions should be the same with or without -O0. @.str = private constant [12 x i8] c"x + y = %i\0A\00", align 1 ; <[12 x i8]*> [#uses=1] From clattner at apple.com Tue Jun 15 17:01:30 2010 From: clattner at apple.com (Chris Lattner) Date: Tue, 15 Jun 2010 15:01:30 -0700 Subject: [llvm-commits] [llvm] r106051 - in /llvm/trunk: docs/ include/llvm/CodeGen/ lib/CodeGen/ test/CodeGen/ARM/ test/CodeGen/Generic/ test/CodeGen/PowerPC/ test/CodeGen/Thumb/ test/CodeGen/X86/ In-Reply-To: <20100615215833.ED6BC2A6C12C@llvm.org> References: <20100615215833.ED6BC2A6C12C@llvm.org> Message-ID: On Jun 15, 2010, at 2:58 PM, Jakob Stoklund Olesen wrote: > Author: stoklund > Date: Tue Jun 15 16:58:33 2010 > New Revision: 106051 > > URL: http://llvm.org/viewvc/llvm-project?rev=106051&view=rev > Log: > Remove the local register allocator. > Please use the fast allocator instead. Woohoo! From bob.wilson at apple.com Tue Jun 15 17:07:22 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 15 Jun 2010 15:07:22 -0700 Subject: [llvm-commits] [patch] Update llvm-gcc to produce "" for the default calling convention on ARM In-Reply-To: References: <76A0798C-9AB8-43E8-99C1-7AFE618CEBEB@apple.com> Message-ID: <3ED0C896-FA3E-47B3-848F-EC74642A84E4@apple.com> On Jun 15, 2010, at 2:50 PM, Rafael Espindola wrote: >> As far as I understand this, you want to change llvm-gcc and clang to set the CC to "" when it matches the backend's default for the target. This patch seems insufficient. You'll need to check to see what the current target is set to and compare the current ABI against the default for that target. > > An updated patch is attached. With it and a gcc configured for > arm-none-linux-gnueabi I get: > > *) no -mabi -> "" > *) -mabi=aapcs -> "" > *) -mcpu=cortex-a8 -> arm_apcscc > *) -mfloat-abi=hard -> arm_aapcs_vfpcc > > Is it OK? Yeah, I think that will work. From dalej at apple.com Tue Jun 15 17:08:33 2010 From: dalej at apple.com (Dale Johannesen) Date: Tue, 15 Jun 2010 22:08:33 -0000 Subject: [llvm-commits] [llvm] r106053 - in /llvm/trunk: lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseRegisterInfo.cpp lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMRegisterInfo.td lib/Target/ARM/Thumb1InstrInfo.cpp lib/Target/ARM/Thumb2InstrInfo.cpp utils/TableGen/ARMDecoderEmitter.cpp utils/TableGen/EDEmitter.cpp Message-ID: <20100615220833.4E0972A6C12C@llvm.org> Author: johannes Date: Tue Jun 15 17:08:33 2010 New Revision: 106053 URL: http://llvm.org/viewvc/llvm-project?rev=106053&view=rev Log: Next round of tail call changes. Register used in a tail call must not be callee-saved; following x86, add a new regclass to represent this. Also fixes a couple of bugs. Still disabled by default; Thumb doesn't work yet. Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp llvm/trunk/utils/TableGen/EDEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=106053&r1=106052&r2=106053&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Jun 15 17:08:33 2010 @@ -596,6 +596,7 @@ return true; } case ARM::MOVr: + case ARM::MOVr_TC: case ARM::tMOVr: case ARM::tMOVgpr2tgpr: case ARM::tMOVtgpr2gpr: @@ -701,11 +702,11 @@ const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC, DebugLoc DL) const { - // tGPR is used sometimes in ARM instructions that need to avoid using - // certain registers. Just treat it as GPR here. - if (DestRC == ARM::tGPRRegisterClass) + // tGPR or tcGPR is used sometimes in ARM instructions that need to avoid + // using certain registers. Just treat them as GPR here. + if (DestRC == ARM::tGPRRegisterClass || DestRC == ARM::tcGPRRegisterClass) DestRC = ARM::GPRRegisterClass; - if (SrcRC == ARM::tGPRRegisterClass) + if (SrcRC == ARM::tGPRRegisterClass || SrcRC == ARM::tcGPRRegisterClass) SrcRC = ARM::GPRRegisterClass; // Allow DPR / DPR_VFP2 / DPR_8 cross-class copies. @@ -799,7 +800,7 @@ // tGPR is used sometimes in ARM instructions that need to avoid using // certain registers. Just treat it as GPR here. - if (RC == ARM::tGPRRegisterClass) + if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass) RC = ARM::GPRRegisterClass; if (RC == ARM::GPRRegisterClass) { @@ -890,7 +891,7 @@ // tGPR is used sometimes in ARM instructions that need to avoid using // certain registers. Just treat it as GPR here. - if (RC == ARM::tGPRRegisterClass) + if (RC == ARM::tGPRRegisterClass || RC == ARM::tcGPRRegisterClass) RC = ARM::GPRRegisterClass; if (RC == ARM::GPRRegisterClass) { Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=106053&r1=106052&r2=106053&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Tue Jun 15 17:08:33 2010 @@ -1662,13 +1662,15 @@ addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), JumpTarget.getTargetFlags()); } else if (RetOpcode == ARM::TCRETURNri) { - BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPr), JumpTarget.getReg()); + BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPr)). + addReg(JumpTarget.getReg(), RegState::Kill); } else if (RetOpcode == ARM::TCRETURNriND) { - BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPrND), JumpTarget.getReg()); + BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPrND)). + addReg(JumpTarget.getReg(), RegState::Kill); } MachineInstr *NewMI = prior(MBBI); - for (unsigned i = 2, e = MBBI->getNumOperands(); i != e; ++i) + for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i) NewMI->addOperand(MBBI->getOperand(i)); // Delete the pseudo instruction TCRETURN. Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=106053&r1=106052&r2=106053&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Jun 15 17:08:33 2010 @@ -1109,11 +1109,14 @@ // Build a sequence of copy-to-reg nodes chained together with token chain // and flag operands which copy the outgoing args into the appropriate regs. SDValue InFlag; - for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { - Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, - RegsToPass[i].second, InFlag); - InFlag = Chain.getValue(1); - } + // Tail call byval lowering might overwrite argument registers so in case of + // tail call optimization the copies to registers are lowered later. + if (!isTailCall) + for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { + Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, + RegsToPass[i].second, InFlag); + InFlag = Chain.getValue(1); + } // For tail calls lower the arguments to the 'real' stack slot. if (isTailCall) { Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td?rev=106053&r1=106052&r2=106053&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td Tue Jun 15 17:08:33 2010 @@ -349,6 +349,83 @@ }]; } +// For tail calls, we can't use callee-saved registers, as they are restored +// to the saved value before the tail call, which would clobber a call address. +// Note, getMinimalPhysRegClass(R0) returns tGPR because of the names of +// this class and the preceding one(!) This is what we want. +def tcGPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R9, R12]> { + let MethodProtos = [{ + iterator allocation_order_begin(const MachineFunction &MF) const; + iterator allocation_order_end(const MachineFunction &MF) const; + }]; + let MethodBodies = [{ + // R9 is available. + static const unsigned ARM_GPR_R9_TC[] = { + ARM::R0, ARM::R1, ARM::R2, ARM::R3, + ARM::R9, ARM::R12 }; + // R9 is not available. + static const unsigned ARM_GPR_NOR9_TC[] = { + ARM::R0, ARM::R1, ARM::R2, ARM::R3, + ARM::R12 }; + + // For Thumb1 mode, we don't want to allocate hi regs at all, as we + // don't know how to spill them. If we make our prologue/epilogue code + // smarter at some point, we can go back to using the above allocation + // orders for the Thumb1 instructions that know how to use hi regs. + static const unsigned THUMB_GPR_AO_TC[] = { + ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; + + tcGPRClass::iterator + tcGPRClass::allocation_order_begin(const MachineFunction &MF) const { + const TargetMachine &TM = MF.getTarget(); + const ARMSubtarget &Subtarget = TM.getSubtarget(); + if (Subtarget.isThumb1Only()) + return THUMB_GPR_AO_TC; + if (Subtarget.isTargetDarwin()) { + if (Subtarget.isR9Reserved()) + return ARM_GPR_NOR9_TC; + else + return ARM_GPR_R9_TC; + } else { + if (Subtarget.isR9Reserved()) + return ARM_GPR_NOR9_TC; + else if (Subtarget.isThumb()) + return ARM_GPR_R9_TC; + else + return ARM_GPR_R9_TC; + } + } + + tcGPRClass::iterator + tcGPRClass::allocation_order_end(const MachineFunction &MF) const { + const TargetMachine &TM = MF.getTarget(); + const ARMSubtarget &Subtarget = TM.getSubtarget(); + GPRClass::iterator I; + + if (Subtarget.isThumb1Only()) { + I = THUMB_GPR_AO_TC + (sizeof(THUMB_GPR_AO_TC)/sizeof(unsigned)); + return I; + } + + if (Subtarget.isTargetDarwin()) { + if (Subtarget.isR9Reserved()) + I = ARM_GPR_NOR9_TC + (sizeof(ARM_GPR_NOR9_TC)/sizeof(unsigned)); + else + I = ARM_GPR_R9_TC + (sizeof(ARM_GPR_R9_TC)/sizeof(unsigned)); + } else { + if (Subtarget.isR9Reserved()) + I = ARM_GPR_NOR9_TC + (sizeof(ARM_GPR_NOR9_TC)/sizeof(unsigned)); + else if (Subtarget.isThumb()) + I = ARM_GPR_R9_TC + (sizeof(ARM_GPR_R9_TC)/sizeof(unsigned)); + else + I = ARM_GPR_R9_TC + (sizeof(ARM_GPR_R9_TC)/sizeof(unsigned)); + } + return I; + } + }]; +} + + // Scalar single precision floating point register class.. def SPR : RegisterClass<"ARM", [f32], 32, [S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, Modified: llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp?rev=106053&r1=106052&r2=106053&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp Tue Jun 15 17:08:33 2010 @@ -39,8 +39,8 @@ const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC, DebugLoc DL) const { - if (DestRC == ARM::GPRRegisterClass) { - if (SrcRC == ARM::GPRRegisterClass) { + if (DestRC == ARM::GPRRegisterClass || DestRC == ARM::tcGPRRegisterClass) { + if (SrcRC == ARM::GPRRegisterClass || SrcRC == ARM::tcGPRRegisterClass) { BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg); return true; } else if (SrcRC == ARM::tGPRRegisterClass) { @@ -48,7 +48,7 @@ return true; } } else if (DestRC == ARM::tGPRRegisterClass) { - if (SrcRC == ARM::GPRRegisterClass) { + if (SrcRC == ARM::GPRRegisterClass || SrcRC == ARM::tcGPRRegisterClass) { BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg); return true; } else if (SrcRC == ARM::tGPRRegisterClass) { Modified: llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp?rev=106053&r1=106052&r2=106053&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp Tue Jun 15 17:08:33 2010 @@ -42,8 +42,8 @@ const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC, DebugLoc DL) const { - if (DestRC == ARM::GPRRegisterClass) { - if (SrcRC == ARM::GPRRegisterClass) { + if (DestRC == ARM::GPRRegisterClass || DestRC == ARM::tcGPRRegisterClass) { + if (SrcRC == ARM::GPRRegisterClass || SrcRC == ARM::tcGPRRegisterClass) { BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg); return true; } else if (SrcRC == ARM::tGPRRegisterClass) { @@ -51,7 +51,7 @@ return true; } } else if (DestRC == ARM::tGPRRegisterClass) { - if (SrcRC == ARM::GPRRegisterClass) { + if (SrcRC == ARM::GPRRegisterClass || SrcRC == ARM::tcGPRRegisterClass) { BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg); return true; } else if (SrcRC == ARM::tGPRRegisterClass) { @@ -70,7 +70,8 @@ unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { - if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass) { + if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass || + RC == ARM::tcGPRRegisterClass) { DebugLoc DL; if (I != MBB.end()) DL = I->getDebugLoc(); @@ -95,7 +96,8 @@ unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { - if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass) { + if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass || + RC == ARM::tcGPRRegisterClass) { DebugLoc DL; if (I != MBB.end()) DL = I->getDebugLoc(); Modified: llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp?rev=106053&r1=106052&r2=106053&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp Tue Jun 15 17:08:33 2010 @@ -1579,7 +1579,8 @@ if (Name == "TCRETURNdi" || Name == "TCRETURNdiND" || Name == "TCRETURNri" || Name == "TCRETURNriND" || Name == "TAILJMPd" || Name == "TAILJMPdND" || - Name == "TAILJMPr" || Name == "TAILJMPrND") + Name == "TAILJMPr" || Name == "TAILJMPrND" || + Name == "MOVr_TC") return false; // VLDMQ/VSTMQ can be hanlded with the more generic VLDMD/VSTMD. Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=106053&r1=106052&r2=106053&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/EDEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/EDEmitter.cpp Tue Jun 15 17:08:33 2010 @@ -570,6 +570,7 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type, const std::string &name) { REG("GPR"); + REG("tcGPR"); REG("cc_out"); REG("s_cc_out"); REG("tGPR"); From natebegeman at mac.com Tue Jun 15 17:10:31 2010 From: natebegeman at mac.com (Nate Begeman) Date: Tue, 15 Jun 2010 22:10:31 -0000 Subject: [llvm-commits] [llvm] r106054 - /llvm/trunk/utils/TableGen/NeonEmitter.cpp Message-ID: <20100615221031.2E83B2A6C12C@llvm.org> Author: sampo Date: Tue Jun 15 17:10:31 2010 New Revision: 106054 URL: http://llvm.org/viewvc/llvm-project?rev=106054&view=rev Log: Make VC++ happy Modified: llvm/trunk/utils/TableGen/NeonEmitter.cpp Modified: llvm/trunk/utils/TableGen/NeonEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/NeonEmitter.cpp?rev=106054&r1=106053&r2=106054&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/NeonEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/NeonEmitter.cpp Tue Jun 15 17:10:31 2010 @@ -526,17 +526,17 @@ s += a + " - " + b; break; case OpMulN: - b = Duplicate(nElts << quad, typestr, "b"); + b = Duplicate(nElts << (int)quad, typestr, "b"); case OpMul: s += a + " * " + b; break; case OpMlaN: - c = Duplicate(nElts << quad, typestr, "c"); + c = Duplicate(nElts << (int)quad, typestr, "c"); case OpMla: s += a + " + ( " + b + " * " + c + " )"; break; case OpMlsN: - c = Duplicate(nElts << quad, typestr, "c"); + c = Duplicate(nElts << (int)quad, typestr, "c"); case OpMls: s += a + " - ( " + b + " * " + c + " )"; break; @@ -590,7 +590,7 @@ s += "(__neon_int64x1_t)(((__neon_int64x2_t)" + a + ")[0])"; break; case OpDup: - s += Duplicate(nElts << quad, typestr, a); + s += Duplicate(nElts << (int)quad, typestr, a); break; case OpSelect: // ((0 & 1) | (~0 & 2)) @@ -600,7 +600,7 @@ break; case OpRev16: s += "__builtin_shufflevector(" + a + ", " + a; - for (unsigned i = 2; i <= nElts << quad; i += 2) + for (unsigned i = 2; i <= nElts << (int)quad; i += 2) for (unsigned j = 0; j != 2; ++j) s += ", " + utostr(i - j - 1); s += ")"; @@ -608,14 +608,14 @@ case OpRev32: nElts >>= 1; s += "__builtin_shufflevector(" + a + ", " + a; - for (unsigned i = nElts; i <= nElts << (1 + quad); i += nElts) + for (unsigned i = nElts; i <= nElts << (1 + (int)quad); i += nElts) for (unsigned j = 0; j != nElts; ++j) s += ", " + utostr(i - j - 1); s += ")"; break; case OpRev64: s += "__builtin_shufflevector(" + a + ", " + a; - for (unsigned i = nElts; i <= nElts << quad; i += nElts) + for (unsigned i = nElts; i <= nElts << (int)quad; i += nElts) for (unsigned j = 0; j != nElts; ++j) s += ", " + utostr(i - j - 1); s += ")"; @@ -953,15 +953,15 @@ switch (type) { case 'c': - return (8 << quad) - 1; + return (8 << (int)quad) - 1; case 'h': case 's': - return (4 << quad) - 1; + return (4 << (int)quad) - 1; case 'f': case 'i': - return (2 << quad) - 1; + return (2 << (int)quad) - 1; case 'l': - return (1 << quad) - 1; + return (1 << (int)quad) - 1; default: throw "unhandled type!"; break; From rafael.espindola at gmail.com Tue Jun 15 17:11:59 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Tue, 15 Jun 2010 22:11:59 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r106055 - /llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm-target.h Message-ID: <20100615221159.531732A6C12C@llvm.org> Author: rafael Date: Tue Jun 15 17:11:59 2010 New Revision: 106055 URL: http://llvm.org/viewvc/llvm-project?rev=106055&view=rev Log: If the target ABI and the DEFAULT ABI use the same calling convention, use the C calling convention instead of forcing a particular one. Modified: llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm-target.h Modified: llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm-target.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm-target.h?rev=106055&r1=106054&r2=106055&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm-target.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm-target.h Tue Jun 15 17:11:59 2010 @@ -25,17 +25,24 @@ specification says that varargs functions must use the base standard instead of the VFP hard float variant. We check for that with (isVoid || hasArgList). */ + +/* from TARGET_AAPCS_BASED */ +#define DEFAULT_TARGET_AAPCS_BASED \ + (ARM_DEFAULT_ABI != ARM_ABI_APCS && ARM_DEFAULT_ABI != ARM_ABI_ATPCS) + #define TARGET_ADJUST_LLVM_CC(CC, type) \ { \ - if (TARGET_AAPCS_BASED) \ - CC = ((TARGET_VFP && TARGET_HARD_FLOAT_ABI && \ + if (TARGET_AAPCS_BASED) { \ + if (TARGET_VFP && TARGET_HARD_FLOAT_ABI && \ ((TYPE_ARG_TYPES(type) == 0) || \ (TREE_VALUE(tree_last(TYPE_ARG_TYPES(type))) == \ - void_type_node))) ? \ - CallingConv::ARM_AAPCS_VFP : \ - CallingConv::ARM_AAPCS); \ - else \ - CC = CallingConv::ARM_APCS; \ + void_type_node))) \ + CC = CallingConv::ARM_AAPCS_VFP; \ + if (!DEFAULT_TARGET_AAPCS_BASED) \ + CC = CallingConv::ARM_AAPCS; \ + } else if (DEFAULT_TARGET_AAPCS_BASED) { \ + CC = CallingConv::ARM_APCS; \ + } \ } #ifdef LLVM_ABI_H From rafael.espindola at gmail.com Tue Jun 15 17:16:40 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Tue, 15 Jun 2010 22:16:40 -0000 Subject: [llvm-commits] [llvm] r106056 - /llvm/trunk/test/FrontendC/pr5406.c Message-ID: <20100615221640.D79C82A6C12C@llvm.org> Author: rafael Date: Tue Jun 15 17:16:40 2010 New Revision: 106056 URL: http://llvm.org/viewvc/llvm-project?rev=106056&view=rev Log: Update test to match recent llvm-gcc change. Modified: llvm/trunk/test/FrontendC/pr5406.c Modified: llvm/trunk/test/FrontendC/pr5406.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/pr5406.c?rev=106056&r1=106055&r2=106056&view=diff ============================================================================== --- llvm/trunk/test/FrontendC/pr5406.c (original) +++ llvm/trunk/test/FrontendC/pr5406.c Tue Jun 15 17:16:40 2010 @@ -8,7 +8,7 @@ void foo (int i, ...); -// CHECK: call arm_aapcscc void (i32, ...)* @foo(i32 1, i32 {{.*}}) nounwind +// CHECK: call void (i32, ...)* @foo(i32 1, i32 {{.*}}) nounwind int main (void) { A0 a3; From bob.wilson at apple.com Tue Jun 15 17:18:54 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 15 Jun 2010 22:18:54 -0000 Subject: [llvm-commits] [llvm] r106057 - /llvm/trunk/lib/CodeGen/IfConversion.cpp Message-ID: <20100615221854.3276F2A6C12C@llvm.org> Author: bwilson Date: Tue Jun 15 17:18:54 2010 New Revision: 106057 URL: http://llvm.org/viewvc/llvm-project?rev=106057&view=rev Log: Fix 80col violations, remove trailing whitespace, and clarify a comment. Modified: llvm/trunk/lib/CodeGen/IfConversion.cpp Modified: llvm/trunk/lib/CodeGen/IfConversion.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/IfConversion.cpp?rev=106057&r1=106056&r2=106057&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/IfConversion.cpp (original) +++ llvm/trunk/lib/CodeGen/IfConversion.cpp Tue Jun 15 17:18:54 2010 @@ -33,19 +33,19 @@ static cl::opt IfCvtFnStart("ifcvt-fn-start", cl::init(-1), cl::Hidden); static cl::opt IfCvtFnStop("ifcvt-fn-stop", cl::init(-1), cl::Hidden); static cl::opt IfCvtLimit("ifcvt-limit", cl::init(-1), cl::Hidden); -static cl::opt DisableSimple("disable-ifcvt-simple", +static cl::opt DisableSimple("disable-ifcvt-simple", cl::init(false), cl::Hidden); -static cl::opt DisableSimpleF("disable-ifcvt-simple-false", +static cl::opt DisableSimpleF("disable-ifcvt-simple-false", cl::init(false), cl::Hidden); -static cl::opt DisableTriangle("disable-ifcvt-triangle", +static cl::opt DisableTriangle("disable-ifcvt-triangle", cl::init(false), cl::Hidden); -static cl::opt DisableTriangleR("disable-ifcvt-triangle-rev", +static cl::opt DisableTriangleR("disable-ifcvt-triangle-rev", cl::init(false), cl::Hidden); -static cl::opt DisableTriangleF("disable-ifcvt-triangle-false", +static cl::opt DisableTriangleF("disable-ifcvt-triangle-false", cl::init(false), cl::Hidden); -static cl::opt DisableTriangleFR("disable-ifcvt-triangle-false-rev", +static cl::opt DisableTriangleFR("disable-ifcvt-triangle-false-rev", cl::init(false), cl::Hidden); -static cl::opt DisableDiamond("disable-ifcvt-diamond", +static cl::opt DisableDiamond("disable-ifcvt-diamond", cl::init(false), cl::Hidden); STATISTIC(NumSimple, "Number of simple if-conversions performed"); @@ -281,7 +281,8 @@ case ICSimpleFalse: { bool isFalse = Kind == ICSimpleFalse; if ((isFalse && DisableSimpleF) || (!isFalse && DisableSimple)) break; - DEBUG(dbgs() << "Ifcvt (Simple" << (Kind == ICSimpleFalse ? " false" :"") + DEBUG(dbgs() << "Ifcvt (Simple" << (Kind == ICSimpleFalse ? + " false" : "") << "): BB#" << BBI.BB->getNumber() << " (" << ((Kind == ICSimpleFalse) ? BBI.FalseBB->getNumber() @@ -431,7 +432,7 @@ /// ValidTriangle - Returns true if the 'true' and 'false' blocks (along /// with their common predecessor) forms a valid triangle shape for ifcvt. /// If 'FalseBranch' is true, it checks if 'true' block's false branch -/// branches to the false branch rather than the other way around. It also +/// branches to the 'false' block rather than the other way around. It also /// returns the number of instructions that the ifcvt would need to duplicate /// if performed in 'Dups'. bool IfConverter::ValidTriangle(BBInfo &TrueBBI, BBInfo &FalseBBI, @@ -570,7 +571,7 @@ // No false branch. This BB must end with a conditional branch and a // fallthrough. if (!BBI.FalseBB) - BBI.FalseBB = findFalseBlock(BBI.BB, BBI.TrueBB); + BBI.FalseBB = findFalseBlock(BBI.BB, BBI.TrueBB); if (!BBI.FalseBB) { // Malformed bcc? True and false blocks are the same? BBI.IsUnpredicable = true; @@ -749,7 +750,7 @@ Tokens.push_back(new IfcvtToken(BBI, ICTriangle, TNeedSub, Dups)); Enqueued = true; } - + if (ValidTriangle(TrueBBI, FalseBBI, true, Dups) && MeetIfcvtSizeLimit(TrueBBI.NonPredSize) && FeasibilityAnalysis(TrueBBI, BBI.BrCond, true, true)) { @@ -765,7 +766,7 @@ // | \_ // | | // | TBB---> exit - // | + // | // FBB Tokens.push_back(new IfcvtToken(BBI, ICSimple, TNeedSub, Dups)); Enqueued = true; @@ -1022,7 +1023,7 @@ RemoveExtraEdges(BBI); // Update block info. BB can be iteratively if-converted. - if (!IterIfcvt) + if (!IterIfcvt) BBI.IsDone = true; InvalidatePreds(BBI.BB); CvtBBI->IsDone = true; @@ -1253,7 +1254,7 @@ continue; Pred->ReplaceUsesOfBlockWith(FromBBI.BB, ToBBI.BB); } - + std::vector Succs(FromBBI.BB->succ_begin(), FromBBI.BB->succ_end()); MachineBasicBlock *NBB = getNextBlock(FromBBI.BB); From dalej at apple.com Tue Jun 15 17:24:09 2010 From: dalej at apple.com (Dale Johannesen) Date: Tue, 15 Jun 2010 22:24:09 -0000 Subject: [llvm-commits] [llvm] r106058 - /llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Message-ID: <20100615222409.1903F2A6C12C@llvm.org> Author: johannes Date: Tue Jun 15 17:24:08 2010 New Revision: 106058 URL: http://llvm.org/viewvc/llvm-project?rev=106058&view=rev Log: Add file missing from previous commit. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=106058&r1=106057&r2=106058&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Jun 15 17:24:08 2010 @@ -1044,7 +1044,7 @@ Pseudo, IIC_Br, "@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>; - def TCRETURNri : AInoP<(outs), (ins tGPR:$dst, variable_ops), + def TCRETURNri : AInoP<(outs), (ins tcGPR:$dst, variable_ops), Pseudo, IIC_Br, "@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>; @@ -1052,7 +1052,7 @@ IIC_Br, "b\t$dst @ TAILCALL", []>, Requires<[IsDarwin]>; - def TAILJMPr : AXI<(outs), (ins tGPR:$dst, variable_ops), + def TAILJMPr : AXI<(outs), (ins tcGPR:$dst, variable_ops), BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL", []>, Requires<[IsDarwin]> { let Inst{7-4} = 0b0001; @@ -1476,6 +1476,14 @@ let Inst{25} = 0; } +// A version for the smaller set of tail call registers. +let neverHasSideEffects = 1 in +def MOVr_TC : AsI1<0b1101, (outs tcGPR:$dst), (ins tcGPR:$src), DPFrm, + IIC_iMOVr, "mov", "\t$dst, $src", []>, UnaryDP { + let Inst{11-4} = 0b00000000; + let Inst{25} = 0; +} + def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm, IIC_iMOVsr, "mov", "\t$dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP { @@ -2700,8 +2708,8 @@ // TODO: add,sub,and, 3-instr forms? // Tail calls -def : ARMPat<(ARMtcret tGPR:$dst), - (TCRETURNri tGPR:$dst)>, Requires<[IsDarwin]>; +def : ARMPat<(ARMtcret tcGPR:$dst), + (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>; def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>; @@ -2709,8 +2717,8 @@ def : ARMPat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>; -def : ARMPat<(ARMtcret tGPR:$dst), - (TCRETURNriND tGPR:$dst)>, Requires<[IsNotDarwin]>; +def : ARMPat<(ARMtcret tcGPR:$dst), + (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>; def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>; From echristo at apple.com Tue Jun 15 17:59:05 2010 From: echristo at apple.com (Eric Christopher) Date: Tue, 15 Jun 2010 22:59:05 -0000 Subject: [llvm-commits] [llvm] r106062 - /llvm/trunk/lib/MC/MachObjectWriter.cpp Message-ID: <20100615225905.758892A6C12C@llvm.org> Author: echristo Date: Tue Jun 15 17:59:05 2010 New Revision: 106062 URL: http://llvm.org/viewvc/llvm-project?rev=106062&view=rev Log: Some more work on mach-o TLV relocations. Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MachObjectWriter.cpp?rev=106062&r1=106061&r2=106062&view=diff ============================================================================== --- llvm/trunk/lib/MC/MachObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/MachObjectWriter.cpp Tue Jun 15 17:59:05 2010 @@ -738,6 +738,38 @@ Relocations[Fragment->getParent()].push_back(MRE); } + void RecordTLVPRelocation(const MCAssembler &Asm, + const MCAsmLayout &Layout, + const MCFragment *Fragment, + const MCFixup &Fixup, MCValue Target, + uint64_t &FixedValue) { + assert(Target.getSymA()->getKind() == MCSymbolRefExpr::VK_TLVP && + !Is64Bit && + "Should only be called with a 32-bit TLVP relocation!"); + + // If this is a subtraction then we're pcrel. + unsigned Log2Size = getFixupKindLog2Size(Fixup.getKind()); + uint32_t Value = Layout.getFragmentOffset(Fragment)+Fixup.getOffset(); + unsigned IsPCRel = 0; + + // Get the symbol data. + MCSymbolData *SD_A = &Asm.getSymbolData(Target.getSymA()->getSymbol()); + unsigned Index = SD_A->getIndex(); + + if (Target.getSymB()) + IsPCRel = 1; + + // struct relocation_info (8 bytes) + MachRelocationEntry MRE; + MRE.Word0 = Value; + MRE.Word1 = ((Index << 0) | + (IsPCRel << 24) | + (Log2Size << 25) | + (1 << 27) | // Extern + (RIT_TLV << 28)); // Type + Relocations[Fragment->getParent()].push_back(MRE); + } + void RecordRelocation(const MCAssembler &Asm, const MCAsmLayout &Layout, const MCFragment *Fragment, const MCFixup &Fixup, MCValue Target, uint64_t &FixedValue) { @@ -749,6 +781,12 @@ unsigned IsPCRel = isFixupKindPCRel(Fixup.getKind()); unsigned Log2Size = getFixupKindLog2Size(Fixup.getKind()); + // If this is a 32-bit TLVP reloc it's handled a bit differently. + if (Target.getSymA()->getKind() == MCSymbolRefExpr::VK_TLVP) { + RecordTLVPRelocation(Asm, Layout, Fragment, Fixup, Target, FixedValue); + return; + } + // If this is a difference or a defined symbol plus an offset, then we need // a scattered relocation entry. // Differences always require scattered relocations. From stuart at apple.com Tue Jun 15 18:06:30 2010 From: stuart at apple.com (Stuart Hastings) Date: Tue, 15 Jun 2010 23:06:30 -0000 Subject: [llvm-commits] [llvm] r106063 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Message-ID: <20100615230630.E1F1A2A6C12C@llvm.org> Author: stuart Date: Tue Jun 15 18:06:30 2010 New Revision: 106063 URL: http://llvm.org/viewvc/llvm-project?rev=106063&view=rev Log: Added a comment. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=106063&r1=106062&r2=106063&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Tue Jun 15 18:06:30 2010 @@ -2353,6 +2353,11 @@ if (!WScope->getParent()) { StringRef SPName = DISubprogram(Scope).getLinkageName(); + // We used to check only for a linkage name, but that fails + // since we began omitting the linkage name for private + // functions. The new way is to check for the name in metadata, + // but that's not supported in old .ll test cases. Ergo, we + // check both. if (SPName == Asm->MF->getFunction()->getName() || DISubprogram(Scope).getFunction() == Asm->MF->getFunction()) CurrentFnDbgScope = WScope; From echristo at apple.com Tue Jun 15 18:08:42 2010 From: echristo at apple.com (Eric Christopher) Date: Tue, 15 Jun 2010 23:08:42 -0000 Subject: [llvm-commits] [llvm] r106064 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20100615230842.B0F6A2A6C12C@llvm.org> Author: echristo Date: Tue Jun 15 18:08:42 2010 New Revision: 106064 URL: http://llvm.org/viewvc/llvm-project?rev=106064&view=rev Log: For 32-bit non-pic tlv mach-o addressing we don't need a pic base or a relative address. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=106064&r1=106063&r2=106064&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Jun 15 18:08:42 2010 @@ -8543,6 +8543,15 @@ .addReg(0); MIB = BuildMI(BB, DL, TII->get(X86::CALL64m)); addDirectMem(MIB, X86::RDI).addReg(0); + } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { + MachineInstrBuilder MIB = BuildMI(BB, DL, TII->get(X86::MOV32rm), X86::EAX) + .addReg(0) + .addImm(0).addReg(0) + .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, + MI->getOperand(3).getTargetFlags()) + .addReg(0); + MIB = BuildMI(BB, DL, TII->get(X86::CALL32m)); + addDirectMem(MIB, X86::EAX).addReg(0); } else { MachineInstrBuilder MIB = BuildMI(BB, DL, TII->get(X86::MOV32rm), X86::EAX) .addReg(TII->getGlobalBaseReg(F)) From isanbard at gmail.com Tue Jun 15 18:46:31 2010 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 15 Jun 2010 23:46:31 -0000 Subject: [llvm-commits] [llvm] r106066 - in /llvm/trunk: lib/CodeGen/MachineSink.cpp lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/MachineSink-CritEdge.ll Message-ID: <20100615234631.7B3142A6C12C@llvm.org> Author: void Date: Tue Jun 15 18:46:31 2010 New Revision: 106066 URL: http://llvm.org/viewvc/llvm-project?rev=106066&view=rev Log: Create a more targeted fix for not sinking instructions into a range where it will conflict with another live range. The place which creates this scenerio is the code in X86 that lowers a select instruction by splitting the MBBs. This eliminates the need to check from the bottom up in an MBB for live pregs. Modified: llvm/trunk/lib/CodeGen/MachineSink.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/test/CodeGen/X86/MachineSink-CritEdge.ll Modified: llvm/trunk/lib/CodeGen/MachineSink.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineSink.cpp?rev=106066&r1=106065&r2=106066&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineSink.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineSink.cpp Tue Jun 15 18:46:31 2010 @@ -25,7 +25,6 @@ #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" -#include "llvm/ADT/SmallSet.h" #include "llvm/ADT/Statistic.h" #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" @@ -62,7 +61,6 @@ bool ProcessBlock(MachineBasicBlock &MBB); bool SinkInstruction(MachineInstr *MI, bool &SawStore); bool AllUsesDominatedByBlock(unsigned Reg, MachineBasicBlock *MBB) const; - bool LiveOutOfBasicBlock(const MachineInstr *MI, unsigned Reg) const; }; } // end anonymous namespace @@ -168,44 +166,6 @@ return MadeChange; } -/// LiveOutOfBasicBlock - Determine if the physical register, defined and dead -/// in MI, is live on exit from the basic block. -bool MachineSinking::LiveOutOfBasicBlock(const MachineInstr *MI, - unsigned Reg) const { - assert(TargetRegisterInfo::isPhysicalRegister(Reg) && - "Only want to determine if a physical register is live out of a BB!"); - - const MachineBasicBlock *MBB = MI->getParent(); - SmallSet KilledRegs; - MachineBasicBlock::const_iterator I = MBB->end(); - MachineBasicBlock::const_iterator E = MBB->begin(); - assert(I != E && "How can there be an empty block at this point?!"); - - // Loop through the instructions bottom-up. If we see a kill of the preg - // first, then it's not live out of the BB. If we see a use or def first, then - // we assume that it is live out of the BB. - do { - const MachineInstr &CurMI = *--I; - - for (unsigned i = 0, e = CurMI.getNumOperands(); i != e; ++i) { - const MachineOperand &MO = CurMI.getOperand(i); - if (!MO.isReg()) continue; // Ignore non-register operands. - - unsigned MOReg = MO.getReg(); - if (MOReg == 0) continue; - - if (MOReg == Reg) { - if (MO.isKill()) - return false; - if (MO.isUse() || MO.isDef()) - return true; - } - } - } while (I != E); - - return false; -} - /// SinkInstruction - Determine whether it is safe to sink the specified machine /// instruction out of its current block into a successor. bool MachineSinking::SinkInstruction(MachineInstr *MI, bool &SawStore) { @@ -228,7 +188,6 @@ // SuccToSinkTo - This is the successor to sink this instruction to, once we // decide. MachineBasicBlock *SuccToSinkTo = 0; - SmallVector PhysRegs; for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); @@ -257,12 +216,9 @@ if (AllocatableSet.test(AliasReg)) return false; } - } else { - if (!MO.isDead()) - // A def that isn't dead. We can't move it. - return false; - else - PhysRegs.push_back(Reg); + } else if (!MO.isDead()) { + // A def that isn't dead. We can't move it. + return false; } } else { // Virtual register uses are always safe to sink. @@ -329,10 +285,14 @@ // If the instruction to move defines a dead physical register which is live // when leaving the basic block, don't move it because it could turn into a // "zombie" define of that preg. E.g., EFLAGS. () - for (SmallVectorImpl::const_iterator - I = PhysRegs.begin(), E = PhysRegs.end(); I != E; ++I) - if (LiveOutOfBasicBlock(MI, *I)) + for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) { + const MachineOperand &MO = MI->getOperand(I); + if (!MO.isReg()) continue; + unsigned Reg = MO.getReg(); + if (Reg == 0 || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue; + if (SuccToSinkTo->isLiveIn(Reg)) return false; + } DEBUG(dbgs() << "Sink instr " << *MI << "\tinto block " << *SuccToSinkTo); Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=106066&r1=106065&r2=106066&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Jun 15 18:46:31 2010 @@ -8465,22 +8465,42 @@ MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); unsigned Opc = X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); + BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB); F->insert(It, copy0MBB); F->insert(It, sinkMBB); + // Update machine-CFG edges by first adding all successors of the current // block to the new block which will contain the Phi node for the select. for (MachineBasicBlock::succ_iterator I = BB->succ_begin(), E = BB->succ_end(); I != E; ++I) sinkMBB->addSuccessor(*I); + // Next, remove all successors of the current block, and add the true // and fallthrough blocks as its successors. while (!BB->succ_empty()) BB->removeSuccessor(BB->succ_begin()); + // Add the true and fallthrough blocks as its successors. BB->addSuccessor(copy0MBB); BB->addSuccessor(sinkMBB); + // If the EFLAGS register isn't dead in the terminator, then claim that it's + // live into the sink and copy blocks. + const MachineFunction *MF = BB->getParent(); + const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); + BitVector ReservedRegs = TRI->getReservedRegs(*MF); + const MachineInstr *Term = BB->getFirstTerminator(); + + for (unsigned I = 0, E = Term->getNumOperands(); I != E; ++I) { + const MachineOperand &MO = Term->getOperand(I); + if (!MO.isReg() || MO.isKill() || MO.isDead()) continue; + unsigned Reg = MO.getReg(); + if (Reg != X86::EFLAGS) continue; + copy0MBB->addLiveIn(Reg); + sinkMBB->addLiveIn(Reg); + } + // copy0MBB: // %FalseValue = ... // # fallthrough to sinkMBB Modified: llvm/trunk/test/CodeGen/X86/MachineSink-CritEdge.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/MachineSink-CritEdge.ll?rev=106066&r1=106065&r2=106066&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/MachineSink-CritEdge.ll (original) +++ llvm/trunk/test/CodeGen/X86/MachineSink-CritEdge.ll Tue Jun 15 18:46:31 2010 @@ -1,10 +1,4 @@ ; RUN: llc < %s | FileCheck %s -; XFAIL: * -; -; See . This test isn't valid after we made machine -; sinking more conservative about sinking instructions that define a preg into a -; block when we don't know if the preg is killed within the current block. - target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-apple-darwin10.0.0" From stoklund at 2pi.dk Tue Jun 15 19:13:06 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 15 Jun 2010 17:13:06 -0700 Subject: [llvm-commits] [llvm] r106066 - in /llvm/trunk: lib/CodeGen/MachineSink.cpp lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/MachineSink-CritEdge.ll In-Reply-To: <20100615234631.7B3142A6C12C@llvm.org> References: <20100615234631.7B3142A6C12C@llvm.org> Message-ID: <532AD9F7-E201-4FD1-8EAE-3FB93C19FCE2@2pi.dk> On Jun 15, 2010, at 4:46 PM, Bill Wendling wrote: > Author: void > Date: Tue Jun 15 18:46:31 2010 > New Revision: 106066 > > URL: http://llvm.org/viewvc/llvm-project?rev=106066&view=rev > Log: > Create a more targeted fix for not sinking instructions into a range where it > will conflict with another live range. The place which creates this scenerio is > the code in X86 that lowers a select instruction by splitting the MBBs. This > eliminates the need to check from the bottom up in an MBB for live pregs. Looks good to me. > @@ -329,10 +285,14 @@ > // If the instruction to move defines a dead physical register which is live > // when leaving the basic block, don't move it because it could turn into a > // "zombie" define of that preg. E.g., EFLAGS. () > - for (SmallVectorImpl::const_iterator > - I = PhysRegs.begin(), E = PhysRegs.end(); I != E; ++I) > - if (LiveOutOfBasicBlock(MI, *I)) > + for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) { > + const MachineOperand &MO = MI->getOperand(I); > + if (!MO.isReg()) continue; > + unsigned Reg = MO.getReg(); > + if (Reg == 0 || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue; > + if (SuccToSinkTo->isLiveIn(Reg)) > return false; > + } This loop catches both physreg defs and uses. That is on purpose, right? The comment doesn't mention uses. /jakob From echristo at apple.com Tue Jun 15 19:26:36 2010 From: echristo at apple.com (Eric Christopher) Date: Wed, 16 Jun 2010 00:26:36 -0000 Subject: [llvm-commits] [llvm] r106072 - /llvm/trunk/lib/MC/MachObjectWriter.cpp Message-ID: <20100616002636.E5FD82A6C12C@llvm.org> Author: echristo Date: Tue Jun 15 19:26:36 2010 New Revision: 106072 URL: http://llvm.org/viewvc/llvm-project?rev=106072&view=rev Log: Fix indentation. Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MachObjectWriter.cpp?rev=106072&r1=106071&r2=106072&view=diff ============================================================================== --- llvm/trunk/lib/MC/MachObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/MachObjectWriter.cpp Tue Jun 15 19:26:36 2010 @@ -739,10 +739,10 @@ } void RecordTLVPRelocation(const MCAssembler &Asm, - const MCAsmLayout &Layout, - const MCFragment *Fragment, - const MCFixup &Fixup, MCValue Target, - uint64_t &FixedValue) { + const MCAsmLayout &Layout, + const MCFragment *Fragment, + const MCFixup &Fixup, MCValue Target, + uint64_t &FixedValue) { assert(Target.getSymA()->getKind() == MCSymbolRefExpr::VK_TLVP && !Is64Bit && "Should only be called with a 32-bit TLVP relocation!"); From echristo at apple.com Tue Jun 15 19:27:31 2010 From: echristo at apple.com (Eric Christopher) Date: Wed, 16 Jun 2010 00:27:31 -0000 Subject: [llvm-commits] [llvm] r106073 - /llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Message-ID: <20100616002731.220132A6C12C@llvm.org> Author: echristo Date: Tue Jun 15 19:27:30 2010 New Revision: 106073 URL: http://llvm.org/viewvc/llvm-project?rev=106073&view=rev Log: Don't emit the linkage for initializer label for mach-o tls. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=106073&r1=106072&r2=106073&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Tue Jun 15 19:27:30 2010 @@ -330,7 +330,6 @@ else if (GVKind.isThreadData()) { OutStreamer.SwitchSection(TheSection); - EmitLinkage(GV->getLinkage(), MangSym); EmitAlignment(AlignLog, GV); OutStreamer.EmitLabel(MangSym); From dpatel at apple.com Tue Jun 15 19:53:55 2010 From: dpatel at apple.com (Devang Patel) Date: Wed, 16 Jun 2010 00:53:55 -0000 Subject: [llvm-commits] [llvm] r106075 - in /llvm/trunk: include/llvm/Module.h lib/Analysis/DebugInfo.cpp lib/CodeGen/AsmPrinter/DwarfDebug.cpp lib/VMCore/Module.cpp Message-ID: <20100616005355.C0B432A6C12D@llvm.org> Author: dpatel Date: Tue Jun 15 19:53:55 2010 New Revision: 106075 URL: http://llvm.org/viewvc/llvm-project?rev=106075&view=rev Log: Use separate named MDNode to hold each function's local variable info. This speeds up local variable handling in DwarfDebug. Modified: llvm/trunk/include/llvm/Module.h llvm/trunk/lib/Analysis/DebugInfo.cpp llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp llvm/trunk/lib/VMCore/Module.cpp Modified: llvm/trunk/include/llvm/Module.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Module.h?rev=106075&r1=106074&r2=106075&view=diff ============================================================================== --- llvm/trunk/include/llvm/Module.h (original) +++ llvm/trunk/include/llvm/Module.h Tue Jun 15 19:53:55 2010 @@ -326,6 +326,7 @@ /// specified name. This method returns null if a NamedMDNode with the /// specified name is not found. NamedMDNode *getNamedMetadata(StringRef Name) const; + NamedMDNode *getNamedMetadataUsingTwine(Twine Name) const; /// getOrInsertNamedMetadata - Return the first named MDNode in the module /// with the specified name. This method returns a new NamedMDNode if a Modified: llvm/trunk/lib/Analysis/DebugInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DebugInfo.cpp?rev=106075&r1=106074&r2=106075&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/DebugInfo.cpp (original) +++ llvm/trunk/lib/Analysis/DebugInfo.cpp Tue Jun 15 19:53:55 2010 @@ -1053,8 +1053,12 @@ // The optimizer may remove local variable. If there is an interest // to preserve variable info in such situation then stash it in a // named mdnode. - NamedMDNode *NMD = M.getOrInsertNamedMetadata("llvm.dbg.lv"); - NMD->addOperand(Node); + DISubprogram Fn(getDISubprogram(Context)); + const Twine FnLVName = Twine("llvm.dbg.lv.", Fn.getName()); + NamedMDNode *FnLocals = M.getNamedMetadataUsingTwine(FnLVName); + if (!FnLocals) + FnLocals = NamedMDNode::Create(VMContext, FnLVName, NULL, 0, &M); + FnLocals->addOperand(Node); } return DIVariable(Node); } Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=106075&r1=106074&r2=106075&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Tue Jun 15 19:53:55 2010 @@ -2259,8 +2259,9 @@ } // Collect info for variables that were optimized out. - if (NamedMDNode *NMD = - MF->getFunction()->getParent()->getNamedMetadata("llvm.dbg.lv")) { + const Twine FnLVName = Twine("llvm.dbg.lv.", MF->getFunction()->getName()); + if (NamedMDNode *NMD = + MF->getFunction()->getParent()->getNamedMetadataUsingTwine(FnLVName)) { for (unsigned i = 0, e = NMD->getNumOperands(); i != e; ++i) { DIVariable DV(cast_or_null(NMD->getOperand(i))); if (!DV || !Processed.insert(DV)) Modified: llvm/trunk/lib/VMCore/Module.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Module.cpp?rev=106075&r1=106074&r2=106075&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Module.cpp (original) +++ llvm/trunk/lib/VMCore/Module.cpp Tue Jun 15 19:53:55 2010 @@ -17,6 +17,7 @@ #include "llvm/DerivedTypes.h" #include "llvm/GVMaterializer.h" #include "llvm/LLVMContext.h" +#include "llvm/ADT/SmallString.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringExtras.h" #include "llvm/Support/LeakDetector.h" @@ -316,6 +317,12 @@ return NamedMDSymTab->lookup(Name); } +NamedMDNode *Module::getNamedMetadataUsingTwine(Twine Name) const { + SmallString<256> NameData; + StringRef NameRef = Name.toStringRef(NameData); + return NamedMDSymTab->lookup(NameRef); +} + /// getOrInsertNamedMetadata - Return the first named MDNode in the module /// with the specified name. This method returns a new NamedMDNode if a /// NamedMDNode with the specified name is not found. From daniel at zuster.org Tue Jun 15 20:53:42 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 16 Jun 2010 01:53:42 -0000 Subject: [llvm-commits] [test-suite] r106077 - /test-suite/trunk/Makefile.programs Message-ID: <20100616015342.DAF212A6C12C@llvm.org> Author: ddunbar Date: Tue Jun 15 20:53:42 2010 New Revision: 106077 URL: http://llvm.org/viewvc/llvm-project?rev=106077&view=rev Log: Sigh, fix a shell quoting issue when calling DiffOutput under RunToolSafely. Modified: test-suite/trunk/Makefile.programs Modified: test-suite/trunk/Makefile.programs URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/Makefile.programs?rev=106077&r1=106076&r2=106077&view=diff ============================================================================== --- test-suite/trunk/Makefile.programs (original) +++ test-suite/trunk/Makefile.programs Tue Jun 15 20:53:42 2010 @@ -69,7 +69,7 @@ # loop on some inputs, which blocks testing some historical revisions. We can # remove this once we build our own test tools. DIFFPROG := $(PROGDIR)/RunToolSafely.sh 60 \ - $(PROGDIR)/DiffOutput.sh "$(LLVMTOOLCURRENT)/fpcmp $(TOLERANCEOPT)" + $(PROGDIR)/DiffOutput.sh "\"$(LLVMTOOLCURRENT)/fpcmp $(TOLERANCEOPT)\"" # RUNTIMELIMIT - The number of seconds we should wait before certain events # timeout. This is overridable on the commandline or in tests makefiles. From isanbard at gmail.com Tue Jun 15 23:31:34 2010 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 15 Jun 2010 21:31:34 -0700 Subject: [llvm-commits] [llvm] r106066 - in /llvm/trunk: lib/CodeGen/MachineSink.cpp lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/MachineSink-CritEdge.ll In-Reply-To: <532AD9F7-E201-4FD1-8EAE-3FB93C19FCE2@2pi.dk> References: <20100615234631.7B3142A6C12C@llvm.org> <532AD9F7-E201-4FD1-8EAE-3FB93C19FCE2@2pi.dk> Message-ID: On Jun 15, 2010, at 5:13 PM, Jakob Stoklund Olesen wrote: > > On Jun 15, 2010, at 4:46 PM, Bill Wendling wrote: > >> Author: void >> Date: Tue Jun 15 18:46:31 2010 >> New Revision: 106066 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=106066&view=rev >> Log: >> Create a more targeted fix for not sinking instructions into a range where it >> will conflict with another live range. The place which creates this scenerio is >> the code in X86 that lowers a select instruction by splitting the MBBs. This >> eliminates the need to check from the bottom up in an MBB for live pregs. > > Looks good to me. > >> @@ -329,10 +285,14 @@ >> // If the instruction to move defines a dead physical register which is live >> // when leaving the basic block, don't move it because it could turn into a >> // "zombie" define of that preg. E.g., EFLAGS. () >> - for (SmallVectorImpl::const_iterator >> - I = PhysRegs.begin(), E = PhysRegs.end(); I != E; ++I) >> - if (LiveOutOfBasicBlock(MI, *I)) >> + for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) { >> + const MachineOperand &MO = MI->getOperand(I); >> + if (!MO.isReg()) continue; >> + unsigned Reg = MO.getReg(); >> + if (Reg == 0 || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue; >> + if (SuccToSinkTo->isLiveIn(Reg)) >> return false; >> + } > > This loop catches both physreg defs and uses. That is on purpose, right? The comment doesn't mention uses. > Yes. It would be bad to move either a def or use into the live range it's not meant to inhabit. I'll modify the comment. Thanks! -bw From daniel at zuster.org Wed Jun 16 00:24:17 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 16 Jun 2010 05:24:17 -0000 Subject: [llvm-commits] [zorg] r106079 - in /zorg/trunk/lnt/lnt: util/stats.py viewer/simple.ptl Message-ID: <20100616052417.7DEDE2A6C12C@llvm.org> Author: ddunbar Date: Wed Jun 16 00:24:17 2010 New Revision: 106079 URL: http://llvm.org/viewvc/llvm-project?rev=106079&view=rev Log: LNT/simple: Move some code into lnt.util.stats. Added: zorg/trunk/lnt/lnt/util/stats.py Modified: zorg/trunk/lnt/lnt/viewer/simple.ptl Added: zorg/trunk/lnt/lnt/util/stats.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/util/stats.py?rev=106079&view=auto ============================================================================== --- zorg/trunk/lnt/lnt/util/stats.py (added) +++ zorg/trunk/lnt/lnt/util/stats.py Wed Jun 16 00:24:17 2010 @@ -0,0 +1,21 @@ +import math + +def mean(l): + return sum(l)/len(l) + +def median(l): + l = list(l) + l.sort() + N = len(l) + return (l[(N-1)//2] + l[N//2])*.5 + +def median_absolute_deviation(l, med = None): + if med is None: + med = median(l) + return median([abs(x - med) for x in l]) + +def standard_deviation(l): + m = mean(l) + means_sqrd = sum([(v - m)**2 for v in l]) / len(l) + rms = math.sqrt(means_sqrd) + return rms Modified: zorg/trunk/lnt/lnt/viewer/simple.ptl URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/viewer/simple.ptl?rev=106079&r1=106078&r2=106079&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/viewer/simple.ptl (original) +++ zorg/trunk/lnt/lnt/viewer/simple.ptl Wed Jun 16 00:24:17 2010 @@ -4,7 +4,6 @@ Nightly Test UI instance for actual nightly test data. """ -import math import sys import time @@ -13,6 +12,7 @@ from quixote.errors import TraversalError from lnt.db import perfdbsummary +from lnt.util import stats import Util from Util import safediv @@ -20,26 +20,6 @@ from PerfDB import Machine, Run, RunInfo, Test -def mean(l): - return sum(l)/len(l) - -def median(l): - l = list(l) - l.sort() - N = len(l) - return (l[(N-1)//2] + l[N//2])*.5 - -def median_absolute_deviation(l, med = None): - if med is None: - med = median(l) - return median([abs(x - med) for x in l]) - -def standard_deviation(l): - m = mean(l) - means_sqrd = sum([(v - m)**2 for v in l]) / len(l) - rms = math.sqrt(means_sqrd) - return rms - class SimpleRunUI(Directory): _q_exports = ["", "graph"] @@ -308,8 +288,8 @@ else: points_data.append((x, min_value)) if show_mad_error: - med = median(values) - mad = median_absolute_deviation(values, med) + med = stats.median(values) + mad = stats.median_absolute_deviation(values, med) errorbar_data.append((x, med - mad, med + mad)) points.append((x, min_value, mad, med)) data.sort() @@ -596,7 +576,7 @@ for v in sample_map.get((run_id, test.id), ())] if previous_values: - sd_value = standard_deviation(previous_values) + sd_value = stats.standard_deviation(previous_values) sd_cell_value = "%.4f" % sd_value else: sd_cell_value = "-" @@ -608,7 +588,7 @@ for v in sample_map.get((run_id, test.id), ())] if previous_values: - mad_value = median_absolute_deviation(previous_values) + mad_value = stats.median_absolute_deviation(previous_values) mad_cell_value = "%.4f" % mad_value else: mad_cell_value = "-" From daniel at zuster.org Wed Jun 16 00:24:21 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 16 Jun 2010 05:24:21 -0000 Subject: [llvm-commits] [zorg] r106080 - in /zorg/trunk/lnt/lnt: db/runinfo.py viewer/simple.ptl Message-ID: <20100616052421.A20C62A6C12D@llvm.org> Author: ddunbar Date: Wed Jun 16 00:24:21 2010 New Revision: 106080 URL: http://llvm.org/viewvc/llvm-project?rev=106080&view=rev Log: LNT/simple: Add SimpleRunInfo, to standardize collecting pass/fail information about a run. - This moves 'simple' style runs to compute significant changes based on the standard deviation of the previous samples. This will hopefully allow us to eliminate the noise from nightly test reports. - This also updates the LNT/simple viewer to make it easier to see the interesting changes: o Use buildbot style red/green/yellow to report regressions, improvements, or persistent failures. o By default, only show significant performance changes, and ignore cases when the test changes from pass to fail or vice versa. Added: zorg/trunk/lnt/lnt/db/runinfo.py Modified: zorg/trunk/lnt/lnt/viewer/simple.ptl Added: zorg/trunk/lnt/lnt/db/runinfo.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/db/runinfo.py?rev=106080&view=auto ============================================================================== --- zorg/trunk/lnt/lnt/db/runinfo.py (added) +++ zorg/trunk/lnt/lnt/db/runinfo.py Wed Jun 16 00:24:21 2010 @@ -0,0 +1,199 @@ +from lnt.util import stats +from lnt.viewer import Util +from lnt.viewer.PerfDB import Sample + +REGRESSED = 0 +IMPROVED = 1 +UNCHANGED_PASS = 2 +UNCHANGED_FAIL = 3 + +class ComparisonResult: + def __init__(self, cur_value, prev_value, delta, pct_delta, stddev, MAD, + cur_failed, prev_failed): + self.current = cur_value + self.previous = prev_value + self.delta = delta + self.pct_delta = pct_delta + self.stddev = stddev + self.MAD = MAD + self.failed = cur_failed + self.prev_failed = prev_failed + + def get_test_status(self): + # Compute the comparison status for the test success. + if self.failed: + if self.prev_failed: + return UNCHANGED_FAIL + else: + return REGRESSED + else: + if self.prev_failed: + return IMPROVED + else: + return UNCHANGED_PASS + + def get_value_status(self, confidence_interval=1.96, value_precision=0.01): + if self.current is None or self.previous is None: + return None + + # Don't report value errors for tests which fail, or which just started + # passing. + # + # FIXME: One bug here is that we risk losing performance data on tests + # which flop to failure then back. What would be nice to do here is to + # find the last value in a passing run, or to move to using proper keyed + # reference runs. + if self.failed: + return UNCHANGED_FAIL + elif self.prev_failed: + return UNCHANGED_PASS + + # Ignore tests whose delt is too small relative to the precision we can + # sample at; otherwise quantization means that we can't measure the + # standard deviation with enough accuracy. + if abs(self.delta) <= value_precision * confidence_interval: + if self.failed: + return UNCHANGED_FAIL + else: + return UNCHANGED_PASS + + # If we have a comparison window, then measure using a symmetic + # confidence interval. + if self.stddev is not None: + if abs(self.delta) > self.stddev * confidence_interval: + if self.delta < 0: + return IMPROVED + else: + return REGRESSED + else: + if self.failed: + return UNCHANGED_FAIL + else: + return UNCHANGED_PASS + + # Otherwise, use the old "significant change" metric of > 5%. + if abs(self.pct_delta) >= .05: + if self.pct_delta < 0: + return IMPROVED + else: + return REGRESSED + else: + if self.failed: + return UNCHANGED_FAIL + else: + return UNCHANGED_PASS + +class SimpleRunInfo: + def __init__(self, db, test_suite_summary): + self.db = db + self.test_suite_summary = test_suite_summary + + self.sample_map = Util.multidict() + self.loaded_samples = set() + + def get_run_comparison_result(self, run, compare_to, test_name, pset, + comparison_window=[]): + # Get the test. + test = self.test_suite_summary.test_map.get((test_name, pset)) + if test is None: + return ComparisonResult(run_value=None, prev_value=None, delta=None, + pct_delta=None, stddev=None, MAD=None, + cur_failed=None, prev_failed=None) + + # Get the test status info. + status_info = self.test_suite_summary.test_status_map.get(test_name) + if status_info is not None: + status_name,status_kind = status_info + status_test = self.test_suite_summary.test_map.get( + (status_name, pset)) + else: + status_test = status_kind = None + + # Load the sample data for the current and previous runs and the + # comparison window. + if compare_to is None: + compare_id = None + else: + compare_id = compare_to.id + runs_to_load = set(comparison_window) + runs_to_load.add(run.id) + if compare_id is not None: + runs_to_load.add(compare_id) + self._load_samples_for_runs(runs_to_load) + + # Lookup the current and previous values. + run_values = self.sample_map.get((run.id, test.id)) + prev_values = self.sample_map.get((compare_id, test.id)) + + # Determine whether this (test,pset) passed or failed in the current and + # previous runs. + run_failed = prev_failed = False + if not status_test: + run_failed = not run_values + prev_failed = not prev_values + else: + run_status = self.sample_map.get((run.id,status_test.id)) + prev_status = self.sample_map.get((compare_id,status_test.id)) + + # FIXME: Support XFAILs. + # + # FIXME: What to do about the multiple entries here. We could start + # by just treating non-matching samples as errors. + if status_kind == False: # .success style + run_failed = not run_status or not run_status[0] + prev_failed = not prev_status or not prev_status[0] + else: + run_failed = run_status and run_status[0] != 0 + prev_failed = prev_status and prev_status[0] != 0 + + # Get the current and previous values. + if run_values: + run_value = min(run_values) + else: + run_value = None + if prev_values: + prev_value = min(prev_values) + else: + prev_value = None + + # If we are missing current or comparison values we are done. + if run_value is None or prev_value is None: + return ComparisonResult( + run_value, prev_value, delta=None, + pct_delta=None, stddev=None, MAD=None, + cur_failed=run_failed, prev_failed=prev_failed) + + # Compute the comparison status for the test value. + delta = run_value - prev_value + if prev_value != 0: + pct_delta = delta / prev_value + else: + pct_delta = 0.0 + + # Get all previous values in the comparison window. + prev_values = [v for run_id in comparison_window + for v in self.sample_map.get((run_id, test.id), ())] + if prev_values: + stddev = stats.standard_deviation(prev_values) + MAD = stats.median_absolute_deviation(prev_values) + else: + stddev = None + MAD = None + + return ComparisonResult(run_value, prev_value, delta, + pct_delta, stddev, MAD, + run_failed, prev_failed) + + def _load_samples_for_runs(self, runs): + # Find the set of new runs to load. + to_load = set(runs) - self.loaded_samples + if not to_load: + return + + q = self.db.session.query(Sample.value, Sample.run_id, Sample.test_id) + q = q.filter(Sample.run_id.in_(to_load)) + for value,run_id,test_id in q: + self.sample_map[(run_id,test_id)] = value + + self.loaded_samples |= to_load + Modified: zorg/trunk/lnt/lnt/viewer/simple.ptl URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/viewer/simple.ptl?rev=106080&r1=106079&r2=106080&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/viewer/simple.ptl (original) +++ zorg/trunk/lnt/lnt/viewer/simple.ptl Wed Jun 16 00:24:21 2010 @@ -11,6 +11,7 @@ from quixote.directory import Directory from quixote.errors import TraversalError +from lnt.db import runinfo from lnt.db import perfdbsummary from lnt.util import stats @@ -459,94 +460,63 @@ self.show_run_page(db, run, run_summary, compare_to, graph_body) def _q_index_body [html] (self, db, run, run_summary, compare_to): - # Find the tests. The simple UI maps all tests that start with - # 'simple.'. - # - # One sensible addition would be to allow 'simple.foo.success' as a test - # to indicate the success or failure of the test. We would assume that - # the test succeeded if its .success test was missing, which leads to a - # nice compact format (failures are expected to be rare). - - if compare_to: - prev_id = compare_to.id - interesting_runs = [run.id, prev_id] - else: - prev_id = None - interesting_runs = [run.id] - # Load the test suite summary. ts_summary = perfdbsummary.get_simple_suite_summary(db, self.tag) + sri = runinfo.SimpleRunInfo(db, ts_summary) - cur_id = run.id - previous_runs = [] + # Get the filtering form. + form = quixote.form.Form(method=str("get")) + form.add(quixote.form.CheckboxWidget, "show_delta", + title="Show Delta") + form.add(quixote.form.CheckboxWidget, "show_stddev", + title="Show Standard Deviation") + form.add(quixote.form.CheckboxWidget, "show_mad", + title="Show Median Absolute Deviation") + form.add(quixote.form.CheckboxWidget, "show_all", + title="Show All Values") + form.add(quixote.form.IntWidget, "num_comparison_runs", + title="Number of Comparison Runs") + form.add_submit("submit", "Update") request = quixote.get_request() - show_delta = bool(request.form.get('show_delta')) - show_stddev = bool(request.form.get('show_stddev')) - show_mad = bool(request.form.get('show_mad')) - - if show_stddev or show_mad: - for i in range(5): - cur_id = run_summary.get_previous_run_on_machine(cur_id) - if not cur_id: - break - - previous_runs.append(cur_id) - if cur_id not in interesting_runs: - interesting_runs.append(cur_id) - - interesting_runs = tuple(set(interesting_runs + previous_runs)) - - # Load the run sample data. - q = db.session.query(Sample.value, Sample.run_id, Sample.test_id) - q = q.filter(Sample.run_id.in_(interesting_runs)) - - sample_map = Util.multidict() - for value,run_id,test_id in q: - key = (run_id,test_id) - sample_map[key] = value + show_delta = bool(form['show_delta']) + show_stddev = bool(form['show_stddev']) + show_mad = bool(form['show_mad']) + show_all = bool(form['show_all']) + try: + num_comparison_runs = int(form['num_comparison_runs']) + except: + num_comparison_runs = 5 - # Render the page. + self.renderPopupBegin('view_options', 'View Options', True) + form.render() + self.renderPopupEnd() - def get_cell_value [html] (test, status_test, status_kind, name, pset): - run_values = sample_map.get((run.id,test.id)) - prev_values = sample_map.get((prev_id,test.id)) - - # Determine whether this (test,pset) passed or failed in the current - # and previous runs. - run_failed = prev_failed = False - if not status_test: - run_failed = not run_values - prev_failed = not prev_values - else: - run_status = sample_map.get((run.id,status_test.id)) - prev_status = sample_map.get((prev_id,status_test.id)) + # Gather the runs to use for statistical data. + cur_id = run.id + comparison_window = [] + for i in range(num_comparison_runs): + cur_id = run_summary.get_previous_run_on_machine(cur_id) + if not cur_id: + break + comparison_window.append(cur_id) - # FIXME: What to do about the multiple entries here. We could - # start by just treating non-matching samples as errors. - if status_kind == False: # .success style - run_failed = not run_status or not run_status[0] - prev_failed = not prev_status or not prev_status[0] - else: - run_failed = run_status and run_status[0] != 0 - prev_failed = prev_status and prev_status[0] != 0 + # Render the page. + def get_cell_value [html] (cr): + test_status = cr.get_test_status() + value_status = cr.get_value_status() run_cell_value = "-" - if run_values: - run_value = min(run_values) - run_cell_value = "%.4f" % run_value - else: - run_value = None + if cr.current is not None: + run_cell_value = "%.4f" % cr.current cell_color = None - if run_failed: - if prev_failed: - cell_color = (255,195,67) - else: - cell_color = (233,128,128) - else: - if prev_failed: - cell_color = (143,223,95) + if test_status == runinfo.REGRESSED: + cell_color = (233,128,128) + elif test_status == runinfo.IMPROVED: + cell_color = (143,223,95) + elif test_status == runinfo.UNCHANGED_FAIL: + cell_color = (255,195,67) if cell_color: """ @@ -556,44 +526,27 @@ """ """ - prev_value = None if show_delta: - if prev_value is not None and run_value is not None: - """""" % (run_value - prev_value) + if cr.delta is not None: + """""" % cr.delta else: """""" - if show_stddev: - previous_values = [v for run_id in previous_runs - for v in sample_map.get((run_id, - test.id), ())] - if previous_values: - sd_value = stats.standard_deviation(previous_values) - sd_cell_value = "%.4f" % sd_value + if cr.stddev is not None: + """""" % cr.stddev else: - sd_cell_value = "-" - """ - """ if show_mad: - previous_values = [v for run_id in previous_runs - for v in sample_map.get((run_id, - test.id), ())] - if previous_values: - mad_value = stats.median_absolute_deviation(previous_values) - mad_cell_value = "%.4f" % mad_value + if cr.MAD is not None: + """""" % cr.MAD else: - mad_cell_value = "-" - """ - """ """

Parameter Sets

@@ -660,19 +613,9 @@ """ % (name, name) for pset in ts_summary.parameter_sets: - test = ts_summary.test_map.get((name,pset)) - if test is None: - """ - """ - continue - - status_info = ts_summary.test_status_map.get(name) - if status_info: - status_name,status_kind = status_info - status_test = ts_summary.test_map.get((status_name,pset)) - else: - status_test = status_kind = None - get_cell_value(test, status_test, status_kind, name, pset) + cr = sri.get_run_comparison_result(run, compare_to, name, pset, + comparison_window) + get_cell_value(cr) """ """ """ From jmolenda at apple.com Tue Jun 15 20:02:34 2010 From: jmolenda at apple.com (Jason Molenda) Date: Tue, 15 Jun 2010 18:02:34 -0700 Subject: [llvm-commits] I'd like to add a few constants to the Support/Dwarf.h file Message-ID: <2FCF8E0E-FB23-43D5-8ECA-9EC4C6C9F2A4@apple.com> There are several places in lldb where we have big switch statements to handle dwarf constants; we need all of the intermediate values defined if we're going to share llvm's Dwarf constants header file. OK to commit? Index: Dwarf.h =================================================================== --- Dwarf.h (revision 106065) +++ Dwarf.h (working copy) @@ -300,12 +300,99 @@ DW_OP_ne = 0x2e, DW_OP_lit0 = 0x30, DW_OP_lit1 = 0x31, + DW_OP_lit2 = 0x32, + DW_OP_lit3 = 0x33, + DW_OP_lit4 = 0x34, + DW_OP_lit5 = 0x35, + DW_OP_lit6 = 0x36, + DW_OP_lit7 = 0x37, + DW_OP_lit8 = 0x38, + DW_OP_lit9 = 0x39, + DW_OP_lit10 = 0x3a, + DW_OP_lit11 = 0x3b, + DW_OP_lit12 = 0x3c, + DW_OP_lit13 = 0x3d, + DW_OP_lit14 = 0x3e, + DW_OP_lit15 = 0x3f, + DW_OP_lit16 = 0x40, + DW_OP_lit17 = 0x41, + DW_OP_lit18 = 0x42, + DW_OP_lit19 = 0x43, + DW_OP_lit20 = 0x44, + DW_OP_lit21 = 0x45, + DW_OP_lit22 = 0x46, + DW_OP_lit23 = 0x47, + DW_OP_lit24 = 0x48, + DW_OP_lit25 = 0x49, + DW_OP_lit26 = 0x4a, + DW_OP_lit27 = 0x4b, + DW_OP_lit28 = 0x4c, + DW_OP_lit29 = 0x4d, + DW_OP_lit30 = 0x4e, DW_OP_lit31 = 0x4f, DW_OP_reg0 = 0x50, DW_OP_reg1 = 0x51, + DW_OP_reg2 = 0x52, + DW_OP_reg3 = 0x53, + DW_OP_reg4 = 0x54, + DW_OP_reg5 = 0x55, + DW_OP_reg6 = 0x56, + DW_OP_reg7 = 0x57, + DW_OP_reg8 = 0x58, + DW_OP_reg9 = 0x59, + DW_OP_reg10 = 0x5a, + DW_OP_reg11 = 0x5b, + DW_OP_reg12 = 0x5c, + DW_OP_reg13 = 0x5d, + DW_OP_reg14 = 0x5e, + DW_OP_reg15 = 0x5f, + DW_OP_reg16 = 0x60, + DW_OP_reg17 = 0x61, + DW_OP_reg18 = 0x62, + DW_OP_reg19 = 0x63, + DW_OP_reg20 = 0x64, + DW_OP_reg21 = 0x65, + DW_OP_reg22 = 0x66, + DW_OP_reg23 = 0x67, + DW_OP_reg24 = 0x68, + DW_OP_reg25 = 0x69, + DW_OP_reg26 = 0x6a, + DW_OP_reg27 = 0x6b, + DW_OP_reg28 = 0x6c, + DW_OP_reg29 = 0x6d, + DW_OP_reg30 = 0x6e, DW_OP_reg31 = 0x6f, DW_OP_breg0 = 0x70, DW_OP_breg1 = 0x71, + DW_OP_breg2 = 0x72, + DW_OP_breg3 = 0x73, + DW_OP_breg4 = 0x74, + DW_OP_breg5 = 0x75, + DW_OP_breg6 = 0x76, + DW_OP_breg7 = 0x77, + DW_OP_breg8 = 0x78, + DW_OP_breg9 = 0x79, + DW_OP_breg10 = 0x7a, + DW_OP_breg11 = 0x7b, + DW_OP_breg12 = 0x7c, + DW_OP_breg13 = 0x7d, + DW_OP_breg14 = 0x7e, + DW_OP_breg15 = 0x7f, + DW_OP_breg16 = 0x80, + DW_OP_breg17 = 0x81, + DW_OP_breg18 = 0x82, + DW_OP_breg19 = 0x83, + DW_OP_breg20 = 0x84, + DW_OP_breg21 = 0x85, + DW_OP_breg22 = 0x86, + DW_OP_breg23 = 0x87, + DW_OP_breg24 = 0x88, + DW_OP_breg25 = 0x89, + DW_OP_breg26 = 0x8a, + DW_OP_breg27 = 0x8b, + DW_OP_breg28 = 0x8c, + DW_OP_breg29 = 0x8d, + DW_OP_breg30 = 0x8e, DW_OP_breg31 = 0x8f, DW_OP_regx = 0x90, DW_OP_fbreg = 0x91, From echristo at apple.com Wed Jun 16 01:26:54 2010 From: echristo at apple.com (Eric Christopher) Date: Tue, 15 Jun 2010 23:26:54 -0700 Subject: [llvm-commits] I'd like to add a few constants to the Support/Dwarf.h file In-Reply-To: <2FCF8E0E-FB23-43D5-8ECA-9EC4C6C9F2A4@apple.com> References: <2FCF8E0E-FB23-43D5-8ECA-9EC4C6C9F2A4@apple.com> Message-ID: On Jun 15, 2010, at 6:02 PM, Jason Molenda wrote: > OK to commit? Yep. -eric From devang.patel at gmail.com Wed Jun 16 01:27:15 2010 From: devang.patel at gmail.com (Devang Patel) Date: Tue, 15 Jun 2010 23:27:15 -0700 Subject: [llvm-commits] I'd like to add a few constants to the Support/Dwarf.h file In-Reply-To: <2FCF8E0E-FB23-43D5-8ECA-9EC4C6C9F2A4@apple.com> References: <2FCF8E0E-FB23-43D5-8ECA-9EC4C6C9F2A4@apple.com> Message-ID: On Tue, Jun 15, 2010 at 6:02 PM, Jason Molenda wrote: > There are several places in lldb where we have big switch statements to handle dwarf constants; we need all of the intermediate values defined if we're going to share llvm's Dwarf constants header file. ?OK to commit? yes > > > Index: Dwarf.h > =================================================================== > --- Dwarf.h ? ? (revision 106065) > +++ Dwarf.h ? ? (working copy) > @@ -300,12 +300,99 @@ > ? DW_OP_ne = 0x2e, > ? DW_OP_lit0 = 0x30, > ? DW_OP_lit1 = 0x31, > + ?DW_OP_lit2 = 0x32, > + ?DW_OP_lit3 = 0x33, > + ?DW_OP_lit4 = 0x34, > + ?DW_OP_lit5 = 0x35, > + ?DW_OP_lit6 = 0x36, > + ?DW_OP_lit7 = 0x37, > + ?DW_OP_lit8 = 0x38, > + ?DW_OP_lit9 = 0x39, > + ?DW_OP_lit10 = 0x3a, > + ?DW_OP_lit11 = 0x3b, > + ?DW_OP_lit12 = 0x3c, > + ?DW_OP_lit13 = 0x3d, > + ?DW_OP_lit14 = 0x3e, > + ?DW_OP_lit15 = 0x3f, > + ?DW_OP_lit16 = 0x40, > + ?DW_OP_lit17 = 0x41, > + ?DW_OP_lit18 = 0x42, > + ?DW_OP_lit19 = 0x43, > + ?DW_OP_lit20 = 0x44, > + ?DW_OP_lit21 = 0x45, > + ?DW_OP_lit22 = 0x46, > + ?DW_OP_lit23 = 0x47, > + ?DW_OP_lit24 = 0x48, > + ?DW_OP_lit25 = 0x49, > + ?DW_OP_lit26 = 0x4a, > + ?DW_OP_lit27 = 0x4b, > + ?DW_OP_lit28 = 0x4c, > + ?DW_OP_lit29 = 0x4d, > + ?DW_OP_lit30 = 0x4e, > ? DW_OP_lit31 = 0x4f, > ? DW_OP_reg0 = 0x50, > ? DW_OP_reg1 = 0x51, > + ?DW_OP_reg2 = 0x52, > + ?DW_OP_reg3 = 0x53, > + ?DW_OP_reg4 = 0x54, > + ?DW_OP_reg5 = 0x55, > + ?DW_OP_reg6 = 0x56, > + ?DW_OP_reg7 = 0x57, > + ?DW_OP_reg8 = 0x58, > + ?DW_OP_reg9 = 0x59, > + ?DW_OP_reg10 = 0x5a, > + ?DW_OP_reg11 = 0x5b, > + ?DW_OP_reg12 = 0x5c, > + ?DW_OP_reg13 = 0x5d, > + ?DW_OP_reg14 = 0x5e, > + ?DW_OP_reg15 = 0x5f, > + ?DW_OP_reg16 = 0x60, > + ?DW_OP_reg17 = 0x61, > + ?DW_OP_reg18 = 0x62, > + ?DW_OP_reg19 = 0x63, > + ?DW_OP_reg20 = 0x64, > + ?DW_OP_reg21 = 0x65, > + ?DW_OP_reg22 = 0x66, > + ?DW_OP_reg23 = 0x67, > + ?DW_OP_reg24 = 0x68, > + ?DW_OP_reg25 = 0x69, > + ?DW_OP_reg26 = 0x6a, > + ?DW_OP_reg27 = 0x6b, > + ?DW_OP_reg28 = 0x6c, > + ?DW_OP_reg29 = 0x6d, > + ?DW_OP_reg30 = 0x6e, > ? DW_OP_reg31 = 0x6f, > ? DW_OP_breg0 = 0x70, > ? DW_OP_breg1 = 0x71, > + ?DW_OP_breg2 = 0x72, > + ?DW_OP_breg3 = 0x73, > + ?DW_OP_breg4 = 0x74, > + ?DW_OP_breg5 = 0x75, > + ?DW_OP_breg6 = 0x76, > + ?DW_OP_breg7 = 0x77, > + ?DW_OP_breg8 = 0x78, > + ?DW_OP_breg9 = 0x79, > + ?DW_OP_breg10 = 0x7a, > + ?DW_OP_breg11 = 0x7b, > + ?DW_OP_breg12 = 0x7c, > + ?DW_OP_breg13 = 0x7d, > + ?DW_OP_breg14 = 0x7e, > + ?DW_OP_breg15 = 0x7f, > + ?DW_OP_breg16 = 0x80, > + ?DW_OP_breg17 = 0x81, > + ?DW_OP_breg18 = 0x82, > + ?DW_OP_breg19 = 0x83, > + ?DW_OP_breg20 = 0x84, > + ?DW_OP_breg21 = 0x85, > + ?DW_OP_breg22 = 0x86, > + ?DW_OP_breg23 = 0x87, > + ?DW_OP_breg24 = 0x88, > + ?DW_OP_breg25 = 0x89, > + ?DW_OP_breg26 = 0x8a, > + ?DW_OP_breg27 = 0x8b, > + ?DW_OP_breg28 = 0x8c, > + ?DW_OP_breg29 = 0x8d, > + ?DW_OP_breg30 = 0x8e, > ? DW_OP_breg31 = 0x8f, > ? DW_OP_regx = 0x90, > ? DW_OP_fbreg = 0x91, > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -- - Devang From dpatel at apple.com Wed Jun 16 01:42:02 2010 From: dpatel at apple.com (Devang Patel) Date: Wed, 16 Jun 2010 06:42:02 -0000 Subject: [llvm-commits] [llvm] r106088 - /llvm/trunk/lib/Analysis/DebugInfo.cpp Message-ID: <20100616064202.5B5C82A6C12C@llvm.org> Author: dpatel Date: Wed Jun 16 01:42:02 2010 New Revision: 106088 URL: http://llvm.org/viewvc/llvm-project?rev=106088&view=rev Log: Check function pointer first, before comparing function names. Modified: llvm/trunk/lib/Analysis/DebugInfo.cpp Modified: llvm/trunk/lib/Analysis/DebugInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DebugInfo.cpp?rev=106088&r1=106087&r2=106088&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/DebugInfo.cpp (original) +++ llvm/trunk/lib/Analysis/DebugInfo.cpp Wed Jun 16 01:42:02 2010 @@ -406,6 +406,8 @@ /// information for the function F. bool DISubprogram::describes(const Function *F) { assert(F && "Invalid function"); + if (F == getFunction()) + return true; StringRef Name = getLinkageName(); if (Name.empty()) Name = getName(); From daniel at zuster.org Wed Jun 16 02:19:39 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 16 Jun 2010 07:19:39 -0000 Subject: [llvm-commits] [zorg] r106089 - in /zorg/trunk/lnt/lnt: db/runinfo.py util/NTEmailReport.py Message-ID: <20100616071939.BAF712A6C12C@llvm.org> Author: ddunbar Date: Wed Jun 16 02:19:39 2010 New Revision: 106089 URL: http://llvm.org/viewvc/llvm-project?rev=106089&view=rev Log: LNT/simple: Add support for generating email reports from LNT/simple style submissions. Modified: zorg/trunk/lnt/lnt/db/runinfo.py zorg/trunk/lnt/lnt/util/NTEmailReport.py Modified: zorg/trunk/lnt/lnt/db/runinfo.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/db/runinfo.py?rev=106089&r1=106088&r2=106089&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/db/runinfo.py (original) +++ zorg/trunk/lnt/lnt/db/runinfo.py Wed Jun 16 02:19:39 2010 @@ -2,10 +2,10 @@ from lnt.viewer import Util from lnt.viewer.PerfDB import Sample -REGRESSED = 0 -IMPROVED = 1 -UNCHANGED_PASS = 2 -UNCHANGED_FAIL = 3 +REGRESSED = 'REGRESSED' +IMPROVED = 'IMPROVED' +UNCHANGED_PASS = 'UNCHANGED_PASS' +UNCHANGED_FAIL = 'UNCHANGED_FAIL' class ComparisonResult: def __init__(self, cur_value, prev_value, delta, pct_delta, stddev, MAD, Modified: zorg/trunk/lnt/lnt/util/NTEmailReport.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/util/NTEmailReport.py?rev=106089&r1=106088&r2=106089&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/util/NTEmailReport.py (original) +++ zorg/trunk/lnt/lnt/util/NTEmailReport.py Wed Jun 16 02:19:39 2010 @@ -12,6 +12,9 @@ import StringIO from lnt import viewer +from lnt.db import runinfo +from lnt.db import perfdbsummary +from lnt.viewer import Util from lnt.viewer import PerfDB from lnt.viewer.NTUtil import * @@ -61,9 +64,168 @@ best = r return best +def getSimpleReport(db, run, baseurl, was_added, will_commit): + tag = run.info['tag'].value + + # Get the run summary. + run_summary = perfdbsummary.SimpleSuiteRunSummary.get_summary(db, tag) + + # Load the test suite summary. + ts_summary = perfdbsummary.get_simple_suite_summary(db, tag) + + # Get the run pass/fail information. + sri = runinfo.SimpleRunInfo(db, ts_summary) + + # Gather the runs to use for statistical data. + num_comparison_runs = 5 + cur_id = run.id + comparison_window = [] + for i in range(num_comparison_runs): + cur_id = run_summary.get_previous_run_on_machine(cur_id) + if not cur_id: + break + comparison_window.append(cur_id) + + # Find previous run to compare to. + id = run_summary.get_previous_run_on_machine(run.id) + if id is not None: + compare_to = db.getRun(id) + + # Gather the changes to report, mapped by parameter set. + new_failures = Util.multidict() + new_passes = Util.multidict() + perf_regressions = Util.multidict() + perf_improvements = Util.multidict() + added_tests = Util.multidict() + removed_tests = Util.multidict() + existing_failures = Util.multidict() + for name in ts_summary.test_names: + for pset in ts_summary.parameter_sets: + cr = sri.get_run_comparison_result(run, compare_to, name, pset, + comparison_window) + test_status = cr.get_test_status() + perf_status = cr.get_value_status() + if test_status == runinfo.REGRESSED: + new_failures[pset] = (name, cr) + elif test_status == runinfo.IMPROVED: + new_passes[pset] = (name, cr) + elif cr.current is None: + removed_tests[pset] = (name, cr) + elif cr.previous is None: + added_tests[pset] = (name, cr) + elif test_status == runinfo.UNCHANGED_FAIL: + existing_failures[pset] = (name, cr) + elif perf_status == runinfo.REGRESSED: + perf_regressions[pset] = (name, cr) + elif perf_status == runinfo.IMPROVED: + perf_improvements[pset] = (name, cr) + + # Generate the report. + report = StringIO.StringIO() + + machine = run.machine + subject = """%s nightly tester results""" % machine.name + + # Generate the report header. + if baseurl[-1] == '/': + baseurl = baseurl[:-1] + print >>report, """%s/%d/""" % (baseurl, run.id) + print >>report, """Nickname: %s:%d""" % (machine.name, machine.number) + if 'name' in machine.info: + print >>report, """Name: %s""" % (machine.info['name'].value,) + print >>report, """Comparing:""" + print >>report, """ Run: %d, Order: %s, Start Time: %s, End Time: %s""" % ( + run.id, run.info['run_order'].value, run.start_time, run.end_time) + if compare_to: + print >>report, (""" To: %d, Order: %s, """ + """Start Time: %s, End Time: %s""") % ( + compare_to.id, compare_to.info['run_order'].value, + compare_to.start_time, compare_to.end_time) + if run.machine != compare_to.machine: + print >>report, """*** WARNING ***:""", + print >>report, """comparison is against a different machine""", + print >>report, """(%s:%d)""" % (compare_to.machine.name, + compare_to.machine.number) + else: + print >>report, """ To: (none)""" + print >>report + + if existing_failures: + print >>report, 'Total Existing Failures:', sum( + map(len, existing_failures.values())) + print >>report + + # Generate the summary of the changes. + items_info = (('New Failures', new_failures, False), + ('New Passes', new_passes, False), + ('Performance Regressions', perf_regressions, True), + ('Performance Improvements', perf_improvements, True), + ('Removed Tests', removed_tests, False), + ('Added Tests', added_tests, False)) + total_changes = sum([sum(map(len, items.values())) + for _,items,_ in items_info]) + if total_changes: + print >>report, """===============""" + print >>report, """Changes Summary""" + print >>report, """===============""" + print >>report + for name,items,_ in items_info: + if items: + print >>report, '%s: %d' % (name, sum(map(len, items.values()))) + print >>report + + print >>report, """==============""" + print >>report, """Changes Detail""" + print >>report, """==============""" + for name,items,show_perf in items_info: + if not items: + continue + + print >>report + print >>report, name + print >>report, '-' * len(name) + for pset,tests in items.items(): + if show_perf: + tests.sort(key = lambda (_,cr): -abs(cr.pct_delta)) + + if pset or len(items) > 1: + print >>report + print >>report, "Parameter Set:", pset + for name,cr in tests: + if show_perf: + print >>report, (' %s: %.2f%%' + '(%.4f => %.4f, std. dev.: %.4f)') % ( + name, 100. * cr.pct_delta, + cr.previous, cr.current, cr.stddev) + else: + print >>report, ' %s' % (name,) + + # Generate a list of the existing failures. + if False and existing_failures: + print >>report + print >>report, """=================""" + print >>report, """Existing Failures""" + print >>report, """=================""" + for pset,tests in existing_failures.items(): + if pset or len(existing_failures) > 1: + print >>report + print >>report, "Parameter Set:", pset + for name,cr in tests: + print >>report, ' %s' % (name,) + + print 'Subject:',subject + print report.getvalue() + raise SystemExit,0 + return subject, report.getvalue() + def getReport(db, run, baseurl, was_added, will_commit): report = StringIO.StringIO() + # Use a simple report unless the tag indicates this is an old style nightly + # test run. + if 'tag' in run.info and run.info['tag'].value != 'nightlytest': + return getSimpleReport(db, run, baseurl, was_added, will_commit) + machine = run.machine compareTo = None From daniel at zuster.org Wed Jun 16 02:19:42 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 16 Jun 2010 07:19:42 -0000 Subject: [llvm-commits] [zorg] r106090 - /zorg/trunk/lnt/lnt/db/runinfo.py Message-ID: <20100616071942.7EB9E2A6C12D@llvm.org> Author: ddunbar Date: Wed Jun 16 02:19:42 2010 New Revision: 106090 URL: http://llvm.org/viewvc/llvm-project?rev=106090&view=rev Log: LNT/simple: Switch default report to 99% confidence interval and increase quantization filter, to increase chance that reports are interesting. Modified: zorg/trunk/lnt/lnt/db/runinfo.py Modified: zorg/trunk/lnt/lnt/db/runinfo.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/db/runinfo.py?rev=106090&r1=106089&r2=106090&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/db/runinfo.py (original) +++ zorg/trunk/lnt/lnt/db/runinfo.py Wed Jun 16 02:19:42 2010 @@ -32,7 +32,7 @@ else: return UNCHANGED_PASS - def get_value_status(self, confidence_interval=1.96, value_precision=0.01): + def get_value_status(self, confidence_interval=2.576, value_precision=0.01): if self.current is None or self.previous is None: return None @@ -51,7 +51,7 @@ # Ignore tests whose delt is too small relative to the precision we can # sample at; otherwise quantization means that we can't measure the # standard deviation with enough accuracy. - if abs(self.delta) <= value_precision * confidence_interval: + if abs(self.delta) <= 2 * value_precision * confidence_interval: if self.failed: return UNCHANGED_FAIL else: From evan.cheng at apple.com Wed Jun 16 02:35:02 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 16 Jun 2010 07:35:02 -0000 Subject: [llvm-commits] [llvm] r106091 - in /llvm/trunk: lib/CodeGen/AggressiveAntiDepBreaker.cpp lib/CodeGen/AggressiveAntiDepBreaker.h lib/CodeGen/CriticalAntiDepBreaker.cpp lib/CodeGen/CriticalAntiDepBreaker.h lib/CodeGen/IfConversion.cpp lib/CodeGen/PostRAHazardRecognizer.cpp lib/CodeGen/RegisterScavenging.cpp lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMTargetMachine.cpp test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll test/CodeGen/Thumb2/thumb2-ifcvt2.ll Message-ID: <20100616073502.6596C2A6C12D@llvm.org> Author: evancheng Date: Wed Jun 16 02:35:02 2010 New Revision: 106091 URL: http://llvm.org/viewvc/llvm-project?rev=106091&view=rev Log: Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler. Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.h llvm/trunk/lib/CodeGen/IfConversion.cpp llvm/trunk/lib/CodeGen/PostRAHazardRecognizer.cpp llvm/trunk/lib/CodeGen/RegisterScavenging.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp llvm/trunk/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt2.ll Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp?rev=106091&r1=106090&r2=106091&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp (original) +++ llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp Wed Jun 16 02:35:02 2010 @@ -21,6 +21,7 @@ #include "llvm/CodeGen/MachineInstr.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" @@ -114,6 +115,7 @@ TargetSubtarget::RegClassVector& CriticalPathRCs) : AntiDepBreaker(), MF(MFi), MRI(MF.getRegInfo()), + TII(MF.getTarget().getInstrInfo()), TRI(MF.getTarget().getRegisterInfo()), AllocatableSet(TRI->getAllocatableSet(MF)), State(NULL) { @@ -163,25 +165,27 @@ DefIndices[AliasReg] = ~0u; } } - } else { - // In a non-return block, examine the live-in regs of all successors. - for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(), + } + + // In a non-return block, examine the live-in regs of all successors. + // Note a return block can have successors if the return instruction is + // predicated. + for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(), SE = BB->succ_end(); SI != SE; ++SI) - for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(), + for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(), E = (*SI)->livein_end(); I != E; ++I) { - unsigned Reg = *I; - State->UnionGroups(Reg, 0); - KillIndices[Reg] = BB->size(); - DefIndices[Reg] = ~0u; - // Repeat, for all aliases. - for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { - unsigned AliasReg = *Alias; - State->UnionGroups(AliasReg, 0); - KillIndices[AliasReg] = BB->size(); - DefIndices[AliasReg] = ~0u; - } + unsigned Reg = *I; + State->UnionGroups(Reg, 0); + KillIndices[Reg] = BB->size(); + DefIndices[Reg] = ~0u; + // Repeat, for all aliases. + for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { + unsigned AliasReg = *Alias; + State->UnionGroups(AliasReg, 0); + KillIndices[AliasReg] = BB->size(); + DefIndices[AliasReg] = ~0u; } - } + } // Mark live-out callee-saved registers. In a return block this is // all callee-saved registers. In non-return this is any @@ -390,7 +394,8 @@ // If MI's defs have a special allocation requirement, don't allow // any def registers to be changed. Also assume all registers // defined in a call must not be changed (ABI). - if (MI->getDesc().isCall() || MI->getDesc().hasExtraDefRegAllocReq()) { + if (MI->getDesc().isCall() || MI->getDesc().hasExtraDefRegAllocReq() || + TII->isPredicated(MI)) { DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)"); State->UnionGroups(Reg, 0); } @@ -443,6 +448,26 @@ std::multimap& RegRefs = State->GetRegRefs(); + // If MI's uses have special allocation requirement, don't allow + // any use registers to be changed. Also assume all registers + // used in a call must not be changed (ABI). + // FIXME: The issue with predicated instruction is more complex. We are being + // conservatively here because the kill markers cannot be trusted after + // if-conversion: + // %R6 = LDR %SP, %reg0, 92, pred:14, pred:%reg0; mem:LD4[FixedStack14] + // ... + // STR %R0, %R6, %reg0, 0, pred:0, pred:%CPSR; mem:ST4[%395] + // %R6 = LDR %SP, %reg0, 100, pred:0, pred:%CPSR; mem:LD4[FixedStack12] + // STR %R0, %R6, %reg0, 0, pred:14, pred:%reg0; mem:ST4[%396](align=8) + // + // The first R6 kill is not really a kill since it's killed by a predicated + // instruction which may not be executed. The second R6 def may or may not + // re-define R6 so it's not safe to change it since the last R6 use cannot be + // changed. + bool Special = MI->getDesc().isCall() || + MI->getDesc().hasExtraSrcRegAllocReq() || + TII->isPredicated(MI); + // Scan the register uses for this instruction and update // live-ranges, groups and RegRefs. for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { @@ -459,10 +484,7 @@ // for the register. HandleLastUse(Reg, Count, "(last-use)"); - // If MI's uses have special allocation requirement, don't allow - // any use registers to be changed. Also assume all registers - // used in a call must not be changed (ABI). - if (MI->getDesc().isCall() || MI->getDesc().hasExtraSrcRegAllocReq()) { + if (Special) { DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)"); State->UnionGroups(Reg, 0); } Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h?rev=106091&r1=106090&r2=106091&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h (original) +++ llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h Wed Jun 16 02:35:02 2010 @@ -115,6 +115,7 @@ class AggressiveAntiDepBreaker : public AntiDepBreaker { MachineFunction& MF; MachineRegisterInfo &MRI; + const TargetInstrInfo *TII; const TargetRegisterInfo *TRI; /// AllocatableSet - The set of allocatable registers. Modified: llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp?rev=106091&r1=106090&r2=106091&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp (original) +++ llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp Wed Jun 16 02:35:02 2010 @@ -18,6 +18,7 @@ #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" @@ -29,6 +30,7 @@ CriticalAntiDepBreaker(MachineFunction& MFi) : AntiDepBreaker(), MF(MFi), MRI(MF.getRegInfo()), + TII(MF.getTarget().getInstrInfo()), TRI(MF.getTarget().getRegisterInfo()), AllocatableSet(TRI->getAllocatableSet(MF)) { @@ -71,25 +73,27 @@ DefIndices[AliasReg] = ~0u; } } - } else { - // In a non-return block, examine the live-in regs of all successors. - for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(), + } + + // In a non-return block, examine the live-in regs of all successors. + // Note a return block can have successors if the return instruction is + // predicated. + for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(), SE = BB->succ_end(); SI != SE; ++SI) - for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(), + for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(), E = (*SI)->livein_end(); I != E; ++I) { - unsigned Reg = *I; - Classes[Reg] = reinterpret_cast(-1); - KillIndices[Reg] = BB->size(); - DefIndices[Reg] = ~0u; - // Repeat, for all aliases. - for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { - unsigned AliasReg = *Alias; - Classes[AliasReg] = reinterpret_cast(-1); - KillIndices[AliasReg] = BB->size(); - DefIndices[AliasReg] = ~0u; - } + unsigned Reg = *I; + Classes[Reg] = reinterpret_cast(-1); + KillIndices[Reg] = BB->size(); + DefIndices[Reg] = ~0u; + // Repeat, for all aliases. + for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { + unsigned AliasReg = *Alias; + Classes[AliasReg] = reinterpret_cast(-1); + KillIndices[AliasReg] = BB->size(); + DefIndices[AliasReg] = ~0u; } - } + } // Mark live-out callee-saved registers. In a return block this is // all callee-saved registers. In non-return this is any @@ -164,6 +168,26 @@ } void CriticalAntiDepBreaker::PrescanInstruction(MachineInstr *MI) { + // It's not safe to change register allocation for source operands of + // that have special allocation requirements. Also assume all registers + // used in a call must not be changed (ABI). + // FIXME: The issue with predicated instruction is more complex. We are being + // conservatively here because the kill markers cannot be trusted after + // if-conversion: + // %R6 = LDR %SP, %reg0, 92, pred:14, pred:%reg0; mem:LD4[FixedStack14] + // ... + // STR %R0, %R6, %reg0, 0, pred:0, pred:%CPSR; mem:ST4[%395] + // %R6 = LDR %SP, %reg0, 100, pred:0, pred:%CPSR; mem:LD4[FixedStack12] + // STR %R0, %R6, %reg0, 0, pred:14, pred:%reg0; mem:ST4[%396](align=8) + // + // The first R6 kill is not really a kill since it's killed by a predicated + // instruction which may not be executed. The second R6 def may or may not + // re-define R6 so it's not safe to change it since the last R6 use cannot be + // changed. + bool Special = MI->getDesc().isCall() || + MI->getDesc().hasExtraSrcRegAllocReq() || + TII->isPredicated(MI); + // Scan the register operands for this instruction and update // Classes and RegRefs. for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { @@ -199,9 +223,7 @@ if (Classes[Reg] != reinterpret_cast(-1)) RegRefs.insert(std::make_pair(Reg, &MO)); - // It's not safe to change register allocation for source operands of - // that have special allocation requirements. - if (MO.isUse() && MI->getDesc().hasExtraSrcRegAllocReq()) { + if (MO.isUse() && Special) { if (KeepRegs.insert(Reg)) { for (const unsigned *Subreg = TRI->getSubRegisters(Reg); *Subreg; ++Subreg) @@ -216,38 +238,43 @@ // Update liveness. // Proceding upwards, registers that are defed but not used in this // instruction are now dead. - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { - MachineOperand &MO = MI->getOperand(i); - if (!MO.isReg()) continue; - unsigned Reg = MO.getReg(); - if (Reg == 0) continue; - if (!MO.isDef()) continue; - // Ignore two-addr defs. - if (MI->isRegTiedToUseOperand(i)) continue; - - DefIndices[Reg] = Count; - KillIndices[Reg] = ~0u; - assert(((KillIndices[Reg] == ~0u) != - (DefIndices[Reg] == ~0u)) && - "Kill and Def maps aren't consistent for Reg!"); - KeepRegs.erase(Reg); - Classes[Reg] = 0; - RegRefs.erase(Reg); - // Repeat, for all subregs. - for (const unsigned *Subreg = TRI->getSubRegisters(Reg); - *Subreg; ++Subreg) { - unsigned SubregReg = *Subreg; - DefIndices[SubregReg] = Count; - KillIndices[SubregReg] = ~0u; - KeepRegs.erase(SubregReg); - Classes[SubregReg] = 0; - RegRefs.erase(SubregReg); - } - // Conservatively mark super-registers as unusable. - for (const unsigned *Super = TRI->getSuperRegisters(Reg); - *Super; ++Super) { - unsigned SuperReg = *Super; - Classes[SuperReg] = reinterpret_cast(-1); + + if (!TII->isPredicated(MI)) { + // Predicated defs are modeled as read + write, i.e. similar to two + // address updates. + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + MachineOperand &MO = MI->getOperand(i); + if (!MO.isReg()) continue; + unsigned Reg = MO.getReg(); + if (Reg == 0) continue; + if (!MO.isDef()) continue; + // Ignore two-addr defs. + if (MI->isRegTiedToUseOperand(i)) continue; + + DefIndices[Reg] = Count; + KillIndices[Reg] = ~0u; + assert(((KillIndices[Reg] == ~0u) != + (DefIndices[Reg] == ~0u)) && + "Kill and Def maps aren't consistent for Reg!"); + KeepRegs.erase(Reg); + Classes[Reg] = 0; + RegRefs.erase(Reg); + // Repeat, for all subregs. + for (const unsigned *Subreg = TRI->getSubRegisters(Reg); + *Subreg; ++Subreg) { + unsigned SubregReg = *Subreg; + DefIndices[SubregReg] = Count; + KillIndices[SubregReg] = ~0u; + KeepRegs.erase(SubregReg); + Classes[SubregReg] = 0; + RegRefs.erase(SubregReg); + } + // Conservatively mark super-registers as unusable. + for (const unsigned *Super = TRI->getSuperRegisters(Reg); + *Super; ++Super) { + unsigned SuperReg = *Super; + Classes[SuperReg] = reinterpret_cast(-1); + } } } for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { @@ -478,7 +505,11 @@ PrescanInstruction(MI); - if (MI->getDesc().hasExtraDefRegAllocReq()) + // If MI's defs have a special allocation requirement, don't allow + // any def registers to be changed. Also assume all registers + // defined in a call must not be changed (ABI). + if (MI->getDesc().isCall() || MI->getDesc().hasExtraDefRegAllocReq() || + TII->isPredicated(MI)) // If this instruction's defs have special allocation requirement, don't // break this anti-dependency. AntiDepReg = 0; @@ -490,7 +521,7 @@ if (!MO.isReg()) continue; unsigned Reg = MO.getReg(); if (Reg == 0) continue; - if (MO.isUse() && AntiDepReg == Reg) { + if (MO.isUse() && TRI->regsOverlap(AntiDepReg, Reg)) { AntiDepReg = 0; break; } Modified: llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.h?rev=106091&r1=106090&r2=106091&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.h (original) +++ llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.h Wed Jun 16 02:35:02 2010 @@ -22,15 +22,18 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/ScheduleDAG.h" -#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/SmallSet.h" #include namespace llvm { +class TargetInstrInfo; +class TargetRegisterInfo; + class CriticalAntiDepBreaker : public AntiDepBreaker { MachineFunction& MF; MachineRegisterInfo &MRI; + const TargetInstrInfo *TII; const TargetRegisterInfo *TRI; /// AllocatableSet - The set of allocatable registers. Modified: llvm/trunk/lib/CodeGen/IfConversion.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/IfConversion.cpp?rev=106091&r1=106090&r2=106091&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/IfConversion.cpp (original) +++ llvm/trunk/lib/CodeGen/IfConversion.cpp Wed Jun 16 02:35:02 2010 @@ -20,6 +20,7 @@ #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" @@ -47,6 +48,8 @@ cl::init(false), cl::Hidden); static cl::opt DisableDiamond("disable-ifcvt-diamond", cl::init(false), cl::Hidden); +static cl::opt IfCvtBranchFold("ifcvt-branch-fold", + cl::init(true), cl::Hidden); STATISTIC(NumSimple, "Number of simple if-conversions performed"); STATISTIC(NumSimpleFalse, "Number of simple (F) if-conversions performed"); @@ -146,6 +149,7 @@ const TargetLowering *TLI; const TargetInstrInfo *TII; + const TargetRegisterInfo *TRI; bool MadeChange; int FnNum; public: @@ -176,9 +180,11 @@ unsigned NumDups1, unsigned NumDups2); void PredicateBlock(BBInfo &BBI, MachineBasicBlock::iterator E, - SmallVectorImpl &Cond); + SmallVectorImpl &Cond, + SmallSet &Redefs); void CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI, SmallVectorImpl &Cond, + SmallSet &Redefs, bool IgnoreBr = false); void MergeBlocks(BBInfo &ToBBI, BBInfo &FromBBI); @@ -226,6 +232,7 @@ bool IfConverter::runOnMachineFunction(MachineFunction &MF) { TLI = MF.getTarget().getTargetLowering(); TII = MF.getTarget().getInstrInfo(); + TRI = MF.getTarget().getRegisterInfo(); if (!TII) return false; DEBUG(dbgs() << "\nIfcvt: function (" << ++FnNum << ") \'" @@ -362,7 +369,7 @@ Roots.clear(); BBAnalysis.clear(); - if (MadeChange) { + if (MadeChange && !IfCvtBranchFold) { BranchFolder BF(false); BF.OptimizeFunction(MF, TII, MF.getTarget().getRegisterInfo(), @@ -823,12 +830,17 @@ /// that all the intervening blocks are empty (given BB can fall through to its /// next block). static bool canFallThroughTo(MachineBasicBlock *BB, MachineBasicBlock *ToBB) { - MachineFunction::iterator I = BB; + MachineFunction::iterator PI = BB; + MachineFunction::iterator I = llvm::next(PI); MachineFunction::iterator TI = ToBB; MachineFunction::iterator E = BB->getParent()->end(); - while (++I != TI) - if (I == E || !I->empty()) + while (I != TI) { + // Check isSuccessor to avoid case where the next block is empty, but + // it's not a successor. + if (I == E || !I->empty() || !PI->isSuccessor(I)) return false; + PI = I++; + } return true; } @@ -863,6 +875,66 @@ BBI.BB->CorrectExtraCFGEdges(TBB, FBB, !Cond.empty()); } +/// InitPredRedefs / UpdatePredRedefs - Defs by predicated instructions are +/// modeled as read + write (sort like two-address instructions). These +/// routines track register liveness and add implicit uses to if-converted +/// instructions to conform to the model. +static void InitPredRedefs(MachineBasicBlock *BB, SmallSet &Redefs, + const TargetRegisterInfo *TRI) { + for (MachineBasicBlock::livein_iterator I = BB->livein_begin(), + E = BB->livein_end(); I != E; ++I) { + unsigned Reg = *I; + Redefs.insert(Reg); + for (const unsigned *Subreg = TRI->getSubRegisters(Reg); + *Subreg; ++Subreg) + Redefs.insert(*Subreg); + } +} + +static void UpdatePredRedefs(MachineInstr *MI, SmallSet &Redefs, + const TargetRegisterInfo *TRI, + bool AddImpUse = false) { + SmallVector Defs; + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + const MachineOperand &MO = MI->getOperand(i); + if (!MO.isReg()) + continue; + unsigned Reg = MO.getReg(); + if (!Reg) + continue; + if (MO.isDef()) + Defs.push_back(Reg); + else if (MO.isKill()) { + Redefs.erase(Reg); + for (const unsigned *SR = TRI->getSubRegisters(Reg); *SR; ++SR) + Redefs.erase(*SR); + } + } + for (unsigned i = 0, e = Defs.size(); i != e; ++i) { + unsigned Reg = Defs[i]; + if (Redefs.count(Reg)) { + if (AddImpUse) + // Treat predicated update as read + write. + MI->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/, + true/*IsImp*/,false/*IsKill*/)); + } else { + Redefs.insert(Reg); + for (const unsigned *SR = TRI->getSubRegisters(Reg); *SR; ++SR) + Redefs.insert(*SR); + } + } +} + +static void UpdatePredRedefs(MachineBasicBlock::iterator I, + MachineBasicBlock::iterator E, + SmallSet &Redefs, + const TargetRegisterInfo *TRI) { + while (I != E) { + UpdatePredRedefs(I, Redefs, TRI); + ++I; + } +} + /// IfConvertSimple - If convert a simple (split, no rejoin) sub-CFG. /// bool IfConverter::IfConvertSimple(BBInfo &BBI, IfcvtKind Kind) { @@ -887,13 +959,19 @@ if (TII->ReverseBranchCondition(Cond)) assert(false && "Unable to reverse branch condition!"); + // Initialize liveins to the first BB. These are potentiall re-defined by + // predicated instructions. + SmallSet Redefs; + InitPredRedefs(CvtBBI->BB, Redefs, TRI); + InitPredRedefs(NextBBI->BB, Redefs, TRI); + if (CvtBBI->BB->pred_size() > 1) { BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB); // Copy instructions in the true block, predicate them, and add them to // the entry block. - CopyAndPredicateBlock(BBI, *CvtBBI, Cond); + CopyAndPredicateBlock(BBI, *CvtBBI, Cond, Redefs); } else { - PredicateBlock(*CvtBBI, CvtBBI->BB->end(), Cond); + PredicateBlock(*CvtBBI, CvtBBI->BB->end(), Cond, Redefs); // Merge converted block into entry block. BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB); @@ -971,17 +1049,23 @@ } } + // Initialize liveins to the first BB. These are potentiall re-defined by + // predicated instructions. + SmallSet Redefs; + InitPredRedefs(CvtBBI->BB, Redefs, TRI); + InitPredRedefs(NextBBI->BB, Redefs, TRI); + bool HasEarlyExit = CvtBBI->FalseBB != NULL; bool DupBB = CvtBBI->BB->pred_size() > 1; if (DupBB) { BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB); // Copy instructions in the true block, predicate them, and add them to // the entry block. - CopyAndPredicateBlock(BBI, *CvtBBI, Cond, true); + CopyAndPredicateBlock(BBI, *CvtBBI, Cond, Redefs, true); } else { // Predicate the 'true' block after removing its branch. CvtBBI->NonPredSize -= TII->RemoveBranch(*CvtBBI->BB); - PredicateBlock(*CvtBBI, CvtBBI->BB->end(), Cond); + PredicateBlock(*CvtBBI, CvtBBI->BB->end(), Cond, Redefs); // Now merge the entry of the triangle with the true block. BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB); @@ -1085,6 +1169,11 @@ // Remove the conditional branch from entry to the blocks. BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB); + // Initialize liveins to the first BB. These are potentiall re-defined by + // predicated instructions. + SmallSet Redefs; + InitPredRedefs(BBI1->BB, Redefs, TRI); + // Remove the duplicated instructions at the beginnings of both paths. MachineBasicBlock::iterator DI1 = BBI1->BB->begin(); MachineBasicBlock::iterator DI2 = BBI2->BB->begin(); @@ -1102,6 +1191,8 @@ ++DI2; --NumDups1; } + + UpdatePredRedefs(BBI1->BB->begin(), DI1, Redefs, TRI); BBI.BB->splice(BBI.BB->end(), BBI1->BB, BBI1->BB->begin(), DI1); BBI2->BB->erase(BBI2->BB->begin(), DI2); @@ -1118,7 +1209,7 @@ ++i; } BBI1->BB->erase(DI1, BBI1->BB->end()); - PredicateBlock(*BBI1, BBI1->BB->end(), *Cond1); + PredicateBlock(*BBI1, BBI1->BB->end(), *Cond1, Redefs); // Predicate the 'false' block. BBI2->NonPredSize -= TII->RemoveBranch(*BBI2->BB); @@ -1132,7 +1223,7 @@ if (!DI2->isDebugValue()) --NumDups2; } - PredicateBlock(*BBI2, DI2, *Cond2); + PredicateBlock(*BBI2, DI2, *Cond2, Redefs); // Merge the true block into the entry of the diamond. MergeBlocks(BBI, *BBI1); @@ -1168,7 +1259,8 @@ /// specified end with the specified condition. void IfConverter::PredicateBlock(BBInfo &BBI, MachineBasicBlock::iterator E, - SmallVectorImpl &Cond) { + SmallVectorImpl &Cond, + SmallSet &Redefs) { for (MachineBasicBlock::iterator I = BBI.BB->begin(); I != E; ++I) { if (I->isDebugValue() || TII->isPredicated(I)) continue; @@ -1178,6 +1270,10 @@ #endif llvm_unreachable(0); } + + // If the predicated instruction now re-defines a register as the result of + // if-conversion, add an implicit kill. + UpdatePredRedefs(I, Redefs, TRI, true); } std::copy(Cond.begin(), Cond.end(), std::back_inserter(BBI.Predicate)); @@ -1192,6 +1288,7 @@ /// the destination block. Skip end of block branches if IgnoreBr is true. void IfConverter::CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI, SmallVectorImpl &Cond, + SmallSet &Redefs, bool IgnoreBr) { MachineFunction &MF = *ToBBI.BB->getParent(); @@ -1207,13 +1304,18 @@ ToBBI.BB->insert(ToBBI.BB->end(), MI); ToBBI.NonPredSize++; - if (!isPredicated && !MI->isDebugValue()) + if (!isPredicated && !MI->isDebugValue()) { if (!TII->PredicateInstruction(MI, Cond)) { #ifndef NDEBUG dbgs() << "Unable to predicate " << *I << "!\n"; #endif llvm_unreachable(0); } + } + + // If the predicated instruction now re-defines a register as the result of + // if-conversion, add an implicit kill. + UpdatePredRedefs(MI, Redefs, TRI, true); } std::vector Succs(FromBBI.BB->succ_begin(), Modified: llvm/trunk/lib/CodeGen/PostRAHazardRecognizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PostRAHazardRecognizer.cpp?rev=106091&r1=106090&r2=106091&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PostRAHazardRecognizer.cpp (original) +++ llvm/trunk/lib/CodeGen/PostRAHazardRecognizer.cpp Wed Jun 16 02:35:02 2010 @@ -72,7 +72,7 @@ } } -PostRAHazardRecognizer::HazardType +ScheduleHazardRecognizer::HazardType PostRAHazardRecognizer::getHazardType(SUnit *SU) { if (ItinData.isEmpty()) return NoHazard; Modified: llvm/trunk/lib/CodeGen/RegisterScavenging.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterScavenging.cpp?rev=106091&r1=106090&r2=106091&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegisterScavenging.cpp (original) +++ llvm/trunk/lib/CodeGen/RegisterScavenging.cpp Wed Jun 16 02:35:02 2010 @@ -141,6 +141,10 @@ // Find out which registers are early clobbered, killed, defined, and marked // def-dead in this instruction. + // FIXME: The scavenger is not predication aware. If the instruction is + // predicated, conservatively assume "kill" markers do not actually kill the + // register. Similarly ignores "dead" markers. + bool isPred = TII->isPredicated(MI); BitVector EarlyClobberRegs(NumPhysRegs); BitVector KillRegs(NumPhysRegs); BitVector DefRegs(NumPhysRegs); @@ -155,11 +159,11 @@ if (MO.isUse()) { // Two-address operands implicitly kill. - if (MO.isKill() || MI->isRegTiedToDefOperand(i)) + if (!isPred && (MO.isKill() || MI->isRegTiedToDefOperand(i))) addRegWithSubRegs(KillRegs, Reg); } else { assert(MO.isDef()); - if (MO.isDead()) + if (!isPred && MO.isDead()) addRegWithSubRegs(DeadRegs, Reg); else addRegWithSubRegs(DefRegs, Reg); Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=106091&r1=106090&r2=106091&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Jun 16 02:35:02 2010 @@ -62,6 +62,11 @@ cl::desc("Generate calls via indirect call instructions."), cl::init(false)); +static cl::opt +ARMInterworking("arm-interworking", cl::Hidden, + cl::desc("Enable / disable ARM interworking (for debugging only)"), + cl::init(true)); + static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, @@ -1188,7 +1193,7 @@ getTargetMachine().getRelocationModel() != Reloc::Static; isARMFunc = !Subtarget->isThumb() || isStub; // ARM call to a local ARM function is predicable. - isLocalARMFunc = !Subtarget->isThumb() && !isExt; + isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking); // tBX takes a register source operand. if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) { unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId(); Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=106091&r1=106090&r2=106091&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Wed Jun 16 02:35:02 2010 @@ -27,6 +27,11 @@ cl::desc("Form IT blocks early before register allocation"), cl::init(false)); +static cl::opt +EarlyIfConvert("arm-early-if-convert", cl::Hidden, + cl::desc("Run if-conversion before post-ra scheduling"), + cl::init(false)); + static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) { Triple TheTriple(TT); switch (TheTriple.getOS()) { @@ -125,13 +130,17 @@ // proper scheduling. PM.add(createARMExpandPseudoPass()); + if (EarlyIfConvert && OptLevel != CodeGenOpt::None) { + if (!Subtarget.isThumb1Only()) + PM.add(createIfConverterPass()); + } + return true; } bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel) { - // FIXME: temporarily disabling load / store optimization pass for Thumb1. - if (OptLevel != CodeGenOpt::None) { + if (!EarlyIfConvert && OptLevel != CodeGenOpt::None) { if (!Subtarget.isThumb1Only()) PM.add(createIfConverterPass()); } Modified: llvm/trunk/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll?rev=106091&r1=106090&r2=106091&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll Wed Jun 16 02:35:02 2010 @@ -12,6 +12,8 @@ ; CHECK: _ZNKSs7compareERKSs: ; CHECK: it eq ; CHECK-NEXT: subeq.w r0, r6, r8 +; CHECK-NEXT: %bb +; CHECK-NEXT: %bb1 ; CHECK-NEXT: ldmia.w sp, {r4, r5, r6, r8, r9, pc} entry: %0 = tail call arm_aapcs_vfpcc i32 @_ZNKSs4sizeEv(%"struct.std::basic_string,std::allocator >"* %this) ; [#uses=3] Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt2.ll?rev=106091&r1=106090&r2=106091&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt2.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt2.ll Wed Jun 16 02:35:02 2010 @@ -31,7 +31,7 @@ ; CHECK: CountTree: ; CHECK: it eq ; CHECK: cmpeq -; CHECK: bne +; CHECK: beq ; CHECK: itt eq ; CHECK: moveq ; CHECK: popeq From daniel at zuster.org Wed Jun 16 02:38:28 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 16 Jun 2010 07:38:28 -0000 Subject: [llvm-commits] [zorg] r106092 - /zorg/trunk/lnt/lnt/util/NTEmailReport.py Message-ID: <20100616073828.C91072A6C12E@llvm.org> Author: ddunbar Date: Wed Jun 16 02:38:28 2010 New Revision: 106092 URL: http://llvm.org/viewvc/llvm-project?rev=106092&view=rev Log: LNT/simple: Fix a bug in reporting added/removed tests. Modified: zorg/trunk/lnt/lnt/util/NTEmailReport.py Modified: zorg/trunk/lnt/lnt/util/NTEmailReport.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/util/NTEmailReport.py?rev=106092&r1=106091&r2=106092&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/util/NTEmailReport.py (original) +++ zorg/trunk/lnt/lnt/util/NTEmailReport.py Wed Jun 16 02:38:28 2010 @@ -109,9 +109,9 @@ new_failures[pset] = (name, cr) elif test_status == runinfo.IMPROVED: new_passes[pset] = (name, cr) - elif cr.current is None: + elif cr.current is None and cr.previous is not None: removed_tests[pset] = (name, cr) - elif cr.previous is None: + elif cr.current is not None and cr.previous is None: added_tests[pset] = (name, cr) elif test_status == runinfo.UNCHANGED_FAIL: existing_failures[pset] = (name, cr) From baldrick at free.fr Wed Jun 16 03:50:52 2010 From: baldrick at free.fr (Duncan Sands) Date: Wed, 16 Jun 2010 08:50:52 -0000 Subject: [llvm-commits] [dragonegg] r106095 - /dragonegg/trunk/extras/do_self_strap Message-ID: <20100616085052.6AAFD2A6C12C@llvm.org> Author: baldrick Date: Wed Jun 16 03:50:52 2010 New Revision: 106095 URL: http://llvm.org/viewvc/llvm-project?rev=106095&view=rev Log: Do not use -l: sometimes it starts vast numbers of simultaneous compilations, which then cause the machine to grind to a halt with mad swapping. Modified: dragonegg/trunk/extras/do_self_strap Modified: dragonegg/trunk/extras/do_self_strap URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/extras/do_self_strap?rev=106095&r1=106094&r2=106095&view=diff ============================================================================== --- dragonegg/trunk/extras/do_self_strap (original) +++ dragonegg/trunk/extras/do_self_strap Wed Jun 16 03:50:52 2010 @@ -57,7 +57,7 @@ --disable-threads --enable-debug-symbols $LLVM_OPTIONS" COMPARE="cmp --ignore-initial=16" # How to compare object files -MAKE="nice -n 20 make -j -l3" # How to run make +MAKE="nice -n 20 make -j2" # How to run make MAKE_INSTALL="nice -n 20 make install" # How to run make install From benny.kra at googlemail.com Wed Jun 16 05:30:29 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Wed, 16 Jun 2010 10:30:29 -0000 Subject: [llvm-commits] [llvm] r106097 - in /llvm/trunk: lib/Transforms/Scalar/SimplifyLibCalls.cpp test/Transforms/SimplifyLibCalls/StrNCmp.ll Message-ID: <20100616103029.E7C822A6C12C@llvm.org> Author: d0k Date: Wed Jun 16 05:30:29 2010 New Revision: 106097 URL: http://llvm.org/viewvc/llvm-project?rev=106097&view=rev Log: simplify-libcalls: fold strncmp(x, y, 1) -> memcmp(x, y, 1) The memcmp will be optimized further and even the pathological case 'strstr(x, "x") == x' generates optimal code now. Modified: llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp llvm/trunk/test/Transforms/SimplifyLibCalls/StrNCmp.ll Modified: llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp?rev=106097&r1=106096&r2=106097&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Wed Jun 16 05:30:29 2010 @@ -342,6 +342,9 @@ if (Length == 0) // strncmp(x,y,0) -> 0 return ConstantInt::get(CI->getType(), 0); + if (TD && Length == 1) // strncmp(x,y,1) -> memcmp(x,y,1) + return EmitMemCmp(Str1P, Str2P, CI->getOperand(3), B, TD); + std::string Str1, Str2; bool HasStr1 = GetConstantStringInfo(Str1P, Str1); bool HasStr2 = GetConstantStringInfo(Str2P, Str2); Modified: llvm/trunk/test/Transforms/SimplifyLibCalls/StrNCmp.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyLibCalls/StrNCmp.ll?rev=106097&r1=106096&r2=106097&view=diff ============================================================================== --- llvm/trunk/test/Transforms/SimplifyLibCalls/StrNCmp.ll (original) +++ llvm/trunk/test/Transforms/SimplifyLibCalls/StrNCmp.ll Wed Jun 16 05:30:29 2010 @@ -2,6 +2,9 @@ ; RUN: opt < %s -simplify-libcalls -S | \ ; RUN: not grep {call.*strncmp} +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32" +target triple = "i386-apple-darwin9.0" + @hello = constant [6 x i8] c"hello\00" ; <[6 x i8]*> [#uses=1] @hell = constant [5 x i8] c"hell\00" ; <[5 x i8]*> [#uses=1] @null = constant [1 x i8] zeroinitializer ; <[1 x i8]*> [#uses=1] @@ -26,3 +29,7 @@ ret i32 %rslt4 } +define i32 @test1(i8* %P, i8* %Q) { + %cmp = call i32 @strncmp(i8* %P, i8* %Q, i32 1) + ret i32 %cmp +} From espindola at google.com Wed Jun 16 09:27:53 2010 From: espindola at google.com (Rafael Espindola) Date: Wed, 16 Jun 2010 10:27:53 -0400 Subject: [llvm-commits] [patch] Remove arm_aapcscc from some tests In-Reply-To: <7BDDBF70-72CC-4A74-A676-568E4D35E8B9@apple.com> References: <250924C5-EF3C-4CB0-BD7C-7F42F9B1D27D@apple.com> <9601F397-5FAC-469F-A704-EF38972AE22E@apple.com> <7BDDBF70-72CC-4A74-A676-568E4D35E8B9@apple.com> Message-ID: > I'm OK with it as long as the default ABI for non-Linux targets is APCS. ?I took a quick look at it seems like that is true; AAPCS is only the default if the triple includes "eabi". ?Otherwise, you're potentially changing the behavior of a lot of tests. ?Even if those tests are not directly related to testing the ABI, there may be differences that affect what the tests do. So, it looks like APCS is the default (I have no opinion if that is correct or not). Is this patch ok or should I update it to also pass a darwin triple to llc? Cheers, -- Rafael ?vila de Esp?ndola From espindola at google.com Wed Jun 16 10:05:24 2010 From: espindola at google.com (Rafael Espindola) Date: Wed, 16 Jun 2010 11:05:24 -0400 Subject: [llvm-commits] [patch] Fix PR7357 Message-ID: With the changes to llvm-gcc and clang, the fix to PR7357 is actually trivial: don't try to change a call if the calling convention is not the default. Cheers, -- Rafael ?vila de Esp?ndola -------------- next part -------------- A non-text attachment was scrubbed... Name: PR7357.patch Type: text/x-patch Size: 1526 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100616/329d198e/attachment.bin From benny.kra at googlemail.com Wed Jun 16 10:47:00 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Wed, 16 Jun 2010 15:47:00 -0000 Subject: [llvm-commits] [llvm] r106102 - /llvm/trunk/lib/Target/README.txt Message-ID: <20100616154700.6E0782A6C12C@llvm.org> Author: d0k Date: Wed Jun 16 10:47:00 2010 New Revision: 106102 URL: http://llvm.org/viewvc/llvm-project?rev=106102&view=rev Log: TODO-- Modified: llvm/trunk/lib/Target/README.txt Modified: llvm/trunk/lib/Target/README.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/README.txt?rev=106102&r1=106101&r2=106102&view=diff ============================================================================== --- llvm/trunk/lib/Target/README.txt (original) +++ llvm/trunk/lib/Target/README.txt Wed Jun 16 10:47:00 2010 @@ -1439,33 +1439,6 @@ //===---------------------------------------------------------------------===// -186.crafty contains this interesting pattern: - -%77 = call i8* @strstr(i8* getelementptr ([6 x i8]* @"\01LC5", i32 0, i32 0), - i8* %30) -%phitmp648 = icmp eq i8* %77, getelementptr ([6 x i8]* @"\01LC5", i32 0, i32 0) -br i1 %phitmp648, label %bb70, label %bb76 - -bb70: ; preds = %OptionMatch.exit91, %bb69 - %78 = call i32 @strlen(i8* %30) nounwind readonly align 1 ; [#uses=1] - -This is basically: - cststr = "abcdef"; - if (strstr(cststr, P) == cststr) { - x = strlen(P); - ... - -The strstr call would be significantly cheaper written as: - -cststr = "abcdef"; -if (memcmp(P, str, strlen(P))) - x = strlen(P); - -This is memcmp+strlen instead of strstr. This also makes the strlen fully -redundant. - -//===---------------------------------------------------------------------===// - 186.crafty also contains this code: %1906 = call i32 @strlen(i8* getelementptr ([32 x i8]* @pgn_event, i32 0,i32 0)) From stoklund at 2pi.dk Wed Jun 16 11:36:15 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 16 Jun 2010 09:36:15 -0700 Subject: [llvm-commits] [llvm] r106038 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp test/CodeGen/Generic/v-binop-widen.ll test/CodeGen/Generic/v-binop-widen2.ll In-Reply-To: <20100615202905.4C9A42A6C12C@llvm.org> References: <20100615202905.4C9A42A6C12C@llvm.org> Message-ID: On Jun 15, 2010, at 1:29 PM, Mon P Wang wrote: > Added: llvm/trunk/test/CodeGen/Generic/v-binop-widen.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/v-binop-widen.ll?rev=106038&view=auto > ============================================================================== > --- llvm/trunk/test/CodeGen/Generic/v-binop-widen.ll (added) > +++ llvm/trunk/test/CodeGen/Generic/v-binop-widen.ll Tue Jun 15 15:29:05 2010 > @@ -0,0 +1,8 @@ > +; RUN: llc -march=x86 %s This writes an output file in the test directory. Please use '< %s' instead. Thanks, /jakob From asl at math.spbu.ru Wed Jun 16 12:04:05 2010 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Wed, 16 Jun 2010 21:04:05 +0400 Subject: [llvm-commits] [patch] Update llvm-gcc to produce "" for the default calling convention on ARM In-Reply-To: References: <76A0798C-9AB8-43E8-99C1-7AFE618CEBEB@apple.com> Message-ID: > An updated patch is attached. With it and a gcc configured for > arm-none-linux-gnueabi I get: > > *) no -mabi -> "" > *) -mabi=aapcs -> "" > *) ?-mcpu=cortex-a8 ?-> arm_apcscc > *) ?-mfloat-abi=hard ?-> arm_aapcs_vfpcc > > Is it OK? Looks ok for me. -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From asl at math.spbu.ru Wed Jun 16 12:05:50 2010 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Wed, 16 Jun 2010 21:05:50 +0400 (MSD) Subject: [llvm-commits] =?utf-8?q?=5Bpatch=5D_Remove_arm=5Faapcscc_from_so?= =?utf-8?q?me_tests?= Message-ID: <201006161705.o5GH5oJ3066330@LocalMailer> > > I'm OK with it as long as the default ABI for non-Linux targets is APCS. ?I took a quick look at it seems like that is true; AAPCS is only the default if the triple includes "eabi". ?Otherwise, you're potentially changing the behavior of a lot of tests. ?Even if those tests are not directly related to testing the ABI, there may be differences that affect what the tests do. > > So, it looks like APCS is the default (I have no opinion if that is > correct or not). Yes, looks like I was mistaken wrt AAPCS. The latter is effective only for eabi (or if AAPCS ABI is explicitly selected). -- WBR, Anton Korobeynikov From dgregor at apple.com Wed Jun 16 12:42:01 2010 From: dgregor at apple.com (Douglas Gregor) Date: Wed, 16 Jun 2010 17:42:01 -0000 Subject: [llvm-commits] [llvm] r106117 - /llvm/trunk/include/llvm/Analysis/IntervalIterator.h Message-ID: <20100616174201.844BA2A6C12C@llvm.org> Author: dgregor Date: Wed Jun 16 12:42:01 2010 New Revision: 106117 URL: http://llvm.org/viewvc/llvm-project?rev=106117&view=rev Log: Eliminate a redundant "typename" keyword Modified: llvm/trunk/include/llvm/Analysis/IntervalIterator.h Modified: llvm/trunk/include/llvm/Analysis/IntervalIterator.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/IntervalIterator.h?rev=106117&r1=106116&r2=106117&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/IntervalIterator.h (original) +++ llvm/trunk/include/llvm/Analysis/IntervalIterator.h Wed Jun 16 12:42:01 2010 @@ -88,7 +88,7 @@ template, class IGT = GraphTraits > > class IntervalIterator { - std::stack > IntStack; + std::stack > IntStack; std::set Visited; OrigContainer_t *OrigContainer; bool IOwnMem; // If True, delete intervals when done with them From daniel at zuster.org Wed Jun 16 12:56:08 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 16 Jun 2010 10:56:08 -0700 Subject: [llvm-commits] [llvm] r106038 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp test/CodeGen/Generic/v-binop-widen.ll test/CodeGen/Generic/v-binop-widen2.ll In-Reply-To: References: <20100615202905.4C9A42A6C12C@llvm.org> Message-ID: On Wed, Jun 16, 2010 at 9:36 AM, Jakob Stoklund Olesen wrote: > > On Jun 15, 2010, at 1:29 PM, Mon P Wang wrote: > >> Added: llvm/trunk/test/CodeGen/Generic/v-binop-widen.ll >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/v-binop-widen.ll?rev=106038&view=auto >> ============================================================================== >> --- llvm/trunk/test/CodeGen/Generic/v-binop-widen.ll (added) >> +++ llvm/trunk/test/CodeGen/Generic/v-binop-widen.ll Tue Jun 15 15:29:05 2010 >> @@ -0,0 +1,8 @@ >> +; RUN: llc -march=x86 %s > > This writes an output file in the test directory. Please use '< %s' instead. Shouldn't it be checking something as well? - Daniel > > Thanks, > /jakob > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From isanbard at gmail.com Wed Jun 16 13:01:31 2010 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 16 Jun 2010 18:01:31 -0000 Subject: [llvm-commits] [llvm] r106119 - /llvm/trunk/lib/CodeGen/MachineSink.cpp Message-ID: <20100616180131.2BC782A6C12C@llvm.org> Author: void Date: Wed Jun 16 13:01:31 2010 New Revision: 106119 URL: http://llvm.org/viewvc/llvm-project?rev=106119&view=rev Log: Improve comment to include that the use of a preg is also verboten in this situation. Modified: llvm/trunk/lib/CodeGen/MachineSink.cpp Modified: llvm/trunk/lib/CodeGen/MachineSink.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineSink.cpp?rev=106119&r1=106118&r2=106119&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineSink.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineSink.cpp Wed Jun 16 13:01:31 2010 @@ -282,9 +282,10 @@ if (MI->getParent() == SuccToSinkTo) return false; - // If the instruction to move defines a dead physical register which is live - // when leaving the basic block, don't move it because it could turn into a - // "zombie" define of that preg. E.g., EFLAGS. () + // If the instruction to move defines or uses a dead physical register which + // is live when leaving the basic block, don't move it because it could turn + // into a zombie define or misuse of that preg. E.g., EFLAGS. + // () for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) { const MachineOperand &MO = MI->getOperand(I); if (!MO.isReg()) continue; From dpatel at apple.com Wed Jun 16 13:04:12 2010 From: dpatel at apple.com (Devang Patel) Date: Wed, 16 Jun 2010 18:04:12 -0000 Subject: [llvm-commits] [llvm] r106121 - /llvm/trunk/test/DebugInfo/2010-06-01-DeadArg-DbgInfo.ll Message-ID: <20100616180412.9866A2A6C12C@llvm.org> Author: dpatel Date: Wed Jun 16 13:04:12 2010 New Revision: 106121 URL: http://llvm.org/viewvc/llvm-project?rev=106121&view=rev Log: Update test to explicitly capture llc output. Modified: llvm/trunk/test/DebugInfo/2010-06-01-DeadArg-DbgInfo.ll Modified: llvm/trunk/test/DebugInfo/2010-06-01-DeadArg-DbgInfo.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/2010-06-01-DeadArg-DbgInfo.ll?rev=106121&r1=106120&r2=106121&view=diff ============================================================================== --- llvm/trunk/test/DebugInfo/2010-06-01-DeadArg-DbgInfo.ll (original) +++ llvm/trunk/test/DebugInfo/2010-06-01-DeadArg-DbgInfo.ll Wed Jun 16 13:04:12 2010 @@ -1,4 +1,5 @@ -; RUN: llc -O2 < %s | grep this | grep -v undef +; RUN: llc -O2 %s -o %t +; RUN: grep this %t | grep -v undef ; Test to check that unused argument 'this' is not undefined in debug info. %struct.foo = type { i32 } From wendling at apple.com Wed Jun 16 13:17:29 2010 From: wendling at apple.com (Bill Wendling) Date: Wed, 16 Jun 2010 11:17:29 -0700 Subject: [llvm-commits] I'd like to add a few constants to the Support/Dwarf.h file In-Reply-To: <2FCF8E0E-FB23-43D5-8ECA-9EC4C6C9F2A4@apple.com> References: <2FCF8E0E-FB23-43D5-8ECA-9EC4C6C9F2A4@apple.com> Message-ID: <4AAB1010-29A8-4833-B9EC-2BF35DE99AA1@apple.com> Looks okay. Go ahead and commit. -bw On Jun 15, 2010, at 6:02 PM, Jason Molenda wrote: > There are several places in lldb where we have big switch statements to handle dwarf constants; we need all of the intermediate values defined if we're going to share llvm's Dwarf constants header file. OK to commit? > > > Index: Dwarf.h > =================================================================== > --- Dwarf.h (revision 106065) > +++ Dwarf.h (working copy) > @@ -300,12 +300,99 @@ > DW_OP_ne = 0x2e, > DW_OP_lit0 = 0x30, > DW_OP_lit1 = 0x31, > + DW_OP_lit2 = 0x32, > + DW_OP_lit3 = 0x33, > + DW_OP_lit4 = 0x34, > + DW_OP_lit5 = 0x35, > + DW_OP_lit6 = 0x36, > + DW_OP_lit7 = 0x37, > + DW_OP_lit8 = 0x38, > + DW_OP_lit9 = 0x39, > + DW_OP_lit10 = 0x3a, > + DW_OP_lit11 = 0x3b, > + DW_OP_lit12 = 0x3c, > + DW_OP_lit13 = 0x3d, > + DW_OP_lit14 = 0x3e, > + DW_OP_lit15 = 0x3f, > + DW_OP_lit16 = 0x40, > + DW_OP_lit17 = 0x41, > + DW_OP_lit18 = 0x42, > + DW_OP_lit19 = 0x43, > + DW_OP_lit20 = 0x44, > + DW_OP_lit21 = 0x45, > + DW_OP_lit22 = 0x46, > + DW_OP_lit23 = 0x47, > + DW_OP_lit24 = 0x48, > + DW_OP_lit25 = 0x49, > + DW_OP_lit26 = 0x4a, > + DW_OP_lit27 = 0x4b, > + DW_OP_lit28 = 0x4c, > + DW_OP_lit29 = 0x4d, > + DW_OP_lit30 = 0x4e, > DW_OP_lit31 = 0x4f, > DW_OP_reg0 = 0x50, > DW_OP_reg1 = 0x51, > + DW_OP_reg2 = 0x52, > + DW_OP_reg3 = 0x53, > + DW_OP_reg4 = 0x54, > + DW_OP_reg5 = 0x55, > + DW_OP_reg6 = 0x56, > + DW_OP_reg7 = 0x57, > + DW_OP_reg8 = 0x58, > + DW_OP_reg9 = 0x59, > + DW_OP_reg10 = 0x5a, > + DW_OP_reg11 = 0x5b, > + DW_OP_reg12 = 0x5c, > + DW_OP_reg13 = 0x5d, > + DW_OP_reg14 = 0x5e, > + DW_OP_reg15 = 0x5f, > + DW_OP_reg16 = 0x60, > + DW_OP_reg17 = 0x61, > + DW_OP_reg18 = 0x62, > + DW_OP_reg19 = 0x63, > + DW_OP_reg20 = 0x64, > + DW_OP_reg21 = 0x65, > + DW_OP_reg22 = 0x66, > + DW_OP_reg23 = 0x67, > + DW_OP_reg24 = 0x68, > + DW_OP_reg25 = 0x69, > + DW_OP_reg26 = 0x6a, > + DW_OP_reg27 = 0x6b, > + DW_OP_reg28 = 0x6c, > + DW_OP_reg29 = 0x6d, > + DW_OP_reg30 = 0x6e, > DW_OP_reg31 = 0x6f, > DW_OP_breg0 = 0x70, > DW_OP_breg1 = 0x71, > + DW_OP_breg2 = 0x72, > + DW_OP_breg3 = 0x73, > + DW_OP_breg4 = 0x74, > + DW_OP_breg5 = 0x75, > + DW_OP_breg6 = 0x76, > + DW_OP_breg7 = 0x77, > + DW_OP_breg8 = 0x78, > + DW_OP_breg9 = 0x79, > + DW_OP_breg10 = 0x7a, > + DW_OP_breg11 = 0x7b, > + DW_OP_breg12 = 0x7c, > + DW_OP_breg13 = 0x7d, > + DW_OP_breg14 = 0x7e, > + DW_OP_breg15 = 0x7f, > + DW_OP_breg16 = 0x80, > + DW_OP_breg17 = 0x81, > + DW_OP_breg18 = 0x82, > + DW_OP_breg19 = 0x83, > + DW_OP_breg20 = 0x84, > + DW_OP_breg21 = 0x85, > + DW_OP_breg22 = 0x86, > + DW_OP_breg23 = 0x87, > + DW_OP_breg24 = 0x88, > + DW_OP_breg25 = 0x89, > + DW_OP_breg26 = 0x8a, > + DW_OP_breg27 = 0x8b, > + DW_OP_breg28 = 0x8c, > + DW_OP_breg29 = 0x8d, > + DW_OP_breg30 = 0x8e, > DW_OP_breg31 = 0x8f, > DW_OP_regx = 0x90, > DW_OP_fbreg = 0x91, > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dpatel at apple.com Wed Jun 16 13:19:49 2010 From: dpatel at apple.com (Devang Patel) Date: Wed, 16 Jun 2010 18:19:49 -0000 Subject: [llvm-commits] [llvm] r106122 - /llvm/trunk/test/DebugInfo/2010-06-01-DeadArg-DbgInfo.ll Message-ID: <20100616181949.3AA9B2A6C12C@llvm.org> Author: dpatel Date: Wed Jun 16 13:19:49 2010 New Revision: 106122 URL: http://llvm.org/viewvc/llvm-project?rev=106122&view=rev Log: This requires more investigation. Unblock buildbots for now. Modified: llvm/trunk/test/DebugInfo/2010-06-01-DeadArg-DbgInfo.ll Modified: llvm/trunk/test/DebugInfo/2010-06-01-DeadArg-DbgInfo.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/2010-06-01-DeadArg-DbgInfo.ll?rev=106122&r1=106121&r2=106122&view=diff ============================================================================== --- llvm/trunk/test/DebugInfo/2010-06-01-DeadArg-DbgInfo.ll (original) +++ llvm/trunk/test/DebugInfo/2010-06-01-DeadArg-DbgInfo.ll Wed Jun 16 13:19:49 2010 @@ -1,7 +1,7 @@ ; RUN: llc -O2 %s -o %t -; RUN: grep this %t | grep -v undef +; RUN: grep "this <- undef" %t | count 0 ; Test to check that unused argument 'this' is not undefined in debug info. - +; XFAIL: * %struct.foo = type { i32 } @llvm.used = appending global [1 x i8*] [i8* bitcast (i32 (%struct.foo*, i32)* @_ZN3foo3bazEi to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] From grosbach at apple.com Wed Jun 16 13:45:08 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 16 Jun 2010 18:45:08 -0000 Subject: [llvm-commits] [llvm] r106126 - /llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Message-ID: <20100616184508.7A9942A6C12C@llvm.org> Author: grosbach Date: Wed Jun 16 13:45:08 2010 New Revision: 106126 URL: http://llvm.org/viewvc/llvm-project?rev=106126&view=rev Log: add FIXME Modified: llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Modified: llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp?rev=106126&r1=106125&r2=106126&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp (original) +++ llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Wed Jun 16 13:45:08 2010 @@ -289,6 +289,9 @@ } // If we decided we need a spill, do it. + // FIXME: Spilling this way is overkill, as it forces all uses of + // the value to be reloaded from the stack slot, even those that aren't + // in the unwind blocks. We should be more selective. if (NeedsSpill) { ++NumSpilled; DemoteRegToStack(*Inst, true); From rafael.espindola at gmail.com Wed Jun 16 14:34:01 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Wed, 16 Jun 2010 19:34:01 -0000 Subject: [llvm-commits] [llvm] r106134 - in /llvm/trunk: lib/Transforms/Scalar/SimplifyLibCalls.cpp test/Transforms/SimplifyLibCalls/PR7357.ll Message-ID: <20100616193401.40E792A6C12C@llvm.org> Author: rafael Date: Wed Jun 16 14:34:01 2010 New Revision: 106134 URL: http://llvm.org/viewvc/llvm-project?rev=106134&view=rev Log: Make sure that simplify libcalls does not replace a call with one calling convention with a new call with a different calling convention. Added: llvm/trunk/test/Transforms/SimplifyLibCalls/PR7357.ll Modified: llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Modified: llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp?rev=106134&r1=106133&r2=106134&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Wed Jun 16 14:34:01 2010 @@ -66,6 +66,11 @@ this->TD = TD; if (CI->getCalledFunction()) Context = &CI->getCalledFunction()->getContext(); + + // We never change the calling convention. + if (CI->getCallingConv() != llvm::CallingConv::C) + return NULL; + return CallOptimizer(CI->getCalledFunction(), CI, B); } }; Added: llvm/trunk/test/Transforms/SimplifyLibCalls/PR7357.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyLibCalls/PR7357.ll?rev=106134&view=auto ============================================================================== --- llvm/trunk/test/Transforms/SimplifyLibCalls/PR7357.ll (added) +++ llvm/trunk/test/Transforms/SimplifyLibCalls/PR7357.ll Wed Jun 16 14:34:01 2010 @@ -0,0 +1,16 @@ +; RUN: opt < %s -default-data-layout="e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32" -simplify-libcalls -S | FileCheck %s + at .str1 = private constant [11 x i8] c"(){};[]&|:\00", align 4 + +; check that simplify libcalls will not replace a call with one calling +; convention with a new call with a different calling convention. + +; CHECK: define arm_aapcscc i32 @foo(i32 %argc) +; CHECK: call arm_aapcscc i8* @strchr +define arm_aapcscc i32 @foo(i32 %argc) nounwind { +bb.nph: + call arm_aapcscc i8* @strchr(i8* getelementptr ([11 x i8]* @.str1, i32 0, +i32 0), i32 %argc) nounwind readonly + ret i32 0 +} + +declare arm_aapcscc i8* @strchr(i8*, i32) nounwind readonly From dpatel at apple.com Wed Jun 16 14:39:46 2010 From: dpatel at apple.com (Devang Patel) Date: Wed, 16 Jun 2010 19:39:46 -0000 Subject: [llvm-commits] [llvm] r106135 - /llvm/trunk/test/DebugInfo/2010-06-01-DeadArg-DbgInfo.ll Message-ID: <20100616193946.0E4452A6C12D@llvm.org> Author: dpatel Date: Wed Jun 16 14:39:45 2010 New Revision: 106135 URL: http://llvm.org/viewvc/llvm-project?rev=106135&view=rev Log: Be specific. Use FileCheck. Modified: llvm/trunk/test/DebugInfo/2010-06-01-DeadArg-DbgInfo.ll Modified: llvm/trunk/test/DebugInfo/2010-06-01-DeadArg-DbgInfo.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/2010-06-01-DeadArg-DbgInfo.ll?rev=106135&r1=106134&r2=106135&view=diff ============================================================================== --- llvm/trunk/test/DebugInfo/2010-06-01-DeadArg-DbgInfo.ll (original) +++ llvm/trunk/test/DebugInfo/2010-06-01-DeadArg-DbgInfo.ll Wed Jun 16 14:39:45 2010 @@ -1,12 +1,13 @@ -; RUN: llc -O2 %s -o %t -; RUN: grep "this <- undef" %t | count 0 +; RUN: llc -O2 < %s | FileCheck %s ; Test to check that unused argument 'this' is not undefined in debug info. -; XFAIL: * + +target triple = "x86_64-apple-darwin10.2" %struct.foo = type { i32 } @llvm.used = appending global [1 x i8*] [i8* bitcast (i32 (%struct.foo*, i32)* @_ZN3foo3bazEi to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] define i32 @_ZN3foo3bazEi(%struct.foo* nocapture %this, i32 %x) nounwind readnone optsize noinline ssp align 2 { +;CHECK: DEBUG_VALUE: baz:this <- RDI+0 entry: tail call void @llvm.dbg.value(metadata !{%struct.foo* %this}, i64 0, metadata !15) tail call void @llvm.dbg.value(metadata !{i32 %x}, i64 0, metadata !16) From simmon12 at illinois.edu Wed Jun 16 14:54:14 2010 From: simmon12 at illinois.edu (Patrick Simmons) Date: Wed, 16 Jun 2010 19:54:14 -0000 Subject: [llvm-commits] [poolalloc] r106138 - in /poolalloc/trunk: include/dsa/DataStructure.h lib/DSA/CMakeLists.txt lib/DSA/Local.cpp lib/rDSA/CMakeLists.txt Message-ID: <20100616195414.6F9A52A6C12C@llvm.org> Author: psimmons Date: Wed Jun 16 14:54:14 2010 New Revision: 106138 URL: http://llvm.org/viewvc/llvm-project?rev=106138&view=rev Log: Fix big related to EntryPointAnalysis being used without being required in BU-eq Removed: poolalloc/trunk/lib/rDSA/CMakeLists.txt Modified: poolalloc/trunk/include/dsa/DataStructure.h poolalloc/trunk/lib/DSA/CMakeLists.txt poolalloc/trunk/lib/DSA/Local.cpp Modified: poolalloc/trunk/include/dsa/DataStructure.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/dsa/DataStructure.h?rev=106138&r1=106137&r2=106138&view=diff ============================================================================== --- poolalloc/trunk/include/dsa/DataStructure.h (original) +++ poolalloc/trunk/include/dsa/DataStructure.h Wed Jun 16 14:54:14 2010 @@ -285,6 +285,7 @@ virtual bool runOnModule(Module &M); virtual void getAnalysisUsage(AnalysisUsage &AU) const { + AU.addRequired(); AU.addRequired(); AU.setPreservesCFG(); } Modified: poolalloc/trunk/lib/DSA/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/CMakeLists.txt?rev=106138&r1=106137&r2=106138&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/CMakeLists.txt (original) +++ poolalloc/trunk/lib/DSA/CMakeLists.txt Wed Jun 16 14:54:14 2010 @@ -1,2 +1,2 @@ -file(GLOB sources *.cpp) +file(GLOB sources "*.cpp") add_llvm_library( LLVMDataStructure ${sources} ) Modified: poolalloc/trunk/lib/DSA/Local.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/Local.cpp?rev=106138&r1=106137&r2=106138&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/Local.cpp (original) +++ poolalloc/trunk/lib/DSA/Local.cpp Wed Jun 16 14:54:14 2010 @@ -683,6 +683,14 @@ return true; } + case Intrinsic::eh_selector: { + DSNode * Node = createNode(); + Node->setIncompleteMarker(); + Node->foldNodeCompletely(); + setDestTo (*(CS.getInstruction()), Node); + return true; + } + case Intrinsic::atomic_cmp_swap: { DSNodeHandle Ptr = getValueDest(*CS.arg_begin()); Ptr.getNode()->setReadMarker(); Removed: poolalloc/trunk/lib/rDSA/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/rDSA/CMakeLists.txt?rev=106137&view=auto ============================================================================== --- poolalloc/trunk/lib/rDSA/CMakeLists.txt (original) +++ poolalloc/trunk/lib/rDSA/CMakeLists.txt (removed) @@ -1,2 +0,0 @@ -file(GLOB sources *.cpp) -add_llvm_library( rDSA ${sources} ) From daniel at zuster.org Wed Jun 16 15:04:22 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 16 Jun 2010 20:04:22 -0000 Subject: [llvm-commits] [llvm] r106140 - in /llvm/trunk: include/llvm/MC/MCObjectStreamer.h lib/MC/CMakeLists.txt lib/MC/MCMachOStreamer.cpp lib/MC/MCObjectStreamer.cpp Message-ID: <20100616200422.39F9C2A6C12C@llvm.org> Author: ddunbar Date: Wed Jun 16 15:04:22 2010 New Revision: 106140 URL: http://llvm.org/viewvc/llvm-project?rev=106140&view=rev Log: MC: Factor out an MCObjectStreamer class, which will be shared by the concrete object file format writers. Added: llvm/trunk/include/llvm/MC/MCObjectStreamer.h llvm/trunk/lib/MC/MCObjectStreamer.cpp Modified: llvm/trunk/lib/MC/CMakeLists.txt llvm/trunk/lib/MC/MCMachOStreamer.cpp Added: llvm/trunk/include/llvm/MC/MCObjectStreamer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCObjectStreamer.h?rev=106140&view=auto ============================================================================== --- llvm/trunk/include/llvm/MC/MCObjectStreamer.h (added) +++ llvm/trunk/include/llvm/MC/MCObjectStreamer.h Wed Jun 16 15:04:22 2010 @@ -0,0 +1,43 @@ +//===- MCObjectStreamer.h - MCStreamer Object File Interface ----*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_MC_MCOBJECTSTREAMER_H +#define LLVM_MC_MCOBJECTSTREAMER_H + +#include "llvm/MC/MCStreamer.h" + +namespace llvm { +class MCAssembler; +class MCCodeEmitter; +class MCSectionData; +class TargetAsmBackend; +class raw_ostream; + +/// \brief Streaming object file generation interface. +/// +/// This class provides an implementation of the MCStreamer interface which is +/// suitable for use with the assembler backend. Specific object file formats +/// are expected to subclass this interface to implement directives specific +/// to that file format or custom semantics expected by the object writer +/// implementation. +class MCObjectStreamer : public MCStreamer { + MCAssembler *Assembler; + +protected: + MCObjectStreamer(MCContext &Context, TargetAsmBackend &TAB, + raw_ostream &_OS, MCCodeEmitter *_Emitter); + ~MCObjectStreamer(); + +public: + MCAssembler &getAssembler() { return *Assembler; } +}; + +} // end namespace llvm + +#endif Modified: llvm/trunk/lib/MC/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/CMakeLists.txt?rev=106140&r1=106139&r2=106140&view=diff ============================================================================== --- llvm/trunk/lib/MC/CMakeLists.txt (original) +++ llvm/trunk/lib/MC/CMakeLists.txt Wed Jun 16 15:04:22 2010 @@ -14,6 +14,7 @@ MCLoggingStreamer.cpp MCMachOStreamer.cpp MCNullStreamer.cpp + MCObjectStreamer.cpp MCObjectWriter.cpp MCSection.cpp MCSectionCOFF.cpp Modified: llvm/trunk/lib/MC/MCMachOStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCMachOStreamer.cpp?rev=106140&r1=106139&r2=106140&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCMachOStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCMachOStreamer.cpp Wed Jun 16 15:04:22 2010 @@ -14,6 +14,7 @@ #include "llvm/MC/MCCodeEmitter.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" +#include "llvm/MC/MCObjectStreamer.h" #include "llvm/MC/MCSection.h" #include "llvm/MC/MCSymbol.h" #include "llvm/MC/MCMachOSymbolFlags.h" @@ -25,10 +26,9 @@ namespace { -class MCMachOStreamer : public MCStreamer { +class MCMachOStreamer : public MCObjectStreamer { private: - MCAssembler Assembler; MCSectionData *CurSectionData; /// Track the current atom for each section. @@ -65,12 +65,8 @@ public: MCMachOStreamer(MCContext &Context, TargetAsmBackend &TAB, - raw_ostream &_OS, MCCodeEmitter *_Emitter) - : MCStreamer(Context), Assembler(Context, TAB, *_Emitter, _OS), - CurSectionData(0) {} - ~MCMachOStreamer() {} - - MCAssembler &getAssembler() { return Assembler; } + raw_ostream &OS, MCCodeEmitter *Emitter) + : MCObjectStreamer(Context, TAB, OS, Emitter), CurSectionData(0) {} const MCExpr *AddValueSymbols(const MCExpr *Value) { switch (Value->getKind()) { @@ -86,7 +82,7 @@ } case MCExpr::SymbolRef: - Assembler.getOrCreateSymbolData( + getAssembler().getOrCreateSymbolData( cast(Value)->getSymbol()); break; @@ -166,7 +162,7 @@ if (Section == CurSection) return; CurSection = Section; - CurSectionData = &Assembler.getOrCreateSectionData(*Section); + CurSectionData = &getAssembler().getOrCreateSectionData(*Section); } void MCMachOStreamer::EmitLabel(MCSymbol *Symbol) { @@ -174,11 +170,11 @@ assert(!Symbol->isVariable() && "Cannot emit a variable symbol!"); assert(CurSection && "Cannot emit before setting section!"); - MCSymbolData &SD = Assembler.getOrCreateSymbolData(*Symbol); + MCSymbolData &SD = getAssembler().getOrCreateSymbolData(*Symbol); // Update the current atom map, if necessary. bool MustCreateFragment = false; - if (Assembler.isSymbolLinkerVisible(&SD)) { + if (getAssembler().isSymbolLinkerVisible(&SD)) { CurrentAtomMap[CurSectionData] = &SD; // We have to create a new fragment, fragments cannot span atoms. @@ -210,7 +206,7 @@ void MCMachOStreamer::EmitAssemblerFlag(MCAssemblerFlag Flag) { switch (Flag) { case MCAF_SubsectionsViaSymbols: - Assembler.setSubsectionsViaSymbols(true); + getAssembler().setSubsectionsViaSymbols(true); return; } @@ -219,7 +215,7 @@ void MCMachOStreamer::EmitAssignment(MCSymbol *Symbol, const MCExpr *Value) { // FIXME: Lift context changes into super class. - Assembler.getOrCreateSymbolData(*Symbol); + getAssembler().getOrCreateSymbolData(*Symbol); Symbol->setVariableValue(AddValueSymbols(Value)); } @@ -233,14 +229,14 @@ IndirectSymbolData ISD; ISD.Symbol = Symbol; ISD.SectionData = CurSectionData; - Assembler.getIndirectSymbols().push_back(ISD); + getAssembler().getIndirectSymbols().push_back(ISD); return; } // Adding a symbol attribute always introduces the symbol, note that an // important side effect of calling getOrCreateSymbolData here is to register // the symbol with the assembler. - MCSymbolData &SD = Assembler.getOrCreateSymbolData(*Symbol); + MCSymbolData &SD = getAssembler().getOrCreateSymbolData(*Symbol); // The implementation of symbol attributes is designed to match 'as', but it // leaves much to desired. It doesn't really make sense to arbitrarily add and @@ -313,7 +309,8 @@ // Encode the 'desc' value into the lowest implementation defined bits. assert(DescValue == (DescValue & SF_DescFlagsMask) && "Invalid .desc value!"); - Assembler.getOrCreateSymbolData(*Symbol).setFlags(DescValue&SF_DescFlagsMask); + getAssembler().getOrCreateSymbolData(*Symbol).setFlags( + DescValue & SF_DescFlagsMask); } void MCMachOStreamer::EmitCommonSymbol(MCSymbol *Symbol, uint64_t Size, @@ -321,14 +318,14 @@ // FIXME: Darwin 'as' does appear to allow redef of a .comm by itself. assert(Symbol->isUndefined() && "Cannot define a symbol twice!"); - MCSymbolData &SD = Assembler.getOrCreateSymbolData(*Symbol); + MCSymbolData &SD = getAssembler().getOrCreateSymbolData(*Symbol); SD.setExternal(true); SD.setCommon(Size, ByteAlignment); } void MCMachOStreamer::EmitZerofill(const MCSection *Section, MCSymbol *Symbol, unsigned Size, unsigned ByteAlignment) { - MCSectionData &SectData = Assembler.getOrCreateSectionData(*Section); + MCSectionData &SectData = getAssembler().getOrCreateSectionData(*Section); // The symbol may not be present, which only creates the section. if (!Symbol) @@ -338,7 +335,7 @@ assert(Symbol->isUndefined() && "Cannot define a symbol twice!"); - MCSymbolData &SD = Assembler.getOrCreateSymbolData(*Symbol); + MCSymbolData &SD = getAssembler().getOrCreateSymbolData(*Symbol); // Emit an align fragment if necessary. if (ByteAlignment != 1) @@ -346,7 +343,7 @@ MCFragment *F = new MCFillFragment(0, 0, Size, &SectData); SD.setFragment(F); - if (Assembler.isSymbolLinkerVisible(&SD)) + if (getAssembler().isSymbolLinkerVisible(&SD)) F->setAtom(&SD); Symbol->setSection(*Section); @@ -431,7 +428,7 @@ SmallVector Fixups; SmallString<256> Code; raw_svector_ostream VecOS(Code); - Assembler.getEmitter().EncodeInstruction(Inst, VecOS, Fixups); + getAssembler().getEmitter().EncodeInstruction(Inst, VecOS, Fixups); VecOS.flush(); IF->getCode() = Code; @@ -444,7 +441,7 @@ SmallVector Fixups; SmallString<256> Code; raw_svector_ostream VecOS(Code); - Assembler.getEmitter().EncodeInstruction(Inst, VecOS, Fixups); + getAssembler().getEmitter().EncodeInstruction(Inst, VecOS, Fixups); VecOS.flush(); // Add the fixups and data. @@ -464,18 +461,18 @@ CurSectionData->setHasInstructions(true); // If this instruction doesn't need relaxation, just emit it as data. - if (!Assembler.getBackend().MayNeedRelaxation(Inst)) { + if (!getAssembler().getBackend().MayNeedRelaxation(Inst)) { EmitInstToData(Inst); return; } // Otherwise, if we are relaxing everything, relax the instruction as much as // possible and emit it as data. - if (Assembler.getRelaxAll()) { + if (getAssembler().getRelaxAll()) { MCInst Relaxed; - Assembler.getBackend().RelaxInstruction(Inst, Relaxed); - while (Assembler.getBackend().MayNeedRelaxation(Relaxed)) - Assembler.getBackend().RelaxInstruction(Relaxed, Relaxed); + getAssembler().getBackend().RelaxInstruction(Inst, Relaxed); + while (getAssembler().getBackend().MayNeedRelaxation(Relaxed)) + getAssembler().getBackend().RelaxInstruction(Relaxed, Relaxed); EmitInstToData(Relaxed); return; } @@ -485,7 +482,7 @@ } void MCMachOStreamer::Finish() { - Assembler.Finish(); + getAssembler().Finish(); } MCStreamer *llvm::createMachOStreamer(MCContext &Context, TargetAsmBackend &TAB, Added: llvm/trunk/lib/MC/MCObjectStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCObjectStreamer.cpp?rev=106140&view=auto ============================================================================== --- llvm/trunk/lib/MC/MCObjectStreamer.cpp (added) +++ llvm/trunk/lib/MC/MCObjectStreamer.cpp Wed Jun 16 15:04:22 2010 @@ -0,0 +1,24 @@ +//===- lib/MC/MCObjectStreamer.cpp - Object File MCStreamer Interface -----===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "llvm/MC/MCObjectStreamer.h" + +#include "llvm/MC/MCAssembler.h" +using namespace llvm; + +MCObjectStreamer::MCObjectStreamer(MCContext &Context, TargetAsmBackend &TAB, + raw_ostream &_OS, MCCodeEmitter *_Emitter) + : MCStreamer(Context), + Assembler(new MCAssembler(Context, TAB, *_Emitter, _OS)) +{ +} + +MCObjectStreamer::~MCObjectStreamer() { + delete Assembler; +} From daniel at zuster.org Wed Jun 16 15:04:25 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 16 Jun 2010 20:04:25 -0000 Subject: [llvm-commits] [llvm] r106141 - in /llvm/trunk: include/llvm/MC/MCObjectStreamer.h lib/MC/MCMachOStreamer.cpp lib/MC/MCObjectStreamer.cpp Message-ID: <20100616200425.BA8EF2A6C12D@llvm.org> Author: ddunbar Date: Wed Jun 16 15:04:25 2010 New Revision: 106141 URL: http://llvm.org/viewvc/llvm-project?rev=106141&view=rev Log: MC: Lift SwitchSection() and Finish() into MCObjectStreamer. Modified: llvm/trunk/include/llvm/MC/MCObjectStreamer.h llvm/trunk/lib/MC/MCMachOStreamer.cpp llvm/trunk/lib/MC/MCObjectStreamer.cpp Modified: llvm/trunk/include/llvm/MC/MCObjectStreamer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCObjectStreamer.h?rev=106141&r1=106140&r2=106141&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCObjectStreamer.h (original) +++ llvm/trunk/include/llvm/MC/MCObjectStreamer.h Wed Jun 16 15:04:25 2010 @@ -28,14 +28,27 @@ /// implementation. class MCObjectStreamer : public MCStreamer { MCAssembler *Assembler; + MCSectionData *CurSectionData; protected: MCObjectStreamer(MCContext &Context, TargetAsmBackend &TAB, raw_ostream &_OS, MCCodeEmitter *_Emitter); ~MCObjectStreamer(); + MCSectionData *getCurrentSectionData() const { + return CurSectionData; + } + public: MCAssembler &getAssembler() { return *Assembler; } + + /// @name MCStreamer Interface + /// @{ + + virtual void SwitchSection(const MCSection *Section); + virtual void Finish(); + + /// @} }; } // end namespace llvm Modified: llvm/trunk/lib/MC/MCMachOStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCMachOStreamer.cpp?rev=106141&r1=106140&r2=106141&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCMachOStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCMachOStreamer.cpp Wed Jun 16 15:04:25 2010 @@ -27,19 +27,16 @@ namespace { class MCMachOStreamer : public MCObjectStreamer { - private: - MCSectionData *CurSectionData; - /// Track the current atom for each section. DenseMap CurrentAtomMap; private: MCFragment *getCurrentFragment() const { - assert(CurSectionData && "No current section!"); + assert(getCurrentSectionData() && "No current section!"); - if (!CurSectionData->empty()) - return &CurSectionData->getFragmentList().back(); + if (!getCurrentSectionData()->empty()) + return &getCurrentSectionData()->getFragmentList().back(); return 0; } @@ -55,8 +52,8 @@ /// Create a new data fragment in the current section. MCDataFragment *createDataFragment() const { - MCDataFragment *DF = new MCDataFragment(CurSectionData); - DF->setAtom(CurrentAtomMap.lookup(CurSectionData)); + MCDataFragment *DF = new MCDataFragment(getCurrentSectionData()); + DF->setAtom(CurrentAtomMap.lookup(getCurrentSectionData())); return DF; } @@ -66,7 +63,7 @@ public: MCMachOStreamer(MCContext &Context, TargetAsmBackend &TAB, raw_ostream &OS, MCCodeEmitter *Emitter) - : MCObjectStreamer(Context, TAB, OS, Emitter), CurSectionData(0) {} + : MCObjectStreamer(Context, TAB, OS, Emitter) {} const MCExpr *AddValueSymbols(const MCExpr *Value) { switch (Value->getKind()) { @@ -97,7 +94,6 @@ /// @name MCStreamer Interface /// @{ - virtual void SwitchSection(const MCSection *Section); virtual void EmitLabel(MCSymbol *Symbol); virtual void EmitAssemblerFlag(MCAssemblerFlag Flag); virtual void EmitAssignment(MCSymbol *Symbol, const MCExpr *Value); @@ -148,23 +144,12 @@ } virtual void EmitInstruction(const MCInst &Inst); - virtual void Finish(); /// @} }; } // end anonymous namespace. -void MCMachOStreamer::SwitchSection(const MCSection *Section) { - assert(Section && "Cannot switch to a null section!"); - - // If already in this section, then this is a noop. - if (Section == CurSection) return; - - CurSection = Section; - CurSectionData = &getAssembler().getOrCreateSectionData(*Section); -} - void MCMachOStreamer::EmitLabel(MCSymbol *Symbol) { assert(Symbol->isUndefined() && "Cannot define a symbol twice!"); assert(!Symbol->isVariable() && "Cannot emit a variable symbol!"); @@ -175,7 +160,7 @@ // Update the current atom map, if necessary. bool MustCreateFragment = false; if (getAssembler().isSymbolLinkerVisible(&SD)) { - CurrentAtomMap[CurSectionData] = &SD; + CurrentAtomMap[getCurrentSectionData()] = &SD; // We have to create a new fragment, fragments cannot span atoms. MustCreateFragment = true; @@ -228,7 +213,7 @@ // important for matching the string table that 'as' generates. IndirectSymbolData ISD; ISD.Symbol = Symbol; - ISD.SectionData = CurSectionData; + ISD.SectionData = getCurrentSectionData(); getAssembler().getIndirectSymbols().push_back(ISD); return; } @@ -389,12 +374,12 @@ if (MaxBytesToEmit == 0) MaxBytesToEmit = ByteAlignment; MCFragment *F = new MCAlignFragment(ByteAlignment, Value, ValueSize, - MaxBytesToEmit, CurSectionData); - F->setAtom(CurrentAtomMap.lookup(CurSectionData)); + MaxBytesToEmit, getCurrentSectionData()); + F->setAtom(CurrentAtomMap.lookup(getCurrentSectionData())); // Update the maximum alignment on the current section if necessary. - if (ByteAlignment > CurSectionData->getAlignment()) - CurSectionData->setAlignment(ByteAlignment); + if (ByteAlignment > getCurrentSectionData()->getAlignment()) + getCurrentSectionData()->setAlignment(ByteAlignment); } void MCMachOStreamer::EmitCodeAlignment(unsigned ByteAlignment, @@ -402,24 +387,24 @@ if (MaxBytesToEmit == 0) MaxBytesToEmit = ByteAlignment; MCAlignFragment *F = new MCAlignFragment(ByteAlignment, 0, 1, MaxBytesToEmit, - CurSectionData); + getCurrentSectionData()); F->setEmitNops(true); - F->setAtom(CurrentAtomMap.lookup(CurSectionData)); + F->setAtom(CurrentAtomMap.lookup(getCurrentSectionData())); // Update the maximum alignment on the current section if necessary. - if (ByteAlignment > CurSectionData->getAlignment()) - CurSectionData->setAlignment(ByteAlignment); + if (ByteAlignment > getCurrentSectionData()->getAlignment()) + getCurrentSectionData()->setAlignment(ByteAlignment); } void MCMachOStreamer::EmitValueToOffset(const MCExpr *Offset, unsigned char Value) { - MCFragment *F = new MCOrgFragment(*Offset, Value, CurSectionData); - F->setAtom(CurrentAtomMap.lookup(CurSectionData)); + MCFragment *F = new MCOrgFragment(*Offset, Value, getCurrentSectionData()); + F->setAtom(CurrentAtomMap.lookup(getCurrentSectionData())); } void MCMachOStreamer::EmitInstToFragment(const MCInst &Inst) { - MCInstFragment *IF = new MCInstFragment(Inst, CurSectionData); - IF->setAtom(CurrentAtomMap.lookup(CurSectionData)); + MCInstFragment *IF = new MCInstFragment(Inst, getCurrentSectionData()); + IF->setAtom(CurrentAtomMap.lookup(getCurrentSectionData())); // Add the fixups and data. // @@ -458,7 +443,7 @@ if (Inst.getOperand(i).isExpr()) AddValueSymbols(Inst.getOperand(i).getExpr()); - CurSectionData->setHasInstructions(true); + getCurrentSectionData()->setHasInstructions(true); // If this instruction doesn't need relaxation, just emit it as data. if (!getAssembler().getBackend().MayNeedRelaxation(Inst)) { @@ -481,10 +466,6 @@ EmitInstToFragment(Inst); } -void MCMachOStreamer::Finish() { - getAssembler().Finish(); -} - MCStreamer *llvm::createMachOStreamer(MCContext &Context, TargetAsmBackend &TAB, raw_ostream &OS, MCCodeEmitter *CE, bool RelaxAll) { Modified: llvm/trunk/lib/MC/MCObjectStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCObjectStreamer.cpp?rev=106141&r1=106140&r2=106141&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCObjectStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCObjectStreamer.cpp Wed Jun 16 15:04:25 2010 @@ -14,11 +14,26 @@ MCObjectStreamer::MCObjectStreamer(MCContext &Context, TargetAsmBackend &TAB, raw_ostream &_OS, MCCodeEmitter *_Emitter) - : MCStreamer(Context), - Assembler(new MCAssembler(Context, TAB, *_Emitter, _OS)) + : MCStreamer(Context), Assembler(new MCAssembler(Context, TAB, + *_Emitter, _OS)), + CurSectionData(0) { } MCObjectStreamer::~MCObjectStreamer() { delete Assembler; } + +void MCObjectStreamer::SwitchSection(const MCSection *Section) { + assert(Section && "Cannot switch to a null section!"); + + // If already in this section, then this is a noop. + if (Section == CurSection) return; + + CurSection = Section; + CurSectionData = &getAssembler().getOrCreateSectionData(*Section); +} + +void MCObjectStreamer::Finish() { + getAssembler().Finish(); +} From daniel at zuster.org Wed Jun 16 15:04:29 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 16 Jun 2010 20:04:29 -0000 Subject: [llvm-commits] [llvm] r106142 - in /llvm/trunk: include/llvm/MC/MCAssembler.h lib/MC/MCAssembler.cpp lib/MC/MCMachOStreamer.cpp lib/MC/MachObjectWriter.cpp Message-ID: <20100616200429.974C02A6C12C@llvm.org> Author: ddunbar Date: Wed Jun 16 15:04:29 2010 New Revision: 106142 URL: http://llvm.org/viewvc/llvm-project?rev=106142&view=rev Log: MC: Simplify MCAssembler::isSymbolLinkerVisible to only take an MCSymbol. Modified: llvm/trunk/include/llvm/MC/MCAssembler.h llvm/trunk/lib/MC/MCAssembler.cpp llvm/trunk/lib/MC/MCMachOStreamer.cpp llvm/trunk/lib/MC/MachObjectWriter.cpp Modified: llvm/trunk/include/llvm/MC/MCAssembler.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAssembler.h?rev=106142&r1=106141&r2=106142&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCAssembler.h (original) +++ llvm/trunk/include/llvm/MC/MCAssembler.h Wed Jun 16 15:04:29 2010 @@ -641,7 +641,7 @@ /// in the symbol table, or whether it can be discarded by the assembler. This /// also effects whether the assembler treats the label as potentially /// defining a separate atom. - bool isSymbolLinkerVisible(const MCSymbolData *SD) const; + bool isSymbolLinkerVisible(const MCSymbol &SD) const; /// Emit the section contents using the given object writer. // Modified: llvm/trunk/lib/MC/MCAssembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=106142&r1=106141&r2=106142&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAssembler.cpp (original) +++ llvm/trunk/lib/MC/MCAssembler.cpp Wed Jun 16 15:04:29 2010 @@ -308,24 +308,23 @@ return !B_Base && BaseSymbol == A_Base; } -bool MCAssembler::isSymbolLinkerVisible(const MCSymbolData *SD) const { +bool MCAssembler::isSymbolLinkerVisible(const MCSymbol &Symbol) const { // Non-temporary labels should always be visible to the linker. - if (!SD->getSymbol().isTemporary()) + if (!Symbol.isTemporary()) return true; // Absolute temporary labels are never visible. - if (!SD->getFragment()) + if (!Symbol.isInSection()) return false; // Otherwise, check if the section requires symbols even for temporary labels. - return getBackend().doesSectionRequireSymbols( - SD->getFragment()->getParent()->getSection()); + return getBackend().doesSectionRequireSymbols(Symbol.getSection()); } const MCSymbolData *MCAssembler::getAtom(const MCAsmLayout &Layout, const MCSymbolData *SD) const { // Linker visible symbols define atoms. - if (isSymbolLinkerVisible(SD)) + if (isSymbolLinkerVisible(SD->getSymbol())) return SD; // Absolute and undefined symbols have no defining atom. Modified: llvm/trunk/lib/MC/MCMachOStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCMachOStreamer.cpp?rev=106142&r1=106141&r2=106142&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCMachOStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCMachOStreamer.cpp Wed Jun 16 15:04:29 2010 @@ -159,7 +159,7 @@ // Update the current atom map, if necessary. bool MustCreateFragment = false; - if (getAssembler().isSymbolLinkerVisible(&SD)) { + if (getAssembler().isSymbolLinkerVisible(SD.getSymbol())) { CurrentAtomMap[getCurrentSectionData()] = &SD; // We have to create a new fragment, fragments cannot span atoms. @@ -328,7 +328,7 @@ MCFragment *F = new MCFillFragment(0, 0, Size, &SectData); SD.setFragment(F); - if (getAssembler().isSymbolLinkerVisible(&SD)) + if (getAssembler().isSymbolLinkerVisible(SD.getSymbol())) F->setAtom(&SD); Symbol->setSection(*Section); Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MachObjectWriter.cpp?rev=106142&r1=106141&r2=106142&view=diff ============================================================================== --- llvm/trunk/lib/MC/MachObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/MachObjectWriter.cpp Wed Jun 16 15:04:29 2010 @@ -936,7 +936,7 @@ const MCSymbol &Symbol = it->getSymbol(); // Ignore non-linker visible symbols. - if (!Asm.isSymbolLinkerVisible(it)) + if (!Asm.isSymbolLinkerVisible(it->getSymbol())) continue; if (!it->isExternal() && !Symbol.isUndefined()) @@ -972,7 +972,7 @@ const MCSymbol &Symbol = it->getSymbol(); // Ignore non-linker visible symbols. - if (!Asm.isSymbolLinkerVisible(it)) + if (!Asm.isSymbolLinkerVisible(it->getSymbol())) continue; if (it->isExternal() || Symbol.isUndefined()) From daniel at zuster.org Wed Jun 16 15:04:32 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 16 Jun 2010 20:04:32 -0000 Subject: [llvm-commits] [llvm] r106143 - /llvm/trunk/lib/MC/MCMachOStreamer.cpp Message-ID: <20100616200432.30A4F2A6C12E@llvm.org> Author: ddunbar Date: Wed Jun 16 15:04:32 2010 New Revision: 106143 URL: http://llvm.org/viewvc/llvm-project?rev=106143&view=rev Log: MC/Mach-O: Rewrite atom association to be a final pass we do in Finish(), instead of tracking as part of emission. - This allows sharing more code with the MCObjectStreamer. Modified: llvm/trunk/lib/MC/MCMachOStreamer.cpp Modified: llvm/trunk/lib/MC/MCMachOStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCMachOStreamer.cpp?rev=106143&r1=106142&r2=106143&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCMachOStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCMachOStreamer.cpp Wed Jun 16 15:04:32 2010 @@ -28,10 +28,6 @@ class MCMachOStreamer : public MCObjectStreamer { private: - /// Track the current atom for each section. - DenseMap CurrentAtomMap; - -private: MCFragment *getCurrentFragment() const { assert(getCurrentSectionData() && "No current section!"); @@ -46,17 +42,10 @@ MCDataFragment *getOrCreateDataFragment() const { MCDataFragment *F = dyn_cast_or_null(getCurrentFragment()); if (!F) - F = createDataFragment(); + F = new MCDataFragment(getCurrentSectionData()); return F; } - /// Create a new data fragment in the current section. - MCDataFragment *createDataFragment() const { - MCDataFragment *DF = new MCDataFragment(getCurrentSectionData()); - DF->setAtom(CurrentAtomMap.lookup(getCurrentSectionData())); - return DF; - } - void EmitInstToFragment(const MCInst &Inst); void EmitInstToData(const MCInst &Inst); @@ -145,6 +134,8 @@ virtual void EmitInstruction(const MCInst &Inst); + virtual void Finish(); + /// @} }; @@ -155,23 +146,20 @@ assert(!Symbol->isVariable() && "Cannot emit a variable symbol!"); assert(CurSection && "Cannot emit before setting section!"); - MCSymbolData &SD = getAssembler().getOrCreateSymbolData(*Symbol); + Symbol->setSection(*CurSection); - // Update the current atom map, if necessary. - bool MustCreateFragment = false; - if (getAssembler().isSymbolLinkerVisible(SD.getSymbol())) { - CurrentAtomMap[getCurrentSectionData()] = &SD; + MCSymbolData &SD = getAssembler().getOrCreateSymbolData(*Symbol); - // We have to create a new fragment, fragments cannot span atoms. - MustCreateFragment = true; - } + // We have to create a new fragment if this is an atom defining symbol, + // fragments cannot span atoms. + if (getAssembler().isSymbolLinkerVisible(SD.getSymbol())) + new MCDataFragment(getCurrentSectionData()); // FIXME: This is wasteful, we don't necessarily need to create a data // fragment. Instead, we should mark the symbol as pointing into the data // fragment if it exists, otherwise we should just queue the label and set its // fragment pointer when we emit the next fragment. - MCDataFragment *F = - MustCreateFragment ? createDataFragment() : getOrCreateDataFragment(); + MCDataFragment *F = getOrCreateDataFragment(); assert(!SD.getFragment() && "Unexpected fragment on symbol data!"); SD.setFragment(F); SD.setOffset(F->getContents().size()); @@ -184,8 +172,6 @@ // FIXME: Cleanup this code, these bits should be emitted based on semantic // properties, not on the order of definition, etc. SD.setFlags(SD.getFlags() & ~SF_ReferenceTypeMask); - - Symbol->setSection(*CurSection); } void MCMachOStreamer::EmitAssemblerFlag(MCAssemblerFlag Flag) { @@ -328,8 +314,6 @@ MCFragment *F = new MCFillFragment(0, 0, Size, &SectData); SD.setFragment(F); - if (getAssembler().isSymbolLinkerVisible(SD.getSymbol())) - F->setAtom(&SD); Symbol->setSection(*Section); @@ -373,9 +357,8 @@ unsigned MaxBytesToEmit) { if (MaxBytesToEmit == 0) MaxBytesToEmit = ByteAlignment; - MCFragment *F = new MCAlignFragment(ByteAlignment, Value, ValueSize, - MaxBytesToEmit, getCurrentSectionData()); - F->setAtom(CurrentAtomMap.lookup(getCurrentSectionData())); + new MCAlignFragment(ByteAlignment, Value, ValueSize, MaxBytesToEmit, + getCurrentSectionData()); // Update the maximum alignment on the current section if necessary. if (ByteAlignment > getCurrentSectionData()->getAlignment()) @@ -389,7 +372,6 @@ MCAlignFragment *F = new MCAlignFragment(ByteAlignment, 0, 1, MaxBytesToEmit, getCurrentSectionData()); F->setEmitNops(true); - F->setAtom(CurrentAtomMap.lookup(getCurrentSectionData())); // Update the maximum alignment on the current section if necessary. if (ByteAlignment > getCurrentSectionData()->getAlignment()) @@ -398,13 +380,11 @@ void MCMachOStreamer::EmitValueToOffset(const MCExpr *Offset, unsigned char Value) { - MCFragment *F = new MCOrgFragment(*Offset, Value, getCurrentSectionData()); - F->setAtom(CurrentAtomMap.lookup(getCurrentSectionData())); + new MCOrgFragment(*Offset, Value, getCurrentSectionData()); } void MCMachOStreamer::EmitInstToFragment(const MCInst &Inst) { MCInstFragment *IF = new MCInstFragment(Inst, getCurrentSectionData()); - IF->setAtom(CurrentAtomMap.lookup(getCurrentSectionData())); // Add the fixups and data. // @@ -466,6 +446,39 @@ EmitInstToFragment(Inst); } +void MCMachOStreamer::Finish() { + // We have to set the fragment atom associations so we can relax properly for + // Mach-O. + + // First, scan the symbol table to build a lookup table from fragments to + // defining symbols. + DenseMap DefiningSymbolMap; + for (MCAssembler::symbol_iterator it = getAssembler().symbol_begin(), + ie = getAssembler().symbol_end(); it != ie; ++it) { + if (getAssembler().isSymbolLinkerVisible(it->getSymbol()) && + it->getFragment()) { + // An atom defining symbol should never be internal to a fragment. + assert(it->getOffset() == 0 && "Invalid offset in atom defining symbol!"); + DefiningSymbolMap[it->getFragment()] = it; + } + } + + // Set the fragment atom associations by tracking the last seen atom defining + // symbol. + for (MCAssembler::iterator it = getAssembler().begin(), + ie = getAssembler().end(); it != ie; ++it) { + MCSymbolData *CurrentAtom = 0; + for (MCSectionData::iterator it2 = it->begin(), + ie2 = it->end(); it2 != ie2; ++it2) { + if (MCSymbolData *SD = DefiningSymbolMap.lookup(it2)) + CurrentAtom = SD; + it2->setAtom(CurrentAtom); + } + } + + this->MCObjectStreamer::Finish(); +} + MCStreamer *llvm::createMachOStreamer(MCContext &Context, TargetAsmBackend &TAB, raw_ostream &OS, MCCodeEmitter *CE, bool RelaxAll) { From criswell at uiuc.edu Wed Jun 16 15:41:43 2010 From: criswell at uiuc.edu (John Criswell) Date: Wed, 16 Jun 2010 20:41:43 -0000 Subject: [llvm-commits] [poolalloc] r106145 - in /poolalloc/trunk/lib/PoolAllocate: PoolAllocate.cpp TransformFunctionBody.cpp Message-ID: <20100616204143.49ECC2A6C12C@llvm.org> Author: criswell Date: Wed Jun 16 15:41:43 2010 New Revision: 106145 URL: http://llvm.org/viewvc/llvm-project?rev=106145&view=rev Log: Added comments and improved formatting. Modified: poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp Modified: poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp?rev=106145&r1=106144&r2=106145&view=diff ============================================================================== --- poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp (original) +++ poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp Wed Jun 16 15:41:43 2010 @@ -138,10 +138,14 @@ // Map that maps an original function to its clone std::map FuncMap; + // // Now clone a function using the pool arg list obtained in the previous // pass over the modules. Loop over only the function initially in the // program, don't traverse newly added ones. If the function needs new // arguments, make its clone. + // + // FIXME: Can the code below invalidate the function iterator? + // std::set ClonedFunctions; for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I) if (!I->isDeclaration() && !ClonedFunctions.count(I) && @@ -367,10 +371,38 @@ G->getNodeForValue(*I).getNode()->markReachableNodes(NodesFromGlobals); } -static void MarkNodesWhichMustBePassedIn(DenseSet &MarkedNodes, - Function &F, DSGraph* G, - bool PassAllArguments) { +// +// Function: MarkNodesWhichMustBePassedIn() +// +// Description: +// Given a function and its DSGraph, determine which values will need to have +// their pools passed in from the caller. +// +// Inputs: +// F - A reference to the function to analyze. +// G - The DSGraph of the function F. +// PassAllArguments - Flags whether all arguments should have their pool +// handles passed into the function. +// +// Outputs: +// MarkedNodes - A set of DSNodes whose associated pools should be +// passed into the function when it is called. +// +static void +MarkNodesWhichMustBePassedIn (DenseSet &MarkedNodes, + Function &F, DSGraph* G, + bool PassAllArguments) { // Mark globals and incomplete nodes as live... (this handles arguments) + + // + // Scan through all of the function's arguments. If they have an associated + // DSNode, then we need to pass the argument's pool handle into the function. + // We also need to pass in pools for any value that is reachable via a + // function argument. + // + // Of course, skip this is this function is the main() function. We can't + // really add pools to main(). :) + // if (F.getName() != "main") { // All DSNodes reachable from arguments must be passed in. for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); @@ -382,20 +414,30 @@ } } - // Marked the returned node as needing to be passed in. + // + // Mark the returned node as needing to be passed in. + // if (DSNode *RetNode = G->getReturnNodeFor(F).getNode()) RetNode->markReachableNodes(MarkedNodes); + // // Calculate which DSNodes are reachable from globals. If a node is reachable // from a global, we will create a global pool for it, so no argument passage // is required. + // DenseSet NodesFromGlobals; GetNodesReachableFromGlobals(G, NodesFromGlobals); + // // Remove any nodes reachable from a global. These nodes will be put into // global pools, which do not require arguments to be passed in. Also, erase // any marked node that is not a heap node. Since no allocations or frees // will be done with it, it needs no argument. + // + // FIXME: + // 1) PassAllArguments seems to be ignored here. Why is that? + // 2) Why is the heap node check part of the PassAllArguments check? + // for (DenseSet::iterator I = MarkedNodes.begin(), E = MarkedNodes.end(); I != E; ) { const DSNode *N = *I; ++I; @@ -449,13 +491,14 @@ if (MaxArgsAdded < FI.ArgNodes.size()) MaxArgsAdded = FI.ArgNodes.size(); ++NumCloned; - - // Figure out what the arguments are to be for the new version of the - // function - const FunctionType *OldFuncTy = F.getFunctionType(); + // + // Determine the type of the new function. We will insert new parameters + // for the pools to pass into the function, and then we will insert the + // original parameter values after that. + // std::vector ArgTys(FI.ArgNodes.size(), PoolDescPtrTy); + const FunctionType *OldFuncTy = F.getFunctionType(); ArgTys.reserve(OldFuncTy->getNumParams() + FI.ArgNodes.size()); - ArgTys.insert(ArgTys.end(), OldFuncTy->param_begin(), OldFuncTy->param_end()); // Create the new function prototype @@ -471,7 +514,6 @@ // pool descriptors map std::map &PoolDescriptors = FI.PoolDescriptors; Function::arg_iterator NI = New->arg_begin(); - for (unsigned i = 0, e = FI.ArgNodes.size(); i != e; ++i, ++NI) { NI->setName("PDa"); PoolDescriptors[FI.ArgNodes[i]] = NI; @@ -500,6 +542,10 @@ // verbatim. This is incorrect; each attribute should be shifted one so // that the pool descriptor has no attributes. // + // FIXME: I believe the code below assumes that we've only added one pool + // handle. We actually add one pool handle per incoming argument + // that needs a pool handle. + // const AttrListPtr OldAttrs = New->getAttributes(); if (!OldAttrs.isEmpty()) { AttrListPtr NewAttrsVector; @@ -519,9 +565,10 @@ New->setAttributes (NewAttrsVector); } - // Invert the ValueMap into the NewToOldValueMap + // + // Invert the ValueMap into the NewToOldValueMap. + // std::map &NewToOldValueMap = FI.NewToOldValueMap; - for (DenseMap::iterator I = ValueMap.begin(), E = ValueMap.end(); I != E; ++I) NewToOldValueMap.insert(std::make_pair(I->second, I->first)); @@ -661,10 +708,16 @@ // the DSNodes specified by the NodesToPA list. This adds an entry to the // PoolDescriptors map for each DSNode. // -void PoolAllocate::CreatePools(Function &F, DSGraph* DSG, - const std::vector &NodesToPA, - std::map &PoolDescriptors) { +// Note that this method does not insert calls to poolinit() or pooldestroy(). +// Those are added later. +// +void +PoolAllocate::CreatePools (Function &F, DSGraph* DSG, + const std::vector &NodesToPA, + std::map &PoolDescriptors) { + // + // If there are no pools to create, then do nothing. + // if (NodesToPA.empty()) return; std::vector ResultPools; @@ -679,13 +732,18 @@ // vars. bool IsMain = F.getNameStr() == "main" && F.hasExternalLinkage(); - // Perform all global assignments as specified. + // + // Create each pool and update the DSGraph to account for the new pool. + // Additionally, update the mapping between DSNodes and pools. + // for (unsigned i = 0, e = ResultPools.size(); i != e; ++i) { Heuristic::OnePool &Pool = ResultPools[i]; Value *PoolDesc = Pool.PoolDesc; if (PoolDesc == 0) { + // // Create a pool descriptor for the pool. The poolinit will be inserted // later. + // if (!IsMain) { PoolDesc = new AllocaInst(PoolDescType, 0, "PD", InsertPoint); @@ -705,13 +763,22 @@ ++NumTSPools; } } + + // + // Update the mapping of DSNodes to pool descriptors. + // + // FIXME: + // What are unallocated DSNodes? + // for (unsigned N = 0, e = Pool.NodesInPool.size(); N != e; ++N) { PoolDescriptors[Pool.NodesInPool[N]] = PoolDesc; UnallocatedNodes.erase(Pool.NodesInPool[N]); // Handled! } } + // // Any unallocated DSNodes get null pool descriptor pointers. + // for (std::set::iterator I = UnallocatedNodes.begin(), E = UnallocatedNodes.end(); I != E; ++I) { PoolDescriptors[*I] = ConstantPointerNull::get(PointerType::getUnqual(PoolDescType)); @@ -740,10 +807,20 @@ DSGraph::NodeMapTy GlobalsGraphNodeMapping; G->computeGToGGMapping(GlobalsGraphNodeMapping); + // // Loop over all of the nodes which are non-escaping, adding pool-allocatable - // ones to the NodesToPA vector. - for (DSGraph::node_iterator I = G->node_begin(), E = G->node_end(); I != E;++I){ - // We only need to make a pool if there is a heap object in it... + // ones to the NodesToPA vector. In other words, scan over the DSGraph and + // find nodes for which a new pool must be created within this function. + // + for (DSGraph::node_iterator I = G->node_begin(), E = G->node_end(); + I != E; + ++I){ + // + // Only the following nodes are pool allocated: + // 1) Heap nodes + // 2) Array nodes when bounds checking is enabled. + // 3) Nodes which are mirrored in the globals graph and are heap nodes. + // DSNode *N = I; if ((N->isHeapNode()) || (BoundsChecksEnabled && (N->isArrayNode())) || (GlobalsGraphNodeMapping.count(N) && GlobalsGraphNodeMapping[N].getNode()->isHeapNode())) { @@ -761,6 +838,9 @@ } } + // + // Add code to create the pools that are local to this function. + // if (!FI.NodesToPA.empty()) { errs() << "[" << F.getNameStr() << "] " << FI.NodesToPA.size() << " nodes pool allocatable\n"; @@ -1040,6 +1120,9 @@ assert(isa(PoolDescriptors[Node]) && "Why pool allocate this?"); AllocaInst *PD = cast(PoolDescriptors[Node]); + // + // FIXME: What is the purpose of the PoolUses and AllocasHandled code + // below? // FIXME: Turn this into an assert and fix the problem!! //assert(PoolUses.count(PD) && "Pool is not used, but is marked heap?!"); if (!PoolUses.count(PD) && !PoolFrees.count(PD)) continue; Modified: poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp?rev=106145&r1=106144&r2=106145&view=diff ============================================================================== --- poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp (original) +++ poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp Wed Jun 16 15:41:43 2010 @@ -50,7 +50,8 @@ // PoolUses - For each pool (identified by the pool descriptor) keep track // of which blocks require the memory in the pool to not be freed. This // does not include poolfree's. Note that this is only tracked for pools - // which this is the home of, ie, they are Alloca instructions. + // for which the given function is the pool's home i.e., the pool is an + // alloca instruction because it is allocated within the current function. std::multimap &PoolUses; // PoolDestroys - For each pool, keep track of the actual poolfree calls @@ -96,6 +97,14 @@ Instruction *TransformAllocationInstr(Instruction *I, Value *Size); Instruction *InsertPoolFreeInstr(Value *V, Instruction *Where); + // + // Method: UpdateNewToOldValueMap() + // + // Description: + // This method removes the old mapping indexed by OldVal and inserts one + // or two new mappings mapping NewV1 and NewV2 to the value that was + // indexed by OldVal. + // void UpdateNewToOldValueMap(Value *OldVal, Value *NewV1, Value *NewV2 = 0) { std::map::iterator I = FI.NewToOldValueMap.find(OldVal); @@ -132,10 +141,11 @@ }; } -void PoolAllocate::TransformBody(DSGraph* g, PA::FuncInfo &fi, - std::multimap &poolUses, - std::multimap &poolFrees, - Function &F) { +void +PoolAllocate::TransformBody (DSGraph* g, PA::FuncInfo &fi, + std::multimap &poolUses, + std::multimap &poolFrees, + Function &F) { FuncTransform(*this, g, fi, poolUses, poolFrees).visit(F); } From grosbach at apple.com Wed Jun 16 16:07:06 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 16 Jun 2010 21:07:06 -0000 Subject: [llvm-commits] [llvm] r106146 - /llvm/trunk/test/CodeGen/Generic/v-binop-widen.ll Message-ID: <20100616210706.E9B3C2A6C12C@llvm.org> Author: grosbach Date: Wed Jun 16 16:07:06 2010 New Revision: 106146 URL: http://llvm.org/viewvc/llvm-project?rev=106146&view=rev Log: modify so the test doesn't drop an output file in the test source directory. The test should also likely have some FileCheck bits to validate the output(?). Modified: llvm/trunk/test/CodeGen/Generic/v-binop-widen.ll Modified: llvm/trunk/test/CodeGen/Generic/v-binop-widen.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/v-binop-widen.ll?rev=106146&r1=106145&r2=106146&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Generic/v-binop-widen.ll (original) +++ llvm/trunk/test/CodeGen/Generic/v-binop-widen.ll Wed Jun 16 16:07:06 2010 @@ -1,4 +1,4 @@ -; RUN: llc -march=x86 %s +; RUN: llc -march=x86 < %s %vec = type <9 x float> define %vec @vecdiv( %vec %p1, %vec %p2) From grosbach at apple.com Wed Jun 16 16:09:42 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 16 Jun 2010 14:09:42 -0700 Subject: [llvm-commits] [llvm] r106038 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp test/CodeGen/Generic/v-binop-widen.ll test/CodeGen/Generic/v-binop-widen2.ll In-Reply-To: References: <20100615202905.4C9A42A6C12C@llvm.org> Message-ID: <86890B00-CE41-41F8-AC07-EF87AAA2CC41@apple.com> I changed the test to use "< %s" in r106146 so it'll stop polluting the test source directoy. I don't know what FileCheck entries should also be there, though. On Jun 16, 2010, at 10:56 AM, Daniel Dunbar wrote: > On Wed, Jun 16, 2010 at 9:36 AM, Jakob Stoklund Olesen wrote: >> >> On Jun 15, 2010, at 1:29 PM, Mon P Wang wrote: >> >>> Added: llvm/trunk/test/CodeGen/Generic/v-binop-widen.ll >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/v-binop-widen.ll?rev=106038&view=auto >>> ============================================================================== >>> --- llvm/trunk/test/CodeGen/Generic/v-binop-widen.ll (added) >>> +++ llvm/trunk/test/CodeGen/Generic/v-binop-widen.ll Tue Jun 15 15:29:05 2010 >>> @@ -0,0 +1,8 @@ >>> +; RUN: llc -march=x86 %s >> >> This writes an output file in the test directory. Please use '< %s' instead. > > Shouldn't it be checking something as well? > > - Daniel > >> >> Thanks, >> /jakob >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From grosbach at apple.com Wed Jun 16 16:13:38 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 16 Jun 2010 21:13:38 -0000 Subject: [llvm-commits] [llvm] r106149 - /llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp Message-ID: <20100616211338.C911B2A6C12C@llvm.org> Author: grosbach Date: Wed Jun 16 16:13:38 2010 New Revision: 106149 URL: http://llvm.org/viewvc/llvm-project?rev=106149&view=rev Log: A few more places where SCEVExpander bits need to skip over debug intrinsics when iterating through instructions. Yet more work for rdar://7797940 Modified: llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp Modified: llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp?rev=106149&r1=106148&r2=106149&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp Wed Jun 16 16:13:38 2010 @@ -97,7 +97,7 @@ BasicBlock::iterator It = I; ++It; if (isa(I)) It = cast(I)->getNormalDest()->begin(); - while (isa(It)) ++It; + while (isa(It) || isa(It)) ++It; if (It != BasicBlock::iterator(CI)) { // Recreate the cast after the user. // The old cast is left in place in case it is being used @@ -115,7 +115,7 @@ BasicBlock::iterator IP = I; ++IP; if (InvokeInst *II = dyn_cast(I)) IP = II->getNormalDest()->begin(); - while (isa(IP)) ++IP; + while (isa(IP) || isa(IP)) ++IP; Instruction *CI = CastInst::Create(Op, V, Ty, V->getName(), IP); rememberInstruction(CI); return CI; @@ -1070,7 +1070,8 @@ BasicBlock::iterator SaveInsertPt = Builder.GetInsertPoint(); BasicBlock::iterator NewInsertPt = llvm::next(BasicBlock::iterator(cast(V))); - while (isa(NewInsertPt)) ++NewInsertPt; + while (isa(NewInsertPt) || isa(NewInsertPt)) + ++NewInsertPt; V = expandCodeFor(SE.getTruncateExpr(SE.getUnknown(V), Ty), 0, NewInsertPt); restoreInsertPoint(SaveInsertBB, SaveInsertPt); From stoklund at 2pi.dk Wed Jun 16 16:16:50 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 16 Jun 2010 14:16:50 -0700 Subject: [llvm-commits] [llvm] r106038 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp test/CodeGen/Generic/v-binop-widen.ll test/CodeGen/Generic/v-binop-widen2.ll In-Reply-To: <86890B00-CE41-41F8-AC07-EF87AAA2CC41@apple.com> References: <20100615202905.4C9A42A6C12C@llvm.org> <86890B00-CE41-41F8-AC07-EF87AAA2CC41@apple.com> Message-ID: <8BB70DCD-CA07-4568-BCCD-0BCD6CE38F04@2pi.dk> On Jun 16, 2010, at 2:09 PM, Jim Grosbach wrote: > I changed the test to use "< %s" in r106146 so it'll stop polluting the test source directoy. I don't know what FileCheck entries should also be there, though. Many tests pass simply by not crashing llc. I am guessing that is the case here. If the test case can crash llc without needing fancy options, multiple tests can be collected in one file, see test/CodeGen/X86/crash.ll. From grosbach at apple.com Wed Jun 16 16:26:29 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 16 Jun 2010 14:26:29 -0700 Subject: [llvm-commits] [llvm] r106038 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp test/CodeGen/Generic/v-binop-widen.ll test/CodeGen/Generic/v-binop-widen2.ll In-Reply-To: <8BB70DCD-CA07-4568-BCCD-0BCD6CE38F04@2pi.dk> References: <20100615202905.4C9A42A6C12C@llvm.org> <86890B00-CE41-41F8-AC07-EF87AAA2CC41@apple.com> <8BB70DCD-CA07-4568-BCCD-0BCD6CE38F04@2pi.dk> Message-ID: <5E5F113A-3C82-4985-A5B4-ED0BF885B3BF@apple.com> On Jun 16, 2010, at 2:16 PM, Jakob Stoklund Olesen wrote: > > On Jun 16, 2010, at 2:09 PM, Jim Grosbach wrote: > >> I changed the test to use "< %s" in r106146 so it'll stop polluting the test source directoy. I don't know what FileCheck entries should also be there, though. > > Many tests pass simply by not crashing llc. I am guessing that is the case here. > > If the test case can crash llc without needing fancy options, multiple tests can be collected in one file, see test/CodeGen/X86/crash.ll. > That's a good point and entirely reasonable. If that's the case here, just adding a comment to that effect in the file or moving the test to crash.ll instead of in its own .ll file should clear up potential future confusion. From stoklund at 2pi.dk Wed Jun 16 16:29:40 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 16 Jun 2010 21:29:40 -0000 Subject: [llvm-commits] [llvm] r106152 - in /llvm/trunk: lib/CodeGen/LiveIntervalAnalysis.cpp test/CodeGen/Thumb2/crash.ll Message-ID: <20100616212940.617292A6C12C@llvm.org> Author: stoklund Date: Wed Jun 16 16:29:40 2010 New Revision: 106152 URL: http://llvm.org/viewvc/llvm-project?rev=106152&view=rev Log: Allow a register to be redefined multiple times in a basic block. LiveVariableAnalysis was a bit picky about a register only being redefined once, but that really isn't necessary. Here is an example of chained INSERT_SUBREGs that we can handle now: 68 %reg1040 = INSERT_SUBREG %reg1040, %reg1028, 14 register: %reg1040 +[70,134:0) 76 %reg1040 = INSERT_SUBREG %reg1040, %reg1029, 13 register: %reg1040 replace range with [70,78:1) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,134:0) 0 at 78-(134) 1 at 70-(78) 84 %reg1040 = INSERT_SUBREG %reg1040, %reg1030, 12 register: %reg1040 replace range with [78,86:2) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,86:2)[86,134:0) 0 at 86-(134) 1 at 70-(78) 2 at 78-(86) 92 %reg1040 = INSERT_SUBREG %reg1040, %reg1031, 11 register: %reg1040 replace range with [86,94:3) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,86:2)[86,94:3)[94,134:0) 0 at 94-(134) 1 at 70-(78) 2 at 78-(86) 3 at 86-(94) rdar://problem/8096390 Added: llvm/trunk/test/CodeGen/Thumb2/crash.ll Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=106152&r1=106151&r2=106152&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Wed Jun 16 16:29:40 2010 @@ -434,11 +434,6 @@ // are actually two values in the live interval. Because of this we // need to take the LiveRegion that defines this register and split it // into two values. - // Two-address vregs should always only be redefined once. This means - // that at this point, there should be exactly one value number in it. - assert((PartReDef || interval.containsOneValue()) && - "Unexpected 2-addr liveint!"); - SlotIndex DefIndex = interval.getValNumInfo(0)->def.getDefIndex(); SlotIndex RedefIndex = MIIdx.getDefIndex(); if (MO.isEarlyClobber()) RedefIndex = MIIdx.getUseIndex(); @@ -446,8 +441,9 @@ const LiveRange *OldLR = interval.getLiveRangeContaining(RedefIndex.getUseIndex()); VNInfo *OldValNo = OldLR->valno; + SlotIndex DefIndex = OldValNo->def.getDefIndex(); - // Delete the initial value, which should be short and continuous, + // Delete the previous value, which should be short and continuous, // because the 2-addr copy must be in the same MBB as the redef. interval.removeRange(DefIndex, RedefIndex); Added: llvm/trunk/test/CodeGen/Thumb2/crash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/crash.ll?rev=106152&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/crash.ll (added) +++ llvm/trunk/test/CodeGen/Thumb2/crash.ll Wed Jun 16 16:29:40 2010 @@ -0,0 +1,21 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32" +target triple = "thumbv7-apple-darwin10" + +; This function would crash LiveIntervalAnalysis by creating a chain of 4 INSERT_SUBREGs of the same register. +define arm_apcscc void @NEON_vst4q_u32(i32* nocapture %sp0, i32* nocapture %sp1, i32* nocapture %sp2, i32* nocapture %sp3, i32* %dp) nounwind { +entry: + %0 = bitcast i32* %sp0 to <4 x i32>* ; <<4 x i32>*> [#uses=1] + %1 = load <4 x i32>* %0, align 16 ; <<4 x i32>> [#uses=1] + %2 = bitcast i32* %sp1 to <4 x i32>* ; <<4 x i32>*> [#uses=1] + %3 = load <4 x i32>* %2, align 16 ; <<4 x i32>> [#uses=1] + %4 = bitcast i32* %sp2 to <4 x i32>* ; <<4 x i32>*> [#uses=1] + %5 = load <4 x i32>* %4, align 16 ; <<4 x i32>> [#uses=1] + %6 = bitcast i32* %sp3 to <4 x i32>* ; <<4 x i32>*> [#uses=1] + %7 = load <4 x i32>* %6, align 16 ; <<4 x i32>> [#uses=1] + %8 = bitcast i32* %dp to i8* ; [#uses=1] + tail call void @llvm.arm.neon.vst4.v4i32(i8* %8, <4 x i32> %1, <4 x i32> %3, <4 x i32> %5, <4 x i32> %7) + ret void +} + +declare void @llvm.arm.neon.vst4.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>) nounwind From echristo at apple.com Wed Jun 16 16:32:38 2010 From: echristo at apple.com (Eric Christopher) Date: Wed, 16 Jun 2010 21:32:38 -0000 Subject: [llvm-commits] [llvm] r106154 - /llvm/trunk/lib/MC/MachObjectWriter.cpp Message-ID: <20100616213238.E6C182A6C12C@llvm.org> Author: echristo Date: Wed Jun 16 16:32:38 2010 New Revision: 106154 URL: http://llvm.org/viewvc/llvm-project?rev=106154&view=rev Log: In progress on 32-bit addends. Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MachObjectWriter.cpp?rev=106154&r1=106153&r2=106154&view=diff ============================================================================== --- llvm/trunk/lib/MC/MachObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/MachObjectWriter.cpp Wed Jun 16 16:32:38 2010 @@ -756,8 +756,14 @@ MCSymbolData *SD_A = &Asm.getSymbolData(Target.getSymA()->getSymbol()); unsigned Index = SD_A->getIndex(); - if (Target.getSymB()) + // We're only going to have a second symbol in pic mode and it'll be a + // subtraction from the picbase. For 32-bit pic the addend is the difference + // between the picbase and the next address. + if (Target.getSymB()) { IsPCRel = 1; + } else { + FixedValue = 0; + } // struct relocation_info (8 bytes) MachRelocationEntry MRE; From bob.wilson at apple.com Wed Jun 16 16:34:01 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Wed, 16 Jun 2010 21:34:01 -0000 Subject: [llvm-commits] [llvm] r106155 - in /llvm/trunk/lib/Target/ARM: ARM.h ARMISelDAGToDAG.cpp ARMISelLowering.cpp NEONPreAllocPass.cpp Message-ID: <20100616213401.F1ACE2A6C12C@llvm.org> Author: bwilson Date: Wed Jun 16 16:34:01 2010 New Revision: 106155 URL: http://llvm.org/viewvc/llvm-project?rev=106155&view=rev Log: Remove the hidden "neon-reg-sequence" option. The reg sequences are working now, so there's no need to disable them. Modified: llvm/trunk/lib/Target/ARM/ARM.h llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp Modified: llvm/trunk/lib/Target/ARM/ARM.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.h?rev=106155&r1=106154&r2=106155&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARM.h (original) +++ llvm/trunk/lib/Target/ARM/ARM.h Wed Jun 16 16:34:01 2010 @@ -90,10 +90,6 @@ } } -/// ModelWithRegSequence - Return true if isel should use REG_SEQUENCE to model -/// operations involving sub-registers. -bool ModelWithRegSequence(); - FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM, CodeGenOpt::Level OptLevel); Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=106155&r1=106154&r2=106155&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Wed Jun 16 16:34:01 2010 @@ -36,11 +36,6 @@ using namespace llvm; -static cl::opt -UseRegSeq("neon-reg-sequence", cl::Hidden, - cl::desc("Use reg_sequence to model ld / st of multiple neon regs"), - cl::init(true)); - //===--------------------------------------------------------------------===// /// ARMDAGToDAGISel - ARM specific code to select ARM machine /// instructions for SelectionDAG operations. @@ -962,16 +957,8 @@ DebugLoc dl = V0.getNode()->getDebugLoc(); SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32); SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32); - if (llvm::ModelWithRegSequence()) { - const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 }; - return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4); - } - SDValue Undef = - SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0); - SDNode *Pair = CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, dl, - VT, Undef, V0, SubReg0); - return CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, dl, - VT, SDValue(Pair, 0), V1, SubReg1); + const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 }; + return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4); } /// PairDRegs - Form a quad register from a pair of D registers. @@ -980,16 +967,8 @@ DebugLoc dl = V0.getNode()->getDebugLoc(); SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32); SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32); - if (llvm::ModelWithRegSequence()) { - const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 }; - return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4); - } - SDValue Undef = - SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0); - SDNode *Pair = CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, dl, - VT, Undef, V0, SubReg0); - return CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, dl, - VT, SDValue(Pair, 0), V1, SubReg1); + const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 }; + return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4); } /// PairQRegs - Form 4 consecutive D registers from a pair of Q registers. @@ -1115,7 +1094,7 @@ std::vector ResTys(NumVecs, VT); ResTys.push_back(MVT::Other); SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 5); - if (!llvm::ModelWithRegSequence() || NumVecs < 2) + if (NumVecs < 2) return VLd; SDValue RegSeq; @@ -1156,24 +1135,17 @@ Chain = SDValue(VLd, 2 * NumVecs); // Combine the even and odd subregs to produce the result. - if (llvm::ModelWithRegSequence()) { - if (NumVecs == 1) { - SDNode *Q = PairDRegs(VT, SDValue(VLd, 0), SDValue(VLd, 1)); - ReplaceUses(SDValue(N, 0), SDValue(Q, 0)); - } else { - SDValue QQ = SDValue(QuadDRegs(MVT::v4i64, - SDValue(VLd, 0), SDValue(VLd, 1), - SDValue(VLd, 2), SDValue(VLd, 3)), 0); - SDValue Q0 = CurDAG->getTargetExtractSubreg(ARM::qsub_0, dl, VT, QQ); - SDValue Q1 = CurDAG->getTargetExtractSubreg(ARM::qsub_1, dl, VT, QQ); - ReplaceUses(SDValue(N, 0), Q0); - ReplaceUses(SDValue(N, 1), Q1); - } + if (NumVecs == 1) { + SDNode *Q = PairDRegs(VT, SDValue(VLd, 0), SDValue(VLd, 1)); + ReplaceUses(SDValue(N, 0), SDValue(Q, 0)); } else { - for (unsigned Vec = 0; Vec < NumVecs; ++Vec) { - SDNode *Q = PairDRegs(VT, SDValue(VLd, 2*Vec), SDValue(VLd, 2*Vec+1)); - ReplaceUses(SDValue(N, Vec), SDValue(Q, 0)); - } + SDValue QQ = SDValue(QuadDRegs(MVT::v4i64, + SDValue(VLd, 0), SDValue(VLd, 1), + SDValue(VLd, 2), SDValue(VLd, 3)), 0); + SDValue Q0 = CurDAG->getTargetExtractSubreg(ARM::qsub_0, dl, VT, QQ); + SDValue Q1 = CurDAG->getTargetExtractSubreg(ARM::qsub_1, dl, VT, QQ); + ReplaceUses(SDValue(N, 0), Q0); + ReplaceUses(SDValue(N, 1), Q1); } } else { // Otherwise, quad registers are loaded with two separate instructions, @@ -1196,37 +1168,27 @@ SDNode *VLdB = CurDAG->getMachineNode(Opc, dl, ResTys, OpsB, 6); Chain = SDValue(VLdB, NumVecs+1); - if (llvm::ModelWithRegSequence()) { - SDValue V0 = SDValue(VLdA, 0); - SDValue V1 = SDValue(VLdB, 0); - SDValue V2 = SDValue(VLdA, 1); - SDValue V3 = SDValue(VLdB, 1); - SDValue V4 = SDValue(VLdA, 2); - SDValue V5 = SDValue(VLdB, 2); - SDValue V6 = (NumVecs == 3) - ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,RegVT), - 0) - : SDValue(VLdA, 3); - SDValue V7 = (NumVecs == 3) - ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,RegVT), - 0) - : SDValue(VLdB, 3); - SDValue RegSeq = SDValue(OctoDRegs(MVT::v8i64, V0, V1, V2, V3, - V4, V5, V6, V7), 0); + SDValue V0 = SDValue(VLdA, 0); + SDValue V1 = SDValue(VLdB, 0); + SDValue V2 = SDValue(VLdA, 1); + SDValue V3 = SDValue(VLdB, 1); + SDValue V4 = SDValue(VLdA, 2); + SDValue V5 = SDValue(VLdB, 2); + SDValue V6 = (NumVecs == 3) + ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,RegVT), 0) + : SDValue(VLdA, 3); + SDValue V7 = (NumVecs == 3) + ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,RegVT), 0) + : SDValue(VLdB, 3); + SDValue RegSeq = SDValue(OctoDRegs(MVT::v8i64, V0, V1, V2, V3, + V4, V5, V6, V7), 0); - // Extract out the 3 / 4 Q registers. - assert(ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering"); - for (unsigned Vec = 0; Vec < NumVecs; ++Vec) { - SDValue Q = CurDAG->getTargetExtractSubreg(ARM::qsub_0+Vec, - dl, VT, RegSeq); - ReplaceUses(SDValue(N, Vec), Q); - } - } else { - // Combine the even and odd subregs to produce the result. - for (unsigned Vec = 0; Vec < NumVecs; ++Vec) { - SDNode *Q = PairDRegs(VT, SDValue(VLdA, Vec), SDValue(VLdB, Vec)); - ReplaceUses(SDValue(N, Vec), SDValue(Q, 0)); - } + // Extract out the 3 / 4 Q registers. + assert(ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering"); + for (unsigned Vec = 0; Vec < NumVecs; ++Vec) { + SDValue Q = CurDAG->getTargetExtractSubreg(ARM::qsub_0+Vec, + dl, VT, RegSeq); + ReplaceUses(SDValue(N, Vec), Q); } } ReplaceUses(SDValue(N, NumVecs), Chain); @@ -1274,7 +1236,7 @@ Ops.push_back(Align); if (is64BitVector) { - if (llvm::ModelWithRegSequence() && NumVecs >= 2) { + if (NumVecs >= 2) { SDValue RegSeq; SDValue V0 = N->getOperand(0+3); SDValue V1 = N->getOperand(1+3); @@ -1319,7 +1281,7 @@ // Quad registers are directly supported for VST1 and VST2, // storing pairs of D regs. unsigned Opc = QOpcodes0[OpcodeIndex]; - if (llvm::ModelWithRegSequence() && NumVecs == 2) { + if (NumVecs == 2) { // First extract the pair of Q registers. SDValue Q0 = N->getOperand(3); SDValue Q1 = N->getOperand(4); @@ -1357,76 +1319,48 @@ // Otherwise, quad registers are stored with two separate instructions, // where one stores the even registers and the other stores the odd registers. - if (llvm::ModelWithRegSequence()) { - // Form the QQQQ REG_SEQUENCE. - SDValue V[8]; - for (unsigned Vec = 0, i = 0; Vec < NumVecs; ++Vec, i+=2) { - V[i] = CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, RegVT, - N->getOperand(Vec+3)); - V[i+1] = CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, RegVT, - N->getOperand(Vec+3)); - } - if (NumVecs == 3) - V[6] = V[7] = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, - dl, RegVT), 0); - - SDValue RegSeq = SDValue(OctoDRegs(MVT::v8i64, V[0], V[1], V[2], V[3], - V[4], V[5], V[6], V[7]), 0); - - // Store the even D registers. - assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering"); - Ops.push_back(Reg0); // post-access address offset - for (unsigned Vec = 0; Vec < NumVecs; ++Vec) - Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0+Vec*2, dl, - RegVT, RegSeq)); - Ops.push_back(Pred); - Ops.push_back(Reg0); // predicate register - Ops.push_back(Chain); - unsigned Opc = QOpcodes0[OpcodeIndex]; - SDNode *VStA = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(), - MVT::Other, Ops.data(), NumVecs+6); - Chain = SDValue(VStA, 1); - - // Store the odd D registers. - Ops[0] = SDValue(VStA, 0); // MemAddr - for (unsigned Vec = 0; Vec < NumVecs; ++Vec) - Ops[Vec+3] = CurDAG->getTargetExtractSubreg(ARM::dsub_1+Vec*2, dl, - RegVT, RegSeq); - Ops[NumVecs+5] = Chain; - Opc = QOpcodes1[OpcodeIndex]; - SDNode *VStB = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(), - MVT::Other, Ops.data(), NumVecs+6); - Chain = SDValue(VStB, 1); - ReplaceUses(SDValue(N, 0), Chain); - return NULL; - } else { - Ops.push_back(Reg0); // post-access address offset - - // Store the even subregs. - for (unsigned Vec = 0; Vec < NumVecs; ++Vec) - Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, RegVT, - N->getOperand(Vec+3))); - Ops.push_back(Pred); - Ops.push_back(Reg0); // predicate register - Ops.push_back(Chain); - unsigned Opc = QOpcodes0[OpcodeIndex]; - SDNode *VStA = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(), - MVT::Other, Ops.data(), NumVecs+6); - Chain = SDValue(VStA, 1); - // Store the odd subregs. - Ops[0] = SDValue(VStA, 0); // MemAddr - for (unsigned Vec = 0; Vec < NumVecs; ++Vec) - Ops[Vec+3] = CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, RegVT, - N->getOperand(Vec+3)); - Ops[NumVecs+5] = Chain; - Opc = QOpcodes1[OpcodeIndex]; - SDNode *VStB = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(), - MVT::Other, Ops.data(), NumVecs+6); - Chain = SDValue(VStB, 1); - ReplaceUses(SDValue(N, 0), Chain); - return NULL; - } + // Form the QQQQ REG_SEQUENCE. + SDValue V[8]; + for (unsigned Vec = 0, i = 0; Vec < NumVecs; ++Vec, i+=2) { + V[i] = CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, RegVT, + N->getOperand(Vec+3)); + V[i+1] = CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, RegVT, + N->getOperand(Vec+3)); + } + if (NumVecs == 3) + V[6] = V[7] = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, + dl, RegVT), 0); + + SDValue RegSeq = SDValue(OctoDRegs(MVT::v8i64, V[0], V[1], V[2], V[3], + V[4], V[5], V[6], V[7]), 0); + + // Store the even D registers. + assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering"); + Ops.push_back(Reg0); // post-access address offset + for (unsigned Vec = 0; Vec < NumVecs; ++Vec) + Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0+Vec*2, dl, + RegVT, RegSeq)); + Ops.push_back(Pred); + Ops.push_back(Reg0); // predicate register + Ops.push_back(Chain); + unsigned Opc = QOpcodes0[OpcodeIndex]; + SDNode *VStA = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(), + MVT::Other, Ops.data(), NumVecs+6); + Chain = SDValue(VStA, 1); + + // Store the odd D registers. + Ops[0] = SDValue(VStA, 0); // MemAddr + for (unsigned Vec = 0; Vec < NumVecs; ++Vec) + Ops[Vec+3] = CurDAG->getTargetExtractSubreg(ARM::dsub_1+Vec*2, dl, + RegVT, RegSeq); + Ops[NumVecs+5] = Chain; + Opc = QOpcodes1[OpcodeIndex]; + SDNode *VStB = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(), + MVT::Other, Ops.data(), NumVecs+6); + Chain = SDValue(VStB, 1); + ReplaceUses(SDValue(N, 0), Chain); + return NULL; } SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad, @@ -1482,35 +1416,26 @@ unsigned Opc = 0; if (is64BitVector) { Opc = DOpcodes[OpcodeIndex]; - if (llvm::ModelWithRegSequence()) { - SDValue RegSeq; - SDValue V0 = N->getOperand(0+3); - SDValue V1 = N->getOperand(1+3); - if (NumVecs == 2) { - RegSeq = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0); - } else { - SDValue V2 = N->getOperand(2+3); - SDValue V3 = (NumVecs == 3) - ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0) - : N->getOperand(3+3); - RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0); - } - - // Now extract the D registers back out. - Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, VT, - RegSeq)); - Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, VT, - RegSeq)); - if (NumVecs > 2) - Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_2, dl, VT, - RegSeq)); - if (NumVecs > 3) - Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_3, dl, VT, - RegSeq)); + SDValue RegSeq; + SDValue V0 = N->getOperand(0+3); + SDValue V1 = N->getOperand(1+3); + if (NumVecs == 2) { + RegSeq = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0); } else { - for (unsigned Vec = 0; Vec < NumVecs; ++Vec) - Ops.push_back(N->getOperand(Vec+3)); + SDValue V2 = N->getOperand(2+3); + SDValue V3 = (NumVecs == 3) + ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0) + : N->getOperand(3+3); + RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0); } + + // Now extract the D registers back out. + Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, VT, RegSeq)); + Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, VT, RegSeq)); + if (NumVecs > 2) + Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_2, dl, VT,RegSeq)); + if (NumVecs > 3) + Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_3, dl, VT,RegSeq)); } else { // Check if this is loading the even or odd subreg of a Q register. if (Lane < NumElts) { @@ -1520,31 +1445,24 @@ Opc = QOpcodes1[OpcodeIndex]; } - if (llvm::ModelWithRegSequence()) { - SDValue RegSeq; - SDValue V0 = N->getOperand(0+3); - SDValue V1 = N->getOperand(1+3); - if (NumVecs == 2) { - RegSeq = SDValue(PairQRegs(MVT::v4i64, V0, V1), 0); - } else { - SDValue V2 = N->getOperand(2+3); - SDValue V3 = (NumVecs == 3) - ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0) - : N->getOperand(3+3); - RegSeq = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0); - } - - // Extract the subregs of the input vector. - unsigned SubIdx = Even ? ARM::dsub_0 : ARM::dsub_1; - for (unsigned Vec = 0; Vec < NumVecs; ++Vec) - Ops.push_back(CurDAG->getTargetExtractSubreg(SubIdx+Vec*2, dl, RegVT, - RegSeq)); + SDValue RegSeq; + SDValue V0 = N->getOperand(0+3); + SDValue V1 = N->getOperand(1+3); + if (NumVecs == 2) { + RegSeq = SDValue(PairQRegs(MVT::v4i64, V0, V1), 0); } else { - // Extract the subregs of the input vector. - for (unsigned Vec = 0; Vec < NumVecs; ++Vec) - Ops.push_back(CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT, - N->getOperand(Vec+3))); + SDValue V2 = N->getOperand(2+3); + SDValue V3 = (NumVecs == 3) + ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0) + : N->getOperand(3+3); + RegSeq = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0); } + + // Extract the subregs of the input vector. + unsigned SubIdx = Even ? ARM::dsub_0 : ARM::dsub_1; + for (unsigned Vec = 0; Vec < NumVecs; ++Vec) + Ops.push_back(CurDAG->getTargetExtractSubreg(SubIdx+Vec*2, dl, RegVT, + RegSeq)); } Ops.push_back(getI32Imm(Lane)); Ops.push_back(Pred); @@ -1558,73 +1476,54 @@ ResTys.push_back(MVT::Other); SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(),NumVecs+6); - if (llvm::ModelWithRegSequence()) { - // Form a REG_SEQUENCE to force register allocation. - SDValue RegSeq; - if (is64BitVector) { - SDValue V0 = SDValue(VLdLn, 0); - SDValue V1 = SDValue(VLdLn, 1); - if (NumVecs == 2) { - RegSeq = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0); - } else { - SDValue V2 = SDValue(VLdLn, 2); - // If it's a vld3, form a quad D-register but discard the last part. - SDValue V3 = (NumVecs == 3) - ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0) - : SDValue(VLdLn, 3); - RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0); - } + // Form a REG_SEQUENCE to force register allocation. + SDValue RegSeq; + if (is64BitVector) { + SDValue V0 = SDValue(VLdLn, 0); + SDValue V1 = SDValue(VLdLn, 1); + if (NumVecs == 2) { + RegSeq = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0); } else { - // For 128-bit vectors, take the 64-bit results of the load and insert - // them as subregs into the result. - SDValue V[8]; - for (unsigned Vec = 0, i = 0; Vec < NumVecs; ++Vec, i+=2) { - if (Even) { - V[i] = SDValue(VLdLn, Vec); - V[i+1] = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, - dl, RegVT), 0); - } else { - V[i] = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, - dl, RegVT), 0); - V[i+1] = SDValue(VLdLn, Vec); - } + SDValue V2 = SDValue(VLdLn, 2); + // If it's a vld3, form a quad D-register but discard the last part. + SDValue V3 = (NumVecs == 3) + ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0) + : SDValue(VLdLn, 3); + RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0); + } + } else { + // For 128-bit vectors, take the 64-bit results of the load and insert + // them as subregs into the result. + SDValue V[8]; + for (unsigned Vec = 0, i = 0; Vec < NumVecs; ++Vec, i+=2) { + if (Even) { + V[i] = SDValue(VLdLn, Vec); + V[i+1] = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, + dl, RegVT), 0); + } else { + V[i] = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, + dl, RegVT), 0); + V[i+1] = SDValue(VLdLn, Vec); } - if (NumVecs == 3) - V[6] = V[7] = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, - dl, RegVT), 0); - - if (NumVecs == 2) - RegSeq = SDValue(QuadDRegs(MVT::v4i64, V[0], V[1], V[2], V[3]), 0); - else - RegSeq = SDValue(OctoDRegs(MVT::v8i64, V[0], V[1], V[2], V[3], - V[4], V[5], V[6], V[7]), 0); } + if (NumVecs == 3) + V[6] = V[7] = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, + dl, RegVT), 0); - assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering"); - assert(ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering"); - unsigned SubIdx = is64BitVector ? ARM::dsub_0 : ARM::qsub_0; - for (unsigned Vec = 0; Vec < NumVecs; ++Vec) - ReplaceUses(SDValue(N, Vec), - CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, RegSeq)); - ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, NumVecs)); - return NULL; - } - - // For a 64-bit vector load to D registers, nothing more needs to be done. - if (is64BitVector) - return VLdLn; - - // For 128-bit vectors, take the 64-bit results of the load and insert them - // as subregs into the result. - for (unsigned Vec = 0; Vec < NumVecs; ++Vec) { - SDValue QuadVec = CurDAG->getTargetInsertSubreg(SubregIdx, dl, VT, - N->getOperand(Vec+3), - SDValue(VLdLn, Vec)); - ReplaceUses(SDValue(N, Vec), QuadVec); + if (NumVecs == 2) + RegSeq = SDValue(QuadDRegs(MVT::v4i64, V[0], V[1], V[2], V[3]), 0); + else + RegSeq = SDValue(OctoDRegs(MVT::v8i64, V[0], V[1], V[2], V[3], + V[4], V[5], V[6], V[7]), 0); } - Chain = SDValue(VLdLn, NumVecs); - ReplaceUses(SDValue(N, NumVecs), Chain); + assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering"); + assert(ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering"); + unsigned SubIdx = is64BitVector ? ARM::dsub_0 : ARM::qsub_0; + for (unsigned Vec = 0; Vec < NumVecs; ++Vec) + ReplaceUses(SDValue(N, Vec), + CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, RegSeq)); + ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, NumVecs)); return NULL; } @@ -2410,9 +2309,3 @@ CodeGenOpt::Level OptLevel) { return new ARMDAGToDAGISel(TM, OptLevel); } - -/// ModelWithRegSequence - Return true if isel should use REG_SEQUENCE to model -/// operations involving sub-registers. -bool llvm::ModelWithRegSequence() { - return UseRegSeq; -} Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=106155&r1=106154&r2=106155&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Jun 16 16:34:01 2010 @@ -109,10 +109,7 @@ } setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom); setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom); - if (llvm::ModelWithRegSequence()) - setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal); - else - setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Custom); + setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal); setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Expand); setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand); setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand); Modified: llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp?rev=106155&r1=106154&r2=106155&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp (original) +++ llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp Wed Jun 16 16:34:01 2010 @@ -467,8 +467,7 @@ unsigned FirstOpnd, NumRegs, Offset, Stride; if (!isNEONMultiRegOp(MI->getOpcode(), FirstOpnd, NumRegs, Offset, Stride)) continue; - if (llvm::ModelWithRegSequence() && - FormsRegSequence(MI, FirstOpnd, NumRegs, Offset, Stride)) + if (FormsRegSequence(MI, FirstOpnd, NumRegs, Offset, Stride)) continue; MachineBasicBlock::iterator NextI = llvm::next(MBBI); From daniel at zuster.org Wed Jun 16 16:34:57 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 16 Jun 2010 14:34:57 -0700 Subject: [llvm-commits] [llvm] r106038 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp test/CodeGen/Generic/v-binop-widen.ll test/CodeGen/Generic/v-binop-widen2.ll In-Reply-To: <20100615202905.4C9A42A6C12C@llvm.org> References: <20100615202905.4C9A42A6C12C@llvm.org> Message-ID: On Tue, Jun 15, 2010 at 1:29 PM, Mon P Wang wrote: > Author: wangmp > Date: Tue Jun 15 15:29:05 2010 > New Revision: 106038 > > URL: http://llvm.org/viewvc/llvm-project?rev=106038&view=rev > Log: > Fixed vector widening of binary instructions that can trap. Patch by Visa Putkinen! > > Added: > ? ?llvm/trunk/test/CodeGen/Generic/v-binop-widen.ll > ? ?llvm/trunk/test/CodeGen/Generic/v-binop-widen2.ll Also, this test appears to be still crashing on ARM: http://google1.osuosl.org:8011/builders/llvm-arm-linux/builds/3426/steps/test-llvm/logs/v-binop-widen2.ll Should it be moved to x86? - Daniel > Modified: > ? ?llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=106038&r1=106037&r2=106038&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Tue Jun 15 15:29:05 2010 > @@ -1271,7 +1271,7 @@ > ? EVT WidenEltVT = WidenVT.getVectorElementType(); > ? EVT VT = WidenVT; > ? unsigned NumElts = ?VT.getVectorNumElements(); > - ?while (!TLI.isTypeLegal(VT) && NumElts != 1) { > + ?while (!TLI.isTypeSynthesizable(VT) && NumElts != 1) { > ? ? ?NumElts = NumElts / 2; > ? ? ?VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts); > ? } > @@ -1286,13 +1286,20 @@ > ? ? return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements()); > ? } else { > ? ? // Since the operation can trap, apply operation on the original vector. > + ? ?EVT MaxVT = VT; > ? ? SDValue InOp1 = GetWidenedVector(N->getOperand(0)); > ? ? SDValue InOp2 = GetWidenedVector(N->getOperand(1)); > ? ? unsigned CurNumElts = N->getValueType(0).getVectorNumElements(); > > ? ? SmallVector ConcatOps(CurNumElts); > ? ? unsigned ConcatEnd = 0; ?// Current ConcatOps index. > - ? ?unsigned Idx = 0; ? ? ? ?// Current Idx into input vectors. > + ? ?int Idx = 0; ? ? ? ?// Current Idx into input vectors. > + > + ? ?// NumElts := greatest synthesizable vector size (at most WidenVT) > + ? ?// while (orig. vector has unhandled elements) { > + ? ?// ? take munches of size NumElts from the beginning and add to ConcatOps > + ? ?// ? NumElts := next smaller supported vector size or 1 > + ? ?// } > ? ? while (CurNumElts != 0) { > ? ? ? while (CurNumElts >= NumElts) { > ? ? ? ? SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1, > @@ -1303,26 +1310,21 @@ > ? ? ? ? Idx += NumElts; > ? ? ? ? CurNumElts -= NumElts; > ? ? ? } > - ? ? ?EVT PrevVecVT = VT; > ? ? ? do { > ? ? ? ? NumElts = NumElts / 2; > ? ? ? ? VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts); > - ? ? ?} while (!TLI.isTypeLegal(VT) && NumElts != 1); > + ? ? ?} while (!TLI.isTypeSynthesizable(VT) && NumElts != 1); > > ? ? ? if (NumElts == 1) { > - ? ? ? ?// Since we are using concat vector, build a vector from the scalar ops. > - ? ? ? ?SDValue VecOp = DAG.getUNDEF(PrevVecVT); > ? ? ? ? for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) { > ? ? ? ? ? SDValue EOp1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?InOp1, DAG.getIntPtrConstant(Idx)); > ? ? ? ? ? SDValue EOp2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?InOp2, DAG.getIntPtrConstant(Idx)); > - ? ? ? ? ?VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, PrevVecVT, VecOp, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DAG.getNode(Opcode, dl, WidenEltVT, EOp1, EOp2), > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DAG.getIntPtrConstant(i)); > + ? ? ? ? ?ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? EOp1, EOp2); > ? ? ? ? } > ? ? ? ? CurNumElts = 0; > - ? ? ? ?ConcatOps[ConcatEnd++] = VecOp; > ? ? ? } > ? ? } > > @@ -1333,23 +1335,65 @@ > ? ? ? ? return ConcatOps[0]; > ? ? } > > - ? ?// Rebuild vector to one with the widen type > - ? ?Idx = ConcatEnd - 1; > - ? ?while (Idx != 0) { > + ? ?// while (Some element of ConcatOps is not of type MaxVT) { > + ? ?// ? From the end of ConcatOps, collect elements of the same type and put > + ? ?// ? them into an op of the next larger supported type > + ? ?// } > + ? ?while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) { > + ? ? ?Idx = ConcatEnd - 1; > ? ? ? VT = ConcatOps[Idx--].getValueType(); > - ? ? ?while (Idx != 0 && ConcatOps[Idx].getValueType() == VT) > - ? ? ? ?--Idx; > - ? ? ?if (Idx != 0) { > - ? ? ? ?VT = ConcatOps[Idx].getValueType(); > - ? ? ? ?ConcatOps[Idx+1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? &ConcatOps[Idx+1], ConcatEnd - Idx - 1); > + ? ? ?while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT) > + ? ? ? ?Idx--; > + > + ? ? ?int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1; > + ? ? ?EVT NextVT; > + ? ? ?do { > + ? ? ? ?NextSize *= 2; > + ? ? ? ?NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize); > + ? ? ?} while (!TLI.isTypeSynthesizable(NextVT)); > + > + ? ? ?if (!VT.isVector()) { > + ? ? ? ?// Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT > + ? ? ? ?SDValue VecOp = DAG.getUNDEF(NextVT); > + ? ? ? ?unsigned NumToInsert = ConcatEnd - Idx - 1; > + ? ? ? ?for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) { > + ? ? ? ? ?VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?ConcatOps[OpIdx], DAG.getIntPtrConstant(i)); > + ? ? ? ?} > + ? ? ? ?ConcatOps[Idx+1] = VecOp; > ? ? ? ? ConcatEnd = Idx + 2; > + ? ? ?} > + ? ? ?else { > + ? ? ? ?// Vector type, create a CONCAT_VECTORS of type NextVT > + ? ? ? ?SDValue undefVec = DAG.getUNDEF(VT); > + ? ? ? ?unsigned OpsToConcat = NextSize/VT.getVectorNumElements(); > + ? ? ? ?SmallVector SubConcatOps(OpsToConcat); > + ? ? ? ?unsigned RealVals = ConcatEnd - Idx - 1; > + ? ? ? ?unsigned SubConcatEnd = 0; > + ? ? ? ?unsigned SubConcatIdx = Idx + 1; > + ? ? ? ?while (SubConcatEnd < RealVals) > + ? ? ? ? ?SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx]; > + ? ? ? ?while (SubConcatEnd < OpsToConcat) > + ? ? ? ? ?SubConcatOps[SubConcatEnd++] = undefVec; > + ? ? ? ?ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?NextVT, &SubConcatOps[0], > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?OpsToConcat); > + ? ? ? ?ConcatEnd = SubConcatIdx + 1; > ? ? ? } > ? ? } > + > + ? ?// Check to see if we have a single operation with the widen type. > + ? ?if (ConcatEnd == 1) { > + ? ? ?VT = ConcatOps[0].getValueType(); > + ? ? ?if (VT == WidenVT) > + ? ? ? ?return ConcatOps[0]; > + ? ?} > > - ? ?unsigned NumOps = WidenVT.getVectorNumElements()/VT.getVectorNumElements(); > + ? ?// add undefs of size MaxVT until ConcatOps grows to length of WidenVT > + ? ?unsigned NumOps = > + ? ? ? ?WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements(); > ? ? if (NumOps != ConcatEnd ) { > - ? ? ?SDValue UndefVal = DAG.getUNDEF(VT); > + ? ? ?SDValue UndefVal = DAG.getUNDEF(MaxVT); > ? ? ? for (unsigned j = ConcatEnd; j < NumOps; ++j) > ? ? ? ? ConcatOps[j] = UndefVal; > ? ? } > @@ -1379,7 +1423,7 @@ > ? ? ? return DAG.getNode(Opcode, dl, WidenVT, InOp); > ? } > > - ?if (TLI.isTypeLegal(InWidenVT)) { > + ?if (TLI.isTypeSynthesizable(InWidenVT)) { > ? ? // Because the result and the input are different vector types, widening > ? ? // the result could create a legal type but widening the input might make > ? ? // it an illegal type that might lead to repeatedly splitting the input > @@ -1521,7 +1565,7 @@ > ? ? ? NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts); > ? ? } > > - ? ?if (TLI.isTypeLegal(NewInVT)) { > + ? ?if (TLI.isTypeSynthesizable(NewInVT)) { > ? ? ? // Because the result and the input are different vector types, widening > ? ? ? // the result could create a legal type but widening the input might make > ? ? ? // it an illegal type that might lead to repeatedly splitting the input > @@ -1662,7 +1706,7 @@ > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SatOp, CvtCode); > ? } > > - ?if (TLI.isTypeLegal(InWidenVT)) { > + ?if (TLI.isTypeSynthesizable(InWidenVT)) { > ? ? // Because the result and the input are different vector types, widening > ? ? // the result could create a legal type but widening the input might make > ? ? // it an illegal type that might lead to repeatedly splitting the input > @@ -1988,7 +2032,7 @@ > ? if (InWidenSize % Size == 0 && !VT.isVector()) { > ? ? unsigned NewNumElts = InWidenSize / Size; > ? ? EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts); > - ? ?if (TLI.isTypeLegal(NewVT)) { > + ? ?if (TLI.isTypeSynthesizable(NewVT)) { > ? ? ? SDValue BitOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, InOp); > ? ? ? return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp, > ? ? ? ? ? ? ? ? ? ? ? ? ?DAG.getIntPtrConstant(0)); > @@ -2086,7 +2130,7 @@ > ? ? unsigned MemVTWidth = MemVT.getSizeInBits(); > ? ? if (MemVT.getSizeInBits() <= WidenEltWidth) > ? ? ? break; > - ? ?if (TLI.isTypeLegal(MemVT) && (WidenWidth % MemVTWidth) == 0 && > + ? ?if (TLI.isTypeSynthesizable(MemVT) && (WidenWidth % MemVTWidth) == 0 && > ? ? ? ? (MemVTWidth <= Width || > ? ? ? ? ?(Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) { > ? ? ? RetVT = MemVT; > @@ -2100,7 +2144,7 @@ > ? ? ? ?VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) { > ? ? EVT MemVT = (MVT::SimpleValueType) VT; > ? ? unsigned MemVTWidth = MemVT.getSizeInBits(); > - ? ?if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() && > + ? ?if (TLI.isTypeSynthesizable(MemVT) && WidenEltVT == MemVT.getVectorElementType() && > ? ? ? ? (WidenWidth % MemVTWidth) == 0 && > ? ? ? ? (MemVTWidth <= Width || > ? ? ? ? ?(Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) { > > Added: llvm/trunk/test/CodeGen/Generic/v-binop-widen.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/v-binop-widen.ll?rev=106038&view=auto > ============================================================================== > --- llvm/trunk/test/CodeGen/Generic/v-binop-widen.ll (added) > +++ llvm/trunk/test/CodeGen/Generic/v-binop-widen.ll Tue Jun 15 15:29:05 2010 > @@ -0,0 +1,8 @@ > +; RUN: llc -march=x86 %s > + > +%vec = type <9 x float> > +define %vec @vecdiv( %vec %p1, %vec %p2) > +{ > + ?%result = fdiv %vec %p1, %p2 > + ?ret %vec %result > +} > > Added: llvm/trunk/test/CodeGen/Generic/v-binop-widen2.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/v-binop-widen2.ll?rev=106038&view=auto > ============================================================================== > --- llvm/trunk/test/CodeGen/Generic/v-binop-widen2.ll (added) > +++ llvm/trunk/test/CodeGen/Generic/v-binop-widen2.ll Tue Jun 15 15:29:05 2010 > @@ -0,0 +1,37 @@ > +; RUN: llvm-as < %s | lli > + > +%vec = type <6 x float> > + > +define %vec @vecdiv( %vec %p1, %vec %p2) > +{ > + ?%result = fdiv %vec %p1, %p2 > + ?ret %vec %result > +} > + > + at a = constant %vec < float 2.0, float 4.0, float 8.0, float 16.0, float 32.0, float 64.0 > > + at b = constant %vec < float 2.0, float 2.0, float 2.0, float 2.0, float 2.0, float 2.0 > > + > +; Expected result: < 1.0, 2.0, 4.0, ..., 2.0^(n-1) > > +; main() returns 0 if the result is expected and 1 otherwise > +define i32 @main() nounwind { > +entry: > + ?%avec = load %vec* @a > + ?%bvec = load %vec* @b > + > + ?%res = call %vec @vecdiv(%vec %avec, %vec %bvec) > + ?br label %loop > +loop: > + ?%idx = phi i32 [0, %entry], [%nextInd, %looptail] > + ?%expected = phi float [1.0, %entry], [%nextExpected, %looptail] > + ?%elem = extractelement %vec %res, i32 %idx > + ?%expcmp = fcmp oeq float %elem, %expected > + ?br i1 %expcmp, label %looptail, label %return > +looptail: > + ?%nextExpected = fmul float %expected, 2.0 > + ?%nextInd = add i32 %idx, 1 > + ?%cmp = icmp slt i32 %nextInd, 6 > + ?br i1 %cmp, label %loop, label %return > +return: > + ?%retval = phi i32 [0, %looptail], [1, %loop] > + ?ret i32 %retval > +} > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From criswell at uiuc.edu Wed Jun 16 17:04:21 2010 From: criswell at uiuc.edu (John Criswell) Date: Wed, 16 Jun 2010 22:04:21 -0000 Subject: [llvm-commits] [poolalloc] r106156 - in /poolalloc/trunk/test: Makefile TEST.FL2.Makefile TEST.FL2.report Message-ID: <20100616220421.2BDF12A6C12C@llvm.org> Author: criswell Date: Wed Jun 16 17:04:21 2010 New Revision: 106156 URL: http://llvm.org/viewvc/llvm-project?rev=106156&view=rev Log: Added the progalloc test to test the FL2 allocator. Added: poolalloc/trunk/test/TEST.FL2.Makefile poolalloc/trunk/test/TEST.FL2.report Modified: poolalloc/trunk/test/Makefile Modified: poolalloc/trunk/test/Makefile URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/Makefile?rev=106156&r1=106155&r2=106156&view=diff ============================================================================== --- poolalloc/trunk/test/Makefile (original) +++ poolalloc/trunk/test/Makefile Wed Jun 16 17:04:21 2010 @@ -37,12 +37,12 @@ NORMAL_PROBLEM_SIZE_DIRS := \ - External/SPEC/CINT2000/175.vpr \ + MultiSource/Benchmarks/Olden/bh \ + #MultiSource/Benchmarks/Olden \ + #External/SPEC/CINT2000/175.vpr \ #External/SPEC/CINT2000 \ #External/SPEC/CINT2000/181.mcf \ #External/SPEC/CINT2000/186.crafty \ - #MultiSource/Benchmarks/Olden \ - #MultiSource/Benchmarks/Olden/bh \ #External/FPGrowth \ #External/Namd \ #External/Povray \ @@ -110,6 +110,30 @@ done @printf "\a"; sleep 1; printf "\a"; sleep 1; printf "\a" +# Program tests for the allocator +progalloc:: + for dir in $(LARGE_PROBLEM_SIZE_DIRS); do \ + (cd $$dir; \ + PROJECT_DIR=$(PROJ_OBJ_ROOT) $(MAKE) -j1 TEST=FL2 \ + LARGE_PROBLEM_SIZE=1 report.html) \ + done + for dir in $(NORMAL_PROBLEM_SIZE_DIRS); do \ + (cd $$dir; \ + PROJECT_DIR=$(PROJ_OBJ_ROOT) $(MAKE) -j1 TEST=FL2 \ + report.html) \ + done + @for dir in $(LARGE_PROBLEM_SIZE_DIRS); do \ + (cd $$dir; \ + PROJECT_DIR=$(PROJ_OBJ_ROOT) $(MAKE) -s -j1 TEST=FL2 \ + LARGE_PROBLEM_SIZE=1 report) \ + done + @for dir in $(NORMAL_PROBLEM_SIZE_DIRS); do \ + (cd $$dir; \ + PROJECT_DIR=$(PROJ_OBJ_ROOT) $(MAKE) -s -j1 TEST=FL2 \ + report) \ + done + @printf "\a"; sleep 1; printf "\a"; sleep 1; printf "\a" + # Program tests for Pool Allocation progtest:: for dir in $(LARGE_PROBLEM_SIZE_DIRS); do \ Added: poolalloc/trunk/test/TEST.FL2.Makefile URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/TEST.FL2.Makefile?rev=106156&view=auto ============================================================================== --- poolalloc/trunk/test/TEST.FL2.Makefile (added) +++ poolalloc/trunk/test/TEST.FL2.Makefile Wed Jun 16 17:04:21 2010 @@ -0,0 +1,171 @@ +##===- poolalloc/test/TEST.FL2.Makefile --------------------*- Makefile -*-===## +# +# This test uses simple pool allocation to test the FL2 allocator. +# +##===----------------------------------------------------------------------===## + +CFLAGS = -O2 -fno-strict-aliasing + +EXTRA_PA_FLAGS := + +# HEURISTIC can be set to: +# AllNodes +ifdef HEURISTIC +EXTRA_PA_FLAGS += -poolalloc-heuristic=$(HEURISTIC) +endif + +CURDIR := $(shell cd .; pwd) +PROGDIR := $(shell cd $(LLVM_SRC_ROOT)/projects/test-suite; pwd)/ +RELDIR := $(subst $(PROGDIR),,$(CURDIR)) +PADIR := $(LLVM_OBJ_ROOT)/projects/poolalloc + +# Watchdog utility +WATCHDOG := $(LLVM_OBJ_ROOT)/projects/poolalloc/$(CONFIGURATION)/bin/watchdog + +# Bits of runtime to improve analysis +PA_PRE_RT := $(PADIR)/$(CONFIGURATION)/lib/libpa_pre_rt.bca + +# Pool allocator pass shared object +PA_SO := $(PADIR)/$(CONFIGURATION)/lib/libpoolalloc$(SHLIBEXT) +DSA_SO := $(PADIR)/$(CONFIGURATION)/lib/libLLVMDataStructure$(SHLIBEXT) +ASSIST_SO := $(PADIR)/$(CONFIGURATION)/lib/libAssistDS$(SHLIBEXT) + +# Pool allocator runtime library +#PA_RT := $(PADIR)/$(CONFIGURATION)/lib/libpoolalloc_fl_rt.bc +#PA_RT_O := $(PROJECT_DIR)/lib/$(CONFIGURATION)/poolalloc_rt.o +PA_RT_O := $(PADIR)/$(CONFIGURATION)/lib/libpoolalloc_rt.a +#PA_RT_O := $(PROJECT_DIR)/lib/$(CONFIGURATION)/poolalloc_fl_rt.o + +# Command to run opt with the pool allocator pass loaded +OPT_PA := $(WATCHDOG) $(LOPT) -load $(DSA_SO) -load $(PA_SO) + +# OPT_PA_STATS - Run opt with the -stats and -time-passes options, capturing the +# output to a file. +OPT_PA_STATS = $(OPT_PA) -info-output-file=$(CURDIR)/$@.info -stats -time-passes + +OPTZN_PASSES := -globaldce -ipsccp -deadargelim -adce -instcombine -simplifycfg + + +$(PROGRAMS_TO_TEST:%=Output/%.temp.bc): \ +Output/%.temp.bc: Output/%.llvm.bc + -$(LLVMLD) -link-as-library $< $(PA_PRE_RT) -o $@ + +$(PROGRAMS_TO_TEST:%=Output/%.base.bc): \ +Output/%.base.bc: Output/%.temp.bc $(LOPT) $(ASSIST_SO) + -$(LOPT) -load $(ASSIST_SO) -instnamer -internalize -indclone -funcspec -ipsccp -deadargelim -instcombine -globaldce -stats $< -f -o $@ + +# This rule runs the pool allocator on the .base.bc file to produce a new .bc +# file +$(PROGRAMS_TO_TEST:%=Output/%.poolalloc.bc): \ +Output/%.poolalloc.bc: Output/%.base.bc $(PA_SO) $(LOPT) + - at rm -f $(CURDIR)/$@.info + -$(OPT_PA_STATS) -poolalloc-simple $(EXTRA_PA_FLAGS) $(OPTZN_PASSES) $< -o $@ -f 2>&1 > $@.out + +$(PROGRAMS_TO_TEST:%=Output/%.nonpa.bc): \ +Output/%.nonpa.bc: Output/%.base.bc $(LOPT) + - at rm -f $(CURDIR)/$@.info + -$(LOPT) $(OPTZN_PASSES) $< -o $@ -f 2>&1 > $@.out + +# This rule compiles the new .bc file into a .s file +$(PROGRAMS_TO_TEST:%=Output/%.poolalloc.s): \ +Output/%.poolalloc.s: Output/%.poolalloc.bc $(LLC) + -$(LLC) -f $< -o $@ + +$(PROGRAMS_TO_TEST:%=Output/%.nonpa.s): \ +Output/%.nonpa.s: Output/%.nonpa.bc $(LLC) + -$(LLC) -f $< -o $@ + +# Compile the .s file into an executable +$(PROGRAMS_TO_TEST:%=Output/%.poolalloc): \ +Output/%.poolalloc: Output/%.poolalloc.s $(PA_RT_O) + -$(CC) $(CFLAGS) $< $(PA_RT_O) $(LLCLIBS) $(LDFLAGS) -o $@ + +$(PROGRAMS_TO_TEST:%=Output/%.nonpa): \ +Output/%.nonpa: Output/%.nonpa.s $(PA_RT_O) + -$(CC) $(CFLAGS) $< $(PA_RT_O) $(LLCLIBS) $(LDFLAGS) -o $@ + + +ifndef PROGRAMS_HAVE_CUSTOM_RUN_RULES + +# This rule runs the generated executable, generating timing information, for +# normal test programs +$(PROGRAMS_TO_TEST:%=Output/%.poolalloc.out): \ +Output/%.poolalloc.out: Output/%.poolalloc + -$(RUNSAFELY) $(STDIN_FILENAME) $@ $< $(RUN_OPTIONS) + +$(PROGRAMS_TO_TEST:%=Output/%.nonpa.out): \ +Output/%.nonpa.out: Output/%.nonpa + -$(RUNSAFELY) $(STDIN_FILENAME) $@ $< $(RUN_OPTIONS) +else + +# This rule runs the generated executable, generating timing information, for +# SPEC +$(PROGRAMS_TO_TEST:%=Output/%.poolalloc.out): \ +Output/%.poolalloc.out: Output/%.poolalloc + -$(SPEC_SANDBOX) poolalloc-$(RUN_TYPE) $@ $(REF_IN_DIR) \ + $(RUNSAFELY) $(STDIN_FILENAME) $(STDOUT_FILENAME) \ + ../../$< $(RUN_OPTIONS) + -(cd Output/poolalloc-$(RUN_TYPE); cat $(LOCAL_OUTPUTS)) > $@ + -cp Output/poolalloc-$(RUN_TYPE)/$(STDOUT_FILENAME).time $@.time + +$(PROGRAMS_TO_TEST:%=Output/%.nonpa.out): \ +Output/%.nonpa.out: Output/%.nonpa + -$(SPEC_SANDBOX) nonpa-$(RUN_TYPE) $@ $(REF_IN_DIR) \ + $(RUNSAFELY) $(STDIN_FILENAME) $(STDOUT_FILENAME) \ + ../../$< $(RUN_OPTIONS) + -(cd Output/nonpa-$(RUN_TYPE); cat $(LOCAL_OUTPUTS)) > $@ + -cp Output/nonpa-$(RUN_TYPE)/$(STDOUT_FILENAME).time $@.time + +endif + + +# This rule diffs the post-poolallocated version to make sure we didn't break +# the program! +$(PROGRAMS_TO_TEST:%=Output/%.poolalloc.diff-nat): \ +Output/%.poolalloc.diff-nat: Output/%.out-nat Output/%.poolalloc.out + @cp Output/$*.out-nat Output/$*.poolalloc.out-nat + -$(DIFFPROG) nat $*.poolalloc $(HIDEDIFF) + +$(PROGRAMS_TO_TEST:%=Output/%.nonpa.diff-nat): \ +Output/%.nonpa.diff-nat: Output/%.out-nat Output/%.nonpa.out + @cp Output/$*.out-nat Output/$*.nonpa.out-nat + -$(DIFFPROG) nat $*.nonpa $(HIDEDIFF) + + +# This rule wraps everything together to build the actual output the report is +# generated from. +$(PROGRAMS_TO_TEST:%=Output/%.$(TEST).report.txt): \ +Output/%.$(TEST).report.txt: Output/%.out-nat \ + Output/%.nonpa.diff-nat \ + Output/%.poolalloc.diff-nat \ + Output/%.LOC.txt + @-cat $< + @echo > $@ + @echo "---------------------------------------------------------------" >> $@ + @echo ">>> ========= '$(RELDIR)/$*' Program" >> $@ + @echo "---------------------------------------------------------------" >> $@ + @echo >> $@ + @-if test -f Output/$*.nonpa.diff-nat; then \ + printf "GCC-RUN-TIME: " >> $@;\ + grep "^program" Output/$*.out-nat.time >> $@;\ + fi + @-if test -f Output/$*.nonpa.diff-nat; then \ + printf "RUN-TIME-NORMAL: " >> $@;\ + grep "^program" Output/$*.nonpa.out.time >> $@;\ + fi + @-if test -f Output/$*.poolalloc.diff-nat; then \ + printf "RUN-TIME-POOLALLOC: " >> $@;\ + grep "^program" Output/$*.poolalloc.out.time >> $@;\ + fi + -printf "LOC: " >> $@ + -cat Output/$*.LOC.txt >> $@ + @-cat Output/$*.$(TEST).bc.info >> $@ + +$(PROGRAMS_TO_TEST:%=test.$(TEST).%): \ +test.$(TEST).%: Output/%.$(TEST).report.txt + @echo "---------------------------------------------------------------" + @echo ">>> ========= '$(RELDIR)/$*' Program" + @echo "---------------------------------------------------------------" + @-cat $< + +REPORT_DEPENDENCIES := $(PA_RT_O) $(PA_SO) $(PROGRAMS_TO_TEST:%=Output/%.llvm.bc) $(LLC) $(LOPT) Added: poolalloc/trunk/test/TEST.FL2.report URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/TEST.FL2.report?rev=106156&view=auto ============================================================================== --- poolalloc/trunk/test/TEST.FL2.report (added) +++ poolalloc/trunk/test/TEST.FL2.report Wed Jun 16 17:04:21 2010 @@ -0,0 +1,89 @@ +##=== TEST.poolalloc.report - Report description for poolalloc -*- perl -*-===## +# +# This file defines a report to be generated for the pool allocator tests. +# +##===----------------------------------------------------------------------===## + +# Sort by program name +$SortCol = 0; +$TrimRepeatedPrefix = 1; + +# FormatTime - Convert a time from 1m23.45 into 83.45 +sub FormatTime { + my $Time = shift; + if ($Time =~ m/([0-9]+)[m:]([0-9.]+)/) { + return sprintf("%7.3f", $1*60.0+$2); + } + + return sprintf("%6.2f", $Time); +} + + +sub RuntimePercent { + my ($Cols, $Col) = @_; + if ($Cols->[$Col-1] ne "*" and $Cols->[4] ne "*" and + $Cols->[4] != "0") { + return sprintf "%7.2f", 100*$Cols->[$Col-1]/$Cols->[4]; + } else { + return "n/a"; + } +} + + at LatexColumns = (1, 5, 8, 12, 9, 13, 14, 15, 2, 16); + +my $FREEBENCH = 'MultiSource/Benchmarks/FreeBench'; +my $PTRDIST = 'MultiSource/Benchmarks/Ptrdist'; + + at LatexRowMapOrder = ( + '164.gzip/164.gzip' => '164.gzip', + '175.vpr/175.vpr' => '175.vpr', + '181.mcf/181.mcf' => '181.mcf', + '186.crafty/186.crafty' => '186.crafty', + '197.parser/197.parser' => '197.parser', + '197.parser.hacked/197.parser.hacked' => '197.parser(b)', + '255.vortex/255.vortex' => '255.vortex', + '256.bzip2/256.bzip2' => '256.bzip2', + '300.twolf/300.twolf' => '300.twolf', + '-' => '-', + "anagram/anagram" => 'anagram', + "bc/bc" => 'bc', + "ft/ft" => 'ft', + "ks/ks" => 'ks', + "yacr2/yacr2" => 'yacr2', + '-' => '-', + "analyzer" => 'analyzer', + "neural" => 'neural', + "pcompress2" => 'pcompress2', + "piff2" => 'piff2', + '-' => '-', + "bh/bh" => 'bh', + "bisort/bisort" => 'bisort', + "em3d/em3d" => 'em3d', + "health/health" => 'health', + "mst/mst" => 'mst', + "perimeter/perimeter" => 'perimeter', + "power/power" => 'power', + "treeadd/treeadd" => 'treeadd', + "tsp/tsp" => 'tsp', + '-' => '-', + "llu" => 'llu-bench', + ); + + +# These are the columns for the report. The first entry is the header for the +# column, the second is the regex to use to match the value. Empty list create +# seperators, and closures may be put in for custom processing. +( +# Name + ["Name:" , '\'([^\']+)\' Program'], + ["LOC" , 'LOC:\s*([0-9]+)'], + [], +# Times + ["GCC", 'GCC-RUN-TIME: program\s*([.0-9m:]+)', \&FormatTime], + ["NonPATime", 'RUN-TIME-NORMAL: program\s*([.0-9m:]+)', \&FormatTime], + [], + ["FL2 Time", 'RUN-TIME-POOLALLOC: program\s*([.0-9m:]+)', \&FormatTime], + ["FL2 run%", \&RuntimePercent], + [] +); + From bob.wilson at apple.com Wed Jun 16 17:07:41 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Wed, 16 Jun 2010 15:07:41 -0700 Subject: [llvm-commits] [patch] Remove arm_aapcscc from some tests In-Reply-To: References: <250924C5-EF3C-4CB0-BD7C-7F42F9B1D27D@apple.com> <9601F397-5FAC-469F-A704-EF38972AE22E@apple.com> <7BDDBF70-72CC-4A74-A676-568E4D35E8B9@apple.com> Message-ID: <9CD57DB2-205F-42CA-852A-46AE3A8CF804@apple.com> On Jun 16, 2010, at 7:27 AM, Rafael Espindola wrote: >> I'm OK with it as long as the default ABI for non-Linux targets is APCS. I took a quick look at it seems like that is true; AAPCS is only the default if the triple includes "eabi". Otherwise, you're potentially changing the behavior of a lot of tests. Even if those tests are not directly related to testing the ABI, there may be differences that affect what the tests do. > > So, it looks like APCS is the default (I have no opinion if that is > correct or not). Is this patch ok or should I update it to also pass a > darwin triple to llc? It's OK. If I were you, I'd just leave these tests as they are, but I can't see any problem with changing them. From stoklund at 2pi.dk Wed Jun 16 17:11:08 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 16 Jun 2010 22:11:08 -0000 Subject: [llvm-commits] [llvm] r106157 - /llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp Message-ID: <20100616221108.658402A6C12C@llvm.org> Author: stoklund Date: Wed Jun 16 17:11:08 2010 New Revision: 106157 URL: http://llvm.org/viewvc/llvm-project?rev=106157&view=rev Log: Don't attempt preserving conservative kill flags. We were doing it wrong. This is before LiveVariables anyway, where these kill flags are recalculated. Modified: llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp Modified: llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp?rev=106157&r1=106156&r2=106157&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp (original) +++ llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp Wed Jun 16 17:11:08 2010 @@ -448,8 +448,7 @@ assert(DefMI->isExtractSubreg()); MO.setReg(LastSrcReg); MO.setSubReg(SubIds[R]); - if (R != 0) - MO.setIsKill(false); + MO.setIsKill(false); // Delete the EXTRACT_SUBREG if its result is now dead. if (MRI->use_empty(OldReg)) DefMI->eraseFromParent(); From dgregor at apple.com Wed Jun 16 17:32:18 2010 From: dgregor at apple.com (Douglas Gregor) Date: Wed, 16 Jun 2010 22:32:18 -0000 Subject: [llvm-commits] [llvm] r106162 - /llvm/trunk/include/llvm/Analysis/IntervalIterator.h Message-ID: <20100616223218.299DF2A6C12C@llvm.org> Author: dgregor Date: Wed Jun 16 17:32:18 2010 New Revision: 106162 URL: http://llvm.org/viewvc/llvm-project?rev=106162&view=rev Log: Revert r106117, which was the result of me misreading the C++98/03 specification. Modified: llvm/trunk/include/llvm/Analysis/IntervalIterator.h Modified: llvm/trunk/include/llvm/Analysis/IntervalIterator.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/IntervalIterator.h?rev=106162&r1=106161&r2=106162&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/IntervalIterator.h (original) +++ llvm/trunk/include/llvm/Analysis/IntervalIterator.h Wed Jun 16 17:32:18 2010 @@ -88,7 +88,7 @@ template, class IGT = GraphTraits > > class IntervalIterator { - std::stack > IntStack; + std::stack > IntStack; std::set Visited; OrigContainer_t *OrigContainer; bool IOwnMem; // If True, delete intervals when done with them From grosbach at apple.com Wed Jun 16 17:41:09 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 16 Jun 2010 22:41:09 -0000 Subject: [llvm-commits] [llvm] r106164 - /llvm/trunk/lib/Transforms/Utils/DemoteRegToStack.cpp Message-ID: <20100616224109.395502A6C12C@llvm.org> Author: grosbach Date: Wed Jun 16 17:41:09 2010 New Revision: 106164 URL: http://llvm.org/viewvc/llvm-project?rev=106164&view=rev Log: remove trailing whitespace Modified: llvm/trunk/lib/Transforms/Utils/DemoteRegToStack.cpp Modified: llvm/trunk/lib/Transforms/Utils/DemoteRegToStack.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/DemoteRegToStack.cpp?rev=106164&r1=106163&r2=106164&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/DemoteRegToStack.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/DemoteRegToStack.cpp Wed Jun 16 17:41:09 2010 @@ -35,7 +35,7 @@ I.eraseFromParent(); return 0; } - + // Create a stack slot to hold the value. AllocaInst *Slot; if (AllocaPoint) { @@ -46,7 +46,7 @@ Slot = new AllocaInst(I.getType(), 0, I.getName()+".reg2mem", F->getEntryBlock().begin()); } - + // Change all of the users of the instruction to read from the stack slot // instead. while (!I.use_empty()) { @@ -67,7 +67,7 @@ Value *&V = Loads[PN->getIncomingBlock(i)]; if (V == 0) { // Insert the load into the predecessor block - V = new LoadInst(Slot, I.getName()+".reload", VolatileLoads, + V = new LoadInst(Slot, I.getName()+".reload", VolatileLoads, PN->getIncomingBlock(i)->getTerminator()); } PN->setIncomingValue(i, V); @@ -110,8 +110,8 @@ /// The phi node is deleted and it returns the pointer to the alloca inserted. AllocaInst* llvm::DemotePHIToStack(PHINode *P, Instruction *AllocaPoint) { if (P->use_empty()) { - P->eraseFromParent(); - return 0; + P->eraseFromParent(); + return 0; } // Create a stack slot to hold the value. @@ -124,23 +124,23 @@ Slot = new AllocaInst(P->getType(), 0, P->getName()+".reg2mem", F->getEntryBlock().begin()); } - + // Iterate over each operand, insert store in each predecessor. for (unsigned i = 0, e = P->getNumIncomingValues(); i < e; ++i) { if (InvokeInst *II = dyn_cast(P->getIncomingValue(i))) { - assert(II->getParent() != P->getIncomingBlock(i) && + assert(II->getParent() != P->getIncomingBlock(i) && "Invoke edge not supported yet"); II=II; } - new StoreInst(P->getIncomingValue(i), Slot, + new StoreInst(P->getIncomingValue(i), Slot, P->getIncomingBlock(i)->getTerminator()); } - + // Insert load in place of the phi and replace all uses. Value *V = new LoadInst(Slot, P->getName()+".reload", P); P->replaceAllUsesWith(V); - + // Delete phi. P->eraseFromParent(); - + return Slot; } From daniel at zuster.org Wed Jun 16 18:06:17 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 16 Jun 2010 23:06:17 -0000 Subject: [llvm-commits] [zorg] r106168 - in /zorg/trunk/lnt/lnt: util/ImportData.py viewer/Config.py Message-ID: <20100616230617.23D6C2A6C12C@llvm.org> Author: ddunbar Date: Wed Jun 16 18:06:16 2010 New Revision: 106168 URL: http://llvm.org/viewvc/llvm-project?rev=106168&view=rev Log: LNT: Factor out an EmailConfig object. Modified: zorg/trunk/lnt/lnt/util/ImportData.py zorg/trunk/lnt/lnt/viewer/Config.py Modified: zorg/trunk/lnt/lnt/util/ImportData.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/util/ImportData.py?rev=106168&r1=106167&r2=106168&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/util/ImportData.py (original) +++ zorg/trunk/lnt/lnt/util/ImportData.py Wed Jun 16 18:06:16 2010 @@ -37,26 +37,17 @@ return (False, None) print >>log, ' LOAD TIME: %.2fs' % (time.time() - startTime,) - # Check if this is a nightlytest run. - tag = data.get('Run',{}).get('Info',{}).get('tag',None) - is_nt = tag is None or tag == 'nightlytest' - # Find the email address for this machine's results. toAddress = None - if is_nt and config.ntEmailEnabled: - if isinstance(config.ntEmailTo, str): - toAddress = config.ntEmailTo - else: - # Find the machine name. - machineName = str(data.get('Machine',{}).get('Name')) - for pattern,addr in config.ntEmailTo: - if re.match(pattern, machineName): - toAddress = addr - break - else: - print >>log,("ERROR: unable to match machine name " - "for test results email address!") - return (False, None) + email_config = config.databases[db_name].email_config + if email_config.enabled: + # Find the machine name. + machineName = str(data.get('Machine',{}).get('Name')) + toAddress = email_config.get_to_address(machineName) + if toAddress is None: + print >>log,("ERROR: unable to match machine name " + "for test results email address!") + return (False, None) importStartTime = time.time() try: @@ -83,7 +74,7 @@ NTEmailReport.emailReport(db, run, "%s/db_%s/nightlytest/" % (config.zorgURL, db_name), - config.ntEmailHost, config.ntEmailFrom, + email_config.host, email_config.from_address, toAddress, success, commit) print >>log, "ADDED: %d machines" % (db.getNumMachines() - numMachines,) Modified: zorg/trunk/lnt/lnt/viewer/Config.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/viewer/Config.py?rev=106168&r1=106167&r2=106168&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/viewer/Config.py (original) +++ zorg/trunk/lnt/lnt/viewer/Config.py Wed Jun 16 18:06:16 2010 @@ -3,23 +3,44 @@ """ import os +import re + +class EmailConfig: + def __init__(self, enabled, host, from_address, to_address): + self.enabled = enabled + self.host = host + self.from_address = from_address + self.to_address = to_address + + def get_to_address(self, machine_name): + # The email to_address field can either be a string, or a list of tuples + # of the form [(accept-regexp-pattern, to-address)]. + if isinstance(self.to_address, str): + return self.to_address + + for pattern,addr in self.to_address: + if re.match(pattern, machine_name): + return addr class DBInfo: @staticmethod - def fromData(baseDir, dict): + def fromData(baseDir, dict, default_email_config): dbPath = dict.get('path') if '://' not in dbPath: dbPath = os.path.join(baseDir, dbPath) return DBInfo(dbPath, bool(dict.get('showNightlytest')), bool(dict.get('showGeneral')), - bool(dict.get('showSimple'))) + bool(dict.get('showSimple')), + default_email_config) - def __init__(self, path, showNightlytest, showGeneral, showSimple): + def __init__(self, path, showNightlytest, showGeneral, showSimple, + email_config): self.path = path self.showGeneral = showGeneral self.showNightlytest = showNightlytest self.showSimple = showSimple + self.email_config = email_config class Config: @staticmethod @@ -28,23 +49,20 @@ # config file. baseDir = os.path.dirname(os.path.abspath(path)) - ntEmailer = data.get('nt_emailer') - if ntEmailer: - ntEmailEnabled = bool(ntEmailer.get('enabled')) - ntEmailHost = str(ntEmailer.get('host')) - ntEmailFrom = str(ntEmailer.get('from')) - + # Get the default email config. + emailer = data.get('nt_emailer') + if emailer: # The email to field can either be a string, or a list of tuples of # the form [(accept-regexp-pattern, to-address)]. - item = ntEmailer.get('to') - if isinstance(item, str): - ntEmailTo = item - else: - ntEmailTo = [(str(a),str(b)) - for a,b in item] + to_address = emailer.get('to') + if not isinstance(to_address, str): + to_address = [(str(a),str(b)) for a,b in to_address] + default_email_config = EmailConfig(bool(emailer.get('enabled')), + str(emailer.get('host')), + str(emailer.get('from')), + to_address) else: - ntEmailEnabled = False - ntEmailHost = ntEmailFrom = ntEmailTo = "" + default_email_config = EmailConfig(False, '', '', []) dbDir = data.get('db_dir', '.') dbDirPath = os.path.join(baseDir, dbDir) @@ -54,12 +72,11 @@ return Config(data.get('name', 'LNT'), data['zorgURL'], dbDir, os.path.join(baseDir, tempDir), - dict([(k,DBInfo.fromData(dbDirPath, v)) - for k,v in data['databases'].items()]), - ntEmailEnabled, ntEmailHost, ntEmailFrom, ntEmailTo) + dict([(k,DBInfo.fromData(dbDirPath, v, + default_email_config)) + for k,v in data['databases'].items()])) - def __init__(self, name, zorgURL, dbDir, tempDir, databases, - ntEmailEnabled, ntEmailHost, ntEmailFrom, ntEmailTo): + def __init__(self, name, zorgURL, dbDir, tempDir, databases): self.name = name self.zorgURL = zorgURL self.dbDir = dbDir @@ -67,7 +84,3 @@ while self.zorgURL.endswith('/'): self.zorgURL = zorgURL[:-1] self.databases = databases - self.ntEmailEnabled = ntEmailEnabled - self.ntEmailHost = ntEmailHost - self.ntEmailFrom = ntEmailFrom - self.ntEmailTo = ntEmailTo From daniel at zuster.org Wed Jun 16 18:06:20 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 16 Jun 2010 23:06:20 -0000 Subject: [llvm-commits] [zorg] r106169 - in /zorg/trunk/lnt/lnt: util/NTEmailReport.py viewer/Config.py Message-ID: <20100616230620.4216C2A6C12D@llvm.org> Author: ddunbar Date: Wed Jun 16 18:06:20 2010 New Revision: 106169 URL: http://llvm.org/viewvc/llvm-project?rev=106169&view=rev Log: LNT: Support per-database emailer configs, and tidy up LNT/simple reports. Modified: zorg/trunk/lnt/lnt/util/NTEmailReport.py zorg/trunk/lnt/lnt/viewer/Config.py Modified: zorg/trunk/lnt/lnt/util/NTEmailReport.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/util/NTEmailReport.py?rev=106169&r1=106168&r2=106169&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/util/NTEmailReport.py (original) +++ zorg/trunk/lnt/lnt/util/NTEmailReport.py Wed Jun 16 18:06:20 2010 @@ -90,6 +90,9 @@ id = run_summary.get_previous_run_on_machine(run.id) if id is not None: compare_to = db.getRun(id) + else: + # FIXME: Look for run across machine. + compare_to = None # Gather the changes to report, mapped by parameter set. new_failures = Util.multidict() @@ -147,7 +150,7 @@ print >>report, """(%s:%d)""" % (compare_to.machine.name, compare_to.machine.number) else: - print >>report, """ To: (none)""" + print >>report, """ To: (none)""" print >>report if existing_failures: @@ -213,9 +216,6 @@ for name,cr in tests: print >>report, ' %s' % (name,) - print 'Subject:',subject - print report.getvalue() - raise SystemExit,0 return subject, report.getvalue() def getReport(db, run, baseurl, was_added, will_commit): Modified: zorg/trunk/lnt/lnt/viewer/Config.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/viewer/Config.py?rev=106169&r1=106168&r2=106169&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/viewer/Config.py (original) +++ zorg/trunk/lnt/lnt/viewer/Config.py Wed Jun 16 18:06:20 2010 @@ -6,6 +6,16 @@ import re class EmailConfig: + @staticmethod + def fromData(data): + # The email to field can either be a string, or a list of tuples of + # the form [(accept-regexp-pattern, to-address)]. + to_address = data.get('to') + if not isinstance(to_address, str): + to_address = [(str(a),str(b)) for a,b in to_address] + return EmailConfig(bool(data.get('enabled')), str(data.get('host')), + str(data.get('from')), to_address) + def __init__(self, enabled, host, from_address, to_address): self.enabled = enabled self.host = host @@ -28,11 +38,17 @@ dbPath = dict.get('path') if '://' not in dbPath: dbPath = os.path.join(baseDir, dbPath) + + # Support per-database email configurations. + email_config = default_email_config + if 'emailer' in dict: + email_config = EmailConfig.fromData(dict['emailer']) + return DBInfo(dbPath, bool(dict.get('showNightlytest')), bool(dict.get('showGeneral')), bool(dict.get('showSimple')), - default_email_config) + email_config) def __init__(self, path, showNightlytest, showGeneral, showSimple, email_config): @@ -52,15 +68,7 @@ # Get the default email config. emailer = data.get('nt_emailer') if emailer: - # The email to field can either be a string, or a list of tuples of - # the form [(accept-regexp-pattern, to-address)]. - to_address = emailer.get('to') - if not isinstance(to_address, str): - to_address = [(str(a),str(b)) for a,b in to_address] - default_email_config = EmailConfig(bool(emailer.get('enabled')), - str(emailer.get('host')), - str(emailer.get('from')), - to_address) + default_email_config = EmailConfig.fromData(emailer) else: default_email_config = EmailConfig(False, '', '', []) From bruno.cardoso at gmail.com Wed Jun 16 18:24:12 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Wed, 16 Jun 2010 23:24:12 -0000 Subject: [llvm-commits] [llvm] r106171 - in /llvm/trunk: docs/TableGenFundamentals.html test/TableGen/eqbit.td utils/TableGen/Record.cpp Message-ID: <20100616232412.98FE32A6C12C@llvm.org> Author: bruno Date: Wed Jun 16 18:24:12 2010 New Revision: 106171 URL: http://llvm.org/viewvc/llvm-project?rev=106171&view=rev Log: let the '!eq' expression support 'int' and 'bit' types Added: llvm/trunk/test/TableGen/eqbit.td Modified: llvm/trunk/docs/TableGenFundamentals.html llvm/trunk/utils/TableGen/Record.cpp Modified: llvm/trunk/docs/TableGenFundamentals.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/TableGenFundamentals.html?rev=106171&r1=106170&r2=106171&view=diff ============================================================================== --- llvm/trunk/docs/TableGenFundamentals.html (original) +++ llvm/trunk/docs/TableGenFundamentals.html Wed Jun 16 18:24:12 2010 @@ -425,8 +425,8 @@
'b' if the result of integer operator 'a' is nonzero, 'c' otherwise.
!eq(a,b)
Integer one if string a is equal to string b, zero otherwise. This - only operates on string objects. Use !cast to compare other - types of objects.
+ only operates on string, int and bit objects. Use !cast to + compare other types of objects.

Note that all of the values have rules specifying how they convert to values Added: llvm/trunk/test/TableGen/eqbit.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/TableGen/eqbit.td?rev=106171&view=auto ============================================================================== --- llvm/trunk/test/TableGen/eqbit.td (added) +++ llvm/trunk/test/TableGen/eqbit.td Wed Jun 16 18:24:12 2010 @@ -0,0 +1,11 @@ +// RUN: tblgen %s | FileCheck %s +// XFAIL: vg_leak +// CHECK: a = 6 +// CHECK: a = 5 + +class A { + int a = !if(!eq(b, 1), 5, 6); +} + +def X : A<0>; +def Y : A; Modified: llvm/trunk/utils/TableGen/Record.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/Record.cpp?rev=106171&r1=106170&r2=106171&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/Record.cpp (original) +++ llvm/trunk/utils/TableGen/Record.cpp Wed Jun 16 18:24:12 2010 @@ -721,9 +721,20 @@ break; } case EQ: { - // Make sure we've resolved + // try to fold eq comparison for 'bit' and 'int', otherwise fallback + // to string objects. + IntInit* L = + dynamic_cast(LHS->convertInitializerTo(new IntRecTy())); + IntInit* R = + dynamic_cast(RHS->convertInitializerTo(new IntRecTy())); + + if (L && R) + return new IntInit(L->getValue() == R->getValue()); + StringInit *LHSs = dynamic_cast(LHS); StringInit *RHSs = dynamic_cast(RHS); + + // Make sure we've resolved if (LHSs && RHSs) return new IntInit(LHSs->getValue() == RHSs->getValue()); From grosbach at apple.com Wed Jun 16 18:45:49 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 16 Jun 2010 23:45:49 -0000 Subject: [llvm-commits] [llvm] r106173 - /llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Message-ID: <20100616234549.939C42A6C12C@llvm.org> Author: grosbach Date: Wed Jun 16 18:45:49 2010 New Revision: 106173 URL: http://llvm.org/viewvc/llvm-project?rev=106173&view=rev Log: format and 80-column cleanup Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=106173&r1=106172&r2=106173&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Jun 16 18:45:49 2010 @@ -1358,8 +1358,8 @@ //?? if (RegInfo->needsStackRealignment(MF)) //?? return false; - // Do not sibcall optimize vararg calls unless the call site is not passing any - // arguments. + // Do not sibcall optimize vararg calls unless the call site is not passing + // any arguments. if (isVarArg && !Outs.empty()) return false; @@ -1814,8 +1814,7 @@ SDValue ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, - const ARMSubtarget *Subtarget) - const { + const ARMSubtarget *Subtarget) const { unsigned IntNo = cast(Op.getOperand(0))->getZExtValue(); DebugLoc dl = Op.getDebugLoc(); switch (IntNo) { @@ -1855,7 +1854,7 @@ } static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG, - const ARMSubtarget *Subtarget) { + const ARMSubtarget *Subtarget) { DebugLoc dl = Op.getDebugLoc(); SDValue Op5 = Op.getOperand(5); SDValue Res; From rideau3 at gmail.com Wed Jun 16 18:45:50 2010 From: rideau3 at gmail.com (Sean Hunt) Date: Wed, 16 Jun 2010 23:45:50 -0000 Subject: [llvm-commits] [llvm] r106174 - in /llvm/trunk/utils/TableGen: ClangAttrEmitter.cpp ClangAttrEmitter.h TableGen.cpp Message-ID: <20100616234550.61C052A6C12D@llvm.org> Author: coppro Date: Wed Jun 16 18:45:50 2010 New Revision: 106174 URL: http://llvm.org/viewvc/llvm-project?rev=106174&view=rev Log: Add preliminary clang attribute generation support. The attribute class generation support is still somewhat limited. See the accompanying clang commit for more details. Added: llvm/trunk/utils/TableGen/ClangAttrEmitter.cpp llvm/trunk/utils/TableGen/ClangAttrEmitter.h Modified: llvm/trunk/utils/TableGen/TableGen.cpp Added: llvm/trunk/utils/TableGen/ClangAttrEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/ClangAttrEmitter.cpp?rev=106174&view=auto ============================================================================== --- llvm/trunk/utils/TableGen/ClangAttrEmitter.cpp (added) +++ llvm/trunk/utils/TableGen/ClangAttrEmitter.cpp Wed Jun 16 18:45:50 2010 @@ -0,0 +1,85 @@ +//===- ClangAttrEmitter.cpp - Generate Clang attribute handling =-*- C++ -*--=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// These tablegen backends emit Clang attribute processing code +// +//===----------------------------------------------------------------------===// + +#include "ClangAttrEmitter.h" +#include "Record.h" +#include + +using namespace llvm; + +void ClangAttrClassEmitter::run(raw_ostream &OS) { + OS << "// This file is generated by TableGen. Do not edit.\n\n"; + OS << "#ifndef LLVM_CLANG_ATTR_CLASSES_INC\n"; + OS << "#define LLVM_CLANG_ATTR_CLASSES_INC\n\n"; + + std::vector Attrs = Records.getAllDerivedDefinitions("Attr"); + + for (std::vector::iterator i = Attrs.begin(), e = Attrs.end(); + i != e; ++i) { + Record &R = **i; + + if (R.getValueAsBit("DoNotEmit")) + continue; + + OS << "class " << R.getName() << "Attr : public Attr {\n"; + + std::vector Args = R.getValueAsListOfDefs("Args"); + std::vector::iterator ai, ae = Args.end(); + + // FIXME: Handle arguments + assert(Args.empty() && "Can't yet handle arguments"); + + OS << "\n public:\n"; + OS << " " << R.getName() << "Attr("; + + // Arguments go here + + OS << ")\n"; + OS << " : Attr(attr::" << R.getName() << ")"; + + // Arguments go here + + OS << " {}\n\n"; + + OS << " virtual Attr *clone (ASTContext &C) const;\n"; + OS << " static bool classof(const Attr *A) { return A->getKind() == " + << "attr::" << R.getName() << "; }\n"; + OS << " static bool classof(const " << R.getName() + << "Attr *) { return true; }\n"; + OS << "};\n\n"; + } + + OS << "#endif\n"; +} + +void ClangAttrListEmitter::run(raw_ostream &OS) { + OS << "// This file is generated by TableGen. Do not edit.\n\n"; + + OS << "#ifndef LAST_ATTR\n"; + OS << "#define LAST_ATTR(NAME) ATTR(NAME)\n"; + OS << "#endif\n\n"; + + std::vector Attrs = Records.getAllDerivedDefinitions("Attr"); + std::vector::iterator i = Attrs.begin(), e = Attrs.end(); + + if (i != e) { + // Move the end iterator back to emit the last attribute. + for(--e; i != e; ++i) + OS << "ATTR(" << (*i)->getName() << ")\n"; + + OS << "LAST_ATTR(" << (*i)->getName() << ")\n\n"; + } + + OS << "#undef LAST_ATTR\n"; + OS << "#undef ATTR\n"; +} Added: llvm/trunk/utils/TableGen/ClangAttrEmitter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/ClangAttrEmitter.h?rev=106174&view=auto ============================================================================== --- llvm/trunk/utils/TableGen/ClangAttrEmitter.h (added) +++ llvm/trunk/utils/TableGen/ClangAttrEmitter.h Wed Jun 16 18:45:50 2010 @@ -0,0 +1,49 @@ +//===- ClangAttrEmitter.h - Generate Clang attribute handling =-*- C++ -*--===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// These tablegen backends emit Clang attribute processing code +// +//===----------------------------------------------------------------------===// + +#ifndef CLANGATTR_EMITTER_H +#define CLANGATTR_EMITTER_H + +#include "TableGenBackend.h" + +namespace llvm { + +/// ClangAttrClassEmitter - class emits the class defintions for attributes for +/// clang. +class ClangAttrClassEmitter : public TableGenBackend { + RecordKeeper &Records; + + public: + explicit ClangAttrClassEmitter(RecordKeeper &R) + : Records(R) + {} + + void run(raw_ostream &OS); +}; + +/// ClangAttrListEmitter - class emits the enumeration list for attributes for +/// clang. +class ClangAttrListEmitter : public TableGenBackend { + RecordKeeper &Records; + + public: + explicit ClangAttrListEmitter(RecordKeeper &R) + : Records(R) + {} + + void run(raw_ostream &OS); +}; + +} + +#endif Modified: llvm/trunk/utils/TableGen/TableGen.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TableGen.cpp?rev=106174&r1=106173&r2=106174&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/TableGen.cpp (original) +++ llvm/trunk/utils/TableGen/TableGen.cpp Wed Jun 16 18:45:50 2010 @@ -19,6 +19,7 @@ #include "AsmWriterEmitter.h" #include "CallingConvEmitter.h" #include "ClangASTNodesEmitter.h" +#include "ClangAttrEmitter.h" #include "ClangDiagnosticsEmitter.h" #include "CodeEmitterGen.h" #include "DAGISelEmitter.h" @@ -53,6 +54,8 @@ GenARMDecoder, GenDisassembler, GenCallingConv, + GenClangAttrClasses, + GenClangAttrList, GenClangDiagsDefs, GenClangDiagGroups, GenClangDeclNodes, @@ -111,6 +114,10 @@ "Generate intrinsic information"), clEnumValN(GenTgtIntrinsic, "gen-tgt-intrinsic", "Generate target intrinsic information"), + clEnumValN(GenClangAttrClasses, "gen-clang-attr-classes", + "Generate clang attribute clases"), + clEnumValN(GenClangAttrList, "gen-clang-attr-list", + "Generate a clang attribute list"), clEnumValN(GenClangDiagsDefs, "gen-clang-diags-defs", "Generate Clang diagnostics definitions"), clEnumValN(GenClangDiagGroups, "gen-clang-diag-groups", @@ -248,6 +255,12 @@ case GenAsmMatcher: AsmMatcherEmitter(Records).run(Out); break; + case GenClangAttrClasses: + ClangAttrClassEmitter(Records).run(Out); + break; + case GenClangAttrList: + ClangAttrListEmitter(Records).run(Out); + break; case GenClangDiagsDefs: ClangDiagsDefsEmitter(Records, ClangComponent).run(Out); break; From wdietz2 at illinois.edu Wed Jun 16 18:48:42 2010 From: wdietz2 at illinois.edu (Will Dietz) Date: Wed, 16 Jun 2010 23:48:42 -0000 Subject: [llvm-commits] [poolalloc] r106176 - /poolalloc/trunk/test/Makefile Message-ID: <20100616234842.D65212A6C12C@llvm.org> Author: wdietz2 Date: Wed Jun 16 18:48:42 2010 New Revision: 106176 URL: http://llvm.org/viewvc/llvm-project?rev=106176&view=rev Log: poolalloc: added support for running dejagnu tests Modified: poolalloc/trunk/test/Makefile Modified: poolalloc/trunk/test/Makefile URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/Makefile?rev=106176&r1=106175&r2=106176&view=diff ============================================================================== --- poolalloc/trunk/test/Makefile (original) +++ poolalloc/trunk/test/Makefile Wed Jun 16 18:48:42 2010 @@ -7,6 +7,8 @@ # The default target in this directory is the test:: target test:: +#Eventually we'll want to automatically run the dejagnu tests too +#test:: unit LEVEL = .. include $(LEVEL)/Makefile.common @@ -318,3 +320,80 @@ report report.csv) @printf "\a"; sleep 1; printf "\a"; sleep 1; printf "\a" +##===----------------------------------------------------------------------===## +# Unit tests +##===----------------------------------------------------------------------===## + +#DISCLAIMER +#I would prefer being able to do something like above, by setting +#some "PROJECT_DIR" variable, but alas I don't see that for the dejagnu +#test framework. So for now we hijack the existing framework as much as +#possible--feel free to replace this if you know a cleaner way. + +.PHONY: check_runtest unit + +#Path to dejagnu's runtest binary. +RUNTEST=runtest + +#Figure out what our configuration is +#Better way? +ifeq ($(ENABLE_OPTIMIZED),1) +CONFIGURATION := "Release" +else +CONFIGURATION := "Debug" +endif + +# Pathname to poolalloc object tree +PADIR := $(LLVM_OBJ_ROOT)/projects/poolalloc +# Pathame to the DSA pass dynamic library +DSA_SO := $(PADIR)/$(CONFIGURATION)/lib/libLLVMDataStructure$(SHLIBEXT) + +DSAOPT := $(PROJ_OBJ_ROOT)/test/tools/dsaopt + +TOOLS= $(DSAOPT) + +#Check that our RUNTEST variable points to a runtest we can use +check_runtest: + @which runtest; \ + if [ $$? -ne 0 ]; then \ + echo \"$(RUNTEST)\" is not valid. Please put runtest on your PATH; \ + echo or set the RUNTEST variable correctly.; \ + exit 1; \ + fi + +#Grab site.exp per normal llvm testing, but modify it to run in this project +site.exp: + @echo "Generating site.exp..." + @make -C $(LLVM_OBJ_ROOT)/test site.exp + @cp $(LLVM_OBJ_ROOT)/test/site.exp site.tmp + @echo "set srcdir $(PROJ_SRC_DIR)" >> site.tmp + @echo "set srcroot $(PROJ_SRC_DIR)" >> site.tmp + @echo "set objdir $(PROJ_OBJ_DIR)" >> site.tmp + @echo "set objroot $(PROJ_OBJ_DIR)" >> site.tmp + @cp site.tmp $@ + +#wrapper script for 'opt' so we can avoid manually loading the dsa lib +$(DSAOPT): + @mkdir -p `dirname $@` + @echo "#!/bin/sh" >> $@.tmp + @echo 'opt -load $(DSA_SO) $$@' >> $@.tmp + @chmod +x $@.tmp + @mv $@.tmp $@ + +#We need this locally, might be able to avoid this by modifying site.exp +llvm.exp: + cp $(LLVM_SRC_ROOT)/test/lib/llvm.exp $@ + +#Build up the runtest command by making sure useful tools are on its path +RUNTEST_CMD = \ + PATH=$(LLVMToolDir):$(LLVM_SRC_ROOT)/test/Scripts:$(LLVMGCCDIR)/bin:$(PATH):$(PROJ_OBJ_ROOT)/test/tools \ + $(RUNTEST) + +#Run the dejagnu tests for this project +unit: check_runtest site.exp llvm.exp $(TOOLS) + $(RUNTEST_CMD) + +clean:: + -$(RM) -rf `find $(PROJ_OBJ_DIR) -name Output -type d -print` + -$(RM) $(PROJ_OBJ_ROOT)/test/site.exp $(PROJ_OBJ_ROOT)/test/llvm.exp + -$(RM) -rf tools From wdietz2 at illinois.edu Wed Jun 16 18:49:36 2010 From: wdietz2 at illinois.edu (Will Dietz) Date: Wed, 16 Jun 2010 23:49:36 -0000 Subject: [llvm-commits] [poolalloc] r106177 - in /poolalloc/trunk/test/var_arg: ./ basic.c dg.exp multiple_callee.c Message-ID: <20100616234936.135AC2A6C12C@llvm.org> Author: wdietz2 Date: Wed Jun 16 18:49:35 2010 New Revision: 106177 URL: http://llvm.org/viewvc/llvm-project?rev=106177&view=rev Log: poolalloc: added basic var_arg tests Added: poolalloc/trunk/test/var_arg/ poolalloc/trunk/test/var_arg/basic.c poolalloc/trunk/test/var_arg/dg.exp poolalloc/trunk/test/var_arg/multiple_callee.c Added: poolalloc/trunk/test/var_arg/basic.c URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/var_arg/basic.c?rev=106177&view=auto ============================================================================== --- poolalloc/trunk/test/var_arg/basic.c (added) +++ poolalloc/trunk/test/var_arg/basic.c Wed Jun 16 18:49:35 2010 @@ -0,0 +1,33 @@ +#include +#include +//This is a basic use of vararg pointer use + +//--build the code into a .bc +//RUN: llvm-gcc -O0 %s -S --emit-llvm -o - | llvm-as > %t.bc +//--check if ds-aa breaks, breaks opts, or results in miscompiled code +//RUN: dsaopt %t.bc -ds-aa -O3 -o - | lli -force-interpreter > %t.out1 +//RUN: opt %t.bc -O3 -o - | lli -force-interpreter > %t.out2 +//RUN: diff %t.out1 %t.out2 +//--check properties of this particular test +//N/A + +static int get( int unused, ... ) +{ + va_list ap; + va_start( ap, unused ); + + int *val = va_arg( ap, int* ); + + va_end( ap ); + + return *val; +} + +int main() +{ + int stack_val = 5; + + int ret = get( 0, &stack_val ); + + return ret; +} Added: poolalloc/trunk/test/var_arg/dg.exp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/var_arg/dg.exp?rev=106177&view=auto ============================================================================== --- poolalloc/trunk/test/var_arg/dg.exp (added) +++ poolalloc/trunk/test/var_arg/dg.exp Wed Jun 16 18:49:35 2010 @@ -0,0 +1,3 @@ +load_lib llvm.exp + +RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]] Added: poolalloc/trunk/test/var_arg/multiple_callee.c URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/var_arg/multiple_callee.c?rev=106177&view=auto ============================================================================== --- poolalloc/trunk/test/var_arg/multiple_callee.c (added) +++ poolalloc/trunk/test/var_arg/multiple_callee.c Wed Jun 16 18:49:35 2010 @@ -0,0 +1,54 @@ +#include +//This tests having multiple parameters + +//What to check: +//'val' should alias stack_val and stack_val2 +//'p1' and 'p2' should alias +//'p1' and 'p2' should be modref'd by assign +//(accordingly stack_val/stack_val2 are modref'd) +// +//--build the code into a .bc +//RUN: llvm-gcc -O0 %s -S --emit-llvm -o - | llvm-as > %t.bc +//--check if ds-aa breaks, breaks opts, or results in miscompiled code +//RUN: lli -force-interpreter %t.bc > %t.refout +//RUN: dsaopt %t.bc -ds-aa -O3 -o - | lli -force-interpreter > %t.out +//RUN: diff %t.refout %t.out +//--check properties of this particular test +//N/A + +static int assign( int count, ... ) +{ + va_list ap; + va_start( ap, count ); + + int sum = 0; + int i = 1; + int ** old = va_arg( ap, int** ); + for ( ; i < count; ++i ) + { + int **val = va_arg( ap, int** ); + *old = *val; + old = val; + } + + va_end( ap ); + + return sum; +} + +int main() +{ + int stack_val = 5; + int stack_val2 = 10; + + int * p1 = &stack_val; + int * p2 = &stack_val2; + + assign( 2, &p1, &p2 ); + + if ( p1 != &stack_val || p2 != &stack_val2 ) + { + return -1; + } + return 0; +} From rideau3 at gmail.com Wed Jun 16 18:52:37 2010 From: rideau3 at gmail.com (Sean Hunt) Date: Wed, 16 Jun 2010 23:52:37 -0000 Subject: [llvm-commits] [llvm] r106178 - /llvm/trunk/utils/TableGen/CMakeLists.txt Message-ID: <20100616235237.600F92A6C12C@llvm.org> Author: coppro Date: Wed Jun 16 18:52:37 2010 New Revision: 106178 URL: http://llvm.org/viewvc/llvm-project?rev=106178&view=rev Log: Make sure CMake can build the files added by my previous commit. Modified: llvm/trunk/utils/TableGen/CMakeLists.txt Modified: llvm/trunk/utils/TableGen/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CMakeLists.txt?rev=106178&r1=106177&r2=106178&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CMakeLists.txt (original) +++ llvm/trunk/utils/TableGen/CMakeLists.txt Wed Jun 16 18:52:37 2010 @@ -5,6 +5,7 @@ AsmWriterInst.cpp CallingConvEmitter.cpp ClangASTNodesEmitter.cpp + ClangAttrNodesEmitter.cpp ClangDiagnosticsEmitter.cpp CodeEmitterGen.cpp CodeGenDAGPatterns.cpp From rideau3 at gmail.com Wed Jun 16 19:10:16 2010 From: rideau3 at gmail.com (Sean Hunt) Date: Thu, 17 Jun 2010 00:10:16 -0000 Subject: [llvm-commits] [llvm] r106179 - /llvm/trunk/utils/TableGen/CMakeLists.txt Message-ID: <20100617001016.2DBD12A6C12C@llvm.org> Author: coppro Date: Wed Jun 16 19:10:16 2010 New Revision: 106179 URL: http://llvm.org/viewvc/llvm-project?rev=106179&view=rev Log: Fix the typo in my previous one-line commit. Modified: llvm/trunk/utils/TableGen/CMakeLists.txt Modified: llvm/trunk/utils/TableGen/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CMakeLists.txt?rev=106179&r1=106178&r2=106179&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CMakeLists.txt (original) +++ llvm/trunk/utils/TableGen/CMakeLists.txt Wed Jun 16 19:10:16 2010 @@ -5,7 +5,7 @@ AsmWriterInst.cpp CallingConvEmitter.cpp ClangASTNodesEmitter.cpp - ClangAttrNodesEmitter.cpp + ClangAttrEmitter.cpp ClangDiagnosticsEmitter.cpp CodeEmitterGen.cpp CodeGenDAGPatterns.cpp From bruno.cardoso at gmail.com Wed Jun 16 19:31:36 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Thu, 17 Jun 2010 00:31:36 -0000 Subject: [llvm-commits] [llvm] r106185 - in /llvm/trunk: docs/TableGenFundamentals.html test/TableGen/ifbit.td utils/TableGen/Record.cpp Message-ID: <20100617003136.A00502A6C12C@llvm.org> Author: bruno Date: Wed Jun 16 19:31:36 2010 New Revision: 106185 URL: http://llvm.org/viewvc/llvm-project?rev=106185&view=rev Log: For a tablegen expression such as !if(a,b,c), let 'a' be evaluated for 'bit' operators Added: llvm/trunk/test/TableGen/ifbit.td Modified: llvm/trunk/docs/TableGenFundamentals.html llvm/trunk/utils/TableGen/Record.cpp Modified: llvm/trunk/docs/TableGenFundamentals.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/TableGenFundamentals.html?rev=106185&r1=106184&r2=106185&view=diff ============================================================================== --- llvm/trunk/docs/TableGenFundamentals.html (original) +++ llvm/trunk/docs/TableGenFundamentals.html Wed Jun 16 19:31:36 2010 @@ -422,7 +422,8 @@

!null(a)
An integer {0,1} indicating whether list 'a' is empty.
!if(a,b,c)
-
'b' if the result of integer operator 'a' is nonzero, 'c' otherwise.
+
'b' if the result of 'int' or 'bit' operator 'a' is nonzero, + 'c' otherwise.
!eq(a,b)
Integer one if string a is equal to string b, zero otherwise. This only operates on string, int and bit objects. Use !cast to Added: llvm/trunk/test/TableGen/ifbit.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/TableGen/ifbit.td?rev=106185&view=auto ============================================================================== --- llvm/trunk/test/TableGen/ifbit.td (added) +++ llvm/trunk/test/TableGen/ifbit.td Wed Jun 16 19:31:36 2010 @@ -0,0 +1,11 @@ +// RUN: tblgen %s | FileCheck %s +// XFAIL: vg_leak +// CHECK: a = 6 +// CHECK: a = 5 + +class A { + int a = !if(b, 5, 6); +} + +def X : A<0>; +def Y : A; Modified: llvm/trunk/utils/TableGen/Record.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/Record.cpp?rev=106185&r1=106184&r2=106185&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/Record.cpp (original) +++ llvm/trunk/utils/TableGen/Record.cpp Wed Jun 16 19:31:36 2010 @@ -981,7 +981,8 @@ } case IF: { - IntInit *LHSi = dynamic_cast(LHS); + IntInit *LHSi = + dynamic_cast(LHS->convertInitializerTo(new IntRecTy())); if (LHSi) { if (LHSi->getValue()) { return MHS; @@ -1000,7 +1001,8 @@ Init *lhs = LHS->resolveReferences(R, RV); if (Opc == IF && lhs != LHS) { - IntInit *Value = dynamic_cast(lhs); + IntInit *Value = + dynamic_cast(LHS->convertInitializerTo(new IntRecTy())); if (Value != 0) { // Short-circuit if (Value->getValue()) { From wdietz2 at illinois.edu Wed Jun 16 19:44:35 2010 From: wdietz2 at illinois.edu (Will Dietz) Date: Thu, 17 Jun 2010 00:44:35 -0000 Subject: [llvm-commits] [poolalloc] r106190 - in /poolalloc/trunk/test/var_arg: basic.c multiple_callee.c Message-ID: <20100617004435.913C92A6C12C@llvm.org> Author: wdietz2 Date: Wed Jun 16 19:44:35 2010 New Revision: 106190 URL: http://llvm.org/viewvc/llvm-project?rev=106190&view=rev Log: var_arg tests: clean up return values, simplify test execution Modified: poolalloc/trunk/test/var_arg/basic.c poolalloc/trunk/test/var_arg/multiple_callee.c Modified: poolalloc/trunk/test/var_arg/basic.c URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/var_arg/basic.c?rev=106190&r1=106189&r2=106190&view=diff ============================================================================== --- poolalloc/trunk/test/var_arg/basic.c (original) +++ poolalloc/trunk/test/var_arg/basic.c Wed Jun 16 19:44:35 2010 @@ -5,9 +5,9 @@ //--build the code into a .bc //RUN: llvm-gcc -O0 %s -S --emit-llvm -o - | llvm-as > %t.bc //--check if ds-aa breaks, breaks opts, or results in miscompiled code -//RUN: dsaopt %t.bc -ds-aa -O3 -o - | lli -force-interpreter > %t.out1 -//RUN: opt %t.bc -O3 -o - | lli -force-interpreter > %t.out2 -//RUN: diff %t.out1 %t.out2 +//RUN: lli %t.bc > %t.refout +//RUN: dsaopt %t.bc -ds-aa -O3 -o - | lli > %t.out +//RUN: diff %t.refout %t.out //--check properties of this particular test //N/A @@ -29,5 +29,5 @@ int ret = get( 0, &stack_val ); - return ret; + return ret - 5; } Modified: poolalloc/trunk/test/var_arg/multiple_callee.c URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/var_arg/multiple_callee.c?rev=106190&r1=106189&r2=106190&view=diff ============================================================================== --- poolalloc/trunk/test/var_arg/multiple_callee.c (original) +++ poolalloc/trunk/test/var_arg/multiple_callee.c Wed Jun 16 19:44:35 2010 @@ -10,8 +10,8 @@ //--build the code into a .bc //RUN: llvm-gcc -O0 %s -S --emit-llvm -o - | llvm-as > %t.bc //--check if ds-aa breaks, breaks opts, or results in miscompiled code -//RUN: lli -force-interpreter %t.bc > %t.refout -//RUN: dsaopt %t.bc -ds-aa -O3 -o - | lli -force-interpreter > %t.out +//RUN: lli %t.bc > %t.refout +//RUN: dsaopt %t.bc -ds-aa -instcombine -ds-aa -gvn -ds-aa -dce -o - | lli > %t.out //RUN: diff %t.refout %t.out //--check properties of this particular test //N/A @@ -44,11 +44,13 @@ int * p1 = &stack_val; int * p2 = &stack_val2; + //This will change p1 to point to *p2 assign( 2, &p1, &p2 ); - if ( p1 != &stack_val || p2 != &stack_val2 ) + //This check should succeed, p1 points to stack_val now + if ( p1 != &stack_val ) { - return -1; + return 0; } - return 0; + return -1; } From echristo at apple.com Wed Jun 16 19:49:46 2010 From: echristo at apple.com (Eric Christopher) Date: Thu, 17 Jun 2010 00:49:46 -0000 Subject: [llvm-commits] [llvm] r106191 - /llvm/trunk/lib/MC/MachObjectWriter.cpp Message-ID: <20100617004946.825812A6C12C@llvm.org> Author: echristo Date: Wed Jun 16 19:49:46 2010 New Revision: 106191 URL: http://llvm.org/viewvc/llvm-project?rev=106191&view=rev Log: Update comment. Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MachObjectWriter.cpp?rev=106191&r1=106190&r2=106191&view=diff ============================================================================== --- llvm/trunk/lib/MC/MachObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/MachObjectWriter.cpp Wed Jun 16 19:49:46 2010 @@ -758,7 +758,8 @@ // We're only going to have a second symbol in pic mode and it'll be a // subtraction from the picbase. For 32-bit pic the addend is the difference - // between the picbase and the next address. + // between the picbase and the next address. For 32-bit static the addend + // is zero. if (Target.getSymB()) { IsPCRel = 1; } else { From echristo at apple.com Wed Jun 16 19:51:48 2010 From: echristo at apple.com (Eric Christopher) Date: Thu, 17 Jun 2010 00:51:48 -0000 Subject: [llvm-commits] [llvm] r106194 - /llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp Message-ID: <20100617005148.974F22A6C12C@llvm.org> Author: echristo Date: Wed Jun 16 19:51:48 2010 New Revision: 106194 URL: http://llvm.org/viewvc/llvm-project?rev=106194&view=rev Log: Hack to let the move lowering handle dynamic-no-pic absolute moves of TLVP: movl _a at TLVP, %eax Daniel: Please review if you get a chance. Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp?rev=106194&r1=106193&r2=106194&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp Wed Jun 16 19:51:48 2010 @@ -277,10 +277,21 @@ return; // Check whether this is an absolute address. - if (Inst.getOperand(AddrBase + 0).getReg() != 0 || - Inst.getOperand(AddrBase + 2).getReg() != 0 || - Inst.getOperand(AddrBase + 4).getReg() != 0 || - Inst.getOperand(AddrBase + 1).getImm() != 1) + // FIXME: We know TLVP symbol refs aren't, but there should be a better way + // to do this here. + bool Absolute = true; + if (Inst.getOperand(AddrOp).isExpr()) { + const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr(); + if (const MCSymbolRefExpr *SRE = dyn_cast(MCE)) + if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP) + Absolute = false; + } + + if (Absolute && + (Inst.getOperand(AddrBase + 0).getReg() != 0 || + Inst.getOperand(AddrBase + 2).getReg() != 0 || + Inst.getOperand(AddrBase + 4).getReg() != 0 || + Inst.getOperand(AddrBase + 1).getImm() != 1)) return; // If so, rewrite the instruction. From jmolenda at apple.com Wed Jun 16 20:23:24 2010 From: jmolenda at apple.com (Jason Molenda) Date: Thu, 17 Jun 2010 01:23:24 -0000 Subject: [llvm-commits] [llvm] r106197 - in /llvm/trunk: include/llvm/Support/Dwarf.h lib/Support/Dwarf.cpp Message-ID: <20100617012325.0DFA02A6C12C@llvm.org> Author: jmolenda Date: Wed Jun 16 20:23:24 2010 New Revision: 106197 URL: http://llvm.org/viewvc/llvm-project?rev=106197&view=rev Log: Add the entire range of DW_OP_lit[0..31], DW_OP_reg[0..31], and DW_OP_breg[0..31] to Dwarf.h. Add "DW_" prefix to the llvm::dwarf::*String methods which did not already have them in Dwarf.cpp. Modified: llvm/trunk/include/llvm/Support/Dwarf.h llvm/trunk/lib/Support/Dwarf.cpp Modified: llvm/trunk/include/llvm/Support/Dwarf.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/Dwarf.h?rev=106197&r1=106196&r2=106197&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/Dwarf.h (original) +++ llvm/trunk/include/llvm/Support/Dwarf.h Wed Jun 16 20:23:24 2010 @@ -300,12 +300,99 @@ DW_OP_ne = 0x2e, DW_OP_lit0 = 0x30, DW_OP_lit1 = 0x31, + DW_OP_lit2 = 0x32, + DW_OP_lit3 = 0x33, + DW_OP_lit4 = 0x34, + DW_OP_lit5 = 0x35, + DW_OP_lit6 = 0x36, + DW_OP_lit7 = 0x37, + DW_OP_lit8 = 0x38, + DW_OP_lit9 = 0x39, + DW_OP_lit10 = 0x3a, + DW_OP_lit11 = 0x3b, + DW_OP_lit12 = 0x3c, + DW_OP_lit13 = 0x3d, + DW_OP_lit14 = 0x3e, + DW_OP_lit15 = 0x3f, + DW_OP_lit16 = 0x40, + DW_OP_lit17 = 0x41, + DW_OP_lit18 = 0x42, + DW_OP_lit19 = 0x43, + DW_OP_lit20 = 0x44, + DW_OP_lit21 = 0x45, + DW_OP_lit22 = 0x46, + DW_OP_lit23 = 0x47, + DW_OP_lit24 = 0x48, + DW_OP_lit25 = 0x49, + DW_OP_lit26 = 0x4a, + DW_OP_lit27 = 0x4b, + DW_OP_lit28 = 0x4c, + DW_OP_lit29 = 0x4d, + DW_OP_lit30 = 0x4e, DW_OP_lit31 = 0x4f, DW_OP_reg0 = 0x50, DW_OP_reg1 = 0x51, + DW_OP_reg2 = 0x52, + DW_OP_reg3 = 0x53, + DW_OP_reg4 = 0x54, + DW_OP_reg5 = 0x55, + DW_OP_reg6 = 0x56, + DW_OP_reg7 = 0x57, + DW_OP_reg8 = 0x58, + DW_OP_reg9 = 0x59, + DW_OP_reg10 = 0x5a, + DW_OP_reg11 = 0x5b, + DW_OP_reg12 = 0x5c, + DW_OP_reg13 = 0x5d, + DW_OP_reg14 = 0x5e, + DW_OP_reg15 = 0x5f, + DW_OP_reg16 = 0x60, + DW_OP_reg17 = 0x61, + DW_OP_reg18 = 0x62, + DW_OP_reg19 = 0x63, + DW_OP_reg20 = 0x64, + DW_OP_reg21 = 0x65, + DW_OP_reg22 = 0x66, + DW_OP_reg23 = 0x67, + DW_OP_reg24 = 0x68, + DW_OP_reg25 = 0x69, + DW_OP_reg26 = 0x6a, + DW_OP_reg27 = 0x6b, + DW_OP_reg28 = 0x6c, + DW_OP_reg29 = 0x6d, + DW_OP_reg30 = 0x6e, DW_OP_reg31 = 0x6f, DW_OP_breg0 = 0x70, DW_OP_breg1 = 0x71, + DW_OP_breg2 = 0x72, + DW_OP_breg3 = 0x73, + DW_OP_breg4 = 0x74, + DW_OP_breg5 = 0x75, + DW_OP_breg6 = 0x76, + DW_OP_breg7 = 0x77, + DW_OP_breg8 = 0x78, + DW_OP_breg9 = 0x79, + DW_OP_breg10 = 0x7a, + DW_OP_breg11 = 0x7b, + DW_OP_breg12 = 0x7c, + DW_OP_breg13 = 0x7d, + DW_OP_breg14 = 0x7e, + DW_OP_breg15 = 0x7f, + DW_OP_breg16 = 0x80, + DW_OP_breg17 = 0x81, + DW_OP_breg18 = 0x82, + DW_OP_breg19 = 0x83, + DW_OP_breg20 = 0x84, + DW_OP_breg21 = 0x85, + DW_OP_breg22 = 0x86, + DW_OP_breg23 = 0x87, + DW_OP_breg24 = 0x88, + DW_OP_breg25 = 0x89, + DW_OP_breg26 = 0x8a, + DW_OP_breg27 = 0x8b, + DW_OP_breg28 = 0x8c, + DW_OP_breg29 = 0x8d, + DW_OP_breg30 = 0x8e, DW_OP_breg31 = 0x8f, DW_OP_regx = 0x90, DW_OP_fbreg = 0x91, Modified: llvm/trunk/lib/Support/Dwarf.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Dwarf.cpp?rev=106197&r1=106196&r2=106197&view=diff ============================================================================== --- llvm/trunk/lib/Support/Dwarf.cpp (original) +++ llvm/trunk/lib/Support/Dwarf.cpp Wed Jun 16 20:23:24 2010 @@ -86,8 +86,8 @@ /// const char *llvm::dwarf::ChildrenString(unsigned Children) { switch (Children) { - case DW_CHILDREN_no: return "CHILDREN_no"; - case DW_CHILDREN_yes: return "CHILDREN_yes"; + case DW_CHILDREN_no: return "DW_CHILDREN_no"; + case DW_CHILDREN_yes: return "DW_CHILDREN_yes"; } return 0; } @@ -207,27 +207,27 @@ /// const char *llvm::dwarf::FormEncodingString(unsigned Encoding) { switch (Encoding) { - case DW_FORM_addr: return "FORM_addr"; - case DW_FORM_block2: return "FORM_block2"; - case DW_FORM_block4: return "FORM_block4"; - case DW_FORM_data2: return "FORM_data2"; - case DW_FORM_data4: return "FORM_data4"; - case DW_FORM_data8: return "FORM_data8"; - case DW_FORM_string: return "FORM_string"; - case DW_FORM_block: return "FORM_block"; - case DW_FORM_block1: return "FORM_block1"; - case DW_FORM_data1: return "FORM_data1"; - case DW_FORM_flag: return "FORM_flag"; - case DW_FORM_sdata: return "FORM_sdata"; - case DW_FORM_strp: return "FORM_strp"; - case DW_FORM_udata: return "FORM_udata"; - case DW_FORM_ref_addr: return "FORM_ref_addr"; - case DW_FORM_ref1: return "FORM_ref1"; - case DW_FORM_ref2: return "FORM_ref2"; - case DW_FORM_ref4: return "FORM_ref4"; - case DW_FORM_ref8: return "FORM_ref8"; - case DW_FORM_ref_udata: return "FORM_ref_udata"; - case DW_FORM_indirect: return "FORM_indirect"; + case DW_FORM_addr: return "DW_FORM_addr"; + case DW_FORM_block2: return "DW_FORM_block2"; + case DW_FORM_block4: return "DW_FORM_block4"; + case DW_FORM_data2: return "DW_FORM_data2"; + case DW_FORM_data4: return "DW_FORM_data4"; + case DW_FORM_data8: return "DW_FORM_data8"; + case DW_FORM_string: return "DW_FORM_string"; + case DW_FORM_block: return "DW_FORM_block"; + case DW_FORM_block1: return "DW_FORM_block1"; + case DW_FORM_data1: return "DW_FORM_data1"; + case DW_FORM_flag: return "DW_FORM_flag"; + case DW_FORM_sdata: return "DW_FORM_sdata"; + case DW_FORM_strp: return "DW_FORM_strp"; + case DW_FORM_udata: return "DW_FORM_udata"; + case DW_FORM_ref_addr: return "DW_FORM_ref_addr"; + case DW_FORM_ref1: return "DW_FORM_ref1"; + case DW_FORM_ref2: return "DW_FORM_ref2"; + case DW_FORM_ref4: return "DW_FORM_ref4"; + case DW_FORM_ref8: return "DW_FORM_ref8"; + case DW_FORM_ref_udata: return "DW_FORM_ref_udata"; + case DW_FORM_indirect: return "DW_FORM_indirect"; } return 0; } @@ -236,72 +236,159 @@ /// encoding. const char *llvm::dwarf::OperationEncodingString(unsigned Encoding) { switch (Encoding) { - case DW_OP_addr: return "OP_addr"; - case DW_OP_deref: return "OP_deref"; - case DW_OP_const1u: return "OP_const1u"; - case DW_OP_const1s: return "OP_const1s"; - case DW_OP_const2u: return "OP_const2u"; - case DW_OP_const2s: return "OP_const2s"; - case DW_OP_const4u: return "OP_const4u"; - case DW_OP_const4s: return "OP_const4s"; - case DW_OP_const8u: return "OP_const8u"; - case DW_OP_const8s: return "OP_const8s"; - case DW_OP_constu: return "OP_constu"; - case DW_OP_consts: return "OP_consts"; - case DW_OP_dup: return "OP_dup"; - case DW_OP_drop: return "OP_drop"; - case DW_OP_over: return "OP_over"; - case DW_OP_pick: return "OP_pick"; - case DW_OP_swap: return "OP_swap"; - case DW_OP_rot: return "OP_rot"; - case DW_OP_xderef: return "OP_xderef"; - case DW_OP_abs: return "OP_abs"; - case DW_OP_and: return "OP_and"; - case DW_OP_div: return "OP_div"; - case DW_OP_minus: return "OP_minus"; - case DW_OP_mod: return "OP_mod"; - case DW_OP_mul: return "OP_mul"; - case DW_OP_neg: return "OP_neg"; - case DW_OP_not: return "OP_not"; - case DW_OP_or: return "OP_or"; - case DW_OP_plus: return "OP_plus"; - case DW_OP_plus_uconst: return "OP_plus_uconst"; - case DW_OP_shl: return "OP_shl"; - case DW_OP_shr: return "OP_shr"; - case DW_OP_shra: return "OP_shra"; - case DW_OP_xor: return "OP_xor"; - case DW_OP_skip: return "OP_skip"; - case DW_OP_bra: return "OP_bra"; - case DW_OP_eq: return "OP_eq"; - case DW_OP_ge: return "OP_ge"; - case DW_OP_gt: return "OP_gt"; - case DW_OP_le: return "OP_le"; - case DW_OP_lt: return "OP_lt"; - case DW_OP_ne: return "OP_ne"; - case DW_OP_lit0: return "OP_lit0"; - case DW_OP_lit1: return "OP_lit1"; - case DW_OP_lit31: return "OP_lit31"; - case DW_OP_reg0: return "OP_reg0"; - case DW_OP_reg1: return "OP_reg1"; - case DW_OP_reg31: return "OP_reg31"; - case DW_OP_breg0: return "OP_breg0"; - case DW_OP_breg1: return "OP_breg1"; - case DW_OP_breg31: return "OP_breg31"; - case DW_OP_regx: return "OP_regx"; - case DW_OP_fbreg: return "OP_fbreg"; - case DW_OP_bregx: return "OP_bregx"; - case DW_OP_piece: return "OP_piece"; - case DW_OP_deref_size: return "OP_deref_size"; - case DW_OP_xderef_size: return "OP_xderef_size"; - case DW_OP_nop: return "OP_nop"; - case DW_OP_push_object_address: return "OP_push_object_address"; - case DW_OP_call2: return "OP_call2"; - case DW_OP_call4: return "OP_call4"; - case DW_OP_call_ref: return "OP_call_ref"; - case DW_OP_form_tls_address: return "OP_form_tls_address"; - case DW_OP_call_frame_cfa: return "OP_call_frame_cfa"; - case DW_OP_lo_user: return "OP_lo_user"; - case DW_OP_hi_user: return "OP_hi_user"; + case DW_OP_addr: return "DW_OP_addr"; + case DW_OP_deref: return "DW_OP_deref"; + case DW_OP_const1u: return "DW_OP_const1u"; + case DW_OP_const1s: return "DW_OP_const1s"; + case DW_OP_const2u: return "DW_OP_const2u"; + case DW_OP_const2s: return "DW_OP_const2s"; + case DW_OP_const4u: return "DW_OP_const4u"; + case DW_OP_const4s: return "DW_OP_const4s"; + case DW_OP_const8u: return "DW_OP_const8u"; + case DW_OP_const8s: return "DW_OP_const8s"; + case DW_OP_constu: return "DW_OP_constu"; + case DW_OP_consts: return "DW_OP_consts"; + case DW_OP_dup: return "DW_OP_dup"; + case DW_OP_drop: return "DW_OP_drop"; + case DW_OP_over: return "DW_OP_over"; + case DW_OP_pick: return "DW_OP_pick"; + case DW_OP_swap: return "DW_OP_swap"; + case DW_OP_rot: return "DW_OP_rot"; + case DW_OP_xderef: return "DW_OP_xderef"; + case DW_OP_abs: return "DW_OP_abs"; + case DW_OP_and: return "DW_OP_and"; + case DW_OP_div: return "DW_OP_div"; + case DW_OP_minus: return "DW_OP_minus"; + case DW_OP_mod: return "DW_OP_mod"; + case DW_OP_mul: return "DW_OP_mul"; + case DW_OP_neg: return "DW_OP_neg"; + case DW_OP_not: return "DW_OP_not"; + case DW_OP_or: return "DW_OP_or"; + case DW_OP_plus: return "DW_OP_plus"; + case DW_OP_plus_uconst: return "DW_OP_plus_uconst"; + case DW_OP_shl: return "DW_OP_shl"; + case DW_OP_shr: return "DW_OP_shr"; + case DW_OP_shra: return "DW_OP_shra"; + case DW_OP_xor: return "DW_OP_xor"; + case DW_OP_skip: return "DW_OP_skip"; + case DW_OP_bra: return "DW_OP_bra"; + case DW_OP_eq: return "DW_OP_eq"; + case DW_OP_ge: return "DW_OP_ge"; + case DW_OP_gt: return "DW_OP_gt"; + case DW_OP_le: return "DW_OP_le"; + case DW_OP_lt: return "DW_OP_lt"; + case DW_OP_ne: return "DW_OP_ne"; + case DW_OP_lit0: return "DW_OP_lit0"; + case DW_OP_lit1: return "DW_OP_lit1"; + case DW_OP_lit2: return "DW_OP_lit2"; + case DW_OP_lit3: return "DW_OP_lit3"; + case DW_OP_lit4: return "DW_OP_lit4"; + case DW_OP_lit5: return "DW_OP_lit5"; + case DW_OP_lit6: return "DW_OP_lit6"; + case DW_OP_lit7: return "DW_OP_lit7"; + case DW_OP_lit8: return "DW_OP_lit8"; + case DW_OP_lit9: return "DW_OP_lit9"; + case DW_OP_lit10: return "DW_OP_lit10"; + case DW_OP_lit11: return "DW_OP_lit11"; + case DW_OP_lit12: return "DW_OP_lit12"; + case DW_OP_lit13: return "DW_OP_lit13"; + case DW_OP_lit14: return "DW_OP_lit14"; + case DW_OP_lit15: return "DW_OP_lit15"; + case DW_OP_lit16: return "DW_OP_lit16"; + case DW_OP_lit17: return "DW_OP_lit17"; + case DW_OP_lit18: return "DW_OP_lit18"; + case DW_OP_lit19: return "DW_OP_lit19"; + case DW_OP_lit20: return "DW_OP_lit20"; + case DW_OP_lit21: return "DW_OP_lit21"; + case DW_OP_lit22: return "DW_OP_lit22"; + case DW_OP_lit23: return "DW_OP_lit23"; + case DW_OP_lit24: return "DW_OP_lit24"; + case DW_OP_lit25: return "DW_OP_lit25"; + case DW_OP_lit26: return "DW_OP_lit26"; + case DW_OP_lit27: return "DW_OP_lit27"; + case DW_OP_lit28: return "DW_OP_lit28"; + case DW_OP_lit29: return "DW_OP_lit29"; + case DW_OP_lit30: return "DW_OP_lit30"; + case DW_OP_lit31: return "DW_OP_lit31"; + case DW_OP_reg0: return "DW_OP_reg0"; + case DW_OP_reg1: return "DW_OP_reg1"; + case DW_OP_reg2: return "DW_OP_reg2"; + case DW_OP_reg3: return "DW_OP_reg3"; + case DW_OP_reg4: return "DW_OP_reg4"; + case DW_OP_reg5: return "DW_OP_reg5"; + case DW_OP_reg6: return "DW_OP_reg6"; + case DW_OP_reg7: return "DW_OP_reg7"; + case DW_OP_reg8: return "DW_OP_reg8"; + case DW_OP_reg9: return "DW_OP_reg9"; + case DW_OP_reg10: return "DW_OP_reg10"; + case DW_OP_reg11: return "DW_OP_reg11"; + case DW_OP_reg12: return "DW_OP_reg12"; + case DW_OP_reg13: return "DW_OP_reg13"; + case DW_OP_reg14: return "DW_OP_reg14"; + case DW_OP_reg15: return "DW_OP_reg15"; + case DW_OP_reg16: return "DW_OP_reg16"; + case DW_OP_reg17: return "DW_OP_reg17"; + case DW_OP_reg18: return "DW_OP_reg18"; + case DW_OP_reg19: return "DW_OP_reg19"; + case DW_OP_reg20: return "DW_OP_reg20"; + case DW_OP_reg21: return "DW_OP_reg21"; + case DW_OP_reg22: return "DW_OP_reg22"; + case DW_OP_reg23: return "DW_OP_reg23"; + case DW_OP_reg24: return "DW_OP_reg24"; + case DW_OP_reg25: return "DW_OP_reg25"; + case DW_OP_reg26: return "DW_OP_reg26"; + case DW_OP_reg27: return "DW_OP_reg27"; + case DW_OP_reg28: return "DW_OP_reg28"; + case DW_OP_reg29: return "DW_OP_reg29"; + case DW_OP_reg30: return "DW_OP_reg30"; + case DW_OP_reg31: return "DW_OP_reg31"; + case DW_OP_breg0: return "DW_OP_breg0"; + case DW_OP_breg1: return "DW_OP_breg1"; + case DW_OP_breg2: return "DW_OP_breg2"; + case DW_OP_breg3: return "DW_OP_breg3"; + case DW_OP_breg4: return "DW_OP_breg4"; + case DW_OP_breg5: return "DW_OP_breg5"; + case DW_OP_breg6: return "DW_OP_breg6"; + case DW_OP_breg7: return "DW_OP_breg7"; + case DW_OP_breg8: return "DW_OP_breg8"; + case DW_OP_breg9: return "DW_OP_breg9"; + case DW_OP_breg10: return "DW_OP_breg10"; + case DW_OP_breg11: return "DW_OP_breg11"; + case DW_OP_breg12: return "DW_OP_breg12"; + case DW_OP_breg13: return "DW_OP_breg13"; + case DW_OP_breg14: return "DW_OP_breg14"; + case DW_OP_breg15: return "DW_OP_breg15"; + case DW_OP_breg16: return "DW_OP_breg16"; + case DW_OP_breg17: return "DW_OP_breg17"; + case DW_OP_breg18: return "DW_OP_breg18"; + case DW_OP_breg19: return "DW_OP_breg19"; + case DW_OP_breg20: return "DW_OP_breg20"; + case DW_OP_breg21: return "DW_OP_breg21"; + case DW_OP_breg22: return "DW_OP_breg22"; + case DW_OP_breg23: return "DW_OP_breg23"; + case DW_OP_breg24: return "DW_OP_breg24"; + case DW_OP_breg25: return "DW_OP_breg25"; + case DW_OP_breg26: return "DW_OP_breg26"; + case DW_OP_breg27: return "DW_OP_breg27"; + case DW_OP_breg28: return "DW_OP_breg28"; + case DW_OP_breg29: return "DW_OP_breg29"; + case DW_OP_breg30: return "DW_OP_breg30"; + case DW_OP_breg31: return "DW_OP_breg31"; + case DW_OP_regx: return "DW_OP_regx"; + case DW_OP_fbreg: return "DW_OP_fbreg"; + case DW_OP_bregx: return "DW_OP_bregx"; + case DW_OP_piece: return "DW_OP_piece"; + case DW_OP_deref_size: return "DW_OP_deref_size"; + case DW_OP_xderef_size: return "DW_OP_xderef_size"; + case DW_OP_nop: return "DW_OP_nop"; + case DW_OP_push_object_address: return "DW_OP_push_object_address"; + case DW_OP_call2: return "DW_OP_call2"; + case DW_OP_call4: return "DW_OP_call4"; + case DW_OP_call_ref: return "DW_OP_call_ref"; + case DW_OP_form_tls_address: return "DW_OP_form_tls_address"; + case DW_OP_call_frame_cfa: return "DW_OP_call_frame_cfa"; + case DW_OP_lo_user: return "DW_OP_lo_user"; + case DW_OP_hi_user: return "DW_OP_hi_user"; } return 0; } @@ -310,23 +397,23 @@ /// encoding. const char *llvm::dwarf::AttributeEncodingString(unsigned Encoding) { switch (Encoding) { - case DW_ATE_address: return "ATE_address"; - case DW_ATE_boolean: return "ATE_boolean"; - case DW_ATE_complex_float: return "ATE_complex_float"; - case DW_ATE_float: return "ATE_float"; - case DW_ATE_signed: return "ATE_signed"; - case DW_ATE_signed_char: return "ATE_signed_char"; - case DW_ATE_unsigned: return "ATE_unsigned"; - case DW_ATE_unsigned_char: return "ATE_unsigned_char"; - case DW_ATE_imaginary_float: return "ATE_imaginary_float"; - case DW_ATE_packed_decimal: return "ATE_packed_decimal"; - case DW_ATE_numeric_string: return "ATE_numeric_string"; - case DW_ATE_edited: return "ATE_edited"; - case DW_ATE_signed_fixed: return "ATE_signed_fixed"; - case DW_ATE_unsigned_fixed: return "ATE_unsigned_fixed"; - case DW_ATE_decimal_float: return "ATE_decimal_float"; - case DW_ATE_lo_user: return "ATE_lo_user"; - case DW_ATE_hi_user: return "ATE_hi_user"; + case DW_ATE_address: return "DW_ATE_address"; + case DW_ATE_boolean: return "DW_ATE_boolean"; + case DW_ATE_complex_float: return "DW_ATE_complex_float"; + case DW_ATE_float: return "DW_ATE_float"; + case DW_ATE_signed: return "DW_ATE_signed"; + case DW_ATE_signed_char: return "DW_ATE_signed_char"; + case DW_ATE_unsigned: return "DW_ATE_unsigned"; + case DW_ATE_unsigned_char: return "DW_ATE_unsigned_char"; + case DW_ATE_imaginary_float: return "DW_ATE_imaginary_float"; + case DW_ATE_packed_decimal: return "DW_ATE_packed_decimal"; + case DW_ATE_numeric_string: return "DW_ATE_numeric_string"; + case DW_ATE_edited: return "DW_ATE_edited"; + case DW_ATE_signed_fixed: return "DW_ATE_signed_fixed"; + case DW_ATE_unsigned_fixed: return "DW_ATE_unsigned_fixed"; + case DW_ATE_decimal_float: return "DW_ATE_decimal_float"; + case DW_ATE_lo_user: return "DW_ATE_lo_user"; + case DW_ATE_hi_user: return "DW_ATE_hi_user"; } return 0; } @@ -335,11 +422,11 @@ /// attribute. const char *llvm::dwarf::DecimalSignString(unsigned Sign) { switch (Sign) { - case DW_DS_unsigned: return "DS_unsigned"; - case DW_DS_leading_overpunch: return "DS_leading_overpunch"; - case DW_DS_trailing_overpunch: return "DS_trailing_overpunch"; - case DW_DS_leading_separate: return "DS_leading_separate"; - case DW_DS_trailing_separate: return "DS_trailing_separate"; + case DW_DS_unsigned: return "DW_DS_unsigned"; + case DW_DS_leading_overpunch: return "DW_DS_leading_overpunch"; + case DW_DS_trailing_overpunch: return "DW_DS_trailing_overpunch"; + case DW_DS_leading_separate: return "DW_DS_leading_separate"; + case DW_DS_trailing_separate: return "DW_DS_trailing_separate"; } return 0; } @@ -348,11 +435,11 @@ /// const char *llvm::dwarf::EndianityString(unsigned Endian) { switch (Endian) { - case DW_END_default: return "END_default"; - case DW_END_big: return "END_big"; - case DW_END_little: return "END_little"; - case DW_END_lo_user: return "END_lo_user"; - case DW_END_hi_user: return "END_hi_user"; + case DW_END_default: return "DW_END_default"; + case DW_END_big: return "DW_END_big"; + case DW_END_little: return "DW_END_little"; + case DW_END_lo_user: return "DW_END_lo_user"; + case DW_END_hi_user: return "DW_END_hi_user"; } return 0; } @@ -362,9 +449,9 @@ const char *llvm::dwarf::AccessibilityString(unsigned Access) { switch (Access) { // Accessibility codes - case DW_ACCESS_public: return "ACCESS_public"; - case DW_ACCESS_protected: return "ACCESS_protected"; - case DW_ACCESS_private: return "ACCESS_private"; + case DW_ACCESS_public: return "DW_ACCESS_public"; + case DW_ACCESS_protected: return "DW_ACCESS_protected"; + case DW_ACCESS_private: return "DW_ACCESS_private"; } return 0; } @@ -373,9 +460,9 @@ /// const char *llvm::dwarf::VisibilityString(unsigned Visibility) { switch (Visibility) { - case DW_VIS_local: return "VIS_local"; - case DW_VIS_exported: return "VIS_exported"; - case DW_VIS_qualified: return "VIS_qualified"; + case DW_VIS_local: return "DW_VIS_local"; + case DW_VIS_exported: return "DW_VIS_exported"; + case DW_VIS_qualified: return "DW_VIS_qualified"; } return 0; } @@ -384,9 +471,9 @@ /// const char *llvm::dwarf::VirtualityString(unsigned Virtuality) { switch (Virtuality) { - case DW_VIRTUALITY_none: return "VIRTUALITY_none"; - case DW_VIRTUALITY_virtual: return "VIRTUALITY_virtual"; - case DW_VIRTUALITY_pure_virtual: return "VIRTUALITY_pure_virtual"; + case DW_VIRTUALITY_none: return "DW_VIRTUALITY_none"; + case DW_VIRTUALITY_virtual: return "DW_VIRTUALITY_virtual"; + case DW_VIRTUALITY_pure_virtual: return "DW_VIRTUALITY_pure_virtual"; } return 0; } @@ -395,27 +482,27 @@ /// const char *llvm::dwarf::LanguageString(unsigned Language) { switch (Language) { - case DW_LANG_C89: return "LANG_C89"; - case DW_LANG_C: return "LANG_C"; - case DW_LANG_Ada83: return "LANG_Ada83"; - case DW_LANG_C_plus_plus: return "LANG_C_plus_plus"; - case DW_LANG_Cobol74: return "LANG_Cobol74"; - case DW_LANG_Cobol85: return "LANG_Cobol85"; - case DW_LANG_Fortran77: return "LANG_Fortran77"; - case DW_LANG_Fortran90: return "LANG_Fortran90"; - case DW_LANG_Pascal83: return "LANG_Pascal83"; - case DW_LANG_Modula2: return "LANG_Modula2"; - case DW_LANG_Java: return "LANG_Java"; - case DW_LANG_C99: return "LANG_C99"; - case DW_LANG_Ada95: return "LANG_Ada95"; - case DW_LANG_Fortran95: return "LANG_Fortran95"; - case DW_LANG_PLI: return "LANG_PLI"; - case DW_LANG_ObjC: return "LANG_ObjC"; - case DW_LANG_ObjC_plus_plus: return "LANG_ObjC_plus_plus"; - case DW_LANG_UPC: return "LANG_UPC"; - case DW_LANG_D: return "LANG_D"; - case DW_LANG_lo_user: return "LANG_lo_user"; - case DW_LANG_hi_user: return "LANG_hi_user"; + case DW_LANG_C89: return "DW_LANG_C89"; + case DW_LANG_C: return "DW_LANG_C"; + case DW_LANG_Ada83: return "DW_LANG_Ada83"; + case DW_LANG_C_plus_plus: return "DW_LANG_C_plus_plus"; + case DW_LANG_Cobol74: return "DW_LANG_Cobol74"; + case DW_LANG_Cobol85: return "DW_LANG_Cobol85"; + case DW_LANG_Fortran77: return "DW_LANG_Fortran77"; + case DW_LANG_Fortran90: return "DW_LANG_Fortran90"; + case DW_LANG_Pascal83: return "DW_LANG_Pascal83"; + case DW_LANG_Modula2: return "DW_LANG_Modula2"; + case DW_LANG_Java: return "DW_LANG_Java"; + case DW_LANG_C99: return "DW_LANG_C99"; + case DW_LANG_Ada95: return "DW_LANG_Ada95"; + case DW_LANG_Fortran95: return "DW_LANG_Fortran95"; + case DW_LANG_PLI: return "DW_LANG_PLI"; + case DW_LANG_ObjC: return "DW_LANG_ObjC"; + case DW_LANG_ObjC_plus_plus: return "DW_LANG_ObjC_plus_plus"; + case DW_LANG_UPC: return "DW_LANG_UPC"; + case DW_LANG_D: return "DW_LANG_D"; + case DW_LANG_lo_user: return "DW_LANG_lo_user"; + case DW_LANG_hi_user: return "DW_LANG_hi_user"; } return 0; } @@ -424,10 +511,10 @@ /// const char *llvm::dwarf::CaseString(unsigned Case) { switch (Case) { - case DW_ID_case_sensitive: return "ID_case_sensitive"; - case DW_ID_up_case: return "ID_up_case"; - case DW_ID_down_case: return "ID_down_case"; - case DW_ID_case_insensitive: return "ID_case_insensitive"; + case DW_ID_case_sensitive: return "DW_ID_case_sensitive"; + case DW_ID_up_case: return "DW_ID_up_case"; + case DW_ID_down_case: return "DW_ID_down_case"; + case DW_ID_case_insensitive: return "DW_ID_case_insensitive"; } return 0; } @@ -436,11 +523,11 @@ /// const char *llvm::dwarf::ConventionString(unsigned Convention) { switch (Convention) { - case DW_CC_normal: return "CC_normal"; - case DW_CC_program: return "CC_program"; - case DW_CC_nocall: return "CC_nocall"; - case DW_CC_lo_user: return "CC_lo_user"; - case DW_CC_hi_user: return "CC_hi_user"; + case DW_CC_normal: return "DW_CC_normal"; + case DW_CC_program: return "DW_CC_program"; + case DW_CC_nocall: return "DW_CC_nocall"; + case DW_CC_lo_user: return "DW_CC_lo_user"; + case DW_CC_hi_user: return "DW_CC_hi_user"; } return 0; } @@ -449,10 +536,10 @@ /// const char *llvm::dwarf::InlineCodeString(unsigned Code) { switch (Code) { - case DW_INL_not_inlined: return "INL_not_inlined"; - case DW_INL_inlined: return "INL_inlined"; - case DW_INL_declared_not_inlined: return "INL_declared_not_inlined"; - case DW_INL_declared_inlined: return "INL_declared_inlined"; + case DW_INL_not_inlined: return "DW_INL_not_inlined"; + case DW_INL_inlined: return "DW_INL_inlined"; + case DW_INL_declared_not_inlined: return "DW_INL_declared_not_inlined"; + case DW_INL_declared_inlined: return "DW_INL_declared_inlined"; } return 0; } @@ -461,8 +548,8 @@ /// const char *llvm::dwarf::ArrayOrderString(unsigned Order) { switch (Order) { - case DW_ORD_row_major: return "ORD_row_major"; - case DW_ORD_col_major: return "ORD_col_major"; + case DW_ORD_row_major: return "DW_ORD_row_major"; + case DW_ORD_col_major: return "DW_ORD_col_major"; } return 0; } @@ -471,8 +558,8 @@ /// descriptor. const char *llvm::dwarf::DiscriminantString(unsigned Discriminant) { switch (Discriminant) { - case DW_DSC_label: return "DSC_label"; - case DW_DSC_range: return "DSC_range"; + case DW_DSC_label: return "DW_DSC_label"; + case DW_DSC_range: return "DW_DSC_range"; } return 0; } @@ -481,18 +568,18 @@ /// const char *llvm::dwarf::LNStandardString(unsigned Standard) { switch (Standard) { - case DW_LNS_copy: return "LNS_copy"; - case DW_LNS_advance_pc: return "LNS_advance_pc"; - case DW_LNS_advance_line: return "LNS_advance_line"; - case DW_LNS_set_file: return "LNS_set_file"; - case DW_LNS_set_column: return "LNS_set_column"; - case DW_LNS_negate_stmt: return "LNS_negate_stmt"; - case DW_LNS_set_basic_block: return "LNS_set_basic_block"; - case DW_LNS_const_add_pc: return "LNS_const_add_pc"; - case DW_LNS_fixed_advance_pc: return "LNS_fixed_advance_pc"; - case DW_LNS_set_prologue_end: return "LNS_set_prologue_end"; - case DW_LNS_set_epilogue_begin: return "LNS_set_epilogue_begin"; - case DW_LNS_set_isa: return "LNS_set_isa"; + case DW_LNS_copy: return "DW_LNS_copy"; + case DW_LNS_advance_pc: return "DW_LNS_advance_pc"; + case DW_LNS_advance_line: return "DW_LNS_advance_line"; + case DW_LNS_set_file: return "DW_LNS_set_file"; + case DW_LNS_set_column: return "DW_LNS_set_column"; + case DW_LNS_negate_stmt: return "DW_LNS_negate_stmt"; + case DW_LNS_set_basic_block: return "DW_LNS_set_basic_block"; + case DW_LNS_const_add_pc: return "DW_LNS_const_add_pc"; + case DW_LNS_fixed_advance_pc: return "DW_LNS_fixed_advance_pc"; + case DW_LNS_set_prologue_end: return "DW_LNS_set_prologue_end"; + case DW_LNS_set_epilogue_begin: return "DW_LNS_set_epilogue_begin"; + case DW_LNS_set_isa: return "DW_LNS_set_isa"; } return 0; } @@ -502,11 +589,11 @@ const char *llvm::dwarf::LNExtendedString(unsigned Encoding) { switch (Encoding) { // Line Number Extended Opcode Encodings - case DW_LNE_end_sequence: return "LNE_end_sequence"; - case DW_LNE_set_address: return "LNE_set_address"; - case DW_LNE_define_file: return "LNE_define_file"; - case DW_LNE_lo_user: return "LNE_lo_user"; - case DW_LNE_hi_user: return "LNE_hi_user"; + case DW_LNE_end_sequence: return "DW_LNE_end_sequence"; + case DW_LNE_set_address: return "DW_LNE_set_address"; + case DW_LNE_define_file: return "DW_LNE_define_file"; + case DW_LNE_lo_user: return "DW_LNE_lo_user"; + case DW_LNE_hi_user: return "DW_LNE_hi_user"; } return 0; } @@ -516,11 +603,11 @@ const char *llvm::dwarf::MacinfoString(unsigned Encoding) { switch (Encoding) { // Macinfo Type Encodings - case DW_MACINFO_define: return "MACINFO_define"; - case DW_MACINFO_undef: return "MACINFO_undef"; - case DW_MACINFO_start_file: return "MACINFO_start_file"; - case DW_MACINFO_end_file: return "MACINFO_end_file"; - case DW_MACINFO_vendor_ext: return "MACINFO_vendor_ext"; + case DW_MACINFO_define: return "DW_MACINFO_define"; + case DW_MACINFO_undef: return "DW_MACINFO_undef"; + case DW_MACINFO_start_file: return "DW_MACINFO_start_file"; + case DW_MACINFO_end_file: return "DW_MACINFO_end_file"; + case DW_MACINFO_vendor_ext: return "DW_MACINFO_vendor_ext"; } return 0; } @@ -529,33 +616,33 @@ /// encodings. const char *llvm::dwarf::CallFrameString(unsigned Encoding) { switch (Encoding) { - case DW_CFA_advance_loc: return "CFA_advance_loc"; - case DW_CFA_offset: return "CFA_offset"; - case DW_CFA_restore: return "CFA_restore"; - case DW_CFA_set_loc: return "CFA_set_loc"; - case DW_CFA_advance_loc1: return "CFA_advance_loc1"; - case DW_CFA_advance_loc2: return "CFA_advance_loc2"; - case DW_CFA_advance_loc4: return "CFA_advance_loc4"; - case DW_CFA_offset_extended: return "CFA_offset_extended"; - case DW_CFA_restore_extended: return "CFA_restore_extended"; - case DW_CFA_undefined: return "CFA_undefined"; - case DW_CFA_same_value: return "CFA_same_value"; - case DW_CFA_register: return "CFA_register"; - case DW_CFA_remember_state: return "CFA_remember_state"; - case DW_CFA_restore_state: return "CFA_restore_state"; - case DW_CFA_def_cfa: return "CFA_def_cfa"; - case DW_CFA_def_cfa_register: return "CFA_def_cfa_register"; - case DW_CFA_def_cfa_offset: return "CFA_def_cfa_offset"; - case DW_CFA_def_cfa_expression: return "CFA_def_cfa_expression"; - case DW_CFA_expression: return "CFA_expression"; - case DW_CFA_offset_extended_sf: return "CFA_offset_extended_sf"; - case DW_CFA_def_cfa_sf: return "CFA_def_cfa_sf"; - case DW_CFA_def_cfa_offset_sf: return "CFA_def_cfa_offset_sf"; - case DW_CFA_val_offset: return "CFA_val_offset"; - case DW_CFA_val_offset_sf: return "CFA_val_offset_sf"; - case DW_CFA_val_expression: return "CFA_val_expression"; - case DW_CFA_lo_user: return "CFA_lo_user"; - case DW_CFA_hi_user: return "CFA_hi_user"; + case DW_CFA_advance_loc: return "DW_CFA_advance_loc"; + case DW_CFA_offset: return "DW_CFA_offset"; + case DW_CFA_restore: return "DW_CFA_restore"; + case DW_CFA_set_loc: return "DW_CFA_set_loc"; + case DW_CFA_advance_loc1: return "DW_CFA_advance_loc1"; + case DW_CFA_advance_loc2: return "DW_CFA_advance_loc2"; + case DW_CFA_advance_loc4: return "DW_CFA_advance_loc4"; + case DW_CFA_offset_extended: return "DW_CFA_offset_extended"; + case DW_CFA_restore_extended: return "DW_CFA_restore_extended"; + case DW_CFA_undefined: return "DW_CFA_undefined"; + case DW_CFA_same_value: return "DW_CFA_same_value"; + case DW_CFA_register: return "DW_CFA_register"; + case DW_CFA_remember_state: return "DW_CFA_remember_state"; + case DW_CFA_restore_state: return "DW_CFA_restore_state"; + case DW_CFA_def_cfa: return "DW_CFA_def_cfa"; + case DW_CFA_def_cfa_register: return "DW_CFA_def_cfa_register"; + case DW_CFA_def_cfa_offset: return "DW_CFA_def_cfa_offset"; + case DW_CFA_def_cfa_expression: return "DW_CFA_def_cfa_expression"; + case DW_CFA_expression: return "DW_CFA_expression"; + case DW_CFA_offset_extended_sf: return "DW_CFA_offset_extended_sf"; + case DW_CFA_def_cfa_sf: return "DW_CFA_def_cfa_sf"; + case DW_CFA_def_cfa_offset_sf: return "DW_CFA_def_cfa_offset_sf"; + case DW_CFA_val_offset: return "DW_CFA_val_offset"; + case DW_CFA_val_offset_sf: return "DW_CFA_val_offset_sf"; + case DW_CFA_val_expression: return "DW_CFA_val_expression"; + case DW_CFA_lo_user: return "DW_CFA_lo_user"; + case DW_CFA_hi_user: return "DW_CFA_hi_user"; } return 0; } From wdietz2 at illinois.edu Wed Jun 16 20:33:57 2010 From: wdietz2 at illinois.edu (Will Dietz) Date: Thu, 17 Jun 2010 01:33:57 -0000 Subject: [llvm-commits] [poolalloc] r106198 - in /poolalloc/trunk/test/var_arg: basic.c multiple_callee.c Message-ID: <20100617013357.11A9D2A6C12C@llvm.org> Author: wdietz2 Date: Wed Jun 16 20:33:56 2010 New Revision: 106198 URL: http://llvm.org/viewvc/llvm-project?rev=106198&view=rev Log: var_arg test: ignore opt complaining about duplicate definitions to stderr multiple_callee: check the ds-aa results for correct mod/ref information Modified: poolalloc/trunk/test/var_arg/basic.c poolalloc/trunk/test/var_arg/multiple_callee.c Modified: poolalloc/trunk/test/var_arg/basic.c URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/var_arg/basic.c?rev=106198&r1=106197&r2=106198&view=diff ============================================================================== --- poolalloc/trunk/test/var_arg/basic.c (original) +++ poolalloc/trunk/test/var_arg/basic.c Wed Jun 16 20:33:56 2010 @@ -6,7 +6,7 @@ //RUN: llvm-gcc -O0 %s -S --emit-llvm -o - | llvm-as > %t.bc //--check if ds-aa breaks, breaks opts, or results in miscompiled code //RUN: lli %t.bc > %t.refout -//RUN: dsaopt %t.bc -ds-aa -O3 -o - | lli > %t.out +//RUN: dsaopt %t.bc -ds-aa -O3 -o - 2>/dev/null | lli > %t.out //RUN: diff %t.refout %t.out //--check properties of this particular test //N/A Modified: poolalloc/trunk/test/var_arg/multiple_callee.c URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/var_arg/multiple_callee.c?rev=106198&r1=106197&r2=106198&view=diff ============================================================================== --- poolalloc/trunk/test/var_arg/multiple_callee.c (original) +++ poolalloc/trunk/test/var_arg/multiple_callee.c Wed Jun 16 20:33:56 2010 @@ -11,10 +11,15 @@ //RUN: llvm-gcc -O0 %s -S --emit-llvm -o - | llvm-as > %t.bc //--check if ds-aa breaks, breaks opts, or results in miscompiled code //RUN: lli %t.bc > %t.refout -//RUN: dsaopt %t.bc -ds-aa -instcombine -ds-aa -gvn -ds-aa -dce -o - | lli > %t.out +//RUN: dsaopt %t.bc -ds-aa -instcombine -ds-aa -gvn -ds-aa -dce -o - 2>/dev/null | lli > %t.out //RUN: diff %t.refout %t.out //--check properties of this particular test -//N/A +//RUN: dsaopt %t.bc -ds-aa -aa-eval -print-all-alias-modref-info >& %t.aa +//ds-aa should tell us that assign modifies p1 +//RUN: cat %t.aa | grep {Ptr:.*p1.*@assign} | grep {^\[ \]*ModRef} +//ds-aa should tell us that assign does something to p2 +//RUN: cat %t.aa | grep {Ptr:.*p2.*@assign} | grep -v NoModRef + static int assign( int count, ... ) { From grosbach at apple.com Wed Jun 16 20:37:00 2010 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 17 Jun 2010 01:37:00 -0000 Subject: [llvm-commits] [llvm] r106199 - /llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Message-ID: <20100617013700.84B122A6C12C@llvm.org> Author: grosbach Date: Wed Jun 16 20:37:00 2010 New Revision: 106199 URL: http://llvm.org/viewvc/llvm-project?rev=106199&view=rev Log: simplify code a bit and add a more explanatory assert for cases that previously would result in 'cannot yet select' errors. Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=106199&r1=106198&r2=106199&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Jun 16 20:37:00 2010 @@ -1857,22 +1857,18 @@ const ARMSubtarget *Subtarget) { DebugLoc dl = Op.getDebugLoc(); SDValue Op5 = Op.getOperand(5); - SDValue Res; unsigned isDeviceBarrier = cast(Op5)->getZExtValue(); - if (isDeviceBarrier) { - if (Subtarget->hasV7Ops()) - Res = DAG.getNode(ARMISD::SYNCBARRIER, dl, MVT::Other, Op.getOperand(0)); - else - Res = DAG.getNode(ARMISD::SYNCBARRIER, dl, MVT::Other, Op.getOperand(0), - DAG.getConstant(0, MVT::i32)); - } else { - if (Subtarget->hasV7Ops()) - Res = DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); - else - Res = DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0), - DAG.getConstant(0, MVT::i32)); - } - return Res; + // v6 and v7 can both handle barriers directly, but need handled a bit + // differently. Thumb1 and pre-v6 ARM mode use a libcall instead and should + // never get here. + unsigned Opc = isDeviceBarrier ? ARMISD::SYNCBARRIER : ARMISD::MEMBARRIER; + if (Subtarget->hasV7Ops()) + return DAG.getNode(Opc, dl, MVT::Other, Op.getOperand(0)); + else if (Subtarget->hasV6Ops() && !Subtarget->isThumb1Only()) + return DAG.getNode(Opc, dl, MVT::Other, Op.getOperand(0), + DAG.getConstant(0, MVT::i32)); + assert(0 && "Unexpected ISD::MEMBARRIER encountered. Should be libcall!"); + return SDValue(); } static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) { From bruno.cardoso at gmail.com Wed Jun 16 20:50:40 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Thu, 17 Jun 2010 01:50:40 -0000 Subject: [llvm-commits] [llvm] r106201 - /llvm/trunk/utils/TableGen/Record.cpp Message-ID: <20100617015040.1C6E42A6C12C@llvm.org> Author: bruno Date: Wed Jun 16 20:50:39 2010 New Revision: 106201 URL: http://llvm.org/viewvc/llvm-project?rev=106201&view=rev Log: Fix the handling of !if result, avoiding null results for non 'int'. Modified: llvm/trunk/utils/TableGen/Record.cpp Modified: llvm/trunk/utils/TableGen/Record.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/Record.cpp?rev=106201&r1=106200&r2=106201&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/Record.cpp (original) +++ llvm/trunk/utils/TableGen/Record.cpp Wed Jun 16 20:50:39 2010 @@ -981,8 +981,9 @@ } case IF: { - IntInit *LHSi = - dynamic_cast(LHS->convertInitializerTo(new IntRecTy())); + IntInit *LHSi = dynamic_cast(LHS); + if (Init *I = LHS->convertInitializerTo(new IntRecTy())) + LHSi = dynamic_cast(I); if (LHSi) { if (LHSi->getValue()) { return MHS; @@ -1001,8 +1002,9 @@ Init *lhs = LHS->resolveReferences(R, RV); if (Opc == IF && lhs != LHS) { - IntInit *Value = - dynamic_cast(LHS->convertInitializerTo(new IntRecTy())); + IntInit *Value = dynamic_cast(lhs); + if (Init *I = lhs->convertInitializerTo(new IntRecTy())) + Value = dynamic_cast(I); if (Value != 0) { // Short-circuit if (Value->getValue()) { From grosbach at apple.com Wed Jun 16 21:00:54 2010 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 17 Jun 2010 02:00:54 -0000 Subject: [llvm-commits] [llvm] r106203 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <20100617020054.104862A6C12C@llvm.org> Author: grosbach Date: Wed Jun 16 21:00:53 2010 New Revision: 106203 URL: http://llvm.org/viewvc/llvm-project?rev=106203&view=rev Log: ISD::MEMBARRIER should lower to a libcall (__sync_synchronize) if the target sets the legalize action to Expand. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=106203&r1=106202&r2=106203&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Jun 16 21:00:53 2010 @@ -2359,10 +2359,22 @@ case ISD::EH_RETURN: case ISD::EH_LABEL: case ISD::PREFETCH: - case ISD::MEMBARRIER: case ISD::VAEND: Results.push_back(Node->getOperand(0)); break; + case ISD::MEMBARRIER: { + // If the target didn't lower this, lower it to '__sync_synchronize()' call + TargetLowering::ArgListTy Args; + std::pair CallResult = + TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()), + false, false, false, false, 0, CallingConv::C, false, + /*isReturnValueUsed=*/true, + DAG.getExternalSymbol("__sync_synchronize", + TLI.getPointerTy()), + Args, DAG, dl); + Results.push_back(CallResult.second); + break; + } case ISD::DYNAMIC_STACKALLOC: ExpandDYNAMIC_STACKALLOC(Node, Results); break; From grosbach at apple.com Wed Jun 16 21:02:03 2010 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 17 Jun 2010 02:02:03 -0000 Subject: [llvm-commits] [llvm] r106204 - /llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Message-ID: <20100617020203.43E7D2A6C12C@llvm.org> Author: grosbach Date: Wed Jun 16 21:02:03 2010 New Revision: 106204 URL: http://llvm.org/viewvc/llvm-project?rev=106204&view=rev Log: Thumb1 and any pre-v6 ARM target should use the libcall expansion of ISD::MEMBARRIER. v7 and v7 ARM mode continue to use the custom lowering. Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=106204&r1=106203&r2=106204&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Jun 16 21:02:03 2010 @@ -405,7 +405,12 @@ // doesn't yet know how to not do that for SjLj. setExceptionSelectorRegister(ARM::R0); setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); - setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom); + // Handle atomics directly for ARMv[67] (except for Thumb1), otherwise + // use the default expansion. + TargetLowering::LegalizeAction AtomicAction = + (Subtarget->hasV7Ops() || + (Subtarget->hasV6Ops() && !Subtarget->isThumb1Only())) ? Custom : Expand; + setOperationAction(ISD::MEMBARRIER, MVT::Other, AtomicAction); // If the subtarget does not have extract instructions, sign_extend_inreg // needs to be expanded. Extract is available in ARM mode on v6 and up, From natebegeman at mac.com Wed Jun 16 23:15:13 2010 From: natebegeman at mac.com (Nate Begeman) Date: Thu, 17 Jun 2010 04:15:13 -0000 Subject: [llvm-commits] [llvm] r106207 - in /llvm/trunk/utils/TableGen: NeonEmitter.cpp TableGen.cpp Message-ID: <20100617041513.AB3B32A6C12C@llvm.org> Author: sampo Date: Wed Jun 16 23:15:13 2010 New Revision: 106207 URL: http://llvm.org/viewvc/llvm-project?rev=106207&view=rev Log: Modify tablegen to support generating all NEON code used by clang at once. Modified: llvm/trunk/utils/TableGen/NeonEmitter.cpp llvm/trunk/utils/TableGen/TableGen.cpp Modified: llvm/trunk/utils/TableGen/NeonEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/NeonEmitter.cpp?rev=106207&r1=106206&r2=106207&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/NeonEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/NeonEmitter.cpp Wed Jun 16 23:15:13 2010 @@ -968,37 +968,66 @@ } } -/// runHeader - generate one of three different tables which are used by clang -/// to support ARM NEON codegen. By default, this will produce the contents of -/// BuiltinsARM.def's NEON section. You may also enable the genSemaTypes or -/// getSemaRange variables below to generate code that SemaChecking will use to -/// validate the builtin function calls. -/// -/// This is not used as part of the build system currently, but is run manually -/// and the output placed in the appropriate file. +/// runHeader - Emit a file with sections defining: +/// 1. the NEON section of BuiltinsARM.def. +/// 2. the SemaChecking code for the type overload checking. +/// 3. the SemaChecking code for validation of intrinsic immedate arguments. void NeonEmitter::runHeader(raw_ostream &OS) { std::vector RV = Records.getAllDerivedDefinitions("Inst"); StringMap EmittedMap; - // Set true to generate the overloaded type checking code for SemaChecking.cpp - bool genSemaTypes = false; - - // Set true to generate the intrinsic range checking code for shift/lane - // immediates for SemaChecking.cpp - bool genSemaRange = true; - + // Generate BuiltinsARM.def for NEON + OS << "#ifdef GET_NEON_BUILTINS\n"; for (unsigned i = 0, e = RV.size(); i != e; ++i) { Record *R = RV[i]; - OpKind k = OpMap[R->getValueAsDef("Operand")->getName()]; if (k != OpNone) continue; + + std::string Proto = R->getValueAsString("Prototype"); + + // Functions with 'a' (the splat code) in the type prototype should not get + // their own builtin as they use the non-splat variant. + if (Proto.find('a') != std::string::npos) + continue; + + std::string Types = R->getValueAsString("Types"); + SmallVector TypeVec; + ParseTypes(R, Types, TypeVec); + + if (R->getSuperClasses().size() < 2) + throw TGError(R->getLoc(), "Builtin has no class kind"); std::string name = LowercaseString(R->getName()); + ClassKind ck = ClassMap[R->getSuperClasses()[1]]; + + for (unsigned ti = 0, te = TypeVec.size(); ti != te; ++ti) { + // Generate the BuiltinsARM.def declaration for this builtin, ensuring + // that each unique BUILTIN() macro appears only once in the output + // stream. + std::string bd = GenBuiltinDef(name, Proto, TypeVec[ti], ck); + if (EmittedMap.count(bd)) + continue; + + EmittedMap[bd] = OpNone; + OS << bd << "\n"; + } + } + OS << "#endif\n\n"; + + // Generate the overloaded type checking code for SemaChecking.cpp + OS << "#ifdef GET_NEON_OVERLOAD_CHECK\n"; + for (unsigned i = 0, e = RV.size(); i != e; ++i) { + Record *R = RV[i]; + OpKind k = OpMap[R->getValueAsDef("Operand")->getName()]; + if (k != OpNone) + continue; + std::string Proto = R->getValueAsString("Prototype"); std::string Types = R->getValueAsString("Types"); - + std::string name = LowercaseString(R->getName()); + // Functions with 'a' (the splat code) in the type prototype should not get // their own builtin as they use the non-splat variant. if (Proto.find('a') != std::string::npos) @@ -1006,12 +1035,62 @@ // Functions which have a scalar argument cannot be overloaded, no need to // check them if we are emitting the type checking code. - if (genSemaTypes && Proto.find('s') != std::string::npos) + if (Proto.find('s') != std::string::npos) + continue; + + SmallVector TypeVec; + ParseTypes(R, Types, TypeVec); + + if (R->getSuperClasses().size() < 2) + throw TGError(R->getLoc(), "Builtin has no class kind"); + + int si = -1, qi = -1; + unsigned mask = 0, qmask = 0; + for (unsigned ti = 0, te = TypeVec.size(); ti != te; ++ti) { + // Generate the switch case(s) for this builtin for the type validation. + bool quad = false, poly = false, usgn = false; + (void) ClassifyType(TypeVec[ti], quad, poly, usgn); + + if (quad) { + qi = ti; + qmask |= 1 << GetNeonEnum(Proto, TypeVec[ti]); + } else { + si = ti; + mask |= 1 << GetNeonEnum(Proto, TypeVec[ti]); + } + } + if (mask) + OS << "case ARM::BI__builtin_neon_" + << MangleName(name, TypeVec[si], ClassB) + << ": mask = " << "0x" << utohexstr(mask) << "; break;\n"; + if (qmask) + OS << "case ARM::BI__builtin_neon_" + << MangleName(name, TypeVec[qi], ClassB) + << ": mask = " << "0x" << utohexstr(qmask) << "; break;\n"; + } + OS << "#endif\n\n"; + + // Generate the intrinsic range checking code for shift/lane immediates. + OS << "#ifdef GET_NEON_IMMEDIATE_CHECK\n"; + for (unsigned i = 0, e = RV.size(); i != e; ++i) { + Record *R = RV[i]; + + OpKind k = OpMap[R->getValueAsDef("Operand")->getName()]; + if (k != OpNone) + continue; + + std::string name = LowercaseString(R->getName()); + std::string Proto = R->getValueAsString("Prototype"); + std::string Types = R->getValueAsString("Types"); + + // Functions with 'a' (the splat code) in the type prototype should not get + // their own builtin as they use the non-splat variant. + if (Proto.find('a') != std::string::npos) continue; // Functions which do not have an immediate do not need to have range // checking code emitted. - if (genSemaRange && Proto.find('i') == std::string::npos) + if (Proto.find('i') == std::string::npos) continue; SmallVector TypeVec; @@ -1022,76 +1101,43 @@ ClassKind ck = ClassMap[R->getSuperClasses()[1]]; - int si = -1, qi = -1; - unsigned mask = 0, qmask = 0; for (unsigned ti = 0, te = TypeVec.size(); ti != te; ++ti) { + std::string namestr, shiftstr, rangestr; - // Generate the switch case(s) for this builtin for the type validation. - if (genSemaTypes) { - bool quad = false, poly = false, usgn = false; - (void) ClassifyType(TypeVec[ti], quad, poly, usgn); - - if (quad) { - qi = ti; - qmask |= 1 << GetNeonEnum(Proto, TypeVec[ti]); - } else { - si = ti; - mask |= 1 << GetNeonEnum(Proto, TypeVec[ti]); + // Builtins which are overloaded by type will need to have their upper + // bound computed at Sema time based on the type constant. + if (Proto.find('s') == std::string::npos) { + ck = ClassB; + if (R->getValueAsBit("isShift")) { + shiftstr = ", true"; + + // Right shifts have an 'r' in the name, left shifts do not. + if (name.find('r') != std::string::npos) + rangestr = "l = 1; "; } - continue; + rangestr += "u = RFT(TV" + shiftstr + ")"; + } else { + rangestr = "u = " + utostr(RangeFromType(TypeVec[ti])); } + // Make sure cases appear only once. + namestr = MangleName(name, TypeVec[ti], ck); + if (EmittedMap.count(namestr)) + continue; + EmittedMap[namestr] = OpNone; - if (genSemaRange) { - std::string namestr, shiftstr, rangestr; - - // Builtins which are overloaded by type will need to have their upper - // bound computed at Sema time based on the type constant. - if (Proto.find('s') == std::string::npos) { - ck = ClassB; - if (R->getValueAsBit("isShift")) { - shiftstr = ", true"; - - // Right shifts have an 'r' in the name, left shifts do not. - if (name.find('r') != std::string::npos) - rangestr = "l = 1; "; - } - rangestr += "u = RFT(TV" + shiftstr + ")"; - } else { - rangestr = "u = " + utostr(RangeFromType(TypeVec[ti])); + unsigned immidx = 0; + for (unsigned ii = 1, ie = Proto.size(); ii != ie; ++ii) { + switch (Proto[ii]) { + default: immidx += 1; break; + case '2': immidx += 2; break; + case '3': immidx += 3; break; + case '4': immidx += 4; break; + case 'i': ie = ii + 1; break; } - // Make sure cases appear only once. - namestr = MangleName(name, TypeVec[ti], ck); - if (EmittedMap.count(namestr)) - continue; - EmittedMap[namestr] = OpNone; - - OS << "case ARM::BI__builtin_neon_" - << MangleName(name, TypeVec[ti], ck) << ": i = " << Proto.find('i')-1 - << "; " << rangestr << "; break;\n"; - continue; } - - // Generate the BuiltinsARM.def declaration for this builtin, ensuring - // that each unique BUILTIN() macro appears only once in the output - // stream. - std::string bd = GenBuiltinDef(name, Proto, TypeVec[ti], ck); - if (EmittedMap.count(bd)) - continue; - - EmittedMap[bd] = OpNone; - OS << bd << "\n"; - } - - if (genSemaTypes) { - if (mask) - OS << "case ARM::BI__builtin_neon_" - << MangleName(name, TypeVec[si], ClassB) - << ": mask = " << "0x" << utohexstr(mask) << "; break;\n"; - if (qmask) - OS << "case ARM::BI__builtin_neon_" - << MangleName(name, TypeVec[qi], ClassB) - << ": mask = " << "0x" << utohexstr(qmask) << "; break;\n"; - continue; + OS << "case ARM::BI__builtin_neon_" << MangleName(name, TypeVec[ti], ck) + << ": i = " << immidx << "; " << rangestr << "; break;\n"; } } + OS << "#endif\n\n"; } Modified: llvm/trunk/utils/TableGen/TableGen.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TableGen.cpp?rev=106207&r1=106206&r2=106207&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/TableGen.cpp (original) +++ llvm/trunk/utils/TableGen/TableGen.cpp Wed Jun 16 23:15:13 2010 @@ -68,8 +68,8 @@ GenTgtIntrinsic, GenLLVMCConf, GenEDHeader, GenEDInfo, - GenNeonHeader, - GenNeonBuiltinsDef, + GenArmNeon, + GenArmNeonSema, PrintEnums }; @@ -132,10 +132,10 @@ "Generate enhanced disassembly info header"), clEnumValN(GenEDInfo, "gen-enhanced-disassembly-info", "Generate enhanced disassembly info"), - clEnumValN(GenNeonHeader, "gen-arm-neon-header", + clEnumValN(GenArmNeon, "gen-arm-neon", "Generate arm_neon.h for clang"), - clEnumValN(GenNeonBuiltinsDef, "gen-arm-neon-builtins-def", - "Generate NEON BuiltinsARM.def for clang"), + clEnumValN(GenArmNeonSema, "gen-arm-neon-sema", + "Generate ARM NEON sema support for clang"), clEnumValN(PrintEnums, "print-enums", "Print enum values for a class"), clEnumValEnd)); @@ -307,10 +307,10 @@ case GenEDInfo: EDEmitter(Records).run(Out); break; - case GenNeonHeader: + case GenArmNeon: NeonEmitter(Records).run(Out); break; - case GenNeonBuiltinsDef: + case GenArmNeonSema: NeonEmitter(Records).runHeader(Out); break; case PrintEnums: From deeppatel1987 at gmail.com Thu Jun 17 08:39:07 2010 From: deeppatel1987 at gmail.com (Sandeep Patel) Date: Thu, 17 Jun 2010 13:39:07 +0000 Subject: [llvm-commits] [patch] Update llvm-gcc to produce "" for the default calling convention on ARM In-Reply-To: References: <76A0798C-9AB8-43E8-99C1-7AFE618CEBEB@apple.com> Message-ID: On Wed, Jun 16, 2010 at 5:04 PM, Anton Korobeynikov wrote: >> An updated patch is attached. With it and a gcc configured for >> arm-none-linux-gnueabi I get: >> >> *) no -mabi -> "" >> *) -mabi=aapcs -> "" >> *) ?-mcpu=cortex-a8 ?-> arm_apcscc >> *) ?-mfloat-abi=hard ?-> arm_aapcs_vfpcc >> >> Is it OK? > Looks ok for me. If I read PR7357 correctly, then you're relying on the CC being "". That means you're really just disabling simplify-libcalls on an AAPCS-VFP platform. deep From espindola at google.com Thu Jun 17 09:01:02 2010 From: espindola at google.com (Rafael Espindola) Date: Thu, 17 Jun 2010 10:01:02 -0400 Subject: [llvm-commits] [patch] Update llvm-gcc to produce "" for the default calling convention on ARM In-Reply-To: References: <76A0798C-9AB8-43E8-99C1-7AFE618CEBEB@apple.com> Message-ID: > If I read PR7357 correctly, then you're relying on the CC being "". > That means you're really just disabling simplify-libcalls on an > AAPCS-VFP platform. In a AAPCS-VFP platform, when do we need to mark a function with arm_aapcs_vfpcc? The only difference is that floats are passed on the hard registers, right? So maybe the correct behavior is to just take this patch a bit further and have in a AAPCS-VFP platform: *) no -mabi or -mfloat-abi -> "" *) -mabi=aapcs -> "" *) -mabi=apcs-gnu -> arm_apcscc *) -mabi=aapcss -mfloat-abi=soft -> arm_aapcscc In other words, the default for a platform that uses AAPCS-VFP by default would be aapcs-vfp and you could just use "" as the calling convention for that. Note that right now the patch has disabled simplify libcalls for aapcs-vfp, but that is actually a bug fix, since it was producing code that had undefined behavior (calling a function with one CC using another). AAPCS platform had that bug, and we found it in the very real case of building SPEC. What platform uses AAPCS-VFP by default btw? > deep > Cheers, -- Rafael ?vila de Esp?ndola From asl at math.spbu.ru Thu Jun 17 09:09:04 2010 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Thu, 17 Jun 2010 18:09:04 +0400 Subject: [llvm-commits] [patch] Update llvm-gcc to produce "" for the default calling convention on ARM In-Reply-To: References: <76A0798C-9AB8-43E8-99C1-7AFE618CEBEB@apple.com> Message-ID: > What platform uses AAPCS-VFP by default btw? Every AAPCS platform using hard FP ABI. Note that libcalls on such a platform should use normal AAPCS CC (not VFP). -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From espindola at google.com Thu Jun 17 09:13:01 2010 From: espindola at google.com (Rafael Espindola) Date: Thu, 17 Jun 2010 10:13:01 -0400 Subject: [llvm-commits] [patch] Update llvm-gcc to produce "" for the default calling convention on ARM In-Reply-To: References: <76A0798C-9AB8-43E8-99C1-7AFE618CEBEB@apple.com> Message-ID: On 17 June 2010 10:09, Anton Korobeynikov wrote: >> What platform uses AAPCS-VFP by default btw? > Every AAPCS platform using hard FP ABI. Note that libcalls on such a > platform should use normal AAPCS CC (not VFP). Nice. So the real bug is probably in llvm-gcc marking those functions with aapcs_vfpcc (or at least I missed the special case for libcalls in the code....) Cheers, -- Rafael ?vila de Esp?ndola From criswell at cs.uiuc.edu Thu Jun 17 09:16:16 2010 From: criswell at cs.uiuc.edu (John Criswell) Date: Thu, 17 Jun 2010 09:16:16 -0500 Subject: [llvm-commits] CVS: llvm-www/safecode/menagerie/attacks.html index.html memsafety.html other.html Message-ID: <201006171416.o5HEGGH0000498@maute.cs.uiuc.edu> Changes in directory llvm-www/safecode/menagerie: attacks.html updated: 1.2 -> 1.3 index.html updated: 1.2 -> 1.3 memsafety.html updated: 1.3 -> 1.4 other.html updated: 1.2 -> 1.3 --- Log message: Added more papers. --- Diffs of the changes: (+93 -78) attacks.html | 54 +++++++++++++++++++++++------------------------------- index.html | 23 +---------------------- memsafety.html | 45 +++++++++++++++++++++++++++++++++++++++++++-- other.html | 49 ++++++++++++++++++++++++++----------------------- 4 files changed, 93 insertions(+), 78 deletions(-) Index: llvm-www/safecode/menagerie/attacks.html diff -u llvm-www/safecode/menagerie/attacks.html:1.2 llvm-www/safecode/menagerie/attacks.html:1.3 --- llvm-www/safecode/menagerie/attacks.html:1.2 Thu Jun 10 17:32:32 2010 +++ llvm-www/safecode/menagerie/attacks.html Thu Jun 17 09:15:41 2010 @@ -1,3 +1,4 @@ + @@ -59,61 +60,52 @@

Introduction

- Understand attacks that exploit the lack of memory safety in programs is + Know thy enemy. +

+ +

+ Understanding attacks that exploit the lack of memory safety in programs + is vital to understanding the different types of memory safety as well as the tradeoffs between enforcing one kind of memory safety over another. - Not all memory safety techniques are equally safe. + Not all memory safety techniques are created equal.

- Below are papers that describe how attacks exploit memory safety errors - for fun and profit. They're good to read; just don't make a career out - of using them. + Below are papers that describe how attacks exploit memory safety errors. + They're good to read; just make sure you use them for research and not + for fun and profit.

Memory Safety Exploit Papers

Index: llvm-www/safecode/menagerie/index.html diff -u llvm-www/safecode/menagerie/index.html:1.2 llvm-www/safecode/menagerie/index.html:1.3 --- llvm-www/safecode/menagerie/index.html:1.2 Thu Jun 10 17:32:32 2010 +++ llvm-www/safecode/menagerie/index.html Thu Jun 17 09:15:41 2010 @@ -82,30 +82,9 @@
  • - June 10, 2010: - New Paper by WhatsHisName was published in AGoodConference + June 9, 2010: Started creation of the menagerie.
- Index: llvm-www/safecode/menagerie/memsafety.html diff -u llvm-www/safecode/menagerie/memsafety.html:1.3 llvm-www/safecode/menagerie/memsafety.html:1.4 --- llvm-www/safecode/menagerie/memsafety.html:1.3 Thu Jun 10 23:32:43 2010 +++ llvm-www/safecode/menagerie/memsafety.html Thu Jun 17 09:15:41 2010 @@ -99,7 +99,6 @@
-
  • @@ -114,6 +113,20 @@
    +
  • + + + Securing Software by Enforcing Data-Flow Integrity + +
    + Miguel Castro, Manuel Costa, and Tim Harris +
    + Seventh USENIX Symposium on Operating Systems Design and + Implementation, November 2006. +
    • + +
    +
  • Efficiently Detecting All Dangling Pointer Uses in Production Servers @@ -121,7 +134,8 @@
    Dinakar Dhurjati and Vikram Adve.
    - International Conference on Dependable Systems and Networks (DSN), 2006 + International Conference on Dependable Systems and Networks (DSN), June + 2006

    • @@ -191,6 +205,19 @@
  • + + A Practical Dynamic Buffer Overflow Detector + +
    + Olatunji Ruwase and Monica S. Lam. +
    + Proceedings of the Network and Distributed System Security (NDSS) + Symposium, February 2004. +
    • + +
    + +
  • Memory Safety without Runtime Checks or Garbage Collection for Embedded Systems @@ -214,6 +241,20 @@ Internaltional Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), October 2002.
    • + +
    + +
  • + + Backwards-Compatible Bounds Checking for Arrays and Pointers in C + Programs + +
    + Richard W. M. Jones and Paul H. J. Kelly. +
    + Third International Workshop on Automated Debugging, May 1997. +
    • + Index: llvm-www/safecode/menagerie/other.html diff -u llvm-www/safecode/menagerie/other.html:1.2 llvm-www/safecode/menagerie/other.html:1.3 --- llvm-www/safecode/menagerie/other.html:1.2 Thu Jun 10 17:32:32 2010 +++ llvm-www/safecode/menagerie/other.html Thu Jun 17 09:15:41 2010 @@ -63,8 +63,8 @@ semantic behavior, it is not the only approach to thwarting such attacks. Information flow, randomization, and canaries have also been used to detect attacks against undefined C program behavior. A researcher in - memory safety should also be aware of these techniques and understand why - memory safety is a more comprehensive technique. + memory safety should also be aware of these techniques and understand the + tradeoffs between full memory safety and these other techniques.

    @@ -76,40 +76,43 @@

    Information Flow Papers

    + + +

    Randomization Papers

    + + +

    Miscellaneous Papers

    + +     - - -

    Randomization Papers

    - - -

    Ad Hoc Technique Papers

    + From visa.putkinen at cs.hut.fi Thu Jun 17 09:17:37 2010 From: visa.putkinen at cs.hut.fi (Visa Putkinen) Date: Thu, 17 Jun 2010 17:17:37 +0300 Subject: [llvm-commits] [llvm] r106038 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp test/CodeGen/Generic/v-binop-widen.ll test/CodeGen/Generic/v-binop-widen2.ll In-Reply-To: <8BB70DCD-CA07-4568-BCCD-0BCD6CE38F04@2pi.dk> References: <20100615202905.4C9A42A6C12C@llvm.org> <86890B00-CE41-41F8-AC07-EF87AAA2CC41@apple.com> <8BB70DCD-CA07-4568-BCCD-0BCD6CE38F04@2pi.dk> Message-ID: <20100617141737.GA10744@hutcs.cs.hut.fi> On Wed, Jun 16, 2010 at 02:16:50PM -0700, Jakob Stoklund Olesen wrote: > On Jun 16, 2010, at 2:09 PM, Jim Grosbach wrote: > > I changed the test to use "< %s" in r106146 so it'll stop polluting the test source directoy. I don't know what FileCheck entries should also be there, though. Thanks, Jim. I'll use "< %s" in the future. > Many tests pass simply by not crashing llc. I am guessing that is the case here. That is indeed the case here. > If the test case can crash llc without needing fancy options, multiple tests can be collected in one file, see test/CodeGen/X86/crash.ll. Good to know. In that case v-binop-widen.ll should be moved into a crash.ll (or be removed altogether). The test was supposed to demo a crash in X86 target caused by a bug in common CodeGen code. So should such tests be under test/CodeGen/X86 or test/CodeGen/Generic? - Visa From stoklund at 2pi.dk Thu Jun 17 09:25:05 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 17 Jun 2010 07:25:05 -0700 Subject: [llvm-commits] [llvm] r106038 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp test/CodeGen/Generic/v-binop-widen.ll test/CodeGen/Generic/v-binop-widen2.ll In-Reply-To: <20100617141737.GA10744@hutcs.cs.hut.fi> References: <20100615202905.4C9A42A6C12C@llvm.org> <86890B00-CE41-41F8-AC07-EF87AAA2CC41@apple.com> <8BB70DCD-CA07-4568-BCCD-0BCD6CE38F04@2pi.dk> <20100617141737.GA10744@hutcs.cs.hut.fi> Message-ID: On Jun 17, 2010, at 7:17 AM, Visa Putkinen wrote: > On Wed, Jun 16, 2010 at 02:16:50PM -0700, Jakob Stoklund Olesen wrote: >> On Jun 16, 2010, at 2:09 PM, Jim Grosbach wrote: >>> I changed the test to use "< %s" in r106146 so it'll stop polluting the test source directoy. I don't know what FileCheck entries should also be there, though. > > Thanks, Jim. I'll use "< %s" in the future. > >> Many tests pass simply by not crashing llc. I am guessing that is the case here. > > That is indeed the case here. > >> If the test case can crash llc without needing fancy options, multiple tests can be collected in one file, see test/CodeGen/X86/crash.ll. > > Good to know. In that case v-binop-widen.ll should be moved into a > crash.ll (or be removed altogether). The test was supposed to demo a > crash in X86 target caused by a bug in common CodeGen code. So should > such tests be under test/CodeGen/X86 or test/CodeGen/Generic? If it requires the X86 target, it should go in the X86 directory. The X86 target may not be present when running the Generic tests. -------------- next part -------------- A non-text attachment was scrubbed... Name: smime.p7s Type: application/pkcs7-signature Size: 1929 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100617/4eba55b1/attachment.bin From criswell at cs.uiuc.edu Thu Jun 17 09:46:33 2010 From: criswell at cs.uiuc.edu (John Criswell) Date: Thu, 17 Jun 2010 09:46:33 -0500 Subject: [llvm-commits] CVS: llvm-www/safecode/menagerie/other.html Message-ID: <201006171446.o5HEkXkh001816@maute.cs.uiuc.edu> Changes in directory llvm-www/safecode/menagerie: other.html updated: 1.3 -> 1.4 --- Log message: Replaced tabs with spaces. Added randomization papers. --- Diffs of the changes: (+86 -43) other.html | 129 ++++++++++++++++++++++++++++++++++++++++--------------------- 1 file changed, 86 insertions(+), 43 deletions(-) Index: llvm-www/safecode/menagerie/other.html diff -u llvm-www/safecode/menagerie/other.html:1.3 llvm-www/safecode/menagerie/other.html:1.4 --- llvm-www/safecode/menagerie/other.html:1.3 Thu Jun 17 09:15:41 2010 +++ llvm-www/safecode/menagerie/other.html Thu Jun 17 09:46:21 2010 @@ -21,42 +21,42 @@
    - -
    - + From dgregor at apple.com Thu Jun 17 10:17:07 2010 From: dgregor at apple.com (Douglas Gregor) Date: Thu, 17 Jun 2010 15:17:07 -0000 Subject: [llvm-commits] [llvm] r106219 - /llvm/trunk/cmake/modules/TableGen.cmake Message-ID: <20100617151707.B16E12A6C12C@llvm.org> Author: dgregor Date: Thu Jun 17 10:17:07 2010 New Revision: 106219 URL: http://llvm.org/viewvc/llvm-project?rev=106219&view=rev Log: Allow absolute paths in LLVM_TARGET_DEFINITIONS for CMake's TableGen rule Modified: llvm/trunk/cmake/modules/TableGen.cmake Modified: llvm/trunk/cmake/modules/TableGen.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/TableGen.cmake?rev=106219&r1=106218&r2=106219&view=diff ============================================================================== --- llvm/trunk/cmake/modules/TableGen.cmake (original) +++ llvm/trunk/cmake/modules/TableGen.cmake Thu Jun 17 10:17:07 2010 @@ -6,10 +6,16 @@ file(GLOB local_tds "*.td") file(GLOB_RECURSE global_tds "${LLVM_MAIN_SRC_DIR}/include/llvm/*.td") + if (IS_ABSOLUTE ${LLVM_TARGET_DEFINITIONS}) + set(LLVM_TARGET_DEFINITIONS_ABSOLUTE ${LLVM_TARGET_DEFINITIONS}) + else() + set(LLVM_TARGET_DEFINITIONS_ABSOLUTE + ${CMAKE_CURRENT_SOURCE_DIR}/${LLVM_TARGET_DEFINITIONS}) + endif() add_custom_command(OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${ofn} COMMAND ${LLVM_TABLEGEN_EXE} ${ARGN} -I ${CMAKE_CURRENT_SOURCE_DIR} -I ${LLVM_MAIN_SRC_DIR}/lib/Target -I ${LLVM_MAIN_INCLUDE_DIR} - ${CMAKE_CURRENT_SOURCE_DIR}/${LLVM_TARGET_DEFINITIONS} + ${LLVM_TARGET_DEFINITIONS_ABSOLUTE} -o ${CMAKE_CURRENT_BINARY_DIR}/${ofn} DEPENDS tblgen ${local_tds} ${global_tds} COMMENT "Building ${ofn}..." From rafael.espindola at gmail.com Thu Jun 17 10:18:27 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 17 Jun 2010 15:18:27 -0000 Subject: [llvm-commits] [llvm] r106221 - in /llvm/trunk/test: CodeGen/ARM/ CodeGen/Generic/ CodeGen/Thumb/ CodeGen/Thumb2/ Transforms/GVN/ Transforms/IndVarSimplify/ Transforms/InstCombine/ Transforms/LoopUnswitch/ Transforms/ScalarRepl/ Message-ID: <20100617151828.A1EF32A6C12C@llvm.org> Author: rafael Date: Thu Jun 17 10:18:27 2010 New Revision: 106221 URL: http://llvm.org/viewvc/llvm-project?rev=106221&view=rev Log: Remove arm_apcscc from the test files. It is the default and doing this matches what llvm-gcc and clang now produce. Modified: llvm/trunk/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll llvm/trunk/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll llvm/trunk/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll llvm/trunk/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll llvm/trunk/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll llvm/trunk/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll llvm/trunk/test/CodeGen/ARM/2009-07-01-CommuteBug.ll llvm/trunk/test/CodeGen/ARM/2009-07-18-RewriterBug.ll llvm/trunk/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll llvm/trunk/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll llvm/trunk/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll llvm/trunk/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill.ll llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll llvm/trunk/test/CodeGen/ARM/2009-08-26-ScalarToVector.ll llvm/trunk/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll llvm/trunk/test/CodeGen/ARM/2009-08-29-ExtractEltf32.ll llvm/trunk/test/CodeGen/ARM/2009-08-29-TooLongSplat.ll llvm/trunk/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll llvm/trunk/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll llvm/trunk/test/CodeGen/ARM/2009-09-09-AllOnes.ll llvm/trunk/test/CodeGen/ARM/2009-09-24-spill-align.ll llvm/trunk/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll llvm/trunk/test/CodeGen/ARM/2010-04-09-NeonSelect.ll llvm/trunk/test/CodeGen/ARM/2010-04-13-v2f64SplitArg.ll llvm/trunk/test/CodeGen/ARM/2010-04-14-SplitVector.ll llvm/trunk/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll llvm/trunk/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll llvm/trunk/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll llvm/trunk/test/CodeGen/ARM/2010-05-21-BuildVector.ll llvm/trunk/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll llvm/trunk/test/CodeGen/ARM/arm-returnaddr.ll llvm/trunk/test/CodeGen/ARM/fpconsts.ll llvm/trunk/test/CodeGen/ARM/indirectbr.ll llvm/trunk/test/CodeGen/ARM/inlineasm3.ll llvm/trunk/test/CodeGen/ARM/lsr-on-unrolled-loops.ll llvm/trunk/test/CodeGen/ARM/reg_sequence.ll llvm/trunk/test/CodeGen/ARM/remat.ll llvm/trunk/test/CodeGen/ARM/select-imm.ll llvm/trunk/test/CodeGen/ARM/spill-q.ll llvm/trunk/test/CodeGen/ARM/trap.ll llvm/trunk/test/CodeGen/ARM/unaligned_load_store.ll llvm/trunk/test/CodeGen/ARM/vdup.ll llvm/trunk/test/CodeGen/ARM/vext.ll llvm/trunk/test/CodeGen/ARM/vmov.ll llvm/trunk/test/CodeGen/ARM/vrev.ll llvm/trunk/test/CodeGen/Generic/2010-ZeroSizedArg.ll llvm/trunk/test/CodeGen/Thumb/2009-07-19-SPDecBug.ll llvm/trunk/test/CodeGen/Thumb/2009-07-20-TwoAddrBug.ll llvm/trunk/test/CodeGen/Thumb/2009-07-27-PEIAssert.ll llvm/trunk/test/CodeGen/Thumb/2009-08-12-ConstIslandAssert.ll llvm/trunk/test/CodeGen/Thumb/2009-08-12-RegInfoAssert.ll llvm/trunk/test/CodeGen/Thumb/2009-08-20-ISelBug.ll llvm/trunk/test/CodeGen/Thumb/2009-12-17-pre-regalloc-taildup.ll llvm/trunk/test/CodeGen/Thumb/2010-01-15-local-alloc-spill-physical.ll llvm/trunk/test/CodeGen/Thumb/asmprinter-bug.ll llvm/trunk/test/CodeGen/Thumb/machine-licm.ll llvm/trunk/test/CodeGen/Thumb/pop.ll llvm/trunk/test/CodeGen/Thumb/push.ll llvm/trunk/test/CodeGen/Thumb/trap.ll llvm/trunk/test/CodeGen/Thumb2/2009-07-17-CrossRegClassCopy.ll llvm/trunk/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll llvm/trunk/test/CodeGen/Thumb2/2009-07-23-CPIslandBug.ll llvm/trunk/test/CodeGen/Thumb2/2009-07-30-PEICrash.ll llvm/trunk/test/CodeGen/Thumb2/2009-08-01-WrongLDRBOpc.ll llvm/trunk/test/CodeGen/Thumb2/2009-08-02-CoalescerBug.ll llvm/trunk/test/CodeGen/Thumb2/2009-08-04-CoalescerBug.ll llvm/trunk/test/CodeGen/Thumb2/2009-08-04-ScavengerAssert.ll llvm/trunk/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll llvm/trunk/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug2.ll llvm/trunk/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug3.ll llvm/trunk/test/CodeGen/Thumb2/2009-08-07-NeonFPBug.ll llvm/trunk/test/CodeGen/Thumb2/2009-08-10-ISelBug.ll llvm/trunk/test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll llvm/trunk/test/CodeGen/Thumb2/2009-11-01-CopyReg2RegBug.ll llvm/trunk/test/CodeGen/Thumb2/2009-11-11-ScavengerAssert.ll llvm/trunk/test/CodeGen/Thumb2/2009-11-13-STRDBug.ll llvm/trunk/test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll llvm/trunk/test/CodeGen/Thumb2/2010-01-06-TailDuplicateLabels.ll llvm/trunk/test/CodeGen/Thumb2/2010-01-19-RemovePredicates.ll llvm/trunk/test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll llvm/trunk/test/CodeGen/Thumb2/2010-02-24-BigStack.ll llvm/trunk/test/CodeGen/Thumb2/2010-03-08-addi12-ccout.ll llvm/trunk/test/CodeGen/Thumb2/2010-03-15-AsmCCClobber.ll llvm/trunk/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll llvm/trunk/test/CodeGen/Thumb2/2010-04-26-CopyRegCrash.ll llvm/trunk/test/CodeGen/Thumb2/2010-05-24-rsbs.ll llvm/trunk/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll llvm/trunk/test/CodeGen/Thumb2/cross-rc-coalescing-1.ll llvm/trunk/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll llvm/trunk/test/CodeGen/Thumb2/frameless.ll llvm/trunk/test/CodeGen/Thumb2/frameless2.ll llvm/trunk/test/CodeGen/Thumb2/ifcvt-neon.ll llvm/trunk/test/CodeGen/Thumb2/ldr-str-imm12.ll llvm/trunk/test/CodeGen/Thumb2/lsr-deficiency.ll llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll llvm/trunk/test/CodeGen/Thumb2/pic-load.ll llvm/trunk/test/CodeGen/Thumb2/sign_extend_inreg.ll llvm/trunk/test/CodeGen/Thumb2/thumb2-cbnz.ll llvm/trunk/test/CodeGen/Thumb2/thumb2-spill-q.ll llvm/trunk/test/CodeGen/Thumb2/thumb2-tbh.ll llvm/trunk/test/Transforms/GVN/load-pre-align.ll llvm/trunk/test/Transforms/IndVarSimplify/single-element-range.ll llvm/trunk/test/Transforms/InstCombine/call.ll llvm/trunk/test/Transforms/InstCombine/crash.ll llvm/trunk/test/Transforms/LoopUnswitch/preserve-analyses.ll llvm/trunk/test/Transforms/ScalarRepl/2009-12-11-NeonTypes.ll llvm/trunk/test/Transforms/ScalarRepl/2010-01-18-SelfCopy.ll Modified: llvm/trunk/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll Thu Jun 17 10:18:27 2010 @@ -3,7 +3,7 @@ %struct.rtunion = type { i64 } %struct.rtx_def = type { i16, i8, i8, [1 x %struct.rtunion] } -define arm_apcscc void @simplify_unary_real(i8* nocapture %p) nounwind { +define void @simplify_unary_real(i8* nocapture %p) nounwind { entry: %tmp121 = load i64* null, align 4 ; [#uses=1] %0 = getelementptr %struct.rtx_def* null, i32 0, i32 3, i32 3, i32 0 ; [#uses=1] Modified: llvm/trunk/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll Thu Jun 17 10:18:27 2010 @@ -8,11 +8,11 @@ @"\01LC16" = external constant [33 x i8], align 1 ; <[33 x i8]*> [#uses=1] @"\01LC17" = external constant [47 x i8], align 1 ; <[47 x i8]*> [#uses=1] -declare arm_apcscc i32 @printf(i8* nocapture, ...) nounwind +declare i32 @printf(i8* nocapture, ...) nounwind -declare arm_apcscc void @diff(i8*, i8*, i32, i32, i32, i32) nounwind +declare void @diff(i8*, i8*, i32, i32, i32, i32) nounwind -define arm_apcscc void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { entry: br i1 undef, label %bb5, label %bb @@ -44,17 +44,17 @@ store i32 0, i32* @no_mat, align 4 store i32 0, i32* @no_mis, align 4 %3 = getelementptr i8* %B, i32 %0 ; [#uses=1] - tail call arm_apcscc void @diff(i8* undef, i8* %3, i32 undef, i32 undef, i32 undef, i32 undef) nounwind + tail call void @diff(i8* undef, i8* %3, i32 undef, i32 undef, i32 undef, i32 undef) nounwind %4 = sitofp i32 undef to double ; [#uses=1] %5 = fdiv double %4, 1.000000e+01 ; [#uses=1] - %6 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([29 x i8]* @"\01LC12", i32 0, i32 0), double %5) nounwind ; [#uses=0] + %6 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([29 x i8]* @"\01LC12", i32 0, i32 0), double %5) nounwind ; [#uses=0] %7 = load i32* @al_len, align 4 ; [#uses=1] %8 = load i32* @no_mat, align 4 ; [#uses=1] %9 = load i32* @no_mis, align 4 ; [#uses=1] %10 = sub i32 %7, %8 ; [#uses=1] %11 = sub i32 %10, %9 ; [#uses=1] - %12 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC16", i32 0, i32 0), i32 %11) nounwind ; [#uses=0] - %13 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([47 x i8]* @"\01LC17", i32 0, i32 0), i32 undef, i32 %1, i32 undef, i32 undef) nounwind ; [#uses=0] + %12 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC16", i32 0, i32 0), i32 %11) nounwind ; [#uses=0] + %13 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([47 x i8]* @"\01LC17", i32 0, i32 0), i32 undef, i32 %1, i32 undef, i32 undef) nounwind ; [#uses=0] br i1 undef, label %bb15, label %bb12 bb12: ; preds = %bb11 Modified: llvm/trunk/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll Thu Jun 17 10:18:27 2010 @@ -6,11 +6,11 @@ @"\01LC15" = external constant [33 x i8], align 1 ; <[33 x i8]*> [#uses=1] @"\01LC17" = external constant [47 x i8], align 1 ; <[47 x i8]*> [#uses=1] -declare arm_apcscc i32 @printf(i8* nocapture, ...) nounwind +declare i32 @printf(i8* nocapture, ...) nounwind -declare arm_apcscc void @diff(i8*, i8*, i32, i32, i32, i32) nounwind +declare void @diff(i8*, i8*, i32, i32, i32, i32) nounwind -define arm_apcscc void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { entry: br i1 undef, label %bb5, label %bb @@ -41,11 +41,11 @@ store i32 0, i32* @no_mat, align 4 store i32 0, i32* @no_mis, align 4 %4 = getelementptr i8* %B, i32 %0 ; [#uses=1] - tail call arm_apcscc void @diff(i8* undef, i8* %4, i32 undef, i32 %3, i32 undef, i32 undef) nounwind - %5 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC11", i32 0, i32 0), i32 %tmp13) nounwind ; [#uses=0] + tail call void @diff(i8* undef, i8* %4, i32 undef, i32 %3, i32 undef, i32 undef) nounwind + %5 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC11", i32 0, i32 0), i32 %tmp13) nounwind ; [#uses=0] %6 = load i32* @no_mis, align 4 ; [#uses=1] - %7 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC15", i32 0, i32 0), i32 %6) nounwind ; [#uses=0] - %8 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([47 x i8]* @"\01LC17", i32 0, i32 0), i32 undef, i32 %1, i32 undef, i32 %2) nounwind ; [#uses=0] + %7 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC15", i32 0, i32 0), i32 %6) nounwind ; [#uses=0] + %8 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([47 x i8]* @"\01LC17", i32 0, i32 0), i32 undef, i32 %1, i32 undef, i32 %2) nounwind ; [#uses=0] br i1 undef, label %bb15, label %bb12 bb12: ; preds = %bb11 Modified: llvm/trunk/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll Thu Jun 17 10:18:27 2010 @@ -2,7 +2,7 @@ @JJ = external global i32* ; [#uses=1] -define arm_apcscc void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { entry: br i1 undef, label %bb5, label %bb Modified: llvm/trunk/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll Thu Jun 17 10:18:27 2010 @@ -6,9 +6,9 @@ @no_mis = external global i32 ; [#uses=1] @name1 = external global i8* ; [#uses=1] -declare arm_apcscc void @diff(i8*, i8*, i32, i32, i32, i32) nounwind +declare void @diff(i8*, i8*, i32, i32, i32, i32) nounwind -define arm_apcscc void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { entry: br i1 undef, label %bb5, label %bb @@ -35,7 +35,7 @@ store i32 0, i32* @no_mis, align 4 %1 = getelementptr i8* %A, i32 0 ; [#uses=1] %2 = getelementptr i8* %B, i32 0 ; [#uses=1] - tail call arm_apcscc void @diff(i8* %1, i8* %2, i32 undef, i32 undef, i32 undef, i32 undef) nounwind + tail call void @diff(i8* %1, i8* %2, i32 undef, i32 undef, i32 undef, i32 undef) nounwind br i1 undef, label %bb15, label %bb12 bb12: ; preds = %bb11 Modified: llvm/trunk/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll Thu Jun 17 10:18:27 2010 @@ -2,7 +2,7 @@ @XX = external global i32* ; [#uses=1] -define arm_apcscc void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { entry: br i1 undef, label %bb5, label %bb Modified: llvm/trunk/test/CodeGen/ARM/2009-07-01-CommuteBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-07-01-CommuteBug.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-07-01-CommuteBug.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2009-07-01-CommuteBug.ll Thu Jun 17 10:18:27 2010 @@ -4,7 +4,7 @@ @II = external global i32* ; [#uses=1] @JJ = external global i32* ; [#uses=1] -define arm_apcscc void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { entry: br i1 undef, label %bb5, label %bb Modified: llvm/trunk/test/CodeGen/ARM/2009-07-18-RewriterBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-07-18-RewriterBug.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-07-18-RewriterBug.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2009-07-18-RewriterBug.ll Thu Jun 17 10:18:27 2010 @@ -8,7 +8,7 @@ @_2E_str7 = internal constant [21 x i8] c"ERROR: Only 1 point!\00", section "__TEXT,__cstring,cstring_literals", align 1 ; <[21 x i8]*> [#uses=1] @llvm.used = appending global [1 x i8*] [i8* bitcast (void (%struct.EDGE_PAIR*, %struct.VERTEX*, %struct.VERTEX*)* @build_delaunay to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] -define arm_apcscc void @build_delaunay(%struct.EDGE_PAIR* noalias nocapture sret %agg.result, %struct.VERTEX* %tree, %struct.VERTEX* %extra) nounwind { +define void @build_delaunay(%struct.EDGE_PAIR* noalias nocapture sret %agg.result, %struct.VERTEX* %tree, %struct.VERTEX* %extra) nounwind { entry: %delright = alloca %struct.EDGE_PAIR, align 8 ; <%struct.EDGE_PAIR*> [#uses=3] %delleft = alloca %struct.EDGE_PAIR, align 8 ; <%struct.EDGE_PAIR*> [#uses=3] @@ -29,10 +29,10 @@ br i1 %6, label %get_low.exit, label %bb1.i get_low.exit: ; preds = %bb1.i - call arm_apcscc void @build_delaunay(%struct.EDGE_PAIR* noalias sret %delright, %struct.VERTEX* %2, %struct.VERTEX* %extra) nounwind + call void @build_delaunay(%struct.EDGE_PAIR* noalias sret %delright, %struct.VERTEX* %2, %struct.VERTEX* %extra) nounwind %7 = getelementptr %struct.VERTEX* %tree, i32 0, i32 1 ; <%struct.VERTEX**> [#uses=1] %8 = load %struct.VERTEX** %7, align 4 ; <%struct.VERTEX*> [#uses=1] - call arm_apcscc void @build_delaunay(%struct.EDGE_PAIR* noalias sret %delleft, %struct.VERTEX* %8, %struct.VERTEX* %tree) nounwind + call void @build_delaunay(%struct.EDGE_PAIR* noalias sret %delleft, %struct.VERTEX* %8, %struct.VERTEX* %tree) nounwind %9 = getelementptr %struct.EDGE_PAIR* %delleft, i32 0, i32 0 ; <%struct.edge_rec**> [#uses=1] %10 = load %struct.edge_rec** %9, align 8 ; <%struct.edge_rec*> [#uses=2] %11 = getelementptr %struct.EDGE_PAIR* %delleft, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] @@ -141,7 +141,7 @@ %85 = inttoptr i32 %84 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %86 = getelementptr %struct.edge_rec* %ldi_addr.0.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] %87 = load %struct.VERTEX** %86, align 4 ; <%struct.VERTEX*> [#uses=1] - %88 = call arm_apcscc %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=6] + %88 = call %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=6] %89 = getelementptr %struct.edge_rec* %88, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=4] store %struct.edge_rec* %88, %struct.edge_rec** %89, align 4 %90 = getelementptr %struct.edge_rec* %88, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=2] @@ -780,7 +780,7 @@ %592 = and i32 %589, -64 ; [#uses=1] %593 = or i32 %591, %592 ; [#uses=1] %594 = inttoptr i32 %593 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %595 = call arm_apcscc %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=5] + %595 = call %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=5] %596 = getelementptr %struct.edge_rec* %595, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=4] store %struct.edge_rec* %595, %struct.edge_rec** %596, align 4 %597 = getelementptr %struct.edge_rec* %595, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] @@ -882,7 +882,7 @@ %677 = and i32 %674, -64 ; [#uses=1] %678 = or i32 %676, %677 ; [#uses=1] %679 = inttoptr i32 %678 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %680 = call arm_apcscc %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=4] + %680 = call %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=4] %681 = getelementptr %struct.edge_rec* %680, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=5] store %struct.edge_rec* %680, %struct.edge_rec** %681, align 4 %682 = getelementptr %struct.edge_rec* %680, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] @@ -1005,15 +1005,15 @@ %762 = getelementptr %struct.VERTEX* %tree, i32 0, i32 1 ; <%struct.VERTEX**> [#uses=1] %763 = load %struct.VERTEX** %762, align 4 ; <%struct.VERTEX*> [#uses=4] %764 = icmp eq %struct.VERTEX* %763, null ; [#uses=1] - %765 = call arm_apcscc %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=5] + %765 = call %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=5] %766 = getelementptr %struct.edge_rec* %765, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=4] store %struct.edge_rec* %765, %struct.edge_rec** %766, align 4 %767 = getelementptr %struct.edge_rec* %765, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=3] br i1 %764, label %bb10, label %bb11 bb8: ; preds = %entry - %768 = call arm_apcscc i32 @puts(i8* getelementptr ([21 x i8]* @_2E_str7, i32 0, i32 0)) nounwind ; [#uses=0] - call arm_apcscc void @exit(i32 -1) noreturn nounwind + %768 = call i32 @puts(i8* getelementptr ([21 x i8]* @_2E_str7, i32 0, i32 0)) nounwind ; [#uses=0] + call void @exit(i32 -1) noreturn nounwind unreachable bb10: ; preds = %bb7 @@ -1053,7 +1053,7 @@ store %struct.VERTEX* %tree, %struct.VERTEX** %790, align 4 %791 = getelementptr %struct.edge_rec* %785, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] store %struct.edge_rec* %783, %struct.edge_rec** %791, align 4 - %792 = call arm_apcscc %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=4] + %792 = call %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=4] %793 = getelementptr %struct.edge_rec* %792, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=4] store %struct.edge_rec* %792, %struct.edge_rec** %793, align 4 %794 = getelementptr %struct.edge_rec* %792, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] @@ -1117,7 +1117,7 @@ %843 = or i32 %841, %842 ; [#uses=1] %844 = inttoptr i32 %843 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %845 = load %struct.VERTEX** %767, align 4 ; <%struct.VERTEX*> [#uses=1] - %846 = call arm_apcscc %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=4] + %846 = call %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=4] %847 = getelementptr %struct.edge_rec* %846, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=7] store %struct.edge_rec* %846, %struct.edge_rec** %847, align 4 %848 = getelementptr %struct.edge_rec* %846, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] @@ -1316,8 +1316,8 @@ ret void } -declare arm_apcscc i32 @puts(i8* nocapture) nounwind +declare i32 @puts(i8* nocapture) nounwind -declare arm_apcscc void @exit(i32) noreturn nounwind +declare void @exit(i32) noreturn nounwind -declare arm_apcscc %struct.edge_rec* @alloc_edge() nounwind +declare %struct.edge_rec* @alloc_edge() nounwind Modified: llvm/trunk/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll Thu Jun 17 10:18:27 2010 @@ -6,9 +6,9 @@ %struct.cli_bm_patt = type { i8*, i8*, i16, i16, i8*, i8*, i8, %struct.cli_bm_patt*, i16 } %struct.cli_matcher = type { i16, i8, i8*, %struct.cli_bm_patt**, i32*, i32, i8, i8, %struct.cli_ac_node*, %struct.cli_ac_node**, %struct.cli_ac_patt**, i32, i32, i32 } -declare arm_apcscc i32 @strlen(i8* nocapture) nounwind readonly +declare i32 @strlen(i8* nocapture) nounwind readonly -define arm_apcscc i32 @cli_ac_addsig(%struct.cli_matcher* nocapture %root, i8* %virname, i8* %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, i8* %offset, i8 zeroext %target) nounwind { +define i32 @cli_ac_addsig(%struct.cli_matcher* nocapture %root, i8* %virname, i8* %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, i8* %offset, i8 zeroext %target) nounwind { entry: br i1 undef, label %bb126, label %bb1 @@ -86,7 +86,7 @@ %0 = load i16* undef, align 4 ; [#uses=1] %1 = icmp eq i16 %0, 0 ; [#uses=1] %iftmp.20.0 = select i1 %1, i8* %hexsig, i8* null ; [#uses=1] - %2 = tail call arm_apcscc i32 @strlen(i8* %iftmp.20.0) nounwind readonly ; [#uses=0] + %2 = tail call i32 @strlen(i8* %iftmp.20.0) nounwind readonly ; [#uses=0] unreachable bb126: ; preds = %entry Modified: llvm/trunk/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll Thu Jun 17 10:18:27 2010 @@ -6,7 +6,7 @@ %struct.cli_bm_patt = type { i8*, i8*, i16, i16, i8*, i8*, i8, %struct.cli_bm_patt*, i16 } %struct.cli_matcher = type { i16, i8, i8*, %struct.cli_bm_patt**, i32*, i32, i8, i8, %struct.cli_ac_node*, %struct.cli_ac_node**, %struct.cli_ac_patt**, i32, i32, i32 } -define arm_apcscc i32 @cli_ac_addsig(%struct.cli_matcher* nocapture %root, i8* %virname, i8* %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, i8* %offset, i8 zeroext %target) nounwind { +define i32 @cli_ac_addsig(%struct.cli_matcher* nocapture %root, i8* %virname, i8* %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, i8* %offset, i8 zeroext %target) nounwind { entry: br i1 undef, label %bb126, label %bb1 Modified: llvm/trunk/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll Thu Jun 17 10:18:27 2010 @@ -4,7 +4,7 @@ declare double @llvm.exp.f64(double) nounwind readonly -define arm_apcscc void @findratio(double* nocapture %res1, double* nocapture %res2) nounwind { +define void @findratio(double* nocapture %res1, double* nocapture %res2) nounwind { entry: br label %bb Modified: llvm/trunk/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll Thu Jun 17 10:18:27 2010 @@ -4,7 +4,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64" target triple = "armv7-apple-darwin9" -define arm_apcscc <4 x i32> @scale(<4 x i32> %v, i32 %f) nounwind { +define <4 x i32> @scale(<4 x i32> %v, i32 %f) nounwind { entry: %v_addr = alloca <4 x i32> ; <<4 x i32>*> [#uses=2] %f_addr = alloca i32 ; [#uses=2] Modified: llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill.ll Thu Jun 17 10:18:27 2010 @@ -7,7 +7,7 @@ %struct.tree = type { i32, double, double, %struct.tree*, %struct.tree*, %struct.tree*, %struct.tree* } @g = common global %struct.tree* null -define arm_apcscc %struct.tree* @tsp(%struct.tree* %t, i32 %nproc) nounwind { +define %struct.tree* @tsp(%struct.tree* %t, i32 %nproc) nounwind { entry: %t.idx51.val.i = load double* null ; [#uses=1] br i1 undef, label %bb4.i, label %bb.i Modified: llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll Thu Jun 17 10:18:27 2010 @@ -9,7 +9,7 @@ %struct.icstruct = type { [3 x i32], i16 } %struct.node = type { i16, double, [3 x double], i32, i32 } -declare arm_apcscc double @floor(double) nounwind readnone +declare double @floor(double) nounwind readnone define void @intcoord(%struct.icstruct* noalias nocapture sret %agg.result, i1 %a, double %b) { entry: @@ -28,7 +28,7 @@ br i1 %a, label %bb11, label %bb9 bb9: ; preds = %bb7 - %0 = tail call arm_apcscc double @floor(double %b) nounwind readnone ; [#uses=0] + %0 = tail call double @floor(double %b) nounwind readnone ; [#uses=0] br label %bb11 bb11: ; preds = %bb9, %bb7 Modified: llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll Thu Jun 17 10:18:27 2010 @@ -9,7 +9,7 @@ %struct.Patient = type { i32, i32, i32, %struct.Village* } %struct.Village = type { [4 x %struct.Village*], %struct.Village*, %struct.List, %struct.Hosp, i32, i32 } -define arm_apcscc %struct.Village* @alloc_tree(i32 %level, i32 %label, %struct.Village* %back, i1 %p) nounwind { +define %struct.Village* @alloc_tree(i32 %level, i32 %label, %struct.Village* %back, i1 %p) nounwind { entry: br i1 %p, label %bb8, label %bb1 Modified: llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll Thu Jun 17 10:18:27 2010 @@ -8,19 +8,19 @@ @.str1 = external constant [31 x i8], align 1 ; <[31 x i8]*> [#uses=1] @.str2 = external constant [4 x i8], align 1 ; <[4 x i8]*> [#uses=1] -declare arm_apcscc i32 @getUnknown(i32, ...) nounwind +declare i32 @getUnknown(i32, ...) nounwind declare void @llvm.va_start(i8*) nounwind declare void @llvm.va_end(i8*) nounwind -declare arm_apcscc i32 @printf(i8* nocapture, ...) nounwind +declare i32 @printf(i8* nocapture, ...) nounwind -define arm_apcscc i32 @main() nounwind { +define i32 @main() nounwind { entry: - %0 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([31 x i8]* @.str1, i32 0, i32 0), i32 1, i32 1, i32 1, i32 1, i32 1, i32 1) nounwind ; [#uses=0] - %1 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([31 x i8]* @.str1, i32 0, i32 0), i32 -128, i32 116, i32 116, i32 -3852, i32 -31232, i32 -1708916736) nounwind ; [#uses=0] - %2 = tail call arm_apcscc i32 (i32, ...)* @getUnknown(i32 undef, i32 116, i32 116, i32 -3852, i32 -31232, i32 30556, i32 -1708916736) nounwind ; [#uses=1] - %3 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([4 x i8]* @.str2, i32 0, i32 0), i32 %2) nounwind ; [#uses=0] + %0 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([31 x i8]* @.str1, i32 0, i32 0), i32 1, i32 1, i32 1, i32 1, i32 1, i32 1) nounwind ; [#uses=0] + %1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([31 x i8]* @.str1, i32 0, i32 0), i32 -128, i32 116, i32 116, i32 -3852, i32 -31232, i32 -1708916736) nounwind ; [#uses=0] + %2 = tail call i32 (i32, ...)* @getUnknown(i32 undef, i32 116, i32 116, i32 -3852, i32 -31232, i32 30556, i32 -1708916736) nounwind ; [#uses=1] + %3 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([4 x i8]* @.str2, i32 0, i32 0), i32 %2) nounwind ; [#uses=0] ret i32 0 } Modified: llvm/trunk/test/CodeGen/ARM/2009-08-26-ScalarToVector.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-08-26-ScalarToVector.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-08-26-ScalarToVector.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2009-08-26-ScalarToVector.ll Thu Jun 17 10:18:27 2010 @@ -10,7 +10,7 @@ declare <2 x i32> @llvm.arm.neon.vpadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone -define arm_apcscc void @_ZN6squish10ClusterFit9Compress3EPv(%quuz* %this, i8* %block) { +define void @_ZN6squish10ClusterFit9Compress3EPv(%quuz* %this, i8* %block) { entry: %0 = lshr <4 x i32> zeroinitializer, ; <<4 x i32>> [#uses=1] %1 = shufflevector <4 x i32> %0, <4 x i32> undef, <2 x i32> ; <<2 x i32>> [#uses=1] Modified: llvm/trunk/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll Thu Jun 17 10:18:27 2010 @@ -8,7 +8,7 @@ %quux = type { i32 (...)**, %baz*, i32 } %quuz = type { %quux, i32, %bar, [128 x i8], [16 x %foo], %foo, %foo, %foo } -define arm_apcscc void @aaaa(%quuz* %this, i8* %block) { +define void @aaaa(%quuz* %this, i8* %block) { entry: br i1 undef, label %bb.nph269, label %bb201 Modified: llvm/trunk/test/CodeGen/ARM/2009-08-29-ExtractEltf32.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-08-29-ExtractEltf32.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-08-29-ExtractEltf32.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2009-08-29-ExtractEltf32.ll Thu Jun 17 10:18:27 2010 @@ -2,7 +2,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32" target triple = "thumbv7-elf" -define arm_apcscc void @foo() nounwind { +define void @foo() nounwind { entry: %0 = tail call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> undef, <2 x float> undef) nounwind ; <<2 x float>> [#uses=1] %tmp28 = extractelement <2 x float> %0, i32 0 ; [#uses=1] Modified: llvm/trunk/test/CodeGen/ARM/2009-08-29-TooLongSplat.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-08-29-TooLongSplat.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-08-29-TooLongSplat.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2009-08-29-TooLongSplat.ll Thu Jun 17 10:18:27 2010 @@ -2,7 +2,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32" target triple = "thumbv7-elf" -define arm_apcscc void @aaa() nounwind { +define void @aaa() nounwind { entry: %0 = fmul <4 x float> undef, ; <<4 x float>> [#uses=1] %tmp31 = extractelement <4 x float> %0, i32 0 ; [#uses=1] Modified: llvm/trunk/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll Thu Jun 17 10:18:27 2010 @@ -2,7 +2,7 @@ %struct.A = type { i32* } -define arm_apcscc void @"\01-[MyFunction Name:]"() { +define void @"\01-[MyFunction Name:]"() { entry: %save_filt.1 = alloca i32 ; [#uses=2] %save_eptr.0 = alloca i8* ; [#uses=2] @@ -10,12 +10,12 @@ %eh_exception = alloca i8* ; [#uses=5] %eh_selector = alloca i32 ; [#uses=3] %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] - call arm_apcscc void @_ZN1AC1Ev(%struct.A* %a) - invoke arm_apcscc void @_Z3barv() + call void @_ZN1AC1Ev(%struct.A* %a) + invoke void @_Z3barv() to label %invcont unwind label %lpad invcont: ; preds = %entry - call arm_apcscc void @_ZN1AD1Ev(%struct.A* %a) nounwind + call void @_ZN1AD1Ev(%struct.A* %a) nounwind br label %return bb: ; preds = %ppad @@ -23,7 +23,7 @@ store i32 %eh_select, i32* %save_filt.1, align 4 %eh_value = load i8** %eh_exception ; [#uses=1] store i8* %eh_value, i8** %save_eptr.0, align 4 - call arm_apcscc void @_ZN1AD1Ev(%struct.A* %a) nounwind + call void @_ZN1AD1Ev(%struct.A* %a) nounwind %0 = load i8** %save_eptr.0, align 4 ; [#uses=1] store i8* %0, i8** %eh_exception, align 4 %1 = load i32* %save_filt.1, align 4 ; [#uses=1] @@ -46,16 +46,16 @@ Unwind: ; preds = %bb %eh_ptr3 = load i8** %eh_exception ; [#uses=1] - call arm_apcscc void @_Unwind_SjLj_Resume(i8* %eh_ptr3) + call void @_Unwind_SjLj_Resume(i8* %eh_ptr3) unreachable } -define linkonce_odr arm_apcscc void @_ZN1AC1Ev(%struct.A* %this) { +define linkonce_odr void @_ZN1AC1Ev(%struct.A* %this) { entry: %this_addr = alloca %struct.A* ; <%struct.A**> [#uses=2] %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] store %struct.A* %this, %struct.A** %this_addr - %0 = call arm_apcscc i8* @_Znwm(i32 4) ; [#uses=1] + %0 = call i8* @_Znwm(i32 4) ; [#uses=1] %1 = bitcast i8* %0 to i32* ; [#uses=1] %2 = load %struct.A** %this_addr, align 4 ; <%struct.A*> [#uses=1] %3 = getelementptr inbounds %struct.A* %2, i32 0, i32 0 ; [#uses=1] @@ -66,9 +66,9 @@ ret void } -declare arm_apcscc i8* @_Znwm(i32) +declare i8* @_Znwm(i32) -define linkonce_odr arm_apcscc void @_ZN1AD1Ev(%struct.A* %this) nounwind { +define linkonce_odr void @_ZN1AD1Ev(%struct.A* %this) nounwind { entry: %this_addr = alloca %struct.A* ; <%struct.A**> [#uses=2] %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] @@ -77,7 +77,7 @@ %1 = getelementptr inbounds %struct.A* %0, i32 0, i32 0 ; [#uses=1] %2 = load i32** %1, align 4 ; [#uses=1] %3 = bitcast i32* %2 to i8* ; [#uses=1] - call arm_apcscc void @_ZdlPv(i8* %3) nounwind + call void @_ZdlPv(i8* %3) nounwind br label %bb bb: ; preds = %entry @@ -88,9 +88,9 @@ } ;CHECK: L_LSDA_0: -declare arm_apcscc void @_ZdlPv(i8*) nounwind +declare void @_ZdlPv(i8*) nounwind -declare arm_apcscc void @_Z3barv() +declare void @_Z3barv() declare i8* @llvm.eh.exception() nounwind @@ -98,6 +98,6 @@ declare i32 @llvm.eh.typeid.for.i32(i8*) nounwind -declare arm_apcscc i32 @__gxx_personality_sj0(...) +declare i32 @__gxx_personality_sj0(...) -declare arm_apcscc void @_Unwind_SjLj_Resume(i8*) +declare void @_Unwind_SjLj_Resume(i8*) Modified: llvm/trunk/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll Thu Jun 17 10:18:27 2010 @@ -30,11 +30,11 @@ @.str218 = private constant [6 x i8] c"%7d%c\00", align 1 ; <[6 x i8]*> [#uses=1] @.str319 = private constant [30 x i8] c"Failed to allocate %u bytes.\0A\00", align 1 ; <[30 x i8]*> [#uses=1] -declare arm_apcscc i32 @puts(i8* nocapture) nounwind +declare i32 @puts(i8* nocapture) nounwind -declare arm_apcscc i32 @getchar() nounwind +declare i32 @getchar() nounwind -define internal arm_apcscc i32 @transpose() nounwind readonly { +define internal i32 @transpose() nounwind readonly { ; CHECK: push entry: %0 = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 1), align 4 ; [#uses=1] @@ -101,6 +101,6 @@ ret i32 -128 } -declare arm_apcscc noalias i8* @calloc(i32, i32) nounwind +declare noalias i8* @calloc(i32, i32) nounwind declare void @llvm.memset.i64(i8* nocapture, i8, i64, i32) nounwind Modified: llvm/trunk/test/CodeGen/ARM/2009-09-09-AllOnes.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-09-09-AllOnes.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-09-09-AllOnes.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2009-09-09-AllOnes.ll Thu Jun 17 10:18:27 2010 @@ -2,7 +2,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32" target triple = "thumbv7-elf" -define arm_apcscc void @foo() { +define void @foo() { entry: %0 = insertelement <4 x i32> undef, i32 -1, i32 3 store <4 x i32> %0, <4 x i32>* undef, align 16 Modified: llvm/trunk/test/CodeGen/ARM/2009-09-24-spill-align.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-09-24-spill-align.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-09-24-spill-align.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2009-09-24-spill-align.ll Thu Jun 17 10:18:27 2010 @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s ; pr4926 -define arm_apcscc void @test_vget_lanep16() nounwind { +define void @test_vget_lanep16() nounwind { entry: %arg0_poly16x4_t = alloca <4 x i16> ; <<4 x i16>*> [#uses=1] %out_poly16_t = alloca i16 ; [#uses=1] Modified: llvm/trunk/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll Thu Jun 17 10:18:27 2010 @@ -6,7 +6,7 @@ %struct.int16x8_t = type { <8 x i16> } %struct.int16x8x2_t = type { [2 x %struct.int16x8_t] } -define arm_apcscc void @t(%struct.int16x8x2_t* noalias nocapture sret %agg.result, <8 x i16> %tmp.0, %struct.int16x8x2_t* nocapture %dst) nounwind { +define void @t(%struct.int16x8x2_t* noalias nocapture sret %agg.result, <8 x i16> %tmp.0, %struct.int16x8x2_t* nocapture %dst) nounwind { entry: ;CHECK: vtrn.16 %0 = shufflevector <8 x i16> %tmp.0, <8 x i16> undef, <8 x i32> Modified: llvm/trunk/test/CodeGen/ARM/2010-04-09-NeonSelect.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-04-09-NeonSelect.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2010-04-09-NeonSelect.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2010-04-09-NeonSelect.ll Thu Jun 17 10:18:27 2010 @@ -1,7 +1,7 @@ ; RUN: llc -march=arm -mattr=+neon < %s ; Radar 7770501: Don't crash on SELECT and SELECT_CC with NEON vector values. -define arm_apcscc void @vDSP_FFT16_copv(float* nocapture %O, float* nocapture %I, i32 %Direction) nounwind { +define void @vDSP_FFT16_copv(float* nocapture %O, float* nocapture %I, i32 %Direction) nounwind { entry: %.22 = select i1 undef, <4 x float> undef, <4 x float> zeroinitializer ; <<4 x float>> [#uses=1] %0 = fadd <4 x float> undef, %.22 ; <<4 x float>> [#uses=1] Modified: llvm/trunk/test/CodeGen/ARM/2010-04-13-v2f64SplitArg.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-04-13-v2f64SplitArg.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2010-04-13-v2f64SplitArg.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2010-04-13-v2f64SplitArg.ll Thu Jun 17 10:18:27 2010 @@ -1,7 +1,7 @@ ; RUN: llc < %s -mtriple=arm-apple-darwin -mcpu=cortex-a8 ; Radar 7855014 -define arm_apcscc void @test1(i32 %f0, i32 %f1, i32 %f2, <4 x i32> %f3) nounwind { +define void @test1(i32 %f0, i32 %f1, i32 %f2, <4 x i32> %f3) nounwind { entry: unreachable } Modified: llvm/trunk/test/CodeGen/ARM/2010-04-14-SplitVector.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-04-14-SplitVector.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2010-04-14-SplitVector.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2010-04-14-SplitVector.ll Thu Jun 17 10:18:27 2010 @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mcpu=arm1136jf-s ; Radar 7854640 -define arm_apcscc void @test() nounwind { +define void @test() nounwind { bb: br i1 undef, label %bb9, label %bb10 Modified: llvm/trunk/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll Thu Jun 17 10:18:27 2010 @@ -3,7 +3,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64-n32" target triple = "armv4t-apple-darwin10" -define hidden arm_apcscc i32 @__addvsi3(i32 %a, i32 %b) nounwind { +define hidden i32 @__addvsi3(i32 %a, i32 %b) nounwind { entry: tail call void @llvm.dbg.value(metadata !{i32 %b}, i64 0, metadata !0) %0 = add nsw i32 %b, %a, !dbg !9 ; [#uses=1] Modified: llvm/trunk/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll Thu Jun 17 10:18:27 2010 @@ -10,7 +10,7 @@ @.str = external constant [1 x i8] ; <[1 x i8]*> [#uses=1] -define arm_apcscc void @yy(%struct.q* %qq) nounwind { +define void @yy(%struct.q* %qq) nounwind { entry: %vla6 = alloca i8, i32 undef, align 1 ; [#uses=1] %vla10 = alloca i8, i32 undef, align 1 ; [#uses=1] @@ -19,18 +19,18 @@ %tmp21 = load i32* undef ; [#uses=1] %0 = mul i32 1, %tmp21 ; [#uses=1] %vla22 = alloca i8, i32 %0, align 1 ; [#uses=1] - call arm_apcscc void (...)* @zz(i8* getelementptr inbounds ([1 x i8]* @.str, i32 0, i32 0), i32 2, i32 1) + call void (...)* @zz(i8* getelementptr inbounds ([1 x i8]* @.str, i32 0, i32 0), i32 2, i32 1) br i1 undef, label %if.then, label %if.end36 if.then: ; preds = %entry - %call = call arm_apcscc i32 (...)* @x(%struct.q* undef, i8* undef, i8* %vla6, i8* %vla10, i32 undef) ; [#uses=0] - %call35 = call arm_apcscc i32 (...)* @x(%struct.q* undef, i8* %vla14, i8* %vla18, i8* %vla22, i32 undef) ; [#uses=0] + %call = call i32 (...)* @x(%struct.q* undef, i8* undef, i8* %vla6, i8* %vla10, i32 undef) ; [#uses=0] + %call35 = call i32 (...)* @x(%struct.q* undef, i8* %vla14, i8* %vla18, i8* %vla22, i32 undef) ; [#uses=0] unreachable if.end36: ; preds = %entry ret void } -declare arm_apcscc void @zz(...) +declare void @zz(...) -declare arm_apcscc i32 @x(...) +declare i32 @x(...) Modified: llvm/trunk/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll Thu Jun 17 10:18:27 2010 @@ -4,7 +4,7 @@ %struct.foo = type { i64, i64 } -define arm_apcscc zeroext i8 @t(%struct.foo* %this) noreturn optsize { +define zeroext i8 @t(%struct.foo* %this) noreturn optsize { entry: ; ARM: t: ; ARM: str r0, [r1], r0 Modified: llvm/trunk/test/CodeGen/ARM/2010-05-21-BuildVector.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-05-21-BuildVector.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2010-05-21-BuildVector.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2010-05-21-BuildVector.ll Thu Jun 17 10:18:27 2010 @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s ; Radar 7872877 -define arm_apcscc void @test(float* %fltp, i32 %packedValue, float* %table) nounwind { +define void @test(float* %fltp, i32 %packedValue, float* %table) nounwind { entry: %0 = load float* %fltp %1 = insertelement <4 x float> undef, float %0, i32 0 Modified: llvm/trunk/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll Thu Jun 17 10:18:27 2010 @@ -3,7 +3,7 @@ %struct.__int8x8x2_t = type { [2 x <8 x i8>] } -define arm_apcscc void @foo(%struct.__int8x8x2_t* nocapture %a, i8* %b) nounwind { +define void @foo(%struct.__int8x8x2_t* nocapture %a, i8* %b) nounwind { entry: %0 = bitcast %struct.__int8x8x2_t* %a to i128* ; [#uses=1] %srcval = load i128* %0, align 8 ; [#uses=2] Modified: llvm/trunk/test/CodeGen/ARM/arm-returnaddr.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/arm-returnaddr.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/arm-returnaddr.ll (original) +++ llvm/trunk/test/CodeGen/ARM/arm-returnaddr.ll Thu Jun 17 10:18:27 2010 @@ -3,7 +3,7 @@ ; rdar://8015977 ; rdar://8020118 -define arm_apcscc i8* @rt0(i32 %x) nounwind readnone { +define i8* @rt0(i32 %x) nounwind readnone { entry: ; CHECK: rt0: ; CHECK: mov r0, lr @@ -11,7 +11,7 @@ ret i8* %0 } -define arm_apcscc i8* @rt2() nounwind readnone { +define i8* @rt2() nounwind readnone { entry: ; CHECK: rt2: ; CHECK: ldr r0, [r7] Modified: llvm/trunk/test/CodeGen/ARM/fpconsts.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fpconsts.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fpconsts.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fpconsts.ll Thu Jun 17 10:18:27 2010 @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=arm -mattr=+vfp3 | FileCheck %s -define arm_apcscc float @t1(float %x) nounwind readnone optsize { +define float @t1(float %x) nounwind readnone optsize { entry: ; CHECK: t1: ; CHECK: vmov.f32 s1, #4.000000e+00 @@ -8,7 +8,7 @@ ret float %0 } -define arm_apcscc double @t2(double %x) nounwind readnone optsize { +define double @t2(double %x) nounwind readnone optsize { entry: ; CHECK: t2: ; CHECK: vmov.f64 d1, #3.000000e+00 @@ -16,7 +16,7 @@ ret double %0 } -define arm_apcscc double @t3(double %x) nounwind readnone optsize { +define double @t3(double %x) nounwind readnone optsize { entry: ; CHECK: t3: ; CHECK: vmov.f64 d1, #-1.300000e+01 @@ -24,7 +24,7 @@ ret double %0 } -define arm_apcscc float @t4(float %x) nounwind readnone optsize { +define float @t4(float %x) nounwind readnone optsize { entry: ; CHECK: t4: ; CHECK: vmov.f32 s1, #-2.400000e+01 Modified: llvm/trunk/test/CodeGen/ARM/indirectbr.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/indirectbr.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/indirectbr.ll (original) +++ llvm/trunk/test/CodeGen/ARM/indirectbr.ll Thu Jun 17 10:18:27 2010 @@ -5,7 +5,7 @@ @nextaddr = global i8* null ; [#uses=2] @C.0.2070 = private constant [5 x i8*] [i8* blockaddress(@foo, %L1), i8* blockaddress(@foo, %L2), i8* blockaddress(@foo, %L3), i8* blockaddress(@foo, %L4), i8* blockaddress(@foo, %L5)] ; <[5 x i8*]*> [#uses=1] -define internal arm_apcscc i32 @foo(i32 %i) nounwind { +define internal i32 @foo(i32 %i) nounwind { ; ARM: foo: ; THUMB: foo: ; THUMB2: foo: Modified: llvm/trunk/test/CodeGen/ARM/inlineasm3.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/inlineasm3.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/inlineasm3.ll (original) +++ llvm/trunk/test/CodeGen/ARM/inlineasm3.ll Thu Jun 17 10:18:27 2010 @@ -3,7 +3,7 @@ ; Radar 7449043 %struct.int32x4_t = type { <4 x i32> } -define arm_apcscc void @t() nounwind { +define void @t() nounwind { entry: ; CHECK: vmov.I64 q15, #0 ; CHECK: vmov.32 d30[0], r0 @@ -16,7 +16,7 @@ ; Radar 7457110 %struct.int32x2_t = type { <4 x i32> } -define arm_apcscc void @t2() nounwind { +define void @t2() nounwind { entry: ; CHECK: vmov d30, d0 ; CHECK: vmov.32 r0, d30[0] Modified: llvm/trunk/test/CodeGen/ARM/lsr-on-unrolled-loops.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/lsr-on-unrolled-loops.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/lsr-on-unrolled-loops.ll (original) +++ llvm/trunk/test/CodeGen/ARM/lsr-on-unrolled-loops.ll Thu Jun 17 10:18:27 2010 @@ -40,7 +40,7 @@ %22 = type { void (%0*)*, void (%0*, i8***, i32, i8**, i32)* } %23 = type { void (%0*, i32)*, void (%0*, i8**, i8**, i32)*, void (%0*)*, void (%0*)* } -define arm_apcscc void @test(%0* nocapture %a0, %11* nocapture %a1, i16* nocapture %a2, i8** nocapture %a3, i32 %a4) nounwind { +define void @test(%0* nocapture %a0, %11* nocapture %a1, i16* nocapture %a2, i8** nocapture %a3, i32 %a4) nounwind { bb: %t = alloca [64 x float], align 4 %t5 = getelementptr inbounds %0* %a0, i32 0, i32 65 @@ -393,7 +393,7 @@ %struct.z_stream = type { i8*, i32, i32, i8*, i32, i32, i8*, %struct.internal_state*, i8* (i8*, i32, i32)*, void (i8*, i8*)*, i8*, i32, i32, i32 } %union.anon = type { i16 } -define arm_apcscc i32 @longest_match(%struct.internal_state* %s, i32 %cur_match) nounwind optsize { +define i32 @longest_match(%struct.internal_state* %s, i32 %cur_match) nounwind optsize { entry: %0 = getelementptr inbounds %struct.internal_state* %s, i32 0, i32 31 ; [#uses=1] %1 = load i32* %0, align 4 ; [#uses=2] Modified: llvm/trunk/test/CodeGen/ARM/reg_sequence.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/reg_sequence.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/reg_sequence.ll (original) +++ llvm/trunk/test/CodeGen/ARM/reg_sequence.ll Thu Jun 17 10:18:27 2010 @@ -8,7 +8,7 @@ %struct.__neon_int16x8x2_t = type { <8 x i16>, <8 x i16> } %struct.__neon_int32x4x2_t = type { <4 x i32>, <4 x i32> } -define arm_apcscc void @t1(i16* %i_ptr, i16* %o_ptr, %struct.int32x4_t* nocapture %vT0ptr, %struct.int32x4_t* nocapture %vT1ptr) nounwind { +define void @t1(i16* %i_ptr, i16* %o_ptr, %struct.int32x4_t* nocapture %vT0ptr, %struct.int32x4_t* nocapture %vT1ptr) nounwind { entry: ; CHECK: t1: ; CHECK: vld1.16 @@ -41,7 +41,7 @@ ret void } -define arm_apcscc void @t2(i16* %i_ptr, i16* %o_ptr, %struct.int16x8_t* nocapture %vT0ptr, %struct.int16x8_t* nocapture %vT1ptr) nounwind { +define void @t2(i16* %i_ptr, i16* %o_ptr, %struct.int16x8_t* nocapture %vT0ptr, %struct.int16x8_t* nocapture %vT1ptr) nounwind { entry: ; CHECK: t2: ; CHECK: vld1.16 @@ -88,7 +88,7 @@ ret <8 x i8> %tmp4 } -define arm_apcscc void @t4(i32* %in, i32* %out) nounwind { +define void @t4(i32* %in, i32* %out) nounwind { entry: ; CHECK: t4: ; CHECK: vld2.32 @@ -163,7 +163,7 @@ ret <8 x i8> %tmp5 } -define arm_apcscc void @t7(i32* %iptr, i32* %optr) nounwind { +define void @t7(i32* %iptr, i32* %optr) nounwind { entry: ; CHECK: t7: ; CHECK: vld2.32 Modified: llvm/trunk/test/CodeGen/ARM/remat.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/remat.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/remat.ll (original) +++ llvm/trunk/test/CodeGen/ARM/remat.ll Thu Jun 17 10:18:27 2010 @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 -stats -info-output-file - | grep "Number of re-materialization" -define arm_apcscc i32 @main(i32 %argc, i8** nocapture %argv, double %d1, double %d2) nounwind { +define i32 @main(i32 %argc, i8** nocapture %argv, double %d1, double %d2) nounwind { entry: br i1 undef, label %smvp.exit, label %bb.i3 @@ -25,7 +25,7 @@ br i1 %14, label %phi1.exit, label %bb.i35 bb.i35: ; preds = %bb142 - %5 = call arm_apcscc double @sin(double %15) nounwind readonly ; [#uses=1] + %5 = call double @sin(double %15) nounwind readonly ; [#uses=1] %6 = fmul double %5, 0x4031740AFA84AD8A ; [#uses=1] %7 = fsub double 1.000000e+00, undef ; [#uses=1] %8 = fdiv double %7, 6.000000e-01 ; [#uses=1] @@ -62,4 +62,4 @@ unreachable } -declare arm_apcscc double @sin(double) nounwind readonly +declare double @sin(double) nounwind readonly Modified: llvm/trunk/test/CodeGen/ARM/select-imm.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/select-imm.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/select-imm.ll (original) +++ llvm/trunk/test/CodeGen/ARM/select-imm.ll Thu Jun 17 10:18:27 2010 @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -march=arm -mattr=+thumb2 | FileCheck %s --check-prefix=T2 -define arm_apcscc i32 @t1(i32 %c) nounwind readnone { +define i32 @t1(i32 %c) nounwind readnone { entry: ; ARM: t1: ; ARM: mov r1, #101 @@ -17,7 +17,7 @@ ret i32 %1 } -define arm_apcscc i32 @t2(i32 %c) nounwind readnone { +define i32 @t2(i32 %c) nounwind readnone { entry: ; ARM: t2: ; ARM: mov r1, #101 @@ -33,7 +33,7 @@ ret i32 %1 } -define arm_apcscc i32 @t3(i32 %a) nounwind readnone { +define i32 @t3(i32 %a) nounwind readnone { entry: ; ARM: t3: ; ARM: mov r0, #0 Modified: llvm/trunk/test/CodeGen/ARM/spill-q.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/spill-q.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/spill-q.ll (original) +++ llvm/trunk/test/CodeGen/ARM/spill-q.ll Thu Jun 17 10:18:27 2010 @@ -9,7 +9,7 @@ declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*) nounwind readonly -define arm_apcscc void @aaa(%quuz* %this, i8* %block) { +define void @aaa(%quuz* %this, i8* %block) { ; CHECK: aaa: ; CHECK: bic sp, sp, #15 ; CHECK: vst1.64 {{.*}}sp, :128 Modified: llvm/trunk/test/CodeGen/ARM/trap.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/trap.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/trap.ll (original) +++ llvm/trunk/test/CodeGen/ARM/trap.ll Thu Jun 17 10:18:27 2010 @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm | FileCheck %s ; rdar://7961298 -define arm_apcscc void @t() nounwind { +define void @t() nounwind { entry: ; CHECK: t: ; CHECK: trap Modified: llvm/trunk/test/CodeGen/ARM/unaligned_load_store.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/unaligned_load_store.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/unaligned_load_store.ll (original) +++ llvm/trunk/test/CodeGen/ARM/unaligned_load_store.ll Thu Jun 17 10:18:27 2010 @@ -4,7 +4,7 @@ ; rdar://7113725 -define arm_apcscc void @t(i8* nocapture %a, i8* nocapture %b) nounwind { +define void @t(i8* nocapture %a, i8* nocapture %b) nounwind { entry: ; GENERIC: t: ; GENERIC: ldrb r2 Modified: llvm/trunk/test/CodeGen/ARM/vdup.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vdup.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vdup.ll (original) +++ llvm/trunk/test/CodeGen/ARM/vdup.ll Thu Jun 17 10:18:27 2010 @@ -244,25 +244,25 @@ ret <4 x float> %tmp2 } -define arm_apcscc <2 x i64> @foo(<2 x i64> %arg0_int64x1_t) nounwind readnone { +define <2 x i64> @foo(<2 x i64> %arg0_int64x1_t) nounwind readnone { entry: %0 = shufflevector <2 x i64> %arg0_int64x1_t, <2 x i64> undef, <2 x i32> ret <2 x i64> %0 } -define arm_apcscc <2 x i64> @bar(<2 x i64> %arg0_int64x1_t) nounwind readnone { +define <2 x i64> @bar(<2 x i64> %arg0_int64x1_t) nounwind readnone { entry: %0 = shufflevector <2 x i64> %arg0_int64x1_t, <2 x i64> undef, <2 x i32> ret <2 x i64> %0 } -define arm_apcscc <2 x double> @baz(<2 x double> %arg0_int64x1_t) nounwind readnone { +define <2 x double> @baz(<2 x double> %arg0_int64x1_t) nounwind readnone { entry: %0 = shufflevector <2 x double> %arg0_int64x1_t, <2 x double> undef, <2 x i32> ret <2 x double> %0 } -define arm_apcscc <2 x double> @qux(<2 x double> %arg0_int64x1_t) nounwind readnone { +define <2 x double> @qux(<2 x double> %arg0_int64x1_t) nounwind readnone { entry: %0 = shufflevector <2 x double> %arg0_int64x1_t, <2 x double> undef, <2 x i32> ret <2 x double> %0 Modified: llvm/trunk/test/CodeGen/ARM/vext.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vext.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vext.ll (original) +++ llvm/trunk/test/CodeGen/ARM/vext.ll Thu Jun 17 10:18:27 2010 @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -define arm_apcscc <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind { +define <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK: test_vextd: ;CHECK: vext %tmp1 = load <8 x i8>* %A @@ -9,7 +9,7 @@ ret <8 x i8> %tmp3 } -define arm_apcscc <8 x i8> @test_vextRd(<8 x i8>* %A, <8 x i8>* %B) nounwind { +define <8 x i8> @test_vextRd(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK: test_vextRd: ;CHECK: vext %tmp1 = load <8 x i8>* %A @@ -18,7 +18,7 @@ ret <8 x i8> %tmp3 } -define arm_apcscc <16 x i8> @test_vextq(<16 x i8>* %A, <16 x i8>* %B) nounwind { +define <16 x i8> @test_vextq(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK: test_vextq: ;CHECK: vext %tmp1 = load <16 x i8>* %A @@ -27,7 +27,7 @@ ret <16 x i8> %tmp3 } -define arm_apcscc <16 x i8> @test_vextRq(<16 x i8>* %A, <16 x i8>* %B) nounwind { +define <16 x i8> @test_vextRq(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK: test_vextRq: ;CHECK: vext %tmp1 = load <16 x i8>* %A @@ -36,7 +36,7 @@ ret <16 x i8> %tmp3 } -define arm_apcscc <4 x i16> @test_vextd16(<4 x i16>* %A, <4 x i16>* %B) nounwind { +define <4 x i16> @test_vextd16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK: test_vextd16: ;CHECK: vext %tmp1 = load <4 x i16>* %A @@ -45,7 +45,7 @@ ret <4 x i16> %tmp3 } -define arm_apcscc <4 x i32> @test_vextq32(<4 x i32>* %A, <4 x i32>* %B) nounwind { +define <4 x i32> @test_vextq32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK: test_vextq32: ;CHECK: vext %tmp1 = load <4 x i32>* %A Modified: llvm/trunk/test/CodeGen/ARM/vmov.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vmov.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vmov.ll (original) +++ llvm/trunk/test/CodeGen/ARM/vmov.ll Thu Jun 17 10:18:27 2010 @@ -136,7 +136,7 @@ ; Check for correct assembler printing for immediate values. %struct.int8x8_t = type { <8 x i8> } -define arm_apcscc void @vdupn128(%struct.int8x8_t* noalias nocapture sret %agg.result) nounwind { +define void @vdupn128(%struct.int8x8_t* noalias nocapture sret %agg.result) nounwind { entry: ;CHECK: vdupn128: ;CHECK: vmov.i8 d0, #0x80 @@ -145,7 +145,7 @@ ret void } -define arm_apcscc void @vdupnneg75(%struct.int8x8_t* noalias nocapture sret %agg.result) nounwind { +define void @vdupnneg75(%struct.int8x8_t* noalias nocapture sret %agg.result) nounwind { entry: ;CHECK: vdupnneg75: ;CHECK: vmov.i8 d0, #0xB5 Modified: llvm/trunk/test/CodeGen/ARM/vrev.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vrev.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vrev.ll (original) +++ llvm/trunk/test/CodeGen/ARM/vrev.ll Thu Jun 17 10:18:27 2010 @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -define arm_apcscc <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind { +define <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind { ;CHECK: test_vrev64D8: ;CHECK: vrev64.8 %tmp1 = load <8 x i8>* %A @@ -8,7 +8,7 @@ ret <8 x i8> %tmp2 } -define arm_apcscc <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind { +define <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind { ;CHECK: test_vrev64D16: ;CHECK: vrev64.16 %tmp1 = load <4 x i16>* %A @@ -16,7 +16,7 @@ ret <4 x i16> %tmp2 } -define arm_apcscc <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind { +define <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind { ;CHECK: test_vrev64D32: ;CHECK: vrev64.32 %tmp1 = load <2 x i32>* %A @@ -24,7 +24,7 @@ ret <2 x i32> %tmp2 } -define arm_apcscc <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind { +define <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind { ;CHECK: test_vrev64Df: ;CHECK: vrev64.32 %tmp1 = load <2 x float>* %A @@ -32,7 +32,7 @@ ret <2 x float> %tmp2 } -define arm_apcscc <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind { +define <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind { ;CHECK: test_vrev64Q8: ;CHECK: vrev64.8 %tmp1 = load <16 x i8>* %A @@ -40,7 +40,7 @@ ret <16 x i8> %tmp2 } -define arm_apcscc <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind { +define <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind { ;CHECK: test_vrev64Q16: ;CHECK: vrev64.16 %tmp1 = load <8 x i16>* %A @@ -48,7 +48,7 @@ ret <8 x i16> %tmp2 } -define arm_apcscc <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind { +define <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind { ;CHECK: test_vrev64Q32: ;CHECK: vrev64.32 %tmp1 = load <4 x i32>* %A @@ -56,7 +56,7 @@ ret <4 x i32> %tmp2 } -define arm_apcscc <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind { +define <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind { ;CHECK: test_vrev64Qf: ;CHECK: vrev64.32 %tmp1 = load <4 x float>* %A @@ -64,7 +64,7 @@ ret <4 x float> %tmp2 } -define arm_apcscc <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind { +define <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind { ;CHECK: test_vrev32D8: ;CHECK: vrev32.8 %tmp1 = load <8 x i8>* %A @@ -72,7 +72,7 @@ ret <8 x i8> %tmp2 } -define arm_apcscc <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind { +define <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind { ;CHECK: test_vrev32D16: ;CHECK: vrev32.16 %tmp1 = load <4 x i16>* %A @@ -80,7 +80,7 @@ ret <4 x i16> %tmp2 } -define arm_apcscc <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind { +define <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind { ;CHECK: test_vrev32Q8: ;CHECK: vrev32.8 %tmp1 = load <16 x i8>* %A @@ -88,7 +88,7 @@ ret <16 x i8> %tmp2 } -define arm_apcscc <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind { +define <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind { ;CHECK: test_vrev32Q16: ;CHECK: vrev32.16 %tmp1 = load <8 x i16>* %A @@ -96,7 +96,7 @@ ret <8 x i16> %tmp2 } -define arm_apcscc <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind { +define <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind { ;CHECK: test_vrev16D8: ;CHECK: vrev16.8 %tmp1 = load <8 x i8>* %A @@ -104,7 +104,7 @@ ret <8 x i8> %tmp2 } -define arm_apcscc <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind { +define <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind { ;CHECK: test_vrev16Q8: ;CHECK: vrev16.8 %tmp1 = load <16 x i8>* %A Modified: llvm/trunk/test/CodeGen/Generic/2010-ZeroSizedArg.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2010-ZeroSizedArg.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Generic/2010-ZeroSizedArg.ll (original) +++ llvm/trunk/test/CodeGen/Generic/2010-ZeroSizedArg.ll Thu Jun 17 10:18:27 2010 @@ -6,7 +6,7 @@ @.str = private constant [1 x i8] c" " -define arm_apcscc void @t(%0) nounwind { +define void @t(%0) nounwind { entry: %arg0 = alloca %union.T0 %1 = bitcast %union.T0* %arg0 to %0* @@ -14,4 +14,4 @@ ret void } -declare arm_apcscc i32 @printf(i8*, ...) +declare i32 @printf(i8*, ...) Modified: llvm/trunk/test/CodeGen/Thumb/2009-07-19-SPDecBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/2009-07-19-SPDecBug.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/2009-07-19-SPDecBug.ll (original) +++ llvm/trunk/test/CodeGen/Thumb/2009-07-19-SPDecBug.ll Thu Jun 17 10:18:27 2010 @@ -1,7 +1,7 @@ ; RUN: llc < %s -mtriple=thumbv6-elf | not grep "subs sp" ; PR4567 -define arm_apcscc i8* @__gets_chk(i8* %s, i32 %slen) nounwind { +define i8* @__gets_chk(i8* %s, i32 %slen) nounwind { entry: br i1 undef, label %bb, label %bb1 @@ -23,11 +23,11 @@ br i1 undef, label %bb5, label %bb6 bb5: ; preds = %bb4 - %2 = call arm_apcscc i8* @gets(i8* %s) nounwind ; [#uses=1] + %2 = call i8* @gets(i8* %s) nounwind ; [#uses=1] ret i8* %2 bb6: ; preds = %bb4 unreachable } -declare arm_apcscc i8* @gets(i8*) nounwind +declare i8* @gets(i8*) nounwind Modified: llvm/trunk/test/CodeGen/Thumb/2009-07-20-TwoAddrBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/2009-07-20-TwoAddrBug.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/2009-07-20-TwoAddrBug.ll (original) +++ llvm/trunk/test/CodeGen/Thumb/2009-07-20-TwoAddrBug.ll Thu Jun 17 10:18:27 2010 @@ -2,7 +2,7 @@ @Time.2535 = external global i64 ; [#uses=2] -define arm_apcscc i64 @millisecs() nounwind { +define i64 @millisecs() nounwind { entry: %0 = load i64* @Time.2535, align 4 ; [#uses=2] %1 = add i64 %0, 1 ; [#uses=1] Modified: llvm/trunk/test/CodeGen/Thumb/2009-07-27-PEIAssert.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/2009-07-27-PEIAssert.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/2009-07-27-PEIAssert.ll (original) +++ llvm/trunk/test/CodeGen/Thumb/2009-07-27-PEIAssert.ll Thu Jun 17 10:18:27 2010 @@ -4,10 +4,10 @@ %struct.List = type { i32, i32* } @llvm.used = appending global [1 x i8*] [i8* bitcast (i32 ()* @main to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] -define arm_apcscc i32 @main() nounwind { +define i32 @main() nounwind { entry: %ll = alloca %struct.LinkList*, align 4 ; <%struct.LinkList**> [#uses=1] - %0 = call arm_apcscc i32 @ReadList(%struct.LinkList** %ll, %struct.List** null) nounwind ; [#uses=1] + %0 = call i32 @ReadList(%struct.LinkList** %ll, %struct.List** null) nounwind ; [#uses=1] switch i32 %0, label %bb5 [ i32 7, label %bb4 i32 42, label %bb3 @@ -23,4 +23,4 @@ ret i32 1 } -declare arm_apcscc i32 @ReadList(%struct.LinkList** nocapture, %struct.List** nocapture) nounwind +declare i32 @ReadList(%struct.LinkList** nocapture, %struct.List** nocapture) nounwind Modified: llvm/trunk/test/CodeGen/Thumb/2009-08-12-ConstIslandAssert.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/2009-08-12-ConstIslandAssert.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/2009-08-12-ConstIslandAssert.ll (original) +++ llvm/trunk/test/CodeGen/Thumb/2009-08-12-ConstIslandAssert.ll Thu Jun 17 10:18:27 2010 @@ -2,7 +2,7 @@ %struct.BF_KEY = type { [18 x i32], [1024 x i32] } -define arm_apcscc void @BF_encrypt(i32* nocapture %data, %struct.BF_KEY* nocapture %key, i32 %encrypt) nounwind { +define void @BF_encrypt(i32* nocapture %data, %struct.BF_KEY* nocapture %key, i32 %encrypt) nounwind { entry: %0 = getelementptr %struct.BF_KEY* %key, i32 0, i32 0, i32 0; [#uses=2] %1 = load i32* %data, align 4 ; [#uses=2] Modified: llvm/trunk/test/CodeGen/Thumb/2009-08-12-RegInfoAssert.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/2009-08-12-RegInfoAssert.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/2009-08-12-RegInfoAssert.ll (original) +++ llvm/trunk/test/CodeGen/Thumb/2009-08-12-RegInfoAssert.ll Thu Jun 17 10:18:27 2010 @@ -3,15 +3,15 @@ %struct.vorbis_comment = type { i8**, i32*, i32, i8* } @.str16 = external constant [2 x i8], align 1 ; <[2 x i8]*> [#uses=1] -declare arm_apcscc i8* @__strcpy_chk(i8*, i8*, i32) nounwind +declare i8* @__strcpy_chk(i8*, i8*, i32) nounwind -declare arm_apcscc i8* @__strcat_chk(i8*, i8*, i32) nounwind +declare i8* @__strcat_chk(i8*, i8*, i32) nounwind -define arm_apcscc i8* @vorbis_comment_query(%struct.vorbis_comment* nocapture %vc, i8* %tag, i32 %count) nounwind { +define i8* @vorbis_comment_query(%struct.vorbis_comment* nocapture %vc, i8* %tag, i32 %count) nounwind { entry: %0 = alloca i8, i32 undef, align 4 ; [#uses=2] - %1 = call arm_apcscc i8* @__strcpy_chk(i8* %0, i8* %tag, i32 -1) nounwind; [#uses=0] - %2 = call arm_apcscc i8* @__strcat_chk(i8* %0, i8* getelementptr ([2 x i8]* @.str16, i32 0, i32 0), i32 -1) nounwind; [#uses=0] + %1 = call i8* @__strcpy_chk(i8* %0, i8* %tag, i32 -1) nounwind; [#uses=0] + %2 = call i8* @__strcat_chk(i8* %0, i8* getelementptr ([2 x i8]* @.str16, i32 0, i32 0), i32 -1) nounwind; [#uses=0] %3 = getelementptr %struct.vorbis_comment* %vc, i32 0, i32 0; [#uses=1] br label %bb11 Modified: llvm/trunk/test/CodeGen/Thumb/2009-08-20-ISelBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/2009-08-20-ISelBug.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/2009-08-20-ISelBug.ll (original) +++ llvm/trunk/test/CodeGen/Thumb/2009-08-20-ISelBug.ll Thu Jun 17 10:18:27 2010 @@ -9,7 +9,7 @@ @llvm.used = appending global [1 x i8*] [i8* bitcast (i32 (%struct.asl_file_t*, i64, i64*)* @t to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] -define arm_apcscc i32 @t(%struct.asl_file_t* %s, i64 %off, i64* %out) nounwind optsize { +define i32 @t(%struct.asl_file_t* %s, i64 %off, i64* %out) nounwind optsize { ; CHECK: t: ; CHECK: adds r0, #8 entry: @@ -32,7 +32,7 @@ br i1 %8, label %bb13, label %bb5 bb5: ; preds = %bb3 - %9 = call arm_apcscc i32 @fseeko(%struct.FILE* %2, i64 %off, i32 0) nounwind ; [#uses=1] + %9 = call i32 @fseeko(%struct.FILE* %2, i64 %off, i32 0) nounwind ; [#uses=1] %10 = icmp eq i32 %9, 0 ; [#uses=1] br i1 %10, label %bb7, label %bb13 @@ -40,7 +40,7 @@ store i64 0, i64* %val, align 4 %11 = load %struct.FILE** %1, align 4 ; <%struct.FILE*> [#uses=1] %val8 = bitcast i64* %val to i8* ; [#uses=1] - %12 = call arm_apcscc i32 @fread(i8* noalias %val8, i32 8, i32 1, %struct.FILE* noalias %11) nounwind ; [#uses=1] + %12 = call i32 @fread(i8* noalias %val8, i32 8, i32 1, %struct.FILE* noalias %11) nounwind ; [#uses=1] %13 = icmp eq i32 %12, 1 ; [#uses=1] br i1 %13, label %bb10, label %bb13 @@ -50,7 +50,7 @@ bb11: ; preds = %bb10 %15 = load i64* %val, align 4 ; [#uses=1] - %16 = call arm_apcscc i64 @asl_core_ntohq(i64 %15) nounwind ; [#uses=1] + %16 = call i64 @asl_core_ntohq(i64 %15) nounwind ; [#uses=1] store i64 %16, i64* %out, align 4 ret i32 0 @@ -59,8 +59,8 @@ ret i32 %.0 } -declare arm_apcscc i32 @fseeko(%struct.FILE* nocapture, i64, i32) nounwind +declare i32 @fseeko(%struct.FILE* nocapture, i64, i32) nounwind -declare arm_apcscc i32 @fread(i8* noalias nocapture, i32, i32, %struct.FILE* noalias nocapture) nounwind +declare i32 @fread(i8* noalias nocapture, i32, i32, %struct.FILE* noalias nocapture) nounwind -declare arm_apcscc i64 @asl_core_ntohq(i64) +declare i64 @asl_core_ntohq(i64) Modified: llvm/trunk/test/CodeGen/Thumb/2009-12-17-pre-regalloc-taildup.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/2009-12-17-pre-regalloc-taildup.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/2009-12-17-pre-regalloc-taildup.ll (original) +++ llvm/trunk/test/CodeGen/Thumb/2009-12-17-pre-regalloc-taildup.ll Thu Jun 17 10:18:27 2010 @@ -10,7 +10,7 @@ @codetable.2928 = internal constant [5 x i8*] [i8* blockaddress(@interpret_threaded, %RETURN), i8* blockaddress(@interpret_threaded, %INCREMENT), i8* blockaddress(@interpret_threaded, %DECREMENT), i8* blockaddress(@interpret_threaded, %DOUBLE), i8* blockaddress(@interpret_threaded, %SWAPWORD)] ; <[5 x i8*]*> [#uses=5] @llvm.used = appending global [1 x i8*] [i8* bitcast (i32 (i8*)* @interpret_threaded to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] -define arm_apcscc i32 @interpret_threaded(i8* nocapture %opcodes) nounwind readonly optsize { +define i32 @interpret_threaded(i8* nocapture %opcodes) nounwind readonly optsize { entry: %0 = load i8* %opcodes, align 1 ; [#uses=1] %1 = zext i8 %0 to i32 ; [#uses=1] Modified: llvm/trunk/test/CodeGen/Thumb/2010-01-15-local-alloc-spill-physical.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/2010-01-15-local-alloc-spill-physical.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/2010-01-15-local-alloc-spill-physical.ll (original) +++ llvm/trunk/test/CodeGen/Thumb/2010-01-15-local-alloc-spill-physical.ll Thu Jun 17 10:18:27 2010 @@ -4,10 +4,10 @@ @fred = internal global i32 0 ; [#uses=1] -define arm_apcscc void @foo() nounwind { +define void @foo() nounwind { entry: ; CHECK: str r0, [sp - %0 = call arm_apcscc i32 (...)* @bar() nounwind ; [#uses=1] + %0 = call i32 (...)* @bar() nounwind ; [#uses=1] ; CHECK: blx _bar ; CHECK: ldr r1, [sp store i32 %0, i32* @fred, align 4 @@ -17,4 +17,4 @@ ret void } -declare arm_apcscc i32 @bar(...) +declare i32 @bar(...) Modified: llvm/trunk/test/CodeGen/Thumb/asmprinter-bug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/asmprinter-bug.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/asmprinter-bug.ll (original) +++ llvm/trunk/test/CodeGen/Thumb/asmprinter-bug.ll Thu Jun 17 10:18:27 2010 @@ -13,7 +13,7 @@ @__stderrp = external global %struct.FILE* ; <%struct.FILE**> [#uses=1] @.str1 = private constant [28 x i8] c"Final valprev=%d, index=%d\0A\00", section "__TEXT,__cstring,cstring_literals", align 1 ; <[28 x i8]*> [#uses=1] -define arm_apcscc void @adpcm_coder(i16* nocapture %indata, i8* nocapture %outdata, i32 %len, %struct.adpcm_state* nocapture %state) nounwind { +define void @adpcm_coder(i16* nocapture %indata, i8* nocapture %outdata, i32 %len, %struct.adpcm_state* nocapture %state) nounwind { entry: %0 = getelementptr %struct.adpcm_state* %state, i32 0, i32 0 ; [#uses=2] %1 = load i16* %0, align 2 ; [#uses=1] @@ -138,7 +138,7 @@ ret void } -define arm_apcscc void @adpcm_decoder(i8* nocapture %indata, i16* nocapture %outdata, i32 %len, %struct.adpcm_state* nocapture %state) nounwind { +define void @adpcm_decoder(i8* nocapture %indata, i16* nocapture %outdata, i32 %len, %struct.adpcm_state* nocapture %state) nounwind { entry: %0 = getelementptr %struct.adpcm_state* %state, i32 0, i32 0 ; [#uses=2] %1 = load i16* %0, align 2 ; [#uses=1] @@ -245,17 +245,17 @@ ret void } -define arm_apcscc i32 @main() nounwind { +define i32 @main() nounwind { entry: br label %bb bb: ; preds = %bb3, %entry - %0 = tail call arm_apcscc i32 (...)* @read(i32 0, i8* getelementptr ([500 x i8]* @abuf, i32 0, i32 0), i32 500) nounwind ; [#uses=4] + %0 = tail call i32 (...)* @read(i32 0, i8* getelementptr ([500 x i8]* @abuf, i32 0, i32 0), i32 500) nounwind ; [#uses=4] %1 = icmp slt i32 %0, 0 ; [#uses=1] br i1 %1, label %bb1, label %bb2 bb1: ; preds = %bb - tail call arm_apcscc void @perror(i8* getelementptr ([11 x i8]* @.str, i32 0, i32 0)) nounwind + tail call void @perror(i8* getelementptr ([11 x i8]* @.str, i32 0, i32 0)) nounwind ret i32 1 bb2: ; preds = %bb @@ -264,9 +264,9 @@ bb3: ; preds = %bb2 %3 = shl i32 %0, 1 ; [#uses=1] - tail call arm_apcscc void @adpcm_decoder(i8* getelementptr ([500 x i8]* @abuf, i32 0, i32 0), i16* getelementptr ([1000 x i16]* @sbuf, i32 0, i32 0), i32 %3, %struct.adpcm_state* @state) nounwind + tail call void @adpcm_decoder(i8* getelementptr ([500 x i8]* @abuf, i32 0, i32 0), i16* getelementptr ([1000 x i16]* @sbuf, i32 0, i32 0), i32 %3, %struct.adpcm_state* @state) nounwind %4 = shl i32 %0, 2 ; [#uses=1] - %5 = tail call arm_apcscc i32 (...)* @write(i32 1, i16* getelementptr ([1000 x i16]* @sbuf, i32 0, i32 0), i32 %4) nounwind ; [#uses=0] + %5 = tail call i32 (...)* @write(i32 1, i16* getelementptr ([1000 x i16]* @sbuf, i32 0, i32 0), i32 %4) nounwind ; [#uses=0] br label %bb bb4: ; preds = %bb2 @@ -275,14 +275,14 @@ %8 = sext i16 %7 to i32 ; [#uses=1] %9 = load i8* getelementptr (%struct.adpcm_state* @state, i32 0, i32 1), align 2 ; [#uses=1] %10 = sext i8 %9 to i32 ; [#uses=1] - %11 = tail call arm_apcscc i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* %6, i8* getelementptr ([28 x i8]* @.str1, i32 0, i32 0), i32 %8, i32 %10) nounwind ; [#uses=0] + %11 = tail call i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* %6, i8* getelementptr ([28 x i8]* @.str1, i32 0, i32 0), i32 %8, i32 %10) nounwind ; [#uses=0] ret i32 0 } -declare arm_apcscc i32 @read(...) +declare i32 @read(...) -declare arm_apcscc void @perror(i8* nocapture) nounwind +declare void @perror(i8* nocapture) nounwind -declare arm_apcscc i32 @write(...) +declare i32 @write(...) -declare arm_apcscc i32 @fprintf(%struct.FILE* nocapture, i8* nocapture, ...) nounwind +declare i32 @fprintf(%struct.FILE* nocapture, i8* nocapture, ...) nounwind Modified: llvm/trunk/test/CodeGen/Thumb/machine-licm.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/machine-licm.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/machine-licm.ll (original) +++ llvm/trunk/test/CodeGen/Thumb/machine-licm.ll Thu Jun 17 10:18:27 2010 @@ -7,7 +7,7 @@ @GV = external global i32 ; [#uses=2] -define arm_apcscc void @t(i32* nocapture %vals, i32 %c) nounwind { +define void @t(i32* nocapture %vals, i32 %c) nounwind { entry: ; CHECK: t: %0 = icmp eq i32 %c, 0 ; [#uses=1] Modified: llvm/trunk/test/CodeGen/Thumb/pop.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/pop.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/pop.ll (original) +++ llvm/trunk/test/CodeGen/Thumb/pop.ll Thu Jun 17 10:18:27 2010 @@ -1,7 +1,7 @@ ; RUN: llc < %s -mtriple=thumb-apple-darwin | FileCheck %s ; rdar://7268481 -define arm_apcscc void @t(i8* %a, ...) nounwind { +define void @t(i8* %a, ...) nounwind { ; CHECK: t: ; CHECK: pop {r3} ; CHECK-NEXT: add sp, #12 Modified: llvm/trunk/test/CodeGen/Thumb/push.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/push.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/push.ll (original) +++ llvm/trunk/test/CodeGen/Thumb/push.ll Thu Jun 17 10:18:27 2010 @@ -1,7 +1,7 @@ ; RUN: llc < %s -mtriple=thumb-apple-darwin -disable-fp-elim | FileCheck %s ; rdar://7268481 -define arm_apcscc void @t() nounwind { +define void @t() nounwind { ; CHECK: t: ; CHECK-NEXT : push {r7} entry: Modified: llvm/trunk/test/CodeGen/Thumb/trap.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/trap.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/trap.ll (original) +++ llvm/trunk/test/CodeGen/Thumb/trap.ll Thu Jun 17 10:18:27 2010 @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=thumb | FileCheck %s ; rdar://7961298 -define arm_apcscc void @t() nounwind { +define void @t() nounwind { entry: ; CHECK: t: ; CHECK: trap Modified: llvm/trunk/test/CodeGen/Thumb2/2009-07-17-CrossRegClassCopy.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-07-17-CrossRegClassCopy.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2009-07-17-CrossRegClassCopy.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2009-07-17-CrossRegClassCopy.ll Thu Jun 17 10:18:27 2010 @@ -4,9 +4,9 @@ target triple = "thumbv6t2-elf" %struct.dwarf_cie = type <{ i32, i32, i8, [0 x i8], [3 x i8] }> -declare arm_apcscc i8* @read_sleb128(i8*, i32* nocapture) nounwind +declare i8* @read_sleb128(i8*, i32* nocapture) nounwind -define arm_apcscc i32 @get_cie_encoding(%struct.dwarf_cie* %cie) nounwind { +define i32 @get_cie_encoding(%struct.dwarf_cie* %cie) nounwind { entry: br i1 undef, label %bb1, label %bb13 @@ -27,7 +27,7 @@ %.sum40 = add i32 %indvar.i, undef ; [#uses=1] %.sum31 = add i32 %.sum40, 2 ; [#uses=1] %scevgep.i = getelementptr %struct.dwarf_cie* %cie, i32 0, i32 3, i32 %.sum31 ; [#uses=1] - %3 = call arm_apcscc i8* @read_sleb128(i8* %scevgep.i, i32* undef) ; [#uses=0] + %3 = call i8* @read_sleb128(i8* %scevgep.i, i32* undef) ; [#uses=0] unreachable bb13: ; preds = %entry Modified: llvm/trunk/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2009-07-21-ISelBug.ll Thu Jun 17 10:18:27 2010 @@ -3,7 +3,7 @@ @"\01LC" = external constant [36 x i8], align 1 ; <[36 x i8]*> [#uses=1] -define arm_apcscc i32 @t(i32, ...) nounwind { +define i32 @t(i32, ...) nounwind { entry: ; CHECK: t: ; CHECK: add r7, sp, #12 @@ -24,7 +24,7 @@ %15 = sext i8 %6 to i32 ; [#uses=2] %16 = sext i16 %10 to i32 ; [#uses=2] %17 = sext i16 %13 to i32 ; [#uses=2] - %18 = call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([36 x i8]* @"\01LC", i32 0, i32 0), i32 -128, i32 0, i32 %15, i32 %16, i32 %17, i32 0, i32 %14) nounwind ; [#uses=0] + %18 = call i32 (i8*, ...)* @printf(i8* getelementptr ([36 x i8]* @"\01LC", i32 0, i32 0), i32 -128, i32 0, i32 %15, i32 %16, i32 %17, i32 0, i32 %14) nounwind ; [#uses=0] %19 = add i32 0, %15 ; [#uses=1] %20 = add i32 %19, %16 ; [#uses=1] %21 = add i32 %20, %14 ; [#uses=1] @@ -33,4 +33,4 @@ ret i32 %23 } -declare arm_apcscc i32 @printf(i8* nocapture, ...) nounwind +declare i32 @printf(i8* nocapture, ...) nounwind Modified: llvm/trunk/test/CodeGen/Thumb2/2009-07-23-CPIslandBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-07-23-CPIslandBug.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2009-07-23-CPIslandBug.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2009-07-23-CPIslandBug.ll Thu Jun 17 10:18:27 2010 @@ -1,7 +1,7 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mattr=+vfp2,+thumb2 ; rdar://7083961 -define arm_apcscc i32 @value(i64 %b1, i64 %b2) nounwind readonly { +define i32 @value(i64 %b1, i64 %b2) nounwind readonly { entry: %0 = icmp eq i32 undef, 0 ; [#uses=1] %mod.0.ph.ph = select i1 %0, float -1.000000e+00, float 1.000000e+00 ; [#uses=1] Modified: llvm/trunk/test/CodeGen/Thumb2/2009-07-30-PEICrash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-07-30-PEICrash.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2009-07-30-PEICrash.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2009-07-30-PEICrash.ll Thu Jun 17 10:18:27 2010 @@ -28,7 +28,7 @@ %struct.jvirt_barray_control = type { [64 x i16]**, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.jvirt_barray_control*, %struct.backing_store_info } %struct.jvirt_sarray_control = type { i8**, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.jvirt_sarray_control*, %struct.backing_store_info } -define arm_apcscc void @jpeg_idct_float(%struct.jpeg_decompress_struct* nocapture %cinfo, %struct.jpeg_component_info* nocapture %compptr, i16* nocapture %coef_block, i8** nocapture %output_buf, i32 %output_col) nounwind { +define void @jpeg_idct_float(%struct.jpeg_decompress_struct* nocapture %cinfo, %struct.jpeg_component_info* nocapture %compptr, i16* nocapture %coef_block, i8** nocapture %output_buf, i32 %output_col) nounwind { entry: %workspace = alloca [64 x float], align 4 ; <[64 x float]*> [#uses=11] %0 = load i8** undef, align 4 ; [#uses=5] Modified: llvm/trunk/test/CodeGen/Thumb2/2009-08-01-WrongLDRBOpc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-08-01-WrongLDRBOpc.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2009-08-01-WrongLDRBOpc.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2009-08-01-WrongLDRBOpc.ll Thu Jun 17 10:18:27 2010 @@ -6,7 +6,7 @@ @lefline = external global [100 x [20 x i32]] ; <[100 x [20 x i32]]*> [#uses=1] @sep = external global [20 x i32] ; <[20 x i32]*> [#uses=1] -define arm_apcscc void @main(i32 %argc, i8** %argv) noreturn nounwind { +define void @main(i32 %argc, i8** %argv) noreturn nounwind { ; CHECK: main: ; CHECK: ldrb entry: Modified: llvm/trunk/test/CodeGen/Thumb2/2009-08-02-CoalescerBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-08-02-CoalescerBug.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2009-08-02-CoalescerBug.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2009-08-02-CoalescerBug.ll Thu Jun 17 10:18:27 2010 @@ -22,9 +22,9 @@ %"struct.xalanc_1_8::XalanDOMString" = type { %"struct.std::vector >", i32 } %"struct.xalanc_1_8::XalanOutputStream" = type { i32 (...)**, i32, %"struct.std::basic_ostream >.base"*, i32, %"struct.std::vector >", %"struct.xalanc_1_8::XalanDOMString", i8, i8, %"struct.std::CharVectorType" } -declare arm_apcscc void @_ZN10xalanc_1_814FormatterToXML17writeParentTagEndEv(%"struct.xalanc_1_8::FormatterToXML"*) +declare void @_ZN10xalanc_1_814FormatterToXML17writeParentTagEndEv(%"struct.xalanc_1_8::FormatterToXML"*) -define arm_apcscc void @_ZN10xalanc_1_814FormatterToXML5cdataEPKtj(%"struct.xalanc_1_8::FormatterToXML"* %this, i16* %ch, i32 %length) { +define void @_ZN10xalanc_1_814FormatterToXML5cdataEPKtj(%"struct.xalanc_1_8::FormatterToXML"* %this, i16* %ch, i32 %length) { entry: %0 = getelementptr %"struct.xalanc_1_8::FormatterToXML"* %this, i32 0, i32 13 ; [#uses=1] br i1 undef, label %bb4, label %bb @@ -36,11 +36,11 @@ %3 = getelementptr i32 (...)** %2, i32 11 ; [#uses=1] %4 = load i32 (...)** %3, align 4 ; [#uses=1] %5 = bitcast i32 (...)* %4 to void (%"struct.xalanc_1_8::FormatterToXML"*, i16*, i32)* ; [#uses=1] - tail call arm_apcscc void %5(%"struct.xalanc_1_8::FormatterToXML"* %this, i16* %ch, i32 %length) + tail call void %5(%"struct.xalanc_1_8::FormatterToXML"* %this, i16* %ch, i32 %length) ret void bb4: ; preds = %entry - tail call arm_apcscc void @_ZN10xalanc_1_814FormatterToXML17writeParentTagEndEv(%"struct.xalanc_1_8::FormatterToXML"* %this) - tail call arm_apcscc void undef(%"struct.xalanc_1_8::FormatterToXML"* %this, i16* %ch, i32 0, i32 %length, i8 zeroext undef) + tail call void @_ZN10xalanc_1_814FormatterToXML17writeParentTagEndEv(%"struct.xalanc_1_8::FormatterToXML"* %this) + tail call void undef(%"struct.xalanc_1_8::FormatterToXML"* %this, i16* %ch, i32 0, i32 %length, i8 zeroext undef) ret void } Modified: llvm/trunk/test/CodeGen/Thumb2/2009-08-04-CoalescerBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-08-04-CoalescerBug.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2009-08-04-CoalescerBug.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2009-08-04-CoalescerBug.ll Thu Jun 17 10:18:27 2010 @@ -28,17 +28,17 @@ @.str1822946 = external constant [8 x i8], align 1 ; <[8 x i8]*> [#uses=1] @.str1842948 = external constant [11 x i8], align 1 ; <[11 x i8]*> [#uses=1] -declare arm_apcscc i32 @fprintf(%struct.FILE* nocapture, i8* nocapture, ...) nounwind +declare i32 @fprintf(%struct.FILE* nocapture, i8* nocapture, ...) nounwind -declare arm_apcscc i32 @"\01_fwrite"(i8*, i32, i32, i8*) +declare i32 @"\01_fwrite"(i8*, i32, i32, i8*) -declare arm_apcscc %struct.FILE* @OpenIncGraphicFile(i8*, i8 zeroext, %struct.rec** nocapture, %struct.FILE_POS*, i32* nocapture) nounwind +declare %struct.FILE* @OpenIncGraphicFile(i8*, i8 zeroext, %struct.rec** nocapture, %struct.FILE_POS*, i32* nocapture) nounwind -declare arm_apcscc void @Error(i32, i32, i8*, i32, %struct.FILE_POS*, ...) nounwind +declare void @Error(i32, i32, i8*, i32, %struct.FILE_POS*, ...) nounwind -declare arm_apcscc i8* @fgets(i8*, i32, %struct.FILE* nocapture) nounwind +declare i8* @fgets(i8*, i32, %struct.FILE* nocapture) nounwind -define arm_apcscc void @PS_PrintGraphicInclude(%struct.rec* %x, i32 %colmark, i32 %rowmark) nounwind { +define void @PS_PrintGraphicInclude(%struct.rec* %x, i32 %colmark, i32 %rowmark) nounwind { entry: br label %bb5 @@ -49,7 +49,7 @@ br i1 undef, label %bb5, label %bb6 bb6: ; preds = %bb5 - %0 = call arm_apcscc %struct.FILE* @OpenIncGraphicFile(i8* undef, i8 zeroext 0, %struct.rec** undef, %struct.FILE_POS* null, i32* undef) nounwind ; <%struct.FILE*> [#uses=1] + %0 = call %struct.FILE* @OpenIncGraphicFile(i8* undef, i8 zeroext 0, %struct.rec** undef, %struct.FILE_POS* null, i32* undef) nounwind ; <%struct.FILE*> [#uses=1] br i1 false, label %bb.i, label %FontHalfXHeight.exit bb.i: ; preds = %bb6 @@ -67,22 +67,22 @@ br i1 %2, label %bb.i5, label %FontName.exit bb.i5: ; preds = %FontSize.exit - call arm_apcscc void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 1, i32 2, i8* getelementptr ([20 x i8]* @.str24239, i32 0, i32 0), i32 0, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*), i8* getelementptr ([10 x i8]* @.str81872, i32 0, i32 0)) nounwind + call void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 1, i32 2, i8* getelementptr ([20 x i8]* @.str24239, i32 0, i32 0), i32 0, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*), i8* getelementptr ([10 x i8]* @.str81872, i32 0, i32 0)) nounwind br label %FontName.exit FontName.exit: ; preds = %bb.i5, %FontSize.exit - %3 = call arm_apcscc i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* undef, i8* getelementptr ([8 x i8]* @.str1822946, i32 0, i32 0), i32 %1, i8* undef) nounwind ; [#uses=0] - %4 = call arm_apcscc i32 @"\01_fwrite"(i8* getelementptr ([11 x i8]* @.str1842948, i32 0, i32 0), i32 1, i32 10, i8* undef) nounwind ; [#uses=0] + %3 = call i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* undef, i8* getelementptr ([8 x i8]* @.str1822946, i32 0, i32 0), i32 %1, i8* undef) nounwind ; [#uses=0] + %4 = call i32 @"\01_fwrite"(i8* getelementptr ([11 x i8]* @.str1842948, i32 0, i32 0), i32 1, i32 10, i8* undef) nounwind ; [#uses=0] %5 = sub i32 %colmark, undef ; [#uses=1] %6 = sub i32 %rowmark, undef ; [#uses=1] %7 = load %struct.FILE** @out_fp, align 4 ; <%struct.FILE*> [#uses=1] - %8 = call arm_apcscc i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* %7, i8* getelementptr ([17 x i8]* @.str212784, i32 0, i32 0), i32 %5, i32 %6) nounwind ; [#uses=0] + %8 = call i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* %7, i8* getelementptr ([17 x i8]* @.str212784, i32 0, i32 0), i32 %5, i32 %6) nounwind ; [#uses=0] store i32 0, i32* @cpexists, align 4 %9 = getelementptr %struct.rec* %y.0, i32 0, i32 0, i32 3, i32 0, i32 0, i32 1 ; [#uses=1] %10 = load i32* %9, align 4 ; [#uses=1] %11 = sub i32 0, %10 ; [#uses=1] %12 = load %struct.FILE** @out_fp, align 4 ; <%struct.FILE*> [#uses=1] - %13 = call arm_apcscc i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* %12, i8* getelementptr ([17 x i8]* @.str212784, i32 0, i32 0), i32 undef, i32 %11) nounwind ; [#uses=0] + %13 = call i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* %12, i8* getelementptr ([17 x i8]* @.str212784, i32 0, i32 0), i32 undef, i32 %11) nounwind ; [#uses=0] store i32 0, i32* @cpexists, align 4 br label %bb100.outer.outer @@ -132,7 +132,7 @@ br label %bb2.i41 bb2.i.i15.critedge: ; preds = %bb.i47 - %16 = call arm_apcscc i8* @fgets(i8* undef, i32 512, %struct.FILE* %0) nounwind ; [#uses=0] + %16 = call i8* @fgets(i8* undef, i32 512, %struct.FILE* %0) nounwind ; [#uses=0] %iftmp.560.0 = select i1 undef, i32 2, i32 0 ; [#uses=1] br label %bb100.outer Modified: llvm/trunk/test/CodeGen/Thumb2/2009-08-04-ScavengerAssert.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-08-04-ScavengerAssert.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2009-08-04-ScavengerAssert.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2009-08-04-ScavengerAssert.ll Thu Jun 17 10:18:27 2010 @@ -55,25 +55,25 @@ @.str1872951 = external constant [17 x i8], align 1 ; <[17 x i8]*> [#uses=1] @.str1932957 = external constant [26 x i8], align 1 ; <[26 x i8]*> [#uses=1] -declare arm_apcscc i32 @fprintf(%struct.FILE* nocapture, i8* nocapture, ...) nounwind +declare i32 @fprintf(%struct.FILE* nocapture, i8* nocapture, ...) nounwind -declare arm_apcscc i32 @"\01_fwrite"(i8*, i32, i32, i8*) +declare i32 @"\01_fwrite"(i8*, i32, i32, i8*) -declare arm_apcscc i32 @remove(i8* nocapture) nounwind +declare i32 @remove(i8* nocapture) nounwind -declare arm_apcscc %struct.FILE* @OpenIncGraphicFile(i8*, i8 zeroext, %struct.rec** nocapture, %struct.FILE_POS*, i32* nocapture) nounwind +declare %struct.FILE* @OpenIncGraphicFile(i8*, i8 zeroext, %struct.rec** nocapture, %struct.FILE_POS*, i32* nocapture) nounwind -declare arm_apcscc %struct.rec* @MakeWord(i32, i8* nocapture, %struct.FILE_POS*) nounwind +declare %struct.rec* @MakeWord(i32, i8* nocapture, %struct.FILE_POS*) nounwind -declare arm_apcscc void @Error(i32, i32, i8*, i32, %struct.FILE_POS*, ...) nounwind +declare void @Error(i32, i32, i8*, i32, %struct.FILE_POS*, ...) nounwind -declare arm_apcscc i32 @"\01_fputs"(i8*, %struct.FILE*) +declare i32 @"\01_fputs"(i8*, %struct.FILE*) -declare arm_apcscc noalias i8* @calloc(i32, i32) nounwind +declare noalias i8* @calloc(i32, i32) nounwind -declare arm_apcscc i8* @fgets(i8*, i32, %struct.FILE* nocapture) nounwind +declare i8* @fgets(i8*, i32, %struct.FILE* nocapture) nounwind -define arm_apcscc void @PS_PrintGraphicInclude(%struct.rec* %x, i32 %colmark, i32 %rowmark) nounwind { +define void @PS_PrintGraphicInclude(%struct.rec* %x, i32 %colmark, i32 %rowmark) nounwind { entry: %buff = alloca [512 x i8], align 4 ; <[512 x i8]*> [#uses=5] %0 = getelementptr %struct.rec* %x, i32 0, i32 0, i32 1, i32 0, i32 0 ; [#uses=2] @@ -94,7 +94,7 @@ br i1 %8, label %bb2, label %bb3 bb2: ; preds = %bb1 - call arm_apcscc void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 1, i32 2, i8* getelementptr ([20 x i8]* @.str24239, i32 0, i32 0), i32 0, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*), i8* getelementptr ([40 x i8]* @.str1802944, i32 0, i32 0)) nounwind + call void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 1, i32 2, i8* getelementptr ([20 x i8]* @.str24239, i32 0, i32 0), i32 0, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*), i8* getelementptr ([40 x i8]* @.str1802944, i32 0, i32 0)) nounwind br label %bb3 bb3: ; preds = %bb2, %bb1 @@ -108,7 +108,7 @@ bb6: ; preds = %bb5 %10 = load i8* %0, align 4 ; [#uses=1] %11 = getelementptr %struct.rec* %y.0, i32 0, i32 0, i32 1, i32 0 ; <%struct.FILE_POS*> [#uses=1] - %12 = call arm_apcscc %struct.FILE* @OpenIncGraphicFile(i8* undef, i8 zeroext %10, %struct.rec** null, %struct.FILE_POS* %11, i32* undef) nounwind ; <%struct.FILE*> [#uses=4] + %12 = call %struct.FILE* @OpenIncGraphicFile(i8* undef, i8 zeroext %10, %struct.rec** null, %struct.FILE_POS* %11, i32* undef) nounwind ; <%struct.FILE*> [#uses=4] br i1 false, label %bb7, label %bb8 bb7: ; preds = %bb6 @@ -124,7 +124,7 @@ br i1 %15, label %bb.i, label %FontHalfXHeight.exit bb.i: ; preds = %bb9 - call arm_apcscc void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 1, i32 2, i8* getelementptr ([20 x i8]* @.str24239, i32 0, i32 0), i32 0, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*), i8* getelementptr ([17 x i8]* @.str111875, i32 0, i32 0)) nounwind + call void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 1, i32 2, i8* getelementptr ([20 x i8]* @.str24239, i32 0, i32 0), i32 0, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*), i8* getelementptr ([17 x i8]* @.str111875, i32 0, i32 0)) nounwind %.pre186 = load i32* @currentfont, align 4 ; [#uses=1] br label %FontHalfXHeight.exit @@ -139,7 +139,7 @@ br i1 undef, label %bb2.i, label %FontSize.exit bb2.i: ; preds = %bb1.i - call arm_apcscc void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 37, i32 61, i8* getelementptr ([30 x i8]* @.str101874, i32 0, i32 0), i32 1, %struct.FILE_POS* null) nounwind + call void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 37, i32 61, i8* getelementptr ([30 x i8]* @.str101874, i32 0, i32 0), i32 1, %struct.FILE_POS* null) nounwind unreachable FontSize.exit: ; preds = %bb1.i @@ -151,35 +151,35 @@ br i1 %21, label %bb.i5, label %FontName.exit bb.i5: ; preds = %FontSize.exit - call arm_apcscc void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 1, i32 2, i8* getelementptr ([20 x i8]* @.str24239, i32 0, i32 0), i32 0, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*), i8* getelementptr ([10 x i8]* @.str81872, i32 0, i32 0)) nounwind + call void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 1, i32 2, i8* getelementptr ([20 x i8]* @.str24239, i32 0, i32 0), i32 0, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*), i8* getelementptr ([10 x i8]* @.str81872, i32 0, i32 0)) nounwind br label %FontName.exit FontName.exit: ; preds = %bb.i5, %FontSize.exit %22 = phi %struct.FONT_INFO* [ undef, %bb.i5 ], [ undef, %FontSize.exit ] ; <%struct.FONT_INFO*> [#uses=1] %23 = getelementptr %struct.FONT_INFO* %22, i32 %19, i32 5 ; <%struct.rec**> [#uses=0] - %24 = call arm_apcscc i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* undef, i8* getelementptr ([8 x i8]* @.str1822946, i32 0, i32 0), i32 %18, i8* null) nounwind ; [#uses=0] + %24 = call i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* undef, i8* getelementptr ([8 x i8]* @.str1822946, i32 0, i32 0), i32 %18, i8* null) nounwind ; [#uses=0] br label %bb10 bb10: ; preds = %FontName.exit, %bb8 - %25 = call arm_apcscc i32 @"\01_fwrite"(i8* getelementptr ([11 x i8]* @.str1842948, i32 0, i32 0), i32 1, i32 10, i8* undef) nounwind ; [#uses=0] + %25 = call i32 @"\01_fwrite"(i8* getelementptr ([11 x i8]* @.str1842948, i32 0, i32 0), i32 1, i32 10, i8* undef) nounwind ; [#uses=0] %26 = sub i32 %rowmark, undef ; [#uses=1] %27 = load %struct.FILE** @out_fp, align 4 ; <%struct.FILE*> [#uses=1] - %28 = call arm_apcscc i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* %27, i8* getelementptr ([17 x i8]* @.str212784, i32 0, i32 0), i32 undef, i32 %26) nounwind ; [#uses=0] + %28 = call i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* %27, i8* getelementptr ([17 x i8]* @.str212784, i32 0, i32 0), i32 undef, i32 %26) nounwind ; [#uses=0] store i32 0, i32* @cpexists, align 4 - %29 = call arm_apcscc i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* undef, i8* getelementptr ([17 x i8]* @.str192782, i32 0, i32 0), double 2.000000e+01, double 2.000000e+01) nounwind ; [#uses=0] + %29 = call i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* undef, i8* getelementptr ([17 x i8]* @.str192782, i32 0, i32 0), double 2.000000e+01, double 2.000000e+01) nounwind ; [#uses=0] %30 = getelementptr %struct.rec* %y.0, i32 0, i32 0, i32 3, i32 0, i32 0, i32 0 ; [#uses=1] %31 = load i32* %30, align 4 ; [#uses=1] %32 = sub i32 0, %31 ; [#uses=1] %33 = load i32* undef, align 4 ; [#uses=1] %34 = sub i32 0, %33 ; [#uses=1] %35 = load %struct.FILE** @out_fp, align 4 ; <%struct.FILE*> [#uses=1] - %36 = call arm_apcscc i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* %35, i8* getelementptr ([17 x i8]* @.str212784, i32 0, i32 0), i32 %32, i32 %34) nounwind ; [#uses=0] + %36 = call i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* %35, i8* getelementptr ([17 x i8]* @.str212784, i32 0, i32 0), i32 %32, i32 %34) nounwind ; [#uses=0] store i32 0, i32* @cpexists, align 4 %37 = load %struct.rec** null, align 4 ; <%struct.rec*> [#uses=1] %38 = getelementptr %struct.rec* %37, i32 0, i32 0, i32 4 ; <%struct.FOURTH_UNION*> [#uses=1] - %39 = call arm_apcscc i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* undef, i8* getelementptr ([23 x i8]* @.str1852949, i32 0, i32 0), %struct.FOURTH_UNION* %38) nounwind ; [#uses=0] + %39 = call i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* undef, i8* getelementptr ([23 x i8]* @.str1852949, i32 0, i32 0), %struct.FOURTH_UNION* %38) nounwind ; [#uses=0] %buff14 = getelementptr [512 x i8]* %buff, i32 0, i32 0 ; [#uses=5] - %40 = call arm_apcscc i8* @fgets(i8* %buff14, i32 512, %struct.FILE* %12) nounwind ; [#uses=0] + %40 = call i8* @fgets(i8* %buff14, i32 512, %struct.FILE* %12) nounwind ; [#uses=0] %iftmp.506.0 = select i1 undef, i32 2, i32 0 ; [#uses=1] %41 = getelementptr [512 x i8]* %buff, i32 0, i32 26 ; [#uses=1] br label %bb100.outer.outer @@ -230,7 +230,7 @@ br i1 %50, label %bb24, label %bb2.i.i68 bb24: ; preds = %bb3.i77 - %51 = call arm_apcscc %struct.rec* @MakeWord(i32 11, i8* %41, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*)) nounwind ; <%struct.rec*> [#uses=0] + %51 = call %struct.rec* @MakeWord(i32 11, i8* %41, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*)) nounwind ; <%struct.rec*> [#uses=0] %52 = load i8* getelementptr ([150 x i8]* @zz_lengths, i32 0, i32 0), align 4 ; [#uses=1] %53 = zext i8 %52 to i32 ; [#uses=2] %54 = getelementptr [524 x %struct.rec*]* @zz_free, i32 0, i32 %53 ; <%struct.rec**> [#uses=2] @@ -245,7 +245,7 @@ br i1 undef, label %bb1.i58, label %bb2.i60 bb1.i58: ; preds = %bb.i56 - call arm_apcscc void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 31, i32 1, i8* getelementptr ([32 x i8]* @.str1575, i32 0, i32 0), i32 1, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*)) nounwind + call void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 31, i32 1, i8* getelementptr ([32 x i8]* @.str1575, i32 0, i32 0), i32 1, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*)) nounwind br label %bb2.i60 bb2.i60: ; preds = %bb1.i58, %bb.i56 @@ -287,7 +287,7 @@ br label %bb41 bb41: ; preds = %bb37, %bb35 - %61 = call arm_apcscc i8* @fgets(i8* %buff14, i32 512, %struct.FILE* %12) nounwind ; [#uses=1] + %61 = call i8* @fgets(i8* %buff14, i32 512, %struct.FILE* %12) nounwind ; [#uses=1] %62 = icmp eq i8* %61, null ; [#uses=1] %iftmp.554.0 = select i1 %62, i32 2, i32 1 ; [#uses=1] br label %bb100.outer @@ -342,11 +342,11 @@ br i1 undef, label %bb2.i6.i26, label %bb55 bb55: ; preds = %bb2.i6.i26 - %69 = call arm_apcscc i32 @"\01_fputs"(i8* %buff14, %struct.FILE* undef) nounwind ; [#uses=0] + %69 = call i32 @"\01_fputs"(i8* %buff14, %struct.FILE* undef) nounwind ; [#uses=0] unreachable bb58: ; preds = %StringBeginsWith.exit.i20 - %70 = call arm_apcscc i8* @fgets(i8* %buff14, i32 512, %struct.FILE* %12) nounwind ; [#uses=0] + %70 = call i8* @fgets(i8* %buff14, i32 512, %struct.FILE* %12) nounwind ; [#uses=0] %iftmp.560.0 = select i1 undef, i32 2, i32 0 ; [#uses=1] br label %bb100.outer @@ -367,7 +367,7 @@ br i1 %phitmp93, label %bb66, label %bb2.i.i bb66: ; preds = %StringBeginsWith.exit - %71 = call arm_apcscc %struct.rec* @MakeWord(i32 11, i8* undef, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*)) nounwind ; <%struct.rec*> [#uses=4] + %71 = call %struct.rec* @MakeWord(i32 11, i8* undef, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*)) nounwind ; <%struct.rec*> [#uses=4] %72 = load i8* getelementptr ([150 x i8]* @zz_lengths, i32 0, i32 0), align 4 ; [#uses=1] %73 = zext i8 %72 to i32 ; [#uses=2] %74 = getelementptr [524 x %struct.rec*]* @zz_free, i32 0, i32 %73 ; <%struct.rec**> [#uses=2] @@ -379,13 +379,13 @@ br i1 undef, label %bb.i2, label %GetMemory.exit bb.i2: ; preds = %bb69 - %77 = call arm_apcscc noalias i8* @calloc(i32 1020, i32 4) nounwind ; [#uses=1] + %77 = call noalias i8* @calloc(i32 1020, i32 4) nounwind ; [#uses=1] %78 = bitcast i8* %77 to i8** ; [#uses=3] store i8** %78, i8*** @next_free.4772, align 4 br i1 undef, label %bb1.i3, label %bb2.i4 bb1.i3: ; preds = %bb.i2 - call arm_apcscc void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 31, i32 1, i8* getelementptr ([32 x i8]* @.str1575, i32 0, i32 0), i32 1, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*)) nounwind + call void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 31, i32 1, i8* getelementptr ([32 x i8]* @.str1575, i32 0, i32 0), i32 1, %struct.FILE_POS* bitcast (%4* @no_file_pos to %struct.FILE_POS*)) nounwind br label %bb2.i4 bb2.i4: ; preds = %bb1.i3, %bb.i2 @@ -482,7 +482,7 @@ unreachable bb94: ; preds = %strip_out.exit, %StringBeginsWith.exit.i - %96 = call arm_apcscc i8* @fgets(i8* %buff14, i32 512, %struct.FILE* %12) nounwind ; [#uses=0] + %96 = call i8* @fgets(i8* %buff14, i32 512, %struct.FILE* %12) nounwind ; [#uses=0] unreachable bb100.outer: ; preds = %bb58, %bb41, %bb100.outer.outer @@ -497,12 +497,12 @@ br i1 %97, label %bb103, label %bb102 bb102: ; preds = %bb101.split - %98 = call arm_apcscc i32 @remove(i8* getelementptr ([9 x i8]* @.str19294, i32 0, i32 0)) nounwind ; [#uses=0] + %98 = call i32 @remove(i8* getelementptr ([9 x i8]* @.str19294, i32 0, i32 0)) nounwind ; [#uses=0] unreachable bb103: ; preds = %bb101.split %99 = load %struct.FILE** @out_fp, align 4 ; <%struct.FILE*> [#uses=1] - %100 = call arm_apcscc i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* %99, i8* getelementptr ([26 x i8]* @.str1932957, i32 0, i32 0)) nounwind ; [#uses=0] + %100 = call i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* %99, i8* getelementptr ([26 x i8]* @.str1932957, i32 0, i32 0)) nounwind ; [#uses=0] store i32 0, i32* @wordcount, align 4 ret void } Modified: llvm/trunk/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll Thu Jun 17 10:18:27 2010 @@ -8,7 +8,7 @@ %struct.Results = type { float, float, float } %struct.Village = type { [4 x %struct.Village*], %struct.Village*, %struct.List, %struct.Hosp, i32, i32 } -define arm_apcscc void @get_results(%struct.Results* noalias nocapture sret %agg.result, %struct.Village* %village) nounwind { +define void @get_results(%struct.Results* noalias nocapture sret %agg.result, %struct.Village* %village) nounwind { entry: br i1 undef, label %bb, label %bb6.preheader Modified: llvm/trunk/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug2.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug2.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug2.ll Thu Jun 17 10:18:27 2010 @@ -6,7 +6,7 @@ %struct.Patient = type { i32, i32, i32, %struct.Village* } %struct.Village = type { [4 x %struct.Village*], %struct.Village*, %struct.List, %struct.Hosp, i32, i32 } -define arm_apcscc %struct.List* @sim(%struct.Village* %village) nounwind { +define %struct.List* @sim(%struct.Village* %village) nounwind { entry: br i1 undef, label %bb14, label %bb3.preheader Modified: llvm/trunk/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug3.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug3.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug3.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug3.ll Thu Jun 17 10:18:27 2010 @@ -6,7 +6,7 @@ %struct.Patient = type { i32, i32, i32, %struct.Village* } %struct.Village = type { [4 x %struct.Village*], %struct.Village*, %struct.List, %struct.Hosp, i32, i32 } -define arm_apcscc %struct.List* @sim(%struct.Village* %village) nounwind { +define %struct.List* @sim(%struct.Village* %village) nounwind { entry: br i1 undef, label %bb14, label %bb3.preheader Modified: llvm/trunk/test/CodeGen/Thumb2/2009-08-07-NeonFPBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-08-07-NeonFPBug.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2009-08-07-NeonFPBug.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2009-08-07-NeonFPBug.ll Thu Jun 17 10:18:27 2010 @@ -28,7 +28,7 @@ %struct.jvirt_barray_control = type { [64 x i16]**, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.jvirt_barray_control*, %struct.backing_store_info } %struct.jvirt_sarray_control = type { i8**, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.jvirt_sarray_control*, %struct.backing_store_info } -define arm_apcscc void @jpeg_idct_float(%struct.jpeg_decompress_struct* nocapture %cinfo, %struct.jpeg_component_info* nocapture %compptr, i16* nocapture %coef_block, i8** nocapture %output_buf, i32 %output_col) nounwind { +define void @jpeg_idct_float(%struct.jpeg_decompress_struct* nocapture %cinfo, %struct.jpeg_component_info* nocapture %compptr, i16* nocapture %coef_block, i8** nocapture %output_buf, i32 %output_col) nounwind { entry: br label %bb Modified: llvm/trunk/test/CodeGen/Thumb2/2009-08-10-ISelBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-08-10-ISelBug.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2009-08-10-ISelBug.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2009-08-10-ISelBug.ll Thu Jun 17 10:18:27 2010 @@ -1,6 +1,6 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+vfp2 -define arm_apcscc float @t1(i32 %v0) nounwind { +define float @t1(i32 %v0) nounwind { entry: store i32 undef, i32* undef, align 4 %0 = load [4 x i8]** undef, align 4 ; <[4 x i8]*> [#uses=1] Modified: llvm/trunk/test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll Thu Jun 17 10:18:27 2010 @@ -4,7 +4,7 @@ @getNeighbour = external global void (i32, i32, i32, i32, %struct.pix_pos*)*, align 4 ; [#uses=2] -define arm_apcscc void @t() nounwind { +define void @t() nounwind { ; CHECK: t: ; CHECK: it eq ; CHECK-NEXT: cmpeq @@ -47,12 +47,12 @@ %tmp14.i302 = load i32* undef ; [#uses=4] %add.i307452 = or i32 %shl1959, 1 ; [#uses=1] %sub.i308 = add i32 %shl, -1 ; [#uses=4] - call arm_apcscc void undef(i32 %tmp14.i302, i32 %sub.i308, i32 %shl1959, i32 0, %struct.pix_pos* undef) nounwind + call void undef(i32 %tmp14.i302, i32 %sub.i308, i32 %shl1959, i32 0, %struct.pix_pos* undef) nounwind %tmp49.i309 = load void (i32, i32, i32, i32, %struct.pix_pos*)** @getNeighbour ; [#uses=1] - call arm_apcscc void %tmp49.i309(i32 %tmp14.i302, i32 %sub.i308, i32 %add.i307452, i32 0, %struct.pix_pos* null) nounwind + call void %tmp49.i309(i32 %tmp14.i302, i32 %sub.i308, i32 %add.i307452, i32 0, %struct.pix_pos* null) nounwind %tmp49.1.i = load void (i32, i32, i32, i32, %struct.pix_pos*)** @getNeighbour ; [#uses=1] - call arm_apcscc void %tmp49.1.i(i32 %tmp14.i302, i32 %sub.i308, i32 undef, i32 0, %struct.pix_pos* %arrayidx56.2.i) nounwind - call arm_apcscc void undef(i32 %tmp14.i302, i32 %sub.i308, i32 undef, i32 0, %struct.pix_pos* %arrayidx56.3.i) nounwind + call void %tmp49.1.i(i32 %tmp14.i302, i32 %sub.i308, i32 undef, i32 0, %struct.pix_pos* %arrayidx56.2.i) nounwind + call void undef(i32 %tmp14.i302, i32 %sub.i308, i32 undef, i32 0, %struct.pix_pos* %arrayidx56.3.i) nounwind unreachable if.else2003: ; preds = %for.body1940 Modified: llvm/trunk/test/CodeGen/Thumb2/2009-11-01-CopyReg2RegBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-11-01-CopyReg2RegBug.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2009-11-01-CopyReg2RegBug.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2009-11-01-CopyReg2RegBug.ll Thu Jun 17 10:18:27 2010 @@ -1,6 +1,6 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=pic -disable-fp-elim -mcpu=cortex-a8 -define arm_apcscc void @get_initial_mb16x16_cost() nounwind { +define void @get_initial_mb16x16_cost() nounwind { entry: br i1 undef, label %bb4, label %bb1 Modified: llvm/trunk/test/CodeGen/Thumb2/2009-11-11-ScavengerAssert.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-11-11-ScavengerAssert.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2009-11-11-ScavengerAssert.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2009-11-11-ScavengerAssert.ll Thu Jun 17 10:18:27 2010 @@ -3,9 +3,9 @@ %struct.OP = type { %struct.OP*, %struct.OP*, %struct.OP* ()*, i32, i16, i16, i8, i8 } %struct.SV = type { i8*, i32, i32 } -declare arm_apcscc void @Perl_mg_set(%struct.SV*) nounwind +declare void @Perl_mg_set(%struct.SV*) nounwind -define arm_apcscc %struct.OP* @Perl_pp_complement() nounwind { +define %struct.OP* @Perl_pp_complement() nounwind { entry: %0 = load %struct.SV** null, align 4 ; <%struct.SV*> [#uses=2] br i1 undef, label %bb21, label %bb5 @@ -23,7 +23,7 @@ %4 = bitcast i8* %3 to i32* ; [#uses=1] %5 = load i32* %4, align 4 ; [#uses=1] %storemerge5 = xor i32 %5, -1 ; [#uses=1] - call arm_apcscc void @Perl_sv_setiv(%struct.SV* undef, i32 %storemerge5) nounwind + call void @Perl_sv_setiv(%struct.SV* undef, i32 %storemerge5) nounwind %6 = getelementptr inbounds %struct.SV* undef, i32 0, i32 2 ; [#uses=1] %7 = load i32* %6, align 4 ; [#uses=1] %8 = and i32 %7, 16384 ; [#uses=1] @@ -34,7 +34,7 @@ unreachable bb11: ; preds = %bb7 - call arm_apcscc void @Perl_mg_set(%struct.SV* undef) nounwind + call void @Perl_mg_set(%struct.SV* undef) nounwind br label %bb12 bb12: ; preds = %bb11, %bb7 @@ -42,11 +42,11 @@ br label %bb44 bb13: ; preds = %bb5 - %10 = call arm_apcscc i32 @Perl_sv_2uv(%struct.SV* %0) nounwind ; [#uses=0] + %10 = call i32 @Perl_sv_2uv(%struct.SV* %0) nounwind ; [#uses=0] br i1 undef, label %bb.i, label %bb1.i bb.i: ; preds = %bb13 - call arm_apcscc void @Perl_sv_setiv(%struct.SV* undef, i32 undef) nounwind + call void @Perl_sv_setiv(%struct.SV* undef, i32 undef) nounwind br label %Perl_sv_setuv.exit bb1.i: ; preds = %bb13 @@ -60,7 +60,7 @@ br i1 %14, label %bb20, label %bb19 bb19: ; preds = %Perl_sv_setuv.exit - call arm_apcscc void @Perl_mg_set(%struct.SV* undef) nounwind + call void @Perl_mg_set(%struct.SV* undef) nounwind br label %bb20 bb20: ; preds = %bb19, %Perl_sv_setuv.exit @@ -80,6 +80,6 @@ ret %struct.OP* undef } -declare arm_apcscc void @Perl_sv_setiv(%struct.SV*, i32) nounwind +declare void @Perl_sv_setiv(%struct.SV*, i32) nounwind -declare arm_apcscc i32 @Perl_sv_2uv(%struct.SV*) nounwind +declare i32 @Perl_sv_2uv(%struct.SV*) nounwind Modified: llvm/trunk/test/CodeGen/Thumb2/2009-11-13-STRDBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-11-13-STRDBug.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2009-11-13-STRDBug.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2009-11-13-STRDBug.ll Thu Jun 17 10:18:27 2010 @@ -1,7 +1,7 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 ; rdar://7394794 -define arm_apcscc void @lshift_double(i64 %l1, i64 %h1, i64 %count, i32 %prec, i64* nocapture %lv, i64* nocapture %hv, i32 %arith) nounwind { +define void @lshift_double(i64 %l1, i64 %h1, i64 %count, i32 %prec, i64* nocapture %lv, i64* nocapture %hv, i32 %arith) nounwind { entry: %..i = select i1 false, i64 0, i64 0 ; [#uses=1] br i1 undef, label %bb11.i, label %bb6.i Modified: llvm/trunk/test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll Thu Jun 17 10:18:27 2010 @@ -1,7 +1,7 @@ ; RUN: opt < %s -std-compile-opts | \ ; RUN: llc -mtriple=thumbv7-apple-darwin10 -mattr=+neon | FileCheck %s -define arm_apcscc void @fred(i32 %three_by_three, i8* %in, double %dt1, i32 %x_size, i32 %y_size, i8* %bp) nounwind { +define void @fred(i32 %three_by_three, i8* %in, double %dt1, i32 %x_size, i32 %y_size, i8* %bp) nounwind { entry: ; -- The loop following the load should only use a single add-literation ; instruction. @@ -45,7 +45,7 @@ store i8* %bp, i8** %bp_addr %0 = load i8** %in_addr, align 4 ; [#uses=1] store i8* %0, i8** %out, align 4 - %1 = call arm_apcscc i32 (...)* @foo() nounwind ; [#uses=1] + %1 = call i32 (...)* @foo() nounwind ; [#uses=1] store i32 %1, i32* %i, align 4 %2 = load i32* %three_by_three_addr, align 4 ; [#uses=1] %3 = icmp eq i32 %2, 0 ; [#uses=1] @@ -76,7 +76,7 @@ %15 = load i32* %n_max, align 4 ; [#uses=1] %16 = load i32* %n_max, align 4 ; [#uses=1] %17 = mul i32 %15, %16 ; [#uses=1] - %18 = call arm_apcscc noalias i8* @malloc(i32 %17) nounwind ; [#uses=1] + %18 = call noalias i8* @malloc(i32 %17) nounwind ; [#uses=1] store i8* %18, i8** %dp, align 4 %19 = load i8** %dp, align 4 ; [#uses=1] store i8* %19, i8** %dpt, align 4 @@ -123,6 +123,6 @@ ret void } -declare arm_apcscc i32 @foo(...) +declare i32 @foo(...) -declare arm_apcscc noalias i8* @malloc(i32) nounwind +declare noalias i8* @malloc(i32) nounwind Modified: llvm/trunk/test/CodeGen/Thumb2/2010-01-06-TailDuplicateLabels.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2010-01-06-TailDuplicateLabels.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2010-01-06-TailDuplicateLabels.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2010-01-06-TailDuplicateLabels.ll Thu Jun 17 10:18:27 2010 @@ -17,14 +17,14 @@ @_ZN3WTFL12thread_heapsE = internal global %"struct.WTF::TCMalloc_ThreadCache"* null ; <%"struct.WTF::TCMalloc_ThreadCache"**> [#uses=1] @llvm.used = appending global [1 x i8*] [i8* bitcast (%"struct.WTF::TCMalloc_ThreadCache"* ()* @_ZN3WTF20TCMalloc_ThreadCache22CreateCacheIfNecessaryEv to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] -define arm_apcscc %"struct.WTF::TCMalloc_ThreadCache"* @_ZN3WTF20TCMalloc_ThreadCache22CreateCacheIfNecessaryEv() nounwind { +define %"struct.WTF::TCMalloc_ThreadCache"* @_ZN3WTF20TCMalloc_ThreadCache22CreateCacheIfNecessaryEv() nounwind { entry: - %0 = tail call arm_apcscc i32 @pthread_mutex_lock(%struct.PlatformMutex* getelementptr inbounds (%struct.SpinLock* @_ZN3WTFL13pageheap_lockE, i32 0, i32 0)) nounwind + %0 = tail call i32 @pthread_mutex_lock(%struct.PlatformMutex* getelementptr inbounds (%struct.SpinLock* @_ZN3WTFL13pageheap_lockE, i32 0, i32 0)) nounwind %.b24 = load i1* @_ZN3WTFL10tsd_initedE.b, align 4 ; [#uses=1] br i1 %.b24, label %bb5, label %bb6 bb5: ; preds = %entry - %1 = tail call arm_apcscc %struct._opaque_pthread_t* @pthread_self() nounwind + %1 = tail call %struct._opaque_pthread_t* @pthread_self() nounwind br label %bb6 bb6: ; preds = %bb5, %entry @@ -34,7 +34,7 @@ bb7: ; preds = %bb11 %2 = getelementptr inbounds %"struct.WTF::TCMalloc_ThreadCache"* %h.0, i32 0, i32 1 %3 = load %struct._opaque_pthread_t** %2, align 4 - %4 = tail call arm_apcscc i32 @pthread_equal(%struct._opaque_pthread_t* %3, %struct._opaque_pthread_t* %me.0) nounwind + %4 = tail call i32 @pthread_equal(%struct._opaque_pthread_t* %3, %struct._opaque_pthread_t* %me.0) nounwind %5 = icmp eq i32 %4, 0 br i1 %5, label %bb10, label %bb14 @@ -49,12 +49,12 @@ br i1 %7, label %bb13, label %bb7 bb13: ; preds = %bb11 - %8 = tail call arm_apcscc %"struct.WTF::TCMalloc_ThreadCache"* @_ZN3WTF20TCMalloc_ThreadCache7NewHeapEP17_opaque_pthread_t(%struct._opaque_pthread_t* %me.0) nounwind + %8 = tail call %"struct.WTF::TCMalloc_ThreadCache"* @_ZN3WTF20TCMalloc_ThreadCache7NewHeapEP17_opaque_pthread_t(%struct._opaque_pthread_t* %me.0) nounwind br label %bb14 bb14: ; preds = %bb13, %bb7 %heap.1 = phi %"struct.WTF::TCMalloc_ThreadCache"* [ %8, %bb13 ], [ %h.0, %bb7 ] ; <%"struct.WTF::TCMalloc_ThreadCache"*> [#uses=4] - %9 = tail call arm_apcscc i32 @pthread_mutex_unlock(%struct.PlatformMutex* getelementptr inbounds (%struct.SpinLock* @_ZN3WTFL13pageheap_lockE, i32 0, i32 0)) nounwind + %9 = tail call i32 @pthread_mutex_unlock(%struct.PlatformMutex* getelementptr inbounds (%struct.SpinLock* @_ZN3WTFL13pageheap_lockE, i32 0, i32 0)) nounwind %10 = getelementptr inbounds %"struct.WTF::TCMalloc_ThreadCache"* %heap.1, i32 0, i32 2 %11 = load i8* %10, align 4 %toBool15not = icmp eq i8 %11, 0 ; [#uses=1] @@ -68,22 +68,22 @@ store i8 1, i8* %10, align 4 %12 = load i32* @_ZN3WTFL8heap_keyE, align 4 %13 = bitcast %"struct.WTF::TCMalloc_ThreadCache"* %heap.1 to i8* - %14 = tail call arm_apcscc i32 @pthread_setspecific(i32 %12, i8* %13) nounwind + %14 = tail call i32 @pthread_setspecific(i32 %12, i8* %13) nounwind ret %"struct.WTF::TCMalloc_ThreadCache"* %heap.1 bb22: ; preds = %bb19, %bb14 ret %"struct.WTF::TCMalloc_ThreadCache"* %heap.1 } -declare arm_apcscc i32 @pthread_mutex_lock(%struct.PlatformMutex*) +declare i32 @pthread_mutex_lock(%struct.PlatformMutex*) -declare arm_apcscc i32 @pthread_mutex_unlock(%struct.PlatformMutex*) +declare i32 @pthread_mutex_unlock(%struct.PlatformMutex*) -declare hidden arm_apcscc %"struct.WTF::TCMalloc_ThreadCache"* @_ZN3WTF20TCMalloc_ThreadCache7NewHeapEP17_opaque_pthread_t(%struct._opaque_pthread_t*) nounwind +declare hidden %"struct.WTF::TCMalloc_ThreadCache"* @_ZN3WTF20TCMalloc_ThreadCache7NewHeapEP17_opaque_pthread_t(%struct._opaque_pthread_t*) nounwind -declare arm_apcscc i32 @pthread_setspecific(i32, i8*) +declare i32 @pthread_setspecific(i32, i8*) -declare arm_apcscc %struct._opaque_pthread_t* @pthread_self() +declare %struct._opaque_pthread_t* @pthread_self() -declare arm_apcscc i32 @pthread_equal(%struct._opaque_pthread_t*, %struct._opaque_pthread_t*) +declare i32 @pthread_equal(%struct._opaque_pthread_t*, %struct._opaque_pthread_t*) Modified: llvm/trunk/test/CodeGen/Thumb2/2010-01-19-RemovePredicates.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2010-01-19-RemovePredicates.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2010-01-19-RemovePredicates.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2010-01-19-RemovePredicates.ll Thu Jun 17 10:18:27 2010 @@ -6,16 +6,16 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32" target triple = "thumbv7-apple-darwin10" -declare arm_apcscc void @etoe53(i16* nocapture, i16* nocapture) nounwind +declare void @etoe53(i16* nocapture, i16* nocapture) nounwind -define arm_apcscc void @earith(double* nocapture %value, i32 %icode, double* nocapture %r1, double* nocapture %r2) nounwind { +define void @earith(double* nocapture %value, i32 %icode, double* nocapture %r1, double* nocapture %r2) nounwind { entry: %v = alloca [6 x i16], align 4 ; <[6 x i16]*> [#uses=1] br i1 undef, label %bb2.i, label %bb5 bb2.i: ; preds = %entry %0 = bitcast double* %value to i16* ; [#uses=1] - call arm_apcscc void @etoe53(i16* null, i16* %0) nounwind + call void @etoe53(i16* null, i16* %0) nounwind ret void bb5: ; preds = %entry @@ -48,6 +48,6 @@ bb46: ; preds = %bb26, %bb10 %1 = bitcast double* %value to i16* ; [#uses=1] %v47 = getelementptr inbounds [6 x i16]* %v, i32 0, i32 0 ; [#uses=1] - call arm_apcscc void @etoe53(i16* %v47, i16* %1) nounwind + call void @etoe53(i16* %v47, i16* %1) nounwind ret void } Modified: llvm/trunk/test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll Thu Jun 17 10:18:27 2010 @@ -1,7 +1,7 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32" -define arm_apcscc i32 @test(i32 %n) nounwind { +define i32 @test(i32 %n) nounwind { ; CHECK: test: ; CHECK-NOT: mov ; CHECK: return @@ -16,11 +16,11 @@ bb: ; preds = %bb.nph, %bb %indvar = phi i32 [ 0, %bb.nph ], [ %indvar.next, %bb ] ; [#uses=1] %u.05 = phi i64 [ undef, %bb.nph ], [ %ins, %bb ] ; [#uses=1] - %1 = tail call arm_apcscc i32 @f() nounwind ; [#uses=1] + %1 = tail call i32 @f() nounwind ; [#uses=1] %tmp4 = zext i32 %1 to i64 ; [#uses=1] %mask = and i64 %u.05, -4294967296 ; [#uses=1] %ins = or i64 %tmp4, %mask ; [#uses=2] - tail call arm_apcscc void @g(i64 %ins) nounwind + tail call void @g(i64 %ins) nounwind %indvar.next = add i32 %indvar, 1 ; [#uses=2] %exitcond = icmp eq i32 %indvar.next, %tmp ; [#uses=1] br i1 %exitcond, label %return, label %bb @@ -29,7 +29,7 @@ ret i32 undef } -define arm_apcscc i32 @test_dead_cycle(i32 %n) nounwind { +define i32 @test_dead_cycle(i32 %n) nounwind { ; CHECK: test_dead_cycle: ; CHECK: blx ; CHECK-NOT: mov @@ -50,11 +50,11 @@ br i1 %1, label %bb1, label %bb2 bb1: ; preds = %bb - %2 = tail call arm_apcscc i32 @f() nounwind ; [#uses=1] + %2 = tail call i32 @f() nounwind ; [#uses=1] %tmp6 = zext i32 %2 to i64 ; [#uses=1] %mask = and i64 %u.17, -4294967296 ; [#uses=1] %ins = or i64 %tmp6, %mask ; [#uses=1] - tail call arm_apcscc void @g(i64 %ins) nounwind + tail call void @g(i64 %ins) nounwind br label %bb2 bb2: ; preds = %bb1, %bb @@ -71,6 +71,6 @@ ret i32 undef } -declare arm_apcscc i32 @f() +declare i32 @f() -declare arm_apcscc void @g(i64) +declare void @g(i64) Modified: llvm/trunk/test/CodeGen/Thumb2/2010-02-24-BigStack.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2010-02-24-BigStack.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2010-02-24-BigStack.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2010-02-24-BigStack.ll Thu Jun 17 10:18:27 2010 @@ -4,7 +4,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32" target triple = "thumbv7-apple-darwin3.0.0-iphoneos" -define arm_apcscc void @FindMin(double* %panelTDEL, i8* %dclOfRow, i32 %numRows, i32 %numCols, double* %retMin_RES_TDEL) { +define void @FindMin(double* %panelTDEL, i8* %dclOfRow, i32 %numRows, i32 %numCols, double* %retMin_RES_TDEL) { entry: %panelTDEL.addr = alloca double*, align 4 ; [#uses=1] %panelResTDEL = alloca [2560 x double], align 4 ; <[2560 x double]*> [#uses=0] Modified: llvm/trunk/test/CodeGen/Thumb2/2010-03-08-addi12-ccout.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2010-03-08-addi12-ccout.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2010-03-08-addi12-ccout.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2010-03-08-addi12-ccout.ll Thu Jun 17 10:18:27 2010 @@ -2,13 +2,13 @@ @.str41196 = external constant [2 x i8], align 4 ; <[2 x i8]*> [#uses=1] -declare arm_apcscc void @syStopraw(i32) nounwind +declare void @syStopraw(i32) nounwind -declare arm_apcscc i32 @SyFopen(i8*, i8*) nounwind +declare i32 @SyFopen(i8*, i8*) nounwind -declare arm_apcscc i8* @SyFgets(i8*, i32) nounwind +declare i8* @SyFgets(i8*, i32) nounwind -define arm_apcscc void @SyHelp(i8* nocapture %topic, i32 %fin) nounwind { +define void @SyHelp(i8* nocapture %topic, i32 %fin) nounwind { entry: %line = alloca [256 x i8], align 4 ; <[256 x i8]*> [#uses=1] %secname = alloca [1024 x i8], align 4 ; <[1024 x i8]*> [#uses=0] @@ -70,7 +70,7 @@ unreachable bb224: ; preds = %bb162 - %0 = call arm_apcscc i32 @SyFopen(i8* undef, i8* getelementptr inbounds ([2 x i8]* @.str41196, i32 0, i32 0)) nounwind ; [#uses=2] + %0 = call i32 @SyFopen(i8* undef, i8* getelementptr inbounds ([2 x i8]* @.str41196, i32 0, i32 0)) nounwind ; [#uses=2] br i1 false, label %bb297, label %bb300 bb297: ; preds = %bb224 @@ -177,7 +177,7 @@ br i1 undef, label %bb373, label %bb388 bb373: ; preds = %bb383, %bb369 - %7 = call arm_apcscc i8* @SyFgets(i8* undef, i32 %0) nounwind ; [#uses=1] + %7 = call i8* @SyFgets(i8* undef, i32 %0) nounwind ; [#uses=1] %8 = icmp eq i8* %7, null ; [#uses=1] br i1 %8, label %bb375, label %bb383 @@ -241,7 +241,7 @@ br i1 undef, label %return, label %bb406 bb406: ; preds = %bb405 - call arm_apcscc void @syStopraw(i32 %fin) nounwind + call void @syStopraw(i32 %fin) nounwind ret void bb407: ; preds = %bb404 @@ -255,7 +255,7 @@ br label %bb440 bb440: ; preds = %bb428, %bb300 - %13 = call arm_apcscc i8* @SyFgets(i8* undef, i32 %0) nounwind ; [#uses=0] + %13 = call i8* @SyFgets(i8* undef, i32 %0) nounwind ; [#uses=0] br i1 false, label %bb442, label %bb308 bb442: ; preds = %bb440 Modified: llvm/trunk/test/CodeGen/Thumb2/2010-03-15-AsmCCClobber.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2010-03-15-AsmCCClobber.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2010-03-15-AsmCCClobber.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2010-03-15-AsmCCClobber.ll Thu Jun 17 10:18:27 2010 @@ -13,7 +13,7 @@ ; CHECK: InlineAsm End ; CHECK: cmp ; CHECK: beq -define arm_apcscc void @test(%s1* %this, i32 %format, i32 %w, i32 %h, i32 %levels, i32* %s, i8* %data, i32* nocapture %rowbytes, void (i8*, i8*)* %release, i8* %info) nounwind { +define void @test(%s1* %this, i32 %format, i32 %w, i32 %h, i32 %levels, i32* %s, i8* %data, i32* nocapture %rowbytes, void (i8*, i8*)* %release, i8* %info) nounwind { entry: %tmp1 = getelementptr inbounds %s1* %this, i32 0, i32 0, i32 0, i32 1, i32 0, i32 0 volatile store i32 1, i32* %tmp1, align 4 @@ -32,9 +32,9 @@ %tmp19 = getelementptr inbounds %s1* %this, i32 0, i32 10 store i64 0, i64* %tmp19, align 4 %tmp20 = getelementptr inbounds %s1* %this, i32 0, i32 0 - tail call arm_apcscc void @f1(%s3* %tmp20, i32* %s) nounwind + tail call void @f1(%s3* %tmp20, i32* %s) nounwind %tmp21 = shl i32 %format, 6 - %tmp22 = tail call arm_apcscc zeroext i8 @f2(i32 %format) nounwind + %tmp22 = tail call zeroext i8 @f2(i32 %format) nounwind %toBoolnot = icmp eq i8 %tmp22, 0 %tmp23 = zext i1 %toBoolnot to i32 %flags.0 = or i32 %tmp23, %tmp21 @@ -59,5 +59,5 @@ ret void } -declare arm_apcscc void @f1(%s3*, i32*) -declare arm_apcscc zeroext i8 @f2(i32) +declare void @f1(%s3*, i32*) +declare zeroext i8 @f2(i32) Modified: llvm/trunk/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll Thu Jun 17 10:18:27 2010 @@ -4,7 +4,7 @@ ; Make sure the result of the first dynamic_alloc isn't copied back to sp more ; than once. We'll deal with poor codegen later. -define arm_apcscc void @t() nounwind ssp { +define void @t() nounwind ssp { entry: ; CHECK: t: ; CHECK: mov r0, sp Modified: llvm/trunk/test/CodeGen/Thumb2/2010-04-26-CopyRegCrash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2010-04-26-CopyRegCrash.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2010-04-26-CopyRegCrash.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2010-04-26-CopyRegCrash.ll Thu Jun 17 10:18:27 2010 @@ -4,7 +4,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32" target triple = "thumbv7-apple-darwin10" -define arm_apcscc void @test(i32 %mode) nounwind optsize noinline { +define void @test(i32 %mode) nounwind optsize noinline { entry: br i1 undef, label %return, label %bb3 Modified: llvm/trunk/test/CodeGen/Thumb2/2010-05-24-rsbs.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2010-05-24-rsbs.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2010-05-24-rsbs.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2010-05-24-rsbs.ll Thu Jun 17 10:18:27 2010 @@ -2,7 +2,7 @@ ; Radar 8017376: Missing 's' suffix for t2RSBS instructions. ; CHECK: rsbs -define arm_apcscc i64 @test(i64 %x) nounwind readnone { +define i64 @test(i64 %x) nounwind readnone { entry: %0 = sub nsw i64 1, %x ; [#uses=1] ret i64 %0 Modified: llvm/trunk/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll Thu Jun 17 10:18:27 2010 @@ -12,7 +12,7 @@ @.str = private constant [7 x i8] c"%g %g\0A\00", align 4 ; <[7 x i8]*> [#uses=1] -define arm_apcscc i32 @main(i32 %argc, i8** nocapture %Argv) nounwind { +define i32 @main(i32 %argc, i8** nocapture %Argv) nounwind { entry: %0 = icmp eq i32 %argc, 2123 ; [#uses=1] %U.0 = select i1 %0, double 3.282190e+01, double 8.731834e+02 ; [#uses=2] @@ -31,11 +31,11 @@ %tmp7 = extractelement <2 x double> %5, i32 0 ; [#uses=1] %tmp5 = extractelement <2 x double> %5, i32 1 ; [#uses=1] ; CHECK: printf - %7 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([7 x i8]* @.str, i32 0, i32 0), double %tmp7, double %tmp5) nounwind ; [#uses=0] + %7 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([7 x i8]* @.str, i32 0, i32 0), double %tmp7, double %tmp5) nounwind ; [#uses=0] %tmp3 = extractelement <2 x double> %6, i32 0 ; [#uses=1] %tmp1 = extractelement <2 x double> %6, i32 1 ; [#uses=1] - %8 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([7 x i8]* @.str, i32 0, i32 0), double %tmp3, double %tmp1) nounwind ; [#uses=0] + %8 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([7 x i8]* @.str, i32 0, i32 0), double %tmp3, double %tmp1) nounwind ; [#uses=0] ret i32 0 } -declare arm_apcscc i32 @printf(i8* nocapture, ...) nounwind +declare i32 @printf(i8* nocapture, ...) nounwind Modified: llvm/trunk/test/CodeGen/Thumb2/cross-rc-coalescing-1.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/cross-rc-coalescing-1.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/cross-rc-coalescing-1.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/cross-rc-coalescing-1.ll Thu Jun 17 10:18:27 2010 @@ -4,9 +4,9 @@ %struct.__sFILEX = type opaque %struct.__sbuf = type { i8*, i32 } -declare arm_apcscc i32 @fgetc(%struct.FILE* nocapture) nounwind +declare i32 @fgetc(%struct.FILE* nocapture) nounwind -define arm_apcscc i32 @main(i32 %argc, i8** nocapture %argv) nounwind { +define i32 @main(i32 %argc, i8** nocapture %argv) nounwind { entry: br i1 undef, label %bb, label %bb1 @@ -20,7 +20,7 @@ unreachable bb1.i2: ; preds = %bb1 - %0 = call arm_apcscc i32 @fgetc(%struct.FILE* undef) nounwind ; [#uses=0] + %0 = call i32 @fgetc(%struct.FILE* undef) nounwind ; [#uses=0] br i1 undef, label %bb2.i3, label %bb3.i4 bb2.i3: ; preds = %bb1.i2 Modified: llvm/trunk/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll Thu Jun 17 10:18:27 2010 @@ -1,6 +1,6 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 | grep vmov.f32 | count 1 -define arm_apcscc void @fht(float* nocapture %fz, i16 signext %n) nounwind { +define void @fht(float* nocapture %fz, i16 signext %n) nounwind { entry: br label %bb5 Modified: llvm/trunk/test/CodeGen/Thumb2/frameless.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/frameless.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/frameless.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/frameless.ll Thu Jun 17 10:18:27 2010 @@ -1,6 +1,6 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -disable-fp-elim | not grep mov ; RUN: llc < %s -mtriple=thumbv7-linux -disable-fp-elim | not grep mov -define arm_apcscc void @t() nounwind readnone { +define void @t() nounwind readnone { ret void } Modified: llvm/trunk/test/CodeGen/Thumb2/frameless2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/frameless2.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/frameless2.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/frameless2.ll Thu Jun 17 10:18:27 2010 @@ -3,7 +3,7 @@ %struct.noise3 = type { [3 x [17 x i32]] } %struct.noiseguard = type { i32, i32, i32 } -define arm_apcscc void @vorbis_encode_noisebias_setup(i8* nocapture %vi.0.7.val, double %s, i32 %block, i32* nocapture %suppress, %struct.noise3* nocapture %in, %struct.noiseguard* nocapture %guard, double %userbias) nounwind { +define void @vorbis_encode_noisebias_setup(i8* nocapture %vi.0.7.val, double %s, i32 %block, i32* nocapture %suppress, %struct.noise3* nocapture %in, %struct.noiseguard* nocapture %guard, double %userbias) nounwind { entry: %0 = getelementptr %struct.noiseguard* %guard, i32 %block, i32 2; [#uses=1] %1 = load i32* %0, align 4 ; [#uses=1] Modified: llvm/trunk/test/CodeGen/Thumb2/ifcvt-neon.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/ifcvt-neon.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/ifcvt-neon.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/ifcvt-neon.ll Thu Jun 17 10:18:27 2010 @@ -4,7 +4,7 @@ @a = common global float 0.000000e+00 ; [#uses=2] @b = common global float 0.000000e+00 ; [#uses=1] -define arm_apcscc float @t(i32 %c) nounwind { +define float @t(i32 %c) nounwind { entry: %0 = icmp sgt i32 %c, 1 ; [#uses=1] %1 = load float* @a, align 4 ; [#uses=2] Modified: llvm/trunk/test/CodeGen/Thumb2/ldr-str-imm12.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/ldr-str-imm12.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/ldr-str-imm12.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/ldr-str-imm12.ll Thu Jun 17 10:18:27 2010 @@ -20,7 +20,7 @@ @zz_hold = external global %union.rec* ; <%union.rec**> [#uses=2] @zz_res = external global %union.rec* ; <%union.rec**> [#uses=1] -define arm_apcscc %union.rec* @Manifest(%union.rec* %x, %union.rec* %env, %struct.STYLE* %style, %union.rec** %bthr, %union.rec** %fthr, %union.rec** %target, %union.rec** %crs, i32 %ok, i32 %need_expand, %union.rec** %enclose, i32 %fcr) nounwind { +define %union.rec* @Manifest(%union.rec* %x, %union.rec* %env, %struct.STYLE* %style, %union.rec** %bthr, %union.rec** %fthr, %union.rec** %target, %union.rec** %crs, i32 %ok, i32 %need_expand, %union.rec** %enclose, i32 %fcr) nounwind { entry: ; CHECK: ldr.w r9, [r7, #28] %xgaps.i = alloca [32 x %union.rec*], align 4 ; <[32 x %union.rec*]*> [#uses=0] @@ -56,7 +56,7 @@ store %union.rec* null, %union.rec** @zz_hold, align 4 store %union.rec* null, %union.rec** @zz_res, align 4 store %union.rec* %x, %union.rec** @zz_hold, align 4 - %0 = call arm_apcscc %union.rec* @Manifest(%union.rec* undef, %union.rec* %env, %struct.STYLE* %style, %union.rec** %bthr, %union.rec** %fthr, %union.rec** %target, %union.rec** %crs, i32 %ok, i32 %need_expand, %union.rec** %enclose, i32 %fcr) nounwind ; <%union.rec*> [#uses=0] + %0 = call %union.rec* @Manifest(%union.rec* undef, %union.rec* %env, %struct.STYLE* %style, %union.rec** %bthr, %union.rec** %fthr, %union.rec** %target, %union.rec** %crs, i32 %ok, i32 %need_expand, %union.rec** %enclose, i32 %fcr) nounwind ; <%union.rec*> [#uses=0] unreachable bb438: ; preds = %bb20, %bb20 Modified: llvm/trunk/test/CodeGen/Thumb2/lsr-deficiency.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/lsr-deficiency.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/lsr-deficiency.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/lsr-deficiency.ll Thu Jun 17 10:18:27 2010 @@ -11,7 +11,7 @@ @G = external global i32 ; [#uses=2] @array = external global i32* ; [#uses=1] -define arm_apcscc void @t() nounwind optsize { +define void @t() nounwind optsize { ; CHECK: t: ; CHECK: mov.w r2, #1000 entry: Modified: llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll Thu Jun 17 10:18:27 2010 @@ -8,7 +8,7 @@ @GV = external global i32 ; [#uses=2] -define arm_apcscc void @t1(i32* nocapture %vals, i32 %c) nounwind { +define void @t1(i32* nocapture %vals, i32 %c) nounwind { entry: ; CHECK: t1: ; CHECK: cbz @@ -52,7 +52,7 @@ } ; rdar://8001136 -define arm_apcscc void @t2(i8* %ptr1, i8* %ptr2) nounwind { +define void @t2(i8* %ptr1, i8* %ptr2) nounwind { entry: ; CHECK: t2: ; CHECK: adr r{{.}}, #LCPI1_0 Modified: llvm/trunk/test/CodeGen/Thumb2/pic-load.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/pic-load.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/pic-load.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/pic-load.ll Thu Jun 17 10:18:27 2010 @@ -5,7 +5,7 @@ @__dso_handle = external global { } ; <{ }*> [#uses=1] @llvm.used = appending global [1 x i8*] [i8* bitcast (i32 (void ()*)* @atexit to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] -define hidden arm_apcscc i32 @atexit(void ()* %func) nounwind { +define hidden i32 @atexit(void ()* %func) nounwind { entry: ; CHECK: atexit: ; CHECK: add r0, pc @@ -14,8 +14,8 @@ store void ()* %func, void ()** %0, align 4 %1 = getelementptr %struct.one_atexit_routine* %r, i32 0, i32 1 ; [#uses=1] store i32 0, i32* %1, align 4 - %2 = call arm_apcscc i32 @atexit_common(%struct.one_atexit_routine* %r, i8* bitcast ({ }* @__dso_handle to i8*)) nounwind ; [#uses=1] + %2 = call i32 @atexit_common(%struct.one_atexit_routine* %r, i8* bitcast ({ }* @__dso_handle to i8*)) nounwind ; [#uses=1] ret i32 %2 } -declare arm_apcscc i32 @atexit_common(%struct.one_atexit_routine*, i8*) nounwind +declare i32 @atexit_common(%struct.one_atexit_routine*, i8*) nounwind Modified: llvm/trunk/test/CodeGen/Thumb2/sign_extend_inreg.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/sign_extend_inreg.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/sign_extend_inreg.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/sign_extend_inreg.ll Thu Jun 17 10:18:27 2010 @@ -3,7 +3,7 @@ target triple = "thumbv7-apple-darwin10" -define arm_apcscc i32 @f1(i16* %ptr) nounwind { +define i32 @f1(i16* %ptr) nounwind { ; CHECK-A8: f1 ; CHECK-A8: sxth ; CHECK-M3: f1 Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-cbnz.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-cbnz.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-cbnz.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-cbnz.ll Thu Jun 17 10:18:27 2010 @@ -1,7 +1,7 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s ; rdar://7354379 -declare arm_apcscc double @floor(double) nounwind readnone +declare double @floor(double) nounwind readnone define void @t(i1 %a, double %b) { entry: @@ -23,7 +23,7 @@ ; CHECK: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cbnz - %0 = tail call arm_apcscc double @floor(double %b) nounwind readnone ; [#uses=0] + %0 = tail call double @floor(double %b) nounwind readnone ; [#uses=0] br label %bb11 bb11: ; preds = %bb9, %bb7 Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-spill-q.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-spill-q.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-spill-q.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-spill-q.ll Thu Jun 17 10:18:27 2010 @@ -9,7 +9,7 @@ declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*) nounwind readonly -define arm_apcscc void @aaa(%quuz* %this, i8* %block) { +define void @aaa(%quuz* %this, i8* %block) { ; CHECK: aaa: ; CHECK: bic r4, r4, #15 ; CHECK: vst1.64 {{.*}}[{{.*}}, :128] Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-tbh.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-tbh.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-tbh.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-tbh.ll Thu Jun 17 10:18:27 2010 @@ -8,13 +8,13 @@ @.str31 = external constant [28 x i8], align 1 ; <[28 x i8]*> [#uses=1] @_T_gtol = external global %struct._T_tstr* ; <%struct._T_tstr**> [#uses=2] -declare arm_apcscc i32 @strlen(i8* nocapture) nounwind readonly +declare i32 @strlen(i8* nocapture) nounwind readonly -declare arm_apcscc void @Z_fatal(i8*) noreturn nounwind +declare void @Z_fatal(i8*) noreturn nounwind -declare arm_apcscc noalias i8* @calloc(i32, i32) nounwind +declare noalias i8* @calloc(i32, i32) nounwind -define arm_apcscc i32 @main(i32 %argc, i8** nocapture %argv) nounwind { +define i32 @main(i32 %argc, i8** nocapture %argv) nounwind { ; CHECK: main: ; CHECK: tbb entry: @@ -28,39 +28,39 @@ br label %bb40.i bb7.i: ; preds = %bb42.i - call arm_apcscc void @_T_addtol(%struct._T_tstr** @_T_gtol, i32 0, i8* null) nounwind + call void @_T_addtol(%struct._T_tstr** @_T_gtol, i32 0, i8* null) nounwind unreachable bb15.i: ; preds = %bb42.i - call arm_apcscc void @_T_addtol(%struct._T_tstr** @_T_gtol, i32 2, i8* null) nounwind + call void @_T_addtol(%struct._T_tstr** @_T_gtol, i32 2, i8* null) nounwind unreachable bb23.i: ; preds = %bb42.i - %1 = call arm_apcscc i32 @strlen(i8* null) nounwind readonly ; [#uses=0] + %1 = call i32 @strlen(i8* null) nounwind readonly ; [#uses=0] unreachable bb33.i: ; preds = %bb42.i store i32 0, i32* @_C_nextcmd, align 4 - %2 = call arm_apcscc noalias i8* @calloc(i32 21, i32 1) nounwind ; [#uses=0] + %2 = call noalias i8* @calloc(i32 21, i32 1) nounwind ; [#uses=0] unreachable bb34.i: ; preds = %bb42.i %3 = load i32* @_C_nextcmd, align 4 ; [#uses=1] %4 = add i32 %3, 1 ; [#uses=1] store i32 %4, i32* @_C_nextcmd, align 4 - %5 = call arm_apcscc noalias i8* @calloc(i32 22, i32 1) nounwind ; [#uses=0] + %5 = call noalias i8* @calloc(i32 22, i32 1) nounwind ; [#uses=0] unreachable bb35.i: ; preds = %bb42.i - %6 = call arm_apcscc noalias i8* @calloc(i32 20, i32 1) nounwind ; [#uses=0] + %6 = call noalias i8* @calloc(i32 20, i32 1) nounwind ; [#uses=0] unreachable bb37.i: ; preds = %bb42.i - %7 = call arm_apcscc noalias i8* @calloc(i32 14, i32 1) nounwind ; [#uses=0] + %7 = call noalias i8* @calloc(i32 14, i32 1) nounwind ; [#uses=0] unreachable bb39.i: ; preds = %bb42.i - call arm_apcscc void @Z_fatal(i8* getelementptr ([28 x i8]* @.str31, i32 0, i32 0)) nounwind + call void @Z_fatal(i8* getelementptr ([28 x i8]* @.str31, i32 0, i32 0)) nounwind unreachable bb40.i: ; preds = %bb42.i, %bb5.i, %bb1.i2 @@ -81,4 +81,4 @@ ] } -declare arm_apcscc void @_T_addtol(%struct._T_tstr** nocapture, i32, i8*) nounwind +declare void @_T_addtol(%struct._T_tstr** nocapture, i32, i8*) nounwind Modified: llvm/trunk/test/Transforms/GVN/load-pre-align.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GVN/load-pre-align.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/Transforms/GVN/load-pre-align.ll (original) +++ llvm/trunk/test/Transforms/GVN/load-pre-align.ll Thu Jun 17 10:18:27 2010 @@ -4,7 +4,7 @@ @p = external global i32 -define arm_apcscc i32 @test(i32 %n) nounwind { +define i32 @test(i32 %n) nounwind { ; CHECK: @test entry: br label %for.cond Modified: llvm/trunk/test/Transforms/IndVarSimplify/single-element-range.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/single-element-range.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/Transforms/IndVarSimplify/single-element-range.ll (original) +++ llvm/trunk/test/Transforms/IndVarSimplify/single-element-range.ll Thu Jun 17 10:18:27 2010 @@ -3,7 +3,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64" target triple = "armv6-apple-darwin10" -define arm_apcscc void @sqlite3_free_table(i8** %azResult) nounwind { +define void @sqlite3_free_table(i8** %azResult) nounwind { entry: br i1 undef, label %return, label %bb Modified: llvm/trunk/test/Transforms/InstCombine/call.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/call.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/call.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/call.ll Thu Jun 17 10:18:27 2010 @@ -100,7 +100,7 @@ declare void @test8a() define i8* @test8() { - invoke arm_apcscc void @test8a() + invoke void @test8a() to label %invoke.cont unwind label %try.handler invoke.cont: ; preds = %entry @@ -114,5 +114,5 @@ ; calling conv, but the implementation of test8a may actually end up using the ; right calling conv. ; CHECK: @test8() { -; CHECK-NEXT: invoke arm_apcscc void @test8a() +; CHECK-NEXT: invoke void @test8a() Modified: llvm/trunk/test/Transforms/InstCombine/crash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/crash.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/crash.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/crash.ll Thu Jun 17 10:18:27 2010 @@ -127,11 +127,11 @@ } ; PR5471 -define arm_apcscc i32 @test5a() { +define i32 @test5a() { ret i32 0 } -define arm_apcscc void @test5() { +define void @test5() { store i1 true, i1* undef %1 = invoke i32 @test5a() to label %exit unwind label %exit exit: @@ -212,7 +212,7 @@ entry: store i1 true, i1* undef store i1 true, i1* undef - invoke arm_apcscc void @test10a() + invoke void @test10a() to label %invoke.cont unwind label %try.handler ; [#uses=0] invoke.cont: ; preds = %entry Modified: llvm/trunk/test/Transforms/LoopUnswitch/preserve-analyses.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopUnswitch/preserve-analyses.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/Transforms/LoopUnswitch/preserve-analyses.ll (original) +++ llvm/trunk/test/Transforms/LoopUnswitch/preserve-analyses.ll Thu Jun 17 10:18:27 2010 @@ -9,7 +9,7 @@ @delim1 = external global i32 ; [#uses=1] @delim2 = external global i32 ; [#uses=1] -define arm_apcscc i32 @ineqn(i8* %s, i8* %p) nounwind readonly { +define i32 @ineqn(i8* %s, i8* %p) nounwind readonly { entry: %0 = load i32* @delim1, align 4 ; [#uses=1] %1 = load i32* @delim2, align 4 ; [#uses=1] Modified: llvm/trunk/test/Transforms/ScalarRepl/2009-12-11-NeonTypes.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ScalarRepl/2009-12-11-NeonTypes.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/Transforms/ScalarRepl/2009-12-11-NeonTypes.ll (original) +++ llvm/trunk/test/Transforms/ScalarRepl/2009-12-11-NeonTypes.ll Thu Jun 17 10:18:27 2010 @@ -9,7 +9,7 @@ %struct.int16x8x2_t = type { [2 x %struct.int16x8_t] } %union..0anon = type { %struct.int16x8x2_t } -define arm_apcscc void @test(<8 x i16> %tmp.0, %struct.int16x8x2_t* %dst) nounwind { +define void @test(<8 x i16> %tmp.0, %struct.int16x8x2_t* %dst) nounwind { ; CHECK: @test ; CHECK-NOT: alloca ; CHECK: "alloca point" @@ -68,7 +68,7 @@ ; Radar 7466574 %struct._NSRange = type { i64 } -define arm_apcscc void @test_memcpy_self() nounwind { +define void @test_memcpy_self() nounwind { ; CHECK: @test_memcpy_self ; CHECK-NOT: alloca ; CHECK: br i1 Modified: llvm/trunk/test/Transforms/ScalarRepl/2010-01-18-SelfCopy.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ScalarRepl/2010-01-18-SelfCopy.ll?rev=106221&r1=106220&r2=106221&view=diff ============================================================================== --- llvm/trunk/test/Transforms/ScalarRepl/2010-01-18-SelfCopy.ll (original) +++ llvm/trunk/test/Transforms/ScalarRepl/2010-01-18-SelfCopy.ll Thu Jun 17 10:18:27 2010 @@ -5,7 +5,7 @@ %struct.test = type { [3 x double ] } -define arm_apcscc void @test_memcpy_self() nounwind { +define void @test_memcpy_self() nounwind { ; CHECK: @test_memcpy_self ; CHECK-NOT: alloca ; CHECK: ret void From criswell at uiuc.edu Thu Jun 17 10:56:56 2010 From: criswell at uiuc.edu (John Criswell) Date: Thu, 17 Jun 2010 15:56:56 -0000 Subject: [llvm-commits] [poolalloc] r106223 - /poolalloc/trunk/test/TEST.FL2.Makefile Message-ID: <20100617155656.752462A6C12C@llvm.org> Author: criswell Date: Thu Jun 17 10:56:56 2010 New Revision: 106223 URL: http://llvm.org/viewvc/llvm-project?rev=106223&view=rev Log: Don't use the simple pool allocator. It depends too much on SAFECode to do cleanup tasks. Modified: poolalloc/trunk/test/TEST.FL2.Makefile Modified: poolalloc/trunk/test/TEST.FL2.Makefile URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/TEST.FL2.Makefile?rev=106223&r1=106222&r2=106223&view=diff ============================================================================== --- poolalloc/trunk/test/TEST.FL2.Makefile (original) +++ poolalloc/trunk/test/TEST.FL2.Makefile Thu Jun 17 10:56:56 2010 @@ -59,7 +59,7 @@ $(PROGRAMS_TO_TEST:%=Output/%.poolalloc.bc): \ Output/%.poolalloc.bc: Output/%.base.bc $(PA_SO) $(LOPT) - at rm -f $(CURDIR)/$@.info - -$(OPT_PA_STATS) -poolalloc-simple $(EXTRA_PA_FLAGS) $(OPTZN_PASSES) $< -o $@ -f 2>&1 > $@.out + -$(OPT_PA_STATS) -poolalloc -poolalloc-heuristic=AllInOneGlobalPool $(EXTRA_PA_FLAGS) $(OPTZN_PASSES) $< -o $@ -f 2>&1 > $@.out $(PROGRAMS_TO_TEST:%=Output/%.nonpa.bc): \ Output/%.nonpa.bc: Output/%.base.bc $(LOPT) From nlewycky at google.com Thu Jun 17 12:35:45 2010 From: nlewycky at google.com (Nick Lewycky) Date: Thu, 17 Jun 2010 10:35:45 -0700 Subject: [llvm-commits] [patch] Update llvm-gcc to produce "" for the default calling convention on ARM In-Reply-To: References: <76A0798C-9AB8-43E8-99C1-7AFE618CEBEB@apple.com> Message-ID: On 17 June 2010 06:39, Sandeep Patel wrote: > On Wed, Jun 16, 2010 at 5:04 PM, Anton Korobeynikov > wrote: > >> An updated patch is attached. With it and a gcc configured for > >> arm-none-linux-gnueabi I get: > >> > >> *) no -mabi -> "" > >> *) -mabi=aapcs -> "" > >> *) -mcpu=cortex-a8 -> arm_apcscc > >> *) -mfloat-abi=hard -> arm_aapcs_vfpcc > >> > >> Is it OK? > > Looks ok for me. > > If I read PR7357 correctly, then you're relying on the CC being "". > That means you're really just disabling simplify-libcalls on an > AAPCS-VFP platform. > Why isn't aapcs-vfp the default cc on "an AAPCS-VFP platform"? Nick -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100617/843756ab/attachment.html From dalej at apple.com Thu Jun 17 12:42:35 2010 From: dalej at apple.com (Dale Johannesen) Date: Thu, 17 Jun 2010 17:42:35 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r106225 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Message-ID: <20100617174235.2582B2A6C12C@llvm.org> Author: johannes Date: Thu Jun 17 12:42:34 2010 New Revision: 106225 URL: http://llvm.org/viewvc/llvm-project?rev=106225&view=rev Log: Inline asm: handle matching constraints on memory arguments. 8074175. Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=106225&r1=106224&r2=106225&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Thu Jun 17 12:42:34 2010 @@ -4696,6 +4696,7 @@ SmallVector StoreCallResultAddrs; SmallVector CallResultTypes; SmallVector CallResultIsSigned; + SmallVector, 4> OutputLocations; // Process outputs. ValNum = 0; @@ -4763,11 +4764,13 @@ ConstraintStr += SimplifiedConstraint; CallResultTypes.push_back(DestValTy); CallResultIsSigned.push_back(!TYPE_UNSIGNED(TREE_TYPE(Operand))); + OutputLocations.push_back(std::make_pair(true, CallResultTypes.size()-1)); } else { ConstraintStr += ",=*"; ConstraintStr += SimplifiedConstraint; CallOps.push_back(Dest.Ptr); CallArgTypes.push_back(Dest.Ptr->getType()); + OutputLocations.push_back(std::make_pair(false, CallArgTypes.size()-1)); } } @@ -4832,8 +4835,19 @@ // is big endian. if (ISDIGIT(Constraint[0])) { unsigned Match = atoi(Constraint); - const Type *OTy = (Match < CallResultTypes.size()) - ? CallResultTypes[Match] : 0; + // This output might have gotten put in either CallResult or CallArg + // depending whether it's a register or not. Find its type. + const Type *OTy = 0; + if (Match < OutputLocations.size()) { + // Indices here known to be within range. + if (OutputLocations[Match].first) + OTy = CallResultTypes[OutputLocations[Match].second]; + else { + OTy = CallArgTypes[OutputLocations[Match].second]; + assert(OTy->isPointerTy() && "Expected pointer type!"); + OTy = cast(OTy)->getElementType(); + } + } if (OTy && OTy != OpTy) { if (!(OTy->isIntegerTy() || OTy->isPointerTy()) || !(OpTy->isIntegerTy() || OpTy->isPointerTy())) { From dalej at apple.com Thu Jun 17 12:43:14 2010 From: dalej at apple.com (Dale Johannesen) Date: Thu, 17 Jun 2010 17:43:14 -0000 Subject: [llvm-commits] [llvm] r106226 - /llvm/trunk/test/FrontendC/2010-06-17-asmcrash.c Message-ID: <20100617174314.65C8D2A6C12C@llvm.org> Author: johannes Date: Thu Jun 17 12:43:14 2010 New Revision: 106226 URL: http://llvm.org/viewvc/llvm-project?rev=106226&view=rev Log: Testcase for llvm-gcc 106225. Added: llvm/trunk/test/FrontendC/2010-06-17-asmcrash.c Added: llvm/trunk/test/FrontendC/2010-06-17-asmcrash.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/2010-06-17-asmcrash.c?rev=106226&view=auto ============================================================================== --- llvm/trunk/test/FrontendC/2010-06-17-asmcrash.c (added) +++ llvm/trunk/test/FrontendC/2010-06-17-asmcrash.c Thu Jun 17 12:43:14 2010 @@ -0,0 +1,16 @@ +// RUN: %llvmgcc -S -o - %s | llc -mtriple=x86_64-apple-darwin | FileCheck %s +// XFAIL: * +// XTARGET: x86,i386,i686 + +typedef long long int64_t; +typedef unsigned char uint8_t; +typedef int64_t x86_reg; + +void avg_pixels8_mmx2(uint8_t *block, const uint8_t *pixels, int line_size, int h) +{ + __asm__ volatile("# %0 %1 %2 %3" + :"+g"(h), "+S"(pixels), "+D"(block) + :"r" ((x86_reg)line_size) + :"%""rax", "memory"); +// CHECK: # (%rsp) %rsi %rdi %rcx + } From grosbach at apple.com Thu Jun 17 12:50:54 2010 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 17 Jun 2010 17:50:54 -0000 Subject: [llvm-commits] [llvm] r106227 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <20100617175054.C490B2A6C12C@llvm.org> Author: grosbach Date: Thu Jun 17 12:50:54 2010 New Revision: 106227 URL: http://llvm.org/viewvc/llvm-project?rev=106227&view=rev Log: Add entries for Expanding atomic intrinsics to libcalls. Just a placeholder for the moment. The implementation of the libcall will follow. Currently, the llvm-gcc knows when the intrinsics can be correctly handled by the back end and only generates them in those cases, issuing libcalls directly otherwise. That's too much coupling. The intrinsics should always be generated and the back end decide how to handle them, be it with a libcall, inline code, or whatever. This patch is a step in that direction. rdar://8097623 Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=106227&r1=106226&r2=106227&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Jun 17 12:50:54 2010 @@ -2375,6 +2375,25 @@ Results.push_back(CallResult.second); break; } + // By default, atomic intrinsics are marked Legal and lowered. Targets + // which don't support them directly, however, may want libcalls, in which + // case they mark them Expand, and we get here. + // FIXME: Unimplemented for now. Add libcalls. + case ISD::ATOMIC_SWAP: + case ISD::ATOMIC_LOAD_ADD: + case ISD::ATOMIC_LOAD_SUB: + case ISD::ATOMIC_LOAD_AND: + case ISD::ATOMIC_LOAD_OR: + case ISD::ATOMIC_LOAD_XOR: + case ISD::ATOMIC_LOAD_NAND: + case ISD::ATOMIC_LOAD_MIN: + case ISD::ATOMIC_LOAD_MAX: + case ISD::ATOMIC_LOAD_UMIN: + case ISD::ATOMIC_LOAD_UMAX: + case ISD::ATOMIC_CMP_SWAP: { + assert (0 && "atomic intrinsic not lowered!"); + Results.push_back(Node->getOperand(0)); + } case ISD::DYNAMIC_STACKALLOC: ExpandDYNAMIC_STACKALLOC(Node, Results); break; From grosbach at apple.com Thu Jun 17 12:58:54 2010 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 17 Jun 2010 17:58:54 -0000 Subject: [llvm-commits] [llvm] r106229 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <20100617175854.5EC882A6C12C@llvm.org> Author: grosbach Date: Thu Jun 17 12:58:54 2010 New Revision: 106229 URL: http://llvm.org/viewvc/llvm-project?rev=106229&view=rev Log: add missing break. inconsequential as the code shouldn't be reached, but for correctness' sake, it should be there. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=106229&r1=106228&r2=106229&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Jun 17 12:58:54 2010 @@ -2393,6 +2393,7 @@ case ISD::ATOMIC_CMP_SWAP: { assert (0 && "atomic intrinsic not lowered!"); Results.push_back(Node->getOperand(0)); + break; } case ISD::DYNAMIC_STACKALLOC: ExpandDYNAMIC_STACKALLOC(Node, Results); From asl at math.spbu.ru Thu Jun 17 12:57:50 2010 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Thu, 17 Jun 2010 21:57:50 +0400 Subject: [llvm-commits] [patch] Update llvm-gcc to produce "" for the default calling convention on ARM In-Reply-To: References: <76A0798C-9AB8-43E8-99C1-7AFE618CEBEB@apple.com> Message-ID: > Why isn't aapcs-vfp the default cc on "an AAPCS-VFP platform"? It is. The problem is that libcalls should use AAPCS w/o VFP. -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From nlewycky at google.com Thu Jun 17 13:16:20 2010 From: nlewycky at google.com (Nick Lewycky) Date: Thu, 17 Jun 2010 11:16:20 -0700 Subject: [llvm-commits] [patch] Update llvm-gcc to produce "" for the default calling convention on ARM In-Reply-To: References: <76A0798C-9AB8-43E8-99C1-7AFE618CEBEB@apple.com> Message-ID: Oh okay. I thought that aapcs was the default on an aapcs_vfp platform, and all the functions which are aapcs_vfp capable (ie., not varargs, maybe some other rules) have an explicit aapcs_vfp cc. Then the change to libcalls would optimize them just fine. Nick On 17 June 2010 10:57, Anton Korobeynikov wrote: > > Why isn't aapcs-vfp the default cc on "an AAPCS-VFP platform"? > It is. The problem is that libcalls should use AAPCS w/o VFP. > > -- > With best regards, Anton Korobeynikov > Faculty of Mathematics and Mechanics, Saint Petersburg State University > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100617/8b839467/attachment.html From dalej at apple.com Thu Jun 17 13:24:26 2010 From: dalej at apple.com (Dale Johannesen) Date: Thu, 17 Jun 2010 11:24:26 -0700 Subject: [llvm-commits] [llvm] r106227 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp In-Reply-To: <20100617175054.C490B2A6C12C@llvm.org> References: <20100617175054.C490B2A6C12C@llvm.org> Message-ID: <823B421C-99D3-4755-BCE2-60C079B88101@apple.com> On Jun 17, 2010, at 10:50 AM, Jim Grosbach wrote: > Add entries for Expanding atomic intrinsics to libcalls. Just a > placeholder > for the moment. The implementation of the libcall will follow. > > Currently, the llvm-gcc knows when the intrinsics can be correctly > handled by > the back end and only generates them in those cases, issuing > libcalls directly > otherwise. That's too much coupling. The intrinsics should always be > generated and the back end decide how to handle them, be it with a > libcall, > inline code, or whatever. This patch is a step in that direction. I think this is overstated. Which intrinsics are valid is dependent on dialect; for example, there are many library functions in C99 that are not in C89. It is appropriate for FEs to determine which calls the BEs are allowed to treat specially according to language rules, and generate intrinsics only for these. The actual special treatment, if any, I agree should be up to the BEs. From grosbach at apple.com Thu Jun 17 13:38:53 2010 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 17 Jun 2010 11:38:53 -0700 Subject: [llvm-commits] [llvm] r106227 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp In-Reply-To: <823B421C-99D3-4755-BCE2-60C079B88101@apple.com> References: <20100617175054.C490B2A6C12C@llvm.org> <823B421C-99D3-4755-BCE2-60C079B88101@apple.com> Message-ID: On Jun 17, 2010, at 11:24 AM, Dale Johannesen wrote: > > On Jun 17, 2010, at 10:50 AM, Jim Grosbach wrote: > >> Add entries for Expanding atomic intrinsics to libcalls. Just a placeholder >> for the moment. The implementation of the libcall will follow. >> >> Currently, the llvm-gcc knows when the intrinsics can be correctly handled by >> the back end and only generates them in those cases, issuing libcalls directly >> otherwise. That's too much coupling. The intrinsics should always be >> generated and the back end decide how to handle them, be it with a libcall, >> inline code, or whatever. This patch is a step in that direction. > > I think this is overstated. Which intrinsics are valid is dependent on dialect; for example, there are many library functions in C99 that are not in C89. It is appropriate for FEs to determine which calls the BEs are allowed to treat specially according to language rules, and generate intrinsics only for these. The actual special treatment, if any, I agree should be up to the BEs. > In that paragraph "the intrinsics" should be read as "the atomic intrinsics." You're absolutely correct that there are other sorts where the FE should be making decisions about whether to use them. From gohman at apple.com Thu Jun 17 14:23:51 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 17 Jun 2010 19:23:51 -0000 Subject: [llvm-commits] [llvm] r106234 - /llvm/trunk/docs/LangRef.html Message-ID: <20100617192351.52F7F2A6C12C@llvm.org> Author: djg Date: Thu Jun 17 14:23:50 2010 New Revision: 106234 URL: http://llvm.org/viewvc/llvm-project?rev=106234&view=rev Log: Minor clarification. Modified: llvm/trunk/docs/LangRef.html Modified: llvm/trunk/docs/LangRef.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=106234&r1=106233&r2=106234&view=diff ============================================================================== --- llvm/trunk/docs/LangRef.html (original) +++ llvm/trunk/docs/LangRef.html Thu Jun 17 14:23:50 2010 @@ -1389,7 +1389,7 @@

    LLVM IR does not associate types with memory. The result type of a load merely indicates the size and alignment of the memory from which to load, as well as the -interpretation of the value. The first operand of a +interpretation of the value. The first operand type of a store similarly only indicates the size and alignment of the store.

    From criswell at cs.uiuc.edu Thu Jun 17 15:14:29 2010 From: criswell at cs.uiuc.edu (John Criswell) Date: Thu, 17 Jun 2010 15:14:29 -0500 Subject: [llvm-commits] CVS: llvm-www/safecode/funding.html downloads.html index.html links.html sidebar.incl sva.html Message-ID: <201006172014.o5HKETmJ017041@maute.cs.uiuc.edu> Changes in directory llvm-www/safecode: funding.html added (r1.1) downloads.html updated: 1.6 -> 1.7 index.html updated: 1.30 -> 1.31 links.html updated: 1.6 -> 1.7 sidebar.incl updated: 1.4 -> 1.5 sva.html updated: 1.3 -> 1.4 --- Log message: Added a funding page to present more material on our sponsers. --- Diffs of the changes: (+115 -2) downloads.html | 2 + funding.html | 108 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ index.html | 2 - links.html | 2 + sidebar.incl | 1 sva.html | 2 - 6 files changed, 115 insertions(+), 2 deletions(-) Index: llvm-www/safecode/funding.html diff -c /dev/null llvm-www/safecode/funding.html:1.1 *** /dev/null Thu Jun 17 15:14:27 2010 --- llvm-www/safecode/funding.html Thu Jun 17 15:14:17 2010 *************** *** 0 **** --- 1,108 ---- + + + + + + + + + + + + + + + + SAFECode + + + + + +
    + + + + +
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    Funding

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    + SAFECode and the Secure Virtual Architecture have been funded by the + following grants: +

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    • + National Science Foundation Grants CNS 07-16768 and CNS 07-09122 +
      • + +
    • + DoD MURI AF Subcontract UCB 00006769: + "Hardware, Languages, and Architectures for Defense Against Hostile + Operating Systems" +
      • +
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    + Thank you for your support! +

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    + + + + + + + Index: llvm-www/safecode/downloads.html diff -u llvm-www/safecode/downloads.html:1.6 llvm-www/safecode/downloads.html:1.7 --- llvm-www/safecode/downloads.html:1.6 Mon May 17 12:19:19 2010 +++ llvm-www/safecode/downloads.html Thu Jun 17 15:14:17 2010 @@ -65,6 +65,8 @@


    +
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    Index: llvm-www/safecode/index.html diff -u llvm-www/safecode/index.html:1.30 llvm-www/safecode/index.html:1.31 --- llvm-www/safecode/index.html:1.30 Mon May 17 14:53:21 2010 +++ llvm-www/safecode/index.html Thu Jun 17 15:14:17 2010 @@ -4,7 +4,7 @@ - + Index: llvm-www/safecode/links.html diff -u llvm-www/safecode/links.html:1.6 llvm-www/safecode/links.html:1.7 --- llvm-www/safecode/links.html:1.6 Mon May 17 12:28:14 2010 +++ llvm-www/safecode/links.html Thu Jun 17 15:14:17 2010 @@ -66,6 +66,8 @@

    +

    +


    Index: llvm-www/safecode/sidebar.incl diff -u llvm-www/safecode/sidebar.incl:1.4 llvm-www/safecode/sidebar.incl:1.5 --- llvm-www/safecode/sidebar.incl:1.4 Mon May 17 12:19:19 2010 +++ llvm-www/safecode/sidebar.incl Thu Jun 17 15:14:17 2010 @@ -7,6 +7,7 @@
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    • Index: llvm-www/safecode/sva.html diff -u llvm-www/safecode/sva.html:1.3 llvm-www/safecode/sva.html:1.4 --- llvm-www/safecode/sva.html:1.3 Mon May 17 14:53:21 2010 +++ llvm-www/safecode/sva.html Thu Jun 17 15:14:17 2010 @@ -4,7 +4,7 @@ - + From daniel at zuster.org Thu Jun 17 16:24:14 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 17 Jun 2010 21:24:14 -0000 Subject: [llvm-commits] [zorg] r106237 - /zorg/trunk/lnt/docs/tests.rst Message-ID: <20100617212414.543262A6C12C@llvm.org> Author: ddunbar Date: Thu Jun 17 16:24:14 2010 New Revision: 106237 URL: http://llvm.org/viewvc/llvm-project?rev=106237&view=rev Log: LNT/docs: Fix a typo. Modified: zorg/trunk/lnt/docs/tests.rst Modified: zorg/trunk/lnt/docs/tests.rst URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/docs/tests.rst?rev=106237&r1=106236&r2=106237&view=diff ============================================================================== --- zorg/trunk/lnt/docs/tests.rst (original) +++ zorg/trunk/lnt/docs/tests.rst Thu Jun 17 16:24:14 2010 @@ -31,7 +31,7 @@ [2] 69694 # Watch the server log. - $ tail -f /tmp/runserver.log + $ tail -f /tmp/FOO/runserver.log * Running on http://localhost:8000/ ... From daniel at zuster.org Thu Jun 17 16:24:17 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 17 Jun 2010 21:24:17 -0000 Subject: [llvm-commits] [zorg] r106238 - in /zorg/trunk/lnt/lnt: db/perfdbsummary.py db/runinfo.py lnttool/__init__.py viewer/simple.ptl Message-ID: <20100617212417.C66B22A6C12D@llvm.org> Author: ddunbar Date: Thu Jun 17 16:24:17 2010 New Revision: 106238 URL: http://llvm.org/viewvc/llvm-project?rev=106238&view=rev Log: LNT/simple: Switch SimpleSuiteSummary to only store test IDs, not test instances, which may become invalid once the DB session has closed. Modified: zorg/trunk/lnt/lnt/db/perfdbsummary.py zorg/trunk/lnt/lnt/db/runinfo.py zorg/trunk/lnt/lnt/lnttool/__init__.py zorg/trunk/lnt/lnt/viewer/simple.ptl Modified: zorg/trunk/lnt/lnt/db/perfdbsummary.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/db/perfdbsummary.py?rev=106238&r1=106237&r2=106238&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/db/perfdbsummary.py (original) +++ zorg/trunk/lnt/lnt/db/perfdbsummary.py Thu Jun 17 16:24:17 2010 @@ -48,7 +48,7 @@ # Collect all the test data. test_names = set() parameter_sets = set() - test_map = {} + test_id_map = {} has_status_markers = False has_success_markers = False for t in tests: @@ -59,7 +59,7 @@ key = tuple(items) parameter_sets.add(key) - test_map[(name, key)] = t + test_id_map[(name, key)] = t.id if name.endswith('.success'): test_name = name.rsplit('.', 1)[0] @@ -97,16 +97,16 @@ parameter_sets.sort() return SimpleSuiteSummary(revision, tag, test_names, - test_map, test_status_map, + test_id_map, test_status_map, parameter_keys, parameter_sets) def __init__(self, revision, tag, test_names, - test_map, test_status_map, + test_id_map, test_status_map, parameter_keys, parameter_sets): self.revision = revision self.tag = tag self.test_names = test_names - self.test_map = test_map + self.test_id_map = test_id_map self.test_status_map = test_status_map self.parameter_keys = parameter_keys self.parameter_sets = parameter_sets Modified: zorg/trunk/lnt/lnt/db/runinfo.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/db/runinfo.py?rev=106238&r1=106237&r2=106238&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/db/runinfo.py (original) +++ zorg/trunk/lnt/lnt/db/runinfo.py Thu Jun 17 16:24:17 2010 @@ -94,8 +94,8 @@ def get_run_comparison_result(self, run, compare_to, test_name, pset, comparison_window=[]): # Get the test. - test = self.test_suite_summary.test_map.get((test_name, pset)) - if test is None: + test_id = self.test_suite_summary.test_id_map.get((test_name, pset)) + if test_id is None: return ComparisonResult(run_value=None, prev_value=None, delta=None, pct_delta=None, stddev=None, MAD=None, cur_failed=None, prev_failed=None) @@ -104,10 +104,10 @@ status_info = self.test_suite_summary.test_status_map.get(test_name) if status_info is not None: status_name,status_kind = status_info - status_test = self.test_suite_summary.test_map.get( + status_test_id = self.test_suite_summary.test_id_map.get( (status_name, pset)) else: - status_test = status_kind = None + status_test_id = status_kind = None # Load the sample data for the current and previous runs and the # comparison window. @@ -122,8 +122,8 @@ self._load_samples_for_runs(runs_to_load) # Lookup the current and previous values. - run_values = self.sample_map.get((run.id, test.id)) - prev_values = self.sample_map.get((compare_id, test.id)) + run_values = self.sample_map.get((run.id, test_id)) + prev_values = self.sample_map.get((compare_id, test_id)) # Determine whether this (test,pset) passed or failed in the current and # previous runs. @@ -132,8 +132,8 @@ run_failed = not run_values prev_failed = not prev_values else: - run_status = self.sample_map.get((run.id,status_test.id)) - prev_status = self.sample_map.get((compare_id,status_test.id)) + run_status = self.sample_map.get((run.id,status_test_id)) + prev_status = self.sample_map.get((compare_id,status_test_id)) # FIXME: Support XFAILs. # Modified: zorg/trunk/lnt/lnt/lnttool/__init__.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/lnttool/__init__.py?rev=106238&r1=106237&r2=106238&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/lnttool/__init__.py (original) +++ zorg/trunk/lnt/lnt/lnttool/__init__.py Thu Jun 17 16:24:17 2010 @@ -149,6 +149,8 @@ parser = OptionParser("%%prog %s [options] +" % name) parser.add_option("", "--commit", dest="commit", type=int, + help=("whether the result should be committed " + "[%default]"), default=False) (opts, args) = parser.parse_args(args) Modified: zorg/trunk/lnt/lnt/viewer/simple.ptl URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/viewer/simple.ptl?rev=106238&r1=106237&r2=106238&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/viewer/simple.ptl (original) +++ zorg/trunk/lnt/lnt/viewer/simple.ptl Thu Jun 17 16:24:17 2010 @@ -229,7 +229,7 @@ graph_psets.append(ts_summary.parameter_sets[int(name[5:])]) # Get the test ids we want data for. - test_ids = [ts_summary.test_map[(name,pset)].id + test_ids = [ts_summary.test_id_map[(name,pset)] for name in graph_tests for pset in graph_psets] @@ -270,7 +270,7 @@ show_all_points = False for name in graph_tests: for pset in graph_psets: - test_id = ts_summary.test_map[(name,pset)].id + test_id = ts_summary.test_id_map[(name,pset)] # Get the plot for this test. # From daniel at zuster.org Thu Jun 17 16:41:45 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 17 Jun 2010 21:41:45 -0000 Subject: [llvm-commits] [zorg] r106239 - /zorg/trunk/lnt/lnt/db/runinfo.py Message-ID: <20100617214145.0F9392A6C12C@llvm.org> Author: ddunbar Date: Thu Jun 17 16:41:44 2010 New Revision: 106239 URL: http://llvm.org/viewvc/llvm-project?rev=106239&view=rev Log: LNT/simple: Fix a couple refactos. Modified: zorg/trunk/lnt/lnt/db/runinfo.py Modified: zorg/trunk/lnt/lnt/db/runinfo.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/db/runinfo.py?rev=106239&r1=106238&r2=106239&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/db/runinfo.py (original) +++ zorg/trunk/lnt/lnt/db/runinfo.py Thu Jun 17 16:41:44 2010 @@ -128,7 +128,7 @@ # Determine whether this (test,pset) passed or failed in the current and # previous runs. run_failed = prev_failed = False - if not status_test: + if not status_test_id: run_failed = not run_values prev_failed = not prev_values else: @@ -172,7 +172,7 @@ # Get all previous values in the comparison window. prev_values = [v for run_id in comparison_window - for v in self.sample_map.get((run_id, test.id), ())] + for v in self.sample_map.get((run_id, test_id), ())] if prev_values: stddev = stats.standard_deviation(prev_values) MAD = stats.median_absolute_deviation(prev_values) From daniel at zuster.org Thu Jun 17 16:42:23 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 17 Jun 2010 21:42:23 -0000 Subject: [llvm-commits] [zorg] r106240 - /zorg/trunk/lnt/lnt/viewer/simple.ptl Message-ID: <20100617214223.41CB82A6C12C@llvm.org> Author: ddunbar Date: Thu Jun 17 16:42:23 2010 New Revision: 106240 URL: http://llvm.org/viewvc/llvm-project?rev=106240&view=rev Log: LNT/simple: Reduce number of entries in ordered delta table. Modified: zorg/trunk/lnt/lnt/viewer/simple.ptl Modified: zorg/trunk/lnt/lnt/viewer/simple.ptl URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/viewer/simple.ptl?rev=106240&r1=106239&r2=106240&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/viewer/simple.ptl (original) +++ zorg/trunk/lnt/lnt/viewer/simple.ptl Thu Jun 17 16:42:23 2010 @@ -389,7 +389,7 @@ for p0,p1 in Util.pairs(points)] deltas.sort() deltas.reverse() - for (pct,(r0,t0,mad0,med0),(r1,t1,mad1,med1)) in deltas[:50]: + for (pct,(r0,t0,mad0,med0),(r1,t1,mad1,med1)) in deltas[:20]: """
    From daniel at zuster.org Thu Jun 17 16:43:17 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 17 Jun 2010 21:43:17 -0000 Subject: [llvm-commits] [zorg] r106241 - /zorg/trunk/lnt/lnt/db/perfdbsummary.py Message-ID: <20100617214317.DB0282A6C12C@llvm.org> Author: ddunbar Date: Thu Jun 17 16:43:17 2010 New Revision: 106241 URL: http://llvm.org/viewvc/llvm-project?rev=106241&view=rev Log: LNT: Fix a caching bug where we didn't properly invalidate summary objects when fetching from a database which had a pending uncommitted transaction. Modified: zorg/trunk/lnt/lnt/db/perfdbsummary.py Modified: zorg/trunk/lnt/lnt/db/perfdbsummary.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/db/perfdbsummary.py?rev=106241&r1=106240&r2=106241&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/db/perfdbsummary.py (original) +++ zorg/trunk/lnt/lnt/db/perfdbsummary.py Thu Jun 17 16:43:17 2010 @@ -33,7 +33,8 @@ self.suites = suites def is_up_to_date(self, db): - return self.revision == db.get_revision_number("Run") + return (not db.modified_run and + self.revision == db.get_revision_number("Run")) class SimpleSuiteSummary(object): @staticmethod @@ -112,7 +113,8 @@ self.parameter_sets = parameter_sets def is_up_to_date(self, db): - return self.revision == db.get_revision_number("Test") + return (not db.modified_test and + self.revision == db.get_revision_number("Test")) _cache = {} def get_simple_suite_summary(db, tag): @@ -186,7 +188,8 @@ self.machine_id_by_run = machine_id_by_run def is_up_to_date(self, db): - return self.revision == db.get_revision_number("RunInfo") + return (not db.modified_run and + self.revision == db.get_revision_number("RunInfo")) def get_run_order(self, run_id): return self.order_by_run.get(run_id) From stuart at apple.com Thu Jun 17 17:43:57 2010 From: stuart at apple.com (Stuart Hastings) Date: Thu, 17 Jun 2010 22:43:57 -0000 Subject: [llvm-commits] [llvm] r106243 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CellSPU/ lib/Target/MBlaze/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PIC16/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/SystemZ/ lib/Target/X86/ lib/Target/XCore/ Message-ID: <20100617224357.4EFE22A6C12C@llvm.org> Author: stuart Date: Thu Jun 17 17:43:56 2010 New Revision: 106243 URL: http://llvm.org/viewvc/llvm-project?rev=106243&view=rev Log: Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This addresses a longstanding deficiency noted in many FIXMEs scattered across all the targets. This effectively moves the problem up one level, replacing eleven FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path through FastISel where we actually supply a DebugLoc, fixing Radar 7421831. Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h llvm/trunk/include/llvm/Target/TargetInstrInfo.h llvm/trunk/lib/CodeGen/BranchFolding.cpp llvm/trunk/lib/CodeGen/IfConversion.cpp llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp llvm/trunk/lib/CodeGen/PHIElimination.cpp llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.h llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp llvm/trunk/lib/Target/Mips/MipsInstrInfo.h llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.h llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h llvm/trunk/lib/Target/X86/X86FastISel.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.h llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FastISel.h?rev=106243&r1=106242&r2=106243&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/FastISel.h (original) +++ llvm/trunk/include/llvm/CodeGen/FastISel.h Thu Jun 17 17:43:56 2010 @@ -286,7 +286,7 @@ /// FastEmitBranch - Emit an unconditional branch to the given block, /// unless it is the immediate (fall-through) successor, and update /// the CFG. - void FastEmitBranch(MachineBasicBlock *MBB); + void FastEmitBranch(MachineBasicBlock *MBB, DebugLoc DL); unsigned UpdateValueMap(const Value* I, unsigned Reg); Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=106243&r1=106242&r2=106243&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Thu Jun 17 17:43:56 2010 @@ -315,8 +315,9 @@ /// branch to analyze. At least this much must be implemented, else tail /// merging needs to be disabled. virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, - MachineBasicBlock *FBB, - const SmallVectorImpl &Cond) const { + MachineBasicBlock *FBB, + const SmallVectorImpl &Cond, + DebugLoc DL) const { assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); return 0; } Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchFolding.cpp?rev=106243&r1=106242&r2=106243&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/BranchFolding.cpp (original) +++ llvm/trunk/lib/CodeGen/BranchFolding.cpp Thu Jun 17 17:43:56 2010 @@ -373,7 +373,8 @@ // If OldBB isn't immediately before OldBB, insert a branch to it. if (++MachineFunction::iterator(OldBB) != MachineFunction::iterator(NewDest)) - TII->InsertBranch(*OldBB, NewDest, 0, SmallVector()); + TII->InsertBranch(*OldBB, NewDest, 0, SmallVector(), + OldInst->getDebugLoc()); OldBB->addSuccessor(NewDest); ++NumTailMerge; } @@ -443,18 +444,20 @@ MachineFunction::iterator I = llvm::next(MachineFunction::iterator(CurMBB)); MachineBasicBlock *TBB = 0, *FBB = 0; SmallVector Cond; + DebugLoc dl; // FIXME: this is nowhere if (I != MF->end() && !TII->AnalyzeBranch(*CurMBB, TBB, FBB, Cond, true)) { MachineBasicBlock *NextBB = I; if (TBB == NextBB && !Cond.empty() && !FBB) { if (!TII->ReverseBranchCondition(Cond)) { TII->RemoveBranch(*CurMBB); - TII->InsertBranch(*CurMBB, SuccBB, NULL, Cond); + TII->InsertBranch(*CurMBB, SuccBB, NULL, Cond, dl); return; } } } - TII->InsertBranch(*CurMBB, SuccBB, NULL, SmallVector()); + TII->InsertBranch(*CurMBB, SuccBB, NULL, + SmallVector(), dl); } bool @@ -874,10 +877,11 @@ } // Remove the unconditional branch at the end, if any. if (TBB && (Cond.empty() || FBB)) { + DebugLoc dl; // FIXME: this is nowhere TII->RemoveBranch(*PBB); if (!Cond.empty()) // reinsert conditional branch only, for now - TII->InsertBranch(*PBB, (TBB == IBB) ? FBB : TBB, 0, NewCond); + TII->InsertBranch(*PBB, (TBB == IBB) ? FBB : TBB, 0, NewCond, dl); } MergePotentials.push_back(MergePotentialsElt(HashEndOfMBB(PBB), *P)); } @@ -976,6 +980,7 @@ bool BranchFolder::OptimizeBlock(MachineBasicBlock *MBB) { bool MadeChange = false; MachineFunction &MF = *MBB->getParent(); + DebugLoc dl; // FIXME: this is nowhere ReoptimizeBlock: MachineFunction::iterator FallThrough = MBB; @@ -1027,7 +1032,7 @@ TII->RemoveBranch(PrevBB); PriorCond.clear(); if (PriorTBB != MBB) - TII->InsertBranch(PrevBB, PriorTBB, 0, PriorCond); + TII->InsertBranch(PrevBB, PriorTBB, 0, PriorCond, dl); MadeChange = true; ++NumBranchOpts; goto ReoptimizeBlock; @@ -1066,7 +1071,7 @@ // the condition is false, remove the uncond second branch. if (PriorFBB == MBB) { TII->RemoveBranch(PrevBB); - TII->InsertBranch(PrevBB, PriorTBB, 0, PriorCond); + TII->InsertBranch(PrevBB, PriorTBB, 0, PriorCond, dl); MadeChange = true; ++NumBranchOpts; goto ReoptimizeBlock; @@ -1079,7 +1084,7 @@ SmallVector NewPriorCond(PriorCond); if (!TII->ReverseBranchCondition(NewPriorCond)) { TII->RemoveBranch(PrevBB); - TII->InsertBranch(PrevBB, PriorFBB, 0, NewPriorCond); + TII->InsertBranch(PrevBB, PriorFBB, 0, NewPriorCond, dl); MadeChange = true; ++NumBranchOpts; goto ReoptimizeBlock; @@ -1116,7 +1121,7 @@ << "To make fallthrough to: " << *PriorTBB << "\n"); TII->RemoveBranch(PrevBB); - TII->InsertBranch(PrevBB, MBB, 0, NewPriorCond); + TII->InsertBranch(PrevBB, MBB, 0, NewPriorCond, dl); // Move this block to the end of the function. MBB->moveAfter(--MF.end()); @@ -1145,7 +1150,7 @@ SmallVector NewCond(CurCond); if (!TII->ReverseBranchCondition(NewCond)) { TII->RemoveBranch(*MBB); - TII->InsertBranch(*MBB, CurFBB, CurTBB, NewCond); + TII->InsertBranch(*MBB, CurFBB, CurTBB, NewCond, dl); MadeChange = true; ++NumBranchOpts; goto ReoptimizeBlock; @@ -1200,7 +1205,7 @@ PriorFBB = MBB; } TII->RemoveBranch(PrevBB); - TII->InsertBranch(PrevBB, PriorTBB, PriorFBB, PriorCond); + TII->InsertBranch(PrevBB, PriorTBB, PriorFBB, PriorCond, dl); } // Iterate through all the predecessors, revectoring each in-turn. @@ -1226,7 +1231,7 @@ if (!NewCurUnAnalyzable && NewCurTBB && NewCurTBB == NewCurFBB) { TII->RemoveBranch(*PMBB); NewCurCond.clear(); - TII->InsertBranch(*PMBB, NewCurTBB, 0, NewCurCond); + TII->InsertBranch(*PMBB, NewCurTBB, 0, NewCurCond, dl); MadeChange = true; ++NumBranchOpts; PMBB->CorrectExtraCFGEdges(NewCurTBB, 0, false); @@ -1246,7 +1251,7 @@ } // Add the branch back if the block is more than just an uncond branch. - TII->InsertBranch(*MBB, CurTBB, 0, CurCond); + TII->InsertBranch(*MBB, CurTBB, 0, CurCond, dl); } } @@ -1286,7 +1291,7 @@ if (CurFallsThru) { MachineBasicBlock *NextBB = llvm::next(MachineFunction::iterator(MBB)); CurCond.clear(); - TII->InsertBranch(*MBB, NextBB, 0, CurCond); + TII->InsertBranch(*MBB, NextBB, 0, CurCond, dl); } MBB->moveAfter(PredBB); MadeChange = true; Modified: llvm/trunk/lib/CodeGen/IfConversion.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/IfConversion.cpp?rev=106243&r1=106242&r2=106243&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/IfConversion.cpp (original) +++ llvm/trunk/lib/CodeGen/IfConversion.cpp Thu Jun 17 17:43:56 2010 @@ -395,9 +395,10 @@ /// ReverseBranchCondition - Reverse the condition of the end of the block /// branch. Swap block's 'true' and 'false' successors. bool IfConverter::ReverseBranchCondition(BBInfo &BBI) { + DebugLoc dl; // FIXME: this is nowhere if (!TII->ReverseBranchCondition(BBI.BrCond)) { TII->RemoveBranch(*BBI.BB); - TII->InsertBranch(*BBI.BB, BBI.FalseBB, BBI.TrueBB, BBI.BrCond); + TII->InsertBranch(*BBI.BB, BBI.FalseBB, BBI.TrueBB, BBI.BrCond, dl); std::swap(BBI.TrueBB, BBI.FalseBB); return true; } @@ -862,8 +863,9 @@ /// static void InsertUncondBranch(MachineBasicBlock *BB, MachineBasicBlock *ToBB, const TargetInstrInfo *TII) { + DebugLoc dl; // FIXME: this is nowhere SmallVector NoCond; - TII->InsertBranch(*BB, ToBB, NULL, NoCond); + TII->InsertBranch(*BB, ToBB, NULL, NoCond, dl); } /// RemoveExtraEdges - Remove true / false edges if either / both are no longer @@ -1014,6 +1016,7 @@ BBInfo &FalseBBI = BBAnalysis[BBI.FalseBB->getNumber()]; BBInfo *CvtBBI = &TrueBBI; BBInfo *NextBBI = &FalseBBI; + DebugLoc dl; // FIXME: this is nowhere SmallVector Cond(BBI.BrCond.begin(), BBI.BrCond.end()); if (Kind == ICTriangleFalse || Kind == ICTriangleFRev) @@ -1078,7 +1081,7 @@ CvtBBI->BrCond.end()); if (TII->ReverseBranchCondition(RevCond)) assert(false && "Unable to reverse branch condition!"); - TII->InsertBranch(*BBI.BB, CvtBBI->FalseBB, NULL, RevCond); + TII->InsertBranch(*BBI.BB, CvtBBI->FalseBB, NULL, RevCond, dl); BBI.BB->addSuccessor(CvtBBI->FalseBB); } Modified: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp?rev=106243&r1=106242&r2=106243&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp Thu Jun 17 17:43:56 2010 @@ -245,6 +245,7 @@ MachineBasicBlock *TBB = 0, *FBB = 0; SmallVector Cond; + DebugLoc dl; // FIXME: this is nowhere bool B = TII->AnalyzeBranch(*this, TBB, FBB, Cond); (void) B; assert(!B && "UpdateTerminators requires analyzable predecessors!"); @@ -259,7 +260,7 @@ // its layout successor, insert a branch. TBB = *succ_begin(); if (!isLayoutSuccessor(TBB)) - TII->InsertBranch(*this, TBB, 0, Cond); + TII->InsertBranch(*this, TBB, 0, Cond, dl); } } else { if (FBB) { @@ -270,10 +271,10 @@ if (TII->ReverseBranchCondition(Cond)) return; TII->RemoveBranch(*this); - TII->InsertBranch(*this, FBB, 0, Cond); + TII->InsertBranch(*this, FBB, 0, Cond, dl); } else if (isLayoutSuccessor(FBB)) { TII->RemoveBranch(*this); - TII->InsertBranch(*this, TBB, 0, Cond); + TII->InsertBranch(*this, TBB, 0, Cond, dl); } } else { // The block has a fallthrough conditional branch. @@ -284,14 +285,14 @@ if (TII->ReverseBranchCondition(Cond)) { // We can't reverse the condition, add an unconditional branch. Cond.clear(); - TII->InsertBranch(*this, MBBA, 0, Cond); + TII->InsertBranch(*this, MBBA, 0, Cond, dl); return; } TII->RemoveBranch(*this); - TII->InsertBranch(*this, MBBA, 0, Cond); + TII->InsertBranch(*this, MBBA, 0, Cond, dl); } else if (!isLayoutSuccessor(MBBA)) { TII->RemoveBranch(*this); - TII->InsertBranch(*this, TBB, MBBA, Cond); + TII->InsertBranch(*this, TBB, MBBA, Cond, dl); } } } Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.cpp?rev=106243&r1=106242&r2=106243&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PHIElimination.cpp (original) +++ llvm/trunk/lib/CodeGen/PHIElimination.cpp Thu Jun 17 17:43:56 2010 @@ -402,6 +402,7 @@ assert(A && B && "Missing MBB end point"); MachineFunction *MF = A->getParent(); + DebugLoc dl; // FIXME: this is nowhere // We may need to update A's terminator, but we can't do that if AnalyzeBranch // fails. If A uses a jump table, we won't touch it. @@ -427,7 +428,7 @@ NMBB->addSuccessor(B); if (!NMBB->isLayoutSuccessor(B)) { Cond.clear(); - MF->getTarget().getInstrInfo()->InsertBranch(*NMBB, B, NULL, Cond); + MF->getTarget().getInstrInfo()->InsertBranch(*NMBB, B, NULL, Cond, dl); } // Fix PHI nodes in B so they refer to NMBB instead of A Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=106243&r1=106242&r2=106243&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Thu Jun 17 17:43:56 2010 @@ -655,12 +655,12 @@ /// unless it is the immediate (fall-through) successor, and update /// the CFG. void -FastISel::FastEmitBranch(MachineBasicBlock *MSucc) { +FastISel::FastEmitBranch(MachineBasicBlock *MSucc, DebugLoc DL) { if (MBB->isLayoutSuccessor(MSucc)) { // The unconditional fall-through case, which needs no instructions. } else { // The unconditional branch case. - TII.InsertBranch(*MBB, MSucc, NULL, SmallVector()); + TII.InsertBranch(*MBB, MSucc, NULL, SmallVector(), DL); } MBB->addSuccessor(MSucc); } @@ -763,7 +763,7 @@ if (BI->isUnconditional()) { const BasicBlock *LLVMSucc = BI->getSuccessor(0); MachineBasicBlock *MSucc = MBBMap[LLVMSucc]; - FastEmitBranch(MSucc); + FastEmitBranch(MSucc, BI->getDebugLoc()); return true; } Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=106243&r1=106242&r2=106243&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Thu Jun 17 17:43:56 2010 @@ -347,11 +347,9 @@ unsigned ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, - MachineBasicBlock *FBB, - const SmallVectorImpl &Cond) const { - // FIXME this should probably have a DebugLoc argument - DebugLoc dl; - + MachineBasicBlock *FBB, + const SmallVectorImpl &Cond, + DebugLoc DL) const { ARMFunctionInfo *AFI = MBB.getParent()->getInfo(); int BOpc = !AFI->isThumbFunction() ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); @@ -365,17 +363,17 @@ if (FBB == 0) { if (Cond.empty()) // Unconditional branch? - BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB); + BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB); else - BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB) + BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); return 1; } // Two-way conditional branch. - BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB) + BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB) .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); - BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB); + BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB); return 2; } Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h?rev=106243&r1=106242&r2=106243&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Thu Jun 17 17:43:56 2010 @@ -225,7 +225,8 @@ virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, - const SmallVectorImpl &Cond) const; + const SmallVectorImpl &Cond, + DebugLoc DL) const; virtual bool ReverseBranchCondition(SmallVectorImpl &Cond) const; Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp?rev=106243&r1=106242&r2=106243&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp Thu Jun 17 17:43:56 2010 @@ -110,9 +110,8 @@ unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, - const SmallVectorImpl &Cond) const { - // FIXME this should probably have a DebugLoc argument - DebugLoc dl; + const SmallVectorImpl &Cond, + DebugLoc DL) const { assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 2 || Cond.size() == 0) && "Alpha branch conditions have two components!"); @@ -120,25 +119,25 @@ // One-way branch. if (FBB == 0) { if (Cond.empty()) // Unconditional branch - BuildMI(&MBB, dl, get(Alpha::BR)).addMBB(TBB); + BuildMI(&MBB, DL, get(Alpha::BR)).addMBB(TBB); else // Conditional branch if (isAlphaIntCondCode(Cond[0].getImm())) - BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_I)) + BuildMI(&MBB, DL, get(Alpha::COND_BRANCH_I)) .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); else - BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_F)) + BuildMI(&MBB, DL, get(Alpha::COND_BRANCH_F)) .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); return 1; } // Two-way Conditional Branch. if (isAlphaIntCondCode(Cond[0].getImm())) - BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_I)) + BuildMI(&MBB, DL, get(Alpha::COND_BRANCH_I)) .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); else - BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_F)) + BuildMI(&MBB, DL, get(Alpha::COND_BRANCH_F)) .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); - BuildMI(&MBB, dl, get(Alpha::BR)).addMBB(FBB); + BuildMI(&MBB, DL, get(Alpha::BR)).addMBB(FBB); return 2; } Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h?rev=106243&r1=106242&r2=106243&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h (original) +++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h Thu Jun 17 17:43:56 2010 @@ -42,8 +42,9 @@ int &FrameIndex) const; virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, - MachineBasicBlock *FBB, - const SmallVectorImpl &Cond) const; + MachineBasicBlock *FBB, + const SmallVectorImpl &Cond, + DebugLoc DL) const; virtual bool copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SrcReg, Modified: llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp?rev=106243&r1=106242&r2=106243&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp Thu Jun 17 17:43:56 2010 @@ -104,10 +104,8 @@ InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, - const SmallVectorImpl &Cond) const { - // FIXME this should probably have a DebugLoc operand - DebugLoc DL; - + const SmallVectorImpl &Cond, + DebugLoc DL) const { // Shouldn't be a fall through. assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 1 || Cond.size() == 0) && Modified: llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.h?rev=106243&r1=106242&r2=106243&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.h (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.h Thu Jun 17 17:43:56 2010 @@ -44,7 +44,8 @@ InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, - const SmallVectorImpl &Cond) const; + const SmallVectorImpl &Cond, + DebugLoc DL) const; virtual bool copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp?rev=106243&r1=106242&r2=106243&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp Thu Jun 17 17:43:56 2010 @@ -554,9 +554,8 @@ unsigned SPUInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, - const SmallVectorImpl &Cond) const { - // FIXME this should probably have a DebugLoc argument - DebugLoc dl; + const SmallVectorImpl &Cond, + DebugLoc DL) const { // Shouldn't be a fall through. assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 2 || Cond.size() == 0) && @@ -566,14 +565,14 @@ if (FBB == 0) { if (Cond.empty()) { // Unconditional branch - MachineInstrBuilder MIB = BuildMI(&MBB, dl, get(SPU::BR)); + MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(SPU::BR)); MIB.addMBB(TBB); DEBUG(errs() << "Inserted one-way uncond branch: "); DEBUG((*MIB).dump()); } else { // Conditional branch - MachineInstrBuilder MIB = BuildMI(&MBB, dl, get(Cond[0].getImm())); + MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm())); MIB.addReg(Cond[1].getReg()).addMBB(TBB); DEBUG(errs() << "Inserted one-way cond branch: "); @@ -581,8 +580,8 @@ } return 1; } else { - MachineInstrBuilder MIB = BuildMI(&MBB, dl, get(Cond[0].getImm())); - MachineInstrBuilder MIB2 = BuildMI(&MBB, dl, get(SPU::BR)); + MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm())); + MachineInstrBuilder MIB2 = BuildMI(&MBB, DL, get(SPU::BR)); // Two-way Conditional Branch. MIB.addReg(Cond[1].getReg()).addMBB(TBB); Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h?rev=106243&r1=106242&r2=106243&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h (original) +++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h Thu Jun 17 17:43:56 2010 @@ -94,8 +94,9 @@ virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, - MachineBasicBlock *FBB, - const SmallVectorImpl &Cond) const; + MachineBasicBlock *FBB, + const SmallVectorImpl &Cond, + DebugLoc DL) const; }; } Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp?rev=106243&r1=106242&r2=106243&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp Thu Jun 17 17:43:56 2010 @@ -185,10 +185,11 @@ unsigned MBlazeInstrInfo:: InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, - const SmallVectorImpl &Cond) const { + const SmallVectorImpl &Cond, + DebugLoc DL) const { // Can only insert uncond branches so far. assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!"); - BuildMI(&MBB, DebugLoc(), get(MBlaze::BRI)).addMBB(TBB); + BuildMI(&MBB, DL, get(MBlaze::BRI)).addMBB(TBB); return 1; } Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h?rev=106243&r1=106242&r2=106243&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h Thu Jun 17 17:43:56 2010 @@ -198,7 +198,8 @@ /// Branch Analysis virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, - const SmallVectorImpl &Cond) const; + const SmallVectorImpl &Cond, + DebugLoc DL) const; virtual bool copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, unsigned SrcReg, Modified: llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp?rev=106243&r1=106242&r2=106243&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp Thu Jun 17 17:43:56 2010 @@ -330,10 +330,8 @@ unsigned MSP430InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, - const SmallVectorImpl &Cond) const { - // FIXME this should probably have a DebugLoc operand - DebugLoc DL; - + const SmallVectorImpl &Cond, + DebugLoc DL) const { // Shouldn't be a fall through. assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 1 || Cond.size() == 0) && Modified: llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h?rev=106243&r1=106242&r2=106243&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h (original) +++ llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h Thu Jun 17 17:43:56 2010 @@ -93,7 +93,8 @@ unsigned RemoveBranch(MachineBasicBlock &MBB) const; unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, - const SmallVectorImpl &Cond) const; + const SmallVectorImpl &Cond, + DebugLoc DL) const; }; Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=106243&r1=106242&r2=106243&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Thu Jun 17 17:43:56 2010 @@ -520,9 +520,8 @@ unsigned MipsInstrInfo:: InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, - const SmallVectorImpl &Cond) const { - // FIXME this should probably have a DebugLoc argument - DebugLoc dl; + const SmallVectorImpl &Cond, + DebugLoc DL) const { // Shouldn't be a fall through. assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 3 || Cond.size() == 2 || Cond.size() == 0) && @@ -531,18 +530,18 @@ if (FBB == 0) { // One way branch. if (Cond.empty()) { // Unconditional branch? - BuildMI(&MBB, dl, get(Mips::J)).addMBB(TBB); + BuildMI(&MBB, DL, get(Mips::J)).addMBB(TBB); } else { // Conditional branch. unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm()); const TargetInstrDesc &TID = get(Opc); if (TID.getNumOperands() == 3) - BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()) + BuildMI(&MBB, DL, TID).addReg(Cond[1].getReg()) .addReg(Cond[2].getReg()) .addMBB(TBB); else - BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()) + BuildMI(&MBB, DL, TID).addReg(Cond[1].getReg()) .addMBB(TBB); } @@ -554,12 +553,12 @@ const TargetInstrDesc &TID = get(Opc); if (TID.getNumOperands() == 3) - BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg()) + BuildMI(&MBB, DL, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg()) .addMBB(TBB); else - BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addMBB(TBB); + BuildMI(&MBB, DL, TID).addReg(Cond[1].getReg()).addMBB(TBB); - BuildMI(&MBB, dl, get(Mips::J)).addMBB(FBB); + BuildMI(&MBB, DL, get(Mips::J)).addMBB(FBB); return 2; } Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.h?rev=106243&r1=106242&r2=106243&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.h (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.h Thu Jun 17 17:43:56 2010 @@ -204,7 +204,8 @@ virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, - const SmallVectorImpl &Cond) const; + const SmallVectorImpl &Cond, + DebugLoc DL) const; virtual bool copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, unsigned SrcReg, Modified: llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp?rev=106243&r1=106242&r2=106243&view=diff ============================================================================== --- llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp Thu Jun 17 17:43:56 2010 @@ -196,15 +196,15 @@ unsigned PIC16InstrInfo:: InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, - const SmallVectorImpl &Cond) const { + const SmallVectorImpl &Cond, + DebugLoc DL) const { // Shouldn't be a fall through. assert(TBB && "InsertBranch must not be told to insert a fallthrough"); if (FBB == 0) { // One way branch. if (Cond.empty()) { // Unconditional branch? - DebugLoc dl; - BuildMI(&MBB, dl, get(PIC16::br_uncond)).addMBB(TBB); + BuildMI(&MBB, DL, get(PIC16::br_uncond)).addMBB(TBB); } return 1; } Modified: llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.h?rev=106243&r1=106242&r2=106243&view=diff ============================================================================== --- llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.h (original) +++ llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.h Thu Jun 17 17:43:56 2010 @@ -70,7 +70,8 @@ virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, - const SmallVectorImpl &Cond) const; + const SmallVectorImpl &Cond, + DebugLoc DL) const; virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl &Cond, Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=106243&r1=106242&r2=106243&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Thu Jun 17 17:43:56 2010 @@ -316,9 +316,8 @@ unsigned PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, - const SmallVectorImpl &Cond) const { - // FIXME this should probably have a DebugLoc argument - DebugLoc dl; + const SmallVectorImpl &Cond, + DebugLoc DL) const { // Shouldn't be a fall through. assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 2 || Cond.size() == 0) && @@ -327,17 +326,17 @@ // One-way branch. if (FBB == 0) { if (Cond.empty()) // Unconditional branch - BuildMI(&MBB, dl, get(PPC::B)).addMBB(TBB); + BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB); else // Conditional branch - BuildMI(&MBB, dl, get(PPC::BCC)) + BuildMI(&MBB, DL, get(PPC::BCC)) .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); return 1; } // Two-way Conditional Branch. - BuildMI(&MBB, dl, get(PPC::BCC)) + BuildMI(&MBB, DL, get(PPC::BCC)) .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); - BuildMI(&MBB, dl, get(PPC::B)).addMBB(FBB); + BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB); return 2; } Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h?rev=106243&r1=106242&r2=106243&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h Thu Jun 17 17:43:56 2010 @@ -109,7 +109,8 @@ virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, - const SmallVectorImpl &Cond) const; + const SmallVectorImpl &Cond, + DebugLoc DL) const; virtual bool copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SrcReg, Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp?rev=106243&r1=106242&r2=106243&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp Thu Jun 17 17:43:56 2010 @@ -109,12 +109,11 @@ unsigned SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, MachineBasicBlock *FBB, - const SmallVectorImpl &Cond)const{ - // FIXME this should probably take a DebugLoc argument - DebugLoc dl; + const SmallVectorImpl &Cond, + DebugLoc DL)const{ // Can only insert uncond branches so far. assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!"); - BuildMI(&MBB, dl, get(SP::BA)).addMBB(TBB); + BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB); return 1; } Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h?rev=106243&r1=106242&r2=106243&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h (original) +++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h Thu Jun 17 17:43:56 2010 @@ -68,7 +68,8 @@ virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, - const SmallVectorImpl &Cond) const; + const SmallVectorImpl &Cond, + DebugLoc DL) const; virtual bool copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp?rev=106243&r1=106242&r2=106243&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp Thu Jun 17 17:43:56 2010 @@ -521,9 +521,8 @@ unsigned SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, - const SmallVectorImpl &Cond) const { - // FIXME: this should probably have a DebugLoc operand - DebugLoc DL; + const SmallVectorImpl &Cond, + DebugLoc DL) const { // Shouldn't be a fall through. assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 1 || Cond.size() == 0) && Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h?rev=106243&r1=106242&r2=106243&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h Thu Jun 17 17:43:56 2010 @@ -102,7 +102,8 @@ bool AllowModify) const; virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, - const SmallVectorImpl &Cond) const; + const SmallVectorImpl &Cond, + DebugLoc DL) const; virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; SystemZCC::CondCodes getOppositeCondition(SystemZCC::CondCodes CC) const; Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=106243&r1=106242&r2=106243&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Thu Jun 17 17:43:56 2010 @@ -891,7 +891,7 @@ BuildMI(MBB, DL, TII.get(X86::JP_4)).addMBB(TrueMBB); } - FastEmitBranch(FalseMBB); + FastEmitBranch(FalseMBB, DL); MBB->addSuccessor(TrueMBB); return true; } @@ -946,7 +946,7 @@ BuildMI(MBB, DL, TII.get(OpCode == X86::SETOr ? X86::JO_4 : X86::JB_4)) .addMBB(TrueMBB); - FastEmitBranch(FalseMBB); + FastEmitBranch(FalseMBB, DL); MBB->addSuccessor(TrueMBB); return true; } @@ -961,7 +961,7 @@ BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg); BuildMI(MBB, DL, TII.get(X86::JNE_4)).addMBB(TrueMBB); - FastEmitBranch(FalseMBB); + FastEmitBranch(FalseMBB, DL); MBB->addSuccessor(TrueMBB); return true; } Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=106243&r1=106242&r2=106243&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Thu Jun 17 17:43:56 2010 @@ -1839,9 +1839,8 @@ unsigned X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, - const SmallVectorImpl &Cond) const { - // FIXME this should probably have a DebugLoc operand - DebugLoc dl; + const SmallVectorImpl &Cond, + DebugLoc DL) const { // Shouldn't be a fall through. assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 1 || Cond.size() == 0) && @@ -1850,7 +1849,7 @@ if (Cond.empty()) { // Unconditional branch? assert(!FBB && "Unconditional branch with multiple successors!"); - BuildMI(&MBB, dl, get(X86::JMP_4)).addMBB(TBB); + BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB); return 1; } @@ -1860,27 +1859,27 @@ switch (CC) { case X86::COND_NP_OR_E: // Synthesize NP_OR_E with two branches. - BuildMI(&MBB, dl, get(X86::JNP_4)).addMBB(TBB); + BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB); ++Count; - BuildMI(&MBB, dl, get(X86::JE_4)).addMBB(TBB); + BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB); ++Count; break; case X86::COND_NE_OR_P: // Synthesize NE_OR_P with two branches. - BuildMI(&MBB, dl, get(X86::JNE_4)).addMBB(TBB); + BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB); ++Count; - BuildMI(&MBB, dl, get(X86::JP_4)).addMBB(TBB); + BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB); ++Count; break; default: { unsigned Opc = GetCondBranchFromCond(CC); - BuildMI(&MBB, dl, get(Opc)).addMBB(TBB); + BuildMI(&MBB, DL, get(Opc)).addMBB(TBB); ++Count; } } if (FBB) { // Two-way Conditional branch. Insert the second branch. - BuildMI(&MBB, dl, get(X86::JMP_4)).addMBB(FBB); + BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB); ++Count; } return Count; Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=106243&r1=106242&r2=106243&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Thu Jun 17 17:43:56 2010 @@ -612,7 +612,8 @@ virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, - const SmallVectorImpl &Cond) const; + const SmallVectorImpl &Cond, + DebugLoc DL) const; virtual bool copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SrcReg, Modified: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp?rev=106243&r1=106242&r2=106243&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp Thu Jun 17 17:43:56 2010 @@ -299,9 +299,8 @@ unsigned XCoreInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, MachineBasicBlock *FBB, - const SmallVectorImpl &Cond)const{ - // FIXME there should probably be a DebugLoc argument here - DebugLoc dl; + const SmallVectorImpl &Cond, + DebugLoc DL)const{ // Shouldn't be a fall through. assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 2 || Cond.size() == 0) && @@ -310,11 +309,11 @@ if (FBB == 0) { // One way branch. if (Cond.empty()) { // Unconditional branch - BuildMI(&MBB, dl, get(XCore::BRFU_lu6)).addMBB(TBB); + BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(TBB); } else { // Conditional branch. unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); - BuildMI(&MBB, dl, get(Opc)).addReg(Cond[1].getReg()) + BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()) .addMBB(TBB); } return 1; @@ -323,9 +322,9 @@ // Two-way Conditional branch. assert(Cond.size() == 2 && "Unexpected number of components!"); unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); - BuildMI(&MBB, dl, get(Opc)).addReg(Cond[1].getReg()) + BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()) .addMBB(TBB); - BuildMI(&MBB, dl, get(XCore::BRFU_lu6)).addMBB(FBB); + BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(FBB); return 2; } Modified: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h?rev=106243&r1=106242&r2=106243&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h (original) +++ llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h Thu Jun 17 17:43:56 2010 @@ -58,8 +58,9 @@ bool AllowModify) const; virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, - MachineBasicBlock *FBB, - const SmallVectorImpl &Cond) const; + MachineBasicBlock *FBB, + const SmallVectorImpl &Cond, + DebugLoc DL) const; virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; From stuart at apple.com Thu Jun 17 17:43:58 2010 From: stuart at apple.com (Stuart Hastings) Date: Thu, 17 Jun 2010 22:43:58 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r106244 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Message-ID: <20100617224358.507712A6C12D@llvm.org> Author: stuart Date: Thu Jun 17 17:43:58 2010 New Revision: 106244 URL: http://llvm.org/viewvc/llvm-project?rev=106244&view=rev Log: Add a stop point to empty basic blocks. Radar 7421831. Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=106244&r1=106243&r2=106244&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Thu Jun 17 17:43:58 2010 @@ -812,11 +812,12 @@ basic_block bb; edge e; edge_iterator ei; + tree stmt = NULL_TREE; FOR_EACH_BB (bb) { for (block_stmt_iterator bsi = bsi_start (bb); !bsi_end_p (bsi); bsi_next (&bsi)) { MemRef DestLoc; - tree stmt = bsi_stmt (bsi); + stmt = bsi_stmt (bsi); // If this stmt returns an aggregate value (e.g. a call whose result is // ignored), create a temporary to receive the value. Note that we don't @@ -828,6 +829,21 @@ Emit(stmt, DestLoc.Ptr ? &DestLoc : NULL); } + // If we didn't see any statements, the current bb is an empty + // basic block. But an empty block must have one outgoing edge, + // and there might be some location info there; grab it. + if (!stmt && EmitDebugInfo()) { + assert(EDGE_COUNT(b->succs) == 1 && "empty basic block with multiple successors?") ; + e = EDGE_I(bb->succs, 0); + source_locus locus = e->goto_locus; + if (locus) { + // Set new location on the way up the tree. + TheDebugInfo->setLocationFile(LOCATION_FILE(*locus)); + TheDebugInfo->setLocationLine(LOCATION_LINE(*locus)); + } + TheDebugInfo->EmitStopPoint(Fn, Builder.GetInsertBlock(), Builder); + } + FOR_EACH_EDGE (e, ei, bb->succs) if (e->flags & EDGE_FALLTHRU) break; From bruno.cardoso at gmail.com Thu Jun 17 18:00:16 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Thu, 17 Jun 2010 23:00:16 -0000 Subject: [llvm-commits] [llvm] r106246 - /llvm/trunk/utils/TableGen/Record.cpp Message-ID: <20100617230017.059BB2A6C12C@llvm.org> Author: bruno Date: Thu Jun 17 18:00:16 2010 New Revision: 106246 URL: http://llvm.org/viewvc/llvm-project?rev=106246&view=rev Log: In case Rec is a definition and not a class, do the proper comparison! Modified: llvm/trunk/utils/TableGen/Record.cpp Modified: llvm/trunk/utils/TableGen/Record.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/Record.cpp?rev=106246&r1=106245&r2=106246&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/Record.cpp (original) +++ llvm/trunk/utils/TableGen/Record.cpp Thu Jun 17 18:00:16 2010 @@ -270,7 +270,15 @@ } bool RecordRecTy::baseClassOf(const RecordRecTy *RHS) const { - return Rec == RHS->getRecord() || RHS->getRecord()->isSubClassOf(Rec); + if (Rec == RHS->getRecord() || RHS->getRecord()->isSubClassOf(Rec)) + return true; + + const std::vector &SC = Rec->getSuperClasses(); + for (unsigned i = 0, e = SC.size(); i != e; ++i) + if (RHS->getRecord()->isSubClassOf(SC[i])) + return true; + + return false; } From fjahanian at apple.com Thu Jun 17 18:03:28 2010 From: fjahanian at apple.com (Fariborz Jahanian) Date: Thu, 17 Jun 2010 23:03:28 -0000 Subject: [llvm-commits] [test-suite] r106249 - /test-suite/trunk/SingleSource/UnitTests/ObjC++/property-reference.mm Message-ID: <20100617230328.867292A6C12C@llvm.org> Author: fjahanian Date: Thu Jun 17 18:03:28 2010 New Revision: 106249 URL: http://llvm.org/viewvc/llvm-project?rev=106249&view=rev Log: Test case for fix to radar 7501812 (clang fix). Added: test-suite/trunk/SingleSource/UnitTests/ObjC++/property-reference.mm Added: test-suite/trunk/SingleSource/UnitTests/ObjC++/property-reference.mm URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/ObjC%2B%2B/property-reference.mm?rev=106249&view=auto ============================================================================== --- test-suite/trunk/SingleSource/UnitTests/ObjC++/property-reference.mm (added) +++ test-suite/trunk/SingleSource/UnitTests/ObjC++/property-reference.mm Thu Jun 17 18:03:28 2010 @@ -0,0 +1,69 @@ +#import +#import +// rdar: //7501812 + +class Value +{ +public: + explicit Value(int amount) : m_amount(amount){} + + int GetAmount() const { return m_amount; } + +private: + int m_amount; +}; + +typedef std::tr1::shared_ptr ValuePtr; + + at interface ValueUser : NSObject +{ + at private + ValuePtr* _valuePtr; +} +- (id)initWithValue:(ValuePtr&)valuePtr; + at property ValuePtr value; + at end + + at implementation ValueUser +- (id)initWithValue:(ValuePtr&)valuePtr +{ + self = [super init]; + _valuePtr = new ValuePtr(valuePtr); + return self; +} + +- (void)setValue:(ValuePtr)valuePtr +{ + *_valuePtr = valuePtr; +} + +- (ValuePtr)value +{ + return *_valuePtr; +} + +- (void)dealloc +{ + delete _valuePtr; + [super dealloc]; +} + at end + +int main() +{ + NSAutoreleasePool* pool = [[NSAutoreleasePool alloc] init]; + + ValuePtr valuePtr(new Value(42)); + ValueUser* valueUser = [[ValueUser alloc] initWithValue:valuePtr]; + +#ifdef __clang__ + ::NSLog(@"The value's amount is %d", (valueUser.value)->GetAmount()); +#endif + ::NSLog(@"The value's amount is %d", [valueUser value]->GetAmount()); + + [valueUser release]; + + [pool release]; + + return 0; +} From bruno.cardoso at gmail.com Thu Jun 17 18:05:30 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Thu, 17 Jun 2010 23:05:30 -0000 Subject: [llvm-commits] [llvm] r106251 - in /llvm/trunk/lib/Target/X86: X86InstrFormats.td X86InstrSSE.td Message-ID: <20100617230530.A35B52A6C12C@llvm.org> Author: bruno Date: Thu Jun 17 18:05:30 2010 New Revision: 106251 URL: http://llvm.org/viewvc/llvm-project?rev=106251&view=rev Log: Use new tablegen resources in SSE tablegen code. This will be done incrementally and intermixed with the adding of more AVX instructions. This is a first step in that direction Modified: llvm/trunk/lib/Target/X86/X86InstrFormats.td llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFormats.td?rev=106251&r1=106250&r2=106251&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrFormats.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrFormats.td Thu Jun 17 18:05:30 2010 @@ -214,6 +214,17 @@ let CodeSize = 3; } +// SI - SSE 1 & 2 scalar instructions +class SI o, Format F, dag outs, dag ins, string asm, list pattern> + : I { + let Predicates = !if(hasVEX_4VPrefix /* VEX_4V */, + !if(!eq(Prefix, 11 /* XD */), [HasAVX, HasSSE2], [HasAVX, HasSSE1]), + !if(!eq(Prefix, 12 /* XS */), [HasSSE2], [HasSSE1])); + + // AVX instructions have a 'v' prefix in the mnemonic + let AsmString = !if(hasVEX_4VPrefix, !strconcat("v", asm), asm); +} + // SSE1 Instruction Templates: // // SSI - SSE1 instructions with XS prefix. Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=106251&r1=106250&r2=106251&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Jun 17 18:05:30 2010 @@ -646,6 +646,17 @@ defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef, 1, 1, 0>; } +/// sse12_fp_scalar - SSE 1 & 2 scalar instructions class +multiclass sse12_fp_scalar opc, string OpcodeStr, SDNode OpNode, + RegisterClass RC, X86MemOperand memop> { + let isCommutable = 1 in { + def rr : SI; + } + def rm : SI; +} + /// basic_sse12_fp_binop_rm - SSE 1 & 2 binops come in both scalar and /// vector forms. /// @@ -660,66 +671,30 @@ let Constraints = "$src1 = $dst" in { multiclass basic_sse12_fp_binop_rm opc, string OpcodeStr, SDNode OpNode, bit Commutable = 0> { - // Scalar operation, reg+reg. - def SSrr : SSI { - let isCommutable = Commutable; - } - - def SDrr : SDI { - let isCommutable = Commutable; - } - - def V#NAME#SSrr : VSSI { - let isCommutable = Commutable; - let Constraints = ""; - let isAsmParserOnly = 1; - } - - def V#NAME#SDrr : VSDI { - let isCommutable = Commutable; - let Constraints = ""; - let isAsmParserOnly = 1; - } - - // Scalar operation, reg+mem. - def SSrm : SSI; - - def SDrm : SDI; - - def V#NAME#SSrm : VSSI { - let Constraints = ""; - let isAsmParserOnly = 1; - } - def V#NAME#SDrm : VSDI { - let Constraints = ""; - let isAsmParserOnly = 1; + let Constraints = "", isAsmParserOnly = 1, hasVEX_4VPrefix = 1 in { + // Scalar operation, reg+reg. + let Prefix = 12 /* XS */ in + defm V#NAME#SS : sse12_fp_scalar; + + let Prefix = 11 /* XD */ in + defm V#NAME#SD : sse12_fp_scalar; + } + + let Constraints = "$src1 = $dst" in { + // Scalar operation, reg+reg. + let Prefix = 12 /* XS */ in + defm SS : sse12_fp_scalar; + let Prefix = 11 /* XD */ in + defm SD : sse12_fp_scalar; } // Vector operation, reg+reg. @@ -863,8 +838,11 @@ // Arithmetic instructions defm ADD : basic_sse12_fp_binop_rm<0x58, "add", fadd, 1>; defm MUL : basic_sse12_fp_binop_rm<0x59, "mul", fmul, 1>; -defm SUB : basic_sse12_fp_binop_rm<0x5C, "sub", fsub>; -defm DIV : basic_sse12_fp_binop_rm<0x5E, "div", fdiv>; + +let isCommutable = 0 in { + defm SUB : basic_sse12_fp_binop_rm<0x5C, "sub", fsub>; + defm DIV : basic_sse12_fp_binop_rm<0x5E, "div", fdiv>; +} /// sse12_fp_binop_rm - Other SSE 1 & 2 binops /// From daniel at zuster.org Thu Jun 17 18:19:34 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 17 Jun 2010 23:19:34 -0000 Subject: [llvm-commits] [zorg] r106253 - /zorg/trunk/lnt/lnt/util/ImportData.py Message-ID: <20100617231934.826BF2A6C12C@llvm.org> Author: ddunbar Date: Thu Jun 17 18:19:34 2010 New Revision: 106253 URL: http://llvm.org/viewvc/llvm-project?rev=106253&view=rev Log: Add a FIXME. Modified: zorg/trunk/lnt/lnt/util/ImportData.py Modified: zorg/trunk/lnt/lnt/util/ImportData.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/util/ImportData.py?rev=106253&r1=106252&r2=106253&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/util/ImportData.py (original) +++ zorg/trunk/lnt/lnt/util/ImportData.py Thu Jun 17 18:19:34 2010 @@ -71,6 +71,8 @@ if not disable_email and toAddress is not None: print >>log, "\nMAILING RESULTS TO: %r\n" % toAddress + # FIXME: The url below is wrong, it shouldn't be hardcoded to + # nightlytest. NTEmailReport.emailReport(db, run, "%s/db_%s/nightlytest/" % (config.zorgURL, db_name), From deeppatel1987 at gmail.com Thu Jun 17 18:30:09 2010 From: deeppatel1987 at gmail.com (Sandeep Patel) Date: Thu, 17 Jun 2010 23:30:09 +0000 Subject: [llvm-commits] [patch] Update llvm-gcc to produce "" for the default calling convention on ARM In-Reply-To: References: <76A0798C-9AB8-43E8-99C1-7AFE618CEBEB@apple.com> Message-ID: On Thu, Jun 17, 2010 at 5:57 PM, Anton Korobeynikov wrote: >> Why isn't aapcs-vfp the default cc on "an AAPCS-VFP platform"? > It is. The problem is that libcalls should use AAPCS w/o VFP. See ARMISelLowering.cpp:247. I have a more precise patch for this area I haven't submitted yet, but the essence is the same. Also, ARM (CodeSourcery) introduced the syntax __attribute__((pcs("aapcs"))) into GCC to allow mixed declarations of different CCs. I haven't yet patched llvm-gcc or Clang with this syntax, but I wanted to be prepared to do so when we saw a use for it. (I have no idea why ARM wanted this syntax since they just slipped it in with other changes.) deep From gohman at apple.com Thu Jun 17 18:34:09 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 17 Jun 2010 23:34:09 -0000 Subject: [llvm-commits] [llvm] r106254 - /llvm/trunk/lib/Analysis/ScalarEvolution.cpp Message-ID: <20100617233409.AAE092A6C12C@llvm.org> Author: djg Date: Thu Jun 17 18:34:09 2010 New Revision: 106254 URL: http://llvm.org/viewvc/llvm-project?rev=106254&view=rev Log: Simplify this code. Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=106254&r1=106253&r2=106254&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Thu Jun 17 18:34:09 2010 @@ -1747,17 +1747,9 @@ // NLI * LI * {Start,+,Step} --> NLI * {LI*Start,+,LI*Step} SmallVector NewOps; NewOps.reserve(AddRec->getNumOperands()); - if (LIOps.size() == 1) { - const SCEV *Scale = LIOps[0]; - for (unsigned i = 0, e = AddRec->getNumOperands(); i != e; ++i) - NewOps.push_back(getMulExpr(Scale, AddRec->getOperand(i))); - } else { - for (unsigned i = 0, e = AddRec->getNumOperands(); i != e; ++i) { - SmallVector MulOps(LIOps.begin(), LIOps.end()); - MulOps.push_back(AddRec->getOperand(i)); - NewOps.push_back(getMulExpr(MulOps)); - } - } + const SCEV *Scale = getMulExpr(LIOps); + for (unsigned i = 0, e = AddRec->getNumOperands(); i != e; ++i) + NewOps.push_back(getMulExpr(Scale, AddRec->getOperand(i))); // It's tempting to propagate the NSW flag here, but nsw multiplication // is not associative so this isn't necessarily safe. From gohman at apple.com Thu Jun 17 19:06:04 2010 From: gohman at apple.com (Dan Gohman) Date: Fri, 18 Jun 2010 00:06:04 -0000 Subject: [llvm-commits] [llvm] r106255 - /llvm/trunk/test/CodeGen/X86/vec-trunc-store.ll Message-ID: <20100618000604.1BD602A6C12C@llvm.org> Author: djg Date: Thu Jun 17 19:06:03 2010 New Revision: 106255 URL: http://llvm.org/viewvc/llvm-project?rev=106255&view=rev Log: Make this test less fragile. Modified: llvm/trunk/test/CodeGen/X86/vec-trunc-store.ll Modified: llvm/trunk/test/CodeGen/X86/vec-trunc-store.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec-trunc-store.ll?rev=106255&r1=106254&r2=106255&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/vec-trunc-store.ll (original) +++ llvm/trunk/test/CodeGen/X86/vec-trunc-store.ll Thu Jun 17 19:06:03 2010 @@ -1,13 +1,15 @@ -; RUN: llc < %s -march=x86-64 -disable-mmx | grep punpcklwd | count 2 +; RUN: llc < %s -march=x86-64 -disable-mmx >/dev/null -define void @foo() nounwind { - %cti69 = trunc <8 x i32> undef to <8 x i16> ; <<8 x i16>> [#uses=1] +define void @foo(<8 x i32>* %p) nounwind { + %t = load <8 x i32>* %p + %cti69 = trunc <8 x i32> %t to <8 x i16> ; <<8 x i16>> [#uses=1] store <8 x i16> %cti69, <8 x i16>* undef ret void } -define void @bar() nounwind { - %cti44 = trunc <4 x i32> undef to <4 x i16> ; <<4 x i16>> [#uses=1] +define void @bar(<4 x i32>* %p) nounwind { + %t = load <4 x i32>* %p + %cti44 = trunc <4 x i32> %t to <4 x i16> ; <<4 x i16>> [#uses=1] store <4 x i16> %cti44, <4 x i16>* undef ret void } From gohman at apple.com Thu Jun 17 19:08:30 2010 From: gohman at apple.com (Dan Gohman) Date: Fri, 18 Jun 2010 00:08:30 -0000 Subject: [llvm-commits] [llvm] r106256 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Message-ID: <20100618000830.3AA562A6C12C@llvm.org> Author: djg Date: Thu Jun 17 19:08:30 2010 New Revision: 106256 URL: http://llvm.org/viewvc/llvm-project?rev=106256&view=rev Log: Handle ext(ext(x)) -> ext(x) immediately, since it's simple. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=106256&r1=106255&r2=106256&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Jun 17 19:08:30 2010 @@ -2474,7 +2474,8 @@ VT.getVectorNumElements() == Operand.getValueType().getVectorNumElements()) && "Vector element count mismatch!"); - if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND) + if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || + OpOpcode == ISD::ANY_EXTEND) // (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x) return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); break; From daniel at zuster.org Thu Jun 17 19:25:34 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Fri, 18 Jun 2010 00:25:34 -0000 Subject: [llvm-commits] [test-suite] r106257 - in /test-suite/trunk/SingleSource/UnitTests/ObjC++: property-reference.mm property-reference.reference_output Message-ID: <20100618002534.C122B2A6C12C@llvm.org> Author: ddunbar Date: Thu Jun 17 19:25:34 2010 New Revision: 106257 URL: http://llvm.org/viewvc/llvm-project?rev=106257&view=rev Log: Make test more deterministic and add reference output. Added: test-suite/trunk/SingleSource/UnitTests/ObjC++/property-reference.reference_output Modified: test-suite/trunk/SingleSource/UnitTests/ObjC++/property-reference.mm Modified: test-suite/trunk/SingleSource/UnitTests/ObjC++/property-reference.mm URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/ObjC%2B%2B/property-reference.mm?rev=106257&r1=106256&r2=106257&view=diff ============================================================================== --- test-suite/trunk/SingleSource/UnitTests/ObjC++/property-reference.mm (original) +++ test-suite/trunk/SingleSource/UnitTests/ObjC++/property-reference.mm Thu Jun 17 19:25:34 2010 @@ -1,4 +1,4 @@ -#import +#import #import // rdar: //7501812 @@ -56,10 +56,8 @@ ValuePtr valuePtr(new Value(42)); ValueUser* valueUser = [[ValueUser alloc] initWithValue:valuePtr]; -#ifdef __clang__ - ::NSLog(@"The value's amount is %d", (valueUser.value)->GetAmount()); -#endif - ::NSLog(@"The value's amount is %d", [valueUser value]->GetAmount()); + printf("The value's amount is %d\n", (valueUser.value)->GetAmount()); + printf("The value's amount is %d\n", [valueUser value]->GetAmount()); [valueUser release]; Added: test-suite/trunk/SingleSource/UnitTests/ObjC++/property-reference.reference_output URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/ObjC%2B%2B/property-reference.reference_output?rev=106257&view=auto ============================================================================== --- test-suite/trunk/SingleSource/UnitTests/ObjC++/property-reference.reference_output (added) +++ test-suite/trunk/SingleSource/UnitTests/ObjC++/property-reference.reference_output Thu Jun 17 19:25:34 2010 @@ -0,0 +1,3 @@ +The value's amount is 42 +The value's amount is 42 +exit 0 From sabre at nondot.org Thu Jun 17 19:35:33 2010 From: sabre at nondot.org (Chris Lattner) Date: Fri, 18 Jun 2010 00:35:33 -0000 Subject: [llvm-commits] [llvm] r106259 - /llvm/trunk/Makefile.rules Message-ID: <20100618003533.121702A6C12C@llvm.org> Author: lattner Date: Thu Jun 17 19:35:32 2010 New Revision: 106259 URL: http://llvm.org/viewvc/llvm-project?rev=106259&view=rev Log: improve portability to solaris 10, PR7380, patch by Simon Billingsley! Modified: llvm/trunk/Makefile.rules Modified: llvm/trunk/Makefile.rules URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=106259&r1=106258&r2=106259&view=diff ============================================================================== --- llvm/trunk/Makefile.rules (original) +++ llvm/trunk/Makefile.rules Thu Jun 17 19:35:32 2010 @@ -808,7 +808,7 @@ $(RecursiveTargets):: $(Verb) for dir in $(DIRS); do \ if ([ ! -f $$dir/Makefile ] || \ - test $$dir/Makefile -ot $(PROJ_SRC_DIR)/$$dir/Makefile ); then \ + command test $$dir/Makefile -ot $(PROJ_SRC_DIR)/$$dir/Makefile ); then \ $(MKDIR) $$dir; \ $(CP) $(PROJ_SRC_DIR)/$$dir/Makefile $$dir/Makefile; \ fi; \ @@ -831,7 +831,7 @@ $(RecursiveTargets):: $(Verb) for dir in $(EXPERIMENTAL_DIRS); do \ if ([ ! -f $$dir/Makefile ] || \ - test $$dir/Makefile -ot $(PROJ_SRC_DIR)/$$dir/Makefile ); then \ + command test $$dir/Makefile -ot $(PROJ_SRC_DIR)/$$dir/Makefile ); then \ $(MKDIR) $$dir; \ $(CP) $(PROJ_SRC_DIR)/$$dir/Makefile $$dir/Makefile; \ fi; \ @@ -866,7 +866,7 @@ $(ParallelTargets) : $(Verb) if ([ ! -f $(@D)/Makefile ] || \ - test $(@D)/Makefile -ot \ + command test $(@D)/Makefile -ot \ $(PROJ_SRC_DIR)/$(@D)/Makefile ); then \ $(MKDIR) $(@D); \ $(CP) $(PROJ_SRC_DIR)/$(@D)/Makefile $(@D)/Makefile; \ @@ -887,7 +887,7 @@ $(Verb) for dir in $(OPTIONAL_DIRS); do \ if [ -d $(PROJ_SRC_DIR)/$$dir ]; then\ if ([ ! -f $$dir/Makefile ] || \ - test $$dir/Makefile -ot $(PROJ_SRC_DIR)/$$dir/Makefile ); then \ + command test $$dir/Makefile -ot $(PROJ_SRC_DIR)/$$dir/Makefile ); then \ $(MKDIR) $$dir; \ $(CP) $(PROJ_SRC_DIR)/$$dir/Makefile $$dir/Makefile; \ fi; \ From gohman at apple.com Thu Jun 17 19:53:08 2010 From: gohman at apple.com (Dan Gohman) Date: Fri, 18 Jun 2010 00:53:08 -0000 Subject: [llvm-commits] [llvm] r106260 - /llvm/trunk/lib/Analysis/ScalarEvolutionAliasAnalysis.cpp Message-ID: <20100618005308.4C6B92A6C12C@llvm.org> Author: djg Date: Thu Jun 17 19:53:08 2010 New Revision: 106260 URL: http://llvm.org/viewvc/llvm-project?rev=106260&view=rev Log: Fix a typo in a comment. Modified: llvm/trunk/lib/Analysis/ScalarEvolutionAliasAnalysis.cpp Modified: llvm/trunk/lib/Analysis/ScalarEvolutionAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolutionAliasAnalysis.cpp?rev=106260&r1=106259&r2=106260&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolutionAliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolutionAliasAnalysis.cpp Thu Jun 17 19:53:08 2010 @@ -12,7 +12,7 @@ // // This differs from traditional loop dependence analysis in that it tests // for dependencies within a single iteration of a loop, rather than -// dependences between different iterations. +// dependencies between different iterations. // // ScalarEvolution has a more complete understanding of pointer arithmetic // than BasicAliasAnalysis' collection of ad-hoc analyses. From gohman at apple.com Thu Jun 17 20:05:21 2010 From: gohman at apple.com (Dan Gohman) Date: Fri, 18 Jun 2010 01:05:21 -0000 Subject: [llvm-commits] [llvm] r106263 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAGISel.h include/llvm/Target/TargetLowering.h lib/CodeGen/SelectionDAG/DAGCombiner.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp lib/CodeGen/SelectionDAG/TargetLowering.cpp lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/shift-folding.ll test/CodeGen/X86/store-narrow.ll Message-ID: <20100618010522.2C1652A6C12C@llvm.org> Author: djg Date: Thu Jun 17 20:05:21 2010 New Revision: 106263 URL: http://llvm.org/viewvc/llvm-project?rev=106263&view=rev Log: Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass, which is faster, simpler, and less surprising. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h llvm/trunk/include/llvm/Target/TargetLowering.h llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/test/CodeGen/X86/shift-folding.ll llvm/trunk/test/CodeGen/X86/store-narrow.ll Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h?rev=106263&r1=106262&r2=106263&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h Thu Jun 17 20:05:21 2010 @@ -292,7 +292,6 @@ MachineBasicBlock *CodeGenAndEmitDAG(MachineBasicBlock *BB); void LowerArguments(const BasicBlock *BB); - void ShrinkDemandedOps(); void ComputeLiveOutVRegInfo(); /// Create the scheduler. If a specific scheduler was specified Modified: llvm/trunk/include/llvm/Target/TargetLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=106263&r1=106262&r2=106263&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetLowering.h (original) +++ llvm/trunk/include/llvm/Target/TargetLowering.h Thu Jun 17 20:05:21 2010 @@ -766,14 +766,12 @@ SelectionDAG &DAG; bool LegalTys; bool LegalOps; - bool ShrinkOps; SDValue Old; SDValue New; explicit TargetLoweringOpt(SelectionDAG &InDAG, - bool LT, bool LO, - bool Shrink = false) : - DAG(InDAG), LegalTys(LT), LegalOps(LO), ShrinkOps(Shrink) {} + bool LT, bool LO) : + DAG(InDAG), LegalTys(LT), LegalOps(LO) {} bool LegalTypes() const { return LegalTys; } bool LegalOperations() const { return LegalOps; } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=106263&r1=106262&r2=106263&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Jun 17 20:05:21 2010 @@ -2028,7 +2028,7 @@ // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) - // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) + // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) // // do not sink logical op inside of a vector extend, since it may combine // into a vsetcc. @@ -2038,7 +2038,10 @@ // Avoid infinite looping with PromoteIntBinOp. (N0.getOpcode() == ISD::ANY_EXTEND && (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) || - (N0.getOpcode() == ISD::TRUNCATE && TLI.isTypeLegal(Op0VT))) && + (N0.getOpcode() == ISD::TRUNCATE && + (!TLI.isZExtFree(VT, Op0VT) || + !TLI.isTruncateFree(Op0VT, VT)) && + TLI.isTypeLegal(Op0VT))) && !VT.isVector() && Op0VT == N1.getOperand(0).getValueType() && (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { @@ -2425,6 +2428,11 @@ if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) return SDValue(Rot, 0); + // Simplify the operands using demanded-bits information. + if (!VT.isVector() && + SimplifyDemandedBits(SDValue(N, 0))) + return SDValue(N, 0); + return SDValue(); } @@ -3158,6 +3166,11 @@ return NewSRL; } + // Attempt to convert a srl of a load into a narrower zero-extending load. + SDValue NarrowLoad = ReduceLoadWidth(N); + if (NarrowLoad.getNode()) + return NarrowLoad; + // Here is a common situation. We want to optimize: // // %a = ... @@ -3635,10 +3648,7 @@ // fold (zext (truncate x)) -> (and x, mask) if (N0.getOpcode() == ISD::TRUNCATE && - (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT)) && - (!TLI.isTruncateFree(N0.getOperand(0).getValueType(), - N0.getValueType()) || - !TLI.isZExtFree(N0.getValueType(), VT))) { + (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { SDValue Op = N0.getOperand(0); if (Op.getValueType().bitsLT(VT)) { Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); @@ -4024,6 +4034,7 @@ /// extended, also fold the extension to form a extending load. SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { unsigned Opc = N->getOpcode(); + ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; SDValue N0 = N->getOperand(0); EVT VT = N->getValueType(0); @@ -4040,6 +4051,15 @@ ExtVT = cast(N->getOperand(1))->getVT(); if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, ExtVT)) return SDValue(); + } else if (Opc == ISD::SRL) { + // Annother special-case: SRL is basically zero-extending a narrower + // value. + ExtType = ISD::ZEXTLOAD; + N0 = SDValue(N, 0); + ConstantSDNode *N01 = dyn_cast(N0.getOperand(1)); + if (!N01) return SDValue(); + ExtVT = EVT::getIntegerVT(*DAG.getContext(), + VT.getSizeInBits() - N01->getZExtValue()); } unsigned EVTBits = ExtVT.getSizeInBits(); @@ -4243,8 +4263,17 @@ // fold (truncate (load x)) -> (smaller load x) // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) - if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) - return ReduceLoadWidth(N); + if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { + SDValue Reduced = ReduceLoadWidth(N); + if (Reduced.getNode()) + return Reduced; + } + + // Simplify the operands using demanded-bits information. + if (!VT.isVector() && + SimplifyDemandedBits(SDValue(N, 0))) + return SDValue(N, 0); + return SDValue(); } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=106263&r1=106262&r2=106263&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Jun 17 20:05:21 2010 @@ -2474,10 +2474,18 @@ VT.getVectorNumElements() == Operand.getValueType().getVectorNumElements()) && "Vector element count mismatch!"); + if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ANY_EXTEND) // (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x) return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); + + // (ext (trunx x)) -> x + if (OpOpcode == ISD::TRUNCATE) { + SDValue OpOp = Operand.getNode()->getOperand(0); + if (OpOp.getValueType() == VT) + return OpOp; + } break; case ISD::TRUNCATE: assert(VT.isInteger() && Operand.getValueType().isInteger() && Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=106263&r1=106262&r2=106263&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Jun 17 20:05:21 2010 @@ -372,102 +372,6 @@ }; } -/// TrivialTruncElim - Eliminate some trivial nops that can result from -/// ShrinkDemandedOps: (trunc (ext n)) -> n. -static bool TrivialTruncElim(SDValue Op, - TargetLowering::TargetLoweringOpt &TLO) { - SDValue N0 = Op.getOperand(0); - EVT VT = Op.getValueType(); - if ((N0.getOpcode() == ISD::ZERO_EXTEND || - N0.getOpcode() == ISD::SIGN_EXTEND || - N0.getOpcode() == ISD::ANY_EXTEND) && - N0.getOperand(0).getValueType() == VT) { - return TLO.CombineTo(Op, N0.getOperand(0)); - } - return false; -} - -/// ShrinkDemandedOps - A late transformation pass that shrink expressions -/// using TargetLowering::TargetLoweringOpt::ShrinkDemandedOp. It converts -/// x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. -void SelectionDAGISel::ShrinkDemandedOps() { - SmallVector Worklist; - SmallPtrSet InWorklist; - - // Add all the dag nodes to the worklist. - Worklist.reserve(CurDAG->allnodes_size()); - for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(), - E = CurDAG->allnodes_end(); I != E; ++I) { - Worklist.push_back(I); - InWorklist.insert(I); - } - - TargetLowering::TargetLoweringOpt TLO(*CurDAG, true, true, true); - while (!Worklist.empty()) { - SDNode *N = Worklist.pop_back_val(); - InWorklist.erase(N); - - if (N->use_empty() && N != CurDAG->getRoot().getNode()) { - // Deleting this node may make its operands dead, add them to the worklist - // if they aren't already there. - for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) - if (InWorklist.insert(N->getOperand(i).getNode())) - Worklist.push_back(N->getOperand(i).getNode()); - - CurDAG->DeleteNode(N); - continue; - } - - // Run ShrinkDemandedOp on scalar binary operations. - if (N->getNumValues() != 1 || - !N->getValueType(0).isSimple() || !N->getValueType(0).isInteger()) - continue; - - unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits(); - APInt Demanded = APInt::getAllOnesValue(BitWidth); - APInt KnownZero, KnownOne; - if (!TLI.SimplifyDemandedBits(SDValue(N, 0), Demanded, - KnownZero, KnownOne, TLO) && - (N->getOpcode() != ISD::TRUNCATE || - !TrivialTruncElim(SDValue(N, 0), TLO))) - continue; - - // Revisit the node. - assert(!InWorklist.count(N) && "Already in worklist"); - Worklist.push_back(N); - InWorklist.insert(N); - - // Replace the old value with the new one. - DEBUG(errs() << "\nShrinkDemandedOps replacing "; - TLO.Old.getNode()->dump(CurDAG); - errs() << "\nWith: "; - TLO.New.getNode()->dump(CurDAG); - errs() << '\n'); - - if (InWorklist.insert(TLO.New.getNode())) - Worklist.push_back(TLO.New.getNode()); - - SDOPsWorkListRemover DeadNodes(Worklist, InWorklist); - CurDAG->ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); - - if (!TLO.Old.getNode()->use_empty()) continue; - - for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); - i != e; ++i) { - SDNode *OpNode = TLO.Old.getNode()->getOperand(i).getNode(); - if (OpNode->hasOneUse()) { - // Add OpNode to the end of the list to revisit. - DeadNodes.RemoveFromWorklist(OpNode); - Worklist.push_back(OpNode); - InWorklist.insert(OpNode); - } - } - - DeadNodes.RemoveFromWorklist(TLO.Old.getNode()); - CurDAG->DeleteNode(TLO.Old.getNode()); - } -} - void SelectionDAGISel::ComputeLiveOutVRegInfo() { SmallPtrSet VisitedNodes; SmallVector Worklist; @@ -636,10 +540,8 @@ DEBUG(dbgs() << "Optimized legalized selection DAG:\n"); DEBUG(CurDAG->dump()); - if (OptLevel != CodeGenOpt::None) { - ShrinkDemandedOps(); + if (OptLevel != CodeGenOpt::None) ComputeLiveOutVRegInfo(); - } if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=106263&r1=106262&r2=106263&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Thu Jun 17 20:05:21 2010 @@ -1042,7 +1042,7 @@ if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) return true; // If the operation can be done in a smaller type, do so. - if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) + if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) return true; // Output known-1 bits are only known if set in both the LHS & RHS. @@ -1076,7 +1076,7 @@ if (TLO.ShrinkDemandedConstant(Op, NewMask)) return true; // If the operation can be done in a smaller type, do so. - if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) + if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) return true; // Output known-0 bits are only known if clear in both the LHS & RHS. @@ -1101,7 +1101,7 @@ if ((KnownZero2 & NewMask) == NewMask) return TLO.CombineTo(Op, Op.getOperand(1)); // If the operation can be done in a smaller type, do so. - if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) + if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) return true; // If all of the unknown bits are known to be zero on one side or the other @@ -1548,7 +1548,7 @@ KnownOne2, TLO, Depth+1)) return true; // See if the operation should be performed at a smaller bit width. - if (TLO.ShrinkOps && TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) + if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) return true; } // FALL THROUGH Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=106263&r1=106262&r2=106263&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Jun 17 20:05:21 2010 @@ -9641,8 +9641,10 @@ if (ShAmt1.getOpcode() == ISD::SUB) { SDValue Sum = ShAmt1.getOperand(0); if (ConstantSDNode *SumC = dyn_cast(Sum)) { - if (SumC->getSExtValue() == Bits && - ShAmt1.getOperand(1) == ShAmt0) + SDValue ShAmt1Op1 = ShAmt1.getOperand(1); + if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE) + ShAmt1Op1 = ShAmt1Op1.getOperand(0); + if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0) return DAG.getNode(Opc, DL, VT, Op0, Op1, DAG.getNode(ISD::TRUNCATE, DL, Modified: llvm/trunk/test/CodeGen/X86/shift-folding.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/shift-folding.ll?rev=106263&r1=106262&r2=106263&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/shift-folding.ll (original) +++ llvm/trunk/test/CodeGen/X86/shift-folding.ll Thu Jun 17 20:05:21 2010 @@ -21,3 +21,8 @@ ret i32* %P2 } +define fastcc i32 @test4(i32* %d) nounwind { + %tmp4 = load i32* %d + %tmp512 = lshr i32 %tmp4, 24 + ret i32 %tmp512 +} Modified: llvm/trunk/test/CodeGen/X86/store-narrow.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/store-narrow.ll?rev=106263&r1=106262&r2=106263&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/store-narrow.ll (original) +++ llvm/trunk/test/CodeGen/X86/store-narrow.ll Thu Jun 17 20:05:21 2010 @@ -67,7 +67,7 @@ ; X64: movw %si, 2(%rdi) ; X32: test4: -; X32: movzwl 8(%esp), %eax +; X32: movl 8(%esp), %eax ; X32: movw %ax, 2(%{{.*}}) } From bruno.cardoso at gmail.com Thu Jun 17 20:12:56 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Fri, 18 Jun 2010 01:12:56 -0000 Subject: [llvm-commits] [llvm] r106264 - in /llvm/trunk: lib/Target/X86/X86InstrSSE.td test/MC/AsmParser/X86/x86_32-encoding.s test/MC/AsmParser/X86/x86_64-encoding.s Message-ID: <20100618011256.D53CB2A6C12C@llvm.org> Author: bruno Date: Thu Jun 17 20:12:56 2010 New Revision: 106264 URL: http://llvm.org/viewvc/llvm-project?rev=106264&view=rev Log: Add {mix,max}{ss,sd}{rr,rm} AVX forms. Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=106264&r1=106263&r2=106264&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Jun 17 20:12:56 2010 @@ -857,30 +857,31 @@ multiclass sse12_fp_binop_rm opc, string OpcodeStr, SDNode OpNode, bit Commutable = 0> { - // Scalar operation, reg+reg. - def SSrr : SSI { - let isCommutable = Commutable; - } - - def SDrr : SDI { - let isCommutable = Commutable; + let Constraints = "", isAsmParserOnly = 1, hasVEX_4VPrefix = 1 in { + // Scalar operation, reg+reg. + let Prefix = 12 /* XS */ in + defm V#NAME#SS : sse12_fp_scalar; + + let Prefix = 11 /* XD */ in + defm V#NAME#SD : sse12_fp_scalar; + } + + let Constraints = "$src1 = $dst" in { + // Scalar operation, reg+reg. + let Prefix = 12 /* XS */ in + defm SS : sse12_fp_scalar; + let Prefix = 11 /* XD */ in + defm SD : sse12_fp_scalar; } - // Scalar operation, reg+mem. - def SSrm : SSI; - - def SDrm : SDI; - // Vector operation, reg+reg. def PSrr : PSI; -defm MIN : sse12_fp_binop_rm<0x5D, "min", X86fmin>; +let isCommutable = 0 in { + defm MAX : sse12_fp_binop_rm<0x5F, "max", X86fmax>; + defm MIN : sse12_fp_binop_rm<0x5D, "min", X86fmin>; +} //===----------------------------------------------------------------------===// // SSE packed FP Instructions Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s?rev=106264&r1=106263&r2=106264&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s Thu Jun 17 20:12:56 2010 @@ -10180,3 +10180,35 @@ // CHECK: vdivpd 3735928559(%ebx,%ecx,8), %xmm2, %xmm5 // CHECK: encoding: [0xc5,0xe9,0x5e,0xac,0xcb,0xef,0xbe,0xad,0xde] vdivpd 3735928559(%ebx,%ecx,8), %xmm2, %xmm5 +// CHECK: vmaxss %xmm2, %xmm4, %xmm6 +// CHECK: encoding: [0xc5,0xda,0x5f,0xf2] + vmaxss %xmm2, %xmm4, %xmm6 + +// CHECK: vmaxsd %xmm2, %xmm4, %xmm6 +// CHECK: encoding: [0xc5,0xdb,0x5f,0xf2] + vmaxsd %xmm2, %xmm4, %xmm6 + +// CHECK: vminss %xmm2, %xmm4, %xmm6 +// CHECK: encoding: [0xc5,0xda,0x5d,0xf2] + vminss %xmm2, %xmm4, %xmm6 + +// CHECK: vminsd %xmm2, %xmm4, %xmm6 +// CHECK: encoding: [0xc5,0xdb,0x5d,0xf2] + vminsd %xmm2, %xmm4, %xmm6 + +// CHECK: vmaxss -4(%ebx,%ecx,8), %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xea,0x5f,0x6c,0xcb,0xfc] + vmaxss -4(%ebx,%ecx,8), %xmm2, %xmm5 + +// CHECK: vmaxsd -4(%ebx,%ecx,8), %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xeb,0x5f,0x6c,0xcb,0xfc] + vmaxsd -4(%ebx,%ecx,8), %xmm2, %xmm5 + +// CHECK: vminss -4(%ebx,%ecx,8), %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xea,0x5d,0x6c,0xcb,0xfc] + vminss -4(%ebx,%ecx,8), %xmm2, %xmm5 + +// CHECK: vminsd -4(%ebx,%ecx,8), %xmm2, %xmm5 +// CHECK: encoding: [0xc5,0xeb,0x5d,0x6c,0xcb,0xfc] + vminsd -4(%ebx,%ecx,8), %xmm2, %xmm5 + Modified: llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s?rev=106264&r1=106263&r2=106264&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s Thu Jun 17 20:12:56 2010 @@ -231,3 +231,36 @@ // CHECK: vdivpd -4(%rcx,%rbx,8), %xmm10, %xmm11 // CHECK: encoding: [0xc5,0x29,0x5e,0x5c,0xd9,0xfc] vdivpd -4(%rcx,%rbx,8), %xmm10, %xmm11 + +// CHECK: vmaxss %xmm10, %xmm14, %xmm12 +// CHECK: encoding: [0xc4,0x41,0x0a,0x5f,0xe2] + vmaxss %xmm10, %xmm14, %xmm12 + +// CHECK: vmaxsd %xmm10, %xmm14, %xmm12 +// CHECK: encoding: [0xc4,0x41,0x0b,0x5f,0xe2] + vmaxsd %xmm10, %xmm14, %xmm12 + +// CHECK: vminss %xmm10, %xmm14, %xmm12 +// CHECK: encoding: [0xc4,0x41,0x0a,0x5d,0xe2] + vminss %xmm10, %xmm14, %xmm12 + +// CHECK: vminsd %xmm10, %xmm14, %xmm12 +// CHECK: encoding: [0xc4,0x41,0x0b,0x5d,0xe2] + vminsd %xmm10, %xmm14, %xmm12 + +// CHECK: vmaxss -4(%rbx,%rcx,8), %xmm12, %xmm10 +// CHECK: encoding: [0xc5,0x1a,0x5f,0x54,0xcb,0xfc] + vmaxss -4(%rbx,%rcx,8), %xmm12, %xmm10 + +// CHECK: vmaxsd -4(%rbx,%rcx,8), %xmm12, %xmm10 +// CHECK: encoding: [0xc5,0x1b,0x5f,0x54,0xcb,0xfc] + vmaxsd -4(%rbx,%rcx,8), %xmm12, %xmm10 + +// CHECK: vminss -4(%rbx,%rcx,8), %xmm12, %xmm10 +// CHECK: encoding: [0xc5,0x1a,0x5d,0x54,0xcb,0xfc] + vminss -4(%rbx,%rcx,8), %xmm12, %xmm10 + +// CHECK: vminsd -4(%rbx,%rcx,8), %xmm12, %xmm10 +// CHECK: encoding: [0xc5,0x1b,0x5d,0x54,0xcb,0xfc] + vminsd -4(%rbx,%rcx,8), %xmm12, %xmm10 + From gohman at apple.com Thu Jun 17 20:24:29 2010 From: gohman at apple.com (Dan Gohman) Date: Fri, 18 Jun 2010 01:24:29 -0000 Subject: [llvm-commits] [llvm] r106266 - in /llvm/trunk: lib/Target/X86/X86ISelDAGToDAG.cpp test/CodeGen/X86/2010-03-17-ISelBug.ll Message-ID: <20100618012429.F41E32A6C12C@llvm.org> Author: djg Date: Thu Jun 17 20:24:29 2010 New Revision: 106266 URL: http://llvm.org/viewvc/llvm-project?rev=106266&view=rev Log: Don't maintain a set of deleted nodes; instead, use a HandleSDNode to track a node over CSE events. This fixes PR7368. Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp llvm/trunk/test/CodeGen/X86/2010-03-17-ISelBug.ll Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=106266&r1=106265&r2=106266&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Thu Jun 17 20:24:29 2010 @@ -137,21 +137,6 @@ } namespace { - class X86ISelListener : public SelectionDAG::DAGUpdateListener { - SmallSet Deletes; - public: - explicit X86ISelListener() {} - virtual void NodeDeleted(SDNode *N, SDNode *E) { - Deletes.insert(N); - } - virtual void NodeUpdated(SDNode *N) { - // Ignore updates. - } - bool IsDeleted(SDNode *N) { - return Deletes.count(N); - } - }; - //===--------------------------------------------------------------------===// /// ISel - X86 specific code to select X86 machine instructions for /// SelectionDAG operations. @@ -199,7 +184,6 @@ bool MatchWrapper(SDValue N, X86ISelAddressMode &AM); bool MatchAddress(SDValue N, X86ISelAddressMode &AM); bool MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM, - X86ISelListener &DeadNodes, unsigned Depth); bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM); bool SelectAddr(SDNode *Op, SDValue N, SDValue &Base, @@ -664,8 +648,7 @@ /// returning true if it cannot be done. This just pattern matches for the /// addressing mode. bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM) { - X86ISelListener DeadNodes; - if (MatchAddressRecursively(N, AM, DeadNodes, 0)) + if (MatchAddressRecursively(N, AM, 0)) return true; // Post-processing: Convert lea(,%reg,2) to lea(%reg,%reg), which has @@ -713,7 +696,6 @@ } bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM, - X86ISelListener &DeadNodes, unsigned Depth) { bool is64Bit = Subtarget->is64Bit(); DebugLoc dl = N.getDebugLoc(); @@ -876,13 +858,13 @@ // other uses, since it avoids a two-address sub instruction, however // it costs an additional mov if the index register has other uses. + // Add an artificial use to this node so that we can keep track of + // it if it gets CSE'd with a different node. + HandleSDNode Handle(N); + // Test if the LHS of the sub can be folded. X86ISelAddressMode Backup = AM; - if (MatchAddressRecursively(N.getNode()->getOperand(0), AM, - DeadNodes, Depth+1) || - // If it is successful but the recursive update causes N to be deleted, - // then it's not safe to continue. - DeadNodes.IsDeleted(N.getNode())) { + if (MatchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1)) { AM = Backup; break; } @@ -893,7 +875,7 @@ } int Cost = 0; - SDValue RHS = N.getNode()->getOperand(1); + SDValue RHS = Handle.getValue().getNode()->getOperand(1); // If the RHS involves a register with multiple uses, this // transformation incurs an extra mov, due to the neg instruction // clobbering its operand. @@ -944,35 +926,27 @@ } case ISD::ADD: { + // Add an artificial use to this node so that we can keep track of + // it if it gets CSE'd with a different node. + HandleSDNode Handle(N); + SDValue LHS = Handle.getValue().getNode()->getOperand(0); + SDValue RHS = Handle.getValue().getNode()->getOperand(1); + X86ISelAddressMode Backup = AM; - if (!MatchAddressRecursively(N.getNode()->getOperand(0), AM, - DeadNodes, Depth+1)) { - if (DeadNodes.IsDeleted(N.getNode())) - // If it is successful but the recursive update causes N to be deleted, - // then it's not safe to continue. - return true; - if (!MatchAddressRecursively(N.getNode()->getOperand(1), AM, - DeadNodes, Depth+1)) - // If it is successful but the recursive update causes N to be deleted, - // then it's not safe to continue. - return DeadNodes.IsDeleted(N.getNode()); - } + if (!MatchAddressRecursively(LHS, AM, Depth+1) && + !MatchAddressRecursively(RHS, AM, Depth+1)) + return false; + AM = Backup; + LHS = Handle.getValue().getNode()->getOperand(0); + RHS = Handle.getValue().getNode()->getOperand(1); // Try again after commuting the operands. + if (!MatchAddressRecursively(RHS, AM, Depth+1) && + !MatchAddressRecursively(LHS, AM, Depth+1)) + return false; AM = Backup; - if (!MatchAddressRecursively(N.getNode()->getOperand(1), AM, - DeadNodes, Depth+1)) { - if (DeadNodes.IsDeleted(N.getNode())) - // If it is successful but the recursive update causes N to be deleted, - // then it's not safe to continue. - return true; - if (!MatchAddressRecursively(N.getNode()->getOperand(0), AM, - DeadNodes, Depth+1)) - // If it is successful but the recursive update causes N to be deleted, - // then it's not safe to continue. - return DeadNodes.IsDeleted(N.getNode()); - } - AM = Backup; + LHS = Handle.getValue().getNode()->getOperand(0); + RHS = Handle.getValue().getNode()->getOperand(1); // If we couldn't fold both operands into the address at the same time, // see if we can just put each operand into a register and fold at least @@ -980,8 +954,8 @@ if (AM.BaseType == X86ISelAddressMode::RegBase && !AM.Base_Reg.getNode() && !AM.IndexReg.getNode()) { - AM.Base_Reg = N.getNode()->getOperand(0); - AM.IndexReg = N.getNode()->getOperand(1); + AM.Base_Reg = LHS; + AM.IndexReg = RHS; AM.Scale = 1; return false; } @@ -996,7 +970,7 @@ uint64_t Offset = CN->getSExtValue(); // Start with the LHS as an addr mode. - if (!MatchAddressRecursively(N.getOperand(0), AM, DeadNodes, Depth+1) && + if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) && // Address could not have picked a GV address for the displacement. AM.GV == NULL && // On x86-64, the resultant disp must fit in 32-bits. @@ -1073,7 +1047,7 @@ CurDAG->RepositionNode(N.getNode(), Shl.getNode()); Shl.getNode()->setNodeId(N.getNode()->getNodeId()); } - CurDAG->ReplaceAllUsesWith(N, Shl, &DeadNodes); + CurDAG->ReplaceAllUsesWith(N, Shl); AM.IndexReg = And; AM.Scale = (1 << ScaleLog); return false; @@ -1124,7 +1098,7 @@ NewSHIFT.getNode()->setNodeId(N.getNode()->getNodeId()); } - CurDAG->ReplaceAllUsesWith(N, NewSHIFT, &DeadNodes); + CurDAG->ReplaceAllUsesWith(N, NewSHIFT); AM.Scale = 1 << ShiftCst; AM.IndexReg = NewAND; Modified: llvm/trunk/test/CodeGen/X86/2010-03-17-ISelBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-03-17-ISelBug.ll?rev=106266&r1=106265&r2=106266&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2010-03-17-ISelBug.ll (original) +++ llvm/trunk/test/CodeGen/X86/2010-03-17-ISelBug.ll Thu Jun 17 20:24:29 2010 @@ -1,4 +1,5 @@ ; RUN: llc < %s -mtriple=i386-apple-darwin5 + ; rdar://7761790 %"struct..0$_485" = type { i16, i16, i32 } @@ -37,3 +38,30 @@ %4 = add nsw i32 %index.6379, 1 ; [#uses=1] br label %bb169 } + +; PR7368 + +%struct.bufBit_s = type { i8*, i8 } + +define fastcc void @printSwipe([2 x [256 x %struct.bufBit_s]]* nocapture %colourLines) nounwind { +entry: + br label %for.body190 + +for.body261.i: ; preds = %for.body261.i, %for.body190 + %line.3300.i = phi i32 [ undef, %for.body190 ], [ %add292.i, %for.body261.i ] ; [#uses=3] + %conv268.i = and i32 %line.3300.i, 255 ; [#uses=1] + %tmp278.i = getelementptr [2 x [256 x %struct.bufBit_s]]* %colourLines, i32 undef, i32 %pen.1100, i32 %conv268.i, i32 0 ; [#uses=1] + store i8* undef, i8** %tmp278.i + %tmp338 = shl i32 %line.3300.i, 3 ; [#uses=1] + %tmp339 = and i32 %tmp338, 2040 ; [#uses=1] + %tmp285.i = getelementptr i8* %scevgep328, i32 %tmp339 ; [#uses=1] + store i8 undef, i8* %tmp285.i + %add292.i = add nsw i32 0, %line.3300.i ; [#uses=1] + br i1 undef, label %for.body190, label %for.body261.i + +for.body190: ; preds = %for.body261.i, %for.body190, %bb.nph104 + %pen.1100 = phi i32 [ 0, %entry ], [ %inc230, %for.body261.i ], [ %inc230, %for.body190 ] ; [#uses=3] + %scevgep328 = getelementptr [2 x [256 x %struct.bufBit_s]]* %colourLines, i32 undef, i32 %pen.1100, i32 0, i32 1 ; [#uses=1] + %inc230 = add i32 %pen.1100, 1 ; [#uses=2] + br i1 undef, label %for.body190, label %for.body261.i +} From gohman at apple.com Thu Jun 17 20:35:11 2010 From: gohman at apple.com (Dan Gohman) Date: Fri, 18 Jun 2010 01:35:11 -0000 Subject: [llvm-commits] [llvm] r106267 - in /llvm/trunk: lib/Transforms/Scalar/IndVarSimplify.cpp test/Transforms/IndVarSimplify/indirectbr.ll Message-ID: <20100618013512.05D502A6C12C@llvm.org> Author: djg Date: Thu Jun 17 20:35:11 2010 New Revision: 106267 URL: http://llvm.org/viewvc/llvm-project?rev=106267&view=rev Log: Disable indvars on loops when LoopSimplify form is not available. This fixes PR7333. Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp llvm/trunk/test/Transforms/IndVarSimplify/indirectbr.ll Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=106267&r1=106266&r2=106267&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Thu Jun 17 20:35:11 2010 @@ -467,6 +467,17 @@ } bool IndVarSimplify::runOnLoop(Loop *L, LPPassManager &LPM) { + // If LoopSimplify form is not available, stay out of trouble. Some notes: + // - LSR currently only supports LoopSimplify-form loops. Indvars' + // canonicalization can be a pessimization without LSR to "clean up" + // afterwards. + // - We depend on having a preheader; in particular, + // Loop::getCanonicalInductionVariable only supports loops with preheaders, + // and we're in trouble if we can't find the induction variable even when + // we've manually inserted one. + if (!L->isLoopSimplifyForm()) + return false; + IU = &getAnalysis(); LI = &getAnalysis(); SE = &getAnalysis(); Modified: llvm/trunk/test/Transforms/IndVarSimplify/indirectbr.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/indirectbr.ll?rev=106267&r1=106266&r2=106267&view=diff ============================================================================== --- llvm/trunk/test/Transforms/IndVarSimplify/indirectbr.ll (original) +++ llvm/trunk/test/Transforms/IndVarSimplify/indirectbr.ll Thu Jun 17 20:35:11 2010 @@ -1,6 +1,6 @@ ; RUN: opt < %s -indvars -S -disable-output -; PR5758 +; PR5758 define zeroext i1 @foo() nounwind { entry: indirectbr i8* undef, [label %"202", label %"133"] @@ -20,3 +20,20 @@ "202": ; preds = %entry ret i1 false } + +; PR7333 +define void @__atomvec_module__put_vrml_bonds() nounwind { +bb7.preheader: ; preds = %entry + indirectbr i8* undef, [label %bb14, label %bb16] + +bb14: ; preds = %bb14, %bb7.preheader + br label %bb16 + +bb16: ; preds = %bb16, %bb14, %bb7.preheader + %S.31.0 = phi i64 [ %3, %bb16 ], [ 1, %bb7.preheader ], [ 1, %bb14 ] ; [#uses=2] + %0 = add nsw i64 %S.31.0, -1 ; [#uses=1] + %1 = getelementptr inbounds [3 x double]* undef, i64 0, i64 %0 ; [#uses=1] + %2 = load double* %1, align 8 ; [#uses=0] + %3 = add nsw i64 %S.31.0, 1 ; [#uses=1] + br label %bb16 +} From gohman at apple.com Thu Jun 17 20:49:17 2010 From: gohman at apple.com (Dan Gohman) Date: Fri, 18 Jun 2010 01:49:17 -0000 Subject: [llvm-commits] [llvm] r106269 - /llvm/trunk/test/Other/2010-05-06-Printer.ll Message-ID: <20100618014917.6E6AB2A6C12C@llvm.org> Author: djg Date: Thu Jun 17 20:49:17 2010 New Revision: 106269 URL: http://llvm.org/viewvc/llvm-project?rev=106269&view=rev Log: Don't write a file named "&1". Modified: llvm/trunk/test/Other/2010-05-06-Printer.ll Modified: llvm/trunk/test/Other/2010-05-06-Printer.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Other/2010-05-06-Printer.ll?rev=106269&r1=106268&r2=106269&view=diff ============================================================================== --- llvm/trunk/test/Other/2010-05-06-Printer.ll (original) +++ llvm/trunk/test/Other/2010-05-06-Printer.ll Thu Jun 17 20:49:17 2010 @@ -1,4 +1,4 @@ -; RUN: llc -O2 -print-after-all < %s 2>&1 +; RUN: llc -O2 -print-after-all < %s 2>/dev/null define void @tester(){ ret void From gohman at apple.com Thu Jun 17 20:55:50 2010 From: gohman at apple.com (Dan Gohman) Date: Fri, 18 Jun 2010 01:55:50 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r106270 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Message-ID: <20100618015550.C94A62A6C12C@llvm.org> Author: djg Date: Thu Jun 17 20:55:50 2010 New Revision: 106270 URL: http://llvm.org/viewvc/llvm-project?rev=106270&view=rev Log: Unbreak debug builds. Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=106270&r1=106269&r2=106270&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Thu Jun 17 20:55:50 2010 @@ -833,7 +833,7 @@ // basic block. But an empty block must have one outgoing edge, // and there might be some location info there; grab it. if (!stmt && EmitDebugInfo()) { - assert(EDGE_COUNT(b->succs) == 1 && "empty basic block with multiple successors?") ; + assert(EDGE_COUNT(bb->succs) == 1 && "empty basic block with multiple successors?") ; e = EDGE_I(bb->succs, 0); source_locus locus = e->goto_locus; if (locus) { From gohman at apple.com Thu Jun 17 21:01:10 2010 From: gohman at apple.com (Dan Gohman) Date: Fri, 18 Jun 2010 02:01:10 -0000 Subject: [llvm-commits] [llvm] r106271 - /llvm/trunk/lib/ExecutionEngine/Interpreter/Execution.cpp Message-ID: <20100618020110.D6F342A6C12C@llvm.org> Author: djg Date: Thu Jun 17 21:01:10 2010 New Revision: 106271 URL: http://llvm.org/viewvc/llvm-project?rev=106271&view=rev Log: Handle execution entrypoints with non-integer return types. Fix from Russel Power in PR7284. Modified: llvm/trunk/lib/ExecutionEngine/Interpreter/Execution.cpp Modified: llvm/trunk/lib/ExecutionEngine/Interpreter/Execution.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/Interpreter/Execution.cpp?rev=106271&r1=106270&r2=106271&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/Interpreter/Execution.cpp (original) +++ llvm/trunk/lib/ExecutionEngine/Interpreter/Execution.cpp Thu Jun 17 21:01:10 2010 @@ -591,7 +591,7 @@ ECStack.pop_back(); if (ECStack.empty()) { // Finished main. Put result into exit code... - if (RetTy && RetTy->isIntegerTy()) { // Nonvoid return type? + if (RetTy && !RetTy->isVoidTy()) { // Nonvoid return type? ExitValue = Result; // Capture the exit value of the program } else { memset(&ExitValue.Untyped, 0, sizeof(ExitValue.Untyped)); From espindola at google.com Thu Jun 17 21:15:16 2010 From: espindola at google.com (Rafael Espindola) Date: Thu, 17 Jun 2010 22:15:16 -0400 Subject: [llvm-commits] [patch] Update llvm-gcc to produce "" for the default calling convention on ARM In-Reply-To: References: <76A0798C-9AB8-43E8-99C1-7AFE618CEBEB@apple.com> Message-ID: > See ARMISelLowering.cpp:247. I have a more precise patch for this area > I haven't submitted yet, but the essence is the same. > > Also, ARM (CodeSourcery) introduced the syntax > __attribute__((pcs("aapcs"))) into GCC to allow mixed declarations of > different CCs. I haven't yet patched llvm-gcc or Clang with this > syntax, but I wanted to be prepared to do so when we saw a use for it. > (I have no idea why ARM wanted this syntax since they just slipped it > in with other changes.) I see. The problem are the bits of LLVM before the ARM backend. They don't know that "" is the same as some other calling convention. Yet, we want to be able to have passes that create call to new functions. Without making the basic LLVM passes aware of CC equivalences, I think what we can do is *) Declare that any pass introducing a new call to an external function must assume the "' calling convention. A consequence of this is that for AAPCS_VFP most functions would have the arm_aapcs_vfpcc calling convention, but libcalls would have "". *) Declare that any pass introducing a new call should do so with the same calling convention as the call being replaced. *) Add the CC to use to some target data The problem with the first and third options are that it assumes that all functions we could possible with to add calls to have the same CC. The second option is more flexible in that we would be able to add calls to functions with different CCs, but it assumes that we will always be replacing an existing call. Which option do you guys think is best? I still think we can implement all that we need with the first one. Lets see on a target with AAPCS_VFP calling convention *) Library functions take "" as the calling convention *) All normal functions take arm_aapcs_vfpcc *) If given an attribute CC that is not aapcs, set the calling convention accordingly. If it is aapcs, use "" AAPCS and APCS stay as they are. Do you think this would work? Am I missing something? > deep > Cheers, -- Rafael ?vila de Esp?ndola From echristo at apple.com Thu Jun 17 21:41:20 2010 From: echristo at apple.com (Eric Christopher) Date: Fri, 18 Jun 2010 02:41:20 -0000 Subject: [llvm-commits] [llvm] r106273 - /llvm/trunk/lib/Target/X86/X86Instr64bit.td Message-ID: <20100618024120.243952A6C12C@llvm.org> Author: echristo Date: Thu Jun 17 21:41:19 2010 New Revision: 106273 URL: http://llvm.org/viewvc/llvm-project?rev=106273&view=rev Log: Some assorted isTwoAddress -> Constraints cleanup. Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=106273&r1=106272&r2=106273&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original) +++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Thu Jun 17 21:41:19 2010 @@ -293,7 +293,7 @@ "lea{q}\t{$src|$dst}, {$dst|$src}", [(set GR64:$dst, lea64addr:$src)]>; -let isTwoAddress = 1 in +let Constraints = "$src = $dst" in def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src), "bswap{q}\t$dst", [(set GR64:$dst, (bswap GR64:$src))]>, TB; @@ -521,7 +521,7 @@ def ADD64i32 : RIi32<0x05, RawFrm, (outs), (ins i64i32imm:$src), "add{q}\t{$src, %rax|%rax, $src}", []>; -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { let isConvertibleToThreeAddress = 1 in { let isCommutable = 1 in // Register-Register Addition @@ -559,7 +559,7 @@ [(set GR64:$dst, EFLAGS, (X86add_flag GR64:$src1, (load addr:$src2)))]>; -} // isTwoAddress +} // Constraints = "$src1 = $dst" // Memory-Register Addition def ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), @@ -580,7 +580,7 @@ def ADC64i32 : RIi32<0x15, RawFrm, (outs), (ins i64i32imm:$src), "adc{q}\t{$src, %rax|%rax, $src}", []>; -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { let isCommutable = 1 in def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), @@ -606,7 +606,7 @@ (ins GR64:$src1, i64i32imm:$src2), "adc{q}\t{$src2, $dst|$dst, $src2}", [(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2))]>; -} // isTwoAddress +} // Constraints = "$src1 = $dst" def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), "adc{q}\t{$src2, $dst|$dst, $src2}", @@ -621,7 +621,7 @@ addr:$dst)]>; } // Uses = [EFLAGS] -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { // Register-Register Subtraction def SUB64rr : RI<0x29, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), @@ -653,7 +653,7 @@ "sub{q}\t{$src2, $dst|$dst, $src2}", [(set GR64:$dst, EFLAGS, (X86sub_flag GR64:$src1, i64immSExt32:$src2))]>; -} // isTwoAddress +} // Constraints = "$src1 = $dst" def SUB64i32 : RIi32<0x2D, RawFrm, (outs), (ins i64i32imm:$src), "sub{q}\t{$src, %rax|%rax, $src}", []>; @@ -677,7 +677,7 @@ (implicit EFLAGS)]>; let Uses = [EFLAGS] in { -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), "sbb{q}\t{$src2, $dst|$dst, $src2}", @@ -702,7 +702,7 @@ (ins GR64:$src1, i64i32imm:$src2), "sbb{q}\t{$src2, $dst|$dst, $src2}", [(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>; -} // isTwoAddress +} // Constraints = "$src1 = $dst" def SBB64i32 : RIi32<0x1D, RawFrm, (outs), (ins i64i32imm:$src), "sbb{q}\t{$src, %rax|%rax, $src}", []>; @@ -736,7 +736,7 @@ } let Defs = [EFLAGS] in { -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { let isCommutable = 1 in // Register-Register Signed Integer Multiplication def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst), @@ -751,7 +751,7 @@ "imul{q}\t{$src2, $dst|$dst, $src2}", [(set GR64:$dst, EFLAGS, (X86smul_flag GR64:$src1, (load addr:$src2)))]>, TB; -} // isTwoAddress +} // Constraints = "$src1 = $dst" // Suprisingly enough, these are not two address instructions! @@ -803,7 +803,7 @@ // Unary instructions let Defs = [EFLAGS], CodeSize = 2 in { -let isTwoAddress = 1 in +let Constraints = "$src = $dst" in def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src), "neg{q}\t$dst", [(set GR64:$dst, (ineg GR64:$src)), (implicit EFLAGS)]>; @@ -811,14 +811,14 @@ [(store (ineg (loadi64 addr:$dst)), addr:$dst), (implicit EFLAGS)]>; -let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in +let Constraints = "$src = $dst", isConvertibleToThreeAddress = 1 in def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src), "inc{q}\t$dst", [(set GR64:$dst, EFLAGS, (X86inc_flag GR64:$src))]>; def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst", [(store (add (loadi64 addr:$dst), 1), addr:$dst), (implicit EFLAGS)]>; -let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in +let Constraints = "$src = $dst", isConvertibleToThreeAddress = 1 in def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src), "dec{q}\t$dst", [(set GR64:$dst, EFLAGS, (X86dec_flag GR64:$src))]>; def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst", @@ -826,7 +826,7 @@ (implicit EFLAGS)]>; // In 64-bit mode, single byte INC and DEC cannot be encoded. -let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in { +let Constraints = "$src = $dst", isConvertibleToThreeAddress = 1 in { // Can transform into LEA. def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst", @@ -844,38 +844,36 @@ "dec{l}\t$dst", [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src))]>, Requires<[In64BitMode]>; -} // isConvertibleToThreeAddress +} // Constraints = "$src = $dst", isConvertibleToThreeAddress // These are duplicates of their 32-bit counterparts. Only needed so X86 knows // how to unfold them. -let isTwoAddress = 0, CodeSize = 2 in { - def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst", - [(store (add (loadi16 addr:$dst), 1), addr:$dst), - (implicit EFLAGS)]>, - OpSize, Requires<[In64BitMode]>; - def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst", - [(store (add (loadi32 addr:$dst), 1), addr:$dst), - (implicit EFLAGS)]>, - Requires<[In64BitMode]>; - def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst", - [(store (add (loadi16 addr:$dst), -1), addr:$dst), - (implicit EFLAGS)]>, - OpSize, Requires<[In64BitMode]>; - def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst", - [(store (add (loadi32 addr:$dst), -1), addr:$dst), - (implicit EFLAGS)]>, - Requires<[In64BitMode]>; -} +def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst", + [(store (add (loadi16 addr:$dst), 1), addr:$dst), + (implicit EFLAGS)]>, + OpSize, Requires<[In64BitMode]>; +def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst", + [(store (add (loadi32 addr:$dst), 1), addr:$dst), + (implicit EFLAGS)]>, + Requires<[In64BitMode]>; +def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst", + [(store (add (loadi16 addr:$dst), -1), addr:$dst), + (implicit EFLAGS)]>, + OpSize, Requires<[In64BitMode]>; +def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst", + [(store (add (loadi32 addr:$dst), -1), addr:$dst), + (implicit EFLAGS)]>, + Requires<[In64BitMode]>; } // Defs = [EFLAGS], CodeSize let Defs = [EFLAGS] in { // Shift instructions -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { let Uses = [CL] in -def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src), +def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1), "shl{q}\t{%cl, $dst|$dst, %CL}", - [(set GR64:$dst, (shl GR64:$src, CL))]>; + [(set GR64:$dst, (shl GR64:$src1, CL))]>; let isConvertibleToThreeAddress = 1 in // Can transform into LEA. def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2), @@ -885,7 +883,7 @@ // 'add reg,reg' is cheaper. def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1), "shl{q}\t$dst", []>; -} // isTwoAddress +} // Constraints = "$src1 = $dst" let Uses = [CL] in def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst), @@ -898,18 +896,18 @@ "shl{q}\t$dst", [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>; -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { let Uses = [CL] in -def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src), +def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src1), "shr{q}\t{%cl, $dst|$dst, %CL}", - [(set GR64:$dst, (srl GR64:$src, CL))]>; + [(set GR64:$dst, (srl GR64:$src1, CL))]>; def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2), "shr{q}\t{$src2, $dst|$dst, $src2}", [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>; def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1), "shr{q}\t$dst", [(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>; -} // isTwoAddress +} // Constraints = "$src1 = $dst" let Uses = [CL] in def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst), @@ -922,11 +920,11 @@ "shr{q}\t$dst", [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>; -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { let Uses = [CL] in -def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src), +def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src1), "sar{q}\t{%cl, $dst|$dst, %CL}", - [(set GR64:$dst, (sra GR64:$src, CL))]>; + [(set GR64:$dst, (sra GR64:$src1, CL))]>; def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2), "sar{q}\t{$src2, $dst|$dst, $src2}", @@ -934,7 +932,7 @@ def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1), "sar{q}\t$dst", [(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>; -} // isTwoAddress +} // Constraints = "$src = $dst" let Uses = [CL] in def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst), @@ -949,7 +947,7 @@ // Rotate instructions -let isTwoAddress = 1 in { +let Constraints = "$src = $dst" in { def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src), "rcl{q}\t{1, $dst|$dst, 1}", []>; def RCL64ri : RIi8<0xC1, MRM2r, (outs GR64:$dst), (ins GR64:$src, i8imm:$cnt), @@ -966,9 +964,8 @@ def RCR64rCL : RI<0xD3, MRM3r, (outs GR64:$dst), (ins GR64:$src), "rcr{q}\t{%cl, $dst|$dst, CL}", []>; } -} +} // Constraints = "$src = $dst" -let isTwoAddress = 0 in { def RCL64m1 : RI<0xD1, MRM2m, (outs), (ins i64mem:$dst), "rcl{q}\t{1, $dst|$dst, 1}", []>; def RCL64mi : RIi8<0xC1, MRM2m, (outs), (ins i64mem:$dst, i8imm:$cnt), @@ -984,13 +981,12 @@ def RCR64mCL : RI<0xD3, MRM3m, (outs), (ins i64mem:$dst), "rcr{q}\t{%cl, $dst|$dst, CL}", []>; } -} -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { let Uses = [CL] in -def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src), +def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src1), "rol{q}\t{%cl, $dst|$dst, %CL}", - [(set GR64:$dst, (rotl GR64:$src, CL))]>; + [(set GR64:$dst, (rotl GR64:$src1, CL))]>; def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2), "rol{q}\t{$src2, $dst|$dst, $src2}", @@ -998,7 +994,7 @@ def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1), "rol{q}\t$dst", [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>; -} // isTwoAddress +} // Constraints = "$src1 = $dst" let Uses = [CL] in def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst), @@ -1011,11 +1007,11 @@ "rol{q}\t$dst", [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>; -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { let Uses = [CL] in -def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src), +def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src1), "ror{q}\t{%cl, $dst|$dst, %CL}", - [(set GR64:$dst, (rotr GR64:$src, CL))]>; + [(set GR64:$dst, (rotr GR64:$src1, CL))]>; def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2), "ror{q}\t{$src2, $dst|$dst, $src2}", @@ -1023,7 +1019,7 @@ def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1), "ror{q}\t$dst", [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>; -} // isTwoAddress +} // Constraints = "$src1 = $dst" let Uses = [CL] in def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst), @@ -1037,7 +1033,7 @@ [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)]>; // Double shift instructions (generalizations of rotate) -let isTwoAddress = 1 in { +let Constraints = "$src1 = $dst" in { let Uses = [CL] in { def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), @@ -1067,7 +1063,7 @@ (i8 imm:$src3)))]>, TB; } // isCommutable -} // isTwoAddress +} // Constraints = "$src1 = $dst" let Uses = [CL] in { def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), From baldrick at free.fr Fri Jun 18 00:55:14 2010 From: baldrick at free.fr (Duncan Sands) Date: Fri, 18 Jun 2010 07:55:14 +0200 Subject: [llvm-commits] [llvm-gcc-4.2] r106244 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp In-Reply-To: <20100617224358.507712A6C12D@llvm.org> References: <20100617224358.507712A6C12D@llvm.org> Message-ID: <4C1B0A42.8010802@free.fr> Hi Stuart, > Add a stop point to empty basic blocks. Radar 7421831. please add a testcase. I don't think you provided any testcases yet for your changes improving debug info generation in llvm-gcc, please correct me if I'm wrong. Ciao, Duncan. From baldrick at free.fr Fri Jun 18 01:07:13 2010 From: baldrick at free.fr (Duncan Sands) Date: Fri, 18 Jun 2010 08:07:13 +0200 Subject: [llvm-commits] [llvm] r106267 - in /llvm/trunk: lib/Transforms/Scalar/IndVarSimplify.cpp test/Transforms/IndVarSimplify/indirectbr.ll In-Reply-To: <20100618013512.05D502A6C12C@llvm.org> References: <20100618013512.05D502A6C12C@llvm.org> Message-ID: <4C1B0D11.7060401@free.fr> Hi Dan, thanks for fixing this. > Disable indvars on loops when LoopSimplify form is not available. > This fixes PR7333. This raises the question of why the loop wasn't in loop-simplify form. The original infinite loop occurred when running the standard set of optimization passes, so shouldn't all loops be in loop-simplify form by the time they hit indvars? Ciao, Duncan. From eli.friedman at gmail.com Fri Jun 18 01:09:48 2010 From: eli.friedman at gmail.com (Eli Friedman) Date: Thu, 17 Jun 2010 23:09:48 -0700 Subject: [llvm-commits] [llvm] r106267 - in /llvm/trunk: lib/Transforms/Scalar/IndVarSimplify.cpp test/Transforms/IndVarSimplify/indirectbr.ll In-Reply-To: <4C1B0D11.7060401@free.fr> References: <20100618013512.05D502A6C12C@llvm.org> <4C1B0D11.7060401@free.fr> Message-ID: On Thu, Jun 17, 2010 at 11:07 PM, Duncan Sands wrote: > Hi Dan, thanks for fixing this. > >> Disable indvars on loops when LoopSimplify form is not available. >> This fixes PR7333. > > This raises the question of why the loop wasn't in loop-simplify form. > The original infinite loop occurred when running the standard set of > optimization passes, so shouldn't all loops be in loop-simplify form > by the time they hit indvars? indirectbr leads to unsplittable edges. -Eli From baldrick at free.fr Fri Jun 18 01:21:39 2010 From: baldrick at free.fr (Duncan Sands) Date: Fri, 18 Jun 2010 08:21:39 +0200 Subject: [llvm-commits] [llvm] r106267 - in /llvm/trunk: lib/Transforms/Scalar/IndVarSimplify.cpp test/Transforms/IndVarSimplify/indirectbr.ll In-Reply-To: References: <20100618013512.05D502A6C12C@llvm.org> <4C1B0D11.7060401@free.fr> Message-ID: <4C1B1073.6040203@free.fr> >> This raises the question of why the loop wasn't in loop-simplify form. >> The original infinite loop occurred when running the standard set of >> optimization passes, so shouldn't all loops be in loop-simplify form >> by the time they hit indvars? > > indirectbr leads to unsplittable edges. Of course, silly of me to have missed that. Thanks for pointing it out! Ciao, Duncan. From gohman at apple.com Fri Jun 18 09:01:07 2010 From: gohman at apple.com (Dan Gohman) Date: Fri, 18 Jun 2010 14:01:07 -0000 Subject: [llvm-commits] [llvm] r106278 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAGNodes.h lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/Target/X86/X86ISelLowering.cpp Message-ID: <20100618140107.69DE82A6C12C@llvm.org> Author: djg Date: Fri Jun 18 09:01:07 2010 New Revision: 106278 URL: http://llvm.org/viewvc/llvm-project?rev=106278&view=rev Log: isValueValidForType can be a static member function. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=106278&r1=106277&r2=106278&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Fri Jun 18 09:01:07 2010 @@ -1130,7 +1130,7 @@ } bool isExactlyValue(const APFloat& V) const; - bool isValueValidForType(EVT VT, const APFloat& Val); + static bool isValueValidForType(EVT VT, const APFloat& Val); static bool classof(const ConstantFPSDNode *) { return true; } static bool classof(const SDNode *N) { Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=106278&r1=106277&r2=106278&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Jun 18 09:01:07 2010 @@ -357,7 +357,7 @@ EVT SVT = VT; while (SVT != MVT::f32) { SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1); - if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) && + if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) && // Only do this if the target has a native EXTLOAD instruction from // smaller type. TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) && Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=106278&r1=106277&r2=106278&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Jun 18 09:01:07 2010 @@ -10252,8 +10252,8 @@ // 32-bit signed value if (ConstantSDNode *C = dyn_cast(Op)) { const ConstantInt *CI = C->getConstantIntValue(); - if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()), - C->getSExtValue())) { + if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), + C->getSExtValue())) { // Widen to 64 bits here to get it sign extended. Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64); break; @@ -10267,8 +10267,8 @@ // 32-bit unsigned value if (ConstantSDNode *C = dyn_cast(Op)) { const ConstantInt *CI = C->getConstantIntValue(); - if (CI->isValueValidForType(Type::getInt32Ty(*DAG.getContext()), - C->getZExtValue())) { + if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), + C->getZExtValue())) { Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); break; } From espindola at google.com Fri Jun 18 09:21:08 2010 From: espindola at google.com (Rafael Espindola) Date: Fri, 18 Jun 2010 10:21:08 -0400 Subject: [llvm-commits] [gold][patch] Add a pass-through option to the plugin Message-ID: The attached patch adds a pass-through option to the plugin. The use for this option is to ask the linker to take another look into some library or object. The case when one might want to do this is when codegen introduces a new undefined reference. The canonical example is libgcc. Cheers, -- Rafael ?vila de Esp?ndola -------------- next part -------------- A non-text attachment was scrubbed... Name: pass-through.patch Type: text/x-patch Size: 2424 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100618/21457598/attachment.bin From gohman at apple.com Fri Jun 18 09:22:04 2010 From: gohman at apple.com (Dan Gohman) Date: Fri, 18 Jun 2010 14:22:04 -0000 Subject: [llvm-commits] [llvm] r106279 - in /llvm/trunk: include/llvm/ include/llvm/CodeGen/ lib/Analysis/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ lib/Target/ARM/ lib/Target/CellSPU/ lib/Target/PIC16/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/X86/ Message-ID: <20100618142204.E682F2A6C12C@llvm.org> Author: djg Date: Fri Jun 18 09:22:04 2010 New Revision: 106279 URL: http://llvm.org/viewvc/llvm-project?rev=106279&view=rev Log: Eliminate unnecessary uses of getZExtValue(). Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h llvm/trunk/include/llvm/IntrinsicInst.h llvm/trunk/lib/Analysis/ConstantFolding.cpp llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp llvm/trunk/lib/Target/X86/X86FastISel.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=106279&r1=106278&r2=106279&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Fri Jun 18 09:22:04 2010 @@ -1082,6 +1082,7 @@ uint64_t getZExtValue() const { return Value->getZExtValue(); } int64_t getSExtValue() const { return Value->getSExtValue(); } + bool isOne() const { return Value->isOne(); } bool isNullValue() const { return Value->isNullValue(); } bool isAllOnesValue() const { return Value->isAllOnesValue(); } Modified: llvm/trunk/include/llvm/IntrinsicInst.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicInst.h?rev=106279&r1=106278&r2=106279&view=diff ============================================================================== --- llvm/trunk/include/llvm/IntrinsicInst.h (original) +++ llvm/trunk/include/llvm/IntrinsicInst.h Fri Jun 18 09:22:04 2010 @@ -136,7 +136,7 @@ return cast(const_cast(getOperand(5))); } bool isVolatile() const { - return getVolatileCst()->getZExtValue() != 0; + return !getVolatileCst()->isZero(); } /// getDest - This is just like getRawDest, but it strips off any cast Modified: llvm/trunk/lib/Analysis/ConstantFolding.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ConstantFolding.cpp?rev=106279&r1=106278&r2=106279&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ConstantFolding.cpp (original) +++ llvm/trunk/lib/Analysis/ConstantFolding.cpp Fri Jun 18 09:22:04 2010 @@ -208,7 +208,7 @@ i != e; ++i, ++GTI) { ConstantInt *CI = dyn_cast(*i); if (!CI) return false; // Index isn't a simple constant? - if (CI->getZExtValue() == 0) continue; // Not adding anything. + if (CI->isZero()) continue; // Not adding anything. if (const StructType *ST = dyn_cast(*GTI)) { // N = N + Offset Modified: llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp?rev=106279&r1=106278&r2=106279&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp (original) +++ llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp Fri Jun 18 09:22:04 2010 @@ -210,7 +210,7 @@ if (Val + 4 == NumOps) { if (ConstantInt *FinalVal = dyn_cast(II->getOperand(NumOps - 1))) - return (FinalVal->getZExtValue() == 0); + return FinalVal->isZero(); } } } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=106279&r1=106278&r2=106279&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Fri Jun 18 09:22:04 2010 @@ -345,7 +345,7 @@ // If this is a constant subscript, handle it quickly. if (const ConstantInt *CI = dyn_cast(Idx)) { - if (CI->getZExtValue() == 0) continue; + if (CI->isZero()) continue; uint64_t Offs = TD.getTypeAllocSize(Ty)*cast(CI)->getSExtValue(); N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, Offs, VT); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=106279&r1=106278&r2=106279&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Fri Jun 18 09:22:04 2010 @@ -2734,7 +2734,7 @@ // If this is a constant subscript, handle it quickly. if (const ConstantInt *CI = dyn_cast(Idx)) { - if (CI->getZExtValue() == 0) continue; + if (CI->isZero()) continue; uint64_t Offs = TD->getTypeAllocSize(Ty)*cast(CI)->getSExtValue(); SDValue OffsVal; @@ -4367,7 +4367,7 @@ SDValue Arg = getValue(I.getOperand(0)); EVT Ty = Arg.getValueType(); - if (CI->getZExtValue() == 0) + if (CI->isZero()) Res = DAG.getConstant(-1ULL, Ty); else Res = DAG.getConstant(0, Ty); Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=106279&r1=106278&r2=106279&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Fri Jun 18 09:22:04 2010 @@ -536,7 +536,7 @@ DebugLoc dl = Op->getDebugLoc(); if (N.getOpcode() != ISD::ADD) { ConstantSDNode *NC = dyn_cast(N); - if (!NC || NC->getZExtValue() != 0) + if (!NC || !NC->isNullValue()) return false; Base = Offset = N; Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=106279&r1=106278&r2=106279&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Fri Jun 18 09:22:04 2010 @@ -2867,7 +2867,7 @@ case SPUISD::IndirectAddr: { if (!ST->usingLargeMem() && Op0.getOpcode() == SPUISD::AFormAddr) { ConstantSDNode *CN = dyn_cast(N->getOperand(1)); - if (CN != 0 && CN->getZExtValue() == 0) { + if (CN != 0 && CN->isNullValue()) { // (SPUindirect (SPUaform , 0), 0) -> // (SPUaform , 0) Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=106279&r1=106278&r2=106279&view=diff ============================================================================== --- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Fri Jun 18 09:22:04 2010 @@ -1791,14 +1791,14 @@ static void LookThroughSetCC(SDValue &LHS, SDValue &RHS, ISD::CondCode CC, unsigned &SPCC) { if (isa(RHS) && - cast(RHS)->getZExtValue() == 0 && + cast(RHS)->isNullValue() && CC == ISD::SETNE && (LHS.getOpcode() == PIC16ISD::SELECT_ICC && LHS.getOperand(3).getOpcode() == PIC16ISD::SUBCC) && isa(LHS.getOperand(0)) && isa(LHS.getOperand(1)) && - cast(LHS.getOperand(0))->getZExtValue() == 1 && - cast(LHS.getOperand(1))->getZExtValue() == 0) { + cast(LHS.getOperand(0))->isOne() && + cast(LHS.getOperand(1))->isNullValue()) { SDValue CMPCC = LHS.getOperand(3); SPCC = cast(LHS.getOperand(2))->getZExtValue(); LHS = CMPCC.getOperand(0); Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=106279&r1=106278&r2=106279&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Fri Jun 18 09:22:04 2010 @@ -5042,19 +5042,19 @@ default: break; case PPCISD::SHL: if (ConstantSDNode *C = dyn_cast(N->getOperand(0))) { - if (C->getZExtValue() == 0) // 0 << V -> 0. + if (C->isNullValue()) // 0 << V -> 0. return N->getOperand(0); } break; case PPCISD::SRL: if (ConstantSDNode *C = dyn_cast(N->getOperand(0))) { - if (C->getZExtValue() == 0) // 0 >>u V -> 0. + if (C->isNullValue()) // 0 >>u V -> 0. return N->getOperand(0); } break; case PPCISD::SRA: if (ConstantSDNode *C = dyn_cast(N->getOperand(0))) { - if (C->getZExtValue() == 0 || // 0 >>s V -> 0. + if (C->isNullValue() || // 0 >>s V -> 0. C->isAllOnesValue()) // -1 >>s V -> -1. return N->getOperand(0); } Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=106279&r1=106278&r2=106279&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Fri Jun 18 09:22:04 2010 @@ -737,7 +737,7 @@ static void LookThroughSetCC(SDValue &LHS, SDValue &RHS, ISD::CondCode CC, unsigned &SPCC) { if (isa(RHS) && - cast(RHS)->getZExtValue() == 0 && + cast(RHS)->isNullValue() && CC == ISD::SETNE && ((LHS.getOpcode() == SPISD::SELECT_ICC && LHS.getOperand(3).getOpcode() == SPISD::CMPICC) || @@ -745,8 +745,8 @@ LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) && isa(LHS.getOperand(0)) && isa(LHS.getOperand(1)) && - cast(LHS.getOperand(0))->getZExtValue() == 1 && - cast(LHS.getOperand(1))->getZExtValue() == 0) { + cast(LHS.getOperand(0))->isOne() && + cast(LHS.getOperand(1))->isNullValue()) { SDValue CMPCC = LHS.getOperand(3); SPCC = cast(LHS.getOperand(2))->getZExtValue(); LHS = CMPCC.getOperand(0); Modified: llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp?rev=106279&r1=106278&r2=106279&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp (original) +++ llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp Fri Jun 18 09:22:04 2010 @@ -101,7 +101,7 @@ ConstantInt *Null = dyn_cast(CVA->getOperand(ATy->getNumElements()-1)); - if (Null == 0 || Null->getZExtValue() != 0) + if (Null == 0 || !Null->isZero()) return false; // Not null terminated. // Verify that the null doesn't occur anywhere else in the string. Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=106279&r1=106278&r2=106279&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Fri Jun 18 09:22:04 2010 @@ -1210,7 +1210,7 @@ unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); BuildMI(MBB, DL, TII.get(OpC), ResultReg). - addImm(CI->getZExtValue() == 0 ? -1ULL : 0); + addImm(CI->isZero() ? -1ULL : 0); UpdateValueMap(&I, ResultReg); return true; } Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=106279&r1=106278&r2=106279&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Jun 18 09:22:04 2010 @@ -3185,7 +3185,7 @@ /// constant +0.0. bool X86::isZeroNode(SDValue Elt) { return ((isa(Elt) && - cast(Elt)->getZExtValue() == 0) || + cast(Elt)->isNullValue()) || (isa(Elt) && cast(Elt)->getValueAPF().isPosZero())); } @@ -6229,7 +6229,7 @@ if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() && Op1.getOpcode() == ISD::Constant && - cast(Op1)->getZExtValue() == 0 && + cast(Op1)->isNullValue() && (CC == ISD::SETEQ || CC == ISD::SETNE)) { SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG); if (NewSetCC.getNode()) From gohman at apple.com Fri Jun 18 09:32:32 2010 From: gohman at apple.com (Dan Gohman) Date: Fri, 18 Jun 2010 14:32:32 -0000 Subject: [llvm-commits] [llvm] r106280 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20100618143232.86DD72A6C12C@llvm.org> Author: djg Date: Fri Jun 18 09:32:32 2010 New Revision: 106280 URL: http://llvm.org/viewvc/llvm-project?rev=106280&view=rev Log: Delete unused variables. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=106280&r1=106279&r2=106280&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Jun 18 09:32:32 2010 @@ -10251,7 +10251,6 @@ case 'e': { // 32-bit signed value if (ConstantSDNode *C = dyn_cast(Op)) { - const ConstantInt *CI = C->getConstantIntValue(); if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), C->getSExtValue())) { // Widen to 64 bits here to get it sign extended. @@ -10266,7 +10265,6 @@ case 'Z': { // 32-bit unsigned value if (ConstantSDNode *C = dyn_cast(Op)) { - const ConstantInt *CI = C->getConstantIntValue(); if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), C->getZExtValue())) { Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); From gohman at apple.com Fri Jun 18 09:33:51 2010 From: gohman at apple.com (Dan Gohman) Date: Fri, 18 Jun 2010 14:33:51 -0000 Subject: [llvm-commits] [llvm] r106281 - in /llvm/trunk: include/llvm/Analysis/ScalarEvolution.h lib/Analysis/ScalarEvolution.cpp Message-ID: <20100618143351.184582A6C12C@llvm.org> Author: djg Date: Fri Jun 18 09:33:50 2010 New Revision: 106281 URL: http://llvm.org/viewvc/llvm-project?rev=106281&view=rev Log: Remove getIntegerSCEV; it's redundant with getConstant, and getConstant is more consistent with the ConstantInt API. Modified: llvm/trunk/include/llvm/Analysis/ScalarEvolution.h llvm/trunk/lib/Analysis/ScalarEvolution.cpp Modified: llvm/trunk/include/llvm/Analysis/ScalarEvolution.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/ScalarEvolution.h?rev=106281&r1=106280&r2=106281&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/ScalarEvolution.h (original) +++ llvm/trunk/include/llvm/Analysis/ScalarEvolution.h Fri Jun 18 09:33:50 2010 @@ -530,10 +530,6 @@ /// widening. const SCEV *getTruncateOrNoop(const SCEV *V, const Type *Ty); - /// getIntegerSCEV - Given a SCEVable type, create a constant for the - /// specified signed integer value and return a SCEV for the constant. - const SCEV *getIntegerSCEV(int64_t Val, const Type *Ty); - /// getUMaxFromMismatchedTypes - Promote the operands to the wider of /// the types using zero-extension, and then perform a umax operation /// with them. Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=106281&r1=106280&r2=106281&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Fri Jun 18 09:33:50 2010 @@ -2394,13 +2394,6 @@ return S; } -/// getIntegerSCEV - Given a SCEVable type, create a constant for the -/// specified signed integer value and return a SCEV for the constant. -const SCEV *ScalarEvolution::getIntegerSCEV(int64_t Val, const Type *Ty) { - const IntegerType *ITy = cast(getEffectiveSCEVType(Ty)); - return getConstant(ConstantInt::get(ITy, Val)); -} - /// getNegativeSCEV - Return a SCEV corresponding to -V = -1*V /// const SCEV *ScalarEvolution::getNegativeSCEV(const SCEV *V) { From criswell at cs.uiuc.edu Fri Jun 18 10:17:11 2010 From: criswell at cs.uiuc.edu (John Criswell) Date: Fri, 18 Jun 2010 10:17:11 -0500 Subject: [llvm-commits] CVS: llvm-www/safecode/menagerie/memsafety.html Message-ID: <201006181517.o5IFHBq3032610@maute.cs.uiuc.edu> Changes in directory llvm-www/safecode/menagerie: memsafety.html updated: 1.4 -> 1.5 --- Log message: Fixed spelling mistake noticed by Gabor. --- Diffs of the changes: (+1 -1) memsafety.html | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Index: llvm-www/safecode/menagerie/memsafety.html diff -u llvm-www/safecode/menagerie/memsafety.html:1.4 llvm-www/safecode/menagerie/memsafety.html:1.5 --- llvm-www/safecode/menagerie/memsafety.html:1.4 Thu Jun 17 09:15:41 2010 +++ llvm-www/safecode/menagerie/memsafety.html Fri Jun 18 10:16:41 2010 @@ -238,7 +238,7 @@
    Sumant Kowshik, Dinakar Dhurjati, Vikram Adve.
    - Internaltional Conference on Compilers, Architecture and Synthesis for + International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), October 2002. From criswell at cs.uiuc.edu Fri Jun 18 10:17:11 2010 From: criswell at cs.uiuc.edu (John Criswell) Date: Fri, 18 Jun 2010 10:17:11 -0500 Subject: [llvm-commits] CVS: llvm-www/safecode/pubs.html Message-ID: <201006181517.o5IFHB4K032611@maute.cs.uiuc.edu> Changes in directory llvm-www/safecode: pubs.html updated: 1.9 -> 1.10 --- Log message: Fixed spelling mistake noticed by Gabor. --- Diffs of the changes: (+1 -1) pubs.html | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Index: llvm-www/safecode/pubs.html diff -u llvm-www/safecode/pubs.html:1.9 llvm-www/safecode/pubs.html:1.10 --- llvm-www/safecode/pubs.html:1.9 Mon May 17 14:42:39 2010 +++ llvm-www/safecode/pubs.html Fri Jun 18 10:16:38 2010 @@ -193,7 +193,7 @@
    Sumant Kowshik, Dinakar Dhurjati, Vikram Adve.
    - Internaltional Conference on Compilers, Architecture and Synthesis for + International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), October 2002. From gohman at apple.com Fri Jun 18 10:30:29 2010 From: gohman at apple.com (Dan Gohman) Date: Fri, 18 Jun 2010 15:30:29 -0000 Subject: [llvm-commits] [llvm] r106282 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAG.h lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp lib/CodeGen/SelectionDAG/LegalizeTypes.cpp lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp lib/Target/X86/X86ISelDAGToDAG.cpp lib/Target/X86/X86ISelLowering.cpp Message-ID: <20100618153029.EE3482A6C12C@llvm.org> Author: djg Date: Fri Jun 18 10:30:29 2010 New Revision: 106282 URL: http://llvm.org/viewvc/llvm-project?rev=106282&view=rev Log: Change UpdateNodeOperands' operand and return value from SDValue to SDNode *, since it doesn't care about the ResNo value. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/trunk/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=106282&r1=106281&r2=106282&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Fri Jun 18 10:30:29 2010 @@ -678,15 +678,15 @@ /// already exists. If the resultant node does not exist in the DAG, the /// input node is returned. As a degenerate case, if you specify the same /// input operands as the node already has, the input node is returned. - SDValue UpdateNodeOperands(SDValue N, SDValue Op); - SDValue UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2); - SDValue UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, + SDNode *UpdateNodeOperands(SDNode *N, SDValue Op); + SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2); + SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3); - SDValue UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, + SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3, SDValue Op4); - SDValue UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, + SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3, SDValue Op4, SDValue Op5); - SDValue UpdateNodeOperands(SDValue N, + SDNode *UpdateNodeOperands(SDNode *N, const SDValue *Ops, unsigned NumOps); /// SelectNodeTo - These are used for target selectors to *mutate* the Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=106282&r1=106281&r2=106282&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Jun 18 10:30:29 2010 @@ -927,8 +927,8 @@ break; } - Result = DAG.UpdateNodeOperands(Result.getValue(0), Ops.data(), - Ops.size()); + Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), Ops.data(), + Ops.size()), 0); switch (Action) { case TargetLowering::Legal: for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) @@ -1018,7 +1018,8 @@ if (Tmp1 != Node->getOperand(0)) { SmallVector Ops(Node->op_begin(), Node->op_end()); Ops[0] = Tmp1; - Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); + Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), &Ops[0], Ops.size()), + Result.getResNo()); } // Remember that the CALLSEQ_START is legalized. @@ -1060,7 +1061,9 @@ if (Tmp1 != Node->getOperand(0)) { SmallVector Ops(Node->op_begin(), Node->op_end()); Ops[0] = Tmp1; - Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); + Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), + &Ops[0], Ops.size()), + Result.getResNo()); } } else { Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); @@ -1069,7 +1072,9 @@ SmallVector Ops(Node->op_begin(), Node->op_end()); Ops[0] = Tmp1; Ops.back() = Tmp2; - Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); + Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), + &Ops[0], Ops.size()), + Result.getResNo()); } } assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); @@ -1089,7 +1094,9 @@ ISD::LoadExtType ExtType = LD->getExtensionType(); if (ExtType == ISD::NON_EXTLOAD) { EVT VT = Node->getValueType(0); - Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); + Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), + Tmp1, Tmp2, LD->getOffset()), + Result.getResNo()); Tmp3 = Result.getValue(0); Tmp4 = Result.getValue(1); @@ -1269,7 +1276,9 @@ isCustom = true; // FALLTHROUGH case TargetLowering::Legal: - Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); + Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), + Tmp1, Tmp2, LD->getOffset()), + Result.getResNo()); Tmp1 = Result.getValue(0); Tmp2 = Result.getValue(1); @@ -1357,8 +1366,10 @@ { Tmp3 = LegalizeOp(ST->getValue()); - Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, - ST->getOffset()); + Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), + Tmp1, Tmp3, Tmp2, + ST->getOffset()), + Result.getResNo()); EVT VT = Tmp3.getValueType(); switch (TLI.getOperationAction(ISD::STORE, VT)) { @@ -1461,8 +1472,10 @@ } else { if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || Tmp2 != ST->getBasePtr()) - Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, - ST->getOffset()); + Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), + Tmp1, Tmp3, Tmp2, + ST->getOffset()), + Result.getResNo()); switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { default: assert(0 && "This action is not supported yet!"); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp?rev=106282&r1=106281&r2=106282&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp Fri Jun 18 10:30:29 2010 @@ -698,9 +698,10 @@ } // Update N to have the operands specified. - return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), + return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), DAG.getCondCode(CCCode), NewLHS, NewRHS, - N->getOperand(4)); + N->getOperand(4)), + 0); } SDValue DAGTypeLegalizer::SoftenFloatOp_FP_TO_SINT(SDNode *N) { @@ -739,9 +740,10 @@ } // Update N to have the operands specified. - return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS, + return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS, N->getOperand(2), N->getOperand(3), - DAG.getCondCode(CCCode)); + DAG.getCondCode(CCCode)), + 0); } SDValue DAGTypeLegalizer::SoftenFloatOp_SETCC(SDNode *N) { @@ -757,8 +759,9 @@ } // Otherwise, update N to have the operands specified. - return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS, - DAG.getCondCode(CCCode)); + return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS, + DAG.getCondCode(CCCode)), + 0); } SDValue DAGTypeLegalizer::SoftenFloatOp_STORE(SDNode *N, unsigned OpNo) { @@ -1294,9 +1297,9 @@ } // Update N to have the operands specified. - return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), + return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), DAG.getCondCode(CCCode), NewLHS, NewRHS, - N->getOperand(4)); + N->getOperand(4)), 0); } SDValue DAGTypeLegalizer::ExpandFloatOp_FP_ROUND(SDNode *N) { @@ -1375,9 +1378,9 @@ } // Update N to have the operands specified. - return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS, + return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS, N->getOperand(2), N->getOperand(3), - DAG.getCondCode(CCCode)); + DAG.getCondCode(CCCode)), 0); } SDValue DAGTypeLegalizer::ExpandFloatOp_SETCC(SDNode *N) { @@ -1393,8 +1396,8 @@ } // Otherwise, update N to have the operands specified. - return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS, - DAG.getCondCode(CCCode)); + return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS, + DAG.getCondCode(CCCode)), 0); } SDValue DAGTypeLegalizer::ExpandFloatOp_STORE(SDNode *N, unsigned OpNo) { Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=106282&r1=106281&r2=106282&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Fri Jun 18 10:30:29 2010 @@ -725,8 +725,9 @@ // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always // legal types. - return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), - N->getOperand(1), LHS, RHS, N->getOperand(4)); + return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), + N->getOperand(1), LHS, RHS, N->getOperand(4)), + 0); } SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) { @@ -737,8 +738,8 @@ SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT); // The chain (Op#0) and basic block destination (Op#2) are always legal types. - return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Cond, - N->getOperand(2)); + return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond, + N->getOperand(2)), 0); } SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) { @@ -773,7 +774,7 @@ for (unsigned i = 0; i < NumElts; ++i) NewOps.push_back(GetPromotedInteger(N->getOperand(i))); - return DAG.UpdateNodeOperands(SDValue(N, 0), &NewOps[0], NumElts); + return SDValue(DAG.UpdateNodeOperands(N, &NewOps[0], NumElts), 0); } SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) { @@ -798,17 +799,18 @@ assert(N->getOperand(1).getValueType().getSizeInBits() >= N->getValueType(0).getVectorElementType().getSizeInBits() && "Type of inserted value narrower than vector element type!"); - return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), + return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), GetPromotedInteger(N->getOperand(1)), - N->getOperand(2)); + N->getOperand(2)), + 0); } assert(OpNo == 2 && "Different operand and result vector types?"); // Promote the index. SDValue Idx = ZExtPromotedInteger(N->getOperand(2)); - return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), - N->getOperand(1), Idx); + return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), + N->getOperand(1), Idx), 0); } SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) { @@ -819,15 +821,14 @@ SDValue Flag = GetPromotedInteger(N->getOperand(i)); NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1); } - return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps, - array_lengthof(NewOps)); + return SDValue(DAG.UpdateNodeOperands(N, NewOps, array_lengthof(NewOps)), 0); } SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) { // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote // the operand in place. - return DAG.UpdateNodeOperands(SDValue(N, 0), - GetPromotedInteger(N->getOperand(0))); + return SDValue(DAG.UpdateNodeOperands(N, + GetPromotedInteger(N->getOperand(0))), 0); } SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) { @@ -837,8 +838,8 @@ EVT SVT = TLI.getSetCCResultType(N->getOperand(1).getValueType()); SDValue Cond = PromoteTargetBoolean(N->getOperand(0), SVT); - return DAG.UpdateNodeOperands(SDValue(N, 0), Cond, - N->getOperand(1), N->getOperand(2)); + return SDValue(DAG.UpdateNodeOperands(N, Cond, + N->getOperand(1), N->getOperand(2)), 0); } SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) { @@ -849,8 +850,8 @@ PromoteSetCCOperands(LHS, RHS, cast(N->getOperand(4))->get()); // The CC (#4) and the possible return values (#2 and #3) have legal types. - return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2), - N->getOperand(3), N->getOperand(4)); + return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2), + N->getOperand(3), N->getOperand(4)), 0); } SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) { @@ -861,12 +862,12 @@ PromoteSetCCOperands(LHS, RHS, cast(N->getOperand(2))->get()); // The CC (#2) is always legal. - return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2)); + return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0); } SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) { - return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), - ZExtPromotedInteger(N->getOperand(1))); + return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), + ZExtPromotedInteger(N->getOperand(1))), 0); } SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) { @@ -878,8 +879,8 @@ } SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) { - return DAG.UpdateNodeOperands(SDValue(N, 0), - SExtPromotedInteger(N->getOperand(0))); + return SDValue(DAG.UpdateNodeOperands(N, + SExtPromotedInteger(N->getOperand(0))), 0); } SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){ @@ -905,8 +906,8 @@ } SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) { - return DAG.UpdateNodeOperands(SDValue(N, 0), - ZExtPromotedInteger(N->getOperand(0))); + return SDValue(DAG.UpdateNodeOperands(N, + ZExtPromotedInteger(N->getOperand(0))), 0); } SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) { @@ -2224,9 +2225,9 @@ } // Update N to have the operands specified. - return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), + return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), DAG.getCondCode(CCCode), NewLHS, NewRHS, - N->getOperand(4)); + N->getOperand(4)), 0); } SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) { @@ -2242,9 +2243,9 @@ } // Update N to have the operands specified. - return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS, + return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS, N->getOperand(2), N->getOperand(3), - DAG.getCondCode(CCCode)); + DAG.getCondCode(CCCode)), 0); } SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) { @@ -2260,8 +2261,8 @@ } // Otherwise, update N to have the operands specified. - return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS, - DAG.getCondCode(CCCode)); + return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS, + DAG.getCondCode(CCCode)), 0); } SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) { @@ -2270,7 +2271,7 @@ // upper half of the shift amount is zero. Just use the lower half. SDValue Lo, Hi; GetExpandedInteger(N->getOperand(1), Lo, Hi); - return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Lo); + return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0); } SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) { @@ -2279,7 +2280,7 @@ // constant to valid type. SDValue Lo, Hi; GetExpandedInteger(N->getOperand(0), Lo, Hi); - return DAG.UpdateNodeOperands(SDValue(N, 0), Lo); + return SDValue(DAG.UpdateNodeOperands(N, Lo), 0); } SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) { Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp?rev=106282&r1=106281&r2=106282&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Fri Jun 18 10:30:29 2010 @@ -492,8 +492,7 @@ // Some operands changed - update the node. if (!NewOps.empty()) { - SDNode *M = DAG.UpdateNodeOperands(SDValue(N, 0), &NewOps[0], - NewOps.size()).getNode(); + SDNode *M = DAG.UpdateNodeOperands(N, &NewOps[0], NewOps.size()); if (M != N) { // The node morphed into a different node. Normally for this to happen // the original node would have to be marked NewNode. However this can Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp?rev=106282&r1=106281&r2=106282&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp Fri Jun 18 10:30:29 2010 @@ -116,7 +116,7 @@ Ops.push_back(LegalizeOp(Node->getOperand(i))); SDValue Result = - DAG.UpdateNodeOperands(Op.getValue(0), Ops.data(), Ops.size()); + SDValue(DAG.UpdateNodeOperands(Op.getNode(), Ops.data(), Ops.size()), 0); bool HasVectorValue = false; for (SDNode::value_iterator J = Node->value_begin(), E = Node->value_end(); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=106282&r1=106281&r2=106282&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Fri Jun 18 10:30:29 2010 @@ -1087,10 +1087,11 @@ uint64_t LoElts = Lo.getValueType().getVectorNumElements(); if (IdxVal < LoElts) - return DAG.UpdateNodeOperands(SDValue(N, 0), Lo, Idx); - return DAG.UpdateNodeOperands(SDValue(N, 0), Hi, + return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0); + return SDValue(DAG.UpdateNodeOperands(N, Hi, DAG.getConstant(IdxVal - LoElts, - Idx.getValueType())); + Idx.getValueType())), + 0); } // Store the vector to the stack. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=106282&r1=106281&r2=106282&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Fri Jun 18 10:30:29 2010 @@ -4439,17 +4439,16 @@ /// already exists. If the resultant node does not exist in the DAG, the /// input node is returned. As a degenerate case, if you specify the same /// input operands as the node already has, the input node is returned. -SDValue SelectionDAG::UpdateNodeOperands(SDValue InN, SDValue Op) { - SDNode *N = InN.getNode(); +SDNode *SelectionDAG::UpdateNodeOperands(SDNode *N, SDValue Op) { assert(N->getNumOperands() == 1 && "Update with wrong number of operands"); // Check to see if there is no change. - if (Op == N->getOperand(0)) return InN; + if (Op == N->getOperand(0)) return N; // See if the modified node already exists. void *InsertPos = 0; if (SDNode *Existing = FindModifiedNodeSlot(N, Op, InsertPos)) - return SDValue(Existing, InN.getResNo()); + return Existing; // Nope it doesn't. Remove the node from its current place in the maps. if (InsertPos) @@ -4461,22 +4460,20 @@ // If this gets put into a CSE map, add it. if (InsertPos) CSEMap.InsertNode(N, InsertPos); - return InN; + return N; } -SDValue SelectionDAG:: -UpdateNodeOperands(SDValue InN, SDValue Op1, SDValue Op2) { - SDNode *N = InN.getNode(); +SDNode *SelectionDAG::UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2) { assert(N->getNumOperands() == 2 && "Update with wrong number of operands"); // Check to see if there is no change. if (Op1 == N->getOperand(0) && Op2 == N->getOperand(1)) - return InN; // No operands changed, just return the input node. + return N; // No operands changed, just return the input node. // See if the modified node already exists. void *InsertPos = 0; if (SDNode *Existing = FindModifiedNodeSlot(N, Op1, Op2, InsertPos)) - return SDValue(Existing, InN.getResNo()); + return Existing; // Nope it doesn't. Remove the node from its current place in the maps. if (InsertPos) @@ -4491,32 +4488,31 @@ // If this gets put into a CSE map, add it. if (InsertPos) CSEMap.InsertNode(N, InsertPos); - return InN; + return N; } -SDValue SelectionDAG:: -UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, SDValue Op3) { +SDNode *SelectionDAG:: +UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3) { SDValue Ops[] = { Op1, Op2, Op3 }; return UpdateNodeOperands(N, Ops, 3); } -SDValue SelectionDAG:: -UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, +SDNode *SelectionDAG:: +UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3, SDValue Op4) { SDValue Ops[] = { Op1, Op2, Op3, Op4 }; return UpdateNodeOperands(N, Ops, 4); } -SDValue SelectionDAG:: -UpdateNodeOperands(SDValue N, SDValue Op1, SDValue Op2, +SDNode *SelectionDAG:: +UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3, SDValue Op4, SDValue Op5) { SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; return UpdateNodeOperands(N, Ops, 5); } -SDValue SelectionDAG:: -UpdateNodeOperands(SDValue InN, const SDValue *Ops, unsigned NumOps) { - SDNode *N = InN.getNode(); +SDNode *SelectionDAG:: +UpdateNodeOperands(SDNode *N, const SDValue *Ops, unsigned NumOps) { assert(N->getNumOperands() == NumOps && "Update with wrong number of operands"); @@ -4530,12 +4526,12 @@ } // No operands changed, just return the input node. - if (!AnyChange) return InN; + if (!AnyChange) return N; // See if the modified node already exists. void *InsertPos = 0; if (SDNode *Existing = FindModifiedNodeSlot(N, Ops, NumOps, InsertPos)) - return SDValue(Existing, InN.getResNo()); + return Existing; // Nope it doesn't. Remove the node from its current place in the maps. if (InsertPos) @@ -4549,7 +4545,7 @@ // If this gets put into a CSE map, add it. if (InsertPos) CSEMap.InsertNode(N, InsertPos); - return InN; + return N; } /// DropOperands - Release the operands and set this node to have Modified: llvm/trunk/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp?rev=106282&r1=106281&r2=106282&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp Fri Jun 18 10:30:29 2010 @@ -132,8 +132,8 @@ SDValue Val) { SmallVector ops(N->op_begin(), N->op_end()); ops[Num] = Val; - SDValue New = DAG.UpdateNodeOperands(SDValue(N, 0), ops.data(), ops.size()); - DAG.ReplaceAllUsesWith(N, New.getNode()); + SDNode *New = DAG.UpdateNodeOperands(N, ops.data(), ops.size()); + DAG.ReplaceAllUsesWith(N, New); } // After instruction selection, insert COPY_TO_REGCLASS nodes to help in Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=106282&r1=106281&r2=106282&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Fri Jun 18 10:30:29 2010 @@ -370,14 +370,14 @@ } for (unsigned i = 1, e = OrigChain.getNumOperands(); i != e; ++i) Ops.push_back(OrigChain.getOperand(i)); - CurDAG->UpdateNodeOperands(OrigChain, &Ops[0], Ops.size()); - CurDAG->UpdateNodeOperands(Load, Call.getOperand(0), + CurDAG->UpdateNodeOperands(OrigChain.getNode(), &Ops[0], Ops.size()); + CurDAG->UpdateNodeOperands(Load.getNode(), Call.getOperand(0), Load.getOperand(1), Load.getOperand(2)); Ops.clear(); Ops.push_back(SDValue(Load.getNode(), 1)); for (unsigned i = 1, e = Call.getNode()->getNumOperands(); i != e; ++i) Ops.push_back(Call.getOperand(i)); - CurDAG->UpdateNodeOperands(Call, &Ops[0], Ops.size()); + CurDAG->UpdateNodeOperands(Call.getNode(), &Ops[0], Ops.size()); } /// isCalleeLoad - Return true if call address is a load and it can be Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=106282&r1=106281&r2=106282&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Jun 18 10:30:29 2010 @@ -6609,14 +6609,14 @@ (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); CCode = X86::GetOppositeBranchCondition(CCode); CC = DAG.getConstant(CCode, MVT::i8); - SDValue User = SDValue(*Op.getNode()->use_begin(), 0); + SDNode *User = *Op.getNode()->use_begin(); // Look for an unconditional branch following this conditional branch. // We need this because we need to reverse the successors in order // to implement FCMP_OEQ. - if (User.getOpcode() == ISD::BR) { - SDValue FalseBB = User.getOperand(1); - SDValue NewBR = - DAG.UpdateNodeOperands(User, User.getOperand(0), Dest); + if (User->getOpcode() == ISD::BR) { + SDValue FalseBB = User->getOperand(1); + SDNode *NewBR = + DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); assert(NewBR == User); Dest = FalseBB; @@ -9871,9 +9871,10 @@ switch (atomic.getOpcode()) { case ISD::ATOMIC_CMP_SWAP: - return DAG.UpdateNodeOperands(atomic, fence.getOperand(0), + return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), + fence.getOperand(0), atomic.getOperand(1), atomic.getOperand(2), - atomic.getOperand(3)); + atomic.getOperand(3)), atomic.getResNo()); case ISD::ATOMIC_SWAP: case ISD::ATOMIC_LOAD_ADD: case ISD::ATOMIC_LOAD_SUB: @@ -9885,8 +9886,10 @@ case ISD::ATOMIC_LOAD_MAX: case ISD::ATOMIC_LOAD_UMIN: case ISD::ATOMIC_LOAD_UMAX: - return DAG.UpdateNodeOperands(atomic, fence.getOperand(0), - atomic.getOperand(1), atomic.getOperand(2)); + return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), + fence.getOperand(0), + atomic.getOperand(1), atomic.getOperand(2)), + atomic.getResNo()); default: return SDValue(); } From gohman at apple.com Fri Jun 18 10:36:18 2010 From: gohman at apple.com (Dan Gohman) Date: Fri, 18 Jun 2010 15:36:18 -0000 Subject: [llvm-commits] [llvm] r106283 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Message-ID: <20100618153618.A0E8A2A6C12C@llvm.org> Author: djg Date: Fri Jun 18 10:36:18 2010 New Revision: 106283 URL: http://llvm.org/viewvc/llvm-project?rev=106283&view=rev Log: Don't call clear() on DbgInfo when it's going to be deleted anyway. Don't replace the old DbgInfo with a new one when clear() on the old one is sufficient. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=106283&r1=106282&r2=106283&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Fri Jun 18 10:36:18 2010 @@ -807,7 +807,6 @@ SelectionDAG::~SelectionDAG() { allnodes_clear(); delete Ordering; - DbgInfo->clear(); delete DbgInfo; } @@ -837,8 +836,6 @@ delete Ordering; Ordering = new SDNodeOrdering(); DbgInfo->clear(); - delete DbgInfo; - DbgInfo = new SDDbgInfo(); } SDValue SelectionDAG::getSExtOrTrunc(SDValue Op, DebugLoc DL, EVT VT) { From gohman at apple.com Fri Jun 18 10:40:59 2010 From: gohman at apple.com (Dan Gohman) Date: Fri, 18 Jun 2010 15:40:59 -0000 Subject: [llvm-commits] [llvm] r106284 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Message-ID: <20100618154059.2CE7C2A6C12C@llvm.org> Author: djg Date: Fri Jun 18 10:40:58 2010 New Revision: 106284 URL: http://llvm.org/viewvc/llvm-project?rev=106284&view=rev Log: Don't replace the old Ordering object with a new one; just clear() the old one. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=106284&r1=106283&r2=106284&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Fri Jun 18 10:40:58 2010 @@ -833,8 +833,7 @@ EntryNode.UseList = 0; AllNodes.push_back(&EntryNode); Root = getEntryNode(); - delete Ordering; - Ordering = new SDNodeOrdering(); + Ordering->clear(); DbgInfo->clear(); } From gohman at apple.com Fri Jun 18 10:56:31 2010 From: gohman at apple.com (Dan Gohman) Date: Fri, 18 Jun 2010 15:56:31 -0000 Subject: [llvm-commits] [llvm] r106285 - in /llvm/trunk: include/llvm/Support/Timer.h lib/CodeGen/AsmPrinter/AsmPrinter.cpp lib/CodeGen/AsmPrinter/DwarfDebug.cpp lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp lib/Support/Timer.cpp Message-ID: <20100618155631.C26992A6C12C@llvm.org> Author: djg Date: Fri Jun 18 10:56:31 2010 New Revision: 106285 URL: http://llvm.org/viewvc/llvm-project?rev=106285&view=rev Log: Give NamedRegionTimer an Enabled flag, allowing all its clients to switch from this: if (TimePassesIsEnabled) { NamedRegionTimer T(Name, GroupName); do_something(); } else { do_something(); // duplicate the code, this time without a timer! } to this: { NamedRegionTimer T(Name, GroupName, TimePassesIsEnabled); do_something(); } Modified: llvm/trunk/include/llvm/Support/Timer.h llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp llvm/trunk/lib/Support/Timer.cpp Modified: llvm/trunk/include/llvm/Support/Timer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/Timer.h?rev=106285&r1=106284&r2=106285&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/Timer.h (original) +++ llvm/trunk/include/llvm/Support/Timer.h Fri Jun 18 10:56:31 2010 @@ -150,8 +150,10 @@ /// is primarily used for debugging and for hunting performance problems. /// struct NamedRegionTimer : public TimeRegion { - explicit NamedRegionTimer(StringRef Name); - explicit NamedRegionTimer(StringRef Name, StringRef GroupName); + explicit NamedRegionTimer(StringRef Name, + bool Enabled = true); + explicit NamedRegionTimer(StringRef Name, StringRef GroupName, + bool Enabled = true); }; Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=106285&r1=106284&r2=106285&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Fri Jun 18 10:56:31 2010 @@ -427,20 +427,12 @@ // Emit pre-function debug and/or EH information. if (DE) { - if (TimePassesIsEnabled) { - NamedRegionTimer T(EHTimerName, DWARFGroupName); - DE->BeginFunction(MF); - } else { - DE->BeginFunction(MF); - } + NamedRegionTimer T(EHTimerName, DWARFGroupName, TimePassesIsEnabled); + DE->BeginFunction(MF); } if (DD) { - if (TimePassesIsEnabled) { - NamedRegionTimer T(DbgTimerName, DWARFGroupName); - DD->beginFunction(MF); - } else { - DD->beginFunction(MF); - } + NamedRegionTimer T(DbgTimerName, DWARFGroupName, TimePassesIsEnabled); + DD->beginFunction(MF); } } @@ -610,12 +602,8 @@ } if (ShouldPrintDebugScopes) { - if (TimePassesIsEnabled) { - NamedRegionTimer T(DbgTimerName, DWARFGroupName); - DD->beginScope(II); - } else { - DD->beginScope(II); - } + NamedRegionTimer T(DbgTimerName, DWARFGroupName, TimePassesIsEnabled); + DD->beginScope(II); } if (isVerbose()) @@ -648,12 +636,8 @@ } if (ShouldPrintDebugScopes) { - if (TimePassesIsEnabled) { - NamedRegionTimer T(DbgTimerName, DWARFGroupName); - DD->endScope(II); - } else { - DD->endScope(II); - } + NamedRegionTimer T(DbgTimerName, DWARFGroupName, TimePassesIsEnabled); + DD->endScope(II); } } } @@ -691,20 +675,12 @@ // Emit post-function debug information. if (DD) { - if (TimePassesIsEnabled) { - NamedRegionTimer T(DbgTimerName, DWARFGroupName); - DD->endFunction(MF); - } else { - DD->endFunction(MF); - } + NamedRegionTimer T(DbgTimerName, DWARFGroupName, TimePassesIsEnabled); + DD->endFunction(MF); } if (DE) { - if (TimePassesIsEnabled) { - NamedRegionTimer T(EHTimerName, DWARFGroupName); - DE->EndFunction(); - } else { - DE->EndFunction(); - } + NamedRegionTimer T(EHTimerName, DWARFGroupName, TimePassesIsEnabled); + DE->EndFunction(); } MMI->EndFunction(); @@ -729,19 +705,15 @@ // Finalize debug and EH information. if (DE) { - if (TimePassesIsEnabled) { - NamedRegionTimer T(EHTimerName, DWARFGroupName); - DE->EndModule(); - } else { + { + NamedRegionTimer T(EHTimerName, DWARFGroupName, TimePassesIsEnabled); DE->EndModule(); } delete DE; DE = 0; } if (DD) { - if (TimePassesIsEnabled) { - NamedRegionTimer T(DbgTimerName, DWARFGroupName); - DD->endModule(); - } else { + { + NamedRegionTimer T(DbgTimerName, DWARFGroupName, TimePassesIsEnabled); DD->endModule(); } delete DD; DD = 0; Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=106285&r1=106284&r2=106285&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Fri Jun 18 10:56:31 2010 @@ -322,11 +322,9 @@ DwarfStrSectionSym = TextSectionSym = 0; DwarfDebugRangeSectionSym = DwarfDebugLocSectionSym = 0; FunctionBeginSym = FunctionEndSym = 0; - if (TimePassesIsEnabled) { - NamedRegionTimer T(DbgTimerName, DWARFGroupName); - beginModule(M); - } else { - beginModule(M); + { + NamedRegionTimer T(DbgTimerName, DWARFGroupName, TimePassesIsEnabled); + beginModule(M); } } DwarfDebug::~DwarfDebug() { Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=106285&r1=106284&r2=106285&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Fri Jun 18 10:56:31 2010 @@ -443,10 +443,8 @@ if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); // Run the DAG combiner in pre-legalize mode. - if (TimePassesIsEnabled) { - NamedRegionTimer T("DAG Combining 1", GroupName); - CurDAG->Combine(Unrestricted, *AA, OptLevel); - } else { + { + NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled); CurDAG->Combine(Unrestricted, *AA, OptLevel); } @@ -459,10 +457,8 @@ BlockName); bool Changed; - if (TimePassesIsEnabled) { - NamedRegionTimer T("Type Legalization", GroupName); - Changed = CurDAG->LegalizeTypes(); - } else { + { + NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled); Changed = CurDAG->LegalizeTypes(); } @@ -474,10 +470,9 @@ CurDAG->viewGraph("dag-combine-lt input for " + BlockName); // Run the DAG combiner in post-type-legalize mode. - if (TimePassesIsEnabled) { - NamedRegionTimer T("DAG Combining after legalize types", GroupName); - CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); - } else { + { + NamedRegionTimer T("DAG Combining after legalize types", GroupName, + TimePassesIsEnabled); CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); } @@ -485,18 +480,14 @@ DEBUG(CurDAG->dump()); } - if (TimePassesIsEnabled) { - NamedRegionTimer T("Vector Legalization", GroupName); - Changed = CurDAG->LegalizeVectors(); - } else { + { + NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled); Changed = CurDAG->LegalizeVectors(); } if (Changed) { - if (TimePassesIsEnabled) { - NamedRegionTimer T("Type Legalization 2", GroupName); - CurDAG->LegalizeTypes(); - } else { + { + NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled); CurDAG->LegalizeTypes(); } @@ -504,10 +495,9 @@ CurDAG->viewGraph("dag-combine-lv input for " + BlockName); // Run the DAG combiner in post-type-legalize mode. - if (TimePassesIsEnabled) { - NamedRegionTimer T("DAG Combining after legalize vectors", GroupName); - CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); - } else { + { + NamedRegionTimer T("DAG Combining after legalize vectors", GroupName, + TimePassesIsEnabled); CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); } @@ -517,10 +507,8 @@ if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); - if (TimePassesIsEnabled) { - NamedRegionTimer T("DAG Legalization", GroupName); - CurDAG->Legalize(OptLevel); - } else { + { + NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled); CurDAG->Legalize(OptLevel); } @@ -530,10 +518,8 @@ if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); // Run the DAG combiner in post-legalize mode. - if (TimePassesIsEnabled) { - NamedRegionTimer T("DAG Combining 2", GroupName); - CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); - } else { + { + NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled); CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); } @@ -547,10 +533,8 @@ // Third, instruction select all of the operations to machine code, adding the // code to the MachineBasicBlock. - if (TimePassesIsEnabled) { - NamedRegionTimer T("Instruction Selection", GroupName); - DoInstructionSelection(); - } else { + { + NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled); DoInstructionSelection(); } @@ -561,10 +545,9 @@ // Schedule machine code. ScheduleDAGSDNodes *Scheduler = CreateScheduler(); - if (TimePassesIsEnabled) { - NamedRegionTimer T("Instruction Scheduling", GroupName); - Scheduler->Run(CurDAG, BB, BB->end()); - } else { + { + NamedRegionTimer T("Instruction Scheduling", GroupName, + TimePassesIsEnabled); Scheduler->Run(CurDAG, BB, BB->end()); } @@ -572,18 +555,15 @@ // Emit machine code to BB. This can change 'BB' to the last block being // inserted into. - if (TimePassesIsEnabled) { - NamedRegionTimer T("Instruction Creation", GroupName); - BB = Scheduler->EmitSchedule(); - } else { + { + NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled); BB = Scheduler->EmitSchedule(); } // Free the scheduler state. - if (TimePassesIsEnabled) { - NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName); - delete Scheduler; - } else { + { + NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName, + TimePassesIsEnabled); delete Scheduler; } Modified: llvm/trunk/lib/Support/Timer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Timer.cpp?rev=106285&r1=106284&r2=106285&view=diff ============================================================================== --- llvm/trunk/lib/Support/Timer.cpp (original) +++ llvm/trunk/lib/Support/Timer.cpp Fri Jun 18 10:56:31 2010 @@ -236,11 +236,13 @@ return T; } -NamedRegionTimer::NamedRegionTimer(StringRef Name) - : TimeRegion(getNamedRegionTimer(Name)) {} - -NamedRegionTimer::NamedRegionTimer(StringRef Name, StringRef GroupName) - : TimeRegion(NamedGroupedTimers->get(Name, GroupName)) {} +NamedRegionTimer::NamedRegionTimer(StringRef Name, + bool Enabled) + : TimeRegion(!Enabled ? 0 : &getNamedRegionTimer(Name)) {} + +NamedRegionTimer::NamedRegionTimer(StringRef Name, StringRef GroupName, + bool Enabled) + : TimeRegion(!Enabled ? 0 : &NamedGroupedTimers->get(Name, GroupName)) {} //===----------------------------------------------------------------------===// // TimerGroup Implementation From gohman at apple.com Fri Jun 18 11:00:29 2010 From: gohman at apple.com (Dan Gohman) Date: Fri, 18 Jun 2010 16:00:29 -0000 Subject: [llvm-commits] [llvm] r106286 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Message-ID: <20100618160029.D80812A6C12C@llvm.org> Author: djg Date: Fri Jun 18 11:00:29 2010 New Revision: 106286 URL: http://llvm.org/viewvc/llvm-project?rev=106286&view=rev Log: Minor code simplifications. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=106286&r1=106285&r2=106286&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Fri Jun 18 11:00:29 2010 @@ -437,8 +437,7 @@ BlockName = MF->getFunction()->getNameStr() + ":" + BB->getBasicBlock()->getNameStr(); - DEBUG(dbgs() << "Initial selection DAG:\n"); - DEBUG(CurDAG->dump()); + DEBUG(dbgs() << "Initial selection DAG:\n"; CurDAG->dump()); if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); @@ -448,8 +447,7 @@ CurDAG->Combine(Unrestricted, *AA, OptLevel); } - DEBUG(dbgs() << "Optimized lowered selection DAG:\n"); - DEBUG(CurDAG->dump()); + DEBUG(dbgs() << "Optimized lowered selection DAG:\n"; CurDAG->dump()); // Second step, hack on the DAG until it only uses operations and types that // the target supports. @@ -462,8 +460,7 @@ Changed = CurDAG->LegalizeTypes(); } - DEBUG(dbgs() << "Type-legalized selection DAG:\n"); - DEBUG(CurDAG->dump()); + DEBUG(dbgs() << "Type-legalized selection DAG:\n"; CurDAG->dump()); if (Changed) { if (ViewDAGCombineLT) @@ -476,8 +473,8 @@ CurDAG->Combine(NoIllegalTypes, *AA, OptLevel); } - DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n"); - DEBUG(CurDAG->dump()); + DEBUG(dbgs() << "Optimized type-legalized selection DAG:\n"; + CurDAG->dump()); } { @@ -501,8 +498,8 @@ CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); } - DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n"); - DEBUG(CurDAG->dump()); + DEBUG(dbgs() << "Optimized vector-legalized selection DAG:\n"; + CurDAG->dump()); } if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); @@ -512,8 +509,7 @@ CurDAG->Legalize(OptLevel); } - DEBUG(dbgs() << "Legalized selection DAG:\n"); - DEBUG(CurDAG->dump()); + DEBUG(dbgs() << "Legalized selection DAG:\n"; CurDAG->dump()); if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); @@ -523,8 +519,7 @@ CurDAG->Combine(NoIllegalOperations, *AA, OptLevel); } - DEBUG(dbgs() << "Optimized legalized selection DAG:\n"); - DEBUG(CurDAG->dump()); + DEBUG(dbgs() << "Optimized legalized selection DAG:\n"; CurDAG->dump()); if (OptLevel != CodeGenOpt::None) ComputeLiveOutVRegInfo(); @@ -538,8 +533,7 @@ DoInstructionSelection(); } - DEBUG(dbgs() << "Selected selection DAG:\n"); - DEBUG(CurDAG->dump()); + DEBUG(dbgs() << "Selected selection DAG:\n"; CurDAG->dump()); if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); @@ -784,8 +778,8 @@ SelectionDAGISel::FinishBasicBlock(MachineBasicBlock *BB) { DEBUG(dbgs() << "Total amount of phi nodes to update: " - << FuncInfo->PHINodesToUpdate.size() << "\n"); - DEBUG(for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) + << FuncInfo->PHINodesToUpdate.size() << "\n"; + for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) dbgs() << "Node " << i << " : (" << FuncInfo->PHINodesToUpdate[i].first << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n"); From criswell at cs.uiuc.edu Fri Jun 18 11:06:46 2010 From: criswell at cs.uiuc.edu (John Criswell) Date: Fri, 18 Jun 2010 11:06:46 -0500 Subject: [llvm-commits] CVS: llvm-www/safecode/menagerie/other.html Message-ID: <201006181606.o5IG6k9r002262@maute.cs.uiuc.edu> Changes in directory llvm-www/safecode/menagerie: other.html updated: 1.4 -> 1.5 --- Log message: Added the Archipelago and Dalton papers. Changed the name of the randomization header to more accurately reflect the paper contained thereunder (is that even a word?). --- Diffs of the changes: (+33 -1) other.html | 34 +++++++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) Index: llvm-www/safecode/menagerie/other.html diff -u llvm-www/safecode/menagerie/other.html:1.4 llvm-www/safecode/menagerie/other.html:1.5 --- llvm-www/safecode/menagerie/other.html:1.4 Thu Jun 17 09:46:21 2010 +++ llvm-www/safecode/menagerie/other.html Fri Jun 18 11:06:33 2010 @@ -75,8 +75,24 @@

    Information Flow Papers

    + + -

    Randomization Papers

    +

    Randomization and Probabilistic Safety Papers

    • @@ -109,6 +125,22 @@
      +
    • + + Archipelago: Trading Address Space for Reliability and Security + +
      + Vitaliy B. Lvin, Gene Novark, Emery D. Berger, and Benjamin G. Zorn +
      + Proceedings of the Thirteenth International Conference on + Architectural Support for Programming Languages and Operating + Systems (ASPLOS '08), + Seattle, WA, March 2008. +
      +
      • + +
      +
    • DieHard: Probabilistic Memory Safety for Unsafe Languages From gohman at apple.com Fri Jun 18 11:09:11 2010 From: gohman at apple.com (Dan Gohman) Date: Fri, 18 Jun 2010 16:09:11 -0000 Subject: [llvm-commits] [llvm] r106287 - in /llvm/trunk: include/llvm/Analysis/Dominators.h lib/CodeGen/MachineDominators.cpp Message-ID: <20100618160911.39CCE2A6C12C@llvm.org> Author: djg Date: Fri Jun 18 11:09:11 2010 New Revision: 106287 URL: http://llvm.org/viewvc/llvm-project?rev=106287&view=rev Log: Don't bother calling releaseMemory before destroying the DominatorTreeBase. Modified: llvm/trunk/include/llvm/Analysis/Dominators.h llvm/trunk/lib/CodeGen/MachineDominators.cpp Modified: llvm/trunk/include/llvm/Analysis/Dominators.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/Dominators.h?rev=106287&r1=106286&r2=106287&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/Dominators.h (original) +++ llvm/trunk/include/llvm/Analysis/Dominators.h Fri Jun 18 11:09:11 2010 @@ -704,7 +704,6 @@ } ~DominatorTree() { - DT->releaseMemory(); delete DT; } Modified: llvm/trunk/lib/CodeGen/MachineDominators.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineDominators.cpp?rev=106287&r1=106286&r2=106287&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineDominators.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineDominators.cpp Fri Jun 18 11:09:11 2010 @@ -46,7 +46,6 @@ } MachineDominatorTree::~MachineDominatorTree() { - DT->releaseMemory(); delete DT; } From criswell at cs.uiuc.edu Fri Jun 18 11:13:29 2010 From: criswell at cs.uiuc.edu (John Criswell) Date: Fri, 18 Jun 2010 11:13:29 -0500 Subject: [llvm-commits] CVS: llvm-www/safecode/menagerie/attacks.html Message-ID: <201006181613.o5IGDTEg002633@maute.cs.uiuc.edu> Changes in directory llvm-www/safecode/menagerie: attacks.html updated: 1.3 -> 1.4 --- Log message: Added the classic Alepha1 paper on stack smashing. Added the paper on the Return-oriented rootkit compiler. Re-ordered attack papers based on year of publication. --- Diffs of the changes: (+49 -5) attacks.html | 54 +++++++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 49 insertions(+), 5 deletions(-) Index: llvm-www/safecode/menagerie/attacks.html diff -u llvm-www/safecode/menagerie/attacks.html:1.3 llvm-www/safecode/menagerie/attacks.html:1.4 --- llvm-www/safecode/menagerie/attacks.html:1.3 Thu Jun 17 09:15:41 2010 +++ llvm-www/safecode/menagerie/attacks.html Fri Jun 18 11:13:17 2010 @@ -79,9 +79,36 @@

      Memory Safety Exploit Papers

      -
      • From criswell at cs.uiuc.edu Fri Jun 18 11:26:49 2010 From: criswell at cs.uiuc.edu (John Criswell) Date: Fri, 18 Jun 2010 11:26:49 -0500 Subject: [llvm-commits] CVS: llvm-www/safecode/menagerie/attacks.html Message-ID: <201006181626.o5IGQn7H003275@maute.cs.uiuc.edu> Changes in directory llvm-www/safecode/menagerie: attacks.html updated: 1.4 -> 1.5 --- Log message: Fixed spelling error. --- Diffs of the changes: (+1 -1) attacks.html | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Index: llvm-www/safecode/menagerie/attacks.html diff -u llvm-www/safecode/menagerie/attacks.html:1.4 llvm-www/safecode/menagerie/attacks.html:1.5 --- llvm-www/safecode/menagerie/attacks.html:1.4 Fri Jun 18 11:13:17 2010 +++ llvm-www/safecode/menagerie/attacks.html Fri Jun 18 11:26:36 2010 @@ -83,7 +83,7 @@
    • - Return-Oriented Rookits: Bypassing Kernel Code Integrity Protectin + Return-Oriented Rookits: Bypassing Kernel Code Integrity Protection Mechanisms
      Ralf Hund, Thorsten Holz, and Felix C. Freiling From stoklund at 2pi.dk Fri Jun 18 11:49:33 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Fri, 18 Jun 2010 16:49:33 -0000 Subject: [llvm-commits] [llvm] r106289 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/ARM/crash-O0.ll Message-ID: <20100618164933.EAFA92A6C12C@llvm.org> Author: stoklund Date: Fri Jun 18 11:49:33 2010 New Revision: 106289 URL: http://llvm.org/viewvc/llvm-project?rev=106289&view=rev Log: Treat the ARM inline asm {cc} constraint as a physreg (%CPSR), just like X86 does for {flags}. If we create virtual registers of the CCR class, RegAllocFast may try to spill them, and we can't do that. Added: llvm/trunk/test/CodeGen/ARM/crash-O0.ll Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=106289&r1=106288&r2=106289&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri Jun 18 11:49:33 2010 @@ -4945,7 +4945,7 @@ } } if (StringRef("{cc}").equals_lower(Constraint)) - return std::make_pair(0U, ARM::CCRRegisterClass); + return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass); return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); } Added: llvm/trunk/test/CodeGen/ARM/crash-O0.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/crash-O0.ll?rev=106289&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/crash-O0.ll (added) +++ llvm/trunk/test/CodeGen/ARM/crash-O0.ll Fri Jun 18 11:49:33 2010 @@ -0,0 +1,12 @@ +; RUN: llc < %s -O0 -relocation-model=pic -disable-fp-elim +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64-n32" +target triple = "armv6-apple-darwin10" + +%struct0 = type { i32, i32 } + +; This function would crash RegAllocFast because it tried to spill %CPSR. +define arm_apcscc void @clobber_cc() nounwind noinline ssp { +entry: + %asmtmp = call %struct0 asm sideeffect "...", "=&r,=&r,r,Ir,r,~{cc},~{memory}"(i32* undef, i32 undef, i32 1) nounwind ; <%0> [#uses=0] + unreachable +} From bob.wilson at apple.com Fri Jun 18 12:07:24 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Fri, 18 Jun 2010 17:07:24 -0000 Subject: [llvm-commits] [llvm] r106291 - /llvm/trunk/lib/CodeGen/IfConversion.cpp Message-ID: <20100618170724.1FCA12A6C12C@llvm.org> Author: bwilson Date: Fri Jun 18 12:07:23 2010 New Revision: 106291 URL: http://llvm.org/viewvc/llvm-project?rev=106291&view=rev Log: Fix PR7372: Conditional branches (at least on ARM) are treated as predicated, so when IfConverter::CopyAndPredicateBlock checks to see if it should ignore an instruction because it is a branch, it should not check if the branch is predicated. This case (when IgnoreBr is true) is only relevant from IfConvertTriangle, where new branches are inserted after the block has been copied and predicated. If the original branch is not removed, we end up with multiple conditional branches (possibly conflicting) at the end of the block. Aside from any immediate errors resulting from that, this confuses the AnalyzeBranch functions so that the branches are not analyzable. That in turn causes the IfConverter to think that the "Simple" pattern can be applied, and things go downhill fast because the "Simple" pattern does _not_ apply if the block can fall through. This is pretty fragile. If there are other degenerate cases where AnalyzeBranch fails, but where the block may still fall through, the IfConverter should not perform its "Simple" if-conversion. But, I don't know how to do that with the current AnalyzeBranch interface, so for now, the best thing seems to be to avoid creating branches that AnalyzeBranch cannot handle. Evan, please review! Modified: llvm/trunk/lib/CodeGen/IfConversion.cpp Modified: llvm/trunk/lib/CodeGen/IfConversion.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/IfConversion.cpp?rev=106291&r1=106290&r2=106291&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/IfConversion.cpp (original) +++ llvm/trunk/lib/CodeGen/IfConversion.cpp Fri Jun 18 12:07:23 2010 @@ -1298,16 +1298,15 @@ for (MachineBasicBlock::iterator I = FromBBI.BB->begin(), E = FromBBI.BB->end(); I != E; ++I) { const TargetInstrDesc &TID = I->getDesc(); - bool isPredicated = TII->isPredicated(I); // Do not copy the end of the block branches. - if (IgnoreBr && !isPredicated && TID.isBranch()) + if (IgnoreBr && TID.isBranch()) break; MachineInstr *MI = MF.CloneMachineInstr(I); ToBBI.BB->insert(ToBBI.BB->end(), MI); ToBBI.NonPredSize++; - if (!isPredicated && !MI->isDebugValue()) { + if (!TII->isPredicated(I) && !MI->isDebugValue()) { if (!TII->PredicateInstruction(MI, Cond)) { #ifndef NDEBUG dbgs() << "Unable to predicate " << *I << "!\n"; From grosbach at apple.com Fri Jun 18 12:40:42 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 18 Jun 2010 17:40:42 -0000 Subject: [llvm-commits] [llvm] r106292 - /llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h Message-ID: <20100618174042.537D52A6C12C@llvm.org> Author: grosbach Date: Fri Jun 18 12:40:42 2010 New Revision: 106292 URL: http://llvm.org/viewvc/llvm-project?rev=106292&view=rev Log: Grammar. Modified: llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h Modified: llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h?rev=106292&r1=106291&r2=106292&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h (original) +++ llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h Fri Jun 18 12:40:42 2010 @@ -130,7 +130,7 @@ /// This node represents a target intrinsic function with no side effects. /// The first operand is the ID number of the intrinsic from the /// llvm::Intrinsic namespace. The operands to the intrinsic follow. The - /// node has returns the result of the intrinsic. + /// node returns the result of the intrinsic. INTRINSIC_WO_CHAIN, /// RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) From dalej at apple.com Fri Jun 18 12:44:25 2010 From: dalej at apple.com (Dale Johannesen) Date: Fri, 18 Jun 2010 17:44:25 -0000 Subject: [llvm-commits] [test-suite] r106294 - /test-suite/trunk/External/SPEC/CINT2000/186.crafty/Makefile Message-ID: <20100618174425.39B572A6C12C@llvm.org> Author: johannes Date: Fri Jun 18 12:44:25 2010 New Revision: 106294 URL: http://llvm.org/viewvc/llvm-project?rev=106294&view=rev Log: Make crafty work with ARCH=THUMB. Modified: test-suite/trunk/External/SPEC/CINT2000/186.crafty/Makefile Modified: test-suite/trunk/External/SPEC/CINT2000/186.crafty/Makefile URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/External/SPEC/CINT2000/186.crafty/Makefile?rev=106294&r1=106293&r2=106294&view=diff ============================================================================== --- test-suite/trunk/External/SPEC/CINT2000/186.crafty/Makefile (original) +++ test-suite/trunk/External/SPEC/CINT2000/186.crafty/Makefile Fri Jun 18 12:44:25 2010 @@ -31,6 +31,9 @@ ifeq ($(ARCH),ARM) CPPFLAGS += -DHAS_LONGLONG endif +ifeq ($(ARCH),THUMB) + CPPFLAGS += -DHAS_LONGLONG +endif ifeq ($(TARGET_OS),Darwin) CPPFLAGS += -DUNIX -DLINUX endif From espindola at google.com Fri Jun 18 12:52:45 2010 From: espindola at google.com (Rafael Espindola) Date: Fri, 18 Jun 2010 13:52:45 -0400 Subject: [llvm-commits] [llvm] r106291 - /llvm/trunk/lib/CodeGen/IfConversion.cpp In-Reply-To: <20100618170724.1FCA12A6C12C@llvm.org> References: <20100618170724.1FCA12A6C12C@llvm.org> Message-ID: Thanks! Just in time for a bootstrap test on the beaglebord during the weekend :-) On 18 June 2010 13:07, Bob Wilson wrote: > Author: bwilson > Date: Fri Jun 18 12:07:23 2010 > New Revision: 106291 > > URL: http://llvm.org/viewvc/llvm-project?rev=106291&view=rev > Log: > Fix PR7372: Conditional branches (at least on ARM) are treated as predicated, > so when IfConverter::CopyAndPredicateBlock checks to see if it should ignore > an instruction because it is a branch, it should not check if the branch is > predicated. > > This case (when IgnoreBr is true) is only relevant from IfConvertTriangle, > where new branches are inserted after the block has been copied and predicated. > If the original branch is not removed, we end up with multiple conditional > branches (possibly conflicting) at the end of the block. ?Aside from any > immediate errors resulting from that, this confuses the AnalyzeBranch functions > so that the branches are not analyzable. ?That in turn causes the IfConverter to > think that the "Simple" pattern can be applied, and things go downhill fast > because the "Simple" pattern does _not_ apply if the block can fall through. > > This is pretty fragile. ?If there are other degenerate cases where AnalyzeBranch > fails, but where the block may still fall through, the IfConverter should not > perform its "Simple" if-conversion. ?But, I don't know how to do that with the > current AnalyzeBranch interface, so for now, the best thing seems to be to > avoid creating branches that AnalyzeBranch cannot handle. > > Evan, please review! > > Modified: > ? ?llvm/trunk/lib/CodeGen/IfConversion.cpp > > Modified: llvm/trunk/lib/CodeGen/IfConversion.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/IfConversion.cpp?rev=106291&r1=106290&r2=106291&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/IfConversion.cpp (original) > +++ llvm/trunk/lib/CodeGen/IfConversion.cpp Fri Jun 18 12:07:23 2010 > @@ -1298,16 +1298,15 @@ > ? for (MachineBasicBlock::iterator I = FromBBI.BB->begin(), > ? ? ? ? ?E = FromBBI.BB->end(); I != E; ++I) { > ? ? const TargetInstrDesc &TID = I->getDesc(); > - ? ?bool isPredicated = TII->isPredicated(I); > ? ? // Do not copy the end of the block branches. > - ? ?if (IgnoreBr && !isPredicated && TID.isBranch()) > + ? ?if (IgnoreBr && TID.isBranch()) > ? ? ? break; > > ? ? MachineInstr *MI = MF.CloneMachineInstr(I); > ? ? ToBBI.BB->insert(ToBBI.BB->end(), MI); > ? ? ToBBI.NonPredSize++; > > - ? ?if (!isPredicated && !MI->isDebugValue()) { > + ? ?if (!TII->isPredicated(I) && !MI->isDebugValue()) { > ? ? ? if (!TII->PredicateInstruction(MI, Cond)) { > ?#ifndef NDEBUG > ? ? ? ? dbgs() << "Unable to predicate " << *I << "!\n"; > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -- Rafael ?vila de Esp?ndola From dalej at apple.com Fri Jun 18 13:13:12 2010 From: dalej at apple.com (Dale Johannesen) Date: Fri, 18 Jun 2010 18:13:12 -0000 Subject: [llvm-commits] [llvm] r106295 - in /llvm/trunk/lib/Target/ARM: ARMISelLowering.cpp ARMInstrInfo.td Message-ID: <20100618181312.38F132A6C12C@llvm.org> Author: johannes Date: Fri Jun 18 13:13:11 2010 New Revision: 106295 URL: http://llvm.org/viewvc/llvm-project?rev=106295&view=rev Log: Last round of changes for ARM tail calls. Not turning them on yet. Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=106295&r1=106294&r2=106295&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri Jun 18 13:13:11 2010 @@ -1101,7 +1101,7 @@ } } else if (VA.isRegLoc()) { RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); - } else { + } else if (!IsSibCall) { assert(VA.isMemLoc()); MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, @@ -1357,12 +1357,6 @@ // Look for obvious safe cases to perform tail call optimization that do not // require ABI changes. This is what gcc calls sibcall. - // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to - // emit a special epilogue. - // Not sure yet if this is true on ARM. -//?? if (RegInfo->needsStackRealignment(MF)) -//?? return false; - // Do not sibcall optimize vararg calls unless the call site is not passing // any arguments. if (isVarArg && !Outs.empty()) @@ -1373,6 +1367,19 @@ if (isCalleeStructRet || isCallerStructRet) return false; + // On Thumb, for the moment, we can only do this to functions defined in this + // compilation, or to indirect calls. A Thumb B to an ARM function is not + // easily fixed up in the linker, unlike BL. + if (Subtarget->isThumb()) { + if (GlobalAddressSDNode *G = dyn_cast(Callee)) { + const GlobalValue *GV = G->getGlobal(); + if (GV->isDeclaration() || GV->isWeakForLinker()) + return false; + } else if (isa(Callee)) { + return false; + } + } + // If the calling conventions do not match, then we'd better make sure the // results are returned in the same way as what the caller expects. if (!CCMatch) { Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=106295&r1=106294&r2=106295&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Fri Jun 18 13:13:11 2010 @@ -1049,7 +1049,7 @@ "@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>; def TAILJMPd : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops), - IIC_Br, "b\t$dst @ TAILCALL", + IIC_Br, "b.w\t$dst @ TAILCALL", []>, Requires<[IsDarwin]>; def TAILJMPr : AXI<(outs), (ins tcGPR:$dst, variable_ops), @@ -1084,7 +1084,7 @@ "@TC_RETURN","\t$dst", []>, Requires<[IsNotDarwin]>; def TAILJMPdND : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops), - IIC_Br, "b\t$dst @ TAILCALL", + IIC_Br, "b.w\t$dst @ TAILCALL", []>, Requires<[IsNotDarwin]>; def TAILJMPrND : AXI<(outs), (ins tGPR:$dst, variable_ops), From gohman at apple.com Fri Jun 18 13:13:55 2010 From: gohman at apple.com (Dan Gohman) Date: Fri, 18 Jun 2010 18:13:55 -0000 Subject: [llvm-commits] [llvm] r106296 - in /llvm/trunk: include/llvm/CodeGen/MachineRegisterInfo.h include/llvm/Target/TargetInstrDesc.h include/llvm/Target/TargetRegisterInfo.h lib/CodeGen/MachineRegisterInfo.cpp lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h lib/Target/TargetInstrInfo.cpp utils/TableGen/InstrInfoEmitter.cpp utils/TableGen/RegisterInfoEmitter.cpp Message-ID: <20100618181355.5F97C2A6C12C@llvm.org> Author: djg Date: Fri Jun 18 13:13:55 2010 New Revision: 106296 URL: http://llvm.org/viewvc/llvm-project?rev=106296&view=rev Log: Start TargetRegisterClass indices at 0 instead of 1, so that MachineRegisterInfo doesn't have to confusingly allocate an extra entry. Modified: llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h llvm/trunk/include/llvm/Target/TargetInstrDesc.h llvm/trunk/include/llvm/Target/TargetRegisterInfo.h llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h llvm/trunk/lib/Target/TargetInstrInfo.cpp llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Modified: llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h?rev=106296&r1=106295&r2=106296&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h Fri Jun 18 13:13:55 2010 @@ -35,7 +35,7 @@ /// RegClassVRegMap - This vector acts as a map from TargetRegisterClass to /// virtual registers. For each target register class, it keeps a list of /// virtual registers belonging to the class. - std::vector > RegClass2VRegMap; + std::vector *RegClass2VRegMap; /// RegAllocHints - This vector records register allocation hints for virtual /// registers. For each virtual register, it keeps a register and hint type Modified: llvm/trunk/include/llvm/Target/TargetInstrDesc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrDesc.h?rev=106296&r1=106295&r2=106296&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetInstrDesc.h (original) +++ llvm/trunk/include/llvm/Target/TargetInstrDesc.h Fri Jun 18 13:13:55 2010 @@ -55,7 +55,7 @@ /// /// NOTE: This member should be considered to be private, all access should go /// through "getRegClass(TRI)" below. - unsigned short RegClass; + short RegClass; /// Flags - These are flags from the TOI::OperandFlags enum. unsigned short Flags; Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=106296&r1=106295&r2=106296&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Fri Jun 18 13:13:55 2010 @@ -523,8 +523,8 @@ /// getRegClass - Returns the register class associated with the enumeration /// value. See class TargetOperandInfo. const TargetRegisterClass *getRegClass(unsigned i) const { - assert(i <= getNumRegClasses() && "Register Class ID out of range"); - return i ? RegClassBegin[i - 1] : NULL; + assert(i < getNumRegClasses() && "Register Class ID out of range"); + return RegClassBegin[i]; } /// getPointerRegClass - Returns a TargetRegisterClass used for pointer Modified: llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp?rev=106296&r1=106295&r2=106296&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp Fri Jun 18 13:13:55 2010 @@ -20,7 +20,7 @@ MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) { VRegInfo.reserve(256); RegAllocHints.reserve(256); - RegClass2VRegMap.resize(TRI.getNumRegClasses()+1); // RC ID starts at 1. + RegClass2VRegMap = new std::vector[TRI.getNumRegClasses()]; UsedPhysRegs.resize(TRI.getNumRegs()); // Create the physreg use/def lists. @@ -52,7 +52,7 @@ // Remove from old register class's vregs list. This may be slow but // fortunately this operation is rarely needed. std::vector &VRegs = RegClass2VRegMap[OldRC->getID()]; - std::vector::iterator I=std::find(VRegs.begin(), VRegs.end(), VR); + std::vector::iterator I = std::find(VRegs.begin(), VRegs.end(), VR); VRegs.erase(I); // Add to new register class's vregs list. Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=106296&r1=106295&r2=106296&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Fri Jun 18 13:13:55 2010 @@ -765,7 +765,7 @@ || Opcode == ARM::SMC || Opcode == ARM::SVC) && "Unexpected Opcode"); - assert(NumOps >= 1 && OpInfo[0].RegClass == 0 && "Reg operand expected"); + assert(NumOps >= 1 && OpInfo[0].RegClass < 0 && "Reg operand expected"); int Imm32 = 0; if (Opcode == ARM::SMC) { @@ -1106,7 +1106,7 @@ assert((OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) && (OpInfo[OpIdx+1].RegClass == ARM::GPRRegClassID) && - (OpInfo[OpIdx+2].RegClass == 0) && + (OpInfo[OpIdx+2].RegClass < 0) && "Expect 3 reg operands"); // Register-controlled shifts have Inst{7} = 0 and Inst{4} = 1. @@ -1201,7 +1201,7 @@ return false; assert((OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) && - (OpInfo[OpIdx+1].RegClass == 0) && + (OpInfo[OpIdx+1].RegClass < 0) && "Expect 1 reg operand followed by 1 imm operand"); ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub; @@ -1323,7 +1323,7 @@ return false; assert((OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) && - (OpInfo[OpIdx+1].RegClass == 0) && + (OpInfo[OpIdx+1].RegClass < 0) && "Expect 1 reg operand followed by 1 imm operand"); ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub; @@ -1494,7 +1494,7 @@ // If there is still an operand info left which is an immediate operand, add // an additional imm5 LSL/ASR operand. - if (ThreeReg && OpInfo[OpIdx].RegClass == 0 + if (ThreeReg && OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) { // Extract the 5-bit immediate field Inst{11-7}. unsigned ShiftAmt = (insn >> ARMII::ShiftShift) & 0x1F; @@ -1540,7 +1540,7 @@ // If there is still an operand info left which is an immediate operand, add // an additional rotate immediate operand. - if (OpIdx < NumOps && OpInfo[OpIdx].RegClass == 0 + if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) { // Extract the 2-bit rotate field Inst{11-10}. unsigned rot = (insn >> ARMII::ExtRotImmShift) & 3; @@ -1725,7 +1725,7 @@ "Tied to operand expected"); MI.addOperand(MI.getOperand(0)); - assert(OpInfo[2].RegClass == 0 && !OpInfo[2].isPredicate() && + assert(OpInfo[2].RegClass < 0 && !OpInfo[2].isPredicate() && !OpInfo[2].isOptionalDef() && "Imm operand expected"); MI.addOperand(MCOperand::CreateImm(fbits)); @@ -1984,7 +1984,7 @@ ++OpIdx; // Extract/decode the f64/f32 immediate. - if (OpIdx < NumOps && OpInfo[OpIdx].RegClass == 0 + if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) { // The asm syntax specifies the before-expanded . // Not VFPExpandImm(slice(insn,19,16) << 4 | slice(insn, 3, 0), @@ -2273,7 +2273,7 @@ } assert((OpIdx+1) < NumOps && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID && - OpInfo[OpIdx + 1].RegClass == 0 && "Addrmode #6 Operands expected"); + OpInfo[OpIdx + 1].RegClass < 0 && "Addrmode #6 Operands expected"); MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, Rn))); MI.addOperand(MCOperand::CreateImm(0)); // Alignment ignored? @@ -2299,7 +2299,7 @@ } // Handle possible lane index. - if (OpIdx < NumOps && OpInfo[OpIdx].RegClass == 0 + if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) { MI.addOperand(MCOperand::CreateImm(decodeLaneIndex(insn))); ++OpIdx; @@ -2325,7 +2325,7 @@ } assert((OpIdx+1) < NumOps && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID && - OpInfo[OpIdx + 1].RegClass == 0 && "Addrmode #6 Operands expected"); + OpInfo[OpIdx + 1].RegClass < 0 && "Addrmode #6 Operands expected"); MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, Rn))); MI.addOperand(MCOperand::CreateImm(0)); // Alignment ignored? @@ -2344,7 +2344,7 @@ } // Handle possible lane index. - if (OpIdx < NumOps && OpInfo[OpIdx].RegClass == 0 + if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) { MI.addOperand(MCOperand::CreateImm(decodeLaneIndex(insn))); ++OpIdx; @@ -2408,7 +2408,7 @@ assert(NumOps >= 2 && (OpInfo[0].RegClass == ARM::DPRRegClassID || OpInfo[0].RegClass == ARM::QPRRegClassID) && - (OpInfo[1].RegClass == 0) && + (OpInfo[1].RegClass < 0) && "Expect 1 reg operand followed by 1 imm operand"); // Qd/Dd = Inst{22:15-12} => NEON Rd @@ -2522,7 +2522,7 @@ } // Add the imm operand, if required. - if (OpIdx < NumOps && OpInfo[OpIdx].RegClass == 0 + if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) { unsigned imm = 0xFFFFFFFF; @@ -2602,7 +2602,7 @@ decodeNEONRm(insn)))); ++OpIdx; - assert(OpInfo[OpIdx].RegClass == 0 && "Imm operand expected"); + assert(OpInfo[OpIdx].RegClass < 0 && "Imm operand expected"); // Add the imm operand. @@ -2732,7 +2732,7 @@ getRegisterEnum(B, OpInfo[OpIdx].RegClass, m))); ++OpIdx; - if (OpIdx < NumOps && OpInfo[OpIdx].RegClass == 0 + if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) { // Add the imm operand. unsigned Imm = 0; @@ -2857,7 +2857,7 @@ assert(TID.getNumDefs() == 1 && NumOps >= 3 && OpInfo[0].RegClass == ARM::GPRRegClassID && OpInfo[1].RegClass == ARM::DPRRegClassID && - OpInfo[2].RegClass == 0 && + OpInfo[2].RegClass < 0 && "Expect >= 3 operands with one dst operand"); ElemSize esize = @@ -2893,7 +2893,7 @@ OpInfo[1].RegClass == ARM::DPRRegClassID && TID.getOperandConstraint(1, TOI::TIED_TO) != -1 && OpInfo[2].RegClass == ARM::GPRRegClassID && - OpInfo[3].RegClass == 0 && + OpInfo[3].RegClass < 0 && "Expect >= 3 operands with one dst operand"); ElemSize esize = @@ -3203,7 +3203,8 @@ // a pair of TargetOperandInfos with isPredicate() property. if (NumOpsRemaining >= 2 && OpInfo[Idx].isPredicate() && OpInfo[Idx+1].isPredicate() && - OpInfo[Idx].RegClass == 0 && OpInfo[Idx+1].RegClass == ARM::CCRRegClassID) + OpInfo[Idx].RegClass < 0 && + OpInfo[Idx+1].RegClass == ARM::CCRRegClassID) { // If we are inside an IT block, get the IT condition bits maintained via // ARMBasicMCBuilder::ITState[7:0], through ARMBasicMCBuilder::GetITCond(). @@ -3235,7 +3236,8 @@ // a pair of TargetOperandInfos with isPredicate() property. if (NumOpsRemaining >= 2 && OpInfo[Idx].isPredicate() && OpInfo[Idx+1].isPredicate() && - OpInfo[Idx].RegClass == 0 && OpInfo[Idx+1].RegClass == ARM::CCRRegClassID) + OpInfo[Idx].RegClass < 0 && + OpInfo[Idx+1].RegClass == ARM::CCRRegClassID) { // If we are inside an IT block, get the IT condition bits maintained via // ARMBasicMCBuilder::ITState[7:0], through ARMBasicMCBuilder::GetITCond(). Modified: llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h?rev=106296&r1=106295&r2=106296&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h Fri Jun 18 13:13:55 2010 @@ -395,7 +395,7 @@ MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::tGPRRegClassID, getT1tRm(insn)))); } else { - assert(OpInfo[OpIdx].RegClass == 0 && + assert(OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef() && "Pure imm operand expected"); MI.addOperand(MCOperand::CreateImm(UseRt ? getT1Imm8(insn) @@ -531,7 +531,7 @@ if (!OpInfo) return false; assert(NumOps >= 2 && OpInfo[0].RegClass == ARM::tGPRRegClassID && - (OpInfo[1].RegClass == 0 && + (OpInfo[1].RegClass < 0 && !OpInfo[1].isPredicate() && !OpInfo[1].isOptionalDef()) && "Invalid arguments"); @@ -598,7 +598,7 @@ assert(OpIdx < NumOps && "More operands expected"); - if (OpInfo[OpIdx].RegClass == 0 && !OpInfo[OpIdx].isPredicate() && + if (OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) { MI.addOperand(MCOperand::CreateImm(Imm5 ? getT1Imm5(insn) : 0)); @@ -632,7 +632,7 @@ assert(NumOps >= 3 && OpInfo[0].RegClass == ARM::tGPRRegClassID && OpInfo[1].RegClass == ARM::GPRRegClassID && - (OpInfo[2].RegClass == 0 && + (OpInfo[2].RegClass < 0 && !OpInfo[2].isPredicate() && !OpInfo[2].isOptionalDef()) && "Invalid arguments"); @@ -658,7 +658,7 @@ if (!OpInfo) return false; assert(NumOps >= 2 && OpInfo[0].RegClass == ARM::tGPRRegClassID && - (OpInfo[1].RegClass == 0 && + (OpInfo[1].RegClass < 0 && !OpInfo[1].isPredicate() && !OpInfo[1].isOptionalDef()) && "Invalid arguments"); @@ -685,7 +685,7 @@ assert(NumOps >= 3 && OpInfo[0].RegClass == ARM::tGPRRegClassID && OpInfo[1].RegClass == ARM::GPRRegClassID && - (OpInfo[2].RegClass == 0 && + (OpInfo[2].RegClass < 0 && !OpInfo[2].isPredicate() && !OpInfo[2].isOptionalDef()) && "Invalid arguments"); @@ -761,7 +761,7 @@ // Predicate operands are handled elsewhere. if (NumOps == 2 && OpInfo[0].isPredicate() && OpInfo[1].isPredicate() && - OpInfo[0].RegClass == 0 && OpInfo[1].RegClass == ARM::CCRRegClassID) { + OpInfo[0].RegClass < 0 && OpInfo[1].RegClass == ARM::CCRRegClassID) { return true; } @@ -808,7 +808,7 @@ } assert(NumOps >= 2 && OpInfo[0].RegClass == ARM::tGPRRegClassID && - (OpInfo[1].RegClass==0 || OpInfo[1].RegClass==ARM::tGPRRegClassID) + (OpInfo[1].RegClass < 0 || OpInfo[1].RegClass==ARM::tGPRRegClassID) && "Expect >=2 operands"); // Add the destination operand. @@ -913,7 +913,7 @@ const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; if (!OpInfo) return false; - assert(NumOps == 3 && OpInfo[0].RegClass == 0 && + assert(NumOps == 3 && OpInfo[0].RegClass < 0 && OpInfo[1].isPredicate() && OpInfo[2].RegClass == ARM::CCRRegClassID && "Exactly 3 operands expected"); @@ -939,7 +939,7 @@ const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; if (!OpInfo) return false; - assert(NumOps == 1 && OpInfo[0].RegClass == 0 && "1 imm operand expected"); + assert(NumOps == 1 && OpInfo[0].RegClass < 0 && "1 imm operand expected"); unsigned Imm11 = getT1Imm11(insn); @@ -1239,7 +1239,7 @@ && OpInfo[0].RegClass == ARM::GPRRegClassID && OpInfo[1].RegClass == ARM::GPRRegClassID && OpInfo[2].RegClass == ARM::GPRRegClassID - && OpInfo[3].RegClass == 0 + && OpInfo[3].RegClass < 0 && "Expect >= 4 operands and first 3 as reg operands"); // Add the operands. @@ -1322,8 +1322,8 @@ assert(NumOps == 4 && OpInfo[0].RegClass == ARM::GPRRegClassID && OpInfo[1].RegClass == ARM::GPRRegClassID - && OpInfo[2].RegClass == 0 - && OpInfo[3].RegClass == 0 + && OpInfo[2].RegClass < 0 + && OpInfo[3].RegClass < 0 && "Exactlt 4 operands expect and first two as reg operands"); // Only need to populate the src reg operand. MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, @@ -1375,7 +1375,7 @@ if (NumOps == OpIdx) return true; - if (OpInfo[OpIdx].RegClass == 0 && !OpInfo[OpIdx].isPredicate() + if (OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) { if (Thumb2ShiftOpcode(Opcode)) @@ -1440,7 +1440,7 @@ } // The modified immediate operand should come next. - assert(OpIdx < NumOps && OpInfo[OpIdx].RegClass == 0 && + assert(OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef() && "Pure imm operand expected"); @@ -1555,7 +1555,7 @@ ++OpIdx; } - assert(OpInfo[OpIdx].RegClass == 0 && !OpInfo[OpIdx].isPredicate() + assert(OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef() && "Pure imm operand expected"); @@ -1772,7 +1772,7 @@ MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, decodeRm(insn)))); } else { - assert(OpInfo[OpIdx].RegClass == 0 && !OpInfo[OpIdx].isPredicate() + assert(OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef() && "Pure imm operand expected"); int Offset = 0; @@ -1792,7 +1792,7 @@ } ++OpIdx; - if (OpIdx < NumOps && OpInfo[OpIdx].RegClass == 0 && + if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) { // Fills in the shift amount for t2PLDs, t2PLDWs, t2PLIs. MI.addOperand(MCOperand::CreateImm(slice(insn, 5, 4))); @@ -1818,7 +1818,7 @@ assert(NumOps >= 2 && OpInfo[0].RegClass == ARM::GPRRegClassID && - OpInfo[1].RegClass == 0 && + OpInfo[1].RegClass < 0 && "Expect >= 2 operands, first as reg, and second as imm operand"); // Build the register operand, followed by the (+/-)imm12 immediate. @@ -1930,7 +1930,7 @@ ++OpIdx; } - assert(OpInfo[OpIdx].RegClass == 0 && !OpInfo[OpIdx].isPredicate() + assert(OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef() && "Pure imm operand expected"); @@ -1981,7 +1981,7 @@ decodeRm(insn)))); ++OpIdx; - if (OpIdx < NumOps && OpInfo[OpIdx].RegClass == 0 + if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) { // Add the rotation amount immediate. MI.addOperand(MCOperand::CreateImm(decodeRotate(insn))); Modified: llvm/trunk/lib/Target/TargetInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetInstrInfo.cpp?rev=106296&r1=106295&r2=106296&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/TargetInstrInfo.cpp Fri Jun 18 13:13:55 2010 @@ -28,6 +28,10 @@ TargetOperandInfo::getRegClass(const TargetRegisterInfo *TRI) const { if (isLookupPtrRegClass()) return TRI->getPointerRegClass(RegClass); + // Instructions like INSERT_SUBREG do not have fixed register classes. + if (RegClass < 0) + return 0; + // Otherwise just look it up normally. return TRI->getRegClass(RegClass); } Modified: llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp?rev=106296&r1=106295&r2=106296&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp Fri Jun 18 13:13:55 2010 @@ -92,7 +92,8 @@ else if (OpR->isSubClassOf("PointerLikeRegClass")) Res += utostr(OpR->getValueAsInt("RegClassKind")) + ", "; else - Res += "0, "; + // -1 means the operand does not have a fixed register class. + Res += "-1, "; // Fill in applicable flags. Res += "0"; Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=106296&r1=106295&r2=106296&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Fri Jun 18 13:13:55 2010 @@ -96,7 +96,7 @@ for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { if (i) OS << ",\n"; OS << " " << RegisterClasses[i].getName() << "RegClassID"; - OS << " = " << (i+1); + OS << " = " << i; } OS << "\n };\n\n"; From nlewycky at google.com Fri Jun 18 13:17:16 2010 From: nlewycky at google.com (Nick Lewycky) Date: Fri, 18 Jun 2010 11:17:16 -0700 Subject: [llvm-commits] [gold][patch] Add a pass-through option to the plugin In-Reply-To: References: Message-ID: Style cleanup: + for (std::vector::iterator i = options::pass_through.begin(), + e = options::pass_through.end(); + i != e; + ++i) { The i != e; and ++i can be on one line + std::string& item = *i; Space before &, not after + if (add_input_library (item_p + 2) != LDPS_OK) { Extra space after function name before paren. + if (add_input_file (item_p) != LDPS_OK) { Extra space again! Please fix those and commit. This sure is a strange problem. The linker asks us what symbols the IR files use, we tell it the wrong list (lacking symbols we will use) because we can't produce the right one until after we have all the information about all native symbols and all the IR files. The linker may have already discarded a symbol as unused, only to have it come back to life after add_input_file. Would it make sense to hard-code the plugin to tell gold to search in libc and libgcc for any symbols that simplify-libcalls or the backend may have added? That might not work so well for compiler-rt users. Would it make sense to have gold iterate on the list of symbols? They probably wouldn't like that at all, it would be the same as ignoring the order of libraries and .o files on the command line. Maybe we could conservatively include every libc/libgcc function our optimizers might add? It'd be a pain to maintain. Anyhow, I'm not going to ask you to pursue that (unless you really want to). Your fix solves the problem without introducing a big mess for any of the pieces. Could anyone comment on what Apple's LTO link does about this? Nick On 18 June 2010 07:21, Rafael Espindola wrote: > The attached patch adds a pass-through option to the plugin. The use > for this option is to ask the linker to take another look into some > library or object. The case when one might want to do this is when > codegen introduces a new undefined reference. The canonical example is > libgcc. > > Cheers, > -- > Rafael ?vila de Esp?ndola > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100618/0a3f9eb1/attachment.html From gohman at apple.com Fri Jun 18 13:54:05 2010 From: gohman at apple.com (Dan Gohman) Date: Fri, 18 Jun 2010 18:54:05 -0000 Subject: [llvm-commits] [llvm] r106298 - /llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp Message-ID: <20100618185405.F2B122A6C12C@llvm.org> Author: djg Date: Fri Jun 18 13:54:05 2010 New Revision: 106298 URL: http://llvm.org/viewvc/llvm-project?rev=106298&view=rev Log: Don't leak RegClass2VRegMap, which is now a new[] array instead of a std::vector. Modified: llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp Modified: llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp?rev=106298&r1=106297&r2=106298&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp Fri Jun 18 13:54:05 2010 @@ -37,6 +37,7 @@ "PhysRegUseDefLists has entries after all instructions are deleted"); #endif delete [] PhysRegUseDefLists; + delete [] RegClass2VRegMap; } /// setRegClass - Set the register class of the specified virtual register. From dalej at apple.com Fri Jun 18 14:00:18 2010 From: dalej at apple.com (Dale Johannesen) Date: Fri, 18 Jun 2010 19:00:18 -0000 Subject: [llvm-commits] [llvm] r106299 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/ARM/call-tc.ll test/CodeGen/ARM/ifcvt6-tc.ll test/CodeGen/ARM/insn-sched1-tc.ll test/CodeGen/ARM/ldm-tc.ll test/CodeGen/Thumb2/thumb2-call-tc.ll test/CodeGen/Thumb2/thumb2-ifcvt1-tc.ll Message-ID: <20100618190018.9B0C12A6C12C@llvm.org> Author: johannes Date: Fri Jun 18 14:00:18 2010 New Revision: 106299 URL: http://llvm.org/viewvc/llvm-project?rev=106299&view=rev Log: Enable tail calls on ARM by default, with some basic tests. This has been well tested on Darwin but not elsewhere. It should work provided the linker correctly resolves B.W
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