From dpatel at apple.com  Mon Jun 28 00:53:08 2010
From: dpatel at apple.com (Devang Patel)
Date: Mon, 28 Jun 2010 05:53:08 -0000
Subject: [llvm-commits] [llvm] r106989 -
	/llvm/trunk/lib/Analysis/DebugInfo.cpp
Message-ID: <20100628055308.618B02A6C12C@llvm.org>

Author: dpatel
Date: Mon Jun 28 00:53:08 2010
New Revision: 106989

URL: http://llvm.org/viewvc/llvm-project?rev=106989&view=rev
Log:
Use named MDNode, llvm.dbg.sp, to collect subprogram info. This will be used to emit  local variable's debug info of deleted functions.

Modified:
    llvm/trunk/lib/Analysis/DebugInfo.cpp

Modified: llvm/trunk/lib/Analysis/DebugInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DebugInfo.cpp?rev=106989&r1=106988&r2=106989&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/DebugInfo.cpp (original)
+++ llvm/trunk/lib/Analysis/DebugInfo.cpp Mon Jun 28 00:53:08 2010
@@ -971,7 +971,12 @@
     ConstantInt::get(Type::getInt1Ty(VMContext), isOptimized),
     Fn
   };
-  return DISubprogram(MDNode::get(VMContext, &Elts[0], 17));
+  MDNode *Node = MDNode::get(VMContext, &Elts[0], 17);
+
+  // Create a named metadata so that we do not lose this mdnode.
+  NamedMDNode *NMD = M.getOrInsertNamedMetadata("llvm.dbg.sp");
+  NMD->addOperand(Node);
+  return DISubprogram(Node);
 }
 
 /// CreateSubprogramDefinition - Create new subprogram descriptor for the
@@ -1000,7 +1005,12 @@
     DeclNode->getOperand(15), // isOptimized
     SPDeclaration.getFunction()
   };
-  return DISubprogram(MDNode::get(VMContext, &Elts[0], 16));
+  MDNode *Node =MDNode::get(VMContext, &Elts[0], 16);
+
+  // Create a named metadata so that we do not lose this mdnode.
+  NamedMDNode *NMD = M.getOrInsertNamedMetadata("llvm.dbg.sp");
+  NMD->addOperand(Node);
+  return DISubprogram(Node);
 }
 
 /// CreateGlobalVariable - Create a new descriptor for the specified global.
@@ -1230,17 +1240,19 @@
           processLocation(DILocation(IA));
       }
 
-  NamedMDNode *NMD = M.getNamedMetadata("llvm.dbg.gv");
-  if (!NMD)
-    return;
-
-  for (unsigned i = 0, e = NMD->getNumOperands(); i != e; ++i) {
-    DIGlobalVariable DIG(cast<MDNode>(NMD->getOperand(i)));
-    if (addGlobalVariable(DIG)) {
-      addCompileUnit(DIG.getCompileUnit());
-      processType(DIG.getType());
+  if (NamedMDNode *NMD = M.getNamedMetadata("llvm.dbg.gv")) {
+    for (unsigned i = 0, e = NMD->getNumOperands(); i != e; ++i) {
+      DIGlobalVariable DIG(cast<MDNode>(NMD->getOperand(i)));
+      if (addGlobalVariable(DIG)) {
+        addCompileUnit(DIG.getCompileUnit());
+        processType(DIG.getType());
+      }
     }
   }
+
+  if (NamedMDNode *NMD = M.getNamedMetadata("llvm.dbg.sp"))
+    for (unsigned i = 0, e = NMD->getNumOperands(); i != e; ++i)
+      processSubprogram(DISubprogram(NMD->getOperand(i)));
 }
 
 /// processLocation - Process DILocation.




From dpatel at apple.com  Mon Jun 28 00:59:14 2010
From: dpatel at apple.com (Devang Patel)
Date: Mon, 28 Jun 2010 05:59:14 -0000
Subject: [llvm-commits] [llvm] r106990 - in
 /llvm/trunk/lib/CodeGen/AsmPrinter: DwarfDebug.cpp DwarfDebug.h
Message-ID: <20100628055914.19A2B2A6C12C@llvm.org>

Author: dpatel
Date: Mon Jun 28 00:59:13 2010
New Revision: 106990

URL: http://llvm.org/viewvc/llvm-project?rev=106990&view=rev
Log:
Remove dead code.

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=106990&r1=106989&r2=106990&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Mon Jun 28 00:59:13 2010
@@ -2589,7 +2589,6 @@
            RE = Ranges.end(); RI != RE; ++RI) {
       assert(RI->first && "DbgRange does not have first instruction!");      
       assert(RI->second && "DbgRange does not have second instruction!");      
-      InsnsBeginScopeSet.insert(RI->first);
       InsnsEndScopeSet.insert(RI->second);
     }
   }
@@ -2753,7 +2752,6 @@
   DbgVariableToDbgInstMap.clear();
   DbgVariableLabelsMap.clear();
   DeleteContainerSeconds(DbgScopeMap);
-  InsnsBeginScopeSet.clear();
   InsnsEndScopeSet.clear();
   ConcreteScopes.clear();
   DeleteContainerSeconds(AbstractScopes);

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h?rev=106990&r1=106989&r2=106990&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Mon Jun 28 00:59:13 2010
@@ -210,7 +210,7 @@
   DenseMap<DIE *, const MDNode *> ContainingTypeMap;
 
   typedef SmallVector<DbgScope *, 2> ScopeVector;
-  SmallPtrSet<const MachineInstr *, 8> InsnsBeginScopeSet;
+
   SmallPtrSet<const MachineInstr *, 8> InsnsEndScopeSet;
 
   /// InlineInfo - Keep track of inlined functions and their location.  This




From baldrick at free.fr  Mon Jun 28 03:01:15 2010
From: baldrick at free.fr (Duncan Sands)
Date: Mon, 28 Jun 2010 08:01:15 -0000
Subject: [llvm-commits] [dragonegg] r106991 -
	/dragonegg/trunk/llvm-backend.cpp
Message-ID: <20100628080115.46AFC2A6C12D@llvm.org>

Author: baldrick
Date: Mon Jun 28 03:01:15 2010
New Revision: 106991

URL: http://llvm.org/viewvc/llvm-project?rev=106991&view=rev
Log:
Check if turning on the ODR is still breaking the self-host
build.

Modified:
    dragonegg/trunk/llvm-backend.cpp

Modified: dragonegg/trunk/llvm-backend.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/llvm-backend.cpp?rev=106991&r1=106990&r2=106991&view=diff
==============================================================================
--- dragonegg/trunk/llvm-backend.cpp (original)
+++ dragonegg/trunk/llvm-backend.cpp Mon Jun 28 03:01:15 2010
@@ -537,7 +537,7 @@
   } else if (LanguageName == "GNU C") {
     flag_vararg_requires_arguments = true; // "T foo() {}" -> "T foo(void) {}"
   } else if (LanguageName == "GNU C++") {
-//    flag_odr = true; // C++ obeys the one-definition-rule
+    flag_odr = true; // C++ obeys the one-definition-rule
   } else if (LanguageName == "GNU Fortran") {
   } else if (LanguageName == "GNU GIMPLE") { // LTO gold plugin
   } else if (LanguageName == "GNU Java") {




From anton at korobeynikov.info  Mon Jun 28 03:29:23 2010
From: anton at korobeynikov.info (Anton Korobeynikov)
Date: Mon, 28 Jun 2010 12:29:23 +0400
Subject: [llvm-commits] Global Merge Pass for ARM
In-Reply-To: <AANLkTin8rBAIenURpVtQKIOJ_23JHXVbI3xH3TLph9lp@mail.gmail.com>
References: <1274006983.22060.61.camel@aslstation>
	<85FA0CB8-76CF-42A8-AD4F-C17F08902366@apple.com>
	<AANLkTily_30vdBcmwWVeiJaAKlrsB0mOok13_BERjKN3@mail.gmail.com>
	<B9CA014A-E61A-45F3-A5E7-B2F2928A4DB1@apple.com>
	<1275140451.22060.104.camel@aslstation>
	<2511C9BB-5E58-4A8C-B7DB-C134052193CC@apple.com>
	<AANLkTil3OHharErO50AZX9mujk8RzY7c5yn9TffufVlA@mail.gmail.com>
	<AANLkTin8rBAIenURpVtQKIOJ_23JHXVbI3xH3TLph9lp@mail.gmail.com>
Message-ID: <AANLkTilDBPIuRKvH7fwaplxpqGlhzRJ74FRfZikyDLNA@mail.gmail.com>

> Ping?
Ping^2

-- 
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University


From baldrick at free.fr  Mon Jun 28 04:22:34 2010
From: baldrick at free.fr (Duncan Sands)
Date: Mon, 28 Jun 2010 09:22:34 -0000
Subject: [llvm-commits] [dragonegg] r106994 -
	/dragonegg/trunk/llvm-backend.cpp
Message-ID: <20100628092234.5D8B52A6C12C@llvm.org>

Author: baldrick
Date: Mon Jun 28 04:22:34 2010
New Revision: 106994

URL: http://llvm.org/viewvc/llvm-project?rev=106994&view=rev
Log:
Turning on the ODR still causes the x86-32 self-host to fail, so turn
it off again.

Modified:
    dragonegg/trunk/llvm-backend.cpp

Modified: dragonegg/trunk/llvm-backend.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/llvm-backend.cpp?rev=106994&r1=106993&r2=106994&view=diff
==============================================================================
--- dragonegg/trunk/llvm-backend.cpp (original)
+++ dragonegg/trunk/llvm-backend.cpp Mon Jun 28 04:22:34 2010
@@ -537,7 +537,7 @@
   } else if (LanguageName == "GNU C") {
     flag_vararg_requires_arguments = true; // "T foo() {}" -> "T foo(void) {}"
   } else if (LanguageName == "GNU C++") {
-    flag_odr = true; // C++ obeys the one-definition-rule
+//    flag_odr = true; // C++ obeys the one-definition-rule
   } else if (LanguageName == "GNU Fortran") {
   } else if (LanguageName == "GNU GIMPLE") { // LTO gold plugin
   } else if (LanguageName == "GNU Java") {




From ggreif at gmail.com  Mon Jun 28 06:20:43 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Mon, 28 Jun 2010 11:20:43 -0000
Subject: [llvm-commits] [llvm] r107000 -
	/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp
Message-ID: <20100628112043.123952A6C12C@llvm.org>

Author: ggreif
Date: Mon Jun 28 06:20:42 2010
New Revision: 107000

URL: http://llvm.org/viewvc/llvm-project?rev=107000&view=rev
Log:
use cached value

Modified:
    llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=107000&r1=106999&r2=107000&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Mon Jun 28 06:20:42 2010
@@ -965,7 +965,7 @@
       isSafeGEP(GEPI, AI, GEPOffset, Info);
       if (!Info.isUnsafe)
         isSafeForScalarRepl(GEPI, AI, GEPOffset, Info);
-    } else if (MemIntrinsic *MI = dyn_cast<MemIntrinsic>(UI)) {
+    } else if (MemIntrinsic *MI = dyn_cast<MemIntrinsic>(User)) {
       ConstantInt *Length = dyn_cast<ConstantInt>(MI->getLength());
       if (Length)
         isSafeMemAccess(AI, Offset, Length->getZExtValue(), 0,




From ggreif at gmail.com  Mon Jun 28 07:23:36 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Mon, 28 Jun 2010 12:23:36 -0000
Subject: [llvm-commits] [llvm] r107001 -
	/llvm/trunk/include/llvm/Instructions.h
Message-ID: <20100628122336.4BCF32A6C12C@llvm.org>

Author: ggreif
Date: Mon Jun 28 07:23:36 2010
New Revision: 107001

URL: http://llvm.org/viewvc/llvm-project?rev=107001&view=rev
Log:
extend ArgOperand interface: setArgOperand
(in both CallInst and InvokeInst)

also add a (short-lived) constant to CallInst, that names
the operand index of the first call argument. This is
strictly transitional and should not be used for new code.

Modified:
    llvm/trunk/include/llvm/Instructions.h

Modified: llvm/trunk/include/llvm/Instructions.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=107001&r1=107000&r2=107001&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Instructions.h (original)
+++ llvm/trunk/include/llvm/Instructions.h Mon Jun 28 07:23:36 2010
@@ -943,8 +943,10 @@
   /// Provide fast operand accessors
   DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
 
+  enum { ArgOffset = 1 }; ///< temporary, do not use for new code!
   unsigned getNumArgOperands() const { return getNumOperands() - 1; }
-  Value *getArgOperand(unsigned i) const { return getOperand(i + 1); }
+  Value *getArgOperand(unsigned i) const { return getOperand(i + ArgOffset); }
+  void setArgOperand(unsigned i, Value *v) { setOperand(i + ArgOffset, v); }
 
   /// getCallingConv/setCallingConv - Get or set the calling convention of this
   /// function call.
@@ -2440,6 +2442,7 @@
 
   unsigned getNumArgOperands() const { return getNumOperands() - 3; }
   Value *getArgOperand(unsigned i) const { return getOperand(i); }
+  void setArgOperand(unsigned i, Value *v) { setOperand(i, v); }
 
   /// getCallingConv/setCallingConv - Get or set the calling convention of this
   /// function call.




From ggreif at gmail.com  Mon Jun 28 07:29:20 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Mon, 28 Jun 2010 12:29:20 -0000
Subject: [llvm-commits] [llvm] r107002 -
	/llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp
Message-ID: <20100628122920.83D1F2A6C12C@llvm.org>

Author: ggreif
Date: Mon Jun 28 07:29:20 2010
New Revision: 107002

URL: http://llvm.org/viewvc/llvm-project?rev=107002&view=rev
Log:
use ArgOperand API and CallInst::ArgOffset

Modified:
    llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp

Modified: llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp?rev=107002&r1=107001&r2=107002&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp Mon Jun 28 07:29:20 2010
@@ -420,11 +420,11 @@
         FT->getParamType(2) != TD->getIntPtrType(Context) ||
         FT->getParamType(3) != TD->getIntPtrType(Context))
       return false;
-    
-    if (isFoldable(4, 3, false)) {
-      EmitMemCpy(CI->getOperand(1), CI->getOperand(2), CI->getOperand(3),
+
+    if (isFoldable(3 + CallInst::ArgOffset, 2 + CallInst::ArgOffset, false)) {
+      EmitMemCpy(CI->getArgOperand(0), CI->getArgOperand(1), CI->getArgOperand(2),
                  1, false, B, TD);
-      replaceCall(CI->getOperand(1));
+      replaceCall(CI->getArgOperand(0));
       return true;
     }
     return false;
@@ -443,11 +443,11 @@
         FT->getParamType(2) != TD->getIntPtrType(Context) ||
         FT->getParamType(3) != TD->getIntPtrType(Context))
       return false;
-    
-    if (isFoldable(4, 3, false)) {
-      EmitMemMove(CI->getOperand(1), CI->getOperand(2), CI->getOperand(3),
+
+    if (isFoldable(3 + CallInst::ArgOffset, 2 + CallInst::ArgOffset, false)) {
+      EmitMemMove(CI->getArgOperand(0), CI->getArgOperand(1), CI->getArgOperand(2),
                   1, false, B, TD);
-      replaceCall(CI->getOperand(1));
+      replaceCall(CI->getArgOperand(0));
       return true;
     }
     return false;
@@ -461,9 +461,9 @@
         FT->getParamType(2) != TD->getIntPtrType(Context) ||
         FT->getParamType(3) != TD->getIntPtrType(Context))
       return false;
-    
-    if (isFoldable(4, 3, false)) {
-      Value *Val = B.CreateIntCast(CI->getOperand(2), B.getInt8Ty(),
+
+    if (isFoldable(3 + CallInst::ArgOffset, 2 + CallInst::ArgOffset, false)) {
+      Value *Val = B.CreateIntCast(CI->getArgOperand(1), B.getInt8Ty(),
                                    false);
       EmitMemSet(CI->getArgOperand(0), Val,  CI->getArgOperand(2), false, B, TD);
       replaceCall(CI->getArgOperand(0));
@@ -487,8 +487,8 @@
     // st[rp]cpy_chk call which may fail at runtime if the size is too long.
     // TODO: It might be nice to get a maximum length out of the possible
     // string lengths for varying.
-    if (isFoldable(3, 2, true)) {
-      Value *Ret = EmitStrCpy(CI->getOperand(1), CI->getOperand(2), B, TD,
+    if (isFoldable(2 + CallInst::ArgOffset, 1 + CallInst::ArgOffset, true)) {
+      Value *Ret = EmitStrCpy(CI->getArgOperand(0), CI->getArgOperand(1), B, TD,
                               Name.substr(2, 6));
       replaceCall(Ret);
       return true;
@@ -504,10 +504,10 @@
         !FT->getParamType(2)->isIntegerTy() ||
         FT->getParamType(3) != TD->getIntPtrType(Context))
       return false;
-    
-    if (isFoldable(4, 3, false)) {
-      Value *Ret = EmitStrNCpy(CI->getOperand(1), CI->getOperand(2),
-                               CI->getOperand(3), B, TD, Name.substr(2, 7));
+
+    if (isFoldable(3 + CallInst::ArgOffset, 2 + CallInst::ArgOffset, false)) {
+      Value *Ret = EmitStrNCpy(CI->getArgOperand(0), CI->getArgOperand(1),
+                               CI->getArgOperand(2), B, TD, Name.substr(2, 7));
       replaceCall(Ret);
       return true;
     }




From ggreif at gmail.com  Mon Jun 28 07:30:07 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Mon, 28 Jun 2010 12:30:07 -0000
Subject: [llvm-commits] [llvm] r107003 -
	/llvm/trunk/lib/Transforms/Utils/AddrModeMatcher.cpp
Message-ID: <20100628123007.D6C512A6C12C@llvm.org>

Author: ggreif
Date: Mon Jun 28 07:30:07 2010
New Revision: 107003

URL: http://llvm.org/viewvc/llvm-project?rev=107003&view=rev
Log:
use CallInst::ArgOffset

Modified:
    llvm/trunk/lib/Transforms/Utils/AddrModeMatcher.cpp

Modified: llvm/trunk/lib/Transforms/Utils/AddrModeMatcher.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/AddrModeMatcher.cpp?rev=107003&r1=107002&r2=107003&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/AddrModeMatcher.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/AddrModeMatcher.cpp Mon Jun 28 07:30:07 2010
@@ -382,7 +382,7 @@
   std::vector<InlineAsm::ConstraintInfo>
   Constraints = IA->ParseConstraints();
   
-  unsigned ArgNo = 1;   // ArgNo - The operand of the CallInst.
+  unsigned ArgNo = CallInst::ArgOffset;   // ArgNo - The operand of the CallInst.
   for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
     TargetLowering::AsmOperandInfo OpInfo(Constraints[i]);
     




From ggreif at gmail.com  Mon Jun 28 07:31:35 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Mon, 28 Jun 2010 12:31:35 -0000
Subject: [llvm-commits] [llvm] r107004 -
 /llvm/trunk/lib/Transforms/Instrumentation/ProfilingUtils.cpp
Message-ID: <20100628123135.C3E622A6C12C@llvm.org>

Author: ggreif
Date: Mon Jun 28 07:31:35 2010
New Revision: 107004

URL: http://llvm.org/viewvc/llvm-project?rev=107004&view=rev
Log:
use setArgOperand

Modified:
    llvm/trunk/lib/Transforms/Instrumentation/ProfilingUtils.cpp

Modified: llvm/trunk/lib/Transforms/Instrumentation/ProfilingUtils.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Instrumentation/ProfilingUtils.cpp?rev=107004&r1=107003&r2=107004&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Instrumentation/ProfilingUtils.cpp (original)
+++ llvm/trunk/lib/Transforms/Instrumentation/ProfilingUtils.cpp Mon Jun 28 07:31:35 2010
@@ -61,8 +61,8 @@
   }
   Args[3] = ConstantInt::get(Type::getInt32Ty(Context), NumElements);
 
-  Instruction *InitCall = CallInst::Create(InitFn, Args.begin(), Args.end(),
-                                           "newargc", InsertPos);
+  CallInst *InitCall = CallInst::Create(InitFn, Args.begin(), Args.end(),
+                                        "newargc", InsertPos);
 
   // If argc or argv are not available in main, just pass null values in.
   Function::arg_iterator AI;
@@ -73,10 +73,10 @@
     if (AI->getType() != ArgVTy) {
       Instruction::CastOps opcode = CastInst::getCastOpcode(AI, false, ArgVTy, 
                                                             false);
-      InitCall->setOperand(2, 
+      InitCall->setArgOperand(1, 
           CastInst::Create(opcode, AI, ArgVTy, "argv.cast", InitCall));
     } else {
-      InitCall->setOperand(2, AI);
+      InitCall->setArgOperand(1, AI);
     }
     /* FALL THROUGH */
 
@@ -93,12 +93,12 @@
       }
       opcode = CastInst::getCastOpcode(AI, true,
                                        Type::getInt32Ty(Context), true);
-      InitCall->setOperand(1, 
+      InitCall->setArgOperand(0, 
           CastInst::Create(opcode, AI, Type::getInt32Ty(Context),
                            "argc.cast", InitCall));
     } else {
       AI->replaceAllUsesWith(InitCall);
-      InitCall->setOperand(1, AI);
+      InitCall->setArgOperand(0, AI);
     }
 
   case 0: break;




From espindola at google.com  Mon Jun 28 07:56:08 2010
From: espindola at google.com (Rafael Espindola)
Date: Mon, 28 Jun 2010 08:56:08 -0400
Subject: [llvm-commits] [patch] Don't use FpSET_ST0_80 with ST0 and ST1
	registers
In-Reply-To: <AANLkTimCo0bchxrq3clbKgcDmYg3H6ONGhLs__kcJsfI@mail.gmail.com>
References: <AANLkTimCo0bchxrq3clbKgcDmYg3H6ONGhLs__kcJsfI@mail.gmail.com>
Message-ID: <AANLkTilWKhxf070ILdyUdbohK6-nkR7w3N_sBGUTnmY-@mail.gmail.com>

Just noticed the subject is wrong, it should be "Don't use MOV_Fp8080
with ST0 and ST1 registers" :-)

OK, I did a lot of extra testing:

* Install debian sid 32 bits in a chroot
* patch and build llvm
* bootstrap llvm-gcc
* run the testsuite with llc-beta set to -mattr=-see
* revert the patch and build llvm
* run the testsuite with llc-beta set to -mattr=-see (again)

I got the same failures with and without the patch (attached). Is the patch OK?

Cheers,
-- 
Rafael ?vila de Esp?ndola
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From daniel at zuster.org  Mon Jun 28 10:47:18 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Mon, 28 Jun 2010 15:47:18 -0000
Subject: [llvm-commits] [llvm] r107009 -
	/llvm/trunk/lib/CodeGen/IfConversion.cpp
Message-ID: <20100628154718.290892A6C12C@llvm.org>

Author: ddunbar
Date: Mon Jun 28 10:47:17 2010
New Revision: 107009

URL: http://llvm.org/viewvc/llvm-project?rev=107009&view=rev
Log:
Revert r106907, "make sure to handle dbg_value instructions in the middle of the
block, not...", it caused a bunch of nightly test regressions.

Modified:
    llvm/trunk/lib/CodeGen/IfConversion.cpp

Modified: llvm/trunk/lib/CodeGen/IfConversion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/IfConversion.cpp?rev=107009&r1=107008&r2=107009&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/IfConversion.cpp (original)
+++ llvm/trunk/lib/CodeGen/IfConversion.cpp Mon Jun 28 10:47:17 2010
@@ -1228,18 +1228,10 @@
     ++DI2;
   BBI1->NonPredSize -= NumDups1;
   BBI2->NonPredSize -= NumDups1;
-  
-  // Skip past the dups on each side separately since there may be
-  // differing dbg_value entries.
-  for (unsigned i = 0; i < NumDups1; ++i) {
-    ++DI1;
-    if (!DI1->isDebugValue())
-      ++i;
-  }
   while (NumDups1 != 0) {
+    ++DI1;
     ++DI2;
-    if (!DI2->isDebugValue())
-      --NumDups1;
+    --NumDups1;
   }
 
   UpdatePredRedefs(BBI1->BB->begin(), DI1, Redefs, TRI);




From criswell at uiuc.edu  Mon Jun 28 10:48:13 2010
From: criswell at uiuc.edu (John Criswell)
Date: Mon, 28 Jun 2010 15:48:13 -0000
Subject: [llvm-commits] [poolalloc] r107010 -
	/poolalloc/trunk/lib/PoolAllocate/Heuristic.cpp
Message-ID: <20100628154814.004272A6C12C@llvm.org>

Author: criswell
Date: Mon Jun 28 10:48:13 2010
New Revision: 107010

URL: http://llvm.org/viewvc/llvm-project?rev=107010&view=rev
Log:
Updated alignment heuristic code for modern DSA; DSA can now infer multiple
types per offset within an object.
Added comments about things that still need to be fixed.

Modified:
    poolalloc/trunk/lib/PoolAllocate/Heuristic.cpp

Modified: poolalloc/trunk/lib/PoolAllocate/Heuristic.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/Heuristic.cpp?rev=107010&r1=107009&r2=107010&view=diff
==============================================================================
--- poolalloc/trunk/lib/PoolAllocate/Heuristic.cpp (original)
+++ poolalloc/trunk/lib/PoolAllocate/Heuristic.cpp Mon Jun 28 10:48:13 2010
@@ -101,9 +101,16 @@
 // Description:
 //  Determine if an object of the specified type should be allocated on an
 //  8-byte boundary.  This may either be required by the target platform or may
-//  merely improved performance by aligning data the way the processor wants
+//  merely improve performance by aligning data the way the processor wants
 //  it.
 //
+// Inputs:
+//  Ty   - The type of the object for which alignment should be tested.
+//  Offs - The offset of the type within a derived type (e.g., a structure).
+//         We will try to align a structure on an 8 byte boundary if one of its
+//         elements can/needs to be.
+//  TD   - A reference to the TargetData pass.
+//
 // Return value:
 //  true - This type should be allocated on an 8-byte boundary.
 //  false - This type does not need to be allocated on an 8-byte boundary.
@@ -112,36 +119,47 @@
 //  FIXME: This is a complete hack for X86 right now.
 //  FIXME: This code needs to be updated for x86-64.
 //  FIXME: This code needs to handle LLVM first-class structures and vectors.
-//  FIXME: What does Offs do?
 //
-static bool Wants8ByteAlignment(const Type *Ty, unsigned Offs,
-                                const TargetData &TD) {
+static bool
+Wants8ByteAlignment(const Type *Ty, unsigned Offs, const TargetData &TD) {
+  //
+  // If the user has requested this optimization to be turned off, don't bother
+  // doing it.
+  //
   if (DisableAlignOpt) return true;
 
+  //
+  // If this type is at an align-able offset within its larger data structure,
+  // see if we should 8 byte align it.
+  //
   if ((Offs & 7) == 0) {
     //
-    // Note:
-    //  The LLVM API has changed, and I do not know how to tell if a type is
-    //  is a double integer.  Furthermore, the alignment of a double to 8 bits
-    //  appears to be a hack, and it is not clear as to why.  Therefore, we
-    //  will simply align all floating point types on an 8 bit boundary.
+    // Doubles always want to be 8-byte aligned regardless of what TargetData
+    // claims.
+    //
+    if (Ty->isDoubleTy()) return true;
+
     //
-#if 0
-    // Doubles always want to be 8-byte aligned.
-    if (Ty == Type::DoubleTy) return true;
-#else
-    if (Ty->isFloatingPointTy()) return true;
-#endif
-    
     // If we are on a 64-bit system, we want to align 8-byte integers and
     // pointers.
+    //
     if (TD.getPrefTypeAlignment(Ty) == 8)
       return true;
   }
 
+  //
+  // If this is a first-class data type, but it is located at an offset within
+  // a structure that cannot be 8-byte aligned, then we cannot ever guarantee
+  // to 8-byte align it.  Therefore, do not try to force it to 8-byte
+  // alignment.
   if (Ty->isFirstClassType())
     return false;
 
+  //
+  // If this is a structure or array type, check if any of its elements at
+  // 8-byte alignment desire to have 8-byte alignment.  If so, then the entire
+  // object wants 8-byte alignment.
+  //
   if (const StructType *STy = dyn_cast<StructType>(Ty)) {
     const StructLayout *SL = TD.getStructLayout(STy);
     for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
@@ -155,6 +173,7 @@
     errs() << *Ty << "\n";
     assert(0 && "Unknown type!");
   }
+
   return false;
 }
 
@@ -166,35 +185,49 @@
   return Wants8ByteAlignment(Ty, 0, TD) ? 8 : 4;
 }
 
+///
 /// getRecommendedAlignment - Return the recommended object alignment for this
 /// DSNode.
 ///
-unsigned Heuristic::getRecommendedAlignment(const DSNode *N) {
-#if 0
-  const Type * VoidType = Type::getVoidTy(getGlobalContext());
-
+/// @Node - The DSNode for which allocation alignment information is requested.
+///
+/// FIXME: This method assumes an object wants 4-byte or 8-byte alignment.  The
+///        new types in LLVM may want larger alignments such as 16-byte
+///        alignment.  Need to update this code to handle that.
+///
+unsigned
+Heuristic::getRecommendedAlignment(const DSNode *Node) {
   //
-  // If this node has a void type (which can be signified by getType()
-  // returning NULL) or the node is collapsed, then there is no known
-  // alignment.  We will return 0 to let the runtime decide.
+  // Get the TargetData information from the DSNode's DSGraph.
   //
-  if ((!(N->getType())) || (N->getType() == VoidType))
-    return 0;
+  const TargetData &TD = Node->getParentGraph()->getTargetData();
 
-  const TargetData &TD = N->getParentGraph()->getTargetData();
-
-  // If there are no doubles on an 8-byte boundary in this structure, there is
-  // no reason to 8-byte align objects in the pool.
-  return Wants8ByteAlignment(N->getType(), 0, TD) ? 8 : 4;
-#else
-  //
-  // I believe there was a FIXME in the previous version of this code, but it
-  // was too vague for me to understand what, exactly, needed to be fixed.
   //
-  // In any event, it seems that this code should be deactivated for now.
+  // Iterate through all the types that the DSA type-inference algorithm
+  // found and determine if any of them should be 8-byte aligned.  If so, then
+  // we'll 8-byte align the entire structure.
   //
-  return 0;
-#endif
+  DSNode::const_type_iterator tyi;
+  for (tyi = Node->type_begin(); tyi != Node->type_end(); ++tyi) {
+    for (svset<const Type*>::const_iterator tyii = tyi->second->begin(),
+         tyee = tyi->second->end(); tyii != tyee; ++tyii) {
+      //
+      // Get the type of object allocated.  If there is no type, then it is
+      // implicitly of void type.
+      //
+      const Type * TypeCreated = *tyii;
+      if (TypeCreated) {
+        //
+        // If the type contains a pointer, it must be changed.
+        //
+        if (Wants8ByteAlignment(TypeCreated, tyi->first, TD)) {
+          return 8;
+        }
+      }
+    }
+  }
+
+  return 4;
 }
  
 




From gohman at apple.com  Mon Jun 28 10:55:15 2010
From: gohman at apple.com (Dan Gohman)
Date: Mon, 28 Jun 2010 15:55:15 -0000
Subject: [llvm-commits] [llvm] r107011 - /llvm/trunk/Makefile.rules
Message-ID: <20100628155515.C45222A6C12C@llvm.org>

Author: djg
Date: Mon Jun 28 10:55:15 2010
New Revision: 107011

URL: http://llvm.org/viewvc/llvm-project?rev=107011&view=rev
Log:
Fix this build message so that it displays the correct library
name, specifically the "lib" prefix.

Modified:
    llvm/trunk/Makefile.rules

Modified: llvm/trunk/Makefile.rules
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=107011&r1=107010&r2=107011&view=diff
==============================================================================
--- llvm/trunk/Makefile.rules (original)
+++ llvm/trunk/Makefile.rules Mon Jun 28 10:55:15 2010
@@ -1131,7 +1131,7 @@
 	  $(ProjLibsOptions) $(LLVMLibsOptions) $(LIBS)
 else
 $(LibName.SO): $(ObjectsO) $(LibDir)/.dir
-	$(Echo) Linking $(BuildMode) Shared Library $(LIBRARYNAME)$(SHLIBEXT)
+	$(Echo) Linking $(BuildMode) Shared Library $(basename $@)
 	$(Verb) $(Link) $(SharedLinkOptions) -o $@ $(ObjectsO)
 endif
 




From gohman at apple.com  Mon Jun 28 11:01:37 2010
From: gohman at apple.com (Dan Gohman)
Date: Mon, 28 Jun 2010 16:01:37 -0000
Subject: [llvm-commits] [llvm] r107013 - in /llvm/trunk:
 include/llvm/Analysis/Passes.h lib/Analysis/AliasAnalysisEvaluator.cpp
Message-ID: <20100628160137.80B092A6C12C@llvm.org>

Author: djg
Date: Mon Jun 28 11:01:37 2010
New Revision: 107013

URL: http://llvm.org/viewvc/llvm-project?rev=107013&view=rev
Log:
Generalize AAEval so that it can be used both per-function and
interprocedurally. Note that as of this writing, existing alias
analysis passes are not prepared to be used interprocedurally.

Modified:
    llvm/trunk/include/llvm/Analysis/Passes.h
    llvm/trunk/lib/Analysis/AliasAnalysisEvaluator.cpp

Modified: llvm/trunk/include/llvm/Analysis/Passes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/Passes.h?rev=107013&r1=107012&r2=107013&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/Passes.h (original)
+++ llvm/trunk/include/llvm/Analysis/Passes.h Mon Jun 28 11:01:37 2010
@@ -53,6 +53,13 @@
 
   //===--------------------------------------------------------------------===//
   //
+  // createInterproceduralAAEvalPass - This pass implements a simple
+  // N^2 interprocedural alias analysis accuracy evaluator.
+  //
+  Pass *createInterproceduralAAEvalPass();
+
+  //===--------------------------------------------------------------------===//
+  //
   // createNoAAPass - This pass implements a "I don't know" alias analysis.
   //
   ImmutablePass *createNoAAPass();

Modified: llvm/trunk/lib/Analysis/AliasAnalysisEvaluator.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasAnalysisEvaluator.cpp?rev=107013&r1=107012&r2=107013&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/AliasAnalysisEvaluator.cpp (original)
+++ llvm/trunk/lib/Analysis/AliasAnalysisEvaluator.cpp Mon Jun 28 11:01:37 2010
@@ -21,11 +21,11 @@
 #include "llvm/DerivedTypes.h"
 #include "llvm/Function.h"
 #include "llvm/Instructions.h"
+#include "llvm/Module.h"
 #include "llvm/Pass.h"
 #include "llvm/Analysis/Passes.h"
 #include "llvm/Analysis/AliasAnalysis.h"
 #include "llvm/Assembly/Writer.h"
-#include "llvm/Target/TargetData.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/InstIterator.h"
 #include "llvm/Support/CommandLine.h"
@@ -45,20 +45,21 @@
 static cl::opt<bool> PrintModRef("print-modref", cl::ReallyHidden);
 
 namespace {
-  class AAEval : public FunctionPass {
+  /// AAEval - Base class for exhaustive alias analysis evaluators.
+  class AAEval {
+  protected:
     unsigned NoAlias, MayAlias, MustAlias;
     unsigned NoModRef, Mod, Ref, ModRef;
 
-  public:
-    static char ID; // Pass identification, replacement for typeid
-    AAEval() : FunctionPass(&ID) {}
+    SetVector<Value *> Pointers;
+    SetVector<CallSite> CallSites;
 
-    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+    void getAnalysisUsage(AnalysisUsage &AU) const {
       AU.addRequired<AliasAnalysis>();
       AU.setPreservesAll();
     }
 
-    bool doInitialization(Module &M) {
+    void doInitialization(Module &M) {
       NoAlias = MayAlias = MustAlias = 0;
       NoModRef = Mod = Ref = ModRef = 0;
 
@@ -66,19 +67,85 @@
         PrintNoAlias = PrintMayAlias = PrintMustAlias = true;
         PrintNoModRef = PrintMod = PrintRef = PrintModRef = true;
       }
+    }
+
+    void runOnFunction(Function &F);
+    void evaluate(AliasAnalysis *AA, Module *M);
+    void doFinalization(Module &M);
+  };
+
+  class FunctionAAEval : public FunctionPass, AAEval {
+  public:
+    static char ID; // Pass identification, replacement for typeid
+    FunctionAAEval() : FunctionPass(&ID) {}
+
+    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+      return AAEval::getAnalysisUsage(AU);
+    }
+
+    virtual bool doInitialization(Module &M) {
+      AAEval::doInitialization(M);
+      return false;
+    }
+
+    virtual bool runOnFunction(Function &F) {
+      AAEval::runOnFunction(F);
+
+      if (PrintNoAlias || PrintMayAlias || PrintMustAlias ||
+          PrintNoModRef || PrintMod || PrintRef || PrintModRef)
+        errs() << "Function: " << F.getName() << ": " << Pointers.size()
+               << " pointers, " << CallSites.size() << " call sites\n";
+
+      AAEval::evaluate(&getAnalysis<AliasAnalysis>(), F.getParent());
+      return false;
+    }
+
+    virtual bool doFinalization(Module &M) {
+      AAEval::doFinalization(M);
       return false;
     }
+  };
+
+  class InterproceduralAAEval : public ModulePass, AAEval {
+  public:
+    static char ID; // Pass identification, replacement for typeid
+    InterproceduralAAEval() : ModulePass(&ID) {}
+
+    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+      return AAEval::getAnalysisUsage(AU);
+    }
+
+    virtual bool runOnModule(Module &M) {
+      AAEval::doInitialization(M);
+      for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I)
+        AAEval::runOnFunction(*I);
+
+      if (PrintNoAlias || PrintMayAlias || PrintMustAlias ||
+          PrintNoModRef || PrintMod || PrintRef || PrintModRef)
+        errs() << "Module: " << Pointers.size()
+               << " pointers, " << CallSites.size() << " call sites\n";
 
-    bool runOnFunction(Function &F);
-    bool doFinalization(Module &M);
+      AAEval::evaluate(&getAnalysis<AliasAnalysis>(), &M);
+      AAEval::doFinalization(M);
+      return false;
+    }
   };
 }
 
-char AAEval::ID = 0;
-static RegisterPass<AAEval>
+char FunctionAAEval::ID = 0;
+static RegisterPass<FunctionAAEval>
 X("aa-eval", "Exhaustive Alias Analysis Precision Evaluator", false, true);
 
-FunctionPass *llvm::createAAEvalPass() { return new AAEval(); }
+FunctionPass *llvm::createAAEvalPass() { return new FunctionAAEval(); }
+
+char InterproceduralAAEval::ID = 0;
+static RegisterPass<InterproceduralAAEval>
+Y("interprocedural-aa-eval",
+  "Exhaustive Interprocedural Alias Analysis Precision Evaluator", false, true);
+
+Pass *llvm::createInterproceduralAAEvalPass() {
+  return new InterproceduralAAEval();
+}
 
 static void PrintResults(const char *Msg, bool P, const Value *V1,
                          const Value *V2, const Module *M) {
@@ -113,12 +180,7 @@
       && !isa<ConstantPointerNull>(V);
 }
 
-bool AAEval::runOnFunction(Function &F) {
-  AliasAnalysis &AA = getAnalysis<AliasAnalysis>();
-
-  SetVector<Value *> Pointers;
-  SetVector<CallSite> CallSites;
-
+void AAEval::runOnFunction(Function &F) {
   for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I)
     if (I->getType()->isPointerTy())    // Add all pointer arguments.
       Pointers.insert(I);
@@ -148,33 +210,31 @@
 
     if (CS.getInstruction()) CallSites.insert(CS);
   }
+}
 
-  if (PrintNoAlias || PrintMayAlias || PrintMustAlias ||
-      PrintNoModRef || PrintMod || PrintRef || PrintModRef)
-    errs() << "Function: " << F.getName() << ": " << Pointers.size()
-           << " pointers, " << CallSites.size() << " call sites\n";
+void AAEval::evaluate(AliasAnalysis *AA, Module *M) {
 
   // iterate over the worklist, and run the full (n^2)/2 disambiguations
   for (SetVector<Value *>::iterator I1 = Pointers.begin(), E = Pointers.end();
        I1 != E; ++I1) {
     unsigned I1Size = ~0u;
     const Type *I1ElTy = cast<PointerType>((*I1)->getType())->getElementType();
-    if (I1ElTy->isSized()) I1Size = AA.getTypeStoreSize(I1ElTy);
+    if (I1ElTy->isSized()) I1Size = AA->getTypeStoreSize(I1ElTy);
 
     for (SetVector<Value *>::iterator I2 = Pointers.begin(); I2 != I1; ++I2) {
       unsigned I2Size = ~0u;
       const Type *I2ElTy =cast<PointerType>((*I2)->getType())->getElementType();
-      if (I2ElTy->isSized()) I2Size = AA.getTypeStoreSize(I2ElTy);
+      if (I2ElTy->isSized()) I2Size = AA->getTypeStoreSize(I2ElTy);
 
-      switch (AA.alias(*I1, I1Size, *I2, I2Size)) {
+      switch (AA->alias(*I1, I1Size, *I2, I2Size)) {
       case AliasAnalysis::NoAlias:
-        PrintResults("NoAlias", PrintNoAlias, *I1, *I2, F.getParent());
+        PrintResults("NoAlias", PrintNoAlias, *I1, *I2, M);
         ++NoAlias; break;
       case AliasAnalysis::MayAlias:
-        PrintResults("MayAlias", PrintMayAlias, *I1, *I2, F.getParent());
+        PrintResults("MayAlias", PrintMayAlias, *I1, *I2, M);
         ++MayAlias; break;
       case AliasAnalysis::MustAlias:
-        PrintResults("MustAlias", PrintMustAlias, *I1, *I2, F.getParent());
+        PrintResults("MustAlias", PrintMustAlias, *I1, *I2, M);
         ++MustAlias; break;
       default:
         errs() << "Unknown alias query result!\n";
@@ -191,20 +251,20 @@
          V != Ve; ++V) {
       unsigned Size = ~0u;
       const Type *ElTy = cast<PointerType>((*V)->getType())->getElementType();
-      if (ElTy->isSized()) Size = AA.getTypeStoreSize(ElTy);
+      if (ElTy->isSized()) Size = AA->getTypeStoreSize(ElTy);
 
-      switch (AA.getModRefInfo(*C, *V, Size)) {
+      switch (AA->getModRefInfo(*C, *V, Size)) {
       case AliasAnalysis::NoModRef:
-        PrintModRefResults("NoModRef", PrintNoModRef, I, *V, F.getParent());
+        PrintModRefResults("NoModRef", PrintNoModRef, I, *V, M);
         ++NoModRef; break;
       case AliasAnalysis::Mod:
-        PrintModRefResults("     Mod", PrintMod, I, *V, F.getParent());
+        PrintModRefResults("     Mod", PrintMod, I, *V, M);
         ++Mod; break;
       case AliasAnalysis::Ref:
-        PrintModRefResults("     Ref", PrintRef, I, *V, F.getParent());
+        PrintModRefResults("     Ref", PrintRef, I, *V, M);
         ++Ref; break;
       case AliasAnalysis::ModRef:
-        PrintModRefResults("  ModRef", PrintModRef, I, *V, F.getParent());
+        PrintModRefResults("  ModRef", PrintModRef, I, *V, M);
         ++ModRef; break;
       default:
         errs() << "Unknown alias query result!\n";
@@ -212,7 +272,8 @@
     }
   }
 
-  return false;
+  Pointers.clear();
+  CallSites.clear();
 }
 
 static void PrintPercent(unsigned Num, unsigned Sum) {
@@ -220,7 +281,7 @@
          << ((Num*1000ULL/Sum) % 10) << "%)\n";
 }
 
-bool AAEval::doFinalization(Module &M) {
+void AAEval::doFinalization(Module &M) {
   unsigned AliasSum = NoAlias + MayAlias + MustAlias;
   errs() << "===== Alias Analysis Evaluator Report =====\n";
   if (AliasSum == 0) {
@@ -256,6 +317,4 @@
            << NoModRef*100/ModRefSum  << "%/" << Mod*100/ModRefSum << "%/"
            << Ref*100/ModRefSum << "%/" << ModRef*100/ModRefSum << "%\n";
   }
-
-  return false;
 }




From ggreif at gmail.com  Mon Jun 28 11:40:52 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Mon, 28 Jun 2010 16:40:52 -0000
Subject: [llvm-commits] [llvm] r107014 -
	/llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp
Message-ID: <20100628164052.5B9BE2A6C12C@llvm.org>

Author: ggreif
Date: Mon Jun 28 11:40:52 2010
New Revision: 107014

URL: http://llvm.org/viewvc/llvm-project?rev=107014&view=rev
Log:
simplify: we have solid argument iterator range

Modified:
    llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp

Modified: llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp?rev=107014&r1=107013&r2=107014&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp (original)
+++ llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp Mon Jun 28 11:40:52 2010
@@ -383,24 +383,21 @@
            SI = SelsToConvert.begin(), SE = SelsToConvert.end();
          SI != SE; ++SI) {
       IntrinsicInst *II = *SI;
-      SmallVector<Value*, 8> Args;
 
       // Use the exception object pointer and the personality function
       // from the original selector.
       CallSite CS(II);
       IntrinsicInst::op_iterator I = CS.arg_begin();
-      Args.push_back(*I++); // Exception object pointer.
-      Args.push_back(*I++); // Personality function.
-
       IntrinsicInst::op_iterator E = CS.arg_end();
       IntrinsicInst::op_iterator B = prior(E);
 
       // Exclude last argument if it is an integer.
       if (isa<ConstantInt>(B)) E = B;
 
-      // Add in any filter IDs.
-      for (; I != E; ++I)
-        Args.push_back(*I);
+      // Add exception object pointer (front).
+      // Add personality function (next).
+      // Add in any filter IDs (rest).
+      SmallVector<Value*, 8> Args(I, E);
 
       Args.push_back(EHCatchAllValue->getInitializer()); // Catch-all indicator.
 




From ggreif at gmail.com  Mon Jun 28 11:43:57 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Mon, 28 Jun 2010 16:43:57 -0000
Subject: [llvm-commits] [llvm] r107015 -
	/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp
Message-ID: <20100628164357.F05ED2A6C12C@llvm.org>

Author: ggreif
Date: Mon Jun 28 11:43:57 2010
New Revision: 107015

URL: http://llvm.org/viewvc/llvm-project?rev=107015&view=rev
Log:
employ CallInst::ArgOffset (for now)

Modified:
    llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=107015&r1=107014&r2=107015&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Mon Jun 28 11:43:57 2010
@@ -969,7 +969,7 @@
       ConstantInt *Length = dyn_cast<ConstantInt>(MI->getLength());
       if (Length)
         isSafeMemAccess(AI, Offset, Length->getZExtValue(), 0,
-                        UI.getOperandNo() == 1, Info);
+                        UI.getOperandNo() == CallInst::ArgOffset, Info);
       else
         MarkUnsafe(Info);
     } else if (LoadInst *LI = dyn_cast<LoadInst>(User)) {
@@ -1799,7 +1799,7 @@
     if (isOffset) return false;
 
     // If the memintrinsic isn't using the alloca as the dest, reject it.
-    if (UI.getOperandNo() != 1) return false;
+    if (UI.getOperandNo() != CallInst::ArgOffset) return false;
     
     // If the source of the memcpy/move is not a constant global, reject it.
     if (!PointsToConstantGlobal(MI->getSource()))




From ggreif at gmail.com  Mon Jun 28 11:45:00 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Mon, 28 Jun 2010 16:45:00 -0000
Subject: [llvm-commits] [llvm] r107016 -
 /llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
Message-ID: <20100628164500.ED7612A6C12C@llvm.org>

Author: ggreif
Date: Mon Jun 28 11:45:00 2010
New Revision: 107016

URL: http://llvm.org/viewvc/llvm-project?rev=107016&view=rev
Log:
use ArgOperand API

Modified:
    llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp

Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp?rev=107016&r1=107015&r2=107016&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp Mon Jun 28 11:45:00 2010
@@ -1052,12 +1052,12 @@
     case Intrinsic::x86_sse2_mul_sd:
     case Intrinsic::x86_sse2_min_sd:
     case Intrinsic::x86_sse2_max_sd:
-      TmpV = SimplifyDemandedVectorElts(II->getOperand(1), DemandedElts,
+      TmpV = SimplifyDemandedVectorElts(II->getArgOperand(0), DemandedElts,
                                         UndefElts, Depth+1);
-      if (TmpV) { II->setOperand(1, TmpV); MadeChange = true; }
-      TmpV = SimplifyDemandedVectorElts(II->getOperand(2), DemandedElts,
+      if (TmpV) { II->setArgOperand(0, TmpV); MadeChange = true; }
+      TmpV = SimplifyDemandedVectorElts(II->getArgOperand(1), DemandedElts,
                                         UndefElts2, Depth+1);
-      if (TmpV) { II->setOperand(2, TmpV); MadeChange = true; }
+      if (TmpV) { II->setArgOperand(1, TmpV); MadeChange = true; }
 
       // If only the low elt is demanded and this is a scalarizable intrinsic,
       // scalarize it now.




From ggreif at gmail.com  Mon Jun 28 11:50:58 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Mon, 28 Jun 2010 16:50:58 -0000
Subject: [llvm-commits] [llvm] r107017 -
	/llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp
Message-ID: <20100628165058.1BC4C2A6C12C@llvm.org>

Author: ggreif
Date: Mon Jun 28 11:50:57 2010
New Revision: 107017

URL: http://llvm.org/viewvc/llvm-project?rev=107017&view=rev
Log:
use ArgOperand API

Modified:
    llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp

Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp?rev=107017&r1=107016&r2=107017&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp Mon Jun 28 11:50:57 2010
@@ -197,7 +197,7 @@
                       *MI);
 
   // Set the size of the copy to 0, it will be deleted on the next iteration.
-  MI->setOperand(3, Constant::getNullValue(MemOpLength->getType()));
+  MI->setArgOperand(2, Constant::getNullValue(MemOpLength->getType()));
   return MI;
 }
 
@@ -513,11 +513,11 @@
   // FALL THROUGH uadd into sadd
   case Intrinsic::sadd_with_overflow:
     // Canonicalize constants into the RHS.
-    if (isa<Constant>(II->getOperand(1)) &&
-        !isa<Constant>(II->getOperand(2))) {
-      Value *LHS = II->getOperand(1);
-      II->setOperand(1, II->getOperand(2));
-      II->setOperand(2, LHS);
+    if (isa<Constant>(II->getArgOperand(0)) &&
+        !isa<Constant>(II->getArgOperand(1))) {
+      Value *LHS = II->getArgOperand(0);
+      II->setArgOperand(0, II->getArgOperand(1));
+      II->setArgOperand(1, LHS);
       return II;
     }
 
@@ -560,11 +560,11 @@
   case Intrinsic::umul_with_overflow:
   case Intrinsic::smul_with_overflow:
     // Canonicalize constants into the RHS.
-    if (isa<Constant>(II->getOperand(1)) &&
-        !isa<Constant>(II->getOperand(2))) {
-      Value *LHS = II->getOperand(1);
-      II->setOperand(1, II->getOperand(2));
-      II->setOperand(2, LHS);
+    if (isa<Constant>(II->getArgOperand(0)) &&
+        !isa<Constant>(II->getArgOperand(1))) {
+      Value *LHS = II->getArgOperand(0);
+      II->setArgOperand(0, II->getArgOperand(1));
+      II->setArgOperand(1, LHS);
       return II;
     }
 
@@ -632,7 +632,7 @@
     APInt UndefElts(VWidth, 0);
     if (Value *V = SimplifyDemandedVectorElts(II->getArgOperand(0), DemandedElts,
                                               UndefElts)) {
-      II->setOperand(1, V);
+      II->setArgOperand(0, V);
       return II;
     }
     break;




From gkistanova at gmail.com  Mon Jun 28 11:35:58 2010
From: gkistanova at gmail.com (Galina Kistanova)
Date: Mon, 28 Jun 2010 09:35:58 -0700
Subject: [llvm-commits] Fwd: [zorg] r106933 -
	/zorg/trunk/buildbot/osuosl/master/config/status.py
In-Reply-To: <4C25A9B7.6060506@free.fr>
References: <20100626003739.319A82A6C12C@llvm.org> <4C25A9B7.6060506@free.fr>
Message-ID: <AANLkTilTzz7-G2l2Y5ZYPTc-FosopWwGEo7YP_tkeP_0@mail.gmail.com>

Hello Daniel,



Please do reconfig the buildbot when you have a minute if you are OK with
this change.



Thanks



Galina


Forwarded conversation
Subject: [llvm-commits] [zorg] r106933 -
/zorg/trunk/buildbot/osuosl/master/config/status.py
------------------------

From: *Galina Kistanova* <gkistanova at gmail.com>
Date: Fri, Jun 25, 2010 at 5:37 PM
To: llvm-commits at cs.uiuc.edu


Author: gkistanova
Date: Fri Jun 25 19:37:39 2010
New Revision: 106933

URL: http://llvm.org/viewvc/llvm-project?rev=106933&view=rev
Log:
Added e-mail notifier for dragonegg builders which sends the last 15 lines
of stdio

Modified:
   zorg/trunk/buildbot/osuosl/master/config/status.py

Modified: zorg/trunk/buildbot/osuosl/master/config/status.py
URL:
http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/status.py?rev=106933&r1=106932&r2=106933&view=diff
==============================================================================
--- zorg/trunk/buildbot/osuosl/master/config/status.py (original)
+++ zorg/trunk/buildbot/osuosl/master/config/status.py Fri Jun 25 19:37:39
2010
@@ -6,6 +6,7 @@

 import config
 from zorg.buildbot.util.ConfigEmailLookup import ConfigEmailLookup
+from zorg.buildbot.util.InformativeMailNotifier import
InformativeMailNotifier

 def get_status_targets(standard_builders):
    default_email = config.options.get('Master Options', 'default_email')
@@ -24,4 +25,13 @@
            host = "irc.oftc.net", nick = "llvmbb", channels = ["#llvm"],
            allowForce = True,
            notify_events = ['successToFailure', 'failureToSuccess']),
+        InformativeMailNotifier(
+            fromaddr = "buildbot at google1.osuosl.org",
+            sendToInterestedUsers= False,
+            extraRecipients = ["baldrick at free.fr", "gkistanova at gmail.com"],
+            subject="Build %(builder)s Failure",
+            mode = "failing",
+            builders = ["dragonegg-i386-linux", "dragonegg-x86_64-linux"],
+            addLogs=False,
+            num_lines = 15),

----------
From: *Duncan Sands* <baldrick at free.fr>
Date: Sat, Jun 26, 2010 at 12:18 AM
To: llvm-commits at cs.uiuc.edu


Thanks for doing this Galina, it should be much better than having to scroll
down 10000 lines of output to find what went wrong :)

Ciao,

Duncan.
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From criswell at uiuc.edu  Mon Jun 28 12:16:46 2010
From: criswell at uiuc.edu (John Criswell)
Date: Mon, 28 Jun 2010 17:16:46 -0000
Subject: [llvm-commits] [poolalloc] r107020 -
	/poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp
Message-ID: <20100628171646.1125C2A6C12C@llvm.org>

Author: criswell
Date: Mon Jun 28 12:16:45 2010
New Revision: 107020

URL: http://llvm.org/viewvc/llvm-project?rev=107020&view=rev
Log:
Fixed the code that repairs the function attributes of cloned functions to
work with LLVM 2.7.  This modifies the code to simply strip attributes off of
the new pool arguments.

Modified:
    poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp

Modified: poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp?rev=107020&r1=107019&r2=107020&view=diff
==============================================================================
--- poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp (original)
+++ poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp Mon Jun 28 12:16:45 2010
@@ -12,6 +12,8 @@
 //
 //===----------------------------------------------------------------------===//
 
+#include <iostream>
+
 #define DEBUG_TYPE "poolalloc"
 
 #include "dsa/DataStructure.h"
@@ -572,30 +574,19 @@
 
   //
   // The CloneFunctionInto() function will copy the parameter attributes
-  // verbatim.  This is incorrect; each attribute should be shifted one so
-  // that the pool descriptor has no attributes.
-  //
-  // FIXME: I believe the code below assumes that we've only added one pool
-  //        handle.  We actually add one pool handle per incoming argument
-  //        that needs a pool handle.
-  //
-  const AttrListPtr OldAttrs = New->getAttributes();
-  if (!OldAttrs.isEmpty()) {
-    AttrListPtr NewAttrsVector;
-    for (unsigned index = 0; index < OldAttrs.getNumSlots(); ++index) {
-      const AttributeWithIndex & PAWI = OldAttrs.getSlot(index);
-      unsigned argIndex = PAWI.Index;
-
-      // If it's not the return value, move the attribute to the next
-      // parameter.
-      if (argIndex) ++argIndex;
-
-      // Add the parameter to the new list.
-      NewAttrsVector.addAttr(argIndex, PAWI.Attrs);
+  // almost correctly.  However, it will set attributes incorrectly on the new
+  // pool descriptor arguments.  Go through and strip away the attributes on
+  // the pool descriptor arguments.
+  //
+  Function::ArgumentListType & ArgList = New->getArgumentList ();
+  Function::ArgumentListType::iterator arg = ArgList.begin();
+  for (; arg != ArgList.end(); ++arg) {
+    if (arg->getType() == PoolDescPtrTy) {
+      arg->removeAttr (Attribute::ByVal     |
+                       Attribute::Nest      |
+                       Attribute::StructRet |
+                       Attribute::NoCapture);
     }
-
-    // Assign the new attributes to the function clone
-    New->setAttributes (NewAttrsVector);
   }
 
   //




From dalej at apple.com  Mon Jun 28 12:31:54 2010
From: dalej at apple.com (Dale Johannesen)
Date: Mon, 28 Jun 2010 10:31:54 -0700
Subject: [llvm-commits] [llvm] r106792 - in /llvm/trunk:
	lib/CodeGen/AsmPrinter/DwarfDebug.cpp
	test/FrontendC/2010-06-24-DbgInlinedFnParameter.c
In-Reply-To: <32A5D2B9-79EF-469C-9EDD-785749310B65@apple.com>
References: <20100624215119.ED5B72A6C12C@llvm.org>
	<AANLkTin8uyctwFV9AORUTDfPMZiEIicZ4yhGjkF9Pb4b@mail.gmail.com>
	<32A5D2B9-79EF-469C-9EDD-785749310B65@apple.com>
Message-ID: <A0544094-F342-4660-9D3D-E95ADA915B34@apple.com>

This is still failing.  Is there a fix in sight?

On Jun 25, 2010, at 11:42 AMPDT, Devang Patel wrote:

> Is it possible for some to send me generated 2010-06-24- 
> DbgInlinedFnParameter.c.tmp.s ?
>
> Thanks,
> -
> Devang
> On Jun 25, 2010, at 7:21 AM, Daniel Dunbar wrote:
>
>> Hi Devang,
>>
>> This test is failing on a two-stage llvm-gcc bootstrap. See here:
>>  http://google1.osuosl.org:8011/builders/llvm-gcc-i686-darwin10-selfhost/builds/5139/steps/test.llvm.stage2/logs/2010-06-24-dbginlinedfnparameter.c
>>
>> - Daniel
>>
>> On Thu, Jun 24, 2010 at 2:51 PM, Devang Patel <dpatel at apple.com>  
>> wrote:
>>> Author: dpatel
>>> Date: Thu Jun 24 16:51:19 2010
>>> New Revision: 106792
>>>
>>> URL: http://llvm.org/viewvc/llvm-project?rev=106792&view=rev
>>> Log:
>>> DBG_VALUE machine instruction pointing to undefined register for a  
>>> variable justify a separate scope if the variable is inlined  
>>> function's argument.
>>> Radar 8122864.
>>>
>>> Added:
>>>    llvm/trunk/test/FrontendC/2010-06-24-DbgInlinedFnParameter.c
>>> Modified:
>>>    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
>>>
>>> Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=106792&r1=106791&r2=106792&view=diff
>>> = 
>>> = 
>>> = 
>>> = 
>>> = 
>>> = 
>>> = 
>>> = 
>>> = 
>>> = 
>>> ====================================================================
>>> --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
>>> +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Thu Jun 24  
>>> 16:51:19 2010
>>> @@ -2390,8 +2390,6 @@
>>>  static bool hasValidLocation(LLVMContext &Ctx,
>>>                              const MachineInstr *MInsn,
>>>                              const MDNode *&Scope, const MDNode  
>>> *&InlinedAt) {
>>> -  if (MInsn->isDebugValue())
>>> -    return false;
>>>   DebugLoc DL = MInsn->getDebugLoc();
>>>   if (DL.isUnknown()) return false;
>>>
>>> @@ -2655,7 +2653,6 @@
>>>         assert (MI->getNumOperands() > 1 && "Invalid machine  
>>> instruction!");
>>>         DIVariable DV(MI->getOperand(MI->getNumOperands() -  
>>> 1).getMetadata());
>>>         if (!DV.Verify()) continue;
>>> -        if (isDbgValueInUndefinedReg(MI)) continue;
>>>         // If DBG_VALUE is for a local variable then it needs a  
>>> label.
>>>         if (DV.getTag() != dwarf::DW_TAG_arg_variable)
>>>           InsnNeedsLabel.insert(MI);
>>> @@ -2663,7 +2660,7 @@
>>>         else if (!DISubprogram(DV.getContext()).describes(MF- 
>>> >getFunction()))
>>>           InsnNeedsLabel.insert(MI);
>>>         // DBG_VALUE indicating argument location change needs a  
>>> label.
>>> -        else if (!ProcessedArgs.insert(DV))
>>> +        else if (isDbgValueInUndefinedReg(MI) == false && ! 
>>> ProcessedArgs.insert(DV))
>>>           InsnNeedsLabel.insert(MI);
>>>       } else {
>>>         // If location is unknown then instruction needs a  
>>> location only if
>>>
>>> Added: llvm/trunk/test/FrontendC/2010-06-24-DbgInlinedFnParameter.c
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/2010-06-24-DbgInlinedFnParameter.c?rev=106792&view=auto
>>> = 
>>> = 
>>> = 
>>> = 
>>> = 
>>> = 
>>> = 
>>> = 
>>> = 
>>> = 
>>> ====================================================================
>>> --- llvm/trunk/test/FrontendC/2010-06-24-DbgInlinedFnParameter.c  
>>> (added)
>>> +++ llvm/trunk/test/FrontendC/2010-06-24-DbgInlinedFnParameter.c  
>>> Thu Jun 24 16:51:19 2010
>>> @@ -0,0 +1,15 @@
>>> +// RUN: %llvmgcc -S -O2 -g %s -o - | llc -O2 -o %t.s
>>> +// RUN: grep  "# DW_TAG_formal_parameter" %t.s | count 4
>>> +// Radar 8122864
>>> +static int foo(int a, int j) {
>>> +  int k = 0;
>>> +  if (a)
>>> +    k = a + j;
>>> +  else
>>> +    k = j;
>>> +  return k;
>>> +}
>>> +int bar(int o, int p) {
>>> +
>>> +  return foo(o, p);
>>> +}
>>>
>>>
>>> _______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

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From echristo at apple.com  Mon Jun 28 12:38:54 2010
From: echristo at apple.com (Eric Christopher)
Date: Mon, 28 Jun 2010 10:38:54 -0700
Subject: [llvm-commits] [llvm] r106792 - in /llvm/trunk:
	lib/CodeGen/AsmPrinter/DwarfDebug.cpp
	test/FrontendC/2010-06-24-DbgInlinedFnParameter.c
In-Reply-To: <32A5D2B9-79EF-469C-9EDD-785749310B65@apple.com>
References: <20100624215119.ED5B72A6C12C@llvm.org>
	<AANLkTin8uyctwFV9AORUTDfPMZiEIicZ4yhGjkF9Pb4b@mail.gmail.com>
	<32A5D2B9-79EF-469C-9EDD-785749310B65@apple.com>
Message-ID: <A31EC509-D57B-4005-91C6-91BF57F20E3C@apple.com>


On Jun 25, 2010, at 11:42 AM, Devang Patel wrote:

> Is it possible for some to send me generated 2010-06-24-DbgInlinedFnParameter.c.tmp.s ?

don't know if anyone ever did, but here.

-eric

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From dpatel at apple.com  Mon Jun 28 13:04:03 2010
From: dpatel at apple.com (Devang Patel)
Date: Mon, 28 Jun 2010 11:04:03 -0700
Subject: [llvm-commits] [llvm] r106792 - in /llvm/trunk:
	lib/CodeGen/AsmPrinter/DwarfDebug.cpp
	test/FrontendC/2010-06-24-DbgInlinedFnParameter.c
In-Reply-To: <A31EC509-D57B-4005-91C6-91BF57F20E3C@apple.com>
References: <20100624215119.ED5B72A6C12C@llvm.org>
	<AANLkTin8uyctwFV9AORUTDfPMZiEIicZ4yhGjkF9Pb4b@mail.gmail.com>
	<32A5D2B9-79EF-469C-9EDD-785749310B65@apple.com>
	<A31EC509-D57B-4005-91C6-91BF57F20E3C@apple.com>
Message-ID: <FE240E93-16BD-48F7-8AD1-2083D15A768D@apple.com>


On Jun 28, 2010, at 10:38 AM, Eric Christopher wrote:

> 
> On Jun 25, 2010, at 11:42 AM, Devang Patel wrote:
> 
>> Is it possible for some to send me generated 2010-06-24-DbgInlinedFnParameter.c.tmp.s ?
> 
> don't know if anyone ever did, but here.


Thanks Eric!

I do see that one of the formal parameter's debug info is dropped for function foo here. Nothing comes to m ind immediately why this is happening on this target. Meanwhile, I'll make this test darwin specific.
-
Devang


> -eric
> 
> <foo.s>




From dpatel at apple.com  Mon Jun 28 13:04:03 2010
From: dpatel at apple.com (Devang Patel)
Date: Mon, 28 Jun 2010 18:04:03 -0000
Subject: [llvm-commits] [llvm] r107025 -
 /llvm/trunk/test/FrontendC/2010-06-24-DbgInlinedFnParameter.c
Message-ID: <20100628180403.EE84C2A6C12C@llvm.org>

Author: dpatel
Date: Mon Jun 28 13:04:03 2010
New Revision: 107025

URL: http://llvm.org/viewvc/llvm-project?rev=107025&view=rev
Log:
Make this test darwin specific.

Modified:
    llvm/trunk/test/FrontendC/2010-06-24-DbgInlinedFnParameter.c

Modified: llvm/trunk/test/FrontendC/2010-06-24-DbgInlinedFnParameter.c
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/2010-06-24-DbgInlinedFnParameter.c?rev=107025&r1=107024&r2=107025&view=diff
==============================================================================
--- llvm/trunk/test/FrontendC/2010-06-24-DbgInlinedFnParameter.c (original)
+++ llvm/trunk/test/FrontendC/2010-06-24-DbgInlinedFnParameter.c Mon Jun 28 13:04:03 2010
@@ -1,7 +1,7 @@
 // RUN: %llvmgcc -S -O2 -g %s -o - | llc -O2 -o %t.s
 // RUN: grep  "# DW_TAG_formal_parameter" %t.s | count 4
 // Radar 8122864
-// XFAIL: powerpc
+// XTARGET: x86,darwin
 static int foo(int a, int j) {
   int k = 0;
   if (a)




From criswell at uiuc.edu  Mon Jun 28 13:11:17 2010
From: criswell at uiuc.edu (John Criswell)
Date: Mon, 28 Jun 2010 18:11:17 -0000
Subject: [llvm-commits] [poolalloc] r107026 -
	/poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp
Message-ID: <20100628181117.F06742A6C12C@llvm.org>

Author: criswell
Date: Mon Jun 28 13:11:17 2010
New Revision: 107026

URL: http://llvm.org/viewvc/llvm-project?rev=107026&view=rev
Log:
Fix copying of parameter attributes properly; don't trust the copyAttributes()
method.

Modified:
    poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp

Modified: poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp?rev=107026&r1=107025&r2=107026&view=diff
==============================================================================
--- poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp (original)
+++ poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp Mon Jun 28 13:11:17 2010
@@ -573,29 +573,46 @@
   CloneFunctionInto(New, &F, ValueMap, Returns);
 
   //
-  // The CloneFunctionInto() function will copy the parameter attributes
-  // almost correctly.  However, it will set attributes incorrectly on the new
-  // pool descriptor arguments.  Go through and strip away the attributes on
-  // the pool descriptor arguments.
+  // Invert the ValueMap into the NewToOldValueMap.
+  //
+  std::map<Value*, const Value*> &NewToOldValueMap = FI.NewToOldValueMap;
+  for (DenseMap<const Value*, Value*>::iterator I = ValueMap.begin(),
+         E = ValueMap.end(); I != E; ++I)
+    NewToOldValueMap.insert(std::make_pair(I->second, I->first));
+
+  //
+  // The cloned function will have its function attributes set more or less
+  // correctly at this point.  However, it will not have its parameter
+  // attributes set correctly.  We need to go through each argument in the
+  // old function and copy the parameter attributes over correctly.
+  //
+
+  //
+  // Begin by clearing out all function parameter attributes.
   //
   Function::ArgumentListType & ArgList = New->getArgumentList ();
   Function::ArgumentListType::iterator arg = ArgList.begin();
   for (; arg != ArgList.end(); ++arg) {
-    if (arg->getType() == PoolDescPtrTy) {
-      arg->removeAttr (Attribute::ByVal     |
-                       Attribute::Nest      |
-                       Attribute::StructRet |
-                       Attribute::NoCapture);
-    }
+    arg->removeAttr (Attribute::ParameterOnly);
+    arg->removeAttr (Attribute::NoAlias);
   }
 
   //
-  // Invert the ValueMap into the NewToOldValueMap.
+  // Copy over the attributes from the old parameters to the new parameters.
   //
-  std::map<Value*, const Value*> &NewToOldValueMap = FI.NewToOldValueMap;
-  for (DenseMap<const Value*, Value*>::iterator I = ValueMap.begin(),
-         E = ValueMap.end(); I != E; ++I)
-    NewToOldValueMap.insert(std::make_pair(I->second, I->first));
+  Function::ArgumentListType & OldArgList = F.getArgumentList ();
+  arg = OldArgList.begin();
+  for (; arg != OldArgList.end(); ++arg) {
+    Argument * newArg = dyn_cast<Argument>(ValueMap[arg]);
+    assert (newArg && "Value Map for arguments incorrect!\n");
+
+    if (arg->hasByValAttr ())     newArg->addAttr (Attribute::ByVal);
+    if (arg->hasNestAttr ())      newArg->addAttr (Attribute::Nest);
+    if (arg->hasNoAliasAttr ())   newArg->addAttr (Attribute::NoAlias); 
+    if (arg->hasNoCaptureAttr ()) newArg->addAttr (Attribute::NoCapture); 
+    if (arg->hasStructRetAttr ()) newArg->addAttr (Attribute::StructRet); 
+  }
+
   return FI.Clone = New;
 }
 




From dpatel at apple.com  Mon Jun 28 13:25:03 2010
From: dpatel at apple.com (Devang Patel)
Date: Mon, 28 Jun 2010 18:25:03 -0000
Subject: [llvm-commits] [llvm] r107027 - in /llvm/trunk:
 lib/CodeGen/AsmPrinter/DwarfDebug.cpp lib/CodeGen/AsmPrinter/DwarfDebug.h
 test/FrontendC/2010-06-28-DbgLocalVar.c
Message-ID: <20100628182503.718AC2A6C12C@llvm.org>

Author: dpatel
Date: Mon Jun 28 13:25:03 2010
New Revision: 107027

URL: http://llvm.org/viewvc/llvm-project?rev=107027&view=rev
Log:
Preserve deleted function's local variables' debug info.
Radar 8122864.

Added:
    llvm/trunk/test/FrontendC/2010-06-28-DbgLocalVar.c
Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=107027&r1=107026&r2=107027&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Mon Jun 28 13:25:03 2010
@@ -1386,6 +1386,7 @@
 /// If there are global variables in this scope then create and insert
 /// DIEs for these variables.
 DIE *DwarfDebug::updateSubprogramScopeDIE(const MDNode *SPNode) {
+  ProcessedSPNodes.insert(SPNode);
   CompileUnit *SPCU = getCompileUnit(SPNode);
   DIE *SPDie = SPCU->getDIE(SPNode);
   assert(SPDie && "Unable to find subprogram DIE!");
@@ -2005,6 +2006,40 @@
 ///
 void DwarfDebug::endModule() {
   if (!FirstCU) return;
+  const Module *M = MMI->getModule();
+  if (NamedMDNode *AllSPs = M->getNamedMetadata("llvm.dbg.sp")) {
+    for (unsigned SI = 0, SE = AllSPs->getNumOperands(); SI != SE; ++SI) {
+      if (ProcessedSPNodes.count(AllSPs->getOperand(SI)) != 0) continue;
+      DISubprogram SP(AllSPs->getOperand(SI));
+      if (!SP.Verify()) continue;
+
+      // Collect info for variables that were optimized out.
+      StringRef FName = SP.getLinkageName();
+      if (FName.empty())
+        FName = SP.getName();
+      NamedMDNode *NMD = 
+        M->getNamedMetadata(Twine("llvm.dbg.lv.", getRealLinkageName(FName)));
+      if (!NMD) continue;
+      unsigned E = NMD->getNumOperands();
+      if (!E) continue;
+      DbgScope *Scope = new DbgScope(NULL, DIDescriptor(SP), NULL);
+      for (unsigned I = 0; I != E; ++I) {
+        DIVariable DV(NMD->getOperand(I));
+        if (!DV.Verify()) continue;
+        Scope->addVariable(new DbgVariable(DV));
+      }
+      
+      // Construct subprogram DIE and add variables DIEs.
+      constructSubprogramDIE(SP);
+      DIE *ScopeDIE = getCompileUnit(SP)->getDIE(SP);
+      const SmallVector<DbgVariable *, 8> &Variables = Scope->getVariables();
+      for (unsigned i = 0, N = Variables.size(); i < N; ++i) {
+        DIE *VariableDIE = constructVariableDIE(Variables[i], Scope);
+        if (VariableDIE)
+          ScopeDIE->addChild(VariableDIE);
+      }
+    }
+  }
 
   // Attach DW_AT_inline attribute with inlined subprogram DIEs.
   for (SmallPtrSet<DIE *, 4>::iterator AI = InlinedSubprogramDIEs.begin(),

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h?rev=107027&r1=107026&r2=107027&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Mon Jun 28 13:25:03 2010
@@ -219,6 +219,10 @@
   DenseMap<const MDNode *, SmallVector<InlineInfoLabels, 4> > InlineInfo;
   SmallVector<const MDNode *, 4> InlinedSPNodes;
 
+  // ProcessedSPNodes - This is a collection of subprogram MDNodes that
+  // are processed to create DIEs.
+  SmallPtrSet<const MDNode *, 16> ProcessedSPNodes;
+
   /// LabelsBeforeInsn - Maps instruction with label emitted before 
   /// instruction.
   DenseMap<const MachineInstr *, MCSymbol *> LabelsBeforeInsn;

Added: llvm/trunk/test/FrontendC/2010-06-28-DbgLocalVar.c
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/2010-06-28-DbgLocalVar.c?rev=107027&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC/2010-06-28-DbgLocalVar.c (added)
+++ llvm/trunk/test/FrontendC/2010-06-28-DbgLocalVar.c Mon Jun 28 13:25:03 2010
@@ -0,0 +1,14 @@
+// RUN: %llvmgcc -S -O2 -g %s -o - | llc -O2 -o %t.s 
+// RUN: grep DW_TAG_structure_type %t.s | count 2
+// Radar 8122864
+
+// Code is not generated for function foo, but preserve type information of
+// local variable xyz.
+static foo() {
+  struct X { int a; int b; } xyz;
+}
+
+int bar() {
+  foo();
+  return 1;
+}




From echristo at apple.com  Mon Jun 28 13:25:51 2010
From: echristo at apple.com (Eric Christopher)
Date: Mon, 28 Jun 2010 18:25:51 -0000
Subject: [llvm-commits] [llvm] r107028 - in /llvm/trunk:
 autoconf/configure.ac configure include/llvm/Config/config.h.in
 lib/Support/PrettyStackTrace.cpp
Message-ID: <20100628182551.C6C952A6C12C@llvm.org>

Author: echristo
Date: Mon Jun 28 13:25:51 2010
New Revision: 107028

URL: http://llvm.org/viewvc/llvm-project?rev=107028&view=rev
Log:
Pull in the libCrashReporterClient.a information with a warning comment.

Remove library check and regenerate configure.

Modified:
    llvm/trunk/autoconf/configure.ac
    llvm/trunk/configure
    llvm/trunk/include/llvm/Config/config.h.in
    llvm/trunk/lib/Support/PrettyStackTrace.cpp

Modified: llvm/trunk/autoconf/configure.ac
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=107028&r1=107027&r2=107028&view=diff
==============================================================================
--- llvm/trunk/autoconf/configure.ac (original)
+++ llvm/trunk/autoconf/configure.ac Mon Jun 28 13:25:51 2010
@@ -1248,10 +1248,6 @@
 AC_DEFINE_UNQUOTED([USE_OPROFILE],$USE_OPROFILE,
                    [Define if we have the oprofile JIT-support library])
 
-dnl gCRAnnotations isn't the function we care about, but it's the only
-dnl thing exported.
-AC_CHECK_LIB(CrashReporterClient, gCRAnnotations)
-
 dnl===-----------------------------------------------------------------------===
 dnl===
 dnl=== SECTION 6: Check for header files

Modified: llvm/trunk/configure
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=107028&r1=107027&r2=107028&view=diff
==============================================================================
--- llvm/trunk/configure (original)
+++ llvm/trunk/configure Mon Jun 28 13:25:51 2010
@@ -14775,94 +14775,6 @@
 
 
 
-{ echo "$as_me:$LINENO: checking for gCRAnnotations in -lCrashReporterClient" >&5
-echo $ECHO_N "checking for gCRAnnotations in -lCrashReporterClient... $ECHO_C" >&6; }
-if test "${ac_cv_lib_CrashReporterClient_gCRAnnotations+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  ac_check_lib_save_LIBS=$LIBS
-LIBS="-lCrashReporterClient  $LIBS"
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-
-/* Override any GCC internal prototype to avoid an error.
-   Use char because int might match the return type of a GCC
-   builtin and then its argument prototype would still apply.  */
-#ifdef __cplusplus
-extern "C"
-#endif
-char gCRAnnotations ();
-int
-main ()
-{
-return gCRAnnotations ();
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (ac_try="$ac_link"
-case "(($ac_try" in
-  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
-  *) ac_try_echo=$ac_try;;
-esac
-eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5
-  (eval "$ac_link") 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag" || test ! -s conftest.err'
-  { (case "(($ac_try" in
-  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
-  *) ac_try_echo=$ac_try;;
-esac
-eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5
-  (eval "$ac_try") 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (case "(($ac_try" in
-  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
-  *) ac_try_echo=$ac_try;;
-esac
-eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5
-  (eval "$ac_try") 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_lib_CrashReporterClient_gCRAnnotations=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-	ac_cv_lib_CrashReporterClient_gCRAnnotations=no
-fi
-
-rm -f core conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-LIBS=$ac_check_lib_save_LIBS
-fi
-{ echo "$as_me:$LINENO: result: $ac_cv_lib_CrashReporterClient_gCRAnnotations" >&5
-echo "${ECHO_T}$ac_cv_lib_CrashReporterClient_gCRAnnotations" >&6; }
-if test $ac_cv_lib_CrashReporterClient_gCRAnnotations = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define HAVE_LIBCRASHREPORTERCLIENT 1
-_ACEOF
-
-  LIBS="-lCrashReporterClient $LIBS"
-
-fi
-
-
-
 
 
 

Modified: llvm/trunk/include/llvm/Config/config.h.in
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Config/config.h.in?rev=107028&r1=107027&r2=107028&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Config/config.h.in (original)
+++ llvm/trunk/include/llvm/Config/config.h.in Mon Jun 28 13:25:51 2010
@@ -178,10 +178,6 @@
 /* Set to 1 if the isnan function is found in <math.h> */
 #undef HAVE_ISNAN_IN_MATH_H
 
-/* Define to 1 if you have the `CrashReporterClient' library
-   (-lCrashReporterClient). */
-#undef HAVE_LIBCRASHREPORTERCLIENT
-
 /* Define if you have the libdl library or equivalent. */
 #undef HAVE_LIBDL
 

Modified: llvm/trunk/lib/Support/PrettyStackTrace.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/PrettyStackTrace.cpp?rev=107028&r1=107027&r2=107028&view=diff
==============================================================================
--- llvm/trunk/lib/Support/PrettyStackTrace.cpp (original)
+++ llvm/trunk/lib/Support/PrettyStackTrace.cpp Mon Jun 28 13:25:51 2010
@@ -54,8 +54,15 @@
   OS.flush();
 }
 
-// Integrate with crash reporter.
-#if defined (__APPLE__) && !defined (HAVE_CRASHREPORTERCLIENT_H)
+// Integrate with crash reporter libraries.
+#if defined (__APPLE__) && defined (HAVE_CRASHREPORTERCLIENT_H)
+//  If any clients of llvm try to link to libCrashReporterClient.a themselves,
+//  only one crash info struct will be used.
+CRASH_REPORTER_CLIENT_HIDDEN 
+struct crashreporter_annotations_t gCRAnnotations 
+        __attribute__((section("__DATA," CRASHREPORTER_ANNOTATIONS_SECTION))) 
+        = { CRASHREPORTER_ANNOTATIONS_VERSION, 0, 0, 0 };
+#else if defined (__APPLE__)
 static const char *__crashreporter_info__ = 0;
 asm(".desc ___crashreporter_info__, 0x10");
 #endif




From echristo at apple.com  Mon Jun 28 13:26:13 2010
From: echristo at apple.com (Eric Christopher)
Date: Mon, 28 Jun 2010 18:26:13 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r107033 - in /llvm-gcc-4.2/trunk/gcc:
	configure configure.ac
Message-ID: <20100628182613.ED52B2A6C12D@llvm.org>

Author: echristo
Date: Mon Jun 28 13:26:13 2010
New Revision: 107033

URL: http://llvm.org/viewvc/llvm-project?rev=107033&view=rev
Log:
Remove libCrashReporterClient.a check, regenerate configure.

Modified:
    llvm-gcc-4.2/trunk/gcc/configure
    llvm-gcc-4.2/trunk/gcc/configure.ac

Modified: llvm-gcc-4.2/trunk/gcc/configure
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/configure?rev=107033&r1=107032&r2=107033&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/configure (original)
+++ llvm-gcc-4.2/trunk/gcc/configure Mon Jun 28 13:26:13 2010
@@ -14810,99 +14810,6 @@
     ;;
 esac
 
-# Check if we have a particular darwin crash reporter library.
-case ${host} in
-  *-*-darwin*)
-
-{ echo "$as_me:$LINENO: checking for gCRAnnotations in -lCrashReporterClient" >&5
-echo $ECHO_N "checking for gCRAnnotations in -lCrashReporterClient... $ECHO_C" >&6; }
-if test "${ac_cv_lib_CrashReporterClient_gCRAnnotations+set}" = set; then
-  echo $ECHO_N "(cached) $ECHO_C" >&6
-else
-  ac_check_lib_save_LIBS=$LIBS
-LIBS="-lCrashReporterClient  $LIBS"
-cat >conftest.$ac_ext <<_ACEOF
-/* confdefs.h.  */
-_ACEOF
-cat confdefs.h >>conftest.$ac_ext
-cat >>conftest.$ac_ext <<_ACEOF
-/* end confdefs.h.  */
-
-/* Override any GCC internal prototype to avoid an error.
-   Use char because int might match the return type of a GCC
-   builtin and then its argument prototype would still apply.  */
-#ifdef __cplusplus
-extern "C"
-#endif
-char gCRAnnotations ();
-int
-main ()
-{
-return gCRAnnotations ();
-  ;
-  return 0;
-}
-_ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (ac_try="$ac_link"
-case "(($ac_try" in
-  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
-  *) ac_try_echo=$ac_try;;
-esac
-eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5
-  (eval "$ac_link") 2>conftest.er1
-  ac_status=$?
-  grep -v '^ *+' conftest.er1 >conftest.err
-  rm -f conftest.er1
-  cat conftest.err >&5
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag" || test ! -s conftest.err'
-  { (case "(($ac_try" in
-  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
-  *) ac_try_echo=$ac_try;;
-esac
-eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5
-  (eval "$ac_try") 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
-  { (case "(($ac_try" in
-  *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;;
-  *) ac_try_echo=$ac_try;;
-esac
-eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5
-  (eval "$ac_try") 2>&5
-  ac_status=$?
-  echo "$as_me:$LINENO: \$? = $ac_status" >&5
-  (exit $ac_status); }; }; then
-  ac_cv_lib_CrashReporterClient_gCRAnnotations=yes
-else
-  echo "$as_me: failed program was:" >&5
-sed 's/^/| /' conftest.$ac_ext >&5
-
-	ac_cv_lib_CrashReporterClient_gCRAnnotations=no
-fi
-
-rm -f core conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
-LIBS=$ac_check_lib_save_LIBS
-fi
-{ echo "$as_me:$LINENO: result: $ac_cv_lib_CrashReporterClient_gCRAnnotations" >&5
-echo "${ECHO_T}$ac_cv_lib_CrashReporterClient_gCRAnnotations" >&6; }
-if test $ac_cv_lib_CrashReporterClient_gCRAnnotations = yes; then
-  cat >>confdefs.h <<_ACEOF
-#define HAVE_LIBCRASHREPORTERCLIENT 1
-_ACEOF
-
-  LIBS="-lCrashReporterClient $LIBS"
-
-fi
-
-    ;;
-esac
-
 # ---------
 # Threading
 # ---------

Modified: llvm-gcc-4.2/trunk/gcc/configure.ac
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/configure.ac?rev=107033&r1=107032&r2=107033&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/configure.ac (original)
+++ llvm-gcc-4.2/trunk/gcc/configure.ac Mon Jun 28 13:26:13 2010
@@ -1466,13 +1466,6 @@
     ;;
 esac
 
-# Check if we have a particular darwin crash reporter library.
-case ${host} in
-  *-*-darwin*)
-    AC_CHECK_LIB(CrashReporterClient, gCRAnnotations)
-    ;;
-esac
-
 # ---------
 # Threading
 # ---------




From echristo at apple.com  Mon Jun 28 13:33:48 2010
From: echristo at apple.com (Eric Christopher)
Date: Mon, 28 Jun 2010 18:33:48 -0000
Subject: [llvm-commits] [llvm] r107042 -
	/llvm/trunk/lib/Support/PrettyStackTrace.cpp
Message-ID: <20100628183348.C85562A6C12C@llvm.org>

Author: echristo
Date: Mon Jun 28 13:33:48 2010
New Revision: 107042

URL: http://llvm.org/viewvc/llvm-project?rev=107042&view=rev
Log:
Fix thinko.

Modified:
    llvm/trunk/lib/Support/PrettyStackTrace.cpp

Modified: llvm/trunk/lib/Support/PrettyStackTrace.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/PrettyStackTrace.cpp?rev=107042&r1=107041&r2=107042&view=diff
==============================================================================
--- llvm/trunk/lib/Support/PrettyStackTrace.cpp (original)
+++ llvm/trunk/lib/Support/PrettyStackTrace.cpp Mon Jun 28 13:33:48 2010
@@ -58,11 +58,13 @@
 #if defined (__APPLE__) && defined (HAVE_CRASHREPORTERCLIENT_H)
 //  If any clients of llvm try to link to libCrashReporterClient.a themselves,
 //  only one crash info struct will be used.
+extern "C" {
 CRASH_REPORTER_CLIENT_HIDDEN 
 struct crashreporter_annotations_t gCRAnnotations 
         __attribute__((section("__DATA," CRASHREPORTER_ANNOTATIONS_SECTION))) 
-        = { CRASHREPORTER_ANNOTATIONS_VERSION, 0, 0, 0 };
-#else if defined (__APPLE__)
+        = { CRASHREPORTER_ANNOTATIONS_VERSION, 0, 0, 0, 0 };
+}
+#elif defined (__APPLE__)
 static const char *__crashreporter_info__ = 0;
 asm(".desc ___crashreporter_info__, 0x10");
 #endif




From stoklund at 2pi.dk  Mon Jun 28 13:34:34 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Mon, 28 Jun 2010 18:34:34 -0000
Subject: [llvm-commits] [llvm] r107043 - in /llvm/trunk:
 lib/CodeGen/RegAllocFast.cpp test/CodeGen/X86/2008-09-18-inline-asm-2.ll
 test/CodeGen/X86/2010-06-28-FastAllocTiedOperand.ll
Message-ID: <20100628183434.D05DF2A6C12C@llvm.org>

Author: stoklund
Date: Mon Jun 28 13:34:34 2010
New Revision: 107043

URL: http://llvm.org/viewvc/llvm-project?rev=107043&view=rev
Log:
Add more special treatment for inline asm in RegAllocFast.

When an instruction has tied operands and physreg defines, we must take extra
care that the tied operands conflict with neither physreg defs nor uses.

The special treatment is given to inline asm and instructions with tied operands
/ early clobbers and physreg defines.

This fixes PR7509.

Added:
    llvm/trunk/test/CodeGen/X86/2010-06-28-FastAllocTiedOperand.ll
Modified:
    llvm/trunk/lib/CodeGen/RegAllocFast.cpp
    llvm/trunk/test/CodeGen/X86/2008-09-18-inline-asm-2.ll

Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=107043&r1=107042&r2=107043&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocFast.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp Mon Jun 28 13:34:34 2010
@@ -140,6 +140,8 @@
   private:
     bool runOnMachineFunction(MachineFunction &Fn);
     void AllocateBasicBlock();
+    void handleThroughOperands(MachineInstr *MI,
+                               SmallVectorImpl<unsigned> &VirtDead);
     int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
     bool isLastUseOfLocalReg(MachineOperand&);
 
@@ -612,6 +614,77 @@
   return MO.isDead();
 }
 
+// Handle special instruction operand like early clobbers and tied ops when
+// there are additional physreg defines.
+void RAFast::handleThroughOperands(MachineInstr *MI,
+                                   SmallVectorImpl<unsigned> &VirtDead) {
+  DEBUG(dbgs() << "Scanning for through registers:");
+  SmallSet<unsigned, 8> ThroughRegs;
+  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+    MachineOperand &MO = MI->getOperand(i);
+    if (!MO.isReg()) continue;
+    unsigned Reg = MO.getReg();
+    if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
+    if (MO.isEarlyClobber() || MI->isRegTiedToDefOperand(i)) {
+      if (ThroughRegs.insert(Reg))
+        DEBUG(dbgs() << " %reg" << Reg);
+    }
+  }
+
+  // If any physreg defines collide with preallocated through registers,
+  // we must spill and reallocate.
+  DEBUG(dbgs() << "\nChecking for physdef collisions.\n");
+  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+    MachineOperand &MO = MI->getOperand(i);
+    if (!MO.isReg() || !MO.isDef()) continue;
+    unsigned Reg = MO.getReg();
+    if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
+    UsedInInstr.set(Reg);
+    if (ThroughRegs.count(PhysRegState[Reg]))
+      definePhysReg(MI, Reg, regFree);
+    for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) {
+      UsedInInstr.set(*AS);
+      if (ThroughRegs.count(PhysRegState[*AS]))
+        definePhysReg(MI, *AS, regFree);
+    }
+  }
+
+  DEBUG(dbgs() << "Allocating tied uses and early clobbers.\n");
+  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+    MachineOperand &MO = MI->getOperand(i);
+    if (!MO.isReg()) continue;
+    unsigned Reg = MO.getReg();
+    if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
+    if (MO.isUse()) {
+      unsigned DefIdx = 0;
+      if (!MI->isRegTiedToDefOperand(i, &DefIdx)) continue;
+      DEBUG(dbgs() << "Operand " << i << "("<< MO << ") is tied to operand "
+        << DefIdx << ".\n");
+      LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, 0);
+      unsigned PhysReg = LRI->second.PhysReg;
+      setPhysReg(MI, i, PhysReg);
+    } else if (MO.isEarlyClobber()) {
+      // Note: defineVirtReg may invalidate MO.
+      LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, 0);
+      unsigned PhysReg = LRI->second.PhysReg;
+      if (setPhysReg(MI, i, PhysReg))
+        VirtDead.push_back(Reg);
+    }
+  }
+
+  // Restore UsedInInstr to a state usable for allocating normal virtual uses.
+  UsedInInstr.reset();
+  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+    MachineOperand &MO = MI->getOperand(i);
+    if (!MO.isReg() || (MO.isDef() && !MO.isEarlyClobber())) continue;
+    unsigned Reg = MO.getReg();
+    if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
+    UsedInInstr.set(Reg);
+    for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
+      UsedInInstr.set(*AS);
+  }
+}
+
 void RAFast::AllocateBasicBlock() {
   DEBUG(dbgs() << "\nAllocating " << *MBB);
 
@@ -625,7 +698,7 @@
          E = MBB->livein_end(); I != E; ++I)
     definePhysReg(MII, *I, regReserved);
 
-  SmallVector<unsigned, 8> PhysECs, VirtDead;
+  SmallVector<unsigned, 8> VirtDead;
   SmallVector<MachineInstr*, 32> Coalesced;
 
   // Otherwise, sequentially allocate each instruction in the MBB.
@@ -689,12 +762,12 @@
 
     // Track registers used by instruction.
     UsedInInstr.reset();
-    PhysECs.clear();
 
     // First scan.
     // Mark physreg uses and early clobbers as used.
     // Find the end of the virtreg operands
     unsigned VirtOpEnd = 0;
+    bool hasTiedOps = false, hasEarlyClobbers = false, hasPhysDefs = false;
     for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
       MachineOperand &MO = MI->getOperand(i);
       if (!MO.isReg()) continue;
@@ -702,6 +775,11 @@
       if (!Reg) continue;
       if (TargetRegisterInfo::isVirtualRegister(Reg)) {
         VirtOpEnd = i+1;
+        if (MO.isUse())
+          hasTiedOps = hasTiedOps ||
+                                TID.getOperandConstraint(i, TOI::TIED_TO) != -1;
+        else if (MO.isEarlyClobber())
+          hasEarlyClobbers = true;
         continue;
       }
       if (!Allocatable.test(Reg)) continue;
@@ -710,13 +788,26 @@
       } else if (MO.isEarlyClobber()) {
         definePhysReg(MI, Reg, (MO.isImplicit() || MO.isDead()) ?
                                regFree : regReserved);
-        PhysECs.push_back(Reg);
-      }
+        hasEarlyClobbers = true;
+      } else
+        hasPhysDefs = true;
+    }
+
+    // The instruction may have virtual register operands that must be allocated
+    // the same register at use-time and def-time: early clobbers and tied
+    // operands. If there are also physical defs, these registers must avoid
+    // both physical defs and uses, making them more constrained than normal
+    // operands.
+    // We didn't detect inline asm tied operands above, so just make this extra
+    // pass for all inline asm.
+    if (MI->isInlineAsm() || hasEarlyClobbers || (hasTiedOps && hasPhysDefs)) {
+      handleThroughOperands(MI, VirtDead);
+      // Don't attempt coalescing when we have funny stuff going on.
+      CopyDst = 0;
     }
 
     // Second scan.
-    // Allocate virtreg uses and early clobbers.
-    // Collect VirtKills
+    // Allocate virtreg uses.
     for (unsigned i = 0; i != VirtOpEnd; ++i) {
       MachineOperand &MO = MI->getOperand(i);
       if (!MO.isReg()) continue;
@@ -728,15 +819,6 @@
         CopySrc = (CopySrc == Reg || CopySrc == PhysReg) ? PhysReg : 0;
         if (setPhysReg(MI, i, PhysReg))
           killVirtReg(LRI);
-      } else if (MO.isEarlyClobber()) {
-        // Note: defineVirtReg may invalidate MO.
-        LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, 0);
-        unsigned PhysReg = LRI->second.PhysReg;
-        if (setPhysReg(MI, i, PhysReg))
-          VirtDead.push_back(Reg);
-        PhysECs.push_back(PhysReg);
-        // Don't attempt coalescing when earlyclobbers are present.
-        CopyDst = 0;
       }
     }
 
@@ -744,12 +826,16 @@
 
     // Track registers defined by instruction - early clobbers at this point.
     UsedInInstr.reset();
-    for (unsigned i = 0, e = PhysECs.size(); i != e; ++i) {
-      unsigned PhysReg = PhysECs[i];
-      UsedInInstr.set(PhysReg);
-      for (const unsigned *AS = TRI->getAliasSet(PhysReg);
-            unsigned Alias = *AS; ++AS)
-        UsedInInstr.set(Alias);
+    if (hasEarlyClobbers) {
+      for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+        MachineOperand &MO = MI->getOperand(i);
+        if (!MO.isReg() || !MO.isDef()) continue;
+        unsigned Reg = MO.getReg();
+        if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
+        UsedInInstr.set(Reg);
+        for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
+          UsedInInstr.set(*AS);
+      }
     }
 
     unsigned DefOpEnd = MI->getNumOperands();

Modified: llvm/trunk/test/CodeGen/X86/2008-09-18-inline-asm-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-09-18-inline-asm-2.ll?rev=107043&r1=107042&r2=107043&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2008-09-18-inline-asm-2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2008-09-18-inline-asm-2.ll Mon Jun 28 13:34:34 2010
@@ -1,5 +1,5 @@
 ; RUN: llc < %s -march=x86 | grep "#%ebp %esi %edi 8(%edx) %eax (%ebx)"
-; RUN: llc < %s -march=x86 -regalloc=fast  | grep "#%edi %ebp %edx 8(%ebx) %eax (%esi)"
+; RUN: llc < %s -march=x86 -regalloc=fast  | grep "#%edi %ebx %edx 8(%ebp) %eax (%esi)"
 
 ; The 1st, 2nd, 3rd and 5th registers above must all be different.  The registers
 ; referenced in the 4th and 6th operands must not be the same as the 1st or 5th

Added: llvm/trunk/test/CodeGen/X86/2010-06-28-FastAllocTiedOperand.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-06-28-FastAllocTiedOperand.ll?rev=107043&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2010-06-28-FastAllocTiedOperand.ll (added)
+++ llvm/trunk/test/CodeGen/X86/2010-06-28-FastAllocTiedOperand.ll Mon Jun 28 13:34:34 2010
@@ -0,0 +1,21 @@
+; RUN: llc < %s -march=x86 -O0 | FileCheck %s
+; PR7509
+%asmtype = type { i32, i8*, i32, i32 }
+
+; Arguments 1 and 4 must be the same. No other output arguments may be
+; allocated %eax.
+
+; CHECK: InlineAsm Start
+; CHECK: arg1 %[[A1:...]]
+; CHECK-NOT: ax
+; CHECK: arg4 %[[A1]]
+; CHECK: InlineAsm End
+
+define i32 @func(i8* %s) nounwind ssp {
+entry:
+  %0 = tail call %asmtype asm "arg0 $0\0A\09arg1 $1\0A\09arg2 $2\0A\09arg3 $3\0A\09arg4 $4", "={ax},=r,=r,=r,1,~{dirflag},~{fpsr},~{flags}"(i8* %s) nounwind, !srcloc !0 ; <%0> [#uses=1]
+  %asmresult = extractvalue %asmtype %0, 0              ; <i64> [#uses=1]
+  ret i32 %asmresult
+}
+
+!0 = metadata !{i32 108}




From stoklund at 2pi.dk  Mon Jun 28 14:31:15 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Mon, 28 Jun 2010 19:31:15 -0000
Subject: [llvm-commits] [llvm] r107045 -
 /llvm/trunk/test/CodeGen/X86/2010-06-28-FastAllocTiedOperand.ll
Message-ID: <20100628193115.BD4F22A6C12C@llvm.org>

Author: stoklund
Date: Mon Jun 28 14:31:15 2010
New Revision: 107045

URL: http://llvm.org/viewvc/llvm-project?rev=107045&view=rev
Log:
Add a triple so test runs on Linux as well.

Modified:
    llvm/trunk/test/CodeGen/X86/2010-06-28-FastAllocTiedOperand.ll

Modified: llvm/trunk/test/CodeGen/X86/2010-06-28-FastAllocTiedOperand.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-06-28-FastAllocTiedOperand.ll?rev=107045&r1=107044&r2=107045&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2010-06-28-FastAllocTiedOperand.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2010-06-28-FastAllocTiedOperand.ll Mon Jun 28 14:31:15 2010
@@ -1,5 +1,6 @@
 ; RUN: llc < %s -march=x86 -O0 | FileCheck %s
 ; PR7509
+target triple = "i386-apple-darwin10"
 %asmtype = type { i32, i8*, i32, i32 }
 
 ; Arguments 1 and 4 must be the same. No other output arguments may be




From stoklund at 2pi.dk  Mon Jun 28 14:39:57 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Mon, 28 Jun 2010 19:39:57 -0000
Subject: [llvm-commits] [llvm] r107046 -
	/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
Message-ID: <20100628193958.061472A6C12C@llvm.org>

Author: stoklund
Date: Mon Jun 28 14:39:57 2010
New Revision: 107046

URL: http://llvm.org/viewvc/llvm-project?rev=107046&view=rev
Log:
After physreg coalescing, physical registers might not have live ranges where
you would expect.

Don't assert on that case, just give up.

This fixes PR7513.

Modified:
    llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp

Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=107046&r1=107045&r2=107046&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
+++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Mon Jun 28 14:39:57 2010
@@ -122,7 +122,8 @@
   // AValNo is the value number in A that defines the copy, A3 in the example.
   SlotIndex CopyUseIdx = CopyIdx.getUseIndex();
   LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyUseIdx);
-  assert(ALR != IntA.end() && "Live range not found!");
+  // The live range might not exist after fun with physreg coalescing.
+  if (ALR == IntA.end()) return false;
   VNInfo *AValNo = ALR->valno;
   // If it's re-defined by an early clobber somewhere in the live range, then
   // it's not safe to eliminate the copy. FIXME: This is a temporary workaround.




From stoklund at 2pi.dk  Mon Jun 28 15:01:15 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Mon, 28 Jun 2010 20:01:15 -0000
Subject: [llvm-commits] [llvm] r107049 -
	/llvm/trunk/test/CodeGen/X86/2010-06-25-asm-RA-crash.ll
Message-ID: <20100628200115.7644C2A6C12C@llvm.org>

Author: stoklund
Date: Mon Jun 28 15:01:15 2010
New Revision: 107049

URL: http://llvm.org/viewvc/llvm-project?rev=107049&view=rev
Log:
Don't write temporary files in test directory

Modified:
    llvm/trunk/test/CodeGen/X86/2010-06-25-asm-RA-crash.ll

Modified: llvm/trunk/test/CodeGen/X86/2010-06-25-asm-RA-crash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-06-25-asm-RA-crash.ll?rev=107049&r1=107048&r2=107049&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2010-06-25-asm-RA-crash.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2010-06-25-asm-RA-crash.ll Mon Jun 28 15:01:15 2010
@@ -1,4 +1,4 @@
-; RUN: llc %s -disable-fp-elim -mtriple=i686-pc-mingw32
+; RUN: llc < %s -disable-fp-elim -mtriple=i686-pc-mingw32
 
 %struct.__SEH2Frame = type {}
 




From dalej at apple.com  Mon Jun 28 15:06:59 2010
From: dalej at apple.com (Dale Johannesen)
Date: Mon, 28 Jun 2010 20:06:59 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r107051 -
	/llvm-gcc-4.2/trunk/gcc/c-decl.c
Message-ID: <20100628200659.DA25B2A6C12C@llvm.org>

Author: johannes
Date: Mon Jun 28 15:06:59 2010
New Revision: 107051

URL: http://llvm.org/viewvc/llvm-project?rev=107051&view=rev
Log:
Don't emit warnings for labels created internally
as part of parsing asm-block style inline asm.  7729514.


Modified:
    llvm-gcc-4.2/trunk/gcc/c-decl.c

Modified: llvm-gcc-4.2/trunk/gcc/c-decl.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/c-decl.c?rev=107051&r1=107050&r2=107051&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/c-decl.c (original)
+++ llvm-gcc-4.2/trunk/gcc/c-decl.c Mon Jun 28 15:06:59 2010
@@ -771,7 +771,10 @@
 	      error ("label %q+D used but not defined", p);
 	      DECL_INITIAL (p) = error_mark_node;
 	    }
-	  else if (!TREE_USED (p) && warn_unused_label)
+/* LLVM LOCAL begin 7729514 */
+  	  else if (!TREE_USED (p) && warn_unused_label &&
+                   strncmp( IDENTIFIER_POINTER (DECL_NAME (p)), "LASM$", 5) != 0)
+/* LLVM LOCAL end */
 	    {
 	      if (DECL_INITIAL (p))
 		warning (0, "label %q+D defined but not used", p);




From dalej at apple.com  Mon Jun 28 15:07:30 2010
From: dalej at apple.com (Dale Johannesen)
Date: Mon, 28 Jun 2010 20:07:30 -0000
Subject: [llvm-commits] [llvm] r107052 -
	/llvm/trunk/test/FrontendC/2010-06-28-nowarn.c
Message-ID: <20100628200730.F24062A6C12C@llvm.org>

Author: johannes
Date: Mon Jun 28 15:07:30 2010
New Revision: 107052

URL: http://llvm.org/viewvc/llvm-project?rev=107052&view=rev
Log:
Testcase for llvm-gcc fix 107051.


Added:
    llvm/trunk/test/FrontendC/2010-06-28-nowarn.c

Added: llvm/trunk/test/FrontendC/2010-06-28-nowarn.c
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/2010-06-28-nowarn.c?rev=107052&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC/2010-06-28-nowarn.c (added)
+++ llvm/trunk/test/FrontendC/2010-06-28-nowarn.c Mon Jun 28 15:07:30 2010
@@ -0,0 +1,21 @@
+// RUN: %llvmgcc %s -c -m32 -fasm-blocks -o /dev/null
+// This should not warn about unreferenced label. 7729514.
+// XFAIL: *
+// XTARGET: i386,i686,x86,darwin
+
+void quarterAsm(int array[], int len)
+{
+  __asm
+  {
+    mov esi, array;
+    mov ecx, len;
+    shr ecx, 2;
+loop:
+    movdqa xmm0, [esi];
+    psrad xmm0, 2;
+    movdqa [esi], xmm0;
+    add esi, 16;
+    sub ecx, 1;
+    jnz loop;
+  }
+}




From dpatel at apple.com  Mon Jun 28 15:24:35 2010
From: dpatel at apple.com (Devang Patel)
Date: Mon, 28 Jun 2010 20:24:35 -0000
Subject: [llvm-commits] [llvm] r107059 -
 /llvm/trunk/test/FrontendC/2010-06-24-DbgInlinedFnParameter.c
Message-ID: <20100628202435.981FC2A6C12C@llvm.org>

Author: dpatel
Date: Mon Jun 28 15:24:35 2010
New Revision: 107059

URL: http://llvm.org/viewvc/llvm-project?rev=107059&view=rev
Log:
Remove this weak test.

Removed:
    llvm/trunk/test/FrontendC/2010-06-24-DbgInlinedFnParameter.c

Removed: llvm/trunk/test/FrontendC/2010-06-24-DbgInlinedFnParameter.c
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/2010-06-24-DbgInlinedFnParameter.c?rev=107058&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC/2010-06-24-DbgInlinedFnParameter.c (original)
+++ llvm/trunk/test/FrontendC/2010-06-24-DbgInlinedFnParameter.c (removed)
@@ -1,16 +0,0 @@
-// RUN: %llvmgcc -S -O2 -g %s -o - | llc -O2 -o %t.s
-// RUN: grep  "# DW_TAG_formal_parameter" %t.s | count 4
-// Radar 8122864
-// XTARGET: x86,darwin
-static int foo(int a, int j) {
-  int k = 0;
-  if (a)
-    k = a + j;
-  else
-    k = j;
-  return k;
-}
-int bar(int o, int p) {
-
-  return foo(o, p);
-}




From grosbach at apple.com  Mon Jun 28 15:26:01 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 28 Jun 2010 20:26:01 -0000
Subject: [llvm-commits] [llvm] r107060 -
	/llvm/trunk/lib/CodeGen/IfConversion.cpp
Message-ID: <20100628202601.1AF6B2A6C12C@llvm.org>

Author: grosbach
Date: Mon Jun 28 15:26:00 2010
New Revision: 107060

URL: http://llvm.org/viewvc/llvm-project?rev=107060&view=rev
Log:
new, no longer brain-dead, r106907

Modified:
    llvm/trunk/lib/CodeGen/IfConversion.cpp

Modified: llvm/trunk/lib/CodeGen/IfConversion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/IfConversion.cpp?rev=107060&r1=107059&r2=107060&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/IfConversion.cpp (original)
+++ llvm/trunk/lib/CodeGen/IfConversion.cpp Mon Jun 28 15:26:00 2010
@@ -1228,10 +1228,17 @@
     ++DI2;
   BBI1->NonPredSize -= NumDups1;
   BBI2->NonPredSize -= NumDups1;
+
+  // Skip past the dups on each side separately since there may be
+  // differing dbg_value entries.
+  for (unsigned i = 0; i < NumDups1; ++DI1) {
+    if (!DI1->isDebugValue())
+      ++i;
+  }
   while (NumDups1 != 0) {
-    ++DI1;
     ++DI2;
-    --NumDups1;
+    if (!DI2->isDebugValue())
+      --NumDups1;
   }
 
   UpdatePredRedefs(BBI1->BB->begin(), DI1, Redefs, TRI);




From grosbach at apple.com  Mon Jun 28 15:41:34 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 28 Jun 2010 20:41:34 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r107062 - in /llvm-gcc-4.2/trunk:
 ChangeLog.apple build_gcc gcc/ChangeLog.apple gcc/config/arm/darwin.h
Message-ID: <20100628204135.20CA12A6C12C@llvm.org>

Author: grosbach
Date: Mon Jun 28 15:41:34 2010
New Revision: 107062

URL: http://llvm.org/viewvc/llvm-project?rev=107062&view=rev
Log:
Cleanup ARM build script to be more consistent about defaults.

Modified:
    llvm-gcc-4.2/trunk/ChangeLog.apple
    llvm-gcc-4.2/trunk/build_gcc
    llvm-gcc-4.2/trunk/gcc/ChangeLog.apple
    llvm-gcc-4.2/trunk/gcc/config/arm/darwin.h

Modified: llvm-gcc-4.2/trunk/ChangeLog.apple
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/ChangeLog.apple?rev=107062&r1=107061&r2=107062&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/ChangeLog.apple (original)
+++ llvm-gcc-4.2/trunk/ChangeLog.apple Mon Jun 28 15:41:34 2010
@@ -1,3 +1,9 @@
+2010-06-28 Jim Grosbach <grosbach at apple.com>
+
+	Radar 7449793
+	* build_gcc: Set DEFAULT_TARGET_OS to iOS when specified, OSX
+	otherwise.
+
 2009-05-27  Bob Wilson  <bob.wilson at apple.com>
 
 	Radar 6915254

Modified: llvm-gcc-4.2/trunk/build_gcc
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/build_gcc?rev=107062&r1=107061&r2=107062&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/build_gcc (original)
+++ llvm-gcc-4.2/trunk/build_gcc Mon Jun 28 15:41:34 2010
@@ -125,6 +125,12 @@
 ARM_LIBSTDCXX_VERSION=4.2.1
 ARM_CONFIGFLAGS="--with-gxx-include-dir=/usr/include/c++/$ARM_LIBSTDCXX_VERSION"
 
+# When building for a non-embedded train, ARM defaults to MacOSX, just like
+# x86 and ppc.
+if [ "x$RC_TARGET_CONFIG" = "xiPhone" ]; then
+  ARM_DARWIN_TARGET_IPHONEOS="YES"
+fi
+
 if [ -n "$ARM_SDK" ]; then
   ARM_SYSROOT=`xcodebuild -version -sdk $ARM_SDK Path`
 else
@@ -357,9 +363,20 @@
     fi
     # APPLE LOCAL end ARM ARM_CONFIGFLAGS
    fi
-   make $MAKEFLAGS all CFLAGS="$CFLAGS" CXXFLAGS="$CFLAGS" || exit 1
+   if [ $t = 'arm' ] ; then
+     if [ $ARM_DARWIN_TARGET_IPHONEOS = 'YES' ] ; then
+       DEFAULT_TARGET="-DDEFAULT_TARGET_OS=DARWIN_VERSION_IPHONEOS"
+     else
+        DEFAULT_TARGET="-DDEFAULT_TARGET_OS=DARWIN_VERSION_MACOSX"
+     fi
+   else
+     DEFAULT_TARGET=""
+   fi
+   make $MAKEFLAGS all CFLAGS="$CFLAGS $DEFAULT_TARGET" \
+     CXXFLAGS="$CFLAGS $DEFAULT_TARGET" || exit 1
    make $MAKEFLAGS DESTDIR=$DIR/dst-$BUILD-$t install-gcc install-target \
-     CFLAGS="$CFLAGS" CXXFLAGS="$CFLAGS" || exit 1
+     CFLAGS="$CFLAGS $DEFAULT_TARGET" \
+     CXXFLAGS="$CFLAGS $DEFAULT_TARGET" | exit 1
 
    # Add the compiler we just built to the path.
    # LLVM LOCAL Support for non /usr $DEST_ROOT

Modified: llvm-gcc-4.2/trunk/gcc/ChangeLog.apple
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/ChangeLog.apple?rev=107062&r1=107061&r2=107062&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/ChangeLog.apple (original)
+++ llvm-gcc-4.2/trunk/gcc/ChangeLog.apple Mon Jun 28 15:41:34 2010
@@ -1,3 +1,10 @@
+2010-06-28 Jim Grosbach <grosbach at apple.com>
+
+	Radar 7449793
+	* config/arm/darwin.h (DEFAULT_TARGET_OS): New.
+	(DARWIN_DEFAULT_VERSION_TYPE): OSX or iOS, depending on setting of
+	DEFAULT_TARGET_OS.
+
 2010-03-16  Fariborz Jahanian <fjahanian at apple.com>
 
         Radar 7760213

Modified: llvm-gcc-4.2/trunk/gcc/config/arm/darwin.h
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/darwin.h?rev=107062&r1=107061&r2=107062&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/config/arm/darwin.h (original)
+++ llvm-gcc-4.2/trunk/gcc/config/arm/darwin.h Mon Jun 28 15:41:34 2010
@@ -247,7 +247,11 @@
 #define DARWIN_LD_MINVERSION_SPEC "-iphoneos_version_min %(darwin_minversion)"
 
 /* Use iPhone OS version numbers by default.  */
+#ifdef DEFAULT_TARGET_OS
+#define DARWIN_DEFAULT_VERSION_TYPE  DEFAULT_TARGET_OS
+#else
 #define DARWIN_DEFAULT_VERSION_TYPE  DARWIN_VERSION_IPHONEOS
+#endif
 
 #define DARWIN_IPHONEOS_LIBGCC_SPEC "-lgcc_s.1 -lgcc"
 




From dpatel at apple.com  Mon Jun 28 15:53:04 2010
From: dpatel at apple.com (Devang Patel)
Date: Mon, 28 Jun 2010 20:53:04 -0000
Subject: [llvm-commits] [llvm] r107065 -
	/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
Message-ID: <20100628205304.E921B2A6C12C@llvm.org>

Author: dpatel
Date: Mon Jun 28 15:53:04 2010
New Revision: 107065

URL: http://llvm.org/viewvc/llvm-project?rev=107065&view=rev
Log:
Include inlined function in list of processed subprograms.

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=107065&r1=107064&r2=107065&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Mon Jun 28 15:53:04 2010
@@ -1386,7 +1386,6 @@
 /// If there are global variables in this scope then create and insert
 /// DIEs for these variables.
 DIE *DwarfDebug::updateSubprogramScopeDIE(const MDNode *SPNode) {
-  ProcessedSPNodes.insert(SPNode);
   CompileUnit *SPCU = getCompileUnit(SPNode);
   DIE *SPDie = SPCU->getDIE(SPNode);
   assert(SPDie && "Unable to find subprogram DIE!");
@@ -1692,6 +1691,7 @@
   if (Scope->getInlinedAt())
     ScopeDIE = constructInlinedScopeDIE(Scope);
   else if (DS.isSubprogram()) {
+    ProcessedSPNodes.insert(DS);
     if (Scope->isAbstractScope())
       ScopeDIE = getCompileUnit(DS)->getDIE(DS);
     else




From isanbard at gmail.com  Mon Jun 28 16:08:32 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Mon, 28 Jun 2010 21:08:32 -0000
Subject: [llvm-commits] [llvm] r107067 -
	/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Message-ID: <20100628210832.E6B172A6C12C@llvm.org>

Author: void
Date: Mon Jun 28 16:08:32 2010
New Revision: 107067

URL: http://llvm.org/viewvc/llvm-project?rev=107067&view=rev
Log:
Reduce indentation via early exit. NFC.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=107067&r1=107066&r2=107067&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Jun 28 16:08:32 2010
@@ -6026,6 +6026,7 @@
   bool NeedCF = false;
   bool NeedOF = false;
   switch (X86CC) {
+  default: break;
   case X86::COND_A: case X86::COND_AE:
   case X86::COND_B: case X86::COND_BE:
     NeedCF = true;
@@ -6035,120 +6036,129 @@
   case X86::COND_O: case X86::COND_NO:
     NeedOF = true;
     break;
-  default: break;
   }
 
   // See if we can use the EFLAGS value from the operand instead of
   // doing a separate TEST. TEST always sets OF and CF to 0, so unless
   // we prove that the arithmetic won't overflow, we can't use OF or CF.
-  if (Op.getResNo() == 0 && !NeedOF && !NeedCF) {
-    unsigned Opcode = 0;
-    unsigned NumOperands = 0;
-    switch (Op.getNode()->getOpcode()) {
-    case ISD::ADD:
-      // Due to an isel shortcoming, be conservative if this add is
-      // likely to be selected as part of a load-modify-store
-      // instruction. When the root node in a match is a store, isel
-      // doesn't know how to remap non-chain non-flag uses of other
-      // nodes in the match, such as the ADD in this case. This leads
-      // to the ADD being left around and reselected, with the result
-      // being two adds in the output.  Alas, even if none our users
-      // are stores, that doesn't prove we're O.K.  Ergo, if we have
-      // any parents that aren't CopyToReg or SETCC, eschew INC/DEC.
-      // A better fix seems to require climbing the DAG back to the
-      // root, and it doesn't seem to be worth the effort.
-      for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
-             UE = Op.getNode()->use_end(); UI != UE; ++UI)
-        if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
-          goto default_case;
-      if (ConstantSDNode *C =
-            dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
-        // An add of one will be selected as an INC.
-        if (C->getAPIntValue() == 1) {
-          Opcode = X86ISD::INC;
-          NumOperands = 1;
-          break;
-        }
-        // An add of negative one (subtract of one) will be selected as a DEC.
-        if (C->getAPIntValue().isAllOnesValue()) {
-          Opcode = X86ISD::DEC;
-          NumOperands = 1;
-          break;
-        }
+  if (Op.getResNo() != 0 || NeedOF || NeedCF)
+    // Emit a CMP with 0, which is the TEST pattern.
+    return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
+                       DAG.getConstant(0, Op.getValueType()));
+
+  unsigned Opcode = 0;
+  unsigned NumOperands = 0;
+  switch (Op.getNode()->getOpcode()) {
+  case ISD::ADD:
+    // Due to an isel shortcoming, be conservative if this add is likely to be
+    // selected as part of a load-modify-store instruction. When the root node
+    // in a match is a store, isel doesn't know how to remap non-chain non-flag
+    // uses of other nodes in the match, such as the ADD in this case. This
+    // leads to the ADD being left around and reselected, with the result being
+    // two adds in the output.  Alas, even if none our users are stores, that
+    // doesn't prove we're O.K.  Ergo, if we have any parents that aren't
+    // CopyToReg or SETCC, eschew INC/DEC.  A better fix seems to require
+    // climbing the DAG back to the root, and it doesn't seem to be worth the
+    // effort.
+    for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
+           UE = Op.getNode()->use_end(); UI != UE; ++UI)
+      if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
+        goto default_case;
+
+    if (ConstantSDNode *C =
+        dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
+      // An add of one will be selected as an INC.
+      if (C->getAPIntValue() == 1) {
+        Opcode = X86ISD::INC;
+        NumOperands = 1;
+        break;
       }
-      // Otherwise use a regular EFLAGS-setting add.
-      Opcode = X86ISD::ADD;
-      NumOperands = 2;
-      break;
-    case ISD::AND: {
-      // If the primary and result isn't used, don't bother using X86ISD::AND,
-      // because a TEST instruction will be better.
-      bool NonFlagUse = false;
-      for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
-             UE = Op.getNode()->use_end(); UI != UE; ++UI) {
-        SDNode *User = *UI;
-        unsigned UOpNo = UI.getOperandNo();
-        if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
-          // Look pass truncate.
-          UOpNo = User->use_begin().getOperandNo();
-          User = *User->use_begin();
-        }
-        if (User->getOpcode() != ISD::BRCOND &&
-            User->getOpcode() != ISD::SETCC &&
-            (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
-          NonFlagUse = true;
-          break;
-        }
+
+      // An add of negative one (subtract of one) will be selected as a DEC.
+      if (C->getAPIntValue().isAllOnesValue()) {
+        Opcode = X86ISD::DEC;
+        NumOperands = 1;
+        break;
       }
-      if (!NonFlagUse)
+    }
+
+    // Otherwise use a regular EFLAGS-setting add.
+    Opcode = X86ISD::ADD;
+    NumOperands = 2;
+    break;
+  case ISD::AND: {
+    // If the primary and result isn't used, don't bother using X86ISD::AND,
+    // because a TEST instruction will be better.
+    bool NonFlagUse = false;
+    for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
+           UE = Op.getNode()->use_end(); UI != UE; ++UI) {
+      SDNode *User = *UI;
+      unsigned UOpNo = UI.getOperandNo();
+      if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
+        // Look pass truncate.
+        UOpNo = User->use_begin().getOperandNo();
+        User = *User->use_begin();
+      }
+
+      if (User->getOpcode() != ISD::BRCOND &&
+          User->getOpcode() != ISD::SETCC &&
+          (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
+        NonFlagUse = true;
         break;
+      }
     }
+
+    if (!NonFlagUse)
+      break;
+  }
     // FALL THROUGH
-    case ISD::SUB:
-    case ISD::OR:
-    case ISD::XOR:
-      // Due to the ISEL shortcoming noted above, be conservative if this op is
-      // likely to be selected as part of a load-modify-store instruction.
-      for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
+  case ISD::SUB:
+  case ISD::OR:
+  case ISD::XOR:
+    // Due to the ISEL shortcoming noted above, be conservative if this op is
+    // likely to be selected as part of a load-modify-store instruction.
+    for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
            UE = Op.getNode()->use_end(); UI != UE; ++UI)
-        if (UI->getOpcode() == ISD::STORE)
-          goto default_case;
-      // Otherwise use a regular EFLAGS-setting instruction.
-      switch (Op.getNode()->getOpcode()) {
-      case ISD::SUB: Opcode = X86ISD::SUB; break;
-      case ISD::OR:  Opcode = X86ISD::OR;  break;
-      case ISD::XOR: Opcode = X86ISD::XOR; break;
-      case ISD::AND: Opcode = X86ISD::AND; break;
-      default: llvm_unreachable("unexpected operator!");
-      }
-      NumOperands = 2;
-      break;
-    case X86ISD::ADD:
-    case X86ISD::SUB:
-    case X86ISD::INC:
-    case X86ISD::DEC:
-    case X86ISD::OR:
-    case X86ISD::XOR:
-    case X86ISD::AND:
-      return SDValue(Op.getNode(), 1);
-    default:
-    default_case:
-      break;
-    }
-    if (Opcode != 0) {
-      SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
-      SmallVector<SDValue, 4> Ops;
-      for (unsigned i = 0; i != NumOperands; ++i)
-        Ops.push_back(Op.getOperand(i));
-      SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
-      DAG.ReplaceAllUsesWith(Op, New);
-      return SDValue(New.getNode(), 1);
+      if (UI->getOpcode() == ISD::STORE)
+        goto default_case;
+
+    // Otherwise use a regular EFLAGS-setting instruction.
+    switch (Op.getNode()->getOpcode()) {
+    default: llvm_unreachable("unexpected operator!");
+    case ISD::SUB: Opcode = X86ISD::SUB; break;
+    case ISD::OR:  Opcode = X86ISD::OR;  break;
+    case ISD::XOR: Opcode = X86ISD::XOR; break;
+    case ISD::AND: Opcode = X86ISD::AND; break;
     }
+
+    NumOperands = 2;
+    break;
+  case X86ISD::ADD:
+  case X86ISD::SUB:
+  case X86ISD::INC:
+  case X86ISD::DEC:
+  case X86ISD::OR:
+  case X86ISD::XOR:
+  case X86ISD::AND:
+    return SDValue(Op.getNode(), 1);
+  default:
+  default_case:
+    break;
   }
 
-  // Otherwise just emit a CMP with 0, which is the TEST pattern.
-  return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
-                     DAG.getConstant(0, Op.getValueType()));
+  if (Opcode == 0)
+    // Emit a CMP with 0, which is the TEST pattern.
+    return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
+                       DAG.getConstant(0, Op.getValueType()));
+
+  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
+  SmallVector<SDValue, 4> Ops;
+  for (unsigned i = 0; i != NumOperands; ++i)
+    Ops.push_back(Op.getOperand(i));
+
+  SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
+  DAG.ReplaceAllUsesWith(Op, New);
+  return SDValue(New.getNode(), 1);
 }
 
 /// Emit nodes that will be selected as "cmp Op0,Op1", or something




From bob.wilson at apple.com  Mon Jun 28 16:12:20 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Mon, 28 Jun 2010 21:12:20 -0000
Subject: [llvm-commits] [llvm] r107068 -
	/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
Message-ID: <20100628211220.212A62A6C12C@llvm.org>

Author: bwilson
Date: Mon Jun 28 16:12:19 2010
New Revision: 107068

URL: http://llvm.org/viewvc/llvm-project?rev=107068&view=rev
Log:
Support Thumb mode encoding of NEON instructions.

Modified:
    llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=107068&r1=107067&r2=107068&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Mon Jun 28 16:12:19 2010
@@ -1585,6 +1585,15 @@
   return Binary;
 }
 
+/// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
+/// data-processing instruction to the corresponding Thumb encoding.
+static unsigned convertNEONDataProcToThumb(unsigned Binary) {
+  assert((Binary & 0xfe000000) == 0xf2000000 &&
+         "not an ARM NEON data-processing instruction");
+  unsigned UBit = (Binary >> 24) & 1;
+  return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
+}
+
 void ARMCodeEmitter::emitNEONGetLaneInstruction(const MachineInstr &MI) {
   unsigned Binary = getBinaryCodeForInstr(MI);
 
@@ -1630,6 +1639,8 @@
   Binary |= (Imm3 << 16);
   unsigned Imm4 = Imm & 0xf;
   Binary |= Imm4;
+  if (Subtarget->isThumb())
+    Binary = convertNEONDataProcToThumb(Binary);
   emitWordLE(Binary);
 }
 
@@ -1642,6 +1653,8 @@
   if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
     ++OpIdx;
   Binary |= encodeNEONRm(MI, OpIdx);
+  if (Subtarget->isThumb())
+    Binary = convertNEONDataProcToThumb(Binary);
   // FIXME: This does not handle VDUPfdf or VDUPfqf.
   emitWordLE(Binary);
 }
@@ -1658,6 +1671,8 @@
   if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
     ++OpIdx;
   Binary |= encodeNEONRm(MI, OpIdx);
+  if (Subtarget->isThumb())
+    Binary = convertNEONDataProcToThumb(Binary);
   // FIXME: This does not handle VMOVDneon or VMOVQ.
   emitWordLE(Binary);
 }




From bob.wilson at apple.com  Mon Jun 28 16:16:31 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Mon, 28 Jun 2010 21:16:31 -0000
Subject: [llvm-commits] [llvm] r107070 -
	/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
Message-ID: <20100628211631.203912A6C12C@llvm.org>

Author: bwilson
Date: Mon Jun 28 16:16:30 2010
New Revision: 107070

URL: http://llvm.org/viewvc/llvm-project?rev=107070&view=rev
Log:
Refactor encoding function for NEON 1-register with modified immediate format.

Modified:
    llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=107070&r1=107069&r2=107070&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Mon Jun 28 16:16:30 2010
@@ -1630,15 +1630,11 @@
   // Immediate fields: Op, Cmode, I, Imm3, Imm4
   unsigned Imm = MI.getOperand(1).getImm();
   unsigned Op = (Imm >> 12) & 1;
-  Binary |= (Op << 5);
   unsigned Cmode = (Imm >> 8) & 0xf;
-  Binary |= (Cmode << 8);
   unsigned I = (Imm >> 7) & 1;
-  Binary |= (I << 24);
   unsigned Imm3 = (Imm >> 4) & 0x7;
-  Binary |= (Imm3 << 16);
   unsigned Imm4 = Imm & 0xf;
-  Binary |= Imm4;
+  Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
   if (Subtarget->isThumb())
     Binary = convertNEONDataProcToThumb(Binary);
   emitWordLE(Binary);




From gohman at apple.com  Mon Jun 28 16:16:52 2010
From: gohman at apple.com (Dan Gohman)
Date: Mon, 28 Jun 2010 21:16:52 -0000
Subject: [llvm-commits] [llvm] r107071 - in /llvm/trunk:
 lib/Analysis/BasicAliasAnalysis.cpp lib/VMCore/Value.cpp
 test/Analysis/BasicAA/unreachable-block.ll
Message-ID: <20100628211652.97A622A6C12C@llvm.org>

Author: djg
Date: Mon Jun 28 16:16:52 2010
New Revision: 107071

URL: http://llvm.org/viewvc/llvm-project?rev=107071&view=rev
Log:
Fix Value::stripPointerCasts and BasicAA to avoid trouble on
code in unreachable blocks, which have have use-def cycles.
This fixes PR7514.

Added:
    llvm/trunk/test/Analysis/BasicAA/unreachable-block.ll
Modified:
    llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp
    llvm/trunk/lib/VMCore/Value.cpp

Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=107071&r1=107070&r2=107071&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Mon Jun 28 16:16:52 2010
@@ -189,9 +189,9 @@
     BasicAliasAnalysis() : NoAA(&ID) {}
     AliasResult alias(const Value *V1, unsigned V1Size,
                       const Value *V2, unsigned V2Size) {
-      assert(VisitedPHIs.empty() && "VisitedPHIs must be cleared after use!");
+      assert(Visited.empty() && "Visited must be cleared after use!");
       AliasResult Alias = aliasCheck(V1, V1Size, V2, V2Size);
-      VisitedPHIs.clear();
+      Visited.clear();
       return Alias;
     }
 
@@ -213,8 +213,8 @@
     }
     
   private:
-    // VisitedPHIs - Track PHI nodes visited by a aliasCheck() call.
-    SmallPtrSet<const Value*, 16> VisitedPHIs;
+    // Visited - Track instructions visited by a aliasPHI, aliasSelect(), and aliasGEP().
+    SmallPtrSet<const Value*, 16> Visited;
 
     // aliasGEP - Provide a bunch of ad-hoc rules to disambiguate a GEP
     // instruction against another.
@@ -440,6 +440,13 @@
                              const Value *V2, unsigned V2Size,
                              const Value *UnderlyingV1,
                              const Value *UnderlyingV2) {
+  // If this GEP has been visited before, we're on a use-def cycle.
+  // Such cycles are only valid when PHI nodes are involved or in unreachable
+  // code. The visitPHI function catches cycles containing PHIs, but there
+  // could still be a cycle without PHIs in unreachable code.
+  if (!Visited.insert(GEP1))
+    return MayAlias;
+
   int64_t GEP1BaseOffset;
   SmallVector<std::pair<const Value*, int64_t>, 4> GEP1VariableIndices;
 
@@ -550,6 +557,13 @@
 AliasAnalysis::AliasResult
 BasicAliasAnalysis::aliasSelect(const SelectInst *SI, unsigned SISize,
                                 const Value *V2, unsigned V2Size) {
+  // If this select has been visited before, we're on a use-def cycle.
+  // Such cycles are only valid when PHI nodes are involved or in unreachable
+  // code. The visitPHI function catches cycles containing PHIs, but there
+  // could still be a cycle without PHIs in unreachable code.
+  if (!Visited.insert(SI))
+    return MayAlias;
+
   // If the values are Selects with the same condition, we can do a more precise
   // check: just check for aliases between the values on corresponding arms.
   if (const SelectInst *SI2 = dyn_cast<SelectInst>(V2))
@@ -570,11 +584,17 @@
   // If both arms of the Select node NoAlias or MustAlias V2, then returns
   // NoAlias / MustAlias. Otherwise, returns MayAlias.
   AliasResult Alias =
-    aliasCheck(SI->getTrueValue(), SISize, V2, V2Size);
+    aliasCheck(V2, V2Size, SI->getTrueValue(), SISize);
   if (Alias == MayAlias)
     return MayAlias;
+
+  // If V2 is visited, the recursive case will have been caught in the
+  // above aliasCheck call, so these subsequent calls to aliasCheck
+  // don't need to assume that V2 is being visited recursively.
+  Visited.erase(V2);
+
   AliasResult ThisAlias =
-    aliasCheck(SI->getFalseValue(), SISize, V2, V2Size);
+    aliasCheck(V2, V2Size, SI->getFalseValue(), SISize);
   if (ThisAlias != Alias)
     return MayAlias;
   return Alias;
@@ -586,7 +606,7 @@
 BasicAliasAnalysis::aliasPHI(const PHINode *PN, unsigned PNSize,
                              const Value *V2, unsigned V2Size) {
   // The PHI node has already been visited, avoid recursion any further.
-  if (!VisitedPHIs.insert(PN))
+  if (!Visited.insert(PN))
     return MayAlias;
 
   // If the values are PHIs in the same block, we can do a more precise
@@ -636,10 +656,10 @@
   for (unsigned i = 1, e = V1Srcs.size(); i != e; ++i) {
     Value *V = V1Srcs[i];
 
-    // If V2 is a PHI, the recursive case will have been caught in the
+    // If V2 is visited, the recursive case will have been caught in the
     // above aliasCheck call, so these subsequent calls to aliasCheck
     // don't need to assume that V2 is being visited recursively.
-    VisitedPHIs.erase(V2);
+    Visited.erase(V2);
 
     AliasResult ThisAlias = aliasCheck(V2, V2Size, V, PNSize);
     if (ThisAlias != Alias || ThisAlias == MayAlias)

Modified: llvm/trunk/lib/VMCore/Value.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Value.cpp?rev=107071&r1=107070&r2=107071&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Value.cpp (original)
+++ llvm/trunk/lib/VMCore/Value.cpp Mon Jun 28 16:16:52 2010
@@ -322,7 +322,13 @@
 Value *Value::stripPointerCasts() {
   if (!getType()->isPointerTy())
     return this;
+
+  // Even though we don't look through PHI nodes, we could be called on an
+  // instruction in an unreachable block, which may be on a cycle.
+  SmallPtrSet<Value *, 4> Visited;
+
   Value *V = this;
+  Visited.insert(V);
   do {
     if (GEPOperator *GEP = dyn_cast<GEPOperator>(V)) {
       if (!GEP->hasAllZeroIndices())
@@ -338,7 +344,9 @@
       return V;
     }
     assert(V->getType()->isPointerTy() && "Unexpected operand type!");
-  } while (1);
+  } while (Visited.insert(V));
+
+  return V;
 }
 
 Value *Value::getUnderlyingObject(unsigned MaxLookup) {

Added: llvm/trunk/test/Analysis/BasicAA/unreachable-block.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/BasicAA/unreachable-block.ll?rev=107071&view=auto
==============================================================================
--- llvm/trunk/test/Analysis/BasicAA/unreachable-block.ll (added)
+++ llvm/trunk/test/Analysis/BasicAA/unreachable-block.ll Mon Jun 28 16:16:52 2010
@@ -0,0 +1,16 @@
+; RUN: opt -aa-eval -disable-output < %s >& /dev/null
+
+; BasicAA shouldn't infinitely recurse on the use-def cycles in
+; unreachable code.
+
+define void @func_2() nounwind {
+entry:
+  unreachable
+
+bb:
+  %t = select i1 undef, i32* %t, i32* undef
+  %p = select i1 undef, i32* %p, i32* %p
+  %q = select i1 undef, i32* undef, i32* %p
+  %a = getelementptr i8* %a, i32 0
+  unreachable
+}




From grosbach at apple.com  Mon Jun 28 16:29:17 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 28 Jun 2010 21:29:17 -0000
Subject: [llvm-commits] [llvm] r107073 -
	/llvm/trunk/lib/Target/ARM/Thumb2HazardRecognizer.cpp
Message-ID: <20100628212917.CE3EB2A6C12C@llvm.org>

Author: grosbach
Date: Mon Jun 28 16:29:17 2010
New Revision: 107073

URL: http://llvm.org/viewvc/llvm-project?rev=107073&view=rev
Log:
tidy up style. no functional change.

Modified:
    llvm/trunk/lib/Target/ARM/Thumb2HazardRecognizer.cpp

Modified: llvm/trunk/lib/Target/ARM/Thumb2HazardRecognizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2HazardRecognizer.cpp?rev=107073&r1=107072&r2=107073&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb2HazardRecognizer.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb2HazardRecognizer.cpp Mon Jun 28 16:29:17 2010
@@ -41,9 +41,10 @@
     ITBlockSize = 4 - NumTZ;
     MachineBasicBlock::iterator I = MI;
     for (unsigned i = 0; i < ITBlockSize; ++i) {
-      ++I;
-      while (I->isDebugValue())
+      // Advance to the next instruction, skipping any dbg_value instructions.
+      do {
         ++I;
+      } while (I->isDebugValue());
       ITBlockMIs[ITBlockSize-1-i] = &*I;
     }
   }




From gohman at apple.com  Mon Jun 28 16:30:08 2010
From: gohman at apple.com (Dan Gohman)
Date: Mon, 28 Jun 2010 21:30:08 -0000
Subject: [llvm-commits] [llvm] r107074 - in /llvm/trunk:
 lib/VMCore/ConstantFold.cpp test/Transforms/InstCombine/icmp.ll
Message-ID: <20100628213008.2C0862A6C12C@llvm.org>

Author: djg
Date: Mon Jun 28 16:30:07 2010
New Revision: 107074

URL: http://llvm.org/viewvc/llvm-project?rev=107074&view=rev
Log:
Constant fold x == undef to undef.

Modified:
    llvm/trunk/lib/VMCore/ConstantFold.cpp
    llvm/trunk/test/Transforms/InstCombine/icmp.ll

Modified: llvm/trunk/lib/VMCore/ConstantFold.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/ConstantFold.cpp?rev=107074&r1=107073&r2=107074&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/ConstantFold.cpp (original)
+++ llvm/trunk/lib/VMCore/ConstantFold.cpp Mon Jun 28 16:30:07 2010
@@ -1817,8 +1817,15 @@
     return Constant::getAllOnesValue(ResultTy);
 
   // Handle some degenerate cases first
-  if (isa<UndefValue>(C1) || isa<UndefValue>(C2))
+  if (isa<UndefValue>(C1) || isa<UndefValue>(C2)) {
+    // For EQ and NE, we can always pick a value for the undef to make the
+    // predicate pass or fail, so we can return undef.
+    if (ICmpInst::isEquality(ICmpInst::Predicate(pred)))
+      return UndefValue::get(ResultTy);
+    // Otherwise, pick the same value as the non-undef operand, and fold
+    // it to true or false.
     return ConstantInt::get(ResultTy, CmpInst::isTrueWhenEqual(pred));
+  }
 
   // No compile-time operations on this type yet.
   if (C1->getType()->isPPC_FP128Ty())

Modified: llvm/trunk/test/Transforms/InstCombine/icmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/icmp.ll?rev=107074&r1=107073&r2=107074&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/icmp.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/icmp.ll Mon Jun 28 16:30:07 2010
@@ -131,3 +131,26 @@
 ; CHECK: ret i1 false
 }
 
+define i1 @test14(i8 %X) nounwind readnone {
+entry:
+        %cmp = icmp slt i8 undef, -128
+        ret i1 %cmp
+; CHECK: @test14
+; CHECK: ret i1 false
+}
+
+define i1 @test15() nounwind readnone {
+entry:
+        %cmp = icmp eq i8 undef, -128
+        ret i1 %cmp
+; CHECK: @test15
+; CHECK: ret i1 undef
+}
+
+define i1 @test16() nounwind readnone {
+entry:
+        %cmp = icmp ne i8 undef, -128
+        ret i1 %cmp
+; CHECK: @test16
+; CHECK: ret i1 undef
+}




From enderby at apple.com  Mon Jun 28 16:45:58 2010
From: enderby at apple.com (Kevin Enderby)
Date: Mon, 28 Jun 2010 21:45:58 -0000
Subject: [llvm-commits] [llvm] r107077 - in /llvm/trunk:
 include/llvm/MC/MCContext.h include/llvm/MC/MCParser/AsmParser.h
 lib/MC/MCContext.cpp lib/MC/MCParser/AsmParser.cpp
Message-ID: <20100628214558.4439A2A6C12C@llvm.org>

Author: enderby
Date: Mon Jun 28 16:45:58 2010
New Revision: 107077

URL: http://llvm.org/viewvc/llvm-project?rev=107077&view=rev
Log:
Added the darwin .secure_log_unique and .secure_log_reset directives.

Modified:
    llvm/trunk/include/llvm/MC/MCContext.h
    llvm/trunk/include/llvm/MC/MCParser/AsmParser.h
    llvm/trunk/lib/MC/MCContext.cpp
    llvm/trunk/lib/MC/MCParser/AsmParser.cpp

Modified: llvm/trunk/include/llvm/MC/MCContext.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCContext.h?rev=107077&r1=107076&r2=107077&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCContext.h (original)
+++ llvm/trunk/include/llvm/MC/MCContext.h Mon Jun 28 16:45:58 2010
@@ -14,6 +14,7 @@
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/StringMap.h"
 #include "llvm/Support/Allocator.h"
+#include "llvm/Support/raw_ostream.h"
 
 namespace llvm {
   class MCAsmInfo;
@@ -54,6 +55,17 @@
     /// for the LocalLabelVal and adds it to the map if needed.
     unsigned GetInstance(int64_t LocalLabelVal);
     
+    /// The file name of the log file from the enviromment variable
+    /// AS_SECURE_LOG_FILE.  Which must be set before the .secure_log_unique
+    /// directive is used or it is an error.
+    char *SecureLogFile;
+    /// The stream that gets written to for the .secure_log_unique directive.
+    raw_ostream *SecureLog;
+    /// Boolean toggled when .secure_log_unique / .secure_log_reset is seen to
+    /// catch errors if .secure_log_unique appears twice without
+    /// .secure_log_reset appearing between them.
+    bool SecureLogUsed;
+
     /// Allocator - Allocator object used for creating machine code objects.
     ///
     /// We use a bump pointer allocator to avoid the need to track all allocated
@@ -127,6 +139,16 @@
     
     /// @}
 
+    char *getSecureLogFile() { return SecureLogFile; }
+    raw_ostream *getSecureLog() { return SecureLog; }
+    bool getSecureLogUsed() { return SecureLogUsed; }
+    void setSecureLog(raw_ostream *Value) {
+      SecureLog = Value;
+    }
+    void setSecureLogUsed(bool Value) {
+      SecureLogUsed = Value;
+    }
+
     void *Allocate(unsigned Size, unsigned Align = 8) {
       return Allocator.Allocate(Size, Align);
     }

Modified: llvm/trunk/include/llvm/MC/MCParser/AsmParser.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/AsmParser.h?rev=107077&r1=107076&r2=107077&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCParser/AsmParser.h (original)
+++ llvm/trunk/include/llvm/MC/MCParser/AsmParser.h Mon Jun 28 16:45:58 2010
@@ -143,6 +143,10 @@
   bool ParseDirectiveDarwinSubsectionsViaSymbols();
   // Darwin specific .dump and .load
   bool ParseDirectiveDarwinDumpOrLoad(SMLoc IDLoc, bool IsDump);
+  // Darwin specific .secure_log_unique
+  bool ParseDirectiveDarwinSecureLogUnique(SMLoc IDLoc);
+  // Darwin specific .secure_log_reset
+  bool ParseDirectiveDarwinSecureLogReset(SMLoc IDLoc);
 
   bool ParseDirectiveAbort(); // ".abort"
   bool ParseDirectiveInclude(); // ".include"

Modified: llvm/trunk/lib/MC/MCContext.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCContext.cpp?rev=107077&r1=107076&r2=107077&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCContext.cpp (original)
+++ llvm/trunk/lib/MC/MCContext.cpp Mon Jun 28 16:45:58 2010
@@ -27,6 +27,10 @@
   MachOUniquingMap = 0;
   ELFUniquingMap = 0;
   COFFUniquingMap = 0;
+
+  SecureLogFile = getenv("AS_SECURE_LOG_FILE");
+  SecureLog = 0;
+  SecureLogUsed = false;
 }
 
 MCContext::~MCContext() {
@@ -37,6 +41,9 @@
   delete (MachOUniqueMapTy*)MachOUniquingMap;
   delete (ELFUniqueMapTy*)ELFUniquingMap;
   delete (COFFUniqueMapTy*)COFFUniquingMap;
+
+  // If the stream for the .secure_log_unique directive was created free it.
+  delete (raw_ostream*)SecureLog;
 }
 
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=107077&r1=107076&r2=107077&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original)
+++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Mon Jun 28 16:45:58 2010
@@ -24,6 +24,7 @@
 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
 #include "llvm/Support/Compiler.h"
 #include "llvm/Support/SourceMgr.h"
+#include "llvm/Support/MemoryBuffer.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Target/TargetAsmParser.h"
 using namespace llvm;
@@ -780,6 +781,10 @@
       return ParseDirectiveDarwinDumpOrLoad(IDLoc, /*IsDump=*/true);
     if (IDVal == ".load")
       return ParseDirectiveDarwinDumpOrLoad(IDLoc, /*IsLoad=*/false);
+    if (IDVal == ".secure_log_unique")
+      return ParseDirectiveDarwinSecureLogUnique(IDLoc);
+    if (IDVal == ".secure_log_reset")
+      return ParseDirectiveDarwinSecureLogReset(IDLoc);
 
     // Look up the handler in the handler table, 
     bool(AsmParser::*Handler)(StringRef, SMLoc) = DirectiveMap[IDVal];
@@ -1735,6 +1740,64 @@
   return false;
 }
 
+/// ParseDirectiveDarwinSecureLogUnique
+///  ::= .secure_log_unique "log message"
+bool AsmParser::ParseDirectiveDarwinSecureLogUnique(SMLoc IDLoc) {
+  std::string LogMessage;
+
+  if (Lexer.isNot(AsmToken::String))
+    LogMessage = "";
+  else{
+    LogMessage = getTok().getString();
+    Lex();
+  }
+
+  if (Lexer.isNot(AsmToken::EndOfStatement))
+    return TokError("unexpected token in '.secure_log_unique' directive");
+  
+  if (getContext().getSecureLogUsed() != false)
+    return Error(IDLoc, ".secure_log_unique specified multiple times");
+
+  char *SecureLogFile = getContext().getSecureLogFile();
+  if (SecureLogFile == NULL)
+    return Error(IDLoc, ".secure_log_unique used but AS_SECURE_LOG_FILE "
+                 "environment variable unset.");
+
+  raw_ostream *OS = getContext().getSecureLog();
+  if (OS == NULL) {
+    std::string Err;
+    OS = new raw_fd_ostream(SecureLogFile, Err, raw_fd_ostream::F_Append);
+    if (!Err.empty()) {
+       delete OS;
+       return Error(IDLoc, Twine("can't open secure log file: ") +
+                    SecureLogFile + " (" + Err + ")");
+    }
+    getContext().setSecureLog(OS);
+  }
+
+  int CurBuf = SrcMgr.FindBufferContainingLoc(IDLoc);
+  *OS << SrcMgr.getBufferInfo(CurBuf).Buffer->getBufferIdentifier() << ":"
+      << SrcMgr.FindLineNumber(IDLoc, CurBuf) << ":"
+      << LogMessage + "\n";
+
+  getContext().setSecureLogUsed(true);
+
+  return false;
+}
+
+/// ParseDirectiveDarwinSecureLogReset
+///  ::= .secure_log_reset
+bool AsmParser::ParseDirectiveDarwinSecureLogReset(SMLoc IDLoc) {
+  if (Lexer.isNot(AsmToken::EndOfStatement))
+    return TokError("unexpected token in '.secure_log_reset' directive");
+  
+  Lex();
+
+  getContext().setSecureLogUsed(false);
+
+  return false;
+}
+
 /// ParseDirectiveIf
 /// ::= .if expression
 bool AsmParser::ParseDirectiveIf(SMLoc DirectiveLoc) {




From evan.cheng at apple.com  Mon Jun 28 17:04:30 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 28 Jun 2010 15:04:30 -0700
Subject: [llvm-commits] Global Merge Pass for ARM
In-Reply-To: <AANLkTilDBPIuRKvH7fwaplxpqGlhzRJ74FRfZikyDLNA@mail.gmail.com>
References: <1274006983.22060.61.camel@aslstation>
	<85FA0CB8-76CF-42A8-AD4F-C17F08902366@apple.com>
	<AANLkTily_30vdBcmwWVeiJaAKlrsB0mOok13_BERjKN3@mail.gmail.com>
	<B9CA014A-E61A-45F3-A5E7-B2F2928A4DB1@apple.com>
	<1275140451.22060.104.camel@aslstation>
	<2511C9BB-5E58-4A8C-B7DB-C134052193CC@apple.com>
	<AANLkTil3OHharErO50AZX9mujk8RzY7c5yn9TffufVlA@mail.gmail.com>
	<AANLkTin8rBAIenURpVtQKIOJ_23JHXVbI3xH3TLph9lp@mail.gmail.com>
	<AANLkTilDBPIuRKvH7fwaplxpqGlhzRJ74FRfZikyDLNA@mail.gmail.com>
Message-ID: <340D0C7E-05CF-4161-B9E0-9B8947973FA2@apple.com>

The patch is ok with me. We can refine it later.

Thanks,

Evan

On Jun 28, 2010, at 1:29 AM, Anton Korobeynikov wrote:

>> Ping?
> Ping^2
> 
> -- 
> With best regards, Anton Korobeynikov
> Faculty of Mathematics and Mechanics, Saint Petersburg State University



From dalej at apple.com  Mon Jun 28 17:09:45 2010
From: dalej at apple.com (Dale Johannesen)
Date: Mon, 28 Jun 2010 22:09:45 -0000
Subject: [llvm-commits] [llvm] r107079 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/TargetLowering.cpp
 test/CodeGen/X86/2008-09-18-inline-asm-2.ll
 test/CodeGen/X86/2010-06-28-matched-g-constraint.ll
 test/FrontendC/2010-06-17-asmcrash.c
Message-ID: <20100628220945.73CE82A6C12C@llvm.org>

Author: johannes
Date: Mon Jun 28 17:09:45 2010
New Revision: 107079

URL: http://llvm.org/viewvc/llvm-project?rev=107079&view=rev
Log:
In asm's, output operands with matching input constraints
have to be registers, per gcc documentation.  This affects
the logic for determining what "g" should lower to.  PR 7393.
A couple of existing testcases are affected.


Added:
    llvm/trunk/test/CodeGen/X86/2010-06-28-matched-g-constraint.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    llvm/trunk/test/CodeGen/X86/2008-09-18-inline-asm-2.ll
    llvm/trunk/test/FrontendC/2010-06-17-asmcrash.c

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=107079&r1=107078&r2=107079&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Mon Jun 28 17:09:45 2010
@@ -2547,12 +2547,12 @@
   unsigned BestIdx = 0;
   TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
   int BestGenerality = -1;
-  
+
   // Loop over the options, keeping track of the most general one.
   for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
     TargetLowering::ConstraintType CType =
       TLI.getConstraintType(OpInfo.Codes[i]);
-    
+
     // If this is an 'other' constraint, see if the operand is valid for it.
     // For example, on X86 we might have an 'rI' constraint.  If the operand
     // is an integer in the range [0..31] we want to use I (saving a load
@@ -2570,6 +2570,11 @@
       }
     }
     
+    // Things with matching constraints can only be registers, per gcc
+    // documentation.  This mainly affects "g" constraints.
+    if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
+      continue;
+    
     // This constraint letter is more general than the previous one, use it.
     int Generality = getConstraintGenerality(CType);
     if (Generality > BestGenerality) {

Modified: llvm/trunk/test/CodeGen/X86/2008-09-18-inline-asm-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-09-18-inline-asm-2.ll?rev=107079&r1=107078&r2=107079&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2008-09-18-inline-asm-2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2008-09-18-inline-asm-2.ll Mon Jun 28 17:09:45 2010
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=x86 | grep "#%ebp %esi %edi 8(%edx) %eax (%ebx)"
-; RUN: llc < %s -march=x86 -regalloc=fast  | grep "#%edi %ebx %edx 8(%ebp) %eax (%esi)"
+; RUN: llc < %s -march=x86 | grep "#%ebp %edi %ebx 8(%esi) %eax %dl"
+; RUN: llc < %s -march=x86 -regalloc=fast  | grep "#%ebx %esi %edi 8(%ebp) %eax %dl"
 
 ; The 1st, 2nd, 3rd and 5th registers above must all be different.  The registers
 ; referenced in the 4th and 6th operands must not be the same as the 1st or 5th

Added: llvm/trunk/test/CodeGen/X86/2010-06-28-matched-g-constraint.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-06-28-matched-g-constraint.ll?rev=107079&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2010-06-28-matched-g-constraint.ll (added)
+++ llvm/trunk/test/CodeGen/X86/2010-06-28-matched-g-constraint.ll Mon Jun 28 17:09:45 2010
@@ -0,0 +1,11 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin11 | FileCheck %s
+; Any register is OK for %0, but it must be a register, not memory.
+
+define i32 @foo() nounwind ssp {
+entry:
+; CHECK: GCROOT %eax
+  %_r = alloca i32, align 4                       ; <i32*> [#uses=2]
+  call void asm "/* GCROOT $0 */", "=*imr,0,~{dirflag},~{fpsr},~{flags}"(i32* %_r, i32 4) nounwind
+  %0 = load i32* %_r, align 4                     ; <i32> [#uses=1]
+  ret i32 %0
+}

Modified: llvm/trunk/test/FrontendC/2010-06-17-asmcrash.c
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/2010-06-17-asmcrash.c?rev=107079&r1=107078&r2=107079&view=diff
==============================================================================
--- llvm/trunk/test/FrontendC/2010-06-17-asmcrash.c (original)
+++ llvm/trunk/test/FrontendC/2010-06-17-asmcrash.c Mon Jun 28 17:09:45 2010
@@ -12,5 +12,5 @@
      :"+g"(h), "+S"(pixels), "+D"(block)
      :"r" ((x86_reg)line_size)         
      :"%""rax", "memory");
-// CHECK: # (%rsp) %rsi %rdi %rcx
+// CHECK: # %ecx %rsi %rdi %rdx
  }




From gohman at apple.com  Mon Jun 28 17:09:52 2010
From: gohman at apple.com (Dan Gohman)
Date: Mon, 28 Jun 2010 22:09:52 -0000
Subject: [llvm-commits] [llvm] r107080 - /llvm/trunk/docs/AliasAnalysis.html
Message-ID: <20100628220952.E8BBC2A6C12C@llvm.org>

Author: djg
Date: Mon Jun 28 17:09:52 2010
New Revision: 107080

URL: http://llvm.org/viewvc/llvm-project?rev=107080&view=rev
Log:
Add a blurb about -scev-aa.

Modified:
    llvm/trunk/docs/AliasAnalysis.html

Modified: llvm/trunk/docs/AliasAnalysis.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/AliasAnalysis.html?rev=107080&r1=107079&r2=107080&view=diff
==============================================================================
--- llvm/trunk/docs/AliasAnalysis.html (original)
+++ llvm/trunk/docs/AliasAnalysis.html Mon Jun 28 17:09:52 2010
@@ -789,6 +789,19 @@
 
 </div>
 
+<!-- _______________________________________________________________________ -->
+<div class="doc_subsubsection">
+  <a name="scev-aa">The <tt>-scev-aa</tt> pass</a>
+</div>
+
+<div class="doc_text">
+
+<p>The <tt>-scev-aa</tt> pass implements AliasAnalysis queries by
+translating them into ScalarEvolution queries. This gives it a
+more complete understanding of <tt>getelementptr</tt> instructions
+and loop induction variables than other alias analyses have.</p>
+
+</div>
 
 <!-- ======================================================================= -->
 <div class="doc_subsection">




From stoklund at 2pi.dk  Mon Jun 28 17:09:58 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Mon, 28 Jun 2010 22:09:58 -0000
Subject: [llvm-commits] [test-suite] r107081 -
 /test-suite/trunk/SingleSource/Benchmarks/Misc/lowercase.c
Message-ID: <20100628220958.46C8C2A6C12D@llvm.org>

Author: stoklund
Date: Mon Jun 28 17:09:58 2010
New Revision: 107081

URL: http://llvm.org/viewvc/llvm-project?rev=107081&view=rev
Log:
Speed up test for SMALL_TEST_SIZE

Modified:
    test-suite/trunk/SingleSource/Benchmarks/Misc/lowercase.c

Modified: test-suite/trunk/SingleSource/Benchmarks/Misc/lowercase.c
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/Benchmarks/Misc/lowercase.c?rev=107081&r1=107080&r2=107081&view=diff
==============================================================================
--- test-suite/trunk/SingleSource/Benchmarks/Misc/lowercase.c (original)
+++ test-suite/trunk/SingleSource/Benchmarks/Misc/lowercase.c Mon Jun 28 17:09:58 2010
@@ -40,7 +40,11 @@
   printf("iterations (%ld characters)\n", numberOfIterations, numberOfCharacters);
 
   memset(result, 0, sizeof(UChar) * testDataLength);
+#ifdef SMALL_PROBLEM_SIZE
+  for (i = 0; i < 100000; i++)
+#else
   for (i = 0; i < 10000000; i++)
+#endif
     lower_StringImpl(testData, numberOfCharacters, result);
 }
 




From stoklund at 2pi.dk  Mon Jun 28 17:10:00 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Mon, 28 Jun 2010 22:10:00 -0000
Subject: [llvm-commits] [test-suite] r107082 - in
 /test-suite/trunk/SingleSource/Benchmarks/Misc: perlin.c
 perlin.reference_output.small
Message-ID: <20100628221000.F3DC02A6C12C@llvm.org>

Author: stoklund
Date: Mon Jun 28 17:10:00 2010
New Revision: 107082

URL: http://llvm.org/viewvc/llvm-project?rev=107082&view=rev
Log:
Speed up test for SMALL_TEST_SIZE

Added:
    test-suite/trunk/SingleSource/Benchmarks/Misc/perlin.reference_output.small
Modified:
    test-suite/trunk/SingleSource/Benchmarks/Misc/perlin.c

Modified: test-suite/trunk/SingleSource/Benchmarks/Misc/perlin.c
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/Benchmarks/Misc/perlin.c?rev=107082&r1=107081&r2=107082&view=diff
==============================================================================
--- test-suite/trunk/SingleSource/Benchmarks/Misc/perlin.c (original)
+++ test-suite/trunk/SingleSource/Benchmarks/Misc/perlin.c Mon Jun 28 17:10:00 2010
@@ -65,9 +65,15 @@
   init();
   
   double x, y, z, sum = 0.0;
+#ifdef SMALL_PROBLEM_SIZE
+  for (x = -11352.57; x < 23561.57; x += 1.235)
+    for (y = -346.1235; y < 124.124; y += 2.4325)
+      for (z = -156.235; y < 23.2345; y += 2.45)
+#else
   for (x = -11352.57; x < 23561.57; x += .1235)
     for (y = -346.1235; y < 124.124; y += 1.4325)
       for (z = -156.235; y < 23.2345; y += 2.45)
+#endif
         sum += noise(x, y, z);
   
   printf("%e\n", sum);

Added: test-suite/trunk/SingleSource/Benchmarks/Misc/perlin.reference_output.small
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/Benchmarks/Misc/perlin.reference_output.small?rev=107082&view=auto
==============================================================================
--- test-suite/trunk/SingleSource/Benchmarks/Misc/perlin.reference_output.small (added)
+++ test-suite/trunk/SingleSource/Benchmarks/Misc/perlin.reference_output.small Mon Jun 28 17:10:00 2010
@@ -0,0 +1,2 @@
+2.748063e+01
+exit 0




From stoklund at 2pi.dk  Mon Jun 28 17:10:04 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Mon, 28 Jun 2010 22:10:04 -0000
Subject: [llvm-commits] [test-suite] r107083 - in
 /test-suite/trunk/SingleSource/Benchmarks/Adobe-C++: functionobjects.cpp
 loop_unroll.cpp simple_types_constant_folding.cpp
 simple_types_loop_invariant.cpp stepanov_abstraction.cpp
 stepanov_vector.cpp
Message-ID: <20100628221004.385DF2A6C12E@llvm.org>

Author: stoklund
Date: Mon Jun 28 17:10:04 2010
New Revision: 107083

URL: http://llvm.org/viewvc/llvm-project?rev=107083&view=rev
Log:
Speed up benchmarks for SMALL_PROBLEM_SIZE.

Some of these C++ benchmarks suffer significantly under -O0, so some have been
scaled by a factor 100. The aim is approx 1s runtime for X86 -O0.

Modified:
    test-suite/trunk/SingleSource/Benchmarks/Adobe-C++/functionobjects.cpp
    test-suite/trunk/SingleSource/Benchmarks/Adobe-C++/loop_unroll.cpp
    test-suite/trunk/SingleSource/Benchmarks/Adobe-C++/simple_types_constant_folding.cpp
    test-suite/trunk/SingleSource/Benchmarks/Adobe-C++/simple_types_loop_invariant.cpp
    test-suite/trunk/SingleSource/Benchmarks/Adobe-C++/stepanov_abstraction.cpp
    test-suite/trunk/SingleSource/Benchmarks/Adobe-C++/stepanov_vector.cpp

Modified: test-suite/trunk/SingleSource/Benchmarks/Adobe-C++/functionobjects.cpp
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/Benchmarks/Adobe-C%2B%2B/functionobjects.cpp?rev=107083&r1=107082&r2=107083&view=diff
==============================================================================
--- test-suite/trunk/SingleSource/Benchmarks/Adobe-C++/functionobjects.cpp (original)
+++ test-suite/trunk/SingleSource/Benchmarks/Adobe-C++/functionobjects.cpp Mon Jun 28 17:10:04 2010
@@ -247,7 +247,11 @@
 int main(int argc, char* argv[])
 {
 	int i;
+#ifdef SMALL_PROBLEM_SIZE
+	int iterations = (1 < argc) ? atoi(argv[1]) : 30; // number of iterations
+#else
 	int iterations = (1 < argc) ? atoi(argv[1]) : 300; // number of iterations
+#endif
 	int tablesize = (2 < argc) ? atoi(argv[2]) : 10000; // size of array
 	
 	

Modified: test-suite/trunk/SingleSource/Benchmarks/Adobe-C++/loop_unroll.cpp
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/Benchmarks/Adobe-C%2B%2B/loop_unroll.cpp?rev=107083&r1=107082&r2=107083&view=diff
==============================================================================
--- test-suite/trunk/SingleSource/Benchmarks/Adobe-C++/loop_unroll.cpp (original)
+++ test-suite/trunk/SingleSource/Benchmarks/Adobe-C++/loop_unroll.cpp Mon Jun 28 17:10:04 2010
@@ -39,7 +39,11 @@
 
 // this constant may need to be adjusted to give reasonable minimum times
 // For best results, times should be about 1.0 seconds for the minimum test run
+#ifdef SMALL_PROBLEM_SIZE
+int iterations = 50;
+#else
 int iterations = 1000;
+#endif
 
 // 8000 items, or between 8k and 64k of data
 // this is intended to remain within the L2 cache of most common CPUs

Modified: test-suite/trunk/SingleSource/Benchmarks/Adobe-C++/simple_types_constant_folding.cpp
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/Benchmarks/Adobe-C%2B%2B/simple_types_constant_folding.cpp?rev=107083&r1=107082&r2=107083&view=diff
==============================================================================
--- test-suite/trunk/SingleSource/Benchmarks/Adobe-C++/simple_types_constant_folding.cpp (original)
+++ test-suite/trunk/SingleSource/Benchmarks/Adobe-C++/simple_types_constant_folding.cpp Mon Jun 28 17:10:04 2010
@@ -57,7 +57,11 @@
 
 // this constant may need to be adjusted to give reasonable minimum times
 // For best results, times should be about 1.0 seconds for the minimum test run
+#ifdef SMALL_PROBLEM_SIZE
+int base_iterations = 100;
+#else
 int base_iterations = 5000;
+#endif
 int iterations = base_iterations;
 
 

Modified: test-suite/trunk/SingleSource/Benchmarks/Adobe-C++/simple_types_loop_invariant.cpp
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/Benchmarks/Adobe-C%2B%2B/simple_types_loop_invariant.cpp?rev=107083&r1=107082&r2=107083&view=diff
==============================================================================
--- test-suite/trunk/SingleSource/Benchmarks/Adobe-C++/simple_types_loop_invariant.cpp (original)
+++ test-suite/trunk/SingleSource/Benchmarks/Adobe-C++/simple_types_loop_invariant.cpp Mon Jun 28 17:10:04 2010
@@ -32,8 +32,11 @@
 
 // this constant may need to be adjusted to give reasonable minimum times
 // For best results, times should be about 1.0 seconds for the minimum test run
+#ifdef SMALL_PROBLEM_SIZE
+int iterations = 50;
+#else
 int iterations = 1000;
-
+#endif
 
 // 8000 items, or between 8k and 64k of data
 // this is intended to remain within the L2 cache of most common CPUs

Modified: test-suite/trunk/SingleSource/Benchmarks/Adobe-C++/stepanov_abstraction.cpp
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/Benchmarks/Adobe-C%2B%2B/stepanov_abstraction.cpp?rev=107083&r1=107082&r2=107083&view=diff
==============================================================================
--- test-suite/trunk/SingleSource/Benchmarks/Adobe-C++/stepanov_abstraction.cpp (original)
+++ test-suite/trunk/SingleSource/Benchmarks/Adobe-C++/stepanov_abstraction.cpp Mon Jun 28 17:10:04 2010
@@ -166,7 +166,7 @@
 // this constant may need to be adjusted to give reasonable minimum times
 // For best results, times should be about 1.0 seconds for the minimum test run
 #ifdef SMALL_PROBLEM_SIZE
-int iterations = 10000;
+int iterations = 100;
 #else
 int iterations = 200000;
 #endif

Modified: test-suite/trunk/SingleSource/Benchmarks/Adobe-C++/stepanov_vector.cpp
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/Benchmarks/Adobe-C%2B%2B/stepanov_vector.cpp?rev=107083&r1=107082&r2=107083&view=diff
==============================================================================
--- test-suite/trunk/SingleSource/Benchmarks/Adobe-C++/stepanov_vector.cpp (original)
+++ test-suite/trunk/SingleSource/Benchmarks/Adobe-C++/stepanov_vector.cpp Mon Jun 28 17:10:04 2010
@@ -36,7 +36,11 @@
 
 // this constant may need to be adjusted to give reasonable minimum times
 // For best results, times should be about 1.0 seconds for the minimum test run
+#ifdef SMALL_PROBLEM_SIZE
+int iterations = 600;
+#else
 int iterations = 60000;
+#endif
 
 // 2000 items, or about 16k of data
 // this is intended to remain within the L2 cache of most common CPUs




From stoklund at 2pi.dk  Mon Jun 28 17:10:07 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Mon, 28 Jun 2010 22:10:07 -0000
Subject: [llvm-commits] [test-suite] r107084 - in
 /test-suite/trunk/MultiSource/Benchmarks/PAQ8p: Makefile
 paq8p.reference_output.small small.in
Message-ID: <20100628221007.33F902A6C12D@llvm.org>

Author: stoklund
Date: Mon Jun 28 17:10:07 2010
New Revision: 107084

URL: http://llvm.org/viewvc/llvm-project?rev=107084&view=rev
Log:
Speed up test for SMALL_PROBLEM_SIZE by using a smaller input file.

Added:
    test-suite/trunk/MultiSource/Benchmarks/PAQ8p/small.in
Modified:
    test-suite/trunk/MultiSource/Benchmarks/PAQ8p/Makefile
    test-suite/trunk/MultiSource/Benchmarks/PAQ8p/paq8p.reference_output.small

Modified: test-suite/trunk/MultiSource/Benchmarks/PAQ8p/Makefile
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/MultiSource/Benchmarks/PAQ8p/Makefile?rev=107084&r1=107083&r2=107084&view=diff
==============================================================================
--- test-suite/trunk/MultiSource/Benchmarks/PAQ8p/Makefile (original)
+++ test-suite/trunk/MultiSource/Benchmarks/PAQ8p/Makefile Mon Jun 28 17:10:07 2010
@@ -4,7 +4,7 @@
 CPPFLAGS += -DNOASM -DLLVM
 LDFLAGS = -lstdc++ -lm
 ifdef SMALL_PROBLEM_SIZE
-RUN_OPTIONS = -1 $(PROJ_SRC_DIR)/file1.in
+RUN_OPTIONS = -1 $(PROJ_SRC_DIR)/small.in
 else
 RUN_OPTIONS = -4 $(PROJ_SRC_DIR)/file1.in
 endif

Modified: test-suite/trunk/MultiSource/Benchmarks/PAQ8p/paq8p.reference_output.small
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/MultiSource/Benchmarks/PAQ8p/paq8p.reference_output.small?rev=107084&r1=107083&r2=107084&view=diff
==============================================================================
--- test-suite/trunk/MultiSource/Benchmarks/PAQ8p/paq8p.reference_output.small (original)
+++ test-suite/trunk/MultiSource/Benchmarks/PAQ8p/paq8p.reference_output.small Mon Jun 28 17:10:07 2010
@@ -1,6 +1,6 @@
 Creating archive with 1 file(s)...
-file1.in 262144 ->         4096        8192       12288       16384       20480       24576       28672       32768       36864       40960       45056       49152       53248       57344       61440       65536       69632       73728       77824       81920       86016       90112       94208       98304      102400      106496      110592      114688      118784      122880      126976      131072      135168      139264      143360      147456      151552      155648      159744      163840      1679
 36      172032      176128      180224      184320      188416      192512      196608      200704      204800      208896      212992      217088      221184      225280      229376      233472      237568      241664      245760      249856      253952      258048      262144262360      
-262144 -> 262389
+small.in 2048 -> 2058        
+2048 -> 2085
 Extracting 1 file(s) from archive -1
-Comparing file1.in 262144 ->         4096        8192       12288       16384       20480       24576       28672       32768       36864       40960       45056       49152       53248       57344       61440       65536       69632       73728       77824       81920       86016       90112       94208       98304      102400      106496      110592      114688      118784      122880      126976      131072      135168      139264      143360      147456      151552      155648      159744      163840
       167936      172032      176128      180224      184320      188416      192512      196608      200704      204800      208896      212992      217088      221184      225280      229376      233472      237568      241664      245760      249856      253952      258048identical   
+Comparing small.in 2048 -> identical   
 exit 0

Added: test-suite/trunk/MultiSource/Benchmarks/PAQ8p/small.in
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/MultiSource/Benchmarks/PAQ8p/small.in?rev=107084&view=auto
==============================================================================
Binary files test-suite/trunk/MultiSource/Benchmarks/PAQ8p/small.in (added) and test-suite/trunk/MultiSource/Benchmarks/PAQ8p/small.in Mon Jun 28 17:10:07 2010 differ




From dpatel at apple.com  Mon Jun 28 17:22:47 2010
From: dpatel at apple.com (Devang Patel)
Date: Mon, 28 Jun 2010 22:22:47 -0000
Subject: [llvm-commits] [llvm] r107085 - in /llvm/trunk:
 lib/CodeGen/AsmPrinter/DIE.cpp lib/CodeGen/AsmPrinter/DwarfDebug.cpp
 test/FrontendC/2010-06-28-DbgEntryPC.c
Message-ID: <20100628222247.BF4DB2A6C12C@llvm.org>

Author: dpatel
Date: Mon Jun 28 17:22:47 2010
New Revision: 107085

URL: http://llvm.org/viewvc/llvm-project?rev=107085&view=rev
Log:
Use DW_FORM_addr for DW_AT_entry_pc.

Added:
    llvm/trunk/test/FrontendC/2010-06-28-DbgEntryPC.c
Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp?rev=107085&r1=107084&r2=107085&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DIE.cpp Mon Jun 28 17:22:47 2010
@@ -201,6 +201,7 @@
   case dwarf::DW_FORM_data8: Size = 8; break;
   case dwarf::DW_FORM_udata: Asm->EmitULEB128(Integer); return;
   case dwarf::DW_FORM_sdata: Asm->EmitSLEB128(Integer); return;
+  case dwarf::DW_FORM_addr:  Size = Asm->getTargetData().getPointerSize(); break;
   default: llvm_unreachable("DIE Value form not supported yet");
   }
   Asm->OutStreamer.EmitIntValue(Integer, Size, 0/*addrspace*/);
@@ -221,6 +222,7 @@
   case dwarf::DW_FORM_data8: return sizeof(int64_t);
   case dwarf::DW_FORM_udata: return MCAsmInfo::getULEB128Size(Integer);
   case dwarf::DW_FORM_sdata: return MCAsmInfo::getSLEB128Size(Integer);
+  case dwarf::DW_FORM_addr:  return AP->getTargetData().getPointerSize();
   default: llvm_unreachable("DIE Value form not supported yet"); break;
   }
   return 0;

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=107085&r1=107084&r2=107085&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Mon Jun 28 17:22:47 2010
@@ -1792,7 +1792,7 @@
   addString(Die, dwarf::DW_AT_name, dwarf::DW_FORM_string, FN);
   // Use DW_AT_entry_pc instead of DW_AT_low_pc/DW_AT_high_pc pair. This
   // simplifies debug range entries.
-  addUInt(Die, dwarf::DW_AT_entry_pc, dwarf::DW_FORM_data4, 0);
+  addUInt(Die, dwarf::DW_AT_entry_pc, dwarf::DW_FORM_addr, 0);
   // DW_AT_stmt_list is a offset of line number information for this
   // compile unit in debug_line section. It is always zero when only one
   // compile unit is emitted in one object file.

Added: llvm/trunk/test/FrontendC/2010-06-28-DbgEntryPC.c
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/2010-06-28-DbgEntryPC.c?rev=107085&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC/2010-06-28-DbgEntryPC.c (added)
+++ llvm/trunk/test/FrontendC/2010-06-28-DbgEntryPC.c Mon Jun 28 17:22:47 2010
@@ -0,0 +1,48 @@
+// RUN: %llvmgcc -S -O2 -g %s -o - | llc -O2 | FileCheck %s
+// Use DW_FORM_addr for DW_AT_entry_pc.
+// Radar 8094785
+
+// CHECK:	.byte	17                      ## DW_TAG_compile_unit
+// CHECK-NEXT:	.byte	1                       ## DW_CHILDREN_yes
+// CHECK-NEXT:	.byte	37                      ## DW_AT_producer
+// CHECK-NEXT:	.byte	8                       ## DW_FORM_string
+// CHECK-NEXT:	.byte	19                      ## DW_AT_language
+// CHECK-NEXT:	.byte	11                      ## DW_FORM_data1
+// CHECK-NEXT:	.byte	3                       ## DW_AT_name
+// CHECK-NEXT:	.byte	8                       ## DW_FORM_string
+// CHECK-NEXT:	.byte	82                      ## DW_AT_entry_pc
+// CHECK-NEXT:	.byte	1                       ## DW_FORM_addr
+// CHECK-NEXT:	.byte	16                      ## DW_AT_stmt_list
+// CHECK-NEXT:	.byte	6                       ## DW_FORM_data4
+// CHECK-NEXT:	.byte	27                      ## DW_AT_comp_dir
+// CHECK-NEXT:	.byte	8                       ## DW_FORM_string
+// CHECK-NEXT:	.byte	225                     ## DW_AT_APPLE_optimized
+
+struct a {
+  int c;
+  struct a *d;
+};
+
+int ret;
+
+void foo(int x) __attribute__((noinline));
+void *bar(struct a *b) __attribute__((noinline));
+
+void foo(int x)
+{
+  ret = x;
+}
+
+void *bar(struct a *b) {
+  foo(b->c);
+  return b;
+}
+
+int main(int argc, char *argv[]) {
+  struct a e;
+  e.c = 4;
+  e.d = &e;
+
+  (void)bar(&e);
+  return ret;
+}




From bob.wilson at apple.com  Mon Jun 28 17:23:17 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Mon, 28 Jun 2010 22:23:17 -0000
Subject: [llvm-commits] [llvm] r107086 -
	/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
Message-ID: <20100628222317.495762A6C12C@llvm.org>

Author: bwilson
Date: Mon Jun 28 17:23:17 2010
New Revision: 107086

URL: http://llvm.org/viewvc/llvm-project?rev=107086&view=rev
Log:
Make the ARMCodeEmitter identify Thumb functions via ARMFunctionInfo instead
of the Subtarget.

Modified:
    llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=107086&r1=107085&r2=107086&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Mon Jun 28 17:23:17 2010
@@ -55,6 +55,7 @@
     const std::vector<MachineConstantPoolEntry> *MCPEs;
     const std::vector<MachineJumpTableEntry> *MJTEs;
     bool IsPIC;
+    bool IsThumb;
 
     void getAnalysisUsage(AnalysisUsage &AU) const {
       AU.addRequired<MachineModuleInfo>();
@@ -67,8 +68,8 @@
       : MachineFunctionPass(&ID), JTI(0),
         II((const ARMInstrInfo *)tm.getInstrInfo()),
         TD(tm.getTargetData()), TM(tm),
-    MCE(mce), MCPEs(0), MJTEs(0),
-    IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
+        MCE(mce), MCPEs(0), MJTEs(0),
+        IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
 
     /// getBinaryCodeForInstr - This function, generated by the
     /// CodeEmitterGenerator using TableGen, produces the binary encoding for
@@ -199,6 +200,7 @@
   MJTEs = 0;
   if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
   IsPIC = TM.getRelocationModel() == Reloc::PIC_;
+  IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
   JTI->Initialize(MF, IsPIC);
   MMI = &getAnalysis<MachineModuleInfo>();
   MCE.setModuleInfo(MMI);
@@ -1635,7 +1637,7 @@
   unsigned Imm3 = (Imm >> 4) & 0x7;
   unsigned Imm4 = Imm & 0xf;
   Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
-  if (Subtarget->isThumb())
+  if (IsThumb)
     Binary = convertNEONDataProcToThumb(Binary);
   emitWordLE(Binary);
 }
@@ -1649,7 +1651,7 @@
   if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
     ++OpIdx;
   Binary |= encodeNEONRm(MI, OpIdx);
-  if (Subtarget->isThumb())
+  if (IsThumb)
     Binary = convertNEONDataProcToThumb(Binary);
   // FIXME: This does not handle VDUPfdf or VDUPfqf.
   emitWordLE(Binary);
@@ -1667,7 +1669,7 @@
   if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
     ++OpIdx;
   Binary |= encodeNEONRm(MI, OpIdx);
-  if (Subtarget->isThumb())
+  if (IsThumb)
     Binary = convertNEONDataProcToThumb(Binary);
   // FIXME: This does not handle VMOVDneon or VMOVQ.
   emitWordLE(Binary);




From dalej at apple.com  Mon Jun 28 17:31:52 2010
From: dalej at apple.com (Dale Johannesen)
Date: Mon, 28 Jun 2010 22:31:52 -0000
Subject: [llvm-commits] [llvm] r107088 -
	/llvm/trunk/test/FrontendC/2010-06-28-nowarn.c
Message-ID: <20100628223152.C95AD2A6C12C@llvm.org>

Author: johannes
Date: Mon Jun 28 17:31:52 2010
New Revision: 107088

URL: http://llvm.org/viewvc/llvm-project?rev=107088&view=rev
Log:
Attempt to fix XTARGET.


Modified:
    llvm/trunk/test/FrontendC/2010-06-28-nowarn.c

Modified: llvm/trunk/test/FrontendC/2010-06-28-nowarn.c
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/2010-06-28-nowarn.c?rev=107088&r1=107087&r2=107088&view=diff
==============================================================================
--- llvm/trunk/test/FrontendC/2010-06-28-nowarn.c (original)
+++ llvm/trunk/test/FrontendC/2010-06-28-nowarn.c Mon Jun 28 17:31:52 2010
@@ -1,7 +1,7 @@
 // RUN: %llvmgcc %s -c -m32 -fasm-blocks -o /dev/null
 // This should not warn about unreferenced label. 7729514.
 // XFAIL: *
-// XTARGET: i386,i686,x86,darwin
+// XTARGET: i386*darwin,i686*darwin,x86*darwin
 
 void quarterAsm(int array[], int len)
 {




From dalej at apple.com  Mon Jun 28 17:45:33 2010
From: dalej at apple.com (Dale Johannesen)
Date: Mon, 28 Jun 2010 22:45:33 -0000
Subject: [llvm-commits] [llvm] r107090 -
	/llvm/trunk/test/FrontendC/2010-06-28-nowarn.c
Message-ID: <20100628224533.C8E3E2A6C12C@llvm.org>

Author: johannes
Date: Mon Jun 28 17:45:33 2010
New Revision: 107090

URL: http://llvm.org/viewvc/llvm-project?rev=107090&view=rev
Log:
Refix XTARGET.  Previous attempt matches on powerpc-apple-darwin,
although I don't see why.


Modified:
    llvm/trunk/test/FrontendC/2010-06-28-nowarn.c

Modified: llvm/trunk/test/FrontendC/2010-06-28-nowarn.c
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/2010-06-28-nowarn.c?rev=107090&r1=107089&r2=107090&view=diff
==============================================================================
--- llvm/trunk/test/FrontendC/2010-06-28-nowarn.c (original)
+++ llvm/trunk/test/FrontendC/2010-06-28-nowarn.c Mon Jun 28 17:45:33 2010
@@ -1,7 +1,7 @@
 // RUN: %llvmgcc %s -c -m32 -fasm-blocks -o /dev/null
 // This should not warn about unreferenced label. 7729514.
 // XFAIL: *
-// XTARGET: i386*darwin,i686*darwin,x86*darwin
+// XTARGET: i386-apple-darwin,x86_64-apple-darwin,i686-apple-darwin
 
 void quarterAsm(int array[], int len)
 {




From grosbach at apple.com  Mon Jun 28 18:11:33 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 28 Jun 2010 23:11:33 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r107093 -
	/llvm-gcc-4.2/trunk/build_gcc
Message-ID: <20100628231133.644C72A6C12D@llvm.org>

Author: grosbach
Date: Mon Jun 28 18:11:33 2010
New Revision: 107093

URL: http://llvm.org/viewvc/llvm-project?rev=107093&view=rev
Log:
typo

Modified:
    llvm-gcc-4.2/trunk/build_gcc

Modified: llvm-gcc-4.2/trunk/build_gcc
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/build_gcc?rev=107093&r1=107092&r2=107093&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/build_gcc (original)
+++ llvm-gcc-4.2/trunk/build_gcc Mon Jun 28 18:11:33 2010
@@ -376,7 +376,7 @@
      CXXFLAGS="$CFLAGS $DEFAULT_TARGET" || exit 1
    make $MAKEFLAGS DESTDIR=$DIR/dst-$BUILD-$t install-gcc install-target \
      CFLAGS="$CFLAGS $DEFAULT_TARGET" \
-     CXXFLAGS="$CFLAGS $DEFAULT_TARGET" | exit 1
+     CXXFLAGS="$CFLAGS $DEFAULT_TARGET" || exit 1
 
    # Add the compiler we just built to the path.
    # LLVM LOCAL Support for non /usr $DEST_ROOT




From bob.wilson at apple.com  Mon Jun 28 18:40:25 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Mon, 28 Jun 2010 23:40:25 -0000
Subject: [llvm-commits] [llvm] r107097 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/DAGCombiner.cpp
 test/CodeGen/ARM/2010-06-28-DAGCombineUndef.ll
Message-ID: <20100628234025.871FE2A6C12C@llvm.org>

Author: bwilson
Date: Mon Jun 28 18:40:25 2010
New Revision: 107097

URL: http://llvm.org/viewvc/llvm-project?rev=107097&view=rev
Log:
Unlike other targets, ARM now uses BUILD_VECTORs post-legalization so they
can't be changed arbitrarily by the DAGCombiner without checking if it is
running after legalization.

Added:
    llvm/trunk/test/CodeGen/ARM/2010-06-28-DAGCombineUndef.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=107097&r1=107096&r2=107097&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Jun 28 18:40:25 2010
@@ -2322,7 +2322,8 @@
   }
 
   // fold (or x, undef) -> -1
-  if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) {
+  if (!LegalOperations &&
+      (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) {
     EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
     return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
   }

Added: llvm/trunk/test/CodeGen/ARM/2010-06-28-DAGCombineUndef.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-06-28-DAGCombineUndef.ll?rev=107097&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2010-06-28-DAGCombineUndef.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/2010-06-28-DAGCombineUndef.ll Mon Jun 28 18:40:25 2010
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march=arm -mattr=+neon
+
+define void @main() nounwind {
+entry:
+  store <2 x i64> undef, <2 x i64>* undef, align 16
+  %0 = load <16 x i8>* undef, align 16            ; <<16 x i8>> [#uses=1]
+  %1 = or <16 x i8> zeroinitializer, %0           ; <<16 x i8>> [#uses=1]
+  store <16 x i8> %1, <16 x i8>* undef, align 16
+  ret void
+}




From dpatel at apple.com  Mon Jun 28 19:04:40 2010
From: dpatel at apple.com (Devang Patel)
Date: Tue, 29 Jun 2010 00:04:40 -0000
Subject: [llvm-commits] [llvm] r107103 -
	/llvm/trunk/test/FrontendC/2010-06-28-DbgEntryPC.c
Message-ID: <20100629000440.742252A6C12C@llvm.org>

Author: dpatel
Date: Mon Jun 28 19:04:40 2010
New Revision: 107103

URL: http://llvm.org/viewvc/llvm-project?rev=107103&view=rev
Log:
The comment string does not match for all targets. PowerPC uses ;.

Modified:
    llvm/trunk/test/FrontendC/2010-06-28-DbgEntryPC.c

Modified: llvm/trunk/test/FrontendC/2010-06-28-DbgEntryPC.c
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/2010-06-28-DbgEntryPC.c?rev=107103&r1=107102&r2=107103&view=diff
==============================================================================
--- llvm/trunk/test/FrontendC/2010-06-28-DbgEntryPC.c (original)
+++ llvm/trunk/test/FrontendC/2010-06-28-DbgEntryPC.c Mon Jun 28 19:04:40 2010
@@ -2,6 +2,7 @@
 // Use DW_FORM_addr for DW_AT_entry_pc.
 // Radar 8094785
 
+// XTARGET: x86,i386,i686
 // CHECK:	.byte	17                      ## DW_TAG_compile_unit
 // CHECK-NEXT:	.byte	1                       ## DW_CHILDREN_yes
 // CHECK-NEXT:	.byte	37                      ## DW_AT_producer




From bob.wilson at apple.com  Mon Jun 28 19:26:14 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Tue, 29 Jun 2010 00:26:14 -0000
Subject: [llvm-commits] [llvm] r107107 -
	/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
Message-ID: <20100629002614.0B0982A6C12C@llvm.org>

Author: bwilson
Date: Mon Jun 28 19:26:13 2010
New Revision: 107107

URL: http://llvm.org/viewvc/llvm-project?rev=107107&view=rev
Log:
Fix Thumb encoding of VMOV (scalar to ARM core register).  The encoding is
the same as ARM except that the condition code field is always set to ARMCC::AL.

Modified:
    llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=107107&r1=107106&r2=107107&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Mon Jun 28 19:26:13 2010
@@ -1600,7 +1600,7 @@
   unsigned Binary = getBinaryCodeForInstr(MI);
 
   // Set the conditional execution predicate
-  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
+  Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
 
   unsigned RegT = MI.getOperand(0).getReg();
   RegT = ARMRegisterInfo::getRegisterNumbering(RegT);




From bruno.cardoso at gmail.com  Mon Jun 28 19:36:02 2010
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Tue, 29 Jun 2010 00:36:02 -0000
Subject: [llvm-commits] [llvm] r107108 - in /llvm/trunk:
 lib/Target/X86/X86InstrSSE.td test/MC/AsmParser/X86/x86_32-encoding.s
 test/MC/AsmParser/X86/x86_64-encoding.s
Message-ID: <20100629003603.3272D2A6C12C@llvm.org>

Author: bruno
Date: Mon Jun 28 19:36:02 2010
New Revision: 107108

URL: http://llvm.org/viewvc/llvm-project?rev=107108&view=rev
Log:
Described the missing AVX forms of SSE2 convert instructions

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
    llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=107108&r1=107107&r2=107108&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Jun 28 19:36:02 2010
@@ -944,6 +944,17 @@
 
 /// SSE 2 Only
 
+// Convert scalar double to scalar single
+let isAsmParserOnly = 1 in {
+def VCVTSD2SSrr  : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
+                       (ins FR64:$src1, FR64:$src2),
+                      "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
+                      VEX_4V;
+def VCVTSD2SSrm  : I<0x5A, MRMSrcMem, (outs FR32:$dst),
+                       (ins FR64:$src1, f64mem:$src2),
+                      "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
+                      []>, XD, Requires<[HasAVX, HasSSE2, OptForSize]>, VEX_4V;
+}
 def CVTSD2SSrr  : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
                       "cvtsd2ss\t{$src, $dst|$dst, $src}",
                       [(set FR32:$dst, (fround FR64:$src))]>;
@@ -952,12 +963,27 @@
                       [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
                   Requires<[HasSSE2, OptForSize]>;
 
-def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
-                     "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
-def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
-                     "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
-
-// SSE2 instructions with XS prefix
+let isAsmParserOnly = 1 in
+defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
+                    int_x86_sse2_cvtsd2ss, f64mem, load,
+                    "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}">,
+                    XS, VEX_4V;
+let Constraints = "$src1 = $dst" in
+defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
+             int_x86_sse2_cvtsd2ss, f64mem, load,
+             "cvtsd2ss\t{$src2, $dst|$dst, $src2}">, XS;
+
+// Convert scalar single to scalar double
+let isAsmParserOnly = 1 in { // SSE2 instructions with XS prefix
+def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
+                    (ins FR32:$src1, FR32:$src2),
+                    "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
+                    []>, XS, Requires<[HasAVX, HasSSE2]>, VEX_4V;
+def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
+                    (ins FR32:$src1, f32mem:$src2),
+                    "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
+                    []>, XS, VEX_4V, Requires<[HasAVX, HasSSE2, OptForSize]>;
+}
 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
                    "cvtss2sd\t{$src, $dst|$dst, $src}",
                    [(set FR64:$dst, (fextend FR32:$src))]>, XS,
@@ -967,11 +993,51 @@
                    [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
                  Requires<[HasSSE2, OptForSize]>;
 
+let isAsmParserOnly = 1 in {
+def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
+                      (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
+                    "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
+                    [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
+                                       VR128:$src2))]>, XS, VEX_4V,
+                    Requires<[HasAVX, HasSSE2]>;
+def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
+                      (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
+                    "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
+                    [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
+                                       (load addr:$src2)))]>, XS, VEX_4V,
+                    Requires<[HasAVX, HasSSE2]>;
+}
+let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
+def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
+                      (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
+                    "cvtss2sd\t{$src2, $dst|$dst, $src2}",
+                    [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
+                                       VR128:$src2))]>, XS,
+                    Requires<[HasSSE2]>;
+def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
+                      (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
+                    "cvtss2sd\t{$src2, $dst|$dst, $src2}",
+                    [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
+                                       (load addr:$src2)))]>, XS,
+                    Requires<[HasSSE2]>;
+}
+
 def : Pat<(extloadf32 addr:$src),
           (CVTSS2SDrr (MOVSSrm addr:$src))>,
       Requires<[HasSSE2, OptForSpeed]>;
 
-// SSE2 instructions without OpSize prefix
+// Convert doubleword to packed single/double fp
+let isAsmParserOnly = 1 in { // SSE2 instructions without OpSize prefix
+def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
+                       "vcvtdq2ps\t{$src, $dst|$dst, $src}",
+                       [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
+                     TB, VEX, Requires<[HasAVX, HasSSE2]>;
+def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
+                      "vcvtdq2ps\t{$src, $dst|$dst, $src}",
+                      [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
+                                        (bitconvert (memopv2i64 addr:$src))))]>,
+                     TB, VEX, Requires<[HasAVX, HasSSE2]>;
+}
 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
                        "cvtdq2ps\t{$src, $dst|$dst, $src}",
                        [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
@@ -982,7 +1048,18 @@
                                         (bitconvert (memopv2i64 addr:$src))))]>,
                      TB, Requires<[HasSSE2]>;
 
-// SSE2 instructions with XS prefix
+// FIXME: why the non-intrinsic version is described as SSE3?
+let isAsmParserOnly = 1 in { // SSE2 instructions with XS prefix
+def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
+                       "vcvtdq2pd\t{$src, $dst|$dst, $src}",
+                       [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
+                     XS, VEX, Requires<[HasAVX, HasSSE2]>;
+def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
+                       "vcvtdq2pd\t{$src, $dst|$dst, $src}",
+                       [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
+                                        (bitconvert (memopv2i64 addr:$src))))]>,
+                     XS, VEX, Requires<[HasAVX, HasSSE2]>;
+}
 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
                        "cvtdq2pd\t{$src, $dst|$dst, $src}",
                        [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
@@ -993,6 +1070,29 @@
                                         (bitconvert (memopv2i64 addr:$src))))]>,
                      XS, Requires<[HasSSE2]>;
 
+// Convert packed single/double fp to doubleword
+let isAsmParserOnly = 1 in {
+def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
+                     "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
+def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
+                     "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
+}
+def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
+                     "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
+def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
+                     "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
+
+let isAsmParserOnly = 1 in {
+def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
+                        "cvtps2dq\t{$src, $dst|$dst, $src}",
+                        [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>,
+                        VEX;
+def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
+                         (ins f128mem:$src),
+                         "cvtps2dq\t{$src, $dst|$dst, $src}",
+                         [(set VR128:$dst, (int_x86_sse2_cvtps2dq
+                                            (memop addr:$src)))]>, VEX;
+}
 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
                         "cvtps2dq\t{$src, $dst|$dst, $src}",
                         [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
@@ -1000,12 +1100,54 @@
                          "cvtps2dq\t{$src, $dst|$dst, $src}",
                          [(set VR128:$dst, (int_x86_sse2_cvtps2dq
                                             (memop addr:$src)))]>;
-// SSE2 packed instructions with XS prefix
+
+let isAsmParserOnly = 1 in { // SSE2 packed instructions with XD prefix
+def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
+                       "vcvtpd2dq\t{$src, $dst|$dst, $src}",
+                       [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
+                     XD, VEX, Requires<[HasAVX, HasSSE2]>;
+def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
+                       "vcvtpd2dq\t{$src, $dst|$dst, $src}",
+                       [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
+                                          (memop addr:$src)))]>,
+                     XD, VEX, Requires<[HasAVX, HasSSE2]>;
+}
+def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
+                       "cvtpd2dq\t{$src, $dst|$dst, $src}",
+                       [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
+                     XD, Requires<[HasSSE2]>;
+def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
+                       "cvtpd2dq\t{$src, $dst|$dst, $src}",
+                       [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
+                                          (memop addr:$src)))]>,
+                     XD, Requires<[HasSSE2]>;
+
+
+// Convert with truncation packed single/double fp to doubleword
+let isAsmParserOnly = 1 in { // SSE2 packed instructions with XS prefix
+def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
+                      "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
+def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
+                      "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
+}
 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
                       "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
                       "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
 
+
+let isAsmParserOnly = 1 in {
+def Int_VCVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
+                        "vcvttps2dq\t{$src, $dst|$dst, $src}",
+                        [(set VR128:$dst,
+                              (int_x86_sse2_cvttps2dq VR128:$src))]>,
+                      XS, VEX, Requires<[HasAVX, HasSSE2]>;
+def Int_VCVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
+                        "vcvttps2dq\t{$src, $dst|$dst, $src}",
+                        [(set VR128:$dst, (int_x86_sse2_cvttps2dq
+                                           (memop addr:$src)))]>,
+                      XS, VEX, Requires<[HasAVX, HasSSE2]>;
+}
 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
                         "cvttps2dq\t{$src, $dst|$dst, $src}",
                         [(set VR128:$dst,
@@ -1017,17 +1159,18 @@
                                            (memop addr:$src)))]>,
                       XS, Requires<[HasSSE2]>;
 
-// SSE2 packed instructions with XD prefix
-def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
-                       "cvtpd2dq\t{$src, $dst|$dst, $src}",
-                       [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
-                     XD, Requires<[HasSSE2]>;
-def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
-                       "cvtpd2dq\t{$src, $dst|$dst, $src}",
-                       [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
-                                          (memop addr:$src)))]>,
-                     XD, Requires<[HasSSE2]>;
-
+let isAsmParserOnly = 1 in {
+def Int_VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst),
+                            (ins VR128:$src),
+                          "cvttpd2dq\t{$src, $dst|$dst, $src}",
+                       [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>,
+                       VEX;
+def Int_VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst),
+                          (ins f128mem:$src),
+                          "cvttpd2dq\t{$src, $dst|$dst, $src}",
+                          [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
+                                             (memop addr:$src)))]>, VEX;
+}
 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
                           "cvttpd2dq\t{$src, $dst|$dst, $src}",
                        [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
@@ -1036,12 +1179,31 @@
                           [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
                                              (memop addr:$src)))]>;
 
-// SSE2 instructions without OpSize prefix
+// Convert packed single to packed double
+let isAsmParserOnly = 1 in { // SSE2 instructions without OpSize prefix
+def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
+                       "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX,
+                       Requires<[HasAVX]>;
+def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
+                       "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX,
+                       Requires<[HasAVX]>;
+}
 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
                        "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
                        "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
 
+let isAsmParserOnly = 1 in {
+def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
+                       "cvtps2pd\t{$src, $dst|$dst, $src}",
+                       [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
+                     VEX, Requires<[HasAVX, HasSSE2]>;
+def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
+                       "cvtps2pd\t{$src, $dst|$dst, $src}",
+                       [(set VR128:$dst, (int_x86_sse2_cvtps2pd
+                                          (load addr:$src)))]>,
+                     VEX, Requires<[HasAVX, HasSSE2]>;
+}
 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
                        "cvtps2pd\t{$src, $dst|$dst, $src}",
                        [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
@@ -1052,12 +1214,29 @@
                                           (load addr:$src)))]>,
                      TB, Requires<[HasSSE2]>;
 
+// Convert packed double to packed single
+let isAsmParserOnly = 1 in {
+def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
+                     "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
+// FIXME: the memory form of this instruction should described using
+// use extra asm syntax
+}
 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
                      "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
                      "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
 
 
+let isAsmParserOnly = 1 in {
+def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
+                         "cvtpd2ps\t{$src, $dst|$dst, $src}",
+                        [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
+def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
+                         (ins f128mem:$src),
+                         "cvtpd2ps\t{$src, $dst|$dst, $src}",
+                         [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
+                                            (memop addr:$src)))]>;
+}
 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
                          "cvtpd2ps\t{$src, $dst|$dst, $src}",
                         [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
@@ -1066,33 +1245,6 @@
                          [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
                                             (memop addr:$src)))]>;
 
-// Match intrinsics which expect XMM operand(s).
-// Aliases for intrinsics
-let Constraints = "$src1 = $dst" in {
-def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
-                        (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
-                   "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
-                   [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
-                                      VR128:$src2))]>;
-def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
-                        (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
-                   "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
-                   [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
-                                      (load addr:$src2)))]>;
-def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
-                      (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
-                    "cvtss2sd\t{$src2, $dst|$dst, $src2}",
-                    [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
-                                       VR128:$src2))]>, XS,
-                    Requires<[HasSSE2]>;
-def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
-                      (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
-                    "cvtss2sd\t{$src2, $dst|$dst, $src2}",
-                    [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
-                                       (load addr:$src2)))]>, XS,
-                    Requires<[HasSSE2]>;
-}
-
 //===----------------------------------------------------------------------===//
 // SSE 1 & 2 - Compare Instructions
 //===----------------------------------------------------------------------===//
@@ -1722,9 +1874,6 @@
 ///
 /// And, we have a special variant form for a full-vector intrinsic form.
 ///
-/// These four forms can each have a reg or a mem operand, so there are a
-/// total of eight "instructions".
-///
 multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr,
                            SDNode OpNode,
                            Intrinsic F32Int,

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s?rev=107108&r1=107107&r2=107108&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s Mon Jun 28 19:36:02 2010
@@ -10822,3 +10822,54 @@
 // CHECK: encoding: [0xc5,0xf8,0x5b,0x30]
           vcvtdq2ps  (%eax), %xmm6
 
+// CHECK: vcvtsd2ss  %xmm2, %xmm4, %xmm6
+// CHECK: encoding: [0xc5,0xdb,0x5a,0xf2]
+          vcvtsd2ss  %xmm2, %xmm4, %xmm6
+
+// CHECK: vcvtsd2ss  (%eax), %xmm4, %xmm6
+// CHECK: encoding: [0xc5,0xdb,0x5a,0x30]
+          vcvtsd2ss  (%eax), %xmm4, %xmm6
+
+// CHECK: vcvtps2dq  %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xf9,0x5b,0xda]
+          vcvtps2dq  %xmm2, %xmm3
+
+// CHECK: vcvtps2dq  (%eax), %xmm3
+// CHECK: encoding: [0xc5,0xf9,0x5b,0x18]
+          vcvtps2dq  (%eax), %xmm3
+
+// CHECK: vcvtss2sd  %xmm2, %xmm4, %xmm6
+// CHECK: encoding: [0xc5,0xda,0x5a,0xf2]
+          vcvtss2sd  %xmm2, %xmm4, %xmm6
+
+// CHECK: vcvtss2sd  (%eax), %xmm4, %xmm6
+// CHECK: encoding: [0xc5,0xda,0x5a,0x30]
+          vcvtss2sd  (%eax), %xmm4, %xmm6
+
+// CHECK: vcvtdq2ps  %xmm4, %xmm6
+// CHECK: encoding: [0xc5,0xf8,0x5b,0xf4]
+          vcvtdq2ps  %xmm4, %xmm6
+
+// CHECK: vcvtdq2ps  (%ecx), %xmm4
+// CHECK: encoding: [0xc5,0xf8,0x5b,0x21]
+          vcvtdq2ps  (%ecx), %xmm4
+
+// CHECK: vcvttps2dq  %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xfa,0x5b,0xda]
+          vcvttps2dq  %xmm2, %xmm3
+
+// CHECK: vcvttps2dq  (%eax), %xmm3
+// CHECK: encoding: [0xc5,0xfa,0x5b,0x18]
+          vcvttps2dq  (%eax), %xmm3
+
+// CHECK: vcvtps2pd  %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xf8,0x5a,0xda]
+          vcvtps2pd  %xmm2, %xmm3
+
+// CHECK: vcvtps2pd  (%eax), %xmm3
+// CHECK: encoding: [0xc5,0xf8,0x5a,0x18]
+          vcvtps2pd  (%eax), %xmm3
+
+// CHECK: vcvtpd2ps  %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xf9,0x5a,0xda]
+          vcvtpd2ps  %xmm2, %xmm3

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s?rev=107108&r1=107107&r2=107108&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s Mon Jun 28 19:36:02 2010
@@ -870,3 +870,55 @@
 // CHECK: encoding: [0xc5,0x78,0x5b,0x20]
           vcvtdq2ps  (%rax), %xmm12
 
+// CHECK: vcvtsd2ss  %xmm12, %xmm13, %xmm10
+// CHECK: encoding: [0xc4,0x41,0x13,0x5a,0xd4]
+          vcvtsd2ss  %xmm12, %xmm13, %xmm10
+
+// CHECK: vcvtsd2ss  (%rax), %xmm13, %xmm10
+// CHECK: encoding: [0xc5,0x13,0x5a,0x10]
+          vcvtsd2ss  (%rax), %xmm13, %xmm10
+
+// CHECK: vcvtps2dq  %xmm12, %xmm11
+// CHECK: encoding: [0xc4,0x41,0x79,0x5b,0xdc]
+          vcvtps2dq  %xmm12, %xmm11
+
+// CHECK: vcvtps2dq  (%rax), %xmm11
+// CHECK: encoding: [0xc5,0x79,0x5b,0x18]
+          vcvtps2dq  (%rax), %xmm11
+
+// CHECK: vcvtss2sd  %xmm12, %xmm13, %xmm10
+// CHECK: encoding: [0xc4,0x41,0x12,0x5a,0xd4]
+          vcvtss2sd  %xmm12, %xmm13, %xmm10
+
+// CHECK: vcvtss2sd  (%rax), %xmm13, %xmm10
+// CHECK: encoding: [0xc5,0x12,0x5a,0x10]
+          vcvtss2sd  (%rax), %xmm13, %xmm10
+
+// CHECK: vcvtdq2ps  %xmm13, %xmm10
+// CHECK: encoding: [0xc4,0x41,0x78,0x5b,0xd5]
+          vcvtdq2ps  %xmm13, %xmm10
+
+// CHECK: vcvtdq2ps  (%ecx), %xmm13
+// CHECK: encoding: [0xc5,0x78,0x5b,0x29]
+          vcvtdq2ps  (%ecx), %xmm13
+
+// CHECK: vcvttps2dq  %xmm12, %xmm11
+// CHECK: encoding: [0xc4,0x41,0x7a,0x5b,0xdc]
+          vcvttps2dq  %xmm12, %xmm11
+
+// CHECK: vcvttps2dq  (%rax), %xmm11
+// CHECK: encoding: [0xc5,0x7a,0x5b,0x18]
+          vcvttps2dq  (%rax), %xmm11
+
+// CHECK: vcvtps2pd  %xmm12, %xmm11
+// CHECK: encoding: [0xc4,0x41,0x78,0x5a,0xdc]
+          vcvtps2pd  %xmm12, %xmm11
+
+// CHECK: vcvtps2pd  (%rax), %xmm11
+// CHECK: encoding: [0xc5,0x78,0x5a,0x18]
+          vcvtps2pd  (%rax), %xmm11
+
+// CHECK: vcvtpd2ps  %xmm12, %xmm11
+// CHECK: encoding: [0xc4,0x41,0x79,0x5a,0xdc]
+          vcvtpd2ps  %xmm12, %xmm11
+




From gohman at apple.com  Mon Jun 28 19:50:39 2010
From: gohman at apple.com (Dan Gohman)
Date: Tue, 29 Jun 2010 00:50:39 -0000
Subject: [llvm-commits] [llvm] r107109 - in /llvm/trunk:
 include/llvm/Analysis/AliasAnalysis.h include/llvm/Analysis/Passes.h
 lib/Analysis/AliasAnalysis.cpp lib/Analysis/BasicAliasAnalysis.cpp
 test/Analysis/BasicAA/interprocedural.ll
Message-ID: <20100629005039.39B192A6C12C@llvm.org>

Author: djg
Date: Mon Jun 28 19:50:39 2010
New Revision: 107109

URL: http://llvm.org/viewvc/llvm-project?rev=107109&view=rev
Log:
Add an Intraprocedural form of BasicAliasAnalysis, which aims to
properly handles instructions and arguments defined in different
functions, or across recursive function iterations.

Added:
    llvm/trunk/test/Analysis/BasicAA/interprocedural.ll
Modified:
    llvm/trunk/include/llvm/Analysis/AliasAnalysis.h
    llvm/trunk/include/llvm/Analysis/Passes.h
    llvm/trunk/lib/Analysis/AliasAnalysis.cpp
    llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp

Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/AliasAnalysis.h?rev=107109&r1=107108&r2=107109&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/AliasAnalysis.h (original)
+++ llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Mon Jun 28 19:50:39 2010
@@ -344,10 +344,10 @@
 /// identifiable object.  This returns true for:
 ///    Global Variables and Functions (but not Global Aliases)
 ///    Allocas and Mallocs
-///    ByVal and NoAlias Arguments
-///    NoAlias returns
+///    ByVal and NoAlias Arguments, if Interprocedural is false
+///    NoAlias returns, if Interprocedural is false
 ///
-bool isIdentifiedObject(const Value *V);
+bool isIdentifiedObject(const Value *V, bool Interprocedural = false);
 
 } // End llvm namespace
 

Modified: llvm/trunk/include/llvm/Analysis/Passes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/Passes.h?rev=107109&r1=107108&r2=107109&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/Passes.h (original)
+++ llvm/trunk/include/llvm/Analysis/Passes.h Mon Jun 28 19:50:39 2010
@@ -73,6 +73,14 @@
 
   //===--------------------------------------------------------------------===//
   //
+  // createInterproceduralBasicAliasAnalysisPass - This pass is similar to
+  // baiscaa, except that it properly supports queries to values which live
+  // in different functions.
+  //
+  ImmutablePass *createInterproceduralBasicAliasAnalysisPass();
+
+  //===--------------------------------------------------------------------===//
+  //
   /// createLibCallAliasAnalysisPass - Create an alias analysis pass that knows
   /// about the semantics of a set of libcalls specified by LCI.  The newly
   /// constructed pass takes ownership of the pointer that is provided.

Modified: llvm/trunk/lib/Analysis/AliasAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasAnalysis.cpp?rev=107109&r1=107108&r2=107109&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/AliasAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/AliasAnalysis.cpp Mon Jun 28 19:50:39 2010
@@ -229,16 +229,20 @@
 /// identifiable object.  This returns true for:
 ///    Global Variables and Functions (but not Global Aliases)
 ///    Allocas and Mallocs
-///    ByVal and NoAlias Arguments
-///    NoAlias returns
+///    ByVal and NoAlias Arguments, if Interprocedural is false
+///    NoAlias returns, if Interprocedural is false
 ///
-bool llvm::isIdentifiedObject(const Value *V) {
-  if (isa<AllocaInst>(V) || isNoAliasCall(V))
+bool llvm::isIdentifiedObject(const Value *V, bool Interprocedural) {
+  if (isa<AllocaInst>(V))
     return true;
   if (isa<GlobalValue>(V) && !isa<GlobalAlias>(V))
     return true;
-  if (const Argument *A = dyn_cast<Argument>(V))
-    return A->hasNoAliasAttr() || A->hasByValAttr();
+  if (!Interprocedural) {
+    if (isNoAliasCall(V))
+      return true;
+    if (const Argument *A = dyn_cast<Argument>(V))
+      return A->hasNoAliasAttr() || A->hasByValAttr();
+  }
   return false;
 }
 

Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=107109&r1=107108&r2=107109&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Mon Jun 28 19:50:39 2010
@@ -55,9 +55,10 @@
 
 /// isNonEscapingLocalObject - Return true if the pointer is to a function-local
 /// object that never escapes from the function.
-static bool isNonEscapingLocalObject(const Value *V) {
+static bool isNonEscapingLocalObject(const Value *V, bool Interprocedural) {
   // If this is a local allocation, check to see if it escapes.
-  if (isa<AllocaInst>(V) || isNoAliasCall(V))
+  if (isa<AllocaInst>(V) ||
+      (!Interprocedural && isNoAliasCall(V)))
     // Set StoreCaptures to True so that we can assume in our callers that the
     // pointer is not the result of a load instruction. Currently
     // PointerMayBeCaptured doesn't have any special analysis for the
@@ -68,16 +69,32 @@
   // If this is an argument that corresponds to a byval or noalias argument,
   // then it has not escaped before entering the function.  Check if it escapes
   // inside the function.
-  if (const Argument *A = dyn_cast<Argument>(V))
-    if (A->hasByValAttr() || A->hasNoAliasAttr()) {
-      // Don't bother analyzing arguments already known not to escape.
-      if (A->hasNoCaptureAttr())
-        return true;
-      return !PointerMayBeCaptured(V, false, /*StoreCaptures=*/true);
-    }
+  if (!Interprocedural)
+    if (const Argument *A = dyn_cast<Argument>(V))
+      if (A->hasByValAttr() || A->hasNoAliasAttr()) {
+        // Don't bother analyzing arguments already known not to escape.
+        if (A->hasNoCaptureAttr())
+          return true;
+        return !PointerMayBeCaptured(V, false, /*StoreCaptures=*/true);
+      }
   return false;
 }
 
+/// isEscapeSource - Return true if the pointer is one which would have
+/// been considered an escape by isNonEscapingLocalObject.
+static bool isEscapeSource(const Value *V, bool Interprocedural) {
+  if (!Interprocedural)
+    if (isa<CallInst>(V) || isa<InvokeInst>(V) || isa<Argument>(V))
+      return true;
+
+  // The load case works because isNonEscapingLocalObject considers all
+  // stores to be escapes (it passes true for the StoreCaptures argument
+  // to PointerMayBeCaptured).
+  if (isa<LoadInst>(V))
+    return true;
+
+  return false;
+}
 
 /// isObjectSmallerThan - Return true if we can prove that the object specified
 /// by V is smaller than Size.
@@ -177,19 +194,51 @@
 ImmutablePass *llvm::createNoAAPass() { return new NoAA(); }
 
 //===----------------------------------------------------------------------===//
-// BasicAA Pass
+// BasicAliasAnalysis Pass
 //===----------------------------------------------------------------------===//
 
+static const Function *getParent(const Value *V) {
+  if(const Instruction *inst = dyn_cast<Instruction>(V))
+    return inst->getParent()->getParent();
+
+  if(const Argument *arg = dyn_cast<Argument>(V))
+    return arg->getParent();
+
+  return NULL;
+}
+
+static bool sameParent(const Value *O1, const Value *O2) {
+
+  const Function *F1 = getParent(O1);
+  const Function *F2 = getParent(O2);
+
+  return !F1 || !F2 || F1 == F2;
+}
+
 namespace {
   /// BasicAliasAnalysis - This is the default alias analysis implementation.
   /// Because it doesn't chain to a previous alias analysis (like -no-aa), it
   /// derives from the NoAA class.
   struct BasicAliasAnalysis : public NoAA {
+    /// Interprocedural - Flag for "interprocedural" mode, where we must
+    /// support queries of values which live in different functions.
+    bool Interprocedural;
+
     static char ID; // Class identification, replacement for typeinfo
-    BasicAliasAnalysis() : NoAA(&ID) {}
+    BasicAliasAnalysis()
+      : NoAA(&ID), Interprocedural(false) {}
+    BasicAliasAnalysis(void *PID, bool interprocedural)
+      : NoAA(PID), Interprocedural(interprocedural) {}
+
     AliasResult alias(const Value *V1, unsigned V1Size,
                       const Value *V2, unsigned V2Size) {
       assert(Visited.empty() && "Visited must be cleared after use!");
+#ifdef XDEBUG
+      assert((Interprocedural || sameParent(V1, V2)) &&
+             "BasicAliasAnalysis (-basicaa) doesn't support interprocedural "
+             "queries; use InterproceduralAliasAnalysis "
+             "(-interprocedural-basic-aa) instead.");
+#endif
       AliasResult Alias = aliasCheck(V1, V1Size, V2, V2Size);
       Visited.clear();
       return Alias;
@@ -284,7 +333,7 @@
   // then the call can not mod/ref the pointer unless the call takes the pointer
   // as an argument, and itself doesn't capture it.
   if (!isa<Constant>(Object) && CS.getInstruction() != Object &&
-      isNonEscapingLocalObject(Object)) {
+      isNonEscapingLocalObject(Object, Interprocedural)) {
     bool PassedAsArg = false;
     unsigned ArgNo = 0;
     for (CallSite::arg_iterator CI = CS.arg_begin(), CE = CS.arg_end();
@@ -705,18 +754,25 @@
 
   if (O1 != O2) {
     // If V1/V2 point to two different objects we know that we have no alias.
-    if (isIdentifiedObject(O1) && isIdentifiedObject(O2))
+    if (isIdentifiedObject(O1, Interprocedural) &&
+        isIdentifiedObject(O2, Interprocedural))
       return NoAlias;
 
     // Constant pointers can't alias with non-const isIdentifiedObject objects.
-    if ((isa<Constant>(O1) && isIdentifiedObject(O2) && !isa<Constant>(O2)) ||
-        (isa<Constant>(O2) && isIdentifiedObject(O1) && !isa<Constant>(O1)))
+    if ((isa<Constant>(O1) &&
+         isIdentifiedObject(O2, Interprocedural) &&
+         !isa<Constant>(O2)) ||
+        (isa<Constant>(O2) &&
+         isIdentifiedObject(O1, Interprocedural) &&
+         !isa<Constant>(O1)))
       return NoAlias;
 
-    // Arguments can't alias with local allocations or noalias calls.
-    if ((isa<Argument>(O1) && (isa<AllocaInst>(O2) || isNoAliasCall(O2))) ||
-        (isa<Argument>(O2) && (isa<AllocaInst>(O1) || isNoAliasCall(O1))))
-      return NoAlias;
+    // Arguments can't alias with local allocations or noalias calls, unless
+    // we have to consider interprocedural aliasing.
+    if (!Interprocedural)
+      if ((isa<Argument>(O1) && (isa<AllocaInst>(O2) || isNoAliasCall(O2))) ||
+          (isa<Argument>(O2) && (isa<AllocaInst>(O1) || isNoAliasCall(O1))))
+        return NoAlias;
 
     // Most objects can't alias null.
     if ((isa<ConstantPointerNull>(V2) && isKnownNonNull(O1)) ||
@@ -733,17 +789,13 @@
   
   // If one pointer is the result of a call/invoke or load and the other is a
   // non-escaping local object, then we know the object couldn't escape to a
-  // point where the call could return it. The load case works because
-  // isNonEscapingLocalObject considers all stores to be escapes (it
-  // passes true for the StoreCaptures argument to PointerMayBeCaptured).
+  // point where the call could return it.
   if (O1 != O2) {
-    if ((isa<CallInst>(O1) || isa<InvokeInst>(O1) || isa<LoadInst>(O1) ||
-         isa<Argument>(O1)) &&
-        isNonEscapingLocalObject(O2))
+    if (isEscapeSource(O1, Interprocedural) &&
+        isNonEscapingLocalObject(O2, Interprocedural))
       return NoAlias;
-    if ((isa<CallInst>(O2) || isa<InvokeInst>(O2) || isa<LoadInst>(O2) ||
-         isa<Argument>(O2)) &&
-        isNonEscapingLocalObject(O1))
+    if (isEscapeSource(O2, Interprocedural) &&
+        isNonEscapingLocalObject(O1, Interprocedural))
       return NoAlias;
   }
 
@@ -776,3 +828,33 @@
 
 // Make sure that anything that uses AliasAnalysis pulls in this file.
 DEFINING_FILE_FOR(BasicAliasAnalysis)
+
+//===----------------------------------------------------------------------===//
+// InterproceduralBasicAliasAnalysis Pass
+//===----------------------------------------------------------------------===//
+
+namespace {
+  /// InterproceduralBasicAliasAnalysis - This is similar to basicaa, except
+  /// that it properly supports queries to values which live in different
+  /// functions.
+  ///
+  /// Note that we don't currently take this to the extreme, analyzing all
+  /// call sites of a function to answer a query about an Argument.
+  ///
+  struct InterproceduralBasicAliasAnalysis : public BasicAliasAnalysis {
+    static char ID; // Class identification, replacement for typeinfo
+    InterproceduralBasicAliasAnalysis() : BasicAliasAnalysis(&ID, true) {}
+  };
+}
+
+// Register this pass...
+char InterproceduralBasicAliasAnalysis::ID = 0;
+static RegisterPass<InterproceduralBasicAliasAnalysis>
+W("interprocedural-basic-aa", "Interprocedural Basic Alias Analysis", false, true);
+
+// Declare that we implement the AliasAnalysis interface
+static RegisterAnalysisGroup<AliasAnalysis> Z(W);
+
+ImmutablePass *llvm::createInterproceduralBasicAliasAnalysisPass() {
+  return new InterproceduralBasicAliasAnalysis();
+}

Added: llvm/trunk/test/Analysis/BasicAA/interprocedural.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/BasicAA/interprocedural.ll?rev=107109&view=auto
==============================================================================
--- llvm/trunk/test/Analysis/BasicAA/interprocedural.ll (added)
+++ llvm/trunk/test/Analysis/BasicAA/interprocedural.ll Mon Jun 28 19:50:39 2010
@@ -0,0 +1,42 @@
+; RUN: opt -interprocedural-basic-aa  -interprocedural-aa-eval -print-all-alias-modref-info -disable-output < %s |& FileCheck %s
+
+; The noalias attribute is not safe in an interprocedural context.
+; CHECK: MayAlias: i8* %p, i8* %q
+
+define void @t0(i8* noalias %p) {
+  store i8 0, i8* %p
+  ret void
+}
+define void @t1(i8* noalias %q) {
+  store i8 0, i8* %q
+  ret void
+}
+
+; An alloca can alias an argument in a different function.
+; CHECK: MayAlias: i32* %r, i32* %s
+
+define void @s0(i32* %r) {
+  store i32 0, i32* %r
+  ret void
+}
+
+define void @s1() {
+  %s = alloca i32, i32 10
+  store i32 0, i32* %s
+  call void @s0(i32* %s)
+  ret void
+}
+
+; An alloca can alias an argument in a recursive function.
+; CHECK: MayAlias: i64* %t, i64* %u
+; CHECK: MayAlias: i64* %u, i64* %v
+; CHECK: MayAlias: i64* %t, i64* %v
+
+define i64* @r0(i64* %u) {
+  %t = alloca i64, i32 10
+  %v = call i64* @r0(i64* %t)
+  store i64 0, i64* %t
+  store i64 0, i64* %u
+  store i64 0, i64* %v
+  ret i64* %t
+}




From bob.wilson at apple.com  Mon Jun 28 19:55:23 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Tue, 29 Jun 2010 00:55:23 -0000
Subject: [llvm-commits] [llvm] r107110 - in /llvm/trunk:
 lib/CodeGen/IfConversion.cpp test/CodeGen/Thumb2/thumb2-ifcvt3.ll
Message-ID: <20100629005523.33F482A6C12C@llvm.org>

Author: bwilson
Date: Mon Jun 28 19:55:23 2010
New Revision: 107110

URL: http://llvm.org/viewvc/llvm-project?rev=107110&view=rev
Log:
Reapply my if-conversion cleanup from svn r106939 with fixes.
There are 2 changes relative to the previous version of the patch:

1) For the "simple" if-conversion case, there's no need to worry about
RemoveExtraEdges not handling an unanalyzable branch.  Predicated terminators
are ignored in this context, so RemoveExtraEdges does the right thing.
This might break someday if we ever treat indirect branches (BRIND) as
predicable, but for now, I just removed this part of the patch, because
in the case where we do not add an unconditional branch, we rely on keeping
the fall-through edge to CvtBBI (which is empty after this transformation).

The change relative to the previous patch is:

@@ -1036,10 +1036,6 @@
     IterIfcvt = false;
   }
 
-  // RemoveExtraEdges won't work if the block has an unanalyzable branch,
-  // which is typically the case for IfConvertSimple, so explicitly remove
-  // CvtBBI as a successor.
-  BBI.BB->removeSuccessor(CvtBBI->BB);
   RemoveExtraEdges(BBI);
 
   // Update block info. BB can be iteratively if-converted.


2) My patch exposed a bug in the code for merging the tail of a "diamond",
which had previously never been exercised.  The code was simply checking that
the tail had a single predecessor, but there was a case in
MultiSource/Benchmarks/VersaBench/dbms where that single predecessor was
neither edge of the diamond.  I added the following change to check for
that:

@@ -1276,7 +1276,18 @@
   // tail, add a unconditional branch to it.
   if (TailBB) {
     BBInfo TailBBI = BBAnalysis[TailBB->getNumber()];
-    if (TailBB->pred_size() == 1 && !TailBBI.HasFallThrough) {
+    bool CanMergeTail = !TailBBI.HasFallThrough;
+    // There may still be a fall-through edge from BBI1 or BBI2 to TailBB;
+    // check if there are any other predecessors besides those.
+    unsigned NumPreds = TailBB->pred_size();
+    if (NumPreds > 1)
+      CanMergeTail = false;
+    else if (NumPreds == 1 && CanMergeTail) {
+      MachineBasicBlock::pred_iterator PI = TailBB->pred_begin();
+      if (*PI != BBI1->BB && *PI != BBI2->BB)
+        CanMergeTail = false;
+    }
+    if (CanMergeTail) {
       MergeBlocks(BBI, TailBBI);
       TailBBI.IsDone = true;
     } else {

With these fixes, I was able to run all the SingleSource and MultiSource
tests successfully.

Modified:
    llvm/trunk/lib/CodeGen/IfConversion.cpp
    llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt3.ll

Modified: llvm/trunk/lib/CodeGen/IfConversion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/IfConversion.cpp?rev=107110&r1=107109&r2=107110&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/IfConversion.cpp (original)
+++ llvm/trunk/lib/CodeGen/IfConversion.cpp Mon Jun 28 19:55:23 2010
@@ -186,7 +186,7 @@
                                SmallVectorImpl<MachineOperand> &Cond,
                                SmallSet<unsigned, 4> &Redefs,
                                bool IgnoreBr = false);
-    void MergeBlocks(BBInfo &ToBBI, BBInfo &FromBBI);
+    void MergeBlocks(BBInfo &ToBBI, BBInfo &FromBBI, bool AddEdges = true);
 
     bool MeetIfcvtSizeLimit(MachineBasicBlock &BB, unsigned Size) const {
       return Size > 0 && TII->isProfitableToIfCvt(BB, Size);
@@ -1098,8 +1098,7 @@
   InitPredRedefs(NextBBI->BB, Redefs, TRI);
 
   bool HasEarlyExit = CvtBBI->FalseBB != NULL;
-  bool DupBB = CvtBBI->BB->pred_size() > 1;
-  if (DupBB) {
+  if (CvtBBI->BB->pred_size() > 1) {
     BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB);
     // Copy instructions in the true block, predicate them, and add them to
     // the entry block.
@@ -1111,7 +1110,7 @@
 
     // Now merge the entry of the triangle with the true block.
     BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB);
-    MergeBlocks(BBI, *CvtBBI);
+    MergeBlocks(BBI, *CvtBBI, false);
   }
 
   // If 'true' block has a 'false' successor, add an exit branch to it.
@@ -1184,9 +1183,9 @@
     return false;
   }
 
-  // Merge the 'true' and 'false' blocks by copying the instructions
-  // from the 'false' block to the 'true' block. That is, unless the true
-  // block would clobber the predicate, in that case, do the opposite.
+  // Put the predicated instructions from the 'true' block before the
+  // instructions from the 'false' block, unless the true block would clobber
+  // the predicate, in which case, do the opposite.
   BBInfo *BBI1 = &TrueBBI;
   BBInfo *BBI2 = &FalseBBI;
   SmallVector<MachineOperand, 4> RevCond(BBI.BrCond.begin(), BBI.BrCond.end());
@@ -1275,8 +1274,8 @@
   PredicateBlock(*BBI2, DI2, *Cond2, Redefs);
 
   // Merge the true block into the entry of the diamond.
-  MergeBlocks(BBI, *BBI1);
-  MergeBlocks(BBI, *BBI2);
+  MergeBlocks(BBI, *BBI1, TailBB == 0);
+  MergeBlocks(BBI, *BBI2, TailBB == 0);
 
   // If the if-converted block falls through or unconditionally branches into
   // the tail block, and the tail block does not have other predecessors, then
@@ -1284,16 +1283,32 @@
   // tail, add a unconditional branch to it.
   if (TailBB) {
     BBInfo TailBBI = BBAnalysis[TailBB->getNumber()];
-    if (TailBB->pred_size() == 1 && !TailBBI.HasFallThrough) {
-      BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB);
+    bool CanMergeTail = !TailBBI.HasFallThrough;
+    // There may still be a fall-through edge from BBI1 or BBI2 to TailBB;
+    // check if there are any other predecessors besides those.
+    unsigned NumPreds = TailBB->pred_size();
+    if (NumPreds > 1)
+      CanMergeTail = false;
+    else if (NumPreds == 1 && CanMergeTail) {
+      MachineBasicBlock::pred_iterator PI = TailBB->pred_begin();
+      if (*PI != BBI1->BB && *PI != BBI2->BB)
+        CanMergeTail = false;
+    }
+    if (CanMergeTail) {
       MergeBlocks(BBI, TailBBI);
       TailBBI.IsDone = true;
     } else {
+      BBI.BB->addSuccessor(TailBB);
       InsertUncondBranch(BBI.BB, TailBB, TII);
       BBI.HasFallThrough = false;
     }
   }
 
+  // RemoveExtraEdges won't work if the block has an unanalyzable branch,
+  // which can happen here if TailBB is unanalyzable and is merged, so
+  // explicitly remove BBI1 and BBI2 as successors.
+  BBI.BB->removeSuccessor(BBI1->BB);
+  BBI.BB->removeSuccessor(BBI2->BB);
   RemoveExtraEdges(BBI);
 
   // Update block info.
@@ -1366,17 +1381,19 @@
     UpdatePredRedefs(MI, Redefs, TRI, true);
   }
 
-  std::vector<MachineBasicBlock *> Succs(FromBBI.BB->succ_begin(),
-                                         FromBBI.BB->succ_end());
-  MachineBasicBlock *NBB = getNextBlock(FromBBI.BB);
-  MachineBasicBlock *FallThrough = FromBBI.HasFallThrough ? NBB : NULL;
-
-  for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
-    MachineBasicBlock *Succ = Succs[i];
-    // Fallthrough edge can't be transferred.
-    if (Succ == FallThrough)
-      continue;
-    ToBBI.BB->addSuccessor(Succ);
+  if (!IgnoreBr) {
+    std::vector<MachineBasicBlock *> Succs(FromBBI.BB->succ_begin(),
+                                           FromBBI.BB->succ_end());
+    MachineBasicBlock *NBB = getNextBlock(FromBBI.BB);
+    MachineBasicBlock *FallThrough = FromBBI.HasFallThrough ? NBB : NULL;
+
+    for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
+      MachineBasicBlock *Succ = Succs[i];
+      // Fallthrough edge can't be transferred.
+      if (Succ == FallThrough)
+        continue;
+      ToBBI.BB->addSuccessor(Succ);
+    }
   }
 
   std::copy(FromBBI.Predicate.begin(), FromBBI.Predicate.end(),
@@ -1390,21 +1407,14 @@
 }
 
 /// MergeBlocks - Move all instructions from FromBB to the end of ToBB.
-///
-void IfConverter::MergeBlocks(BBInfo &ToBBI, BBInfo &FromBBI) {
+/// This will leave FromBB as an empty block, so remove all of its
+/// successor edges except for the fall-through edge.  If AddEdges is true,
+/// i.e., when FromBBI's branch is being moved, add those successor edges to
+/// ToBBI.
+void IfConverter::MergeBlocks(BBInfo &ToBBI, BBInfo &FromBBI, bool AddEdges) {
   ToBBI.BB->splice(ToBBI.BB->end(),
                    FromBBI.BB, FromBBI.BB->begin(), FromBBI.BB->end());
 
-  // Redirect all branches to FromBB to ToBB.
-  std::vector<MachineBasicBlock *> Preds(FromBBI.BB->pred_begin(),
-                                         FromBBI.BB->pred_end());
-  for (unsigned i = 0, e = Preds.size(); i != e; ++i) {
-    MachineBasicBlock *Pred = Preds[i];
-    if (Pred == ToBBI.BB)
-      continue;
-    Pred->ReplaceUsesOfBlockWith(FromBBI.BB, ToBBI.BB);
-  }
-
   std::vector<MachineBasicBlock *> Succs(FromBBI.BB->succ_begin(),
                                          FromBBI.BB->succ_end());
   MachineBasicBlock *NBB = getNextBlock(FromBBI.BB);
@@ -1416,7 +1426,8 @@
     if (Succ == FallThrough)
       continue;
     FromBBI.BB->removeSuccessor(Succ);
-    ToBBI.BB->addSuccessor(Succ);
+    if (AddEdges)
+      ToBBI.BB->addSuccessor(Succ);
   }
 
   // Now FromBBI always falls through to the next block!

Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt3.ll?rev=107110&r1=107109&r2=107110&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt3.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt3.ll Mon Jun 28 19:55:23 2010
@@ -23,7 +23,7 @@
 ; CHECK: movne
 ; CHECK: moveq
 ; CHECK: pop
-; CHECK-NEXT: LBB0_1:
+; CHECK-NEXT: @ BB#1:
   %0 = load i64* @posed, align 4                  ; <i64> [#uses=3]
   %1 = sub i64 %0, %.reload78                     ; <i64> [#uses=1]
   %2 = ashr i64 %1, 1                             ; <i64> [#uses=3]




From isanbard at gmail.com  Mon Jun 28 20:08:58 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 29 Jun 2010 01:08:58 -0000
Subject: [llvm-commits] [llvm] r107112 - /llvm/trunk/utils/buildit/build_llvm
Message-ID: <20100629010858.0C39E2A6C12C@llvm.org>

Author: void
Date: Mon Jun 28 20:08:57 2010
New Revision: 107112

URL: http://llvm.org/viewvc/llvm-project?rev=107112&view=rev
Log:
Strip resulting binaries.

Modified:
    llvm/trunk/utils/buildit/build_llvm

Modified: llvm/trunk/utils/buildit/build_llvm
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/buildit/build_llvm?rev=107112&r1=107111&r2=107112&view=diff
==============================================================================
--- llvm/trunk/utils/buildit/build_llvm (original)
+++ llvm/trunk/utils/buildit/build_llvm Mon Jun 28 20:08:57 2010
@@ -331,8 +331,15 @@
 # Remove debugging information from DEST_DIR.
 
 cd $DIR || exit 1
+
 find $DEST_DIR -name \*.a -print | xargs ranlib || exit 1
 find $DEST_DIR -name \*.dSYM -print | xargs rm -r || exit 1
+
+# Strip debugging information from files
+find $DEST_DIR -perm -0111 -type f \
+    ! \( -name '*.la' -o -name gccas -o -name gccld -o -name llvm-config \) \
+    -print | xargs -n 1 -P ${SYSCTL} strip -S
+
 chgrp -h -R wheel $DEST_DIR
 chgrp -R wheel $DEST_DIR
 




From stoklund at 2pi.dk  Mon Jun 28 20:13:07 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 29 Jun 2010 01:13:07 -0000
Subject: [llvm-commits] [llvm] r107114 -
	/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
Message-ID: <20100629011307.645212A6C12C@llvm.org>

Author: stoklund
Date: Mon Jun 28 20:13:07 2010
New Revision: 107114

URL: http://llvm.org/viewvc/llvm-project?rev=107114&view=rev
Log:
When no memoperands are present, assume unaligned, volatile.

Modified:
    llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=107114&r1=107113&r2=107114&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Mon Jun 28 20:13:07 2010
@@ -788,18 +788,21 @@
 /// isMemoryOp - Returns true if instruction is a memory operations (that this
 /// pass is capable of operating on).
 static bool isMemoryOp(const MachineInstr *MI) {
-  if (MI->hasOneMemOperand()) {
-    const MachineMemOperand *MMO = *MI->memoperands_begin();
+  // When no memory operands are present, conservatively assume unaligned,
+  // volatile, unfoldable.
+  if (!MI->hasOneMemOperand())
+    return false;
 
-    // Don't touch volatile memory accesses - we may be changing their order.
-    if (MMO->isVolatile())
-      return false;
+  const MachineMemOperand *MMO = *MI->memoperands_begin();
 
-    // Unaligned ldr/str is emulated by some kernels, but unaligned ldm/stm is
-    // not.
-    if (MMO->getAlignment() < 4)
-      return false;
-  }
+  // Don't touch volatile memory accesses - we may be changing their order.
+  if (MMO->isVolatile())
+    return false;
+
+  // Unaligned ldr/str is emulated by some kernels, but unaligned ldm/stm is
+  // not.
+  if (MMO->getAlignment() < 4)
+    return false;
 
   // str <undef> could probably be eliminated entirely, but for now we just want
   // to avoid making a mess of it.




From bruno.cardoso at gmail.com  Mon Jun 28 20:33:09 2010
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Tue, 29 Jun 2010 01:33:09 -0000
Subject: [llvm-commits] [llvm] r107116 -
	/llvm/trunk/lib/Target/X86/X86InstrSSE.td
Message-ID: <20100629013310.036AB2A6C12C@llvm.org>

Author: bruno
Date: Mon Jun 28 20:33:09 2010
New Revision: 107116

URL: http://llvm.org/viewvc/llvm-project?rev=107116&view=rev
Log:
Refactoring of arithmetic instruction classes with unary operator

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=107116&r1=107115&r2=107116&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Jun 28 20:33:09 2010
@@ -1863,82 +1863,95 @@
   defm MIN : sse12_fp_binop_rm<0x5D, "min", X86fmin>;
 }
 
-// Arithmetic
-
-/// sse1_fp_unop_rm - SSE1 unops come in both scalar and vector forms.
-///
+/// Unop Arithmetic
 /// In addition, we also have a special variant of the scalar form here to
 /// represent the associated intrinsic operation.  This form is unlike the
 /// plain scalar form, in that it takes an entire vector (instead of a
 /// scalar) and leaves the top elements undefined.
 ///
 /// And, we have a special variant form for a full-vector intrinsic form.
-///
-multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr,
-                           SDNode OpNode,
-                           Intrinsic F32Int,
-                           Intrinsic V4F32Int,
-                           bit Commutable = 0> {
-  // Scalar operation, reg.
+
+/// sse1_fp_unop_s - SSE1 unops in scalar form.
+multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
+                           SDNode OpNode, Intrinsic F32Int> {
   def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
                 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
-                [(set FR32:$dst, (OpNode FR32:$src))]> {
-    let isCommutable = Commutable;
-  }
-
-  // Scalar operation, mem.
+                [(set FR32:$dst, (OpNode FR32:$src))]>;
   def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
                 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
                 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
             Requires<[HasSSE1, OptForSize]>;
-
-  // Vector operation, reg.
-  def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
-              !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
-              [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]> {
-    let isCommutable = Commutable;
-  }
-
-  // Vector operation, mem.
-  def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
-                !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
-                [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
-
-  // Intrinsic operation, reg.
   def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
                     !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
-                    [(set VR128:$dst, (F32Int VR128:$src))]> {
-    let isCommutable = Commutable;
-  }
-
-  // Intrinsic operation, mem.
+                    [(set VR128:$dst, (F32Int VR128:$src))]>;
   def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
                     !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
                     [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
+}
 
-  // Vector intrinsic operation, reg
+/// sse1_fp_unop_p - SSE1 unops in scalar form.
+multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr,
+                          SDNode OpNode, Intrinsic V4F32Int> {
+  def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
+              !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
+              [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]>;
+  def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
+                !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
+                [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
   def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
                     !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
-                    [(set VR128:$dst, (V4F32Int VR128:$src))]> {
-    let isCommutable = Commutable;
-  }
-
-  // Vector intrinsic operation, mem
+                    [(set VR128:$dst, (V4F32Int VR128:$src))]>;
   def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
                     !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
                     [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
 }
 
+/// sse2_fp_unop_s - SSE2 unops in scalar form.
+multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
+                          SDNode OpNode, Intrinsic F64Int> {
+  def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
+                !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
+                [(set FR64:$dst, (OpNode FR64:$src))]>;
+  def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
+                !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
+                [(set FR64:$dst, (OpNode (load addr:$src)))]>;
+  def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
+                    !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
+                    [(set VR128:$dst, (F64Int VR128:$src))]>;
+  def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
+                    !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
+                    [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
+}
+
+/// sse2_fp_unop_p - SSE2 unops in vector forms.
+multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
+                          SDNode OpNode, Intrinsic V2F64Int> {
+  def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
+              !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
+              [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]>;
+  def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
+                !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
+                [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
+  def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
+                    !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
+                    [(set VR128:$dst, (V2F64Int VR128:$src))]>;
+  def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
+                    !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
+                    [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
+}
+
 // Square root.
-defm SQRT  : sse1_fp_unop_rm<0x51, "sqrt",  fsqrt,
-                             int_x86_sse_sqrt_ss, int_x86_sse_sqrt_ps>;
+defm SQRT  : sse1_fp_unop_s<0x51, "sqrt",  fsqrt, int_x86_sse_sqrt_ss>,
+             sse1_fp_unop_p<0x51, "sqrt",  fsqrt, int_x86_sse_sqrt_ps>,
+             sse2_fp_unop_s<0x51, "sqrt",  fsqrt, int_x86_sse2_sqrt_sd>,
+             sse2_fp_unop_p<0x51, "sqrt",  fsqrt, int_x86_sse2_sqrt_pd>;
 
 // Reciprocal approximations. Note that these typically require refinement
 // in order to obtain suitable precision.
-defm RSQRT : sse1_fp_unop_rm<0x52, "rsqrt", X86frsqrt,
-                             int_x86_sse_rsqrt_ss, int_x86_sse_rsqrt_ps>;
-defm RCP   : sse1_fp_unop_rm<0x53, "rcp",   X86frcp,
-                             int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>;
+defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss>,
+             sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ps>;
+defm RCP   : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
+             sse1_fp_unop_p<0x53, "rcp", X86frcp, int_x86_sse_rcp_ps>;
 
 // Prefetch intrinsic.
 def PREFETCHT0   : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
@@ -2011,77 +2024,6 @@
 // SSE2 Instructions
 //===---------------------------------------------------------------------===//
 
-// Arithmetic
-
-/// sse2_fp_unop_rm - SSE2 unops come in both scalar and vector forms.
-///
-/// In addition, we also have a special variant of the scalar form here to
-/// represent the associated intrinsic operation.  This form is unlike the
-/// plain scalar form, in that it takes an entire vector (instead of a
-/// scalar) and leaves the top elements undefined.
-///
-/// And, we have a special variant form for a full-vector intrinsic form.
-///
-/// These four forms can each have a reg or a mem operand, so there are a
-/// total of eight "instructions".
-///
-multiclass sse2_fp_unop_rm<bits<8> opc, string OpcodeStr,
-                           SDNode OpNode,
-                           Intrinsic F64Int,
-                           Intrinsic V2F64Int,
-                           bit Commutable = 0> {
-  // Scalar operation, reg.
-  def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
-                !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
-                [(set FR64:$dst, (OpNode FR64:$src))]> {
-    let isCommutable = Commutable;
-  }
-
-  // Scalar operation, mem.
-  def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
-                !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
-                [(set FR64:$dst, (OpNode (load addr:$src)))]>;
-
-  // Vector operation, reg.
-  def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
-              !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
-              [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]> {
-    let isCommutable = Commutable;
-  }
-
-  // Vector operation, mem.
-  def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
-                !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
-                [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
-
-  // Intrinsic operation, reg.
-  def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
-                    !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
-                    [(set VR128:$dst, (F64Int VR128:$src))]> {
-    let isCommutable = Commutable;
-  }
-
-  // Intrinsic operation, mem.
-  def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
-                    !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
-                    [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
-
-  // Vector intrinsic operation, reg
-  def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
-                    !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
-                    [(set VR128:$dst, (V2F64Int VR128:$src))]> {
-    let isCommutable = Commutable;
-  }
-
-  // Vector intrinsic operation, mem
-  def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
-                    !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
-                    [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
-}
-
-// Square root.
-defm SQRT  : sse2_fp_unop_rm<0x51, "sqrt",  fsqrt,
-                             int_x86_sse2_sqrt_sd, int_x86_sse2_sqrt_pd>;
 
 // There is no f64 version of the reciprocal approximation instructions.
 




From gohman at apple.com  Mon Jun 28 20:41:41 2010
From: gohman at apple.com (Dan Gohman)
Date: Tue, 29 Jun 2010 01:41:41 -0000
Subject: [llvm-commits] [llvm] r107117 -
	/llvm/trunk/lib/Analysis/ScalarEvolution.cpp
Message-ID: <20100629014141.6C9962A6C12C@llvm.org>

Author: djg
Date: Mon Jun 28 20:41:41 2010
New Revision: 107117

URL: http://llvm.org/viewvc/llvm-project?rev=107117&view=rev
Log:
Just as its not safe to blindly transfer the nsw bit from an add
instruction to an add scev, it's not safe to blindly transfer the
inbounds flag from a gep instruction to an nsw on the scev for the
gep.

Modified:
    llvm/trunk/lib/Analysis/ScalarEvolution.cpp

Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=107117&r1=107116&r2=107117&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Mon Jun 28 20:41:41 2010
@@ -2763,7 +2763,11 @@
 ///
 const SCEV *ScalarEvolution::createNodeForGEP(GEPOperator *GEP) {
 
-  bool InBounds = GEP->isInBounds();
+  // Don't transfer the inbounds flag from the GEP instruction to the
+  // Add expression, because the Instruction may be guarded by control
+  // flow and the no-overflow bits may not be valid for the expression in
+  // any context.
+
   const Type *IntPtrTy = getEffectiveSCEVType(GEP->getType());
   Value *Base = GEP->getOperand(0);
   // Don't attempt to analyze GEPs over unsized objects.
@@ -2781,7 +2785,7 @@
       unsigned FieldNo = cast<ConstantInt>(Index)->getZExtValue();
       TotalOffset = getAddExpr(TotalOffset,
                                getOffsetOfExpr(STy, FieldNo),
-                               /*HasNUW=*/false, /*HasNSW=*/InBounds);
+                               /*HasNUW=*/false, /*HasNSW=*/false);
     } else {
       // For an array, add the element offset, explicitly scaled.
       const SCEV *LocalOffset = getSCEV(Index);
@@ -2789,13 +2793,13 @@
       LocalOffset = getTruncateOrSignExtend(LocalOffset, IntPtrTy);
       // Lower "inbounds" GEPs to NSW arithmetic.
       LocalOffset = getMulExpr(LocalOffset, getSizeOfExpr(*GTI),
-                               /*HasNUW=*/false, /*HasNSW=*/InBounds);
+                               /*HasNUW=*/false, /*HasNSW=*/false);
       TotalOffset = getAddExpr(TotalOffset, LocalOffset,
-                               /*HasNUW=*/false, /*HasNSW=*/InBounds);
+                               /*HasNUW=*/false, /*HasNSW=*/false);
     }
   }
   return getAddExpr(getSCEV(Base), TotalOffset,
-                    /*HasNUW=*/false, /*HasNSW=*/InBounds);
+                    /*HasNUW=*/false, /*HasNSW=*/false);
 }
 
 /// GetMinTrailingZeros - Determine the minimum number of zero bits that S is




From espindola at google.com  Mon Jun 28 22:15:36 2010
From: espindola at google.com (Rafael Espindola)
Date: Mon, 28 Jun 2010 23:15:36 -0400
Subject: [llvm-commits] [patch] Mostly mechanical removal of
	getPhysicalRegisterRegClass.patch
In-Reply-To: <AEFF279C-8A23-4753-A4A6-89640224C297@2pi.dk>
References: <AANLkTilqt5y4NglQZbWCS7S7jTdaybAvxWQD1-RqbhuK@mail.gmail.com>
	<D707A8E3-C6A1-4FD2-8DB8-FA88FC917365@2pi.dk>
	<AANLkTikDwVDsbrtjOTHmvi0U2OrJ6yjzqyI56d2-HGnm@mail.gmail.com>
	<AEFF279C-8A23-4753-A4A6-89640224C297@2pi.dk>
Message-ID: <AANLkTimgBUUcE2-sTG0Qps20tS8qIh01LB61ABYZuY9e@mail.gmail.com>

> I think I was confused.
>
> I have taken a closer look at InstrEmitter.cpp now. In EmitCopyFromReg(), getPhysicalRegisterRegClass() is only used to provide an argument for copyRegToReg(), and TLI->getRegClassFor(VT) is already used to create the virtual register.
>
> That is fine as is. It is safe to replace getPhysicalRegisterRegClass with getMinimalPhysRegClass there.
>
> The same goes for the uses in ScheduleDAG*.cpp

Sorry it took me so long to reply. Was "lost" in other areas.

The attached patch adds a VT argument to getMinimalPhysRegClass and
replaces the copy related uses of getPhysicalRegisterRegClass with it.
The argument being that if we want to make a copy (or estimate its
cost), it is better to use the smallest class as more efficient
operations might be possible.

The other changes that were needed
*) Update the ARM copyRegToReg to handle SPR_8
*) Update an ARM test, since we now produce a neon move instead of a
vfp move. This is because the optimization:

 else if (DestRC == ARM::DPR_VFP2RegisterClass ||
             SrcRC == ARM::DPR_VFP2RegisterClass)
      // Always use neon reg-reg move if source or dest is NEON-only regclass.
      Opc = ARM::VMOVDneon;

is now used.

> /jakob
>

Cheers,
-- 
Rafael ?vila de Esp?ndola
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From stoklund at 2pi.dk  Mon Jun 28 22:26:26 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Mon, 28 Jun 2010 20:26:26 -0700
Subject: [llvm-commits] [patch] Mostly mechanical removal of
	getPhysicalRegisterRegClass.patch
In-Reply-To: <AANLkTimgBUUcE2-sTG0Qps20tS8qIh01LB61ABYZuY9e@mail.gmail.com>
References: <AANLkTilqt5y4NglQZbWCS7S7jTdaybAvxWQD1-RqbhuK@mail.gmail.com>
	<D707A8E3-C6A1-4FD2-8DB8-FA88FC917365@2pi.dk>
	<AANLkTikDwVDsbrtjOTHmvi0U2OrJ6yjzqyI56d2-HGnm@mail.gmail.com>
	<AEFF279C-8A23-4753-A4A6-89640224C297@2pi.dk>
	<AANLkTimgBUUcE2-sTG0Qps20tS8qIh01LB61ABYZuY9e@mail.gmail.com>
Message-ID: <EFEFA155-7FBA-4942-B731-575ABCD97A83@2pi.dk>


On Jun 28, 2010, at 8:15 PM, Rafael Espindola wrote:

>> I think I was confused.
>> 
>> I have taken a closer look at InstrEmitter.cpp now. In EmitCopyFromReg(), getPhysicalRegisterRegClass() is only used to provide an argument for copyRegToReg(), and TLI->getRegClassFor(VT) is already used to create the virtual register.
>> 
>> That is fine as is. It is safe to replace getPhysicalRegisterRegClass with getMinimalPhysRegClass there.
>> 
>> The same goes for the uses in ScheduleDAG*.cpp
> 
> Sorry it took me so long to reply. Was "lost" in other areas.
> 
> The attached patch adds a VT argument to getMinimalPhysRegClass and
> replaces the copy related uses of getPhysicalRegisterRegClass with it.
> The argument being that if we want to make a copy (or estimate its
> cost), it is better to use the smallest class as more efficient
> operations might be possible.

Looks good.

> The other changes that were needed
> *) Update the ARM copyRegToReg to handle SPR_8

Yup.

> *) Update an ARM test, since we now produce a neon move instead of a
> vfp move. This is because the optimization:
> 
> else if (DestRC == ARM::DPR_VFP2RegisterClass ||
>             SrcRC == ARM::DPR_VFP2RegisterClass)
>      // Always use neon reg-reg move if source or dest is NEON-only regclass.
>      Opc = ARM::VMOVDneon;
> 
> is now used.

This is a little worrying, but probably not your fault.

Maybe the NEONMoveFix pass doesn't work properly for such a small function?

/jakob

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From grosbach at apple.com  Mon Jun 28 23:48:13 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 29 Jun 2010 04:48:13 -0000
Subject: [llvm-commits] [llvm] r107119 -
	/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.h
Message-ID: <20100629044813.E68082A6C12C@llvm.org>

Author: grosbach
Date: Mon Jun 28 23:48:13 2010
New Revision: 107119

URL: http://llvm.org/viewvc/llvm-project?rev=107119&view=rev
Log:
When processing loops for scheduling latencies (used for live outs on loop
back-edges), make sure not to include dbg_value instructions in the count.
Closing in on the end of rdar://7797940

Modified:
    llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.h

Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.h?rev=107119&r1=107118&r2=107119&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.h (original)
+++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.h Mon Jun 28 23:48:13 2010
@@ -69,8 +69,10 @@
                      const SmallSet<unsigned, 8> &LoopLiveIns) {
       unsigned Count = 0;
       for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
-           I != E; ++I, ++Count) {
+           I != E; ++I) {
         const MachineInstr *MI = I;
+        if (MI->isDebugValue())
+          continue;
         for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
           const MachineOperand &MO = MI->getOperand(i);
           if (!MO.isReg() || !MO.isUse())
@@ -79,6 +81,7 @@
           if (LoopLiveIns.count(MOReg))
             Deps.insert(std::make_pair(MOReg, std::make_pair(&MO, Count)));
         }
+        ++Count; // Not every iteration due to dbg_value above.
       }
 
       const std::vector<MachineDomTreeNode*> &Children = Node->getChildren();




From evan.cheng at apple.com  Tue Jun 29 00:00:34 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 28 Jun 2010 22:00:34 -0700
Subject: [llvm-commits] [llvm] r107114 -
	/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
In-Reply-To: <20100629011307.645212A6C12C@llvm.org>
References: <20100629011307.645212A6C12C@llvm.org>
Message-ID: <04D10EF1-91D9-44D6-9161-161B70493ED7@apple.com>


On Jun 28, 2010, at 6:13 PM, Jakob Stoklund Olesen wrote:

> Author: stoklund
> Date: Mon Jun 28 20:13:07 2010
> New Revision: 107114
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=107114&view=rev
> Log:
> When no memoperands are present, assume unaligned, volatile.

Have you checked if this disabled a lot of potential optimizations? I am afraid assuming volatileness is overly conservative.

Evan

> 
> Modified:
>    llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=107114&r1=107113&r2=107114&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Mon Jun 28 20:13:07 2010
> @@ -788,18 +788,21 @@
> /// isMemoryOp - Returns true if instruction is a memory operations (that this
> /// pass is capable of operating on).
> static bool isMemoryOp(const MachineInstr *MI) {
> -  if (MI->hasOneMemOperand()) {
> -    const MachineMemOperand *MMO = *MI->memoperands_begin();
> +  // When no memory operands are present, conservatively assume unaligned,
> +  // volatile, unfoldable.
> +  if (!MI->hasOneMemOperand())
> +    return false;
> 
> -    // Don't touch volatile memory accesses - we may be changing their order.
> -    if (MMO->isVolatile())
> -      return false;
> +  const MachineMemOperand *MMO = *MI->memoperands_begin();
> 
> -    // Unaligned ldr/str is emulated by some kernels, but unaligned ldm/stm is
> -    // not.
> -    if (MMO->getAlignment() < 4)
> -      return false;
> -  }
> +  // Don't touch volatile memory accesses - we may be changing their order.
> +  if (MMO->isVolatile())
> +    return false;
> +
> +  // Unaligned ldr/str is emulated by some kernels, but unaligned ldm/stm is
> +  // not.
> +  if (MMO->getAlignment() < 4)
> +    return false;
> 
>   // str <undef> could probably be eliminated entirely, but for now we just want
>   // to avoid making a mess of it.
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits




From stoklund at 2pi.dk  Tue Jun 29 00:09:48 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Mon, 28 Jun 2010 22:09:48 -0700
Subject: [llvm-commits] [llvm] r107114 -
	/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
In-Reply-To: <04D10EF1-91D9-44D6-9161-161B70493ED7@apple.com>
References: <20100629011307.645212A6C12C@llvm.org>
	<04D10EF1-91D9-44D6-9161-161B70493ED7@apple.com>
Message-ID: <5F342D90-DC02-47A6-A825-EAD20CBFA547@2pi.dk>


On Jun 28, 2010, at 10:00 PM, Evan Cheng wrote:

> 
> On Jun 28, 2010, at 6:13 PM, Jakob Stoklund Olesen wrote:
> 
>> Author: stoklund
>> Date: Mon Jun 28 20:13:07 2010
>> New Revision: 107114
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=107114&view=rev
>> Log:
>> When no memoperands are present, assume unaligned, volatile.
> 
> Have you checked if this disabled a lot of potential optimizations? I am afraid assuming volatileness is overly conservative.

I haven't checked anything but running unit tests.

We need both non-volatile and 4-byte alignment to safely combine loads and stores. If memoperands are missing, I don't see any alternative. How else can we guarantee the optimization is valid?

If this causes missed optimizations, we should ensure that memory operands are present.

/jakob

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From nicholas at mxc.ca  Tue Jun 29 00:22:31 2010
From: nicholas at mxc.ca (Nick Lewycky)
Date: Mon, 28 Jun 2010 22:22:31 -0700
Subject: [llvm-commits] [llvm] r107109 - in /llvm/trunk:
 include/llvm/Analysis/AliasAnalysis.h include/llvm/Analysis/Passes.h
 lib/Analysis/AliasAnalysis.cpp lib/Analysis/BasicAliasAnalysis.cpp
 test/Analysis/BasicAA/interprocedural.ll
In-Reply-To: <20100629005039.39B192A6C12C@llvm.org>
References: <20100629005039.39B192A6C12C@llvm.org>
Message-ID: <4C298317.7050002@mxc.ca>

Dan Gohman wrote:
> Author: djg
> Date: Mon Jun 28 19:50:39 2010
> New Revision: 107109
>
> URL: http://llvm.org/viewvc/llvm-project?rev=107109&view=rev
> Log:
> Add an Intraprocedural form of BasicAliasAnalysis, which aims to
> properly handles instructions and arguments defined in different
> functions, or across recursive function iterations.

Dan,

Why is this an additional pass? Why not infer Interprocedural from 
SameParent()? The idempotents that basicaa was testing for should still 
hold true whenever SameParent() is true. It looks like the 
'Interprocedural BasicAA' is basically a bugfix on BasicAA.

> Added:
>      llvm/trunk/test/Analysis/BasicAA/interprocedural.ll
> Modified:
>      llvm/trunk/include/llvm/Analysis/AliasAnalysis.h
>      llvm/trunk/include/llvm/Analysis/Passes.h
>      llvm/trunk/lib/Analysis/AliasAnalysis.cpp
>      llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp
>
> Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/AliasAnalysis.h?rev=107109&r1=107108&r2=107109&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Analysis/AliasAnalysis.h (original)
> +++ llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Mon Jun 28 19:50:39 2010
> @@ -344,10 +344,10 @@
>   /// identifiable object.  This returns true for:
>   ///    Global Variables and Functions (but not Global Aliases)
>   ///    Allocas and Mallocs
> -///    ByVal and NoAlias Arguments
> -///    NoAlias returns
> +///    ByVal and NoAlias Arguments, if Interprocedural is false
> +///    NoAlias returns, if Interprocedural is false
>   ///
> -bool isIdentifiedObject(const Value *V);
> +bool isIdentifiedObject(const Value *V, bool Interprocedural = false);
>
>   } // End llvm namespace
>
>
> Modified: llvm/trunk/include/llvm/Analysis/Passes.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/Passes.h?rev=107109&r1=107108&r2=107109&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Analysis/Passes.h (original)
> +++ llvm/trunk/include/llvm/Analysis/Passes.h Mon Jun 28 19:50:39 2010
> @@ -73,6 +73,14 @@
>
>     //===--------------------------------------------------------------------===//
>     //
> +  // createInterproceduralBasicAliasAnalysisPass - This pass is similar to
> +  // baiscaa, except that it properly supports queries to values which live
> +  // in different functions.
> +  //
> +  ImmutablePass *createInterproceduralBasicAliasAnalysisPass();
> +
> +  //===--------------------------------------------------------------------===//
> +  //
>     /// createLibCallAliasAnalysisPass - Create an alias analysis pass that knows
>     /// about the semantics of a set of libcalls specified by LCI.  The newly
>     /// constructed pass takes ownership of the pointer that is provided.
>
> Modified: llvm/trunk/lib/Analysis/AliasAnalysis.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasAnalysis.cpp?rev=107109&r1=107108&r2=107109&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Analysis/AliasAnalysis.cpp (original)
> +++ llvm/trunk/lib/Analysis/AliasAnalysis.cpp Mon Jun 28 19:50:39 2010
> @@ -229,16 +229,20 @@
>   /// identifiable object.  This returns true for:
>   ///    Global Variables and Functions (but not Global Aliases)
>   ///    Allocas and Mallocs
> -///    ByVal and NoAlias Arguments
> -///    NoAlias returns
> +///    ByVal and NoAlias Arguments, if Interprocedural is false
> +///    NoAlias returns, if Interprocedural is false
>   ///
> -bool llvm::isIdentifiedObject(const Value *V) {
> -  if (isa<AllocaInst>(V) || isNoAliasCall(V))
> +bool llvm::isIdentifiedObject(const Value *V, bool Interprocedural) {
> +  if (isa<AllocaInst>(V))
>       return true;
>     if (isa<GlobalValue>(V)&&  !isa<GlobalAlias>(V))
>       return true;
> -  if (const Argument *A = dyn_cast<Argument>(V))
> -    return A->hasNoAliasAttr() || A->hasByValAttr();
> +  if (!Interprocedural) {
> +    if (isNoAliasCall(V))
> +      return true;
> +    if (const Argument *A = dyn_cast<Argument>(V))
> +      return A->hasNoAliasAttr() || A->hasByValAttr();
> +  }
>     return false;
>   }
>
>
> Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=107109&r1=107108&r2=107109&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original)
> +++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Mon Jun 28 19:50:39 2010
> @@ -55,9 +55,10 @@
>
>   /// isNonEscapingLocalObject - Return true if the pointer is to a function-local
>   /// object that never escapes from the function.
> -static bool isNonEscapingLocalObject(const Value *V) {
> +static bool isNonEscapingLocalObject(const Value *V, bool Interprocedural) {
>     // If this is a local allocation, check to see if it escapes.
> -  if (isa<AllocaInst>(V) || isNoAliasCall(V))
> +  if (isa<AllocaInst>(V) ||
> +      (!Interprocedural&&  isNoAliasCall(V)))
>       // Set StoreCaptures to True so that we can assume in our callers that the
>       // pointer is not the result of a load instruction. Currently
>       // PointerMayBeCaptured doesn't have any special analysis for the
> @@ -68,16 +69,32 @@
>     // If this is an argument that corresponds to a byval or noalias argument,
>     // then it has not escaped before entering the function.  Check if it escapes
>     // inside the function.
> -  if (const Argument *A = dyn_cast<Argument>(V))
> -    if (A->hasByValAttr() || A->hasNoAliasAttr()) {
> -      // Don't bother analyzing arguments already known not to escape.
> -      if (A->hasNoCaptureAttr())
> -        return true;
> -      return !PointerMayBeCaptured(V, false, /*StoreCaptures=*/true);
> -    }
> +  if (!Interprocedural)
> +    if (const Argument *A = dyn_cast<Argument>(V))
> +      if (A->hasByValAttr() || A->hasNoAliasAttr()) {
> +        // Don't bother analyzing arguments already known not to escape.
> +        if (A->hasNoCaptureAttr())
> +          return true;
> +        return !PointerMayBeCaptured(V, false, /*StoreCaptures=*/true);
> +      }
>     return false;
>   }
>
> +/// isEscapeSource - Return true if the pointer is one which would have
> +/// been considered an escape by isNonEscapingLocalObject.
> +static bool isEscapeSource(const Value *V, bool Interprocedural) {
> +  if (!Interprocedural)
> +    if (isa<CallInst>(V) || isa<InvokeInst>(V) || isa<Argument>(V))
> +      return true;
> +
> +  // The load case works because isNonEscapingLocalObject considers all
> +  // stores to be escapes (it passes true for the StoreCaptures argument
> +  // to PointerMayBeCaptured).
> +  if (isa<LoadInst>(V))
> +    return true;
> +
> +  return false;
> +}
>
>   /// isObjectSmallerThan - Return true if we can prove that the object specified
>   /// by V is smaller than Size.
> @@ -177,19 +194,51 @@
>   ImmutablePass *llvm::createNoAAPass() { return new NoAA(); }
>
>   //===----------------------------------------------------------------------===//
> -// BasicAA Pass
> +// BasicAliasAnalysis Pass
>   //===----------------------------------------------------------------------===//
>
> +static const Function *getParent(const Value *V) {
> +  if(const Instruction *inst = dyn_cast<Instruction>(V))
> +    return inst->getParent()->getParent();

"if ("

> +
> +  if(const Argument *arg = dyn_cast<Argument>(V))
> +    return arg->getParent();

"if ("

Nick

> +
> +  return NULL;
> +}
> +
> +static bool sameParent(const Value *O1, const Value *O2) {
> +
> +  const Function *F1 = getParent(O1);
> +  const Function *F2 = getParent(O2);
> +
> +  return !F1 || !F2 || F1 == F2;
> +}
> +
>   namespace {
>     /// BasicAliasAnalysis - This is the default alias analysis implementation.
>     /// Because it doesn't chain to a previous alias analysis (like -no-aa), it
>     /// derives from the NoAA class.
>     struct BasicAliasAnalysis : public NoAA {
> +    /// Interprocedural - Flag for "interprocedural" mode, where we must
> +    /// support queries of values which live in different functions.
> +    bool Interprocedural;
> +
>       static char ID; // Class identification, replacement for typeinfo
> -    BasicAliasAnalysis() : NoAA(&ID) {}
> +    BasicAliasAnalysis()
> +      : NoAA(&ID), Interprocedural(false) {}
> +    BasicAliasAnalysis(void *PID, bool interprocedural)
> +      : NoAA(PID), Interprocedural(interprocedural) {}
> +
>       AliasResult alias(const Value *V1, unsigned V1Size,
>                         const Value *V2, unsigned V2Size) {
>         assert(Visited.empty()&&  "Visited must be cleared after use!");
> +#ifdef XDEBUG
> +      assert((Interprocedural || sameParent(V1, V2))&&
> +             "BasicAliasAnalysis (-basicaa) doesn't support interprocedural "
> +             "queries; use InterproceduralAliasAnalysis "
> +             "(-interprocedural-basic-aa) instead.");
> +#endif
>         AliasResult Alias = aliasCheck(V1, V1Size, V2, V2Size);
>         Visited.clear();
>         return Alias;
> @@ -284,7 +333,7 @@
>     // then the call can not mod/ref the pointer unless the call takes the pointer
>     // as an argument, and itself doesn't capture it.
>     if (!isa<Constant>(Object)&&  CS.getInstruction() != Object&&
> -      isNonEscapingLocalObject(Object)) {
> +      isNonEscapingLocalObject(Object, Interprocedural)) {
>       bool PassedAsArg = false;
>       unsigned ArgNo = 0;
>       for (CallSite::arg_iterator CI = CS.arg_begin(), CE = CS.arg_end();
> @@ -705,18 +754,25 @@
>
>     if (O1 != O2) {
>       // If V1/V2 point to two different objects we know that we have no alias.
> -    if (isIdentifiedObject(O1)&&  isIdentifiedObject(O2))
> +    if (isIdentifiedObject(O1, Interprocedural)&&
> +        isIdentifiedObject(O2, Interprocedural))
>         return NoAlias;
>
>       // Constant pointers can't alias with non-const isIdentifiedObject objects.
> -    if ((isa<Constant>(O1)&&  isIdentifiedObject(O2)&&  !isa<Constant>(O2)) ||
> -        (isa<Constant>(O2)&&  isIdentifiedObject(O1)&&  !isa<Constant>(O1)))
> +    if ((isa<Constant>(O1)&&
> +         isIdentifiedObject(O2, Interprocedural)&&
> +         !isa<Constant>(O2)) ||
> +        (isa<Constant>(O2)&&
> +         isIdentifiedObject(O1, Interprocedural)&&
> +         !isa<Constant>(O1)))
>         return NoAlias;
>
> -    // Arguments can't alias with local allocations or noalias calls.
> -    if ((isa<Argument>(O1)&&  (isa<AllocaInst>(O2) || isNoAliasCall(O2))) ||
> -        (isa<Argument>(O2)&&  (isa<AllocaInst>(O1) || isNoAliasCall(O1))))
> -      return NoAlias;
> +    // Arguments can't alias with local allocations or noalias calls, unless
> +    // we have to consider interprocedural aliasing.
> +    if (!Interprocedural)
> +      if ((isa<Argument>(O1)&&  (isa<AllocaInst>(O2) || isNoAliasCall(O2))) ||
> +          (isa<Argument>(O2)&&  (isa<AllocaInst>(O1) || isNoAliasCall(O1))))
> +        return NoAlias;
>
>       // Most objects can't alias null.
>       if ((isa<ConstantPointerNull>(V2)&&  isKnownNonNull(O1)) ||
> @@ -733,17 +789,13 @@
>
>     // If one pointer is the result of a call/invoke or load and the other is a
>     // non-escaping local object, then we know the object couldn't escape to a
> -  // point where the call could return it. The load case works because
> -  // isNonEscapingLocalObject considers all stores to be escapes (it
> -  // passes true for the StoreCaptures argument to PointerMayBeCaptured).
> +  // point where the call could return it.
>     if (O1 != O2) {
> -    if ((isa<CallInst>(O1) || isa<InvokeInst>(O1) || isa<LoadInst>(O1) ||
> -         isa<Argument>(O1))&&
> -        isNonEscapingLocalObject(O2))
> +    if (isEscapeSource(O1, Interprocedural)&&
> +        isNonEscapingLocalObject(O2, Interprocedural))
>         return NoAlias;
> -    if ((isa<CallInst>(O2) || isa<InvokeInst>(O2) || isa<LoadInst>(O2) ||
> -         isa<Argument>(O2))&&
> -        isNonEscapingLocalObject(O1))
> +    if (isEscapeSource(O2, Interprocedural)&&
> +        isNonEscapingLocalObject(O1, Interprocedural))
>         return NoAlias;
>     }
>
> @@ -776,3 +828,33 @@
>
>   // Make sure that anything that uses AliasAnalysis pulls in this file.
>   DEFINING_FILE_FOR(BasicAliasAnalysis)
> +
> +//===----------------------------------------------------------------------===//
> +// InterproceduralBasicAliasAnalysis Pass
> +//===----------------------------------------------------------------------===//
> +
> +namespace {
> +  /// InterproceduralBasicAliasAnalysis - This is similar to basicaa, except
> +  /// that it properly supports queries to values which live in different
> +  /// functions.
> +  ///
> +  /// Note that we don't currently take this to the extreme, analyzing all
> +  /// call sites of a function to answer a query about an Argument.
> +  ///
> +  struct InterproceduralBasicAliasAnalysis : public BasicAliasAnalysis {
> +    static char ID; // Class identification, replacement for typeinfo
> +    InterproceduralBasicAliasAnalysis() : BasicAliasAnalysis(&ID, true) {}
> +  };
> +}
> +
> +// Register this pass...
> +char InterproceduralBasicAliasAnalysis::ID = 0;
> +static RegisterPass<InterproceduralBasicAliasAnalysis>
> +W("interprocedural-basic-aa", "Interprocedural Basic Alias Analysis", false, true);
> +
> +// Declare that we implement the AliasAnalysis interface
> +static RegisterAnalysisGroup<AliasAnalysis>  Z(W);
> +
> +ImmutablePass *llvm::createInterproceduralBasicAliasAnalysisPass() {
> +  return new InterproceduralBasicAliasAnalysis();
> +}
>
> Added: llvm/trunk/test/Analysis/BasicAA/interprocedural.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/BasicAA/interprocedural.ll?rev=107109&view=auto
> ==============================================================================
> --- llvm/trunk/test/Analysis/BasicAA/interprocedural.ll (added)
> +++ llvm/trunk/test/Analysis/BasicAA/interprocedural.ll Mon Jun 28 19:50:39 2010
> @@ -0,0 +1,42 @@
> +; RUN: opt -interprocedural-basic-aa  -interprocedural-aa-eval -print-all-alias-modref-info -disable-output<  %s |&  FileCheck %s
> +
> +; The noalias attribute is not safe in an interprocedural context.
> +; CHECK: MayAlias: i8* %p, i8* %q
> +
> +define void @t0(i8* noalias %p) {
> +  store i8 0, i8* %p
> +  ret void
> +}
> +define void @t1(i8* noalias %q) {
> +  store i8 0, i8* %q
> +  ret void
> +}
> +
> +; An alloca can alias an argument in a different function.
> +; CHECK: MayAlias: i32* %r, i32* %s
> +
> +define void @s0(i32* %r) {
> +  store i32 0, i32* %r
> +  ret void
> +}
> +
> +define void @s1() {
> +  %s = alloca i32, i32 10
> +  store i32 0, i32* %s
> +  call void @s0(i32* %s)
> +  ret void
> +}
> +
> +; An alloca can alias an argument in a recursive function.
> +; CHECK: MayAlias: i64* %t, i64* %u
> +; CHECK: MayAlias: i64* %u, i64* %v
> +; CHECK: MayAlias: i64* %t, i64* %v
> +
> +define i64* @r0(i64* %u) {
> +  %t = alloca i64, i32 10
> +  %v = call i64* @r0(i64* %t)
> +  store i64 0, i64* %t
> +  store i64 0, i64* %u
> +  store i64 0, i64* %v
> +  ret i64* %t
> +}
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>



From evan.cheng at apple.com  Tue Jun 29 00:37:59 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 29 Jun 2010 05:37:59 -0000
Subject: [llvm-commits] [llvm] r107121 -
	/llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
Message-ID: <20100629053759.84F532A6C12C@llvm.org>

Author: evancheng
Date: Tue Jun 29 00:37:59 2010
New Revision: 107121

URL: http://llvm.org/viewvc/llvm-project?rev=107121&view=rev
Log:
Change if-cvt options to something that actually as useable.

Modified:
    llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp

Modified: llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp?rev=107121&r1=107120&r2=107121&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp Tue Jun 29 00:37:59 2010
@@ -29,12 +29,14 @@
 using namespace llvm;
 
 static cl::opt<unsigned>
-IfCvtLimit("thumb2-ifcvt-limit (default 3)",
-           cl::Hidden, cl::init(3));
+IfCvtLimit("thumb2-ifcvt-limit", cl::Hidden,
+           cl::desc("Thumb2 if-conversion limit (default 3)"),
+           cl::init(3));
 
 static cl::opt<unsigned>
-IfCvtDiamondLimit("thumb2-ifcvt-diamond-limit (default 3)",
-                  cl::Hidden, cl::init(3));
+IfCvtDiamondLimit("thumb2-ifcvt-diamond-limit", cl::Hidden,
+                  cl::desc("Thumb2 diamond if-conversion limit (default 3)"),
+                  cl::init(3));
 
 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
   : ARMBaseInstrInfo(STI), RI(*this, STI) {




From evan.cheng at apple.com  Tue Jun 29 00:38:36 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 29 Jun 2010 05:38:36 -0000
Subject: [llvm-commits] [llvm] r107122 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrThumb2.td test/CodeGen/Thumb2/thumb2-uxtb.ll
Message-ID: <20100629053836.BF6C12A6C12C@llvm.org>

Author: evancheng
Date: Tue Jun 29 00:38:36 2010
New Revision: 107122

URL: http://llvm.org/viewvc/llvm-project?rev=107122&view=rev
Log:
PR7503: uxtb16 is not available for ARMv7-M. Patch by Brian G. Lucas.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/test/CodeGen/Thumb2/thumb2-uxtb.ll

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=107122&r1=107121&r2=107122&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Jun 29 00:38:36 2010
@@ -1349,9 +1349,9 @@
                                UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
 
 def : T2Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
-            (t2UXTB16r_rot GPR:$Src, 24)>;
+            (t2UXTB16r_rot GPR:$Src, 24)>, Requires<[HasT2ExtractPack]>;
 def : T2Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
-            (t2UXTB16r_rot GPR:$Src, 8)>;
+            (t2UXTB16r_rot GPR:$Src, 8)>, Requires<[HasT2ExtractPack]>;
 
 defm t2UXTAB : T2I_bin_rrot<0b101, "uxtab",
                            BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;

Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-uxtb.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-uxtb.ll?rev=107122&r1=107121&r2=107122&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/thumb2-uxtb.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/thumb2-uxtb.ll Tue Jun 29 00:38:36 2010
@@ -1,47 +1,72 @@
-; RUN: llc < %s -march=thumb -mattr=+thumb2,+t2xtpk | FileCheck %s
+; RUN: llc < %s -march=thumb -mcpu=cortex-a8 | FileCheck %s -check-prefix=ARMv7A
+; RUN: llc < %s -march=thumb -mcpu=cortex-m3 | FileCheck %s -check-prefix=ARMv7M
 
 define i32 @test1(i32 %x) {
-; CHECK: test1
-; CHECK: uxtb16  r0, r0
+; ARMv7A: test1
+; ARMv7A: uxtb16 r0, r0
+
+; ARMv7M: test1
+; ARMv7M: and r0, r0, #16711935
 	%tmp1 = and i32 %x, 16711935		; <i32> [#uses=1]
 	ret i32 %tmp1
 }
 
+; PR7503
 define i32 @test2(i32 %x) {
-; CHECK: test2
-; CHECK: uxtb16  r0, r0, ror #8
+; ARMv7A: test2
+; ARMv7A: uxtb16  r0, r0, ror #8
+
+; ARMv7M: test2
+; ARMv7M: mov.w r1, #16711935
+; ARMv7M: and.w r0, r1, r0, lsr #8
 	%tmp1 = lshr i32 %x, 8		; <i32> [#uses=1]
 	%tmp2 = and i32 %tmp1, 16711935		; <i32> [#uses=1]
 	ret i32 %tmp2
 }
 
 define i32 @test3(i32 %x) {
-; CHECK: test3
-; CHECK: uxtb16  r0, r0, ror #8
+; ARMv7A: test3
+; ARMv7A: uxtb16  r0, r0, ror #8
+
+; ARMv7M: test3
+; ARMv7M: mov.w r1, #16711935
+; ARMv7M: and.w r0, r1, r0, lsr #8
 	%tmp1 = lshr i32 %x, 8		; <i32> [#uses=1]
 	%tmp2 = and i32 %tmp1, 16711935		; <i32> [#uses=1]
 	ret i32 %tmp2
 }
 
 define i32 @test4(i32 %x) {
-; CHECK: test4
-; CHECK: uxtb16  r0, r0, ror #8
+; ARMv7A: test4
+; ARMv7A: uxtb16  r0, r0, ror #8
+
+; ARMv7M: test4
+; ARMv7M: mov.w r1, #16711935
+; ARMv7M: and.w r0, r1, r0, lsr #8
 	%tmp1 = lshr i32 %x, 8		; <i32> [#uses=1]
 	%tmp6 = and i32 %tmp1, 16711935		; <i32> [#uses=1]
 	ret i32 %tmp6
 }
 
 define i32 @test5(i32 %x) {
-; CHECK: test5
-; CHECK: uxtb16  r0, r0, ror #8
+; ARMv7A: test5
+; ARMv7A: uxtb16  r0, r0, ror #8
+
+; ARMv7M: test5
+; ARMv7M: mov.w r1, #16711935
+; ARMv7M: and.w r0, r1, r0, lsr #8
 	%tmp1 = lshr i32 %x, 8		; <i32> [#uses=1]
 	%tmp2 = and i32 %tmp1, 16711935		; <i32> [#uses=1]
 	ret i32 %tmp2
 }
 
 define i32 @test6(i32 %x) {
-; CHECK: test6
-; CHECK: uxtb16  r0, r0, ror #16
+; ARMv7A: test6
+; ARMv7A: uxtb16  r0, r0, ror #16
+
+; ARMv7M: test6
+; ARMv7M: mov.w r1, #16711935
+; ARMv7M: and.w r0, r1, r0, ror #16
 	%tmp1 = lshr i32 %x, 16		; <i32> [#uses=1]
 	%tmp2 = and i32 %tmp1, 255		; <i32> [#uses=1]
 	%tmp4 = shl i32 %x, 16		; <i32> [#uses=1]
@@ -51,8 +76,12 @@
 }
 
 define i32 @test7(i32 %x) {
-; CHECK: test7
-; CHECK: uxtb16  r0, r0, ror #16
+; ARMv7A: test7
+; ARMv7A: uxtb16  r0, r0, ror #16
+
+; ARMv7M: test7
+; ARMv7M: mov.w r1, #16711935
+; ARMv7M: and.w r0, r1, r0, ror #16
 	%tmp1 = lshr i32 %x, 16		; <i32> [#uses=1]
 	%tmp2 = and i32 %tmp1, 255		; <i32> [#uses=1]
 	%tmp4 = shl i32 %x, 16		; <i32> [#uses=1]
@@ -62,8 +91,12 @@
 }
 
 define i32 @test8(i32 %x) {
-; CHECK: test8
-; CHECK: uxtb16  r0, r0, ror #24
+; ARMv7A: test8
+; ARMv7A: uxtb16  r0, r0, ror #24
+
+; ARMv7M: test8
+; ARMv7M: mov.w r1, #16711935
+; ARMv7M: and.w r0, r1, r0, ror #24
 	%tmp1 = shl i32 %x, 8		; <i32> [#uses=1]
 	%tmp2 = and i32 %tmp1, 16711680		; <i32> [#uses=1]
 	%tmp5 = lshr i32 %x, 24		; <i32> [#uses=1]
@@ -72,8 +105,12 @@
 }
 
 define i32 @test9(i32 %x) {
-; CHECK: test9
-; CHECK: uxtb16  r0, r0, ror #24
+; ARMv7A: test9
+; ARMv7A: uxtb16  r0, r0, ror #24
+
+; ARMv7M: test9
+; ARMv7M: mov.w r1, #16711935
+; ARMv7M: and.w r0, r1, r0, ror #24
 	%tmp1 = lshr i32 %x, 24		; <i32> [#uses=1]
 	%tmp4 = shl i32 %x, 8		; <i32> [#uses=1]
 	%tmp5 = and i32 %tmp4, 16711680		; <i32> [#uses=1]
@@ -82,13 +119,19 @@
 }
 
 define i32 @test10(i32 %p0) {
-; CHECK: test10
-; CHECK: mov.w r1, #16253176
-; CHECK: and.w r0, r1, r0, lsr #7
-; CHECK: lsrs  r1, r0, #5
-; CHECK: uxtb16  r1, r1
-; CHECK: orrs r0, r1
-
+; ARMv7A: test10
+; ARMv7A: mov.w r1, #16253176
+; ARMv7A: and.w r0, r1, r0, lsr #7
+; ARMv7A: lsrs  r1, r0, #5
+; ARMv7A: uxtb16  r1, r1
+; ARMv7A: orrs r0, r1
+
+; ARMv7M: test10
+; ARMv7M: mov.w r1, #16253176
+; ARMv7M: and.w r0, r1, r0, lsr #7
+; ARMv7M: mov.w r1, #458759
+; ARMv7M: and.w r1, r1, r0, lsr #5
+; ARMv7M: orrs r0, r1
 	%tmp1 = lshr i32 %p0, 7		; <i32> [#uses=1]
 	%tmp2 = and i32 %tmp1, 16253176		; <i32> [#uses=2]
 	%tmp4 = lshr i32 %tmp2, 5		; <i32> [#uses=1]




From evan.cheng at apple.com  Tue Jun 29 00:46:40 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 28 Jun 2010 22:46:40 -0700
Subject: [llvm-commits] [llvm] r107114 -
	/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
In-Reply-To: <5F342D90-DC02-47A6-A825-EAD20CBFA547@2pi.dk>
References: <20100629011307.645212A6C12C@llvm.org>
	<04D10EF1-91D9-44D6-9161-161B70493ED7@apple.com>
	<5F342D90-DC02-47A6-A825-EAD20CBFA547@2pi.dk>
Message-ID: <0BC7E25D-4488-4954-A149-0D27BF55BBAE@apple.com>


On Jun 28, 2010, at 10:09 PM, Jakob Stoklund Olesen wrote:

> 
> On Jun 28, 2010, at 10:00 PM, Evan Cheng wrote:
> 
>> 
>> On Jun 28, 2010, at 6:13 PM, Jakob Stoklund Olesen wrote:
>> 
>>> Author: stoklund
>>> Date: Mon Jun 28 20:13:07 2010
>>> New Revision: 107114
>>> 
>>> URL: http://llvm.org/viewvc/llvm-project?rev=107114&view=rev
>>> Log:
>>> When no memoperands are present, assume unaligned, volatile.
>> 
>> Have you checked if this disabled a lot of potential optimizations? I am afraid assuming volatileness is overly conservative.
> 
> I haven't checked anything but running unit tests.
> 
> We need both non-volatile and 4-byte alignment to safely combine loads and stores. If memoperands are missing, I don't see any alternative. How else can we guarantee the optimization is valid?
> 
> If this causes missed optimizations, we should ensure that memory operands are present.

I agree. I am just wondering if that's indeed the case. Can you add a llc beta check to look for differences in # of load / store multiple optimizations?

Evan

> 
> /jakob
> 




From stoklund at 2pi.dk  Tue Jun 29 00:50:52 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Mon, 28 Jun 2010 22:50:52 -0700
Subject: [llvm-commits] [llvm] r107114 -
	/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
In-Reply-To: <0BC7E25D-4488-4954-A149-0D27BF55BBAE@apple.com>
References: <20100629011307.645212A6C12C@llvm.org>
	<04D10EF1-91D9-44D6-9161-161B70493ED7@apple.com>
	<5F342D90-DC02-47A6-A825-EAD20CBFA547@2pi.dk>
	<0BC7E25D-4488-4954-A149-0D27BF55BBAE@apple.com>
Message-ID: <DC688401-9B56-48BB-B216-28CC3F31C399@2pi.dk>


On Jun 28, 2010, at 10:46 PM, Evan Cheng wrote:

> 
> On Jun 28, 2010, at 10:09 PM, Jakob Stoklund Olesen wrote:
> 
>> 
>> On Jun 28, 2010, at 10:00 PM, Evan Cheng wrote:
>> 
>>> 
>>> On Jun 28, 2010, at 6:13 PM, Jakob Stoklund Olesen wrote:
>>> 
>>>> Author: stoklund
>>>> Date: Mon Jun 28 20:13:07 2010
>>>> New Revision: 107114
>>>> 
>>>> URL: http://llvm.org/viewvc/llvm-project?rev=107114&view=rev
>>>> Log:
>>>> When no memoperands are present, assume unaligned, volatile.
>>> 
>>> Have you checked if this disabled a lot of potential optimizations? I am afraid assuming volatileness is overly conservative.
>> 
>> I haven't checked anything but running unit tests.
>> 
>> We need both non-volatile and 4-byte alignment to safely combine loads and stores. If memoperands are missing, I don't see any alternative. How else can we guarantee the optimization is valid?
>> 
>> If this causes missed optimizations, we should ensure that memory operands are present.
> 
> I agree. I am just wondering if that's indeed the case. Can you add a llc beta check to look for differences in # of load / store multiple optimizations?

Yep, I'll check.

/jakob

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From chandlerc at gmail.com  Tue Jun 29 01:46:00 2010
From: chandlerc at gmail.com (Chandler Carruth)
Date: Tue, 29 Jun 2010 06:46:00 -0000
Subject: [llvm-commits] [llvm] r107124 -
	/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp
Message-ID: <20100629064600.548C92A6C12C@llvm.org>

Author: chandlerc
Date: Tue Jun 29 01:46:00 2010
New Revision: 107124

URL: http://llvm.org/viewvc/llvm-project?rev=107124&view=rev
Log:
Jump through some silly hoops to make GCC accept that a function may not always
be called.

Modified:
    llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp

Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=107124&r1=107123&r2=107124&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Tue Jun 29 01:46:00 2010
@@ -29,6 +29,7 @@
 #include "llvm/Target/TargetData.h"
 #include "llvm/ADT/SmallPtrSet.h"
 #include "llvm/ADT/SmallVector.h"
+#include "llvm/Support/Compiler.h"
 #include "llvm/Support/ErrorHandling.h"
 #include <algorithm>
 using namespace llvm;
@@ -207,6 +208,8 @@
   return NULL;
 }
 
+static bool sameParent(const Value *O1, const Value *O2) ATTRIBUTE_UNUSED;
+
 static bool sameParent(const Value *O1, const Value *O2) {
 
   const Function *F1 = getParent(O1);




From baldrick at free.fr  Tue Jun 29 02:09:03 2010
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 29 Jun 2010 09:09:03 +0200
Subject: [llvm-commits] [llvm] r107071 - in /llvm/trunk:
 lib/Analysis/BasicAliasAnalysis.cpp lib/VMCore/Value.cpp
 test/Analysis/BasicAA/unreachable-block.ll
In-Reply-To: <20100628211652.97A622A6C12C@llvm.org>
References: <20100628211652.97A622A6C12C@llvm.org>
Message-ID: <4C299C0F.4050809@free.fr>

Hi Dan,

> +define void @func_2() nounwind {
> +entry:
> +  unreachable
> +
> +bb:
> +  %t = select i1 undef, i32* %t, i32* undef
> +  %p = select i1 undef, i32* %p, i32* %p
> +  %q = select i1 undef, i32* undef, i32* %p
> +  %a = getelementptr i8* %a, i32 0
> +  unreachable
> +}

is this IR really valid?  Wouldn't it be better to have the verifier
reject it?

Ciao,

Duncan.


From eli.friedman at gmail.com  Tue Jun 29 02:36:21 2010
From: eli.friedman at gmail.com (Eli Friedman)
Date: Tue, 29 Jun 2010 00:36:21 -0700
Subject: [llvm-commits] [llvm] r107071 - in /llvm/trunk:
	lib/Analysis/BasicAliasAnalysis.cpp lib/VMCore/Value.cpp
	test/Analysis/BasicAA/unreachable-block.ll
In-Reply-To: <4C299C0F.4050809@free.fr>
References: <20100628211652.97A622A6C12C@llvm.org> <4C299C0F.4050809@free.fr>
Message-ID: <AANLkTilfykdmAuFAAhgEgeZoRDfgwtn9HxJXfpXp_vrH@mail.gmail.com>

On Tue, Jun 29, 2010 at 12:09 AM, Duncan Sands <baldrick at free.fr> wrote:
> Hi Dan,
>
>> +define void @func_2() nounwind {
>> +entry:
>> + ?unreachable
>> +
>> +bb:
>> + ?%t = select i1 undef, i32* %t, i32* undef
>> + ?%p = select i1 undef, i32* %p, i32* %p
>> + ?%q = select i1 undef, i32* undef, i32* %p
>> + ?%a = getelementptr i8* %a, i32 0
>> + ?unreachable
>> +}
>
> is this IR really valid? ?Wouldn't it be better to have the verifier
> reject it?

The current rule is that instructions in basic blocks which can't be
reached according to the CFG don't trigger anything like dominance
rules.  One reason is that it would be tricky to define in more
complex cases...

-Eli



From benny.kra at googlemail.com  Tue Jun 29 05:03:11 2010
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Tue, 29 Jun 2010 10:03:11 -0000
Subject: [llvm-commits] [llvm] r107125 -
	/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp
Message-ID: <20100629100312.014852A6C12C@llvm.org>

Author: d0k
Date: Tue Jun 29 05:03:11 2010
New Revision: 107125

URL: http://llvm.org/viewvc/llvm-project?rev=107125&view=rev
Log:
Use a more obvious way to avoid compiling functions which are only used when XDEBUG is enabled.

Modified:
    llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp

Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=107125&r1=107124&r2=107125&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Tue Jun 29 05:03:11 2010
@@ -29,7 +29,6 @@
 #include "llvm/Target/TargetData.h"
 #include "llvm/ADT/SmallPtrSet.h"
 #include "llvm/ADT/SmallVector.h"
-#include "llvm/Support/Compiler.h"
 #include "llvm/Support/ErrorHandling.h"
 #include <algorithm>
 using namespace llvm;
@@ -198,6 +197,7 @@
 // BasicAliasAnalysis Pass
 //===----------------------------------------------------------------------===//
 
+#ifdef XDEBUG
 static const Function *getParent(const Value *V) {
   if(const Instruction *inst = dyn_cast<Instruction>(V))
     return inst->getParent()->getParent();
@@ -208,8 +208,6 @@
   return NULL;
 }
 
-static bool sameParent(const Value *O1, const Value *O2) ATTRIBUTE_UNUSED;
-
 static bool sameParent(const Value *O1, const Value *O2) {
 
   const Function *F1 = getParent(O1);
@@ -217,6 +215,7 @@
 
   return !F1 || !F2 || F1 == F2;
 }
+#endif
 
 namespace {
   /// BasicAliasAnalysis - This is the default alias analysis implementation.




From baldrick at free.fr  Tue Jun 29 06:07:47 2010
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 29 Jun 2010 11:07:47 -0000
Subject: [llvm-commits] [llvm] r107126 -
	/llvm/trunk/tools/gold/gold-plugin.cpp
Message-ID: <20100629110747.42D5D2A6C12C@llvm.org>

Author: baldrick
Date: Tue Jun 29 06:07:47 2010
New Revision: 107126

URL: http://llvm.org/viewvc/llvm-project?rev=107126&view=rev
Log:
Remove variables that are written by not read.

Modified:
    llvm/trunk/tools/gold/gold-plugin.cpp

Modified: llvm/trunk/tools/gold/gold-plugin.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/gold/gold-plugin.cpp?rev=107126&r1=107125&r2=107126&view=diff
==============================================================================
--- llvm/trunk/tools/gold/gold-plugin.cpp (original)
+++ llvm/trunk/tools/gold/gold-plugin.cpp Tue Jun 29 06:07:47 2010
@@ -129,8 +129,6 @@
   // for services.
 
   bool registeredClaimFile = false;
-  bool registeredAllSymbolsRead = false;
-  bool registeredCleanup = false;
 
   for (; tv->tv_tag != LDPT_NULL; ++tv) {
     switch (tv->tv_tag) {
@@ -178,8 +176,6 @@
 
         if ((*callback)(all_symbols_read_hook) != LDPS_OK)
           return LDPS_ERR;
-
-        registeredAllSymbolsRead = true;
       } break;
       case LDPT_REGISTER_CLEANUP_HOOK: {
         ld_plugin_register_cleanup callback;
@@ -187,8 +183,6 @@
 
         if ((*callback)(cleanup_hook) != LDPS_OK)
           return LDPS_ERR;
-
-        registeredCleanup = true;
       } break;
       case LDPT_ADD_SYMBOLS:
         add_symbols = tv->tv_u.tv_add_symbols;




From baldrick at free.fr  Tue Jun 29 06:22:26 2010
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 29 Jun 2010 11:22:26 -0000
Subject: [llvm-commits] [llvm] r107127 - in /llvm/trunk/lib:
 CodeGen/LiveInterval.cpp CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
 Target/ARM/ARMISelLowering.cpp Target/CellSPU/SPUISelDAGToDAG.cpp
 Target/MBlaze/MBlazeISelLowering.cpp Target/PowerPC/PPCISelLowering.cpp
 Target/XCore/XCoreISelLowering.cpp
Message-ID: <20100629112227.195612A6C12C@llvm.org>

Author: baldrick
Date: Tue Jun 29 06:22:26 2010
New Revision: 107127

URL: http://llvm.org/viewvc/llvm-project?rev=107127&view=rev
Log:
Remove initialized but otherwise unused variables.

Modified:
    llvm/trunk/lib/CodeGen/LiveInterval.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
    llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
    llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp

Modified: llvm/trunk/lib/CodeGen/LiveInterval.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveInterval.cpp?rev=107127&r1=107126&r2=107127&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveInterval.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveInterval.cpp Tue Jun 29 06:22:26 2010
@@ -180,7 +180,6 @@
 void LiveInterval::extendIntervalEndTo(Ranges::iterator I, SlotIndex NewEnd) {
   assert(I != ranges.end() && "Not a valid interval!");
   VNInfo *ValNo = I->valno;
-  SlotIndex OldEnd = I->end;
 
   // Search for the first interval that we can't merge with.
   Ranges::iterator MergeTo = next(I);

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=107127&r1=107126&r2=107127&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Tue Jun 29 06:22:26 2010
@@ -2404,7 +2404,6 @@
   // What to do depends on the size of the integer and the size of the pointer.
   // We can either truncate, zero extend, or no-op, accordingly.
   SDValue N = getValue(I.getOperand(0));
-  EVT SrcVT = N.getValueType();
   EVT DestVT = TLI.getValueType(I.getType());
   setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
 }
@@ -2413,7 +2412,6 @@
   // What to do depends on the size of the integer and the size of the pointer.
   // We can either truncate, zero extend, or no-op, accordingly.
   SDValue N = getValue(I.getOperand(0));
-  EVT SrcVT = N.getValueType();
   EVT DestVT = TLI.getValueType(I.getType());
   setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
 }

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=107127&r1=107126&r2=107127&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Jun 29 06:22:26 2010
@@ -1886,7 +1886,6 @@
       DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
                   PseudoSourceValue::getConstantPool(), 0,
                   false, false, 0);
-    SDValue Chain = Result.getValue(1);
 
     if (RelocM == Reloc::PIC_) {
       SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);

Modified: llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp?rev=107127&r1=107126&r2=107127&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp Tue Jun 29 06:22:26 2010
@@ -275,7 +275,6 @@
 
     SDNode *emitBuildVector(SDNode *bvNode) {
       EVT vecVT = bvNode->getValueType(0);
-      EVT eltVT = vecVT.getVectorElementType();
       DebugLoc dl = bvNode->getDebugLoc();
 
       // Check to see if this vector can be represented as a CellSPU immediate

Modified: llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp?rev=107127&r1=107126&r2=107127&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp Tue Jun 29 06:22:26 2010
@@ -439,10 +439,8 @@
 SDValue MBlazeTargetLowering::
 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
   SDValue ResNode;
-  EVT PtrVT = Op.getValueType();
   ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
   const Constant *C = N->getConstVal();
-  SDValue Zero = DAG.getConstant(0, PtrVT);
   DebugLoc dl = Op.getDebugLoc();
 
   SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=107127&r1=107126&r2=107127&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Tue Jun 29 06:22:26 2010
@@ -2737,7 +2737,6 @@
   assert((CallConv == CallingConv::C ||
           CallConv == CallingConv::Fast) && "Unknown calling convention!");
 
-  EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
   unsigned PtrByteSize = 4;
 
   MachineFunction &MF = DAG.getMachineFunction();

Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp?rev=107127&r1=107126&r2=107127&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Tue Jun 29 06:22:26 2010
@@ -1379,7 +1379,6 @@
     SDValue Mul0, Mul1, Addend0, Addend1;
     if (N->getValueType(0) == MVT::i32 &&
         isADDADDMUL(SDValue(N, 0), Mul0, Mul1, Addend0, Addend1, true)) {
-      SDValue Zero = DAG.getConstant(0, MVT::i32);
       SDValue Ignored = DAG.getNode(XCoreISD::LMUL, dl,
                                     DAG.getVTList(MVT::i32, MVT::i32), Mul0,
                                     Mul1, Addend0, Addend1);




From baldrick at free.fr  Tue Jun 29 06:39:45 2010
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 29 Jun 2010 11:39:45 -0000
Subject: [llvm-commits] [llvm] r107128 -
	/llvm/trunk/lib/Analysis/ProfileInfo.cpp
Message-ID: <20100629113945.3847E2A6C12C@llvm.org>

Author: baldrick
Date: Tue Jun 29 06:39:45 2010
New Revision: 107128

URL: http://llvm.org/viewvc/llvm-project?rev=107128&view=rev
Log:
Remove a pointless variable.

Modified:
    llvm/trunk/lib/Analysis/ProfileInfo.cpp

Modified: llvm/trunk/lib/Analysis/ProfileInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ProfileInfo.cpp?rev=107128&r1=107127&r2=107128&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ProfileInfo.cpp (original)
+++ llvm/trunk/lib/Analysis/ProfileInfo.cpp Tue Jun 29 06:39:45 2010
@@ -577,8 +577,6 @@
 
 template<>
 bool ProfileInfoT<Function,BasicBlock>::EstimateMissingEdges(const BasicBlock *BB) {
-  bool hasNoSuccessors = false;
-
   double inWeight = 0;
   std::set<Edge> inMissing;
   std::set<const BasicBlock*> ProcessedPreds;
@@ -596,10 +594,8 @@
   std::set<Edge> outMissing;
   std::set<const BasicBlock*> ProcessedSuccs;
   succ_const_iterator sbbi = succ_begin(BB), sbbe = succ_end(BB);
-  if (sbbi == sbbe) {
+  if (sbbi == sbbe)
     readEdge(this,getEdge(BB,0),outWeight,outMissing);
-    hasNoSuccessors = true;
-  }
   for ( ; sbbi != sbbe; ++sbbi ) {
     if (ProcessedSuccs.insert(*sbbi).second) {
       readEdge(this,getEdge(BB,*sbbi),outWeight,outMissing);




From ggreif at gmail.com  Tue Jun 29 06:41:38 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Tue, 29 Jun 2010 11:41:38 -0000
Subject: [llvm-commits] [llvm] r107129 -
	/llvm/trunk/lib/VMCore/Instructions.cpp
Message-ID: <20100629114138.DCCAA2A6C12C@llvm.org>

Author: ggreif
Date: Tue Jun 29 06:41:38 2010
New Revision: 107129

URL: http://llvm.org/viewvc/llvm-project?rev=107129&view=rev
Log:
encode operand initializations (at fixed index)
in terms of Op<> and ArgOffset. This works for
values of {0, 1} for ArgOffset.
Please note that ArgOffset will become 0 soon and
will go away eventually.

Modified:
    llvm/trunk/lib/VMCore/Instructions.cpp

Modified: llvm/trunk/lib/VMCore/Instructions.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=107129&r1=107128&r2=107129&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Instructions.cpp (original)
+++ llvm/trunk/lib/VMCore/Instructions.cpp Tue Jun 29 06:41:38 2010
@@ -231,8 +231,7 @@
 
 void CallInst::init(Value *Func, Value* const *Params, unsigned NumParams) {
   assert(NumOperands == NumParams+1 && "NumOperands not set up?");
-  Use *OL = OperandList;
-  OL[0] = Func;
+  Op<ArgOffset -1>() = Func;
 
   const FunctionType *FTy =
     cast<FunctionType>(cast<PointerType>(Func->getType())->getElementType());
@@ -245,16 +244,15 @@
     assert((i >= FTy->getNumParams() || 
             FTy->getParamType(i) == Params[i]->getType()) &&
            "Calling a function with a bad signature!");
-    OL[i+1] = Params[i];
+    OperandList[i + ArgOffset] = Params[i];
   }
 }
 
 void CallInst::init(Value *Func, Value *Actual1, Value *Actual2) {
   assert(NumOperands == 3 && "NumOperands not set up?");
-  Use *OL = OperandList;
-  OL[0] = Func;
-  OL[1] = Actual1;
-  OL[2] = Actual2;
+  Op<ArgOffset -1>() = Func;
+  Op<ArgOffset + 0>() = Actual1;
+  Op<ArgOffset + 1>() = Actual2;
 
   const FunctionType *FTy =
     cast<FunctionType>(cast<PointerType>(Func->getType())->getElementType());
@@ -273,9 +271,8 @@
 
 void CallInst::init(Value *Func, Value *Actual) {
   assert(NumOperands == 2 && "NumOperands not set up?");
-  Use *OL = OperandList;
-  OL[0] = Func;
-  OL[1] = Actual;
+  Op<ArgOffset -1>() = Func;
+  Op<ArgOffset + 0>() = Actual;
 
   const FunctionType *FTy =
     cast<FunctionType>(cast<PointerType>(Func->getType())->getElementType());
@@ -291,8 +288,7 @@
 
 void CallInst::init(Value *Func) {
   assert(NumOperands == 1 && "NumOperands not set up?");
-  Use *OL = OperandList;
-  OL[0] = Func;
+  Op<ArgOffset -1>() = Func;
 
   const FunctionType *FTy =
     cast<FunctionType>(cast<PointerType>(Func->getType())->getElementType());




From baldrick at free.fr  Tue Jun 29 07:48:50 2010
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 29 Jun 2010 12:48:50 -0000
Subject: [llvm-commits] [llvm] r107130 -
	/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Message-ID: <20100629124850.4A0782A6C12C@llvm.org>

Author: baldrick
Date: Tue Jun 29 07:48:49 2010
New Revision: 107130

URL: http://llvm.org/viewvc/llvm-project?rev=107130&view=rev
Log:
Remove pointless and unused variables.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=107130&r1=107129&r2=107130&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Jun 29 07:48:49 2010
@@ -2061,7 +2061,6 @@
                                      FPDiff, dl);
   }
 
-  bool WasGlobalOrExternal = false;
   if (getTargetMachine().getCodeModel() == CodeModel::Large) {
     assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
     // In the 64-bit large code model, we have to make all calls
@@ -2069,7 +2068,6 @@
     // pc-relative offset may not be large enough to hold the whole
     // address.
   } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
-    WasGlobalOrExternal = true;
     // If the callee is a GlobalAddress node (quite common, every direct call
     // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
     // it.
@@ -2101,7 +2099,6 @@
                                           G->getOffset(), OpFlags);
     }
   } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
-    WasGlobalOrExternal = true;
     unsigned char OpFlags = 0;
 
     // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external
@@ -2424,7 +2421,6 @@
         ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
       for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
         CCValAssign &VA = ArgLocs[i];
-        EVT RegVT = VA.getLocVT();
         SDValue Arg = Outs[i].Val;
         ISD::ArgFlagsTy Flags = Outs[i].Flags;
         if (VA.getLocInfo() == CCValAssign::Indirect)
@@ -4462,7 +4458,6 @@
   unsigned NumElems = VT.getVectorNumElements();
   unsigned NewWidth = (NumElems == 4) ? 2 : 4;
   EVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
-  EVT MaskEltVT = MaskVT.getVectorElementType();
   EVT NewVT = MaskVT;
   switch (VT.getSimpleVT().SimpleTy) {
   default: assert(false && "Unexpected!");
@@ -6711,7 +6706,6 @@
 
   SDValue Flag;
 
-  EVT IntPtr = getPointerTy();
   EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
 
   Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
@@ -6791,9 +6785,6 @@
 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
   // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
   assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
-  SDValue Chain = Op.getOperand(0);
-  SDValue SrcPtr = Op.getOperand(1);
-  SDValue SrcSV = Op.getOperand(2);
 
   report_fatal_error("VAArgInst is not yet implemented for x86-64!");
   return SDValue();




From baldrick at free.fr  Tue Jun 29 08:00:29 2010
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 29 Jun 2010 13:00:29 -0000
Subject: [llvm-commits] [llvm] r107131 -
	/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
Message-ID: <20100629130029.C85D62A6C12C@llvm.org>

Author: baldrick
Date: Tue Jun 29 08:00:29 2010
New Revision: 107131

URL: http://llvm.org/viewvc/llvm-project?rev=107131&view=rev
Log:
Remove an unused and a pointless variable.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=107131&r1=107130&r2=107131&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Tue Jun 29 08:00:29 2010
@@ -533,7 +533,6 @@
 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDNode *Op, SDValue N,
                                             SDValue &Base, SDValue &Offset){
   // FIXME dl should come from the parent load or store, not the address
-  DebugLoc dl = Op->getDebugLoc();
   if (N.getOpcode() != ISD::ADD) {
     ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
     if (!NC || !NC->isNullValue())
@@ -1382,13 +1381,11 @@
 
   // Quad registers are handled by load/store of subregs. Find the subreg info.
   unsigned NumElts = 0;
-  int SubregIdx = 0;
   bool Even = false;
   EVT RegVT = VT;
   if (!is64BitVector) {
     RegVT = GetNEONSubregVT(VT);
     NumElts = RegVT.getVectorNumElements();
-    SubregIdx = (Lane < NumElts) ? ARM::dsub_0 : ARM::dsub_1;
     Even = Lane < NumElts;
   }
 




From ggreif at gmail.com  Tue Jun 29 08:03:46 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Tue, 29 Jun 2010 13:03:46 -0000
Subject: [llvm-commits] [llvm] r107132 -
	/llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp
Message-ID: <20100629130347.098402A6C12C@llvm.org>

Author: ggreif
Date: Tue Jun 29 08:03:46 2010
New Revision: 107132

URL: http://llvm.org/viewvc/llvm-project?rev=107132&view=rev
Log:
use ArgOperand APIs

Modified:
    llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp

Modified: llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp?rev=107132&r1=107131&r2=107132&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp (original)
+++ llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp Tue Jun 29 08:03:46 2010
@@ -246,10 +246,10 @@
     if (!Sel || Sel->getParent()->getParent() != F) continue;
 
     // Index of the ".llvm.eh.catch.all.value" variable.
-    unsigned OpIdx = Sel->getNumOperands() - 1;
-    GlobalVariable *GV = dyn_cast<GlobalVariable>(Sel->getOperand(OpIdx));
+    unsigned OpIdx = Sel->getNumArgOperands() - 1;
+    GlobalVariable *GV = dyn_cast<GlobalVariable>(Sel->getArgOperand(OpIdx));
     if (GV != EHCatchAllValue) continue;
-    Sel->setOperand(OpIdx, EHCatchAllValue->getInitializer());
+    Sel->setArgOperand(OpIdx, EHCatchAllValue->getInitializer());
     Changed = true;
   }
 




From baldrick at free.fr  Tue Jun 29 08:04:35 2010
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 29 Jun 2010 13:04:35 -0000
Subject: [llvm-commits] [llvm] r107133 -
	/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
Message-ID: <20100629130435.C0D862A6C12C@llvm.org>

Author: baldrick
Date: Tue Jun 29 08:04:35 2010
New Revision: 107133

URL: http://llvm.org/viewvc/llvm-project?rev=107133&view=rev
Log:
Remove unused variable Loc and pointless variables unified_syntax
and thumb_mode.

Modified:
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=107133&r1=107132&r2=107133&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Jun 29 08:04:35 2010
@@ -665,7 +665,6 @@
   
   Operands.push_back(Op.take());
 
-  SMLoc Loc = Parser.getTok().getLoc();
   if (getLexer().isNot(AsmToken::EndOfStatement)) {
 
     // Read the first operand.
@@ -763,15 +762,10 @@
   if (Tok.isNot(AsmToken::Identifier))
     return Error(L, "unexpected token in .syntax directive");
   const StringRef &Mode = Tok.getString();
-  bool unified_syntax;
-  if (Mode == "unified" || Mode == "UNIFIED") {
+  if (Mode == "unified" || Mode == "UNIFIED")
     Parser.Lex();
-    unified_syntax = true;
-  }
-  else if (Mode == "divided" || Mode == "DIVIDED") {
+  else if (Mode == "divided" || Mode == "DIVIDED")
     Parser.Lex();
-    unified_syntax = false;
-  }
   else
     return Error(L, "unrecognized syntax mode in .syntax directive");
 
@@ -791,15 +785,10 @@
   if (Tok.isNot(AsmToken::Integer))
     return Error(L, "unexpected token in .code directive");
   int64_t Val = Parser.getTok().getIntVal();
-  bool thumb_mode;
-  if (Val == 16) {
+  if (Val == 16)
     Parser.Lex();
-    thumb_mode = true;
-  }
-  else if (Val == 32) {
+  else if (Val == 32)
     Parser.Lex();
-    thumb_mode = false;
-  }
   else
     return Error(L, "invalid operand to .code directive");
 




From baldrick at free.fr  Tue Jun 29 08:18:50 2010
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 29 Jun 2010 13:18:50 -0000
Subject: [llvm-commits] [llvm] r107134 -
	/llvm/trunk/test/FrontendC/2010-06-28-DbgEntryPC.c
Message-ID: <20100629131850.A1EEA2A6C12C@llvm.org>

Author: baldrick
Date: Tue Jun 29 08:18:50 2010
New Revision: 107134

URL: http://llvm.org/viewvc/llvm-project?rev=107134&view=rev
Log:
Looks like this test is missing an XFAIL line.

Modified:
    llvm/trunk/test/FrontendC/2010-06-28-DbgEntryPC.c

Modified: llvm/trunk/test/FrontendC/2010-06-28-DbgEntryPC.c
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/2010-06-28-DbgEntryPC.c?rev=107134&r1=107133&r2=107134&view=diff
==============================================================================
--- llvm/trunk/test/FrontendC/2010-06-28-DbgEntryPC.c (original)
+++ llvm/trunk/test/FrontendC/2010-06-28-DbgEntryPC.c Tue Jun 29 08:18:50 2010
@@ -2,6 +2,7 @@
 // Use DW_FORM_addr for DW_AT_entry_pc.
 // Radar 8094785
 
+// XFAIL: *
 // XTARGET: x86,i386,i686
 // CHECK:	.byte	17                      ## DW_TAG_compile_unit
 // CHECK-NEXT:	.byte	1                       ## DW_CHILDREN_yes




From baldrick at free.fr  Tue Jun 29 08:23:22 2010
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 29 Jun 2010 13:23:22 -0000
Subject: [llvm-commits] [llvm] r107135 -
	/llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp
Message-ID: <20100629132322.433D12A6C12C@llvm.org>

Author: baldrick
Date: Tue Jun 29 08:23:22 2010
New Revision: 107135

URL: http://llvm.org/viewvc/llvm-project?rev=107135&view=rev
Log:
Remove pointless variable LastDef.

Modified:
    llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp

Modified: llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp?rev=107135&r1=107134&r2=107135&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp Tue Jun 29 08:23:22 2010
@@ -141,7 +141,6 @@
                                        SmallVector<MachineInstr*,4> &FirstUses,
                                        SmallVector<MachineInstr*,4> &LastUses) {
   bool SeenUse = false;
-  MachineOperand *LastDef = 0;
   MachineOperand *LastUse = 0;
   MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
   while (MBBI != E) {
@@ -175,7 +174,6 @@
         LastUses.push_back(LastUse->getParent());
         LastUse = 0;
       }
-      LastDef = Def;
       SeenUse = false;
     }
   }




From baldrick at free.fr  Tue Jun 29 08:24:40 2010
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 29 Jun 2010 13:24:40 -0000
Subject: [llvm-commits] [llvm] r107136 -
	/llvm/trunk/lib/MC/MCParser/AsmParser.cpp
Message-ID: <20100629132440.BE9432A6C12C@llvm.org>

Author: baldrick
Date: Tue Jun 29 08:24:40 2010
New Revision: 107136

URL: http://llvm.org/viewvc/llvm-project?rev=107136&view=rev
Log:
Remove unused calls to Lexer.getLoc and the pointless variable HasFillExpr.

Modified:
    llvm/trunk/lib/MC/MCParser/AsmParser.cpp

Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=107136&r1=107135&r2=107136&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original)
+++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Tue Jun 29 08:24:40 2010
@@ -844,7 +844,6 @@
   SMLoc EqualLoc = Lexer.getLoc();
 
   const MCExpr *Value;
-  SMLoc StartLoc = Lexer.getLoc();
   if (ParseExpression(Value))
     return true;
   
@@ -1116,7 +1115,6 @@
     return true;
 
   int64_t FillExpr = 0;
-  bool HasFillExpr = false;
   if (Lexer.isNot(AsmToken::EndOfStatement)) {
     if (Lexer.isNot(AsmToken::Comma))
       return TokError("unexpected token in '.space' directive");
@@ -1125,8 +1123,6 @@
     if (ParseAbsoluteExpression(FillExpr))
       return true;
 
-    HasFillExpr = true;
-
     if (Lexer.isNot(AsmToken::EndOfStatement))
       return TokError("unexpected token in '.space' directive");
   }
@@ -1183,7 +1179,6 @@
 ///  ::= .org expression [ , expression ]
 bool AsmParser::ParseDirectiveOrg() {
   const MCExpr *Offset;
-  SMLoc StartLoc = Lexer.getLoc();
   if (ParseExpression(Offset))
     return true;
 
@@ -1387,7 +1382,6 @@
     return TokError("unexpected token in '.desc' directive");
   Lex();
 
-  SMLoc DescLoc = Lexer.getLoc();
   int64_t DescValue;
   if (ParseAbsoluteExpression(DescValue))
     return true;
@@ -1673,7 +1667,6 @@
   Lex();
 
   const MCExpr *Value;
-  SMLoc StartLoc = Lexer.getLoc();
   if (ParseExpression(Value))
     return true;
 




From baldrick at free.fr  Tue Jun 29 08:26:33 2010
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 29 Jun 2010 13:26:33 -0000
Subject: [llvm-commits] [llvm] r107137 -
	/llvm/trunk/lib/MC/MachObjectWriter.cpp
Message-ID: <20100629132633.53F1D2A6C12C@llvm.org>

Author: baldrick
Date: Tue Jun 29 08:26:33 2010
New Revision: 107137

URL: http://llvm.org/viewvc/llvm-project?rev=107137&view=rev
Log:
The variable "Value" is carefully set to Layout.getSymbolAddress,
but then not actually used - maybe a bug?  Remove the variable.

Modified:
    llvm/trunk/lib/MC/MachObjectWriter.cpp

Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MachObjectWriter.cpp?rev=107137&r1=107136&r2=107137&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MachObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/MachObjectWriter.cpp Tue Jun 29 08:26:33 2010
@@ -823,7 +823,6 @@
 
     // See <reloc.h>.
     uint32_t FixupOffset = Layout.getFragmentOffset(Fragment)+Fixup.getOffset();
-    uint32_t Value = 0;
     unsigned Index = 0;
     unsigned IsExtern = 0;
     unsigned Type = 0;
@@ -834,7 +833,6 @@
       // FIXME: Currently, these are never generated (see code below). I cannot
       // find a case where they are actually emitted.
       Type = RIT_Vanilla;
-      Value = 0;
     } else {
       // Check whether we need an external or internal relocation.
       if (doesSymbolRequireExternRelocation(SD)) {
@@ -845,11 +843,9 @@
         // undefined. This occurs with weak definitions, for example.
         if (!SD->Symbol->isUndefined())
           FixedValue -= Layout.getSymbolAddress(SD);
-        Value = 0;
       } else {
         // The index is the section ordinal (1-based).
         Index = SD->getFragment()->getParent()->getOrdinal() + 1;
-        Value = Layout.getSymbolAddress(SD);
       }
 
       Type = RIT_Vanilla;




From baldrick at free.fr  Tue Jun 29 08:30:08 2010
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 29 Jun 2010 13:30:08 -0000
Subject: [llvm-commits] [llvm] r107138 - /llvm/trunk/lib/MC/MCAssembler.cpp
Message-ID: <20100629133008.654572A6C12C@llvm.org>

Author: baldrick
Date: Tue Jun 29 08:30:08 2010
New Revision: 107138

URL: http://llvm.org/viewvc/llvm-project?rev=107138&view=rev
Log:
The variable ValueSize is set to 1 on both code paths, and then
ignored!  Remove it.

Modified:
    llvm/trunk/lib/MC/MCAssembler.cpp

Modified: llvm/trunk/lib/MC/MCAssembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=107138&r1=107137&r2=107138&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAssembler.cpp (original)
+++ llvm/trunk/lib/MC/MCAssembler.cpp Tue Jun 29 08:30:08 2010
@@ -684,12 +684,8 @@
   for (MCAssembler::iterator it = begin(), ie = end(); it != ie; ++it) {
     // Create dummy fragments to eliminate any empty sections, this simplifies
     // layout.
-    if (it->getFragmentList().empty()) {
-      unsigned ValueSize = 1;
-      if (getBackend().isVirtualSection(it->getSection()))
-        ValueSize = 1;
+    if (it->getFragmentList().empty())
       new MCFillFragment(0, 1, 0, it);
-    }
 
     it->setOrdinal(SectionIndex++);
   }




From baldrick at free.fr  Tue Jun 29 08:34:21 2010
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 29 Jun 2010 13:34:21 -0000
Subject: [llvm-commits] [llvm] r107139 -
	/llvm/trunk/lib/CodeGen/ELFCodeEmitter.cpp
Message-ID: <20100629133421.1E51C2A6C12C@llvm.org>

Author: baldrick
Date: Tue Jun 29 08:34:20 2010
New Revision: 107139

URL: http://llvm.org/viewvc/llvm-project?rev=107139&view=rev
Log:
getMachineBasicBlockAddress returns a uintptr_t - don't truncate
to unsigned only to extend back to a pointer sized value on the
next line.

Modified:
    llvm/trunk/lib/CodeGen/ELFCodeEmitter.cpp

Modified: llvm/trunk/lib/CodeGen/ELFCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ELFCodeEmitter.cpp?rev=107139&r1=107138&r2=107139&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ELFCodeEmitter.cpp (original)
+++ llvm/trunk/lib/CodeGen/ELFCodeEmitter.cpp Tue Jun 29 08:34:20 2010
@@ -90,7 +90,7 @@
     for (std::vector<MachineRelocation>::iterator MRI = JTRelocations.begin(),
          MRE = JTRelocations.end(); MRI != MRE; ++MRI) {
       MachineRelocation &MR = *MRI;
-      unsigned MBBOffset = getMachineBasicBlockAddress(MR.getBasicBlock());
+      uintptr_t MBBOffset = getMachineBasicBlockAddress(MR.getBasicBlock());
       MR.setResultPointer((void*)MBBOffset);
       MR.setConstantVal(ES->SectionIdx);
       JTSection.addRelocation(MR);




From rafael.espindola at gmail.com  Tue Jun 29 09:02:34 2010
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Tue, 29 Jun 2010 14:02:34 -0000
Subject: [llvm-commits] [llvm] r107140 - in /llvm/trunk:
 include/llvm/Target/TargetRegisterInfo.h
 lib/CodeGen/SelectionDAG/InstrEmitter.cpp
 lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
 lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
 lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
 lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/TargetRegisterInfo.cpp
 test/CodeGen/ARM/vget_lane.ll
Message-ID: <20100629140234.5FFAE2A6C12C@llvm.org>

Author: rafael
Date: Tue Jun 29 09:02:34 2010
New Revision: 107140

URL: http://llvm.org/viewvc/llvm-project?rev=107140&view=rev
Log:
Add a VT argument to getMinimalPhysRegClass and replace the copy related uses
of getPhysicalRegisterRegClass with it.

If we want to make a copy (or estimate its cost), it is better to use the
smallest class as more efficient operations might be possible.

Modified:
    llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
    llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
    llvm/trunk/lib/Target/TargetRegisterInfo.cpp
    llvm/trunk/test/CodeGen/ARM/vget_lane.ll

Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=107140&r1=107139&r2=107140&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Tue Jun 29 09:02:34 2010
@@ -321,7 +321,8 @@
 
   /// getMinimalPhysRegClass - Returns the Register Class of a physical
   /// register of the given type.
-  const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg) const;
+  const TargetRegisterClass *
+    getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const;
 
   /// getAllocatableSet - Returns a bitset indexed by register number
   /// indicating if a register is allocatable or not. If a register class is

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp?rev=107140&r1=107139&r2=107140&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp Tue Jun 29 09:02:34 2010
@@ -123,7 +123,7 @@
 
   EVT VT = Node->getValueType(ResNo);
   const TargetRegisterClass *SrcRC = 0, *DstRC = 0;
-  SrcRC = TRI->getPhysicalRegisterRegClass(SrcReg, VT);
+  SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
   
   // Figure out the register class to create for the destreg.
   if (VRBase) {
@@ -794,13 +794,13 @@
     if (TargetRegisterInfo::isVirtualRegister(SrcReg))
       SrcTRC = MRI->getRegClass(SrcReg);
     else
-      SrcTRC = TRI->getPhysicalRegisterRegClass(SrcReg,SrcVal.getValueType());
+      SrcTRC = TRI->getMinimalPhysRegClass(SrcReg,SrcVal.getValueType());
 
     if (TargetRegisterInfo::isVirtualRegister(DestReg))
       DstTRC = MRI->getRegClass(DestReg);
     else
-      DstTRC = TRI->getPhysicalRegisterRegClass(DestReg,
-                                            Node->getOperand(1).getValueType());
+      DstTRC = TRI->getMinimalPhysRegClass(DestReg,
+                                           Node->getOperand(1).getValueType());
 
     bool Emitted = TII->copyRegToReg(*MBB, InsertPos, DestReg, SrcReg,
                                      DstTRC, SrcTRC, Node->getDebugLoc());

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp?rev=107140&r1=107139&r2=107140&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp Tue Jun 29 09:02:34 2010
@@ -535,7 +535,7 @@
         SUnit *LRDef = LiveRegDefs[Reg];
         EVT VT = getPhysicalRegisterVT(LRDef->getNode(), Reg, TII);
         const TargetRegisterClass *RC =
-          TRI->getPhysicalRegisterRegClass(Reg, VT);
+          TRI->getMinimalPhysRegClass(Reg, VT);
         const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC);
 
         // If cross copy register class is null, then it must be possible copy

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=107140&r1=107139&r2=107140&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Tue Jun 29 09:02:34 2010
@@ -795,7 +795,7 @@
         SUnit *LRDef = LiveRegDefs[Reg];
         EVT VT = getPhysicalRegisterVT(LRDef->getNode(), Reg, TII);
         const TargetRegisterClass *RC =
-          TRI->getPhysicalRegisterRegClass(Reg, VT);
+          TRI->getMinimalPhysRegClass(Reg, VT);
         const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC);
 
         // If cross copy register class is null, then it must be possible copy

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp?rev=107140&r1=107139&r2=107140&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp Tue Jun 29 09:02:34 2010
@@ -101,7 +101,7 @@
         II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) {
       PhysReg = Reg;
       const TargetRegisterClass *RC =
-        TRI->getPhysicalRegisterRegClass(Reg, Def->getValueType(ResNo));
+        TRI->getMinimalPhysRegClass(Reg, Def->getValueType(ResNo));
       Cost = RC->getCopyCost();
     }
   }

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=107140&r1=107139&r2=107140&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Jun 29 09:02:34 2010
@@ -707,6 +707,11 @@
   if (SrcRC == ARM::tGPRRegisterClass || SrcRC == ARM::tcGPRRegisterClass)
     SrcRC = ARM::GPRRegisterClass;
 
+  if (DestRC == ARM::SPR_8RegisterClass)
+    DestRC = ARM::SPRRegisterClass;
+  if (SrcRC == ARM::SPR_8RegisterClass)
+    SrcRC = ARM::SPRRegisterClass;
+
   // Allow DPR / DPR_VFP2 / DPR_8 cross-class copies.
   if (DestRC == ARM::DPR_8RegisterClass)
     DestRC = ARM::DPR_VFP2RegisterClass;

Modified: llvm/trunk/lib/Target/TargetRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetRegisterInfo.cpp?rev=107140&r1=107139&r2=107140&view=diff
==============================================================================
--- llvm/trunk/lib/Target/TargetRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/TargetRegisterInfo.cpp Tue Jun 29 09:02:34 2010
@@ -63,7 +63,7 @@
 /// getMinimalPhysRegClass - Returns the Register Class of a physical
 /// register of the given type.
 const TargetRegisterClass *
-TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg) const {
+TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, EVT VT) const {
   assert(isPhysicalRegister(reg) && "reg must be a physical register");
 
   // Pick the most sub register class of the right type that contains
@@ -71,7 +71,8 @@
   const TargetRegisterClass* BestRC = 0;
   for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){
     const TargetRegisterClass* RC = *I;
-    if (RC->contains(reg) && (!BestRC || BestRC->hasSubClass(RC)))
+    if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
+        (!BestRC || BestRC->hasSubClass(RC)))
       BestRC = RC;
   }
 

Modified: llvm/trunk/test/CodeGen/ARM/vget_lane.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vget_lane.ll?rev=107140&r1=107139&r2=107140&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vget_lane.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vget_lane.ll Tue Jun 29 09:02:34 2010
@@ -205,7 +205,7 @@
 define arm_aapcs_vfpcc <2 x float> @test_vset_lanef32(float %arg0_float32_t, <2 x float> %arg1_float32x2_t) nounwind {
 ;CHECK: test_vset_lanef32:
 ;CHECK: vmov.f32 s3, s0
-;CHECK: vmov.f64 d0, d1
+;CHECK: vmov d0, d1
 entry:
   %0 = insertelement <2 x float> %arg1_float32x2_t, float %arg0_float32_t, i32 1 ; <<2 x float>> [#uses=1]
   ret <2 x float> %0




From baldrick at free.fr  Tue Jun 29 09:49:35 2010
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 29 Jun 2010 14:49:35 -0000
Subject: [llvm-commits] [llvm] r107141 -
	/llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp
Message-ID: <20100629144935.8FCB82A6C12E@llvm.org>

Author: baldrick
Date: Tue Jun 29 09:49:35 2010
New Revision: 107141

URL: http://llvm.org/viewvc/llvm-project?rev=107141&view=rev
Log:
It seems clear that this should return Changed.

Modified:
    llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp

Modified: llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp?rev=107141&r1=107140&r2=107141&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp (original)
+++ llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp Tue Jun 29 09:49:35 2010
@@ -153,7 +153,7 @@
         Changed = true;
       }
 
-      return false;
+      return Changed;
     }
 
   public:




From baldrick at free.fr  Tue Jun 29 09:52:10 2010
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 29 Jun 2010 14:52:10 -0000
Subject: [llvm-commits] [llvm] r107142 -
	/llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp
Message-ID: <20100629145210.D25BE2A6C12E@llvm.org>

Author: baldrick
Date: Tue Jun 29 09:52:10 2010
New Revision: 107142

URL: http://llvm.org/viewvc/llvm-project?rev=107142&view=rev
Log:
Return Changed.  This required setting Changed if dbg metadata
is stripped off.  Currently set unconditionally, since the API
does not provide a way of working out if anything was actually
stripped off.

Modified:
    llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp

Modified: llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp?rev=107142&r1=107141&r2=107142&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp (original)
+++ llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp Tue Jun 29 09:52:10 2010
@@ -228,22 +228,24 @@
     Changed = true;
     NMD->eraseFromParent();
   }
-  
+
   NMD = M.getNamedMetadata("llvm.dbg.lv");
   if (NMD) {
     Changed = true;
     NMD->eraseFromParent();
   }
-  
+
   unsigned MDDbgKind = M.getMDKindID("dbg");
-  for (Module::iterator MI = M.begin(), ME = M.end(); MI != ME; ++MI) 
+  for (Module::iterator MI = M.begin(), ME = M.end(); MI != ME; ++MI)
     for (Function::iterator FI = MI->begin(), FE = MI->end(); FI != FE;
          ++FI)
       for (BasicBlock::iterator BI = FI->begin(), BE = FI->end(); BI != BE;
-           ++BI) 
+           ++BI) {
+        Changed = true; // FIXME: Only set if there was debug metadata.
         BI->setMetadata(MDDbgKind, 0);
+      }
 
-  return true;
+  return Changed;
 }
 
 bool StripSymbols::runOnModule(Module &M) {




From asl at math.spbu.ru  Tue Jun 29 09:54:26 2010
From: asl at math.spbu.ru (Anton Korobeynikov)
Date: Tue, 29 Jun 2010 18:54:26 +0400
Subject: [llvm-commits] [patch] Mostly mechanical removal of
	getPhysicalRegisterRegClass.patch
In-Reply-To: <EFEFA155-7FBA-4942-B731-575ABCD97A83@2pi.dk>
References: <AANLkTilqt5y4NglQZbWCS7S7jTdaybAvxWQD1-RqbhuK@mail.gmail.com>
	<D707A8E3-C6A1-4FD2-8DB8-FA88FC917365@2pi.dk>
	<AANLkTikDwVDsbrtjOTHmvi0U2OrJ6yjzqyI56d2-HGnm@mail.gmail.com>
	<AEFF279C-8A23-4753-A4A6-89640224C297@2pi.dk>
	<AANLkTimgBUUcE2-sTG0Qps20tS8qIh01LB61ABYZuY9e@mail.gmail.com>
	<EFEFA155-7FBA-4942-B731-575ABCD97A83@2pi.dk>
Message-ID: <AANLkTinvjuW8OuHxExMJECtbVAd1GqyqFAX1JT5IM86-@mail.gmail.com>

Hello, Jakob

> This is a little worrying, but probably not your fault.
Yes. This somehow seems to be a fallout from subreg indices unification.

Basically, the problem is that currently we can easily have
cross-domain switches while walking via subregs.
Look, for example, into DPR_VFP2 regclass. This class is used for NEON
code and thus all the stuff operates inside the NEON domain. It should
not contain any SPR subregs since there are no 32-bit reg-reg moves in
NEON (think about the core with VFP disabled, but not NEON).

In fact, this was the only reason why this regclass does exist - to
restrict the set of regs used for certain neon instructions.
-- 
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University


From espindola at google.com  Tue Jun 29 10:11:17 2010
From: espindola at google.com (Rafael Espindola)
Date: Tue, 29 Jun 2010 11:11:17 -0400
Subject: [llvm-commits] [patch] Mostly mechanical removal of
	getPhysicalRegisterRegClass.patch
In-Reply-To: <AANLkTinvjuW8OuHxExMJECtbVAd1GqyqFAX1JT5IM86-@mail.gmail.com>
References: <AANLkTilqt5y4NglQZbWCS7S7jTdaybAvxWQD1-RqbhuK@mail.gmail.com>
	<D707A8E3-C6A1-4FD2-8DB8-FA88FC917365@2pi.dk>
	<AANLkTikDwVDsbrtjOTHmvi0U2OrJ6yjzqyI56d2-HGnm@mail.gmail.com>
	<AEFF279C-8A23-4753-A4A6-89640224C297@2pi.dk>
	<AANLkTimgBUUcE2-sTG0Qps20tS8qIh01LB61ABYZuY9e@mail.gmail.com>
	<EFEFA155-7FBA-4942-B731-575ABCD97A83@2pi.dk>
	<AANLkTinvjuW8OuHxExMJECtbVAd1GqyqFAX1JT5IM86-@mail.gmail.com>
Message-ID: <AANLkTimv2smH65TcgkCg9oiuxTjE6yS13tfd3yLo9wGG@mail.gmail.com>

On 29 June 2010 10:54, Anton Korobeynikov <asl at math.spbu.ru> wrote:
> Hello, Jakob
>
>> This is a little worrying, but probably not your fault.
> Yes. This somehow seems to be a fallout from subreg indices unification.
>
> Basically, the problem is that currently we can easily have
> cross-domain switches while walking via subregs.
> Look, for example, into DPR_VFP2 regclass. This class is used for NEON
> code and thus all the stuff operates inside the NEON domain. It should
> not contain any SPR subregs since there are no 32-bit reg-reg moves in
> NEON (think about the core with VFP disabled, but not NEON).
>
> In fact, this was the only reason why this regclass does exist - to
> restrict the set of regs used for certain neon instructions.

I think we agreed on IRC. The issues is that the question "give me a
regclass for D0" is ambiguous. Is that the NEON one or the VFP one? If
we don't specify this, the existing DPR_VFP2 class is a valid answer
and gives the copy creation extra freedom.

Since there are cases where we care a lot about moves from neon to
vfp, we should make those explicit. I agree with Anton that what we
should do is

*) Declare the neon registers as independent entities from the vfp
registers (D0N, D1N, ...)
*) Declare the class of neon registers. This will not intersect with
the vfp register classes
*) Declare move instructions between the two (COPY_TO_REGCLASS?). This
will print just like a regular copy, but have a cost that reflects the
move from neon to vfp or the other way.

Check?

Should I revert the patch while we work on this?

> --
> With best regards, Anton Korobeynikov
> Faculty of Mathematics and Mechanics, Saint Petersburg State University
>

Cheers,
-- 
Rafael ?vila de Esp?ndola



From bob.wilson at apple.com  Tue Jun 29 10:29:02 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Tue, 29 Jun 2010 08:29:02 -0700
Subject: [llvm-commits] [patch] Mostly mechanical removal of
	getPhysicalRegisterRegClass.patch
In-Reply-To: <AANLkTimv2smH65TcgkCg9oiuxTjE6yS13tfd3yLo9wGG@mail.gmail.com>
References: <AANLkTilqt5y4NglQZbWCS7S7jTdaybAvxWQD1-RqbhuK@mail.gmail.com>
	<D707A8E3-C6A1-4FD2-8DB8-FA88FC917365@2pi.dk>
	<AANLkTikDwVDsbrtjOTHmvi0U2OrJ6yjzqyI56d2-HGnm@mail.gmail.com>
	<AEFF279C-8A23-4753-A4A6-89640224C297@2pi.dk>
	<AANLkTimgBUUcE2-sTG0Qps20tS8qIh01LB61ABYZuY9e@mail.gmail.com>
	<EFEFA155-7FBA-4942-B731-575ABCD97A83@2pi.dk>
	<AANLkTinvjuW8OuHxExMJECtbVAd1GqyqFAX1JT5IM86-@mail.gmail.com>
	<AANLkTimv2smH65TcgkCg9oiuxTjE6yS13tfd3yLo9wGG@mail.gmail.com>
Message-ID: <74387686-1D9D-42E8-B473-7157DF0EF462@apple.com>


On Jun 29, 2010, at 8:11 AM, Rafael Espindola wrote:

> On 29 June 2010 10:54, Anton Korobeynikov <asl at math.spbu.ru> wrote:
>> Hello, Jakob
>> 
>>> This is a little worrying, but probably not your fault.
>> Yes. This somehow seems to be a fallout from subreg indices unification.
>> 
>> Basically, the problem is that currently we can easily have
>> cross-domain switches while walking via subregs.
>> Look, for example, into DPR_VFP2 regclass. This class is used for NEON
>> code and thus all the stuff operates inside the NEON domain. It should
>> not contain any SPR subregs since there are no 32-bit reg-reg moves in
>> NEON (think about the core with VFP disabled, but not NEON).
>> 
>> In fact, this was the only reason why this regclass does exist - to
>> restrict the set of regs used for certain neon instructions.
> 
> I think we agreed on IRC. The issues is that the question "give me a
> regclass for D0" is ambiguous. Is that the NEON one or the VFP one? If
> we don't specify this, the existing DPR_VFP2 class is a valid answer
> and gives the copy creation extra freedom.
> 
> Since there are cases where we care a lot about moves from neon to
> vfp, we should make those explicit. I agree with Anton that what we
> should do is
> 
> *) Declare the neon registers as independent entities from the vfp
> registers (D0N, D1N, ...)
> *) Declare the class of neon registers. This will not intersect with
> the vfp register classes
> *) Declare move instructions between the two (COPY_TO_REGCLASS?). This
> will print just like a regular copy, but have a cost that reflects the
> move from neon to vfp or the other way.
> 
> Check?

I don't like the sound of this proposal very much.  I know the Cortex-A8 microarchitecture imposes a significantly penalty for moving between NEON and VFP, and maybe the A9 does as well (I forget), but that is just a bad design.  There's nothing in the ARM architecture that encourages those pipelines to be separated as they are in those particular implementations, and we should not design our compiler around that.  Hopefully someday ARM will fix the problem, and at that point, we don't want to be stuck with two sets of equivalent registers.

I missed the IRC discussion.  Could you explain how you came to this conclusion and what other options you considered?


From espindola at google.com  Tue Jun 29 10:46:19 2010
From: espindola at google.com (Rafael Espindola)
Date: Tue, 29 Jun 2010 11:46:19 -0400
Subject: [llvm-commits] [patch] Mostly mechanical removal of
	getPhysicalRegisterRegClass.patch
In-Reply-To: <74387686-1D9D-42E8-B473-7157DF0EF462@apple.com>
References: <AANLkTilqt5y4NglQZbWCS7S7jTdaybAvxWQD1-RqbhuK@mail.gmail.com>
	<D707A8E3-C6A1-4FD2-8DB8-FA88FC917365@2pi.dk>
	<AANLkTikDwVDsbrtjOTHmvi0U2OrJ6yjzqyI56d2-HGnm@mail.gmail.com>
	<AEFF279C-8A23-4753-A4A6-89640224C297@2pi.dk>
	<AANLkTimgBUUcE2-sTG0Qps20tS8qIh01LB61ABYZuY9e@mail.gmail.com>
	<EFEFA155-7FBA-4942-B731-575ABCD97A83@2pi.dk>
	<AANLkTinvjuW8OuHxExMJECtbVAd1GqyqFAX1JT5IM86-@mail.gmail.com>
	<AANLkTimv2smH65TcgkCg9oiuxTjE6yS13tfd3yLo9wGG@mail.gmail.com>
	<74387686-1D9D-42E8-B473-7157DF0EF462@apple.com>
Message-ID: <AANLkTimqNFvRcfhc56eojQ_o1zWs81bRja3HJPVMGMvx@mail.gmail.com>

> I don't like the sound of this proposal very much. ?I know the Cortex-A8 microarchitecture imposes a significantly penalty for moving between NEON and VFP, and maybe the A9 does as well (I forget), but that is just a bad design. ?There's nothing in the ARM architecture that encourages those pipelines to be separated as they are in those particular implementations, and we should not design our compiler around that. ?Hopefully someday ARM will fix the problem, and at that point, we don't want to be stuck with two sets of equivalent registers.

I would say that a compiler has to live with the architectures it is given...

> I missed the IRC discussion. ?Could you explain how you came to this conclusion and what other options you considered?

Skipping some misunderstandings, It went more or less like this

*) I noted that since DPR_VFP2 is a subcass of DPR, we can use it
anywhere that DPR is OK. In particular, the question of "a regclass
for D0" can be answered with both DPR and DPR_VFP2. DPR_VFP2 is
smaller, and can allow copyRegToReg to produce more specialized code.

*) Anton noted that we only want to use DPR_VFP2 for NEON to avoid
copies from VFP to NEON.

*) From that, we have to know when we ask for a regclass for d0 if we
want to use it with NEON or VFP.

*) Anton proposed making the NEON and VFP regclasses independent. A
agreed that it was a good idea.

So I guess we didn't consider other options, since I agreed with his
first suggestion.

Cheers,
-- 
Rafael ?vila de Esp?ndola



From ggreif at gmail.com  Tue Jun 29 11:01:30 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Tue, 29 Jun 2010 16:01:30 -0000
Subject: [llvm-commits] [llvm] r107144 -
	/llvm/trunk/include/llvm/IntrinsicInst.h
Message-ID: <20100629160130.321CB2A6C12C@llvm.org>

Author: ggreif
Date: Tue Jun 29 11:01:30 2010
New Revision: 107144

URL: http://llvm.org/viewvc/llvm-project?rev=107144&view=rev
Log:
use ArgOperand API

Modified:
    llvm/trunk/include/llvm/IntrinsicInst.h

Modified: llvm/trunk/include/llvm/IntrinsicInst.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicInst.h?rev=107144&r1=107143&r2=107144&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IntrinsicInst.h (original)
+++ llvm/trunk/include/llvm/IntrinsicInst.h Tue Jun 29 11:01:30 2010
@@ -43,7 +43,7 @@
     Intrinsic::ID getIntrinsicID() const {
       return (Intrinsic::ID)getCalledFunction()->getIntrinsicID();
     }
-    
+
     // Methods for support type inquiry through isa, cast, and dyn_cast:
     static inline bool classof(const IntrinsicInst *) { return true; }
     static inline bool classof(const CallInst *I) {
@@ -74,7 +74,7 @@
     static inline bool classof(const Value *V) {
       return isa<IntrinsicInst>(V) && classof(cast<IntrinsicInst>(V));
     }
-    
+
     static Value *StripCast(Value *C);
   };
 
@@ -83,7 +83,7 @@
   class DbgDeclareInst : public DbgInfoIntrinsic {
   public:
     Value *getAddress() const;
-    MDNode *getVariable() const { return cast<MDNode>(getOperand(2)); }
+    MDNode *getVariable() const { return cast<MDNode>(getArgOperand(1)); }
 
     // Methods for support type inquiry through isa, cast, and dyn_cast:
     static inline bool classof(const DbgDeclareInst *) { return true; }
@@ -103,9 +103,9 @@
     Value *getValue();
     uint64_t getOffset() const {
       return cast<ConstantInt>(
-                             const_cast<Value*>(getOperand(2)))->getZExtValue();
+                             const_cast<Value*>(getArgOperand(1)))->getZExtValue();
     }
-    MDNode *getVariable() const { return cast<MDNode>(getOperand(3)); }
+    MDNode *getVariable() const { return cast<MDNode>(getArgOperand(2)); }
 
     // Methods for support type inquiry through isa, cast, and dyn_cast:
     static inline bool classof(const DbgValueInst *) { return true; }
@@ -121,19 +121,19 @@
   ///
   class MemIntrinsic : public IntrinsicInst {
   public:
-    Value *getRawDest() const { return const_cast<Value*>(getOperand(1)); }
+    Value *getRawDest() const { return const_cast<Value*>(getArgOperand(0)); }
 
-    Value *getLength() const { return const_cast<Value*>(getOperand(3)); }
+    Value *getLength() const { return const_cast<Value*>(getArgOperand(2)); }
     ConstantInt *getAlignmentCst() const {
-      return cast<ConstantInt>(const_cast<Value*>(getOperand(4)));
+      return cast<ConstantInt>(const_cast<Value*>(getArgOperand(3)));
     }
-    
+
     unsigned getAlignment() const {
       return getAlignmentCst()->getZExtValue();
     }
 
     ConstantInt *getVolatileCst() const {
-      return cast<ConstantInt>(const_cast<Value*>(getOperand(5)));
+      return cast<ConstantInt>(const_cast<Value*>(getArgOperand(4)));
     }
     bool isVolatile() const {
       return !getVolatileCst()->isZero();
@@ -149,27 +149,27 @@
     void setDest(Value *Ptr) {
       assert(getRawDest()->getType() == Ptr->getType() &&
              "setDest called with pointer of wrong type!");
-      setOperand(1, Ptr);
+      setArgOperand(0, Ptr);
     }
 
     void setLength(Value *L) {
       assert(getLength()->getType() == L->getType() &&
              "setLength called with value of wrong type!");
-      setOperand(3, L);
+      setArgOperand(2, L);
     }
-    
+
     void setAlignment(Constant* A) {
-      setOperand(4, A);
+      setArgOperand(3, A);
     }
 
     void setVolatile(Constant* V) {
-      setOperand(5, V);
+      setArgOperand(4, V);
     }
 
     const Type *getAlignmentType() const {
-      return getOperand(4)->getType();
+      return getArgOperand(3)->getType();
     }
-    
+
     // Methods for support type inquiry through isa, cast, and dyn_cast:
     static inline bool classof(const MemIntrinsic *) { return true; }
     static inline bool classof(const IntrinsicInst *I) {
@@ -192,14 +192,14 @@
   public:
     /// get* - Return the arguments to the instruction.
     ///
-    Value *getValue() const { return const_cast<Value*>(getOperand(2)); }
-    
+    Value *getValue() const { return const_cast<Value*>(getArgOperand(1)); }
+
     void setValue(Value *Val) {
       assert(getValue()->getType() == Val->getType() &&
-             "setSource called with pointer of wrong type!");
-      setOperand(2, Val);
+             "setValue called with value of wrong type!");
+      setArgOperand(1, Val);
     }
-    
+
     // Methods for support type inquiry through isa, cast, and dyn_cast:
     static inline bool classof(const MemSetInst *) { return true; }
     static inline bool classof(const IntrinsicInst *I) {
@@ -209,26 +209,26 @@
       return isa<IntrinsicInst>(V) && classof(cast<IntrinsicInst>(V));
     }
   };
-  
+
   /// MemTransferInst - This class wraps the llvm.memcpy/memmove intrinsics.
   ///
   class MemTransferInst : public MemIntrinsic {
   public:
     /// get* - Return the arguments to the instruction.
     ///
-    Value *getRawSource() const { return const_cast<Value*>(getOperand(2)); }
-    
+    Value *getRawSource() const { return const_cast<Value*>(getArgOperand(1)); }
+
     /// getSource - This is just like getRawSource, but it strips off any cast
     /// instructions that feed it, giving the original input.  The returned
     /// value is guaranteed to be a pointer.
     Value *getSource() const { return getRawSource()->stripPointerCasts(); }
-    
+
     void setSource(Value *Ptr) {
       assert(getRawSource()->getType() == Ptr->getType() &&
              "setSource called with pointer of wrong type!");
-      setOperand(2, Ptr);
+      setArgOperand(1, Ptr);
     }
-    
+
     // Methods for support type inquiry through isa, cast, and dyn_cast:
     static inline bool classof(const MemTransferInst *) { return true; }
     static inline bool classof(const IntrinsicInst *I) {
@@ -239,8 +239,8 @@
       return isa<IntrinsicInst>(V) && classof(cast<IntrinsicInst>(V));
     }
   };
-  
-  
+
+
   /// MemCpyInst - This class wraps the llvm.memcpy intrinsic.
   ///
   class MemCpyInst : public MemTransferInst {
@@ -282,7 +282,7 @@
       return isa<IntrinsicInst>(V) && classof(cast<IntrinsicInst>(V));
     }
   };
-  
+
   /// MemoryUseIntrinsic - This is the common base class for the memory use
   /// marker intrinsics.
   ///




From stoklund at 2pi.dk  Tue Jun 29 11:09:58 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 29 Jun 2010 09:09:58 -0700
Subject: [llvm-commits] [patch] Mostly mechanical removal of
	getPhysicalRegisterRegClass.patch
In-Reply-To: <AANLkTimv2smH65TcgkCg9oiuxTjE6yS13tfd3yLo9wGG@mail.gmail.com>
References: <AANLkTilqt5y4NglQZbWCS7S7jTdaybAvxWQD1-RqbhuK@mail.gmail.com>
	<D707A8E3-C6A1-4FD2-8DB8-FA88FC917365@2pi.dk>
	<AANLkTikDwVDsbrtjOTHmvi0U2OrJ6yjzqyI56d2-HGnm@mail.gmail.com>
	<AEFF279C-8A23-4753-A4A6-89640224C297@2pi.dk>
	<AANLkTimgBUUcE2-sTG0Qps20tS8qIh01LB61ABYZuY9e@mail.gmail.com>
	<EFEFA155-7FBA-4942-B731-575ABCD97A83@2pi.dk>
	<AANLkTinvjuW8OuHxExMJECtbVAd1GqyqFAX1JT5IM86-@mail.gmail.com>
	<AANLkTimv2smH65TcgkCg9oiuxTjE6yS13tfd3yLo9wGG@mail.gmail.com>
Message-ID: <AB82423F-0FCC-4038-B5C2-1F9FF6E4D838@2pi.dk>


On Jun 29, 2010, at 8:11 AM, Rafael Espindola wrote:

> On 29 June 2010 10:54, Anton Korobeynikov <asl at math.spbu.ru> wrote:
>> Hello, Jakob
>> 
>>> This is a little worrying, but probably not your fault.
>> Yes. This somehow seems to be a fallout from subreg indices unification.
>> 
>> Basically, the problem is that currently we can easily have
>> cross-domain switches while walking via subregs.
>> Look, for example, into DPR_VFP2 regclass. This class is used for NEON
>> code and thus all the stuff operates inside the NEON domain. It should
>> not contain any SPR subregs since there are no 32-bit reg-reg moves in
>> NEON (think about the core with VFP disabled, but not NEON).
>> 
>> In fact, this was the only reason why this regclass does exist - to
>> restrict the set of regs used for certain neon instructions.
> 
> I think we agreed on IRC. The issues is that the question "give me a
> regclass for D0" is ambiguous. Is that the NEON one or the VFP one? If
> we don't specify this, the existing DPR_VFP2 class is a valid answer
> and gives the copy creation extra freedom.
> 
> Since there are cases where we care a lot about moves from neon to
> vfp, we should make those explicit. I agree with Anton that what we
> should do is
> 
> *) Declare the neon registers as independent entities from the vfp
> registers (D0N, D1N, ...)
> *) Declare the class of neon registers. This will not intersect with
> the vfp register classes
> *) Declare move instructions between the two (COPY_TO_REGCLASS?). This
> will print just like a regular copy, but have a cost that reflects the
> move from neon to vfp or the other way.

I agree that a register subclass (DPR_VFP2) is not going to work for completely separating two execution domains, and a set of register aliases is the way to prevent that.

But is it really necessary? We already have the NEONMoveFix pass to handle this issue. Maybe it just needs to get a bit better? The test case in question is a two-instruction function:

	vmov.f32 s3, s0
	vmov.f64 d0, d1

It should be possible to pick the correct vmov in that case, but I am not surprised NEONMoveFix got it wrong.

The SSEDomainFixPass does something very similar, and it is close to being target independent. I was planning to do that, and use it for both SSE and NEON, but I never got around to it.

What do you think? For NEON it is literally just a question of picking the correct move instruction, nothing else. A whole new set of registers with aliasing to the old ones seems like overkill.

/jakob




From ggreif at gmail.com  Tue Jun 29 11:17:26 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Tue, 29 Jun 2010 16:17:26 -0000
Subject: [llvm-commits] [llvm] r107145 -
	/llvm/trunk/lib/VMCore/AutoUpgrade.cpp
Message-ID: <20100629161726.7496E2A6C12C@llvm.org>

Author: ggreif
Date: Tue Jun 29 11:17:26 2010
New Revision: 107145

URL: http://llvm.org/viewvc/llvm-project?rev=107145&view=rev
Log:
use ArgOperand API

Modified:
    llvm/trunk/lib/VMCore/AutoUpgrade.cpp

Modified: llvm/trunk/lib/VMCore/AutoUpgrade.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AutoUpgrade.cpp?rev=107145&r1=107144&r2=107145&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/AutoUpgrade.cpp (original)
+++ llvm/trunk/lib/VMCore/AutoUpgrade.cpp Tue Jun 29 11:17:26 2010
@@ -429,9 +429,9 @@
       // Remove upgraded multiply.
       CI->eraseFromParent();
     } else if (F->getName() == "llvm.x86.ssse3.palign.r") {
-      Value *Op1 = CI->getOperand(1);
-      Value *Op2 = CI->getOperand(2);
-      Value *Op3 = CI->getOperand(3);
+      Value *Op1 = CI->getArgOperand(0);
+      Value *Op2 = CI->getArgOperand(1);
+      Value *Op3 = CI->getArgOperand(2);
       unsigned shiftVal = cast<ConstantInt>(Op3)->getZExtValue();
       Value *Rep;
       IRBuilder<> Builder(C);
@@ -485,9 +485,9 @@
       CI->eraseFromParent();
       
     } else if (F->getName() == "llvm.x86.ssse3.palign.r.128") {
-      Value *Op1 = CI->getOperand(1);
-      Value *Op2 = CI->getOperand(2);
-      Value *Op3 = CI->getOperand(3);
+      Value *Op1 = CI->getArgOperand(0);
+      Value *Op2 = CI->getArgOperand(1);
+      Value *Op3 = CI->getArgOperand(2);
       unsigned shiftVal = cast<ConstantInt>(Op3)->getZExtValue();
       Value *Rep;
       IRBuilder<> Builder(C);




From ggreif at gmail.com  Tue Jun 29 11:21:21 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Tue, 29 Jun 2010 16:21:21 -0000
Subject: [llvm-commits] [llvm] r107146 -
	/llvm/trunk/include/llvm/Instructions.h
Message-ID: <20100629162121.271562A6C12C@llvm.org>

Author: ggreif
Date: Tue Jun 29 11:21:20 2010
New Revision: 107146

URL: http://llvm.org/viewvc/llvm-project?rev=107146&view=rev
Log:
use ArgOffset constant to prepare for operand rotation

Modified:
    llvm/trunk/include/llvm/Instructions.h

Modified: llvm/trunk/include/llvm/Instructions.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=107146&r1=107145&r2=107146&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Instructions.h (original)
+++ llvm/trunk/include/llvm/Instructions.h Tue Jun 29 11:21:20 2010
@@ -1039,17 +1039,17 @@
   /// indirect function invocation.
   ///
   Function *getCalledFunction() const {
-    return dyn_cast<Function>(Op<0>());
+    return dyn_cast<Function>(Op<ArgOffset -1>());
   }
 
   /// getCalledValue - Get a pointer to the function that is invoked by this
   /// instruction.
-  const Value *getCalledValue() const { return Op<0>(); }
-        Value *getCalledValue()       { return Op<0>(); }
+  const Value *getCalledValue() const { return Op<ArgOffset -1>(); }
+        Value *getCalledValue()       { return Op<ArgOffset -1>(); }
 
   /// setCalledFunction - Set the function called.
   void setCalledFunction(Value* Fn) {
-    Op<0>() = Fn;
+    Op<ArgOffset -1>() = Fn;
   }
 
   // Methods for support type inquiry through isa, cast, and dyn_cast:




From bob.wilson at apple.com  Tue Jun 29 11:25:11 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Tue, 29 Jun 2010 16:25:11 -0000
Subject: [llvm-commits] [llvm] r107147 -
	/llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
Message-ID: <20100629162511.C5AC12A6C12C@llvm.org>

Author: bwilson
Date: Tue Jun 29 11:25:11 2010
New Revision: 107147

URL: http://llvm.org/viewvc/llvm-project?rev=107147&view=rev
Log:
The t2MOVi16 and t2MOVTi16 instructions do not set CPSR.  Trying to add
a CPSR operand to them causes an assertion failure, so apparently these
instructions haven't been getting a lot of use.

Modified:
    llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp

Modified: llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp?rev=107147&r1=107146&r2=107147&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp Tue Jun 29 11:25:11 2010
@@ -224,14 +224,14 @@
       // Use a movw to materialize the 16-bit constant.
       BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
         .addImm(NumBytes)
-        .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
+        .addImm((unsigned)Pred).addReg(PredReg);
       Fits = true;
     } else if ((NumBytes & 0xffff) == 0) {
       // Use a movt to materialize the 32-bit constant.
       BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
         .addReg(DestReg)
         .addImm(NumBytes >> 16)
-        .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
+        .addImm((unsigned)Pred).addReg(PredReg);
       Fits = true;
     }
 




From ggreif at gmail.com  Tue Jun 29 11:27:38 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Tue, 29 Jun 2010 16:27:38 -0000
Subject: [llvm-commits] [llvm] r107148 -
	/llvm/trunk/include/llvm/Instructions.h
Message-ID: <20100629162738.C7EC02A6C12C@llvm.org>

Author: ggreif
Date: Tue Jun 29 11:27:38 2010
New Revision: 107148

URL: http://llvm.org/viewvc/llvm-project?rev=107148&view=rev
Log:
minor cosmetics

Modified:
    llvm/trunk/include/llvm/Instructions.h

Modified: llvm/trunk/include/llvm/Instructions.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=107148&r1=107147&r2=107148&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Instructions.h (original)
+++ llvm/trunk/include/llvm/Instructions.h Tue Jun 29 11:27:38 2010
@@ -1079,7 +1079,7 @@
                                    ->getElementType())->getReturnType(),
                 Instruction::Call,
                 OperandTraits<CallInst>::op_end(this) - (ArgEnd - ArgBegin + 1),
-                (unsigned)(ArgEnd - ArgBegin + 1), InsertAtEnd) {
+                unsigned(ArgEnd - ArgBegin + 1), InsertAtEnd) {
   init(Func, ArgBegin, ArgEnd, NameStr,
        typename std::iterator_traits<InputIterator>::iterator_category());
 }




From grosbach at apple.com  Tue Jun 29 11:55:25 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 29 Jun 2010 16:55:25 -0000
Subject: [llvm-commits] [llvm] r107154 -
	/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
Message-ID: <20100629165525.13F472A6C12C@llvm.org>

Author: grosbach
Date: Tue Jun 29 11:55:24 2010
New Revision: 107154

URL: http://llvm.org/viewvc/llvm-project?rev=107154&view=rev
Log:
skip dbg_value instructions

Modified:
    llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp

Modified: llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp?rev=107154&r1=107153&r2=107154&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp Tue Jun 29 11:55:24 2010
@@ -410,6 +410,8 @@
   // before that instead and adjust the UseMI.
   bool done = false;
   for (MachineBasicBlock::iterator II = I; !done && II != UseMI ; ++II) {
+    if (II->isDebugValue())
+      continue;
     // If this instruction affects R12, adjust our restore point.
     for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
       const MachineOperand &MO = II->getOperand(i);




From criswell at uiuc.edu  Tue Jun 29 12:17:05 2010
From: criswell at uiuc.edu (John Criswell)
Date: Tue, 29 Jun 2010 17:17:05 -0000
Subject: [llvm-commits] [poolalloc] r107164 -
	/poolalloc/trunk/lib/DSA/DSGraph.cpp
Message-ID: <20100629171705.0FAB82A6C12C@llvm.org>

Author: criswell
Date: Tue Jun 29 12:17:04 2010
New Revision: 107164

URL: http://llvm.org/viewvc/llvm-project?rev=107164&view=rev
Log:
Modified the DSGraph::computeNodeMapping() method so that it passes its
StrictChecking parameter to itself in recursive calls.
Added comments.

Modified:
    poolalloc/trunk/lib/DSA/DSGraph.cpp

Modified: poolalloc/trunk/lib/DSA/DSGraph.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DSGraph.cpp?rev=107164&r1=107163&r2=107164&view=diff
==============================================================================
--- poolalloc/trunk/lib/DSA/DSGraph.cpp (original)
+++ poolalloc/trunk/lib/DSA/DSGraph.cpp Tue Jun 29 12:17:04 2010
@@ -1160,9 +1160,28 @@
 /// graph may have multiple nodes representing one node in the second graph),
 /// but it will not work if there is a one-to-many or many-to-many mapping.
 ///
+/// Inputs:
+///   @NH1            - The first root value for which a node mapping is
+///                     desired.  This value can have a NULL DSNode.
+///   @NH2            - The second root value for which a node mapping is
+///                     desired.  This value can have a NULL DSNode.
+///   @StrictChecking - Flags whether strict sanity checks should be enforced.
+///
+/// Outputs:
+///   @NodeMap - A mapping of DSNodes to DSNode handles providing the node
+///              mapping desired by the caller.
+///
+/// Notes:
+///   FIXME: Why was StrictChecking not passed in the recursive calls?
+///   FIXME: Why isn't StrictChecking always desired?
+///
 void DSGraph::computeNodeMapping(const DSNodeHandle &NH1,
                                  const DSNodeHandle &NH2, NodeMapTy &NodeMap,
                                  bool StrictChecking) {
+  //
+  // Get the DSNodes associated with the root values.  If either one of them is
+  // NULL, then we are done.
+  //
   DSNode *N1 = NH1.getNode(), *N2 = NH2.getNode();
   if (N1 == 0 || N2 == 0) return;
 
@@ -1192,10 +1211,10 @@
     // aligned right).
     if (!N1NH.isNull()) {
       if (unsigned(N2Idx)+i < N2Size)
-        computeNodeMapping(N1NH, N2->getLink(N2Idx+i), NodeMap);
+        computeNodeMapping(N1NH, N2->getLink(N2Idx+i), NodeMap, StrictChecking);
       else
         computeNodeMapping(N1NH,
-                           N2->getLink(unsigned(N2Idx+i) % N2Size), NodeMap);
+                           N2->getLink(unsigned(N2Idx+i) % N2Size), NodeMap, StrictChecking);
     }
   }
 }




From criswell at uiuc.edu  Tue Jun 29 12:17:52 2010
From: criswell at uiuc.edu (John Criswell)
Date: Tue, 29 Jun 2010 17:17:52 -0000
Subject: [llvm-commits] [poolalloc] r107165 -
 /poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp
Message-ID: <20100629171752.D5AFA2A6C12C@llvm.org>

Author: criswell
Date: Tue Jun 29 12:17:52 2010
New Revision: 107165

URL: http://llvm.org/viewvc/llvm-project?rev=107165&view=rev
Log:
Added comment on the use of StrictChecking when calling
DSGraph::computeNodeMapping().
Improved code formatting.

Modified:
    poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp

Modified: poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp?rev=107165&r1=107164&r2=107165&view=diff
==============================================================================
--- poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp (original)
+++ poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp Tue Jun 29 12:17:52 2010
@@ -801,12 +801,18 @@
     NewCallee = CastInst::CreatePointerCast(CS.getCalledValue(), PFTy, "tmp", TheCall);
   }
 
+  //
+  // FIXME: Why do we disable strict checking when calling the
+  //        DSGraph::computeNodeMapping() method?
+  //
   Function::const_arg_iterator FAI = CF->arg_begin(), E = CF->arg_end();
-  CallSite::arg_iterator AI = CS.arg_begin() + (thread_creation_point ? 3 : 0), AE = CS.arg_end();
+  CallSite::arg_iterator AI = CS.arg_begin() + (thread_creation_point ? 3 : 0);
+  CallSite::arg_iterator AE = CS.arg_end();
   for ( ; FAI != E && AI != AE; ++FAI, ++AI)
-    if (!isa<Constant>(*AI))
+    if (!isa<Constant>(*AI)) {
       DSGraph::computeNodeMapping(CalleeGraph->getNodeForValue(FAI),
                                   getDSNodeHFor(*AI), NodeMapping, false);
+    }
 
   //assert(AI == AE && "Varargs calls not handled yet!");
 




From bruno.cardoso at gmail.com  Tue Jun 29 12:26:30 2010
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Tue, 29 Jun 2010 17:26:30 -0000
Subject: [llvm-commits] [llvm] r107166 - in /llvm/trunk:
 lib/Target/X86/X86InstrSSE.td test/MC/AsmParser/X86/x86_32-encoding.s
 test/MC/AsmParser/X86/x86_64-encoding.s
Message-ID: <20100629172631.2CD852A6C12C@llvm.org>

Author: bruno
Date: Tue Jun 29 12:26:30 2010
New Revision: 107166

URL: http://llvm.org/viewvc/llvm-project?rev=107166&view=rev
Log:
Add sqrt, rsqrt and rcp AVX instructions

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
    llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=107166&r1=107165&r2=107166&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Jun 29 12:26:30 2010
@@ -1873,7 +1873,7 @@
 
 /// sse1_fp_unop_s - SSE1 unops in scalar form.
 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
-                           SDNode OpNode, Intrinsic F32Int> {
+                          SDNode OpNode, Intrinsic F32Int> {
   def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
                 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
                 [(set FR32:$dst, (OpNode FR32:$src))]>;
@@ -1906,6 +1906,26 @@
                     [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
 }
 
+/// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
+multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
+                              SDNode OpNode, Intrinsic F32Int> {
+  def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
+                !strconcat(!strconcat("v", OpcodeStr),
+                           "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
+  def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2),
+                !strconcat(!strconcat("v", OpcodeStr),
+                           "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+                []>, XS, Requires<[HasAVX, HasSSE1, OptForSize]>;
+  def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
+                (ins VR128:$src1, VR128:$src2),
+                !strconcat(!strconcat("v", OpcodeStr),
+                           "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
+  def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
+                (ins VR128:$src1, ssmem:$src2),
+                !strconcat(!strconcat("v", OpcodeStr),
+                           "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
+}
+
 /// sse2_fp_unop_s - SSE2 unops in scalar form.
 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
                           SDNode OpNode, Intrinsic F64Int> {
@@ -1940,6 +1960,52 @@
                     [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
 }
 
+/// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
+multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
+                              SDNode OpNode, Intrinsic F64Int> {
+  def SDr : VSDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
+                !strconcat(OpcodeStr,
+                           "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
+  def SDm : VSDI<opc, MRMSrcMem, (outs FR64:$dst),
+                (ins FR64:$src1, f64mem:$src2),
+                !strconcat(OpcodeStr,
+                           "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
+  def SDr_Int : VSDI<opc, MRMSrcReg, (outs VR128:$dst),
+           (ins VR128:$src1, VR128:$src2),
+           !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+                    []>;
+  def SDm_Int : VSDI<opc, MRMSrcMem, (outs VR128:$dst),
+           (ins VR128:$src1, sdmem:$src2),
+           !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+                    []>;
+}
+
+let isAsmParserOnly = 1 in {
+  // Square root.
+  let Predicates = [HasAVX, HasSSE2] in {
+  defm VSQRT  : sse2_fp_unop_s_avx<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
+                  VEX_4V;
+
+  defm VSQRT  : sse2_fp_unop_p<0x51, "vsqrt", fsqrt, int_x86_sse2_sqrt_pd>, VEX;
+  }
+
+  let Predicates = [HasAVX, HasSSE1] in {
+  defm VSQRT  : sse1_fp_unop_s_avx<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
+                  VEX_4V;
+  defm VSQRT  : sse1_fp_unop_p<0x51, "vsqrt", fsqrt, int_x86_sse_sqrt_ps>, VEX;
+  // Reciprocal approximations. Note that these typically require refinement
+  // in order to obtain suitable precision.
+  defm VRSQRT : sse1_fp_unop_s_avx<0x52, "rsqrt", X86frsqrt,
+                                   int_x86_sse_rsqrt_ss>, VEX_4V;
+  defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt, int_x86_sse_rsqrt_ps>,
+                                   VEX;
+  defm VRCP   : sse1_fp_unop_s_avx<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
+                                   VEX_4V;
+  defm VRCP   : sse1_fp_unop_p<0x53, "vrcp", X86frcp, int_x86_sse_rcp_ps>,
+                                   VEX;
+  }
+}
+
 // Square root.
 defm SQRT  : sse1_fp_unop_s<0x51, "sqrt",  fsqrt, int_x86_sse_sqrt_ss>,
              sse1_fp_unop_p<0x51, "sqrt",  fsqrt, int_x86_sse_sqrt_ps>,

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s?rev=107166&r1=107165&r2=107166&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s Tue Jun 29 12:26:30 2010
@@ -10873,3 +10873,68 @@
 // CHECK: vcvtpd2ps  %xmm2, %xmm3
 // CHECK: encoding: [0xc5,0xf9,0x5a,0xda]
           vcvtpd2ps  %xmm2, %xmm3
+
+// CHECK: vsqrtpd  %xmm1, %xmm2
+// CHECK: encoding: [0xc5,0xf9,0x51,0xd1]
+          vsqrtpd  %xmm1, %xmm2
+
+// CHECK: vsqrtpd  (%eax), %xmm2
+// CHECK: encoding: [0xc5,0xf9,0x51,0x10]
+          vsqrtpd  (%eax), %xmm2
+
+// CHECK: vsqrtps  %xmm1, %xmm2
+// CHECK: encoding: [0xc5,0xf8,0x51,0xd1]
+          vsqrtps  %xmm1, %xmm2
+
+// CHECK: vsqrtps  (%eax), %xmm2
+// CHECK: encoding: [0xc5,0xf8,0x51,0x10]
+          vsqrtps  (%eax), %xmm2
+
+// CHECK: vsqrtsd  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xeb,0x51,0xd9]
+          vsqrtsd  %xmm1, %xmm2, %xmm3
+
+// CHECK: vsqrtsd  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xeb,0x51,0x18]
+          vsqrtsd  (%eax), %xmm2, %xmm3
+
+// CHECK: vsqrtss  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xea,0x51,0xd9]
+          vsqrtss  %xmm1, %xmm2, %xmm3
+
+// CHECK: vsqrtss  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xea,0x51,0x18]
+          vsqrtss  (%eax), %xmm2, %xmm3
+
+// CHECK: vrsqrtps  %xmm1, %xmm2
+// CHECK: encoding: [0xc5,0xf8,0x52,0xd1]
+          vrsqrtps  %xmm1, %xmm2
+
+// CHECK: vrsqrtps  (%eax), %xmm2
+// CHECK: encoding: [0xc5,0xf8,0x52,0x10]
+          vrsqrtps  (%eax), %xmm2
+
+// CHECK: vrsqrtss  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xea,0x52,0xd9]
+          vrsqrtss  %xmm1, %xmm2, %xmm3
+
+// CHECK: vrsqrtss  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xea,0x52,0x18]
+          vrsqrtss  (%eax), %xmm2, %xmm3
+
+// CHECK: vrcpps  %xmm1, %xmm2
+// CHECK: encoding: [0xc5,0xf8,0x53,0xd1]
+          vrcpps  %xmm1, %xmm2
+
+// CHECK: vrcpps  (%eax), %xmm2
+// CHECK: encoding: [0xc5,0xf8,0x53,0x10]
+          vrcpps  (%eax), %xmm2
+
+// CHECK: vrcpss  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xea,0x53,0xd9]
+          vrcpss  %xmm1, %xmm2, %xmm3
+
+// CHECK: vrcpss  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xea,0x53,0x18]
+          vrcpss  (%eax), %xmm2, %xmm3
+

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s?rev=107166&r1=107165&r2=107166&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s Tue Jun 29 12:26:30 2010
@@ -922,3 +922,67 @@
 // CHECK: encoding: [0xc4,0x41,0x79,0x5a,0xdc]
           vcvtpd2ps  %xmm12, %xmm11
 
+// CHECK: vsqrtpd  %xmm11, %xmm12
+// CHECK: encoding: [0xc4,0x41,0x79,0x51,0xe3]
+          vsqrtpd  %xmm11, %xmm12
+
+// CHECK: vsqrtpd  (%rax), %xmm12
+// CHECK: encoding: [0xc5,0x79,0x51,0x20]
+          vsqrtpd  (%rax), %xmm12
+
+// CHECK: vsqrtps  %xmm11, %xmm12
+// CHECK: encoding: [0xc4,0x41,0x78,0x51,0xe3]
+          vsqrtps  %xmm11, %xmm12
+
+// CHECK: vsqrtps  (%rax), %xmm12
+// CHECK: encoding: [0xc5,0x78,0x51,0x20]
+          vsqrtps  (%rax), %xmm12
+
+// CHECK: vsqrtsd  %xmm11, %xmm12, %xmm10
+// CHECK: encoding: [0xc4,0x41,0x1b,0x51,0xd3]
+          vsqrtsd  %xmm11, %xmm12, %xmm10
+
+// CHECK: vsqrtsd  (%rax), %xmm12, %xmm10
+// CHECK: encoding: [0xc5,0x1b,0x51,0x10]
+          vsqrtsd  (%rax), %xmm12, %xmm10
+
+// CHECK: vsqrtss  %xmm11, %xmm12, %xmm10
+// CHECK: encoding: [0xc4,0x41,0x1a,0x51,0xd3]
+          vsqrtss  %xmm11, %xmm12, %xmm10
+
+// CHECK: vsqrtss  (%rax), %xmm12, %xmm10
+// CHECK: encoding: [0xc5,0x1a,0x51,0x10]
+          vsqrtss  (%rax), %xmm12, %xmm10
+
+// CHECK: vrsqrtps  %xmm11, %xmm12
+// CHECK: encoding: [0xc4,0x41,0x78,0x52,0xe3]
+          vrsqrtps  %xmm11, %xmm12
+
+// CHECK: vrsqrtps  (%rax), %xmm12
+// CHECK: encoding: [0xc5,0x78,0x52,0x20]
+          vrsqrtps  (%rax), %xmm12
+
+// CHECK: vrsqrtss  %xmm11, %xmm12, %xmm10
+// CHECK: encoding: [0xc4,0x41,0x1a,0x52,0xd3]
+          vrsqrtss  %xmm11, %xmm12, %xmm10
+
+// CHECK: vrsqrtss  (%rax), %xmm12, %xmm10
+// CHECK: encoding: [0xc5,0x1a,0x52,0x10]
+          vrsqrtss  (%rax), %xmm12, %xmm10
+
+// CHECK: vrcpps  %xmm11, %xmm12
+// CHECK: encoding: [0xc4,0x41,0x78,0x53,0xe3]
+          vrcpps  %xmm11, %xmm12
+
+// CHECK: vrcpps  (%rax), %xmm12
+// CHECK: encoding: [0xc5,0x78,0x53,0x20]
+          vrcpps  (%rax), %xmm12
+
+// CHECK: vrcpss  %xmm11, %xmm12, %xmm10
+// CHECK: encoding: [0xc4,0x41,0x1a,0x53,0xd3]
+          vrcpss  %xmm11, %xmm12, %xmm10
+
+// CHECK: vrcpss  (%rax), %xmm12, %xmm10
+// CHECK: encoding: [0xc5,0x1a,0x53,0x10]
+          vrcpss  (%rax), %xmm12, %xmm10
+




From bob.wilson at apple.com  Tue Jun 29 12:34:07 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Tue, 29 Jun 2010 17:34:07 -0000
Subject: [llvm-commits] [llvm] r107167 -
	/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
Message-ID: <20100629173407.B168F2A6C12C@llvm.org>

Author: bwilson
Date: Tue Jun 29 12:34:07 2010
New Revision: 107167

URL: http://llvm.org/viewvc/llvm-project?rev=107167&view=rev
Log:
Add support for encoding NEON VMOV (from core register to scalar) instructions.
The encoding is the same as VMOV (from scalar to core register) except that
the operands are in different places.

Modified:
    llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=107167&r1=107166&r2=107167&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Tue Jun 29 12:34:07 2010
@@ -140,7 +140,7 @@
 
     void emitMiscInstruction(const MachineInstr &MI);
 
-    void emitNEONGetLaneInstruction(const MachineInstr &MI);
+    void emitNEONLaneInstruction(const MachineInstr &MI);
     void emitNEON1RegModImmInstruction(const MachineInstr &MI);
     void emitNEON2RegInstruction(const MachineInstr &MI);
     void emitNEON3RegInstruction(const MachineInstr &MI);
@@ -417,7 +417,8 @@
     break;
   // NEON instructions.
   case ARMII::NGetLnFrm:
-    emitNEONGetLaneInstruction(MI);
+  case ARMII::NSetLnFrm:
+    emitNEONLaneInstruction(MI);
     break;
   case ARMII::N1RegModImmFrm:
     emitNEON1RegModImmInstruction(MI);
@@ -1596,16 +1597,28 @@
   return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
 }
 
-void ARMCodeEmitter::emitNEONGetLaneInstruction(const MachineInstr &MI) {
+void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
   unsigned Binary = getBinaryCodeForInstr(MI);
 
+  unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
+  const TargetInstrDesc &TID = MI.getDesc();
+  if ((TID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
+    RegTOpIdx = 0;
+    RegNOpIdx = 1;
+    LnOpIdx = 2;
+  } else { // ARMII::NSetLnFrm
+    RegTOpIdx = 2;
+    RegNOpIdx = 0;
+    LnOpIdx = 3;
+  }
+
   // Set the conditional execution predicate
   Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
 
-  unsigned RegT = MI.getOperand(0).getReg();
+  unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
   RegT = ARMRegisterInfo::getRegisterNumbering(RegT);
   Binary |= (RegT << ARMII::RegRdShift);
-  Binary |= encodeNEONRn(MI, 1);
+  Binary |= encodeNEONRn(MI, RegNOpIdx);
 
   unsigned LaneShift;
   if ((Binary & (1 << 22)) != 0)
@@ -1615,7 +1628,7 @@
   else
     LaneShift = 2; // 32-bit elements
 
-  unsigned Lane = MI.getOperand(2).getImm() << LaneShift;
+  unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
   unsigned Opc1 = Lane >> 2;
   unsigned Opc2 = Lane & 3;
   assert((Opc1 & 3) == 0 && "out-of-range lane number operand");




From bruno.cardoso at gmail.com  Tue Jun 29 12:42:37 2010
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Tue, 29 Jun 2010 17:42:37 -0000
Subject: [llvm-commits] [llvm] r107168 -
	/llvm/trunk/lib/Target/X86/X86InstrSSE.td
Message-ID: <20100629174237.DD7662A6C12C@llvm.org>

Author: bruno
Date: Tue Jun 29 12:42:37 2010
New Revision: 107168

URL: http://llvm.org/viewvc/llvm-project?rev=107168&view=rev
Log:
Move non-temporal movs to their own section

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=107168&r1=107167&r2=107168&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Jun 29 12:42:37 2010
@@ -2019,25 +2019,24 @@
 defm RCP   : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
              sse1_fp_unop_p<0x53, "rcp", X86frcp, int_x86_sse_rcp_ps>;
 
-// Prefetch intrinsic.
-def PREFETCHT0   : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
-    "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
-def PREFETCHT1   : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
-    "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
-def PREFETCHT2   : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
-    "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
-def PREFETCHNTA  : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
-    "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
+//===----------------------------------------------------------------------===//
+// SSE 1 & 2 - Non-temporal stores
+//===----------------------------------------------------------------------===//
 
-// Non-temporal stores
 def MOVNTPSmr_Int : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
                     "movntps\t{$src, $dst|$dst, $src}",
                     [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
+def MOVNTPDmr_Int : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
+                        "movntpd\t{$src, $dst|$dst, $src}",
+                        [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
 
 let AddedComplexity = 400 in { // Prefer non-temporal versions
 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
                     "movntps\t{$src, $dst|$dst, $src}",
                     [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
+def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
+                    "movntpd\t{$src, $dst|$dst, $src}",
+                    [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
 
 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
                     "movntdq\t{$src, $dst|$dst, $src}",
@@ -2052,8 +2051,37 @@
                      "movnti\t{$src, $dst|$dst, $src}",
                      [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
                   TB, Requires<[HasSSE2]>;
+
+let ExeDomain = SSEPackedInt in
+def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
+                    "movntdq\t{$src, $dst|$dst, $src}",
+                    [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
 }
 
+let ExeDomain = SSEPackedInt in
+def MOVNTDQmr_Int : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
+                        "movntdq\t{$src, $dst|$dst, $src}",
+                        [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
+
+def MOVNTImr_Int  :   I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
+                    "movnti\t{$src, $dst|$dst, $src}",
+                    [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
+                  TB, Requires<[HasSSE2]>;
+
+//===----------------------------------------------------------------------===//
+// SSE 1 & 2 - Misc Instructions
+//===----------------------------------------------------------------------===//
+
+// Prefetch intrinsic.
+def PREFETCHT0   : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
+    "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
+def PREFETCHT1   : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
+    "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
+def PREFETCHT2   : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
+    "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
+def PREFETCHNTA  : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
+    "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
+
 // Load, store, and memory fence
 def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
              TB, Requires<[HasSSE1]>;
@@ -2496,30 +2524,6 @@
 
 } // ExeDomain = SSEPackedInt
 
-// Non-temporal stores
-def MOVNTPDmr_Int : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
-                        "movntpd\t{$src, $dst|$dst, $src}",
-                        [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
-let ExeDomain = SSEPackedInt in
-def MOVNTDQmr_Int : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
-                        "movntdq\t{$src, $dst|$dst, $src}",
-                        [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
-def MOVNTImr_Int  :   I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
-                    "movnti\t{$src, $dst|$dst, $src}",
-                    [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
-                  TB, Requires<[HasSSE2]>;
-
-let AddedComplexity = 400 in { // Prefer non-temporal versions
-def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
-                    "movntpd\t{$src, $dst|$dst, $src}",
-                    [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
-
-let ExeDomain = SSEPackedInt in
-def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
-                    "movntdq\t{$src, $dst|$dst, $src}",
-                    [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
-}
-
 // Flush cache
 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
                "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,




From gohman at apple.com  Tue Jun 29 13:09:59 2010
From: gohman at apple.com (Dan Gohman)
Date: Tue, 29 Jun 2010 11:09:59 -0700
Subject: [llvm-commits] [llvm] r107109 - in /llvm/trunk:
	include/llvm/Analysis/AliasAnalysis.h
	include/llvm/Analysis/Passes.h lib/Analysis/AliasAnalysis.cpp
	lib/Analysis/BasicAliasAnalysis.cpp
	test/Analysis/BasicAA/interprocedural.ll
In-Reply-To: <4C298317.7050002@mxc.ca>
References: <20100629005039.39B192A6C12C@llvm.org> <4C298317.7050002@mxc.ca>
Message-ID: <5E31E70D-BC94-4545-BE28-F8927D72097F@apple.com>


On Jun 28, 2010, at 10:22 PM, Nick Lewycky wrote:

> Dan Gohman wrote:
>> Author: djg
>> Date: Mon Jun 28 19:50:39 2010
>> New Revision: 107109
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=107109&view=rev
>> Log:
>> Add an Intraprocedural form of BasicAliasAnalysis, which aims to
>> properly handles instructions and arguments defined in different
>> functions, or across recursive function iterations.
> 
> Dan,
> 
> Why is this an additional pass? Why not infer Interprocedural from SameParent()? The idempotents that basicaa was testing for should still hold true whenever SameParent() is true. It looks like the 'Interprocedural BasicAA' is basically a bugfix on BasicAA.

"noalias" is only meaningful from a single-procedure perspective.
For example:

@G = external global i32
define void @foo(i32* noalias %p) {
  ...
}
...
  call void @foo(i32* @G)

If you're working exclusively within the body of @foo, then alias(@G, %p)
can be NoAlias. From an interprocedural perspective, it can be MustAlias.
Even with something like

define void @bar(double* noalias %a, double* noalias %b) {

it isn't trivial to say that %a doesn't alias %b because if it goes on to do

  call void @bar(double* %b, double* %a)

then there is a sense in which %a could MustAlias %b, interprocedurally.

Then there's "arguments can't alias allocas" logic. From a non-interprocedural
perspective, this works. From an interprocedural perspective, consider
function r0 in the included testcase.

With extra analysis, InterproceduralBasicAliasAnalysis could get more
precise answers. The current code is just an initial effort.

Another interesting thing to consider is that the current alias API
doesn't provide a way to specify the scope to consider for potential
aliasing.

Dan




From gohman at apple.com  Tue Jun 29 13:12:35 2010
From: gohman at apple.com (Dan Gohman)
Date: Tue, 29 Jun 2010 18:12:35 -0000
Subject: [llvm-commits] [llvm] r107175 -
	/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp
Message-ID: <20100629181235.0CA122A6C12D@llvm.org>

Author: djg
Date: Tue Jun 29 13:12:34 2010
New Revision: 107175

URL: http://llvm.org/viewvc/llvm-project?rev=107175&view=rev
Log:
Fix whitespace style.

Modified:
    llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp

Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=107175&r1=107174&r2=107175&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Tue Jun 29 13:12:34 2010
@@ -199,10 +199,10 @@
 
 #ifdef XDEBUG
 static const Function *getParent(const Value *V) {
-  if(const Instruction *inst = dyn_cast<Instruction>(V))
+  if (const Instruction *inst = dyn_cast<Instruction>(V))
     return inst->getParent()->getParent();
 
-  if(const Argument *arg = dyn_cast<Argument>(V))
+  if (const Argument *arg = dyn_cast<Argument>(V))
     return arg->getParent();
 
   return NULL;




From gohman at apple.com  Tue Jun 29 13:17:11 2010
From: gohman at apple.com (Dan Gohman)
Date: Tue, 29 Jun 2010 18:17:11 -0000
Subject: [llvm-commits] [llvm] r107177 -
	/llvm/trunk/test/Analysis/BasicAA/interprocedural.ll
Message-ID: <20100629181711.693CE2A6C12C@llvm.org>

Author: djg
Date: Tue Jun 29 13:17:11 2010
New Revision: 107177

URL: http://llvm.org/viewvc/llvm-project?rev=107177&view=rev
Log:
Add a few more interesting testcases.

Modified:
    llvm/trunk/test/Analysis/BasicAA/interprocedural.ll

Modified: llvm/trunk/test/Analysis/BasicAA/interprocedural.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/BasicAA/interprocedural.ll?rev=107177&r1=107176&r2=107177&view=diff
==============================================================================
--- llvm/trunk/test/Analysis/BasicAA/interprocedural.ll (original)
+++ llvm/trunk/test/Analysis/BasicAA/interprocedural.ll Tue Jun 29 13:17:11 2010
@@ -40,3 +40,24 @@
   store i64 0, i64* %v
   ret i64* %t
 }
+
+; The noalias attribute is not necessarily safe in an interprocedural context even
+; in comparison to other noalias arguments in the same function.
+; CHECK: MayAlias: i8* %w, i8* %x
+
+define void @q0(i8* noalias %w, i8* noalias %x) {
+  store i8 0, i8* %w
+  store i8 0, i8* %x
+  call void @q0(i8* noalias %x, i8* noalias %w)
+  unreachable
+}
+
+; The noalias attribute is not necessarily safe in an interprocedural context.
+; CHECK: MayAlias: double* %y, double* @G
+
+ at G = external global double
+define void @p0(double* noalias %y) {
+  store double 0.0, double* %y
+  store double 0.0, double* @G
+  unreachable
+}




From bruno.cardoso at gmail.com  Tue Jun 29 13:22:01 2010
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Tue, 29 Jun 2010 18:22:01 -0000
Subject: [llvm-commits] [llvm] r107178 - in /llvm/trunk:
 lib/Target/X86/X86InstrSSE.td test/MC/AsmParser/X86/x86_32-encoding.s
 test/MC/AsmParser/X86/x86_64-encoding.s
Message-ID: <20100629182201.514E42A6C12C@llvm.org>

Author: bruno
Date: Tue Jun 29 13:22:01 2010
New Revision: 107178

URL: http://llvm.org/viewvc/llvm-project?rev=107178&view=rev
Log:
Add AVX non-temporal stores

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
    llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=107178&r1=107177&r2=107178&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Jun 29 13:22:01 2010
@@ -2023,6 +2023,47 @@
 // SSE 1 & 2 - Non-temporal stores
 //===----------------------------------------------------------------------===//
 
+let isAsmParserOnly = 1 in {
+  def VMOVNTPSmr_Int : VPSI<0x2B, MRMDestMem, (outs),
+                         (ins i128mem:$dst, VR128:$src),
+                         "movntps\t{$src, $dst|$dst, $src}",
+                         [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>, VEX;
+  def VMOVNTPDmr_Int : VPDI<0x2B, MRMDestMem, (outs),
+                         (ins i128mem:$dst, VR128:$src),
+                         "movntpd\t{$src, $dst|$dst, $src}",
+                         [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>, VEX;
+
+  let ExeDomain = SSEPackedInt in
+    def VMOVNTDQmr_Int : VPDI<0xE7, MRMDestMem, (outs),
+                       (ins f128mem:$dst, VR128:$src),
+                       "movntdq\t{$src, $dst|$dst, $src}",
+                       [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>, VEX;
+
+  let AddedComplexity = 400 in { // Prefer non-temporal versions
+    def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
+                         (ins f128mem:$dst, VR128:$src),
+                         "movntps\t{$src, $dst|$dst, $src}",
+                         [(alignednontemporalstore (v4f32 VR128:$src),
+                                                   addr:$dst)]>, VEX;
+    def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
+                         (ins f128mem:$dst, VR128:$src),
+                         "movntpd\t{$src, $dst|$dst, $src}",
+                         [(alignednontemporalstore (v2f64 VR128:$src),
+                                                   addr:$dst)]>, VEX;
+    def VMOVNTDQ_64mr : VPDI<0xE7, MRMDestMem, (outs),
+                          (ins f128mem:$dst, VR128:$src),
+                          "movntdq\t{$src, $dst|$dst, $src}",
+                          [(alignednontemporalstore (v2f64 VR128:$src),
+                                                    addr:$dst)]>, VEX;
+    let ExeDomain = SSEPackedInt in
+    def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
+                        (ins f128mem:$dst, VR128:$src),
+                        "movntdq\t{$src, $dst|$dst, $src}",
+                        [(alignednontemporalstore (v4f32 VR128:$src),
+                                                  addr:$dst)]>, VEX;
+  }
+}
+
 def MOVNTPSmr_Int : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
                     "movntps\t{$src, $dst|$dst, $src}",
                     [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
@@ -2030,6 +2071,11 @@
                         "movntpd\t{$src, $dst|$dst, $src}",
                         [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
 
+let ExeDomain = SSEPackedInt in
+def MOVNTDQmr_Int : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
+                        "movntdq\t{$src, $dst|$dst, $src}",
+                        [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
+
 let AddedComplexity = 400 in { // Prefer non-temporal versions
 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
                     "movntps\t{$src, $dst|$dst, $src}",
@@ -2042,6 +2088,12 @@
                     "movntdq\t{$src, $dst|$dst, $src}",
                     [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
 
+let ExeDomain = SSEPackedInt in
+def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
+                    "movntdq\t{$src, $dst|$dst, $src}",
+                    [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
+
+// There is no AVX form for instructions below this point
 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
                  "movnti\t{$src, $dst|$dst, $src}",
                  [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
@@ -2052,17 +2104,7 @@
                      [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
                   TB, Requires<[HasSSE2]>;
 
-let ExeDomain = SSEPackedInt in
-def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
-                    "movntdq\t{$src, $dst|$dst, $src}",
-                    [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
 }
-
-let ExeDomain = SSEPackedInt in
-def MOVNTDQmr_Int : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
-                        "movntdq\t{$src, $dst|$dst, $src}",
-                        [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
-
 def MOVNTImr_Int  :   I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
                     "movnti\t{$src, $dst|$dst, $src}",
                     [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s?rev=107178&r1=107177&r2=107178&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s Tue Jun 29 13:22:01 2010
@@ -10938,3 +10938,15 @@
 // CHECK: encoding: [0xc5,0xea,0x53,0x18]
           vrcpss  (%eax), %xmm2, %xmm3
 
+// CHECK: vmovntdq  %xmm1, (%eax)
+// CHECK: encoding: [0xc5,0xf9,0xe7,0x08]
+          vmovntdq  %xmm1, (%eax)
+
+// CHECK: vmovntpd  %xmm1, (%eax)
+// CHECK: encoding: [0xc5,0xf9,0x2b,0x08]
+          vmovntpd  %xmm1, (%eax)
+
+// CHECK: vmovntps  %xmm1, (%eax)
+// CHECK: encoding: [0xc5,0xf8,0x2b,0x08]
+          vmovntps  %xmm1, (%eax)
+

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s?rev=107178&r1=107177&r2=107178&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s Tue Jun 29 13:22:01 2010
@@ -986,3 +986,15 @@
 // CHECK: encoding: [0xc5,0x1a,0x53,0x10]
           vrcpss  (%rax), %xmm12, %xmm10
 
+// CHECK: vmovntdq  %xmm11, (%rax)
+// CHECK: encoding: [0xc5,0x79,0xe7,0x18]
+          vmovntdq  %xmm11, (%rax)
+
+// CHECK: vmovntpd  %xmm11, (%rax)
+// CHECK: encoding: [0xc5,0x79,0x2b,0x18]
+          vmovntpd  %xmm11, (%rax)
+
+// CHECK: vmovntps  %xmm11, (%rax)
+// CHECK: encoding: [0xc5,0x78,0x2b,0x18]
+          vmovntps  %xmm11, (%rax)
+




From evan.cheng at apple.com  Tue Jun 29 13:38:17 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 29 Jun 2010 11:38:17 -0700
Subject: [llvm-commits] [patch] Mostly mechanical removal of
	getPhysicalRegisterRegClass.patch
In-Reply-To: <AB82423F-0FCC-4038-B5C2-1F9FF6E4D838@2pi.dk>
References: <AANLkTilqt5y4NglQZbWCS7S7jTdaybAvxWQD1-RqbhuK@mail.gmail.com>
	<D707A8E3-C6A1-4FD2-8DB8-FA88FC917365@2pi.dk>
	<AANLkTikDwVDsbrtjOTHmvi0U2OrJ6yjzqyI56d2-HGnm@mail.gmail.com>
	<AEFF279C-8A23-4753-A4A6-89640224C297@2pi.dk>
	<AANLkTimgBUUcE2-sTG0Qps20tS8qIh01LB61ABYZuY9e@mail.gmail.com>
	<EFEFA155-7FBA-4942-B731-575ABCD97A83@2pi.dk>
	<AANLkTinvjuW8OuHxExMJECtbVAd1GqyqFAX1JT5IM86-@mail.gmail.com>
	<AANLkTimv2smH65TcgkCg9oiuxTjE6yS13tfd3yLo9wGG@mail.gmail.com>
	<AB82423F-0FCC-4038-B5C2-1F9FF6E4D838@2pi.dk>
Message-ID: <181DFFDD-2A43-43D3-9CF3-B7054973D60E@apple.com>


On Jun 29, 2010, at 9:09 AM, Jakob Stoklund Olesen wrote:

> 
> On Jun 29, 2010, at 8:11 AM, Rafael Espindola wrote:
> 
>> On 29 June 2010 10:54, Anton Korobeynikov <asl at math.spbu.ru> wrote:
>>> Hello, Jakob
>>> 
>>>> This is a little worrying, but probably not your fault.
>>> Yes. This somehow seems to be a fallout from subreg indices unification.
>>> 
>>> Basically, the problem is that currently we can easily have
>>> cross-domain switches while walking via subregs.
>>> Look, for example, into DPR_VFP2 regclass. This class is used for NEON
>>> code and thus all the stuff operates inside the NEON domain. It should
>>> not contain any SPR subregs since there are no 32-bit reg-reg moves in
>>> NEON (think about the core with VFP disabled, but not NEON).
>>> 
>>> In fact, this was the only reason why this regclass does exist - to
>>> restrict the set of regs used for certain neon instructions.
>> 
>> I think we agreed on IRC. The issues is that the question "give me a
>> regclass for D0" is ambiguous. Is that the NEON one or the VFP one? If
>> we don't specify this, the existing DPR_VFP2 class is a valid answer
>> and gives the copy creation extra freedom.
>> 
>> Since there are cases where we care a lot about moves from neon to
>> vfp, we should make those explicit. I agree with Anton that what we
>> should do is
>> 
>> *) Declare the neon registers as independent entities from the vfp
>> registers (D0N, D1N, ...)
>> *) Declare the class of neon registers. This will not intersect with
>> the vfp register classes
>> *) Declare move instructions between the two (COPY_TO_REGCLASS?). This
>> will print just like a regular copy, but have a cost that reflects the
>> move from neon to vfp or the other way.
> 
> I agree that a register subclass (DPR_VFP2) is not going to work for completely separating two execution domains, and a set of register aliases is the way to prevent that.
> 
> But is it really necessary? We already have the NEONMoveFix pass to handle this issue. Maybe it just needs to get a bit better? The test case in question is a two-instruction function:
> 
> 	vmov.f32 s3, s0
> 	vmov.f64 d0, d1
> 
> It should be possible to pick the correct vmov in that case, but I am not surprised NEONMoveFix got it wrong.
> 
> The SSEDomainFixPass does something very similar, and it is close to being target independent. I was planning to do that, and use it for both SSE and NEON, but I never got around to it.
> 
> What do you think? For NEON it is literally just a question of picking the correct move instruction, nothing else. A whole new set of registers with aliasing to the old ones seems like overkill.

I agree with Jakob. There is the job of domain crossing fix up pass.

Evan

> 
> /jakob
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits




From wdietz2 at illinois.edu  Tue Jun 29 13:38:26 2010
From: wdietz2 at illinois.edu (Will Dietz)
Date: Tue, 29 Jun 2010 18:38:26 -0000
Subject: [llvm-commits] [poolalloc] r107188 -
	/poolalloc/trunk/lib/DSA/DataStructureAA.cpp
Message-ID: <20100629183826.EC88C2A6C12C@llvm.org>

Author: wdietz2
Date: Tue Jun 29 13:38:26 2010
New Revision: 107188

URL: http://llvm.org/viewvc/llvm-project?rev=107188&view=rev
Log:
Added simple 'valid' state tracking for DS-AA, and assert if the pass is used after being invalidated.
This helps save debugging time by making it clear if an error is due to ds-aa being invalidated as opposed to wrong DSA results, etc.

Modified:
    poolalloc/trunk/lib/DSA/DataStructureAA.cpp

Modified: poolalloc/trunk/lib/DSA/DataStructureAA.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DataStructureAA.cpp?rev=107188&r1=107187&r2=107188&view=diff
==============================================================================
--- poolalloc/trunk/lib/DSA/DataStructureAA.cpp (original)
+++ poolalloc/trunk/lib/DSA/DataStructureAA.cpp Tue Jun 29 13:38:26 2010
@@ -35,10 +35,12 @@
     // information is also freed.
     CallSite MapCS;
     std::multimap<DSNode*, const DSNode*> CallerCalleeMap;
+    bool valid;
   public:
     static char ID;
-    DSAA() : ModulePass((intptr_t)&ID), TD(0) {}
+    DSAA() : ModulePass((intptr_t)&ID), TD(NULL), BU(NULL), valid(false) {}
     ~DSAA() {
+      valid = false;
       InvalidateCache();
     }
 
@@ -58,9 +60,20 @@
       InitializeAliasAnalysis(this);
       TD = &getAnalysis<TDDataStructures>();
       BU = &getAnalysis<BUDataStructures>();
+      //FIXME: Is this not a safe assumption?
+      //assert(!valid && "DSAA executed twice without being invalidated?");
+      valid = true;
       return false;
     }
 
+
+    void releaseMemory() {
+      valid = false;
+      TD = NULL;
+      BU = NULL;
+      InvalidateCache();
+    }
+
     virtual void getAnalysisUsage(AnalysisUsage &AU) const {
       AliasAnalysis::getAnalysisUsage(AU);
       AU.setPreservesAll();                         // Does not transform code
@@ -91,12 +104,14 @@
     }
 
     virtual void deleteValue(Value *V) {
+      assert(valid && "DSAA invalidated but then queried?!");
       InvalidateCache();
       BU->deleteValue(V);
       TD->deleteValue(V);
     }
 
     virtual void copyValue(Value *From, Value *To) {
+      assert(valid && "DSAA invalidated but then queried?!");
       if (From == To) return;
       InvalidateCache();
       BU->copyValue(From, To);
@@ -133,6 +148,7 @@
 
 AliasAnalysis::AliasResult DSAA::alias(const Value *V1, unsigned V1Size,
                                        const Value *V2, unsigned V2Size) {
+  assert(valid && "DSAA invalidated but then queried?!");
   if (V1 == V2) return MustAlias;
 
   DSGraph *G1 = getGraphForValue(V1);
@@ -183,6 +199,7 @@
 ///
 AliasAnalysis::ModRefResult
 DSAA::getModRefInfo(CallSite CS, Value *P, unsigned Size) {
+  assert(valid && "DSAA invalidated but then queried?!");
   DSNode *N = 0;
   // First step, check our cache.
   if (CS.getInstruction() == MapCS.getInstruction()) {




From bob.wilson at apple.com  Tue Jun 29 13:42:49 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Tue, 29 Jun 2010 18:42:49 -0000
Subject: [llvm-commits] [llvm] r107189 - in /llvm/trunk:
 lib/CodeGen/LowerSubregs.cpp test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll
Message-ID: <20100629184249.2E9222A6C12C@llvm.org>

Author: bwilson
Date: Tue Jun 29 13:42:49 2010
New Revision: 107189

URL: http://llvm.org/viewvc/llvm-project?rev=107189&view=rev
Log:
Fix a register scavenger crash when dealing with undefined subregs.
The LowerSubregs pass needs to preserve implicit def operands attached to
EXTRACT_SUBREG instructions when it replaces those instructions with copies.

Added:
    llvm/trunk/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll
Modified:
    llvm/trunk/lib/CodeGen/LowerSubregs.cpp

Modified: llvm/trunk/lib/CodeGen/LowerSubregs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LowerSubregs.cpp?rev=107189&r1=107188&r2=107189&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LowerSubregs.cpp (original)
+++ llvm/trunk/lib/CodeGen/LowerSubregs.cpp Tue Jun 29 13:42:49 2010
@@ -62,6 +62,7 @@
     void TransferKillFlag(MachineInstr *MI, unsigned SrcReg,
                           const TargetRegisterInfo *TRI,
                           bool AddIfNotFound = false);
+    void TransferImplicitDefs(MachineInstr *MI);
   };
 
   char LowerSubregsInstructionPass::ID = 0;
@@ -104,6 +105,22 @@
   }
 }
 
+/// TransferImplicitDefs - MI is a pseudo-instruction, and the lowered
+/// replacement instructions immediately precede it.  Copy any implicit-def
+/// operands from MI to the replacement instruction.
+void
+LowerSubregsInstructionPass::TransferImplicitDefs(MachineInstr *MI) {
+  MachineBasicBlock::iterator CopyMI = MI;
+  --CopyMI;
+
+  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+    MachineOperand &MO = MI->getOperand(i);
+    if (!MO.isReg() || !MO.isImplicit() || MO.isUse())
+      continue;
+    CopyMI->addOperand(MachineOperand::CreateReg(MO.getReg(), true, true));
+  }
+}
+
 bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
   MachineBasicBlock *MBB = MI->getParent();
 
@@ -149,6 +166,7 @@
       TransferDeadFlag(MI, DstReg, TRI);
     if (MI->getOperand(1).isKill())
       TransferKillFlag(MI, SuperReg, TRI, true);
+    TransferImplicitDefs(MI);
     DEBUG({
         MachineBasicBlock::iterator dMI = MI;
         dbgs() << "subreg: " << *(--dMI);

Added: llvm/trunk/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll?rev=107189&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/2010-06-29-SubregImpDefs.ll Tue Jun 29 13:42:49 2010
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=arm -mattr=+neon
+
+ at .str271 = external constant [21 x i8], align 4   ; <[21 x i8]*> [#uses=1]
+ at llvm.used = appending global [1 x i8*] [i8* bitcast (i32 (i32, i8**)* @main to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
+
+define i32 @main(i32 %argc, i8** %argv) nounwind {
+entry:
+  %0 = shufflevector <2 x i64> undef, <2 x i64> zeroinitializer, <2 x i32> <i32 1, i32 2> ; <<2 x i64>> [#uses=1]
+  store <2 x i64> %0, <2 x i64>* undef, align 16
+  %val4723 = load <8 x i16>* undef                ; <<8 x i16>> [#uses=1]
+  call void @PrintShortX(i8* getelementptr inbounds ([21 x i8]* @.str271, i32 0, i32 0), <8 x i16> %val4723, i32 0) nounwind
+  ret i32 undef
+}
+
+declare void @PrintShortX(i8*, <8 x i16>, i32) nounwind




From wdietz2 at illinois.edu  Tue Jun 29 13:42:52 2010
From: wdietz2 at illinois.edu (Will Dietz)
Date: Tue, 29 Jun 2010 18:42:52 -0000
Subject: [llvm-commits] [poolalloc] r107190 - in /poolalloc/trunk/test:
 TEST.dsaa.Makefile TEST.dsaa.report
Message-ID: <20100629184252.B074D2A6C12D@llvm.org>

Author: wdietz2
Date: Tue Jun 29 13:42:52 2010
New Revision: 107190

URL: http://llvm.org/viewvc/llvm-project?rev=107190&view=rev
Log:
Improve the dsaa tests
fix the report to properly parse the results
add watchdog in opt invocation
remove passes that trigger the 'use after invalidated' issue, for now

Modified:
    poolalloc/trunk/test/TEST.dsaa.Makefile
    poolalloc/trunk/test/TEST.dsaa.report

Modified: poolalloc/trunk/test/TEST.dsaa.Makefile
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/TEST.dsaa.Makefile?rev=107190&r1=107189&r2=107190&view=diff
==============================================================================
--- poolalloc/trunk/test/TEST.dsaa.Makefile (original)
+++ poolalloc/trunk/test/TEST.dsaa.Makefile Tue Jun 29 13:42:52 2010
@@ -15,6 +15,9 @@
 #PADIR   := /home/andrewl/Research/llvm/projects/poolalloc
 PADIR   := $(LLVM_OBJ_ROOT)/projects/poolalloc
 
+# Watchdog utility
+WATCHDOG := $(LLVM_OBJ_ROOT)/projects/poolalloc/$(CONFIGURATION)/bin/watchdog
+
 # Bits of runtime to improve analysis
 PA_PRE_RT := $(PADIR)/$(CONFIGURATION)/lib/libpa_pre_rt.bca
 
@@ -22,14 +25,17 @@
 DSA_SO   := $(PADIR)/$(CONFIGURATION)/lib/libLLVMDataStructure$(SHLIBEXT)
 
 # Command to run opt with the ds-aa pass loaded
-OPT_PA := $(LOPT) -load $(DSA_SO)
+OPT_PA := $(WATCHDOG) $(LOPT) -load $(DSA_SO)
 
 # OPT_PA_STATS - Run opt with the -stats and -time-passes options, capturing the
 # output to a file.
 OPT_PA_STATS = $(OPT_PA) -info-output-file=$(CURDIR)/$@.info -stats -time-passes
 
 #All llvm 2.7 -O3 passes
-OPTZN_PASSES := -preverify -domtree -verify -lowersetjmp -globalopt -ipsccp -deadargelim -instcombine -simplifycfg -basiccg -prune-eh -inline -functionattrs -argpromotion -domtree -domfrontier -scalarrepl -simplify-libcalls -instcombine -jump-threading -simplifycfg -instcombine -tailcallelim -simplifycfg -reassociate -domtree -loops -loopsimplify -domfrontier -loopsimplify -lcssa -loop-rotate -licm -lcssa -loop-unswitch -instcombine -scalar-evolution -loopsimplify -lcssa -iv-users -indvars -loop-deletion -loopsimplify -lcssa -loop-unroll -instcombine -memdep -gvn -memdep -memcpyopt -sccp -instcombine -jump-threading -domtree -memdep -dse -adce -simplifycfg -strip-dead-prototypes -print-used-types -deadtypeelim -globaldce -constmerge -preverify -domtree -verify
+#OPTZN_PASSES := -preverify -domtree -verify -lowersetjmp -globalopt -ipsccp -deadargelim -instcombine -simplifycfg -basiccg -prune-eh -inline -functionattrs -argpromotion -domtree -domfrontier -scalarrepl -simplify-libcalls -instcombine -jump-threading -simplifycfg -instcombine -tailcallelim -simplifycfg -reassociate -domtree -loops -loopsimplify -domfrontier -loopsimplify -lcssa -loop-rotate -licm -lcssa -loop-unswitch -instcombine -scalar-evolution -loopsimplify -lcssa -iv-users -indvars -loop-deletion -loopsimplify -lcssa -loop-unroll -instcombine -memdep -gvn -memdep -memcpyopt -sccp -instcombine -jump-threading -domtree -memdep -dse -adce -simplifycfg -strip-dead-prototypes -print-used-types -deadtypeelim -globaldce -constmerge -preverify -domtree -verify
+
+#Subset of -O3 passes to work around bugs
+OPTZN_PASSES := -preverify -domtree -verify -lowersetjmp -globalopt -ipsccp -deadargelim -instcombine -simplifycfg -basiccg -prune-eh -inline -functionattrs -argpromotion -domtree -domfrontier -scalarrepl -simplify-libcalls -instcombine -jump-threading -simplifycfg -instcombine -tailcallelim -simplifycfg -reassociate -domtree -loops -loopsimplify -domfrontier -loopsimplify -lcssa -loop-rotate -lcssa -loop-unswitch -instcombine -scalar-evolution -loopsimplify -lcssa -iv-users -indvars -loop-deletion -loopsimplify -lcssa -loop-unroll -instcombine -memdep -gvn -memdep -memcpyopt -sccp -instcombine -jump-threading -domtree -adce -simplifycfg -strip-dead-prototypes -print-used-types -deadtypeelim -globaldce -constmerge -preverify -domtree -verify
 
 #-ds-aa -opt1 -ds-aa -opt2, etc
 #this forces each pass to use -ds-aa as it's AA if it would use one
@@ -57,7 +63,7 @@
 $(PROGRAMS_TO_TEST:%=Output/%.dsaopt.bc): \
 Output/%.dsaopt.bc: Output/%.base.bc $(LOPT)
 	- at rm -f $(CURDIR)/$@.info
-	-$(OPT_PA_STATS) $(AA_OPT) $< -o $@ -f 2>&1 > $@.out
+	-$(OPT_PA_STATS) $(AA_OPT) -debug-pass=Executions $< -o $@ -f 2>&1 > $@.out
 
 # This rule compiles the new .bc file into a .s file
 Output/%.s: Output/%.bc $(LLC)

Modified: poolalloc/trunk/test/TEST.dsaa.report
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/TEST.dsaa.report?rev=107190&r1=107189&r2=107190&view=diff
==============================================================================
--- poolalloc/trunk/test/TEST.dsaa.report (original)
+++ poolalloc/trunk/test/TEST.dsaa.report Tue Jun 29 13:42:52 2010
@@ -83,7 +83,7 @@
  ["LLVMOptTime",      'RUN-TIME-LLVMOPT: program\s*([.0-9m:]+)', \&FormatTime],
  ["LLVMOpt run%",        \&RuntimePercent],
  [],
- ["DSA Time",        'RUN-TIME-DSAAOPT: program\s*([.0-9m:]+)', \&FormatTime],
+ ["DSA Time",        'RUN-TIME-DSAA: program\s*([.0-9m:]+)', \&FormatTime],
  ["DSA run%",        \&RuntimePercent],
 # [],
 # ["NoAlias",        'no alias responses[^0-9]*([0-9]*\.[0-9]*)'],




From baldrick at free.fr  Tue Jun 29 13:57:51 2010
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 29 Jun 2010 18:57:51 -0000
Subject: [llvm-commits] [dragonegg] r107192 -
	/dragonegg/trunk/extras/do_self_strap
Message-ID: <20100629185751.107732A6C12C@llvm.org>

Author: baldrick
Date: Tue Jun 29 13:57:50 2010
New Revision: 107192

URL: http://llvm.org/viewvc/llvm-project?rev=107192&view=rev
Log:
Launch more parallel jobs, but only if the load average
is not too high (it is often high on gcc compile farm
machines, which is where the self-host testers run).

Modified:
    dragonegg/trunk/extras/do_self_strap

Modified: dragonegg/trunk/extras/do_self_strap
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/extras/do_self_strap?rev=107192&r1=107191&r2=107192&view=diff
==============================================================================
--- dragonegg/trunk/extras/do_self_strap (original)
+++ dragonegg/trunk/extras/do_self_strap Tue Jun 29 13:57:50 2010
@@ -57,7 +57,7 @@
 	      --disable-threads --enable-debug-symbols $LLVM_OPTIONS"
 
 COMPARE="cmp --ignore-initial=16"	# How to compare object files
-MAKE="nice -n 20 make -j2"		# How to run make
+MAKE="nice -n 20 make -j3 -l2"		# How to run make
 MAKE_INSTALL="nice -n 20 make install"	# How to run make install
 
 




From stoklund at 2pi.dk  Tue Jun 29 14:15:30 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 29 Jun 2010 19:15:30 -0000
Subject: [llvm-commits] [llvm] r107193 - in /llvm/trunk:
 lib/CodeGen/RegAllocFast.cpp
 test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll
Message-ID: <20100629191530.B05F52A6C12E@llvm.org>

Author: stoklund
Date: Tue Jun 29 14:15:30 2010
New Revision: 107193

URL: http://llvm.org/viewvc/llvm-project?rev=107193&view=rev
Log:
Fix the handling of partial redefines in the fast register allocator.

A partial redefine needs to be treated like a tied operand, and the register
must be reloaded while processing use operands.

This fixes a bug where partially redefined registers were processed as normal
defs with a reload added. The reload could clobber another use operand if it was
a kill that allowed register reuse.

Added:
    llvm/trunk/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll
Modified:
    llvm/trunk/lib/CodeGen/RegAllocFast.cpp

Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=107193&r1=107192&r2=107193&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocFast.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp Tue Jun 29 14:15:30 2010
@@ -515,7 +515,6 @@
   bool New;
   tie(LRI, New) = LiveVirtRegs.insert(std::make_pair(VirtReg, LiveReg()));
   LiveReg &LR = LRI->second;
-  bool PartialRedef = MI->getOperand(OpNum).getSubReg();
   if (New) {
     // If there is no hint, peek at the only use of this register.
     if ((!Hint || !TargetRegisterInfo::isPhysicalRegister(Hint)) &&
@@ -527,15 +526,7 @@
         Hint = DstReg;
     }
     allocVirtReg(MI, *LRI, Hint);
-    // If this is only a partial redefinition, we must reload the other parts.
-    if (PartialRedef && MI->readsVirtualRegister(VirtReg)) {
-      const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
-      int FI = getStackSpaceFor(VirtReg, RC);
-      DEBUG(dbgs() << "Reloading for partial redef: %reg" << VirtReg << "\n");
-      TII->loadRegFromStackSlot(*MBB, MI, LR.PhysReg, FI, RC, TRI);
-      ++NumLoads;
-    }
-  } else if (LR.LastUse && !PartialRedef) {
+  } else if (LR.LastUse) {
     // Redefining a live register - kill at the last use, unless it is this
     // instruction defining VirtReg multiple times.
     if (LR.LastUse != MI || LR.LastUse->getOperand(LR.LastOpNum).isUse())
@@ -571,10 +562,16 @@
   } else if (LR.Dirty) {
     if (isLastUseOfLocalReg(MO)) {
       DEBUG(dbgs() << "Killing last use: " << MO << "\n");
-      MO.setIsKill();
+      if (MO.isUse())
+        MO.setIsKill();
+      else
+        MO.setIsDead();
     } else if (MO.isKill()) {
       DEBUG(dbgs() << "Clearing dubious kill: " << MO << "\n");
       MO.setIsKill(false);
+    } else if (MO.isDead()) {
+      DEBUG(dbgs() << "Clearing dubious dead: " << MO << "\n");
+      MO.setIsDead(false);
     }
   } else if (MO.isKill()) {
     // We must remove kill flags from uses of reloaded registers because the
@@ -583,6 +580,9 @@
     // This would cause a second reload of %x into a different register.
     DEBUG(dbgs() << "Clearing clean kill: " << MO << "\n");
     MO.setIsKill(false);
+  } else if (MO.isDead()) {
+    DEBUG(dbgs() << "Clearing clean dead: " << MO << "\n");
+    MO.setIsDead(false);
   }
   assert(LR.PhysReg && "Register not assigned");
   LR.LastUse = MI;
@@ -625,7 +625,8 @@
     if (!MO.isReg()) continue;
     unsigned Reg = MO.getReg();
     if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
-    if (MO.isEarlyClobber() || MI->isRegTiedToDefOperand(i)) {
+    if (MO.isEarlyClobber() || MI->isRegTiedToDefOperand(i) ||
+        (MO.getSubReg() && MI->readsVirtualRegister(Reg))) {
       if (ThroughRegs.insert(Reg))
         DEBUG(dbgs() << " %reg" << Reg);
     }
@@ -649,6 +650,7 @@
     }
   }
 
+  SmallVector<unsigned, 8> PartialDefs;
   DEBUG(dbgs() << "Allocating tied uses and early clobbers.\n");
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     MachineOperand &MO = MI->getOperand(i);
@@ -663,6 +665,14 @@
       LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, 0);
       unsigned PhysReg = LRI->second.PhysReg;
       setPhysReg(MI, i, PhysReg);
+      // Note: we don't update the def operand yet. That would cause the normal
+      // def-scan to attempt spilling.
+    } else if (MO.getSubReg() && MI->readsVirtualRegister(Reg)) {
+      DEBUG(dbgs() << "Partial redefine: " << MO << "\n");
+      // Reload the register, but don't assign to the operand just yet.
+      // That would confuse the later phys-def processing pass.
+      LiveRegMap::iterator LRI = reloadVirtReg(MI, i, Reg, 0);
+      PartialDefs.push_back(LRI->second.PhysReg);
     } else if (MO.isEarlyClobber()) {
       // Note: defineVirtReg may invalidate MO.
       LiveRegMap::iterator LRI = defineVirtReg(MI, i, Reg, 0);
@@ -683,6 +693,10 @@
     for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
       UsedInInstr.set(*AS);
   }
+
+  // Also mark PartialDefs as used to avoid reallocation.
+  for (unsigned i = 0, e = PartialDefs.size(); i != e; ++i)
+    UsedInInstr.set(PartialDefs[i]);
 }
 
 void RAFast::AllocateBasicBlock() {
@@ -767,7 +781,10 @@
     // Mark physreg uses and early clobbers as used.
     // Find the end of the virtreg operands
     unsigned VirtOpEnd = 0;
-    bool hasTiedOps = false, hasEarlyClobbers = false, hasPhysDefs = false;
+    bool hasTiedOps = false;
+    bool hasEarlyClobbers = false;
+    bool hasPartialRedefs = false;
+    bool hasPhysDefs = false;
     for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
       MachineOperand &MO = MI->getOperand(i);
       if (!MO.isReg()) continue;
@@ -775,11 +792,15 @@
       if (!Reg) continue;
       if (TargetRegisterInfo::isVirtualRegister(Reg)) {
         VirtOpEnd = i+1;
-        if (MO.isUse())
+        if (MO.isUse()) {
           hasTiedOps = hasTiedOps ||
                                 TID.getOperandConstraint(i, TOI::TIED_TO) != -1;
-        else if (MO.isEarlyClobber())
-          hasEarlyClobbers = true;
+        } else {
+          if (MO.isEarlyClobber())
+            hasEarlyClobbers = true;
+          if (MO.getSubReg() && MI->readsVirtualRegister(Reg))
+            hasPartialRedefs = true;
+        }
         continue;
       }
       if (!Allocatable.test(Reg)) continue;
@@ -800,7 +821,8 @@
     // operands.
     // We didn't detect inline asm tied operands above, so just make this extra
     // pass for all inline asm.
-    if (MI->isInlineAsm() || hasEarlyClobbers || (hasTiedOps && hasPhysDefs)) {
+    if (MI->isInlineAsm() || hasEarlyClobbers || hasPartialRedefs ||
+        (hasTiedOps && hasPhysDefs)) {
       handleThroughOperands(MI, VirtDead);
       // Don't attempt coalescing when we have funny stuff going on.
       CopyDst = 0;

Added: llvm/trunk/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll?rev=107193&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/2010-06-29-PartialRedefFastAlloc.ll Tue Jun 29 14:15:30 2010
@@ -0,0 +1,22 @@
+; RUN: llc < %s -O0 -mcpu=cortex-a8 | FileCheck %s
+target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32"
+target triple = "thumbv7-apple-darwin10"
+
+; This tests the fast register allocator's handling of partial redefines:
+;
+;	%reg1026<def> = VMOVv16i8 0, pred:14, pred:%reg0
+;	%reg1028:dsub_1<def> = EXTRACT_SUBREG %reg1026<kill>, 1
+;
+; %reg1026 gets allocated %Q0, and if %reg1028 is reloaded for the partial redef,
+; it cannot also get %Q0.
+
+; CHECK: vmov.i8 q0, #0x0
+; CHECK-NOT: vld1.64 {d0,d1}
+; CHECK: vmov.f64 d3, d0
+
+define i32 @main(i32 %argc, i8** %argv) nounwind {
+entry:
+ %0 = shufflevector <2 x i64> undef, <2 x i64> zeroinitializer, <2 x i32> <i32 1, i32 2> ; <<2 x i64>> [#uses=1]
+ store <2 x i64> %0, <2 x i64>* undef, align 16
+ ret i32 undef
+}




From sabre at nondot.org  Tue Jun 29 14:20:38 2010
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 29 Jun 2010 19:20:38 -0000
Subject: [llvm-commits] [llvm] r107195 - in /llvm/trunk/include/llvm:
	AbstractTypeUser.h Type.h
Message-ID: <20100629192038.ABEFA2A6C12E@llvm.org>

Author: lattner
Date: Tue Jun 29 14:20:38 2010
New Revision: 107195

URL: http://llvm.org/viewvc/llvm-project?rev=107195&view=rev
Log:
give PATypeHolder an explicit copy ctor which initializes the type pointer,
and make PATypeHolder work with null pointers.

The implicitly generated one didn't work on numerous levels, but was still
accepted, allowing all sorts of bugs with default constructed pa type holders.

Previously, they "sort of" worked if they were default constructed and then
destructed.  Now they really work, and you can even default construct one,
then assign to it, amazing.

Modified:
    llvm/trunk/include/llvm/AbstractTypeUser.h
    llvm/trunk/include/llvm/Type.h

Modified: llvm/trunk/include/llvm/AbstractTypeUser.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/AbstractTypeUser.h?rev=107195&r1=107194&r2=107195&view=diff
==============================================================================
--- llvm/trunk/include/llvm/AbstractTypeUser.h (original)
+++ llvm/trunk/include/llvm/AbstractTypeUser.h Tue Jun 29 14:20:38 2010
@@ -146,6 +146,7 @@
   mutable const Type *Ty;
   void destroy();
 public:
+  PATypeHolder() : Ty(0) {}
   PATypeHolder(const Type *ty) : Ty(ty) {
     addRef();
   }
@@ -153,7 +154,7 @@
     addRef();
   }
 
-  ~PATypeHolder() { if (Ty) dropRef(); }
+  ~PATypeHolder() { dropRef(); }
 
   operator Type *() const { return get(); }
   Type *get() const;

Modified: llvm/trunk/include/llvm/Type.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Type.h?rev=107195&r1=107194&r2=107195&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Type.h (original)
+++ llvm/trunk/include/llvm/Type.h Tue Jun 29 14:20:38 2010
@@ -504,19 +504,19 @@
 /// reference to the type.
 ///
 inline Type* PATypeHolder::get() const {
+  if (Ty == 0) return 0;
   const Type *NewTy = Ty->getForwardedType();
   if (!NewTy) return const_cast<Type*>(Ty);
   return *const_cast<PATypeHolder*>(this) = NewTy;
 }
 
 inline void PATypeHolder::addRef() {
-  assert(Ty && "Type Holder has a null type!");
-  if (Ty->isAbstract())
+  if (Ty && Ty->isAbstract())
     Ty->addRef();
 }
 
 inline void PATypeHolder::dropRef() {
-  if (Ty->isAbstract())
+  if (Ty && Ty->isAbstract())
     Ty->dropRef();
 }
 




From baldrick at free.fr  Tue Jun 29 15:05:34 2010
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 29 Jun 2010 20:05:34 -0000
Subject: [llvm-commits] [llvm] r107199 -
	/llvm/trunk/include/llvm/ADT/SmallPtrSet.h
Message-ID: <20100629200534.8EAB22A6C12C@llvm.org>

Author: baldrick
Date: Tue Jun 29 15:05:34 2010
New Revision: 107199

URL: http://llvm.org/viewvc/llvm-project?rev=107199&view=rev
Log:
NextPowerOfTwo was already used to ensure that SmallSizePowTwo is a power
of two, no need to do it a second time (NextPowerOfTwo is idempotent).

Modified:
    llvm/trunk/include/llvm/ADT/SmallPtrSet.h

Modified: llvm/trunk/include/llvm/ADT/SmallPtrSet.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/SmallPtrSet.h?rev=107199&r1=107198&r2=107199&view=diff
==============================================================================
--- llvm/trunk/include/llvm/ADT/SmallPtrSet.h (original)
+++ llvm/trunk/include/llvm/ADT/SmallPtrSet.h Tue Jun 29 15:05:34 2010
@@ -236,12 +236,11 @@
   void *SmallArray[SmallSizePowTwo];
   typedef PointerLikeTypeTraits<PtrType> PtrTraits;
 public:
-  SmallPtrSet() : SmallPtrSetImpl(NextPowerOfTwo<SmallSizePowTwo>::Val) {}
+  SmallPtrSet() : SmallPtrSetImpl(SmallSizePowTwo) {}
   SmallPtrSet(const SmallPtrSet &that) : SmallPtrSetImpl(that) {}
 
   template<typename It>
-  SmallPtrSet(It I, It E)
-    : SmallPtrSetImpl(NextPowerOfTwo<SmallSizePowTwo>::Val) {
+  SmallPtrSet(It I, It E) : SmallPtrSetImpl(SmallSizePowTwo) {
     insert(I, E);
   }
 




From baldrick at free.fr  Tue Jun 29 15:12:02 2010
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 29 Jun 2010 20:12:02 -0000
Subject: [llvm-commits] [llvm] r107200 -
	/llvm/trunk/include/llvm/ADT/SmallPtrSet.h
Message-ID: <20100629201202.D2E1C2A6C12C@llvm.org>

Author: baldrick
Date: Tue Jun 29 15:12:02 2010
New Revision: 107200

URL: http://llvm.org/viewvc/llvm-project?rev=107200&view=rev
Log:
Fix a buffer overflow noticed by gcc-4.6: zero is written into
SmallArray[SmallSize] in the SmallPtrSetIteratorImpl, and this is
one off the end of the array.  For those who care, right now gcc
warns about writing off the end because it is confused about the
declaration of SmallArray as having length 1 in the parent class
SmallPtrSetIteratorImpl.  However if you tweak code to unconfuse
it, then it still warns about writing off the end of the array,
because of this buffer overflow.  In short, even with this fix
gcc-4.6 will warn about writing off the end of the array, but now
that is only because it is confused.

Modified:
    llvm/trunk/include/llvm/ADT/SmallPtrSet.h

Modified: llvm/trunk/include/llvm/ADT/SmallPtrSet.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/SmallPtrSet.h?rev=107200&r1=107199&r2=107200&view=diff
==============================================================================
--- llvm/trunk/include/llvm/ADT/SmallPtrSet.h (original)
+++ llvm/trunk/include/llvm/ADT/SmallPtrSet.h Tue Jun 29 15:12:02 2010
@@ -233,7 +233,7 @@
 class SmallPtrSet : public SmallPtrSetImpl {
   // Make sure that SmallSize is a power of two, round up if not.
   enum { SmallSizePowTwo = NextPowerOfTwo<SmallSize>::Val };
-  void *SmallArray[SmallSizePowTwo];
+  void *SmallArray[SmallSizePowTwo+1];
   typedef PointerLikeTypeTraits<PtrType> PtrTraits;
 public:
   SmallPtrSet() : SmallPtrSetImpl(SmallSizePowTwo) {}




From bob.wilson at apple.com  Tue Jun 29 15:13:29 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Tue, 29 Jun 2010 20:13:29 -0000
Subject: [llvm-commits] [llvm] r107201 -
	/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
Message-ID: <20100629201329.3834D2A6C12C@llvm.org>

Author: bwilson
Date: Tue Jun 29 15:13:29 2010
New Revision: 107201

URL: http://llvm.org/viewvc/llvm-project?rev=107201&view=rev
Log:
Add support for encoding VDUP (ARM core register) instructions.

Modified:
    llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=107201&r1=107200&r2=107201&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Tue Jun 29 15:13:29 2010
@@ -141,6 +141,7 @@
     void emitMiscInstruction(const MachineInstr &MI);
 
     void emitNEONLaneInstruction(const MachineInstr &MI);
+    void emitNEONDupInstruction(const MachineInstr &MI);
     void emitNEON1RegModImmInstruction(const MachineInstr &MI);
     void emitNEON2RegInstruction(const MachineInstr &MI);
     void emitNEON3RegInstruction(const MachineInstr &MI);
@@ -420,6 +421,9 @@
   case ARMII::NSetLnFrm:
     emitNEONLaneInstruction(MI);
     break;
+  case ARMII::NDupFrm:
+    emitNEONDupInstruction(MI);
+    break;
   case ARMII::N1RegModImmFrm:
     emitNEON1RegModImmInstruction(MI);
     break;
@@ -1638,6 +1642,19 @@
   emitWordLE(Binary);
 }
 
+void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
+  unsigned Binary = getBinaryCodeForInstr(MI);
+
+  // Set the conditional execution predicate
+  Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
+
+  unsigned RegT = MI.getOperand(1).getReg();
+  RegT = ARMRegisterInfo::getRegisterNumbering(RegT);
+  Binary |= (RegT << ARMII::RegRdShift);
+  Binary |= encodeNEONRn(MI, 0);
+  emitWordLE(Binary);
+}
+
 void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
   unsigned Binary = getBinaryCodeForInstr(MI);
   // Destination register is encoded in Dd.




From dpatel at apple.com  Tue Jun 29 15:17:53 2010
From: dpatel at apple.com (Devang Patel)
Date: Tue, 29 Jun 2010 20:17:53 -0000
Subject: [llvm-commits] [llvm] r107202 - in
 /llvm/trunk/lib/CodeGen/AsmPrinter: DwarfDebug.cpp DwarfDebug.h
Message-ID: <20100629201753.5D9392A6C12C@llvm.org>

Author: dpatel
Date: Tue Jun 29 15:17:53 2010
New Revision: 107202

URL: http://llvm.org/viewvc/llvm-project?rev=107202&view=rev
Log:
Do not hardcode DW_AT_stmt_list value.
Inspired by Artur Pietrek.

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=107202&r1=107201&r2=107202&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Tue Jun 29 15:17:53 2010
@@ -321,6 +321,7 @@
   DwarfFrameSectionSym = DwarfInfoSectionSym = DwarfAbbrevSectionSym = 0;
   DwarfStrSectionSym = TextSectionSym = 0;
   DwarfDebugRangeSectionSym = DwarfDebugLocSectionSym = 0; 
+  DwarfDebugLineSectionSym = CurrentLineSectionSym = 0;
   FunctionBeginSym = FunctionEndSym = 0;
   {
     NamedRegionTimer T(DbgTimerName, DWARFGroupName, TimePassesIsEnabled);
@@ -1794,9 +1795,9 @@
   // simplifies debug range entries.
   addUInt(Die, dwarf::DW_AT_entry_pc, dwarf::DW_FORM_addr, 0);
   // DW_AT_stmt_list is a offset of line number information for this
-  // compile unit in debug_line section. It is always zero when only one
-  // compile unit is emitted in one object file.
-  addUInt(Die, dwarf::DW_AT_stmt_list, dwarf::DW_FORM_data4, 0);
+  // compile unit in debug_line section. This offset is calculated 
+  // during endMoudle().
+  addLabel(Die, dwarf::DW_AT_stmt_list, dwarf::DW_FORM_data4, 0);
 
   if (!Dir.empty())
     addString(Die, dwarf::DW_AT_comp_dir, dwarf::DW_FORM_string, Dir);
@@ -2081,15 +2082,15 @@
   // Compute DIE offsets and sizes.
   computeSizeAndOffsets();
 
+  // Emit source line correspondence into a debug line section.
+  emitDebugLines();
+
   // Emit all the DIEs into a debug info section
   emitDebugInfo();
 
   // Corresponding abbreviations into a abbrev section.
   emitAbbreviations();
 
-  // Emit source line correspondence into a debug line section.
-  emitDebugLines();
-
   // Emit info into a debug pubnames section.
   emitDebugPubNames();
 
@@ -2992,7 +2993,8 @@
   if (const MCSection *MacroInfo = TLOF.getDwarfMacroInfoSection())
     EmitSectionSym(Asm, MacroInfo);
 
-  EmitSectionSym(Asm, TLOF.getDwarfLineSection());
+  DwarfDebugLineSectionSym = 
+    EmitSectionSym(Asm, TLOF.getDwarfLineSection(), "section_line");
   EmitSectionSym(Asm, TLOF.getDwarfLocSection());
   EmitSectionSym(Asm, TLOF.getDwarfPubNamesSection());
   EmitSectionSym(Asm, TLOF.getDwarfPubTypesSection());
@@ -3055,6 +3057,11 @@
                                      4);
       break;
     }
+    case dwarf::DW_AT_stmt_list: {
+      Asm->EmitLabelDifference(CurrentLineSectionSym, 
+                               DwarfDebugLineSectionSym, 4);
+      break;
+    }
     case dwarf::DW_AT_location: {
       if (UseDotDebugLocEntry.count(Die) != 0) {
         DIELabel *L = cast<DIELabel>(Values[i]);
@@ -3200,6 +3207,8 @@
                             Asm->getObjFileLowering().getDwarfLineSection());
 
   // Construct the section header.
+  CurrentLineSectionSym = Asm->GetTempSymbol("section_line_begin");
+  Asm->OutStreamer.EmitLabel(CurrentLineSectionSym);
   Asm->OutStreamer.AddComment("Length of Source Line Info");
   Asm->EmitLabelDifference(Asm->GetTempSymbol("line_end"),
                            Asm->GetTempSymbol("line_begin"), 4);

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h?rev=107202&r1=107201&r2=107202&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Tue Jun 29 15:17:53 2010
@@ -258,6 +258,7 @@
   MCSymbol *DwarfFrameSectionSym, *DwarfInfoSectionSym, *DwarfAbbrevSectionSym;
   MCSymbol *DwarfStrSectionSym, *TextSectionSym, *DwarfDebugRangeSectionSym;
   MCSymbol *DwarfDebugLocSectionSym;
+  MCSymbol *DwarfDebugLineSectionSym, *CurrentLineSectionSym;
   MCSymbol *FunctionBeginSym, *FunctionEndSym;
 private:
   




From bruno.cardoso at gmail.com  Tue Jun 29 15:35:48 2010
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Tue, 29 Jun 2010 20:35:48 -0000
Subject: [llvm-commits] [llvm] r107204 - in /llvm/trunk:
 lib/Target/X86/X86InstrSSE.td lib/Target/X86/X86MCCodeEmitter.cpp
 test/MC/AsmParser/X86/x86_32-encoding.s
 test/MC/AsmParser/X86/x86_64-encoding.s
Message-ID: <20100629203549.171052A6C12C@llvm.org>

Author: bruno
Date: Tue Jun 29 15:35:48 2010
New Revision: 107204

URL: http://llvm.org/viewvc/llvm-project?rev=107204&view=rev
Log:

Add AVX ld/st XCSR register.
Add VEX encoding bits for MRMXm x86 form


Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp
    llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
    llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=107204&r1=107203&r2=107204&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Jun 29 15:35:48 2010
@@ -2019,6 +2019,8 @@
 defm RCP   : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
              sse1_fp_unop_p<0x53, "rcp", X86frcp, int_x86_sse_rcp_ps>;
 
+// There is no f64 version of the reciprocal approximation instructions.
+
 //===----------------------------------------------------------------------===//
 // SSE 1 & 2 - Non-temporal stores
 //===----------------------------------------------------------------------===//
@@ -2111,7 +2113,7 @@
                   TB, Requires<[HasSSE2]>;
 
 //===----------------------------------------------------------------------===//
-// SSE 1 & 2 - Misc Instructions
+// SSE 1 & 2 - Misc Instructions (No AVX form)
 //===----------------------------------------------------------------------===//
 
 // Prefetch intrinsic.
@@ -2128,12 +2130,6 @@
 def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
              TB, Requires<[HasSSE1]>;
 
-// MXCSR register
-def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
-                  "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
-def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
-                  "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
-
 // Alias instructions that map zero vector to pxor / xorp* for sse.
 // We set canFoldAsLoad because this can be converted to a constant-pool
 // load of an all-zeros value if folding it would be beneficial.
@@ -2156,13 +2152,26 @@
 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
           (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
 
+//===----------------------------------------------------------------------===//
+// SSE 1 & 2 - Load/Store XCSR register
+//===----------------------------------------------------------------------===//
+
+let isAsmParserOnly = 1 in {
+  def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
+                    "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, VEX;
+  def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
+                    "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, VEX;
+}
+
+def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
+                  "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
+def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
+                  "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
+
 //===---------------------------------------------------------------------===//
 // SSE2 Instructions
 //===---------------------------------------------------------------------===//
 
-
-// There is no f64 version of the reciprocal approximation instructions.
-
 //===---------------------------------------------------------------------===//
 // SSE integer instructions
 let ExeDomain = SSEPackedInt in {

Modified: llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp?rev=107204&r1=107203&r2=107204&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp Tue Jun 29 15:35:48 2010
@@ -455,15 +455,17 @@
   unsigned NumOps = MI.getNumOperands();
   unsigned CurOp = 0;
 
-  if ((TSFlags & X86II::FormMask) == X86II::MRMDestMem)
-    NumOps = CurOp = X86AddrNumOperands;
-
   switch (TSFlags & X86II::FormMask) {
   case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
-  case X86II::MRMSrcMem:
+  case X86II::MRM0m: case X86II::MRM1m:
+  case X86II::MRM2m: case X86II::MRM3m:
+  case X86II::MRM4m: case X86II::MRM5m:
+  case X86II::MRM6m: case X86II::MRM7m:
   case X86II::MRMDestMem:
+    NumOps = CurOp = X86AddrNumOperands;
+  case X86II::MRMSrcMem:
   case X86II::MRMSrcReg:
-    if (MI.getOperand(CurOp).isReg() &&
+    if (MI.getNumOperands() > CurOp && MI.getOperand(CurOp).isReg() &&
         X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
       VEX_R = 0x0;
 

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s?rev=107204&r1=107203&r2=107204&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s Tue Jun 29 15:35:48 2010
@@ -10950,3 +10950,19 @@
 // CHECK: encoding: [0xc5,0xf8,0x2b,0x08]
           vmovntps  %xmm1, (%eax)
 
+// CHECK: vldmxcsr  (%eax)
+// CHECK: encoding: [0xc5,0xf8,0xae,0x10]
+          vldmxcsr  (%eax)
+
+// CHECK: vstmxcsr  (%eax)
+// CHECK: encoding: [0xc5,0xf8,0xae,0x18]
+          vstmxcsr  (%eax)
+
+// CHECK: vldmxcsr  3735928559
+// CHECK: encoding: [0xc5,0xf8,0xae,0x15,0xef,0xbe,0xad,0xde]
+          vldmxcsr  0xdeadbeef
+
+// CHECK: vstmxcsr  3735928559
+// CHECK: encoding: [0xc5,0xf8,0xae,0x1d,0xef,0xbe,0xad,0xde]
+          vstmxcsr  0xdeadbeef
+

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s?rev=107204&r1=107203&r2=107204&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s Tue Jun 29 15:35:48 2010
@@ -998,3 +998,11 @@
 // CHECK: encoding: [0xc5,0x78,0x2b,0x18]
           vmovntps  %xmm11, (%rax)
 
+// CHECK: vldmxcsr  -4(%rip)
+// CHECK: encoding: [0xc5,0xf8,0xae,0x15,0xfc,0xff,0xff,0xff]
+          vldmxcsr  -4(%rip)
+
+// CHECK: vstmxcsr  -4(%rsp)
+// CHECK: encoding: [0xc5,0xf8,0xae,0x5c,0x24,0xfc]
+          vstmxcsr  -4(%rsp)
+




From stoklund at 2pi.dk  Tue Jun 29 15:39:16 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 29 Jun 2010 13:39:16 -0700
Subject: [llvm-commits] [llvm] r107114 -
	/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
In-Reply-To: <0BC7E25D-4488-4954-A149-0D27BF55BBAE@apple.com>
References: <20100629011307.645212A6C12C@llvm.org>
	<04D10EF1-91D9-44D6-9161-161B70493ED7@apple.com>
	<5F342D90-DC02-47A6-A825-EAD20CBFA547@2pi.dk>
	<0BC7E25D-4488-4954-A149-0D27BF55BBAE@apple.com>
Message-ID: <58535D1C-837D-4136-A1D6-9809389E70F3@2pi.dk>


On Jun 28, 2010, at 10:46 PM, Evan Cheng wrote:

> 
> On Jun 28, 2010, at 10:09 PM, Jakob Stoklund Olesen wrote:
> 
>> 
>> On Jun 28, 2010, at 10:00 PM, Evan Cheng wrote:
>> 
>>> 
>>> On Jun 28, 2010, at 6:13 PM, Jakob Stoklund Olesen wrote:
>>> 
>>>> Author: stoklund
>>>> Date: Mon Jun 28 20:13:07 2010
>>>> New Revision: 107114
>>>> 
>>>> URL: http://llvm.org/viewvc/llvm-project?rev=107114&view=rev
>>>> Log:
>>>> When no memoperands are present, assume unaligned, volatile.
>>> 
>>> Have you checked if this disabled a lot of potential optimizations? I am afraid assuming volatileness is overly conservative.
>> 
>> I haven't checked anything but running unit tests.
>> 
>> We need both non-volatile and 4-byte alignment to safely combine loads and stores. If memoperands are missing, I don't see any alternative. How else can we guarantee the optimization is valid?
>> 
>> If this causes missed optimizations, we should ensure that memory operands are present.
> 
> I agree. I am just wondering if that's indeed the case. Can you add a llc beta check to look for differences in # of load / store multiple optimizations?

I ran an assembly diff across the entire nightly test suite.

We lost 117 of 56783 ldms and 40 of 47702 stms.






From stoklund at 2pi.dk  Tue Jun 29 16:03:41 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 29 Jun 2010 14:03:41 -0700
Subject: [llvm-commits] [llvm] r107199 -
	/llvm/trunk/include/llvm/ADT/SmallPtrSet.h
In-Reply-To: <20100629200534.8EAB22A6C12C@llvm.org>
References: <20100629200534.8EAB22A6C12C@llvm.org>
Message-ID: <1D0E2A71-F497-4894-9481-44D35EB4BB8E@2pi.dk>


On Jun 29, 2010, at 1:05 PM, Duncan Sands wrote:

> Author: baldrick
> Date: Tue Jun 29 15:05:34 2010
> New Revision: 107199
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=107199&view=rev
> Log:
> NextPowerOfTwo was already used to ensure that SmallSizePowTwo is a power
> of two, no need to do it a second time (NextPowerOfTwo is idempotent).

No it isn't.

Ignoring overflow, NextPowerOfTwo(x) is always strictly greater than x.

x --> NextPowerOfTwo(x/2) is idempotent.

/jakob



From isanbard at gmail.com  Tue Jun 29 16:24:00 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 29 Jun 2010 21:24:00 -0000
Subject: [llvm-commits] [llvm] r107205 - in /llvm/trunk: bindings/ada/llvm/
 docs/ include/llvm-c/ include/llvm/ include/llvm/CodeGen/ include/llvm/MC/
 include/llvm/Target/ lib/AsmParser/ lib/Bitcode/Reader/ lib/Bitcode/Writer/
 lib/CodeGen/ lib/CodeGen/AsmPrinter/ lib/Linker/ lib/MC/ lib/Target/
 lib/Target/CppBackend/ lib/Target/XCore/AsmPrinter/ lib/Transforms/IPO/
 lib/VMCore/ tools/llvm-nm/
Message-ID: <20100629212400.DABF32A6C12C@llvm.org>

Author: void
Date: Tue Jun 29 16:24:00 2010
New Revision: 107205

URL: http://llvm.org/viewvc/llvm-project?rev=107205&view=rev
Log:
Introducing the "linker_weak" linkage type. This will be used for Objective-C
metadata types which should be marked as "weak", but which the linker will
remove upon final linkage. For example, the "objc_msgSend_fixup_alloc" symbol is
defined like this:

       .globl l_objc_msgSend_fixup_alloc
       .weak_definition l_objc_msgSend_fixup_alloc
       .section __DATA, __objc_msgrefs, coalesced
       .align 3
l_objc_msgSend_fixup_alloc:
        .quad   _objc_msgSend_fixup
        .quad   L_OBJC_METH_VAR_NAME_1

This is different from the "linker_private" linkage type, because it can't have
the metadata defined with ".weak_definition".

Modified:
    llvm/trunk/bindings/ada/llvm/llvm.ads
    llvm/trunk/docs/LangRef.html
    llvm/trunk/include/llvm-c/Core.h
    llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
    llvm/trunk/include/llvm/CodeGen/MachineFunction.h
    llvm/trunk/include/llvm/GlobalValue.h
    llvm/trunk/include/llvm/MC/MCAsmInfo.h
    llvm/trunk/include/llvm/Target/Mangler.h
    llvm/trunk/lib/AsmParser/LLLexer.cpp
    llvm/trunk/lib/AsmParser/LLParser.cpp
    llvm/trunk/lib/AsmParser/LLToken.h
    llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp
    llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
    llvm/trunk/lib/CodeGen/MachineFunction.cpp
    llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
    llvm/trunk/lib/Linker/LinkModules.cpp
    llvm/trunk/lib/MC/MCAsmInfo.cpp
    llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp
    llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
    llvm/trunk/lib/Target/Mangler.cpp
    llvm/trunk/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp
    llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp
    llvm/trunk/lib/VMCore/AsmWriter.cpp
    llvm/trunk/lib/VMCore/Core.cpp
    llvm/trunk/tools/llvm-nm/llvm-nm.cpp

Modified: llvm/trunk/bindings/ada/llvm/llvm.ads
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/bindings/ada/llvm/llvm.ads?rev=107205&r1=107204&r2=107205&view=diff
==============================================================================
--- llvm/trunk/bindings/ada/llvm/llvm.ads (original)
+++ llvm/trunk/bindings/ada/llvm/llvm.ads Tue Jun 29 16:24:00 2010
@@ -316,7 +316,8 @@
       LLVMExternalWeakLinkage,
       LLVMGhostLinkage,
       LLVMCommonLinkage,
-      LLVMLinkerPrivateLinkage);
+      LLVMLinkerPrivateLinkage,
+      LLVMLinkerWeakLinkage);
 
    for LLVMLinkage use
      (LLVMExternalLinkage            => 0,
@@ -333,7 +334,8 @@
       LLVMExternalWeakLinkage        => 11,
       LLVMGhostLinkage               => 12,
       LLVMCommonLinkage              => 13,
-      LLVMLinkerPrivateLinkage       => 14);
+      LLVMLinkerPrivateLinkage       => 14,
+      LLVMLinkerWeakLinkage          => 15);
 
    pragma Convention (C, LLVMLinkage);
 

Modified: llvm/trunk/docs/LangRef.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=107205&r1=107204&r2=107205&view=diff
==============================================================================
--- llvm/trunk/docs/LangRef.html (original)
+++ llvm/trunk/docs/LangRef.html Tue Jun 29 16:24:00 2010
@@ -24,6 +24,7 @@
         <ol>
           <li><a href="#linkage_private">'<tt>private</tt>' Linkage</a></li>
           <li><a href="#linkage_linker_private">'<tt>linker_private</tt>' Linkage</a></li>
+          <li><a href="#linkage_linker_weak">'<tt>linker_weak</tt>' Linkage</a></li>
           <li><a href="#linkage_internal">'<tt>internal</tt>' Linkage</a></li>
           <li><a href="#linkage_available_externally">'<tt>available_externally</tt>' Linkage</a></li>
           <li><a href="#linkage_linkonce">'<tt>linkonce</tt>' Linkage</a></li>
@@ -546,23 +547,27 @@
 
 <dl>
   <dt><tt><b><a name="linkage_private">private</a></b></tt></dt>
-  <dd>Global values with private linkage are only directly accessible by objects
-      in the current module.  In particular, linking code into a module with an
-      private global value may cause the private to be renamed as necessary to
-      avoid collisions.  Because the symbol is private to the module, all
-      references can be updated. This doesn't show up in any symbol table in the
-      object file.</dd>
+  <dd>Global values with "<tt>private</tt>" linkage are only directly accessible
+      by objects in the current module.  In particular, linking code into a
+      module with an private global value may cause the private to be renamed as
+      necessary to avoid collisions.  Because the symbol is private to the
+      module, all references can be updated. This doesn't show up in any symbol
+      table in the object file.</dd>
 
   <dt><tt><b><a name="linkage_linker_private">linker_private</a></b></tt></dt>
-  <dd>Similar to private, but the symbol is passed through the assembler and
-      removed by the linker after evaluation.  Note that (unlike private
-      symbols) linker_private symbols are subject to coalescing by the linker:
-      weak symbols get merged and redefinitions are rejected.  However, unlike
-      normal strong symbols, they are removed by the linker from the final
-      linked image (executable or dynamic library).</dd>
+  <dd>Similar to <tt>private</tt>, but the symbol is passed through the
+      assembler and removed by the linker after evaluation.  Note that (unlike
+      <tt>private</tt> symbols) <tt>linker_private</tt> symbols are subject to
+      coalescing by the linker: weak symbols get merged and redefinitions are
+      rejected.  However, unlike normal strong symbols, they are removed by the
+      linker from the final linked image (executable or dynamic library).</dd>
+
+  <dt><tt><b><a name="linkage_linker_weak">linker_weak</a></b></tt></dt>
+  <dd>Global values with "<tt>linker_weak</tt>" linkage are given weak linkage,
+      but are removed by the linker after evaluation.</dd>
 
   <dt><tt><b><a name="linkage_internal">internal</a></b></tt></dt>
-  <dd>Similar to private, but the value shows as a local symbol
+  <dd>Similar to <tt>private</tt>, but the value shows as a local symbol
       (<tt>STB_LOCAL</tt> in the case of ELF) in the object file. This
       corresponds to the notion of the '<tt>static</tt>' keyword in C.</dd>
 

Modified: llvm/trunk/include/llvm-c/Core.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm-c/Core.h?rev=107205&r1=107204&r2=107205&view=diff
==============================================================================
--- llvm/trunk/include/llvm-c/Core.h (original)
+++ llvm/trunk/include/llvm-c/Core.h Tue Jun 29 16:24:00 2010
@@ -226,7 +226,8 @@
   LLVMExternalWeakLinkage,/**< ExternalWeak linkage description */
   LLVMGhostLinkage,       /**< Obsolete */
   LLVMCommonLinkage,      /**< Tentative definitions */
-  LLVMLinkerPrivateLinkage /**< Like Private, but linker removes. */
+  LLVMLinkerPrivateLinkage, /**< Like private, but linker removes. */
+  LLVMLinkerWeakLinkage   /**< Like linker private, but weak. */
 } LLVMLinkage;
 
 typedef enum {

Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/AsmPrinter.h?rev=107205&r1=107204&r2=107205&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/AsmPrinter.h (original)
+++ llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Tue Jun 29 16:24:00 2010
@@ -285,7 +285,7 @@
     MCSymbol *GetCPISymbol(unsigned CPID) const;
 
     /// GetJTISymbol - Return the symbol for the specified jump table entry.
-    MCSymbol *GetJTISymbol(unsigned JTID, bool isLinkerPrivate = false) const;
+    MCSymbol *GetJTISymbol(unsigned JTID, bool PassToLinker = false) const;
 
     /// GetJTSetSymbol - Return the symbol for the specified jump table .set
     /// FIXME: privatize to AsmPrinter.

Modified: llvm/trunk/include/llvm/CodeGen/MachineFunction.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFunction.h?rev=107205&r1=107204&r2=107205&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineFunction.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineFunction.h Tue Jun 29 16:24:00 2010
@@ -402,10 +402,10 @@
   //
   
   /// getJTISymbol - Return the MCSymbol for the specified non-empty jump table.
-  /// If isLinkerPrivate is specified, an 'l' label is returned, otherwise a
-  /// normal 'L' label is returned.
-  MCSymbol *getJTISymbol(unsigned JTI, MCContext &Ctx, 
-                         bool isLinkerPrivate = false) const;
+  /// If PassToLinker is specified, an 'l' label is returned, otherwise a normal
+  /// 'L' label is returned.
+  MCSymbol *getJTISymbol(unsigned JTI, MCContext &Ctx,
+                         bool PassToLinker = false) const;
 };
 
 //===--------------------------------------------------------------------===//

Modified: llvm/trunk/include/llvm/GlobalValue.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/GlobalValue.h?rev=107205&r1=107204&r2=107205&view=diff
==============================================================================
--- llvm/trunk/include/llvm/GlobalValue.h (original)
+++ llvm/trunk/include/llvm/GlobalValue.h Tue Jun 29 16:24:00 2010
@@ -39,7 +39,8 @@
     AppendingLinkage,   ///< Special purpose, only applies to global arrays
     InternalLinkage,    ///< Rename collisions when linking (static functions).
     PrivateLinkage,     ///< Like Internal, but omit from symbol table.
-    LinkerPrivateLinkage, ///< Like Private, but linker removes.
+    LinkerPrivateLinkage, ///< Like private, but linker removes.
+    LinkerWeakLinkage,  ///< Like linker private, but weak.
     DLLImportLinkage,   ///< Function to be imported from DLL
     DLLExportLinkage,   ///< Function to be accessible from DLL.
     ExternalWeakLinkage,///< ExternalWeak linkage description.
@@ -132,7 +133,10 @@
     return Linkage == PrivateLinkage;
   }
   static bool isLinkerPrivateLinkage(LinkageTypes Linkage) {
-    return Linkage==LinkerPrivateLinkage;
+    return Linkage == LinkerPrivateLinkage;
+  }
+  static bool isLinkerWeakLinkage(LinkageTypes Linkage) {
+    return Linkage == LinkerWeakLinkage;
   }
   static bool isLocalLinkage(LinkageTypes Linkage) {
     return isInternalLinkage(Linkage) || isPrivateLinkage(Linkage) ||
@@ -187,6 +191,7 @@
   bool hasInternalLinkage() const { return isInternalLinkage(Linkage); }
   bool hasPrivateLinkage() const { return isPrivateLinkage(Linkage); }
   bool hasLinkerPrivateLinkage() const { return isLinkerPrivateLinkage(Linkage); }
+  bool hasLinkerWeakLinkage() const { return isLinkerWeakLinkage(Linkage); }
   bool hasLocalLinkage() const { return isLocalLinkage(Linkage); }
   bool hasDLLImportLinkage() const { return isDLLImportLinkage(Linkage); }
   bool hasDLLExportLinkage() const { return isDLLExportLinkage(Linkage); }

Modified: llvm/trunk/include/llvm/MC/MCAsmInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAsmInfo.h?rev=107205&r1=107204&r2=107205&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCAsmInfo.h (original)
+++ llvm/trunk/include/llvm/MC/MCAsmInfo.h Tue Jun 29 16:24:00 2010
@@ -85,6 +85,11 @@
     /// be passed through the assembler but be removed by the linker.  This
     /// is "l" on Darwin, currently used for some ObjC metadata.
     const char *LinkerPrivateGlobalPrefix;   // Defaults to ""
+
+    /// LinkerWeakGlobalPrefix - This prefix is used for symbols that are marked
+    /// "weak" and should be passed through the assembler, but be removed by the
+    /// linker.  This is "l" on Darwin, currently used for some ObjC metadata.
+    const char *LinkerWeakGlobalPrefix;      // Defaults to ""
     
     /// InlineAsmStart/End - If these are nonempty, they contain a directive to
     /// emit before and after an inline assembly statement.
@@ -335,6 +340,9 @@
     const char *getLinkerPrivateGlobalPrefix() const {
       return LinkerPrivateGlobalPrefix;
     }
+    const char *getLinkerWeakGlobalPrefix() const {
+      return LinkerWeakGlobalPrefix;
+    }
     const char *getInlineAsmStart() const {
       return InlineAsmStart;
     }

Modified: llvm/trunk/include/llvm/Target/Mangler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Mangler.h?rev=107205&r1=107204&r2=107205&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/Mangler.h (original)
+++ llvm/trunk/include/llvm/Target/Mangler.h Tue Jun 29 16:24:00 2010
@@ -32,7 +32,8 @@
   enum ManglerPrefixTy {
     Default,               ///< Emit default string before each symbol.
     Private,               ///< Emit "private" prefix before each symbol.
-    LinkerPrivate          ///< Emit "linker private" prefix before each symbol.
+    LinkerPrivate,         ///< Emit "linker private" prefix before each symbol.
+    LinkerWeak             ///< Emit "linker weak" prefix before each symbol.
   };
 
 private:

Modified: llvm/trunk/lib/AsmParser/LLLexer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLLexer.cpp?rev=107205&r1=107204&r2=107205&view=diff
==============================================================================
--- llvm/trunk/lib/AsmParser/LLLexer.cpp (original)
+++ llvm/trunk/lib/AsmParser/LLLexer.cpp Tue Jun 29 16:24:00 2010
@@ -492,6 +492,7 @@
 
   KEYWORD(private);
   KEYWORD(linker_private);
+  KEYWORD(linker_weak);
   KEYWORD(internal);
   KEYWORD(available_externally);
   KEYWORD(linkonce);

Modified: llvm/trunk/lib/AsmParser/LLParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=107205&r1=107204&r2=107205&view=diff
==============================================================================
--- llvm/trunk/lib/AsmParser/LLParser.cpp (original)
+++ llvm/trunk/lib/AsmParser/LLParser.cpp Tue Jun 29 16:24:00 2010
@@ -198,6 +198,7 @@
     //               OptionalAddrSpace ('constant'|'global') ...
     case lltok::kw_private :       // OptionalLinkage
     case lltok::kw_linker_private: // OptionalLinkage
+    case lltok::kw_linker_weak:    // OptionalLinkage
     case lltok::kw_internal:       // OptionalLinkage
     case lltok::kw_weak:           // OptionalLinkage
     case lltok::kw_weak_odr:       // OptionalLinkage
@@ -629,7 +630,8 @@
       Linkage != GlobalValue::WeakODRLinkage &&
       Linkage != GlobalValue::InternalLinkage &&
       Linkage != GlobalValue::PrivateLinkage &&
-      Linkage != GlobalValue::LinkerPrivateLinkage)
+      Linkage != GlobalValue::LinkerPrivateLinkage &&
+      Linkage != GlobalValue::LinkerWeakLinkage)
     return Error(LinkageLoc, "invalid linkage type for alias");
 
   Constant *Aliasee;
@@ -1013,6 +1015,7 @@
 ///   ::= /*empty*/
 ///   ::= 'private'
 ///   ::= 'linker_private'
+///   ::= 'linker_weak'
 ///   ::= 'internal'
 ///   ::= 'weak'
 ///   ::= 'weak_odr'
@@ -1030,6 +1033,7 @@
   default:                       Res=GlobalValue::ExternalLinkage; return false;
   case lltok::kw_private:        Res = GlobalValue::PrivateLinkage;       break;
   case lltok::kw_linker_private: Res = GlobalValue::LinkerPrivateLinkage; break;
+  case lltok::kw_linker_weak:    Res = GlobalValue::LinkerWeakLinkage;    break;
   case lltok::kw_internal:       Res = GlobalValue::InternalLinkage;      break;
   case lltok::kw_weak:           Res = GlobalValue::WeakAnyLinkage;       break;
   case lltok::kw_weak_odr:       Res = GlobalValue::WeakODRLinkage;       break;
@@ -2704,6 +2708,7 @@
     break;
   case GlobalValue::PrivateLinkage:
   case GlobalValue::LinkerPrivateLinkage:
+  case GlobalValue::LinkerWeakLinkage:
   case GlobalValue::InternalLinkage:
   case GlobalValue::AvailableExternallyLinkage:
   case GlobalValue::LinkOnceAnyLinkage:

Modified: llvm/trunk/lib/AsmParser/LLToken.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLToken.h?rev=107205&r1=107204&r2=107205&view=diff
==============================================================================
--- llvm/trunk/lib/AsmParser/LLToken.h (original)
+++ llvm/trunk/lib/AsmParser/LLToken.h Tue Jun 29 16:24:00 2010
@@ -37,8 +37,9 @@
     kw_declare, kw_define,
     kw_global,  kw_constant,
 
-    kw_private, kw_linker_private, kw_internal, kw_linkonce, kw_linkonce_odr,
-    kw_weak, kw_weak_odr, kw_appending, kw_dllimport, kw_dllexport, kw_common,
+    kw_private, kw_linker_private, kw_linker_weak, kw_internal, kw_linkonce,
+    kw_linkonce_odr, kw_weak, kw_weak_odr, kw_appending, kw_dllimport,
+    kw_dllexport, kw_common,
     kw_available_externally,
     kw_default, kw_hidden, kw_protected,
     kw_extern_weak,

Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp?rev=107205&r1=107204&r2=107205&view=diff
==============================================================================
--- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp (original)
+++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp Tue Jun 29 16:24:00 2010
@@ -75,6 +75,7 @@
   case 11: return GlobalValue::LinkOnceODRLinkage;
   case 12: return GlobalValue::AvailableExternallyLinkage;
   case 13: return GlobalValue::LinkerPrivateLinkage;
+  case 14: return GlobalValue::LinkerWeakLinkage;
   }
 }
 

Modified: llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp?rev=107205&r1=107204&r2=107205&view=diff
==============================================================================
--- llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp (original)
+++ llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp Tue Jun 29 16:24:00 2010
@@ -313,6 +313,7 @@
   case GlobalValue::LinkOnceODRLinkage:         return 11;
   case GlobalValue::AvailableExternallyLinkage: return 12;
   case GlobalValue::LinkerPrivateLinkage:       return 13;
+  case GlobalValue::LinkerWeakLinkage:          return 14;
   }
 }
 

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=107205&r1=107204&r2=107205&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Tue Jun 29 16:24:00 2010
@@ -199,6 +199,7 @@
   case GlobalValue::LinkOnceODRLinkage:
   case GlobalValue::WeakAnyLinkage:
   case GlobalValue::WeakODRLinkage:
+  case GlobalValue::LinkerWeakLinkage:
   case GlobalValue::LinkerPrivateLinkage:
     if (MAI->getWeakDefDirective() != 0) {
       // .globl _foo
@@ -1610,8 +1611,8 @@
 }
 
 /// GetJTISymbol - Return the symbol for the specified jump table entry.
-MCSymbol *AsmPrinter::GetJTISymbol(unsigned JTID, bool isLinkerPrivate) const {
-  return MF->getJTISymbol(JTID, OutContext, isLinkerPrivate);
+MCSymbol *AsmPrinter::GetJTISymbol(unsigned JTID, bool PassToLinker) const {
+  return MF->getJTISymbol(JTID, OutContext, PassToLinker);
 }
 
 /// GetJTSetSymbol - Return the symbol for the specified jump table .set

Modified: llvm/trunk/lib/CodeGen/MachineFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFunction.cpp?rev=107205&r1=107204&r2=107205&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineFunction.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineFunction.cpp Tue Jun 29 16:24:00 2010
@@ -410,17 +410,18 @@
 }
 
 /// getJTISymbol - Return the MCSymbol for the specified non-empty jump table.
-/// If isLinkerPrivate is specified, an 'l' label is returned, otherwise a
-/// normal 'L' label is returned.
-MCSymbol *MachineFunction::getJTISymbol(unsigned JTI, MCContext &Ctx, 
-                                        bool isLinkerPrivate) const {
+/// If isLinkerPrivate or isLinkerWeak is specified, an 'l' label is returned,
+/// otherwise a normal 'L' label is returned.
+MCSymbol *MachineFunction::getJTISymbol(unsigned JTI, MCContext &Ctx,
+                                        bool PassToLinker) const {
   assert(JumpTableInfo && "No jump tables");
   
   assert(JTI < JumpTableInfo->getJumpTables().size() && "Invalid JTI!");
   const MCAsmInfo &MAI = *getTarget().getMCAsmInfo();
   
-  const char *Prefix = isLinkerPrivate ? MAI.getLinkerPrivateGlobalPrefix() :
-                                         MAI.getPrivateGlobalPrefix();
+  const char *Prefix = PassToLinker ?
+    MAI.getLinkerPrivateGlobalPrefix() :
+    MAI.getPrivateGlobalPrefix();
   SmallString<60> Name;
   raw_svector_ostream(Name)
     << Prefix << "JTI" << getFunctionNumber() << '_' << JTI;

Modified: llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp?rev=107205&r1=107204&r2=107205&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp Tue Jun 29 16:24:00 2010
@@ -755,11 +755,12 @@
   /// the directive emitted (this occurs in ObjC metadata).
   if (!GV) return false;
 
-  // Check whether the mangled name has the "Private" or "LinkerPrivate" prefix.
+  // Check whether the mangled name has the "Private", "LinkerPrivate", or
+  // "LinkerWeak" prefix.
   if (GV->hasLocalLinkage() && !isa<Function>(GV)) {
     // FIXME: ObjC metadata is currently emitted as internal symbols that have
-    // \1L and \0l prefixes on them.  Fix them to be Private/LinkerPrivate and
-    // this horrible hack can go away.
+    // \1L and \1l prefixes on them.  Fix them to be Private / LinkerPrivate /
+    // LinkerWeak and this horrible hack can go away.
     MCSymbol *Sym = Mang->getSymbol(GV);
     if (Sym->getName()[0] == 'L' || Sym->getName()[0] == 'l')
       return false;

Modified: llvm/trunk/lib/Linker/LinkModules.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Linker/LinkModules.cpp?rev=107205&r1=107204&r2=107205&view=diff
==============================================================================
--- llvm/trunk/lib/Linker/LinkModules.cpp (original)
+++ llvm/trunk/lib/Linker/LinkModules.cpp Tue Jun 29 16:24:00 2010
@@ -735,6 +735,9 @@
   else if (SL == GlobalValue::LinkerPrivateLinkage &&
            DL == GlobalValue::LinkerPrivateLinkage)
     return GlobalValue::LinkerPrivateLinkage;
+  else if (SL == GlobalValue::LinkerWeakLinkage &&
+           DL == GlobalValue::LinkerWeakLinkage)
+    return GlobalValue::LinkerWeakLinkage;
   else {
     assert (SL == GlobalValue::PrivateLinkage &&
             DL == GlobalValue::PrivateLinkage && "Unexpected linkage type");

Modified: llvm/trunk/lib/MC/MCAsmInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmInfo.cpp?rev=107205&r1=107204&r2=107205&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAsmInfo.cpp (original)
+++ llvm/trunk/lib/MC/MCAsmInfo.cpp Tue Jun 29 16:24:00 2010
@@ -31,6 +31,7 @@
   GlobalPrefix = "";
   PrivateGlobalPrefix = ".";
   LinkerPrivateGlobalPrefix = "";
+  LinkerWeakGlobalPrefix = "";
   InlineAsmStart = "APP";
   InlineAsmEnd = "NO_APP";
   AssemblerDialect = 0;

Modified: llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp?rev=107205&r1=107204&r2=107205&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp (original)
+++ llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp Tue Jun 29 16:24:00 2010
@@ -21,6 +21,7 @@
   GlobalPrefix = "_";
   PrivateGlobalPrefix = "L";
   LinkerPrivateGlobalPrefix = "l";
+  LinkerWeakGlobalPrefix = "l";
   AllowQuotesInName = true;
   HasSingleParameterDotFile = false;
   HasSubsectionsViaSymbols = true;

Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp?rev=107205&r1=107204&r2=107205&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp (original)
+++ llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Tue Jun 29 16:24:00 2010
@@ -286,6 +286,8 @@
     Out << "GlobalValue::PrivateLinkage"; break;
   case GlobalValue::LinkerPrivateLinkage:
     Out << "GlobalValue::LinkerPrivateLinkage"; break;
+  case GlobalValue::LinkerWeakLinkage:
+    Out << "GlobalValue::LinkerWeakLinkage"; break;
   case GlobalValue::AvailableExternallyLinkage:
     Out << "GlobalValue::AvailableExternallyLinkage "; break;
   case GlobalValue::LinkOnceAnyLinkage:

Modified: llvm/trunk/lib/Target/Mangler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mangler.cpp?rev=107205&r1=107204&r2=107205&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mangler.cpp (original)
+++ llvm/trunk/lib/Target/Mangler.cpp Tue Jun 29 16:24:00 2010
@@ -118,6 +118,9 @@
     } else if (PrefixTy == Mangler::LinkerPrivate) {
       const char *Prefix = MAI.getLinkerPrivateGlobalPrefix();
       OutName.append(Prefix, Prefix+strlen(Prefix));
+    } else if (PrefixTy == Mangler::LinkerWeak) {
+      const char *Prefix = MAI.getLinkerWeakGlobalPrefix();
+      OutName.append(Prefix, Prefix+strlen(Prefix));
     }
 
     const char *Prefix = MAI.getGlobalPrefix();
@@ -182,6 +185,8 @@
     PrefixTy = Mangler::Private;
   else if (GV->hasLinkerPrivateLinkage())
     PrefixTy = Mangler::LinkerPrivate;
+  else if (GV->hasLinkerWeakLinkage())
+    PrefixTy = Mangler::LinkerWeak;
   
   // If this global has a name, handle it simply.
   if (GV->hasName()) {

Modified: llvm/trunk/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp?rev=107205&r1=107204&r2=107205&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp Tue Jun 29 16:24:00 2010
@@ -129,6 +129,7 @@
   case GlobalValue::WeakAnyLinkage:
   case GlobalValue::WeakODRLinkage:
   case GlobalValue::ExternalLinkage:
+  case GlobalValue::LinkerWeakLinkage:
     emitArrayBound(GVSym, GV);
     OutStreamer.EmitSymbolAttribute(GVSym, MCSA_Global);
 

Modified: llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp?rev=107205&r1=107204&r2=107205&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp (original)
+++ llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp Tue Jun 29 16:24:00 2010
@@ -535,6 +535,7 @@
   case GlobalValue::WeakAnyLinkage:
   case GlobalValue::WeakODRLinkage:
   case GlobalValue::ExternalWeakLinkage:
+  case GlobalValue::LinkerWeakLinkage:
     return ExternalWeak;
 
   case GlobalValue::ExternalLinkage:

Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=107205&r1=107204&r2=107205&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/AsmWriter.cpp (original)
+++ llvm/trunk/lib/VMCore/AsmWriter.cpp Tue Jun 29 16:24:00 2010
@@ -1419,6 +1419,7 @@
   case GlobalValue::ExternalLinkage: break;
   case GlobalValue::PrivateLinkage:       Out << "private ";        break;
   case GlobalValue::LinkerPrivateLinkage: Out << "linker_private "; break;
+  case GlobalValue::LinkerWeakLinkage:    Out << "linker_weak ";    break;
   case GlobalValue::InternalLinkage:      Out << "internal ";       break;
   case GlobalValue::LinkOnceAnyLinkage:   Out << "linkonce ";       break;
   case GlobalValue::LinkOnceODRLinkage:   Out << "linkonce_odr ";   break;

Modified: llvm/trunk/lib/VMCore/Core.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Core.cpp?rev=107205&r1=107204&r2=107205&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Core.cpp (original)
+++ llvm/trunk/lib/VMCore/Core.cpp Tue Jun 29 16:24:00 2010
@@ -1058,6 +1058,8 @@
     return LLVMPrivateLinkage;
   case GlobalValue::LinkerPrivateLinkage:
     return LLVMLinkerPrivateLinkage;
+  case GlobalValue::LinkerWeakLinkage:
+    return LLVMLinkerWeakLinkage;
   case GlobalValue::DLLImportLinkage:
     return LLVMDLLImportLinkage;
   case GlobalValue::DLLExportLinkage:
@@ -1108,6 +1110,9 @@
   case LLVMLinkerPrivateLinkage:
     GV->setLinkage(GlobalValue::LinkerPrivateLinkage);
     break;
+  case LLVMLinkerWeakLinkage:
+    GV->setLinkage(GlobalValue::LinkerWeakLinkage);
+    break;
   case LLVMDLLImportLinkage:
     GV->setLinkage(GlobalValue::DLLImportLinkage);
     break;

Modified: llvm/trunk/tools/llvm-nm/llvm-nm.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-nm/llvm-nm.cpp?rev=107205&r1=107204&r2=107205&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-nm/llvm-nm.cpp (original)
+++ llvm/trunk/tools/llvm-nm/llvm-nm.cpp Tue Jun 29 16:24:00 2010
@@ -89,7 +89,8 @@
 static void DumpSymbolNameForGlobalValue(GlobalValue &GV) {
   // Private linkage and available_externally linkage don't exist in symtab.
   if (GV.hasPrivateLinkage() || GV.hasLinkerPrivateLinkage() ||
-      GV.hasAvailableExternallyLinkage()) return;
+      GV.hasLinkerWeakLinkage() || GV.hasAvailableExternallyLinkage())
+    return;
   
   const std::string SymbolAddrStr = "        "; // Not used yet...
   char TypeChar = TypeCharForSymbol(GV);




From bruno.cardoso at gmail.com  Tue Jun 29 16:25:12 2010
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Tue, 29 Jun 2010 21:25:12 -0000
Subject: [llvm-commits] [llvm] r107206 -
	/llvm/trunk/lib/Target/X86/X86InstrSSE.td
Message-ID: <20100629212512.540672A6C12C@llvm.org>

Author: bruno
Date: Tue Jun 29 16:25:12 2010
New Revision: 107206

URL: http://llvm.org/viewvc/llvm-project?rev=107206&view=rev
Log:
Add AVX Move Aligned/Unaligned packed integers

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=107206&r1=107205&r2=107206&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Jun 29 16:25:12 2010
@@ -2168,38 +2168,79 @@
 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
                   "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
 
+let ExeDomain = SSEPackedInt in { // SSE integer instructions
+
 //===---------------------------------------------------------------------===//
-// SSE2 Instructions
+// SSE2 - Move Aligned/Unaligned Packed Integers
 //===---------------------------------------------------------------------===//
 
-//===---------------------------------------------------------------------===//
-// SSE integer instructions
-let ExeDomain = SSEPackedInt in {
+let isAsmParserOnly = 1 in {
+  let neverHasSideEffects = 1 in
+  def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
+                     "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
+  def VMOVDQUrr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
+                     "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
+
+  let canFoldAsLoad = 1, mayLoad = 1 in {
+  def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
+                     "movdqa\t{$src, $dst|$dst, $src}",
+                     [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>,
+                     VEX;
+  def VMOVDQUrm :  I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
+                     "vmovdqu\t{$src, $dst|$dst, $src}",
+                     [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
+                   XS, VEX, Requires<[HasAVX, HasSSE2]>;
+  }
+
+  let mayStore = 1 in {
+  def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
+                     (ins i128mem:$dst, VR128:$src),
+                     "movdqa\t{$src, $dst|$dst, $src}",
+                     [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>, VEX;
+  def VMOVDQUmr :  I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
+                     "vmovdqu\t{$src, $dst|$dst, $src}",
+                     [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
+                   XS, VEX, Requires<[HasAVX, HasSSE2]>;
+  }
+}
 
-// Move Instructions
 let neverHasSideEffects = 1 in
 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
                    "movdqa\t{$src, $dst|$dst, $src}", []>;
-let canFoldAsLoad = 1, mayLoad = 1 in
+
+let canFoldAsLoad = 1, mayLoad = 1 in {
 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
                    "movdqa\t{$src, $dst|$dst, $src}",
                    [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
-let mayStore = 1 in
-def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
-                   "movdqa\t{$src, $dst|$dst, $src}",
-                   [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
-let canFoldAsLoad = 1, mayLoad = 1 in
 def MOVDQUrm :   I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
                    "movdqu\t{$src, $dst|$dst, $src}",
                    [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
                  XS, Requires<[HasSSE2]>;
-let mayStore = 1 in
+}
+
+let mayStore = 1 in {
+def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
+                   "movdqa\t{$src, $dst|$dst, $src}",
+                   [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
 def MOVDQUmr :   I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
                    "movdqu\t{$src, $dst|$dst, $src}",
                    [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
                  XS, Requires<[HasSSE2]>;
+}
 
 // Intrinsic forms of MOVDQU load and store
+let isAsmParserOnly = 1 in {
+let canFoldAsLoad = 1 in
+def VMOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
+                       "vmovdqu\t{$src, $dst|$dst, $src}",
+                       [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
+                     XS, VEX, Requires<[HasAVX, HasSSE2]>;
+def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
+                       "vmovdqu\t{$src, $dst|$dst, $src}",
+                       [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
+                     XS, VEX, Requires<[HasAVX, HasSSE2]>;
+}
+
 let canFoldAsLoad = 1 in
 def MOVDQUrm_Int :   I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
                        "movdqu\t{$src, $dst|$dst, $src}",




From isanbard at gmail.com  Tue Jun 29 16:41:58 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 29 Jun 2010 21:41:58 -0000
Subject: [llvm-commits] [llvm] r107207 - /llvm/trunk/docs/LangRef.html
Message-ID: <20100629214158.EB6262A6C12C@llvm.org>

Author: void
Date: Tue Jun 29 16:41:58 2010
New Revision: 107207

URL: http://llvm.org/viewvc/llvm-project?rev=107207&view=rev
Log:
Improve explanation.

Modified:
    llvm/trunk/docs/LangRef.html

Modified: llvm/trunk/docs/LangRef.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=107207&r1=107206&r2=107207&view=diff
==============================================================================
--- llvm/trunk/docs/LangRef.html (original)
+++ llvm/trunk/docs/LangRef.html Tue Jun 29 16:41:58 2010
@@ -560,11 +560,15 @@
       <tt>private</tt> symbols) <tt>linker_private</tt> symbols are subject to
       coalescing by the linker: weak symbols get merged and redefinitions are
       rejected.  However, unlike normal strong symbols, they are removed by the
-      linker from the final linked image (executable or dynamic library).</dd>
+      linker from the final linked image (executable or dynamic library).
+      This is currently only used for Objective-C metadata.</dd>
 
   <dt><tt><b><a name="linkage_linker_weak">linker_weak</a></b></tt></dt>
   <dd>Global values with "<tt>linker_weak</tt>" linkage are given weak linkage,
-      but are removed by the linker after evaluation.</dd>
+      but are removed by the linker after evaluation. Unlike normal weak
+      symbols, linker weak symbols are removed by the linker from the linal
+      linked image (executable or dynamic library). This is currently only used
+      for Objective-C metadata.</dd>
 
   <dt><tt><b><a name="linkage_internal">internal</a></b></tt></dt>
   <dd>Similar to <tt>private</tt>, but the value shows as a local symbol




From dpatel at apple.com  Tue Jun 29 16:51:32 2010
From: dpatel at apple.com (Devang Patel)
Date: Tue, 29 Jun 2010 21:51:32 -0000
Subject: [llvm-commits] [llvm] r107208 -
	/llvm/trunk/lib/CodeGen/MachineInstr.cpp
Message-ID: <20100629215132.932142A6C12C@llvm.org>

Author: dpatel
Date: Tue Jun 29 16:51:32 2010
New Revision: 107208

URL: http://llvm.org/viewvc/llvm-project?rev=107208&view=rev
Log:
Print InlinedAt location.

Modified:
    llvm/trunk/lib/CodeGen/MachineInstr.cpp

Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=107208&r1=107207&r2=107208&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Tue Jun 29 16:51:32 2010
@@ -1211,6 +1211,28 @@
   dbgs() << "  " << *this;
 }
 
+static void printDebugLoc(DebugLoc DL, const MachineFunction *MF, 
+                         raw_ostream &CommentOS) {
+  const LLVMContext &Ctx = MF->getFunction()->getContext();
+  if (!DL.isUnknown()) {          // Print source line info.
+    DIScope Scope(DL.getScope(Ctx));
+    // Omit the directory, because it's likely to be long and uninteresting.
+    if (Scope.Verify())
+      CommentOS << Scope.getFilename();
+    else
+      CommentOS << "<unknown>";
+    CommentOS << ':' << DL.getLine();
+    if (DL.getCol() != 0)
+      CommentOS << ':' << DL.getCol();
+    DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(DL.getInlinedAt(Ctx));
+    if (!InlinedAtDL.isUnknown()) {
+      CommentOS << " @[ ";
+      printDebugLoc(InlinedAtDL, MF, CommentOS);
+      CommentOS << " ]";
+    }
+  }
+}
+
 void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
   // We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
   const MachineFunction *MF = 0;
@@ -1308,19 +1330,8 @@
 
   if (!debugLoc.isUnknown() && MF) {
     if (!HaveSemi) OS << ";";
-
-    // TODO: print InlinedAtLoc information
-
-    DIScope Scope(debugLoc.getScope(MF->getFunction()->getContext()));
     OS << " dbg:";
-    // Omit the directory, since it's usually long and uninteresting.
-    if (Scope.Verify())
-      OS << Scope.getFilename();
-    else
-      OS << "<unknown>";
-    OS << ':' << debugLoc.getLine();
-    if (debugLoc.getCol() != 0)
-      OS << ':' << debugLoc.getCol();
+    printDebugLoc(debugLoc, MF, OS);
   }
 
   OS << "\n";




From clattner at apple.com  Tue Jun 29 16:56:26 2010
From: clattner at apple.com (Chris Lattner)
Date: Tue, 29 Jun 2010 14:56:26 -0700
Subject: [llvm-commits] [llvm] r107205 - in /llvm/trunk:
	bindings/ada/llvm/ docs/ include/llvm-c/ include/llvm/
	include/llvm/CodeGen/ include/llvm/MC/ include/llvm/Target/
	lib/AsmParser/ lib/Bitcode/Reader/ lib/Bitcode/Writer/
	lib/CodeGen/ lib/CodeGen/AsmPrinter/ lib/Linker/ lib/MC/
	lib/Target/ lib/Target/CppBackend/
	lib/Target/XCore/AsmPrinter/ lib/Transforms/IPO/ lib/VMCore/
	tools/llvm-nm/
In-Reply-To: <20100629212400.DABF32A6C12C@llvm.org>
References: <20100629212400.DABF32A6C12C@llvm.org>
Message-ID: <C7E3E4A7-A598-4C61-9513-2DFC7C2EC4CC@apple.com>


On Jun 29, 2010, at 2:24 PM, Bill Wendling wrote:

> Author: void
> Date: Tue Jun 29 16:24:00 2010
> New Revision: 107205
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=107205&view=rev
> Log:
> Introducing the "linker_weak" linkage type. This will be used for Objective-C
> metadata types which should be marked as "weak", but which the linker will
> remove upon final linkage.

Hi Bill,

This would have been good to talk about before you implemented it.  The name linker_weak doesn't seem very descriptive.  How about linker_private_weak or something like that?

> +++ llvm/trunk/docs/LangRef.html Tue Jun 29 16:24:00 2010
> 
>   <dt><tt><b><a name="linkage_linker_private">linker_private</a></b></tt></dt>
> +  <dd>Similar to <tt>private</tt>, but the symbol is passed through the
> +      assembler and removed by the linker after evaluation.  Note that (unlike
> +      <tt>private</tt> symbols) <tt>linker_private</tt> symbols are subject to
> +      coalescing by the linker: weak symbols get merged and redefinitions are
> +      rejected.  However, unlike normal strong symbols, they are removed by the
> +      linker from the final linked image (executable or dynamic library).</dd>

This description doesn't make sense: linker_private symbols aren't weak.  The description of weak stuff should be moved to linker_private_weak.  

> +  <dt><tt><b><a name="linkage_linker_weak">linker_weak</a></b></tt></dt>
> +  <dd>Global values with "<tt>linker_weak</tt>" linkage are given weak linkage,
> +      but are removed by the linker after evaluation.</dd>


This should describe the weak semantics.

> +++ llvm/trunk/include/llvm-c/Core.h Tue Jun 29 16:24:00 2010
> @@ -226,7 +226,8 @@
>   LLVMExternalWeakLinkage,/**< ExternalWeak linkage description */
>   LLVMGhostLinkage,       /**< Obsolete */
>   LLVMCommonLinkage,      /**< Tentative definitions */
> -  LLVMLinkerPrivateLinkage /**< Like Private, but linker removes. */
> +  LLVMLinkerPrivateLinkage, /**< Like private, but linker removes. */
> +  LLVMLinkerWeakLinkage   /**< Like linker private, but weak. */

This enum should also be updated with the rename.

> +++ llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Tue Jun 29 16:24:00 2010
> @@ -285,7 +285,7 @@
>     MCSymbol *GetCPISymbol(unsigned CPID) const;
> 
>     /// GetJTISymbol - Return the symbol for the specified jump table entry.
> -    MCSymbol *GetJTISymbol(unsigned JTID, bool isLinkerPrivate = false) const;
> +    MCSymbol *GetJTISymbol(unsigned JTID, bool PassToLinker = false) const;

"PassToLinker" doesn't mean anything, why did you rename it?  Please rename it to be more descriptive or improve the comment.  "isLinkerPrivate" seems like a perfectly good and descriptive name to me.

> +++ llvm/trunk/include/llvm/GlobalValue.h Tue Jun 29 16:24:00 2010
> @@ -39,7 +39,8 @@
>     AppendingLinkage,   ///< Special purpose, only applies to global arrays
>     InternalLinkage,    ///< Rename collisions when linking (static functions).
>     PrivateLinkage,     ///< Like Internal, but omit from symbol table.
> -    LinkerPrivateLinkage, ///< Like Private, but linker removes.
> +    LinkerPrivateLinkage, ///< Like private, but linker removes.
> +    LinkerWeakLinkage,  ///< Like linker private, but weak.

This enum should be renamed.

>     DLLImportLinkage,   ///< Function to be imported from DLL
>     DLLExportLinkage,   ///< Function to be accessible from DLL.
>     ExternalWeakLinkage,///< ExternalWeak linkage description.
> @@ -132,7 +133,10 @@
>     return Linkage == PrivateLinkage;
>   }
>   static bool isLinkerPrivateLinkage(LinkageTypes Linkage) {
> -    return Linkage==LinkerPrivateLinkage;
> +    return Linkage == LinkerPrivateLinkage;
> +  }
> +  static bool isLinkerWeakLinkage(LinkageTypes Linkage) {
> +    return Linkage == LinkerWeakLinkage;
>   }
>   static bool isLocalLinkage(LinkageTypes Linkage) {
>     return isInternalLinkage(Linkage) || isPrivateLinkage(Linkage) ||

The predicates should be updated.  isLocalLinkage and mayBeOverridden should return true, for example, any others?  

> project/llvm/trunk/include/llvm/MC/MCAsmInfo.h?rev=107205&r1=107204&r2=107205&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/MC/MCAsmInfo.h (original)
> +++ llvm/trunk/include/llvm/MC/MCAsmInfo.h Tue Jun 29 16:24:00 2010
> @@ -85,6 +85,11 @@
>     /// be passed through the assembler but be removed by the linker.  This
>     /// is "l" on Darwin, currently used for some ObjC metadata.
>     const char *LinkerPrivateGlobalPrefix;   // Defaults to ""
> +
> +    /// LinkerWeakGlobalPrefix - This prefix is used for symbols that are marked
> +    /// "weak" and should be passed through the assembler, but be removed by the
> +    /// linker.  This is "l" on Darwin, currently used for some ObjC metadata.
> +    const char *LinkerWeakGlobalPrefix;      // Defaults to ""

Please make this "HasLinkerPrivateWeakLinkage".  There is only one target with this linkage form and it always spells it the same way.  Predicating stuff based on the bool is more clean considering that the *name* is the same as LinkerPrivate the linkage semantics require a new *directive* to be emitted.

In fact, I don't think you actually need this bit at all since asmprinter handles these symbols like all the other .weak stuff.  Is it needed?

> 
> +++ llvm/trunk/include/llvm/Target/Mangler.h Tue Jun 29 16:24:00 2010
> @@ -32,7 +32,8 @@
>   enum ManglerPrefixTy {
>     Default,               ///< Emit default string before each symbol.
>     Private,               ///< Emit "private" prefix before each symbol.
> -    LinkerPrivate          ///< Emit "linker private" prefix before each symbol.
> +    LinkerPrivate,         ///< Emit "linker private" prefix before each symbol.
> +    LinkerWeak             ///< Emit "linker weak" prefix before each symbol.

This shouldn't be needed:  "LinkerWeak" and LinkerPrivate are mangled the same way, just use LinkerPrivate for LinkerPrivateWeak symbols.
> 
> +++ llvm/trunk/lib/AsmParser/LLLexer.cpp Tue Jun 29 16:24:00 2010
> @@ -492,6 +492,7 @@
> 
>   KEYWORD(private);
>   KEYWORD(linker_private);
> +  KEYWORD(linker_weak);

Please also change the name in the .ll files.

> +++ llvm/trunk/lib/CodeGen/MachineFunction.cpp Tue Jun 29 16:24:00 2010
> @@ -410,17 +410,18 @@
> }
> 
> /// getJTISymbol - Return the MCSymbol for the specified non-empty jump table.
> -/// If isLinkerPrivate is specified, an 'l' label is returned, otherwise a
> -/// normal 'L' label is returned.
> -MCSymbol *MachineFunction::getJTISymbol(unsigned JTI, MCContext &Ctx, 
> -                                        bool isLinkerPrivate) const {
> +/// If isLinkerPrivate or isLinkerWeak is specified, an 'l' label is returned,
> +/// otherwise a normal 'L' label is returned.
> +MCSymbol *MachineFunction::getJTISymbol(unsigned JTI, MCContext &Ctx,
> +                                        bool PassToLinker) const {
>   assert(JumpTableInfo && "No jump tables");
> 
>   assert(JTI < JumpTableInfo->getJumpTables().size() && "Invalid JTI!");
>   const MCAsmInfo &MAI = *getTarget().getMCAsmInfo();
> 
> -  const char *Prefix = isLinkerPrivate ? MAI.getLinkerPrivateGlobalPrefix() :
> -                                         MAI.getPrivateGlobalPrefix();
> +  const char *Prefix = PassToLinker ?
> +    MAI.getLinkerPrivateGlobalPrefix() :
> +    MAI.getPrivateGlobalPrefix();

I don't see why you changed this stuff, it seems completely orthogonal to the rest of the patch.  Please change it back.

> +++ llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp Tue Jun 29 16:24:00 2010
> @@ -755,11 +755,12 @@
>   /// the directive emitted (this occurs in ObjC metadata).
>   if (!GV) return false;
> 
> -  // Check whether the mangled name has the "Private" or "LinkerPrivate" prefix.
> +  // Check whether the mangled name has the "Private", "LinkerPrivate", or
> +  // "LinkerWeak" prefix.
>   if (GV->hasLocalLinkage() && !isa<Function>(GV)) {
>     // FIXME: ObjC metadata is currently emitted as internal symbols that have
> -    // \1L and \0l prefixes on them.  Fix them to be Private/LinkerPrivate and
> -    // this horrible hack can go away.
> +    // \1L and \1l prefixes on them.  Fix them to be Private / LinkerPrivate /
> +    // LinkerWeak and this horrible hack can go away.
>     MCSymbol *Sym = Mang->getSymbol(GV);
>     if (Sym->getName()[0] == 'L' || Sym->getName()[0] == 'l')
>       return false;

I greatly look forward to this hack going away! :)

> 
> Modified: llvm/trunk/lib/Linker/LinkModules.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Linker/LinkModules.cpp?rev=107205&r1=107204&r2=107205&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Linker/LinkModules.cpp (original)
> +++ llvm/trunk/lib/Linker/LinkModules.cpp Tue Jun 29 16:24:00 2010
> @@ -735,6 +735,9 @@
>   else if (SL == GlobalValue::LinkerPrivateLinkage &&
>            DL == GlobalValue::LinkerPrivateLinkage)
>     return GlobalValue::LinkerPrivateLinkage;
> +  else if (SL == GlobalValue::LinkerWeakLinkage &&
> +           DL == GlobalValue::LinkerWeakLinkage)
> +    return GlobalValue::LinkerWeakLinkage;
>   else {
>     assert (SL == GlobalValue::PrivateLinkage &&
>             DL == GlobalValue::PrivateLinkage && "Unexpected linkage type");

Is this really enough to cover all the .bc linking cases?

> 
> +++ llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Tue Jun 29 16:24:00 2010
> @@ -286,6 +286,8 @@
>     Out << "GlobalValue::PrivateLinkage"; break;
>   case GlobalValue::LinkerPrivateLinkage:
>     Out << "GlobalValue::LinkerPrivateLinkage"; break;
> +  case GlobalValue::LinkerWeakLinkage:
> +    Out << "GlobalValue::LinkerWeakLinkage"; break;

This will also need to be renamed.

> +++ llvm/trunk/lib/Target/Mangler.cpp Tue Jun 29 16:24:00 2010
> @@ -118,6 +118,9 @@
>     } else if (PrefixTy == Mangler::LinkerPrivate) {
>       const char *Prefix = MAI.getLinkerPrivateGlobalPrefix();
>       OutName.append(Prefix, Prefix+strlen(Prefix));
> +    } else if (PrefixTy == Mangler::LinkerWeak) {
> +      const char *Prefix = MAI.getLinkerWeakGlobalPrefix();
> +      OutName.append(Prefix, Prefix+strlen(Prefix));
>     }
> 
>     const char *Prefix = MAI.getGlobalPrefix();
> @@ -182,6 +185,8 @@
>     PrefixTy = Mangler::Private;
>   else if (GV->hasLinkerPrivateLinkage())
>     PrefixTy = Mangler::LinkerPrivate;
> +  else if (GV->hasLinkerWeakLinkage())
> +    PrefixTy = Mangler::LinkerWeak;

These should go away, just mangle both linker private's the same way.

> +++ llvm/trunk/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp Tue Jun 29 16:24:00 2010
> @@ -129,6 +129,7 @@
>   case GlobalValue::WeakAnyLinkage:
>   case GlobalValue::WeakODRLinkage:
>   case GlobalValue::ExternalLinkage:
> +  case GlobalValue::LinkerWeakLinkage:

Xcore doesn't support this linkage type.  The three darwin targets do support it.  Testcases?  We also need a testcase for .ll file assembly/disassembly.

-Chris


From clattner at apple.com  Tue Jun 29 16:57:12 2010
From: clattner at apple.com (Chris Lattner)
Date: Tue, 29 Jun 2010 14:57:12 -0700
Subject: [llvm-commits] [llvm] r107207 - /llvm/trunk/docs/LangRef.html
In-Reply-To: <20100629214158.EB6262A6C12C@llvm.org>
References: <20100629214158.EB6262A6C12C@llvm.org>
Message-ID: <D9852BE6-BD74-4DEA-A07B-1E193721B114@apple.com>


On Jun 29, 2010, at 2:41 PM, Bill Wendling wrote:

> Author: void
> Date: Tue Jun 29 16:41:58 2010
> New Revision: 107207
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=107207&view=rev
> Log:
> Improve explanation.

This shouldn't say what it is used for, it should say what it's valid for.  Saying it only works on darwin platforms would be a better approach.

-Chris

> 
> Modified:
>    llvm/trunk/docs/LangRef.html
> 
> Modified: llvm/trunk/docs/LangRef.html
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=107207&r1=107206&r2=107207&view=diff
> ==============================================================================
> --- llvm/trunk/docs/LangRef.html (original)
> +++ llvm/trunk/docs/LangRef.html Tue Jun 29 16:41:58 2010
> @@ -560,11 +560,15 @@
>       <tt>private</tt> symbols) <tt>linker_private</tt> symbols are subject to
>       coalescing by the linker: weak symbols get merged and redefinitions are
>       rejected.  However, unlike normal strong symbols, they are removed by the
> -      linker from the final linked image (executable or dynamic library).</dd>
> +      linker from the final linked image (executable or dynamic library).
> +      This is currently only used for Objective-C metadata.</dd>
> 
>   <dt><tt><b><a name="linkage_linker_weak">linker_weak</a></b></tt></dt>
>   <dd>Global values with "<tt>linker_weak</tt>" linkage are given weak linkage,
> -      but are removed by the linker after evaluation.</dd>
> +      but are removed by the linker after evaluation. Unlike normal weak
> +      symbols, linker weak symbols are removed by the linker from the linal
> +      linked image (executable or dynamic library). This is currently only used
> +      for Objective-C metadata.</dd>
> 
>   <dt><tt><b><a name="linkage_internal">internal</a></b></tt></dt>
>   <dd>Similar to <tt>private</tt>, but the value shows as a local symbol
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits




From bruno.cardoso at gmail.com  Tue Jun 29 17:12:16 2010
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Tue, 29 Jun 2010 22:12:16 -0000
Subject: [llvm-commits] [llvm] r107211 -
	/llvm/trunk/lib/Target/X86/X86InstrSSE.td
Message-ID: <20100629221216.395842A6C12C@llvm.org>

Author: bruno
Date: Tue Jun 29 17:12:16 2010
New Revision: 107211

URL: http://llvm.org/viewvc/llvm-project?rev=107211&view=rev
Log:
Move SSE2 Packed Integer instructions around, and create specific sections for each of them

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=107211&r1=107210&r2=107211&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Jun 29 17:12:16 2010
@@ -2168,11 +2168,10 @@
 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
                   "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
 
-let ExeDomain = SSEPackedInt in { // SSE integer instructions
-
 //===---------------------------------------------------------------------===//
-// SSE2 - Move Aligned/Unaligned Packed Integers
+// SSE2 - Move Aligned/Unaligned Packed Integer Instructions
 //===---------------------------------------------------------------------===//
+let ExeDomain = SSEPackedInt in { // SSE integer instructions
 
 let isAsmParserOnly = 1 in {
   let neverHasSideEffects = 1 in
@@ -2251,16 +2250,19 @@
                        [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
                      XS, Requires<[HasSSE2]>;
 
-let Constraints = "$src1 = $dst" in {
+} // ExeDomain = SSEPackedInt
 
-multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
-                            bit Commutable = 0> {
+//===---------------------------------------------------------------------===//
+// SSE2 - Packed Integer Arithmetic Instructions
+//===---------------------------------------------------------------------===//
+
+let ExeDomain = SSEPackedInt in { // SSE integer instructions
+
+multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
   def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
                                (ins VR128:$src1, VR128:$src2),
                !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
-               [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
-    let isCommutable = Commutable;
-  }
+               [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
   def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
                                (ins VR128:$src1, i128mem:$src2),
                !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
@@ -2289,13 +2291,11 @@
 
 /// PDI_binop_rm - Simple SSE2 binary operator.
 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
-                        ValueType OpVT, bit Commutable = 0> {
+                        ValueType OpVT> {
   def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
                                (ins VR128:$src1, VR128:$src2),
                !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
-               [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
-    let isCommutable = Commutable;
-  }
+               [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>;
   def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
                                (ins VR128:$src1, i128mem:$src2),
                !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
@@ -2308,14 +2308,11 @@
 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
 /// to collapse (bitconvert VT to VT) into its operand.
 ///
-multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
-                              bit Commutable = 0> {
+multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode> {
   def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
                (ins VR128:$src1, VR128:$src2),
                !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
-               [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
-    let isCommutable = Commutable;
-  }
+               [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]>;
   def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
                (ins VR128:$src1, i128mem:$src2),
                !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
@@ -2323,50 +2320,53 @@
                (memopv2i64 addr:$src2)))]>;
 }
 
-} // Constraints = "$src1 = $dst"
 } // ExeDomain = SSEPackedInt
 
 // 128-bit Integer Arithmetic
 
-defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
-defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
-defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
-defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
-
-defm PADDSB  : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
-defm PADDSW  : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
-defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
-defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
-
+let Constraints = "$src1 = $dst" in {
+let isCommutable = 1 in {
+defm PADDB  : PDI_binop_rm<0xFC, "paddb", add, v16i8>;
+defm PADDW  : PDI_binop_rm<0xFD, "paddw", add, v8i16>;
+defm PADDD  : PDI_binop_rm<0xFE, "paddd", add, v4i32>;
+defm PADDQ  : PDI_binop_rm_v2i64<0xD4, "paddq", add>;
+defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16>;
+}
 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
 
+// Intrinsic forms
 defm PSUBSB  : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
 defm PSUBSW  : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
+let isCommutable = 1 in {
+defm PADDSB  : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b>;
+defm PADDSW  : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w>;
+defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b>;
+defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w>;
+defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w>;
+defm PMULHW  : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w>;
+defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq>;
+defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd>;
+defm PAVGB   : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b>;
+defm PAVGW   : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w>;
+defm PMINUB  : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b>;
+defm PMINSW  : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w>;
+defm PMAXUB  : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b>;
+defm PMAXSW  : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w>;
+defm PSADBW  : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw>;
+}
 
-defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
-
-defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
-defm PMULHW  : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
-defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
-
-defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
-
-defm PAVGB  : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
-defm PAVGW  : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
-
-
-defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
-defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
-defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
-defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
-defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
+} // Constraints = "$src1 = $dst"
 
+//===---------------------------------------------------------------------===//
+// SSE2 - Packed Integer Logical Instructions
+//===---------------------------------------------------------------------===//
 
+let Constraints = "$src1 = $dst" in {
 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
                                int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
@@ -2386,18 +2386,37 @@
 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
                                int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
 
-// 128-bit logical shifts.
-let Constraints = "$src1 = $dst", neverHasSideEffects = 1,
-    ExeDomain = SSEPackedInt in {
-  def PSLLDQri : PDIi8<0x73, MRM7r,
-                       (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
-                       "pslldq\t{$src2, $dst|$dst, $src2}", []>;
-  def PSRLDQri : PDIi8<0x73, MRM3r,
-                       (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
-                       "psrldq\t{$src2, $dst|$dst, $src2}", []>;
-  // PSRADQri doesn't exist in SSE[1-3].
+let isCommutable = 1 in {
+defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and>;
+defm POR  : PDI_binop_rm_v2i64<0xEB, "por" , or>;
+defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor>;
 }
 
+let ExeDomain = SSEPackedInt in {
+  let neverHasSideEffects = 1 in {
+    // 128-bit logical shifts.
+    def PSLLDQri : PDIi8<0x73, MRM7r,
+                         (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
+                         "pslldq\t{$src2, $dst|$dst, $src2}", []>;
+    def PSRLDQri : PDIi8<0x73, MRM3r,
+                         (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
+                         "psrldq\t{$src2, $dst|$dst, $src2}", []>;
+    // PSRADQri doesn't exist in SSE[1-3].
+  }
+  def PANDNrr : PDI<0xDF, MRMSrcReg,
+                    (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
+                    "pandn\t{$src2, $dst|$dst, $src2}",
+                    [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
+                                              VR128:$src2)))]>;
+
+  def PANDNrm : PDI<0xDF, MRMSrcMem,
+                    (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
+                    "pandn\t{$src2, $dst|$dst, $src2}",
+                    [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
+                                              (memopv2i64 addr:$src2))))]>;
+}
+} // Constraints = "$src1 = $dst"
+
 let Predicates = [HasSSE2] in {
   def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
             (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
@@ -2417,32 +2436,20 @@
             (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
 }
 
-// Logical
-defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
-defm POR  : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
-defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
-
-let Constraints = "$src1 = $dst", ExeDomain = SSEPackedInt in {
-  def PANDNrr : PDI<0xDF, MRMSrcReg,
-                    (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
-                    "pandn\t{$src2, $dst|$dst, $src2}",
-                    [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
-                                              VR128:$src2)))]>;
-
-  def PANDNrm : PDI<0xDF, MRMSrcMem,
-                    (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
-                    "pandn\t{$src2, $dst|$dst, $src2}",
-                    [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
-                                              (memopv2i64 addr:$src2))))]>;
-}
+//===---------------------------------------------------------------------===//
+// SSE2 - Packed Integer Comparison Instructions
+//===---------------------------------------------------------------------===//
 
-// SSE2 Integer comparison
-defm PCMPEQB  : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b, 1>;
-defm PCMPEQW  : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w, 1>;
-defm PCMPEQD  : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d, 1>;
-defm PCMPGTB  : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
-defm PCMPGTW  : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
-defm PCMPGTD  : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
+let Constraints = "$src1 = $dst" in {
+  let isCommutable = 1 in {
+  defm PCMPEQB  : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
+  defm PCMPEQW  : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
+  defm PCMPEQD  : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
+  }
+  defm PCMPGTB  : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
+  defm PCMPGTW  : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
+  defm PCMPGTD  : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
+} // Constraints = "$src1 = $dst"
 
 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
           (PCMPEQBrr VR128:$src1, VR128:$src2)>;
@@ -2470,11 +2477,19 @@
 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
           (PCMPGTDrm VR128:$src1, addr:$src2)>;
 
+//===---------------------------------------------------------------------===//
+// SSE2 - Packed Integer Pack Instructions
+//===---------------------------------------------------------------------===//
 
-// Pack instructions
+let Constraints = "$src1 = $dst" in {
 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
+} // Constraints = "$src1 = $dst"
+
+//===---------------------------------------------------------------------===//
+// SSE2 - Packed Integer Shuffle Instructions
+//===---------------------------------------------------------------------===//
 
 let ExeDomain = SSEPackedInt in {
 
@@ -2523,7 +2538,14 @@
                                              (undef))))]>,
                 XD, Requires<[HasSSE2]>;
 
-// Unpack instructions
+} // ExeDomain = SSEPackedInt
+
+//===---------------------------------------------------------------------===//
+// SSE2 - Packed Integer Unpack Instructions
+//===---------------------------------------------------------------------===//
+
+let ExeDomain = SSEPackedInt in {
+
 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
                        PatFrag unp_frag, PatFrag bc_frag> {
   def rr : PDI<opc, MRMSrcReg,
@@ -2576,6 +2598,14 @@
                                          (memopv2i64 addr:$src2))))]>;
 }
 
+} // ExeDomain = SSEPackedInt
+
+//===---------------------------------------------------------------------===//
+// SSE2 - Packed Misc Integer Instructions
+//===---------------------------------------------------------------------===//
+
+let ExeDomain = SSEPackedInt in {
+
 // Extract / Insert
 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
                     (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),




From isanbard at gmail.com  Tue Jun 29 17:17:37 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 29 Jun 2010 22:17:37 -0000
Subject: [llvm-commits] [llvm] r107212 - /llvm/trunk/utils/buildit/build_llvm
Message-ID: <20100629221737.404082A6C12C@llvm.org>

Author: void
Date: Tue Jun 29 17:17:37 2010
New Revision: 107212

URL: http://llvm.org/viewvc/llvm-project?rev=107212&view=rev
Log:
Use -l option to remove symbols from i386.

Modified:
    llvm/trunk/utils/buildit/build_llvm

Modified: llvm/trunk/utils/buildit/build_llvm
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/buildit/build_llvm?rev=107212&r1=107211&r2=107212&view=diff
==============================================================================
--- llvm/trunk/utils/buildit/build_llvm (original)
+++ llvm/trunk/utils/buildit/build_llvm Tue Jun 29 17:17:37 2010
@@ -244,9 +244,12 @@
 
 if [ "x$LLVM_DEBUG" != "x1" ]; then
     # Strip local symbols from llvm libraries.
-    strip -S $DEST_DIR$DEST_ROOT/lib/*.[oa]
+    #
+    # Use '-l' to strip i386 modules. N.B. that flag doesn't work with kext or
+    # PPC objects!
+    strip -Sl $DEST_DIR$DEST_ROOT/lib/*.[oa]
     for f in `ls $DEST_DIR$DEST_ROOT/lib/*.so`; do
-        strip -Sx $f
+        strip -Sxl $f
     done
 fi
 
@@ -323,7 +326,10 @@
 if [ "$INSTALL_LIBLTO" = "yes" ]; then
   mkdir -p $DT_HOME/lib
   mv lib/libLTO.dylib $DT_HOME/lib/libLTO.dylib
-  strip -S $DT_HOME/lib/libLTO.dylib
+
+  # Use '-l' to strip i386 modules. N.B. that flag doesn't work with kext or
+  # PPC objects!
+  strip -arch all -Sl $DT_HOME/lib/libLTO.dylib
 fi
 rm -f lib/libLTO.a lib/libLTO.la
 
@@ -336,9 +342,12 @@
 find $DEST_DIR -name \*.dSYM -print | xargs rm -r || exit 1
 
 # Strip debugging information from files
+#
+# Use '-l' to strip i386 modules. N.B. that flag doesn't work with kext or
+# PPC objects!
 find $DEST_DIR -perm -0111 -type f \
     ! \( -name '*.la' -o -name gccas -o -name gccld -o -name llvm-config \) \
-    -print | xargs -n 1 -P ${SYSCTL} strip -S
+    -print | xargs -n 1 -P ${SYSCTL} strip -arch all -Sl
 
 chgrp -h -R wheel $DEST_DIR
 chgrp -R wheel $DEST_DIR




From echristo at apple.com  Tue Jun 29 17:22:22 2010
From: echristo at apple.com (Eric Christopher)
Date: Tue, 29 Jun 2010 22:22:22 -0000
Subject: [llvm-commits] [llvm] r107213 - /llvm/trunk/lib/Target/README.txt
Message-ID: <20100629222222.C57472A6C12C@llvm.org>

Author: echristo
Date: Tue Jun 29 17:22:22 2010
New Revision: 107213

URL: http://llvm.org/viewvc/llvm-project?rev=107213&view=rev
Log:
Add another bswap idiom that isn't matched.

Modified:
    llvm/trunk/lib/Target/README.txt

Modified: llvm/trunk/lib/Target/README.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/README.txt?rev=107213&r1=107212&r2=107213&view=diff
==============================================================================
--- llvm/trunk/lib/Target/README.txt (original)
+++ llvm/trunk/lib/Target/README.txt Tue Jun 29 17:22:22 2010
@@ -300,6 +300,14 @@
     return v ^ (t >> 8);
 }
 
+Neither is this (very standard idiom):
+
+int f(int n)
+{
+  return (((n) << 24) | (((n) & 0xff00) << 8) 
+       | (((n) >> 8) & 0xff00) | ((n) >> 24));
+}
+
 //===---------------------------------------------------------------------===//
 
 [LOOP RECOGNITION]




From dpatel at apple.com  Tue Jun 29 17:29:15 2010
From: dpatel at apple.com (Devang Patel)
Date: Tue, 29 Jun 2010 22:29:15 -0000
Subject: [llvm-commits] [llvm] r107214 -
	/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
Message-ID: <20100629222915.A0F422A6C12C@llvm.org>

Author: dpatel
Date: Tue Jun 29 17:29:15 2010
New Revision: 107214

URL: http://llvm.org/viewvc/llvm-project?rev=107214&view=rev
Log:
Print InlinedAt location.


Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=107214&r1=107213&r2=107214&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Tue Jun 29 17:29:15 2010
@@ -450,14 +450,11 @@
 }
 
 
-/// EmitComments - Pretty-print comments for instructions.
-static void EmitComments(const MachineInstr &MI, raw_ostream &CommentOS) {
-  const MachineFunction *MF = MI.getParent()->getParent();
-  const TargetMachine &TM = MF->getTarget();
-  
-  DebugLoc DL = MI.getDebugLoc();
+static void EmitDebugLoc(DebugLoc DL, const MachineFunction *MF, 
+                         raw_ostream &CommentOS) {
+  const LLVMContext &Ctx = MF->getFunction()->getContext();
   if (!DL.isUnknown()) {          // Print source line info.
-    DIScope Scope(DL.getScope(MF->getFunction()->getContext()));
+    DIScope Scope(DL.getScope(Ctx));
     // Omit the directory, because it's likely to be long and uninteresting.
     if (Scope.Verify())
       CommentOS << Scope.getFilename();
@@ -466,6 +463,23 @@
     CommentOS << ':' << DL.getLine();
     if (DL.getCol() != 0)
       CommentOS << ':' << DL.getCol();
+    DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(DL.getInlinedAt(Ctx));
+    if (!InlinedAtDL.isUnknown()) {
+      CommentOS << "[ ";
+      EmitDebugLoc(InlinedAtDL, MF, CommentOS);
+      CommentOS << " ]";
+    }
+  }
+}
+
+/// EmitComments - Pretty-print comments for instructions.
+static void EmitComments(const MachineInstr &MI, raw_ostream &CommentOS) {
+  const MachineFunction *MF = MI.getParent()->getParent();
+  const TargetMachine &TM = MF->getTarget();
+  
+  DebugLoc DL = MI.getDebugLoc();
+  if (!DL.isUnknown()) {          // Print source line info.
+    EmitDebugLoc(DL, MF, CommentOS);
     CommentOS << '\n';
   }
   




From isanbard at gmail.com  Tue Jun 29 17:33:12 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 29 Jun 2010 15:33:12 -0700
Subject: [llvm-commits] [llvm] r107205 - in
	/llvm/trunk:	bindings/ada/llvm/ docs/ include/llvm-c/
	include/llvm/	include/llvm/CodeGen/ include/llvm/MC/
	include/llvm/Target/	lib/AsmParser/ lib/Bitcode/Reader/
	lib/Bitcode/Writer/ lib/CodeGen/ lib/CodeGen/AsmPrinter/
	lib/Linker/ lib/MC/	lib/Target/
	lib/Target/CppBackend/	lib/Target/XCore/AsmPrinter/
	lib/Transforms/IPO/ lib/VMCore/	tools/llvm-nm/
In-Reply-To: <C7E3E4A7-A598-4C61-9513-2DFC7C2EC4CC@apple.com>
References: <20100629212400.DABF32A6C12C@llvm.org>
	<C7E3E4A7-A598-4C61-9513-2DFC7C2EC4CC@apple.com>
Message-ID: <AF811FB0-E72D-44DD-8BBD-1C6D4971F1AF@gmail.com>

On Jun 29, 2010, at 2:56 PM, Chris Lattner wrote:

> On Jun 29, 2010, at 2:24 PM, Bill Wendling wrote:
> 
>> Author: void
>> Date: Tue Jun 29 16:24:00 2010
>> New Revision: 107205
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=107205&view=rev
>> Log:
>> Introducing the "linker_weak" linkage type. This will be used for Objective-C
>> metadata types which should be marked as "weak", but which the linker will
>> remove upon final linkage.
> 
> Hi Bill,
> 
> This would have been good to talk about before you implemented it.  The name linker_weak doesn't seem very descriptive.  How about linker_private_weak or something like that?
> 
I thought about that, but they aren't private from what I can tell. They're marked as ".globl" and ".weak_definition".

>> +++ llvm/trunk/docs/LangRef.html Tue Jun 29 16:24:00 2010
>> 
>>  <dt><tt><b><a name="linkage_linker_private">linker_private</a></b></tt></dt>
>> +  <dd>Similar to <tt>private</tt>, but the symbol is passed through the
>> +      assembler and removed by the linker after evaluation.  Note that (unlike
>> +      <tt>private</tt> symbols) <tt>linker_private</tt> symbols are subject to
>> +      coalescing by the linker: weak symbols get merged and redefinitions are
>> +      rejected.  However, unlike normal strong symbols, they are removed by the
>> +      linker from the final linked image (executable or dynamic library).</dd>
> 
> This description doesn't make sense: linker_private symbols aren't weak.  The description of weak stuff should be moved to linker_private_weak.  
> 
I was quoting you from when I implemented linker_private. :) I'll try to make it more sensible.

>> +  <dt><tt><b><a name="linkage_linker_weak">linker_weak</a></b></tt></dt>
>> +  <dd>Global values with "<tt>linker_weak</tt>" linkage are given weak linkage,
>> +      but are removed by the linker after evaluation.</dd>
> 
> This should describe the weak semantics.
> 
>> +++ llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Tue Jun 29 16:24:00 2010
>> @@ -285,7 +285,7 @@
>>    MCSymbol *GetCPISymbol(unsigned CPID) const;
>> 
>>    /// GetJTISymbol - Return the symbol for the specified jump table entry.
>> -    MCSymbol *GetJTISymbol(unsigned JTID, bool isLinkerPrivate = false) const;
>> +    MCSymbol *GetJTISymbol(unsigned JTID, bool PassToLinker = false) const;
> 
> "PassToLinker" doesn't mean anything, why did you rename it?

I renamed it because the name didn't mean what it used to after the addition of "linker_weak".

> Please rename it to be more descriptive or improve the comment.  "isLinkerPrivate" seems like a perfectly good and descriptive name to me.

It would be if we only had "linker_private" to worry about. If we don't expect linker_private_weak here, then it can be reverted.

>> project/llvm/trunk/include/llvm/MC/MCAsmInfo.h?rev=107205&r1=107204&r2=107205&view=diff
>> ==============================================================================
>> --- llvm/trunk/include/llvm/MC/MCAsmInfo.h (original)
>> +++ llvm/trunk/include/llvm/MC/MCAsmInfo.h Tue Jun 29 16:24:00 2010
>> @@ -85,6 +85,11 @@
>>    /// be passed through the assembler but be removed by the linker.  This
>>    /// is "l" on Darwin, currently used for some ObjC metadata.
>>    const char *LinkerPrivateGlobalPrefix;   // Defaults to ""
>> +
>> +    /// LinkerWeakGlobalPrefix - This prefix is used for symbols that are marked
>> +    /// "weak" and should be passed through the assembler, but be removed by the
>> +    /// linker.  This is "l" on Darwin, currently used for some ObjC metadata.
>> +    const char *LinkerWeakGlobalPrefix;      // Defaults to ""
> 
> Please make this "HasLinkerPrivateWeakLinkage".  There is only one target with this linkage form and it always spells it the same way.  Predicating stuff based on the bool is more clean considering that the *name* is the same as LinkerPrivate the linkage semantics require a new *directive* to be emitted.
> 
> In fact, I don't think you actually need this bit at all since asmprinter handles these symbols like all the other .weak stuff.  Is it needed?
> 
I'll check to see if it's used. If it's not used, then it's relying upon the hack down below, which is bad. However, I much prefer having the prefix string in one place than relying upon it being buried in some deep part of the asm printer.

>> 
>> +++ llvm/trunk/include/llvm/Target/Mangler.h Tue Jun 29 16:24:00 2010
>> @@ -32,7 +32,8 @@
>>  enum ManglerPrefixTy {
>>    Default,               ///< Emit default string before each symbol.
>>    Private,               ///< Emit "private" prefix before each symbol.
>> -    LinkerPrivate          ///< Emit "linker private" prefix before each symbol.
>> +    LinkerPrivate,         ///< Emit "linker private" prefix before each symbol.
>> +    LinkerWeak             ///< Emit "linker weak" prefix before each symbol.
> 
> This shouldn't be needed:  "LinkerWeak" and LinkerPrivate are mangled the same way, just use LinkerPrivate for LinkerPrivateWeak symbols.
>> 
>> +++ llvm/trunk/lib/AsmParser/LLLexer.cpp Tue Jun 29 16:24:00 2010
>> @@ -492,6 +492,7 @@
>> 
>>  KEYWORD(private);
>>  KEYWORD(linker_private);
>> +  KEYWORD(linker_weak);
> 
> Please also change the name in the .ll files.
> 
When you ask me to change the name at the beginning, you don't have to keep reminding me to change it everywhere. :-)

>> +++ llvm/trunk/lib/CodeGen/MachineFunction.cpp Tue Jun 29 16:24:00 2010
>> @@ -410,17 +410,18 @@
>> }
>> 
>> /// getJTISymbol - Return the MCSymbol for the specified non-empty jump table.
>> -/// If isLinkerPrivate is specified, an 'l' label is returned, otherwise a
>> -/// normal 'L' label is returned.
>> -MCSymbol *MachineFunction::getJTISymbol(unsigned JTI, MCContext &Ctx, 
>> -                                        bool isLinkerPrivate) const {
>> +/// If isLinkerPrivate or isLinkerWeak is specified, an 'l' label is returned,
>> +/// otherwise a normal 'L' label is returned.
>> +MCSymbol *MachineFunction::getJTISymbol(unsigned JTI, MCContext &Ctx,
>> +                                        bool PassToLinker) const {
>>  assert(JumpTableInfo && "No jump tables");
>> 
>>  assert(JTI < JumpTableInfo->getJumpTables().size() && "Invalid JTI!");
>>  const MCAsmInfo &MAI = *getTarget().getMCAsmInfo();
>> 
>> -  const char *Prefix = isLinkerPrivate ? MAI.getLinkerPrivateGlobalPrefix() :
>> -                                         MAI.getPrivateGlobalPrefix();
>> +  const char *Prefix = PassToLinker ?
>> +    MAI.getLinkerPrivateGlobalPrefix() :
>> +    MAI.getPrivateGlobalPrefix();
> 
> I don't see why you changed this stuff, it seems completely orthogonal to the rest of the patch.  Please change it back.
> 
How do you mean? Can't these be linker_weak (or linker_private_weak) as well?

>> +++ llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp Tue Jun 29 16:24:00 2010
>> @@ -755,11 +755,12 @@
>>  /// the directive emitted (this occurs in ObjC metadata).
>>  if (!GV) return false;
>> 
>> -  // Check whether the mangled name has the "Private" or "LinkerPrivate" prefix.
>> +  // Check whether the mangled name has the "Private", "LinkerPrivate", or
>> +  // "LinkerWeak" prefix.
>>  if (GV->hasLocalLinkage() && !isa<Function>(GV)) {
>>    // FIXME: ObjC metadata is currently emitted as internal symbols that have
>> -    // \1L and \0l prefixes on them.  Fix them to be Private/LinkerPrivate and
>> -    // this horrible hack can go away.
>> +    // \1L and \1l prefixes on them.  Fix them to be Private / LinkerPrivate /
>> +    // LinkerWeak and this horrible hack can go away.
>>    MCSymbol *Sym = Mang->getSymbol(GV);
>>    if (Sym->getName()[0] == 'L' || Sym->getName()[0] == 'l')
>>      return false;
> 
> I greatly look forward to this hack going away! :)
> 
Me too. :)

>> 
>> Modified: llvm/trunk/lib/Linker/LinkModules.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Linker/LinkModules.cpp?rev=107205&r1=107204&r2=107205&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Linker/LinkModules.cpp (original)
>> +++ llvm/trunk/lib/Linker/LinkModules.cpp Tue Jun 29 16:24:00 2010
>> @@ -735,6 +735,9 @@
>>  else if (SL == GlobalValue::LinkerPrivateLinkage &&
>>           DL == GlobalValue::LinkerPrivateLinkage)
>>    return GlobalValue::LinkerPrivateLinkage;
>> +  else if (SL == GlobalValue::LinkerWeakLinkage &&
>> +           DL == GlobalValue::LinkerWeakLinkage)
>> +    return GlobalValue::LinkerWeakLinkage;
>>  else {
>>    assert (SL == GlobalValue::PrivateLinkage &&
>>            DL == GlobalValue::PrivateLinkage && "Unexpected linkage type");
> 
> Is this really enough to cover all the .bc linking cases?
> 
>> +++ llvm/trunk/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp Tue Jun 29 16:24:00 2010
>> @@ -129,6 +129,7 @@
>>  case GlobalValue::WeakAnyLinkage:
>>  case GlobalValue::WeakODRLinkage:
>>  case GlobalValue::ExternalLinkage:
>> +  case GlobalValue::LinkerWeakLinkage:
> 
> Xcore doesn't support this linkage type.  The three darwin targets do support it.  Testcases?  We also need a testcase for .ll file assembly/disassembly.
> 
There's already one testcase in the test suite. However, it has to wait for a future patch before I can convert it to using this schema.

-bw




From isanbard at gmail.com  Tue Jun 29 17:34:53 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 29 Jun 2010 22:34:53 -0000
Subject: [llvm-commits] [llvm] r107215 - in /llvm/trunk: bindings/ada/llvm/
 docs/ include/llvm-c/ include/llvm/ include/llvm/CodeGen/ include/llvm/MC/
 include/llvm/Target/ lib/AsmParser/ lib/Bitcode/Reader/ lib/Bitcode/Writer/
 lib/CodeGen/ lib/CodeGen/AsmPrinter/ lib/Linker/ lib/MC/ lib/Target/
 lib/Target/CppBackend/ lib/Target/XCore/AsmPrinter/ lib/Transforms/IPO/
 lib/VMCore/ tools/llvm-nm/
Message-ID: <20100629223453.AA9282A6C12C@llvm.org>

Author: void
Date: Tue Jun 29 17:34:52 2010
New Revision: 107215

URL: http://llvm.org/viewvc/llvm-project?rev=107215&view=rev
Log:
Revert r107205 and r107207.

Modified:
    llvm/trunk/bindings/ada/llvm/llvm.ads
    llvm/trunk/docs/LangRef.html
    llvm/trunk/include/llvm-c/Core.h
    llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
    llvm/trunk/include/llvm/CodeGen/MachineFunction.h
    llvm/trunk/include/llvm/GlobalValue.h
    llvm/trunk/include/llvm/MC/MCAsmInfo.h
    llvm/trunk/include/llvm/Target/Mangler.h
    llvm/trunk/lib/AsmParser/LLLexer.cpp
    llvm/trunk/lib/AsmParser/LLParser.cpp
    llvm/trunk/lib/AsmParser/LLToken.h
    llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp
    llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
    llvm/trunk/lib/CodeGen/MachineFunction.cpp
    llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
    llvm/trunk/lib/Linker/LinkModules.cpp
    llvm/trunk/lib/MC/MCAsmInfo.cpp
    llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp
    llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
    llvm/trunk/lib/Target/Mangler.cpp
    llvm/trunk/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp
    llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp
    llvm/trunk/lib/VMCore/AsmWriter.cpp
    llvm/trunk/lib/VMCore/Core.cpp
    llvm/trunk/tools/llvm-nm/llvm-nm.cpp

Modified: llvm/trunk/bindings/ada/llvm/llvm.ads
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/bindings/ada/llvm/llvm.ads?rev=107215&r1=107214&r2=107215&view=diff
==============================================================================
--- llvm/trunk/bindings/ada/llvm/llvm.ads (original)
+++ llvm/trunk/bindings/ada/llvm/llvm.ads Tue Jun 29 17:34:52 2010
@@ -316,8 +316,7 @@
       LLVMExternalWeakLinkage,
       LLVMGhostLinkage,
       LLVMCommonLinkage,
-      LLVMLinkerPrivateLinkage,
-      LLVMLinkerWeakLinkage);
+      LLVMLinkerPrivateLinkage);
 
    for LLVMLinkage use
      (LLVMExternalLinkage            => 0,
@@ -334,8 +333,7 @@
       LLVMExternalWeakLinkage        => 11,
       LLVMGhostLinkage               => 12,
       LLVMCommonLinkage              => 13,
-      LLVMLinkerPrivateLinkage       => 14,
-      LLVMLinkerWeakLinkage          => 15);
+      LLVMLinkerPrivateLinkage       => 14);
 
    pragma Convention (C, LLVMLinkage);
 

Modified: llvm/trunk/docs/LangRef.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=107215&r1=107214&r2=107215&view=diff
==============================================================================
--- llvm/trunk/docs/LangRef.html (original)
+++ llvm/trunk/docs/LangRef.html Tue Jun 29 17:34:52 2010
@@ -24,7 +24,6 @@
         <ol>
           <li><a href="#linkage_private">'<tt>private</tt>' Linkage</a></li>
           <li><a href="#linkage_linker_private">'<tt>linker_private</tt>' Linkage</a></li>
-          <li><a href="#linkage_linker_weak">'<tt>linker_weak</tt>' Linkage</a></li>
           <li><a href="#linkage_internal">'<tt>internal</tt>' Linkage</a></li>
           <li><a href="#linkage_available_externally">'<tt>available_externally</tt>' Linkage</a></li>
           <li><a href="#linkage_linkonce">'<tt>linkonce</tt>' Linkage</a></li>
@@ -547,31 +546,23 @@
 
 <dl>
   <dt><tt><b><a name="linkage_private">private</a></b></tt></dt>
-  <dd>Global values with "<tt>private</tt>" linkage are only directly accessible
-      by objects in the current module.  In particular, linking code into a
-      module with an private global value may cause the private to be renamed as
-      necessary to avoid collisions.  Because the symbol is private to the
-      module, all references can be updated. This doesn't show up in any symbol
-      table in the object file.</dd>
+  <dd>Global values with private linkage are only directly accessible by objects
+      in the current module.  In particular, linking code into a module with an
+      private global value may cause the private to be renamed as necessary to
+      avoid collisions.  Because the symbol is private to the module, all
+      references can be updated. This doesn't show up in any symbol table in the
+      object file.</dd>
 
   <dt><tt><b><a name="linkage_linker_private">linker_private</a></b></tt></dt>
-  <dd>Similar to <tt>private</tt>, but the symbol is passed through the
-      assembler and removed by the linker after evaluation.  Note that (unlike
-      <tt>private</tt> symbols) <tt>linker_private</tt> symbols are subject to
-      coalescing by the linker: weak symbols get merged and redefinitions are
-      rejected.  However, unlike normal strong symbols, they are removed by the
-      linker from the final linked image (executable or dynamic library).
-      This is currently only used for Objective-C metadata.</dd>
-
-  <dt><tt><b><a name="linkage_linker_weak">linker_weak</a></b></tt></dt>
-  <dd>Global values with "<tt>linker_weak</tt>" linkage are given weak linkage,
-      but are removed by the linker after evaluation. Unlike normal weak
-      symbols, linker weak symbols are removed by the linker from the linal
-      linked image (executable or dynamic library). This is currently only used
-      for Objective-C metadata.</dd>
+  <dd>Similar to private, but the symbol is passed through the assembler and
+      removed by the linker after evaluation.  Note that (unlike private
+      symbols) linker_private symbols are subject to coalescing by the linker:
+      weak symbols get merged and redefinitions are rejected.  However, unlike
+      normal strong symbols, they are removed by the linker from the final
+      linked image (executable or dynamic library).</dd>
 
   <dt><tt><b><a name="linkage_internal">internal</a></b></tt></dt>
-  <dd>Similar to <tt>private</tt>, but the value shows as a local symbol
+  <dd>Similar to private, but the value shows as a local symbol
       (<tt>STB_LOCAL</tt> in the case of ELF) in the object file. This
       corresponds to the notion of the '<tt>static</tt>' keyword in C.</dd>
 

Modified: llvm/trunk/include/llvm-c/Core.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm-c/Core.h?rev=107215&r1=107214&r2=107215&view=diff
==============================================================================
--- llvm/trunk/include/llvm-c/Core.h (original)
+++ llvm/trunk/include/llvm-c/Core.h Tue Jun 29 17:34:52 2010
@@ -226,8 +226,7 @@
   LLVMExternalWeakLinkage,/**< ExternalWeak linkage description */
   LLVMGhostLinkage,       /**< Obsolete */
   LLVMCommonLinkage,      /**< Tentative definitions */
-  LLVMLinkerPrivateLinkage, /**< Like private, but linker removes. */
-  LLVMLinkerWeakLinkage   /**< Like linker private, but weak. */
+  LLVMLinkerPrivateLinkage /**< Like Private, but linker removes. */
 } LLVMLinkage;
 
 typedef enum {

Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/AsmPrinter.h?rev=107215&r1=107214&r2=107215&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/AsmPrinter.h (original)
+++ llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Tue Jun 29 17:34:52 2010
@@ -285,7 +285,7 @@
     MCSymbol *GetCPISymbol(unsigned CPID) const;
 
     /// GetJTISymbol - Return the symbol for the specified jump table entry.
-    MCSymbol *GetJTISymbol(unsigned JTID, bool PassToLinker = false) const;
+    MCSymbol *GetJTISymbol(unsigned JTID, bool isLinkerPrivate = false) const;
 
     /// GetJTSetSymbol - Return the symbol for the specified jump table .set
     /// FIXME: privatize to AsmPrinter.

Modified: llvm/trunk/include/llvm/CodeGen/MachineFunction.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFunction.h?rev=107215&r1=107214&r2=107215&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineFunction.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineFunction.h Tue Jun 29 17:34:52 2010
@@ -402,10 +402,10 @@
   //
   
   /// getJTISymbol - Return the MCSymbol for the specified non-empty jump table.
-  /// If PassToLinker is specified, an 'l' label is returned, otherwise a normal
-  /// 'L' label is returned.
-  MCSymbol *getJTISymbol(unsigned JTI, MCContext &Ctx,
-                         bool PassToLinker = false) const;
+  /// If isLinkerPrivate is specified, an 'l' label is returned, otherwise a
+  /// normal 'L' label is returned.
+  MCSymbol *getJTISymbol(unsigned JTI, MCContext &Ctx, 
+                         bool isLinkerPrivate = false) const;
 };
 
 //===--------------------------------------------------------------------===//

Modified: llvm/trunk/include/llvm/GlobalValue.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/GlobalValue.h?rev=107215&r1=107214&r2=107215&view=diff
==============================================================================
--- llvm/trunk/include/llvm/GlobalValue.h (original)
+++ llvm/trunk/include/llvm/GlobalValue.h Tue Jun 29 17:34:52 2010
@@ -39,8 +39,7 @@
     AppendingLinkage,   ///< Special purpose, only applies to global arrays
     InternalLinkage,    ///< Rename collisions when linking (static functions).
     PrivateLinkage,     ///< Like Internal, but omit from symbol table.
-    LinkerPrivateLinkage, ///< Like private, but linker removes.
-    LinkerWeakLinkage,  ///< Like linker private, but weak.
+    LinkerPrivateLinkage, ///< Like Private, but linker removes.
     DLLImportLinkage,   ///< Function to be imported from DLL
     DLLExportLinkage,   ///< Function to be accessible from DLL.
     ExternalWeakLinkage,///< ExternalWeak linkage description.
@@ -133,10 +132,7 @@
     return Linkage == PrivateLinkage;
   }
   static bool isLinkerPrivateLinkage(LinkageTypes Linkage) {
-    return Linkage == LinkerPrivateLinkage;
-  }
-  static bool isLinkerWeakLinkage(LinkageTypes Linkage) {
-    return Linkage == LinkerWeakLinkage;
+    return Linkage==LinkerPrivateLinkage;
   }
   static bool isLocalLinkage(LinkageTypes Linkage) {
     return isInternalLinkage(Linkage) || isPrivateLinkage(Linkage) ||
@@ -191,7 +187,6 @@
   bool hasInternalLinkage() const { return isInternalLinkage(Linkage); }
   bool hasPrivateLinkage() const { return isPrivateLinkage(Linkage); }
   bool hasLinkerPrivateLinkage() const { return isLinkerPrivateLinkage(Linkage); }
-  bool hasLinkerWeakLinkage() const { return isLinkerWeakLinkage(Linkage); }
   bool hasLocalLinkage() const { return isLocalLinkage(Linkage); }
   bool hasDLLImportLinkage() const { return isDLLImportLinkage(Linkage); }
   bool hasDLLExportLinkage() const { return isDLLExportLinkage(Linkage); }

Modified: llvm/trunk/include/llvm/MC/MCAsmInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAsmInfo.h?rev=107215&r1=107214&r2=107215&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCAsmInfo.h (original)
+++ llvm/trunk/include/llvm/MC/MCAsmInfo.h Tue Jun 29 17:34:52 2010
@@ -85,11 +85,6 @@
     /// be passed through the assembler but be removed by the linker.  This
     /// is "l" on Darwin, currently used for some ObjC metadata.
     const char *LinkerPrivateGlobalPrefix;   // Defaults to ""
-
-    /// LinkerWeakGlobalPrefix - This prefix is used for symbols that are marked
-    /// "weak" and should be passed through the assembler, but be removed by the
-    /// linker.  This is "l" on Darwin, currently used for some ObjC metadata.
-    const char *LinkerWeakGlobalPrefix;      // Defaults to ""
     
     /// InlineAsmStart/End - If these are nonempty, they contain a directive to
     /// emit before and after an inline assembly statement.
@@ -340,9 +335,6 @@
     const char *getLinkerPrivateGlobalPrefix() const {
       return LinkerPrivateGlobalPrefix;
     }
-    const char *getLinkerWeakGlobalPrefix() const {
-      return LinkerWeakGlobalPrefix;
-    }
     const char *getInlineAsmStart() const {
       return InlineAsmStart;
     }

Modified: llvm/trunk/include/llvm/Target/Mangler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Mangler.h?rev=107215&r1=107214&r2=107215&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/Mangler.h (original)
+++ llvm/trunk/include/llvm/Target/Mangler.h Tue Jun 29 17:34:52 2010
@@ -32,8 +32,7 @@
   enum ManglerPrefixTy {
     Default,               ///< Emit default string before each symbol.
     Private,               ///< Emit "private" prefix before each symbol.
-    LinkerPrivate,         ///< Emit "linker private" prefix before each symbol.
-    LinkerWeak             ///< Emit "linker weak" prefix before each symbol.
+    LinkerPrivate          ///< Emit "linker private" prefix before each symbol.
   };
 
 private:

Modified: llvm/trunk/lib/AsmParser/LLLexer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLLexer.cpp?rev=107215&r1=107214&r2=107215&view=diff
==============================================================================
--- llvm/trunk/lib/AsmParser/LLLexer.cpp (original)
+++ llvm/trunk/lib/AsmParser/LLLexer.cpp Tue Jun 29 17:34:52 2010
@@ -492,7 +492,6 @@
 
   KEYWORD(private);
   KEYWORD(linker_private);
-  KEYWORD(linker_weak);
   KEYWORD(internal);
   KEYWORD(available_externally);
   KEYWORD(linkonce);

Modified: llvm/trunk/lib/AsmParser/LLParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=107215&r1=107214&r2=107215&view=diff
==============================================================================
--- llvm/trunk/lib/AsmParser/LLParser.cpp (original)
+++ llvm/trunk/lib/AsmParser/LLParser.cpp Tue Jun 29 17:34:52 2010
@@ -198,7 +198,6 @@
     //               OptionalAddrSpace ('constant'|'global') ...
     case lltok::kw_private :       // OptionalLinkage
     case lltok::kw_linker_private: // OptionalLinkage
-    case lltok::kw_linker_weak:    // OptionalLinkage
     case lltok::kw_internal:       // OptionalLinkage
     case lltok::kw_weak:           // OptionalLinkage
     case lltok::kw_weak_odr:       // OptionalLinkage
@@ -630,8 +629,7 @@
       Linkage != GlobalValue::WeakODRLinkage &&
       Linkage != GlobalValue::InternalLinkage &&
       Linkage != GlobalValue::PrivateLinkage &&
-      Linkage != GlobalValue::LinkerPrivateLinkage &&
-      Linkage != GlobalValue::LinkerWeakLinkage)
+      Linkage != GlobalValue::LinkerPrivateLinkage)
     return Error(LinkageLoc, "invalid linkage type for alias");
 
   Constant *Aliasee;
@@ -1015,7 +1013,6 @@
 ///   ::= /*empty*/
 ///   ::= 'private'
 ///   ::= 'linker_private'
-///   ::= 'linker_weak'
 ///   ::= 'internal'
 ///   ::= 'weak'
 ///   ::= 'weak_odr'
@@ -1033,7 +1030,6 @@
   default:                       Res=GlobalValue::ExternalLinkage; return false;
   case lltok::kw_private:        Res = GlobalValue::PrivateLinkage;       break;
   case lltok::kw_linker_private: Res = GlobalValue::LinkerPrivateLinkage; break;
-  case lltok::kw_linker_weak:    Res = GlobalValue::LinkerWeakLinkage;    break;
   case lltok::kw_internal:       Res = GlobalValue::InternalLinkage;      break;
   case lltok::kw_weak:           Res = GlobalValue::WeakAnyLinkage;       break;
   case lltok::kw_weak_odr:       Res = GlobalValue::WeakODRLinkage;       break;
@@ -2708,7 +2704,6 @@
     break;
   case GlobalValue::PrivateLinkage:
   case GlobalValue::LinkerPrivateLinkage:
-  case GlobalValue::LinkerWeakLinkage:
   case GlobalValue::InternalLinkage:
   case GlobalValue::AvailableExternallyLinkage:
   case GlobalValue::LinkOnceAnyLinkage:

Modified: llvm/trunk/lib/AsmParser/LLToken.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLToken.h?rev=107215&r1=107214&r2=107215&view=diff
==============================================================================
--- llvm/trunk/lib/AsmParser/LLToken.h (original)
+++ llvm/trunk/lib/AsmParser/LLToken.h Tue Jun 29 17:34:52 2010
@@ -37,9 +37,8 @@
     kw_declare, kw_define,
     kw_global,  kw_constant,
 
-    kw_private, kw_linker_private, kw_linker_weak, kw_internal, kw_linkonce,
-    kw_linkonce_odr, kw_weak, kw_weak_odr, kw_appending, kw_dllimport,
-    kw_dllexport, kw_common,
+    kw_private, kw_linker_private, kw_internal, kw_linkonce, kw_linkonce_odr,
+    kw_weak, kw_weak_odr, kw_appending, kw_dllimport, kw_dllexport, kw_common,
     kw_available_externally,
     kw_default, kw_hidden, kw_protected,
     kw_extern_weak,

Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp?rev=107215&r1=107214&r2=107215&view=diff
==============================================================================
--- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp (original)
+++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp Tue Jun 29 17:34:52 2010
@@ -75,7 +75,6 @@
   case 11: return GlobalValue::LinkOnceODRLinkage;
   case 12: return GlobalValue::AvailableExternallyLinkage;
   case 13: return GlobalValue::LinkerPrivateLinkage;
-  case 14: return GlobalValue::LinkerWeakLinkage;
   }
 }
 

Modified: llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp?rev=107215&r1=107214&r2=107215&view=diff
==============================================================================
--- llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp (original)
+++ llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp Tue Jun 29 17:34:52 2010
@@ -313,7 +313,6 @@
   case GlobalValue::LinkOnceODRLinkage:         return 11;
   case GlobalValue::AvailableExternallyLinkage: return 12;
   case GlobalValue::LinkerPrivateLinkage:       return 13;
-  case GlobalValue::LinkerWeakLinkage:          return 14;
   }
 }
 

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=107215&r1=107214&r2=107215&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Tue Jun 29 17:34:52 2010
@@ -199,7 +199,6 @@
   case GlobalValue::LinkOnceODRLinkage:
   case GlobalValue::WeakAnyLinkage:
   case GlobalValue::WeakODRLinkage:
-  case GlobalValue::LinkerWeakLinkage:
   case GlobalValue::LinkerPrivateLinkage:
     if (MAI->getWeakDefDirective() != 0) {
       // .globl _foo
@@ -1625,8 +1624,8 @@
 }
 
 /// GetJTISymbol - Return the symbol for the specified jump table entry.
-MCSymbol *AsmPrinter::GetJTISymbol(unsigned JTID, bool PassToLinker) const {
-  return MF->getJTISymbol(JTID, OutContext, PassToLinker);
+MCSymbol *AsmPrinter::GetJTISymbol(unsigned JTID, bool isLinkerPrivate) const {
+  return MF->getJTISymbol(JTID, OutContext, isLinkerPrivate);
 }
 
 /// GetJTSetSymbol - Return the symbol for the specified jump table .set

Modified: llvm/trunk/lib/CodeGen/MachineFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFunction.cpp?rev=107215&r1=107214&r2=107215&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineFunction.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineFunction.cpp Tue Jun 29 17:34:52 2010
@@ -410,18 +410,17 @@
 }
 
 /// getJTISymbol - Return the MCSymbol for the specified non-empty jump table.
-/// If isLinkerPrivate or isLinkerWeak is specified, an 'l' label is returned,
-/// otherwise a normal 'L' label is returned.
-MCSymbol *MachineFunction::getJTISymbol(unsigned JTI, MCContext &Ctx,
-                                        bool PassToLinker) const {
+/// If isLinkerPrivate is specified, an 'l' label is returned, otherwise a
+/// normal 'L' label is returned.
+MCSymbol *MachineFunction::getJTISymbol(unsigned JTI, MCContext &Ctx, 
+                                        bool isLinkerPrivate) const {
   assert(JumpTableInfo && "No jump tables");
   
   assert(JTI < JumpTableInfo->getJumpTables().size() && "Invalid JTI!");
   const MCAsmInfo &MAI = *getTarget().getMCAsmInfo();
   
-  const char *Prefix = PassToLinker ?
-    MAI.getLinkerPrivateGlobalPrefix() :
-    MAI.getPrivateGlobalPrefix();
+  const char *Prefix = isLinkerPrivate ? MAI.getLinkerPrivateGlobalPrefix() :
+                                         MAI.getPrivateGlobalPrefix();
   SmallString<60> Name;
   raw_svector_ostream(Name)
     << Prefix << "JTI" << getFunctionNumber() << '_' << JTI;

Modified: llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp?rev=107215&r1=107214&r2=107215&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp Tue Jun 29 17:34:52 2010
@@ -755,12 +755,11 @@
   /// the directive emitted (this occurs in ObjC metadata).
   if (!GV) return false;
 
-  // Check whether the mangled name has the "Private", "LinkerPrivate", or
-  // "LinkerWeak" prefix.
+  // Check whether the mangled name has the "Private" or "LinkerPrivate" prefix.
   if (GV->hasLocalLinkage() && !isa<Function>(GV)) {
     // FIXME: ObjC metadata is currently emitted as internal symbols that have
-    // \1L and \1l prefixes on them.  Fix them to be Private / LinkerPrivate /
-    // LinkerWeak and this horrible hack can go away.
+    // \1L and \0l prefixes on them.  Fix them to be Private/LinkerPrivate and
+    // this horrible hack can go away.
     MCSymbol *Sym = Mang->getSymbol(GV);
     if (Sym->getName()[0] == 'L' || Sym->getName()[0] == 'l')
       return false;

Modified: llvm/trunk/lib/Linker/LinkModules.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Linker/LinkModules.cpp?rev=107215&r1=107214&r2=107215&view=diff
==============================================================================
--- llvm/trunk/lib/Linker/LinkModules.cpp (original)
+++ llvm/trunk/lib/Linker/LinkModules.cpp Tue Jun 29 17:34:52 2010
@@ -735,9 +735,6 @@
   else if (SL == GlobalValue::LinkerPrivateLinkage &&
            DL == GlobalValue::LinkerPrivateLinkage)
     return GlobalValue::LinkerPrivateLinkage;
-  else if (SL == GlobalValue::LinkerWeakLinkage &&
-           DL == GlobalValue::LinkerWeakLinkage)
-    return GlobalValue::LinkerWeakLinkage;
   else {
     assert (SL == GlobalValue::PrivateLinkage &&
             DL == GlobalValue::PrivateLinkage && "Unexpected linkage type");

Modified: llvm/trunk/lib/MC/MCAsmInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmInfo.cpp?rev=107215&r1=107214&r2=107215&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAsmInfo.cpp (original)
+++ llvm/trunk/lib/MC/MCAsmInfo.cpp Tue Jun 29 17:34:52 2010
@@ -31,7 +31,6 @@
   GlobalPrefix = "";
   PrivateGlobalPrefix = ".";
   LinkerPrivateGlobalPrefix = "";
-  LinkerWeakGlobalPrefix = "";
   InlineAsmStart = "APP";
   InlineAsmEnd = "NO_APP";
   AssemblerDialect = 0;

Modified: llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp?rev=107215&r1=107214&r2=107215&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp (original)
+++ llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp Tue Jun 29 17:34:52 2010
@@ -21,7 +21,6 @@
   GlobalPrefix = "_";
   PrivateGlobalPrefix = "L";
   LinkerPrivateGlobalPrefix = "l";
-  LinkerWeakGlobalPrefix = "l";
   AllowQuotesInName = true;
   HasSingleParameterDotFile = false;
   HasSubsectionsViaSymbols = true;

Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp?rev=107215&r1=107214&r2=107215&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp (original)
+++ llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Tue Jun 29 17:34:52 2010
@@ -286,8 +286,6 @@
     Out << "GlobalValue::PrivateLinkage"; break;
   case GlobalValue::LinkerPrivateLinkage:
     Out << "GlobalValue::LinkerPrivateLinkage"; break;
-  case GlobalValue::LinkerWeakLinkage:
-    Out << "GlobalValue::LinkerWeakLinkage"; break;
   case GlobalValue::AvailableExternallyLinkage:
     Out << "GlobalValue::AvailableExternallyLinkage "; break;
   case GlobalValue::LinkOnceAnyLinkage:

Modified: llvm/trunk/lib/Target/Mangler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mangler.cpp?rev=107215&r1=107214&r2=107215&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mangler.cpp (original)
+++ llvm/trunk/lib/Target/Mangler.cpp Tue Jun 29 17:34:52 2010
@@ -118,9 +118,6 @@
     } else if (PrefixTy == Mangler::LinkerPrivate) {
       const char *Prefix = MAI.getLinkerPrivateGlobalPrefix();
       OutName.append(Prefix, Prefix+strlen(Prefix));
-    } else if (PrefixTy == Mangler::LinkerWeak) {
-      const char *Prefix = MAI.getLinkerWeakGlobalPrefix();
-      OutName.append(Prefix, Prefix+strlen(Prefix));
     }
 
     const char *Prefix = MAI.getGlobalPrefix();
@@ -185,8 +182,6 @@
     PrefixTy = Mangler::Private;
   else if (GV->hasLinkerPrivateLinkage())
     PrefixTy = Mangler::LinkerPrivate;
-  else if (GV->hasLinkerWeakLinkage())
-    PrefixTy = Mangler::LinkerWeak;
   
   // If this global has a name, handle it simply.
   if (GV->hasName()) {

Modified: llvm/trunk/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp?rev=107215&r1=107214&r2=107215&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp Tue Jun 29 17:34:52 2010
@@ -129,7 +129,6 @@
   case GlobalValue::WeakAnyLinkage:
   case GlobalValue::WeakODRLinkage:
   case GlobalValue::ExternalLinkage:
-  case GlobalValue::LinkerWeakLinkage:
     emitArrayBound(GVSym, GV);
     OutStreamer.EmitSymbolAttribute(GVSym, MCSA_Global);
 

Modified: llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp?rev=107215&r1=107214&r2=107215&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp (original)
+++ llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp Tue Jun 29 17:34:52 2010
@@ -535,7 +535,6 @@
   case GlobalValue::WeakAnyLinkage:
   case GlobalValue::WeakODRLinkage:
   case GlobalValue::ExternalWeakLinkage:
-  case GlobalValue::LinkerWeakLinkage:
     return ExternalWeak;
 
   case GlobalValue::ExternalLinkage:

Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=107215&r1=107214&r2=107215&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/AsmWriter.cpp (original)
+++ llvm/trunk/lib/VMCore/AsmWriter.cpp Tue Jun 29 17:34:52 2010
@@ -1419,7 +1419,6 @@
   case GlobalValue::ExternalLinkage: break;
   case GlobalValue::PrivateLinkage:       Out << "private ";        break;
   case GlobalValue::LinkerPrivateLinkage: Out << "linker_private "; break;
-  case GlobalValue::LinkerWeakLinkage:    Out << "linker_weak ";    break;
   case GlobalValue::InternalLinkage:      Out << "internal ";       break;
   case GlobalValue::LinkOnceAnyLinkage:   Out << "linkonce ";       break;
   case GlobalValue::LinkOnceODRLinkage:   Out << "linkonce_odr ";   break;

Modified: llvm/trunk/lib/VMCore/Core.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Core.cpp?rev=107215&r1=107214&r2=107215&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Core.cpp (original)
+++ llvm/trunk/lib/VMCore/Core.cpp Tue Jun 29 17:34:52 2010
@@ -1058,8 +1058,6 @@
     return LLVMPrivateLinkage;
   case GlobalValue::LinkerPrivateLinkage:
     return LLVMLinkerPrivateLinkage;
-  case GlobalValue::LinkerWeakLinkage:
-    return LLVMLinkerWeakLinkage;
   case GlobalValue::DLLImportLinkage:
     return LLVMDLLImportLinkage;
   case GlobalValue::DLLExportLinkage:
@@ -1110,9 +1108,6 @@
   case LLVMLinkerPrivateLinkage:
     GV->setLinkage(GlobalValue::LinkerPrivateLinkage);
     break;
-  case LLVMLinkerWeakLinkage:
-    GV->setLinkage(GlobalValue::LinkerWeakLinkage);
-    break;
   case LLVMDLLImportLinkage:
     GV->setLinkage(GlobalValue::DLLImportLinkage);
     break;

Modified: llvm/trunk/tools/llvm-nm/llvm-nm.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-nm/llvm-nm.cpp?rev=107215&r1=107214&r2=107215&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-nm/llvm-nm.cpp (original)
+++ llvm/trunk/tools/llvm-nm/llvm-nm.cpp Tue Jun 29 17:34:52 2010
@@ -89,8 +89,7 @@
 static void DumpSymbolNameForGlobalValue(GlobalValue &GV) {
   // Private linkage and available_externally linkage don't exist in symtab.
   if (GV.hasPrivateLinkage() || GV.hasLinkerPrivateLinkage() ||
-      GV.hasLinkerWeakLinkage() || GV.hasAvailableExternallyLinkage())
-    return;
+      GV.hasAvailableExternallyLinkage()) return;
   
   const std::string SymbolAddrStr = "        "; // Not used yet...
   char TypeChar = TypeCharForSymbol(GV);




From gohman at apple.com  Tue Jun 29 18:43:07 2010
From: gohman at apple.com (Dan Gohman)
Date: Tue, 29 Jun 2010 23:43:07 -0000
Subject: [llvm-commits] [llvm] r107224 - in /llvm/trunk:
 lib/Analysis/ScalarEvolution.cpp
 test/Transforms/IndVarSimplify/tripcount_compute.ll
Message-ID: <20100629234307.347B32A6C12C@llvm.org>

Author: djg
Date: Tue Jun 29 18:43:06 2010
New Revision: 107224

URL: http://llvm.org/viewvc/llvm-project?rev=107224&view=rev
Log:
Fix ScalarEvolution's tripcount computation for chains of loops
where each loop's induction variable's start value is the exit
value of a preceding loop.

Modified:
    llvm/trunk/lib/Analysis/ScalarEvolution.cpp
    llvm/trunk/test/Transforms/IndVarSimplify/tripcount_compute.ll

Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=107224&r1=107223&r2=107224&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Tue Jun 29 18:43:06 2010
@@ -4337,54 +4337,51 @@
       // the arguments into constants, and if so, try to constant propagate the
       // result.  This is particularly useful for computing loop exit values.
       if (CanConstantFold(I)) {
-        std::vector<Constant*> Operands;
-        Operands.reserve(I->getNumOperands());
+        SmallVector<Constant *, 4> Operands;
+        bool MadeImprovement = false;
         for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
           Value *Op = I->getOperand(i);
           if (Constant *C = dyn_cast<Constant>(Op)) {
             Operands.push_back(C);
-          } else {
-            // If any of the operands is non-constant and if they are
-            // non-integer and non-pointer, don't even try to analyze them
-            // with scev techniques.
-            if (!isSCEVable(Op->getType()))
-              return V;
-
-            const SCEV *OpV = getSCEVAtScope(Op, L);
-            if (const SCEVConstant *SC = dyn_cast<SCEVConstant>(OpV)) {
-              Constant *C = SC->getValue();
-              if (C->getType() != Op->getType())
-                C = ConstantExpr::getCast(CastInst::getCastOpcode(C, false,
-                                                                  Op->getType(),
-                                                                  false),
-                                          C, Op->getType());
-              Operands.push_back(C);
-            } else if (const SCEVUnknown *SU = dyn_cast<SCEVUnknown>(OpV)) {
-              if (Constant *C = dyn_cast<Constant>(SU->getValue())) {
-                if (C->getType() != Op->getType())
-                  C =
-                    ConstantExpr::getCast(CastInst::getCastOpcode(C, false,
-                                                                  Op->getType(),
-                                                                  false),
-                                          C, Op->getType());
-                Operands.push_back(C);
-              } else
-                return V;
-            } else {
-              return V;
-            }
+            continue;
           }
+
+          // If any of the operands is non-constant and if they are
+          // non-integer and non-pointer, don't even try to analyze them
+          // with scev techniques.
+          if (!isSCEVable(Op->getType()))
+            return V;
+
+          const SCEV *OrigV = getSCEV(Op);
+          const SCEV *OpV = getSCEVAtScope(OrigV, L);
+          MadeImprovement |= OrigV != OpV;
+
+          Constant *C = 0;
+          if (const SCEVConstant *SC = dyn_cast<SCEVConstant>(OpV))
+            C = SC->getValue();
+          if (const SCEVUnknown *SU = dyn_cast<SCEVUnknown>(OpV))
+            C = dyn_cast<Constant>(SU->getValue());
+          if (!C) return V;
+          if (C->getType() != Op->getType())
+            C = ConstantExpr::getCast(CastInst::getCastOpcode(C, false,
+                                                              Op->getType(),
+                                                              false),
+                                      C, Op->getType());
+          Operands.push_back(C);
         }
 
-        Constant *C = 0;
-        if (const CmpInst *CI = dyn_cast<CmpInst>(I))
-          C = ConstantFoldCompareInstOperands(CI->getPredicate(),
-                                              Operands[0], Operands[1], TD);
-        else
-          C = ConstantFoldInstOperands(I->getOpcode(), I->getType(),
-                                       &Operands[0], Operands.size(), TD);
-        if (C)
+        // Check to see if getSCEVAtScope actually made an improvement.
+        if (MadeImprovement) {
+          Constant *C = 0;
+          if (const CmpInst *CI = dyn_cast<CmpInst>(I))
+            C = ConstantFoldCompareInstOperands(CI->getPredicate(),
+                                                Operands[0], Operands[1], TD);
+          else
+            C = ConstantFoldInstOperands(I->getOpcode(), I->getType(),
+                                         &Operands[0], Operands.size(), TD);
+          if (!C) return V;
           return getSCEV(C);
+        }
       }
     }
 
@@ -4434,7 +4431,29 @@
   // If this is a loop recurrence for a loop that does not contain L, then we
   // are dealing with the final value computed by the loop.
   if (const SCEVAddRecExpr *AddRec = dyn_cast<SCEVAddRecExpr>(V)) {
-    if (!L || !AddRec->getLoop()->contains(L)) {
+    // First, attempt to evaluate each operand.
+    // Avoid performing the look-up in the common case where the specified
+    // expression has no loop-variant portions.
+    for (unsigned i = 0, e = AddRec->getNumOperands(); i != e; ++i) {
+      const SCEV *OpAtScope = getSCEVAtScope(AddRec->getOperand(i), L);
+      if (OpAtScope == AddRec->getOperand(i))
+        continue;
+
+      // Okay, at least one of these operands is loop variant but might be
+      // foldable.  Build a new instance of the folded commutative expression.
+      SmallVector<const SCEV *, 8> NewOps(AddRec->op_begin(),
+                                          AddRec->op_begin()+i);
+      NewOps.push_back(OpAtScope);
+      for (++i; i != e; ++i)
+        NewOps.push_back(getSCEVAtScope(AddRec->getOperand(i), L));
+
+      AddRec = cast<SCEVAddRecExpr>(getAddRecExpr(NewOps, AddRec->getLoop()));
+      break;
+    }
+
+    // If the scope is outside the addrec's loop, evaluate it by using the
+    // loop exit value of the addrec.
+    if (!AddRec->getLoop()->contains(L)) {
       // To evaluate this recurrence, we need to know how many times the AddRec
       // loop iterates.  Compute this now.
       const SCEV *BackedgeTakenCount = getBackedgeTakenCount(AddRec->getLoop());
@@ -4443,6 +4462,7 @@
       // Then, evaluate the AddRec.
       return AddRec->evaluateAtIteration(BackedgeTakenCount, *this);
     }
+
     return AddRec;
   }
 

Modified: llvm/trunk/test/Transforms/IndVarSimplify/tripcount_compute.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/tripcount_compute.ll?rev=107224&r1=107223&r2=107224&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/IndVarSimplify/tripcount_compute.ll (original)
+++ llvm/trunk/test/Transforms/IndVarSimplify/tripcount_compute.ll Tue Jun 29 18:43:06 2010
@@ -1,9 +1,12 @@
+; RUN: opt < %s -indvars -S | FileCheck %s
+
 ; These tests ensure that we can compute the trip count of various forms of
 ; loops.  If the trip count of the loop is computable, then we will know what
 ; the exit value of the loop will be for some value, allowing us to substitute
 ; it directly into users outside of the loop, making the loop dead.
-;
-; RUN: opt < %s -indvars -loop-deletion -simplifycfg -S | not grep br
+
+; CHECK: @linear_setne
+; CHECK: ret i32 100
 
 define i32 @linear_setne() {
 entry:
@@ -19,6 +22,9 @@
 	ret i32 %i
 }
 
+; CHECK: @linear_setne_2
+; CHECK: ret i32 100
+
 define i32 @linear_setne_2() {
 entry:
 	br label %loop
@@ -33,6 +39,9 @@
 	ret i32 %i
 }
 
+; CHECK: @linear_setne_overflow
+; CHECK: ret i32 0
+
 define i32 @linear_setne_overflow() {
 entry:
 	br label %loop
@@ -47,6 +56,9 @@
 	ret i32 %i
 }
 
+; CHECK: @linear_setlt
+; CHECK: ret i32 100
+
 define i32 @linear_setlt() {
 entry:
 	br label %loop
@@ -61,6 +73,9 @@
 	ret i32 %i
 }
 
+; CHECK: @quadratic_setlt
+; CHECK: ret i32 34
+
 define i32 @quadratic_setlt() {
 entry:
 	br label %loop
@@ -76,6 +91,9 @@
 	ret i32 %i
 }
 
+; CHECK: @chained
+; CHECK: ret i32 200
+
 define i32 @chained() {
 entry:
 	br label %loop
@@ -98,3 +116,47 @@
 loopexit2:		; preds = %loop2
 	ret i32 %j
 }
+
+; CHECK: @chained4
+; CHECK: ret i32 400
+
+define i32 @chained4() {
+entry:
+  br label %loop
+
+loop:                                             ; preds = %loop, %entry
+  %i = phi i32 [ 0, %entry ], [ %i.next, %loop ]  ; <i32> [#uses=3]
+  %i.next = add i32 %i, 1                         ; <i32> [#uses=1]
+  %c = icmp ne i32 %i.next, 100                   ; <i1> [#uses=1]
+  br i1 %c, label %loop, label %loopexit
+
+loopexit:                                         ; preds = %loop
+  br label %loop2
+
+loop2:                                            ; preds = %loop2, %loopexit
+  %j = phi i32 [ %i.next, %loopexit ], [ %j.next, %loop2 ] ; <i32> [#uses=3]
+  %j.next = add i32 %j, 1                         ; <i32> [#uses=1]
+  %c2 = icmp ne i32 %j.next, 200                  ; <i1> [#uses=1]
+  br i1 %c2, label %loop2, label %loopexit2
+
+loopexit2:                                        ; preds = %loop
+  br label %loop8
+
+loop8:                                            ; preds = %loop2, %loopexit
+  %k = phi i32 [ %j.next, %loopexit2 ], [ %k.next, %loop8 ] ; <i32> [#uses=3]
+  %k.next = add i32 %k, 1                         ; <i32> [#uses=1]
+  %c8 = icmp ne i32 %k.next, 300                  ; <i1> [#uses=1]
+  br i1 %c8, label %loop8, label %loopexit8
+
+loopexit8:                                        ; preds = %loop2
+  br label %loop9
+
+loop9:                                            ; preds = %loop2, %loopexit
+  %l = phi i32 [ %k.next, %loopexit8 ], [ %l.next, %loop9 ] ; <i32> [#uses=3]
+  %l.next = add i32 %l, 1                         ; <i32> [#uses=1]
+  %c9 = icmp ne i32 %l.next, 400                  ; <i1> [#uses=1]
+  br i1 %c9, label %loop9, label %loopexit9
+
+loopexit9:                                        ; preds = %loop2
+  ret i32 %l.next
+}




From bruno.cardoso at gmail.com  Tue Jun 29 18:47:49 2010
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Tue, 29 Jun 2010 23:47:49 -0000
Subject: [llvm-commits] [llvm] r107225 - in /llvm/trunk:
 lib/Target/X86/X86InstrSSE.td test/MC/AsmParser/X86/x86_32-encoding.s
 test/MC/AsmParser/X86/x86_64-encoding.s
Message-ID: <20100629234749.6EB1D2A6C12C@llvm.org>

Author: bruno
Date: Tue Jun 29 18:47:49 2010
New Revision: 107225

URL: http://llvm.org/viewvc/llvm-project?rev=107225&view=rev
Log:
Add *several* AVX integer packed binop instructions

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
    llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=107225&r1=107224&r2=107225&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Jun 29 18:47:49 2010
@@ -2258,48 +2258,62 @@
 
 let ExeDomain = SSEPackedInt in { // SSE integer instructions
 
-multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
+multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
+                            bit Is2Addr = 1> {
   def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
-                               (ins VR128:$src1, VR128:$src2),
-               !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
-               [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
+       (ins VR128:$src1, VR128:$src2),
+       !if(Is2Addr,
+           !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
+           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
+       [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
   def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
-                               (ins VR128:$src1, i128mem:$src2),
-               !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
-               [(set VR128:$dst, (IntId VR128:$src1,
-                                        (bitconvert (memopv2i64
-                                                     addr:$src2))))]>;
+       (ins VR128:$src1, i128mem:$src2),
+       !if(Is2Addr,
+           !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
+           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
+       [(set VR128:$dst, (IntId VR128:$src1,
+                                (bitconvert (memopv2i64 addr:$src2))))]>;
 }
 
 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
-                             string OpcodeStr,
-                             Intrinsic IntId, Intrinsic IntId2> {
+                             string OpcodeStr, Intrinsic IntId,
+                             Intrinsic IntId2, bit Is2Addr = 1> {
   def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
-                               (ins VR128:$src1, VR128:$src2),
-               !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
-               [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
+       (ins VR128:$src1, VR128:$src2),
+       !if(Is2Addr,
+           !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
+           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
+       [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
   def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
-                               (ins VR128:$src1, i128mem:$src2),
-               !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
-               [(set VR128:$dst, (IntId VR128:$src1,
+       (ins VR128:$src1, i128mem:$src2),
+       !if(Is2Addr,
+           !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
+           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
+       [(set VR128:$dst, (IntId VR128:$src1,
                                       (bitconvert (memopv2i64 addr:$src2))))]>;
   def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
-                                (ins VR128:$src1, i32i8imm:$src2),
-               !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
-               [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
+       (ins VR128:$src1, i32i8imm:$src2),
+       !if(Is2Addr,
+           !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
+           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
+       [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
 }
 
 /// PDI_binop_rm - Simple SSE2 binary operator.
 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
-                        ValueType OpVT> {
+                        ValueType OpVT, bit Is2Addr = 1> {
   def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
-                               (ins VR128:$src1, VR128:$src2),
-               !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
-               [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>;
+       (ins VR128:$src1, VR128:$src2),
+       !if(Is2Addr,
+           !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
+           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
+       [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>;
   def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
-                               (ins VR128:$src1, i128mem:$src2),
-               !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
-               [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
+       (ins VR128:$src1, i128mem:$src2),
+       !if(Is2Addr,
+           !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
+           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
+       [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
                                      (bitconvert (memopv2i64 addr:$src2)))))]>;
 }
 
@@ -2308,22 +2322,82 @@
 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
 /// to collapse (bitconvert VT to VT) into its operand.
 ///
-multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode> {
+multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
+                              bit Is2Addr = 1> {
   def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
-               (ins VR128:$src1, VR128:$src2),
-               !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
-               [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]>;
+       (ins VR128:$src1, VR128:$src2),
+       !if(Is2Addr,
+           !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
+           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
+       [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]>;
   def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
-               (ins VR128:$src1, i128mem:$src2),
-               !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
-               [(set VR128:$dst, (OpNode VR128:$src1,
-               (memopv2i64 addr:$src2)))]>;
+       (ins VR128:$src1, i128mem:$src2),
+       !if(Is2Addr,
+           !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
+           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
+       [(set VR128:$dst, (OpNode VR128:$src1, (memopv2i64 addr:$src2)))]>;
 }
 
 } // ExeDomain = SSEPackedInt
 
 // 128-bit Integer Arithmetic
 
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE2] in {
+let isCommutable = 1 in {
+defm VPADDB  : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, 0 /* 3 addr */>, VEX_4V;
+defm VPADDW  : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, 0>, VEX_4V;
+defm VPADDD  : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, 0>, VEX_4V;
+defm VPADDQ  : PDI_binop_rm_v2i64<0xD4, "vpaddq", add, 0>, VEX_4V;
+defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, 0>, VEX_4V;
+}
+defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, 0>, VEX_4V;
+defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, 0>, VEX_4V;
+defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, 0>, VEX_4V;
+defm VPSUBQ : PDI_binop_rm_v2i64<0xFB, "vpsubq", sub, 0>, VEX_4V;
+
+// Intrinsic forms
+defm VPSUBSB  : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b, 0>,
+                                 VEX_4V;
+defm VPSUBSW  : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w, 0>,
+                                 VEX_4V;
+defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b, 0>,
+                                 VEX_4V;
+defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w, 0>,
+                                 VEX_4V;
+let isCommutable = 1 in {
+defm VPADDSB  : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b, 0>,
+                                 VEX_4V;
+defm VPADDSW  : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w, 0>,
+                                 VEX_4V;
+defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b, 0>,
+                                 VEX_4V;
+defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w, 0>,
+                                 VEX_4V;
+defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w, 0>,
+                                 VEX_4V;
+defm VPMULHW  : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w, 0>,
+                                 VEX_4V;
+defm VPMULUDQ : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_sse2_pmulu_dq, 0>,
+                                 VEX_4V;
+defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd, 0>,
+                                 VEX_4V;
+defm VPAVGB   : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b, 0>,
+                                 VEX_4V;
+defm VPAVGW   : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w, 0>,
+                                 VEX_4V;
+defm VPMINUB  : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b, 0>,
+                                 VEX_4V;
+defm VPMINSW  : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w, 0>,
+                                 VEX_4V;
+defm VPMAXUB  : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b, 0>,
+                                 VEX_4V;
+defm VPMAXSW  : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w, 0>,
+                                 VEX_4V;
+defm VPSADBW  : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw, 0>,
+                                 VEX_4V;
+}
+}
+
 let Constraints = "$src1 = $dst" in {
 let isCommutable = 1 in {
 defm PADDB  : PDI_binop_rm<0xFC, "paddb", add, v16i8>;

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s?rev=107225&r1=107224&r2=107225&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s Tue Jun 29 18:47:49 2010
@@ -10966,3 +10966,219 @@
 // CHECK: encoding: [0xc5,0xf8,0xae,0x1d,0xef,0xbe,0xad,0xde]
           vstmxcsr  0xdeadbeef
 
+// CHECK: vpsubb  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xf8,0xd9]
+          vpsubb  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpsubb  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xf8,0x18]
+          vpsubb  (%eax), %xmm2, %xmm3
+
+// CHECK: vpsubw  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xf9,0xd9]
+          vpsubw  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpsubw  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xf9,0x18]
+          vpsubw  (%eax), %xmm2, %xmm3
+
+// CHECK: vpsubd  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xfa,0xd9]
+          vpsubd  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpsubd  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xfa,0x18]
+          vpsubd  (%eax), %xmm2, %xmm3
+
+// CHECK: vpsubq  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xfb,0xd9]
+          vpsubq  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpsubq  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xfb,0x18]
+          vpsubq  (%eax), %xmm2, %xmm3
+
+// CHECK: vpsubsb  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xe8,0xd9]
+          vpsubsb  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpsubsb  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xe8,0x18]
+          vpsubsb  (%eax), %xmm2, %xmm3
+
+// CHECK: vpsubsw  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xe9,0xd9]
+          vpsubsw  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpsubsw  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xe9,0x18]
+          vpsubsw  (%eax), %xmm2, %xmm3
+
+// CHECK: vpsubusb  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xd8,0xd9]
+          vpsubusb  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpsubusb  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xd8,0x18]
+          vpsubusb  (%eax), %xmm2, %xmm3
+
+// CHECK: vpsubusw  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xd9,0xd9]
+          vpsubusw  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpsubusw  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xd9,0x18]
+          vpsubusw  (%eax), %xmm2, %xmm3
+
+// CHECK: vpaddb  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xfc,0xd9]
+          vpaddb  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpaddb  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xfc,0x18]
+          vpaddb  (%eax), %xmm2, %xmm3
+
+// CHECK: vpaddw  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xfd,0xd9]
+          vpaddw  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpaddw  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xfd,0x18]
+          vpaddw  (%eax), %xmm2, %xmm3
+
+// CHECK: vpaddd  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xfe,0xd9]
+          vpaddd  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpaddd  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xfe,0x18]
+          vpaddd  (%eax), %xmm2, %xmm3
+
+// CHECK: vpaddq  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xd4,0xd9]
+          vpaddq  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpaddq  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xd4,0x18]
+          vpaddq  (%eax), %xmm2, %xmm3
+
+// CHECK: vpaddsb  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xec,0xd9]
+          vpaddsb  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpaddsb  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xec,0x18]
+          vpaddsb  (%eax), %xmm2, %xmm3
+
+// CHECK: vpaddsw  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xed,0xd9]
+          vpaddsw  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpaddsw  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xed,0x18]
+          vpaddsw  (%eax), %xmm2, %xmm3
+
+// CHECK: vpaddusb  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xdc,0xd9]
+          vpaddusb  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpaddusb  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xdc,0x18]
+          vpaddusb  (%eax), %xmm2, %xmm3
+
+// CHECK: vpaddusw  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xdd,0xd9]
+          vpaddusw  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpaddusw  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xdd,0x18]
+          vpaddusw  (%eax), %xmm2, %xmm3
+
+// CHECK: vpmulhuw  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xe4,0xd9]
+          vpmulhuw  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpmulhuw  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xe4,0x18]
+          vpmulhuw  (%eax), %xmm2, %xmm3
+
+// CHECK: vpmulhw  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xe5,0xd9]
+          vpmulhw  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpmulhw  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xe5,0x18]
+          vpmulhw  (%eax), %xmm2, %xmm3
+
+// CHECK: vpmullw  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xd5,0xd9]
+          vpmullw  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpmullw  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xd5,0x18]
+          vpmullw  (%eax), %xmm2, %xmm3
+
+// CHECK: vpmuludq  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xf4,0xd9]
+          vpmuludq  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpmuludq  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xf4,0x18]
+          vpmuludq  (%eax), %xmm2, %xmm3
+
+// CHECK: vpavgb  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xe0,0xd9]
+          vpavgb  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpavgb  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xe0,0x18]
+          vpavgb  (%eax), %xmm2, %xmm3
+
+// CHECK: vpavgw  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xe3,0xd9]
+          vpavgw  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpavgw  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xe3,0x18]
+          vpavgw  (%eax), %xmm2, %xmm3
+
+// CHECK: vpminsw  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xea,0xd9]
+          vpminsw  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpminsw  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xea,0x18]
+          vpminsw  (%eax), %xmm2, %xmm3
+
+// CHECK: vpminub  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xda,0xd9]
+          vpminub  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpminub  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xda,0x18]
+          vpminub  (%eax), %xmm2, %xmm3
+
+// CHECK: vpmaxsw  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xee,0xd9]
+          vpmaxsw  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpmaxsw  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xee,0x18]
+          vpmaxsw  (%eax), %xmm2, %xmm3
+
+// CHECK: vpmaxub  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xde,0xd9]
+          vpmaxub  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpmaxub  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xde,0x18]
+          vpmaxub  (%eax), %xmm2, %xmm3
+
+// CHECK: vpsadbw  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xf6,0xd9]
+          vpsadbw  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpsadbw  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xf6,0x18]
+          vpsadbw  (%eax), %xmm2, %xmm3
+

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s?rev=107225&r1=107224&r2=107225&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s Tue Jun 29 18:47:49 2010
@@ -1006,3 +1006,219 @@
 // CHECK: encoding: [0xc5,0xf8,0xae,0x5c,0x24,0xfc]
           vstmxcsr  -4(%rsp)
 
+// CHECK: vpsubb  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0xf8,0xeb]
+          vpsubb  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpsubb  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0xf8,0x28]
+          vpsubb  (%rax), %xmm12, %xmm13
+
+// CHECK: vpsubw  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0xf9,0xeb]
+          vpsubw  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpsubw  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0xf9,0x28]
+          vpsubw  (%rax), %xmm12, %xmm13
+
+// CHECK: vpsubd  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0xfa,0xeb]
+          vpsubd  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpsubd  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0xfa,0x28]
+          vpsubd  (%rax), %xmm12, %xmm13
+
+// CHECK: vpsubq  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0xfb,0xeb]
+          vpsubq  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpsubq  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0xfb,0x28]
+          vpsubq  (%rax), %xmm12, %xmm13
+
+// CHECK: vpsubsb  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0xe8,0xeb]
+          vpsubsb  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpsubsb  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0xe8,0x28]
+          vpsubsb  (%rax), %xmm12, %xmm13
+
+// CHECK: vpsubsw  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0xe9,0xeb]
+          vpsubsw  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpsubsw  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0xe9,0x28]
+          vpsubsw  (%rax), %xmm12, %xmm13
+
+// CHECK: vpsubusb  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0xd8,0xeb]
+          vpsubusb  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpsubusb  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0xd8,0x28]
+          vpsubusb  (%rax), %xmm12, %xmm13
+
+// CHECK: vpsubusw  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0xd9,0xeb]
+          vpsubusw  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpsubusw  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0xd9,0x28]
+          vpsubusw  (%rax), %xmm12, %xmm13
+
+// CHECK: vpaddb  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0xfc,0xeb]
+          vpaddb  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpaddb  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0xfc,0x28]
+          vpaddb  (%rax), %xmm12, %xmm13
+
+// CHECK: vpaddw  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0xfd,0xeb]
+          vpaddw  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpaddw  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0xfd,0x28]
+          vpaddw  (%rax), %xmm12, %xmm13
+
+// CHECK: vpaddd  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0xfe,0xeb]
+          vpaddd  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpaddd  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0xfe,0x28]
+          vpaddd  (%rax), %xmm12, %xmm13
+
+// CHECK: vpaddq  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0xd4,0xeb]
+          vpaddq  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpaddq  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0xd4,0x28]
+          vpaddq  (%rax), %xmm12, %xmm13
+
+// CHECK: vpaddsb  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0xec,0xeb]
+          vpaddsb  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpaddsb  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0xec,0x28]
+          vpaddsb  (%rax), %xmm12, %xmm13
+
+// CHECK: vpaddsw  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0xed,0xeb]
+          vpaddsw  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpaddsw  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0xed,0x28]
+          vpaddsw  (%rax), %xmm12, %xmm13
+
+// CHECK: vpaddusb  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0xdc,0xeb]
+          vpaddusb  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpaddusb  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0xdc,0x28]
+          vpaddusb  (%rax), %xmm12, %xmm13
+
+// CHECK: vpaddusw  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0xdd,0xeb]
+          vpaddusw  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpaddusw  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0xdd,0x28]
+          vpaddusw  (%rax), %xmm12, %xmm13
+
+// CHECK: vpmulhuw  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0xe4,0xeb]
+          vpmulhuw  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpmulhuw  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0xe4,0x28]
+          vpmulhuw  (%rax), %xmm12, %xmm13
+
+// CHECK: vpmulhw  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0xe5,0xeb]
+          vpmulhw  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpmulhw  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0xe5,0x28]
+          vpmulhw  (%rax), %xmm12, %xmm13
+
+// CHECK: vpmullw  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0xd5,0xeb]
+          vpmullw  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpmullw  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0xd5,0x28]
+          vpmullw  (%rax), %xmm12, %xmm13
+
+// CHECK: vpmuludq  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0xf4,0xeb]
+          vpmuludq  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpmuludq  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0xf4,0x28]
+          vpmuludq  (%rax), %xmm12, %xmm13
+
+// CHECK: vpavgb  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0xe0,0xeb]
+          vpavgb  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpavgb  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0xe0,0x28]
+          vpavgb  (%rax), %xmm12, %xmm13
+
+// CHECK: vpavgw  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0xe3,0xeb]
+          vpavgw  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpavgw  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0xe3,0x28]
+          vpavgw  (%rax), %xmm12, %xmm13
+
+// CHECK: vpminsw  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0xea,0xeb]
+          vpminsw  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpminsw  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0xea,0x28]
+          vpminsw  (%rax), %xmm12, %xmm13
+
+// CHECK: vpminub  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0xda,0xeb]
+          vpminub  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpminub  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0xda,0x28]
+          vpminub  (%rax), %xmm12, %xmm13
+
+// CHECK: vpmaxsw  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0xee,0xeb]
+          vpmaxsw  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpmaxsw  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0xee,0x28]
+          vpmaxsw  (%rax), %xmm12, %xmm13
+
+// CHECK: vpmaxub  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0xde,0xeb]
+          vpmaxub  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpmaxub  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0xde,0x28]
+          vpmaxub  (%rax), %xmm12, %xmm13
+
+// CHECK: vpsadbw  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0xf6,0xeb]
+          vpsadbw  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpsadbw  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0xf6,0x28]
+          vpsadbw  (%rax), %xmm12, %xmm13
+




From stoklund at 2pi.dk  Tue Jun 29 18:58:39 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 29 Jun 2010 23:58:39 -0000
Subject: [llvm-commits] [llvm] r107227 - in /llvm/trunk:
 include/llvm/CodeGen/MachineRegisterInfo.h lib/CodeGen/CMakeLists.txt
 lib/CodeGen/InlineSpiller.cpp lib/CodeGen/Spiller.cpp
Message-ID: <20100629235839.983DB2A6C12C@llvm.org>

Author: stoklund
Date: Tue Jun 29 18:58:39 2010
New Revision: 107227

URL: http://llvm.org/viewvc/llvm-project?rev=107227&view=rev
Log:
Begin implementation of an inline spiller.

InlineSpiller inserts loads and spills immediately instead of deferring to
VirtRegMap. This is possible now because SlotIndexes allows instructions to be
inserted and renumbered.

This is work in progress, and is mostly a copy of TrivialSpiller so far. It
works very well for functions that don't require spilling.

Added:
    llvm/trunk/lib/CodeGen/InlineSpiller.cpp
Modified:
    llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h
    llvm/trunk/lib/CodeGen/CMakeLists.txt
    llvm/trunk/lib/CodeGen/Spiller.cpp

Modified: llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h?rev=107227&r1=107226&r2=107227&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h Tue Jun 29 18:58:39 2010
@@ -363,7 +363,18 @@
     defusechain_iterator operator++(int) {        // Postincrement
       defusechain_iterator tmp = *this; ++*this; return tmp;
     }
-    
+
+    /// skipInstruction - move forward until reaching a different instruction.
+    /// Return the skipped instruction that is no longer pointed to, or NULL if
+    /// already pointing to end().
+    MachineInstr *skipInstruction() {
+      if (!Op) return 0;
+      MachineInstr *MI = Op->getParent();
+      do ++*this;
+      while (Op && Op->getParent() == MI);
+      return MI;
+    }
+
     MachineOperand &getOperand() const {
       assert(Op && "Cannot dereference end iterator!");
       return *Op;

Modified: llvm/trunk/lib/CodeGen/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CMakeLists.txt?rev=107227&r1=107226&r2=107227&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/CMakeLists.txt (original)
+++ llvm/trunk/lib/CodeGen/CMakeLists.txt Tue Jun 29 18:58:39 2010
@@ -13,6 +13,7 @@
   GCMetadataPrinter.cpp
   GCStrategy.cpp
   IfConversion.cpp
+  InlineSpiller.cpp
   IntrinsicLowering.cpp
   LLVMTargetMachine.cpp
   LatencyPriorityQueue.cpp

Added: llvm/trunk/lib/CodeGen/InlineSpiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/InlineSpiller.cpp?rev=107227&view=auto
==============================================================================
--- llvm/trunk/lib/CodeGen/InlineSpiller.cpp (added)
+++ llvm/trunk/lib/CodeGen/InlineSpiller.cpp Tue Jun 29 18:58:39 2010
@@ -0,0 +1,136 @@
+//===-------- InlineSpiller.cpp - Insert spills and restores inline -------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// The inline spiller modifies the machine function directly instead of
+// inserting spills and restores in VirtRegMap.
+//
+//===----------------------------------------------------------------------===//
+
+#define DEBUG_TYPE "spiller"
+#include "Spiller.h"
+#include "VirtRegMap.h"
+#include "llvm/CodeGen/LiveIntervalAnalysis.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
+
+using namespace llvm;
+
+namespace {
+class InlineSpiller : public Spiller {
+  MachineFunction &mf_;
+  LiveIntervals &lis_;
+  VirtRegMap &vrm_;
+  MachineFrameInfo &mfi_;
+  MachineRegisterInfo &mri_;
+  const TargetInstrInfo &tii_;
+  const TargetRegisterInfo &tri_;
+
+  ~InlineSpiller() {}
+
+public:
+  InlineSpiller(MachineFunction *mf, LiveIntervals *lis, VirtRegMap *vrm)
+    : mf_(*mf), lis_(*lis), vrm_(*vrm),
+      mfi_(*mf->getFrameInfo()),
+      mri_(mf->getRegInfo()),
+      tii_(*mf->getTarget().getInstrInfo()),
+      tri_(*mf->getTarget().getRegisterInfo()) {}
+
+  void spill(LiveInterval *li,
+             std::vector<LiveInterval*> &newIntervals,
+             SmallVectorImpl<LiveInterval*> &spillIs,
+             SlotIndex *earliestIndex);
+};
+}
+
+namespace llvm {
+Spiller *createInlineSpiller(MachineFunction *mf,
+                             LiveIntervals *lis,
+                             const MachineLoopInfo *mli,
+                             VirtRegMap *vrm) {
+  return new InlineSpiller(mf, lis, vrm);
+}
+}
+
+void InlineSpiller::spill(LiveInterval *li,
+                          std::vector<LiveInterval*> &newIntervals,
+                          SmallVectorImpl<LiveInterval*> &spillIs,
+                          SlotIndex *earliestIndex) {
+  DEBUG(dbgs() << "Inline spilling " << *li << "\n");
+  assert(li->isSpillable() && "Attempting to spill already spilled value.");
+  assert(!li->isStackSlot() && "Trying to spill a stack slot.");
+
+  const TargetRegisterClass *RC = mri_.getRegClass(li->reg);
+  unsigned SS = vrm_.assignVirt2StackSlot(li->reg);
+
+  for (MachineRegisterInfo::reg_iterator RI = mri_.reg_begin(li->reg);
+       MachineInstr *MI = RI.skipInstruction();) {
+    SlotIndex Idx = lis_.getInstructionIndex(MI).getDefIndex();
+
+    // Analyze instruction.
+    bool Reads, Writes;
+    SmallVector<unsigned, 8> Ops;
+    tie(Reads, Writes) = MI->readsWritesVirtualRegister(li->reg, &Ops);
+
+    // Allocate interval around instruction.
+    // FIXME: Infer regclass from instruction alone.
+    unsigned NewVReg = mri_.createVirtualRegister(RC);
+    vrm_.grow();
+    LiveInterval &NewLI = lis_.getOrCreateInterval(NewVReg);
+    NewLI.markNotSpillable();
+
+    // Reload if instruction reads register.
+    if (Reads) {
+      MachineBasicBlock::iterator MII = MI;
+      tii_.loadRegFromStackSlot(*MI->getParent(), MII, NewVReg, SS, RC, &tri_);
+      --MII; // Point to load instruction.
+      SlotIndex LoadIdx = lis_.InsertMachineInstrInMaps(MII).getDefIndex();
+      DEBUG(dbgs() << "\treload:  " << LoadIdx << '\t' << *MII);
+      VNInfo *LoadVNI = NewLI.getNextValue(LoadIdx, 0, true,
+                                           lis_.getVNInfoAllocator());
+      NewLI.addRange(LiveRange(LoadIdx, Idx, LoadVNI));
+    }
+
+    // Rewrite instruction operands.
+    bool hasLiveDef = false;
+    for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
+      MachineOperand &MO = MI->getOperand(Ops[i]);
+      MO.setReg(NewVReg);
+      if (MO.isUse()) {
+        if (!MI->isRegTiedToDefOperand(Ops[i]))
+          MO.setIsKill();
+      } else {
+        if (!MO.isDead())
+          hasLiveDef = true;
+      }
+    }
+    DEBUG(dbgs() << "\trewrite: " << Idx << '\t' << *MI);
+
+    // Spill is instruction writes register.
+    // FIXME: Use a second vreg if instruction has no tied ops.
+    if (Writes && hasLiveDef) {
+      MachineBasicBlock::iterator MII = MI;
+      tii_.storeRegToStackSlot(*MI->getParent(), ++MII, NewVReg, true, SS, RC,
+                               &tri_);
+      --MII; // Point to store instruction.
+      SlotIndex StoreIdx = lis_.InsertMachineInstrInMaps(MII).getDefIndex();
+      DEBUG(dbgs() << "\tspilled: " << StoreIdx << '\t' << *MII);
+      VNInfo *StoreVNI = NewLI.getNextValue(Idx, 0, true,
+                                            lis_.getVNInfoAllocator());
+      NewLI.addRange(LiveRange(Idx, StoreIdx, StoreVNI));
+    }
+
+    DEBUG(dbgs() << "\tinterval: " << NewLI << '\n');
+    newIntervals.push_back(&NewLI);
+  }
+}

Modified: llvm/trunk/lib/CodeGen/Spiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Spiller.cpp?rev=107227&r1=107226&r2=107227&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/Spiller.cpp (original)
+++ llvm/trunk/lib/CodeGen/Spiller.cpp Tue Jun 29 18:58:39 2010
@@ -26,7 +26,7 @@
 using namespace llvm;
 
 namespace {
-  enum SpillerName { trivial, standard, splitting };
+  enum SpillerName { trivial, standard, splitting, inline_ };
 }
 
 static cl::opt<SpillerName>
@@ -36,6 +36,7 @@
            cl::values(clEnumVal(trivial,   "trivial spiller"),
                       clEnumVal(standard,  "default spiller"),
                       clEnumVal(splitting, "splitting spiller"),
+                      "inline", inline_,   "inline spiller",
                       clEnumValEnd),
            cl::init(standard));
 
@@ -506,6 +507,13 @@
 } // end anonymous namespace
 
 
+namespace llvm {
+Spiller *createInlineSpiller(MachineFunction*,
+                             LiveIntervals*,
+                             const MachineLoopInfo*,
+                             VirtRegMap*);
+}
+
 llvm::Spiller* llvm::createSpiller(MachineFunction *mf, LiveIntervals *lis,
                                    const MachineLoopInfo *loopInfo,
                                    VirtRegMap *vrm) {
@@ -514,5 +522,6 @@
   case trivial: return new TrivialSpiller(mf, lis, vrm);
   case standard: return new StandardSpiller(lis, loopInfo, vrm);
   case splitting: return new SplittingSpiller(mf, lis, loopInfo, vrm);
+  case inline_: return createInlineSpiller(mf, lis, loopInfo, vrm);
   }
 }




From dpatel at apple.com  Tue Jun 29 19:11:08 2010
From: dpatel at apple.com (Devang Patel)
Date: Wed, 30 Jun 2010 00:11:08 -0000
Subject: [llvm-commits] [llvm] r107228 - in /llvm/trunk:
 lib/CodeGen/AsmPrinter/DwarfDebug.cpp
 test/DebugInfo/2010-06-29-InlinedFnLocalVar.ll
Message-ID: <20100630001108.A98752A6C12C@llvm.org>

Author: dpatel
Date: Tue Jun 29 19:11:08 2010
New Revision: 107228

URL: http://llvm.org/viewvc/llvm-project?rev=107228&view=rev
Log:
Add variables into a scope before constructing scope DIE otherwise variables won't be included DIE tree. 

Added:
    llvm/trunk/test/DebugInfo/2010-06-29-InlinedFnLocalVar.ll
Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=107228&r1=107227&r2=107228&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Tue Jun 29 19:11:08 2010
@@ -2746,7 +2746,6 @@
     // Construct abstract scopes.
     for (SmallVector<DbgScope *, 4>::iterator AI = AbstractScopesList.begin(),
            AE = AbstractScopesList.end(); AI != AE; ++AI) {
-      constructScopeDIE(*AI);
       DISubprogram SP((*AI)->getScopeNode());
       if (SP.Verify()) {
         // Collect info for variables that were optimized out.
@@ -2761,12 +2760,13 @@
           DIVariable DV(cast_or_null<MDNode>(NMD->getOperand(i)));
           if (!DV || !ProcessedVars.insert(DV))
             continue;
-          DbgScope *Scope = DbgScopeMap.lookup(DV.getContext());
+          DbgScope *Scope = AbstractScopes.lookup(DV.getContext());
           if (Scope)
             Scope->addVariable(new DbgVariable(DV));
           }
         }
       }
+      constructScopeDIE(*AI);
     }
     
     DIE *CurFnDIE = constructScopeDIE(CurrentFnDbgScope);

Added: llvm/trunk/test/DebugInfo/2010-06-29-InlinedFnLocalVar.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/2010-06-29-InlinedFnLocalVar.ll?rev=107228&view=auto
==============================================================================
--- llvm/trunk/test/DebugInfo/2010-06-29-InlinedFnLocalVar.ll (added)
+++ llvm/trunk/test/DebugInfo/2010-06-29-InlinedFnLocalVar.ll Tue Jun 29 19:11:08 2010
@@ -0,0 +1,52 @@
+; RUN: llc -O2 %s -o - | FileCheck %s
+; Check struct X for dead variable xyz from inlined function foo.
+
+; CHECK:	DW_TAG_structure_type
+; CHECK-NEXT:	DW_AT_sibling
+; CHECK-NEXT:	DW_AT_name
+ 
+
+ at i = common global i32 0                          ; <i32*> [#uses=2]
+
+declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
+
+declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
+
+define i32 @bar() nounwind ssp {
+entry:
+  %0 = load i32* @i, align 4, !dbg !17            ; <i32> [#uses=2]
+  tail call void @llvm.dbg.value(metadata !{i32 %0}, i64 0, metadata !9), !dbg !19
+  tail call void @llvm.dbg.declare(metadata !20, metadata !10), !dbg !21
+  %1 = mul nsw i32 %0, %0, !dbg !22               ; <i32> [#uses=2]
+  store i32 %1, i32* @i, align 4, !dbg !17
+  ret i32 %1, !dbg !23
+}
+
+!llvm.dbg.sp = !{!0, !6}
+!llvm.dbg.lv.foo = !{!9, !10}
+!llvm.dbg.gv = !{!16}
+
+!0 = metadata !{i32 524334, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"", metadata !1, i32 9, metadata !3, i1 true, i1 true, i32 0, i32 0, null, i1 false, i1 true, null} ; [ DW_TAG_subprogram ]
+!1 = metadata !{i32 524329, metadata !"bar.c", metadata !"/tmp/", metadata !2} ; [ DW_TAG_file_type ]
+!2 = metadata !{i32 524305, i32 0, i32 1, metadata !"bar.c", metadata !"/tmp/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
+!3 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!4 = metadata !{metadata !5, metadata !5}
+!5 = metadata !{i32 524324, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!6 = metadata !{i32 524334, i32 0, metadata !1, metadata !"bar", metadata !"bar", metadata !"bar", metadata !1, i32 14, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, i32 ()* @bar} ; [ DW_TAG_subprogram ]
+!7 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!8 = metadata !{metadata !5}
+!9 = metadata !{i32 524545, metadata !0, metadata !"j", metadata !1, i32 9, metadata !5} ; [ DW_TAG_arg_variable ]
+!10 = metadata !{i32 524544, metadata !11, metadata !"xyz", metadata !1, i32 10, metadata !12} ; [ DW_TAG_auto_variable ]
+!11 = metadata !{i32 524299, metadata !0, i32 9, i32 0} ; [ DW_TAG_lexical_block ]
+!12 = metadata !{i32 524307, metadata !0, metadata !"X", metadata !1, i32 10, i64 64, i64 32, i64 0, i32 0, null, metadata !13, i32 0, null} ; [ DW_TAG_structure_type ]
+!13 = metadata !{metadata !14, metadata !15}
+!14 = metadata !{i32 524301, metadata !12, metadata !"a", metadata !1, i32 10, i64 32, i64 32, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ]
+!15 = metadata !{i32 524301, metadata !12, metadata !"b", metadata !1, i32 10, i64 32, i64 32, i64 32, i32 0, metadata !5} ; [ DW_TAG_member ]
+!16 = metadata !{i32 524340, i32 0, metadata !1, metadata !"i", metadata !"i", metadata !"", metadata !1, i32 5, metadata !5, i1 false, i1 true, i32* @i} ; [ DW_TAG_variable ]
+!17 = metadata !{i32 15, i32 0, metadata !18, null}
+!18 = metadata !{i32 524299, metadata !6, i32 14, i32 0} ; [ DW_TAG_lexical_block ]
+!19 = metadata !{i32 9, i32 0, metadata !0, metadata !17}
+!20 = metadata !{null}
+!21 = metadata !{i32 9, i32 0, metadata !11, metadata !17}
+!22 = metadata !{i32 11, i32 0, metadata !11, metadata !17}
+!23 = metadata !{i32 16, i32 0, metadata !18, null}




From stoklund at 2pi.dk  Tue Jun 29 19:24:51 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Wed, 30 Jun 2010 00:24:51 -0000
Subject: [llvm-commits] [llvm] r107233 - /llvm/trunk/lib/CodeGen/Spiller.cpp
Message-ID: <20100630002451.AE2692A6C12C@llvm.org>

Author: stoklund
Date: Tue Jun 29 19:24:51 2010
New Revision: 107233

URL: http://llvm.org/viewvc/llvm-project?rev=107233&view=rev
Log:
Use clEnumValN macro to work around keyword clash

Modified:
    llvm/trunk/lib/CodeGen/Spiller.cpp

Modified: llvm/trunk/lib/CodeGen/Spiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Spiller.cpp?rev=107233&r1=107232&r2=107233&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/Spiller.cpp (original)
+++ llvm/trunk/lib/CodeGen/Spiller.cpp Tue Jun 29 19:24:51 2010
@@ -36,7 +36,7 @@
            cl::values(clEnumVal(trivial,   "trivial spiller"),
                       clEnumVal(standard,  "default spiller"),
                       clEnumVal(splitting, "splitting spiller"),
-                      "inline", inline_,   "inline spiller",
+                      clEnumValN(inline_,  "inline", "inline spiller"),
                       clEnumValEnd),
            cl::init(standard));
 




From stoklund at 2pi.dk  Tue Jun 29 19:30:36 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Wed, 30 Jun 2010 00:30:36 -0000
Subject: [llvm-commits] [llvm] r107234 -
	/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
Message-ID: <20100630003036.A97C42A6C12C@llvm.org>

Author: stoklund
Date: Tue Jun 29 19:30:36 2010
New Revision: 107234

URL: http://llvm.org/viewvc/llvm-project?rev=107234&view=rev
Log:
Use skipInstruction() as a simpler way of iterating over instructions using SrcReg

Modified:
    llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp

Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=107234&r1=107233&r2=107234&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
+++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Tue Jun 29 19:30:36 2010
@@ -742,16 +742,8 @@
   unsigned DstReg = CP.getDstReg();
   unsigned SubIdx = CP.getSubIdx();
 
-  // Collect all the instructions using SrcReg.
-  SmallPtrSet<MachineInstr*, 32> Instrs;
-  for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg),
-         E = mri_->reg_end(); I != E; ++I)
-    Instrs.insert(&*I);
-
-  for (SmallPtrSet<MachineInstr*, 32>::const_iterator I = Instrs.begin(),
-       E = Instrs.end(); I != E; ++I) {
-    MachineInstr *UseMI = *I;
-
+  for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg);
+       MachineInstr *UseMI = I.skipInstruction();) {
     // A PhysReg copy that won't be coalesced can perhaps be rematerialized
     // instead.
     if (DstIsPhys) {




From evan.cheng at apple.com  Tue Jun 29 20:03:54 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 29 Jun 2010 18:03:54 -0700
Subject: [llvm-commits] [llvm] r107114 -
	/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
In-Reply-To: <58535D1C-837D-4136-A1D6-9809389E70F3@2pi.dk>
References: <20100629011307.645212A6C12C@llvm.org>
	<04D10EF1-91D9-44D6-9161-161B70493ED7@apple.com>
	<5F342D90-DC02-47A6-A825-EAD20CBFA547@2pi.dk>
	<0BC7E25D-4488-4954-A149-0D27BF55BBAE@apple.com>
	<58535D1C-837D-4136-A1D6-9809389E70F3@2pi.dk>
Message-ID: <0F336F91-F80B-425F-B3AD-DCFAB44E6F16@apple.com>


On Jun 29, 2010, at 1:39 PM, Jakob Stoklund Olesen wrote:

> 
> On Jun 28, 2010, at 10:46 PM, Evan Cheng wrote:
> 
>> 
>> On Jun 28, 2010, at 10:09 PM, Jakob Stoklund Olesen wrote:
>> 
>>> 
>>> On Jun 28, 2010, at 10:00 PM, Evan Cheng wrote:
>>> 
>>>> 
>>>> On Jun 28, 2010, at 6:13 PM, Jakob Stoklund Olesen wrote:
>>>> 
>>>>> Author: stoklund
>>>>> Date: Mon Jun 28 20:13:07 2010
>>>>> New Revision: 107114
>>>>> 
>>>>> URL: http://llvm.org/viewvc/llvm-project?rev=107114&view=rev
>>>>> Log:
>>>>> When no memoperands are present, assume unaligned, volatile.
>>>> 
>>>> Have you checked if this disabled a lot of potential optimizations? I am afraid assuming volatileness is overly conservative.
>>> 
>>> I haven't checked anything but running unit tests.
>>> 
>>> We need both non-volatile and 4-byte alignment to safely combine loads and stores. If memoperands are missing, I don't see any alternative. How else can we guarantee the optimization is valid?
>>> 
>>> If this causes missed optimizations, we should ensure that memory operands are present.
>> 
>> I agree. I am just wondering if that's indeed the case. Can you add a llc beta check to look for differences in # of load / store multiple optimizations?
> 
> I ran an assembly diff across the entire nightly test suite.
> 
> We lost 117 of 56783 ldms and 40 of 47702 stms.

Thanks. Can you file a bug about this? We should take a look.

Evan

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From evan.cheng at apple.com  Tue Jun 29 20:05:26 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 29 Jun 2010 18:05:26 -0700
Subject: [llvm-commits] [llvm] r107227 - in /llvm/trunk:
	include/llvm/CodeGen/MachineRegisterInfo.h
	lib/CodeGen/CMakeLists.txt lib/CodeGen/InlineSpiller.cpp
	lib/CodeGen/Spiller.cpp
In-Reply-To: <20100629235839.983DB2A6C12C@llvm.org>
References: <20100629235839.983DB2A6C12C@llvm.org>
Message-ID: <81A9659F-590F-4C11-ABD2-8491950C93D4@apple.com>


On Jun 29, 2010, at 4:58 PM, Jakob Stoklund Olesen wrote:

> Author: stoklund
> Date: Tue Jun 29 18:58:39 2010
> New Revision: 107227
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=107227&view=rev
> Log:
> Begin implementation of an inline spiller.
> 
> InlineSpiller inserts loads and spills immediately instead of deferring to
> VirtRegMap. This is possible now because SlotIndexes allows instructions to be
> inserted and renumbered.
> 
> This is work in progress, and is mostly a copy of TrivialSpiller so far. It
> works very well for functions that don't require spilling.

Sounds like we should switch over now! :-)

Evan

> 
> Added:
>    llvm/trunk/lib/CodeGen/InlineSpiller.cpp
> Modified:
>    llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h
>    llvm/trunk/lib/CodeGen/CMakeLists.txt
>    llvm/trunk/lib/CodeGen/Spiller.cpp
> 
> Modified: llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h?rev=107227&r1=107226&r2=107227&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h Tue Jun 29 18:58:39 2010
> @@ -363,7 +363,18 @@
>     defusechain_iterator operator++(int) {        // Postincrement
>       defusechain_iterator tmp = *this; ++*this; return tmp;
>     }
> -    
> +
> +    /// skipInstruction - move forward until reaching a different instruction.
> +    /// Return the skipped instruction that is no longer pointed to, or NULL if
> +    /// already pointing to end().
> +    MachineInstr *skipInstruction() {
> +      if (!Op) return 0;
> +      MachineInstr *MI = Op->getParent();
> +      do ++*this;
> +      while (Op && Op->getParent() == MI);
> +      return MI;
> +    }
> +
>     MachineOperand &getOperand() const {
>       assert(Op && "Cannot dereference end iterator!");
>       return *Op;
> 
> Modified: llvm/trunk/lib/CodeGen/CMakeLists.txt
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CMakeLists.txt?rev=107227&r1=107226&r2=107227&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/CMakeLists.txt (original)
> +++ llvm/trunk/lib/CodeGen/CMakeLists.txt Tue Jun 29 18:58:39 2010
> @@ -13,6 +13,7 @@
>   GCMetadataPrinter.cpp
>   GCStrategy.cpp
>   IfConversion.cpp
> +  InlineSpiller.cpp
>   IntrinsicLowering.cpp
>   LLVMTargetMachine.cpp
>   LatencyPriorityQueue.cpp
> 
> Added: llvm/trunk/lib/CodeGen/InlineSpiller.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/InlineSpiller.cpp?rev=107227&view=auto
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/InlineSpiller.cpp (added)
> +++ llvm/trunk/lib/CodeGen/InlineSpiller.cpp Tue Jun 29 18:58:39 2010
> @@ -0,0 +1,136 @@
> +//===-------- InlineSpiller.cpp - Insert spills and restores inline -------===//
> +//
> +//                     The LLVM Compiler Infrastructure
> +//
> +// This file is distributed under the University of Illinois Open Source
> +// License. See LICENSE.TXT for details.
> +//
> +//===----------------------------------------------------------------------===//
> +//
> +// The inline spiller modifies the machine function directly instead of
> +// inserting spills and restores in VirtRegMap.
> +//
> +//===----------------------------------------------------------------------===//
> +
> +#define DEBUG_TYPE "spiller"
> +#include "Spiller.h"
> +#include "VirtRegMap.h"
> +#include "llvm/CodeGen/LiveIntervalAnalysis.h"
> +#include "llvm/CodeGen/MachineFrameInfo.h"
> +#include "llvm/CodeGen/MachineFunction.h"
> +#include "llvm/CodeGen/MachineRegisterInfo.h"
> +#include "llvm/Target/TargetMachine.h"
> +#include "llvm/Target/TargetInstrInfo.h"
> +#include "llvm/Support/Debug.h"
> +#include "llvm/Support/raw_ostream.h"
> +
> +using namespace llvm;
> +
> +namespace {
> +class InlineSpiller : public Spiller {
> +  MachineFunction &mf_;
> +  LiveIntervals &lis_;
> +  VirtRegMap &vrm_;
> +  MachineFrameInfo &mfi_;
> +  MachineRegisterInfo &mri_;
> +  const TargetInstrInfo &tii_;
> +  const TargetRegisterInfo &tri_;
> +
> +  ~InlineSpiller() {}
> +
> +public:
> +  InlineSpiller(MachineFunction *mf, LiveIntervals *lis, VirtRegMap *vrm)
> +    : mf_(*mf), lis_(*lis), vrm_(*vrm),
> +      mfi_(*mf->getFrameInfo()),
> +      mri_(mf->getRegInfo()),
> +      tii_(*mf->getTarget().getInstrInfo()),
> +      tri_(*mf->getTarget().getRegisterInfo()) {}
> +
> +  void spill(LiveInterval *li,
> +             std::vector<LiveInterval*> &newIntervals,
> +             SmallVectorImpl<LiveInterval*> &spillIs,
> +             SlotIndex *earliestIndex);
> +};
> +}
> +
> +namespace llvm {
> +Spiller *createInlineSpiller(MachineFunction *mf,
> +                             LiveIntervals *lis,
> +                             const MachineLoopInfo *mli,
> +                             VirtRegMap *vrm) {
> +  return new InlineSpiller(mf, lis, vrm);
> +}
> +}
> +
> +void InlineSpiller::spill(LiveInterval *li,
> +                          std::vector<LiveInterval*> &newIntervals,
> +                          SmallVectorImpl<LiveInterval*> &spillIs,
> +                          SlotIndex *earliestIndex) {
> +  DEBUG(dbgs() << "Inline spilling " << *li << "\n");
> +  assert(li->isSpillable() && "Attempting to spill already spilled value.");
> +  assert(!li->isStackSlot() && "Trying to spill a stack slot.");
> +
> +  const TargetRegisterClass *RC = mri_.getRegClass(li->reg);
> +  unsigned SS = vrm_.assignVirt2StackSlot(li->reg);
> +
> +  for (MachineRegisterInfo::reg_iterator RI = mri_.reg_begin(li->reg);
> +       MachineInstr *MI = RI.skipInstruction();) {
> +    SlotIndex Idx = lis_.getInstructionIndex(MI).getDefIndex();
> +
> +    // Analyze instruction.
> +    bool Reads, Writes;
> +    SmallVector<unsigned, 8> Ops;
> +    tie(Reads, Writes) = MI->readsWritesVirtualRegister(li->reg, &Ops);
> +
> +    // Allocate interval around instruction.
> +    // FIXME: Infer regclass from instruction alone.
> +    unsigned NewVReg = mri_.createVirtualRegister(RC);
> +    vrm_.grow();
> +    LiveInterval &NewLI = lis_.getOrCreateInterval(NewVReg);
> +    NewLI.markNotSpillable();
> +
> +    // Reload if instruction reads register.
> +    if (Reads) {
> +      MachineBasicBlock::iterator MII = MI;
> +      tii_.loadRegFromStackSlot(*MI->getParent(), MII, NewVReg, SS, RC, &tri_);
> +      --MII; // Point to load instruction.
> +      SlotIndex LoadIdx = lis_.InsertMachineInstrInMaps(MII).getDefIndex();
> +      DEBUG(dbgs() << "\treload:  " << LoadIdx << '\t' << *MII);
> +      VNInfo *LoadVNI = NewLI.getNextValue(LoadIdx, 0, true,
> +                                           lis_.getVNInfoAllocator());
> +      NewLI.addRange(LiveRange(LoadIdx, Idx, LoadVNI));
> +    }
> +
> +    // Rewrite instruction operands.
> +    bool hasLiveDef = false;
> +    for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
> +      MachineOperand &MO = MI->getOperand(Ops[i]);
> +      MO.setReg(NewVReg);
> +      if (MO.isUse()) {
> +        if (!MI->isRegTiedToDefOperand(Ops[i]))
> +          MO.setIsKill();
> +      } else {
> +        if (!MO.isDead())
> +          hasLiveDef = true;
> +      }
> +    }
> +    DEBUG(dbgs() << "\trewrite: " << Idx << '\t' << *MI);
> +
> +    // Spill is instruction writes register.
> +    // FIXME: Use a second vreg if instruction has no tied ops.
> +    if (Writes && hasLiveDef) {
> +      MachineBasicBlock::iterator MII = MI;
> +      tii_.storeRegToStackSlot(*MI->getParent(), ++MII, NewVReg, true, SS, RC,
> +                               &tri_);
> +      --MII; // Point to store instruction.
> +      SlotIndex StoreIdx = lis_.InsertMachineInstrInMaps(MII).getDefIndex();
> +      DEBUG(dbgs() << "\tspilled: " << StoreIdx << '\t' << *MII);
> +      VNInfo *StoreVNI = NewLI.getNextValue(Idx, 0, true,
> +                                            lis_.getVNInfoAllocator());
> +      NewLI.addRange(LiveRange(Idx, StoreIdx, StoreVNI));
> +    }
> +
> +    DEBUG(dbgs() << "\tinterval: " << NewLI << '\n');
> +    newIntervals.push_back(&NewLI);
> +  }
> +}
> 
> Modified: llvm/trunk/lib/CodeGen/Spiller.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Spiller.cpp?rev=107227&r1=107226&r2=107227&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/Spiller.cpp (original)
> +++ llvm/trunk/lib/CodeGen/Spiller.cpp Tue Jun 29 18:58:39 2010
> @@ -26,7 +26,7 @@
> using namespace llvm;
> 
> namespace {
> -  enum SpillerName { trivial, standard, splitting };
> +  enum SpillerName { trivial, standard, splitting, inline_ };
> }
> 
> static cl::opt<SpillerName>
> @@ -36,6 +36,7 @@
>            cl::values(clEnumVal(trivial,   "trivial spiller"),
>                       clEnumVal(standard,  "default spiller"),
>                       clEnumVal(splitting, "splitting spiller"),
> +                      "inline", inline_,   "inline spiller",
>                       clEnumValEnd),
>            cl::init(standard));
> 
> @@ -506,6 +507,13 @@
> } // end anonymous namespace
> 
> 
> +namespace llvm {
> +Spiller *createInlineSpiller(MachineFunction*,
> +                             LiveIntervals*,
> +                             const MachineLoopInfo*,
> +                             VirtRegMap*);
> +}
> +
> llvm::Spiller* llvm::createSpiller(MachineFunction *mf, LiveIntervals *lis,
>                                    const MachineLoopInfo *loopInfo,
>                                    VirtRegMap *vrm) {
> @@ -514,5 +522,6 @@
>   case trivial: return new TrivialSpiller(mf, lis, vrm);
>   case standard: return new StandardSpiller(lis, loopInfo, vrm);
>   case splitting: return new SplittingSpiller(mf, lis, loopInfo, vrm);
> +  case inline_: return createInlineSpiller(mf, lis, loopInfo, vrm);
>   }
> }
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits




From stoklund at 2pi.dk  Tue Jun 29 20:17:40 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 29 Jun 2010 18:17:40 -0700
Subject: [llvm-commits] [llvm] r107227 - in /llvm/trunk:
	include/llvm/CodeGen/MachineRegisterInfo.h
	lib/CodeGen/CMakeLists.txt lib/CodeGen/InlineSpiller.cpp
	lib/CodeGen/Spiller.cpp
In-Reply-To: <81A9659F-590F-4C11-ABD2-8491950C93D4@apple.com>
References: <20100629235839.983DB2A6C12C@llvm.org>
	<81A9659F-590F-4C11-ABD2-8491950C93D4@apple.com>
Message-ID: <9C6CCF2B-FA58-4615-8FF7-264993D513E8@2pi.dk>


On Jun 29, 2010, at 6:05 PM, Evan Cheng wrote:

> 
> On Jun 29, 2010, at 4:58 PM, Jakob Stoklund Olesen wrote:
> 
>> Author: stoklund
>> Date: Tue Jun 29 18:58:39 2010
>> New Revision: 107227
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=107227&view=rev
>> Log:
>> Begin implementation of an inline spiller.
>> 
>> InlineSpiller inserts loads and spills immediately instead of deferring to
>> VirtRegMap. This is possible now because SlotIndexes allows instructions to be
>> inserted and renumbered.
>> 
>> This is work in progress, and is mostly a copy of TrivialSpiller so far. It
>> works very well for functions that don't require spilling.
> 
> Sounds like we should switch over now! :-)

Yep, a number of test cases are already passing - the ones not requiring spilling. ;-)

The rest are failing because InlineSpiller is not properly tracking liveness of stack slots. It is simply a matter of figuring out how LiveIntervals::rewriteInstructionsForSpills is doing that.


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From dpatel at apple.com  Tue Jun 29 20:40:11 2010
From: dpatel at apple.com (Devang Patel)
Date: Wed, 30 Jun 2010 01:40:11 -0000
Subject: [llvm-commits] [llvm] r107237 -
	/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
Message-ID: <20100630014011.5441B2A6C12C@llvm.org>

Author: dpatel
Date: Tue Jun 29 20:40:11 2010
New Revision: 107237

URL: http://llvm.org/viewvc/llvm-project?rev=107237&view=rev
Log:
Do not construct DIE for already processed MDNode.

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=107237&r1=107236&r2=107237&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Tue Jun 29 20:40:11 2010
@@ -2766,7 +2766,8 @@
           }
         }
       }
-      constructScopeDIE(*AI);
+      if (ProcessedSPNodes.count((*AI)->getScopeNode()) == 0)
+        constructScopeDIE(*AI);
     }
     
     DIE *CurFnDIE = constructScopeDIE(CurrentFnDbgScope);




From bruno.cardoso at gmail.com  Tue Jun 29 20:58:37 2010
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Wed, 30 Jun 2010 01:58:37 -0000
Subject: [llvm-commits] [llvm] r107238 - in /llvm/trunk:
 lib/Target/X86/X86InstrSSE.td lib/Target/X86/X86MCCodeEmitter.cpp
 test/MC/AsmParser/X86/x86_32-encoding.s
 test/MC/AsmParser/X86/x86_64-encoding.s
Message-ID: <20100630015838.2ACDE2A6C12C@llvm.org>

Author: bruno
Date: Tue Jun 29 20:58:37 2010
New Revision: 107238

URL: http://llvm.org/viewvc/llvm-project?rev=107238&view=rev
Log:
- Add AVX form of all SSE2 logical instructions
- Add VEX encoding bits to x86 MRM0r-MRM7r

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp
    llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
    llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=107238&r1=107237&r2=107238&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Jun 29 20:58:37 2010
@@ -2440,6 +2440,68 @@
 // SSE2 - Packed Integer Logical Instructions
 //===---------------------------------------------------------------------===//
 
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE2] in {
+defm VPSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "vpsllw",
+                                int_x86_sse2_psll_w, int_x86_sse2_pslli_w, 0>,
+                                VEX_4V;
+defm VPSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "vpslld",
+                                int_x86_sse2_psll_d, int_x86_sse2_pslli_d, 0>,
+                                VEX_4V;
+defm VPSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "vpsllq",
+                                int_x86_sse2_psll_q, int_x86_sse2_pslli_q, 0>,
+                                VEX_4V;
+
+defm VPSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "vpsrlw",
+                                int_x86_sse2_psrl_w, int_x86_sse2_psrli_w, 0>,
+                                VEX_4V;
+defm VPSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "vpsrld",
+                                int_x86_sse2_psrl_d, int_x86_sse2_psrli_d, 0>,
+                                VEX_4V;
+defm VPSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "vpsrlq",
+                                int_x86_sse2_psrl_q, int_x86_sse2_psrli_q, 0>,
+                                VEX_4V;
+
+defm VPSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "vpsraw",
+                                int_x86_sse2_psra_w, int_x86_sse2_psrai_w, 0>,
+                                VEX_4V;
+defm VPSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
+                                int_x86_sse2_psra_d, int_x86_sse2_psrai_d, 0>,
+                                VEX_4V;
+
+let isCommutable = 1 in {
+defm VPAND : PDI_binop_rm_v2i64<0xDB, "vpand", and, 0>, VEX_4V;
+defm VPOR  : PDI_binop_rm_v2i64<0xEB, "vpor" , or, 0>, VEX_4V;
+defm VPXOR : PDI_binop_rm_v2i64<0xEF, "vpxor", xor, 0>, VEX_4V;
+}
+
+let ExeDomain = SSEPackedInt in {
+  let neverHasSideEffects = 1 in {
+    // 128-bit logical shifts.
+    def VPSLLDQri : PDIi8<0x73, MRM7r,
+                      (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
+                      "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
+                      VEX_4V;
+    def VPSRLDQri : PDIi8<0x73, MRM3r,
+                      (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
+                      "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
+                      VEX_4V;
+    // PSRADQri doesn't exist in SSE[1-3].
+  }
+  def VPANDNrr : PDI<0xDF, MRMSrcReg,
+                    (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
+                    "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
+                    [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
+                                              VR128:$src2)))]>, VEX_4V;
+
+  def VPANDNrm : PDI<0xDF, MRMSrcMem,
+                    (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
+                    "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
+                    [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
+                                              (memopv2i64 addr:$src2))))]>,
+                                              VEX_4V;
+}
+}
+
 let Constraints = "$src1 = $dst" in {
 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
                                int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;

Modified: llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp?rev=107238&r1=107237&r2=107238&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp Tue Jun 29 20:58:37 2010
@@ -60,6 +60,27 @@
   static unsigned GetX86RegNum(const MCOperand &MO) {
     return X86RegisterInfo::getX86RegNum(MO.getReg());
   }
+
+  // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range
+  // 0-7 and the difference between the 2 groups is given by the REX prefix.
+  // In the VEX prefix, registers are seen sequencially from 0-15 and encoded
+  // in 1's complement form, example:
+  //
+  //  ModRM field => XMM9 => 1
+  //  VEX.VVVV    => XMM9 => ~9
+  //
+  // See table 4-35 of Intel AVX Programming Reference for details.
+  static unsigned char getVEXRegisterEncoding(const MCInst &MI,
+                                              unsigned OpNum) {
+    unsigned SrcReg = MI.getOperand(OpNum).getReg();
+    unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum));
+    if (SrcReg >= X86::XMM8 && SrcReg <= X86::XMM15)
+      SrcRegNum += 8;
+  
+    // The registers represented through VEX_VVVV should
+    // be encoded in 1's complement form.
+    return (~SrcRegNum) & 0xf;
+  }
   
   void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
     OS << (char)C;
@@ -134,7 +155,6 @@
   return new X86MCCodeEmitter(TM, Ctx, true);
 }
 
-
 /// isDisp8 - Return true if this signed displacement fits in a 8-bit 
 /// sign-extended field. 
 static bool isDisp8(int Value) {
@@ -469,29 +489,12 @@
         X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
       VEX_R = 0x0;
 
-    // If the memory destination has been checked first,
-    // go back to the first operand
+    // CurOp and NumOps are equal when VEX_R represents a register used
+    // to index a memory destination (which is the last operand)
     CurOp = (CurOp == NumOps) ? 0 : CurOp+1;
 
-    // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the
-    // range 0-7 and the difference between the 2 groups is given by the
-    // REX prefix. In the VEX prefix, registers are seen sequencially
-    // from 0-15 and encoded in 1's complement form, example:
-    //
-    //  ModRM field => XMM9 => 1
-    //  VEX.VVVV    => XMM9 => ~9
-    //
-    // See table 4-35 of Intel AVX Programming Reference for details.
     if (HasVEX_4V) {
-      unsigned SrcReg = MI.getOperand(CurOp).getReg();
-      unsigned SrcRegNum = GetX86RegNum(MI.getOperand(1));
-      if (SrcReg >= X86::XMM8 && SrcReg <= X86::XMM15)
-        SrcRegNum += 8;
-
-      // The registers represented through VEX_VVVV should
-      // be encoded in 1's complement form.
-      VEX_4V = (~SrcRegNum) & 0xf;
-
+      VEX_4V = getVEXRegisterEncoding(MI, CurOp);
       CurOp++;
     }
 
@@ -505,7 +508,17 @@
         VEX_X = 0x0;
     }
     break;
-  default:
+  default: // MRM0r-MRM7r
+    if (HasVEX_4V)
+      VEX_4V = getVEXRegisterEncoding(MI, CurOp);
+
+    CurOp++;
+    for (; CurOp != NumOps; ++CurOp) {
+      const MCOperand &MO = MI.getOperand(CurOp);
+      if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
+        VEX_B = 0x0;
+    }
+    break;
     assert(0 && "Not implemented!");
   }
 
@@ -831,6 +844,8 @@
   case X86II::MRM2r: case X86II::MRM3r:
   case X86II::MRM4r: case X86II::MRM5r:
   case X86II::MRM6r: case X86II::MRM7r:
+    if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
+      CurOp++;
     EmitByte(BaseOpcode, CurByte, OS);
     EmitRegModRMByte(MI.getOperand(CurOp++),
                      (TSFlags & X86II::FormMask)-X86II::MRM0r,

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s?rev=107238&r1=107237&r2=107238&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s Tue Jun 29 20:58:37 2010
@@ -11182,3 +11182,143 @@
 // CHECK: encoding: [0xc5,0xe9,0xf6,0x18]
           vpsadbw  (%eax), %xmm2, %xmm3
 
+// CHECK: vpsllw  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xf1,0xd9]
+          vpsllw  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpsllw  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xf1,0x18]
+          vpsllw  (%eax), %xmm2, %xmm3
+
+// CHECK: vpslld  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xf2,0xd9]
+          vpslld  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpslld  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xf2,0x18]
+          vpslld  (%eax), %xmm2, %xmm3
+
+// CHECK: vpsllq  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xf3,0xd9]
+          vpsllq  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpsllq  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xf3,0x18]
+          vpsllq  (%eax), %xmm2, %xmm3
+
+// CHECK: vpsraw  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xe1,0xd9]
+          vpsraw  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpsraw  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xe1,0x18]
+          vpsraw  (%eax), %xmm2, %xmm3
+
+// CHECK: vpsrad  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xe2,0xd9]
+          vpsrad  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpsrad  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xe2,0x18]
+          vpsrad  (%eax), %xmm2, %xmm3
+
+// CHECK: vpsrlw  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xd1,0xd9]
+          vpsrlw  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpsrlw  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xd1,0x18]
+          vpsrlw  (%eax), %xmm2, %xmm3
+
+// CHECK: vpsrld  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xd2,0xd9]
+          vpsrld  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpsrld  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xd2,0x18]
+          vpsrld  (%eax), %xmm2, %xmm3
+
+// CHECK: vpsrlq  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xd3,0xd9]
+          vpsrlq  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpsrlq  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xd3,0x18]
+          vpsrlq  (%eax), %xmm2, %xmm3
+
+// CHECK: vpslld  $10, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe1,0x72,0xf2,0x0a]
+          vpslld  $10, %xmm2, %xmm3
+
+// CHECK: vpslldq  $10, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe1,0x73,0xfa,0x0a]
+          vpslldq  $10, %xmm2, %xmm3
+
+// CHECK: vpsllq  $10, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe1,0x73,0xf2,0x0a]
+          vpsllq  $10, %xmm2, %xmm3
+
+// CHECK: vpsllw  $10, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe1,0x71,0xf2,0x0a]
+          vpsllw  $10, %xmm2, %xmm3
+
+// CHECK: vpsrad  $10, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe1,0x72,0xe2,0x0a]
+          vpsrad  $10, %xmm2, %xmm3
+
+// CHECK: vpsraw  $10, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe1,0x71,0xe2,0x0a]
+          vpsraw  $10, %xmm2, %xmm3
+
+// CHECK: vpsrld  $10, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe1,0x72,0xd2,0x0a]
+          vpsrld  $10, %xmm2, %xmm3
+
+// CHECK: vpsrldq  $10, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe1,0x73,0xda,0x0a]
+          vpsrldq  $10, %xmm2, %xmm3
+
+// CHECK: vpsrlq  $10, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe1,0x73,0xd2,0x0a]
+          vpsrlq  $10, %xmm2, %xmm3
+
+// CHECK: vpsrlw  $10, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe1,0x71,0xd2,0x0a]
+          vpsrlw  $10, %xmm2, %xmm3
+
+// CHECK: vpslld  $10, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe1,0x72,0xf2,0x0a]
+          vpslld  $10, %xmm2, %xmm3
+
+// CHECK: vpand  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xdb,0xd9]
+          vpand  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpand  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xdb,0x18]
+          vpand  (%eax), %xmm2, %xmm3
+
+// CHECK: vpor  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xeb,0xd9]
+          vpor  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpor  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xeb,0x18]
+          vpor  (%eax), %xmm2, %xmm3
+
+// CHECK: vpxor  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xef,0xd9]
+          vpxor  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpxor  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xef,0x18]
+          vpxor  (%eax), %xmm2, %xmm3
+
+// CHECK: vpandn  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xdf,0xd9]
+          vpandn  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpandn  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xdf,0x18]
+          vpandn  (%eax), %xmm2, %xmm3
+

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s?rev=107238&r1=107237&r2=107238&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s Tue Jun 29 20:58:37 2010
@@ -1222,3 +1222,143 @@
 // CHECK: encoding: [0xc5,0x19,0xf6,0x28]
           vpsadbw  (%rax), %xmm12, %xmm13
 
+// CHECK: vpsllw  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0xf1,0xeb]
+          vpsllw  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpsllw  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0xf1,0x28]
+          vpsllw  (%rax), %xmm12, %xmm13
+
+// CHECK: vpslld  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0xf2,0xeb]
+          vpslld  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpslld  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0xf2,0x28]
+          vpslld  (%rax), %xmm12, %xmm13
+
+// CHECK: vpsllq  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0xf3,0xeb]
+          vpsllq  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpsllq  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0xf3,0x28]
+          vpsllq  (%rax), %xmm12, %xmm13
+
+// CHECK: vpsraw  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0xe1,0xeb]
+          vpsraw  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpsraw  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0xe1,0x28]
+          vpsraw  (%rax), %xmm12, %xmm13
+
+// CHECK: vpsrad  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0xe2,0xeb]
+          vpsrad  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpsrad  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0xe2,0x28]
+          vpsrad  (%rax), %xmm12, %xmm13
+
+// CHECK: vpsrlw  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0xd1,0xeb]
+          vpsrlw  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpsrlw  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0xd1,0x28]
+          vpsrlw  (%rax), %xmm12, %xmm13
+
+// CHECK: vpsrld  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0xd2,0xeb]
+          vpsrld  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpsrld  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0xd2,0x28]
+          vpsrld  (%rax), %xmm12, %xmm13
+
+// CHECK: vpsrlq  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0xd3,0xeb]
+          vpsrlq  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpsrlq  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0xd3,0x28]
+          vpsrlq  (%rax), %xmm12, %xmm13
+
+// CHECK: vpslld  $10, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0xc1,0x11,0x72,0xf4,0x0a]
+          vpslld  $10, %xmm12, %xmm13
+
+// CHECK: vpslldq  $10, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0xc1,0x11,0x73,0xfc,0x0a]
+          vpslldq  $10, %xmm12, %xmm13
+
+// CHECK: vpsllq  $10, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0xc1,0x11,0x73,0xf4,0x0a]
+          vpsllq  $10, %xmm12, %xmm13
+
+// CHECK: vpsllw  $10, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0xc1,0x11,0x71,0xf4,0x0a]
+          vpsllw  $10, %xmm12, %xmm13
+
+// CHECK: vpsrad  $10, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0xc1,0x11,0x72,0xe4,0x0a]
+          vpsrad  $10, %xmm12, %xmm13
+
+// CHECK: vpsraw  $10, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0xc1,0x11,0x71,0xe4,0x0a]
+          vpsraw  $10, %xmm12, %xmm13
+
+// CHECK: vpsrld  $10, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0xc1,0x11,0x72,0xd4,0x0a]
+          vpsrld  $10, %xmm12, %xmm13
+
+// CHECK: vpsrldq  $10, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0xc1,0x11,0x73,0xdc,0x0a]
+          vpsrldq  $10, %xmm12, %xmm13
+
+// CHECK: vpsrlq  $10, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0xc1,0x11,0x73,0xd4,0x0a]
+          vpsrlq  $10, %xmm12, %xmm13
+
+// CHECK: vpsrlw  $10, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0xc1,0x11,0x71,0xd4,0x0a]
+          vpsrlw  $10, %xmm12, %xmm13
+
+// CHECK: vpslld  $10, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0xc1,0x11,0x72,0xf4,0x0a]
+          vpslld  $10, %xmm12, %xmm13
+
+// CHECK: vpand  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0xdb,0xeb]
+          vpand  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpand  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0xdb,0x28]
+          vpand  (%rax), %xmm12, %xmm13
+
+// CHECK: vpor  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0xeb,0xeb]
+          vpor  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpor  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0xeb,0x28]
+          vpor  (%rax), %xmm12, %xmm13
+
+// CHECK: vpxor  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0xef,0xeb]
+          vpxor  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpxor  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0xef,0x28]
+          vpxor  (%rax), %xmm12, %xmm13
+
+// CHECK: vpandn  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0xdf,0xeb]
+          vpandn  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpandn  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0xdf,0x28]
+          vpandn  (%rax), %xmm12, %xmm13
+




From bruno.cardoso at gmail.com  Tue Jun 29 21:21:09 2010
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Wed, 30 Jun 2010 02:21:09 -0000
Subject: [llvm-commits] [llvm] r107240 - in /llvm/trunk:
 lib/Target/X86/X86InstrSSE.td test/MC/AsmParser/X86/x86_32-encoding.s
 test/MC/AsmParser/X86/x86_64-encoding.s
Message-ID: <20100630022109.9A9BB2A6C12C@llvm.org>

Author: bruno
Date: Tue Jun 29 21:21:09 2010
New Revision: 107240

URL: http://llvm.org/viewvc/llvm-project?rev=107240&view=rev
Log:
Add AVX SSE2 integer packed compare instructions

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
    llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=107240&r1=107239&r2=107240&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Jun 29 21:21:09 2010
@@ -2576,6 +2576,23 @@
 // SSE2 - Packed Integer Comparison Instructions
 //===---------------------------------------------------------------------===//
 
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE2] in {
+  let isCommutable = 1 in {
+  defm VPCMPEQB  : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_sse2_pcmpeq_b, 0>,
+                                   VEX_4V;
+  defm VPCMPEQW  : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_sse2_pcmpeq_w, 0>,
+                                   VEX_4V;
+  defm VPCMPEQD  : PDI_binop_rm_int<0x76, "vpcmpeqd", int_x86_sse2_pcmpeq_d, 0>,
+                                   VEX_4V;
+  }
+  defm VPCMPGTB  : PDI_binop_rm_int<0x64, "vpcmpgtb", int_x86_sse2_pcmpgt_b, 0>,
+                                   VEX_4V;
+  defm VPCMPGTW  : PDI_binop_rm_int<0x65, "vpcmpgtw", int_x86_sse2_pcmpgt_w, 0>,
+                                   VEX_4V;
+  defm VPCMPGTD  : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_sse2_pcmpgt_d, 0>,
+                                   VEX_4V;
+}
+
 let Constraints = "$src1 = $dst" in {
   let isCommutable = 1 in {
   defm PCMPEQB  : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s?rev=107240&r1=107239&r2=107240&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s Tue Jun 29 21:21:09 2010
@@ -11322,3 +11322,51 @@
 // CHECK: encoding: [0xc5,0xe9,0xdf,0x18]
           vpandn  (%eax), %xmm2, %xmm3
 
+// CHECK: vpcmpeqb  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0x74,0xd9]
+          vpcmpeqb  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpcmpeqb  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0x74,0x18]
+          vpcmpeqb  (%eax), %xmm2, %xmm3
+
+// CHECK: vpcmpeqw  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0x75,0xd9]
+          vpcmpeqw  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpcmpeqw  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0x75,0x18]
+          vpcmpeqw  (%eax), %xmm2, %xmm3
+
+// CHECK: vpcmpeqd  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0x76,0xd9]
+          vpcmpeqd  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpcmpeqd  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0x76,0x18]
+          vpcmpeqd  (%eax), %xmm2, %xmm3
+
+// CHECK: vpcmpgtb  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0x64,0xd9]
+          vpcmpgtb  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpcmpgtb  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0x64,0x18]
+          vpcmpgtb  (%eax), %xmm2, %xmm3
+
+// CHECK: vpcmpgtw  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0x65,0xd9]
+          vpcmpgtw  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpcmpgtw  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0x65,0x18]
+          vpcmpgtw  (%eax), %xmm2, %xmm3
+
+// CHECK: vpcmpgtd  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0x66,0xd9]
+          vpcmpgtd  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpcmpgtd  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0x66,0x18]
+          vpcmpgtd  (%eax), %xmm2, %xmm3
+

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s?rev=107240&r1=107239&r2=107240&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s Tue Jun 29 21:21:09 2010
@@ -1362,3 +1362,51 @@
 // CHECK: encoding: [0xc5,0x19,0xdf,0x28]
           vpandn  (%rax), %xmm12, %xmm13
 
+// CHECK: vpcmpeqb  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0x74,0xeb]
+          vpcmpeqb  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpcmpeqb  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0x74,0x28]
+          vpcmpeqb  (%rax), %xmm12, %xmm13
+
+// CHECK: vpcmpeqw  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0x75,0xeb]
+          vpcmpeqw  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpcmpeqw  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0x75,0x28]
+          vpcmpeqw  (%rax), %xmm12, %xmm13
+
+// CHECK: vpcmpeqd  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0x76,0xeb]
+          vpcmpeqd  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpcmpeqd  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0x76,0x28]
+          vpcmpeqd  (%rax), %xmm12, %xmm13
+
+// CHECK: vpcmpgtb  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0x64,0xeb]
+          vpcmpgtb  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpcmpgtb  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0x64,0x28]
+          vpcmpgtb  (%rax), %xmm12, %xmm13
+
+// CHECK: vpcmpgtw  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0x65,0xeb]
+          vpcmpgtw  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpcmpgtw  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0x65,0x28]
+          vpcmpgtw  (%rax), %xmm12, %xmm13
+
+// CHECK: vpcmpgtd  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0x66,0xeb]
+          vpcmpgtd  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpcmpgtd  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0x66,0x28]
+          vpcmpgtd  (%rax), %xmm12, %xmm13
+




From bruno.cardoso at gmail.com  Tue Jun 29 21:30:25 2010
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Wed, 30 Jun 2010 02:30:25 -0000
Subject: [llvm-commits] [llvm] r107241 - in /llvm/trunk:
 lib/Target/X86/X86InstrSSE.td test/MC/AsmParser/X86/x86_32-encoding.s
 test/MC/AsmParser/X86/x86_64-encoding.s
Message-ID: <20100630023025.BA85A2A6C12C@llvm.org>

Author: bruno
Date: Tue Jun 29 21:30:25 2010
New Revision: 107241

URL: http://llvm.org/viewvc/llvm-project?rev=107241&view=rev
Log:
Add AVX SSE2 pack with saturation integer instructions

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
    llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=107241&r1=107240&r2=107241&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Jun 29 21:30:25 2010
@@ -2634,6 +2634,15 @@
 // SSE2 - Packed Integer Pack Instructions
 //===---------------------------------------------------------------------===//
 
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE2] in {
+defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
+                                  0>, VEX_4V;
+defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
+                                  0>, VEX_4V;
+defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
+                                  0>, VEX_4V;
+}
+
 let Constraints = "$src1 = $dst" in {
 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s?rev=107241&r1=107240&r2=107241&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s Tue Jun 29 21:30:25 2010
@@ -11370,3 +11370,27 @@
 // CHECK: encoding: [0xc5,0xe9,0x66,0x18]
           vpcmpgtd  (%eax), %xmm2, %xmm3
 
+// CHECK: vpacksswb  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0x63,0xd9]
+          vpacksswb  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpacksswb  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0x63,0x18]
+          vpacksswb  (%eax), %xmm2, %xmm3
+
+// CHECK: vpackssdw  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0x6b,0xd9]
+          vpackssdw  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpackssdw  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0x6b,0x18]
+          vpackssdw  (%eax), %xmm2, %xmm3
+
+// CHECK: vpackuswb  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0x67,0xd9]
+          vpackuswb  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpackuswb  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0x67,0x18]
+          vpackuswb  (%eax), %xmm2, %xmm3
+

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s?rev=107241&r1=107240&r2=107241&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s Tue Jun 29 21:30:25 2010
@@ -1410,3 +1410,27 @@
 // CHECK: encoding: [0xc5,0x19,0x66,0x28]
           vpcmpgtd  (%rax), %xmm12, %xmm13
 
+// CHECK: vpacksswb  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0x63,0xeb]
+          vpacksswb  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpacksswb  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0x63,0x28]
+          vpacksswb  (%rax), %xmm12, %xmm13
+
+// CHECK: vpackssdw  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0x6b,0xeb]
+          vpackssdw  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpackssdw  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0x6b,0x28]
+          vpackssdw  (%rax), %xmm12, %xmm13
+
+// CHECK: vpackuswb  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0x67,0xeb]
+          vpackuswb  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpackuswb  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0x67,0x28]
+          vpackuswb  (%rax), %xmm12, %xmm13
+




From bruno.cardoso at gmail.com  Tue Jun 29 22:29:36 2010
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Wed, 30 Jun 2010 03:29:36 -0000
Subject: [llvm-commits] [llvm] r107243 -
	/llvm/trunk/lib/Target/X86/X86InstrSSE.td
Message-ID: <20100630032936.AC1F02A6C12C@llvm.org>

Author: bruno
Date: Tue Jun 29 22:29:36 2010
New Revision: 107243

URL: http://llvm.org/viewvc/llvm-project?rev=107243&view=rev
Log:
Small refactoring of SSE2 packed integer shuffle instructions

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=107243&r1=107242&r2=107243&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Jun 29 22:29:36 2010
@@ -2654,53 +2654,34 @@
 //===---------------------------------------------------------------------===//
 
 let ExeDomain = SSEPackedInt in {
+multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, PatFrag pshuf_frag,
+                         PatFrag bc_frag> {
+def ri : Ii8<0x70, MRMSrcReg,
+              (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
+              !strconcat(OpcodeStr,
+                         "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+              [(set VR128:$dst, (vt (pshuf_frag:$src2 VR128:$src1,
+                                                      (undef))))]>;
+def mi : Ii8<0x70, MRMSrcMem,
+              (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
+              !strconcat(OpcodeStr,
+                         "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+              [(set VR128:$dst, (vt (pshuf_frag:$src2
+                                      (bc_frag (memopv2i64 addr:$src1)),
+                                      (undef))))]>;
+}
+} // ExeDomain = SSEPackedInt
 
-// Shuffle and unpack instructions
-let AddedComplexity = 5 in {
-def PSHUFDri : PDIi8<0x70, MRMSrcReg,
-                     (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
-                     "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
-                     [(set VR128:$dst, (v4i32 (pshufd:$src2
-                                               VR128:$src1, (undef))))]>;
-def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
-                     (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
-                     "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
-                     [(set VR128:$dst, (v4i32 (pshufd:$src2
-                                             (bc_v4i32 (memopv2i64 addr:$src1)),
-                                             (undef))))]>;
-}
-
-// SSE2 with ImmT == Imm8 and XS prefix.
-def PSHUFHWri : Ii8<0x70, MRMSrcReg,
-                    (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
-                    "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
-                    [(set VR128:$dst, (v8i16 (pshufhw:$src2 VR128:$src1,
-                                                            (undef))))]>,
-                XS, Requires<[HasSSE2]>;
-def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
-                    (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
-                    "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
-                    [(set VR128:$dst, (v8i16 (pshufhw:$src2
-                                            (bc_v8i16 (memopv2i64 addr:$src1)),
-                                            (undef))))]>,
-                XS, Requires<[HasSSE2]>;
-
-// SSE2 with ImmT == Imm8 and XD prefix.
-def PSHUFLWri : Ii8<0x70, MRMSrcReg,
-                    (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
-                    "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
-                    [(set VR128:$dst, (v8i16 (pshuflw:$src2 VR128:$src1,
-                                                            (undef))))]>,
-                XD, Requires<[HasSSE2]>;
-def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
-                    (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
-                    "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
-                    [(set VR128:$dst, (v8i16 (pshuflw:$src2
-                                             (bc_v8i16 (memopv2i64 addr:$src1)),
-                                             (undef))))]>,
-                XD, Requires<[HasSSE2]>;
+let Predicates = [HasSSE2] in {
+  let AddedComplexity = 5 in
+  defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize;
 
-} // ExeDomain = SSEPackedInt
+  // SSE2 with ImmT == Imm8 and XS prefix.
+  defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, pshufhw, bc_v8i16>, XS;
+
+  // SSE2 with ImmT == Imm8 and XD prefix.
+  defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, pshuflw, bc_v8i16>, XD;
+}
 
 //===---------------------------------------------------------------------===//
 // SSE2 - Packed Integer Unpack Instructions




From ojomojo at gmail.com  Tue Jun 29 22:40:54 2010
From: ojomojo at gmail.com (John Mosby)
Date: Wed, 30 Jun 2010 03:40:54 -0000
Subject: [llvm-commits] [llvm] r107244 -
	/llvm/trunk/lib/CodeGen/ScheduleDAG.cpp
Message-ID: <20100630034054.E89372A6C12C@llvm.org>

Author: jdm
Date: Tue Jun 29 22:40:54 2010
New Revision: 107244

URL: http://llvm.org/viewvc/llvm-project?rev=107244&view=rev
Log:
Remove trailing whitespace, no functionality changes.

Modified:
    llvm/trunk/lib/CodeGen/ScheduleDAG.cpp

Modified: llvm/trunk/lib/CodeGen/ScheduleDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAG.cpp?rev=107244&r1=107243&r2=107244&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ScheduleDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/ScheduleDAG.cpp Tue Jun 29 22:40:54 2010
@@ -380,26 +380,26 @@
 }
 #endif
 
-/// InitDAGTopologicalSorting - create the initial topological 
+/// InitDAGTopologicalSorting - create the initial topological
 /// ordering from the DAG to be scheduled.
 ///
-/// The idea of the algorithm is taken from 
+/// The idea of the algorithm is taken from
 /// "Online algorithms for managing the topological order of
 /// a directed acyclic graph" by David J. Pearce and Paul H.J. Kelly
-/// This is the MNR algorithm, which was first introduced by 
-/// A. Marchetti-Spaccamela, U. Nanni and H. Rohnert in  
+/// This is the MNR algorithm, which was first introduced by
+/// A. Marchetti-Spaccamela, U. Nanni and H. Rohnert in
 /// "Maintaining a topological order under edge insertions".
 ///
-/// Short description of the algorithm: 
+/// Short description of the algorithm:
 ///
 /// Topological ordering, ord, of a DAG maps each node to a topological
 /// index so that for all edges X->Y it is the case that ord(X) < ord(Y).
 ///
-/// This means that if there is a path from the node X to the node Z, 
+/// This means that if there is a path from the node X to the node Z,
 /// then ord(X) < ord(Z).
 ///
 /// This property can be used to check for reachability of nodes:
-/// if Z is reachable from X, then an insertion of the edge Z->X would 
+/// if Z is reachable from X, then an insertion of the edge Z->X would
 /// create a cycle.
 ///
 /// The algorithm first computes a topological ordering for the DAG by
@@ -431,7 +431,7 @@
       // Collect leaf nodes.
       WorkList.push_back(SU);
     }
-  }  
+  }
 
   int Id = DAGSize;
   while (!WorkList.empty()) {
@@ -456,7 +456,7 @@
     SUnit *SU = &SUnits[i];
     for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
          I != E; ++I) {
-      assert(Node2Index[SU->NodeNum] > Node2Index[I->getSUnit()->NodeNum] && 
+      assert(Node2Index[SU->NodeNum] > Node2Index[I->getSUnit()->NodeNum] &&
       "Wrong topological sorting");
     }
   }
@@ -494,7 +494,7 @@
 void ScheduleDAGTopologicalSort::DFS(const SUnit *SU, int UpperBound,
                                      bool& HasLoop) {
   std::vector<const SUnit*> WorkList;
-  WorkList.reserve(SUnits.size()); 
+  WorkList.reserve(SUnits.size());
 
   WorkList.push_back(SU);
   do {
@@ -504,20 +504,20 @@
     for (int I = SU->Succs.size()-1; I >= 0; --I) {
       int s = SU->Succs[I].getSUnit()->NodeNum;
       if (Node2Index[s] == UpperBound) {
-        HasLoop = true; 
+        HasLoop = true;
         return;
       }
       // Visit successors if not already and in affected region.
       if (!Visited.test(s) && Node2Index[s] < UpperBound) {
         WorkList.push_back(SU->Succs[I].getSUnit());
-      } 
-    } 
+      }
+    }
   } while (!WorkList.empty());
 }
 
-/// Shift - Renumber the nodes so that the topological ordering is 
+/// Shift - Renumber the nodes so that the topological ordering is
 /// preserved.
-void ScheduleDAGTopologicalSort::Shift(BitVector& Visited, int LowerBound, 
+void ScheduleDAGTopologicalSort::Shift(BitVector& Visited, int LowerBound,
                                        int UpperBound) {
   std::vector<int> L;
   int shift = 0;
@@ -568,7 +568,7 @@
   // Is Ord(TargetSU) < Ord(SU) ?
   if (LowerBound < UpperBound) {
     Visited.reset();
-    // There may be a path from TargetSU to SU. Check for it. 
+    // There may be a path from TargetSU to SU. Check for it.
     DFS(TargetSU, UpperBound, HasLoop);
   }
   return HasLoop;
@@ -580,8 +580,7 @@
   Index2Node[index] = n;
 }
 
-ScheduleDAGTopologicalSort::ScheduleDAGTopologicalSort(
-                                                     std::vector<SUnit> &sunits)
- : SUnits(sunits) {}
+ScheduleDAGTopologicalSort::
+ScheduleDAGTopologicalSort(std::vector<SUnit> &sunits) : SUnits(sunits) {}
 
 ScheduleHazardRecognizer::~ScheduleHazardRecognizer() {}




From bruno.cardoso at gmail.com  Tue Jun 29 22:47:56 2010
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Wed, 30 Jun 2010 03:47:56 -0000
Subject: [llvm-commits] [llvm] r107245 - in /llvm/trunk:
 lib/Target/X86/X86InstrSSE.td test/MC/AsmParser/X86/x86_32-encoding.s
 test/MC/AsmParser/X86/x86_64-encoding.s
Message-ID: <20100630034756.D2EE02A6C12C@llvm.org>

Author: bruno
Date: Tue Jun 29 22:47:56 2010
New Revision: 107245

URL: http://llvm.org/viewvc/llvm-project?rev=107245&view=rev
Log:
Add AVX SSE2 packed integer shuffle instructions

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
    llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=107245&r1=107244&r2=107245&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Jun 29 22:47:56 2010
@@ -2672,6 +2672,20 @@
 }
 } // ExeDomain = SSEPackedInt
 
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE2] in {
+  let AddedComplexity = 5 in
+  defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, OpSize,
+                               VEX;
+
+  // SSE2 with ImmT == Imm8 and XS prefix.
+  defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, pshufhw, bc_v8i16>, XS,
+                               VEX;
+
+  // SSE2 with ImmT == Imm8 and XD prefix.
+  defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, pshuflw, bc_v8i16>, XD,
+                               VEX;
+}
+
 let Predicates = [HasSSE2] in {
   let AddedComplexity = 5 in
   defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize;

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s?rev=107245&r1=107244&r2=107245&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s Tue Jun 29 22:47:56 2010
@@ -11394,3 +11394,27 @@
 // CHECK: encoding: [0xc5,0xe9,0x67,0x18]
           vpackuswb  (%eax), %xmm2, %xmm3
 
+// CHECK: vpshufd  $4, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xf9,0x70,0xda,0x04]
+          vpshufd  $4, %xmm2, %xmm3
+
+// CHECK: vpshufd  $4, (%eax), %xmm3
+// CHECK: encoding: [0xc5,0xf9,0x70,0x18,0x04]
+          vpshufd  $4, (%eax), %xmm3
+
+// CHECK: vpshufhw  $4, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xfa,0x70,0xda,0x04]
+          vpshufhw  $4, %xmm2, %xmm3
+
+// CHECK: vpshufhw  $4, (%eax), %xmm3
+// CHECK: encoding: [0xc5,0xfa,0x70,0x18,0x04]
+          vpshufhw  $4, (%eax), %xmm3
+
+// CHECK: vpshuflw  $4, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xfb,0x70,0xda,0x04]
+          vpshuflw  $4, %xmm2, %xmm3
+
+// CHECK: vpshuflw  $4, (%eax), %xmm3
+// CHECK: encoding: [0xc5,0xfb,0x70,0x18,0x04]
+          vpshuflw  $4, (%eax), %xmm3
+

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s?rev=107245&r1=107244&r2=107245&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s Tue Jun 29 22:47:56 2010
@@ -1434,3 +1434,27 @@
 // CHECK: encoding: [0xc5,0x19,0x67,0x28]
           vpackuswb  (%rax), %xmm12, %xmm13
 
+// CHECK: vpshufd  $4, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x79,0x70,0xec,0x04]
+          vpshufd  $4, %xmm12, %xmm13
+
+// CHECK: vpshufd  $4, (%rax), %xmm13
+// CHECK: encoding: [0xc5,0x79,0x70,0x28,0x04]
+          vpshufd  $4, (%rax), %xmm13
+
+// CHECK: vpshufhw  $4, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x7a,0x70,0xec,0x04]
+          vpshufhw  $4, %xmm12, %xmm13
+
+// CHECK: vpshufhw  $4, (%rax), %xmm13
+// CHECK: encoding: [0xc5,0x7a,0x70,0x28,0x04]
+          vpshufhw  $4, (%rax), %xmm13
+
+// CHECK: vpshuflw  $4, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x7b,0x70,0xec,0x04]
+          vpshuflw  $4, %xmm12, %xmm13
+
+// CHECK: vpshuflw  $4, (%rax), %xmm13
+// CHECK: encoding: [0xc5,0x7b,0x70,0x28,0x04]
+          vpshuflw  $4, (%rax), %xmm13
+




From bruno.cardoso at gmail.com  Tue Jun 29 23:06:39 2010
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Wed, 30 Jun 2010 04:06:39 -0000
Subject: [llvm-commits] [llvm] r107246 - in /llvm/trunk:
 lib/Target/X86/X86InstrSSE.td test/MC/AsmParser/X86/x86_32-encoding.s
 test/MC/AsmParser/X86/x86_64-encoding.s
Message-ID: <20100630040639.B5EEB2A6C12C@llvm.org>

Author: bruno
Date: Tue Jun 29 23:06:39 2010
New Revision: 107246

URL: http://llvm.org/viewvc/llvm-project?rev=107246&view=rev
Log:
Add AVX SSE2 integer unpack instructions

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
    llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=107246&r1=107245&r2=107246&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Jun 29 23:06:39 2010
@@ -2702,19 +2702,66 @@
 //===---------------------------------------------------------------------===//
 
 let ExeDomain = SSEPackedInt in {
-
 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
-                       PatFrag unp_frag, PatFrag bc_frag> {
+                       PatFrag unp_frag, PatFrag bc_frag, bit Is2Addr = 1> {
   def rr : PDI<opc, MRMSrcReg,
-               (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
-               !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
-               [(set VR128:$dst, (vt (unp_frag VR128:$src1, VR128:$src2)))]>;
+      (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
+      !if(Is2Addr,
+          !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
+          !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
+      [(set VR128:$dst, (vt (unp_frag VR128:$src1, VR128:$src2)))]>;
   def rm : PDI<opc, MRMSrcMem,
-               (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
-               !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
-               [(set VR128:$dst, (unp_frag VR128:$src1,
-                                           (bc_frag (memopv2i64
-                                                        addr:$src2))))]>;
+      (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
+      !if(Is2Addr,
+          !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
+          !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
+      [(set VR128:$dst, (unp_frag VR128:$src1,
+                                  (bc_frag (memopv2i64
+                                               addr:$src2))))]>;
+}
+
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE2] in {
+  defm VPUNPCKLBW  : sse2_unpack<0x60, "vpunpcklbw", v16i8, unpckl, bc_v16i8,
+                                 0>, VEX_4V;
+  defm VPUNPCKLWD  : sse2_unpack<0x61, "vpunpcklwd", v8i16, unpckl, bc_v8i16,
+                                 0>, VEX_4V;
+  defm VPUNPCKLDQ  : sse2_unpack<0x62, "vpunpckldq", v4i32, unpckl, bc_v4i32,
+                                 0>, VEX_4V;
+
+  /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
+  /// knew to collapse (bitconvert VT to VT) into its operand.
+  def VPUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
+                         (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
+                         "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
+                        [(set VR128:$dst,
+                          (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>, VEX_4V;
+  def VPUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
+                         (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
+                         "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
+                        [(set VR128:$dst,
+                          (v2i64 (unpckl VR128:$src1,
+                                         (memopv2i64 addr:$src2))))]>, VEX_4V;
+
+  defm VPUNPCKHBW  : sse2_unpack<0x68, "vpunpckhbw", v16i8, unpckh, bc_v16i8,
+                                 0>, VEX_4V;
+  defm VPUNPCKHWD  : sse2_unpack<0x69, "vpunpckhwd", v8i16, unpckh, bc_v8i16,
+                                 0>, VEX_4V;
+  defm VPUNPCKHDQ  : sse2_unpack<0x6A, "vpunpckhdq", v4i32, unpckh, bc_v4i32,
+                                 0>, VEX_4V;
+
+  /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
+  /// knew to collapse (bitconvert VT to VT) into its operand.
+  def VPUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
+                         (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
+                         "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
+                        [(set VR128:$dst,
+                          (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>, VEX_4V;
+  def VPUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
+                        (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
+                        "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
+                        [(set VR128:$dst,
+                          (v2i64 (unpckh VR128:$src1,
+                                         (memopv2i64 addr:$src2))))]>, VEX_4V;
 }
 
 let Constraints = "$src1 = $dst" in {

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s?rev=107246&r1=107245&r2=107246&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s Tue Jun 29 23:06:39 2010
@@ -11418,3 +11418,67 @@
 // CHECK: encoding: [0xc5,0xfb,0x70,0x18,0x04]
           vpshuflw  $4, (%eax), %xmm3
 
+// CHECK: vpunpcklbw  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0x60,0xd9]
+          vpunpcklbw  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpunpcklbw  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0x60,0x18]
+          vpunpcklbw  (%eax), %xmm2, %xmm3
+
+// CHECK: vpunpcklwd  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0x61,0xd9]
+          vpunpcklwd  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpunpcklwd  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0x61,0x18]
+          vpunpcklwd  (%eax), %xmm2, %xmm3
+
+// CHECK: vpunpckldq  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0x62,0xd9]
+          vpunpckldq  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpunpckldq  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0x62,0x18]
+          vpunpckldq  (%eax), %xmm2, %xmm3
+
+// CHECK: vpunpcklqdq  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0x6c,0xd9]
+          vpunpcklqdq  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpunpcklqdq  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0x6c,0x18]
+          vpunpcklqdq  (%eax), %xmm2, %xmm3
+
+// CHECK: vpunpckhbw  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0x68,0xd9]
+          vpunpckhbw  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpunpckhbw  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0x68,0x18]
+          vpunpckhbw  (%eax), %xmm2, %xmm3
+
+// CHECK: vpunpckhwd  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0x69,0xd9]
+          vpunpckhwd  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpunpckhwd  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0x69,0x18]
+          vpunpckhwd  (%eax), %xmm2, %xmm3
+
+// CHECK: vpunpckhdq  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0x6a,0xd9]
+          vpunpckhdq  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpunpckhdq  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0x6a,0x18]
+          vpunpckhdq  (%eax), %xmm2, %xmm3
+
+// CHECK: vpunpckhqdq  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0x6d,0xd9]
+          vpunpckhqdq  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpunpckhqdq  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0x6d,0x18]
+          vpunpckhqdq  (%eax), %xmm2, %xmm3
+

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s?rev=107246&r1=107245&r2=107246&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s Tue Jun 29 23:06:39 2010
@@ -1458,3 +1458,67 @@
 // CHECK: encoding: [0xc5,0x7b,0x70,0x28,0x04]
           vpshuflw  $4, (%rax), %xmm13
 
+// CHECK: vpunpcklbw  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0x60,0xeb]
+          vpunpcklbw  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpunpcklbw  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0x60,0x28]
+          vpunpcklbw  (%rax), %xmm12, %xmm13
+
+// CHECK: vpunpcklwd  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0x61,0xeb]
+          vpunpcklwd  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpunpcklwd  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0x61,0x28]
+          vpunpcklwd  (%rax), %xmm12, %xmm13
+
+// CHECK: vpunpckldq  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0x62,0xeb]
+          vpunpckldq  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpunpckldq  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0x62,0x28]
+          vpunpckldq  (%rax), %xmm12, %xmm13
+
+// CHECK: vpunpcklqdq  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0x6c,0xeb]
+          vpunpcklqdq  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpunpcklqdq  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0x6c,0x28]
+          vpunpcklqdq  (%rax), %xmm12, %xmm13
+
+// CHECK: vpunpckhbw  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0x68,0xeb]
+          vpunpckhbw  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpunpckhbw  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0x68,0x28]
+          vpunpckhbw  (%rax), %xmm12, %xmm13
+
+// CHECK: vpunpckhwd  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0x69,0xeb]
+          vpunpckhwd  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpunpckhwd  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0x69,0x28]
+          vpunpckhwd  (%rax), %xmm12, %xmm13
+
+// CHECK: vpunpckhdq  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0x6a,0xeb]
+          vpunpckhdq  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpunpckhdq  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0x6a,0x28]
+          vpunpckhdq  (%rax), %xmm12, %xmm13
+
+// CHECK: vpunpckhqdq  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0x6d,0xeb]
+          vpunpckhqdq  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpunpckhqdq  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0x6d,0x28]
+          vpunpckhqdq  (%rax), %xmm12, %xmm13
+




From gohman at apple.com  Wed Jun 30 01:09:46 2010
From: gohman at apple.com (Dan Gohman)
Date: Wed, 30 Jun 2010 06:09:46 -0000
Subject: [llvm-commits] [llvm] r107248 -
	/llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp
Message-ID: <20100630060946.2A9D82A6C12C@llvm.org>

Author: djg
Date: Wed Jun 30 01:09:46 2010
New Revision: 107248

URL: http://llvm.org/viewvc/llvm-project?rev=107248&view=rev
Log:
Simplify.

Modified:
    llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp

Modified: llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp?rev=107248&r1=107247&r2=107248&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp Wed Jun 30 01:09:46 2010
@@ -1101,8 +1101,7 @@
   }
 
   // {0,+,1} --> Insert a canonical induction variable into the loop!
-  if (S->isAffine() &&
-      S->getOperand(1) == SE.getConstant(Ty, 1)) {
+  if (S->isAffine() && S->getOperand(1)->isOne()) {
     // If there's a canonical IV, just use it.
     if (CanonicalIV) {
       assert(Ty == SE.getEffectiveSCEVType(CanonicalIV->getType()) &&




From gohman at apple.com  Wed Jun 30 01:12:16 2010
From: gohman at apple.com (Dan Gohman)
Date: Wed, 30 Jun 2010 06:12:16 -0000
Subject: [llvm-commits] [llvm] r107249 -
	/llvm/trunk/lib/Analysis/ScalarEvolutionAliasAnalysis.cpp
Message-ID: <20100630061216.5A1062A6C12C@llvm.org>

Author: djg
Date: Wed Jun 30 01:12:16 2010
New Revision: 107249

URL: http://llvm.org/viewvc/llvm-project?rev=107249&view=rev
Log:
Rework scev-aa's basic computation so that it doesn't depend
on ScalarEvolution successfully folding and preserving
range information for both A-B and B-A. Now, if it gets
either one, it's sufficient.

Modified:
    llvm/trunk/lib/Analysis/ScalarEvolutionAliasAnalysis.cpp

Modified: llvm/trunk/lib/Analysis/ScalarEvolutionAliasAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolutionAliasAnalysis.cpp?rev=107249&r1=107248&r2=107249&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ScalarEvolutionAliasAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolutionAliasAnalysis.cpp Wed Jun 30 01:12:16 2010
@@ -106,6 +106,12 @@
 AliasAnalysis::AliasResult
 ScalarEvolutionAliasAnalysis::alias(const Value *A, unsigned ASize,
                                     const Value *B, unsigned BSize) {
+  // If either of the memory references is empty, it doesn't matter what the
+  // pointer values are. This allows the code below to ignore this special
+  // case.
+  if (ASize == 0 || BSize == 0)
+    return NoAlias;
+
   // This is ScalarEvolutionAliasAnalysis. Get the SCEVs!
   const SCEV *AS = SE->getSCEV(const_cast<Value *>(A));
   const SCEV *BS = SE->getSCEV(const_cast<Value *>(B));
@@ -118,14 +124,32 @@
   if (SE->getEffectiveSCEVType(AS->getType()) ==
       SE->getEffectiveSCEVType(BS->getType())) {
     unsigned BitWidth = SE->getTypeSizeInBits(AS->getType());
-    APInt AI(BitWidth, ASize);
+    APInt ASizeInt(BitWidth, ASize);
+    APInt BSizeInt(BitWidth, BSize);
+
+    // Compute the difference between the two pointers.
     const SCEV *BA = SE->getMinusSCEV(BS, AS);
-    if (AI.ule(SE->getUnsignedRange(BA).getUnsignedMin())) {
-      APInt BI(BitWidth, BSize);
-      const SCEV *AB = SE->getMinusSCEV(AS, BS);
-      if (BI.ule(SE->getUnsignedRange(AB).getUnsignedMin()))
-        return NoAlias;
-    }
+
+    // Test whether the difference is known to be great enough that memory of
+    // the given sizes don't overlap. This assumes that ASizeInt and BSizeInt
+    // are non-zero, which is special-cased above.
+    if (ASizeInt.ule(SE->getUnsignedRange(BA).getUnsignedMin()) &&
+        (-BSizeInt).uge(SE->getUnsignedRange(BA).getUnsignedMax()))
+      return NoAlias;
+
+    // Folding the subtraction while preserving range information can be tricky
+    // (because of INT_MIN, etc.); if the prior test failed, swap AS and BS
+    // and try again to see if things fold better that way.
+
+    // Compute the difference between the two pointers.
+    const SCEV *AB = SE->getMinusSCEV(AS, BS);
+
+    // Test whether the difference is known to be great enough that memory of
+    // the given sizes don't overlap. This assumes that ASizeInt and BSizeInt
+    // are non-zero, which is special-cased above.
+    if (BSizeInt.ule(SE->getUnsignedRange(AB).getUnsignedMin()) &&
+        (-ASizeInt).uge(SE->getUnsignedRange(AB).getUnsignedMax()))
+      return NoAlias;
   }
 
   // If ScalarEvolution can find an underlying object, form a new query.




From gohman at apple.com  Wed Jun 30 01:58:35 2010
From: gohman at apple.com (Dan Gohman)
Date: Wed, 30 Jun 2010 06:58:35 -0000
Subject: [llvm-commits] [llvm] r107256 -
	/llvm/trunk/lib/Analysis/ScalarEvolution.cpp
Message-ID: <20100630065835.DC94B2A6C12C@llvm.org>

Author: djg
Date: Wed Jun 30 01:58:35 2010
New Revision: 107256

URL: http://llvm.org/viewvc/llvm-project?rev=107256&view=rev
Log:
When computing a new ConservativeResult, intersect it with
the old one instead of replacing it, to be more precise.

Modified:
    llvm/trunk/lib/Analysis/ScalarEvolution.cpp

Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=107256&r1=107255&r2=107256&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Wed Jun 30 01:58:35 2010
@@ -2958,7 +2958,8 @@
       if (const SCEVConstant *C = dyn_cast<SCEVConstant>(AddRec->getStart()))
         if (!C->getValue()->isZero())
           ConservativeResult =
-            ConstantRange(C->getValue()->getValue(), APInt(BitWidth, 0));
+            ConservativeResult.intersectWith(
+              ConstantRange(C->getValue()->getValue(), APInt(BitWidth, 0)));
 
     // TODO: non-affine addrec
     if (AddRec->isAffine()) {




From gohman at apple.com  Wed Jun 30 02:16:37 2010
From: gohman at apple.com (Dan Gohman)
Date: Wed, 30 Jun 2010 07:16:37 -0000
Subject: [llvm-commits] [llvm] r107257 -
	/llvm/trunk/lib/Analysis/ScalarEvolution.cpp
Message-ID: <20100630071637.5E6EE2A6C12C@llvm.org>

Author: djg
Date: Wed Jun 30 02:16:37 2010
New Revision: 107257

URL: http://llvm.org/viewvc/llvm-project?rev=107257&view=rev
Log:
Improve ScalarEvolution's nsw and nuw preservation.

Modified:
    llvm/trunk/lib/Analysis/ScalarEvolution.cpp

Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=107257&r1=107256&r2=107257&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Wed Jun 30 02:16:37 2010
@@ -1552,9 +1552,11 @@
                                              AddRec->op_end());
       AddRecOps[0] = getAddExpr(LIOps);
 
-      // It's tempting to propagate NUW/NSW flags here, but nuw/nsw addition
-      // is not associative so this isn't necessarily safe.
-      const SCEV *NewRec = getAddRecExpr(AddRecOps, AddRecLoop);
+      // Build the new addrec. Propagate the NUW and NSW flags if both the
+      // outer add and the inner addrec are guaranteed to have no overflow.
+      const SCEV *NewRec = getAddRecExpr(AddRecOps, AddRecLoop,
+                                         HasNUW && AddRec->hasNoUnsignedWrap(),
+                                         HasNSW && AddRec->hasNoSignedWrap());
 
       // If all of the other operands were loop invariant, we are done.
       if (Ops.size() == 1) return NewRec;
@@ -1754,11 +1756,11 @@
       for (unsigned i = 0, e = AddRec->getNumOperands(); i != e; ++i)
         NewOps.push_back(getMulExpr(Scale, AddRec->getOperand(i)));
 
-      // It's tempting to propagate the NSW flag here, but nsw multiplication
-      // is not associative so this isn't necessarily safe.
+      // Build the new addrec. Propagate the NUW and NSW flags if both the
+      // outer mul and the inner addrec are guaranteed to have no overflow.
       const SCEV *NewRec = getAddRecExpr(NewOps, AddRec->getLoop(),
                                          HasNUW && AddRec->hasNoUnsignedWrap(),
-                                         /*HasNSW=*/false);
+                                         HasNSW && AddRec->hasNoSignedWrap());
 
       // If all of the other operands were loop invariant, we are done.
       if (Ops.size() == 1) return NewRec;
@@ -2758,15 +2760,49 @@
   return getUnknown(PN);
 }
 
+/// UseFlag - When creating an operator with operands L and R based on an
+/// LLVM IR instruction in basic block BB where the instruction has
+/// nsw, nuw, or inbounds, test whether the corresponding flag can be
+/// set for the resulting SCEV.
+static bool
+UseFlag(bool Flag, const SCEV *L, const SCEV *R, const Value *Inst) {
+  // If the flag is not set, don't use it. This is included here to reduce
+  // clutter in the callers.
+  if (!Flag)
+    return false;
+
+  // Determine the block which contains the instruction with the flag.
+  const Instruction *I = dyn_cast<Instruction>(Inst);
+  if (!I)
+    return false;
+  const BasicBlock *BB = I->getParent();
+
+  // Handle an easy case: test if exactly one of the operands is an addrec
+  // and that the instruction is trivially control-equivalent to the addrec's
+  // loop's header.
+  if (const SCEVAddRecExpr *AR = dyn_cast<SCEVAddRecExpr>(L)) {
+    if (!isa<SCEVAddRecExpr>(R) &&
+        AR->getLoop()->getHeader() == BB)
+      return true;
+  } else if (const SCEVAddRecExpr *AR = dyn_cast<SCEVAddRecExpr>(R)) {
+    if (AR->getLoop()->getHeader() == BB)
+      return true;
+  }
+
+  return false;
+}
+
 /// createNodeForGEP - Expand GEP instructions into add and multiply
 /// operations. This allows them to be analyzed by regular SCEV code.
 ///
 const SCEV *ScalarEvolution::createNodeForGEP(GEPOperator *GEP) {
 
-  // Don't transfer the inbounds flag from the GEP instruction to the
-  // Add expression, because the Instruction may be guarded by control
-  // flow and the no-overflow bits may not be valid for the expression in
-  // any context.
+  // Don't blindly transfer the inbounds flag from the GEP instruction to the
+  // Add expression, because the Instruction may be guarded by control flow
+  // and the no-overflow bits may not be valid for the expression in any
+  // context. However, in the special case where the GEP is in the loop header,
+  // we know it's trivially control-equivalent to any addrecs for that loop.
+  bool InBounds = GEP->isInBounds();
 
   const Type *IntPtrTy = getEffectiveSCEVType(GEP->getType());
   Value *Base = GEP->getOperand(0);
@@ -2783,23 +2819,49 @@
     if (const StructType *STy = dyn_cast<StructType>(*GTI++)) {
       // For a struct, add the member offset.
       unsigned FieldNo = cast<ConstantInt>(Index)->getZExtValue();
-      TotalOffset = getAddExpr(TotalOffset,
-                               getOffsetOfExpr(STy, FieldNo),
-                               /*HasNUW=*/false, /*HasNSW=*/false);
+      const SCEV *FieldOffset = getOffsetOfExpr(STy, FieldNo);
+
+      // Test if the GEP has the inbounds keyword and is control-equivalent
+      // to the addrec.
+      bool HasNUW = UseFlag(InBounds, TotalOffset, FieldOffset, GEP);
+
+      // Add the field offset to the running total offset.
+      TotalOffset = getAddExpr(TotalOffset, FieldOffset,
+                               HasNUW, /*HasNSW=*/false);
     } else {
       // For an array, add the element offset, explicitly scaled.
-      const SCEV *LocalOffset = getSCEV(Index);
+      const SCEV *ElementSize = getSizeOfExpr(*GTI);
+      const SCEV *IndexS = getSCEV(Index);
       // Getelementptr indices are signed.
-      LocalOffset = getTruncateOrSignExtend(LocalOffset, IntPtrTy);
-      // Lower "inbounds" GEPs to NSW arithmetic.
-      LocalOffset = getMulExpr(LocalOffset, getSizeOfExpr(*GTI),
-                               /*HasNUW=*/false, /*HasNSW=*/false);
+      IndexS = getTruncateOrSignExtend(IndexS, IntPtrTy);
+
+      // Test if the GEP has the inbounds keyword and is control-equivalent
+      // to the addrec.
+      bool HasNUW = UseFlag(InBounds, IndexS, ElementSize, GEP);
+
+      // Multiply the index by the element size to compute the element offset.
+      const SCEV *LocalOffset = getMulExpr(IndexS, ElementSize,
+                                           HasNUW, /*HasNSW=*/false);
+
+      // Test if the GEP has the inbounds keyword and is control-equivalent
+      // to the addrec.
+      HasNUW = UseFlag(InBounds, TotalOffset, LocalOffset, GEP);
+
+      // Add the element offset to the running total offset.
       TotalOffset = getAddExpr(TotalOffset, LocalOffset,
-                               /*HasNUW=*/false, /*HasNSW=*/false);
+                               HasNUW, /*HasNSW=*/false);
     }
   }
-  return getAddExpr(getSCEV(Base), TotalOffset,
-                    /*HasNUW=*/false, /*HasNSW=*/false);
+
+  // Get the SCEV for the GEP base.
+  const SCEV *BaseS = getSCEV(Base);
+
+  // Test if the GEP has the inbounds keyword and is control-equivalent
+  // to the addrec.
+  bool HasNUW = UseFlag(InBounds, BaseS, TotalOffset, GEP);
+
+  // Add the total offset from all the GEP indices to the base.
+  return getAddExpr(BaseS, TotalOffset, HasNUW, /*HasNSW=*/false);
 }
 
 /// GetMinTrailingZeros - Determine the minimum number of zero bits that S is
@@ -3191,18 +3253,30 @@
 
   Operator *U = cast<Operator>(V);
   switch (Opcode) {
-  case Instruction::Add:
+  case Instruction::Add: {
+    const SCEV *LHS = getSCEV(U->getOperand(0));
+    const SCEV *RHS = getSCEV(U->getOperand(1));
+
     // Don't transfer the NSW and NUW bits from the Add instruction to the
-    // Add expression, because the Instruction may be guarded by control
-    // flow and the no-overflow bits may not be valid for the expression in
-    // any context.
-    return getAddExpr(getSCEV(U->getOperand(0)),
-                      getSCEV(U->getOperand(1)));
-  case Instruction::Mul:
+    // Add expression unless we can prove that it's safe.
+    AddOperator *Add = cast<AddOperator>(U);
+    bool HasNUW = UseFlag(Add->hasNoUnsignedWrap(), LHS, RHS, Add);
+    bool HasNSW = UseFlag(Add->hasNoSignedWrap(), LHS, RHS, Add);
+
+    return getAddExpr(LHS, RHS, HasNUW, HasNSW);
+  }
+  case Instruction::Mul: {
+    const SCEV *LHS = getSCEV(U->getOperand(0));
+    const SCEV *RHS = getSCEV(U->getOperand(1));
+
     // Don't transfer the NSW and NUW bits from the Mul instruction to the
-    // Mul expression, as with Add.
-    return getMulExpr(getSCEV(U->getOperand(0)),
-                      getSCEV(U->getOperand(1)));
+    // Mul expression unless we can prove that it's safe.
+    MulOperator *Mul = cast<MulOperator>(U);
+    bool HasNUW = UseFlag(Mul->hasNoUnsignedWrap(), LHS, RHS, Mul);
+    bool HasNSW = UseFlag(Mul->hasNoSignedWrap(), LHS, RHS, Mul);
+
+    return getMulExpr(LHS, RHS, HasNUW, HasNSW);
+  }
   case Instruction::UDiv:
     return getUDivExpr(getSCEV(U->getOperand(0)),
                        getSCEV(U->getOperand(1)));




From gohman at apple.com  Wed Jun 30 02:17:47 2010
From: gohman at apple.com (Dan Gohman)
Date: Wed, 30 Jun 2010 07:17:47 -0000
Subject: [llvm-commits] [llvm] r107258 -
	/llvm/trunk/test/Analysis/ScalarEvolution/scev-aa.ll
Message-ID: <20100630071747.57C162A6C12C@llvm.org>

Author: djg
Date: Wed Jun 30 02:17:47 2010
New Revision: 107258

URL: http://llvm.org/viewvc/llvm-project?rev=107258&view=rev
Log:
Add a testcase for scev-aa's new capability.

Modified:
    llvm/trunk/test/Analysis/ScalarEvolution/scev-aa.ll

Modified: llvm/trunk/test/Analysis/ScalarEvolution/scev-aa.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/ScalarEvolution/scev-aa.ll?rev=107258&r1=107257&r2=107258&view=diff
==============================================================================
--- llvm/trunk/test/Analysis/ScalarEvolution/scev-aa.ll (original)
+++ llvm/trunk/test/Analysis/ScalarEvolution/scev-aa.ll Wed Jun 30 02:17:47 2010
@@ -1,8 +1,9 @@
 ; RUN: opt < %s -scev-aa -aa-eval -print-all-alias-modref-info \
 ; RUN:   |& FileCheck %s
 
-; At the time of this writing, -basicaa only misses the example of the form
-; A[i+(j+1)] != A[i+j], which can arise from multi-dimensional array references.
+; At the time of this writing, -basicaa misses the example of the form
+; A[i+(j+1)] != A[i+j], which can arise from multi-dimensional array references,
+; and the example of the form A[0] != A[i+1], where i+1 is known to be positive.
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64"
 
@@ -189,6 +190,26 @@
   ret void
 }
 
-; CHECK: 13 no alias responses
+; CHECK: Function: nonnegative: 2 pointers, 0 call sites
+; CHECK: NoAlias:  i64* %arrayidx, i64* %p
+
+define void @nonnegative(i64* %p) nounwind {
+entry:
+  br label %for.body
+
+for.body:                                         ; preds = %entry, %for.body
+  %i = phi i64 [ %inc, %for.body ], [ 0, %entry ] ; <i64> [#uses=2]
+  %inc = add nsw i64 %i, 1                         ; <i64> [#uses=2]
+  %arrayidx = getelementptr inbounds i64* %p, i64 %inc
+  store i64 0, i64* %arrayidx
+  %tmp6 = load i64* %p                            ; <i64> [#uses=1]
+  %cmp = icmp slt i64 %inc, %tmp6                 ; <i1> [#uses=1]
+  br i1 %cmp, label %for.body, label %for.end
+
+for.end:                                          ; preds = %for.body, %entry
+  ret void
+}
+
+; CHECK: 14 no alias responses
 ; CHECK: 26 may alias responses
 ; CHECK: 18 must alias responses




From ggreif at gmail.com  Wed Jun 30 04:14:26 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Wed, 30 Jun 2010 09:14:26 -0000
Subject: [llvm-commits] [llvm] r107269 -
	/llvm/trunk/lib/Transforms/Utils/AddrModeMatcher.cpp
Message-ID: <20100630091426.7AE0C2A6C12C@llvm.org>

Author: ggreif
Date: Wed Jun 30 04:14:26 2010
New Revision: 107269

URL: http://llvm.org/viewvc/llvm-project?rev=107269&view=rev
Log:
use getArgOperand instead of getOperand

Modified:
    llvm/trunk/lib/Transforms/Utils/AddrModeMatcher.cpp

Modified: llvm/trunk/lib/Transforms/Utils/AddrModeMatcher.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/AddrModeMatcher.cpp?rev=107269&r1=107268&r2=107269&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/AddrModeMatcher.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/AddrModeMatcher.cpp Wed Jun 30 04:14:26 2010
@@ -381,28 +381,28 @@
                                     const TargetLowering &TLI) {
   std::vector<InlineAsm::ConstraintInfo>
   Constraints = IA->ParseConstraints();
-  
-  unsigned ArgNo = CallInst::ArgOffset;   // ArgNo - The operand of the CallInst.
+
+  unsigned ArgNo = 0;   // The argument of the CallInst.
   for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
     TargetLowering::AsmOperandInfo OpInfo(Constraints[i]);
-    
+
     // Compute the value type for each operand.
     switch (OpInfo.Type) {
       case InlineAsm::isOutput:
         if (OpInfo.isIndirect)
-          OpInfo.CallOperandVal = CI->getOperand(ArgNo++);
+          OpInfo.CallOperandVal = CI->getArgOperand(ArgNo++);
         break;
       case InlineAsm::isInput:
-        OpInfo.CallOperandVal = CI->getOperand(ArgNo++);
+        OpInfo.CallOperandVal = CI->getArgOperand(ArgNo++);
         break;
       case InlineAsm::isClobber:
         // Nothing to do.
         break;
     }
-    
+
     // Compute the constraint code and ConstraintType to use.
     TLI.ComputeConstraintToUse(OpInfo, SDValue());
-    
+
     // If this asm operand is our Value*, and if it isn't an indirect memory
     // operand, we can't fold it!
     if (OpInfo.CallOperandVal == OpVal &&
@@ -410,7 +410,7 @@
          !OpInfo.isIndirect))
       return false;
   }
-  
+
   return true;
 }
 




From ggreif at gmail.com  Wed Jun 30 04:15:28 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Wed, 30 Jun 2010 09:15:28 -0000
Subject: [llvm-commits] [llvm] r107270 -
	/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp
Message-ID: <20100630091528.D69912A6C12C@llvm.org>

Author: ggreif
Date: Wed Jun 30 04:15:28 2010
New Revision: 107270

URL: http://llvm.org/viewvc/llvm-project?rev=107270&view=rev
Log:
use getArgOperand instead of getOperand

Modified:
    llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=107270&r1=107269&r2=107270&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Wed Jun 30 04:15:28 2010
@@ -559,7 +559,7 @@
       case Intrinsic::x86_sse2_storeu_pd:
       case Intrinsic::x86_sse2_storeu_dq:
       case Intrinsic::x86_sse2_storel_dq:
-        if (II->getOperand(1) == OperandVal)
+        if (II->getArgOperand(0) == OperandVal)
           isAddress = true;
         break;
     }
@@ -581,7 +581,7 @@
     case Intrinsic::x86_sse2_storeu_pd:
     case Intrinsic::x86_sse2_storeu_dq:
     case Intrinsic::x86_sse2_storel_dq:
-      AccessTy = II->getOperand(1)->getType();
+      AccessTy = II->getArgOperand(0)->getType();
       break;
     }
   }




From ggreif at gmail.com  Wed Jun 30 04:16:16 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Wed, 30 Jun 2010 09:16:16 -0000
Subject: [llvm-commits] [llvm] r107271 -
	/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp
Message-ID: <20100630091616.2F4882A6C12C@llvm.org>

Author: ggreif
Date: Wed Jun 30 04:16:16 2010
New Revision: 107271

URL: http://llvm.org/viewvc/llvm-project?rev=107271&view=rev
Log:
use getArgOperand instead of getOperand

Modified:
    llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=107271&r1=107270&r2=107271&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Wed Jun 30 04:16:16 2010
@@ -1373,7 +1373,7 @@
       // If the stored element is zero (common case), just store a null
       // constant.
       Constant *StoreVal;
-      if (ConstantInt *CI = dyn_cast<ConstantInt>(MI->getOperand(2))) {
+      if (ConstantInt *CI = dyn_cast<ConstantInt>(MI->getArgOperand(1))) {
         if (CI->isZero()) {
           StoreVal = Constant::getNullValue(EltTy);  // 0.0, null, 0, <0,0>
         } else {
@@ -1436,7 +1436,7 @@
       Value *Ops[] = {
         SROADest ? EltPtr : OtherElt,  // Dest ptr
         SROADest ? OtherElt : EltPtr,  // Src ptr
-        ConstantInt::get(MI->getOperand(3)->getType(), EltSize), // Size
+        ConstantInt::get(MI->getArgOperand(2)->getType(), EltSize), // Size
         // Align
         ConstantInt::get(Type::getInt32Ty(MI->getContext()), OtherEltAlign),
         MI->getVolatileCst()
@@ -1451,8 +1451,8 @@
     } else {
       assert(isa<MemSetInst>(MI));
       Value *Ops[] = {
-        EltPtr, MI->getOperand(2),  // Dest, Value,
-        ConstantInt::get(MI->getOperand(3)->getType(), EltSize), // Size
+        EltPtr, MI->getArgOperand(1),  // Dest, Value,
+        ConstantInt::get(MI->getArgOperand(2)->getType(), EltSize), // Size
         Zero,  // Align
         ConstantInt::get(Type::getInt1Ty(MI->getContext()), 0) // isVolatile
       };




From ggreif at gmail.com  Wed Jun 30 04:17:53 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Wed, 30 Jun 2010 09:17:53 -0000
Subject: [llvm-commits] [llvm] r107272 -
	/llvm/trunk/lib/Transforms/Scalar/GVN.cpp
Message-ID: <20100630091753.B1A352A6C12C@llvm.org>

Author: ggreif
Date: Wed Jun 30 04:17:53 2010
New Revision: 107272

URL: http://llvm.org/viewvc/llvm-project?rev=107272&view=rev
Log:
use getNumArgOperands instead of getNumOperands

Modified:
    llvm/trunk/lib/Transforms/Scalar/GVN.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=107272&r1=107271&r2=107272&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Wed Jun 30 04:17:53 2010
@@ -449,7 +449,7 @@
     if (local_dep.isDef()) {
       CallInst* local_cdep = cast<CallInst>(local_dep.getInst());
 
-      if (local_cdep->getNumOperands() != C->getNumOperands()) {
+      if (local_cdep->getNumArgOperands() != C->getNumArgOperands()) {
         valueNumbering[C] = nextValueNumber;
         return nextValueNumber++;
       }
@@ -506,7 +506,7 @@
       return nextValueNumber++;
     }
 
-    if (cdep->getNumOperands() != C->getNumOperands()) {
+    if (cdep->getNumArgOperands() != C->getNumArgOperands()) {
       valueNumbering[C] = nextValueNumber;
       return nextValueNumber++;
     }




From ggreif at gmail.com  Wed Jun 30 04:19:23 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Wed, 30 Jun 2010 09:19:23 -0000
Subject: [llvm-commits] [llvm] r107273 -
	/llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp
Message-ID: <20100630091923.667872A6C12C@llvm.org>

Author: ggreif
Date: Wed Jun 30 04:19:23 2010
New Revision: 107273

URL: http://llvm.org/viewvc/llvm-project?rev=107273&view=rev
Log:
use getArgOperand (corrected by CallInst::ArgOffset) instead of getOperand

Modified:
    llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp?rev=107273&r1=107272&r2=107273&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp Wed Jun 30 04:19:23 2010
@@ -548,7 +548,8 @@
     CI->eraseFromParent();
   }
   bool isFoldable(unsigned SizeCIOp, unsigned, bool) const {
-    if (ConstantInt *SizeCI = dyn_cast<ConstantInt>(CI->getOperand(SizeCIOp)))
+      if (ConstantInt *SizeCI = dyn_cast<ConstantInt>(CI->getArgOperand(SizeCIOp
+                                                        - CallInst::ArgOffset)))
       return SizeCI->isAllOnesValue();
     return false;
   }




From ggreif at gmail.com  Wed Jun 30 07:38:26 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Wed, 30 Jun 2010 12:38:26 -0000
Subject: [llvm-commits] [llvm] r107275 -
	/llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp
Message-ID: <20100630123826.A72CE2A6C12C@llvm.org>

Author: ggreif
Date: Wed Jun 30 07:38:26 2010
New Revision: 107275

URL: http://llvm.org/viewvc/llvm-project?rev=107275&view=rev
Log:
use getArgOperand (corrected by CallInst::ArgOffset) instead of getOperand

Modified:
    llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp

Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp?rev=107275&r1=107274&r2=107275&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp Wed Jun 30 07:38:26 2010
@@ -772,13 +772,13 @@
     NewInstruction = IC->ReplaceInstUsesWith(*CI, With);
   }
   bool isFoldable(unsigned SizeCIOp, unsigned SizeArgOp, bool isString) const {
-    if (ConstantInt *SizeCI = dyn_cast<ConstantInt>(CI->getOperand(SizeCIOp))) {
+    if (ConstantInt *SizeCI = dyn_cast<ConstantInt>(CI->getArgOperand(SizeCIOp - CallInst::ArgOffset))) {
       if (SizeCI->isAllOnesValue())
         return true;
       if (isString)
         return SizeCI->getZExtValue() >=
-               GetStringLength(CI->getOperand(SizeArgOp));
-      if (ConstantInt *Arg = dyn_cast<ConstantInt>(CI->getOperand(SizeArgOp)))
+               GetStringLength(CI->getArgOperand(SizeArgOp - CallInst::ArgOffset));
+      if (ConstantInt *Arg = dyn_cast<ConstantInt>(CI->getArgOperand(SizeArgOp - CallInst::ArgOffset)))
         return SizeCI->getZExtValue() >= Arg->getZExtValue();
     }
     return false;




From ggreif at gmail.com  Wed Jun 30 07:39:23 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Wed, 30 Jun 2010 12:39:23 -0000
Subject: [llvm-commits] [llvm] r107276 -
	/llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp
Message-ID: <20100630123923.8E6362A6C12C@llvm.org>

Author: ggreif
Date: Wed Jun 30 07:39:23 2010
New Revision: 107276

URL: http://llvm.org/viewvc/llvm-project?rev=107276&view=rev
Log:
use CallSite::arg_end instead of CallInst::op_end

Modified:
    llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp

Modified: llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp?rev=107276&r1=107275&r2=107276&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/IntrinsicLowering.cpp Wed Jun 30 07:39:23 2010
@@ -375,7 +375,7 @@
 
   case Intrinsic::siglongjmp: {
     // Insert the call to abort
-    ReplaceCallWith("abort", CI, CI->op_end(), CI->op_end(), 
+    ReplaceCallWith("abort", CI, CS.arg_end(), CS.arg_end(), 
                     Type::getVoidTy(Context));
     break;
   }




From ggreif at gmail.com  Wed Jun 30 07:40:35 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Wed, 30 Jun 2010 12:40:35 -0000
Subject: [llvm-commits] [llvm] r107277 -
	/llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp
Message-ID: <20100630124035.BA7F72A6C12C@llvm.org>

Author: ggreif
Date: Wed Jun 30 07:40:35 2010
New Revision: 107277

URL: http://llvm.org/viewvc/llvm-project?rev=107277&view=rev
Log:
use ArgOperand API

Modified:
    llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp

Modified: llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp?rev=107277&r1=107276&r2=107277&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp (original)
+++ llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp Wed Jun 30 07:40:35 2010
@@ -268,8 +268,8 @@
   if (Declare) {
     while (!Declare->use_empty()) {
       CallInst *CI = cast<CallInst>(Declare->use_back());
-      Value *Arg1 = CI->getOperand(1);
-      Value *Arg2 = CI->getOperand(2);
+      Value *Arg1 = CI->getArgOperand(0);
+      Value *Arg2 = CI->getArgOperand(1);
       assert(CI->use_empty() && "llvm.dbg intrinsic should have void result");
       CI->eraseFromParent();
       if (Arg1->use_empty()) {




From ggreif at gmail.com  Wed Jun 30 07:42:43 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Wed, 30 Jun 2010 12:42:43 -0000
Subject: [llvm-commits] [llvm] r107278 -
	/llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp
Message-ID: <20100630124243.675BE2A6C12C@llvm.org>

Author: ggreif
Date: Wed Jun 30 07:42:43 2010
New Revision: 107278

URL: http://llvm.org/viewvc/llvm-project?rev=107278&view=rev
Log:
use ArgOperand API

Modified:
    llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp?rev=107278&r1=107277&r2=107278&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/SimplifyLibCalls.cpp Wed Jun 30 07:42:43 2010
@@ -348,7 +348,7 @@
       return ConstantInt::get(CI->getType(), 0);
 
     if (TD && Length == 1) // strncmp(x,y,1) -> memcmp(x,y,1)
-      return EmitMemCmp(Str1P, Str2P, CI->getOperand(3), B, TD);
+      return EmitMemCmp(Str1P, Str2P, CI->getArgOperand(2), B, TD);
 
     std::string Str1, Str2;
     bool HasStr1 = GetConstantStringInfo(Str1P, Str1);
@@ -526,9 +526,9 @@
       return B.CreateBitCast(CI->getArgOperand(0), CI->getType());
 
     // fold strstr(a, b) == a -> strncmp(a, b, strlen(b)) == 0
-    if (TD && IsOnlyUsedInEqualityComparison(CI, CI->getOperand(1))) {
-      Value *StrLen = EmitStrLen(CI->getOperand(2), B, TD);
-      Value *StrNCmp = EmitStrNCmp(CI->getOperand(1), CI->getOperand(2),
+    if (TD && IsOnlyUsedInEqualityComparison(CI, CI->getArgOperand(0))) {
+      Value *StrLen = EmitStrLen(CI->getArgOperand(1), B, TD);
+      Value *StrNCmp = EmitStrNCmp(CI->getArgOperand(0), CI->getArgOperand(1),
                                    StrLen, B, TD);
       for (Value::use_iterator UI = CI->use_begin(), UE = CI->use_end();
            UI != UE; ) {
@@ -994,7 +994,7 @@
 
     // Optimize specific format strings.
     // printf("%c", chr) --> putchar(chr)
-    if (FormatStr == "%c" && CI->getNumOperands() > 2 &&
+    if (FormatStr == "%c" && CI->getNumArgOperands() > 1 &&
         CI->getArgOperand(1)->getType()->isIntegerTy()) {
       Value *Res = EmitPutChar(CI->getArgOperand(1), B, TD);
 
@@ -1003,7 +1003,7 @@
     }
 
     // printf("%s\n", str) --> puts(str)
-    if (FormatStr == "%s\n" && CI->getNumOperands() > 2 &&
+    if (FormatStr == "%s\n" && CI->getNumArgOperands() > 1 &&
         CI->getArgOperand(1)->getType()->isPointerTy() &&
         CI->use_empty()) {
       EmitPutS(CI->getArgOperand(1), B, TD);
@@ -1031,7 +1031,7 @@
       return 0;
 
     // If we just have a format string (nothing else crazy) transform it.
-    if (CI->getNumOperands() == 3) {
+    if (CI->getNumArgOperands() == 2) {
       // Make sure there's no % in the constant array.  We could try to handle
       // %% -> % in the future if we cared.
       for (unsigned i = 0, e = FormatStr.size(); i != e; ++i)
@@ -1050,7 +1050,8 @@
 
     // The remaining optimizations require the format string to be "%s" or "%c"
     // and have an extra operand.
-    if (FormatStr.size() != 2 || FormatStr[0] != '%' || CI->getNumOperands() <4)
+    if (FormatStr.size() != 2 || FormatStr[0] != '%' ||
+        CI->getNumArgOperands() < 3)
       return 0;
 
     // Decode the second character of the format string.
@@ -1166,7 +1167,7 @@
       return 0;
 
     // fprintf(F, "foo") --> fwrite("foo", 3, 1, F)
-    if (CI->getNumOperands() == 3) {
+    if (CI->getNumArgOperands() == 2) {
       for (unsigned i = 0, e = FormatStr.size(); i != e; ++i)
         if (FormatStr[i] == '%')  // Could handle %% -> % if we cared.
           return 0; // We found a format specifier.
@@ -1183,7 +1184,8 @@
 
     // The remaining optimizations require the format string to be "%s" or "%c"
     // and have an extra operand.
-    if (FormatStr.size() != 2 || FormatStr[0] != '%' || CI->getNumOperands() <4)
+    if (FormatStr.size() != 2 || FormatStr[0] != '%' ||
+        CI->getNumArgOperands() < 3)
       return 0;
 
     // Decode the second character of the format string.




From ggreif at gmail.com  Wed Jun 30 07:55:46 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Wed, 30 Jun 2010 12:55:46 -0000
Subject: [llvm-commits] [llvm] r107279 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Message-ID: <20100630125546.430132A6C12C@llvm.org>

Author: ggreif
Date: Wed Jun 30 07:55:46 2010
New Revision: 107279

URL: http://llvm.org/viewvc/llvm-project?rev=107279&view=rev
Log:
use ArgOperand API

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=107279&r1=107278&r2=107279&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Wed Jun 30 07:55:46 2010
@@ -4740,7 +4740,7 @@
 /// lowered like a normal call.
 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
   // Verify that the prototype makes sense.  int memcmp(void*,void*,size_t)
-  if (I.getNumOperands() != 4)
+  if (I.getNumArgOperands() != 3)
     return false;
 
   const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
@@ -4839,7 +4839,7 @@
     if (!F->hasLocalLinkage() && F->hasName()) {
       StringRef Name = F->getName();
       if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") {
-        if (I.getNumOperands() == 3 &&   // Basic sanity checks.
+        if (I.getNumArgOperands() == 2 &&   // Basic sanity checks.
             I.getArgOperand(0)->getType()->isFloatingPointTy() &&
             I.getType() == I.getArgOperand(0)->getType() &&
             I.getType() == I.getArgOperand(1)->getType()) {
@@ -4850,7 +4850,7 @@
           return;
         }
       } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") {
-        if (I.getNumOperands() == 2 &&   // Basic sanity checks.
+        if (I.getNumArgOperands() == 1 &&   // Basic sanity checks.
             I.getArgOperand(0)->getType()->isFloatingPointTy() &&
             I.getType() == I.getArgOperand(0)->getType()) {
           SDValue Tmp = getValue(I.getArgOperand(0));
@@ -4859,7 +4859,7 @@
           return;
         }
       } else if (Name == "sin" || Name == "sinf" || Name == "sinl") {
-        if (I.getNumOperands() == 2 &&   // Basic sanity checks.
+        if (I.getNumArgOperands() == 1 &&   // Basic sanity checks.
             I.getArgOperand(0)->getType()->isFloatingPointTy() &&
             I.getType() == I.getArgOperand(0)->getType() &&
             I.onlyReadsMemory()) {
@@ -4869,7 +4869,7 @@
           return;
         }
       } else if (Name == "cos" || Name == "cosf" || Name == "cosl") {
-        if (I.getNumOperands() == 2 &&   // Basic sanity checks.
+        if (I.getNumArgOperands() == 1 &&   // Basic sanity checks.
             I.getArgOperand(0)->getType()->isFloatingPointTy() &&
             I.getType() == I.getArgOperand(0)->getType() &&
             I.onlyReadsMemory()) {
@@ -4879,7 +4879,7 @@
           return;
         }
       } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") {
-        if (I.getNumOperands() == 2 &&   // Basic sanity checks.
+        if (I.getNumArgOperands() == 1 &&   // Basic sanity checks.
             I.getArgOperand(0)->getType()->isFloatingPointTy() &&
             I.getType() == I.getArgOperand(0)->getType() &&
             I.onlyReadsMemory()) {




From ggreif at gmail.com  Wed Jun 30 08:03:38 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Wed, 30 Jun 2010 13:03:38 -0000
Subject: [llvm-commits] [llvm] r107280 -
	/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Message-ID: <20100630130338.404A22A6C12C@llvm.org>

Author: ggreif
Date: Wed Jun 30 08:03:37 2010
New Revision: 107280

URL: http://llvm.org/viewvc/llvm-project?rev=107280&view=rev
Log:
use ArgOperand API

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=107280&r1=107279&r2=107280&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Jun 30 08:03:37 2010
@@ -10022,7 +10022,7 @@
   // so don't worry about this.
 
   // Verify this is a simple bswap.
-  if (CI->getNumOperands() != 2 ||
+  if (CI->getNumArgOperands() != 1 ||
       CI->getType() != CI->getArgOperand(0)->getType() ||
       !CI->getType()->isIntegerTy())
     return false;




From peter at pcc.me.uk  Wed Jun 30 08:42:11 2010
From: peter at pcc.me.uk (Peter Collingbourne)
Date: Wed, 30 Jun 2010 14:42:11 +0100
Subject: [llvm-commits] [PATCH] (try 2) Add an atomic lowering pass
In-Reply-To: <20100623233241.GA20055@pcc.me.uk>
References: <20100622201233.GA2808@pcc.me.uk> <4C21B6F3.2080202@free.fr>
	<20100623233241.GA20055@pcc.me.uk>
Message-ID: <20100630134211.GA14371@pcc.me.uk>

Hi,

Here is the new version of the patch.  I updated it to use
getArgOperand and fixed a coding style issue (header ordering).

Thanks,

On Thu, Jun 24, 2010 at 12:32:42AM +0100, Peter Collingbourne wrote:
> Hi Duncan,
> 
> On Wed, Jun 23, 2010 at 09:25:39AM +0200, Duncan Sands wrote:
> > Hi Peter,
> > 
> > > My main motivation for the single-thread lowering is to be able to run
> > > code that uses these intrinsics in the KLEE symbolic execution engine
> > > but I imagine it could have other uses such as a whole-program LTO
> > > that lowers atomic operations to more efficient non-atomic operations
> > > when it is known to be safe to do so.
> > 
> > instead, how about writing an LLVM IR pass that turns atomic intrinsics into
> > non-atomic equivalent LLVM IR?
> 
> Yes, that seems more sensible.  I refactored the lowering into a pass
> and added the remaining intrinsics (see attached patch).  I'll commit
> this if approved.
> 
> I wonder if IntrinsicLowering should also be made into a pass, for
> consistency with the other lowering passes.
> 
> > Finally, I guess even "single threaded" code
> > may have a use for some atomic operations if it makes use of signal handlers.
> 
> Yes, good point.  Perhaps "non-preemptible" is better terminology
> which is what I used in the new patch.

-- 
Peter
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From ggreif at gmail.com  Wed Jun 30 08:45:50 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Wed, 30 Jun 2010 13:45:50 -0000
Subject: [llvm-commits] [llvm] r107282 -
 /llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
Message-ID: <20100630134550.780402A6C12C@llvm.org>

Author: ggreif
Date: Wed Jun 30 08:45:50 2010
New Revision: 107282

URL: http://llvm.org/viewvc/llvm-project?rev=107282&view=rev
Log:
use ArgOperand API

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp?rev=107282&r1=107281&r2=107282&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp Wed Jun 30 08:45:50 2010
@@ -215,18 +215,18 @@
   // Gather all the type infos for this landing pad and pass them along to
   // MachineModuleInfo.
   std::vector<const GlobalVariable *> TyInfo;
-  unsigned N = I.getNumOperands();
+  unsigned N = I.getNumArgOperands();
 
-  for (unsigned i = N - 1; i > 2; --i) {
-    if (const ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(i))) {
+  for (unsigned i = N - 1; i > 1; --i) {
+    if (const ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(i))) {
       unsigned FilterLength = CI->getZExtValue();
       unsigned FirstCatch = i + FilterLength + !FilterLength;
-      assert (FirstCatch <= N && "Invalid filter length");
+      assert(FirstCatch <= N && "Invalid filter length");
 
       if (FirstCatch < N) {
         TyInfo.reserve(N - FirstCatch);
         for (unsigned j = FirstCatch; j < N; ++j)
-          TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
+          TyInfo.push_back(ExtractTypeInfo(I.getArgOperand(j)));
         MMI->addCatchTypeInfo(MBB, TyInfo);
         TyInfo.clear();
       }
@@ -238,7 +238,7 @@
         // Filter.
         TyInfo.reserve(FilterLength - 1);
         for (unsigned j = i + 1; j < FirstCatch; ++j)
-          TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
+          TyInfo.push_back(ExtractTypeInfo(I.getArgOperand(j)));
         MMI->addFilterTypeInfo(MBB, TyInfo);
         TyInfo.clear();
       }
@@ -247,10 +247,10 @@
     }
   }
 
-  if (N > 3) {
-    TyInfo.reserve(N - 3);
-    for (unsigned j = 3; j < N; ++j)
-      TyInfo.push_back(ExtractTypeInfo(I.getOperand(j)));
+  if (N > 2) {
+    TyInfo.reserve(N - 2);
+    for (unsigned j = 2; j < N; ++j)
+      TyInfo.push_back(ExtractTypeInfo(I.getArgOperand(j)));
     MMI->addCatchTypeInfo(MBB, TyInfo);
   }
 }




From espindola at google.com  Wed Jun 30 09:27:55 2010
From: espindola at google.com (Rafael Espindola)
Date: Wed, 30 Jun 2010 10:27:55 -0400
Subject: [llvm-commits] [patch] Mostly mechanical removal of
	getPhysicalRegisterRegClass.patch
In-Reply-To: <181DFFDD-2A43-43D3-9CF3-B7054973D60E@apple.com>
References: <AANLkTilqt5y4NglQZbWCS7S7jTdaybAvxWQD1-RqbhuK@mail.gmail.com>
	<D707A8E3-C6A1-4FD2-8DB8-FA88FC917365@2pi.dk>
	<AANLkTikDwVDsbrtjOTHmvi0U2OrJ6yjzqyI56d2-HGnm@mail.gmail.com>
	<AEFF279C-8A23-4753-A4A6-89640224C297@2pi.dk>
	<AANLkTimgBUUcE2-sTG0Qps20tS8qIh01LB61ABYZuY9e@mail.gmail.com>
	<EFEFA155-7FBA-4942-B731-575ABCD97A83@2pi.dk>
	<AANLkTinvjuW8OuHxExMJECtbVAd1GqyqFAX1JT5IM86-@mail.gmail.com>
	<AANLkTimv2smH65TcgkCg9oiuxTjE6yS13tfd3yLo9wGG@mail.gmail.com>
	<AB82423F-0FCC-4038-B5C2-1F9FF6E4D838@2pi.dk>
	<181DFFDD-2A43-43D3-9CF3-B7054973D60E@apple.com>
Message-ID: <AANLkTik1Rrc_UQHdXj4669CYEBfKiuzhNmbNZncHsmPJ@mail.gmail.com>

> I agree with Jakob. There is the job of domain crossing fix up pass.

I can give NEONMoveFix a try. Is early next week OK?

> Evan

Cheers,
-- 
Rafael ?vila de Esp?ndola



From criswell at uiuc.edu  Wed Jun 30 09:30:22 2010
From: criswell at uiuc.edu (John Criswell)
Date: Wed, 30 Jun 2010 14:30:22 -0000
Subject: [llvm-commits] [poolalloc] r107283 - in /poolalloc/trunk:
 include/poolalloc/PoolAllocate.h lib/PoolAllocate/PoolAllocate.cpp
Message-ID: <20100630143022.D2F462A6C12C@llvm.org>

Author: criswell
Date: Wed Jun 30 09:30:22 2010
New Revision: 107283

URL: http://llvm.org/viewvc/llvm-project?rev=107283&view=rev
Log:
Added more FIXME comments from code review.
Improved some of the formatting issues.

Modified:
    poolalloc/trunk/include/poolalloc/PoolAllocate.h
    poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp

Modified: poolalloc/trunk/include/poolalloc/PoolAllocate.h
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/poolalloc/PoolAllocate.h?rev=107283&r1=107282&r2=107283&view=diff
==============================================================================
--- poolalloc/trunk/include/poolalloc/PoolAllocate.h (original)
+++ poolalloc/trunk/include/poolalloc/PoolAllocate.h Wed Jun 30 09:30:22 2010
@@ -88,6 +88,8 @@
     /// DSNode.  Note: This does not necessarily include pool arguments that are
     /// passed in because of indirect function calls that are not used in the
     /// function.
+    /// FIXME: This comment should clearly describe which pools are and are not
+    ///        in this data structure.
     std::map<const DSNode*, Value*> PoolDescriptors;
 
     // Reverse mapping for PoolDescriptors, needed by TPPA

Modified: poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp?rev=107283&r1=107282&r2=107283&view=diff
==============================================================================
--- poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp (original)
+++ poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp Wed Jun 30 09:30:22 2010
@@ -216,6 +216,11 @@
     }
   }
 
+  //
+  // FIXME: Make name more descriptive and explain, in a comment here, what this
+  //        code is trying to do (namely, avoid optimizations for performance
+  //        overhead measurements?).
+  //
   if (CurHeuristic->IsRealHeuristic())
     MicroOptimizePoolCalls();
 
@@ -350,6 +355,8 @@
   }
 }
 
+/// FIXME: Should these be in the pooloptimize pass?
+///
 /// MicroOptimizePoolCalls - Apply any microoptimizations to calls to pool
 /// allocation function calls that we can.  This runs after the whole program
 /// has been transformed.
@@ -449,6 +456,7 @@
 
   //
   // Mark the returned node as needing to be passed in.
+  // FIXME: We should not do this for main().
   //
   if (DSNode *RetNode = G->getReturnNodeFor(F).getNode())
     RetNode->markReachableNodes(MarkedNodes);
@@ -469,7 +477,7 @@
   //
   // FIXME:
   //  1) PassAllArguments seems to be ignored here.  Why is that?
-  //  2) Why is the heap node check part of the PassAllArguments check?
+  //  2) Should the heap node check be part of the PassAllArguments check?
   //  3) SAFECode probably needs to pass the pool even if it's not a heap node.
   //     We should probably just do what the heuristic tells us to do.
   //
@@ -518,12 +526,15 @@
   if (G->node_begin() == G->node_end()) return 0;
     
   FuncInfo &FI = *getFuncInfo(F);
+
+  // No need to clone if no pools need to be passed in!
   if (FI.ArgNodes.empty())
-    return 0;           // No need to clone if no pools need to be passed in!
+    return 0;
 
   // Update statistics..
   NumArgsAdded += FI.ArgNodes.size();
-  if (MaxArgsAdded < FI.ArgNodes.size()) MaxArgsAdded = FI.ArgNodes.size();
+  if (MaxArgsAdded < FI.ArgNodes.size())
+    MaxArgsAdded = FI.ArgNodes.size();
   ++NumCloned;
  
   //
@@ -539,7 +550,12 @@
   // Create the new function prototype
   FunctionType *FuncTy = FunctionType::get(OldFuncTy->getReturnType(), ArgTys,
                                            OldFuncTy->isVarArg());
+
+  //
+  // FIXME: Can probably add new function to module during creation
+  //
   // Create the new function...
+  //
   Function *New = Function::Create(FuncTy, Function::InternalLinkage, F.getName());
   New->copyAttributesFrom(&F);
   F.getParent()->getFunctionList().insert(&F, New);
@@ -554,9 +570,15 @@
     PoolDescriptors[FI.ArgNodes[i]] = NI;
   }
 
+  //
   // Map the existing arguments of the old function to the corresponding
   // arguments of the new function, and copy over the names.
+  //
+  //
   DenseMap<const Value*, Value*> ValueMap;
+  // FIXME: Remove use of SAFECodeEnabled flag
+  // FIXME: Is FI.ValueMap empty?  We should put an assert to verify that it
+  //        is.
   if (SAFECodeEnabled)
     for (std::map<const Value*, Value*>::iterator I = FI.ValueMap.begin(),
            E = FI.ValueMap.end(); I != E; ++I)
@@ -581,6 +603,9 @@
     NewToOldValueMap.insert(std::make_pair(I->second, I->first));
 
   //
+  // FIXME: File a bug report for CloneFunctionInto; it should take care of
+  //        this mess for us.  Also check whether it does it correctly.
+  //
   // The cloned function will have its function attributes set more or less
   // correctly at this point.  However, it will not have its parameter
   // attributes set correctly.  We need to go through each argument in the
@@ -619,8 +644,8 @@
 //
 // FIXME: Update comment
 //
-// FIXME: Global pools should probably be initialized by a global ctor instead of by
-//        main().
+// FIXME: Global pools should probably be initialized by a global ctor instead
+//        of by main().
 //
 // SetupGlobalPools - Create global pools for all DSNodes in the globals graph
 // which contain heap objects.  If a global variable points to a piece of memory
@@ -867,6 +892,10 @@
        I != E;
        ++I){
     //
+    // FIXME: Don't do SAFECode specific behavior here; follow the heuristic.
+    // FIXME: Are there nodes which don't have the heap flag localally but have
+    //        it set in the globals graph?
+    //
     // Only the following nodes are pool allocated:
     //  1) Heap nodes
     //  2) Array nodes when bounds checking is enabled.
@@ -874,7 +903,8 @@
     //
     DSNode *N = I;
     if ((N->isHeapNode()) || (BoundsChecksEnabled && (N->isArrayNode())) ||
-    	(GlobalsGraphNodeMapping.count(N) && GlobalsGraphNodeMapping[N].getNode()->isHeapNode())) {
+    	(GlobalsGraphNodeMapping.count(N) &&
+       GlobalsGraphNodeMapping[N].getNode()->isHeapNode())) {
       if (GlobalsGraphNodeMapping.count(N)) {
         // If it is a global pool, set up the pool descriptor appropriately.
         DSNode *GGN = GlobalsGraphNodeMapping[N].getNode();




From baldrick at free.fr  Wed Jun 30 09:49:12 2010
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 30 Jun 2010 16:49:12 +0200
Subject: [llvm-commits] [llvm] r107199 -
	/llvm/trunk/include/llvm/ADT/SmallPtrSet.h
In-Reply-To: <1D0E2A71-F497-4894-9481-44D35EB4BB8E@2pi.dk>
References: <20100629200534.8EAB22A6C12C@llvm.org>
	<1D0E2A71-F497-4894-9481-44D35EB4BB8E@2pi.dk>
Message-ID: <4C2B5968.1040608@free.fr>

Hi Jakob,

>> NextPowerOfTwo was already used to ensure that SmallSizePowTwo is a power
>> of two, no need to do it a second time (NextPowerOfTwo is idempotent).
>
> No it isn't.
>
> Ignoring overflow, NextPowerOfTwo(x) is always strictly greater than x.

are you sure?  C++ templates make my head hurt, but as far as I can see it
works as follows.  Suppose N is a power of two, then the definition

   template<unsigned N>
   struct NextPowerOfTwo {
     enum { Val = NextPowerOfTwoH<N, (N&(N-1)) == 0>::Val };
   };

gives [since the condition (N&(N-1)) == 0 evaluates to true]

   struct NextPowerOfTwo {
   enum { Val = NextPowerOfTwoH<N, true>::Val };
   };

Since NextPowerOfTwoH<N, true> is defined by

   template<unsigned N, bool isPowerTwo>
   struct NextPowerOfTwoH {
     enum { Val = N };
   };

it looks to me like you get Val set to N, and thus the result is N.

Ciao,

Duncan.


From criswell at uiuc.edu  Wed Jun 30 09:55:41 2010
From: criswell at uiuc.edu (John Criswell)
Date: Wed, 30 Jun 2010 14:55:41 -0000
Subject: [llvm-commits] [poolalloc] r107284 -
	/poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp
Message-ID: <20100630145541.DBA412A6C12C@llvm.org>

Author: criswell
Date: Wed Jun 30 09:55:41 2010
New Revision: 107284

URL: http://llvm.org/viewvc/llvm-project?rev=107284&view=rev
Log:
Proactively modified code to avert a potential iterator invalidation error.

Modified:
    poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp

Modified: poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp?rev=107284&r1=107283&r2=107284&view=diff
==============================================================================
--- poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp (original)
+++ poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp Wed Jun 30 09:55:41 2010
@@ -143,23 +143,49 @@
   std::map<Function*, Function*> FuncMap;
 
   //
+  // Functions that require pool handles to be passed in as parameters will
+  // need to be cloned.  Scan through the set of all functions and record which
+  // ones need to be cloned.
+  //
+  // We record the list of functions to clone and then clone them to avoid
+  // iterator invalidation errors (creating a function clone adds a function to
+  // the set of functions in a Module).  This may be a little slower, but
+  // random memory errors are a pain to debug.
+  //
+  std::vector<Function *> FunctionsToClone;
+  for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I) {
+    if (!I->isDeclaration() && Graphs->hasDSGraph(*I)) {
+      FunctionsToClone.push_back (I);
+    }
+  }
+
+  //
   // Now clone a function using the pool arg list obtained in the previous
   // pass over the modules.  Loop over only the function initially in the
-  // program, don't traverse newly added ones.  If the function needs new
+  // program; don't traverse newly added ones.  If the function needs new
   // arguments, make its clone.
   //
-  // FIXME: Can the code below invalidate the function iterator?
   // FIXME: Should use a isClone() method.
   //
   std::set<Function*> ClonedFunctions;
-  for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I)
-    if (!I->isDeclaration() && !ClonedFunctions.count(I) &&
-        Graphs->hasDSGraph(*I))
-      if (Function *Clone = MakeFunctionClone(*I)) {
-        FuncMap[I] = Clone;
-        ClonedFunctions.insert(Clone);
-      }
+  while (FunctionsToClone.size()) {
+    //
+    // Remove a function from the list of functions to clone.
+    //
+    Function * Original = FunctionsToClone.back();
+    FunctionsToClone.pop_back ();
+
+    //
+    // Clone the function.  Record a pointer to the new clone if one was
+    // created.
+    //
+    if (Function *Clone = MakeFunctionClone(*Original)) {
+      FuncMap[Original] = Clone;
+      ClonedFunctions.insert(Clone);
+    }
+  }
   
+  //
   // Now that all call targets are available, rewrite the function bodies of the
   // clones or the original function (if the original has no clone).
   //
@@ -452,14 +478,13 @@
         }
       }
     }
-  }
 
-  //
-  // Mark the returned node as needing to be passed in.
-  // FIXME: We should not do this for main().
-  //
-  if (DSNode *RetNode = G->getReturnNodeFor(F).getNode())
-    RetNode->markReachableNodes(MarkedNodes);
+    //
+    // Mark the returned node as needing to be passed in.
+    //
+    if (DSNode *RetNode = G->getReturnNodeFor(F).getNode())
+      RetNode->markReachableNodes(MarkedNodes);
+  }
 
   //
   // Calculate which DSNodes are reachable from globals.  If a node is reachable




From stoklund at 2pi.dk  Wed Jun 30 10:02:24 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Wed, 30 Jun 2010 08:02:24 -0700
Subject: [llvm-commits] [llvm] r107199 -
	/llvm/trunk/include/llvm/ADT/SmallPtrSet.h
In-Reply-To: <4C2B5968.1040608@free.fr>
References: <20100629200534.8EAB22A6C12C@llvm.org>
	<1D0E2A71-F497-4894-9481-44D35EB4BB8E@2pi.dk>
	<4C2B5968.1040608@free.fr>
Message-ID: <EA85BEB7-3B1D-4114-A0FD-ABE5C374908B@2pi.dk>


On Jun 30, 2010, at 7:49 AM, Duncan Sands wrote:

> Hi Jakob,
> 
>>> NextPowerOfTwo was already used to ensure that SmallSizePowTwo is a power
>>> of two, no need to do it a second time (NextPowerOfTwo is idempotent).
>> 
>> No it isn't.
>> 
>> Ignoring overflow, NextPowerOfTwo(x) is always strictly greater than x.
> 
> are you sure?  C++ templates make my head hurt, but as far as I can see it
> works as follows.

Oh wait, there's a template?

I was talking about the function in MathExtras.h:

/// NextPowerOf2 - Returns the next power of two (in 64-bits)
/// that is strictly greater than A.  Returns zero on overflow.
static inline uint64_t NextPowerOf2(uint64_t A) {
  A |= (A >> 1);
  A |= (A >> 2);
  A |= (A >> 4);
  A |= (A >> 8);
  A |= (A >> 16);
  A |= (A >> 32);
  return A + 1;
}

You are right, the template is idempotent.

Clearly the meaning of the word 'next' is up for debate.

/jakob

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From baldrick at free.fr  Wed Jun 30 10:02:37 2010
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 30 Jun 2010 15:02:37 -0000
Subject: [llvm-commits] [llvm] r107285 - in /llvm/trunk:
 include/llvm/ADT/SmallPtrSet.h lib/Support/SmallPtrSet.cpp
Message-ID: <20100630150237.737722A6C12C@llvm.org>

Author: baldrick
Date: Wed Jun 30 10:02:37 2010
New Revision: 107285

URL: http://llvm.org/viewvc/llvm-project?rev=107285&view=rev
Log:
Rather than giving SmallPtrSetImpl a member field SmallArray which is magically
replaced by a bigger array in SmallPtrSet (by overridding it), instead just use a
pointer to the start of the storage, and have SmallPtrSet pass in the value to use.
This has the disadvantage that SmallPtrSet becomes bigger by one pointer.  It has
the advantage that it no longer uses tricky C++ rules, and is clearly correct while
I'm not sure the previous version was.  This was inspired by g++-4.6 pointing out
that SmallPtrSetImpl was writing off the end of SmallArray, which it was.  Since
SmallArray is replaced with a bigger array in SmallPtrSet, the write was still to
valid memory.  But it was writing off the end of the declared array type - sounds
kind of dubious to me, like it sounded dubious to g++-4.6.  Maybe g++-4.6 is wrong
and this construct is perfectly valid and correctly compiled by all compilers, but
I think it is better to avoid the whole can of worms by avoiding this construct.

Modified:
    llvm/trunk/include/llvm/ADT/SmallPtrSet.h
    llvm/trunk/lib/Support/SmallPtrSet.cpp

Modified: llvm/trunk/include/llvm/ADT/SmallPtrSet.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/SmallPtrSet.h?rev=107285&r1=107284&r2=107285&view=diff
==============================================================================
--- llvm/trunk/include/llvm/ADT/SmallPtrSet.h (original)
+++ llvm/trunk/include/llvm/ADT/SmallPtrSet.h Wed Jun 30 10:02:37 2010
@@ -46,8 +46,10 @@
 class SmallPtrSetImpl {
   friend class SmallPtrSetIteratorImpl;
 protected:
-  /// CurArray - This is the current set of buckets.  If it points to
-  /// SmallArray, then the set is in 'small mode'.
+  /// SmallArray - Points to a fixed size set of buckets, used in 'small mode'.
+  const void **SmallArray;
+  /// CurArray - This is the current set of buckets.  If equal to SmallArray,
+  /// then the set is in 'small mode'.
   const void **CurArray;
   /// CurArraySize - The allocated size of CurArray, always a power of two.
   /// Note that CurArray points to an array that has CurArraySize+1 elements in
@@ -57,15 +59,13 @@
   // If small, this is # elts allocated consequtively
   unsigned NumElements;
   unsigned NumTombstones;
-  const void *SmallArray[1];  // Must be last ivar.
 
   // Helper to copy construct a SmallPtrSet.
-  SmallPtrSetImpl(const SmallPtrSetImpl& that);
-  explicit SmallPtrSetImpl(unsigned SmallSize) {
+  SmallPtrSetImpl(const void **SmallStorage, const SmallPtrSetImpl& that);
+  explicit SmallPtrSetImpl(const void **SmallStorage, unsigned SmallSize) :
+    SmallArray(SmallStorage), CurArray(SmallStorage), CurArraySize(SmallSize) {
     assert(SmallSize && (SmallSize & (SmallSize-1)) == 0 &&
            "Initial size must be a power of two!");
-    CurArray = &SmallArray[0];
-    CurArraySize = SmallSize;
     // The end pointer, always valid, is set to a valid element to help the
     // iterator.
     CurArray[SmallSize] = 0;
@@ -123,7 +123,7 @@
   }
 
 private:
-  bool isSmall() const { return CurArray == &SmallArray[0]; }
+  bool isSmall() const { return CurArray == SmallArray; }
 
   unsigned Hash(const void *Ptr) const {
     return static_cast<unsigned>(((uintptr_t)Ptr >> 4) & (CurArraySize-1));
@@ -233,14 +233,16 @@
 class SmallPtrSet : public SmallPtrSetImpl {
   // Make sure that SmallSize is a power of two, round up if not.
   enum { SmallSizePowTwo = NextPowerOfTwo<SmallSize>::Val };
-  void *SmallArray[SmallSizePowTwo+1];
+  /// SmallStorage - Fixed size storage used in 'small mode'.  The extra element
+  /// ensures that the end iterator actually points to valid memory.
+  const void *SmallStorage[SmallSizePowTwo+1];
   typedef PointerLikeTypeTraits<PtrType> PtrTraits;
 public:
-  SmallPtrSet() : SmallPtrSetImpl(SmallSizePowTwo) {}
-  SmallPtrSet(const SmallPtrSet &that) : SmallPtrSetImpl(that) {}
+  SmallPtrSet() : SmallPtrSetImpl(SmallStorage, SmallSizePowTwo) {}
+  SmallPtrSet(const SmallPtrSet &that) : SmallPtrSetImpl(SmallStorage, that) {}
 
   template<typename It>
-  SmallPtrSet(It I, It E) : SmallPtrSetImpl(SmallSizePowTwo) {
+  SmallPtrSet(It I, It E) : SmallPtrSetImpl(SmallStorage, SmallSizePowTwo) {
     insert(I, E);
   }
 

Modified: llvm/trunk/lib/Support/SmallPtrSet.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/SmallPtrSet.cpp?rev=107285&r1=107284&r2=107285&view=diff
==============================================================================
--- llvm/trunk/lib/Support/SmallPtrSet.cpp (original)
+++ llvm/trunk/lib/Support/SmallPtrSet.cpp Wed Jun 30 10:02:37 2010
@@ -166,10 +166,13 @@
   }
 }
 
-SmallPtrSetImpl::SmallPtrSetImpl(const SmallPtrSetImpl& that) {
+SmallPtrSetImpl::SmallPtrSetImpl(const void **SmallStorage,
+                                 const SmallPtrSetImpl& that) {
+  SmallArray = SmallStorage;
+
   // If we're becoming small, prepare to insert into our stack space
   if (that.isSmall()) {
-    CurArray = &SmallArray[0];
+    CurArray = SmallArray;
   // Otherwise, allocate new heap space (unless we were the same size)
   } else {
     CurArray = (const void**)malloc(sizeof(void*) * (that.CurArraySize+1));
@@ -197,7 +200,7 @@
   if (RHS.isSmall()) {
     if (!isSmall())
       free(CurArray);
-    CurArray = &SmallArray[0];
+    CurArray = SmallArray;
   // Otherwise, allocate new heap space (unless we were the same size)
   } else if (CurArraySize != RHS.CurArraySize) {
     if (isSmall())




From clattner at apple.com  Wed Jun 30 10:20:41 2010
From: clattner at apple.com (Chris Lattner)
Date: Wed, 30 Jun 2010 08:20:41 -0700
Subject: [llvm-commits] [llvm] r107199 -
	/llvm/trunk/include/llvm/ADT/SmallPtrSet.h
In-Reply-To: <EA85BEB7-3B1D-4114-A0FD-ABE5C374908B@2pi.dk>
References: <20100629200534.8EAB22A6C12C@llvm.org>
	<1D0E2A71-F497-4894-9481-44D35EB4BB8E@2pi.dk>
	<4C2B5968.1040608@free.fr>
	<EA85BEB7-3B1D-4114-A0FD-ABE5C374908B@2pi.dk>
Message-ID: <02889862-38C4-48EF-8805-D456DB30CCE9@apple.com>

>>> 
>>> Ignoring overflow, NextPowerOfTwo(x) is always strictly greater than x.
>> 
>> are you sure?  C++ templates make my head hurt, but as far as I can see it
>> works as follows.
> 
> Oh wait, there's a template?
> 
> I was talking about the function in MathExtras.h:
> 
> /// NextPowerOf2 - Returns the next power of two (in 64-bits)
> /// that is strictly greater than A.  Returns zero on overflow.

Please change the comment to be "greater than or equal to A" at least :)

-Chris



From clattner at apple.com  Wed Jun 30 10:24:22 2010
From: clattner at apple.com (Chris Lattner)
Date: Wed, 30 Jun 2010 08:24:22 -0700
Subject: [llvm-commits] [llvm] r107205 - in
	/llvm/trunk:	bindings/ada/llvm/ docs/ include/llvm-c/
	include/llvm/	include/llvm/CodeGen/ include/llvm/MC/
	include/llvm/Target/	lib/AsmParser/ lib/Bitcode/Reader/
	lib/Bitcode/Writer/ lib/CodeGen/ lib/CodeGen/AsmPrinter/
	lib/Linker/ lib/MC/	lib/Target/
	lib/Target/CppBackend/	lib/Target/XCore/AsmPrinter/
	lib/Transforms/IPO/ lib/VMCore/	tools/llvm-nm/
In-Reply-To: <AF811FB0-E72D-44DD-8BBD-1C6D4971F1AF@gmail.com>
References: <20100629212400.DABF32A6C12C@llvm.org>
	<C7E3E4A7-A598-4C61-9513-2DFC7C2EC4CC@apple.com>
	<AF811FB0-E72D-44DD-8BBD-1C6D4971F1AF@gmail.com>
Message-ID: <FA99D48A-0561-420D-AA6C-6983AB1AFEC9@apple.com>


On Jun 29, 2010, at 3:33 PM, Bill Wendling wrote:

> On Jun 29, 2010, at 2:56 PM, Chris Lattner wrote:
> 
>> On Jun 29, 2010, at 2:24 PM, Bill Wendling wrote:
>> 
>>> Author: void
>>> Date: Tue Jun 29 16:24:00 2010
>>> New Revision: 107205
>>> 
>>> URL: http://llvm.org/viewvc/llvm-project?rev=107205&view=rev
>>> Log:
>>> Introducing the "linker_weak" linkage type. This will be used for Objective-C
>>> metadata types which should be marked as "weak", but which the linker will
>>> remove upon final linkage.
>> 
>> Hi Bill,
>> 
>> This would have been good to talk about before you implemented it.  The name linker_weak doesn't seem very descriptive.  How about linker_private_weak or something like that?
>> 
> I thought about that, but they aren't private from what I can tell. They're marked as ".globl" and ".weak_definition".

They are "as private" as other "l" labels, right?  Those are visible across translation units too.  We call it "linker private" so calling this "linker_private_weak" seems reasonable.  Any other suggestions?

>>> 
>>> 
>>>   /// GetJTISymbol - Return the symbol for the specified jump table entry.
>>> -    MCSymbol *GetJTISymbol(unsigned JTID, bool isLinkerPrivate = false) const;
>>> +    MCSymbol *GetJTISymbol(unsigned JTID, bool PassToLinker = false) const;
>> 
>> "PassToLinker" doesn't mean anything, why did you rename it?
> 
> I renamed it because the name didn't mean what it used to after the addition of "linker_weak".
> 
>> Please rename it to be more descriptive or improve the comment.  "isLinkerPrivate" seems like a perfectly good and descriptive name to me.
> 
> It would be if we only had "linker_private" to worry about. If we don't expect linker_private_weak here, then it can be reverted.

It seems that a preferred fix is to pass in the Mangler enum, which is really what this function needs.  Alternatively (if that would require adding a #include to a header), split it into two different functions, one that is private and one that is linker private).

>> 
>> Please make this "HasLinkerPrivateWeakLinkage".  There is only one target with this linkage form and it always spells it the same way.  Predicating stuff based on the bool is more clean considering that the *name* is the same as LinkerPrivate the linkage semantics require a new *directive* to be emitted.
>> 
>> In fact, I don't think you actually need this bit at all since asmprinter handles these symbols like all the other .weak stuff.  Is it needed?
>> 
> I'll check to see if it's used. If it's not used, then it's relying upon the hack down below, which is bad. However, I much prefer having the prefix string in one place than relying upon it being buried in some deep part of the asm printer.

I don't really understand what you mean.

>>> 
>>> +/// If isLinkerPrivate or isLinkerWeak is specified, an 'l' label is returned,
>>> +/// otherwise a normal 'L' label is returned.
>>> +MCSymbol *MachineFunction::getJTISymbol(unsigned JTI, MCContext &Ctx,
>>> +                                        bool PassToLinker) const {
>>> assert(JumpTableInfo && "No jump tables");
>>> 
>>> assert(JTI < JumpTableInfo->getJumpTables().size() && "Invalid JTI!");
>>> const MCAsmInfo &MAI = *getTarget().getMCAsmInfo();
>>> 
>>> -  const char *Prefix = isLinkerPrivate ? MAI.getLinkerPrivateGlobalPrefix() :
>>> -                                         MAI.getPrivateGlobalPrefix();
>>> +  const char *Prefix = PassToLinker ?
>>> +    MAI.getLinkerPrivateGlobalPrefix() :
>>> +    MAI.getPrivateGlobalPrefix();
>> 
>> I don't see why you changed this stuff, it seems completely orthogonal to the rest of the patch.  Please change it back.
>> 
> How do you mean? Can't these be linker_weak (or linker_private_weak) as well?

This looks like code reformatting only.

Thanks for working on this Bill!

-Chris


From eli.friedman at gmail.com  Wed Jun 30 10:28:42 2010
From: eli.friedman at gmail.com (Eli Friedman)
Date: Wed, 30 Jun 2010 08:28:42 -0700
Subject: [llvm-commits] [llvm] r107199 -
	/llvm/trunk/include/llvm/ADT/SmallPtrSet.h
In-Reply-To: <02889862-38C4-48EF-8805-D456DB30CCE9@apple.com>
References: <20100629200534.8EAB22A6C12C@llvm.org>
	<1D0E2A71-F497-4894-9481-44D35EB4BB8E@2pi.dk>
	<4C2B5968.1040608@free.fr>
	<EA85BEB7-3B1D-4114-A0FD-ABE5C374908B@2pi.dk>
	<02889862-38C4-48EF-8805-D456DB30CCE9@apple.com>
Message-ID: <AANLkTimS2bCKcWm2SyecxVm4suTq9iDRCLetc8GFWJ8i@mail.gmail.com>

On Wed, Jun 30, 2010 at 8:20 AM, Chris Lattner <clattner at apple.com> wrote:
>>>>
>>>> Ignoring overflow, NextPowerOfTwo(x) is always strictly greater than x.
>>>
>>> are you sure? ?C++ templates make my head hurt, but as far as I can see it
>>> works as follows.
>>
>> Oh wait, there's a template?
>>
>> I was talking about the function in MathExtras.h:
>>
>> /// NextPowerOf2 - Returns the next power of two (in 64-bits)
>> /// that is strictly greater than A. ?Returns zero on overflow.
>
> Please change the comment to be "greater than or equal to A" at least :)

Umm, that version actually does return a value strictly greater than
the input...

-Eli



From baldrick at free.fr  Wed Jun 30 10:29:46 2010
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 30 Jun 2010 15:29:46 -0000
Subject: [llvm-commits] [llvm] r107286 -
	/llvm/trunk/include/llvm/ADT/SmallPtrSet.h
Message-ID: <20100630152946.CBAC22A6C12C@llvm.org>

Author: baldrick
Date: Wed Jun 30 10:29:46 2010
New Revision: 107286

URL: http://llvm.org/viewvc/llvm-project?rev=107286&view=rev
Log:
Clarify that the NextPowerOfTwo template is idempotent.

Modified:
    llvm/trunk/include/llvm/ADT/SmallPtrSet.h

Modified: llvm/trunk/include/llvm/ADT/SmallPtrSet.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/SmallPtrSet.h?rev=107286&r1=107285&r2=107286&view=diff
==============================================================================
--- llvm/trunk/include/llvm/ADT/SmallPtrSet.h (original)
+++ llvm/trunk/include/llvm/ADT/SmallPtrSet.h Wed Jun 30 10:29:46 2010
@@ -200,7 +200,7 @@
 };
 
 /// NextPowerOfTwo - This is a helper template that rounds N up to the next
-/// power of two.
+/// power of two (which means N itself if N is already a power of two).
 template<unsigned N>
 struct NextPowerOfTwo;
 




From baldrick at free.fr  Wed Jun 30 10:30:34 2010
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 30 Jun 2010 17:30:34 +0200
Subject: [llvm-commits] [llvm] r107199 -
	/llvm/trunk/include/llvm/ADT/SmallPtrSet.h
In-Reply-To: <02889862-38C4-48EF-8805-D456DB30CCE9@apple.com>
References: <20100629200534.8EAB22A6C12C@llvm.org>
	<1D0E2A71-F497-4894-9481-44D35EB4BB8E@2pi.dk>
	<4C2B5968.1040608@free.fr>
	<EA85BEB7-3B1D-4114-A0FD-ABE5C374908B@2pi.dk>
	<02889862-38C4-48EF-8805-D456DB30CCE9@apple.com>
Message-ID: <4C2B631A.6050507@free.fr>

> Please change the comment to be "greater than or equal to A" at least :)

I clarified the template comment in commit 107286.

Ciao,

Duncan.


From daniel at zuster.org  Wed Jun 30 11:23:09 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 30 Jun 2010 16:23:09 -0000
Subject: [llvm-commits] [zorg] r107288 - /zorg/trunk/lnt/lnt/tests/nt.py
Message-ID: <20100630162309.252BD2A6C12C@llvm.org>

Author: ddunbar
Date: Wed Jun 30 11:23:08 2010
New Revision: 107288

URL: http://llvm.org/viewvc/llvm-project?rev=107288&view=rev
Log:
LNT/nt: Don't accept 9999 as a valid tag number for llvm-gcc.

Modified:
    zorg/trunk/lnt/lnt/tests/nt.py

Modified: zorg/trunk/lnt/lnt/tests/nt.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/tests/nt.py?rev=107288&r1=107287&r2=107288&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/tests/nt.py (original)
+++ zorg/trunk/lnt/lnt/tests/nt.py Wed Jun 30 11:23:08 2010
@@ -393,10 +393,11 @@
             run_info['run_order'] = run_info['cc_src_revision']
 
         # Otherwise, if this is a production compiler, look for a source tag. We
-        # don't accept 0 as a valid source tag, since that is what llvm-gcc
-        # defaults to when no build number is given.
+        # don't accept 0 or 9999 as valid source tag, since that is what
+        # llvm-gcc builds use when no build number is given.
         elif (run_info.get('cc_build') == 'PROD' and
-              run_info.get('cc_src_tag') != '0' and
+              (run_info.get('cc_src_tag') != '0' or
+               run_info.get('cc_src_tag') != '9999') and
               run_info.get('cc_src_tag','').isdigit()):
             run_info['run_order'] = run_info['cc_src_tag']
 




From daniel at zuster.org  Wed Jun 30 11:51:08 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 30 Jun 2010 09:51:08 -0700
Subject: [llvm-commits] [llvm] r107199 -
	/llvm/trunk/include/llvm/ADT/SmallPtrSet.h
In-Reply-To: <4C2B631A.6050507@free.fr>
References: <20100629200534.8EAB22A6C12C@llvm.org>
	<1D0E2A71-F497-4894-9481-44D35EB4BB8E@2pi.dk>
	<4C2B5968.1040608@free.fr>
	<EA85BEB7-3B1D-4114-A0FD-ABE5C374908B@2pi.dk>
	<02889862-38C4-48EF-8805-D456DB30CCE9@apple.com>
	<4C2B631A.6050507@free.fr>
Message-ID: <AANLkTilWaGRyI9lo0E0AxhvKeXwi88Hvg1-chMqN_uQL@mail.gmail.com>

Wait, wait, we have two nearly equivalent functions with the same name
and different semantics?

 - Daniel

On Wed, Jun 30, 2010 at 8:30 AM, Duncan Sands <baldrick at free.fr> wrote:
>> Please change the comment to be "greater than or equal to A" at least :)
>
> I clarified the template comment in commit 107286.
>
> Ciao,
>
> Duncan.
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>


From baldrick at free.fr  Wed Jun 30 12:00:54 2010
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 30 Jun 2010 19:00:54 +0200
Subject: [llvm-commits] [llvm] r107199 -
	/llvm/trunk/include/llvm/ADT/SmallPtrSet.h
In-Reply-To: <AANLkTilWaGRyI9lo0E0AxhvKeXwi88Hvg1-chMqN_uQL@mail.gmail.com>
References: <20100629200534.8EAB22A6C12C@llvm.org>	<1D0E2A71-F497-4894-9481-44D35EB4BB8E@2pi.dk>	<4C2B5968.1040608@free.fr>	<EA85BEB7-3B1D-4114-A0FD-ABE5C374908B@2pi.dk>	<02889862-38C4-48EF-8805-D456DB30CCE9@apple.com>	<4C2B631A.6050507@free.fr>
	<AANLkTilWaGRyI9lo0E0AxhvKeXwi88Hvg1-chMqN_uQL@mail.gmail.com>
Message-ID: <4C2B7846.3050905@free.fr>

> Wait, wait, we have two nearly equivalent functions with the same name
> and different semantics?

Yes, but one of them is only used in SmallPtrSet.h to get compile time
evaluation via template madness, so it's not as bad as it sounds.
Renaming it to RoundUpToPowerOfTwo wouldn't hurt I guess.

Ciao,

Duncan.


From bruno.cardoso at gmail.com  Wed Jun 30 12:03:03 2010
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Wed, 30 Jun 2010 17:03:03 -0000
Subject: [llvm-commits] [llvm] r107293 - in /llvm/trunk:
 lib/Target/X86/X86InstrSSE.td test/MC/AsmParser/X86/x86_32-encoding.s
 test/MC/AsmParser/X86/x86_64-encoding.s
Message-ID: <20100630170304.1E7E62A6C12C@llvm.org>

Author: bruno
Date: Wed Jun 30 12:03:03 2010
New Revision: 107293

URL: http://llvm.org/viewvc/llvm-project?rev=107293&view=rev
Log:
Add AVX SSE2 packed integer extract/insert instructions

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
    llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=107293&r1=107292&r2=107293&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Jun 30 12:03:03 2010
@@ -2805,32 +2805,57 @@
 } // ExeDomain = SSEPackedInt
 
 //===---------------------------------------------------------------------===//
-// SSE2 - Packed Misc Integer Instructions
+// SSE2 - Packed Integer Extract and Insert
 //===---------------------------------------------------------------------===//
 
 let ExeDomain = SSEPackedInt in {
+multiclass sse2_pinsrw<bit Is2Addr = 1> {
+  def rri : Ii8<0xC4, MRMSrcReg,
+       (outs VR128:$dst), (ins VR128:$src1,
+        GR32:$src2, i32i8imm:$src3),
+       !if(Is2Addr,
+           "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
+           "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
+       [(set VR128:$dst,
+         (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
+  def rmi : Ii8<0xC4, MRMSrcMem,
+                       (outs VR128:$dst), (ins VR128:$src1,
+                        i16mem:$src2, i32i8imm:$src3),
+       !if(Is2Addr,
+           "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
+           "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
+       [(set VR128:$dst,
+         (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
+                    imm:$src3))]>;
+}
 
-// Extract / Insert
+// Extract
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE2] in
+def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
+                    (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
+                    "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
+                    [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
+                                                imm:$src2))]>, OpSize, VEX;
 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
                     (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
                     "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
                     [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
                                                 imm:$src2))]>;
-let Constraints = "$src1 = $dst" in {
-  def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
-                       (outs VR128:$dst), (ins VR128:$src1,
-                        GR32:$src2, i32i8imm:$src3),
-                       "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
-                       [(set VR128:$dst,
-                         (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
-  def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
-                       (outs VR128:$dst), (ins VR128:$src1,
-                        i16mem:$src2, i32i8imm:$src3),
-                       "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
-                       [(set VR128:$dst,
-                         (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
-                                    imm:$src3))]>;
-}
+
+// Insert
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE2] in
+  defm PINSRW : sse2_pinsrw<0>, OpSize, VEX_4V;
+
+let Constraints = "$src1 = $dst" in
+  defm VPINSRW : sse2_pinsrw, TB, OpSize;
+
+} // ExeDomain = SSEPackedInt
+
+//===---------------------------------------------------------------------===//
+// SSE2 - Packed Misc Integer Instructions
+//===---------------------------------------------------------------------===//
+
+let ExeDomain = SSEPackedInt in {
 
 // Mask creation
 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s?rev=107293&r1=107292&r2=107293&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s Wed Jun 30 12:03:03 2010
@@ -11482,3 +11482,15 @@
 // CHECK: encoding: [0xc5,0xe9,0x6d,0x18]
           vpunpckhqdq  (%eax), %xmm2, %xmm3
 
+// CHECK: vpinsrw  $7, %eax, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xc4,0xd8,0x07]
+          vpinsrw  $7, %eax, %xmm2, %xmm3
+
+// CHECK: vpinsrw  $7, (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xc4,0x18,0x07]
+          vpinsrw  $7, (%eax), %xmm2, %xmm3
+
+// CHECK: vpextrw  $7, %xmm2, %eax
+// CHECK: encoding: [0xc5,0xf9,0xc5,0xc2,0x07]
+          vpextrw  $7, %xmm2, %eax
+

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s?rev=107293&r1=107292&r2=107293&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s Wed Jun 30 12:03:03 2010
@@ -1522,3 +1522,15 @@
 // CHECK: encoding: [0xc5,0x19,0x6d,0x28]
           vpunpckhqdq  (%rax), %xmm12, %xmm13
 
+// CHECK: vpinsrw  $7, %eax, %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0xc4,0xe8,0x07]
+          vpinsrw  $7, %eax, %xmm12, %xmm13
+
+// CHECK: vpinsrw  $7, (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0xc4,0x28,0x07]
+          vpinsrw  $7, (%rax), %xmm12, %xmm13
+
+// CHECK: vpextrw  $7, %xmm12, %eax
+// CHECK: encoding: [0xc4,0xc1,0x79,0xc5,0xc4,0x07]
+          vpextrw  $7, %xmm12, %eax
+




From stoklund at 2pi.dk  Wed Jun 30 12:16:14 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Wed, 30 Jun 2010 10:16:14 -0700
Subject: [llvm-commits] [llvm] r107199 -
	/llvm/trunk/include/llvm/ADT/SmallPtrSet.h
In-Reply-To: <AANLkTilWaGRyI9lo0E0AxhvKeXwi88Hvg1-chMqN_uQL@mail.gmail.com>
References: <20100629200534.8EAB22A6C12C@llvm.org>
	<1D0E2A71-F497-4894-9481-44D35EB4BB8E@2pi.dk>
	<4C2B5968.1040608@free.fr>
	<EA85BEB7-3B1D-4114-A0FD-ABE5C374908B@2pi.dk>
	<02889862-38C4-48EF-8805-D456DB30CCE9@apple.com>
	<4C2B631A.6050507@free.fr>
	<AANLkTilWaGRyI9lo0E0AxhvKeXwi88Hvg1-chMqN_uQL@mail.gmail.com>
Message-ID: <F5FB3EB5-1905-44AE-9AB9-CE3CC585CA93@2pi.dk>


On Jun 30, 2010, at 9:51 AM, Daniel Dunbar wrote:

> Wait, wait, we have two nearly equivalent functions with the same name
> and different semantics?

Well, one is a template that can calculate a runtime constant, and one is a function.

And the names NextPowerOf2 vs NextPowerOfTwo are clearly distinct ;-)

I have been confused a couple of times by NextPowerOf2() not being idempotent, but I have learned it now which is why I complained to Duncan. He was of course talking about the template NextPowerOfTwo<> which is indeed idempotent.

It's all very confusing.

I like Duncan's suggestion of renaming the template to RoundUpToPowerOfTwo or something similar.




From baldrick at free.fr  Wed Jun 30 12:22:28 2010
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 30 Jun 2010 17:22:28 -0000
Subject: [llvm-commits] [llvm] r107295 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Message-ID: <20100630172229.09B782A6C12C@llvm.org>

Author: baldrick
Date: Wed Jun 30 12:22:28 2010
New Revision: 107295

URL: http://llvm.org/viewvc/llvm-project?rev=107295&view=rev
Log:
Remove an unused variable.  The call to getRoot has side-effects, so
this could break something (but doesn't seem to).

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=107295&r1=107294&r2=107295&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Wed Jun 30 12:22:28 2010
@@ -5899,7 +5899,6 @@
   // If this is the entry block, emit arguments.
   const Function &F = *LLVMBB->getParent();
   SelectionDAG &DAG = SDB->DAG;
-  SDValue OldRoot = DAG.getRoot();
   DebugLoc dl = SDB->getCurDebugLoc();
   const TargetData *TD = TLI.getTargetData();
   SmallVector<ISD::InputArg, 16> Ins;




From baldrick at free.fr  Wed Jun 30 12:24:28 2010
From: baldrick at free.fr (Duncan Sands)
Date: Wed, 30 Jun 2010 17:24:28 -0000
Subject: [llvm-commits] [llvm] r107297 -
	/llvm/trunk/include/llvm/ADT/SmallPtrSet.h
Message-ID: <20100630172428.407692A6C12C@llvm.org>

Author: baldrick
Date: Wed Jun 30 12:24:28 2010
New Revision: 107297

URL: http://llvm.org/viewvc/llvm-project?rev=107297&view=rev
Log:
Rename NextPowerOfTwo to RoundUpToPowerOfTwo.

Modified:
    llvm/trunk/include/llvm/ADT/SmallPtrSet.h

Modified: llvm/trunk/include/llvm/ADT/SmallPtrSet.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/SmallPtrSet.h?rev=107297&r1=107296&r2=107297&view=diff
==============================================================================
--- llvm/trunk/include/llvm/ADT/SmallPtrSet.h (original)
+++ llvm/trunk/include/llvm/ADT/SmallPtrSet.h Wed Jun 30 12:24:28 2010
@@ -199,29 +199,29 @@
   }
 };
 
-/// NextPowerOfTwo - This is a helper template that rounds N up to the next
+/// RoundUpToPowerOfTwo - This is a helper template that rounds N up to the next
 /// power of two (which means N itself if N is already a power of two).
 template<unsigned N>
-struct NextPowerOfTwo;
+struct RoundUpToPowerOfTwo;
 
-/// NextPowerOfTwoH - If N is not a power of two, increase it.  This is a helper
-/// template used to implement NextPowerOfTwo.
+/// RoundUpToPowerOfTwoH - If N is not a power of two, increase it.  This is a
+/// helper template used to implement RoundUpToPowerOfTwo.
 template<unsigned N, bool isPowerTwo>
-struct NextPowerOfTwoH {
+struct RoundUpToPowerOfTwoH {
   enum { Val = N };
 };
 template<unsigned N>
-struct NextPowerOfTwoH<N, false> {
+struct RoundUpToPowerOfTwoH<N, false> {
   enum {
     // We could just use NextVal = N+1, but this converges faster.  N|(N-1) sets
     // the right-most zero bits to one all at once, e.g. 0b0011000 -> 0b0011111.
-    Val = NextPowerOfTwo<(N|(N-1)) + 1>::Val
+    Val = RoundUpToPowerOfTwo<(N|(N-1)) + 1>::Val
   };
 };
 
 template<unsigned N>
-struct NextPowerOfTwo {
-  enum { Val = NextPowerOfTwoH<N, (N&(N-1)) == 0>::Val };
+struct RoundUpToPowerOfTwo {
+  enum { Val = RoundUpToPowerOfTwoH<N, (N&(N-1)) == 0>::Val };
 };
   
 
@@ -232,7 +232,7 @@
 template<class PtrType, unsigned SmallSize>
 class SmallPtrSet : public SmallPtrSetImpl {
   // Make sure that SmallSize is a power of two, round up if not.
-  enum { SmallSizePowTwo = NextPowerOfTwo<SmallSize>::Val };
+  enum { SmallSizePowTwo = RoundUpToPowerOfTwo<SmallSize>::Val };
   /// SmallStorage - Fixed size storage used in 'small mode'.  The extra element
   /// ensures that the end iterator actually points to valid memory.
   const void *SmallStorage[SmallSizePowTwo+1];




From gohman at apple.com  Wed Jun 30 12:27:12 2010
From: gohman at apple.com (Dan Gohman)
Date: Wed, 30 Jun 2010 17:27:12 -0000
Subject: [llvm-commits] [llvm] r107298 - in /llvm/trunk:
 lib/Analysis/ScalarEvolution.cpp test/Analysis/ScalarEvolution/scev-aa.ll
Message-ID: <20100630172712.30B1C2A6C12C@llvm.org>

Author: djg
Date: Wed Jun 30 12:27:11 2010
New Revision: 107298

URL: http://llvm.org/viewvc/llvm-project?rev=107298&view=rev
Log:
Revert the part of r107257 which introduced new logic for using
nsw and nuw flags from IR Instructions. On further consideration,
this isn't valid.

Modified:
    llvm/trunk/lib/Analysis/ScalarEvolution.cpp
    llvm/trunk/test/Analysis/ScalarEvolution/scev-aa.ll

Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=107298&r1=107297&r2=107298&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Wed Jun 30 12:27:11 2010
@@ -2760,38 +2760,6 @@
   return getUnknown(PN);
 }
 
-/// UseFlag - When creating an operator with operands L and R based on an
-/// LLVM IR instruction in basic block BB where the instruction has
-/// nsw, nuw, or inbounds, test whether the corresponding flag can be
-/// set for the resulting SCEV.
-static bool
-UseFlag(bool Flag, const SCEV *L, const SCEV *R, const Value *Inst) {
-  // If the flag is not set, don't use it. This is included here to reduce
-  // clutter in the callers.
-  if (!Flag)
-    return false;
-
-  // Determine the block which contains the instruction with the flag.
-  const Instruction *I = dyn_cast<Instruction>(Inst);
-  if (!I)
-    return false;
-  const BasicBlock *BB = I->getParent();
-
-  // Handle an easy case: test if exactly one of the operands is an addrec
-  // and that the instruction is trivially control-equivalent to the addrec's
-  // loop's header.
-  if (const SCEVAddRecExpr *AR = dyn_cast<SCEVAddRecExpr>(L)) {
-    if (!isa<SCEVAddRecExpr>(R) &&
-        AR->getLoop()->getHeader() == BB)
-      return true;
-  } else if (const SCEVAddRecExpr *AR = dyn_cast<SCEVAddRecExpr>(R)) {
-    if (AR->getLoop()->getHeader() == BB)
-      return true;
-  }
-
-  return false;
-}
-
 /// createNodeForGEP - Expand GEP instructions into add and multiply
 /// operations. This allows them to be analyzed by regular SCEV code.
 ///
@@ -2800,9 +2768,7 @@
   // Don't blindly transfer the inbounds flag from the GEP instruction to the
   // Add expression, because the Instruction may be guarded by control flow
   // and the no-overflow bits may not be valid for the expression in any
-  // context. However, in the special case where the GEP is in the loop header,
-  // we know it's trivially control-equivalent to any addrecs for that loop.
-  bool InBounds = GEP->isInBounds();
+  // context.
 
   const Type *IntPtrTy = getEffectiveSCEVType(GEP->getType());
   Value *Base = GEP->getOperand(0);
@@ -2821,13 +2787,8 @@
       unsigned FieldNo = cast<ConstantInt>(Index)->getZExtValue();
       const SCEV *FieldOffset = getOffsetOfExpr(STy, FieldNo);
 
-      // Test if the GEP has the inbounds keyword and is control-equivalent
-      // to the addrec.
-      bool HasNUW = UseFlag(InBounds, TotalOffset, FieldOffset, GEP);
-
       // Add the field offset to the running total offset.
-      TotalOffset = getAddExpr(TotalOffset, FieldOffset,
-                               HasNUW, /*HasNSW=*/false);
+      TotalOffset = getAddExpr(TotalOffset, FieldOffset);
     } else {
       // For an array, add the element offset, explicitly scaled.
       const SCEV *ElementSize = getSizeOfExpr(*GTI);
@@ -2835,33 +2796,19 @@
       // Getelementptr indices are signed.
       IndexS = getTruncateOrSignExtend(IndexS, IntPtrTy);
 
-      // Test if the GEP has the inbounds keyword and is control-equivalent
-      // to the addrec.
-      bool HasNUW = UseFlag(InBounds, IndexS, ElementSize, GEP);
-
       // Multiply the index by the element size to compute the element offset.
-      const SCEV *LocalOffset = getMulExpr(IndexS, ElementSize,
-                                           HasNUW, /*HasNSW=*/false);
-
-      // Test if the GEP has the inbounds keyword and is control-equivalent
-      // to the addrec.
-      HasNUW = UseFlag(InBounds, TotalOffset, LocalOffset, GEP);
+      const SCEV *LocalOffset = getMulExpr(IndexS, ElementSize);
 
       // Add the element offset to the running total offset.
-      TotalOffset = getAddExpr(TotalOffset, LocalOffset,
-                               HasNUW, /*HasNSW=*/false);
+      TotalOffset = getAddExpr(TotalOffset, LocalOffset);
     }
   }
 
   // Get the SCEV for the GEP base.
   const SCEV *BaseS = getSCEV(Base);
 
-  // Test if the GEP has the inbounds keyword and is control-equivalent
-  // to the addrec.
-  bool HasNUW = UseFlag(InBounds, BaseS, TotalOffset, GEP);
-
   // Add the total offset from all the GEP indices to the base.
-  return getAddExpr(BaseS, TotalOffset, HasNUW, /*HasNSW=*/false);
+  return getAddExpr(BaseS, TotalOffset);
 }
 
 /// GetMinTrailingZeros - Determine the minimum number of zero bits that S is
@@ -3253,30 +3200,12 @@
 
   Operator *U = cast<Operator>(V);
   switch (Opcode) {
-  case Instruction::Add: {
-    const SCEV *LHS = getSCEV(U->getOperand(0));
-    const SCEV *RHS = getSCEV(U->getOperand(1));
-
-    // Don't transfer the NSW and NUW bits from the Add instruction to the
-    // Add expression unless we can prove that it's safe.
-    AddOperator *Add = cast<AddOperator>(U);
-    bool HasNUW = UseFlag(Add->hasNoUnsignedWrap(), LHS, RHS, Add);
-    bool HasNSW = UseFlag(Add->hasNoSignedWrap(), LHS, RHS, Add);
-
-    return getAddExpr(LHS, RHS, HasNUW, HasNSW);
-  }
-  case Instruction::Mul: {
-    const SCEV *LHS = getSCEV(U->getOperand(0));
-    const SCEV *RHS = getSCEV(U->getOperand(1));
-
-    // Don't transfer the NSW and NUW bits from the Mul instruction to the
-    // Mul expression unless we can prove that it's safe.
-    MulOperator *Mul = cast<MulOperator>(U);
-    bool HasNUW = UseFlag(Mul->hasNoUnsignedWrap(), LHS, RHS, Mul);
-    bool HasNSW = UseFlag(Mul->hasNoSignedWrap(), LHS, RHS, Mul);
-
-    return getMulExpr(LHS, RHS, HasNUW, HasNSW);
-  }
+  case Instruction::Add:
+    return getAddExpr(getSCEV(U->getOperand(0)),
+                      getSCEV(U->getOperand(1)));
+  case Instruction::Mul:
+    return getMulExpr(getSCEV(U->getOperand(0)),
+                      getSCEV(U->getOperand(1)));
   case Instruction::UDiv:
     return getUDivExpr(getSCEV(U->getOperand(0)),
                        getSCEV(U->getOperand(1)));

Modified: llvm/trunk/test/Analysis/ScalarEvolution/scev-aa.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/ScalarEvolution/scev-aa.ll?rev=107298&r1=107297&r2=107298&view=diff
==============================================================================
--- llvm/trunk/test/Analysis/ScalarEvolution/scev-aa.ll (original)
+++ llvm/trunk/test/Analysis/ScalarEvolution/scev-aa.ll Wed Jun 30 12:27:11 2010
@@ -190,8 +190,9 @@
   ret void
 }
 
+; TODO: This is theoretically provable to be NoAlias.
 ; CHECK: Function: nonnegative: 2 pointers, 0 call sites
-; CHECK: NoAlias:  i64* %arrayidx, i64* %p
+; CHECK: MayAlias:  i64* %arrayidx, i64* %p
 
 define void @nonnegative(i64* %p) nounwind {
 entry:
@@ -210,6 +211,6 @@
   ret void
 }
 
-; CHECK: 14 no alias responses
-; CHECK: 26 may alias responses
+; CHECK: 13 no alias responses
+; CHECK: 27 may alias responses
 ; CHECK: 18 must alias responses




From isanbard at gmail.com  Wed Jun 30 12:49:42 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 30 Jun 2010 10:49:42 -0700
Subject: [llvm-commits] [llvm] r107205 - in
	/llvm/trunk:	bindings/ada/llvm/ docs/ include/llvm-c/
	include/llvm/	include/llvm/CodeGen/ include/llvm/MC/
	include/llvm/Target/	lib/AsmParser/ lib/Bitcode/Reader/
	lib/Bitcode/Writer/ lib/CodeGen/ lib/CodeGen/AsmPrinter/
	lib/Linker/ lib/MC/	lib/Target/
	lib/Target/CppBackend/	lib/Target/XCore/AsmPrinter/
	lib/Transforms/IPO/ lib/VMCore/	tools/llvm-nm/
In-Reply-To: <FA99D48A-0561-420D-AA6C-6983AB1AFEC9@apple.com>
References: <20100629212400.DABF32A6C12C@llvm.org>
	<C7E3E4A7-A598-4C61-9513-2DFC7C2EC4CC@apple.com>
	<AF811FB0-E72D-44DD-8BBD-1C6D4971F1AF@gmail.com>
	<FA99D48A-0561-420D-AA6C-6983AB1AFEC9@apple.com>
Message-ID: <7805A44F-4DAD-467F-B254-E1AB184FD2EB@gmail.com>

On Jun 30, 2010, at 8:24 AM, Chris Lattner wrote:

> On Jun 29, 2010, at 3:33 PM, Bill Wendling wrote:
> 
>> On Jun 29, 2010, at 2:56 PM, Chris Lattner wrote:
>> 
>>> On Jun 29, 2010, at 2:24 PM, Bill Wendling wrote:
>>> 
>>>> Author: void
>>>> Date: Tue Jun 29 16:24:00 2010
>>>> New Revision: 107205
>>>> 
>>>> URL: http://llvm.org/viewvc/llvm-project?rev=107205&view=rev
>>>> Log:
>>>> Introducing the "linker_weak" linkage type. This will be used for Objective-C
>>>> metadata types which should be marked as "weak", but which the linker will
>>>> remove upon final linkage.
>>> 
>>> Hi Bill,
>>> 
>>> This would have been good to talk about before you implemented it.  The name linker_weak doesn't seem very descriptive.  How about linker_private_weak or something like that?
>>> 
>> I thought about that, but they aren't private from what I can tell. They're marked as ".globl" and ".weak_definition".
> 
> They are "as private" as other "l" labels, right?  Those are visible across translation units too.  We call it "linker private" so calling this "linker_private_weak" seems reasonable.  Any other suggestions?

"linker_private_weak" is fine. (I'm not a huge fan of it because we don't have an analogous non-linker linkage. I.e., we don't have a "private_weak" type that corresponds with it.)

>>> Please make this "HasLinkerPrivateWeakLinkage".  There is only one target with this linkage form and it always spells it the same way.  Predicating stuff based on the bool is more clean considering that the *name* is the same as LinkerPrivate the linkage semantics require a new *directive* to be emitted.
>>> 
>>> In fact, I don't think you actually need this bit at all since asmprinter handles these symbols like all the other .weak stuff.  Is it needed?
>>> 
>> I'll check to see if it's used. If it's not used, then it's relying upon the hack down below, which is bad. However, I much prefer having the prefix string in one place than relying upon it being buried in some deep part of the asm printer.
> 
> I don't really understand what you mean.
> 
I want to separate it out from the "linker_private" linkage. In particular, I don't want to say that it will always have the same prefix as linker_private. That's the case with Darwin, but I don't see why that has to be the case for every linker that would want to implement it.

-bw




From bruno.cardoso at gmail.com  Wed Jun 30 13:06:01 2010
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Wed, 30 Jun 2010 18:06:01 -0000
Subject: [llvm-commits] [llvm] r107300 -
	/llvm/trunk/lib/Target/X86/X86InstrSSE.td
Message-ID: <20100630180602.082FB2A6C12C@llvm.org>

Author: bruno
Date: Wed Jun 30 13:06:01 2010
New Revision: 107300

URL: http://llvm.org/viewvc/llvm-project?rev=107300&view=rev
Log:
Fix a bug introduced in r107211 where instructions with memory operands are declared as commutable

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=107300&r1=107299&r2=107300&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Jun 30 13:06:01 2010
@@ -2259,7 +2259,8 @@
 let ExeDomain = SSEPackedInt in { // SSE integer instructions
 
 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
-                            bit Is2Addr = 1> {
+                            bit IsCommutable = 0, bit Is2Addr = 1> {
+  let isCommutable = IsCommutable in
   def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
        (ins VR128:$src1, VR128:$src2),
        !if(Is2Addr,
@@ -2301,7 +2302,8 @@
 
 /// PDI_binop_rm - Simple SSE2 binary operator.
 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
-                        ValueType OpVT, bit Is2Addr = 1> {
+                        ValueType OpVT, bit IsCommutable = 0, bit Is2Addr = 1> {
+  let isCommutable = IsCommutable in
   def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
        (ins VR128:$src1, VR128:$src2),
        !if(Is2Addr,
@@ -2323,7 +2325,8 @@
 /// to collapse (bitconvert VT to VT) into its operand.
 ///
 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
-                              bit Is2Addr = 1> {
+                              bit IsCommutable = 0, bit Is2Addr = 1> {
+  let isCommutable = IsCommutable in
   def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
        (ins VR128:$src1, VR128:$src2),
        !if(Is2Addr,
@@ -2343,69 +2346,63 @@
 // 128-bit Integer Arithmetic
 
 let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE2] in {
-let isCommutable = 1 in {
-defm VPADDB  : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, 0 /* 3 addr */>, VEX_4V;
-defm VPADDW  : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, 0>, VEX_4V;
-defm VPADDD  : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, 0>, VEX_4V;
-defm VPADDQ  : PDI_binop_rm_v2i64<0xD4, "vpaddq", add, 0>, VEX_4V;
-defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, 0>, VEX_4V;
-}
-defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, 0>, VEX_4V;
-defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, 0>, VEX_4V;
-defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, 0>, VEX_4V;
-defm VPSUBQ : PDI_binop_rm_v2i64<0xFB, "vpsubq", sub, 0>, VEX_4V;
+defm VPADDB  : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, 1, 0 /*3addr*/>, VEX_4V;
+defm VPADDW  : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, 1, 0>, VEX_4V;
+defm VPADDD  : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, 1, 0>, VEX_4V;
+defm VPADDQ  : PDI_binop_rm_v2i64<0xD4, "vpaddq", add, 1, 0>, VEX_4V;
+defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, 1, 0>, VEX_4V;
+defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, 0, 0>, VEX_4V;
+defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, 0, 0>, VEX_4V;
+defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, 0, 0>, VEX_4V;
+defm VPSUBQ : PDI_binop_rm_v2i64<0xFB, "vpsubq", sub, 0, 0>, VEX_4V;
 
 // Intrinsic forms
-defm VPSUBSB  : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b, 0>,
+defm VPSUBSB  : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b, 0, 0>,
                                  VEX_4V;
-defm VPSUBSW  : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w, 0>,
+defm VPSUBSW  : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w, 0, 0>,
                                  VEX_4V;
-defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b, 0>,
+defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b, 0, 0>,
                                  VEX_4V;
-defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w, 0>,
+defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w, 0, 0>,
                                  VEX_4V;
-let isCommutable = 1 in {
-defm VPADDSB  : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b, 0>,
+defm VPADDSB  : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b, 1, 0>,
                                  VEX_4V;
-defm VPADDSW  : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w, 0>,
+defm VPADDSW  : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w, 1, 0>,
                                  VEX_4V;
-defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b, 0>,
+defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b, 1, 0>,
                                  VEX_4V;
-defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w, 0>,
+defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w, 1, 0>,
                                  VEX_4V;
-defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w, 0>,
+defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w, 1, 0>,
                                  VEX_4V;
-defm VPMULHW  : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w, 0>,
+defm VPMULHW  : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w, 1, 0>,
                                  VEX_4V;
-defm VPMULUDQ : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_sse2_pmulu_dq, 0>,
+defm VPMULUDQ : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_sse2_pmulu_dq, 1, 0>,
                                  VEX_4V;
-defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd, 0>,
+defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd, 1, 0>,
                                  VEX_4V;
-defm VPAVGB   : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b, 0>,
+defm VPAVGB   : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b, 1, 0>,
                                  VEX_4V;
-defm VPAVGW   : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w, 0>,
+defm VPAVGW   : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w, 1, 0>,
                                  VEX_4V;
-defm VPMINUB  : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b, 0>,
+defm VPMINUB  : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b, 1, 0>,
                                  VEX_4V;
-defm VPMINSW  : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w, 0>,
+defm VPMINSW  : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w, 1, 0>,
                                  VEX_4V;
-defm VPMAXUB  : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b, 0>,
+defm VPMAXUB  : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b, 1, 0>,
                                  VEX_4V;
-defm VPMAXSW  : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w, 0>,
+defm VPMAXSW  : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w, 1, 0>,
                                  VEX_4V;
-defm VPSADBW  : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw, 0>,
+defm VPSADBW  : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw, 1, 0>,
                                  VEX_4V;
 }
-}
 
 let Constraints = "$src1 = $dst" in {
-let isCommutable = 1 in {
-defm PADDB  : PDI_binop_rm<0xFC, "paddb", add, v16i8>;
-defm PADDW  : PDI_binop_rm<0xFD, "paddw", add, v8i16>;
-defm PADDD  : PDI_binop_rm<0xFE, "paddd", add, v4i32>;
-defm PADDQ  : PDI_binop_rm_v2i64<0xD4, "paddq", add>;
-defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16>;
-}
+defm PADDB  : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
+defm PADDW  : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
+defm PADDD  : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
+defm PADDQ  : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
+defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
@@ -2416,23 +2413,21 @@
 defm PSUBSW  : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
-let isCommutable = 1 in {
-defm PADDSB  : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b>;
-defm PADDSW  : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w>;
-defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b>;
-defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w>;
-defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w>;
-defm PMULHW  : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w>;
-defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq>;
-defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd>;
-defm PAVGB   : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b>;
-defm PAVGW   : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w>;
-defm PMINUB  : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b>;
-defm PMINSW  : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w>;
-defm PMAXUB  : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b>;
-defm PMAXSW  : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w>;
-defm PSADBW  : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw>;
-}
+defm PADDSB  : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
+defm PADDSW  : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
+defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
+defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
+defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
+defm PMULHW  : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w, 1>;
+defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
+defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
+defm PAVGB   : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
+defm PAVGW   : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
+defm PMINUB  : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
+defm PMINSW  : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
+defm PMAXUB  : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
+defm PMAXSW  : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
+defm PSADBW  : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
 
 } // Constraints = "$src1 = $dst"
 
@@ -2468,11 +2463,9 @@
                                 int_x86_sse2_psra_d, int_x86_sse2_psrai_d, 0>,
                                 VEX_4V;
 
-let isCommutable = 1 in {
-defm VPAND : PDI_binop_rm_v2i64<0xDB, "vpand", and, 0>, VEX_4V;
-defm VPOR  : PDI_binop_rm_v2i64<0xEB, "vpor" , or, 0>, VEX_4V;
-defm VPXOR : PDI_binop_rm_v2i64<0xEF, "vpxor", xor, 0>, VEX_4V;
-}
+defm VPAND : PDI_binop_rm_v2i64<0xDB, "vpand", and, 1, 0>, VEX_4V;
+defm VPOR  : PDI_binop_rm_v2i64<0xEB, "vpor" , or, 1, 0>, VEX_4V;
+defm VPXOR : PDI_binop_rm_v2i64<0xEF, "vpxor", xor, 1, 0>, VEX_4V;
 
 let ExeDomain = SSEPackedInt in {
   let neverHasSideEffects = 1 in {
@@ -2522,11 +2515,9 @@
 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
                                int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
 
-let isCommutable = 1 in {
-defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and>;
-defm POR  : PDI_binop_rm_v2i64<0xEB, "por" , or>;
-defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor>;
-}
+defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
+defm POR  : PDI_binop_rm_v2i64<0xEB, "por" , or, 1>;
+defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
 
 let ExeDomain = SSEPackedInt in {
   let neverHasSideEffects = 1 in {
@@ -2577,28 +2568,24 @@
 //===---------------------------------------------------------------------===//
 
 let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE2] in {
-  let isCommutable = 1 in {
-  defm VPCMPEQB  : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_sse2_pcmpeq_b, 0>,
-                                   VEX_4V;
-  defm VPCMPEQW  : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_sse2_pcmpeq_w, 0>,
-                                   VEX_4V;
-  defm VPCMPEQD  : PDI_binop_rm_int<0x76, "vpcmpeqd", int_x86_sse2_pcmpeq_d, 0>,
-                                   VEX_4V;
-  }
-  defm VPCMPGTB  : PDI_binop_rm_int<0x64, "vpcmpgtb", int_x86_sse2_pcmpgt_b, 0>,
-                                   VEX_4V;
-  defm VPCMPGTW  : PDI_binop_rm_int<0x65, "vpcmpgtw", int_x86_sse2_pcmpgt_w, 0>,
-                                   VEX_4V;
-  defm VPCMPGTD  : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_sse2_pcmpgt_d, 0>,
-                                   VEX_4V;
+  defm VPCMPEQB  : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_sse2_pcmpeq_b, 1,
+                                    0>, VEX_4V;
+  defm VPCMPEQW  : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_sse2_pcmpeq_w, 1,
+                                    0>, VEX_4V;
+  defm VPCMPEQD  : PDI_binop_rm_int<0x76, "vpcmpeqd", int_x86_sse2_pcmpeq_d, 1,
+                                    0>, VEX_4V;
+  defm VPCMPGTB  : PDI_binop_rm_int<0x64, "vpcmpgtb", int_x86_sse2_pcmpgt_b, 0,
+                                    0>, VEX_4V;
+  defm VPCMPGTW  : PDI_binop_rm_int<0x65, "vpcmpgtw", int_x86_sse2_pcmpgt_w, 0,
+                                    0>, VEX_4V;
+  defm VPCMPGTD  : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_sse2_pcmpgt_d, 0,
+                                    0>, VEX_4V;
 }
 
 let Constraints = "$src1 = $dst" in {
-  let isCommutable = 1 in {
-  defm PCMPEQB  : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
-  defm PCMPEQW  : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
-  defm PCMPEQD  : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
-  }
+  defm PCMPEQB  : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b, 1>;
+  defm PCMPEQW  : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w, 1>;
+  defm PCMPEQD  : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d, 1>;
   defm PCMPGTB  : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
   defm PCMPGTW  : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
   defm PCMPGTD  : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
@@ -2636,11 +2623,11 @@
 
 let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE2] in {
 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
-                                  0>, VEX_4V;
+                                  0, 0>, VEX_4V;
 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
-                                  0>, VEX_4V;
+                                  0, 0>, VEX_4V;
 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
-                                  0>, VEX_4V;
+                                  0, 0>, VEX_4V;
 }
 
 let Constraints = "$src1 = $dst" in {




From wendling at apple.com  Wed Jun 30 13:08:23 2010
From: wendling at apple.com (Bill Wendling)
Date: Wed, 30 Jun 2010 11:08:23 -0700
Subject: [llvm-commits] [llvm] r107205 -
	in	/llvm/trunk:	bindings/ada/llvm/ docs/
	include/llvm-c/	include/llvm/	include/llvm/CodeGen/
	include/llvm/MC/ include/llvm/Target/	lib/AsmParser/
	lib/Bitcode/Reader/	lib/Bitcode/Writer/ lib/CodeGen/
	lib/CodeGen/AsmPrinter/	lib/Linker/ lib/MC/	lib/Target/
	lib/Target/CppBackend/	lib/Target/XCore/AsmPrinter/	lib/Transforms/IPO/
	lib/VMCore/	tools/llvm-nm/
In-Reply-To: <7805A44F-4DAD-467F-B254-E1AB184FD2EB@gmail.com>
References: <20100629212400.DABF32A6C12C@llvm.org>
	<C7E3E4A7-A598-4C61-9513-2DFC7C2EC4CC@apple.com>
	<AF811FB0-E72D-44DD-8BBD-1C6D4971F1AF@gmail.com>
	<FA99D48A-0561-420D-AA6C-6983AB1AFEC9@apple.com>
	<7805A44F-4DAD-467F-B254-E1AB184FD2EB@gmail.com>
Message-ID: <B5AAFD97-0164-48AD-BC09-7137D8A0E205@apple.com>

On Jun 30, 2010, at 10:49 AM, Bill Wendling wrote:

>>>> Please make this "HasLinkerPrivateWeakLinkage".  There is only one target with this linkage form and it always spells it the same way.  Predicating stuff based on the bool is more clean considering that the *name* is the same as LinkerPrivate the linkage semantics require a new *directive* to be emitted.
>>>> 
>>>> In fact, I don't think you actually need this bit at all since asmprinter handles these symbols like all the other .weak stuff.  Is it needed?
>>>> 
>>> I'll check to see if it's used. If it's not used, then it's relying upon the hack down below, which is bad. However, I much prefer having the prefix string in one place than relying upon it being buried in some deep part of the asm printer.
>> 
>> I don't really understand what you mean.
>> 
> I want to separate it out from the "linker_private" linkage. In particular, I don't want to say that it will always have the same prefix as linker_private. That's the case with Darwin, but I don't see why that has to be the case for every linker that would want to implement it.
> 
Or for every target for that matter. Otherwise, these linkages are restricted to a small subset of usages -- Objective-C metadata on Darwin.

-bw




From stoklund at 2pi.dk  Wed Jun 30 13:19:08 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Wed, 30 Jun 2010 18:19:08 -0000
Subject: [llvm-commits] [llvm] r107302 - in /llvm/trunk/lib/CodeGen:
	InlineSpiller.cpp Spiller.cpp
Message-ID: <20100630181908.7E8142A6C12C@llvm.org>

Author: stoklund
Date: Wed Jun 30 13:19:08 2010
New Revision: 107302

URL: http://llvm.org/viewvc/llvm-project?rev=107302&view=rev
Log:
Remember to track spill slot uses in VirtRegMap when inserting loads and stores.
LocalRewriter::runOnMachineFunction uses this information to mark dead spill
slots.

This means that InlineSpiller now also works for functions that spill.

Modified:
    llvm/trunk/lib/CodeGen/InlineSpiller.cpp
    llvm/trunk/lib/CodeGen/Spiller.cpp

Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/InlineSpiller.cpp?rev=107302&r1=107301&r2=107302&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/InlineSpiller.cpp (original)
+++ llvm/trunk/lib/CodeGen/InlineSpiller.cpp Wed Jun 30 13:19:08 2010
@@ -95,6 +95,7 @@
       tii_.loadRegFromStackSlot(*MI->getParent(), MII, NewVReg, SS, RC, &tri_);
       --MII; // Point to load instruction.
       SlotIndex LoadIdx = lis_.InsertMachineInstrInMaps(MII).getDefIndex();
+      vrm_.addSpillSlotUse(SS, MII);
       DEBUG(dbgs() << "\treload:  " << LoadIdx << '\t' << *MII);
       VNInfo *LoadVNI = NewLI.getNextValue(LoadIdx, 0, true,
                                            lis_.getVNInfoAllocator());
@@ -124,6 +125,7 @@
                                &tri_);
       --MII; // Point to store instruction.
       SlotIndex StoreIdx = lis_.InsertMachineInstrInMaps(MII).getDefIndex();
+      vrm_.addSpillSlotUse(SS, MII);
       DEBUG(dbgs() << "\tspilled: " << StoreIdx << '\t' << *MII);
       VNInfo *StoreVNI = NewLI.getNextValue(Idx, 0, true,
                                             lis_.getVNInfoAllocator());

Modified: llvm/trunk/lib/CodeGen/Spiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Spiller.cpp?rev=107302&r1=107301&r2=107302&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/Spiller.cpp (original)
+++ llvm/trunk/lib/CodeGen/Spiller.cpp Wed Jun 30 13:19:08 2010
@@ -137,6 +137,7 @@
         MachineInstr *loadInstr(prior(miItr));
         SlotIndex loadIndex =
           lis->InsertMachineInstrInMaps(loadInstr).getDefIndex();
+        vrm->addSpilSlotUse(ss, loadInstr);
         SlotIndex endIndex = loadIndex.getNextIndex();
         VNInfo *loadVNI =
           newLI->getNextValue(loadIndex, 0, true, lis->getVNInfoAllocator());
@@ -150,6 +151,7 @@
         MachineInstr *storeInstr(llvm::next(miItr));
         SlotIndex storeIndex =
           lis->InsertMachineInstrInMaps(storeInstr).getDefIndex();
+        vrm->addSpilSlotUse(ss, storeInstr);
         SlotIndex beginIndex = storeIndex.getPrevIndex();
         VNInfo *storeVNI =
           newLI->getNextValue(beginIndex, 0, true, lis->getVNInfoAllocator());




From anton at korobeynikov.info  Wed Jun 30 13:22:02 2010
From: anton at korobeynikov.info (Anton Korobeynikov)
Date: Wed, 30 Jun 2010 22:22:02 +0400
Subject: [llvm-commits] [llvm] r107205 - in /llvm/trunk:
	bindings/ada/llvm/ docs/ include/llvm-c/ include/llvm/
	include/llvm/CodeGen/ include/llvm/MC/ include/llvm/Target/
	lib/AsmParser/ lib/Bitcode/Reader/ lib/Bitcode/Writer/
	lib/CodeGen/ lib/CodeGen/Asm
Message-ID: <AANLkTinjM6WxlKZyS00rNnWQMckGRUCI3_-XAFmgpyl4@mail.gmail.com>

> Or for every target for that matter. Otherwise, these linkages are restricted to a small subset of usages -- Objective-C metadata on Darwin.
Is it possible to solve the problem in question w/o introducing new
linkage type?
It seems pretty huge overkill to introduce new linkage type for every
small stuff which is used only on one platform, etc.

-- 
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University


From wendling at apple.com  Wed Jun 30 13:30:53 2010
From: wendling at apple.com (Bill Wendling)
Date: Wed, 30 Jun 2010 11:30:53 -0700
Subject: [llvm-commits] [llvm] r107205 - in
	/llvm/trunk:	bindings/ada/llvm/ docs/ include/llvm-c/
	include/llvm/ include/llvm/CodeGen/	include/llvm/MC/
	include/llvm/Target/ lib/AsmParser/
	lib/Bitcode/Reader/	lib/Bitcode/Writer/ lib/CodeGen/ lib/CodeGen/Asm
In-Reply-To: <AANLkTinjM6WxlKZyS00rNnWQMckGRUCI3_-XAFmgpyl4@mail.gmail.com>
References: <AANLkTinjM6WxlKZyS00rNnWQMckGRUCI3_-XAFmgpyl4@mail.gmail.com>
Message-ID: <624ED7C1-0D25-461A-A1C5-D4A5E0CC5943@apple.com>

On Jun 30, 2010, at 11:22 AM, Anton Korobeynikov wrote:

>> Or for every target for that matter. Otherwise, these linkages are restricted to a small subset of usages -- Objective-C metadata on Darwin.
> Is it possible to solve the problem in question w/o introducing new
> linkage type?
> It seems pretty huge overkill to introduce new linkage type for every
> small stuff which is used only on one platform, etc.
> 
Unfortunately, I don't think so. The linkage has to be carried through from the FE to BE. It is possible to use these linkages for non-ObjC metadata. They aren't without merit on their own. :-)

-bw





From gohman at apple.com  Wed Jun 30 13:36:35 2010
From: gohman at apple.com (Dan Gohman)
Date: Wed, 30 Jun 2010 11:36:35 -0700
Subject: [llvm-commits] [llvm] r107205 -
	in	/llvm/trunk:	bindings/ada/llvm/ docs/
	include/llvm-c/	include/llvm/	include/llvm/CodeGen/
	include/llvm/MC/ include/llvm/Target/	lib/AsmParser/
	lib/Bitcode/Reader/	lib/Bitcode/Writer/ lib/CodeGen/
	lib/CodeGen/AsmPrinter/	lib/Linker/ lib/MC/	lib/Target/
	lib/Target/CppBackend/	lib/Target/XCore/AsmPrinter/	lib/Transforms/IPO/
	lib/VMCore/	tools/llvm-nm/
In-Reply-To: <FA99D48A-0561-420D-AA6C-6983AB1AFEC9@apple.com>
References: <20100629212400.DABF32A6C12C@llvm.org>
	<C7E3E4A7-A598-4C61-9513-2DFC7C2EC4CC@apple.com>
	<AF811FB0-E72D-44DD-8BBD-1C6D4971F1AF@gmail.com>
	<FA99D48A-0561-420D-AA6C-6983AB1AFEC9@apple.com>
Message-ID: <9E57AC43-C5F3-418C-8159-F3AF703BA3F1@apple.com>


On Jun 30, 2010, at 8:24 AM, Chris Lattner wrote:

> 
> On Jun 29, 2010, at 3:33 PM, Bill Wendling wrote:
> 
>> On Jun 29, 2010, at 2:56 PM, Chris Lattner wrote:
>> 
>>> On Jun 29, 2010, at 2:24 PM, Bill Wendling wrote:
>>> 
>>>> Author: void
>>>> Date: Tue Jun 29 16:24:00 2010
>>>> New Revision: 107205
>>>> 
>>>> URL: http://llvm.org/viewvc/llvm-project?rev=107205&view=rev
>>>> Log:
>>>> Introducing the "linker_weak" linkage type. This will be used for Objective-C
>>>> metadata types which should be marked as "weak", but which the linker will
>>>> remove upon final linkage.
>>> 
>>> Hi Bill,
>>> 
>>> This would have been good to talk about before you implemented it.  The name linker_weak doesn't seem very descriptive.  How about linker_private_weak or something like that?
>>> 
>> I thought about that, but they aren't private from what I can tell. They're marked as ".globl" and ".weak_definition".
> 
> They are "as private" as other "l" labels, right?  Those are visible across translation units too.  We call it "linker private" so calling this "linker_private_weak" seems reasonable.  Any other suggestions?

How about "objc_linker_private_weak"?

Unless someone here can really spell out what these things really
mean, without mentioning assembler directives, without mentioning
special label naming conventions, without describing it in terms of
what gcc does for Objective C, and without citing "this is what the
Objective C people say we need", and without excluding any magical
semantics, it would be best to avoid confusion.

Dan




From bruno.cardoso at gmail.com  Wed Jun 30 13:38:10 2010
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Wed, 30 Jun 2010 18:38:10 -0000
Subject: [llvm-commits] [llvm] r107306 - in /llvm/trunk:
 lib/Target/X86/X86InstrSSE.td test/MC/AsmParser/X86/x86_32-encoding.s
 test/MC/AsmParser/X86/x86_64-encoding.s
Message-ID: <20100630183810.D72272A6C12C@llvm.org>

Author: bruno
Date: Wed Jun 30 13:38:10 2010
New Revision: 107306

URL: http://llvm.org/viewvc/llvm-project?rev=107306&view=rev
Log:
Add AVX SSE2 mask creation and conditional store instructions

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
    llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=107306&r1=107305&r2=107306&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Jun 30 13:38:10 2010
@@ -2839,29 +2839,55 @@
 } // ExeDomain = SSEPackedInt
 
 //===---------------------------------------------------------------------===//
-// SSE2 - Packed Misc Integer Instructions
+// SSE2 - Packed Mask Creation
 //===---------------------------------------------------------------------===//
 
 let ExeDomain = SSEPackedInt in {
 
-// Mask creation
+let isAsmParserOnly = 1 in
+def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
+           "pmovmskb\t{$src, $dst|$dst, $src}",
+           [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>, VEX;
 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
-                     "pmovmskb\t{$src, $dst|$dst, $src}",
-                     [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
+           "pmovmskb\t{$src, $dst|$dst, $src}",
+           [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
+
+} // ExeDomain = SSEPackedInt
 
-// Conditional store
+//===---------------------------------------------------------------------===//
+// SSE2 - Conditional Store
+//===---------------------------------------------------------------------===//
+
+let ExeDomain = SSEPackedInt in {
+
+let isAsmParserOnly = 1 in {
 let Uses = [EDI] in
-def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
-                     "maskmovdqu\t{$mask, $src|$src, $mask}",
-                     [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
+def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
+           (ins VR128:$src, VR128:$mask),
+           "maskmovdqu\t{$mask, $src|$src, $mask}",
+           [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>, VEX;
+let Uses = [RDI] in
+def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
+           (ins VR128:$src, VR128:$mask),
+           "maskmovdqu\t{$mask, $src|$src, $mask}",
+           [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>, VEX;
+}
 
+let Uses = [EDI] in
+def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
+           "maskmovdqu\t{$mask, $src|$src, $mask}",
+           [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
 let Uses = [RDI] in
 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
-                     "maskmovdqu\t{$mask, $src|$src, $mask}",
-                     [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
+           "maskmovdqu\t{$mask, $src|$src, $mask}",
+           [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
 
 } // ExeDomain = SSEPackedInt
 
+//===---------------------------------------------------------------------===//
+// SSE2 - Packed Misc Integer Instructions
+//===---------------------------------------------------------------------===//
+
 // Flush cache
 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
                "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s?rev=107306&r1=107305&r2=107306&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s Wed Jun 30 13:38:10 2010
@@ -11494,3 +11494,11 @@
 // CHECK: encoding: [0xc5,0xf9,0xc5,0xc2,0x07]
           vpextrw  $7, %xmm2, %eax
 
+// CHECK: vpmovmskb  %xmm1, %eax
+// CHECK: encoding: [0xc5,0xf9,0xd7,0xc1]
+          vpmovmskb  %xmm1, %eax
+
+// CHECK: vmaskmovdqu  %xmm1, %xmm2
+// CHECK: encoding: [0xc5,0xf9,0xf7,0xd1]
+          vmaskmovdqu  %xmm1, %xmm2
+

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s?rev=107306&r1=107305&r2=107306&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s Wed Jun 30 13:38:10 2010
@@ -1534,3 +1534,11 @@
 // CHECK: encoding: [0xc4,0xc1,0x79,0xc5,0xc4,0x07]
           vpextrw  $7, %xmm12, %eax
 
+// CHECK: vpmovmskb  %xmm12, %eax
+// CHECK: encoding: [0xc4,0xc1,0x79,0xd7,0xc4]
+          vpmovmskb  %xmm12, %eax
+
+// CHECK: vmaskmovdqu  %xmm14, %xmm15
+// CHECK: encoding: [0xc4,0x41,0x79,0xf7,0xfe]
+          vmaskmovdqu  %xmm14, %xmm15
+




From stoklund at 2pi.dk  Wed Jun 30 13:41:20 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Wed, 30 Jun 2010 18:41:20 -0000
Subject: [llvm-commits] [llvm] r107307 - /llvm/trunk/lib/CodeGen/Spiller.cpp
Message-ID: <20100630184120.E58AD2A6C12C@llvm.org>

Author: stoklund
Date: Wed Jun 30 13:41:20 2010
New Revision: 107307

URL: http://llvm.org/viewvc/llvm-project?rev=107307&view=rev
Log:
Some fool committed without testing (or even building) first.

Modified:
    llvm/trunk/lib/CodeGen/Spiller.cpp

Modified: llvm/trunk/lib/CodeGen/Spiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Spiller.cpp?rev=107307&r1=107306&r2=107307&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/Spiller.cpp (original)
+++ llvm/trunk/lib/CodeGen/Spiller.cpp Wed Jun 30 13:41:20 2010
@@ -137,7 +137,7 @@
         MachineInstr *loadInstr(prior(miItr));
         SlotIndex loadIndex =
           lis->InsertMachineInstrInMaps(loadInstr).getDefIndex();
-        vrm->addSpilSlotUse(ss, loadInstr);
+        vrm->addSpillSlotUse(ss, loadInstr);
         SlotIndex endIndex = loadIndex.getNextIndex();
         VNInfo *loadVNI =
           newLI->getNextValue(loadIndex, 0, true, lis->getVNInfoAllocator());
@@ -151,7 +151,7 @@
         MachineInstr *storeInstr(llvm::next(miItr));
         SlotIndex storeIndex =
           lis->InsertMachineInstrInMaps(storeInstr).getDefIndex();
-        vrm->addSpilSlotUse(ss, storeInstr);
+        vrm->addSpillSlotUse(ss, storeInstr);
         SlotIndex beginIndex = storeIndex.getPrevIndex();
         VNInfo *storeVNI =
           newLI->getNextValue(beginIndex, 0, true, lis->getVNInfoAllocator());




From isanbard at gmail.com  Wed Jun 30 13:47:45 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 30 Jun 2010 11:47:45 -0700
Subject: [llvm-commits] [llvm] r107205 -
	in	/llvm/trunk:	bindings/ada/llvm/ docs/
	include/llvm-c/	include/llvm/	include/llvm/CodeGen/
	include/llvm/MC/ include/llvm/Target/	lib/AsmParser/
	lib/Bitcode/Reader/	lib/Bitcode/Writer/ lib/CodeGen/
	lib/CodeGen/AsmPrinter/	lib/Linker/ lib/MC/	lib/Target/
	lib/Target/CppBackend/	lib/Target/XCore/AsmPrinter/	lib/Transforms/IPO/
	lib/VMCore/	tools/llvm-nm/
In-Reply-To: <9E57AC43-C5F3-418C-8159-F3AF703BA3F1@apple.com>
References: <20100629212400.DABF32A6C12C@llvm.org>
	<C7E3E4A7-A598-4C61-9513-2DFC7C2EC4CC@apple.com>
	<AF811FB0-E72D-44DD-8BBD-1C6D4971F1AF@gmail.com>
	<FA99D48A-0561-420D-AA6C-6983AB1AFEC9@apple.com>
	<9E57AC43-C5F3-418C-8159-F3AF703BA3F1@apple.com>
Message-ID: <79223963-640D-43E4-BB73-0D3D9DD729D6@gmail.com>

On Jun 30, 2010, at 11:36 AM, Dan Gohman wrote:

> On Jun 30, 2010, at 8:24 AM, Chris Lattner wrote:
> 
>> 
>> On Jun 29, 2010, at 3:33 PM, Bill Wendling wrote:
>> 
>>> On Jun 29, 2010, at 2:56 PM, Chris Lattner wrote:
>>> 
>>>> On Jun 29, 2010, at 2:24 PM, Bill Wendling wrote:
>>>> 
>>>>> Author: void
>>>>> Date: Tue Jun 29 16:24:00 2010
>>>>> New Revision: 107205
>>>>> 
>>>>> URL: http://llvm.org/viewvc/llvm-project?rev=107205&view=rev
>>>>> Log:
>>>>> Introducing the "linker_weak" linkage type. This will be used for Objective-C
>>>>> metadata types which should be marked as "weak", but which the linker will
>>>>> remove upon final linkage.
>>>> 
>>>> Hi Bill,
>>>> 
>>>> This would have been good to talk about before you implemented it.  The name linker_weak doesn't seem very descriptive.  How about linker_private_weak or something like that?
>>>> 
>>> I thought about that, but they aren't private from what I can tell. They're marked as ".globl" and ".weak_definition".
>> 
>> They are "as private" as other "l" labels, right?  Those are visible across translation units too.  We call it "linker private" so calling this "linker_private_weak" seems reasonable.  Any other suggestions?
> 
> How about "objc_linker_private_weak"?
> 
> Unless someone here can really spell out what these things really
> mean, without mentioning assembler directives, without mentioning
> special label naming conventions, without describing it in terms of
> what gcc does for Objective C, and without citing "this is what the
> Objective C people say we need", and without excluding any magical
> semantics, it would be best to avoid confusion.
> 
I view these linkages as being like their non-"linker linkage" counterparts, but that the linker will remove them from the final linked image. So, "linker_private" is "private" but the linker will remove it from the final linked image and so on. "linker_private_weak" has no non-"linker linkage" counterpart, but its semantics are a natural progression maybe?

-bw




From bruno.cardoso at gmail.com  Wed Jun 30 13:49:10 2010
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Wed, 30 Jun 2010 18:49:10 -0000
Subject: [llvm-commits] [llvm] r107308 -
	/llvm/trunk/lib/Target/X86/X86InstrSSE.td
Message-ID: <20100630184910.9E91B2A6C12C@llvm.org>

Author: bruno
Date: Wed Jun 30 13:49:10 2010
New Revision: 107308

URL: http://llvm.org/viewvc/llvm-project?rev=107308&view=rev
Log:
Move MOVD/MODQ code around, creating sections for each of them

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=107308&r1=107307&r2=107308&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Jun 30 13:49:10 2010
@@ -2885,41 +2885,9 @@
 } // ExeDomain = SSEPackedInt
 
 //===---------------------------------------------------------------------===//
-// SSE2 - Packed Misc Integer Instructions
+// SSE2 - Move Doubleword
 //===---------------------------------------------------------------------===//
 
-// Flush cache
-def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
-               "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
-              TB, Requires<[HasSSE2]>;
-
-// Load, store, and memory fence
-def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
-               "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
-def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
-               "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
-
-// Pause. This "instruction" is encoded as "rep; nop", so even though it
-// was introduced with SSE2, it's backward compatible.
-def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
-
-//TODO: custom lower this so as to never even generate the noop
-def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
-           (i8 0)), (NOOP)>;
-def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
-def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
-def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
-           (i8 1)), (MFENCE)>;
-
-// Alias instructions that map zero vector to pxor / xorp* for sse.
-// We set canFoldAsLoad because this can be converted to a constant-pool
-// load of an all-ones value if folding it would be beneficial.
-let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
-    isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
-  // FIXME: Change encoding to pseudo.
-  def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
-                         [(set VR128:$dst, (v4i32 immAllOnesV))]>;
-
 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
                       "movd\t{$src, $dst|$dst, $src}",
                       [(set VR128:$dst,
@@ -2937,20 +2905,6 @@
                       "movd\t{$src, $dst|$dst, $src}",
                       [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
 
-// SSE2 instructions with XS prefix
-def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
-                    "movq\t{$src, $dst|$dst, $src}",
-                    [(set VR128:$dst,
-                      (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
-                  Requires<[HasSSE2]>;
-def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
-                      "movq\t{$src, $dst|$dst, $src}",
-                      [(store (i64 (vector_extract (v2i64 VR128:$src),
-                                    (iPTR 0))), addr:$dst)]>;
-
-def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
-          (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
-
 def MOVPDI2DIrr  : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
                        "movd\t{$src, $dst|$dst, $src}",
                        [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
@@ -2967,11 +2921,6 @@
                       "movd\t{$src, $dst|$dst, $src}",
                       [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
 
-// Store / copy lower 64-bits of a XMM register.
-def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
-                     "movq\t{$src, $dst|$dst, $src}",
-                     [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
-
 // movd / movq to XMM register zero-extends
 let AddedComplexity = 15 in {
 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
@@ -2998,7 +2947,32 @@
             (MOVZDI2PDIrm addr:$src)>;
 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
             (MOVZDI2PDIrm addr:$src)>;
+}
+
+//===---------------------------------------------------------------------===//
+// SSE2 - Move Quadword
+//===---------------------------------------------------------------------===//
 
+// SSE2 instructions with XS prefix
+def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
+                    "movq\t{$src, $dst|$dst, $src}",
+                    [(set VR128:$dst,
+                      (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
+                  Requires<[HasSSE2]>;
+def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
+                      "movq\t{$src, $dst|$dst, $src}",
+                      [(store (i64 (vector_extract (v2i64 VR128:$src),
+                                    (iPTR 0))), addr:$dst)]>;
+
+def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
+          (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
+
+// Store / copy lower 64-bits of a XMM register.
+def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
+                     "movq\t{$src, $dst|$dst, $src}",
+                     [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
+
+let AddedComplexity = 20 in {
 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
                      "movq\t{$src, $dst|$dst, $src}",
                      [(set VR128:$dst,
@@ -3040,6 +3014,42 @@
                  "movq\t{$src, $dst|$dst, $src}", []>, XS;
 
 //===---------------------------------------------------------------------===//
+// SSE2 - Misc Instructions
+//===---------------------------------------------------------------------===//
+
+// Flush cache
+def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
+               "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
+              TB, Requires<[HasSSE2]>;
+
+// Load, store, and memory fence
+def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
+               "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
+def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
+               "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
+
+// Pause. This "instruction" is encoded as "rep; nop", so even though it
+// was introduced with SSE2, it's backward compatible.
+def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
+
+//TODO: custom lower this so as to never even generate the noop
+def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
+           (i8 0)), (NOOP)>;
+def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
+def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
+def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
+           (i8 1)), (MFENCE)>;
+
+// Alias instructions that map zero vector to pxor / xorp* for sse.
+// We set canFoldAsLoad because this can be converted to a constant-pool
+// load of an all-ones value if folding it would be beneficial.
+let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
+    isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
+  // FIXME: Change encoding to pseudo.
+  def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
+                         [(set VR128:$dst, (v4i32 immAllOnesV))]>;
+
+//===---------------------------------------------------------------------===//
 // SSE3 Instructions
 //===---------------------------------------------------------------------===//
 




From matt at console-pimps.org  Wed Jun 30 14:13:11 2010
From: matt at console-pimps.org (Matt Fleming)
Date: Wed, 30 Jun 2010 20:13:11 +0100
Subject: [llvm-commits] [PATCH] Add some more ELF OSABI values.
Message-ID: <8806a9216ebe6844ecf8f510b1187ebc4d6e8345.1277924817.git.matt@console-pimps.org>

Hi,

does anyone have any issue with me committing the following patch? I've
been carrying it in my git repository containing the ELF MC support, but
there should be no problem with it going into trunk.

Any objections?

---
 include/llvm/Support/ELF.h |   23 +++++++++++++++++++++--
 1 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/include/llvm/Support/ELF.h b/include/llvm/Support/ELF.h
index 51403ff..6e863f8 100644
--- a/include/llvm/Support/ELF.h
+++ b/include/llvm/Support/ELF.h
@@ -150,9 +150,28 @@ enum {
   ELFDATA2MSB = 2  // Big-endian object file
 };
 
-// OS ABI identification -- unused.
+// OS ABI identification.
 enum {
-  ELFOSABI_NONE = 0
+  ELFOSABI_NONE = 0,          // UNIX System V ABI
+  ELFOSABI_HPUX = 1,          // HP-UX operating system
+  ELFOSABI_NETBSD = 2,        // NetBSD
+  ELFOSABI_LINUX = 3,         // GNU/Linux
+  ELFOSABI_HURD = 4,          // GNU/Hurd
+  ELFOSABI_SOLARIS = 6,       // Solaris
+  ELFOSABI_AIX = 7,           // AIX
+  ELFOSABI_IRIX = 8,          // IRIX
+  ELFOSABI_FREEBSD = 9,       // FreeBSD
+  ELFOSABI_TRU64 = 10,        // TRU64 UNIX
+  ELFOSABI_MODESTO = 11,      // Novell Modesto
+  ELFOSABI_OPENBSD = 12,      // OpenBSD
+  ELFOSABI_OPENVMS = 13,      // OpenVMS
+  ELFOSABI_NSK = 14,          // Hewlett-Packard Non-Stop Kernel
+  ELFOSABI_AROS = 15,         // AROS
+  ELFOSABI_FENIXOS = 16,      // FenixOS
+  ELFOSABI_C6000_ELFABI = 64, // Bare-metal TMS320C6000
+  ELFOSABI_C6000_LINUX = 65,  // Linux TMS320C6000
+  ELFOSABI_ARM = 97,          // ARM
+  ELFOSABI_STANDALONE = 255   // Standalone (embedded) application
 };
 
 // Section header.
-- 
1.6.4.rc0



From scanon at apple.com  Wed Jun 30 14:17:37 2010
From: scanon at apple.com (Stephen Canon)
Date: Wed, 30 Jun 2010 12:17:37 -0700
Subject: [llvm-commits] [compiler-rt][patch] add soft-float comparisons to
	compiler-rt
Message-ID: <DBC5C16E-E952-4CD2-BFD9-7B96277A189A@apple.com>

This patch provides the following routines for compiler-rt:

__eqdf2   __gedf2   __nedf2  __ledf2   __gtdf2  __ltdf2  __unorddf2
__eqsf2   __gesf2   __nesf2  __lesf2   __gtsf2  __ltsf2  __unordsf2

These are present in libgcc when it is built for platforms that lack hardware floating-point support.

- Steve

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From matt at console-pimps.org  Wed Jun 30 14:22:29 2010
From: matt at console-pimps.org (Matt Fleming)
Date: Wed, 30 Jun 2010 20:22:29 +0100
Subject: [llvm-commits] [PATCH] add X86_64 relocation entries
Message-ID: <4dfdc3f12a1a3a254f22b03f8d26a382c3424391.1277925479.git.matt@console-pimps.org>

From: Roman Divacky <rdivacky at pes.vlakno.cz>

Here's another patch that adds some ELF values, this one from Roman
Divacky. If no one yells I'll commit this later this week.

---
 include/llvm/Support/ELF.h |   69 ++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 69 insertions(+), 0 deletions(-)

diff --git a/include/llvm/Support/ELF.h b/include/llvm/Support/ELF.h
index 6e863f8..3d413d5 100644
--- a/include/llvm/Support/ELF.h
+++ b/include/llvm/Support/ELF.h
@@ -174,6 +174,42 @@ enum {
   ELFOSABI_STANDALONE = 255   // Standalone (embedded) application
 };
 
+// X86_64 relocations
+enum {
+  R_X86_64_NONE       = 0,
+  R_X86_64_64         = 1,
+  R_X86_64_PC32       = 2,
+  R_X86_64_GOT32      = 3,
+  R_X86_64_PLT32      = 4,
+  R_X86_64_COPY       = 5,
+  R_X86_64_GLOB_DAT   = 6,
+  R_X86_64_JUMP_SLOT  = 7,
+  R_X86_64_RELATIVE   = 8,
+  R_X86_64_GOTPCREL   = 9,
+  R_X86_64_32         = 10,
+  R_X86_64_32S        = 11,
+  R_X86_64_16         = 12,
+  R_X86_64_PC16       = 13,
+  R_X86_64_8          = 14,
+  R_X86_64_PC8        = 15,
+  R_X86_64_DTPMOD64   = 16,
+  R_X86_64_DTPOFF64   = 17,
+  R_X86_64_TPOFF64    = 18,
+  R_X86_64_TLSGD      = 19,
+  R_X86_64_TLSLD      = 20,
+  R_X86_64_DTPOFF32   = 21,
+  R_X86_64_GOTTPOFF   = 22,
+  R_X86_64_TPOFF32    = 23,
+  R_X86_64_PC64       = 24,
+  R_X86_64_GOTOFF64   = 25,
+  R_X86_64_GOTPC32    = 26,
+  R_X86_64_SIZE32     = 32,
+  R_X86_64_SIZE64     = 33,
+  R_X86_64_GOTPC32_TLSDESC = 34,
+  R_X86_64_TLSDESC_CALL    = 35,
+  R_X86_64_TLSDESC    = 36
+};
+
 // Section header.
 struct Elf32_Shdr {
   Elf32_Word sh_name;      // Section name (index into string table)
@@ -339,6 +375,39 @@ struct Elf32_Rela {
   };
 };
 
+// Relocation entry, without explicit addend.
+struct Elf64_Rel {
+  Elf64_Addr r_offset; // Location (file byte offset, or program virtual addr)
+  Elf64_Xword r_info;   // Symbol table index and type of relocation to apply
+
+  // These accessors and mutators correspond to the ELF64_R_SYM, ELF64_R_TYPE,
+  // and ELF64_R_INFO macros defined in the ELF specification:
+  Elf64_Xword getSymbol () const { return (r_info >> 32); }
+  unsigned char getType () const { return (unsigned char) (r_info & 0xffffffffL); }
+  void setSymbol (Elf32_Word s) { setSymbolAndType (s, getType ()); }
+  void setType (unsigned char t) { setSymbolAndType (getSymbol(), t); }
+  void setSymbolAndType (Elf64_Xword s, unsigned char t) {
+    r_info = (s << 32) + (t&0xffffffffL);
+  };
+};
+
+// Relocation entry with explicit addend.
+struct Elf64_Rela {
+  Elf64_Addr  r_offset; // Location (file byte offset, or program virtual addr)
+  Elf64_Xword  r_info;   // Symbol table index and type of relocation to apply
+  Elf64_Sxword r_addend; // Compute value for relocatable field by adding this
+
+  // These accessors and mutators correspond to the ELF64_R_SYM, ELF64_R_TYPE,
+  // and ELF64_R_INFO macros defined in the ELF specification:
+  Elf64_Xword getSymbol () const { return (r_info >> 32); }
+  unsigned char getType () const { return (unsigned char) (r_info & 0xffffffffL); }
+  void setSymbol (Elf64_Xword s) { setSymbolAndType (s, getType ()); }
+  void setType (unsigned char t) { setSymbolAndType (getSymbol(), t); }
+  void setSymbolAndType (Elf64_Xword s, unsigned char t) {
+    r_info = (s << 32) + (t&0xffffffffL);
+  };
+};
+
 // Program header.
 struct Elf32_Phdr {
   Elf32_Word p_type;   // Type of segment
-- 
1.6.4.rc0



From scanon at apple.com  Wed Jun 30 14:24:55 2010
From: scanon at apple.com (Stephen Canon)
Date: Wed, 30 Jun 2010 12:24:55 -0700
Subject: [llvm-commits] [compiler-rt][patch] add soft-float addition and
	subtraction to compiler-rt
Message-ID: <539F1216-67CD-43D5-AB05-52709CF7BF90@apple.com>

This patch provides single- and double-precision soft-float addition and subtraction routines for compiler-rt:

__adddf3  __subdf3
__addsf3  __subsf3

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- Steve

From criswell at uiuc.edu  Wed Jun 30 14:34:16 2010
From: criswell at uiuc.edu (John Criswell)
Date: Wed, 30 Jun 2010 19:34:16 -0000
Subject: [llvm-commits] [poolalloc] r107313 - in /poolalloc/trunk/test:
 Makefile TEST.calltargets.Makefile TEST.calltargets.report
Message-ID: <20100630193416.E2D112A6C12C@llvm.org>

Author: criswell
Date: Wed Jun 30 14:34:16 2010
New Revision: 107313

URL: http://llvm.org/viewvc/llvm-project?rev=107313&view=rev
Log:
Added a test to compute the call targets of indirect function calls.

Added:
    poolalloc/trunk/test/TEST.calltargets.Makefile
    poolalloc/trunk/test/TEST.calltargets.report
Modified:
    poolalloc/trunk/test/Makefile

Modified: poolalloc/trunk/test/Makefile
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/Makefile?rev=107313&r1=107312&r2=107313&view=diff
==============================================================================
--- poolalloc/trunk/test/Makefile (original)
+++ poolalloc/trunk/test/Makefile Wed Jun 30 14:34:16 2010
@@ -41,8 +41,13 @@
 NORMAL_PROBLEM_SIZE_DIRS := \
    MultiSource/Benchmarks/Olden \
    External/SPEC/CINT2000 \
-   #MultiSource/Benchmarks/Olden/bh \
+   #MultiSource/Applications \
+   #MultiSource/Applications/Burg \
+   #MultiSource/Applications/hexxagon \
+   #MultiSource/Applications/kimwitu++ \
+   #MultiSource/Applications/lambda-0.1.3 \
    #External/SPEC/CINT2000/175.vpr \
+   #MultiSource/Benchmarks/Olden/bh \
    #External/SPEC/CINT2000/181.mcf \
    #External/SPEC/CINT2000/186.crafty \
    #External/FPGrowth \
@@ -160,6 +165,30 @@
         done
 	@printf "\a"; sleep 1; printf "\a"; sleep 1; printf "\a"
 
+# Program tests for DSA Call Targets
+progcall::
+	for dir in $(LARGE_PROBLEM_SIZE_DIRS); do \
+            (cd $$dir; \
+               PROJECT_DIR=$(PROJ_OBJ_ROOT) $(MAKE) -j1 TEST=calltargets \
+                   LARGE_PROBLEM_SIZE=1 report.html) \
+        done
+	for dir in $(NORMAL_PROBLEM_SIZE_DIRS); do \
+	    (cd $$dir; \
+               PROJECT_DIR=$(PROJ_OBJ_ROOT) $(MAKE) -j1 TEST=calltargets \
+                   report.html) \
+        done
+	@for dir in $(LARGE_PROBLEM_SIZE_DIRS); do \
+            (cd $$dir; \
+               PROJECT_DIR=$(PROJ_OBJ_ROOT) $(MAKE) -s -j1 TEST=calltargets \
+                   LARGE_PROBLEM_SIZE=1 report) \
+        done
+	@for dir in $(NORMAL_PROBLEM_SIZE_DIRS); do \
+	    (cd $$dir; \
+               PROJECT_DIR=$(PROJ_OBJ_ROOT) $(MAKE) -s -j1 TEST=calltargets \
+                   report) \
+        done
+	@printf "\a"; sleep 1; printf "\a"; sleep 1; printf "\a"
+
 # Program tests for Pool Allocation
 progtest::
 	for dir in $(LARGE_PROBLEM_SIZE_DIRS); do \

Added: poolalloc/trunk/test/TEST.calltargets.Makefile
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/TEST.calltargets.Makefile?rev=107313&view=auto
==============================================================================
--- poolalloc/trunk/test/TEST.calltargets.Makefile (added)
+++ poolalloc/trunk/test/TEST.calltargets.Makefile Wed Jun 30 14:34:16 2010
@@ -0,0 +1,95 @@
+##===- poolalloc/test/TEST.poolalloc.Makefile --------------*- Makefile -*-===##
+#
+# This test runs the pool allocator on all of the Programs, producing some
+# performance numbers and statistics.
+#
+##===----------------------------------------------------------------------===##
+
+CFLAGS = -O2 -fno-strict-aliasing
+
+EXTRA_PA_FLAGS := 
+
+# HEURISTIC can be set to:
+#   AllNodes
+ifdef HEURISTIC
+EXTRA_PA_FLAGS += -poolalloc-heuristic=$(HEURISTIC)
+endif
+
+
+CURDIR  := $(shell cd .; pwd)
+PROGDIR := $(shell cd $(LLVM_SRC_ROOT)/projects/test-suite; pwd)/
+RELDIR  := $(subst $(PROGDIR),,$(CURDIR))
+PADIR   := $(LLVM_OBJ_ROOT)/projects/poolalloc
+
+# Watchdog utility
+WATCHDOG := $(LLVM_OBJ_ROOT)/projects/poolalloc/$(CONFIGURATION)/bin/watchdog
+
+# Bits of runtime to improve analysis
+PA_PRE_RT := $(PADIR)/$(CONFIGURATION)/lib/libpa_pre_rt.bca
+
+# Pool allocator pass shared object
+PA_SO    := $(PADIR)/$(CONFIGURATION)/lib/libpoolalloc$(SHLIBEXT)
+DSA_SO   := $(PADIR)/$(CONFIGURATION)/lib/libLLVMDataStructure$(SHLIBEXT)
+ASSIST_SO := $(PADIR)/$(CONFIGURATION)/lib/libAssistDS$(SHLIBEXT)
+
+# Pool allocator runtime library
+#PA_RT    := $(PADIR)/$(CONFIGURATION)/lib/libpoolalloc_fl_rt.bc
+#PA_RT_O  := $(PROJECT_DIR)/lib/$(CONFIGURATION)/poolalloc_rt.o
+PA_RT_O  := $(PADIR)/$(CONFIGURATION)/lib/libpoolalloc_rt.a
+#PA_RT_O  := $(PROJECT_DIR)/lib/$(CONFIGURATION)/poolalloc_fl_rt.o
+
+# Command to run opt with the pool allocator pass loaded
+OPT_PA := $(WATCHDOG) $(LOPT) -load $(DSA_SO) -load $(PA_SO)
+
+# OPT_PA_STATS - Run opt with the -stats and -time-passes options, capturing the
+# output to a file.
+OPT_PA_STATS = $(OPT_PA) -info-output-file=$(CURDIR)/$@.info -stats -time-passes
+
+OPTZN_PASSES := -globaldce -ipsccp -deadargelim -adce -instcombine -simplifycfg
+
+
+$(PROGRAMS_TO_TEST:%=Output/%.temp.bc): \
+Output/%.temp.bc: Output/%.llvm.bc 
+	-$(LLVMLD) -link-as-library $< $(PA_PRE_RT) -o $@
+
+$(PROGRAMS_TO_TEST:%=Output/%.base.bc): \
+Output/%.base.bc: Output/%.temp.bc $(LOPT) $(ASSIST_SO)
+	-$(LOPT) -load $(ASSIST_SO) -instnamer -internalize -indclone -funcspec -ipsccp -deadargelim -instcombine -globaldce -stats $< -f -o $@ 
+
+# This rule runs the pool allocator on the .base.bc file to produce a new .bc
+# file
+$(PROGRAMS_TO_TEST:%=Output/%.calltargets.data): \
+Output/%.calltargets.data: Output/%.base.bc $(PA_SO) $(LOPT)
+	- at rm -f $(CURDIR)/$@.info
+	-$(OPT_PA_STATS) -analyze -internalize -calltarget $< 2>&1 > $@
+
+# This rule wraps everything together to build the actual output the report is
+# generated from.
+$(PROGRAMS_TO_TEST:%=Output/%.$(TEST).report.txt): \
+Output/%.$(TEST).report.txt: Output/%.out-nat                \
+                             Output/%.calltargets.data       \
+                             Output/%.LOC.txt
+	@-cat $<
+	@echo > $@
+	@echo "---------------------------------------------------------------" >> $@
+	@echo ">>> ========= '$(RELDIR)/$*' Program" >> $@
+	@echo "---------------------------------------------------------------" >> $@
+	@echo >> $@
+	@-if test -f Output/$*.nonpa.diff-nat; then \
+	  printf "GCC-RUN-TIME: " >> $@;\
+	  grep "^program" Output/$*.out-nat.time >> $@;\
+        fi
+	-printf "LOC: " >> $@
+	-cat Output/$*.LOC.txt >> $@
+	@-cat Output/$*.$(TEST).bc.info >> $@
+	@#cat Output/$*.$(TEST).basepa.bc.out  >> $@
+
+
+$(PROGRAMS_TO_TEST:%=test.$(TEST).%): \
+test.$(TEST).%: Output/%.$(TEST).report.txt
+	@echo "---------------------------------------------------------------"
+	@echo ">>> ========= '$(RELDIR)/$*' Program"
+	@echo "---------------------------------------------------------------"
+	@-cat $<
+
+REPORT_DEPENDENCIES := $(PA_RT_O) $(PA_SO) $(PROGRAMS_TO_TEST:%=Output/%.llvm.bc) $(LLC) $(LOPT)

Added: poolalloc/trunk/test/TEST.calltargets.report
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/TEST.calltargets.report?rev=107313&view=auto
==============================================================================
--- poolalloc/trunk/test/TEST.calltargets.report (added)
+++ poolalloc/trunk/test/TEST.calltargets.report Wed Jun 30 14:34:16 2010
@@ -0,0 +1,85 @@
+##=== TEST.poolalloc.report - Report description for poolalloc -*- perl -*-===##
+#
+# This file defines a report to be generated for the pool allocator tests.
+#
+##===----------------------------------------------------------------------===##
+
+# Sort by program name
+$SortCol = 0;
+$TrimRepeatedPrefix = 1;
+
+# FormatTime - Convert a time from 1m23.45 into 83.45
+sub FormatTime {
+  my $Time = shift;
+  if ($Time =~ m/([0-9]+)[m:]([0-9.]+)/) {
+    return sprintf("%7.3f", $1*60.0+$2);
+  }
+
+  return sprintf("%6.2f", $Time);
+}
+
+
+sub RuntimePercent {
+  my ($Cols, $Col) = @_;
+  if ($Cols->[$Col-1] ne "*" and $Cols->[4] ne "*" and
+      $Cols->[4] != "0") {
+    return sprintf "%7.2f", 100*$Cols->[$Col-1]/$Cols->[4];
+  } else {
+    return "n/a";
+  }
+}
+
+ at LatexColumns = (1, 5, 8, 12, 9, 13, 14, 15, 2, 16);
+
+my $FREEBENCH = 'MultiSource/Benchmarks/FreeBench';
+my $PTRDIST   = 'MultiSource/Benchmarks/Ptrdist';
+
+ at LatexRowMapOrder = (
+                     '164.gzip/164.gzip' => '164.gzip',
+                     '175.vpr/175.vpr' => '175.vpr',
+                     '181.mcf/181.mcf' => '181.mcf',
+                     '186.crafty/186.crafty' => '186.crafty',
+                     '197.parser/197.parser' => '197.parser',
+                     '197.parser.hacked/197.parser.hacked' => '197.parser(b)',
+                     '255.vortex/255.vortex' => '255.vortex',
+                     '256.bzip2/256.bzip2' => '256.bzip2',
+                     '300.twolf/300.twolf' => '300.twolf',
+                     '-' => '-',
+                     "anagram/anagram"       => 'anagram',
+                     "bc/bc"                 => 'bc',
+                     "ft/ft"                 => 'ft',
+                     "ks/ks"                 => 'ks',
+                     "yacr2/yacr2"           => 'yacr2',
+                     '-' => '-',
+                     "analyzer"     => 'analyzer',
+                     "neural"       => 'neural',
+                     "pcompress2"   => 'pcompress2',
+                     "piff2"        => 'piff2',
+                     '-' => '-',
+                     "bh/bh" => 'bh',
+                     "bisort/bisort" => 'bisort',
+                     "em3d/em3d" => 'em3d',
+                     "health/health" => 'health',
+                     "mst/mst" => 'mst',
+                     "perimeter/perimeter" => 'perimeter',
+                     "power/power" => 'power',
+                     "treeadd/treeadd" => 'treeadd',
+                     "tsp/tsp" => 'tsp',
+                     '-' => '-',
+                     "llu"          => 'llu-bench',
+                  );
+
+
+# These are the columns for the report.  The first entry is the header for the
+# column, the second is the regex to use to match the value.  Empty list create
+# seperators, and closures may be put in for custom processing.
+(
+# Name
+ ["Name:" , '\'([^\']+)\' Program'],
+ ["LOC"   , 'LOC:\s*([0-9]+)'],
+ [],
+# Times
+ ["GCC",            'GCC-RUN-TIME: program\s*([.0-9m:]+)', \&FormatTime],
+ []
+);
+




From peter at pcc.me.uk  Wed Jun 30 14:39:45 2010
From: peter at pcc.me.uk (Peter Collingbourne)
Date: Wed, 30 Jun 2010 20:39:45 +0100
Subject: [llvm-commits] [PATCH (need approval)] Add support for InsertValue
	and ExtractValue to gep_type_iterator
Message-ID: <1277926785-28322-1-git-send-email-peter@pcc.me.uk>

---
Hi,

This adds iv_type_iterator, ev_type_iterator and vce_type_iterator
to complement gep_type_iterator.

I'm not 100% certain this is the right way to do this.  Perhaps we
should introduce an Operator for generically accessing the index
iterators for {Insert,Extract}Values.  This would work right now
because all the iterators are of underlying type const unsigned *
but of course this may change in the future.

Thanks,
Peter

 include/llvm/Support/GetElementPtrTypeIterator.h |   38 ++++++++++++++++++++-
 1 files changed, 36 insertions(+), 2 deletions(-)

diff --git a/include/llvm/Support/GetElementPtrTypeIterator.h b/include/llvm/Support/GetElementPtrTypeIterator.h
index e5e7fc7..35046fe 100644
--- a/include/llvm/Support/GetElementPtrTypeIterator.h
+++ b/include/llvm/Support/GetElementPtrTypeIterator.h
@@ -8,7 +8,7 @@
 //===----------------------------------------------------------------------===//
 //
 // This file implements an iterator for walking through the types indexed by
-// getelementptr instructions.
+// getelementptr, insertvalue and extractvalue instructions.
 //
 //===----------------------------------------------------------------------===//
 
@@ -17,6 +17,7 @@
 
 #include "llvm/User.h"
 #include "llvm/DerivedTypes.h"
+#include "llvm/Instructions.h"
 
 namespace llvm {
   template<typename ItTy = User::const_op_iterator>
@@ -28,6 +29,12 @@ namespace llvm {
     ItTy OpIt;
     const Type *CurTy;
     generic_gep_type_iterator() {}
+
+    Value *asValue(Value *V) const { return V; }
+    Value *asValue(unsigned U) const {
+      return ConstantInt::get(CurTy->getContext(), APInt(32, U));
+    }
+
   public:
 
     static generic_gep_type_iterator begin(const Type *Ty, ItTy It) {
@@ -63,7 +70,7 @@ namespace llvm {
     // current type directly.
     const Type *operator->() const { return operator*(); }
 
-    Value *getOperand() const { return *OpIt; }
+    Value *getOperand() const { return asValue(*OpIt); }
 
     generic_gep_type_iterator& operator++() {   // Preincrement
       if (const CompositeType *CT = dyn_cast<CompositeType>(CurTy)) {
@@ -81,6 +88,9 @@ namespace llvm {
   };
 
   typedef generic_gep_type_iterator<> gep_type_iterator;
+  typedef generic_gep_type_iterator<ExtractValueInst::idx_iterator> ev_type_iterator;
+  typedef generic_gep_type_iterator<InsertValueInst::idx_iterator> iv_type_iterator;
+  typedef generic_gep_type_iterator<SmallVector<unsigned, 4>::const_iterator> vce_type_iterator;
 
   inline gep_type_iterator gep_type_begin(const User *GEP) {
     return gep_type_iterator::begin(GEP->getOperand(0)->getType(),
@@ -97,6 +107,30 @@ namespace llvm {
     return gep_type_iterator::end(GEP.op_end());
   }
 
+  inline ev_type_iterator ev_type_begin(const ExtractValueInst *EV) {
+    return ev_type_iterator::begin(EV->getOperand(0)->getType(),
+                                   EV->idx_begin());
+  }
+  inline ev_type_iterator ev_type_end(const ExtractValueInst *EV) {
+    return ev_type_iterator::end(EV->idx_end());
+  }
+
+  inline iv_type_iterator iv_type_begin(const InsertValueInst *IV) {
+    return iv_type_iterator::begin(IV->getType(),
+                                   IV->idx_begin());
+  }
+  inline iv_type_iterator iv_type_end(const InsertValueInst *IV) {
+    return iv_type_iterator::end(IV->idx_end());
+  }
+
+  inline vce_type_iterator vce_type_begin(const ConstantExpr *CE) {
+    return vce_type_iterator::begin(CE->getOperand(0)->getType(),
+                                    CE->getIndices().begin());
+  }
+  inline vce_type_iterator vce_type_end(const ConstantExpr *CE) {
+    return vce_type_iterator::end(CE->getIndices().end());
+  }
+
   template<typename ItTy>
   inline generic_gep_type_iterator<ItTy>
   gep_type_begin(const Type *Op0, ItTy I, ItTy E) {
-- 
1.6.5



From daniel at zuster.org  Wed Jun 30 15:05:09 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 30 Jun 2010 20:05:09 -0000
Subject: [llvm-commits] [test-suite] r107314 -
 /test-suite/trunk/External/SPEC/CINT2006/483.xalancbmk/Makefile
Message-ID: <20100630200509.939F42A6C12C@llvm.org>

Author: ddunbar
Date: Wed Jun 30 15:05:09 2010
New Revision: 107314

URL: http://llvm.org/viewvc/llvm-project?rev=107314&view=rev
Log:
TEST=simple: Add missing dependency to make sure test inputs are updated before use.

Modified:
    test-suite/trunk/External/SPEC/CINT2006/483.xalancbmk/Makefile

Modified: test-suite/trunk/External/SPEC/CINT2006/483.xalancbmk/Makefile
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/External/SPEC/CINT2006/483.xalancbmk/Makefile?rev=107314&r1=107313&r2=107314&view=diff
==============================================================================
--- test-suite/trunk/External/SPEC/CINT2006/483.xalancbmk/Makefile (original)
+++ test-suite/trunk/External/SPEC/CINT2006/483.xalancbmk/Makefile Wed Jun 30 15:05:09 2010
@@ -37,7 +37,7 @@
 
 ifdef SMALL_PROBLEM_SIZE
 
-Output/483.xalancbmk.out-nat Output/483.xalancbmk.out-llc Output/483.xalancbmk.out-llc-beta Output/483.xalancbmk.out-opt-beta: Output/small-test.xml Output/100mb.xsd
+Output/483.xalancbmk.out-nat Output/483.xalancbmk.out-simple Output/483.xalancbmk.out-llc Output/483.xalancbmk.out-llc-beta Output/483.xalancbmk.out-opt-beta: Output/small-test.xml Output/100mb.xsd
 
 Output/small-test.xml: $(SPEC_BENCH_DIR)/data/test/input/test.xml
 	$(VERB) sed -E -e 's/([a-z]+ ){5}//g' $< > $@




From gohman at apple.com  Wed Jun 30 15:21:12 2010
From: gohman at apple.com (Dan Gohman)
Date: Wed, 30 Jun 2010 20:21:12 -0000
Subject: [llvm-commits] [llvm] r107316 -
	/llvm/trunk/lib/Analysis/ScalarEvolution.cpp
Message-ID: <20100630202112.DBE262A6C12C@llvm.org>

Author: djg
Date: Wed Jun 30 15:21:12 2010
New Revision: 107316

URL: http://llvm.org/viewvc/llvm-project?rev=107316&view=rev
Log:
In ScalarEvolution::forgetValue, eliminate any SCEVUnknown
entries associated with the value being erased in the
folding set map.  These entries used to be harmless, because
a SCEVUnknown doesn't store any information about its Value*,
so having a new Value allocated at the old Value's address
wasn't a problem. But now that ScalarEvolution is storing more
information about values, this is no longer safe.

Modified:
    llvm/trunk/lib/Analysis/ScalarEvolution.cpp

Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=107316&r1=107315&r2=107316&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Wed Jun 30 15:21:12 2010
@@ -3657,6 +3657,26 @@
         ConstantEvolutionLoopExitValue.erase(PN);
     }
 
+    // If there's a SCEVUnknown tying this value into the SCEV
+    // space, remove it from the folding set map. The SCEVUnknown
+    // object and any other SCEV objects which reference it
+    // (transitively) remain allocated, effectively leaked until
+    // the underlying BumpPtrAllocator is freed.
+    //
+    // This permits SCEV pointers to be used as keys in maps
+    // such as the ValuesAtScopes map.
+    FoldingSetNodeID ID;
+    ID.AddInteger(scUnknown);
+    ID.AddPointer(I);
+    void *IP;
+    if (SCEV *S = UniqueSCEVs.FindNodeOrInsertPos(ID, IP)) {
+      UniqueSCEVs.RemoveNode(S);
+
+      // This isn't necessary, but we might as well remove the
+      // value from the ValuesAtScopes map too.
+      ValuesAtScopes.erase(S);
+    }
+
     PushDefUseChildren(I, Worklist);
   }
 }




From gabor at mac.com  Wed Jun 30 15:59:07 2010
From: gabor at mac.com (Gabor Greif)
Date: Wed, 30 Jun 2010 22:59:07 +0200
Subject: [llvm-commits] [HEADSUP] Another attempt at CallInst operand
	rotation
Message-ID: <9DECA141-D2FD-4C16-9443-875CE46915A2@mac.com>

Hi all,

I am almost ready for the last step with landing my long-standing patch.
I have converted (almost) all low-level interface users of CallInst to
respective high-level interfaces. What remains is a handful of hunks
to flip the switch.

But before I do the final commit I'd like to coerce all external users
to code against the high-level interface too. This will (almost, but
see below) give us static guarantees that out-of-tree code remains
functional across this transition.

Here is my attack plan:

I will fire two rounds,
- the first will catch all instances of CallInst::get/setOperand(0, ...)
   and suggest using get/setCalledValue (or getCalledFuntion).
- the second will make all low-level operand accessors private
   in CallInst, and thus give external clients the chance to use
   *ArgOperand* versions. This will be well-commented in the
   header, explaining the recommended way of accessing
   arguments.

At this point we will have caught 99% of all low-level clients out  
there.

What uncertainties will remain? I can think of two of them:

   o getOperandNo()
   o access via baseclass pointer

The former is a method on Value::use_iterator and I cannot see a way to
intercept it at compile-time.
The latter is always possible and does circumvent the above measures,
there is no remedy against it.

I plan to fire each of these two rounds with one week delay and monitor
the LLVM mailing lists while they are soaking.

After that I'll commit the actual operand rotation.

Last but not least, there will be some cleanup commits:

  - removing CallInst::ArgOffset,
  - fixing the 80-column violations I have introduced,
  - doxygenizing the new interfaces,
  - re-enabling the low-level interface again (possibly
    after 2.8 has brached?).

Well, that's it. I hope that this order of commits will keep
the pain at a bearable level for everyone.

I would be thankful for any comments/suggestions
regarding this plan.

Cheers,

	Gabor





From grosbach at apple.com  Wed Jun 30 16:27:56 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 30 Jun 2010 21:27:56 -0000
Subject: [llvm-commits] [llvm] r107321 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
Message-ID: <20100630212756.9759E2A6C124@llvm.org>

Author: grosbach
Date: Wed Jun 30 16:27:56 2010
New Revision: 107321

URL: http://llvm.org/viewvc/llvm-project?rev=107321&view=rev
Log:
grammar tweak in comment.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp?rev=107321&r1=107320&r2=107321&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp Wed Jun 30 16:27:56 2010
@@ -507,7 +507,7 @@
 }
 
 // ProcessSourceNode - Process nodes with source order numbers. These are added
-// to a vector which EmitSchedule use to determine how to insert dbg_value
+// to a vector which EmitSchedule uses to determine how to insert dbg_value
 // instructions in the right order.
 static void ProcessSourceNode(SDNode *N, SelectionDAG *DAG,
                            InstrEmitter &Emitter,




From dpatel at apple.com  Wed Jun 30 16:29:00 2010
From: dpatel at apple.com (Devang Patel)
Date: Wed, 30 Jun 2010 21:29:00 -0000
Subject: [llvm-commits] [llvm] r107323 - in /llvm/trunk:
 lib/Transforms/IPO/StripSymbols.cpp
 test/Transforms/StripSymbols/2010-06-30-StripDebug.ll
Message-ID: <20100630212900.5D0DB2A6C12C@llvm.org>

Author: dpatel
Date: Wed Jun 30 16:29:00 2010
New Revision: 107323

URL: http://llvm.org/viewvc/llvm-project?rev=107323&view=rev
Log:
Remove all debug info related named mdnodes.

Added:
    llvm/trunk/test/Transforms/StripSymbols/2010-06-30-StripDebug.ll
Modified:
    llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp

Modified: llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp?rev=107323&r1=107322&r2=107323&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp (original)
+++ llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp Wed Jun 30 16:29:00 2010
@@ -223,16 +223,12 @@
     Changed = true;
   }
 
-  NamedMDNode *NMD = M.getNamedMetadata("llvm.dbg.gv");
-  if (NMD) {
-    Changed = true;
-    NMD->eraseFromParent();
-  }
-
-  NMD = M.getNamedMetadata("llvm.dbg.lv");
-  if (NMD) {
-    Changed = true;
-    NMD->eraseFromParent();
+  for (Module::named_metadata_iterator NMI = M.named_metadata_begin(),
+         NME = M.named_metadata_end(); NMI != NME;) {
+    NamedMDNode *NMD = NMI;
+    ++NMI;
+    if (NMD->getName().startswith("llvm.dbg."))
+      NMD->eraseFromParent();
   }
 
   unsigned MDDbgKind = M.getMDKindID("dbg");

Added: llvm/trunk/test/Transforms/StripSymbols/2010-06-30-StripDebug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/StripSymbols/2010-06-30-StripDebug.ll?rev=107323&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/StripSymbols/2010-06-30-StripDebug.ll (added)
+++ llvm/trunk/test/Transforms/StripSymbols/2010-06-30-StripDebug.ll Wed Jun 30 16:29:00 2010
@@ -0,0 +1,28 @@
+; RUN: opt -strip-debug < %s | llvm-dis | grep -v llvm.dbg
+
+ at x = common global i32 0                          ; <i32*> [#uses=0]
+
+define void @foo() nounwind readnone optsize ssp {
+entry:
+  tail call void @llvm.dbg.value(metadata !9, i64 0, metadata !5), !dbg !10
+  ret void, !dbg !11
+}
+
+declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
+
+!llvm.dbg.sp = !{!0}
+!llvm.dbg.lv.foo = !{!5}
+!llvm.dbg.gv = !{!8}
+
+!0 = metadata !{i32 524334, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"foo", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, void ()* @foo} ; [ DW_TAG_subprogram ]
+!1 = metadata !{i32 524329, metadata !"b.c", metadata !"/tmp", metadata !2} ; [ DW_TAG_file_type ]
+!2 = metadata !{i32 524305, i32 0, i32 1, metadata !"b.c", metadata !"/tmp", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
+!3 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!4 = metadata !{null}
+!5 = metadata !{i32 524544, metadata !6, metadata !"y", metadata !1, i32 3, metadata !7} ; [ DW_TAG_auto_variable ]
+!6 = metadata !{i32 524299, metadata !0, i32 2, i32 0} ; [ DW_TAG_lexical_block ]
+!7 = metadata !{i32 524324, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!8 = metadata !{i32 524340, i32 0, metadata !1, metadata !"x", metadata !"x", metadata !"", metadata !1, i32 1, metadata !7, i1 false, i1 true, i32* @x} ; [ DW_TAG_variable ]
+!9 = metadata !{i32 0}
+!10 = metadata !{i32 3, i32 0, metadata !6, null}
+!11 = metadata !{i32 4, i32 0, metadata !6, null}




From wdietz2 at illinois.edu  Wed Jun 30 17:10:52 2010
From: wdietz2 at illinois.edu (Will Dietz)
Date: Wed, 30 Jun 2010 22:10:52 -0000
Subject: [llvm-commits] [poolalloc] r107329 - in /poolalloc/trunk/test:
 TEST.dsaa.Makefile TEST.dsaa.report
Message-ID: <20100630221052.DDF782A6C12C@llvm.org>

Author: wdietz2
Date: Wed Jun 30 17:10:52 2010
New Revision: 107329

URL: http://llvm.org/viewvc/llvm-project?rev=107329&view=rev
Log:
touch up dsaa tests, remove -debug-pass argument

Modified:
    poolalloc/trunk/test/TEST.dsaa.Makefile
    poolalloc/trunk/test/TEST.dsaa.report

Modified: poolalloc/trunk/test/TEST.dsaa.Makefile
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/TEST.dsaa.Makefile?rev=107329&r1=107328&r2=107329&view=diff
==============================================================================
--- poolalloc/trunk/test/TEST.dsaa.Makefile (original)
+++ poolalloc/trunk/test/TEST.dsaa.Makefile Wed Jun 30 17:10:52 2010
@@ -63,7 +63,7 @@
 $(PROGRAMS_TO_TEST:%=Output/%.dsaopt.bc): \
 Output/%.dsaopt.bc: Output/%.base.bc $(LOPT)
 	- at rm -f $(CURDIR)/$@.info
-	-$(OPT_PA_STATS) $(AA_OPT) -debug-pass=Executions $< -o $@ -f 2>&1 > $@.out
+	-$(OPT_PA_STATS) $(AA_OPT) $< -o $@ -f 2>&1 > $@.out
 
 # This rule compiles the new .bc file into a .s file
 Output/%.s: Output/%.bc $(LLC)
@@ -146,7 +146,7 @@
 	fi
 	-printf "LOC: " >> $@
 	-cat Output/$*.LOC.txt >> $@
-	@-cat Output/$*.$(TEST).bc.info >> $@
+	@#-cat Output/$*.$(TEST).bc.info >> $@
 	@#cat Output/$*.$(TEST).basepa.bc.out  >> $@
 
 

Modified: poolalloc/trunk/test/TEST.dsaa.report
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/TEST.dsaa.report?rev=107329&r1=107328&r2=107329&view=diff
==============================================================================
--- poolalloc/trunk/test/TEST.dsaa.report (original)
+++ poolalloc/trunk/test/TEST.dsaa.report Wed Jun 30 17:10:52 2010
@@ -83,7 +83,7 @@
  ["LLVMOptTime",      'RUN-TIME-LLVMOPT: program\s*([.0-9m:]+)', \&FormatTime],
  ["LLVMOpt run%",        \&RuntimePercent],
  [],
- ["DSA Time",        'RUN-TIME-DSAA: program\s*([.0-9m:]+)', \&FormatTime],
+ ["DSA Time",        'RUN-TIME-DSAAOPT: program\s*([.0-9m:]+)', \&FormatTime],
  ["DSA run%",        \&RuntimePercent],
 # [],
 # ["NoAlias",        'no alias responses[^0-9]*([0-9]*\.[0-9]*)'],




From daniel at zuster.org  Wed Jun 30 17:20:13 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 30 Jun 2010 22:20:13 -0000
Subject: [llvm-commits] [test-suite] r107331 -
 /test-suite/trunk/SingleSource/UnitTests/ObjC/dot-syntax-2.reference_output
Message-ID: <20100630222013.4A9DF2A6C12C@llvm.org>

Author: ddunbar
Date: Wed Jun 30 17:20:13 2010
New Revision: 107331

URL: http://llvm.org/viewvc/llvm-project?rev=107331&view=rev
Log:
Adjust reference output for a case where Clang correctly differs from GCC.

Modified:
    test-suite/trunk/SingleSource/UnitTests/ObjC/dot-syntax-2.reference_output

Modified: test-suite/trunk/SingleSource/UnitTests/ObjC/dot-syntax-2.reference_output
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/ObjC/dot-syntax-2.reference_output?rev=107331&r1=107330&r2=107331&view=diff
==============================================================================
--- test-suite/trunk/SingleSource/UnitTests/ObjC/dot-syntax-2.reference_output (original)
+++ test-suite/trunk/SingleSource/UnitTests/ObjC/dot-syntax-2.reference_output Wed Jun 30 17:20:13 2010
@@ -1,3 +1,3 @@
 res: 3
-res: 65535
+res: -1
 exit 0




From grosbach at apple.com  Wed Jun 30 17:20:38 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 30 Jun 2010 22:20:38 -0000
Subject: [llvm-commits] [llvm] r107332 -
	/llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp
Message-ID: <20100630222038.C3A752A6C12C@llvm.org>

Author: grosbach
Date: Wed Jun 30 17:20:38 2010
New Revision: 107332

URL: http://llvm.org/viewvc/llvm-project?rev=107332&view=rev
Log:
Handle array and vector typed parameters in sjljehprepare like we do
structs. rdar://8145832

Modified:
    llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp

Modified: llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp?rev=107332&r1=107331&r2=107332&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp (original)
+++ llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Wed Jun 30 17:20:38 2010
@@ -205,15 +205,15 @@
   for (Function::arg_iterator AI = F->arg_begin(), E = F->arg_end();
        AI != E; ++AI) {
     const Type *Ty = AI->getType();
-    // StructType can't be cast, but is a legal argument type, so we have
+    // Aggregate types can't be cast, but are legal argument types, so we have
     // to handle them differently. We use an extract/insert pair as a
     // lightweight method to achieve the same goal.
-    if (isa<StructType>(Ty)) {
-      Instruction *EI = ExtractValueInst::Create(AI, 0, "", AfterAllocaInsertPt);
+    if (isa<StructType>(Ty) || isa<ArrayType>(Ty) || isa<VectorType>(Ty)) {
+      Instruction *EI = ExtractValueInst::Create(AI, 0, "",AfterAllocaInsertPt);
       Instruction *NI = InsertValueInst::Create(AI, EI, 0);
       NI->insertAfter(EI);
       AI->replaceAllUsesWith(NI);
-      // Set the struct operand of the instructions back to the AllocaInst.
+      // Set the operand of the instructions back to the AllocaInst.
       EI->setOperand(0, AI);
       NI->setOperand(0, AI);
     } else {




From daniel at zuster.org  Wed Jun 30 17:22:46 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 30 Jun 2010 22:22:46 -0000
Subject: [llvm-commits] [llvm] r107334 - /llvm/trunk/Makefile
Message-ID: <20100630222246.430852A6C12C@llvm.org>

Author: ddunbar
Date: Wed Jun 30 17:22:46 2010
New Revision: 107334

URL: http://llvm.org/viewvc/llvm-project?rev=107334&view=rev
Log:
build: Update install-clang target.

Modified:
    llvm/trunk/Makefile

Modified: llvm/trunk/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile?rev=107334&r1=107333&r2=107334&view=diff
==============================================================================
--- llvm/trunk/Makefile (original)
+++ llvm/trunk/Makefile Wed Jun 30 17:22:46 2010
@@ -64,7 +64,7 @@
 
 ifeq ($(MAKECMDGOALS),install-clang)
   DIRS := tools/clang/tools/driver tools/clang/lib/Headers \
-          tools/clang/lib/Runtime tools/clang/docs
+          tools/clang/runtime tools/clang/docs
   OPTIONAL_DIRS :=
   NO_INSTALL = 1
 endif




From grosbach at apple.com  Wed Jun 30 17:22:59 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 30 Jun 2010 22:22:59 -0000
Subject: [llvm-commits] [llvm] r107335 -
	/llvm/trunk/lib/Transforms/Utils/LowerInvoke.cpp
Message-ID: <20100630222259.9C3A02A6C12C@llvm.org>

Author: grosbach
Date: Wed Jun 30 17:22:59 2010
New Revision: 107335

URL: http://llvm.org/viewvc/llvm-project?rev=107335&view=rev
Log:
lowerinvoke needs to handle aggregate function args like sjlj eh does.

Modified:
    llvm/trunk/lib/Transforms/Utils/LowerInvoke.cpp

Modified: llvm/trunk/lib/Transforms/Utils/LowerInvoke.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/LowerInvoke.cpp?rev=107335&r1=107334&r2=107335&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/LowerInvoke.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/LowerInvoke.cpp Wed Jun 30 17:22:59 2010
@@ -310,15 +310,15 @@
   for (Function::arg_iterator AI = F->arg_begin(), E = F->arg_end();
        AI != E; ++AI) {
     const Type *Ty = AI->getType();
-    // StructType can't be cast, but is a legal argument type, so we have
+    // Aggregate types can't be cast, but are legal argument types, so we have
     // to handle them differently. We use an extract/insert pair as a
     // lightweight method to achieve the same goal.
-    if (isa<StructType>(Ty)) {
-      Instruction *EI = ExtractValueInst::Create(AI, 0, "", AfterAllocaInsertPt);
+    if (isa<StructType>(Ty) || isa<ArrayType>(Ty) || isa<VectorType>(Ty)) {
+      Instruction *EI = ExtractValueInst::Create(AI, 0, "",AfterAllocaInsertPt);
       Instruction *NI = InsertValueInst::Create(AI, EI, 0);
       NI->insertAfter(EI);
       AI->replaceAllUsesWith(NI);
-      // Set the struct operand of the instructions back to the AllocaInst.
+      // Set the operand of the instructions back to the AllocaInst.
       EI->setOperand(0, AI);
       NI->setOperand(0, AI);
     } else {




From wdietz2 at illinois.edu  Wed Jun 30 17:26:10 2010
From: wdietz2 at illinois.edu (Will Dietz)
Date: Wed, 30 Jun 2010 22:26:10 -0000
Subject: [llvm-commits] [poolalloc] r107336 -
	/poolalloc/trunk/lib/DSA/DataStructureAA.cpp
Message-ID: <20100630222610.5FFE42A6C12C@llvm.org>

Author: wdietz2
Date: Wed Jun 30 17:26:10 2010
New Revision: 107336

URL: http://llvm.org/viewvc/llvm-project?rev=107336&view=rev
Log:
unconditionally chain copyValue/deleteValue to let other AA's update their data

Modified:
    poolalloc/trunk/lib/DSA/DataStructureAA.cpp

Modified: poolalloc/trunk/lib/DSA/DataStructureAA.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DataStructureAA.cpp?rev=107336&r1=107335&r2=107336&view=diff
==============================================================================
--- poolalloc/trunk/lib/DSA/DataStructureAA.cpp (original)
+++ poolalloc/trunk/lib/DSA/DataStructureAA.cpp Wed Jun 30 17:26:10 2010
@@ -108,6 +108,7 @@
       InvalidateCache();
       BU->deleteValue(V);
       TD->deleteValue(V);
+      AliasAnalysis::deleteValue(V);
     }
 
     virtual void copyValue(Value *From, Value *To) {
@@ -116,6 +117,7 @@
       InvalidateCache();
       BU->copyValue(From, To);
       TD->copyValue(From, To);
+      AliasAnalysis::copyValue(From, To);
     }
 
   private:




From wdietz2 at illinois.edu  Wed Jun 30 17:27:23 2010
From: wdietz2 at illinois.edu (Will Dietz)
Date: Wed, 30 Jun 2010 22:27:23 -0000
Subject: [llvm-commits] [poolalloc] r107337 -
	/poolalloc/trunk/lib/DSA/DataStructure.cpp
Message-ID: <20100630222723.3CC722A6C12C@llvm.org>

Author: wdietz2
Date: Wed Jun 30 17:27:23 2010
New Revision: 107337

URL: http://llvm.org/viewvc/llvm-project?rev=107337&view=rev
Log:
also update VANode mapping when copying a value

Modified:
    poolalloc/trunk/lib/DSA/DataStructure.cpp

Modified: poolalloc/trunk/lib/DSA/DataStructure.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DataStructure.cpp?rev=107337&r1=107336&r2=107337&view=diff
==============================================================================
--- poolalloc/trunk/lib/DSA/DataStructure.cpp (original)
+++ poolalloc/trunk/lib/DSA/DataStructure.cpp Wed Jun 30 17:27:23 2010
@@ -1119,6 +1119,10 @@
     DSNodeHandle Ret = NG->retnodes_begin()->second;
     NG->getReturnNodes().clear();
     NG->getReturnNodes()[ToF] = Ret;
+    // Change the Function* in the vanodes map to the ToF
+    DSNodeHandle VA = NG->vanodes_begin()->second;
+    NG->getVANodes().clear();
+    NG->getOrCreateVANodeFor(ToF) = Ret;
     return;
   }
   




From wendling at apple.com  Wed Jun 30 17:41:03 2010
From: wendling at apple.com (Bill Wendling)
Date: Wed, 30 Jun 2010 15:41:03 -0700
Subject: [llvm-commits] [PATCH] Add some more ELF OSABI values.
In-Reply-To: <8806a9216ebe6844ecf8f510b1187ebc4d6e8345.1277924817.git.matt@console-pimps.org>
References: <8806a9216ebe6844ecf8f510b1187ebc4d6e8345.1277924817.git.matt@console-pimps.org>
Message-ID: <77331FDA-6D14-4962-A88F-84E80040563B@apple.com>

Seems okay. Though why not change ELFOSABI_NONE to something that reflects what the comment says. Maybe ELFOSABI_SYSV or something?

-bw

On Jun 30, 2010, at 12:13 PM, Matt Fleming wrote:

> Hi,
> 
> does anyone have any issue with me committing the following patch? I've
> been carrying it in my git repository containing the ELF MC support, but
> there should be no problem with it going into trunk.
> 
> Any objections?
> 
> ---
> include/llvm/Support/ELF.h |   23 +++++++++++++++++++++--
> 1 files changed, 21 insertions(+), 2 deletions(-)
> 
> diff --git a/include/llvm/Support/ELF.h b/include/llvm/Support/ELF.h
> index 51403ff..6e863f8 100644
> --- a/include/llvm/Support/ELF.h
> +++ b/include/llvm/Support/ELF.h
> @@ -150,9 +150,28 @@ enum {
>   ELFDATA2MSB = 2  // Big-endian object file
> };
> 
> -// OS ABI identification -- unused.
> +// OS ABI identification.
> enum {
> -  ELFOSABI_NONE = 0
> +  ELFOSABI_NONE = 0,          // UNIX System V ABI
> +  ELFOSABI_HPUX = 1,          // HP-UX operating system
> +  ELFOSABI_NETBSD = 2,        // NetBSD
> +  ELFOSABI_LINUX = 3,         // GNU/Linux
> +  ELFOSABI_HURD = 4,          // GNU/Hurd
> +  ELFOSABI_SOLARIS = 6,       // Solaris
> +  ELFOSABI_AIX = 7,           // AIX
> +  ELFOSABI_IRIX = 8,          // IRIX
> +  ELFOSABI_FREEBSD = 9,       // FreeBSD
> +  ELFOSABI_TRU64 = 10,        // TRU64 UNIX
> +  ELFOSABI_MODESTO = 11,      // Novell Modesto
> +  ELFOSABI_OPENBSD = 12,      // OpenBSD
> +  ELFOSABI_OPENVMS = 13,      // OpenVMS
> +  ELFOSABI_NSK = 14,          // Hewlett-Packard Non-Stop Kernel
> +  ELFOSABI_AROS = 15,         // AROS
> +  ELFOSABI_FENIXOS = 16,      // FenixOS
> +  ELFOSABI_C6000_ELFABI = 64, // Bare-metal TMS320C6000
> +  ELFOSABI_C6000_LINUX = 65,  // Linux TMS320C6000
> +  ELFOSABI_ARM = 97,          // ARM
> +  ELFOSABI_STANDALONE = 255   // Standalone (embedded) application
> };
> 
> // Section header.
> -- 
> 1.6.4.rc0
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits




From isanbard at gmail.com  Wed Jun 30 17:49:53 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 30 Jun 2010 22:49:53 -0000
Subject: [llvm-commits] [llvm] r107345 -
	/llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp
Message-ID: <20100630224953.E1EBE2A6C12C@llvm.org>

Author: void
Date: Wed Jun 30 17:49:53 2010
New Revision: 107345

URL: http://llvm.org/viewvc/llvm-project?rev=107345&view=rev
Log:
Use the catch-all selectors we already found when converting them to use the
correct catch-all value. This saves having to iterate through all of the
selectors in the program again.

Modified:
    llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp

Modified: llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp?rev=107345&r1=107344&r2=107345&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp (original)
+++ llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp Wed Jun 30 17:49:53 2010
@@ -88,12 +88,13 @@
     /// CleanupSelectors - Any remaining eh.selector intrinsic calls which still
     /// use the ".llvm.eh.catch.all.value" call need to convert to using its
     /// initializer instead.
-    bool CleanupSelectors();
+    bool CleanupSelectors(SmallPtrSet<IntrinsicInst*, 32> &Sels);
 
     bool HasCatchAllInSelector(IntrinsicInst *);
 
     /// FindAllCleanupSelectors - Find all eh.selector calls that are clean-ups.
-    void FindAllCleanupSelectors(SmallPtrSet<IntrinsicInst*, 32> &Sels);
+    void FindAllCleanupSelectors(SmallPtrSet<IntrinsicInst*, 32> &Sels,
+                                 SmallPtrSet<IntrinsicInst*, 32> &CatchAllSels);
 
     /// FindAllURoRInvokes - Find all URoR invokes in the function.
     void FindAllURoRInvokes(SmallPtrSet<InvokeInst*, 32> &URoRInvokes);
@@ -201,7 +202,8 @@
 
 /// FindAllCleanupSelectors - Find all eh.selector calls that are clean-ups.
 void DwarfEHPrepare::
-FindAllCleanupSelectors(SmallPtrSet<IntrinsicInst*, 32> &Sels) {
+FindAllCleanupSelectors(SmallPtrSet<IntrinsicInst*, 32> &Sels,
+                        SmallPtrSet<IntrinsicInst*, 32> &CatchAllSels) {
   for (Value::use_iterator
          I = SelectorIntrinsic->use_begin(),
          E = SelectorIntrinsic->use_end(); I != E; ++I) {
@@ -212,6 +214,8 @@
 
     if (!HasCatchAllInSelector(II))
       Sels.insert(II);
+    else
+      CatchAllSels.insert(II);
   }
 }
 
@@ -229,7 +233,7 @@
 /// CleanupSelectors - Any remaining eh.selector intrinsic calls which still use
 /// the ".llvm.eh.catch.all.value" call need to convert to using its
 /// initializer instead.
-bool DwarfEHPrepare::CleanupSelectors() {
+bool DwarfEHPrepare::CleanupSelectors(SmallPtrSet<IntrinsicInst*, 32> &Sels) {
   if (!EHCatchAllValue) return false;
 
   if (!SelectorIntrinsic) {
@@ -239,11 +243,9 @@
   }
 
   bool Changed = false;
-  for (Value::use_iterator
-         I = SelectorIntrinsic->use_begin(),
-         E = SelectorIntrinsic->use_end(); I != E; ++I) {
-    IntrinsicInst *Sel = dyn_cast<IntrinsicInst>(I);
-    if (!Sel || Sel->getParent()->getParent() != F) continue;
+  for (SmallPtrSet<IntrinsicInst*, 32>::iterator
+         I = Sels.begin(), E = Sels.end(); I != E; ++I) {
+    IntrinsicInst *Sel = *I;
 
     // Index of the ".llvm.eh.catch.all.value" variable.
     unsigned OpIdx = Sel->getNumArgOperands() - 1;
@@ -300,8 +302,6 @@
 /// function. This is a candidate to merge the selector associated with the URoR
 /// invoke with the one from the URoR's landing pad.
 bool DwarfEHPrepare::HandleURoRInvokes() {
-  if (!DT) return CleanupSelectors(); // We require DominatorTree information.
-
   if (!EHCatchAllValue) {
     EHCatchAllValue =
       F->getParent()->getNamedGlobal(".llvm.eh.catch.all.value");
@@ -314,14 +314,20 @@
     if (!SelectorIntrinsic) return false;
   }
 
+  SmallPtrSet<IntrinsicInst*, 32> Sels;
+  SmallPtrSet<IntrinsicInst*, 32> CatchAllSels;
+  FindAllCleanupSelectors(Sels, CatchAllSels);
+
+  if (!DT)
+    // We require DominatorTree information.
+    return CleanupSelectors(CatchAllSels);
+
   if (!URoR) {
     URoR = F->getParent()->getFunction("_Unwind_Resume_or_Rethrow");
-    if (!URoR) return CleanupSelectors();
+    if (!URoR) return CleanupSelectors(CatchAllSels);
   }
 
-  SmallPtrSet<IntrinsicInst*, 32> Sels;
   SmallPtrSet<InvokeInst*, 32> URoRInvokes;
-  FindAllCleanupSelectors(Sels);
   FindAllURoRInvokes(URoRInvokes);
 
   SmallPtrSet<IntrinsicInst*, 32> SelsToConvert;
@@ -347,7 +353,8 @@
     if (!ExceptionValueIntrinsic) {
       ExceptionValueIntrinsic =
         Intrinsic::getDeclaration(F->getParent(), Intrinsic::eh_exception);
-      if (!ExceptionValueIntrinsic) return CleanupSelectors();
+      if (!ExceptionValueIntrinsic)
+        return CleanupSelectors(CatchAllSels);
     }
 
     for (Value::use_iterator
@@ -414,7 +421,7 @@
     }
   }
 
-  Changed |= CleanupSelectors();
+  Changed |= CleanupSelectors(CatchAllSels);
   return Changed;
 }
 




From wdietz2 at illinois.edu  Wed Jun 30 17:51:49 2010
From: wdietz2 at illinois.edu (Will Dietz)
Date: Wed, 30 Jun 2010 22:51:49 -0000
Subject: [llvm-commits] [poolalloc] r107346 -
	/poolalloc/trunk/lib/DSA/DataStructure.cpp
Message-ID: <20100630225149.1004C2A6C12C@llvm.org>

Author: wdietz2
Date: Wed Jun 30 17:51:48 2010
New Revision: 107346

URL: http://llvm.org/viewvc/llvm-project?rev=107346&view=rev
Log:
Ret->VA

Modified:
    poolalloc/trunk/lib/DSA/DataStructure.cpp

Modified: poolalloc/trunk/lib/DSA/DataStructure.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DataStructure.cpp?rev=107346&r1=107345&r2=107346&view=diff
==============================================================================
--- poolalloc/trunk/lib/DSA/DataStructure.cpp (original)
+++ poolalloc/trunk/lib/DSA/DataStructure.cpp Wed Jun 30 17:51:48 2010
@@ -1122,7 +1122,7 @@
     // Change the Function* in the vanodes map to the ToF
     DSNodeHandle VA = NG->vanodes_begin()->second;
     NG->getVANodes().clear();
-    NG->getOrCreateVANodeFor(ToF) = Ret;
+    NG->getOrCreateVANodeFor(ToF) = VA;
     return;
   }
   




From wdietz2 at illinois.edu  Wed Jun 30 17:59:39 2010
From: wdietz2 at illinois.edu (Will Dietz)
Date: Wed, 30 Jun 2010 22:59:39 -0000
Subject: [llvm-commits] [poolalloc] r107348 - in /poolalloc/trunk:
 include/dsa/DSGraph.h lib/DSA/DataStructure.cpp
Message-ID: <20100630225939.93F242A6C12C@llvm.org>

Author: wdietz2
Date: Wed Jun 30 17:59:39 2010
New Revision: 107348

URL: http://llvm.org/viewvc/llvm-project?rev=107348&view=rev
Log:
expose VANode mapping to clients, make use of it in copyValue()

Modified:
    poolalloc/trunk/include/dsa/DSGraph.h
    poolalloc/trunk/lib/DSA/DataStructure.cpp

Modified: poolalloc/trunk/include/dsa/DSGraph.h
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/dsa/DSGraph.h?rev=107348&r1=107347&r2=107348&view=diff
==============================================================================
--- poolalloc/trunk/include/dsa/DSGraph.h (original)
+++ poolalloc/trunk/include/dsa/DSGraph.h Wed Jun 30 17:59:39 2010
@@ -409,6 +409,12 @@
     return I->second;
   }
 
+  /// getVANodes - Return the mapping of functions to their var-arg nodes for
+  /// this graph.
+  ///
+  const VANodesTy &getVANodes() const { return VANodes; }
+        VANodesTy &getVANodes()       { return VANodes; }
+
   /// getVANodeFor - Return the var-arg node for the specified function.
   ///
   DSNodeHandle &getVANodeFor(const Function &F) {

Modified: poolalloc/trunk/lib/DSA/DataStructure.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DataStructure.cpp?rev=107348&r1=107347&r2=107348&view=diff
==============================================================================
--- poolalloc/trunk/lib/DSA/DataStructure.cpp (original)
+++ poolalloc/trunk/lib/DSA/DataStructure.cpp Wed Jun 30 17:59:39 2010
@@ -1122,7 +1122,7 @@
     // Change the Function* in the vanodes map to the ToF
     DSNodeHandle VA = NG->vanodes_begin()->second;
     NG->getVANodes().clear();
-    NG->getOrCreateVANodeFor(ToF) = VA;
+    NG->getVANodes()[ToF] = VA;
     return;
   }
   




From stoklund at 2pi.dk  Wed Jun 30 18:03:52 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Wed, 30 Jun 2010 23:03:52 -0000
Subject: [llvm-commits] [llvm] r107351 - in /llvm/trunk/lib/CodeGen:
	InlineSpiller.cpp Spiller.h
Message-ID: <20100630230352.5A2892A6C12C@llvm.org>

Author: stoklund
Date: Wed Jun 30 18:03:52 2010
New Revision: 107351

URL: http://llvm.org/viewvc/llvm-project?rev=107351&view=rev
Log:
Add support for rematerialization to InlineSpiller.

Modified:
    llvm/trunk/lib/CodeGen/InlineSpiller.cpp
    llvm/trunk/lib/CodeGen/Spiller.h

Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/InlineSpiller.cpp?rev=107351&r1=107350&r2=107351&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/InlineSpiller.cpp (original)
+++ llvm/trunk/lib/CodeGen/InlineSpiller.cpp Wed Jun 30 18:03:52 2010
@@ -35,6 +35,13 @@
   MachineRegisterInfo &mri_;
   const TargetInstrInfo &tii_;
   const TargetRegisterInfo &tri_;
+  const BitVector reserved_;
+
+  // Variables that are valid during spill(), but used by multiple methods.
+  LiveInterval *li_;
+  const TargetRegisterClass *rc_;
+  int stackSlot_;
+  const SmallVectorImpl<LiveInterval*> *spillIs_;
 
   ~InlineSpiller() {}
 
@@ -44,12 +51,16 @@
       mfi_(*mf->getFrameInfo()),
       mri_(mf->getRegInfo()),
       tii_(*mf->getTarget().getInstrInfo()),
-      tri_(*mf->getTarget().getRegisterInfo()) {}
+      tri_(*mf->getTarget().getRegisterInfo()),
+      reserved_(tri_.getReservedRegs(mf_)) {}
 
   void spill(LiveInterval *li,
              std::vector<LiveInterval*> &newIntervals,
              SmallVectorImpl<LiveInterval*> &spillIs,
              SlotIndex *earliestIndex);
+  bool reMaterialize(LiveInterval &NewLI, MachineBasicBlock::iterator MI);
+  void insertReload(LiveInterval &NewLI, MachineBasicBlock::iterator MI);
+  void insertSpill(LiveInterval &NewLI, MachineBasicBlock::iterator MI);
 };
 }
 
@@ -62,6 +73,109 @@
 }
 }
 
+/// reMaterialize - Attempt to rematerialize li_->reg before MI instead of
+/// reloading it.
+bool InlineSpiller::reMaterialize(LiveInterval &NewLI,
+                                  MachineBasicBlock::iterator MI) {
+  SlotIndex UseIdx = lis_.getInstructionIndex(MI).getUseIndex();
+  LiveRange *LR = li_->getLiveRangeContaining(UseIdx);
+  if (!LR) {
+    DEBUG(dbgs() << "\tundef at " << UseIdx << ", adding <undef> flags.\n");
+    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+      MachineOperand &MO = MI->getOperand(i);
+      if (MO.isReg() && MO.isUse() && MO.getReg() == li_->reg)
+        MO.setIsUndef();
+    }
+    return true;
+  }
+
+  // Find the instruction that defined this value of li_->reg.
+  if (!LR->valno->isDefAccurate())
+    return false;
+  SlotIndex OrigDefIdx = LR->valno->def;
+  MachineInstr *OrigDefMI = lis_.getInstructionFromIndex(OrigDefIdx);
+  if (!OrigDefMI)
+    return false;
+
+  // FIXME: Provide AliasAnalysis argument.
+  if (!tii_.isTriviallyReMaterializable(OrigDefMI))
+    return false;
+
+  // A rematerializable instruction may be using other virtual registers.
+  // Make sure they are available at the new location.
+  for (unsigned i = 0, e = OrigDefMI->getNumOperands(); i != e; ++i) {
+    MachineOperand &MO = OrigDefMI->getOperand(i);
+    if (!MO.isReg() || !MO.getReg() || MO.getReg() == li_->reg)
+      continue;
+    // Reserved physregs are OK. Others are not (probably from coalescing).
+    if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
+      if (reserved_.test(MO.getReg()))
+        continue;
+      else
+        return false;
+    }
+    // We don't want to move any virtual defs.
+    if (MO.isDef())
+      return false;
+    // We have a use of a virtual register other than li_->reg.
+    if (MO.isUndef())
+      continue;
+    // We cannot depend on virtual registers in spillIs_. They will be spilled.
+    for (unsigned si = 0, se = spillIs_->size(); si != se; ++si)
+      if ((*spillIs_)[si]->reg == MO.getReg())
+        return false;
+
+    // Is the register available here with the same value as at OrigDefMI?
+    LiveInterval &ULI = lis_.getInterval(MO.getReg());
+    LiveRange *HereLR = ULI.getLiveRangeContaining(UseIdx);
+    if (!HereLR)
+      return false;
+    LiveRange *DefLR = ULI.getLiveRangeContaining(OrigDefIdx.getUseIndex());
+    if (!DefLR || DefLR->valno != HereLR->valno)
+      return false;
+  }
+
+  // Finally we can rematerialize OrigDefMI before MI.
+  MachineBasicBlock &MBB = *MI->getParent();
+  tii_.reMaterialize(MBB, MI, NewLI.reg, 0, OrigDefMI, tri_);
+  SlotIndex DefIdx = lis_.InsertMachineInstrInMaps(--MI).getDefIndex();
+  DEBUG(dbgs() << "\tremat:  " << DefIdx << '\t' << *MI);
+  VNInfo *DefVNI = NewLI.getNextValue(DefIdx, 0, true,
+                                       lis_.getVNInfoAllocator());
+  NewLI.addRange(LiveRange(DefIdx, UseIdx.getDefIndex(), DefVNI));
+  return true;
+}
+
+/// insertReload - Insert a reload of NewLI.reg before MI.
+void InlineSpiller::insertReload(LiveInterval &NewLI,
+                                 MachineBasicBlock::iterator MI) {
+  MachineBasicBlock &MBB = *MI->getParent();
+  SlotIndex Idx = lis_.getInstructionIndex(MI).getDefIndex();
+  tii_.loadRegFromStackSlot(MBB, MI, NewLI.reg, stackSlot_, rc_, &tri_);
+  --MI; // Point to load instruction.
+  SlotIndex LoadIdx = lis_.InsertMachineInstrInMaps(MI).getDefIndex();
+  vrm_.addSpillSlotUse(stackSlot_, MI);
+  DEBUG(dbgs() << "\treload:  " << LoadIdx << '\t' << *MI);
+  VNInfo *LoadVNI = NewLI.getNextValue(LoadIdx, 0, true,
+                                       lis_.getVNInfoAllocator());
+  NewLI.addRange(LiveRange(LoadIdx, Idx, LoadVNI));
+}
+
+/// insertSpill - Insert a spill of NewLI.reg after MI.
+void InlineSpiller::insertSpill(LiveInterval &NewLI,
+                                MachineBasicBlock::iterator MI) {
+  MachineBasicBlock &MBB = *MI->getParent();
+  SlotIndex Idx = lis_.getInstructionIndex(MI).getDefIndex();
+  tii_.storeRegToStackSlot(MBB, ++MI, NewLI.reg, true, stackSlot_, rc_, &tri_);
+  --MI; // Point to store instruction.
+  SlotIndex StoreIdx = lis_.InsertMachineInstrInMaps(MI).getDefIndex();
+  vrm_.addSpillSlotUse(stackSlot_, MI);
+  DEBUG(dbgs() << "\tspilled: " << StoreIdx << '\t' << *MI);
+  VNInfo *StoreVNI = NewLI.getNextValue(Idx, 0, true,
+                                        lis_.getVNInfoAllocator());
+  NewLI.addRange(LiveRange(Idx, StoreIdx, StoreVNI));
+}
+
 void InlineSpiller::spill(LiveInterval *li,
                           std::vector<LiveInterval*> &newIntervals,
                           SmallVectorImpl<LiveInterval*> &spillIs,
@@ -70,12 +184,14 @@
   assert(li->isSpillable() && "Attempting to spill already spilled value.");
   assert(!li->isStackSlot() && "Trying to spill a stack slot.");
 
-  const TargetRegisterClass *RC = mri_.getRegClass(li->reg);
-  unsigned SS = vrm_.assignVirt2StackSlot(li->reg);
+  li_ = li;
+  rc_ = mri_.getRegClass(li->reg);
+  stackSlot_ = vrm_.assignVirt2StackSlot(li->reg);
+  spillIs_ = &spillIs;
 
+  // Iterate over instructions using register.
   for (MachineRegisterInfo::reg_iterator RI = mri_.reg_begin(li->reg);
        MachineInstr *MI = RI.skipInstruction();) {
-    SlotIndex Idx = lis_.getInstructionIndex(MI).getDefIndex();
 
     // Analyze instruction.
     bool Reads, Writes;
@@ -84,23 +200,16 @@
 
     // Allocate interval around instruction.
     // FIXME: Infer regclass from instruction alone.
-    unsigned NewVReg = mri_.createVirtualRegister(RC);
+    unsigned NewVReg = mri_.createVirtualRegister(rc_);
     vrm_.grow();
     LiveInterval &NewLI = lis_.getOrCreateInterval(NewVReg);
     NewLI.markNotSpillable();
 
-    // Reload if instruction reads register.
-    if (Reads) {
-      MachineBasicBlock::iterator MII = MI;
-      tii_.loadRegFromStackSlot(*MI->getParent(), MII, NewVReg, SS, RC, &tri_);
-      --MII; // Point to load instruction.
-      SlotIndex LoadIdx = lis_.InsertMachineInstrInMaps(MII).getDefIndex();
-      vrm_.addSpillSlotUse(SS, MII);
-      DEBUG(dbgs() << "\treload:  " << LoadIdx << '\t' << *MII);
-      VNInfo *LoadVNI = NewLI.getNextValue(LoadIdx, 0, true,
-                                           lis_.getVNInfoAllocator());
-      NewLI.addRange(LiveRange(LoadIdx, Idx, LoadVNI));
-    }
+    // Attempt remat instead of reload.
+    bool NeedsReload = Reads && !reMaterialize(NewLI, MI);
+
+    if (NeedsReload)
+      insertReload(NewLI, MI);
 
     // Rewrite instruction operands.
     bool hasLiveDef = false;
@@ -115,22 +224,10 @@
           hasLiveDef = true;
       }
     }
-    DEBUG(dbgs() << "\trewrite: " << Idx << '\t' << *MI);
 
-    // Spill is instruction writes register.
     // FIXME: Use a second vreg if instruction has no tied ops.
-    if (Writes && hasLiveDef) {
-      MachineBasicBlock::iterator MII = MI;
-      tii_.storeRegToStackSlot(*MI->getParent(), ++MII, NewVReg, true, SS, RC,
-                               &tri_);
-      --MII; // Point to store instruction.
-      SlotIndex StoreIdx = lis_.InsertMachineInstrInMaps(MII).getDefIndex();
-      vrm_.addSpillSlotUse(SS, MII);
-      DEBUG(dbgs() << "\tspilled: " << StoreIdx << '\t' << *MII);
-      VNInfo *StoreVNI = NewLI.getNextValue(Idx, 0, true,
-                                            lis_.getVNInfoAllocator());
-      NewLI.addRange(LiveRange(Idx, StoreIdx, StoreVNI));
-    }
+    if (Writes && hasLiveDef)
+      insertSpill(NewLI, MI);
 
     DEBUG(dbgs() << "\tinterval: " << NewLI << '\n');
     newIntervals.push_back(&NewLI);

Modified: llvm/trunk/lib/CodeGen/Spiller.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Spiller.h?rev=107351&r1=107350&r2=107351&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/Spiller.h (original)
+++ llvm/trunk/lib/CodeGen/Spiller.h Wed Jun 30 18:03:52 2010
@@ -37,8 +37,8 @@
     /// the Spiller implementation selected.
     ///
     /// @param li            The live interval to be spilled.
-    /// @param spillIs       An essential hook into the register allocator guts
-    ///                      that perhaps serves a purpose(?!)
+    /// @param spillIs       A list of intervals that are about to be spilled,
+    ///                      and so cannot be used for remat etc.
     /// @param newIntervals  The newly created intervals will be appended here.
     /// @param earliestIndex The earliest point for splitting. (OK, it's another
     ///                      pointer to the allocator guts).




From stoklund at 2pi.dk  Wed Jun 30 19:13:04 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Thu, 01 Jul 2010 00:13:04 -0000
Subject: [llvm-commits] [llvm] r107355 -
	/llvm/trunk/lib/CodeGen/InlineSpiller.cpp
Message-ID: <20100701001304.9F42C2A6C12C@llvm.org>

Author: stoklund
Date: Wed Jun 30 19:13:04 2010
New Revision: 107355

URL: http://llvm.org/viewvc/llvm-project?rev=107355&view=rev
Log:
Add memory operand folding support to InlineSpiller.

Modified:
    llvm/trunk/lib/CodeGen/InlineSpiller.cpp

Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/InlineSpiller.cpp?rev=107355&r1=107354&r2=107355&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/InlineSpiller.cpp (original)
+++ llvm/trunk/lib/CodeGen/InlineSpiller.cpp Wed Jun 30 19:13:04 2010
@@ -59,6 +59,8 @@
              SmallVectorImpl<LiveInterval*> &spillIs,
              SlotIndex *earliestIndex);
   bool reMaterialize(LiveInterval &NewLI, MachineBasicBlock::iterator MI);
+  bool foldMemoryOperand(MachineBasicBlock::iterator MI,
+                         const SmallVectorImpl<unsigned> &Ops);
   void insertReload(LiveInterval &NewLI, MachineBasicBlock::iterator MI);
   void insertSpill(LiveInterval &NewLI, MachineBasicBlock::iterator MI);
 };
@@ -146,6 +148,37 @@
   return true;
 }
 
+/// foldMemoryOperand - Try folding stack slot references in Ops into MI.
+/// Return true on success, and MI will be erased.
+bool InlineSpiller::foldMemoryOperand(MachineBasicBlock::iterator MI,
+                                      const SmallVectorImpl<unsigned> &Ops) {
+  // TargetInstrInfo::foldMemoryOperand only expects explicit, non-tied
+  // operands.
+  SmallVector<unsigned, 8> FoldOps;
+  for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
+    unsigned Idx = Ops[i];
+    MachineOperand &MO = MI->getOperand(Idx);
+    if (MO.isImplicit())
+      continue;
+    // FIXME: Teach targets to deal with subregs.
+    if (MO.getSubReg())
+      return false;
+    // Tied use operands should not be passed to foldMemoryOperand.
+    if (!MI->isRegTiedToDefOperand(Idx))
+      FoldOps.push_back(Idx);
+  }
+
+  MachineInstr *FoldMI = tii_.foldMemoryOperand(mf_, MI, FoldOps, stackSlot_);
+  if (!FoldMI)
+    return false;
+  MachineBasicBlock &MBB = *MI->getParent();
+  lis_.ReplaceMachineInstrInMaps(MI, FoldMI);
+  vrm_.addSpillSlotUse(stackSlot_, FoldMI);
+  MBB.insert(MBB.erase(MI), FoldMI);
+  DEBUG(dbgs() << "\tfolded: " << *FoldMI);
+  return true;
+}
+
 /// insertReload - Insert a reload of NewLI.reg before MI.
 void InlineSpiller::insertReload(LiveInterval &NewLI,
                                  MachineBasicBlock::iterator MI) {
@@ -208,6 +241,10 @@
     // Attempt remat instead of reload.
     bool NeedsReload = Reads && !reMaterialize(NewLI, MI);
 
+    // Attempt to fold memory ops.
+    if (NewLI.empty() && foldMemoryOperand(MI, Ops))
+      continue;
+
     if (NeedsReload)
       insertReload(NewLI, MI);
 




From foldr at codedgers.com  Wed Jun 30 20:00:23 2010
From: foldr at codedgers.com (Mikhail Glushenkov)
Date: Thu, 01 Jul 2010 01:00:23 -0000
Subject: [llvm-commits] [llvm] r107360 - in /llvm/trunk:
 include/llvm/CodeGen/AsmPrinter.h include/llvm/CodeGen/GCMetadata.h
 include/llvm/CodeGen/GCMetadataPrinter.h include/llvm/MC/MCSection.h
 include/llvm/MC/SectionKind.h lib/CodeGen/AsmPrinter/OcamlGCPrinter.cpp
Message-ID: <20100701010023.22F282A6C12C@llvm.org>

Author: foldr
Date: Wed Jun 30 20:00:22 2010
New Revision: 107360

URL: http://llvm.org/viewvc/llvm-project?rev=107360&view=rev
Log:
Trailing whitespace.

Modified:
    llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
    llvm/trunk/include/llvm/CodeGen/GCMetadata.h
    llvm/trunk/include/llvm/CodeGen/GCMetadataPrinter.h
    llvm/trunk/include/llvm/MC/MCSection.h
    llvm/trunk/include/llvm/MC/SectionKind.h
    llvm/trunk/lib/CodeGen/AsmPrinter/OcamlGCPrinter.cpp

Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/AsmPrinter.h?rev=107360&r1=107359&r2=107360&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/AsmPrinter.h (original)
+++ llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Wed Jun 30 20:00:22 2010
@@ -64,7 +64,7 @@
     /// Target machine description.
     ///
     TargetMachine &TM;
-    
+
     /// Target Asm Printer information.
     ///
     const MCAsmInfo *MAI;
@@ -73,13 +73,13 @@
     /// streaming.  This owns all of the global MC-related objects for the
     /// generated translation unit.
     MCContext &OutContext;
-    
+
     /// OutStreamer - This is the MCStreamer object for the file we are
     /// generating.  This contains the transient state for the current
     /// translation unit that we are generating (such as the current section
     /// etc).
     MCStreamer &OutStreamer;
-    
+
     /// The current machine function.
     const MachineFunction *MF;
 
@@ -94,30 +94,30 @@
     /// beginning of each call to runOnMachineFunction().
     ///
     MCSymbol *CurrentFnSym;
-    
+
   private:
     // GCMetadataPrinters - The garbage collection metadata printer table.
     void *GCMetadataPrinters;  // Really a DenseMap.
-    
+
     /// VerboseAsm - Emit comments in assembly output if this is true.
     ///
     bool VerboseAsm;
     static char ID;
-    
+
     /// If VerboseAsm is set, a pointer to the loop info for this
     /// function.
     MachineLoopInfo *LI;
 
     /// DD - If the target supports dwarf debug info, this pointer is non-null.
     DwarfDebug *DD;
-    
+
     /// DE - If the target supports dwarf exception info, this pointer is
     /// non-null.
     DwarfException *DE;
-    
+
   protected:
     explicit AsmPrinter(TargetMachine &TM, MCStreamer &Streamer);
-    
+
   public:
     virtual ~AsmPrinter();
 
@@ -128,7 +128,7 @@
     /// getFunctionNumber - Return a unique ID for the current function.
     ///
     unsigned getFunctionNumber() const;
-    
+
     /// getObjFileLowering - Return information about object file lowering.
     const TargetLoweringObjectFile &getObjFileLowering() const;
 
@@ -137,16 +137,16 @@
 
     /// getCurrentSection() - Return the current section we are emitting to.
     const MCSection *getCurrentSection() const;
-    
-    
+
+
     //===------------------------------------------------------------------===//
     // MachineFunctionPass Implementation.
     //===------------------------------------------------------------------===//
-    
+
     /// getAnalysisUsage - Record analysis usage.
-    /// 
+    ///
     void getAnalysisUsage(AnalysisUsage &AU) const;
-    
+
     /// doInitialization - Set up the AsmPrinter when we are working on a new
     /// module.  If your pass overrides this, it must make sure to explicitly
     /// call this implementation.
@@ -155,7 +155,7 @@
     /// doFinalization - Shut down the asmprinter.  If you override this in your
     /// pass, you must make sure to call it explicitly.
     bool doFinalization(Module &M);
-    
+
     /// runOnMachineFunction - Emit the specified function out to the
     /// OutStreamer.
     virtual bool runOnMachineFunction(MachineFunction &MF) {
@@ -163,20 +163,20 @@
       EmitFunctionHeader();
       EmitFunctionBody();
       return false;
-    }      
-    
+    }
+
     //===------------------------------------------------------------------===//
     // Coarse grained IR lowering routines.
     //===------------------------------------------------------------------===//
-    
+
     /// SetupMachineFunction - This should be called when a new MachineFunction
     /// is being processed from runOnMachineFunction.
     void SetupMachineFunction(MachineFunction &MF);
-    
+
     /// EmitFunctionHeader - This method emits the header for the current
     /// function.
     void EmitFunctionHeader();
-    
+
     /// EmitFunctionBody - This method emits the body and trailer for a
     /// function.
     void EmitFunctionBody();
@@ -187,15 +187,15 @@
     /// the code generator.
     ///
     virtual void EmitConstantPool();
-    
-    /// EmitJumpTableInfo - Print assembly representations of the jump tables 
-    /// used by the current function to the current output stream.  
+
+    /// EmitJumpTableInfo - Print assembly representations of the jump tables
+    /// used by the current function to the current output stream.
     ///
     void EmitJumpTableInfo();
-    
+
     /// EmitGlobalVariable - Emit the specified global variable to the .s file.
     virtual void EmitGlobalVariable(const GlobalVariable *GV);
-    
+
     /// EmitSpecialLLVMGlobal - Check to see if the specified global is a
     /// special global used by LLVM.  If so, emit it and return true, otherwise
     /// do nothing and return false.
@@ -208,54 +208,54 @@
     /// if required for correctness.
     ///
     void EmitAlignment(unsigned NumBits, const GlobalValue *GV = 0) const;
-    
+
     /// EmitBasicBlockStart - This method prints the label for the specified
     /// MachineBasicBlock, an alignment (if present) and a comment describing
     /// it if appropriate.
     void EmitBasicBlockStart(const MachineBasicBlock *MBB) const;
-    
+
     /// EmitGlobalConstant - Print a general LLVM constant to the .s file.
     void EmitGlobalConstant(const Constant *CV, unsigned AddrSpace = 0);
-    
-    
+
+
     //===------------------------------------------------------------------===//
     // Overridable Hooks
     //===------------------------------------------------------------------===//
-    
+
     // Targets can, or in the case of EmitInstruction, must implement these to
     // customize output.
-    
+
     /// EmitStartOfAsmFile - This virtual method can be overridden by targets
     /// that want to emit something at the start of their file.
     virtual void EmitStartOfAsmFile(Module &) {}
-    
+
     /// EmitEndOfAsmFile - This virtual method can be overridden by targets that
     /// want to emit something at the end of their file.
     virtual void EmitEndOfAsmFile(Module &) {}
-    
+
     /// EmitFunctionBodyStart - Targets can override this to emit stuff before
     /// the first basic block in the function.
     virtual void EmitFunctionBodyStart() {}
-    
+
     /// EmitFunctionBodyEnd - Targets can override this to emit stuff after
     /// the last basic block in the function.
     virtual void EmitFunctionBodyEnd() {}
-    
+
     /// EmitInstruction - Targets should implement this to emit instructions.
     virtual void EmitInstruction(const MachineInstr *) {
       assert(0 && "EmitInstruction not implemented");
     }
-    
+
     virtual void EmitFunctionEntryLabel();
-    
+
     virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV);
-    
+
     /// isBlockOnlyReachableByFallthough - Return true if the basic block has
     /// exactly one predecessor and the control transfer mechanism between
     /// the predecessor and this block is a fall-through.
     virtual bool
     isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const;
-    
+
     //===------------------------------------------------------------------===//
     // Symbol Lowering Routines.
     //===------------------------------------------------------------------===//
@@ -264,23 +264,23 @@
     /// GetTempSymbol - Return the MCSymbol corresponding to the assembler
     /// temporary label with the specified stem and unique ID.
     MCSymbol *GetTempSymbol(StringRef Name, unsigned ID) const;
-    
+
     /// GetTempSymbol - Return an assembler temporary label with the specified
     /// stem.
     MCSymbol *GetTempSymbol(StringRef Name) const;
-    
-    
+
+
     /// GetSymbolWithGlobalValueBase - Return the MCSymbol for a symbol with
     /// global value name as its base, with the specified suffix, and where the
     /// symbol is forced to have private linkage if ForcePrivate is true.
     MCSymbol *GetSymbolWithGlobalValueBase(const GlobalValue *GV,
                                            StringRef Suffix,
                                            bool ForcePrivate = true) const;
-    
+
     /// GetExternalSymbolSymbol - Return the MCSymbol for the specified
     /// ExternalSymbol.
     MCSymbol *GetExternalSymbolSymbol(StringRef Sym) const;
-    
+
     /// GetCPISymbol - Return the symbol for the specified constant pool entry.
     MCSymbol *GetCPISymbol(unsigned CPID) const;
 
@@ -302,42 +302,42 @@
   public:
     /// printOffset - This is just convenient handler for printing offsets.
     void printOffset(int64_t Offset, raw_ostream &OS) const;
-    
+
     /// EmitInt8 - Emit a byte directive and value.
     ///
     void EmitInt8(int Value) const;
-    
+
     /// EmitInt16 - Emit a short directive and value.
     ///
     void EmitInt16(int Value) const;
-    
+
     /// EmitInt32 - Emit a long directive and value.
     ///
     void EmitInt32(int Value) const;
-    
+
     /// EmitLabelDifference - Emit something like ".long Hi-Lo" where the size
     /// in bytes of the directive is specified by Size and Hi/Lo specify the
     /// labels.  This implicitly uses .set if it is available.
     void EmitLabelDifference(const MCSymbol *Hi, const MCSymbol *Lo,
                              unsigned Size) const;
-    
-    /// EmitLabelOffsetDifference - Emit something like ".long Hi+Offset-Lo" 
+
+    /// EmitLabelOffsetDifference - Emit something like ".long Hi+Offset-Lo"
     /// where the size in bytes of the directive is specified by Size and Hi/Lo
     /// specify the labels.  This implicitly uses .set if it is available.
     void EmitLabelOffsetDifference(const MCSymbol *Hi, uint64_t Offset,
                                    const MCSymbol *Lo, unsigned Size) const;
-    
+
     //===------------------------------------------------------------------===//
     // Dwarf Emission Helper Routines
     //===------------------------------------------------------------------===//
-    
+
     /// EmitSLEB128 - emit the specified signed leb128 value.
     void EmitSLEB128(int Value, const char *Desc = 0) const;
-    
+
     /// EmitULEB128 - emit the specified unsigned leb128 value.
     void EmitULEB128(unsigned Value, const char *Desc = 0,
                      unsigned PadTo = 0) const;
-    
+
     /// EmitCFAByte - Emit a .byte 42 directive for a DW_CFA_xxx value.
     void EmitCFAByte(unsigned Val) const;
 
@@ -346,15 +346,15 @@
     /// describing the encoding.  Desc is a string saying what the encoding is
     /// specifying (e.g. "LSDA").
     void EmitEncodingByte(unsigned Val, const char *Desc = 0) const;
-    
+
     /// GetSizeOfEncodedValue - Return the size of the encoding in bytes.
     unsigned GetSizeOfEncodedValue(unsigned Encoding) const;
-    
+
     /// EmitReference - Emit a reference to a label with a specified encoding.
     ///
     void EmitReference(const MCSymbol *Sym, unsigned Encoding) const;
     void EmitReference(const GlobalValue *GV, unsigned Encoding) const;
-    
+
     /// EmitSectionOffset - Emit the 4-byte offset of Label from the start of
     /// its section.  This can be done with a special directive if the target
     /// supports it (e.g. cygwin) or by emitting it as an offset from a label at
@@ -372,20 +372,20 @@
     //===------------------------------------------------------------------===//
     // Dwarf Lowering Routines
     //===------------------------------------------------------------------===//
-    
+
     /// EmitFrameMoves - Emit frame instructions to describe the layout of the
     /// frame.
-    void EmitFrameMoves(const std::vector<MachineMove> &Moves, 
+    void EmitFrameMoves(const std::vector<MachineMove> &Moves,
                         MCSymbol *BaseLabel, bool isEH) const;
-    
-    
+
+
     //===------------------------------------------------------------------===//
     // Inline Asm Support
     //===------------------------------------------------------------------===//
   public:
     // These are hooks that targets can override to implement inline asm
     // support.  These should probably be moved out of AsmPrinter someday.
-    
+
     /// PrintSpecial - Print information related to the specified machine instr
     /// that is independent of the operand, and may be independent of the instr
     /// itself.  This can be useful for portably encoding the comment character
@@ -394,7 +394,7 @@
     /// for their own strange codes.
     virtual void PrintSpecial(const MachineInstr *MI, raw_ostream &OS,
                               const char *Code) const;
-    
+
     /// PrintAsmOperand - Print the specified operand of MI, an INLINEASM
     /// instruction, using the specified assembler variant.  Targets should
     /// override this to format as appropriate.  This method can return true if
@@ -402,16 +402,16 @@
     virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
                                  unsigned AsmVariant, const char *ExtraCode,
                                  raw_ostream &OS);
-    
+
     /// PrintAsmMemoryOperand - Print the specified operand of MI, an INLINEASM
     /// instruction, using the specified assembler variant as an address.
     /// Targets should override this to format as appropriate.  This method can
     /// return true if the operand is erroneous.
     virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
-                                       unsigned AsmVariant, 
+                                       unsigned AsmVariant,
                                        const char *ExtraCode,
                                        raw_ostream &OS);
-    
+
   private:
     /// Private state for PrintSpecial()
     // Assign a unique ID to this machine instruction.
@@ -422,7 +422,7 @@
 
     /// EmitInlineAsm - Emit a blob of inline asm to the output streamer.
     void EmitInlineAsm(StringRef Str, unsigned LocCookie) const;
-    
+
     /// EmitInlineAsm - This method formats and emits the specified machine
     /// instruction that is an inline asm.
     void EmitInlineAsm(const MachineInstr *MI) const;
@@ -430,13 +430,13 @@
     //===------------------------------------------------------------------===//
     // Internal Implementation Details
     //===------------------------------------------------------------------===//
-    
+
     /// EmitVisibility - This emits visibility information about symbol, if
     /// this is suported by the target.
     void EmitVisibility(MCSymbol *Sym, unsigned Visibility) const;
-    
+
     void EmitLinkage(unsigned Linkage, MCSymbol *GVSym) const;
-    
+
     void EmitJumpTableEntry(const MachineJumpTableInfo *MJTI,
                             const MachineBasicBlock *MBB,
                             unsigned uid) const;

Modified: llvm/trunk/include/llvm/CodeGen/GCMetadata.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GCMetadata.h?rev=107360&r1=107359&r2=107360&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/GCMetadata.h (original)
+++ llvm/trunk/include/llvm/CodeGen/GCMetadata.h Wed Jun 30 20:00:22 2010
@@ -1,4 +1,4 @@
-//===-- GCMetadata.h - Garbage collector metadata -------------------------===//
+//===-- GCMetadata.h - Garbage collector metadata ---------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -14,7 +14,7 @@
 //
 // The GCFunctionInfo class logs the data necessary to build a type accurate
 // stack map. The code generator outputs:
-// 
+//
 //   - Safe points as specified by the GCStrategy's NeededSafePoints.
 //   - Stack offsets for GC roots, as specified by calls to llvm.gcroot
 //
@@ -42,10 +42,10 @@
   class GCStrategy;
   class Constant;
   class MCSymbol;
-  
+
   namespace GC {
     /// PointKind - The type of a collector-safe point.
-    /// 
+    ///
     enum PointKind {
       Loop,    //< Instr is a loop (backwards branch).
       Return,  //< Instr is a return instruction.
@@ -53,138 +53,138 @@
       PostCall //< Instr is the return address of a call.
     };
   }
-  
+
   /// GCPoint - Metadata for a collector-safe point in machine code.
-  /// 
+  ///
   struct GCPoint {
     GC::PointKind Kind; //< The kind of the safe point.
     MCSymbol *Label;    //< A label.
-    
+
     GCPoint(GC::PointKind K, MCSymbol *L) : Kind(K), Label(L) {}
   };
-  
+
   /// GCRoot - Metadata for a pointer to an object managed by the garbage
   /// collector.
   struct GCRoot {
     int Num;            //< Usually a frame index.
     int StackOffset;    //< Offset from the stack pointer.
     const Constant *Metadata;//< Metadata straight from the call to llvm.gcroot.
-    
+
     GCRoot(int N, const Constant *MD) : Num(N), StackOffset(-1), Metadata(MD) {}
   };
-  
-  
+
+
   /// GCFunctionInfo - Garbage collection metadata for a single function.
-  /// 
+  ///
   class GCFunctionInfo {
   public:
     typedef std::vector<GCPoint>::iterator iterator;
     typedef std::vector<GCRoot>::iterator roots_iterator;
     typedef std::vector<GCRoot>::const_iterator live_iterator;
-    
+
   private:
     const Function &F;
     GCStrategy &S;
     uint64_t FrameSize;
     std::vector<GCRoot> Roots;
     std::vector<GCPoint> SafePoints;
-    
+
     // FIXME: Liveness. A 2D BitVector, perhaps?
-    // 
+    //
     //   BitVector Liveness;
-    //   
+    //
     //   bool islive(int point, int root) =
     //     Liveness[point * SafePoints.size() + root]
-    // 
+    //
     // The bit vector is the more compact representation where >3.2% of roots
     // are live per safe point (1.5% on 64-bit hosts).
-    
+
   public:
     GCFunctionInfo(const Function &F, GCStrategy &S);
     ~GCFunctionInfo();
-    
+
     /// getFunction - Return the function to which this metadata applies.
-    /// 
+    ///
     const Function &getFunction() const { return F; }
-    
+
     /// getStrategy - Return the GC strategy for the function.
-    /// 
+    ///
     GCStrategy &getStrategy() { return S; }
-    
+
     /// addStackRoot - Registers a root that lives on the stack. Num is the
     ///                stack object ID for the alloca (if the code generator is
     //                 using  MachineFrameInfo).
     void addStackRoot(int Num, const Constant *Metadata) {
       Roots.push_back(GCRoot(Num, Metadata));
     }
-    
+
     /// addSafePoint - Notes the existence of a safe point. Num is the ID of the
-    /// label just prior to the safe point (if the code generator is using 
+    /// label just prior to the safe point (if the code generator is using
     /// MachineModuleInfo).
     void addSafePoint(GC::PointKind Kind, MCSymbol *Label) {
       SafePoints.push_back(GCPoint(Kind, Label));
     }
-    
+
     /// getFrameSize/setFrameSize - Records the function's frame size.
-    /// 
+    ///
     uint64_t getFrameSize() const { return FrameSize; }
     void setFrameSize(uint64_t S) { FrameSize = S; }
-    
+
     /// begin/end - Iterators for safe points.
-    /// 
+    ///
     iterator begin() { return SafePoints.begin(); }
     iterator end()   { return SafePoints.end();   }
     size_t size() const { return SafePoints.size(); }
-    
+
     /// roots_begin/roots_end - Iterators for all roots in the function.
-    /// 
+    ///
     roots_iterator roots_begin() { return Roots.begin(); }
     roots_iterator roots_end  () { return Roots.end();   }
     size_t roots_size() const { return Roots.size(); }
-    
+
     /// live_begin/live_end - Iterators for live roots at a given safe point.
-    /// 
+    ///
     live_iterator live_begin(const iterator &p) { return roots_begin(); }
     live_iterator live_end  (const iterator &p) { return roots_end();   }
     size_t live_size(const iterator &p) const { return roots_size(); }
   };
-  
-  
+
+
   /// GCModuleInfo - Garbage collection metadata for a whole module.
-  /// 
+  ///
   class GCModuleInfo : public ImmutablePass {
     typedef StringMap<GCStrategy*> strategy_map_type;
     typedef std::vector<GCStrategy*> list_type;
     typedef DenseMap<const Function*,GCFunctionInfo*> finfo_map_type;
-    
+
     strategy_map_type StrategyMap;
     list_type StrategyList;
     finfo_map_type FInfoMap;
-    
+
     GCStrategy *getOrCreateStrategy(const Module *M, const std::string &Name);
-    
+
   public:
     typedef list_type::const_iterator iterator;
-    
+
     static char ID;
-    
+
     GCModuleInfo();
     ~GCModuleInfo();
-    
+
     /// clear - Resets the pass. The metadata deleter pass calls this.
-    /// 
+    ///
     void clear();
-    
+
     /// begin/end - Iterators for used strategies.
-    /// 
+    ///
     iterator begin() const { return StrategyList.begin(); }
     iterator end()   const { return StrategyList.end();   }
-    
+
     /// get - Look up function metadata.
-    /// 
+    ///
     GCFunctionInfo &getFunctionInfo(const Function &F);
   };
-  
+
 }
 
 #endif

Modified: llvm/trunk/include/llvm/CodeGen/GCMetadataPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GCMetadataPrinter.h?rev=107360&r1=107359&r2=107360&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/GCMetadataPrinter.h (original)
+++ llvm/trunk/include/llvm/CodeGen/GCMetadataPrinter.h Wed Jun 30 20:00:22 2010
@@ -25,49 +25,49 @@
 #include "llvm/Support/Registry.h"
 
 namespace llvm {
-  
+
   class GCMetadataPrinter;
-  
+
   /// GCMetadataPrinterRegistry - The GC assembly printer registry uses all the
   /// defaults from Registry.
   typedef Registry<GCMetadataPrinter> GCMetadataPrinterRegistry;
-  
+
   /// GCMetadataPrinter - Emits GC metadata as assembly code.
-  /// 
+  ///
   class GCMetadataPrinter {
   public:
     typedef GCStrategy::list_type list_type;
     typedef GCStrategy::iterator iterator;
-    
+
   private:
     GCStrategy *S;
-    
+
     friend class AsmPrinter;
-    
+
   protected:
     // May only be subclassed.
     GCMetadataPrinter();
-    
+
     // Do not implement.
     GCMetadataPrinter(const GCMetadataPrinter &);
     GCMetadataPrinter &operator=(const GCMetadataPrinter &);
-    
+
   public:
     GCStrategy &getStrategy() { return *S; }
     const Module &getModule() const { return S->getModule(); }
-    
+
     /// begin/end - Iterate over the collected function metadata.
     iterator begin() { return S->begin(); }
     iterator end()   { return S->end();   }
-    
+
     /// beginAssembly/finishAssembly - Emit module metadata as assembly code.
     virtual void beginAssembly(AsmPrinter &AP);
-    
+
     virtual void finishAssembly(AsmPrinter &AP);
-    
+
     virtual ~GCMetadataPrinter();
   };
-  
+
 }
 
 #endif

Modified: llvm/trunk/include/llvm/MC/MCSection.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCSection.h?rev=107360&r1=107359&r2=107360&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCSection.h (original)
+++ llvm/trunk/include/llvm/MC/MCSection.h Wed Jun 30 20:00:22 2010
@@ -23,7 +23,7 @@
   class MCContext;
   class MCAsmInfo;
   class raw_ostream;
-  
+
   /// MCSection - Instances of this class represent a uniqued identifier for a
   /// section in the current translation unit.  The MCContext class uniques and
   /// creates these.
@@ -49,7 +49,7 @@
     SectionKind getKind() const { return Kind; }
 
     SectionVariant getVariant() const { return Variant; }
-    
+
     virtual void PrintSwitchToSection(const MCAsmInfo &MAI,
                                       raw_ostream &OS) const = 0;
 
@@ -63,7 +63,7 @@
 
     static bool classof(const MCSection *) { return true; }
   };
-  
+
 } // end namespace llvm
 
 #endif

Modified: llvm/trunk/include/llvm/MC/SectionKind.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/SectionKind.h?rev=107360&r1=107359&r2=107360&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/SectionKind.h (original)
+++ llvm/trunk/include/llvm/MC/SectionKind.h Wed Jun 30 20:00:22 2010
@@ -29,10 +29,10 @@
   enum Kind {
     /// Metadata - Debug info sections or other metadata.
     Metadata,
-    
+
     /// Text - Text section, used for functions and other executable code.
     Text,
-    
+
     /// ReadOnly - Data that is never written to at program runtime by the
     /// program or the dynamic linker.  Things in the top-level readonly
     /// SectionKind are not mergeable.
@@ -45,7 +45,7 @@
 
            /// Mergeable1ByteCString - 1 byte mergable, null terminated, string.
            Mergeable1ByteCString,
-    
+
            /// Mergeable2ByteCString - 2 byte mergable, null terminated, string.
            Mergeable2ByteCString,
 
@@ -56,11 +56,11 @@
         /// constants together.  For example, this can be used to unique
         /// constant pool entries etc.
         MergeableConst,
-    
+
             /// MergeableConst4 - This is a section used by 4-byte constants,
             /// for example, floats.
             MergeableConst4,
-    
+
             /// MergeableConst8 - This is a section used by 8-byte constants,
             /// for example, doubles.
             MergeableConst8,
@@ -68,33 +68,33 @@
             /// MergeableConst16 - This is a section used by 16-byte constants,
             /// for example, vectors.
             MergeableConst16,
-    
+
     /// Writeable - This is the base of all segments that need to be written
     /// to during program runtime.
-    
+
        /// ThreadLocal - This is the base of all TLS segments.  All TLS
        /// objects must be writeable, otherwise there is no reason for them to
        /// be thread local!
-    
+
            /// ThreadBSS - Zero-initialized TLS data objects.
            ThreadBSS,
-    
+
            /// ThreadData - Initialized TLS data objects.
            ThreadData,
-    
+
        /// GlobalWriteableData - Writeable data that is global (not thread
        /// local).
-    
+
            /// BSS - Zero initialized writeable data.
            BSS,
-    
+
                /// BSSLocal - This is BSS (zero initialized and writable) data
                /// which has local linkage.
                BSSLocal,
-    
+
                /// BSSExtern - This is BSS data with normal external linkage.
                BSSExtern,
-    
+
            /// Common - Data with common linkage.  These represent tentative
            /// definitions, which always have a zero initializer and are never
            /// marked 'constant'.
@@ -123,20 +123,20 @@
            /// mark the pages these globals end up on as read-only after it is
            /// done with its relocation phase.
            ReadOnlyWithRel,
-    
+
                /// ReadOnlyWithRelLocal - This is data that is readonly by the
                /// program, but must be writeable so that the dynamic linker
                /// can perform relocations in it.  This is used when we know
                /// that all the relocations are to globals in this final
                /// linked image.
                ReadOnlyWithRelLocal
-    
+
   } K : 8;
 public:
-  
+
   bool isMetadata() const { return K == Metadata; }
   bool isText() const { return K == Text; }
-  
+
   bool isReadOnly() const {
     return K == ReadOnly || isMergeableCString() ||
            isMergeableConst();
@@ -149,7 +149,7 @@
   bool isMergeable1ByteCString() const { return K == Mergeable1ByteCString; }
   bool isMergeable2ByteCString() const { return K == Mergeable2ByteCString; }
   bool isMergeable4ByteCString() const { return K == Mergeable4ByteCString; }
-  
+
   bool isMergeableConst() const {
     return K == MergeableConst || K == MergeableConst4 ||
            K == MergeableConst8 || K == MergeableConst16;
@@ -157,38 +157,38 @@
   bool isMergeableConst4() const { return K == MergeableConst4; }
   bool isMergeableConst8() const { return K == MergeableConst8; }
   bool isMergeableConst16() const { return K == MergeableConst16; }
-  
+
   bool isWriteable() const {
     return isThreadLocal() || isGlobalWriteableData();
   }
-  
+
   bool isThreadLocal() const {
     return K == ThreadData || K == ThreadBSS;
   }
-  
-  bool isThreadBSS() const { return K == ThreadBSS; } 
-  bool isThreadData() const { return K == ThreadData; } 
+
+  bool isThreadBSS() const { return K == ThreadBSS; }
+  bool isThreadData() const { return K == ThreadData; }
 
   bool isGlobalWriteableData() const {
     return isBSS() || isCommon() || isDataRel() || isReadOnlyWithRel();
   }
-  
+
   bool isBSS() const { return K == BSS || K == BSSLocal || K == BSSExtern; }
   bool isBSSLocal() const { return K == BSSLocal; }
   bool isBSSExtern() const { return K == BSSExtern; }
-  
+
   bool isCommon() const { return K == Common; }
-  
+
   bool isDataRel() const {
     return K == DataRel || K == DataRelLocal || K == DataNoRel;
   }
-  
+
   bool isDataRelLocal() const {
     return K == DataRelLocal || K == DataNoRel;
   }
 
   bool isDataNoRel() const { return K == DataNoRel; }
-  
+
   bool isReadOnlyWithRel() const {
     return K == ReadOnlyWithRel || K == ReadOnlyWithRelLocal;
   }
@@ -196,14 +196,14 @@
   bool isReadOnlyWithRelLocal() const {
     return K == ReadOnlyWithRelLocal;
   }
-private: 
+private:
   static SectionKind get(Kind K) {
     SectionKind Res;
     Res.K = K;
     return Res;
   }
 public:
-  
+
   static SectionKind getMetadata() { return get(Metadata); }
   static SectionKind getText() { return get(Text); }
   static SectionKind getReadOnly() { return get(ReadOnly); }
@@ -234,7 +234,7 @@
     return get(ReadOnlyWithRelLocal);
   }
 };
-  
+
 } // end namespace llvm
 
 #endif

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/OcamlGCPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/OcamlGCPrinter.cpp?rev=107360&r1=107359&r2=107360&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/OcamlGCPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/OcamlGCPrinter.cpp Wed Jun 30 20:00:22 2010
@@ -52,13 +52,13 @@
   SymName.append(MId.begin(), std::find(MId.begin(), MId.end(), '.'));
   SymName += "__";
   SymName += Id;
-  
+
   // Capitalize the first letter of the module name.
   SymName[Letter] = toupper(SymName[Letter]);
-  
+
   SmallString<128> TmpStr;
   AP.Mang->getNameWithPrefix(TmpStr, SymName);
-  
+
   MCSymbol *Sym = AP.OutContext.GetOrCreateSymbol(TmpStr);
 
   AP.OutStreamer.EmitSymbolAttribute(Sym, MCSA_Global);




From foldr at codedgers.com  Wed Jun 30 20:00:27 2010
From: foldr at codedgers.com (Mikhail Glushenkov)
Date: Thu, 01 Jul 2010 01:00:27 -0000
Subject: [llvm-commits] [llvm] r107361 -
	/llvm/trunk/lib/CompilerDriver/Tool.cpp
Message-ID: <20100701010027.845462A6C12D@llvm.org>

Author: foldr
Date: Wed Jun 30 20:00:27 2010
New Revision: 107361

URL: http://llvm.org/viewvc/llvm-project?rev=107361&view=rev
Log:
80-col violation.

Modified:
    llvm/trunk/lib/CompilerDriver/Tool.cpp

Modified: llvm/trunk/lib/CompilerDriver/Tool.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CompilerDriver/Tool.cpp?rev=107361&r1=107360&r2=107361&view=diff
==============================================================================
--- llvm/trunk/lib/CompilerDriver/Tool.cpp (original)
+++ llvm/trunk/lib/CompilerDriver/Tool.cpp Wed Jun 30 20:00:27 2010
@@ -85,7 +85,8 @@
   StrVector Out;
 
   // HACK: this won't be needed when we'll migrate away from CommandLine.
-  std::stable_sort(Args.begin(), Args.end(), &CompareFirst<unsigned, std::string>);
+  std::stable_sort(Args.begin(), Args.end(),
+                   &CompareFirst<unsigned, std::string>);
   for (ArgsVector::iterator B = Args.begin(), E = Args.end(); B != E; ++B) {
     Out.push_back(B->second);
   }




From foldr at codedgers.com  Wed Jun 30 20:00:32 2010
From: foldr at codedgers.com (Mikhail Glushenkov)
Date: Thu, 01 Jul 2010 01:00:32 -0000
Subject: [llvm-commits] [llvm] r107362 -
	/llvm/trunk/tools/llvmc/plugins/Base/Base.td.in
Message-ID: <20100701010032.9CB702A6C12C@llvm.org>

Author: foldr
Date: Wed Jun 30 20:00:32 2010
New Revision: 107362

URL: http://llvm.org/viewvc/llvm-project?rev=107362&view=rev
Log:
Make -filelist work with -linker=c++.

Modified:
    llvm/trunk/tools/llvmc/plugins/Base/Base.td.in

Modified: llvm/trunk/tools/llvmc/plugins/Base/Base.td.in
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/plugins/Base/Base.td.in?rev=107362&r1=107361&r2=107362&view=diff
==============================================================================
--- llvm/trunk/tools/llvmc/plugins/Base/Base.td.in (original)
+++ llvm/trunk/tools/llvmc/plugins/Base/Base.td.in Wed Jun 30 20:00:32 2010
@@ -262,12 +262,12 @@
 ]>;
 
 // Base class for linkers
-class llvm_gcc_based_linker <string cmd_prefix> : Tool<
+class llvm_gcc_based_linker <string cmd_prefix, dag on_empty> : Tool<
 [(in_language ["object-code", "static-library"]),
  (out_language "executable"),
  (output_suffix "out"),
  (command cmd_prefix),
- (works_on_empty (case (not_empty "filelist"), true,
+ (works_on_empty (case (and (not_empty "filelist"), on_empty), true,
                        (default), false)),
  (join),
  (actions (case
@@ -295,9 +295,13 @@
 ]>;
 
 // Default linker
-def llvm_gcc_linker : llvm_gcc_based_linker<"@LLVMGCCCOMMAND@">;
+def llvm_gcc_linker : llvm_gcc_based_linker<"@LLVMGCCCOMMAND@",
+    (not (or (parameter_equals "linker", "g++"),
+         (parameter_equals "linker", "c++")))>;
 // Alternative linker for C++
-def llvm_gcc_cpp_linker : llvm_gcc_based_linker<"@LLVMGXXCOMMAND@">;
+def llvm_gcc_cpp_linker : llvm_gcc_based_linker<"@LLVMGXXCOMMAND@",
+    (or (parameter_equals "linker", "g++"),
+        (parameter_equals "linker", "c++"))>;
 
 // Language map
 




From foldr at codedgers.com  Wed Jun 30 20:00:37 2010
From: foldr at codedgers.com (Mikhail Glushenkov)
Date: Thu, 01 Jul 2010 01:00:37 -0000
Subject: [llvm-commits] [llvm] r107363 -
	/llvm/trunk/test/LLVMC/C++/filelist.cpp
Message-ID: <20100701010038.00FBD2A6C12D@llvm.org>

Author: foldr
Date: Wed Jun 30 20:00:37 2010
New Revision: 107363

URL: http://llvm.org/viewvc/llvm-project?rev=107363&view=rev
Log:
Test for the -filelist fix.

Added:
    llvm/trunk/test/LLVMC/C++/filelist.cpp

Added: llvm/trunk/test/LLVMC/C++/filelist.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/LLVMC/C%2B%2B/filelist.cpp?rev=107363&view=auto
==============================================================================
--- llvm/trunk/test/LLVMC/C++/filelist.cpp (added)
+++ llvm/trunk/test/LLVMC/C++/filelist.cpp Wed Jun 30 20:00:37 2010
@@ -0,0 +1,3 @@
+// Test that the -filelist option works correctly with -linker=c++.
+// RUN: llvmc --dry-run -filelist DUMMY -linker c++ |& grep llvm-g++
+// XFAIL: vg




From bruno.cardoso at gmail.com  Wed Jun 30 20:20:06 2010
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Thu, 01 Jul 2010 01:20:06 -0000
Subject: [llvm-commits] [llvm] r107365 - in /llvm/trunk:
 lib/Target/X86/X86InstrFormats.td lib/Target/X86/X86InstrInfo.h
 lib/Target/X86/X86InstrSSE.td lib/Target/X86/X86MCCodeEmitter.cpp
 test/MC/AsmParser/X86/x86_32-encoding.s
 test/MC/AsmParser/X86/x86_64-encoding.s
Message-ID: <20100701012007.259952A6C12C@llvm.org>

Author: bruno
Date: Wed Jun 30 20:20:06 2010
New Revision: 107365

URL: http://llvm.org/viewvc/llvm-project?rev=107365&view=rev
Log:

- Add AVX SSE2 Move doubleword and quadword instructions.
- Add encode bits for VEX_W
- All 128-bit SSE 1 & SSE2 instructions that are described
  in the .td file now have a AVX encoded form already working.


Modified:
    llvm/trunk/lib/Target/X86/X86InstrFormats.td
    llvm/trunk/lib/Target/X86/X86InstrInfo.h
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp
    llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
    llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s

Modified: llvm/trunk/lib/Target/X86/X86InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFormats.td?rev=107365&r1=107364&r2=107365&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrFormats.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrFormats.td Wed Jun 30 20:20:06 2010
@@ -102,6 +102,7 @@
 class TA     { bits<4> Prefix = 14; }
 class TF     { bits<4> Prefix = 15; }
 class VEX    { bit hasVEXPrefix = 1; }
+class VEX_W  { bit hasVEX_WPrefix = 1; }
 class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; }
 
 class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
@@ -130,8 +131,9 @@
   bit hasLockPrefix = 0;    // Does this inst have a 0xF0 prefix?
   bits<2> SegOvrBits = 0;   // Segment override prefix.
   Domain ExeDomain = d;
-  bit hasVEXPrefix  = 0;    // Does this inst requires a VEX prefix?
-  bit hasVEX_4VPrefix  = 0; // Does this inst requires the VEX.VVVV field?
+  bit hasVEXPrefix = 0;     // Does this inst requires a VEX prefix?
+  bit hasVEX_WPrefix = 0;   // Does this inst set the VEX_W field?
+  bit hasVEX_4VPrefix = 0;  // Does this inst requires the VEX.VVVV field?
 
   // TSFlags layout should be kept in sync with X86InstrInfo.h.
   let TSFlags{5-0}   = FormBits;
@@ -146,7 +148,8 @@
   let TSFlags{23-22} = ExeDomain.Value;
   let TSFlags{31-24} = Opcode;
   let TSFlags{32}    = hasVEXPrefix;
-  let TSFlags{33}    = hasVEX_4VPrefix;
+  let TSFlags{33}    = hasVEX_WPrefix;
+  let TSFlags{34}    = hasVEX_4VPrefix;
 }
 
 class I<bits<8> o, Format f, dag outs, dag ins, string asm,

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=107365&r1=107364&r2=107365&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Wed Jun 30 20:20:06 2010
@@ -429,9 +429,9 @@
     // address instructions in SSE are represented as 3 address ones in AVX
     // and the additional register is encoded in VEX_VVVV prefix.
     //
-    VEXShift    = 0,
-    VEX         = 1 << VEXShift,
-    VEX_4V      = 2 << VEXShift
+    VEX         = 1,
+    VEX_W       = 1 << 1,
+    VEX_4V      = 1 << 2
   };
 
   // getBaseOpcodeFor - This function returns the "base" X86 opcode for the

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=107365&r1=107364&r2=107365&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Jun 30 20:20:06 2010
@@ -2888,6 +2888,18 @@
 // SSE2 - Move Doubleword
 //===---------------------------------------------------------------------===//
 
+// Move Int Doubleword to Packed Double Int
+let isAsmParserOnly = 1 in {
+def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
+                      "movd\t{$src, $dst|$dst, $src}",
+                      [(set VR128:$dst,
+                        (v4i32 (scalar_to_vector GR32:$src)))]>, VEX;
+def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
+                      "movd\t{$src, $dst|$dst, $src}",
+                      [(set VR128:$dst,
+                        (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
+                      VEX;
+}
 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
                       "movd\t{$src, $dst|$dst, $src}",
                       [(set VR128:$dst,
@@ -2897,6 +2909,18 @@
                       [(set VR128:$dst,
                         (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
 
+
+// Move Int Doubleword to Single Scalar
+let isAsmParserOnly = 1 in {
+def VMOVDI2SSrr  : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
+                      "movd\t{$src, $dst|$dst, $src}",
+                      [(set FR32:$dst, (bitconvert GR32:$src))]>, VEX;
+
+def VMOVDI2SSrm  : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
+                      "movd\t{$src, $dst|$dst, $src}",
+                      [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>,
+                      VEX;
+}
 def MOVDI2SSrr  : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
                       "movd\t{$src, $dst|$dst, $src}",
                       [(set FR32:$dst, (bitconvert GR32:$src))]>;
@@ -2905,6 +2929,18 @@
                       "movd\t{$src, $dst|$dst, $src}",
                       [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
 
+// Move Packed Doubleword Int to Packed Double Int
+let isAsmParserOnly = 1 in {
+def VMOVPDI2DIrr  : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
+                       "movd\t{$src, $dst|$dst, $src}",
+                       [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
+                                        (iPTR 0)))]>, VEX;
+def VMOVPDI2DImr  : VPDI<0x7E, MRMDestMem, (outs),
+                       (ins i32mem:$dst, VR128:$src),
+                       "movd\t{$src, $dst|$dst, $src}",
+                       [(store (i32 (vector_extract (v4i32 VR128:$src),
+                                     (iPTR 0))), addr:$dst)]>, VEX;
+}
 def MOVPDI2DIrr  : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
                        "movd\t{$src, $dst|$dst, $src}",
                        [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
@@ -2914,6 +2950,15 @@
                        [(store (i32 (vector_extract (v4i32 VR128:$src),
                                      (iPTR 0))), addr:$dst)]>;
 
+// Move Scalar Single to Double Int
+let isAsmParserOnly = 1 in {
+def VMOVSS2DIrr  : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
+                      "movd\t{$src, $dst|$dst, $src}",
+                      [(set GR32:$dst, (bitconvert FR32:$src))]>, VEX;
+def VMOVSS2DImr  : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
+                      "movd\t{$src, $dst|$dst, $src}",
+                      [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>, VEX;
+}
 def MOVSS2DIrr  : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
                       "movd\t{$src, $dst|$dst, $src}",
                       [(set GR32:$dst, (bitconvert FR32:$src))]>;
@@ -2922,19 +2967,37 @@
                       [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
 
 // movd / movq to XMM register zero-extends
+let AddedComplexity = 15, isAsmParserOnly = 1 in {
+def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
+                       "movd\t{$src, $dst|$dst, $src}",
+                       [(set VR128:$dst, (v4i32 (X86vzmovl
+                                      (v4i32 (scalar_to_vector GR32:$src)))))]>,
+                                      VEX;
+def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
+                       "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
+                       [(set VR128:$dst, (v2i64 (X86vzmovl
+                                      (v2i64 (scalar_to_vector GR64:$src)))))]>,
+                                      VEX, VEX_W;
+}
 let AddedComplexity = 15 in {
 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
                        "movd\t{$src, $dst|$dst, $src}",
                        [(set VR128:$dst, (v4i32 (X86vzmovl
                                       (v4i32 (scalar_to_vector GR32:$src)))))]>;
-// This is X86-64 only.
 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
-                       "mov{d|q}\t{$src, $dst|$dst, $src}",
+                       "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
                        [(set VR128:$dst, (v2i64 (X86vzmovl
                                       (v2i64 (scalar_to_vector GR64:$src)))))]>;
 }
 
 let AddedComplexity = 20 in {
+let isAsmParserOnly = 1 in
+def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
+                       "movd\t{$src, $dst|$dst, $src}",
+                       [(set VR128:$dst,
+                         (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
+                                                   (loadi32 addr:$src))))))]>,
+                                                   VEX;
 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
                        "movd\t{$src, $dst|$dst, $src}",
                        [(set VR128:$dst,
@@ -2953,12 +3016,25 @@
 // SSE2 - Move Quadword
 //===---------------------------------------------------------------------===//
 
-// SSE2 instructions with XS prefix
+// Move Quadword Int to Packed Quadword Int
+let isAsmParserOnly = 1 in
+def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
+                    "vmovq\t{$src, $dst|$dst, $src}",
+                    [(set VR128:$dst,
+                      (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
+                    VEX, Requires<[HasAVX, HasSSE2]>;
 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
                     "movq\t{$src, $dst|$dst, $src}",
                     [(set VR128:$dst,
                       (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
-                  Requires<[HasSSE2]>;
+                    Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
+
+// Move Packed Quadword Int to Quadword Int
+let isAsmParserOnly = 1 in
+def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
+                      "movq\t{$src, $dst|$dst, $src}",
+                      [(store (i64 (vector_extract (v2i64 VR128:$src),
+                                    (iPTR 0))), addr:$dst)]>, VEX;
 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
                       "movq\t{$src, $dst|$dst, $src}",
                       [(store (i64 (vector_extract (v2i64 VR128:$src),
@@ -2968,17 +3044,29 @@
           (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
 
 // Store / copy lower 64-bits of a XMM register.
+let isAsmParserOnly = 1 in
+def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
+                     "movq\t{$src, $dst|$dst, $src}",
+                     [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
                      "movq\t{$src, $dst|$dst, $src}",
                      [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
 
+let AddedComplexity = 20, isAsmParserOnly = 1 in
+def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
+                     "vmovq\t{$src, $dst|$dst, $src}",
+                     [(set VR128:$dst,
+                       (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
+                                                 (loadi64 addr:$src))))))]>,
+                     XS, VEX, Requires<[HasAVX, HasSSE2]>;
+
 let AddedComplexity = 20 in {
 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
                      "movq\t{$src, $dst|$dst, $src}",
                      [(set VR128:$dst,
                        (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
-                                                 (loadi64 addr:$src))))))]>, XS,
-                   Requires<[HasSSE2]>;
+                                                 (loadi64 addr:$src))))))]>,
+                     XS, Requires<[HasSSE2]>;
 
 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
             (MOVZQI2PQIrm addr:$src)>;
@@ -2989,12 +3077,23 @@
 
 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
 // IA32 document. movq xmm1, xmm2 does clear the high bits.
+let isAsmParserOnly = 1, AddedComplexity = 15 in
+def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
+                        "vmovq\t{$src, $dst|$dst, $src}",
+                    [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
+                      XS, VEX, Requires<[HasAVX, HasSSE2]>;
 let AddedComplexity = 15 in
 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
                         "movq\t{$src, $dst|$dst, $src}",
                     [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
                       XS, Requires<[HasSSE2]>;
 
+let AddedComplexity = 20, isAsmParserOnly = 1 in
+def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
+                        "vmovq\t{$src, $dst|$dst, $src}",
+                    [(set VR128:$dst, (v2i64 (X86vzmovl
+                                             (loadv2i64 addr:$src))))]>,
+                      XS, VEX, Requires<[HasAVX, HasSSE2]>;
 let AddedComplexity = 20 in {
 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
                         "movq\t{$src, $dst|$dst, $src}",
@@ -3006,10 +3105,22 @@
             (MOVZPQILo2PQIrm addr:$src)>;
 }
 
+// Instructions to match in the assembler
+let isAsmParserOnly = 1 in {
+// This instructions is in fact an alias to movd with 64 bit dst
+def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
+                      "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
+def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
+                      "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
+}
+
 // Instructions for the disassembler
 // xr = XMM register
 // xm = mem64
 
+let isAsmParserOnly = 1 in
+def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
+                 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
                  "movq\t{$src, $dst|$dst, $src}", []>, XS;
 

Modified: llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp?rev=107365&r1=107364&r2=107365&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp Wed Jun 30 20:20:06 2010
@@ -449,6 +449,9 @@
   if (TSFlags & X86II::OpSize)
     VEX_PP = 0x01;
 
+  if ((TSFlags >> 32) & X86II::VEX_W)
+    VEX_W = 1;
+
   switch (TSFlags & X86II::Op0Mask) {
   default: assert(0 && "Invalid prefix!");
   case X86II::T8:  // 0F 38
@@ -508,15 +511,20 @@
         VEX_X = 0x0;
     }
     break;
-  default: // MRM0r-MRM7r
+  default: // MRMDestReg, MRM0r-MRM7r
+    if (MI.getOperand(CurOp).isReg() &&
+        X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
+      VEX_B = 0;
+
     if (HasVEX_4V)
       VEX_4V = getVEXRegisterEncoding(MI, CurOp);
 
     CurOp++;
     for (; CurOp != NumOps; ++CurOp) {
       const MCOperand &MO = MI.getOperand(CurOp);
-      if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
-        VEX_B = 0x0;
+      if (MO.isReg() && !HasVEX_4V &&
+          X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
+        VEX_R = 0x0;
     }
     break;
     assert(0 && "Not implemented!");
@@ -535,7 +543,7 @@
   //
   unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
 
-  if (VEX_B && VEX_X) { // 2 byte VEX prefix
+  if (VEX_B && VEX_X && !VEX_W) { // 2 byte VEX prefix
     EmitByte(0xC5, CurByte, OS);
     EmitByte(LastByte | (VEX_R << 7), CurByte, OS);
     return;
@@ -543,7 +551,7 @@
 
   // 3 byte VEX prefix
   EmitByte(0xC4, CurByte, OS);
-  EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_5M, CurByte, OS);
+  EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS);
   EmitByte(LastByte | (VEX_W << 7), CurByte, OS);
 }
 

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s?rev=107365&r1=107364&r2=107365&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s Wed Jun 30 20:20:06 2010
@@ -11502,3 +11502,31 @@
 // CHECK: encoding: [0xc5,0xf9,0xf7,0xd1]
           vmaskmovdqu  %xmm1, %xmm2
 
+// CHECK: vmovd  %xmm1, %eax
+// CHECK: encoding: [0xc5,0xf9,0x7e,0xc8]
+          vmovd  %xmm1, %eax
+
+// CHECK: vmovd  %xmm1, (%eax)
+// CHECK: encoding: [0xc5,0xf9,0x7e,0x08]
+          vmovd  %xmm1, (%eax)
+
+// CHECK: vmovd  %eax, %xmm1
+// CHECK: encoding: [0xc5,0xf9,0x6e,0xc8]
+          vmovd  %eax, %xmm1
+
+// CHECK: vmovd  (%eax), %xmm1
+// CHECK: encoding: [0xc5,0xf9,0x6e,0x08]
+          vmovd  (%eax), %xmm1
+
+// CHECK: vmovq  %xmm1, (%eax)
+// CHECK: encoding: [0xc5,0xf9,0xd6,0x08]
+          vmovq  %xmm1, (%eax)
+
+// CHECK: vmovq  %xmm1, %xmm2
+// CHECK: encoding: [0xc5,0xfa,0x7e,0xd1]
+          vmovq  %xmm1, %xmm2
+
+// CHECK: vmovq  (%eax), %xmm1
+// CHECK: encoding: [0xc5,0xfa,0x7e,0x08]
+          vmovq  (%eax), %xmm1
+

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s?rev=107365&r1=107364&r2=107365&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s Wed Jun 30 20:20:06 2010
@@ -1542,3 +1542,39 @@
 // CHECK: encoding: [0xc4,0x41,0x79,0xf7,0xfe]
           vmaskmovdqu  %xmm14, %xmm15
 
+// CHECK: vmovd  %eax, %xmm14
+// CHECK: encoding: [0xc5,0x79,0x6e,0xf0]
+          vmovd  %eax, %xmm14
+
+// CHECK: vmovd  (%rax), %xmm14
+// CHECK: encoding: [0xc5,0x79,0x6e,0x30]
+          vmovd  (%rax), %xmm14
+
+// CHECK: vmovd  %xmm14, (%rax)
+// CHECK: encoding: [0xc5,0x79,0x7e,0x30]
+          vmovd  %xmm14, (%rax)
+
+// CHECK: vmovd  %rax, %xmm14
+// CHECK: encoding: [0xc4,0x61,0xf9,0x6e,0xf0]
+          vmovd  %rax, %xmm14
+
+// CHECK: vmovq  %xmm14, (%rax)
+// CHECK: encoding: [0xc5,0x79,0xd6,0x30]
+          vmovq  %xmm14, (%rax)
+
+// CHECK: vmovq  %xmm14, %xmm12
+// CHECK: encoding: [0xc4,0x41,0x7a,0x7e,0xe6]
+          vmovq  %xmm14, %xmm12
+
+// CHECK: vmovq  (%rax), %xmm14
+// CHECK: encoding: [0xc5,0x7a,0x7e,0x30]
+          vmovq  (%rax), %xmm14
+
+// CHECK: vmovq  %rax, %xmm14
+// CHECK: encoding: [0xc4,0x61,0xf9,0x6e,0xf0]
+          vmovq  %rax, %xmm14
+
+// CHECK: vmovq  %xmm14, %rax
+// CHECK: encoding: [0xc4,0x61,0xf9,0x7e,0xf0]
+          vmovq  %xmm14, %rax
+




From gohman at apple.com  Wed Jun 30 20:33:21 2010
From: gohman at apple.com (Dan Gohman)
Date: Thu, 01 Jul 2010 01:33:21 -0000
Subject: [llvm-commits] [llvm] r107368 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Message-ID: <20100701013321.6915A2A6C12C@llvm.org>

Author: djg
Date: Wed Jun 30 20:33:21 2010
New Revision: 107368

URL: http://llvm.org/viewvc/llvm-project?rev=107368&view=rev
Log:
Don't use operator[] here, because it's not desirable to insert a default
value if the search fails.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=107368&r1=107367&r2=107368&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Wed Jun 30 20:33:21 2010
@@ -6127,8 +6127,11 @@
         }
         Reg = RegOut;
       } else {
-        Reg = FuncInfo.ValueMap[PHIOp];
-        if (Reg == 0) {
+        DenseMap<const Value *, unsigned>::iterator I =
+          FuncInfo.ValueMap.find(PHIOp);
+        if (I != FuncInfo.ValueMap.end())
+          Reg = I->second;
+        else {
           assert(isa<AllocaInst>(PHIOp) &&
                  FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
                  "Didn't codegen value into a register!??");




From gohman at apple.com  Wed Jun 30 20:59:43 2010
From: gohman at apple.com (Dan Gohman)
Date: Thu, 01 Jul 2010 01:59:43 -0000
Subject: [llvm-commits] [llvm] r107371 - in
 /llvm/trunk/lib/CodeGen/SelectionDAG: SelectionDAGBuilder.cpp
 SelectionDAGBuilder.h
Message-ID: <20100701015943.6C3782A6C12C@llvm.org>

Author: djg
Date: Wed Jun 30 20:59:43 2010
New Revision: 107371

URL: http://llvm.org/viewvc/llvm-project?rev=107371&view=rev
Log:
Reapply r106422, splitting the code for materializing a value out of
SelectionDAGBuilder::getValue into a helper function, with fixes to
use DenseMaps safely.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=107371&r1=107370&r2=107371&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Wed Jun 30 20:59:43 2010
@@ -805,27 +805,63 @@
   }
 }
 
+// getValue - Return an SDValue for the given Value.
 SDValue SelectionDAGBuilder::getValue(const Value *V) {
+  // If we already have an SDValue for this value, use it. It's important
+  // to do this first, so that we don't create a CopyFromReg if we already
+  // have a regular SDValue.
   SDValue &N = NodeMap[V];
   if (N.getNode()) return N;
 
+  // If there's a virtual register allocated and initialized for this
+  // value, use it.
+  DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
+  if (It != FuncInfo.ValueMap.end()) {
+    unsigned InReg = It->second;
+    RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
+    SDValue Chain = DAG.getEntryNode();
+    return N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL);
+  }
+
+  // Otherwise create a new SDValue and remember it.
+  SDValue Val = getValueImpl(V);
+  NodeMap[V] = Val;
+  return Val;
+}
+
+/// getNonRegisterValue - Return an SDValue for the given Value, but
+/// don't look in FuncInfo.ValueMap for a virtual register.
+SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
+  // If we already have an SDValue for this value, use it.
+  SDValue &N = NodeMap[V];
+  if (N.getNode()) return N;
+
+  // Otherwise create a new SDValue and remember it.
+  SDValue Val = getValueImpl(V);
+  NodeMap[V] = Val;
+  return Val;
+}
+
+/// getValueImpl - Helper function for getValue and getMaterializedValue.
+/// Create an SDValue for the given value.
+SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
   if (const Constant *C = dyn_cast<Constant>(V)) {
     EVT VT = TLI.getValueType(V->getType(), true);
 
     if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
-      return N = DAG.getConstant(*CI, VT);
+      return DAG.getConstant(*CI, VT);
 
     if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
-      return N = DAG.getGlobalAddress(GV, VT);
+      return DAG.getGlobalAddress(GV, VT);
 
     if (isa<ConstantPointerNull>(C))
-      return N = DAG.getConstant(0, TLI.getPointerTy());
+      return DAG.getConstant(0, TLI.getPointerTy());
 
     if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
-      return N = DAG.getConstantFP(*CFP, VT);
+      return DAG.getConstantFP(*CFP, VT);
 
     if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
-      return N = DAG.getUNDEF(VT);
+      return DAG.getUNDEF(VT);
 
     if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
       visit(CE->getOpcode(), *CE);
@@ -913,12 +949,18 @@
       return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
   }
 
-  unsigned InReg = FuncInfo.ValueMap[V];
-  assert(InReg && "Value not in map!");
+  // If this is an instruction which fast-isel has deferred, select it now.
+  if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
+    assert(Inst->isSafeToSpeculativelyExecute() &&
+           "Instruction with side effects deferred!");
+    visit(*Inst);
+    DenseMap<const Value *, SDValue>::iterator NIt = NodeMap.find(Inst);
+    if (NIt != NodeMap.end() && NIt->second.getNode())
+      return NIt->second;
+  }
 
-  RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
-  SDValue Chain = DAG.getEntryNode();
-  return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL);
+  llvm_unreachable("Can't get register for value!");
+  return SDValue();
 }
 
 /// Get the EVTs and ArgFlags collections that represent the legalized return 
@@ -5881,7 +5923,7 @@
 
 void
 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
-  SDValue Op = getValue(V);
+  SDValue Op = getNonRegisterValue(V);
   assert((Op.getOpcode() != ISD::CopyFromReg ||
           cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
          "Copy from a reg to the same reg!");

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h?rev=107371&r1=107370&r2=107371&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h Wed Jun 30 20:59:43 2010
@@ -346,6 +346,8 @@
   void visit(unsigned Opcode, const User &I);
 
   SDValue getValue(const Value *V);
+  SDValue getNonRegisterValue(const Value *V);
+  SDValue getValueImpl(const Value *V);
 
   void setValue(const Value *V, SDValue NewN) {
     SDValue &N = NodeMap[V];




From gohman at apple.com  Wed Jun 30 21:27:15 2010
From: gohman at apple.com (Dan Gohman)
Date: Thu, 01 Jul 2010 02:27:15 -0000
Subject: [llvm-commits] [llvm] r107373 - in /llvm/trunk:
 lib/Target/X86/X86FastISel.cpp test/CodeGen/X86/fast-isel-gep.ll
Message-ID: <20100701022715.8F4542A6C12C@llvm.org>

Author: djg
Date: Wed Jun 30 21:27:15 2010
New Revision: 107373

URL: http://llvm.org/viewvc/llvm-project?rev=107373&view=rev
Log:
Teach X86FastISel to fold constant offsets and scaled indices in
the same address.

Modified:
    llvm/trunk/lib/Target/X86/X86FastISel.cpp
    llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll

Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=107373&r1=107372&r2=107373&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Wed Jun 30 21:27:15 2010
@@ -423,20 +423,29 @@
         Disp += SL->getElementOffset(Idx);
       } else {
         uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
-        if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
-          // Constant-offset addressing.
-          Disp += CI->getSExtValue() * S;
-        } else if (IndexReg == 0 &&
-                   (!AM.GV || !Subtarget->isPICStyleRIPRel()) &&
-                   (S == 1 || S == 2 || S == 4 || S == 8)) {
-          // Scaled-index addressing.
-          Scale = S;
-          IndexReg = getRegForGEPIndex(Op).first;
-          if (IndexReg == 0)
-            return false;
-        } else
-          // Unsupported.
-          goto unsupported_gep;
+        SmallVector<const Value *, 4> Worklist;
+        Worklist.push_back(Op);
+        do {
+          Op = Worklist.pop_back_val();
+          if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
+            // Constant-offset addressing.
+            Disp += CI->getSExtValue() * S;
+          } else if (IndexReg == 0 &&
+                     (!AM.GV || !Subtarget->isPICStyleRIPRel()) &&
+                     (S == 1 || S == 2 || S == 4 || S == 8)) {
+            // Scaled-index addressing.
+            Scale = S;
+            IndexReg = getRegForGEPIndex(Op).first;
+            if (IndexReg == 0)
+              return false;
+          } else if (const AddOperator *Add = dyn_cast<AddOperator>(Op)) {
+            // An add. Try to fold both operands.
+            Worklist.push_back(Add->getOperand(0));
+            Worklist.push_back(Add->getOperand(1));
+          } else
+            // Unsupported.
+            goto unsupported_gep;
+        } while (!Worklist.empty());
       }
     }
     // Check for displacement overflow.

Modified: llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll?rev=107373&r1=107372&r2=107373&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll Wed Jun 30 21:27:15 2010
@@ -51,3 +51,22 @@
 ; X64:  	ret
 
 }
+
+define double @test4(i64 %x, double* %p) nounwind {
+entry:
+  %x.addr = alloca i64, align 8                   ; <i64*> [#uses=2]
+  %p.addr = alloca double*, align 8               ; <double**> [#uses=2]
+  store i64 %x, i64* %x.addr
+  store double* %p, double** %p.addr
+  %tmp = load i64* %x.addr                        ; <i64> [#uses=1]
+  %add = add nsw i64 %tmp, 16                     ; <i64> [#uses=1]
+  %tmp1 = load double** %p.addr                   ; <double*> [#uses=1]
+  %arrayidx = getelementptr inbounds double* %tmp1, i64 %add ; <double*> [#uses=1]
+  %tmp2 = load double* %arrayidx                  ; <double> [#uses=1]
+  ret double %tmp2
+
+; X32: test4:
+; X32: 128(%e{{.*}},%e{{.*}},8)
+; X64: test4:
+; X64: 128(%r{{.*}},%r{{.*}},8)
+}




From bruno.cardoso at gmail.com  Wed Jun 30 21:33:39 2010
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Thu, 01 Jul 2010 02:33:39 -0000
Subject: [llvm-commits] [llvm] r107375 - in /llvm/trunk:
 lib/Target/X86/X86InstrSSE.td test/MC/AsmParser/X86/x86_32-encoding.s
 test/MC/AsmParser/X86/x86_64-encoding.s
Message-ID: <20100701023339.A118B2A6C12C@llvm.org>

Author: bruno
Date: Wed Jun 30 21:33:39 2010
New Revision: 107375

URL: http://llvm.org/viewvc/llvm-project?rev=107375&view=rev
Log:
Add AVX SSE3 replicate and convert instructions

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
    llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=107375&r1=107374&r2=107375&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Jun 30 21:33:39 2010
@@ -3161,10 +3161,18 @@
                          [(set VR128:$dst, (v4i32 immAllOnesV))]>;
 
 //===---------------------------------------------------------------------===//
-// SSE3 Instructions
+// SSE3 - Conversion Instructions
 //===---------------------------------------------------------------------===//
 
-// Conversion Instructions
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE3] in {
+def VCVTPD2DQrr  : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
+                       "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
+def VCVTDQ2PDrm  : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
+                       "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
+def VCVTDQ2PDrr  : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
+                       "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
+}
+
 def CVTPD2DQrm  : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
                        "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
 def CVTPD2DQrr  : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
@@ -3174,33 +3182,44 @@
 def CVTDQ2PDrr  : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
                        "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
 
-// Move Instructions
-def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
-                      "movshdup\t{$src, $dst|$dst, $src}",
-                      [(set VR128:$dst, (v4f32 (movshdup
-                                                VR128:$src, (undef))))]>;
-def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
-                      "movshdup\t{$src, $dst|$dst, $src}",
-                      [(set VR128:$dst, (movshdup
-                                         (memopv4f32 addr:$src), (undef)))]>;
+//===---------------------------------------------------------------------===//
+// SSE3 - Move Instructions
+//===---------------------------------------------------------------------===//
 
-def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
-                      "movsldup\t{$src, $dst|$dst, $src}",
-                      [(set VR128:$dst, (v4f32 (movsldup
+// Replicate Single FP
+multiclass sse3_replicate_sfp<bits<8> op, PatFrag rep_frag, string OpcodeStr> {
+def rr : S3SI<op, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
+                    !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
+                      [(set VR128:$dst, (v4f32 (rep_frag
                                                 VR128:$src, (undef))))]>;
-def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
-                      "movsldup\t{$src, $dst|$dst, $src}",
-                      [(set VR128:$dst, (movsldup
+def rm : S3SI<op, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
+                    !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
+                      [(set VR128:$dst, (rep_frag
                                          (memopv4f32 addr:$src), (undef)))]>;
+}
 
-def MOVDDUPrr  : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
-                      "movddup\t{$src, $dst|$dst, $src}",
-                      [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
-def MOVDDUPrm  : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
-                      "movddup\t{$src, $dst|$dst, $src}",
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE3] in {
+defm VMOVSHDUP : sse3_replicate_sfp<0x16, movshdup, "vmovshdup">, VEX;
+defm VMOVSLDUP : sse3_replicate_sfp<0x12, movsldup, "vmovsldup">, VEX;
+}
+defm MOVSHDUP : sse3_replicate_sfp<0x16, movshdup, "movshdup">;
+defm MOVSLDUP : sse3_replicate_sfp<0x12, movsldup, "movsldup">;
+
+// Replicate Double FP
+multiclass sse3_replicate_dfp<string OpcodeStr> {
+def rr  : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
+                    !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
+                    [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
+def rm  : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
+                    !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
                     [(set VR128:$dst,
                       (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
                                       (undef))))]>;
+}
+
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE3] in
+  defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
+defm MOVDDUP : sse3_replicate_dfp<"movddup">;
 
 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
                    (undef)),
@@ -3217,6 +3236,10 @@
           (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
 }
 
+//===---------------------------------------------------------------------===//
+// SSE3 Instructions
+//===---------------------------------------------------------------------===//
+
 // Arithmetic
 let Constraints = "$src1 = $dst" in {
   def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s?rev=107375&r1=107374&r2=107375&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s Wed Jun 30 21:33:39 2010
@@ -11530,3 +11530,39 @@
 // CHECK: encoding: [0xc5,0xfa,0x7e,0x08]
           vmovq  (%eax), %xmm1
 
+// CHECK: vcvtpd2dq  %xmm1, %xmm2
+// CHECK: encoding: [0xc5,0xfb,0xe6,0xd1]
+          vcvtpd2dq  %xmm1, %xmm2
+
+// CHECK: vcvtdq2pd  %xmm1, %xmm2
+// CHECK: encoding: [0xc5,0xfa,0xe6,0xd1]
+          vcvtdq2pd  %xmm1, %xmm2
+
+// CHECK: vcvtdq2pd  (%eax), %xmm2
+// CHECK: encoding: [0xc5,0xfa,0xe6,0x10]
+          vcvtdq2pd  (%eax), %xmm2
+
+// CHECK: vmovshdup  %xmm1, %xmm2
+// CHECK: encoding: [0xc5,0xfa,0x16,0xd1]
+          vmovshdup  %xmm1, %xmm2
+
+// CHECK: vmovshdup  (%eax), %xmm2
+// CHECK: encoding: [0xc5,0xfa,0x16,0x10]
+          vmovshdup  (%eax), %xmm2
+
+// CHECK: vmovsldup  %xmm1, %xmm2
+// CHECK: encoding: [0xc5,0xfa,0x12,0xd1]
+          vmovsldup  %xmm1, %xmm2
+
+// CHECK: vmovsldup  (%eax), %xmm2
+// CHECK: encoding: [0xc5,0xfa,0x12,0x10]
+          vmovsldup  (%eax), %xmm2
+
+// CHECK: vmovddup  %xmm1, %xmm2
+// CHECK: encoding: [0xc5,0xfb,0x12,0xd1]
+          vmovddup  %xmm1, %xmm2
+
+// CHECK: vmovddup  (%eax), %xmm2
+// CHECK: encoding: [0xc5,0xfb,0x12,0x10]
+          vmovddup  (%eax), %xmm2
+

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s?rev=107375&r1=107374&r2=107375&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s Wed Jun 30 21:33:39 2010
@@ -1578,3 +1578,39 @@
 // CHECK: encoding: [0xc4,0x61,0xf9,0x7e,0xf0]
           vmovq  %xmm14, %rax
 
+// CHECK: vcvtpd2dq  %xmm11, %xmm12
+// CHECK: encoding: [0xc4,0x41,0x7b,0xe6,0xe3]
+          vcvtpd2dq  %xmm11, %xmm12
+
+// CHECK: vcvtdq2pd  %xmm11, %xmm12
+// CHECK: encoding: [0xc4,0x41,0x7a,0xe6,0xe3]
+          vcvtdq2pd  %xmm11, %xmm12
+
+// CHECK: vcvtdq2pd  (%rax), %xmm12
+// CHECK: encoding: [0xc5,0x7a,0xe6,0x20]
+          vcvtdq2pd  (%rax), %xmm12
+
+// CHECK: vmovshdup  %xmm11, %xmm12
+// CHECK: encoding: [0xc4,0x41,0x7a,0x16,0xe3]
+          vmovshdup  %xmm11, %xmm12
+
+// CHECK: vmovshdup  (%rax), %xmm12
+// CHECK: encoding: [0xc5,0x7a,0x16,0x20]
+          vmovshdup  (%rax), %xmm12
+
+// CHECK: vmovsldup  %xmm11, %xmm12
+// CHECK: encoding: [0xc4,0x41,0x7a,0x12,0xe3]
+          vmovsldup  %xmm11, %xmm12
+
+// CHECK: vmovsldup  (%rax), %xmm12
+// CHECK: encoding: [0xc5,0x7a,0x12,0x20]
+          vmovsldup  (%rax), %xmm12
+
+// CHECK: vmovddup  %xmm11, %xmm12
+// CHECK: encoding: [0xc4,0x41,0x7b,0x12,0xe3]
+          vmovddup  %xmm11, %xmm12
+
+// CHECK: vmovddup  (%rax), %xmm12
+// CHECK: encoding: [0xc5,0x7b,0x12,0x20]
+          vmovddup  (%rax), %xmm12
+




From gohman at apple.com  Wed Jun 30 21:58:22 2010
From: gohman at apple.com (Dan Gohman)
Date: Thu, 01 Jul 2010 02:58:22 -0000
Subject: [llvm-commits] [llvm] r107376 -
	/llvm/trunk/lib/Target/X86/X86FastISel.cpp
Message-ID: <20100701025822.2123A2A6C12C@llvm.org>

Author: djg
Date: Wed Jun 30 21:58:21 2010
New Revision: 107376

URL: http://llvm.org/viewvc/llvm-project?rev=107376&view=rev
Log:
Fix X86FastISel's add folding to actually work, and not fall back
to SelectionDAG.

Modified:
    llvm/trunk/lib/Target/X86/X86FastISel.cpp

Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=107376&r1=107375&r2=107376&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Wed Jun 30 21:58:21 2010
@@ -430,6 +430,14 @@
           if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
             // Constant-offset addressing.
             Disp += CI->getSExtValue() * S;
+          } else if (isa<AddOperator>(Op) &&
+                     isa<ConstantInt>(cast<AddOperator>(Op)->getOperand(1))) {
+            // An add with a constant operand. Fold the constant.
+            ConstantInt *CI =
+              cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
+            Disp += CI->getSExtValue() * S;
+            // Add the other operand back to the work list.
+            Worklist.push_back(cast<AddOperator>(Op)->getOperand(0));
           } else if (IndexReg == 0 &&
                      (!AM.GV || !Subtarget->isPICStyleRIPRel()) &&
                      (S == 1 || S == 2 || S == 4 || S == 8)) {
@@ -438,10 +446,6 @@
             IndexReg = getRegForGEPIndex(Op).first;
             if (IndexReg == 0)
               return false;
-          } else if (const AddOperator *Add = dyn_cast<AddOperator>(Op)) {
-            // An add. Try to fold both operands.
-            Worklist.push_back(Add->getOperand(0));
-            Worklist.push_back(Add->getOperand(1));
           } else
             // Unsupported.
             goto unsupported_gep;




From gohman at apple.com  Wed Jun 30 21:58:57 2010
From: gohman at apple.com (Dan Gohman)
Date: Thu, 01 Jul 2010 02:58:57 -0000
Subject: [llvm-commits] [llvm] r107377 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/FastISel.cpp
 lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
 lib/Target/X86/X86FastISel.cpp test/CodeGen/X86/fast-isel-shift-imm.ll
Message-ID: <20100701025857.A3A102A6C12C@llvm.org>

Author: djg
Date: Wed Jun 30 21:58:57 2010
New Revision: 107377

URL: http://llvm.org/viewvc/llvm-project?rev=107377&view=rev
Log:
Enable on-demand fast-isel.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
    llvm/trunk/lib/Target/X86/X86FastISel.cpp
    llvm/trunk/test/CodeGen/X86/fast-isel-shift-imm.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=107377&r1=107376&r2=107377&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Wed Jun 30 21:58:57 2010
@@ -161,7 +161,10 @@
       }
     }
   } else if (const Operator *Op = dyn_cast<Operator>(V)) {
-    if (!SelectOperator(Op, Op->getOpcode())) return 0;
+    if (!SelectOperator(Op, Op->getOpcode()))
+      if (!isa<Instruction>(Op) ||
+          !TargetSelectInstruction(cast<Instruction>(Op)))
+        return 0;
     Reg = lookUpRegForValue(Op);
   } else if (isa<UndefValue>(V)) {
     Reg = createResultReg(TLI.getRegClassFor(VT));

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=107377&r1=107376&r2=107377&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Jun 30 21:58:57 2010
@@ -709,6 +709,12 @@
       FastIS->startNewBlock(BB);
       // Do FastISel on as many instructions as possible.
       for (; BI != End; ++BI) {
+        // Defer instructions with no side effects; they'll be emitted
+        // on-demand later.
+        if (BI->isSafeToSpeculativelyExecute() &&
+            !FuncInfo->ValueMap.count(BI))
+          continue;
+
         // Try to select the instruction with FastISel.
         if (FastIS->SelectInstruction(BI))
           continue;

Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=107377&r1=107376&r2=107377&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Wed Jun 30 21:58:57 2010
@@ -935,7 +935,7 @@
       if (CI->getIntrinsicID() == Intrinsic::sadd_with_overflow ||
           CI->getIntrinsicID() == Intrinsic::uadd_with_overflow) {
         const MachineInstr *SetMI = 0;
-        unsigned Reg = lookUpRegForValue(EI);
+        unsigned Reg = getRegForValue(EI);
 
         for (MachineBasicBlock::const_reverse_iterator
                RI = MBB->rbegin(), RE = MBB->rend(); RI != RE; ++RI) {

Modified: llvm/trunk/test/CodeGen/X86/fast-isel-shift-imm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-shift-imm.ll?rev=107377&r1=107376&r2=107377&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fast-isel-shift-imm.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fast-isel-shift-imm.ll Wed Jun 30 21:58:57 2010
@@ -1,7 +1,8 @@
 ; RUN: llc < %s -march=x86 -O0 | grep {sarl	\$80, %eax}
 ; PR3242
 
-define i32 @foo(i32 %x) nounwind {
+define void @foo(i32 %x, i32* %p) nounwind {
   %y = ashr i32 %x, 50000
-  ret i32 %y
+  store i32 %y, i32* %p
+  ret void
 }




From gohman at apple.com  Wed Jun 30 22:49:38 2010
From: gohman at apple.com (Dan Gohman)
Date: Thu, 01 Jul 2010 03:49:38 -0000
Subject: [llvm-commits] [llvm] r107380 - in /llvm/trunk:
 include/llvm/CodeGen/FastISel.h lib/CodeGen/SelectionDAG/FastISel.cpp
 test/CodeGen/X86/fast-isel-loads.ll
Message-ID: <20100701034938.C09D62A6C12C@llvm.org>

Author: djg
Date: Wed Jun 30 22:49:38 2010
New Revision: 107380

URL: http://llvm.org/viewvc/llvm-project?rev=107380&view=rev
Log:
Teach fast-isel to avoid loading a value from memory when it's already
available in a register. This is pretty primitive, but it reduces the
number of instructions in common testcases by 4%.

Added:
    llvm/trunk/test/CodeGen/X86/fast-isel-loads.ll
Modified:
    llvm/trunk/include/llvm/CodeGen/FastISel.h
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp

Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FastISel.h?rev=107380&r1=107379&r2=107380&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/FastISel.h (original)
+++ llvm/trunk/include/llvm/CodeGen/FastISel.h Wed Jun 30 22:49:38 2010
@@ -307,6 +307,8 @@
   }
 
 private:
+  bool SelectLoad(const User *I);
+
   bool SelectBinaryOp(const User *I, unsigned ISDOpcode);
 
   bool SelectFNeg(const User *I);

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=107380&r1=107379&r2=107380&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Wed Jun 30 22:49:38 2010
@@ -48,6 +48,7 @@
 #include "llvm/CodeGen/MachineModuleInfo.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/Analysis/DebugInfo.h"
+#include "llvm/Analysis/Loads.h"
 #include "llvm/Target/TargetData.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetLowering.h"
@@ -716,8 +717,31 @@
 }
 
 bool
+FastISel::SelectLoad(const User *I) {
+  LoadInst *LI = const_cast<LoadInst *>(cast<LoadInst>(I));
+
+  // For a load from an alloca, make a limited effort to find the value
+  // already available in a register, avoiding redundant loads.
+  if (!LI->isVolatile() && isa<AllocaInst>(LI->getPointerOperand())) {
+    BasicBlock::iterator ScanFrom = LI;
+    if (const Value *V = FindAvailableLoadedValue(LI->getPointerOperand(),
+                                                  LI->getParent(), ScanFrom)) {
+      unsigned ResultReg = getRegForValue(V);
+      if (ResultReg != 0) {
+        UpdateValueMap(I, ResultReg);
+        return true;
+      }
+    }
+  }
+
+  return false;
+}
+
+bool
 FastISel::SelectOperator(const User *I, unsigned Opcode) {
   switch (Opcode) {
+  case Instruction::Load:
+    return SelectLoad(I);
   case Instruction::Add:
     return SelectBinaryOp(I, ISD::ADD);
   case Instruction::FAdd:

Added: llvm/trunk/test/CodeGen/X86/fast-isel-loads.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-loads.ll?rev=107380&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fast-isel-loads.ll (added)
+++ llvm/trunk/test/CodeGen/X86/fast-isel-loads.ll Wed Jun 30 22:49:38 2010
@@ -0,0 +1,23 @@
+; RUN: llc -march=x86-64 -O0 -asm-verbose=false < %s | FileCheck %s
+
+; Fast-isel shouldn't reload the argument values from the stack.
+
+; CHECK: foo:
+; CHECK-NEXT: movq  %rdi, -8(%rsp)
+; CHECK-NEXT: movq  %rsi, -16(%rsp)
+; CHECK-NEXT: movsd 128(%rsi,%rdi,8), %xmm0
+; CHECK-NEXT: ret
+
+define double @foo(i64 %x, double* %p) nounwind {
+entry:
+  %x.addr = alloca i64, align 8                   ; <i64*> [#uses=2]
+  %p.addr = alloca double*, align 8               ; <double**> [#uses=2]
+  store i64 %x, i64* %x.addr
+  store double* %p, double** %p.addr
+  %tmp = load i64* %x.addr                        ; <i64> [#uses=1]
+  %tmp1 = load double** %p.addr                   ; <double*> [#uses=1]
+  %add = add nsw i64 %tmp, 16                     ; <i64> [#uses=1]
+  %arrayidx = getelementptr inbounds double* %tmp1, i64 %add ; <double*> [#uses=1]
+  %tmp2 = load double* %arrayidx                  ; <double> [#uses=1]
+  ret double %tmp2
+}




From gohman at apple.com  Wed Jun 30 22:49:59 2010
From: gohman at apple.com (Dan Gohman)
Date: Thu, 01 Jul 2010 03:49:59 -0000
Subject: [llvm-commits] [llvm] r107381 -
	/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
Message-ID: <20100701034959.9F6F02A6C12C@llvm.org>

Author: djg
Date: Wed Jun 30 22:49:59 2010
New Revision: 107381

URL: http://llvm.org/viewvc/llvm-project?rev=107381&view=rev
Log:
Fast isel no longer needs DeadMachineInstrElim to clean up after it.

Modified:
    llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp

Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=107381&r1=107380&r2=107381&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original)
+++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Wed Jun 30 22:49:59 2010
@@ -329,19 +329,15 @@
   if (OptLevel != CodeGenOpt::None)
     PM.add(createOptimizePHIsPass());
 
-  // Delete dead machine instructions regardless of optimization level.
-  //
-  // At -O0, fast-isel frequently creates dead instructions.
-  //
-  // With optimization, dead code should already be eliminated. However
-  // there is one known exception: lowered code for arguments that are only
-  // used by tail calls, where the tail calls reuse the incoming stack
-  // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
-  PM.add(createDeadMachineInstructionElimPass());
-  printAndVerify(PM, "After codegen DCE pass",
-                 /* allowDoubleDefs= */ true);
-
   if (OptLevel != CodeGenOpt::None) {
+    // With optimization, dead code should already be eliminated. However
+    // there is one known exception: lowered code for arguments that are only
+    // used by tail calls, where the tail calls reuse the incoming stack
+    // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
+    PM.add(createDeadMachineInstructionElimPass());
+    printAndVerify(PM, "After codegen DCE pass",
+                   /* allowDoubleDefs= */ true);
+
     PM.add(createOptimizeExtsPass());
     if (!DisableMachineLICM)
       PM.add(createMachineLICMPass());




From gohman at apple.com  Wed Jun 30 22:55:40 2010
From: gohman at apple.com (Dan Gohman)
Date: Thu, 01 Jul 2010 03:55:40 -0000
Subject: [llvm-commits] [llvm] r107383 - in
 /llvm/trunk/lib/CodeGen/SelectionDAG: FastISel.cpp FunctionLoweringInfo.cpp
 FunctionLoweringInfo.h SelectionDAGBuilder.cpp SelectionDAGISel.cpp
Message-ID: <20100701035540.38D5F2A6C12C@llvm.org>

Author: djg
Date: Wed Jun 30 22:55:39 2010
New Revision: 107383

URL: http://llvm.org/viewvc/llvm-project?rev=107383&view=rev
Log:
Rename CreateRegForValue to CreateReg, and change its argument
from a Value to a Type, because it doesn't actually care about
the Value.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.h
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=107383&r1=107382&r2=107383&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Wed Jun 30 22:55:39 2010
@@ -1211,7 +1211,7 @@
       // by bailing out early, we may leave behind some dead instructions,
       // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
       // own moves. Second, this check is necessary becuase FastISel doesn't
-      // use CreateRegForValue to create registers, so it always creates
+      // use CreateReg to create registers, so it always creates
       // exactly one register for each non-void instruction.
       EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
       if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp?rev=107383&r1=107382&r2=107383&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp Wed Jun 30 22:55:39 2010
@@ -176,23 +176,23 @@
   return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
 }
 
-/// CreateRegForValue - Allocate the appropriate number of virtual registers of
+/// CreateReg - Allocate the appropriate number of virtual registers of
 /// the correctly promoted or expanded types.  Assign these registers
 /// consecutive vreg numbers and return the first assigned number.
 ///
 /// In the case that the given value has struct or array type, this function
 /// will assign registers for each member or element.
 ///
-unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
+unsigned FunctionLoweringInfo::CreateReg(const Type *Ty) {
   SmallVector<EVT, 4> ValueVTs;
-  ComputeValueVTs(TLI, V->getType(), ValueVTs);
+  ComputeValueVTs(TLI, Ty, ValueVTs);
 
   unsigned FirstReg = 0;
   for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
     EVT ValueVT = ValueVTs[Value];
-    EVT RegisterVT = TLI.getRegisterType(V->getContext(), ValueVT);
+    EVT RegisterVT = TLI.getRegisterType(Ty->getContext(), ValueVT);
 
-    unsigned NumRegs = TLI.getNumRegisters(V->getContext(), ValueVT);
+    unsigned NumRegs = TLI.getNumRegisters(Ty->getContext(), ValueVT);
     for (unsigned i = 0; i != NumRegs; ++i) {
       unsigned R = MakeReg(RegisterVT);
       if (!FirstReg) FirstReg = R;

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.h?rev=107383&r1=107382&r2=107383&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.h (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.h Wed Jun 30 22:55:39 2010
@@ -121,12 +121,12 @@
     return ValueMap.count(V);
   }
 
-  unsigned CreateRegForValue(const Value *V);
+  unsigned CreateReg(const Type *Ty);
   
   unsigned InitializeRegForValue(const Value *V) {
     unsigned &R = ValueMap[V];
     assert(R == 0 && "Already initialized this value register!");
-    return R = CreateRegForValue(V);
+    return R = CreateReg(V->getType());
   }
 };
 

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=107383&r1=107382&r2=107383&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Wed Jun 30 22:55:39 2010
@@ -6164,7 +6164,7 @@
       if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
         unsigned &RegOut = ConstantsOut[C];
         if (RegOut == 0) {
-          RegOut = FuncInfo.CreateRegForValue(C);
+          RegOut = FuncInfo.CreateReg(C->getType());
           CopyValueToVirtualRegister(C, RegOut);
         }
         Reg = RegOut;
@@ -6177,7 +6177,7 @@
           assert(isa<AllocaInst>(PHIOp) &&
                  FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
                  "Didn't codegen value into a register!??");
-          Reg = FuncInfo.CreateRegForValue(PHIOp);
+          Reg = FuncInfo.CreateReg(PHIOp->getType());
           CopyValueToVirtualRegister(PHIOp, Reg);
         }
       }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=107383&r1=107382&r2=107383&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Jun 30 22:55:39 2010
@@ -730,7 +730,7 @@
           if (!BI->getType()->isVoidTy() && !BI->use_empty()) {
             unsigned &R = FuncInfo->ValueMap[BI];
             if (!R)
-              R = FuncInfo->CreateRegForValue(BI);
+              R = FuncInfo->CreateReg(BI->getType());
           }
 
           bool HadTailCall = false;




From gohman at apple.com  Wed Jun 30 22:57:05 2010
From: gohman at apple.com (Dan Gohman)
Date: Thu, 01 Jul 2010 03:57:05 -0000
Subject: [llvm-commits] [llvm] r107384 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Message-ID: <20100701035705.DE8BD2A6C12C@llvm.org>

Author: djg
Date: Wed Jun 30 22:57:05 2010
New Revision: 107384

URL: http://llvm.org/viewvc/llvm-project?rev=107384&view=rev
Log:
Use FuncInfo's isExportedInst accessor method instead of
doing the work manually.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=107384&r1=107383&r2=107384&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Jun 30 22:57:05 2010
@@ -712,7 +712,7 @@
         // Defer instructions with no side effects; they'll be emitted
         // on-demand later.
         if (BI->isSafeToSpeculativelyExecute() &&
-            !FuncInfo->ValueMap.count(BI))
+            !FuncInfo->isExportedInst(BI))
           continue;
 
         // Try to select the instruction with FastISel.




From clattner at apple.com  Wed Jun 30 23:03:43 2010
From: clattner at apple.com (Chris Lattner)
Date: Wed, 30 Jun 2010 21:03:43 -0700
Subject: [llvm-commits] [llvm] r107205 -
	in	/llvm/trunk:	bindings/ada/llvm/ docs/
	include/llvm-c/	include/llvm/	include/llvm/CodeGen/
	include/llvm/MC/ include/llvm/Target/	lib/AsmParser/
	lib/Bitcode/Reader/	lib/Bitcode/Writer/ lib/CodeGen/
	lib/CodeGen/AsmPrinter/	lib/Linker/ lib/MC/	lib/Target/
	lib/Target/CppBackend/	lib/Target/XCore/AsmPrinter/	lib/Transforms/IPO/
	lib/VMCore/	tools/llvm-nm/
In-Reply-To: <B5AAFD97-0164-48AD-BC09-7137D8A0E205@apple.com>
References: <20100629212400.DABF32A6C12C@llvm.org>
	<C7E3E4A7-A598-4C61-9513-2DFC7C2EC4CC@apple.com>
	<AF811FB0-E72D-44DD-8BBD-1C6D4971F1AF@gmail.com>
	<FA99D48A-0561-420D-AA6C-6983AB1AFEC9@apple.com>
	<7805A44F-4DAD-467F-B254-E1AB184FD2EB@gmail.com>
	<B5AAFD97-0164-48AD-BC09-7137D8A0E205@apple.com>
Message-ID: <D50B4716-517B-4A09-8039-B324E97BCB17@apple.com>

>>>> I'll check to see if it's used. If it's not used, then it's relying upon the hack down below, which is bad. However, I much prefer having the prefix string in one place than relying upon it being buried in some deep part of the asm printer.
>>> 
>>> I don't really understand what you mean.
>>> 
>> I want to separate it out from the "linker_private" linkage. In particular, I don't want to say that it will always have the same prefix as linker_private. That's the case with Darwin, but I don't see why that has to be the case for every linker that would want to implement it.
>> 
> Or for every target for that matter. Otherwise, these linkages are restricted to a small subset of usages -- Objective-C metadata on Darwin.

This feature is only supported on one OS (darwin) and all of the targets (arm/ppc/x86) use the same prefix.  I don't see any reason to hookize something that is constant across all supported targets.

-Chris


From clattner at apple.com  Wed Jun 30 23:04:40 2010
From: clattner at apple.com (Chris Lattner)
Date: Wed, 30 Jun 2010 21:04:40 -0700
Subject: [llvm-commits] [llvm] r107205 -
	in	/llvm/trunk:	bindings/ada/llvm/ docs/
	include/llvm-c/	include/llvm/	include/llvm/CodeGen/
	include/llvm/MC/ include/llvm/Target/	lib/AsmParser/
	lib/Bitcode/Reader/	lib/Bitcode/Writer/ lib/CodeGen/
	lib/CodeGen/AsmPrinter/	lib/Linker/ lib/MC/	lib/Target/
	lib/Target/CppBackend/	lib/Target/XCore/AsmPrinter/	lib/Transforms/IPO/
	lib/VMCore/	tools/llvm-nm/
In-Reply-To: <9E57AC43-C5F3-418C-8159-F3AF703BA3F1@apple.com>
References: <20100629212400.DABF32A6C12C@llvm.org>
	<C7E3E4A7-A598-4C61-9513-2DFC7C2EC4CC@apple.com>
	<AF811FB0-E72D-44DD-8BBD-1C6D4971F1AF@gmail.com>
	<FA99D48A-0561-420D-AA6C-6983AB1AFEC9@apple.com>
	<9E57AC43-C5F3-418C-8159-F3AF703BA3F1@apple.com>
Message-ID: <E134F460-3DAE-41B5-A606-F0C56186DE07@apple.com>


On Jun 30, 2010, at 11:36 AM, Dan Gohman wrote:

> 
> On Jun 30, 2010, at 8:24 AM, Chris Lattner wrote:
> 
>> 
>> On Jun 29, 2010, at 3:33 PM, Bill Wendling wrote:
>> 
>>> On Jun 29, 2010, at 2:56 PM, Chris Lattner wrote:
>>> 
>>>> On Jun 29, 2010, at 2:24 PM, Bill Wendling wrote:
>>>> 
>>>>> Author: void
>>>>> Date: Tue Jun 29 16:24:00 2010
>>>>> New Revision: 107205
>>>>> 
>>>>> URL: http://llvm.org/viewvc/llvm-project?rev=107205&view=rev
>>>>> Log:
>>>>> Introducing the "linker_weak" linkage type. This will be used for Objective-C
>>>>> metadata types which should be marked as "weak", but which the linker will
>>>>> remove upon final linkage.
>>>> 
>>>> Hi Bill,
>>>> 
>>>> This would have been good to talk about before you implemented it.  The name linker_weak doesn't seem very descriptive.  How about linker_private_weak or something like that?
>>>> 
>>> I thought about that, but they aren't private from what I can tell. They're marked as ".globl" and ".weak_definition".
>> 
>> They are "as private" as other "l" labels, right?  Those are visible across translation units too.  We call it "linker private" so calling this "linker_private_weak" seems reasonable.  Any other suggestions?
> 
> How about "objc_linker_private_weak"?

No, it's not objc specific, objc metadata just happens to use it.

> Unless someone here can really spell out what these things really
> mean, without mentioning assembler directives, without mentioning
> special label naming conventions, without describing it in terms of
> what gcc does for Objective C, and without citing "this is what the
> Objective C people say we need", and without excluding any magical
> semantics, it would be best to avoid confusion.

This is easy to do, Bill just needs to do it.  I completely agree that it is imperative that this happen!

-Chris


From clattner at apple.com  Wed Jun 30 23:06:02 2010
From: clattner at apple.com (Chris Lattner)
Date: Wed, 30 Jun 2010 21:06:02 -0700
Subject: [llvm-commits] [llvm] r107205 -
	in	/llvm/trunk:	bindings/ada/llvm/ docs/
	include/llvm-c/	include/llvm/	include/llvm/CodeGen/
	include/llvm/MC/ include/llvm/Target/	lib/AsmParser/
	lib/Bitcode/Reader/	lib/Bitcode/Writer/ lib/CodeGen/
	lib/CodeGen/AsmPrinter/	lib/Linker/ lib/MC/	lib/Target/
	lib/Target/CppBackend/	lib/Target/XCore/AsmPrinter/	lib/Transforms/IPO/
	lib/VMCore/	tools/llvm-nm/
In-Reply-To: <79223963-640D-43E4-BB73-0D3D9DD729D6@gmail.com>
References: <20100629212400.DABF32A6C12C@llvm.org>
	<C7E3E4A7-A598-4C61-9513-2DFC7C2EC4CC@apple.com>
	<AF811FB0-E72D-44DD-8BBD-1C6D4971F1AF@gmail.com>
	<FA99D48A-0561-420D-AA6C-6983AB1AFEC9@apple.com>
	<9E57AC43-C5F3-418C-8159-F3AF703BA3F1@apple.com>
	<79223963-640D-43E4-BB73-0D3D9DD729D6@gmail.com>
Message-ID: <CBE117B2-2498-4A1D-8967-0DC60214B58C@apple.com>


On Jun 30, 2010, at 11:47 AM, Bill Wendling wrote:

>> 
>> Unless someone here can really spell out what these things really
>> mean, without mentioning assembler directives, without mentioning
>> special label naming conventions, without describing it in terms of
>> what gcc does for Objective C, and without citing "this is what the
>> Objective C people say we need", and without excluding any magical
>> semantics, it would be best to avoid confusion.
>> 
> I view these linkages as being like their non-"linker linkage" counterparts, but that the linker will remove them from the final linked image. So, "linker_private" is "private" but the linker will remove it from the final linked image and so on. "linker_private_weak" has no non-"linker linkage" counterpart, but its semantics are a natural progression maybe?

The semantics are clear to me: "lfoo" labels are stripped by the linker, but cause multiple definition cause redefinition errors.  "weak lfoo" labels are stripped by the linker, but multiple definitions get merged.  This doesn't seem that complicated.

-Chris


From clattner at apple.com  Wed Jun 30 23:07:38 2010
From: clattner at apple.com (Chris Lattner)
Date: Wed, 30 Jun 2010 21:07:38 -0700
Subject: [llvm-commits] [compiler-rt][patch] add soft-float comparisons
	to compiler-rt
In-Reply-To: <DBC5C16E-E952-4CD2-BFD9-7B96277A189A@apple.com>
References: <DBC5C16E-E952-4CD2-BFD9-7B96277A189A@apple.com>
Message-ID: <8589FA98-3EBF-48B0-B426-6DBC150D963B@apple.com>

Looks great to me, please commit!

-Chris

On Jun 30, 2010, at 12:17 PM, Stephen Canon wrote:

> This patch provides the following routines for compiler-rt:
> 
> __eqdf2   __gedf2   __nedf2  __ledf2   __gtdf2  __ltdf2  __unorddf2
> __eqsf2   __gesf2   __nesf2  __lesf2   __gtsf2  __ltsf2  __unordsf2
> 
> These are present in libgcc when it is built for platforms that lack hardware floating-point support.
> 
> - Steve
> 
> <comparisons.diff>_______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits




From clattner at apple.com  Wed Jun 30 23:08:16 2010
From: clattner at apple.com (Chris Lattner)
Date: Wed, 30 Jun 2010 21:08:16 -0700
Subject: [llvm-commits] [compiler-rt][patch] add soft-float addition and
	subtraction to compiler-rt
In-Reply-To: <539F1216-67CD-43D5-AB05-52709CF7BF90@apple.com>
References: <539F1216-67CD-43D5-AB05-52709CF7BF90@apple.com>
Message-ID: <74592F2C-E4C4-4DB4-8502-94D08C14AEAD@apple.com>


On Jun 30, 2010, at 12:24 PM, Stephen Canon wrote:

> This patch provides single- and double-precision soft-float addition and subtraction routines for compiler-rt:
> 
> __adddf3  __subdf3
> __addsf3  __subsf3

Looks good to me.  Please feel free to commit directly to compiler_rt if you've tested the new code, thanks Steve!

-Chris


From clattner at apple.com  Wed Jun 30 23:09:32 2010
From: clattner at apple.com (Chris Lattner)
Date: Wed, 30 Jun 2010 21:09:32 -0700
Subject: [llvm-commits] [PATCH (need approval)] Add support for
	InsertValue	and ExtractValue to gep_type_iterator
In-Reply-To: <1277926785-28322-1-git-send-email-peter@pcc.me.uk>
References: <1277926785-28322-1-git-send-email-peter@pcc.me.uk>
Message-ID: <F9C9FA6D-7517-46FC-A41F-57282FB2551A@apple.com>

On Jun 30, 2010, at 12:39 PM, Peter Collingbourne wrote:

> ---
> Hi,
> 
> This adds iv_type_iterator, ev_type_iterator and vce_type_iterator
> to complement gep_type_iterator.
> 
> I'm not 100% certain this is the right way to do this.  Perhaps we
> should introduce an Operator for generically accessing the index
> iterators for {Insert,Extract}Values.  This would work right now
> because all the iterators are of underlying type const unsigned *
> but of course this may change in the future.

Hi Peter,

What problem are you trying to solve here?

-Chris

> 
> Thanks,
> Peter
> 
> include/llvm/Support/GetElementPtrTypeIterator.h |   38 ++++++++++++++++++++-
> 1 files changed, 36 insertions(+), 2 deletions(-)
> 
> diff --git a/include/llvm/Support/GetElementPtrTypeIterator.h b/include/llvm/Support/GetElementPtrTypeIterator.h
> index e5e7fc7..35046fe 100644
> --- a/include/llvm/Support/GetElementPtrTypeIterator.h
> +++ b/include/llvm/Support/GetElementPtrTypeIterator.h
> @@ -8,7 +8,7 @@
> //===----------------------------------------------------------------------===//
> //
> // This file implements an iterator for walking through the types indexed by
> -// getelementptr instructions.
> +// getelementptr, insertvalue and extractvalue instructions.
> //
> //===----------------------------------------------------------------------===//
> 
> @@ -17,6 +17,7 @@
> 
> #include "llvm/User.h"
> #include "llvm/DerivedTypes.h"
> +#include "llvm/Instructions.h"
> 
> namespace llvm {
>   template<typename ItTy = User::const_op_iterator>
> @@ -28,6 +29,12 @@ namespace llvm {
>     ItTy OpIt;
>     const Type *CurTy;
>     generic_gep_type_iterator() {}
> +
> +    Value *asValue(Value *V) const { return V; }
> +    Value *asValue(unsigned U) const {
> +      return ConstantInt::get(CurTy->getContext(), APInt(32, U));
> +    }
> +
>   public:
> 
>     static generic_gep_type_iterator begin(const Type *Ty, ItTy It) {
> @@ -63,7 +70,7 @@ namespace llvm {
>     // current type directly.
>     const Type *operator->() const { return operator*(); }
> 
> -    Value *getOperand() const { return *OpIt; }
> +    Value *getOperand() const { return asValue(*OpIt); }
> 
>     generic_gep_type_iterator& operator++() {   // Preincrement
>       if (const CompositeType *CT = dyn_cast<CompositeType>(CurTy)) {
> @@ -81,6 +88,9 @@ namespace llvm {
>   };
> 
>   typedef generic_gep_type_iterator<> gep_type_iterator;
> +  typedef generic_gep_type_iterator<ExtractValueInst::idx_iterator> ev_type_iterator;
> +  typedef generic_gep_type_iterator<InsertValueInst::idx_iterator> iv_type_iterator;
> +  typedef generic_gep_type_iterator<SmallVector<unsigned, 4>::const_iterator> vce_type_iterator;
> 
>   inline gep_type_iterator gep_type_begin(const User *GEP) {
>     return gep_type_iterator::begin(GEP->getOperand(0)->getType(),
> @@ -97,6 +107,30 @@ namespace llvm {
>     return gep_type_iterator::end(GEP.op_end());
>   }
> 
> +  inline ev_type_iterator ev_type_begin(const ExtractValueInst *EV) {
> +    return ev_type_iterator::begin(EV->getOperand(0)->getType(),
> +                                   EV->idx_begin());
> +  }
> +  inline ev_type_iterator ev_type_end(const ExtractValueInst *EV) {
> +    return ev_type_iterator::end(EV->idx_end());
> +  }
> +
> +  inline iv_type_iterator iv_type_begin(const InsertValueInst *IV) {
> +    return iv_type_iterator::begin(IV->getType(),
> +                                   IV->idx_begin());
> +  }
> +  inline iv_type_iterator iv_type_end(const InsertValueInst *IV) {
> +    return iv_type_iterator::end(IV->idx_end());
> +  }
> +
> +  inline vce_type_iterator vce_type_begin(const ConstantExpr *CE) {
> +    return vce_type_iterator::begin(CE->getOperand(0)->getType(),
> +                                    CE->getIndices().begin());
> +  }
> +  inline vce_type_iterator vce_type_end(const ConstantExpr *CE) {
> +    return vce_type_iterator::end(CE->getIndices().end());
> +  }
> +
>   template<typename ItTy>
>   inline generic_gep_type_iterator<ItTy>
>   gep_type_begin(const Type *Op0, ItTy I, ItTy E) {
> -- 
> 1.6.5
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits




From clattner at apple.com  Wed Jun 30 23:12:10 2010
From: clattner at apple.com (Chris Lattner)
Date: Wed, 30 Jun 2010 21:12:10 -0700
Subject: [llvm-commits] [PATCH] add X86_64 relocation entries
In-Reply-To: <4dfdc3f12a1a3a254f22b03f8d26a382c3424391.1277925479.git.matt@console-pimps.org>
References: <4dfdc3f12a1a3a254f22b03f8d26a382c3424391.1277925479.git.matt@console-pimps.org>
Message-ID: <5E54E91E-1A43-4913-8046-CF63EC4342E0@apple.com>


On Jun 30, 2010, at 12:22 PM, Matt Fleming wrote:

> From: Roman Divacky <rdivacky at pes.vlakno.cz>
> 
> Here's another patch that adds some ELF values, this one from Roman
> Divacky. If no one yells I'll commit this later this week.

Looks ok to me, but please stay in 80 columns and punctuate your comments (end with ".").

Thanks Matt!

-Chris

> 
> ---
> include/llvm/Support/ELF.h |   69 ++++++++++++++++++++++++++++++++++++++++++++
> 1 files changed, 69 insertions(+), 0 deletions(-)
> 
> diff --git a/include/llvm/Support/ELF.h b/include/llvm/Support/ELF.h
> index 6e863f8..3d413d5 100644
> --- a/include/llvm/Support/ELF.h
> +++ b/include/llvm/Support/ELF.h
> @@ -174,6 +174,42 @@ enum {
>   ELFOSABI_STANDALONE = 255   // Standalone (embedded) application
> };
> 
> +// X86_64 relocations
> +enum {
> +  R_X86_64_NONE       = 0,
> +  R_X86_64_64         = 1,
> +  R_X86_64_PC32       = 2,
> +  R_X86_64_GOT32      = 3,
> +  R_X86_64_PLT32      = 4,
> +  R_X86_64_COPY       = 5,
> +  R_X86_64_GLOB_DAT   = 6,
> +  R_X86_64_JUMP_SLOT  = 7,
> +  R_X86_64_RELATIVE   = 8,
> +  R_X86_64_GOTPCREL   = 9,
> +  R_X86_64_32         = 10,
> +  R_X86_64_32S        = 11,
> +  R_X86_64_16         = 12,
> +  R_X86_64_PC16       = 13,
> +  R_X86_64_8          = 14,
> +  R_X86_64_PC8        = 15,
> +  R_X86_64_DTPMOD64   = 16,
> +  R_X86_64_DTPOFF64   = 17,
> +  R_X86_64_TPOFF64    = 18,
> +  R_X86_64_TLSGD      = 19,
> +  R_X86_64_TLSLD      = 20,
> +  R_X86_64_DTPOFF32   = 21,
> +  R_X86_64_GOTTPOFF   = 22,
> +  R_X86_64_TPOFF32    = 23,
> +  R_X86_64_PC64       = 24,
> +  R_X86_64_GOTOFF64   = 25,
> +  R_X86_64_GOTPC32    = 26,
> +  R_X86_64_SIZE32     = 32,
> +  R_X86_64_SIZE64     = 33,
> +  R_X86_64_GOTPC32_TLSDESC = 34,
> +  R_X86_64_TLSDESC_CALL    = 35,
> +  R_X86_64_TLSDESC    = 36
> +};
> +
> // Section header.
> struct Elf32_Shdr {
>   Elf32_Word sh_name;      // Section name (index into string table)
> @@ -339,6 +375,39 @@ struct Elf32_Rela {
>   };
> };
> 
> +// Relocation entry, without explicit addend.
> +struct Elf64_Rel {
> +  Elf64_Addr r_offset; // Location (file byte offset, or program virtual addr)
> +  Elf64_Xword r_info;   // Symbol table index and type of relocation to apply
> +
> +  // These accessors and mutators correspond to the ELF64_R_SYM, ELF64_R_TYPE,
> +  // and ELF64_R_INFO macros defined in the ELF specification:
> +  Elf64_Xword getSymbol () const { return (r_info >> 32); }
> +  unsigned char getType () const { return (unsigned char) (r_info & 0xffffffffL); }
> +  void setSymbol (Elf32_Word s) { setSymbolAndType (s, getType ()); }
> +  void setType (unsigned char t) { setSymbolAndType (getSymbol(), t); }
> +  void setSymbolAndType (Elf64_Xword s, unsigned char t) {
> +    r_info = (s << 32) + (t&0xffffffffL);
> +  };
> +};
> +
> +// Relocation entry with explicit addend.
> +struct Elf64_Rela {
> +  Elf64_Addr  r_offset; // Location (file byte offset, or program virtual addr)
> +  Elf64_Xword  r_info;   // Symbol table index and type of relocation to apply
> +  Elf64_Sxword r_addend; // Compute value for relocatable field by adding this
> +
> +  // These accessors and mutators correspond to the ELF64_R_SYM, ELF64_R_TYPE,
> +  // and ELF64_R_INFO macros defined in the ELF specification:
> +  Elf64_Xword getSymbol () const { return (r_info >> 32); }
> +  unsigned char getType () const { return (unsigned char) (r_info & 0xffffffffL); }
> +  void setSymbol (Elf64_Xword s) { setSymbolAndType (s, getType ()); }
> +  void setType (unsigned char t) { setSymbolAndType (getSymbol(), t); }
> +  void setSymbolAndType (Elf64_Xword s, unsigned char t) {
> +    r_info = (s << 32) + (t&0xffffffffL);
> +  };
> +};
> +
> // Program header.
> struct Elf32_Phdr {
>   Elf32_Word p_type;   // Type of segment
> -- 
> 1.6.4.rc0
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits




From clattner at apple.com  Wed Jun 30 23:21:17 2010
From: clattner at apple.com (Chris Lattner)
Date: Wed, 30 Jun 2010 21:21:17 -0700
Subject: [llvm-commits] [llvm] r107109 - in /llvm/trunk:
	include/llvm/Analysis/AliasAnalysis.h	include/llvm/Analysis/Passes.h
	lib/Analysis/AliasAnalysis.cpp	lib/Analysis/BasicAliasAnalysis.cpp
	test/Analysis/BasicAA/interprocedural.ll
In-Reply-To: <5E31E70D-BC94-4545-BE28-F8927D72097F@apple.com>
References: <20100629005039.39B192A6C12C@llvm.org> <4C298317.7050002@mxc.ca>
	<5E31E70D-BC94-4545-BE28-F8927D72097F@apple.com>
Message-ID: <0EAA395C-1A7A-45D2-A6F9-F3B837A0F91C@apple.com>

On Jun 29, 2010, at 11:09 AM, Dan Gohman wrote:
>> Why is this an additional pass? Why not infer Interprocedural from SameParent()? The idempotents that basicaa was testing for should still hold true whenever SameParent() is true. It looks like the 'Interprocedural BasicAA' is basically a bugfix on BasicAA.
> 
> "noalias" is only meaningful from a single-procedure perspective.
> For example:
> 
> @G = external global i32
> define void @foo(i32* noalias %p) {
>  ...
> }
> ...
>  call void @foo(i32* @G)
> 
> If you're working exclusively within the body of @foo, then alias(@G, %p)
> can be NoAlias. From an interprocedural perspective, it can be MustAlias.
> Even with something like
> 
> define void @bar(double* noalias %a, double* noalias %b) {
> 
> it isn't trivial to say that %a doesn't alias %b because if it goes on to do
> 
>  call void @bar(double* %b, double* %a)
> 
> then there is a sense in which %a could MustAlias %b, interprocedurally.

I don't buy this at all.  The current interface to AA (even for interprocedural clients) is context insensitive.  If you want a path or context-sensitive query interface, you'd need a substantially richer and more complex (aka slower) interface.  DSA provides this sort of interface for example.

To be clear, alias(a,b) is always no-alias since the arguments are "no-alias" and they are in the same function.  no-alias clearly doesn't apply if the pointers are in different functions.

> Then there's "arguments can't alias allocas" logic. From a non-interprocedural
> perspective, this works. From an interprocedural perspective, consider
> function r0 in the included testcase.

Again, this is only true if AA were a context or path sensitive interface, but it isn't.  GlobalModRef is an example of a context sensitive analysis which is queried with a context insensitive interface.  DSA (in the poolalloc module) is another.  To be able to do context sensitive queries, you have to be able to pass information into the clients.  I am pretty sure that I covered this in my phd thesis if you care.

> Another interesting thing to consider is that the current alias API
> doesn't provide a way to specify the scope to consider for potential
> aliasing.

Right, and it shouldn't IMO because it is a) very expensive to express and b) completely uninteresting for most clients.  If we wanted to handle context sensitive queries, we should add a new ContextSensitiveAA interface or something.

-Chris


From clattner at apple.com  Wed Jun 30 23:31:50 2010
From: clattner at apple.com (Chris Lattner)
Date: Wed, 30 Jun 2010 21:31:50 -0700
Subject: [llvm-commits] [llvm] r107109 - in /llvm/trunk:
	include/llvm/Analysis/AliasAnalysis.h	include/llvm/Analysis/Passes.h
	lib/Analysis/AliasAnalysis.cpp	lib/Analysis/BasicAliasAnalysis.cpp
	test/Analysis/BasicAA/interprocedural.ll
In-Reply-To: <0EAA395C-1A7A-45D2-A6F9-F3B837A0F91C@apple.com>
References: <20100629005039.39B192A6C12C@llvm.org> <4C298317.7050002@mxc.ca>
	<5E31E70D-BC94-4545-BE28-F8927D72097F@apple.com>
	<0EAA395C-1A7A-45D2-A6F9-F3B837A0F91C@apple.com>
Message-ID: <F25B876D-871E-4D65-9589-D055D1252B14@apple.com>


On Jun 30, 2010, at 9:21 PM, Chris Lattner wrote:

>> 
>> Then there's "arguments can't alias allocas" logic. From a non-interprocedural
>> perspective, this works. From an interprocedural perspective, consider
>> function r0 in the included testcase.
> 
> Again, this is only true if AA were a context or path sensitive interface, but it isn't.  GlobalModRef is an example of a context sensitive analysis which is queried with a context insensitive interface.  DSA (in the poolalloc module) is another.  To be able to do context sensitive queries, you have to be able to pass information into the clients.  I am pretty sure that I covered this in my phd thesis if you care.

Let me put this a different way.  The AliasAnalysis interface is *really only intended* for context insensitive clients.  DSA provides a series of passes (bottom-up, top-down etc) which context sensitive clients can use to get specific information.  The DSA algorithm captures a bunch of information into various data structures, which aren't directly useful for implementing AA.

When it comes to actually implementing the AA interface with the DSA information (section 4.2 of http://llvm.org/pubs/2005-05-04-LattnerPHDThesis.pdf), the problem comes down to using the information captured by the previous passes to respond to the various queries.

For example, the alias query (when both pointers are global or within the same function) find the function the pointer is in and devolves to looking in that one graph.  Amusingly, the implementation currently asserts if the pointers are in two different functions:

http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DataStructureAA.cpp?revision=HEAD&view=markup
...

AliasAnalysis::AliasResult DSAA::alias(const Value *V1, unsigned V1Size,
                                       const Value *V2, unsigned V2Size) {
  assert(valid && "DSAA invalidated but then queried?!");
  if (V1 == V2) return MustAlias;

  DSGraph *G1 = getGraphForValue(V1);
  DSGraph *G2 = getGraphForValue(V2);
  assert((!G1 || !G2 || G1 == G2) && "Alias query for 2 different functions?");

  // Get the graph to use...
  DSGraph* G = G1 ? G1 : (G2 ? G2 : TD->getGlobalsGraph());

This is basically saying "get the one functions graph if either pointer is local to a function, otherwise get the globals graph if they are both global".  The assertion will trigger if you have pointers within different functions.  Asserting in this case is lame of course (DSA should just return MayAlias), but we don't have any clients that make that query.
The DSA information is used in more interesting ways for mod/ref queries.  To answer whether a call to a function modifies an alloca in the caller, for example, it does some heavy graph mapping/manipulation which *is* context sensitive.  However, this is still within the context-sensitive query API.
I don't think we need the "IP BasicAA" pass: if you agree, please remove it.
-Chris
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From clattner at apple.com  Wed Jun 30 23:38:03 2010
From: clattner at apple.com (Chris Lattner)
Date: Wed, 30 Jun 2010 21:38:03 -0700
Subject: [llvm-commits] [llvm] r107377 - in /llvm/trunk:
	lib/CodeGen/SelectionDAG/FastISel.cpp
	lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
	lib/Target/X86/X86FastISel.cpp
	test/CodeGen/X86/fast-isel-shift-imm.ll
In-Reply-To: <20100701025857.A3A102A6C12C@llvm.org>
References: <20100701025857.A3A102A6C12C@llvm.org>
Message-ID: <50013A08-7432-4456-8A53-84445A71EAE0@apple.com>


On Jun 30, 2010, at 7:58 PM, Dan Gohman wrote:

> Author: djg
> Date: Wed Jun 30 21:58:57 2010
> New Revision: 107377
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=107377&view=rev
> Log:
> Enable on-demand fast-isel.

Ok, so instead of going bottom-up, you instead go top-down but only select side-effect-free instructions on demand?  Killing off MachineDCE for fast isel is great, did you verify that it isn't actually zapping anything?

-Chris




From baldrick at free.fr  Thu Jul  1 02:12:27 2010
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 01 Jul 2010 09:12:27 +0200
Subject: [llvm-commits] [llvm] r107323 - in /llvm/trunk:
 lib/Transforms/IPO/StripSymbols.cpp
 test/Transforms/StripSymbols/2010-06-30-StripDebug.ll
In-Reply-To: <20100630212900.5D0DB2A6C12C@llvm.org>
References: <20100630212900.5D0DB2A6C12C@llvm.org>
Message-ID: <4C2C3FDB.4000408@free.fr>

Hi Devang,

> -  NamedMDNode *NMD = M.getNamedMetadata("llvm.dbg.gv");
> -  if (NMD) {
> -    Changed = true;
> -    NMD->eraseFromParent();
> -  }
> -
> -  NMD = M.getNamedMetadata("llvm.dbg.lv");
> -  if (NMD) {
> -    Changed = true;
> -    NMD->eraseFromParent();
> +  for (Module::named_metadata_iterator NMI = M.named_metadata_begin(),
> +         NME = M.named_metadata_end(); NMI != NME;) {
> +    NamedMDNode *NMD = NMI;
> +    ++NMI;
> +    if (NMD->getName().startswith("llvm.dbg."))
> +      NMD->eraseFromParent();

should you set Changed to "true" here?

Ciao,

Duncan.


From wendling at apple.com  Thu Jul  1 03:29:54 2010
From: wendling at apple.com (Bill Wendling)
Date: Thu, 1 Jul 2010 01:29:54 -0700
Subject: [llvm-commits] [llvm] r107205 -
	in	/llvm/trunk:	bindings/ada/llvm/ docs/
	include/llvm-c/	include/llvm/	include/llvm/CodeGen/
	include/llvm/MC/ include/llvm/Target/	lib/AsmParser/
	lib/Bitcode/Reader/	lib/Bitcode/Writer/ lib/CodeGen/
	lib/CodeGen/AsmPrinter/	lib/Linker/ lib/MC/	lib/Target/
	lib/Target/CppBackend/	lib/Target/XCore/AsmPrinter/	lib/Transforms/IPO/
	lib/VMCore/	tools/llvm-nm/
In-Reply-To: <D50B4716-517B-4A09-8039-B324E97BCB17@apple.com>
References: <20100629212400.DABF32A6C12C@llvm.org>
	<C7E3E4A7-A598-4C61-9513-2DFC7C2EC4CC@apple.com>
	<AF811FB0-E72D-44DD-8BBD-1C6D4971F1AF@gmail.com>
	<FA99D48A-0561-420D-AA6C-6983AB1AFEC9@apple.com>
	<7805A44F-4DAD-467F-B254-E1AB184FD2EB@gmail.com>
	<B5AAFD97-0164-48AD-BC09-7137D8A0E205@apple.com>
	<D50B4716-517B-4A09-8039-B324E97BCB17@apple.com>
Message-ID: <8AD968EF-DC22-410F-96B2-4620D2689630@apple.com>

On Jun 30, 2010, at 9:03 PM, Chris Lattner wrote:

>>>>> I'll check to see if it's used. If it's not used, then it's relying upon the hack down below, which is bad. However, I much prefer having the prefix string in one place than relying upon it being buried in some deep part of the asm printer.
>>>> 
>>>> I don't really understand what you mean.
>>>> 
>>> I want to separate it out from the "linker_private" linkage. In particular, I don't want to say that it will always have the same prefix as linker_private. That's the case with Darwin, but I don't see why that has to be the case for every linker that would want to implement it.
>>> 
>> Or for every target for that matter. Otherwise, these linkages are restricted to a small subset of usages -- Objective-C metadata on Darwin.
> 
> This feature is only supported on one OS (darwin) and all of the targets (arm/ppc/x86) use the same prefix.  I don't see any reason to hookize something that is constant across all supported targets.
> 
It's not necessarily restricted to Darwin from now until forever, right? Any other platform is free to implement this as they choose. And they don't have to follow any of the restrictions that Darwin places on it. I.e., that they should require having the same prefixes for both, etc.

But if it is restricted to Darwin and is not for any other platform to use ever, then I'm not so certain that these linkage types are a great idea. Or at least the names should reflect as much - maybe darwin_linker_private, darwin_linker_private_weak.

-bw




From isanbard at gmail.com  Thu Jul  1 03:31:57 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 1 Jul 2010 01:31:57 -0700
Subject: [llvm-commits] [llvm] r107205 -
	in	/llvm/trunk:	bindings/ada/llvm/ docs/
	include/llvm-c/	include/llvm/	include/llvm/CodeGen/
	include/llvm/MC/ include/llvm/Target/	lib/AsmParser/
	lib/Bitcode/Reader/	lib/Bitcode/Writer/ lib/CodeGen/
	lib/CodeGen/AsmPrinter/	lib/Linker/ lib/MC/	lib/Target/
	lib/Target/CppBackend/	lib/Target/XCore/AsmPrinter/	lib/Transforms/IPO/
	lib/VMCore/	tools/llvm-nm/
In-Reply-To: <E134F460-3DAE-41B5-A606-F0C56186DE07@apple.com>
References: <20100629212400.DABF32A6C12C@llvm.org>
	<C7E3E4A7-A598-4C61-9513-2DFC7C2EC4CC@apple.com>
	<AF811FB0-E72D-44DD-8BBD-1C6D4971F1AF@gmail.com>
	<FA99D48A-0561-420D-AA6C-6983AB1AFEC9@apple.com>
	<9E57AC43-C5F3-418C-8159-F3AF703BA3F1@apple.com>
	<E134F460-3DAE-41B5-A606-F0C56186DE07@apple.com>
Message-ID: <CF658B9E-17AA-43D2-965F-D66475019C16@gmail.com>

On Jun 30, 2010, at 9:04 PM, Chris Lattner wrote:

>> Unless someone here can really spell out what these things really
>> mean, without mentioning assembler directives, without mentioning
>> special label naming conventions, without describing it in terms of
>> what gcc does for Objective C, and without citing "this is what the
>> Objective C people say we need", and without excluding any magical
>> semantics, it would be best to avoid confusion.
> 
> This is easy to do, Bill just needs to do it.  I completely agree that it is imperative that this happen!
> 
I have been doing this. :-( But I'm not going to charge headlong into this again without discussion, since I was criticized for not waiting the last time.

-bw




From isanbard at gmail.com  Thu Jul  1 03:35:04 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 1 Jul 2010 01:35:04 -0700
Subject: [llvm-commits] [llvm] r107205 -
	in	/llvm/trunk:	bindings/ada/llvm/ docs/
	include/llvm-c/	include/llvm/	include/llvm/CodeGen/
	include/llvm/MC/ include/llvm/Target/	lib/AsmParser/
	lib/Bitcode/Reader/	lib/Bitcode/Writer/ lib/CodeGen/
	lib/CodeGen/AsmPrinter/	lib/Linker/ lib/MC/	lib/Target/
	lib/Target/CppBackend/	lib/Target/XCore/AsmPrinter/	lib/Transforms/IPO/
	lib/VMCore/	tools/llvm-nm/
In-Reply-To: <CBE117B2-2498-4A1D-8967-0DC60214B58C@apple.com>
References: <20100629212400.DABF32A6C12C@llvm.org>
	<C7E3E4A7-A598-4C61-9513-2DFC7C2EC4CC@apple.com>
	<AF811FB0-E72D-44DD-8BBD-1C6D4971F1AF@gmail.com>
	<FA99D48A-0561-420D-AA6C-6983AB1AFEC9@apple.com>
	<9E57AC43-C5F3-418C-8159-F3AF703BA3F1@apple.com>
	<79223963-640D-43E4-BB73-0D3D9DD729D6@gmail.com>
	<CBE117B2-2498-4A1D-8967-0DC60214B58C@apple.com>
Message-ID: <7AB97E23-B4AA-4784-83D4-B31C6818EE09@gmail.com>

On Jun 30, 2010, at 9:06 PM, Chris Lattner wrote:

> On Jun 30, 2010, at 11:47 AM, Bill Wendling wrote:
> 
>>> 
>>> Unless someone here can really spell out what these things really
>>> mean, without mentioning assembler directives, without mentioning
>>> special label naming conventions, without describing it in terms of
>>> what gcc does for Objective C, and without citing "this is what the
>>> Objective C people say we need", and without excluding any magical
>>> semantics, it would be best to avoid confusion.
>>> 
>> I view these linkages as being like their non-"linker linkage" counterparts, but that the linker will remove them from the final linked image. So, "linker_private" is "private" but the linker will remove it from the final linked image and so on. "linker_private_weak" has no non-"linker linkage" counterpart, but its semantics are a natural progression maybe?
> 
> The semantics are clear to me: "lfoo" labels are stripped by the linker, but cause multiple definition cause redefinition errors.  "weak lfoo" labels are stripped by the linker, but multiple definitions get merged.  This doesn't seem that complicated.
> 
It's not. And it's essentially what I wrote in the RFC that I sent to llvmdev. But you just used a special label naming convention in your description, which is one thing Dan asked not be used to define this.

My remaining concern is that you seem to be asking me to tailor this linkage type for a particular platform (Darwin).

-bw




From baldrick at free.fr  Thu Jul  1 05:27:59 2010
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 01 Jul 2010 10:27:59 -0000
Subject: [llvm-commits] [dragonegg] r107389 - /dragonegg/trunk/Makefile
Message-ID: <20100701102759.7CCC82A6C12E@llvm.org>

Author: baldrick
Date: Thu Jul  1 05:27:59 2010
New Revision: 107389

URL: http://llvm.org/viewvc/llvm-project?rev=107389&view=rev
Log:
Correct the garbage collection header target.

Modified:
    dragonegg/trunk/Makefile

Modified: dragonegg/trunk/Makefile
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/Makefile?rev=107389&r1=107388&r2=107389&view=diff
==============================================================================
--- dragonegg/trunk/Makefile (original)
+++ dragonegg/trunk/Makefile Thu Jul  1 05:27:59 2010
@@ -102,7 +102,7 @@
 # is not used in a normal build.
 GENGTYPE_INPUT=$(SRC_DIR)/llvm-cache.c
 GENGTYPE_OUTPUT=$(SRC_DIR)/gt-llvm-cache.h
-$(GENGTYPE_OUTPUT):
+gt-llvm-cache.h::
 	cd $(HOME)/GCC/objects/gcc && ./build/gengtype \
 	  -P $(GENGTYPE_OUTPUT) $(GCC_PLUGIN_DIR) gtyp-input.list \
 	    $(GENGTYPE_INPUT)




From ggreif at gmail.com  Thu Jul  1 05:41:38 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Thu, 01 Jul 2010 10:41:38 -0000
Subject: [llvm-commits] [llvm] r107390 -
	/llvm/trunk/lib/VMCore/Instructions.cpp
Message-ID: <20100701104138.1F3292A6C12E@llvm.org>

Author: ggreif
Date: Thu Jul  1 05:41:37 2010
New Revision: 107390

URL: http://llvm.org/viewvc/llvm-project?rev=107390&view=rev
Log:
reformulate CallSite::getCallee to adapt to CallInst::ArgOffset, and make it work even if CallInst::op_* are private

Modified:
    llvm/trunk/lib/VMCore/Instructions.cpp

Modified: llvm/trunk/lib/VMCore/Instructions.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=107390&r1=107389&r2=107390&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Instructions.cpp (original)
+++ llvm/trunk/lib/VMCore/Instructions.cpp Thu Jul  1 05:41:37 2010
@@ -33,7 +33,9 @@
 User::op_iterator CallSite::getCallee() const {
   Instruction *II(getInstruction());
   return isCall()
-    ? cast<CallInst>(II)->op_begin()
+    ? (CallInst::ArgOffset
+       ? cast</*FIXME: CallInst*/User>(II)->op_begin()
+       : cast</*FIXME: CallInst*/User>(II)->op_end() - 1)
     : cast<InvokeInst>(II)->op_end() - 3; // Skip BB, BB, Function
 }
 




From baldrick at free.fr  Thu Jul  1 06:10:59 2010
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 01 Jul 2010 11:10:59 -0000
Subject: [llvm-commits] [dragonegg] r107391 - /dragonegg/trunk/llvm-cache.c
Message-ID: <20100701111059.5761F2A6C12E@llvm.org>

Author: baldrick
Date: Thu Jul  1 06:10:59 2010
New Revision: 107391

URL: http://llvm.org/viewvc/llvm-project?rev=107391&view=rev
Log:
Move the garbage collector header up - declarations in it are needed by the
following code when using gcc-4.6.

Modified:
    dragonegg/trunk/llvm-cache.c

Modified: dragonegg/trunk/llvm-cache.c
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/llvm-cache.c?rev=107391&r1=107390&r2=107391&view=diff
==============================================================================
--- dragonegg/trunk/llvm-cache.c (original)
+++ dragonegg/trunk/llvm-cache.c Thu Jul  1 06:10:59 2010
@@ -43,6 +43,9 @@
              param_is(struct tree_llvm_map)))
   htab_t llvm_cache;
 
+// Garbage collector header
+#include "gt-llvm-cache.h"
+
 /// llvm_has_cached - Returns whether a value has been associated with the tree.
 bool llvm_has_cached(union tree_node *tree) {
   struct tree_map_base in;
@@ -129,5 +132,3 @@
 
   htab_traverse(llvm_cache, replace, &u);
 }
-
-#include "gt-llvm-cache.h"




From ggreif at gmail.com  Thu Jul  1 06:26:05 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Thu, 01 Jul 2010 11:26:05 -0000
Subject: [llvm-commits] [llvm] r107392 -
	/llvm/trunk/include/llvm/Support/CallSite.h
Message-ID: <20100701112605.DFAF92A6C12E@llvm.org>

Author: ggreif
Date: Thu Jul  1 06:26:05 2010
New Revision: 107392

URL: http://llvm.org/viewvc/llvm-project?rev=107392&view=rev
Log:
reformulate CallSiteBase::getCallee to adapt to CallInst::ArgOffset, and make it work even if CallInst::op_* are private

Modified:
    llvm/trunk/include/llvm/Support/CallSite.h

Modified: llvm/trunk/include/llvm/Support/CallSite.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/CallSite.h?rev=107392&r1=107391&r2=107392&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/CallSite.h (original)
+++ llvm/trunk/include/llvm/Support/CallSite.h Thu Jul  1 06:26:05 2010
@@ -273,7 +273,9 @@
       // of the op_*() functions here. See CallSite::getCallee.
       //
     if (isCall())
-      return getInstruction()->op_begin(); // Unchanged (ATM)
+      return CallInst::ArgOffset
+             ? getInstruction()->op_begin() // Unchanged
+             : getInstruction()->op_end() - 1; // Skip Function
     else
       return getInstruction()->op_end() - 3; // Skip BB, BB, Function
   }




From peter at pcc.me.uk  Thu Jul  1 06:30:46 2010
From: peter at pcc.me.uk (Peter Collingbourne)
Date: Thu, 1 Jul 2010 12:30:46 +0100
Subject: [llvm-commits] [PATCH (need approval)] Add support
	for	InsertValue and ExtractValue to gep_type_iterator
In-Reply-To: <F9C9FA6D-7517-46FC-A41F-57282FB2551A@apple.com>
References: <1277926785-28322-1-git-send-email-peter@pcc.me.uk>
	<F9C9FA6D-7517-46FC-A41F-57282FB2551A@apple.com>
Message-ID: <20100701113046.GA10397@pcc.me.uk>

On Wed, Jun 30, 2010 at 09:09:32PM -0700, Chris Lattner wrote:
> On Jun 30, 2010, at 12:39 PM, Peter Collingbourne wrote:
> 
> > ---
> > Hi,
> > 
> > This adds iv_type_iterator, ev_type_iterator and vce_type_iterator
> > to complement gep_type_iterator.
> > 
> > I'm not 100% certain this is the right way to do this.  Perhaps we
> > should introduce an Operator for generically accessing the index
> > iterators for {Insert,Extract}Values.  This would work right now
> > because all the iterators are of underlying type const unsigned *
> > but of course this may change in the future.
> 
> Hi Peter,
> 
> What problem are you trying to solve here?

Hi Chris,

In another project (Klee) we needed to extend a procedure that
enumerated the types of a GEP to handle InsertValue and ExtractValue
(this procedure calculates the byte offset of the indices).  To avoid
code duplication we decided to do this in a generic way by extending
the capabilities of gep_type_iterator.

I imagined this would also be useful for other users or perhaps LLVM
itself so we decided to make this a change to LLVM and contribute
it upstream.

Thanks,
-- 
Peter


From baldrick at free.fr  Thu Jul  1 06:50:37 2010
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 01 Jul 2010 13:50:37 +0200
Subject: [llvm-commits] [PATCH (need approval)] Add
 support	for	InsertValue and ExtractValue to gep_type_iterator
In-Reply-To: <20100701113046.GA10397@pcc.me.uk>
References: <1277926785-28322-1-git-send-email-peter@pcc.me.uk>	<F9C9FA6D-7517-46FC-A41F-57282FB2551A@apple.com>
	<20100701113046.GA10397@pcc.me.uk>
Message-ID: <4C2C810D.9090508@free.fr>

Hi Peter,

> In another project (Klee) we needed to extend a procedure that
> enumerated the types of a GEP to handle InsertValue and ExtractValue
> (this procedure calculates the byte offset of the indices).

are you saying that you want to calculate the memory offset for an
InsertValue or ExtractValue?  If so, this doesn't make much sense
to me: these are registers, there is no memory involved.

Ciao,

Duncan.


From gohman at apple.com  Thu Jul  1 07:15:31 2010
From: gohman at apple.com (Dan Gohman)
Date: Thu, 01 Jul 2010 12:15:31 -0000
Subject: [llvm-commits] [llvm] r107393 - in /llvm/trunk:
 lib/CodeGen/LLVMTargetMachine.cpp
 lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
 test/CodeGen/X86/fast-isel-loads.ll
Message-ID: <20100701121531.1834E2A6C12E@llvm.org>

Author: djg
Date: Thu Jul  1 07:15:30 2010
New Revision: 107393

URL: http://llvm.org/viewvc/llvm-project?rev=107393&view=rev
Log:
Temporarily disable on-demand fast-isel.

Modified:
    llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
    llvm/trunk/test/CodeGen/X86/fast-isel-loads.ll

Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=107393&r1=107392&r2=107393&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original)
+++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Thu Jul  1 07:15:30 2010
@@ -329,15 +329,19 @@
   if (OptLevel != CodeGenOpt::None)
     PM.add(createOptimizePHIsPass());
 
-  if (OptLevel != CodeGenOpt::None) {
-    // With optimization, dead code should already be eliminated. However
-    // there is one known exception: lowered code for arguments that are only
-    // used by tail calls, where the tail calls reuse the incoming stack
-    // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
-    PM.add(createDeadMachineInstructionElimPass());
-    printAndVerify(PM, "After codegen DCE pass",
-                   /* allowDoubleDefs= */ true);
+  // Delete dead machine instructions regardless of optimization level.
+  //
+  // At -O0, fast-isel frequently creates dead instructions.
+  //
+  // With optimization, dead code should already be eliminated. However
+  // there is one known exception: lowered code for arguments that are only
+  // used by tail calls, where the tail calls reuse the incoming stack
+  // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
+  PM.add(createDeadMachineInstructionElimPass());
+  printAndVerify(PM, "After codegen DCE pass",
+                 /* allowDoubleDefs= */ true);
 
+  if (OptLevel != CodeGenOpt::None) {
     PM.add(createOptimizeExtsPass());
     if (!DisableMachineLICM)
       PM.add(createMachineLICMPass());

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=107393&r1=107392&r2=107393&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Jul  1 07:15:30 2010
@@ -709,11 +709,13 @@
       FastIS->startNewBlock(BB);
       // Do FastISel on as many instructions as possible.
       for (; BI != End; ++BI) {
+#if 0
         // Defer instructions with no side effects; they'll be emitted
         // on-demand later.
         if (BI->isSafeToSpeculativelyExecute() &&
             !FuncInfo->isExportedInst(BI))
           continue;
+#endif
 
         // Try to select the instruction with FastISel.
         if (FastIS->SelectInstruction(BI))

Modified: llvm/trunk/test/CodeGen/X86/fast-isel-loads.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-loads.ll?rev=107393&r1=107392&r2=107393&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fast-isel-loads.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fast-isel-loads.ll Thu Jul  1 07:15:30 2010
@@ -5,7 +5,7 @@
 ; CHECK: foo:
 ; CHECK-NEXT: movq  %rdi, -8(%rsp)
 ; CHECK-NEXT: movq  %rsi, -16(%rsp)
-; CHECK-NEXT: movsd 128(%rsi,%rdi,8), %xmm0
+; CHECK: movsd 128(%rsi,%rdi,8), %xmm0
 ; CHECK-NEXT: ret
 
 define double @foo(i64 %x, double* %p) nounwind {




From peter at pcc.me.uk  Thu Jul  1 08:22:30 2010
From: peter at pcc.me.uk (Peter Collingbourne)
Date: Thu, 1 Jul 2010 14:22:30 +0100
Subject: [llvm-commits] [PATCH (need approval)] Add support
	for	InsertValue and ExtractValue to gep_type_iterator
In-Reply-To: <4C2C810D.9090508@free.fr>
References: <1277926785-28322-1-git-send-email-peter@pcc.me.uk>
	<F9C9FA6D-7517-46FC-A41F-57282FB2551A@apple.com>
	<20100701113046.GA10397@pcc.me.uk> <4C2C810D.9090508@free.fr>
Message-ID: <20100701132230.GA10914@pcc.me.uk>

On Thu, Jul 01, 2010 at 01:50:37PM +0200, Duncan Sands wrote:
> Hi Peter,
> 
> > In another project (Klee) we needed to extend a procedure that
> > enumerated the types of a GEP to handle InsertValue and ExtractValue
> > (this procedure calculates the byte offset of the indices).
> 
> are you saying that you want to calculate the memory offset for an
> InsertValue or ExtractValue?  If so, this doesn't make much sense
> to me: these are registers, there is no memory involved.

Hi Duncan,

Klee represents each register as a bit vector -- this includes any
type of register, including exotic ones such as structs.  We needed
to be able to calculate an offset into this bit vector to implement
InsertValue and ExtractValue.  I would imagine that other (concrete
or symbolic) interpreters could be implemented in a similar way.

Thanks,
-- 
Peter


From baldrick at free.fr  Thu Jul  1 08:34:05 2010
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 01 Jul 2010 15:34:05 +0200
Subject: [llvm-commits] [PATCH (need approval)] Add support
 for	InsertValue and ExtractValue to gep_type_iterator
In-Reply-To: <20100701132230.GA10914@pcc.me.uk>
References: <1277926785-28322-1-git-send-email-peter@pcc.me.uk>
	<F9C9FA6D-7517-46FC-A41F-57282FB2551A@apple.com>
	<20100701113046.GA10397@pcc.me.uk> <4C2C810D.9090508@free.fr>
	<20100701132230.GA10914@pcc.me.uk>
Message-ID: <4C2C994D.9020205@free.fr>

Hi Peter,

>>> In another project (Klee) we needed to extend a procedure that
>>> enumerated the types of a GEP to handle InsertValue and ExtractValue
>>> (this procedure calculates the byte offset of the indices).
>>
>> are you saying that you want to calculate the memory offset for an
>> InsertValue or ExtractValue?  If so, this doesn't make much sense
>> to me: these are registers, there is no memory involved.
>
> Hi Duncan,
>
> Klee represents each register as a bit vector -- this includes any
> type of register, including exotic ones such as structs.  We needed
> to be able to calculate an offset into this bit vector to implement
> InsertValue and ExtractValue.  I would imagine that other (concrete
> or symbolic) interpreters could be implemented in a similar way.

if I understand right, Klee has chosen a particular way of representing these
registers, and you are suggesting a gep_type_iterator enhancement which only
makes sense when Klee's particular representation is used.  If so, I think it
is best if it stays in Klee.

Ciao,

Duncan.


From peter at pcc.me.uk  Thu Jul  1 09:44:07 2010
From: peter at pcc.me.uk (Peter Collingbourne)
Date: Thu, 1 Jul 2010 15:44:07 +0100
Subject: [llvm-commits] [PATCH (need approval)] Add support
	for	InsertValue and ExtractValue to gep_type_iterator
In-Reply-To: <4C2C994D.9020205@free.fr>
References: <1277926785-28322-1-git-send-email-peter@pcc.me.uk>
	<F9C9FA6D-7517-46FC-A41F-57282FB2551A@apple.com>
	<20100701113046.GA10397@pcc.me.uk> <4C2C810D.9090508@free.fr>
	<20100701132230.GA10914@pcc.me.uk> <4C2C994D.9020205@free.fr>
Message-ID: <20100701144407.GA11275@pcc.me.uk>

On Thu, Jul 01, 2010 at 03:34:05PM +0200, Duncan Sands wrote:
> Hi Peter,
>
>>>> In another project (Klee) we needed to extend a procedure that
>>>> enumerated the types of a GEP to handle InsertValue and ExtractValue
>>>> (this procedure calculates the byte offset of the indices).
>>>
>>> are you saying that you want to calculate the memory offset for an
>>> InsertValue or ExtractValue?  If so, this doesn't make much sense
>>> to me: these are registers, there is no memory involved.
>>
>> Hi Duncan,
>>
>> Klee represents each register as a bit vector -- this includes any
>> type of register, including exotic ones such as structs.  We needed
>> to be able to calculate an offset into this bit vector to implement
>> InsertValue and ExtractValue.  I would imagine that other (concrete
>> or symbolic) interpreters could be implemented in a similar way.
>
> if I understand right, Klee has chosen a particular way of representing these
> registers, and you are suggesting a gep_type_iterator enhancement which only
> makes sense when Klee's particular representation is used.  If so, I think it
> is best if it stays in Klee.

Ok, I'll add this to Klee.

Thanks,
-- 
Peter


From ggreif at gmail.com  Thu Jul  1 10:16:35 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Thu, 01 Jul 2010 15:16:35 -0000
Subject: [llvm-commits] [llvm] r107396 -
	/llvm/trunk/include/llvm/Instructions.h
Message-ID: <20100701151635.D084C2A6C12C@llvm.org>

Author: ggreif
Date: Thu Jul  1 10:16:35 2010
New Revision: 107396

URL: http://llvm.org/viewvc/llvm-project?rev=107396&view=rev
Log:
evil hack to coerce external users (projects)
to update their code to high-level interfaces

If you get compile errors in your project
please update your code according to the
comments.

Modified:
    llvm/trunk/include/llvm/Instructions.h

Modified: llvm/trunk/include/llvm/Instructions.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=107396&r1=107395&r2=107396&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Instructions.h (original)
+++ llvm/trunk/include/llvm/Instructions.h Thu Jul  1 10:16:35 2010
@@ -948,6 +948,13 @@
   Value *getArgOperand(unsigned i) const { return getOperand(i + ArgOffset); }
   void setArgOperand(unsigned i, Value *v) { setOperand(i + ArgOffset, v); }
 
+  /// Provide compile-time errors for accessing operand 0
+  /// @deprecated these will go away soon
+  /// @detail see below comments and update your code to high-level interfaces
+  ///
+  void getOperand(void*); // NO IMPL ---> use getCalledValue (or possibly getCalledFunction) instead
+  void setOperand(void*, Value*); // NO IMPL ---> use setCalledFunction instead
+
   /// getCallingConv/setCallingConv - Get or set the calling convention of this
   /// function call.
   CallingConv::ID getCallingConv() const {




From daniel at zuster.org  Thu Jul  1 10:27:55 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 01 Jul 2010 15:27:55 -0000
Subject: [llvm-commits] [zorg] r107397 - in /zorg/trunk/lnt/lnt/util:
	ImportData.py NTEmailReport.py
Message-ID: <20100701152755.C823D2A6C12C@llvm.org>

Author: ddunbar
Date: Thu Jul  1 10:27:55 2010
New Revision: 107397

URL: http://llvm.org/viewvc/llvm-project?rev=107397&view=rev
Log:
NT/simple: Change email report to include a (short) list of all the preexisting
failures.

Also, fix link to report on server.

Modified:
    zorg/trunk/lnt/lnt/util/ImportData.py
    zorg/trunk/lnt/lnt/util/NTEmailReport.py

Modified: zorg/trunk/lnt/lnt/util/ImportData.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/util/ImportData.py?rev=107397&r1=107396&r2=107397&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/util/ImportData.py (original)
+++ zorg/trunk/lnt/lnt/util/ImportData.py Thu Jul  1 10:27:55 2010
@@ -71,11 +71,8 @@
 
     if not disable_email and toAddress is not None:
         print >>log, "\nMAILING RESULTS TO: %r\n" % toAddress
-        # FIXME: The url below is wrong, it shouldn't be hardcoded to
-        # nightlytest.
         NTEmailReport.emailReport(db, run,
-                                  "%s/db_%s/nightlytest/" % (config.zorgURL,
-                                                             db_name),
+                                  "%s/db_%s/" % (config.zorgURL, db_name),
                                   email_config.host, email_config.from_address,
                                   toAddress, success, commit)
 

Modified: zorg/trunk/lnt/lnt/util/NTEmailReport.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/util/NTEmailReport.py?rev=107397&r1=107396&r2=107397&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/util/NTEmailReport.py (original)
+++ zorg/trunk/lnt/lnt/util/NTEmailReport.py Thu Jul  1 10:27:55 2010
@@ -132,7 +132,7 @@
     # Generate the report header.
     if baseurl[-1] == '/':
         baseurl = baseurl[:-1]
-    print >>report, """%s/%d/""" % (baseurl, run.id)
+    print >>report, """%s/simple/%s/%d/""" % (baseurl, tag, run.id)
     print >>report, """Nickname: %s:%d""" % (machine.name, machine.number)
     if 'name' in machine.info:
         print >>report, """Name: %s""" % (machine.info['name'].value,)
@@ -204,7 +204,7 @@
                         print >>report, '  %s' % (name,)
 
     # Generate a list of the existing failures.
-    if False and existing_failures:
+    if existing_failures:
         print >>report
         print >>report, """================="""
         print >>report, """Existing Failures"""
@@ -213,8 +213,13 @@
             if pset or len(existing_failures) > 1:
                 print >>report
                 print >>report, "Parameter Set:", pset
-            for name,cr in tests:
+
+            # Print at most 10 failures in an email report.
+            N = 10
+            for name,cr in tests[:N]:
                 print >>report, '  %s' % (name,)
+            if len(tests) > 10:
+                print >>report, '  ... and %d more ...' % (len(tests) - 10,)
 
     return subject, report.getvalue()
 
@@ -335,7 +340,7 @@
 
     if baseurl[-1] == '/':
         baseurl = baseurl[:-1]
-    print >>report, """%s/%d/""" % (baseurl, run.id)
+    print >>report, """%s/nightlytest/%d/""" % (baseurl, run.id)
     print >>report, """Nickname: %s:%d""" % (machine.name, machine.number)
     if 'name' in machine.info:
         print >>report, """Name: %s""" % (machine.info['name'].value,)




From ggreif at gmail.com  Thu Jul  1 10:42:00 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Thu, 01 Jul 2010 15:42:00 -0000
Subject: [llvm-commits] [llvm] r107399 -
	/llvm/trunk/include/llvm/Instructions.h
Message-ID: <20100701154200.F20FA2A6C12C@llvm.org>

Author: ggreif
Date: Thu Jul  1 10:42:00 2010
New Revision: 107399

URL: http://llvm.org/viewvc/llvm-project?rev=107399&view=rev
Log:
back out r107396 for now, it needs another minor change to function as advertised

Modified:
    llvm/trunk/include/llvm/Instructions.h

Modified: llvm/trunk/include/llvm/Instructions.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=107399&r1=107398&r2=107399&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Instructions.h (original)
+++ llvm/trunk/include/llvm/Instructions.h Thu Jul  1 10:42:00 2010
@@ -948,13 +948,6 @@
   Value *getArgOperand(unsigned i) const { return getOperand(i + ArgOffset); }
   void setArgOperand(unsigned i, Value *v) { setOperand(i + ArgOffset, v); }
 
-  /// Provide compile-time errors for accessing operand 0
-  /// @deprecated these will go away soon
-  /// @detail see below comments and update your code to high-level interfaces
-  ///
-  void getOperand(void*); // NO IMPL ---> use getCalledValue (or possibly getCalledFunction) instead
-  void setOperand(void*, Value*); // NO IMPL ---> use setCalledFunction instead
-
   /// getCallingConv/setCallingConv - Get or set the calling convention of this
   /// function call.
   CallingConv::ID getCallingConv() const {




From scanon at apple.com  Thu Jul  1 10:52:42 2010
From: scanon at apple.com (Stephen Canon)
Date: Thu, 01 Jul 2010 15:52:42 -0000
Subject: [llvm-commits] [compiler-rt] r107400 - in /compiler-rt/trunk/lib:
 adddf3.c addsf3.c comparedf2.c comparesf2.c extendsfdf2.c fp_lib.h muldf3.c
 mulsf3.c negdf2.c negsf2.c
Message-ID: <20100701155242.4C7DE2A6C12C@llvm.org>

Author: scanon
Date: Thu Jul  1 10:52:42 2010
New Revision: 107400

URL: http://llvm.org/viewvc/llvm-project?rev=107400&view=rev
Log:
Adding soft-float comparisons, addition, subtraction, multiplication and negation

Added:
    compiler-rt/trunk/lib/adddf3.c
    compiler-rt/trunk/lib/addsf3.c
    compiler-rt/trunk/lib/comparedf2.c
    compiler-rt/trunk/lib/comparesf2.c
    compiler-rt/trunk/lib/extendsfdf2.c
    compiler-rt/trunk/lib/fp_lib.h
    compiler-rt/trunk/lib/muldf3.c
    compiler-rt/trunk/lib/mulsf3.c
    compiler-rt/trunk/lib/negdf2.c
    compiler-rt/trunk/lib/negsf2.c

Added: compiler-rt/trunk/lib/adddf3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/adddf3.c?rev=107400&view=auto
==============================================================================
--- compiler-rt/trunk/lib/adddf3.c (added)
+++ compiler-rt/trunk/lib/adddf3.c Thu Jul  1 10:52:42 2010
@@ -0,0 +1,150 @@
+/*
+ *                     The LLVM Compiler Infrastructure
+ *
+ * This file is distributed under the University of Illinois Open Source
+ * License. See LICENSE.TXT for details.
+ */
+
+#define DOUBLE_PRECISION
+#include "fp_lib.h"
+
+// This file implements double-precision soft-float addition and subtraction
+// with the IEEE-754 default rounding (to nearest, ties to even).
+
+fp_t __adddf3(fp_t a, fp_t b) {
+    
+    rep_t aRep = toRep(a);
+    rep_t bRep = toRep(b);
+    const rep_t aAbs = aRep & absMask;
+    const rep_t bAbs = bRep & absMask;
+    
+    // Detect if a or b is zero, infinity, or NaN.
+    if (aAbs - 1U >= infRep - 1U || bAbs - 1U >= infRep - 1U) {
+        
+        // NaN + anything = qNaN
+        if (aAbs > infRep) return fromRep(toRep(a) | quietBit);
+        // anything + NaN = qNaN
+        if (bAbs > infRep) return fromRep(toRep(b) | quietBit);
+        
+        if (aAbs == infRep) {
+            // +/-infinity + -/+infinity = qNaN
+            if ((toRep(a) ^ toRep(b)) == signBit) return fromRep(qnanRep);
+            // +/-infinity + anything remaining = +/- infinity
+            else return a;
+        }
+        
+        // anything remaining + +/-infinity = +/-infinity
+        if (bAbs == infRep) return b;
+        
+        // zero + anything = anything
+        if (!aAbs) {
+            // but we need to get the sign right for zero + zero
+            if (!bAbs) return fromRep(toRep(a) & toRep(b));
+            else return b;
+        }
+        
+        // anything + zero = anything
+        if (!bAbs) return a;
+    }
+    
+    // Swap a and b if necessary so that a has the larger absolute value.
+    if (bAbs > aAbs) {
+        const rep_t temp = aRep;
+        aRep = bRep;
+        bRep = temp;
+    }
+    
+    // Extract the exponent and significand from the (possibly swapped) a and b.
+    int aExponent = aRep >> significandBits & maxExponent;
+    int bExponent = bRep >> significandBits & maxExponent;
+    rep_t aSignificand = aRep & significandMask;
+    rep_t bSignificand = bRep & significandMask;
+    
+    // Normalize any denormals, and adjust the exponent accordingly.
+    if (aExponent == 0) aExponent = normalize(&aSignificand);
+    if (bExponent == 0) bExponent = normalize(&bSignificand);
+    
+    // The sign of the result is the sign of the larger operand, a.  If they
+    // have opposite signs, we are performing a subtraction; otherwise addition.
+    const rep_t resultSign = aRep & signBit;
+    const bool subtraction = (aRep ^ bRep) & signBit;
+    
+    // Shift the significands to give us round, guard and sticky, and or in the
+    // implicit significand bit.  (If we fell through from the denormal path it
+    // was already set by normalize( ), but setting it twice won't hurt
+    // anything.)
+    aSignificand = (aSignificand | implicitBit) << 3;
+    bSignificand = (bSignificand | implicitBit) << 3;
+    
+    // Shift the significand of b by the difference in exponents, with a sticky
+    // bottom bit to get rounding correct.
+    const int align = aExponent - bExponent;
+    if (align) {
+        if (align < typeWidth) {
+            const bool sticky = bSignificand << (typeWidth - align);
+            bSignificand = bSignificand >> align | sticky;
+        } else {
+            bSignificand = 1; // sticky; b is known to be non-zero.
+        }
+    }
+    
+    if (subtraction) {
+        aSignificand -= bSignificand;
+        
+        // If a == -b, return +zero.
+        if (aSignificand == 0) return fromRep(0);
+        
+        // If partial cancellation occured, we need to left-shift the result
+        // and adjust the exponent:
+        if (aSignificand < implicitBit << 3) {
+            const int shift = rep_clz(aSignificand) - rep_clz(implicitBit << 3);
+            aSignificand <<= shift;
+            aExponent -= shift;
+        }
+    }
+    
+    else /* addition */ {
+        aSignificand += bSignificand;
+        
+        // If the addition carried up, we need to right-shift the result and
+        // adjust the exponent:
+        if (aSignificand & implicitBit << 4) {
+            const bool sticky = aSignificand & 1;
+            aSignificand = aSignificand >> 1 | sticky;
+            aExponent += 1;
+        }
+    }
+    
+    // If we have overflowed the type, return +/- infinity:
+    if (aExponent >= maxExponent) return fromRep(infRep | resultSign);
+    
+    if (aExponent <= 0) {
+        // Result is denormal before rounding; the exponent is zero and we
+        // need to shift the significand.
+        const int shift = 1 - aExponent;
+        const bool sticky = aSignificand << (typeWidth - shift);
+        aSignificand = aSignificand >> shift | sticky;
+        aExponent = 0;
+    }
+    
+    // Low three bits are round, guard, and sticky.
+    const int roundGuardSticky = aSignificand & 0x7;
+    
+    // Shift the significand into place, and mask off the implicit bit.
+    rep_t result = aSignificand >> 3 & significandMask;
+    
+    // Insert the exponent and sign.
+    result |= (rep_t)aExponent << significandBits;
+    result |= resultSign;
+    
+    // Final rounding.  The result may overflow to infinity, but that is the
+    // correct result in that case.
+    if (roundGuardSticky > 0x4) result++;
+    if (roundGuardSticky == 0x4) result += result & 1;
+    return fromRep(result);
+}
+
+// Subtraction; flip the sign bit of b and add.
+fp_t __subdf3(fp_t a, fp_t b) {
+    return __adddf3(a, fromRep(toRep(b) ^ signBit));
+}

Added: compiler-rt/trunk/lib/addsf3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/addsf3.c?rev=107400&view=auto
==============================================================================
--- compiler-rt/trunk/lib/addsf3.c (added)
+++ compiler-rt/trunk/lib/addsf3.c Thu Jul  1 10:52:42 2010
@@ -0,0 +1,160 @@
+/*
+ *                     The LLVM Compiler Infrastructure
+ *
+ * This file is distributed under the University of Illinois Open Source
+ * License. See LICENSE.TXT for details.
+ */
+
+#define SINGLE_PRECISION
+#include "fp_lib.h"
+
+// This file implements single-precision soft-float addition and subtraction
+// with the IEEE-754 default rounding (to nearest, ties to even).
+
+fp_t __addsf3(fp_t a, fp_t b) {
+
+    rep_t aRep = toRep(a);
+    rep_t bRep = toRep(b);
+    const rep_t aAbs = aRep & absMask;
+    const rep_t bAbs = bRep & absMask;
+    
+    // Detect if a or b is zero, infinity, or NaN.
+    if (aAbs - 1U >= infRep - 1U || bAbs - 1U >= infRep - 1U) {
+        
+        // NaN + anything = qNaN
+        if (aAbs > infRep) return fromRep(toRep(a) | quietBit);
+        // anything + NaN = qNaN
+        if (bAbs > infRep) return fromRep(toRep(b) | quietBit);
+        
+        if (aAbs == infRep) {
+            // +/-infinity + -/+infinity = qNaN
+            if ((toRep(a) ^ toRep(b)) == signBit) return fromRep(qnanRep);
+            // +/-infinity + anything remaining = +/- infinity
+            else return a;
+        }
+        
+        // anything remaining + +/-infinity = +/-infinity
+        if (bAbs == infRep) return b;
+        
+        // zero + anything = anything
+        if (!aAbs) {
+            // but we need to get the sign right for zero + zero
+            if (!bAbs) return fromRep(toRep(a) & toRep(b));
+            else return b;
+        }
+        
+        // anything + zero = anything
+        if (!bAbs) return a;
+    }
+    
+    // Swap a and b if necessary so that a has the larger absolute value.
+    if (bAbs > aAbs) {
+        const rep_t temp = aRep;
+        aRep = bRep;
+        bRep = temp;
+    }
+    
+    // Extract the exponent and significand from the (possibly swapped) a and b.
+    int aExponent = aRep >> significandBits & maxExponent;
+    int bExponent = bRep >> significandBits & maxExponent;
+    rep_t aSignificand = aRep & significandMask;
+    rep_t bSignificand = bRep & significandMask;
+    
+    // Normalize any denormals, and adjust the exponent accordingly.
+    if (aExponent == 0) aExponent = normalize(&aSignificand);
+    if (bExponent == 0) bExponent = normalize(&bSignificand);
+    
+    // The sign of the result is the sign of the larger operand, a.  If they
+    // have opposite signs, we are performing a subtraction; otherwise addition.
+    const rep_t resultSign = aRep & signBit;
+    const bool subtraction = (aRep ^ bRep) & signBit;
+    
+    // Shift the significands to give us round, guard and sticky, and or in the
+    // implicit significand bit.  (If we fell through from the denormal path it
+    // was already set by normalize( ), but setting it twice won't hurt
+    // anything.)
+    aSignificand = (aSignificand | implicitBit) << 3;
+    bSignificand = (bSignificand | implicitBit) << 3;
+    
+    // Shift the significand of b by the difference in exponents, with a sticky
+    // bottom bit to get rounding correct.
+    const int align = aExponent - bExponent;
+    if (align) {
+        if (align < typeWidth) {
+            const bool sticky = bSignificand << (typeWidth - align);
+            bSignificand = bSignificand >> align | sticky;
+        } else {
+            bSignificand = 1; // sticky; b is known to be non-zero.
+        }
+    }
+    
+    if (subtraction) {
+        aSignificand -= bSignificand;
+        
+        // If a == -b, return +zero.
+        if (aSignificand == 0) return fromRep(0);
+        
+        // If partial cancellation occured, we need to left-shift the result
+        // and adjust the exponent:
+        if (aSignificand < implicitBit << 3) {
+            const int shift = rep_clz(aSignificand) - rep_clz(implicitBit << 3);
+            aSignificand <<= shift;
+            aExponent -= shift;
+        }
+    }
+    
+    else /* addition */ {
+        aSignificand += bSignificand;
+        
+        // If the addition carried up, we need to right-shift the result and
+        // adjust the exponent:
+        if (aSignificand & implicitBit << 4) {
+            const bool sticky = aSignificand & 1;
+            aSignificand = aSignificand >> 1 | sticky;
+            aExponent += 1;
+        }
+    }
+    
+    // If we have overflowed the type, return +/- infinity:
+    if (aExponent >= maxExponent) return fromRep(infRep | resultSign);
+    
+    if (aExponent <= 0) {
+        // Result is denormal before rounding; the exponent is zero and we
+        // need to shift the significand.
+        const int shift = 1 - aExponent;
+        const bool sticky = aSignificand << (typeWidth - shift);
+        aSignificand = aSignificand >> shift | sticky;
+        aExponent = 0;
+    }
+    
+    // Low three bits are round, guard, and sticky.
+    const int roundGuardSticky = aSignificand & 0x7;
+    
+    // Shift the significand into place, and mask off the implicit bit.
+    rep_t result = aSignificand >> 3 & significandMask;
+    
+    // Insert the exponent and sign.
+    result |= (rep_t)aExponent << significandBits;
+    result |= resultSign;
+    
+    // Final rounding.  The result may overflow to infinity, but that is the
+    // correct result in that case.
+    if (roundGuardSticky > 0x4) result++;
+    if (roundGuardSticky == 0x4) result += result & 1;
+    return fromRep(result);
+}
+
+// Subtraction; flip the sign bit of b and add.
+fp_t __subsf3(fp_t a, fp_t b) {
+    return __addsf3(a, fromRep(toRep(b) ^ signBit));
+}
+
+
+
+
+
+
+
+
+
+

Added: compiler-rt/trunk/lib/comparedf2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/comparedf2.c?rev=107400&view=auto
==============================================================================
--- compiler-rt/trunk/lib/comparedf2.c (added)
+++ compiler-rt/trunk/lib/comparedf2.c Thu Jul  1 10:52:42 2010
@@ -0,0 +1,127 @@
+/*
+ *                     The LLVM Compiler Infrastructure
+ *
+ * This file is distributed under the University of Illinois Open Source
+ * License. See LICENSE.TXT for details.
+ */
+
+#define DOUBLE_PRECISION
+#include "fp_lib.h"
+
+// This file implements the following soft-float comparison routines:
+//
+//   __eqdf2   __gedf2   __nedf2
+//   __ledf2   __gtdf2
+//   __ltdf2
+//   __nedf2
+//
+// The semantics of the routines grouped in each column are identical, so there
+// is a single implementation for each, and wrappers to provide the other names.
+//
+// The main routines behave as follows:
+//
+//   __ledf2(a,b) returns -1 if a < b
+//                         0 if a == b
+//                         1 if a > b
+//                         1 if either a or b is NaN
+//
+//   __gedf2(a,b) returns -1 if a < b
+//                         0 if a == b
+//                         1 if a > b
+//                        -1 if either a or b is NaN
+//
+//   __unorddf2(a,b) returns 0 if both a and b are numbers
+//                           1 if either a or b is NaN
+//
+// Note that __ledf2( ) and __gedf2( ) are identical except in their handling of
+// NaN values.
+
+enum LE_RESULT {
+    LE_LESS      = -1,
+    LE_EQUAL     =  0,
+    LE_GREATER   =  1,
+    LE_UNORDERED =  1
+};
+
+enum LE_RESULT __ledf2(fp_t a, fp_t b) {
+    
+    const srep_t aInt = toRep(a);
+    const srep_t bInt = toRep(b);
+    const rep_t aAbs = aInt & absMask;
+    const rep_t bAbs = bInt & absMask;
+    
+    // If either a or b is NaN, they are unordered.
+    if (aAbs > infRep || bAbs > infRep) return LE_UNORDERED;
+    
+    // If a and b are both zeros, they are equal.
+    if ((aAbs | bAbs) == 0) return LE_EQUAL;
+    
+    // If at least one of a and b is positive, we get the same result comparing
+    // a and b as signed integers as we would with a floating-point compare.
+    if ((aInt & bInt) >= 0) {
+        if (aInt < bInt) return LE_LESS;
+        else if (aInt == bInt) return LE_EQUAL;
+        else return LE_GREATER;
+    }
+    
+    // Otherwise, both are negative, so we need to flip the sense of the
+    // comparison to get the correct result.  (This assumes a twos- or ones-
+    // complement integer representation; if integers are represented in a
+    // sign-magnitude representation, then this flip is incorrect).
+    else {
+        if (aInt > bInt) return LE_LESS;
+        else if (aInt == bInt) return LE_EQUAL;
+        else return LE_GREATER;
+    }
+}
+
+
+enum GE_RESULT {
+    GE_LESS      = -1,
+    GE_EQUAL     =  0,
+    GE_GREATER   =  1,
+    GE_UNORDERED = -1   // Note: different from LE_UNORDERED
+};
+
+enum GE_RESULT __gedf2(fp_t a, fp_t b) {
+    
+    const srep_t aInt = toRep(a);
+    const srep_t bInt = toRep(b);
+    const rep_t aAbs = aInt & absMask;
+    const rep_t bAbs = bInt & absMask;
+    
+    if (aAbs > infRep || bAbs > infRep) return GE_UNORDERED;
+    if ((aAbs | bAbs) == 0) return GE_EQUAL;
+    if ((aInt & bInt) >= 0) {
+        if (aInt < bInt) return GE_LESS;
+        else if (aInt == bInt) return GE_EQUAL;
+        else return GE_GREATER;
+    } else {
+        if (aInt > bInt) return GE_LESS;
+        else if (aInt == bInt) return GE_EQUAL;
+        else return GE_GREATER;
+    }
+}
+
+int __unorddf2(fp_t a, fp_t b) {
+    const rep_t aAbs = toRep(a) & absMask;
+    const rep_t bAbs = toRep(b) & absMask;
+    return aAbs > infRep || bAbs > infRep;
+}
+
+enum LE_RESULT __eqdf2(fp_t a, fp_t b) {
+    return __ledf2(a, b);
+}
+
+enum LE_RESULT __ltdf2(fp_t a, fp_t b) {
+    return __ledf2(a, b);
+}
+
+enum LE_RESULT __nedf2(fp_t a, fp_t b) {
+    return __ledf2(a, b);
+}
+
+enum GE_RESULT __gtdf2(fp_t a, fp_t b) {
+    return __gedf2(a, b);
+}
+

Added: compiler-rt/trunk/lib/comparesf2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/comparesf2.c?rev=107400&view=auto
==============================================================================
--- compiler-rt/trunk/lib/comparesf2.c (added)
+++ compiler-rt/trunk/lib/comparesf2.c Thu Jul  1 10:52:42 2010
@@ -0,0 +1,133 @@
+//===-- lib/comparesf2.c - Single-precision comparisons -----------*- C -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the following soft-fp_t comparison routines:
+//
+//   __eqsf2   __gesf2   __nesf2
+//   __lesf2   __gtsf2
+//   __ltsf2
+//   __nesf2
+//
+// The semantics of the routines grouped in each column are identical, so there
+// is a single implementation for each, and wrappers to provide the other names.
+//
+// The main routines behave as follows:
+//
+//   __lesf2(a,b) returns -1 if a < b
+//                         0 if a == b
+//                         1 if a > b
+//                         1 if either a or b is NaN
+//
+//   __gesf2(a,b) returns -1 if a < b
+//                         0 if a == b
+//                         1 if a > b
+//                        -1 if either a or b is NaN
+//
+//   __unordsf2(a,b) returns 0 if both a and b are numbers
+//                           1 if either a or b is NaN
+//
+// Note that __lesf2( ) and __gesf2( ) are identical except in their handling of
+// NaN values.
+//
+//===----------------------------------------------------------------------===//
+
+#define SINGLE_PRECISION
+#include "fp_lib.h"
+
+enum LE_RESULT {
+    LE_LESS      = -1,
+    LE_EQUAL     =  0,
+    LE_GREATER   =  1,
+    LE_UNORDERED =  1
+};
+
+enum LE_RESULT __lesf2(fp_t a, fp_t b) {
+    
+    const srep_t aInt = toRep(a);
+    const srep_t bInt = toRep(b);
+    const rep_t aAbs = aInt & absMask;
+    const rep_t bAbs = bInt & absMask;
+    
+    // If either a or b is NaN, they are unordered.
+    if (aAbs > infRep || bAbs > infRep) return LE_UNORDERED;
+    
+    // If a and b are both zeros, they are equal.
+    if ((aAbs | bAbs) == 0) return LE_EQUAL;
+    
+    // If at least one of a and b is positive, we get the same result comparing
+    // a and b as signed integers as we would with a fp_ting-point compare.
+    if ((aInt & bInt) >= 0) {
+        if (aInt < bInt) return LE_LESS;
+        else if (aInt == bInt) return LE_EQUAL;
+        else return LE_GREATER;
+    }
+    
+    // Otherwise, both are negative, so we need to flip the sense of the
+    // comparison to get the correct result.  (This assumes a twos- or ones-
+    // complement integer representation; if integers are represented in a
+    // sign-magnitude representation, then this flip is incorrect).
+    else {
+        if (aInt > bInt) return LE_LESS;
+        else if (aInt == bInt) return LE_EQUAL;
+        else return LE_GREATER;
+    }
+}
+
+
+enum GE_RESULT {
+    GE_LESS      = -1,
+    GE_EQUAL     =  0,
+    GE_GREATER   =  1,
+    GE_UNORDERED = -1   // Note: different from LE_UNORDERED
+};
+
+enum GE_RESULT __gesf2(fp_t a, fp_t b) {
+    
+    const srep_t aInt = toRep(a);
+    const srep_t bInt = toRep(b);
+    const rep_t aAbs = aInt & absMask;
+    const rep_t bAbs = bInt & absMask;
+    
+    if (aAbs > infRep || bAbs > infRep) return GE_UNORDERED;
+    if ((aAbs | bAbs) == 0) return GE_EQUAL;
+    if ((aInt & bInt) >= 0) {
+        if (aInt < bInt) return GE_LESS;
+        else if (aInt == bInt) return GE_EQUAL;
+        else return GE_GREATER;
+    } else {
+        if (aInt > bInt) return GE_LESS;
+        else if (aInt == bInt) return GE_EQUAL;
+        else return GE_GREATER;
+    }
+}
+
+int __unordsf2(fp_t a, fp_t b) {
+    const rep_t aAbs = toRep(a) & absMask;
+    const rep_t bAbs = toRep(b) & absMask;
+    return aAbs > infRep || bAbs > infRep;
+}
+
+// The following are just other names for the forgoing routines.
+
+enum LE_RESULT __eqsf2(fp_t a, fp_t b) {
+    return __lesf2(a, b);
+}
+
+enum LE_RESULT __ltsf2(fp_t a, fp_t b) {
+    return __lesf2(a, b);
+}
+
+enum LE_RESULT __nesf2(fp_t a, fp_t b) {
+    return __lesf2(a, b);
+}
+
+enum GE_RESULT __gtsf2(fp_t a, fp_t b) {
+    return __gesf2(a, b);
+}
+

Added: compiler-rt/trunk/lib/extendsfdf2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/extendsfdf2.c?rev=107400&view=auto
==============================================================================
--- compiler-rt/trunk/lib/extendsfdf2.c (added)
+++ compiler-rt/trunk/lib/extendsfdf2.c Thu Jul  1 10:52:42 2010
@@ -0,0 +1,133 @@
+/*
+ *                     The LLVM Compiler Infrastructure
+ *
+ * This file is distributed under the University of Illinois Open Source
+ * License. See LICENSE.TXT for details.
+ */
+
+#include <stdint.h>
+#include <limits.h>
+
+// This file implements a fairly generic conversion from a narrower to a wider
+// IEEE-754 floating-point type.  The next 10 lines parametrize which types
+// are to be used as the source and destination, the actual name used for
+// the conversion, and a suitable CLZ function for the source representation
+// type.
+//
+// This routine can be trivially adapted to support conversions from 
+// half-precision or to quad-precision. It does not support types that don't
+// use the usual IEEE-754 interchange formats; specifically, some work would be
+// needed to adapt it to (for example) the Intel 80-bit format or PowerPC
+// double-double format.
+//
+// Note please, however, that this implementation is only intended to support
+// *widening* operations; if you need to convert to a *narrower* floating-point
+// type (e.g. double -> float), then this routine will not do what you want it
+// to.
+//
+// It also requires that integer types at least as large as both formats
+// are available on the target platform; this may pose a problem when trying
+// to add support for quad on some 32-bit systems, for example.  You also may
+// run into trouble finding an appropriate CLZ function for wide source types;
+// you will likely need to roll your own on some platforms.
+//
+// Finally, the following assumptions are made:
+//
+// 1. floating-point types and integer types have the same endianness on the
+//    target platform
+//
+// 2. quiet NaNs, if supported, are indicated by the leading bit of the
+//    significand field being set
+
+#define widen __extendsfdf2
+
+typedef float src_t;
+typedef uint32_t src_rep_t;
+#define SRC_REP_C UINT32_C
+static const int srcSigBits = 23;
+#define src_rep_t_clz __builtin_clz
+
+typedef double dst_t;
+typedef uint64_t dst_rep_t;
+#define DST_REP_C UINT64_C
+static const int dstSigBits = 52;
+
+// End of specialization parameters.  Two helper routines for conversion to and
+// from the representation of floating-point data as integer values follow.
+
+static inline src_rep_t srcToRep(src_t x) {
+    const union { src_t f; src_rep_t i; } rep = {.f = x};
+    return rep.i;
+}
+
+static inline dst_t dstFromRep(dst_rep_t x) {
+    const union { dst_t f; dst_rep_t i; } rep = {.i = x};
+    return rep.f;
+}
+
+// End helper routines.  Conversion implementation follows.
+
+dst_t widen(src_t a) {
+    
+    // Various constants whose values follow from the type parameters.
+    // Any reasonable optimizer will fold and propagate all of these.
+    const int srcBits = sizeof(src_t)*CHAR_BIT;
+    const int srcExpBits = srcBits - srcSigBits - 1;
+    const int srcInfExp = (1 << srcExpBits) - 1;
+    const int srcExpBias = srcInfExp >> 1;
+    const src_rep_t srcMinNormal = SRC_REP_C(1) << srcSigBits;
+    const src_rep_t srcInfinity = (src_rep_t)srcInfExp << srcSigBits;
+    const src_rep_t srcSignMask = SRC_REP_C(1) << (srcSigBits + srcExpBits);
+    const src_rep_t srcAbsMask = srcSignMask - 1;
+    const src_rep_t srcQNaN = SRC_REP_C(1) << (srcSigBits - 1);
+    const src_rep_t srcNaNCode = srcQNaN - 1;
+    const int dstBits = sizeof(dst_t)*CHAR_BIT;
+    const int dstExpBits = dstBits - dstSigBits - 1;
+    const int dstInfExp = (1 << dstExpBits) - 1;
+    const int dstExpBias = dstInfExp >> 1;
+    const dst_rep_t dstMinNormal = DST_REP_C(1) << dstSigBits;
+    
+    // Break a into a sign and representation of the absolute value
+    src_rep_t aRep = srcToRep(a);
+    src_rep_t aAbs = aRep & srcAbsMask;
+    src_rep_t sign = aRep & srcSignMask;
+    dst_rep_t absResult;
+    
+    if (aAbs - srcMinNormal < srcInfinity - srcMinNormal) {
+        // a is a normal number.
+        // Extend to the destination type by shifting the significand and
+        // exponent into the proper position and rebiasing the exponent.
+        absResult = (dst_rep_t)aAbs << (dstSigBits - srcSigBits);
+        absResult += (dst_rep_t)(dstExpBias - srcExpBias) << dstSigBits;
+    }
+    
+    else if (aAbs >= srcInfinity) {
+        // a is NaN or infinity.
+        // Conjure the result by beginning with infinity, then setting the qNaN
+        // bit if appropriate and then by right-aligning the rest of the
+        // trailing NaN payload field.
+        absResult = (dst_rep_t)dstInfExp << dstSigBits;
+        absResult |= (dst_rep_t)(aAbs & srcQNaN) << (dstSigBits - srcSigBits);
+        absResult |= (aAbs & srcNaNCode);
+    }
+    
+    else if (aAbs) {
+        // a is denormal.
+        // renormalize the significand and clear the leading bit, then insert
+        // the correct adjusted exponent in the destination type.
+        const int scale = src_rep_t_clz(aAbs) - src_rep_t_clz(srcMinNormal);
+        absResult = (dst_rep_t)aAbs << (dstSigBits - srcSigBits + scale);
+        absResult ^= dstMinNormal;
+        const int resultExponent = dstExpBias - srcExpBias - scale + 1;
+        absResult |= (dst_rep_t)resultExponent << dstSigBits;
+    }
+
+    else {
+        // a is zero.
+        absResult = 0;
+    }
+    
+    // Apply the signbit to (dst_t)abs(a).
+    dst_rep_t result = absResult | (dst_rep_t)sign << (dstBits - srcBits);
+    return dstFromRep(result);
+}

Added: compiler-rt/trunk/lib/fp_lib.h
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/fp_lib.h?rev=107400&view=auto
==============================================================================
--- compiler-rt/trunk/lib/fp_lib.h (added)
+++ compiler-rt/trunk/lib/fp_lib.h Thu Jul  1 10:52:42 2010
@@ -0,0 +1,123 @@
+// This file is a configuration header for soft-float routines in compiler-rt.
+// This file does not provide any part of the compiler-rt interface.
+
+// Assumes that float and double correspond to the IEEE-754 binary32 and
+// binary64 types, respectively.
+
+#ifndef FP_LIB_HEADER
+#define FP_LIB_HEADER
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <limits.h>
+
+#if defined SINGLE_PRECISION
+#if 0
+#pragma mark single definitions
+#endif
+
+typedef uint32_t rep_t;
+typedef int32_t srep_t;
+typedef float fp_t;
+#define REP_C UINT32_C
+#define significandBits 23
+
+static inline int rep_clz(rep_t a) {
+    return __builtin_clz(a);
+}
+
+#elif defined DOUBLE_PRECISION
+#if 0
+#pragma mark double definitions
+#endif
+
+typedef uint64_t rep_t;
+typedef int64_t srep_t;
+typedef double fp_t;
+#define REP_C UINT64_C
+#define significandBits 52
+
+static inline int rep_clz(rep_t a) {
+#if defined __LP64__
+    return __builtin_clzl(a);
+#else
+    if (a & REP_C(0xffffffff00000000))
+        return 32 + __builtin_clz(a >> 32);
+    else 
+        return __builtin_clz(a & REP_C(0xffffffff));
+#endif
+}
+
+#else
+#error Either SINGLE_PRECISION or DOUBLE_PRECISION must be defined.
+#endif
+
+#if 0
+#pragma mark -
+#pragma mark integer constants
+#endif
+
+#define typeWidth       (sizeof(rep_t)*CHAR_BIT)
+#define exponentBits    (typeWidth - significandBits - 1)
+#define maxExponent     ((1 << exponentBits) - 1)
+#define exponentBias    (maxExponent >> 1)
+
+#if 0
+#pragma mark -
+#pragma mark rep_t constants
+#endif
+
+#define implicitBit     (REP_C(1) << significandBits)
+#define significandMask (implicitBit - 1U)
+#define signBit         (REP_C(1) << (significandBits + exponentBits))
+#define absMask         (signBit - 1U)
+#define exponentMask    (absMask ^ significandMask)
+#define oneRep          ((rep_t)exponentBias << significandBits)
+#define infRep          exponentMask
+#define quietBit        (implicitBit >> 1)
+#define qnanRep         (exponentMask | quietBit)
+
+#if 0
+#pragma mark -
+#pragma mark generic functions
+#endif
+
+static inline rep_t toRep(fp_t x) {
+    const union { fp_t f; rep_t i; } rep = {.f = x};
+    return rep.i;
+}
+
+static inline fp_t fromRep(rep_t x) {
+    const union { fp_t f; rep_t i; } rep = {.i = x};
+    return rep.f;
+}
+
+static inline int normalize(rep_t *significand) {
+    const int shift = rep_clz(*significand) - rep_clz(implicitBit);
+    *significand <<= shift;
+    return 1 - shift;
+}
+
+static inline void wideLeftShift(rep_t *hi, rep_t *lo, int count) {
+    *hi = *hi << count | *lo >> (typeWidth - count);
+    *lo = *lo << count;
+}
+
+static inline void wideRightShiftWithSticky(rep_t *hi, rep_t *lo, int count) {
+    if (count < typeWidth) {
+        const bool sticky = *lo << (typeWidth - count);
+        *lo = *hi << (typeWidth - count) | *lo >> count | sticky;
+        *hi = *hi >> count;
+    }
+    else if (count < 2*typeWidth) {
+        const bool sticky = *hi << (2*typeWidth - count) | *lo;
+        *lo = *hi >> (count - typeWidth) | sticky;
+        *hi = 0;
+    } else {
+        const bool sticky = *hi | *lo;
+        *lo = sticky;
+        *hi = 0;
+    }
+}
+
+#endif // FP_LIB_HEADER

Added: compiler-rt/trunk/lib/muldf3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/muldf3.c?rev=107400&view=auto
==============================================================================
--- compiler-rt/trunk/lib/muldf3.c (added)
+++ compiler-rt/trunk/lib/muldf3.c Thu Jul  1 10:52:42 2010
@@ -0,0 +1,135 @@
+/*
+ *                     The LLVM Compiler Infrastructure
+ *
+ * This file is distributed under the University of Illinois Open Source
+ * License. See LICENSE.TXT for details.
+ */
+
+#define DOUBLE_PRECISION
+#include "fp_lib.h"
+
+// This file implements double-precision soft-float multiplication with the
+// IEEE-754 default rounding (to nearest, ties to even).
+
+#define loWord(a) (a & 0xffffffffU)
+#define hiWord(a) (a >> 32)
+
+// 64x64 -> 128 wide multiply for platforms that don't have such an operation;
+// some 64-bit platforms have this operation, but they tend to have hardware
+// floating-point, so we don't bother with a special case for them here.
+static inline void wideMultiply(rep_t a, rep_t b, rep_t *hi, rep_t *lo) {
+    // Each of the component 32x32 -> 64 products
+    const uint64_t plolo = loWord(a) * loWord(b);
+    const uint64_t plohi = loWord(a) * hiWord(b);
+    const uint64_t philo = hiWord(a) * loWord(b);
+    const uint64_t phihi = hiWord(a) * hiWord(b);
+    // Sum terms that compute to lo in a way that allows us to get the carry
+    const uint64_t r0 = loWord(plolo);
+    const uint64_t r1 = hiWord(plolo) + loWord(plohi) + loWord(philo);
+    *lo = r0 + (r1 << 32);
+    // Sum terms contributing to hi with the carry from lo
+    *hi = hiWord(plohi) + hiWord(philo) + hiWord(r1) + phihi;
+}
+
+fp_t __muldf3(fp_t a, fp_t b) {
+    
+    const unsigned int aExponent = toRep(a) >> significandBits & maxExponent;
+    const unsigned int bExponent = toRep(b) >> significandBits & maxExponent;
+    const rep_t productSign = (toRep(a) ^ toRep(b)) & signBit;
+    
+    rep_t aSignificand = toRep(a) & significandMask;
+    rep_t bSignificand = toRep(b) & significandMask;
+    int scale = 0;
+    
+    // Detect if a or b is zero, denormal, infinity, or NaN.
+    if (aExponent-1U >= maxExponent-1U || bExponent-1U >= maxExponent-1U) {
+        
+        const rep_t aAbs = toRep(a) & absMask;
+        const rep_t bAbs = toRep(b) & absMask;
+        
+        // NaN * anything = qNaN
+        if (aAbs > infRep) return fromRep(toRep(a) | quietBit);
+        // anything * NaN = qNaN
+        if (bAbs > infRep) return fromRep(toRep(b) | quietBit);
+        
+        if (aAbs == infRep) {
+            // infinity * non-zero = +/- infinity
+            if (bAbs) return fromRep(aAbs | productSign);
+            // infinity * zero = NaN
+            else return fromRep(qnanRep);
+        }
+        
+        if (bAbs == infRep) {
+            // non-zero * infinity = +/- infinity
+            if (aAbs) return fromRep(bAbs | productSign);
+            // zero * infinity = NaN
+            else return fromRep(qnanRep);
+        }
+        
+        // zero * anything = +/- zero
+        if (!aAbs) return fromRep(productSign);
+        // anything * zero = +/- zero
+        if (!bAbs) return fromRep(productSign);
+        
+        // one or both of a or b is denormal, the other (if applicable) is a
+        // normal number.  Renormalize one or both of a and b, and set scale to
+        // include the necessary exponent adjustment.
+        if (aAbs < implicitBit) scale += normalize(&aSignificand);
+        if (bAbs < implicitBit) scale += normalize(&bSignificand);
+    }
+    
+    // Or in the implicit significand bit.  (If we fell through from the
+    // denormal path it was already set by normalize( ), but setting it twice
+    // won't hurt anything.)
+    aSignificand |= implicitBit;
+    bSignificand |= implicitBit;
+    
+    // Get the significand of a*b.  Before multiplying the significands, shift
+    // one of them left to left-align it in the field.  Thus, the product will
+    // have (exponentBits + 2) integral digits, all but two of which must be
+    // zero.  Normalizing this result is just a conditional left-shift by one
+    // and bumping the exponent accordingly.
+    rep_t productHi, productLo;
+    wideMultiply(aSignificand, bSignificand << exponentBits,
+                 &productHi, &productLo);
+    
+    int productExponent = aExponent + bExponent - exponentBias + scale;
+    
+    // Normalize the significand, adjust exponent if needed.
+    if (productHi & implicitBit) productExponent++;
+    else wideLeftShift(&productHi, &productLo, 1);
+    
+    // If we have overflowed the type, return +/- infinity.
+    if (productExponent >= maxExponent) return fromRep(infRep | productSign);
+    
+    if (productExponent <= 0) {
+        // Result is denormal before rounding
+        //
+        // If the result is so small that it just underflows to zero, return
+        // a zero of the appropriate sign.  Mathematically there is no need to
+        // handle this case separately, but we make it a special case to
+        // simplify the shift logic.
+        const int shift = 1 - productExponent;
+        if (shift >= typeWidth) return fromRep(productSign);
+        
+        // Otherwise, shift the significand of the result so that the round
+        // bit is the high bit of productLo.
+        wideRightShiftWithSticky(&productHi, &productLo, shift);
+    }
+    
+    else {
+        // Result is normal before rounding; insert the exponent.
+        productHi &= significandMask;
+        productHi |= (rep_t)productExponent << significandBits;
+    }
+    
+    // Insert the sign of the result:
+    productHi |= productSign;
+    
+    // Final rounding.  The final result may overflow to infinity, or underflow
+    // to zero, but those are the correct results in those cases.  We use the
+    // default IEEE-754 round-to-nearest, ties-to-even rounding mode.
+    if (productLo > signBit) productHi++;
+    if (productLo == signBit) productHi += productHi & 1;
+    return fromRep(productHi);
+}

Added: compiler-rt/trunk/lib/mulsf3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/mulsf3.c?rev=107400&view=auto
==============================================================================
--- compiler-rt/trunk/lib/mulsf3.c (added)
+++ compiler-rt/trunk/lib/mulsf3.c Thu Jul  1 10:52:42 2010
@@ -0,0 +1,112 @@
+/*
+ *                     The LLVM Compiler Infrastructure
+ *
+ * This file is distributed under the University of Illinois Open Source
+ * License. See LICENSE.TXT for details.
+ */
+
+#define SINGLE_PRECISION
+#include "fp_lib.h"
+
+// This file implements single-precision soft-float multiplication with the
+// IEEE-754 default rounding (to nearest, ties to even).
+
+// 32x32 --> 64 bit multiply
+static inline void wideMultiply(rep_t a, rep_t b, rep_t *hi, rep_t *lo) {
+    const uint64_t product = (uint64_t)a*b;
+    *hi = product >> 32;
+    *lo = product;
+}
+
+fp_t __mulsf3(fp_t a, fp_t b) {
+    
+    const unsigned int aExponent = toRep(a) >> significandBits & maxExponent;
+    const unsigned int bExponent = toRep(b) >> significandBits & maxExponent;
+    const rep_t productSign = (toRep(a) ^ toRep(b)) & signBit;
+    
+    rep_t aSignificand = toRep(a) & significandMask;
+    rep_t bSignificand = toRep(b) & significandMask;
+    int scale = 0;
+    
+    // Detect if a or b is zero, denormal, infinity, or NaN.
+    if (aExponent-1U >= maxExponent-1U || bExponent-1U >= maxExponent-1U) {
+        
+        const rep_t aAbs = toRep(a) & absMask;
+        const rep_t bAbs = toRep(b) & absMask;
+        
+        // NaN * anything = qNaN
+        if (aAbs > infRep) return fromRep(toRep(a) | quietBit);
+        // anything * NaN = qNaN
+        if (bAbs > infRep) return fromRep(toRep(b) | quietBit);
+        
+        if (aAbs == infRep) {
+            // infinity * non-zero = +/- infinity
+            if (bAbs) return fromRep(aAbs | productSign);
+            // infinity * zero = NaN
+            else return fromRep(qnanRep);
+        }
+        
+        if (bAbs == infRep) {
+            // non-zero * infinity = +/- infinity
+            if (aAbs) return fromRep(bAbs | productSign);
+            // zero * infinity = NaN
+            else return fromRep(qnanRep);
+        }
+        
+        // zero * anything = +/- zero
+        if (!aAbs) return fromRep(productSign);
+        // anything * zero = +/- zero
+        if (!bAbs) return fromRep(productSign);
+        
+        // one or both of a or b is denormal, the other (if applicable) is a
+        // normal number.  Renormalize one or both of a and b, and set scale to
+        // include the necessary exponent adjustment.
+        if (aAbs < implicitBit) scale += normalize(&aSignificand);
+        if (bAbs < implicitBit) scale += normalize(&bSignificand);
+    }
+    
+    // Or in the implicit significand bit.  (If we fell through from the
+    // denormal path it was already set by normalize( ), but setting it twice
+    // won't hurt anything.)
+    aSignificand |= implicitBit;
+    bSignificand |= implicitBit;
+    
+    // Get the significand of a*b.  Before multiplying the significands, shift
+    // one of them left to left-align it in the field.  Thus, the product will
+    // have (exponentBits + 2) integral digits, all but two of which must be
+    // zero.  Normalizing this result is just a conditional left-shift by one
+    // and bumping the exponent accordingly.
+    rep_t productHi, productLo;
+    wideMultiply(aSignificand, bSignificand << exponentBits,
+                 &productHi, &productLo);
+    
+    int productExponent = aExponent + bExponent - exponentBias + scale;
+    
+    // Normalize the significand, adjust exponent if needed.
+    if (productHi & implicitBit) productExponent++;
+    else wideLeftShift(&productHi, &productLo, 1);
+    
+    // If we have overflowed the type, return +/- infinity.
+    if (productExponent >= maxExponent) return fromRep(infRep | productSign);
+    
+    if (productExponent <= 0) {
+        // Result is denormal before rounding, the exponent is zero and we
+        // need to shift the significand.
+        wideRightShiftWithSticky(&productHi, &productLo, 1 - productExponent);
+    }
+    
+    else {
+        // Result is normal before rounding; insert the exponent.
+        productHi &= significandMask;
+        productHi |= (rep_t)productExponent << significandBits;
+    }
+    
+    // Insert the sign of the result:
+    productHi |= productSign;
+    
+    // Final rounding.  The final result may overflow to infinity, or underflow
+    // to zero, but those are the correct results in those cases.
+    if (productLo > signBit) productHi++;
+    if (productLo == signBit) productHi += productHi & 1;
+    return fromRep(productHi);
+}

Added: compiler-rt/trunk/lib/negdf2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/negdf2.c?rev=107400&view=auto
==============================================================================
--- compiler-rt/trunk/lib/negdf2.c (added)
+++ compiler-rt/trunk/lib/negdf2.c Thu Jul  1 10:52:42 2010
@@ -0,0 +1,13 @@
+/*
+ *                     The LLVM Compiler Infrastructure
+ *
+ * This file is distributed under the University of Illinois Open Source
+ * License. See LICENSE.TXT for details.
+ */
+
+#define DOUBLE_PRECISION
+#include "fp_lib.h"
+
+fp_t __negsf2(fp_t a) {
+    return fromRep(toRep(a) ^ signBit);
+}

Added: compiler-rt/trunk/lib/negsf2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/negsf2.c?rev=107400&view=auto
==============================================================================
--- compiler-rt/trunk/lib/negsf2.c (added)
+++ compiler-rt/trunk/lib/negsf2.c Thu Jul  1 10:52:42 2010
@@ -0,0 +1,13 @@
+/*
+ *                     The LLVM Compiler Infrastructure
+ *
+ * This file is distributed under the University of Illinois Open Source
+ * License. See LICENSE.TXT for details.
+ */
+
+#define SINGLE_PRECISION
+#include "fp_lib.h"
+
+fp_t __negsf2(fp_t a) {
+    return fromRep(toRep(a) ^ signBit);
+}




From daniel at zuster.org  Thu Jul  1 11:14:51 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 01 Jul 2010 16:14:51 -0000
Subject: [llvm-commits] [zorg] r107401 - /zorg/trunk/lnt/lnt/tests/nt.py
Message-ID: <20100701161451.9D9532A6C12C@llvm.org>

Author: ddunbar
Date: Thu Jul  1 11:14:51 2010
New Revision: 107401

URL: http://llvm.org/viewvc/llvm-project?rev=107401&view=rev
Log:
LNT/nt: Add --build-mode option, to allow running tests in configurations other
than 'Release'.

Modified:
    zorg/trunk/lnt/lnt/tests/nt.py

Modified: zorg/trunk/lnt/lnt/tests/nt.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/tests/nt.py?rev=107401&r1=107400&r2=107401&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/tests/nt.py (original)
+++ zorg/trunk/lnt/lnt/tests/nt.py Thu Jul  1 11:14:51 2010
@@ -50,9 +50,35 @@
         'TARGET_LLVMGXX' : opts.cxx_under_test,
         'TARGET_FLAGS' : ' '.join(target_flags),
         'TARGET_LLCFLAGS' : ' '.join(target_llcflags),
-        'ENABLE_OPTIMIZED' : '1',
         }
 
+    # Pick apart the build mode.
+    build_mode = opts.build_mode
+    if build_mode.startswith("Debug"):
+        build_mode = build_mode[len("Debug"):]
+        make_variables['ENABLE_OPTIMIZED'] = '0'
+    elif build_mode.startswith("Unoptimized"):
+        build_mode = build_mode[len("Unoptimized"):]
+        make_variables['ENABLE_OPTIMIZED'] = '0'
+    elif build_mode.startswith("Release"):
+        build_mode = build_mode[len("Release"):]
+        make_variables['ENABLE_OPTIMIZED'] = '1'
+    else:
+        fatal('invalid build mode: %r' % opts.build_mode)
+
+    while build_mode:
+        for (name,key) in (('-Asserts', 'DISABLE_ASSERTIONS'),
+                           ('+Checks', 'ENABLE_EXPENSIVE_CHECKS'),
+                           ('+Coverage', 'ENABLE_COVERAGE'),
+                           ('+Debug', 'DEBUG_SYMBOLS'),
+                           ('+Profile', 'ENABLE_PROFILING')):
+            if build_mode.startswith(name):
+                build_mode = build_mode[len(name):]
+                make_variables[key] = '1'
+                break
+        else:
+            fatal('invalid build mode: %r' % opts.build_mode)
+
     # Set the optimization level options.
     make_variables['OPTFLAGS'] = opts.optimize_option
     if opts.optimize_option == '-Os':
@@ -529,7 +555,7 @@
         group.add_option("", "--relocation-model", dest="relocation_model",
                          help=("Set -relocation-model in TARGET_LLCFLAGS "
                                 "[%default]"),
-                         type="str", default=None, metavar="MODEL")
+                         type=str, default=None, metavar="MODEL")
         group.add_option("", "--disable-fp-elim", dest="disable_fp_elim",
                          help=("Set -disable-fp-elim in TARGET_LLCFLAGS"),
                          action="store_true", default=False)
@@ -543,6 +569,10 @@
         parser.add_option_group(group)
 
         group = OptionGroup(parser, "Test Selection")
+        group.add_option("", "--build-mode", dest="build_mode", metavar="NAME",
+                         help="Select the LLVM build mode to use [%default]",
+                         type=str, action="store", default='Release')
+
         group.add_option("", "--simple", dest="test_simple",
                          help="Use TEST=simple instead of TEST=nightly",
                          action="store_true", default=False)




From bruno.cardoso at gmail.com  Thu Jul  1 12:08:18 2010
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Thu, 01 Jul 2010 17:08:18 -0000
Subject: [llvm-commits] [llvm] r107404 - in /llvm/trunk:
 lib/Target/X86/X86InstrSSE.td test/MC/AsmParser/X86/x86_32-encoding.s
 test/MC/AsmParser/X86/x86_64-encoding.s
Message-ID: <20100701170818.A42732A6C12C@llvm.org>

Author: bruno
Date: Thu Jul  1 12:08:18 2010
New Revision: 107404

URL: http://llvm.org/viewvc/llvm-project?rev=107404&view=rev
Log:
Add AVX SSE3 packed addsub instructions

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
    llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=107404&r1=107403&r2=107404&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Jul  1 12:08:18 2010
@@ -3237,33 +3237,44 @@
 }
 
 //===---------------------------------------------------------------------===//
-// SSE3 Instructions
+// SSE3 - Arithmetic
 //===---------------------------------------------------------------------===//
 
-// Arithmetic
-let Constraints = "$src1 = $dst" in {
-  def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
-                        (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
-                        "addsubps\t{$src2, $dst|$dst, $src2}",
-                        [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
-                                           VR128:$src2))]>;
-  def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
-                        (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
-                        "addsubps\t{$src2, $dst|$dst, $src2}",
-                        [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
-                                           (memop addr:$src2)))]>;
-  def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
-                       (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
-                       "addsubpd\t{$src2, $dst|$dst, $src2}",
-                       [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
-                                          VR128:$src2))]>;
-  def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
-                       (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
-                       "addsubpd\t{$src2, $dst|$dst, $src2}",
-                       [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
-                                          (memop addr:$src2)))]>;
+multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, bit Is2Addr = 1> {
+  def rr : I<0xD0, MRMSrcReg,
+       (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
+       !if(Is2Addr,
+           !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
+           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
+       [(set VR128:$dst, (Int VR128:$src1,
+                          VR128:$src2))]>;
+  def rm : I<0xD0, MRMSrcMem,
+       (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
+       !if(Is2Addr,
+           !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
+           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
+       [(set VR128:$dst, (Int VR128:$src1,
+                          (memop addr:$src2)))]>;
+
+}
+
+let isAsmParserOnly = 1, Predicates = [HasSSE3, HasAVX],
+  ExeDomain = SSEPackedDouble in {
+  defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", 0>, XD,
+                              VEX_4V;
+  defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", 0>, OpSize,
+                              VEX_4V;
+}
+let Constraints = "$src1 = $dst", Predicates = [HasSSE3],
+    ExeDomain = SSEPackedDouble in {
+  defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps">, XD;
+  defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd">, TB, OpSize;
 }
 
+//===---------------------------------------------------------------------===//
+// SSE3 Instructions
+//===---------------------------------------------------------------------===//
+
 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
                    "lddqu\t{$src, $dst|$dst, $src}",
                    [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s?rev=107404&r1=107403&r2=107404&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s Thu Jul  1 12:08:18 2010
@@ -11566,3 +11566,19 @@
 // CHECK: encoding: [0xc5,0xfb,0x12,0x10]
           vmovddup  (%eax), %xmm2
 
+// CHECK: vaddsubps  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xeb,0xd0,0xd9]
+          vaddsubps  %xmm1, %xmm2, %xmm3
+
+// CHECK: vaddsubps  (%eax), %xmm1, %xmm2
+// CHECK: encoding: [0xc5,0xf3,0xd0,0x10]
+          vaddsubps  (%eax), %xmm1, %xmm2
+
+// CHECK: vaddsubpd  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0xd0,0xd9]
+          vaddsubpd  %xmm1, %xmm2, %xmm3
+
+// CHECK: vaddsubpd  (%eax), %xmm1, %xmm2
+// CHECK: encoding: [0xc5,0xf1,0xd0,0x10]
+          vaddsubpd  (%eax), %xmm1, %xmm2
+

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s?rev=107404&r1=107403&r2=107404&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s Thu Jul  1 12:08:18 2010
@@ -1614,3 +1614,19 @@
 // CHECK: encoding: [0xc5,0x7b,0x12,0x20]
           vmovddup  (%rax), %xmm12
 
+// CHECK: vaddsubps  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x1b,0xd0,0xeb]
+          vaddsubps  %xmm11, %xmm12, %xmm13
+
+// CHECK: vaddsubps  (%rax), %xmm11, %xmm12
+// CHECK: encoding: [0xc5,0x23,0xd0,0x20]
+          vaddsubps  (%rax), %xmm11, %xmm12
+
+// CHECK: vaddsubpd  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0xd0,0xeb]
+          vaddsubpd  %xmm11, %xmm12, %xmm13
+
+// CHECK: vaddsubpd  (%rax), %xmm11, %xmm12
+// CHECK: encoding: [0xc5,0x21,0xd0,0x20]
+          vaddsubpd  (%rax), %xmm11, %xmm12
+




From bruno.cardoso at gmail.com  Thu Jul  1 12:35:02 2010
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Thu, 01 Jul 2010 17:35:02 -0000
Subject: [llvm-commits] [llvm] r107405 - in /llvm/trunk:
 lib/Target/X86/X86InstrSSE.td test/MC/AsmParser/X86/x86_32-encoding.s
 test/MC/AsmParser/X86/x86_64-encoding.s
Message-ID: <20100701173502.53E9B2A6C12C@llvm.org>

Author: bruno
Date: Thu Jul  1 12:35:02 2010
New Revision: 107405

URL: http://llvm.org/viewvc/llvm-project?rev=107405&view=rev
Log:
Move SSE3 Move patterns to a more appropriate section
Add AVX SSE3 packed horizontal and & sub instructions

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
    llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=107405&r1=107404&r2=107405&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Jul  1 12:35:02 2010
@@ -3221,10 +3221,20 @@
   defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
 
+// Move Unaligned Integer
+let isAsmParserOnly = 1 in
+  def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
+                     "vlddqu\t{$src, $dst|$dst, $src}",
+                     [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
+def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
+                   "lddqu\t{$src, $dst|$dst, $src}",
+                   [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
+
 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
                    (undef)),
           (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
 
+// Several Move patterns
 let AddedComplexity = 5 in {
 def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
           (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
@@ -3236,6 +3246,22 @@
           (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
 }
 
+// vector_shuffle v1, <undef> <1, 1, 3, 3>
+let AddedComplexity = 15 in
+def : Pat<(v4i32 (movshdup VR128:$src, (undef))),
+          (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
+let AddedComplexity = 20 in
+def : Pat<(v4i32 (movshdup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
+          (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
+
+// vector_shuffle v1, <undef> <0, 0, 2, 2>
+let AddedComplexity = 15 in
+  def : Pat<(v4i32 (movsldup VR128:$src, (undef))),
+            (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
+let AddedComplexity = 20 in
+  def : Pat<(v4i32 (movsldup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
+            (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
+
 //===---------------------------------------------------------------------===//
 // SSE3 - Arithmetic
 //===---------------------------------------------------------------------===//
@@ -3275,28 +3301,43 @@
 // SSE3 Instructions
 //===---------------------------------------------------------------------===//
 
-def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
-                   "lddqu\t{$src, $dst|$dst, $src}",
-                   [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
-
 // Horizontal ops
-class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
+class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId, bit Is2Addr = 1>
   : S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
+       !if(Is2Addr,
          !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
+         !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
          [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
-class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
+class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId, bit Is2Addr = 1>
   : S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
+       !if(Is2Addr,
          !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
+         !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
          [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (memop addr:$src2))))]>;
-class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
+class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId, bit Is2Addr = 1>
   : S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
-        !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
+       !if(Is2Addr,
+         !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
+         !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
         [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
-class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
+class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId, bit Is2Addr = 1>
   : S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
-        !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
+       !if(Is2Addr,
+         !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
+         !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
       [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (memopv2f64 addr:$src2))))]>;
 
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE3] in {
+  def VHADDPSrr : S3D_Intrr<0x7C, "vhaddps", int_x86_sse3_hadd_ps, 0>, VEX_4V;
+  def VHADDPSrm : S3D_Intrm<0x7C, "vhaddps", int_x86_sse3_hadd_ps, 0>, VEX_4V;
+  def VHADDPDrr : S3_Intrr <0x7C, "vhaddpd", int_x86_sse3_hadd_pd, 0>, VEX_4V;
+  def VHADDPDrm : S3_Intrm <0x7C, "vhaddpd", int_x86_sse3_hadd_pd, 0>, VEX_4V;
+  def VHSUBPSrr : S3D_Intrr<0x7D, "vhsubps", int_x86_sse3_hsub_ps, 0>, VEX_4V;
+  def VHSUBPSrm : S3D_Intrm<0x7D, "vhsubps", int_x86_sse3_hsub_ps, 0>, VEX_4V;
+  def VHSUBPDrr : S3_Intrr <0x7D, "vhsubpd", int_x86_sse3_hsub_pd, 0>, VEX_4V;
+  def VHSUBPDrm : S3_Intrm <0x7D, "vhsubpd", int_x86_sse3_hsub_pd, 0>, VEX_4V;
+}
+
 let Constraints = "$src1 = $dst" in {
   def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
   def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
@@ -3308,32 +3349,16 @@
   def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
 }
 
+//===---------------------------------------------------------------------===//
+// SSSE3 Instructions
+//===---------------------------------------------------------------------===//
+
 // Thread synchronization
 def MONITOR : I<0x01, MRM_C8, (outs), (ins), "monitor",
                 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
 def MWAIT   : I<0x01, MRM_C9, (outs), (ins), "mwait",
                 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
 
-// vector_shuffle v1, <undef> <1, 1, 3, 3>
-let AddedComplexity = 15 in
-def : Pat<(v4i32 (movshdup VR128:$src, (undef))),
-          (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
-let AddedComplexity = 20 in
-def : Pat<(v4i32 (movshdup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
-          (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
-
-// vector_shuffle v1, <undef> <0, 0, 2, 2>
-let AddedComplexity = 15 in
-  def : Pat<(v4i32 (movsldup VR128:$src, (undef))),
-            (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
-let AddedComplexity = 20 in
-  def : Pat<(v4i32 (movsldup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
-            (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
-
-//===---------------------------------------------------------------------===//
-// SSSE3 Instructions
-//===---------------------------------------------------------------------===//
-
 /// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8.
 multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr,
                               Intrinsic IntId64, Intrinsic IntId128> {

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s?rev=107405&r1=107404&r2=107405&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s Thu Jul  1 12:35:02 2010
@@ -11582,3 +11582,35 @@
 // CHECK: encoding: [0xc5,0xf1,0xd0,0x10]
           vaddsubpd  (%eax), %xmm1, %xmm2
 
+// CHECK: vhaddps  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xeb,0x7c,0xd9]
+          vhaddps  %xmm1, %xmm2, %xmm3
+
+// CHECK: vhaddps  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xeb,0x7c,0x18]
+          vhaddps  (%eax), %xmm2, %xmm3
+
+// CHECK: vhaddpd  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0x7c,0xd9]
+          vhaddpd  %xmm1, %xmm2, %xmm3
+
+// CHECK: vhaddpd  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0x7c,0x18]
+          vhaddpd  (%eax), %xmm2, %xmm3
+
+// CHECK: vhsubps  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xeb,0x7d,0xd9]
+          vhsubps  %xmm1, %xmm2, %xmm3
+
+// CHECK: vhsubps  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xeb,0x7d,0x18]
+          vhsubps  (%eax), %xmm2, %xmm3
+
+// CHECK: vhsubpd  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0x7d,0xd9]
+          vhsubpd  %xmm1, %xmm2, %xmm3
+
+// CHECK: vhsubpd  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc5,0xe9,0x7d,0x18]
+          vhsubpd  (%eax), %xmm2, %xmm3
+

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s?rev=107405&r1=107404&r2=107405&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s Thu Jul  1 12:35:02 2010
@@ -1630,3 +1630,35 @@
 // CHECK: encoding: [0xc5,0x21,0xd0,0x20]
           vaddsubpd  (%rax), %xmm11, %xmm12
 
+// CHECK: vhaddps  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x1b,0x7c,0xeb]
+          vhaddps  %xmm11, %xmm12, %xmm13
+
+// CHECK: vhaddps  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x1b,0x7c,0x28]
+          vhaddps  (%rax), %xmm12, %xmm13
+
+// CHECK: vhaddpd  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0x7c,0xeb]
+          vhaddpd  %xmm11, %xmm12, %xmm13
+
+// CHECK: vhaddpd  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0x7c,0x28]
+          vhaddpd  (%rax), %xmm12, %xmm13
+
+// CHECK: vhsubps  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x1b,0x7d,0xeb]
+          vhsubps  %xmm11, %xmm12, %xmm13
+
+// CHECK: vhsubps  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x1b,0x7d,0x28]
+          vhsubps  (%rax), %xmm12, %xmm13
+
+// CHECK: vhsubpd  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x41,0x19,0x7d,0xeb]
+          vhsubpd  %xmm11, %xmm12, %xmm13
+
+// CHECK: vhsubpd  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc5,0x19,0x7d,0x28]
+          vhsubpd  (%rax), %xmm12, %xmm13
+




From scanon at apple.com  Thu Jul  1 12:58:24 2010
From: scanon at apple.com (Stephen Canon)
Date: Thu, 01 Jul 2010 17:58:24 -0000
Subject: [llvm-commits] [compiler-rt] r107408 - in /compiler-rt/trunk/lib:
 adddf3.c addsf3.c comparedf2.c comparesf2.c extendsfdf2.c fp_lib.h muldf3.c
 mulsf3.c negdf2.c negsf2.c truncdfsf2.c
Message-ID: <20100701175824.753362A6C12C@llvm.org>

Author: scanon
Date: Thu Jul  1 12:58:24 2010
New Revision: 107408

URL: http://llvm.org/viewvc/llvm-project?rev=107408&view=rev
Log:
Correction to previous commit which mistakenly included older versions of some files; now includes the correct LLVM license header

Added:
    compiler-rt/trunk/lib/truncdfsf2.c
Modified:
    compiler-rt/trunk/lib/adddf3.c
    compiler-rt/trunk/lib/addsf3.c
    compiler-rt/trunk/lib/comparedf2.c
    compiler-rt/trunk/lib/comparesf2.c
    compiler-rt/trunk/lib/extendsfdf2.c
    compiler-rt/trunk/lib/fp_lib.h
    compiler-rt/trunk/lib/muldf3.c
    compiler-rt/trunk/lib/mulsf3.c
    compiler-rt/trunk/lib/negdf2.c
    compiler-rt/trunk/lib/negsf2.c

Modified: compiler-rt/trunk/lib/adddf3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/adddf3.c?rev=107408&r1=107407&r2=107408&view=diff
==============================================================================
--- compiler-rt/trunk/lib/adddf3.c (original)
+++ compiler-rt/trunk/lib/adddf3.c Thu Jul  1 12:58:24 2010
@@ -1,16 +1,20 @@
-/*
- *                     The LLVM Compiler Infrastructure
- *
- * This file is distributed under the University of Illinois Open Source
- * License. See LICENSE.TXT for details.
- */
+//===-- lib/adddf3.c - Double-precision addition and subtraction --*- C -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements double-precision soft-float addition and subtraction
+// with the IEEE-754 default rounding (to nearest, ties to even).
+//
+//===----------------------------------------------------------------------===//
 
 #define DOUBLE_PRECISION
 #include "fp_lib.h"
 
-// This file implements double-precision soft-float addition and subtraction
-// with the IEEE-754 default rounding (to nearest, ties to even).
-
 fp_t __adddf3(fp_t a, fp_t b) {
     
     rep_t aRep = toRep(a);

Modified: compiler-rt/trunk/lib/addsf3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/addsf3.c?rev=107408&r1=107407&r2=107408&view=diff
==============================================================================
--- compiler-rt/trunk/lib/addsf3.c (original)
+++ compiler-rt/trunk/lib/addsf3.c Thu Jul  1 12:58:24 2010
@@ -1,16 +1,20 @@
-/*
- *                     The LLVM Compiler Infrastructure
- *
- * This file is distributed under the University of Illinois Open Source
- * License. See LICENSE.TXT for details.
- */
+//===-- lib/addsf3.c - Single-precision addition and subtraction --*- C -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements single-precision soft-float addition and subtraction
+// with the IEEE-754 default rounding (to nearest, ties to even).
+//
+//===----------------------------------------------------------------------===//
 
 #define SINGLE_PRECISION
 #include "fp_lib.h"
 
-// This file implements single-precision soft-float addition and subtraction
-// with the IEEE-754 default rounding (to nearest, ties to even).
-
 fp_t __addsf3(fp_t a, fp_t b) {
 
     rep_t aRep = toRep(a);

Modified: compiler-rt/trunk/lib/comparedf2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/comparedf2.c?rev=107408&r1=107407&r2=107408&view=diff
==============================================================================
--- compiler-rt/trunk/lib/comparedf2.c (original)
+++ compiler-rt/trunk/lib/comparedf2.c Thu Jul  1 12:58:24 2010
@@ -1,16 +1,15 @@
-/*
- *                     The LLVM Compiler Infrastructure
- *
- * This file is distributed under the University of Illinois Open Source
- * License. See LICENSE.TXT for details.
- */
-
-#define DOUBLE_PRECISION
-#include "fp_lib.h"
-
-// This file implements the following soft-float comparison routines:
+//===-- lib/comparedf2.c - Double-precision comparisons -----------*- C -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
 //
-//   __eqdf2   __gedf2   __nedf2
+// // This file implements the following soft-float comparison routines:
+//
+//   __eqdf2   __gedf2   __unorddf2
 //   __ledf2   __gtdf2
 //   __ltdf2
 //   __nedf2
@@ -35,6 +34,11 @@
 //
 // Note that __ledf2( ) and __gedf2( ) are identical except in their handling of
 // NaN values.
+//
+//===----------------------------------------------------------------------===//
+
+#define DOUBLE_PRECISION
+#include "fp_lib.h"
 
 enum LE_RESULT {
     LE_LESS      = -1,
@@ -75,7 +79,6 @@
     }
 }
 
-
 enum GE_RESULT {
     GE_LESS      = -1,
     GE_EQUAL     =  0,
@@ -109,6 +112,8 @@
     return aAbs > infRep || bAbs > infRep;
 }
 
+// The following are alternative names for the preceeding routines.
+
 enum LE_RESULT __eqdf2(fp_t a, fp_t b) {
     return __ledf2(a, b);
 }

Modified: compiler-rt/trunk/lib/comparesf2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/comparesf2.c?rev=107408&r1=107407&r2=107408&view=diff
==============================================================================
--- compiler-rt/trunk/lib/comparesf2.c (original)
+++ compiler-rt/trunk/lib/comparesf2.c Thu Jul  1 12:58:24 2010
@@ -9,7 +9,7 @@
 //
 // This file implements the following soft-fp_t comparison routines:
 //
-//   __eqsf2   __gesf2   __nesf2
+//   __eqsf2   __gesf2   __unordsf2
 //   __lesf2   __gtsf2
 //   __ltsf2
 //   __nesf2
@@ -79,7 +79,6 @@
     }
 }
 
-
 enum GE_RESULT {
     GE_LESS      = -1,
     GE_EQUAL     =  0,
@@ -113,7 +112,7 @@
     return aAbs > infRep || bAbs > infRep;
 }
 
-// The following are just other names for the forgoing routines.
+// The following are alternative names for the preceeding routines.
 
 enum LE_RESULT __eqsf2(fp_t a, fp_t b) {
     return __lesf2(a, b);
@@ -130,4 +129,3 @@
 enum GE_RESULT __gtsf2(fp_t a, fp_t b) {
     return __gesf2(a, b);
 }
-

Modified: compiler-rt/trunk/lib/extendsfdf2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/extendsfdf2.c?rev=107408&r1=107407&r2=107408&view=diff
==============================================================================
--- compiler-rt/trunk/lib/extendsfdf2.c (original)
+++ compiler-rt/trunk/lib/extendsfdf2.c Thu Jul  1 12:58:24 2010
@@ -1,18 +1,15 @@
-/*
- *                     The LLVM Compiler Infrastructure
- *
- * This file is distributed under the University of Illinois Open Source
- * License. See LICENSE.TXT for details.
- */
-
-#include <stdint.h>
-#include <limits.h>
-
+//===-- lib/extendsfdf2.c - single -> double conversion -----------*- C -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
 // This file implements a fairly generic conversion from a narrower to a wider
-// IEEE-754 floating-point type.  The next 10 lines parametrize which types
-// are to be used as the source and destination, the actual name used for
-// the conversion, and a suitable CLZ function for the source representation
-// type.
+// IEEE-754 floating-point type.  The constants and types defined following the
+// includes below parameterize the conversion.
 //
 // This routine can be trivially adapted to support conversions from 
 // half-precision or to quad-precision. It does not support types that don't
@@ -38,8 +35,11 @@
 //
 // 2. quiet NaNs, if supported, are indicated by the leading bit of the
 //    significand field being set
+//
+//===----------------------------------------------------------------------===//
 
-#define widen __extendsfdf2
+#include <stdint.h>
+#include <limits.h>
 
 typedef float src_t;
 typedef uint32_t src_rep_t;
@@ -67,7 +67,7 @@
 
 // End helper routines.  Conversion implementation follows.
 
-dst_t widen(src_t a) {
+dst_t __extendsfdf2(src_t a) {
     
     // Various constants whose values follow from the type parameters.
     // Any reasonable optimizer will fold and propagate all of these.
@@ -75,22 +75,25 @@
     const int srcExpBits = srcBits - srcSigBits - 1;
     const int srcInfExp = (1 << srcExpBits) - 1;
     const int srcExpBias = srcInfExp >> 1;
+    
     const src_rep_t srcMinNormal = SRC_REP_C(1) << srcSigBits;
     const src_rep_t srcInfinity = (src_rep_t)srcInfExp << srcSigBits;
     const src_rep_t srcSignMask = SRC_REP_C(1) << (srcSigBits + srcExpBits);
     const src_rep_t srcAbsMask = srcSignMask - 1;
     const src_rep_t srcQNaN = SRC_REP_C(1) << (srcSigBits - 1);
     const src_rep_t srcNaNCode = srcQNaN - 1;
+    
     const int dstBits = sizeof(dst_t)*CHAR_BIT;
     const int dstExpBits = dstBits - dstSigBits - 1;
     const int dstInfExp = (1 << dstExpBits) - 1;
     const int dstExpBias = dstInfExp >> 1;
+    
     const dst_rep_t dstMinNormal = DST_REP_C(1) << dstSigBits;
     
     // Break a into a sign and representation of the absolute value
-    src_rep_t aRep = srcToRep(a);
-    src_rep_t aAbs = aRep & srcAbsMask;
-    src_rep_t sign = aRep & srcSignMask;
+    const src_rep_t aRep = srcToRep(a);
+    const src_rep_t aAbs = aRep & srcAbsMask;
+    const src_rep_t sign = aRep & srcSignMask;
     dst_rep_t absResult;
     
     if (aAbs - srcMinNormal < srcInfinity - srcMinNormal) {
@@ -104,11 +107,11 @@
     else if (aAbs >= srcInfinity) {
         // a is NaN or infinity.
         // Conjure the result by beginning with infinity, then setting the qNaN
-        // bit if appropriate and then by right-aligning the rest of the
-        // trailing NaN payload field.
+        // bit (if needed) and right-aligning the rest of the trailing NaN
+        // payload field.
         absResult = (dst_rep_t)dstInfExp << dstSigBits;
         absResult |= (dst_rep_t)(aAbs & srcQNaN) << (dstSigBits - srcSigBits);
-        absResult |= (aAbs & srcNaNCode);
+        absResult |= aAbs & srcNaNCode;
     }
     
     else if (aAbs) {
@@ -128,6 +131,6 @@
     }
     
     // Apply the signbit to (dst_t)abs(a).
-    dst_rep_t result = absResult | (dst_rep_t)sign << (dstBits - srcBits);
+    const dst_rep_t result = absResult | (dst_rep_t)sign << (dstBits - srcBits);
     return dstFromRep(result);
 }

Modified: compiler-rt/trunk/lib/fp_lib.h
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/fp_lib.h?rev=107408&r1=107407&r2=107408&view=diff
==============================================================================
--- compiler-rt/trunk/lib/fp_lib.h (original)
+++ compiler-rt/trunk/lib/fp_lib.h Thu Jul  1 12:58:24 2010
@@ -1,8 +1,22 @@
+//===-- lib/fp_lib.h - Floating-point utilities -------------------*- C -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
 // This file is a configuration header for soft-float routines in compiler-rt.
-// This file does not provide any part of the compiler-rt interface.
-
+// This file does not provide any part of the compiler-rt interface, but defines
+// many useful constants and utility routines that are used in the
+// implementation of the soft-float routines in compiler-rt.
+//
 // Assumes that float and double correspond to the IEEE-754 binary32 and
-// binary64 types, respectively.
+// binary64 types, respectively, and that integer endianness matches floating
+// point endianness on the target platform.
+//
+//===----------------------------------------------------------------------===//
 
 #ifndef FP_LIB_HEADER
 #define FP_LIB_HEADER
@@ -12,9 +26,6 @@
 #include <limits.h>
 
 #if defined SINGLE_PRECISION
-#if 0
-#pragma mark single definitions
-#endif
 
 typedef uint32_t rep_t;
 typedef int32_t srep_t;
@@ -27,9 +38,6 @@
 }
 
 #elif defined DOUBLE_PRECISION
-#if 0
-#pragma mark double definitions
-#endif
 
 typedef uint64_t rep_t;
 typedef int64_t srep_t;
@@ -52,21 +60,11 @@
 #error Either SINGLE_PRECISION or DOUBLE_PRECISION must be defined.
 #endif
 
-#if 0
-#pragma mark -
-#pragma mark integer constants
-#endif
-
 #define typeWidth       (sizeof(rep_t)*CHAR_BIT)
 #define exponentBits    (typeWidth - significandBits - 1)
 #define maxExponent     ((1 << exponentBits) - 1)
 #define exponentBias    (maxExponent >> 1)
 
-#if 0
-#pragma mark -
-#pragma mark rep_t constants
-#endif
-
 #define implicitBit     (REP_C(1) << significandBits)
 #define significandMask (implicitBit - 1U)
 #define signBit         (REP_C(1) << (significandBits + exponentBits))
@@ -77,11 +75,6 @@
 #define quietBit        (implicitBit >> 1)
 #define qnanRep         (exponentMask | quietBit)
 
-#if 0
-#pragma mark -
-#pragma mark generic functions
-#endif
-
 static inline rep_t toRep(fp_t x) {
     const union { fp_t f; rep_t i; } rep = {.f = x};
     return rep.i;

Modified: compiler-rt/trunk/lib/muldf3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/muldf3.c?rev=107408&r1=107407&r2=107408&view=diff
==============================================================================
--- compiler-rt/trunk/lib/muldf3.c (original)
+++ compiler-rt/trunk/lib/muldf3.c Thu Jul  1 12:58:24 2010
@@ -1,21 +1,25 @@
-/*
- *                     The LLVM Compiler Infrastructure
- *
- * This file is distributed under the University of Illinois Open Source
- * License. See LICENSE.TXT for details.
- */
+//===-- lib/muldf3.c - Double-precision multiplication ------------*- C -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements double-precision soft-float multiplication
+// with the IEEE-754 default rounding (to nearest, ties to even).
+//
+//===----------------------------------------------------------------------===//
 
 #define DOUBLE_PRECISION
 #include "fp_lib.h"
 
-// This file implements double-precision soft-float multiplication with the
-// IEEE-754 default rounding (to nearest, ties to even).
-
 #define loWord(a) (a & 0xffffffffU)
 #define hiWord(a) (a >> 32)
 
 // 64x64 -> 128 wide multiply for platforms that don't have such an operation;
-// some 64-bit platforms have this operation, but they tend to have hardware
+// many 64-bit platforms have this operation, but they tend to have hardware
 // floating-point, so we don't bother with a special case for them here.
 static inline void wideMultiply(rep_t a, rep_t b, rep_t *hi, rep_t *lo) {
     // Each of the component 32x32 -> 64 products
@@ -23,7 +27,7 @@
     const uint64_t plohi = loWord(a) * hiWord(b);
     const uint64_t philo = hiWord(a) * loWord(b);
     const uint64_t phihi = hiWord(a) * hiWord(b);
-    // Sum terms that compute to lo in a way that allows us to get the carry
+    // Sum terms that contribute to lo in a way that allows us to get the carry
     const uint64_t r0 = loWord(plolo);
     const uint64_t r1 = hiWord(plolo) + loWord(plohi) + loWord(philo);
     *lo = r0 + (r1 << 32);

Modified: compiler-rt/trunk/lib/mulsf3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/mulsf3.c?rev=107408&r1=107407&r2=107408&view=diff
==============================================================================
--- compiler-rt/trunk/lib/mulsf3.c (original)
+++ compiler-rt/trunk/lib/mulsf3.c Thu Jul  1 12:58:24 2010
@@ -1,16 +1,20 @@
-/*
- *                     The LLVM Compiler Infrastructure
- *
- * This file is distributed under the University of Illinois Open Source
- * License. See LICENSE.TXT for details.
- */
+//===-- lib/mulsf3.c - Single-precision multiplication ------------*- C -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements single-precision soft-float multiplication
+// with the IEEE-754 default rounding (to nearest, ties to even).
+//
+//===----------------------------------------------------------------------===//
 
 #define SINGLE_PRECISION
 #include "fp_lib.h"
 
-// This file implements single-precision soft-float multiplication with the
-// IEEE-754 default rounding (to nearest, ties to even).
-
 // 32x32 --> 64 bit multiply
 static inline void wideMultiply(rep_t a, rep_t b, rep_t *hi, rep_t *lo) {
     const uint64_t product = (uint64_t)a*b;

Modified: compiler-rt/trunk/lib/negdf2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/negdf2.c?rev=107408&r1=107407&r2=107408&view=diff
==============================================================================
--- compiler-rt/trunk/lib/negdf2.c (original)
+++ compiler-rt/trunk/lib/negdf2.c Thu Jul  1 12:58:24 2010
@@ -1,13 +1,19 @@
-/*
- *                     The LLVM Compiler Infrastructure
- *
- * This file is distributed under the University of Illinois Open Source
- * License. See LICENSE.TXT for details.
- */
+//===-- lib/negdf3.c - double-precision negation ------------------*- C -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements double-precision soft-float negation.
+//
+//===----------------------------------------------------------------------===//
 
 #define DOUBLE_PRECISION
 #include "fp_lib.h"
 
-fp_t __negsf2(fp_t a) {
+fp_t __negdf2(fp_t a) {
     return fromRep(toRep(a) ^ signBit);
 }

Modified: compiler-rt/trunk/lib/negsf2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/negsf2.c?rev=107408&r1=107407&r2=107408&view=diff
==============================================================================
--- compiler-rt/trunk/lib/negsf2.c (original)
+++ compiler-rt/trunk/lib/negsf2.c Thu Jul  1 12:58:24 2010
@@ -1,9 +1,15 @@
-/*
- *                     The LLVM Compiler Infrastructure
- *
- * This file is distributed under the University of Illinois Open Source
- * License. See LICENSE.TXT for details.
- */
+//===-- lib/negsf3.c - single-precision negation ------------------*- C -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements single-precision soft-float negation.
+//
+//===----------------------------------------------------------------------===//
 
 #define SINGLE_PRECISION
 #include "fp_lib.h"

Added: compiler-rt/trunk/lib/truncdfsf2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/truncdfsf2.c?rev=107408&view=auto
==============================================================================
--- compiler-rt/trunk/lib/truncdfsf2.c (added)
+++ compiler-rt/trunk/lib/truncdfsf2.c Thu Jul  1 12:58:24 2010
@@ -0,0 +1,169 @@
+//===-- lib/truncdfsf2.c - double -> single conversion ------------*- C -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements a fairly generic conversion from a wider to a narrower
+// IEEE-754 floating-point type in the default (round to nearest, ties to even)
+// rounding mode.  The constants and types defined following the includes below
+// parameterize the conversion.
+//
+// This routine can be trivially adapted to support conversions to 
+// half-precision or from quad-precision. It does not support types that don't
+// use the usual IEEE-754 interchange formats; specifically, some work would be
+// needed to adapt it to (for example) the Intel 80-bit format or PowerPC
+// double-double format.
+//
+// Note please, however, that this implementation is only intended to support
+// *narrowing* operations; if you need to convert to a *wider* floating-point
+// type (e.g. float -> double), then this routine will not do what you want it
+// to.
+//
+// It also requires that integer types at least as large as both formats
+// are available on the target platform; this may pose a problem when trying
+// to add support for quad on some 32-bit systems, for example.
+//
+// Finally, the following assumptions are made:
+//
+// 1. floating-point types and integer types have the same endianness on the
+//    target platform
+//
+// 2. quiet NaNs, if supported, are indicated by the leading bit of the
+//    significand field being set
+//
+//===----------------------------------------------------------------------===//
+
+#include <stdint.h>
+#include <limits.h>
+#include <stdbool.h>
+
+typedef double src_t;
+typedef uint64_t src_rep_t;
+#define SRC_REP_C UINT64_C
+static const int srcSigBits = 52;
+
+typedef float dst_t;
+typedef uint32_t dst_rep_t;
+#define DST_REP_C UINT32_C
+static const int dstSigBits = 23;
+
+// End of specialization parameters.  Two helper routines for conversion to and
+// from the representation of floating-point data as integer values follow.
+
+static inline src_rep_t srcToRep(src_t x) {
+    const union { src_t f; src_rep_t i; } rep = {.f = x};
+    return rep.i;
+}
+
+static inline dst_t dstFromRep(dst_rep_t x) {
+    const union { dst_t f; dst_rep_t i; } rep = {.i = x};
+    return rep.f;
+}
+
+// End helper routines.  Conversion implementation follows.
+
+dst_t __truncdfsf2(src_t a) {
+    
+    // Various constants whose values follow from the type parameters.
+    // Any reasonable optimizer will fold and propagate all of these.
+    const int srcBits = sizeof(src_t)*CHAR_BIT;
+    const int srcExpBits = srcBits - srcSigBits - 1;
+    const int srcInfExp = (1 << srcExpBits) - 1;
+    const int srcExpBias = srcInfExp >> 1;
+    
+    const src_rep_t srcMinNormal = SRC_REP_C(1) << srcSigBits;
+    const src_rep_t srcSignificandMask = srcMinNormal - 1;
+    const src_rep_t srcInfinity = (src_rep_t)srcInfExp << srcSigBits;
+    const src_rep_t srcSignMask = SRC_REP_C(1) << (srcSigBits + srcExpBits);
+    const src_rep_t srcAbsMask = srcSignMask - 1;
+    const src_rep_t srcQNaN = SRC_REP_C(1) << (srcSigBits - 1);
+    const src_rep_t srcNaNCode = srcQNaN - 1;
+    const src_rep_t roundMask = (SRC_REP_C(1) << (srcSigBits - dstSigBits)) - 1;
+    const src_rep_t halfway = SRC_REP_C(1) << (srcSigBits - dstSigBits - 1);
+    
+    const int dstBits = sizeof(dst_t)*CHAR_BIT;
+    const int dstExpBits = dstBits - dstSigBits - 1;
+    const int dstInfExp = (1 << dstExpBits) - 1;
+    const int dstExpBias = dstInfExp >> 1;
+    
+    const int underflowExponent = srcExpBias + 1 - dstExpBias;
+    const int overflowExponent = srcExpBias + dstInfExp - dstExpBias;
+    const src_rep_t underflow = (src_rep_t)underflowExponent << srcSigBits;
+    const src_rep_t overflow = (src_rep_t)overflowExponent << srcSigBits;
+    
+    const dst_rep_t dstQNaN = DST_REP_C(1) << (dstSigBits - 1);
+    const dst_rep_t dstNaNCode = dstQNaN - 1;
+
+    // Break a into a sign and representation of the absolute value
+    const src_rep_t aRep = srcToRep(a);
+    const src_rep_t aAbs = aRep & srcAbsMask;
+    const src_rep_t sign = aRep & srcSignMask;
+    dst_rep_t absResult;
+    
+    if (aAbs - underflow < aAbs - overflow) {
+        // The exponent of a is within the range of normal numbers in the
+        // destination format.  We can convert by simply right-shifting with
+        // rounding and adjusting the exponent.
+        absResult = aAbs >> (srcSigBits - dstSigBits);
+        absResult -= (dst_rep_t)(srcExpBias - dstExpBias) << dstSigBits;
+        
+        const src_rep_t roundBits = aAbs & roundMask;
+        
+        // Round to nearest
+        if (roundBits > halfway)
+            absResult++;
+        
+        // Ties to even
+        else if (roundBits == halfway)
+            absResult += absResult & 1;
+    }
+    
+    else if (aAbs > srcInfinity) {
+        // a is NaN.
+        // Conjure the result by beginning with infinity, setting the qNaN
+        // bit and inserting the (truncated) trailing NaN field.
+        absResult = (dst_rep_t)dstInfExp << dstSigBits;
+        absResult |= dstQNaN;
+        absResult |= aAbs & dstNaNCode;
+    }
+    
+    else if (aAbs > overflow) {
+        // a overflows to infinity.
+        absResult = (dst_rep_t)dstInfExp << dstSigBits;
+    }
+    
+    else {
+        // a underflows on conversion to the destination type or is an exact
+        // zero.  The result may be a denormal or zero.  Extract the exponent
+        // to get the shift amount for the denormalization.
+        const int aExp = aAbs >> srcSigBits;
+        const int shift = srcExpBias - dstExpBias - aExp + 1;
+        
+        const src_rep_t significand = aRep & srcSignificandMask | srcMinNormal;
+        
+        // Right shift by the denormalization amount with sticky.
+        if (shift > srcSigBits) {
+            absResult = 0;
+        } else {
+            const bool sticky = significand << (srcBits - shift);
+            src_rep_t denormalizedSignificand = significand >> shift | sticky;
+            absResult = denormalizedSignificand >> (srcSigBits - dstSigBits);
+            const src_rep_t roundBits = denormalizedSignificand & roundMask;
+            // Round to nearest
+            if (roundBits > halfway)
+                absResult++;
+            // Ties to even
+            else if (roundBits == halfway)
+                absResult += absResult & 1;
+        }
+    }
+    
+    // Apply the signbit to (dst_t)abs(a).
+    const dst_rep_t result = absResult | sign >> (srcBits - dstBits);
+    return dstFromRep(result);
+    
+}




From scanon at apple.com  Thu Jul  1 13:02:15 2010
From: scanon at apple.com (Stephen Canon)
Date: Thu, 01 Jul 2010 18:02:15 -0000
Subject: [llvm-commits] [compiler-rt] r107409 -
	/compiler-rt/trunk/lib/truncdfsf2.c
Message-ID: <20100701180215.56DB02A6C12C@llvm.org>

Author: scanon
Date: Thu Jul  1 13:02:15 2010
New Revision: 107409

URL: http://llvm.org/viewvc/llvm-project?rev=107409&view=rev
Log:
... and one more fix to remove some warnings in the new double -> float conversion

Modified:
    compiler-rt/trunk/lib/truncdfsf2.c

Modified: compiler-rt/trunk/lib/truncdfsf2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/truncdfsf2.c?rev=107409&r1=107408&r2=107409&view=diff
==============================================================================
--- compiler-rt/trunk/lib/truncdfsf2.c (original)
+++ compiler-rt/trunk/lib/truncdfsf2.c Thu Jul  1 13:02:15 2010
@@ -76,12 +76,10 @@
     const int srcExpBias = srcInfExp >> 1;
     
     const src_rep_t srcMinNormal = SRC_REP_C(1) << srcSigBits;
-    const src_rep_t srcSignificandMask = srcMinNormal - 1;
+    const src_rep_t significandMask = srcMinNormal - 1;
     const src_rep_t srcInfinity = (src_rep_t)srcInfExp << srcSigBits;
     const src_rep_t srcSignMask = SRC_REP_C(1) << (srcSigBits + srcExpBits);
     const src_rep_t srcAbsMask = srcSignMask - 1;
-    const src_rep_t srcQNaN = SRC_REP_C(1) << (srcSigBits - 1);
-    const src_rep_t srcNaNCode = srcQNaN - 1;
     const src_rep_t roundMask = (SRC_REP_C(1) << (srcSigBits - dstSigBits)) - 1;
     const src_rep_t halfway = SRC_REP_C(1) << (srcSigBits - dstSigBits - 1);
     
@@ -143,7 +141,7 @@
         const int aExp = aAbs >> srcSigBits;
         const int shift = srcExpBias - dstExpBias - aExp + 1;
         
-        const src_rep_t significand = aRep & srcSignificandMask | srcMinNormal;
+        const src_rep_t significand = (aRep & significandMask) | srcMinNormal;
         
         // Right shift by the denormalization amount with sticky.
         if (shift > srcSigBits) {




From dpatel at apple.com  Thu Jul  1 13:27:46 2010
From: dpatel at apple.com (Devang Patel)
Date: Thu, 01 Jul 2010 18:27:46 -0000
Subject: [llvm-commits] [llvm] r107412 -
	/llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp
Message-ID: <20100701182746.68B642A6C12C@llvm.org>

Author: dpatel
Date: Thu Jul  1 13:27:46 2010
New Revision: 107412

URL: http://llvm.org/viewvc/llvm-project?rev=107412&view=rev
Log:
If a named mdnode is removed then mark module as changed.

Modified:
    llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp

Modified: llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp?rev=107412&r1=107411&r2=107412&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp (original)
+++ llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp Thu Jul  1 13:27:46 2010
@@ -227,8 +227,10 @@
          NME = M.named_metadata_end(); NMI != NME;) {
     NamedMDNode *NMD = NMI;
     ++NMI;
-    if (NMD->getName().startswith("llvm.dbg."))
+    if (NMD->getName().startswith("llvm.dbg.")) {
       NMD->eraseFromParent();
+      Changed = true;
+    }
   }
 
   unsigned MDDbgKind = M.getMDKindID("dbg");




From devang.patel at gmail.com  Thu Jul  1 13:28:36 2010
From: devang.patel at gmail.com (Devang Patel)
Date: Thu, 1 Jul 2010 11:28:36 -0700
Subject: [llvm-commits] [llvm] r107323 - in /llvm/trunk:
	lib/Transforms/IPO/StripSymbols.cpp
	test/Transforms/StripSymbols/2010-06-30-StripDebug.ll
In-Reply-To: <4C2C3FDB.4000408@free.fr>
References: <20100630212900.5D0DB2A6C12C@llvm.org> <4C2C3FDB.4000408@free.fr>
Message-ID: <AANLkTimABorn9XLLEIVNCvsZyh_F6pxc_yWhwLR7oNR8@mail.gmail.com>

On Thu, Jul 1, 2010 at 12:12 AM, Duncan Sands <baldrick at free.fr> wrote:
> Hi Devang,
>
> should you set Changed to "true" here?

yup! Fixed.
-
Devang


From scanon at apple.com  Thu Jul  1 13:35:51 2010
From: scanon at apple.com (Stephen Canon)
Date: Thu, 01 Jul 2010 18:35:51 -0000
Subject: [llvm-commits] [compiler-rt] r107414 - in
 /compiler-rt/trunk/test/Unit: comparedf2_test.c comparesf2_test.c
Message-ID: <20100701183551.23D7B2A6C12C@llvm.org>

Author: scanon
Date: Thu Jul  1 13:35:50 2010
New Revision: 107414

URL: http://llvm.org/viewvc/llvm-project?rev=107414&view=rev
Log:
Tests for soft-float comparison functions

Added:
    compiler-rt/trunk/test/Unit/comparedf2_test.c
    compiler-rt/trunk/test/Unit/comparesf2_test.c

Added: compiler-rt/trunk/test/Unit/comparedf2_test.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/test/Unit/comparedf2_test.c?rev=107414&view=auto
==============================================================================
--- compiler-rt/trunk/test/Unit/comparedf2_test.c (added)
+++ compiler-rt/trunk/test/Unit/comparedf2_test.c Thu Jul  1 13:35:50 2010
@@ -0,0 +1,479 @@
+//===-- cmpdf2_test.c - Test __cmpdf2 -------------------------------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file tests single-precision soft-double comparisons for the compiler-rt
+// library.
+//
+//===----------------------------------------------------------------------===//
+
+#include <stdio.h>
+
+int __eqdf2(double, double);
+int __gedf2(double, double);
+int __gtdf2(double, double);
+int __ledf2(double, double);
+int __ltdf2(double, double);
+int __nedf2(double, double);
+int __unorddf2(double, double);
+
+struct TestVector {
+    double a;
+    double b;
+    int eqReference;
+    int geReference;
+    int gtReference;
+    int leReference;
+    int ltReference;
+    int neReference;
+    int unReference;
+};
+
+int test__cmpdf2(const struct TestVector *vector) {
+    
+    if (__eqdf2(vector->a, vector->b) != vector->eqReference) {
+        printf("error in __eqdf2(%a, %a) = %d, expected %d\n",
+               vector->a, vector->b,
+               __eqdf2(vector->a, vector->b),
+               vector->eqReference);
+        return 1;
+    }
+    
+    if (__gedf2(vector->a, vector->b) != vector->geReference) {
+        printf("error in __gedf2(%a, %a) = %d, expected %d\n",
+               vector->a, vector->b,
+               __gedf2(vector->a, vector->b),
+               vector->geReference);
+        return 1;
+    }
+    
+    if (__gtdf2(vector->a, vector->b) != vector->gtReference) {
+        printf("error in __gtdf2(%a, %a) = %d, expected %d\n",
+               vector->a, vector->b,
+               __gtdf2(vector->a, vector->b),
+               vector->gtReference);
+        return 1;
+    }
+    
+    if (__ledf2(vector->a, vector->b) != vector->leReference) {
+        printf("error in __ledf2(%a, %a) = %d, expected %d\n",
+               vector->a, vector->b,
+               __ledf2(vector->a, vector->b),
+               vector->leReference);
+        return 1;
+    }
+    
+    if (__ltdf2(vector->a, vector->b) != vector->ltReference) {
+        printf("error in __ltdf2(%a, %a) = %d, expected %d\n",
+               vector->a, vector->b,
+               __ltdf2(vector->a, vector->b),
+               vector->ltReference);
+        return 1;
+    }
+    
+    if (__nedf2(vector->a, vector->b) != vector->neReference) {
+        printf("error in __nedf2(%a, %a) = %d, expected %d\n",
+               vector->a, vector->b,
+               __nedf2(vector->a, vector->b),
+               vector->neReference);
+        return 1;
+    }
+    
+    if (__unorddf2(vector->a, vector->b) != vector->unReference) {
+        printf("error in __unorddf2(%a, %a) = %d, expected %d\n",
+               vector->a, vector->b,
+               __unorddf2(vector->a, vector->b),
+               vector->unReference);
+        return 1;
+    }
+    
+    return 0;
+}
+
+/*
+void generateVectors() {
+    
+    const double arguments[] = {
+        __builtin_nan(""),
+        -__builtin_inf(),
+        -0x1.fffffffffffffp1023,
+        -0x1.0000000000001p0
+        -0x1.0000000000000p0,
+        -0x1.fffffffffffffp-1,
+        -0x1.0000000000000p-1022,
+        -0x0.fffffffffffffp-1022,
+        -0x0.0000000000001p-1022,
+        -0.0,
+         0.0,
+         0x0.0000000000001p-1022,
+         0x0.fffffffffffffp-1022,
+         0x1.0000000000000p-1022,
+         0x1.fffffffffffffp-1,
+         0x1.0000000000000p0,
+         0x1.0000000000001p0,
+         0x1.fffffffffffffp1023,
+         __builtin_inf()
+    };
+    
+    int numArguments = sizeof arguments / sizeof arguments[0];
+    
+    for (int i=0; i<numArguments; ++i) {
+        for (int j=0; j<numArguments; ++j) {
+            const double a = arguments[i];
+            const double b = arguments[j];
+            const int leResult = a < b ? -1 : a == b ? 0 :  1;
+            const int geResult = a > b ?  1 : a == b ? 0 : -1;
+            const int unResult = a != a || b != b ? 1 : 0;
+            printf("{%a,%a,%d,%d,%d,%d,%d,%d,%d},\n",
+                   a, b, 
+                   leResult,
+                   geResult,
+                   geResult,
+                   leResult,
+                   leResult,
+                   leResult,
+                   unResult);
+        }
+    }
+} */
+
+static const struct TestVector vectors[] = {
+    {__builtin_nan(""),__builtin_nan(""),1,-1,-1,1,1,1,1},
+    {__builtin_nan(""),-__builtin_inf(),1,-1,-1,1,1,1,1},
+    {__builtin_nan(""),-0x1.fffffffffffffp+1023,1,-1,-1,1,1,1,1},
+    {__builtin_nan(""),-0x1p+1,1,-1,-1,1,1,1,1},
+    {__builtin_nan(""),-0x1.fffffffffffffp-1,1,-1,-1,1,1,1,1},
+    {__builtin_nan(""),-0x1p-1022,1,-1,-1,1,1,1,1},
+    {__builtin_nan(""),-0x1.fffffcp-1023,1,-1,-1,1,1,1,1},
+    {__builtin_nan(""),-0x1p-1074,1,-1,-1,1,1,1,1},
+    {__builtin_nan(""),-0x0p+0,1,-1,-1,1,1,1,1},
+    {__builtin_nan(""),0x0p+0,1,-1,-1,1,1,1,1},
+    {__builtin_nan(""),0x1p-1074,1,-1,-1,1,1,1,1},
+    {__builtin_nan(""),0x1.fffffcp-1023,1,-1,-1,1,1,1,1},
+    {__builtin_nan(""),0x1p-1022,1,-1,-1,1,1,1,1},
+    {__builtin_nan(""),0x1.fffffffffffffp-1,1,-1,-1,1,1,1,1},
+    {__builtin_nan(""),0x1p+0,1,-1,-1,1,1,1,1},
+    {__builtin_nan(""),0x1.0000000000001p+0,1,-1,-1,1,1,1,1},
+    {__builtin_nan(""),0x1.fffffffffffffp+1023,1,-1,-1,1,1,1,1},
+    {__builtin_nan(""),__builtin_inf(),1,-1,-1,1,1,1,1},
+    {-__builtin_inf(),__builtin_nan(""),1,-1,-1,1,1,1,1},
+    {-__builtin_inf(),-__builtin_inf(),0,0,0,0,0,0,0},
+    {-__builtin_inf(),-0x1.fffffffffffffp+1023,-1,-1,-1,-1,-1,-1,0},
+    {-__builtin_inf(),-0x1p+1,-1,-1,-1,-1,-1,-1,0},
+    {-__builtin_inf(),-0x1.fffffffffffffp-1,-1,-1,-1,-1,-1,-1,0},
+    {-__builtin_inf(),-0x1p-1022,-1,-1,-1,-1,-1,-1,0},
+    {-__builtin_inf(),-0x1.fffffcp-1023,-1,-1,-1,-1,-1,-1,0},
+    {-__builtin_inf(),-0x1p-1074,-1,-1,-1,-1,-1,-1,0},
+    {-__builtin_inf(),-0x0p+0,-1,-1,-1,-1,-1,-1,0},
+    {-__builtin_inf(),0x0p+0,-1,-1,-1,-1,-1,-1,0},
+    {-__builtin_inf(),0x1p-1074,-1,-1,-1,-1,-1,-1,0},
+    {-__builtin_inf(),0x1.fffffcp-1023,-1,-1,-1,-1,-1,-1,0},
+    {-__builtin_inf(),0x1p-1022,-1,-1,-1,-1,-1,-1,0},
+    {-__builtin_inf(),0x1.fffffffffffffp-1,-1,-1,-1,-1,-1,-1,0},
+    {-__builtin_inf(),0x1p+0,-1,-1,-1,-1,-1,-1,0},
+    {-__builtin_inf(),0x1.0000000000001p+0,-1,-1,-1,-1,-1,-1,0},
+    {-__builtin_inf(),0x1.fffffffffffffp+1023,-1,-1,-1,-1,-1,-1,0},
+    {-__builtin_inf(),__builtin_inf(),-1,-1,-1,-1,-1,-1,0},
+    {-0x1.fffffffffffffp+1023,__builtin_nan(""),1,-1,-1,1,1,1,1},
+    {-0x1.fffffffffffffp+1023,-__builtin_inf(),1,1,1,1,1,1,0},
+    {-0x1.fffffffffffffp+1023,-0x1.fffffffffffffp+1023,0,0,0,0,0,0,0},
+    {-0x1.fffffffffffffp+1023,-0x1p+1,-1,-1,-1,-1,-1,-1,0},
+    {-0x1.fffffffffffffp+1023,-0x1.fffffffffffffp-1,-1,-1,-1,-1,-1,-1,0},
+    {-0x1.fffffffffffffp+1023,-0x1p-1022,-1,-1,-1,-1,-1,-1,0},
+    {-0x1.fffffffffffffp+1023,-0x1.fffffcp-1023,-1,-1,-1,-1,-1,-1,0},
+    {-0x1.fffffffffffffp+1023,-0x1p-1074,-1,-1,-1,-1,-1,-1,0},
+    {-0x1.fffffffffffffp+1023,-0x0p+0,-1,-1,-1,-1,-1,-1,0},
+    {-0x1.fffffffffffffp+1023,0x0p+0,-1,-1,-1,-1,-1,-1,0},
+    {-0x1.fffffffffffffp+1023,0x1p-1074,-1,-1,-1,-1,-1,-1,0},
+    {-0x1.fffffffffffffp+1023,0x1.fffffcp-1023,-1,-1,-1,-1,-1,-1,0},
+    {-0x1.fffffffffffffp+1023,0x1p-1022,-1,-1,-1,-1,-1,-1,0},
+    {-0x1.fffffffffffffp+1023,0x1.fffffffffffffp-1,-1,-1,-1,-1,-1,-1,0},
+    {-0x1.fffffffffffffp+1023,0x1p+0,-1,-1,-1,-1,-1,-1,0},
+    {-0x1.fffffffffffffp+1023,0x1.0000000000001p+0,-1,-1,-1,-1,-1,-1,0},
+    {-0x1.fffffffffffffp+1023,0x1.fffffffffffffp+1023,-1,-1,-1,-1,-1,-1,0},
+    {-0x1.fffffffffffffp+1023,__builtin_inf(),-1,-1,-1,-1,-1,-1,0},
+    {-0x1p+1,__builtin_nan(""),1,-1,-1,1,1,1,1},
+    {-0x1p+1,-__builtin_inf(),1,1,1,1,1,1,0},
+    {-0x1p+1,-0x1.fffffffffffffp+1023,1,1,1,1,1,1,0},
+    {-0x1p+1,-0x1p+1,0,0,0,0,0,0,0},
+    {-0x1p+1,-0x1.fffffffffffffp-1,-1,-1,-1,-1,-1,-1,0},
+    {-0x1p+1,-0x1p-1022,-1,-1,-1,-1,-1,-1,0},
+    {-0x1p+1,-0x1.fffffcp-1023,-1,-1,-1,-1,-1,-1,0},
+    {-0x1p+1,-0x1p-1074,-1,-1,-1,-1,-1,-1,0},
+    {-0x1p+1,-0x0p+0,-1,-1,-1,-1,-1,-1,0},
+    {-0x1p+1,0x0p+0,-1,-1,-1,-1,-1,-1,0},
+    {-0x1p+1,0x1p-1074,-1,-1,-1,-1,-1,-1,0},
+    {-0x1p+1,0x1.fffffcp-1023,-1,-1,-1,-1,-1,-1,0},
+    {-0x1p+1,0x1p-1022,-1,-1,-1,-1,-1,-1,0},
+    {-0x1p+1,0x1.fffffffffffffp-1,-1,-1,-1,-1,-1,-1,0},
+    {-0x1p+1,0x1p+0,-1,-1,-1,-1,-1,-1,0},
+    {-0x1p+1,0x1.0000000000001p+0,-1,-1,-1,-1,-1,-1,0},
+    {-0x1p+1,0x1.fffffffffffffp+1023,-1,-1,-1,-1,-1,-1,0},
+    {-0x1p+1,__builtin_inf(),-1,-1,-1,-1,-1,-1,0},
+    {-0x1.fffffffffffffp-1,__builtin_nan(""),1,-1,-1,1,1,1,1},
+    {-0x1.fffffffffffffp-1,-__builtin_inf(),1,1,1,1,1,1,0},
+    {-0x1.fffffffffffffp-1,-0x1.fffffffffffffp+1023,1,1,1,1,1,1,0},
+    {-0x1.fffffffffffffp-1,-0x1p+1,1,1,1,1,1,1,0},
+    {-0x1.fffffffffffffp-1,-0x1.fffffffffffffp-1,0,0,0,0,0,0,0},
+    {-0x1.fffffffffffffp-1,-0x1p-1022,-1,-1,-1,-1,-1,-1,0},
+    {-0x1.fffffffffffffp-1,-0x1.fffffcp-1023,-1,-1,-1,-1,-1,-1,0},
+    {-0x1.fffffffffffffp-1,-0x1p-1074,-1,-1,-1,-1,-1,-1,0},
+    {-0x1.fffffffffffffp-1,-0x0p+0,-1,-1,-1,-1,-1,-1,0},
+    {-0x1.fffffffffffffp-1,0x0p+0,-1,-1,-1,-1,-1,-1,0},
+    {-0x1.fffffffffffffp-1,0x1p-1074,-1,-1,-1,-1,-1,-1,0},
+    {-0x1.fffffffffffffp-1,0x1.fffffcp-1023,-1,-1,-1,-1,-1,-1,0},
+    {-0x1.fffffffffffffp-1,0x1p-1022,-1,-1,-1,-1,-1,-1,0},
+    {-0x1.fffffffffffffp-1,0x1.fffffffffffffp-1,-1,-1,-1,-1,-1,-1,0},
+    {-0x1.fffffffffffffp-1,0x1p+0,-1,-1,-1,-1,-1,-1,0},
+    {-0x1.fffffffffffffp-1,0x1.0000000000001p+0,-1,-1,-1,-1,-1,-1,0},
+    {-0x1.fffffffffffffp-1,0x1.fffffffffffffp+1023,-1,-1,-1,-1,-1,-1,0},
+    {-0x1.fffffffffffffp-1,__builtin_inf(),-1,-1,-1,-1,-1,-1,0},
+    {-0x1p-1022,__builtin_nan(""),1,-1,-1,1,1,1,1},
+    {-0x1p-1022,-__builtin_inf(),1,1,1,1,1,1,0},
+    {-0x1p-1022,-0x1.fffffffffffffp+1023,1,1,1,1,1,1,0},
+    {-0x1p-1022,-0x1p+1,1,1,1,1,1,1,0},
+    {-0x1p-1022,-0x1.fffffffffffffp-1,1,1,1,1,1,1,0},
+    {-0x1p-1022,-0x1p-1022,0,0,0,0,0,0,0},
+    {-0x1p-1022,-0x1.fffffcp-1023,-1,-1,-1,-1,-1,-1,0},
+    {-0x1p-1022,-0x1p-1074,-1,-1,-1,-1,-1,-1,0},
+    {-0x1p-1022,-0x0p+0,-1,-1,-1,-1,-1,-1,0},
+    {-0x1p-1022,0x0p+0,-1,-1,-1,-1,-1,-1,0},
+    {-0x1p-1022,0x1p-1074,-1,-1,-1,-1,-1,-1,0},
+    {-0x1p-1022,0x1.fffffcp-1023,-1,-1,-1,-1,-1,-1,0},
+    {-0x1p-1022,0x1p-1022,-1,-1,-1,-1,-1,-1,0},
+    {-0x1p-1022,0x1.fffffffffffffp-1,-1,-1,-1,-1,-1,-1,0},
+    {-0x1p-1022,0x1p+0,-1,-1,-1,-1,-1,-1,0},
+    {-0x1p-1022,0x1.0000000000001p+0,-1,-1,-1,-1,-1,-1,0},
+    {-0x1p-1022,0x1.fffffffffffffp+1023,-1,-1,-1,-1,-1,-1,0},
+    {-0x1p-1022,__builtin_inf(),-1,-1,-1,-1,-1,-1,0},
+    {-0x1.fffffcp-1023,__builtin_nan(""),1,-1,-1,1,1,1,1},
+    {-0x1.fffffcp-1023,-__builtin_inf(),1,1,1,1,1,1,0},
+    {-0x1.fffffcp-1023,-0x1.fffffffffffffp+1023,1,1,1,1,1,1,0},
+    {-0x1.fffffcp-1023,-0x1p+1,1,1,1,1,1,1,0},
+    {-0x1.fffffcp-1023,-0x1.fffffffffffffp-1,1,1,1,1,1,1,0},
+    {-0x1.fffffcp-1023,-0x1p-1022,1,1,1,1,1,1,0},
+    {-0x1.fffffcp-1023,-0x1.fffffcp-1023,0,0,0,0,0,0,0},
+    {-0x1.fffffcp-1023,-0x1p-1074,-1,-1,-1,-1,-1,-1,0},
+    {-0x1.fffffcp-1023,-0x0p+0,-1,-1,-1,-1,-1,-1,0},
+    {-0x1.fffffcp-1023,0x0p+0,-1,-1,-1,-1,-1,-1,0},
+    {-0x1.fffffcp-1023,0x1p-1074,-1,-1,-1,-1,-1,-1,0},
+    {-0x1.fffffcp-1023,0x1.fffffcp-1023,-1,-1,-1,-1,-1,-1,0},
+    {-0x1.fffffcp-1023,0x1p-1022,-1,-1,-1,-1,-1,-1,0},
+    {-0x1.fffffcp-1023,0x1.fffffffffffffp-1,-1,-1,-1,-1,-1,-1,0},
+    {-0x1.fffffcp-1023,0x1p+0,-1,-1,-1,-1,-1,-1,0},
+    {-0x1.fffffcp-1023,0x1.0000000000001p+0,-1,-1,-1,-1,-1,-1,0},
+    {-0x1.fffffcp-1023,0x1.fffffffffffffp+1023,-1,-1,-1,-1,-1,-1,0},
+    {-0x1.fffffcp-1023,__builtin_inf(),-1,-1,-1,-1,-1,-1,0},
+    {-0x1p-1074,__builtin_nan(""),1,-1,-1,1,1,1,1},
+    {-0x1p-1074,-__builtin_inf(),1,1,1,1,1,1,0},
+    {-0x1p-1074,-0x1.fffffffffffffp+1023,1,1,1,1,1,1,0},
+    {-0x1p-1074,-0x1p+1,1,1,1,1,1,1,0},
+    {-0x1p-1074,-0x1.fffffffffffffp-1,1,1,1,1,1,1,0},
+    {-0x1p-1074,-0x1p-1022,1,1,1,1,1,1,0},
+    {-0x1p-1074,-0x1.fffffcp-1023,1,1,1,1,1,1,0},
+    {-0x1p-1074,-0x1p-1074,0,0,0,0,0,0,0},
+    {-0x1p-1074,-0x0p+0,-1,-1,-1,-1,-1,-1,0},
+    {-0x1p-1074,0x0p+0,-1,-1,-1,-1,-1,-1,0},
+    {-0x1p-1074,0x1p-1074,-1,-1,-1,-1,-1,-1,0},
+    {-0x1p-1074,0x1.fffffcp-1023,-1,-1,-1,-1,-1,-1,0},
+    {-0x1p-1074,0x1p-1022,-1,-1,-1,-1,-1,-1,0},
+    {-0x1p-1074,0x1.fffffffffffffp-1,-1,-1,-1,-1,-1,-1,0},
+    {-0x1p-1074,0x1p+0,-1,-1,-1,-1,-1,-1,0},
+    {-0x1p-1074,0x1.0000000000001p+0,-1,-1,-1,-1,-1,-1,0},
+    {-0x1p-1074,0x1.fffffffffffffp+1023,-1,-1,-1,-1,-1,-1,0},
+    {-0x1p-1074,__builtin_inf(),-1,-1,-1,-1,-1,-1,0},
+    {-0x0p+0,__builtin_nan(""),1,-1,-1,1,1,1,1},
+    {-0x0p+0,-__builtin_inf(),1,1,1,1,1,1,0},
+    {-0x0p+0,-0x1.fffffffffffffp+1023,1,1,1,1,1,1,0},
+    {-0x0p+0,-0x1p+1,1,1,1,1,1,1,0},
+    {-0x0p+0,-0x1.fffffffffffffp-1,1,1,1,1,1,1,0},
+    {-0x0p+0,-0x1p-1022,1,1,1,1,1,1,0},
+    {-0x0p+0,-0x1.fffffcp-1023,1,1,1,1,1,1,0},
+    {-0x0p+0,-0x1p-1074,1,1,1,1,1,1,0},
+    {-0x0p+0,-0x0p+0,0,0,0,0,0,0,0},
+    {-0x0p+0,0x0p+0,0,0,0,0,0,0,0},
+    {-0x0p+0,0x1p-1074,-1,-1,-1,-1,-1,-1,0},
+    {-0x0p+0,0x1.fffffcp-1023,-1,-1,-1,-1,-1,-1,0},
+    {-0x0p+0,0x1p-1022,-1,-1,-1,-1,-1,-1,0},
+    {-0x0p+0,0x1.fffffffffffffp-1,-1,-1,-1,-1,-1,-1,0},
+    {-0x0p+0,0x1p+0,-1,-1,-1,-1,-1,-1,0},
+    {-0x0p+0,0x1.0000000000001p+0,-1,-1,-1,-1,-1,-1,0},
+    {-0x0p+0,0x1.fffffffffffffp+1023,-1,-1,-1,-1,-1,-1,0},
+    {-0x0p+0,__builtin_inf(),-1,-1,-1,-1,-1,-1,0},
+    {0x0p+0,__builtin_nan(""),1,-1,-1,1,1,1,1},
+    {0x0p+0,-__builtin_inf(),1,1,1,1,1,1,0},
+    {0x0p+0,-0x1.fffffffffffffp+1023,1,1,1,1,1,1,0},
+    {0x0p+0,-0x1p+1,1,1,1,1,1,1,0},
+    {0x0p+0,-0x1.fffffffffffffp-1,1,1,1,1,1,1,0},
+    {0x0p+0,-0x1p-1022,1,1,1,1,1,1,0},
+    {0x0p+0,-0x1.fffffcp-1023,1,1,1,1,1,1,0},
+    {0x0p+0,-0x1p-1074,1,1,1,1,1,1,0},
+    {0x0p+0,-0x0p+0,0,0,0,0,0,0,0},
+    {0x0p+0,0x0p+0,0,0,0,0,0,0,0},
+    {0x0p+0,0x1p-1074,-1,-1,-1,-1,-1,-1,0},
+    {0x0p+0,0x1.fffffcp-1023,-1,-1,-1,-1,-1,-1,0},
+    {0x0p+0,0x1p-1022,-1,-1,-1,-1,-1,-1,0},
+    {0x0p+0,0x1.fffffffffffffp-1,-1,-1,-1,-1,-1,-1,0},
+    {0x0p+0,0x1p+0,-1,-1,-1,-1,-1,-1,0},
+    {0x0p+0,0x1.0000000000001p+0,-1,-1,-1,-1,-1,-1,0},
+    {0x0p+0,0x1.fffffffffffffp+1023,-1,-1,-1,-1,-1,-1,0},
+    {0x0p+0,__builtin_inf(),-1,-1,-1,-1,-1,-1,0},
+    {0x1p-1074,__builtin_nan(""),1,-1,-1,1,1,1,1},
+    {0x1p-1074,-__builtin_inf(),1,1,1,1,1,1,0},
+    {0x1p-1074,-0x1.fffffffffffffp+1023,1,1,1,1,1,1,0},
+    {0x1p-1074,-0x1p+1,1,1,1,1,1,1,0},
+    {0x1p-1074,-0x1.fffffffffffffp-1,1,1,1,1,1,1,0},
+    {0x1p-1074,-0x1p-1022,1,1,1,1,1,1,0},
+    {0x1p-1074,-0x1.fffffcp-1023,1,1,1,1,1,1,0},
+    {0x1p-1074,-0x1p-1074,1,1,1,1,1,1,0},
+    {0x1p-1074,-0x0p+0,1,1,1,1,1,1,0},
+    {0x1p-1074,0x0p+0,1,1,1,1,1,1,0},
+    {0x1p-1074,0x1p-1074,0,0,0,0,0,0,0},
+    {0x1p-1074,0x1.fffffcp-1023,-1,-1,-1,-1,-1,-1,0},
+    {0x1p-1074,0x1p-1022,-1,-1,-1,-1,-1,-1,0},
+    {0x1p-1074,0x1.fffffffffffffp-1,-1,-1,-1,-1,-1,-1,0},
+    {0x1p-1074,0x1p+0,-1,-1,-1,-1,-1,-1,0},
+    {0x1p-1074,0x1.0000000000001p+0,-1,-1,-1,-1,-1,-1,0},
+    {0x1p-1074,0x1.fffffffffffffp+1023,-1,-1,-1,-1,-1,-1,0},
+    {0x1p-1074,__builtin_inf(),-1,-1,-1,-1,-1,-1,0},
+    {0x1.fffffcp-1023,__builtin_nan(""),1,-1,-1,1,1,1,1},
+    {0x1.fffffcp-1023,-__builtin_inf(),1,1,1,1,1,1,0},
+    {0x1.fffffcp-1023,-0x1.fffffffffffffp+1023,1,1,1,1,1,1,0},
+    {0x1.fffffcp-1023,-0x1p+1,1,1,1,1,1,1,0},
+    {0x1.fffffcp-1023,-0x1.fffffffffffffp-1,1,1,1,1,1,1,0},
+    {0x1.fffffcp-1023,-0x1p-1022,1,1,1,1,1,1,0},
+    {0x1.fffffcp-1023,-0x1.fffffcp-1023,1,1,1,1,1,1,0},
+    {0x1.fffffcp-1023,-0x1p-1074,1,1,1,1,1,1,0},
+    {0x1.fffffcp-1023,-0x0p+0,1,1,1,1,1,1,0},
+    {0x1.fffffcp-1023,0x0p+0,1,1,1,1,1,1,0},
+    {0x1.fffffcp-1023,0x1p-1074,1,1,1,1,1,1,0},
+    {0x1.fffffcp-1023,0x1.fffffcp-1023,0,0,0,0,0,0,0},
+    {0x1.fffffcp-1023,0x1p-1022,-1,-1,-1,-1,-1,-1,0},
+    {0x1.fffffcp-1023,0x1.fffffffffffffp-1,-1,-1,-1,-1,-1,-1,0},
+    {0x1.fffffcp-1023,0x1p+0,-1,-1,-1,-1,-1,-1,0},
+    {0x1.fffffcp-1023,0x1.0000000000001p+0,-1,-1,-1,-1,-1,-1,0},
+    {0x1.fffffcp-1023,0x1.fffffffffffffp+1023,-1,-1,-1,-1,-1,-1,0},
+    {0x1.fffffcp-1023,__builtin_inf(),-1,-1,-1,-1,-1,-1,0},
+    {0x1p-1022,__builtin_nan(""),1,-1,-1,1,1,1,1},
+    {0x1p-1022,-__builtin_inf(),1,1,1,1,1,1,0},
+    {0x1p-1022,-0x1.fffffffffffffp+1023,1,1,1,1,1,1,0},
+    {0x1p-1022,-0x1p+1,1,1,1,1,1,1,0},
+    {0x1p-1022,-0x1.fffffffffffffp-1,1,1,1,1,1,1,0},
+    {0x1p-1022,-0x1p-1022,1,1,1,1,1,1,0},
+    {0x1p-1022,-0x1.fffffcp-1023,1,1,1,1,1,1,0},
+    {0x1p-1022,-0x1p-1074,1,1,1,1,1,1,0},
+    {0x1p-1022,-0x0p+0,1,1,1,1,1,1,0},
+    {0x1p-1022,0x0p+0,1,1,1,1,1,1,0},
+    {0x1p-1022,0x1p-1074,1,1,1,1,1,1,0},
+    {0x1p-1022,0x1.fffffcp-1023,1,1,1,1,1,1,0},
+    {0x1p-1022,0x1p-1022,0,0,0,0,0,0,0},
+    {0x1p-1022,0x1.fffffffffffffp-1,-1,-1,-1,-1,-1,-1,0},
+    {0x1p-1022,0x1p+0,-1,-1,-1,-1,-1,-1,0},
+    {0x1p-1022,0x1.0000000000001p+0,-1,-1,-1,-1,-1,-1,0},
+    {0x1p-1022,0x1.fffffffffffffp+1023,-1,-1,-1,-1,-1,-1,0},
+    {0x1p-1022,__builtin_inf(),-1,-1,-1,-1,-1,-1,0},
+    {0x1.fffffffffffffp-1,__builtin_nan(""),1,-1,-1,1,1,1,1},
+    {0x1.fffffffffffffp-1,-__builtin_inf(),1,1,1,1,1,1,0},
+    {0x1.fffffffffffffp-1,-0x1.fffffffffffffp+1023,1,1,1,1,1,1,0},
+    {0x1.fffffffffffffp-1,-0x1p+1,1,1,1,1,1,1,0},
+    {0x1.fffffffffffffp-1,-0x1.fffffffffffffp-1,1,1,1,1,1,1,0},
+    {0x1.fffffffffffffp-1,-0x1p-1022,1,1,1,1,1,1,0},
+    {0x1.fffffffffffffp-1,-0x1.fffffcp-1023,1,1,1,1,1,1,0},
+    {0x1.fffffffffffffp-1,-0x1p-1074,1,1,1,1,1,1,0},
+    {0x1.fffffffffffffp-1,-0x0p+0,1,1,1,1,1,1,0},
+    {0x1.fffffffffffffp-1,0x0p+0,1,1,1,1,1,1,0},
+    {0x1.fffffffffffffp-1,0x1p-1074,1,1,1,1,1,1,0},
+    {0x1.fffffffffffffp-1,0x1.fffffcp-1023,1,1,1,1,1,1,0},
+    {0x1.fffffffffffffp-1,0x1p-1022,1,1,1,1,1,1,0},
+    {0x1.fffffffffffffp-1,0x1.fffffffffffffp-1,0,0,0,0,0,0,0},
+    {0x1.fffffffffffffp-1,0x1p+0,-1,-1,-1,-1,-1,-1,0},
+    {0x1.fffffffffffffp-1,0x1.0000000000001p+0,-1,-1,-1,-1,-1,-1,0},
+    {0x1.fffffffffffffp-1,0x1.fffffffffffffp+1023,-1,-1,-1,-1,-1,-1,0},
+    {0x1.fffffffffffffp-1,__builtin_inf(),-1,-1,-1,-1,-1,-1,0},
+    {0x1p+0,__builtin_nan(""),1,-1,-1,1,1,1,1},
+    {0x1p+0,-__builtin_inf(),1,1,1,1,1,1,0},
+    {0x1p+0,-0x1.fffffffffffffp+1023,1,1,1,1,1,1,0},
+    {0x1p+0,-0x1p+1,1,1,1,1,1,1,0},
+    {0x1p+0,-0x1.fffffffffffffp-1,1,1,1,1,1,1,0},
+    {0x1p+0,-0x1p-1022,1,1,1,1,1,1,0},
+    {0x1p+0,-0x1.fffffcp-1023,1,1,1,1,1,1,0},
+    {0x1p+0,-0x1p-1074,1,1,1,1,1,1,0},
+    {0x1p+0,-0x0p+0,1,1,1,1,1,1,0},
+    {0x1p+0,0x0p+0,1,1,1,1,1,1,0},
+    {0x1p+0,0x1p-1074,1,1,1,1,1,1,0},
+    {0x1p+0,0x1.fffffcp-1023,1,1,1,1,1,1,0},
+    {0x1p+0,0x1p-1022,1,1,1,1,1,1,0},
+    {0x1p+0,0x1.fffffffffffffp-1,1,1,1,1,1,1,0},
+    {0x1p+0,0x1p+0,0,0,0,0,0,0,0},
+    {0x1p+0,0x1.0000000000001p+0,-1,-1,-1,-1,-1,-1,0},
+    {0x1p+0,0x1.fffffffffffffp+1023,-1,-1,-1,-1,-1,-1,0},
+    {0x1p+0,__builtin_inf(),-1,-1,-1,-1,-1,-1,0},
+    {0x1.0000000000001p+0,__builtin_nan(""),1,-1,-1,1,1,1,1},
+    {0x1.0000000000001p+0,-__builtin_inf(),1,1,1,1,1,1,0},
+    {0x1.0000000000001p+0,-0x1.fffffffffffffp+1023,1,1,1,1,1,1,0},
+    {0x1.0000000000001p+0,-0x1p+1,1,1,1,1,1,1,0},
+    {0x1.0000000000001p+0,-0x1.fffffffffffffp-1,1,1,1,1,1,1,0},
+    {0x1.0000000000001p+0,-0x1p-1022,1,1,1,1,1,1,0},
+    {0x1.0000000000001p+0,-0x1.fffffcp-1023,1,1,1,1,1,1,0},
+    {0x1.0000000000001p+0,-0x1p-1074,1,1,1,1,1,1,0},
+    {0x1.0000000000001p+0,-0x0p+0,1,1,1,1,1,1,0},
+    {0x1.0000000000001p+0,0x0p+0,1,1,1,1,1,1,0},
+    {0x1.0000000000001p+0,0x1p-1074,1,1,1,1,1,1,0},
+    {0x1.0000000000001p+0,0x1.fffffcp-1023,1,1,1,1,1,1,0},
+    {0x1.0000000000001p+0,0x1p-1022,1,1,1,1,1,1,0},
+    {0x1.0000000000001p+0,0x1.fffffffffffffp-1,1,1,1,1,1,1,0},
+    {0x1.0000000000001p+0,0x1p+0,1,1,1,1,1,1,0},
+    {0x1.0000000000001p+0,0x1.0000000000001p+0,0,0,0,0,0,0,0},
+    {0x1.0000000000001p+0,0x1.fffffffffffffp+1023,-1,-1,-1,-1,-1,-1,0},
+    {0x1.0000000000001p+0,__builtin_inf(),-1,-1,-1,-1,-1,-1,0},
+    {0x1.fffffffffffffp+1023,__builtin_nan(""),1,-1,-1,1,1,1,1},
+    {0x1.fffffffffffffp+1023,-__builtin_inf(),1,1,1,1,1,1,0},
+    {0x1.fffffffffffffp+1023,-0x1.fffffffffffffp+1023,1,1,1,1,1,1,0},
+    {0x1.fffffffffffffp+1023,-0x1p+1,1,1,1,1,1,1,0},
+    {0x1.fffffffffffffp+1023,-0x1.fffffffffffffp-1,1,1,1,1,1,1,0},
+    {0x1.fffffffffffffp+1023,-0x1p-1022,1,1,1,1,1,1,0},
+    {0x1.fffffffffffffp+1023,-0x1.fffffcp-1023,1,1,1,1,1,1,0},
+    {0x1.fffffffffffffp+1023,-0x1p-1074,1,1,1,1,1,1,0},
+    {0x1.fffffffffffffp+1023,-0x0p+0,1,1,1,1,1,1,0},
+    {0x1.fffffffffffffp+1023,0x0p+0,1,1,1,1,1,1,0},
+    {0x1.fffffffffffffp+1023,0x1p-1074,1,1,1,1,1,1,0},
+    {0x1.fffffffffffffp+1023,0x1.fffffcp-1023,1,1,1,1,1,1,0},
+    {0x1.fffffffffffffp+1023,0x1p-1022,1,1,1,1,1,1,0},
+    {0x1.fffffffffffffp+1023,0x1.fffffffffffffp-1,1,1,1,1,1,1,0},
+    {0x1.fffffffffffffp+1023,0x1p+0,1,1,1,1,1,1,0},
+    {0x1.fffffffffffffp+1023,0x1.0000000000001p+0,1,1,1,1,1,1,0},
+    {0x1.fffffffffffffp+1023,0x1.fffffffffffffp+1023,0,0,0,0,0,0,0},
+    {0x1.fffffffffffffp+1023,__builtin_inf(),-1,-1,-1,-1,-1,-1,0},
+    {__builtin_inf(),__builtin_nan(""),1,-1,-1,1,1,1,1},
+    {__builtin_inf(),-__builtin_inf(),1,1,1,1,1,1,0},
+    {__builtin_inf(),-0x1.fffffffffffffp+1023,1,1,1,1,1,1,0},
+    {__builtin_inf(),-0x1p+1,1,1,1,1,1,1,0},
+    {__builtin_inf(),-0x1.fffffffffffffp-1,1,1,1,1,1,1,0},
+    {__builtin_inf(),-0x1p-1022,1,1,1,1,1,1,0},
+    {__builtin_inf(),-0x1.fffffcp-1023,1,1,1,1,1,1,0},
+    {__builtin_inf(),-0x1p-1074,1,1,1,1,1,1,0},
+    {__builtin_inf(),-0x0p+0,1,1,1,1,1,1,0},
+    {__builtin_inf(),0x0p+0,1,1,1,1,1,1,0},
+    {__builtin_inf(),0x1p-1074,1,1,1,1,1,1,0},
+    {__builtin_inf(),0x1.fffffcp-1023,1,1,1,1,1,1,0},
+    {__builtin_inf(),0x1p-1022,1,1,1,1,1,1,0},
+    {__builtin_inf(),0x1.fffffffffffffp-1,1,1,1,1,1,1,0},
+    {__builtin_inf(),0x1p+0,1,1,1,1,1,1,0},
+    {__builtin_inf(),0x1.0000000000001p+0,1,1,1,1,1,1,0},
+    {__builtin_inf(),0x1.fffffffffffffp+1023,1,1,1,1,1,1,0},
+    {__builtin_inf(),__builtin_inf(),0,0,0,0,0,0,0},
+};    
+
+int main(int argc, char *argv[]) {
+    const int numVectors = sizeof vectors / sizeof vectors[0];
+    int i;
+    for (i = 0; i<numVectors; ++i) {
+        if (test__cmpdf2(&vectors[i])) return 1;
+    }
+    return 0;
+}

Added: compiler-rt/trunk/test/Unit/comparesf2_test.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/test/Unit/comparesf2_test.c?rev=107414&view=auto
==============================================================================
--- compiler-rt/trunk/test/Unit/comparesf2_test.c (added)
+++ compiler-rt/trunk/test/Unit/comparesf2_test.c Thu Jul  1 13:35:50 2010
@@ -0,0 +1,479 @@
+//===-- cmpsf2_test.c - Test __cmpsf2 -------------------------------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file tests single-precision soft-float comparisons for the compiler-rt
+// library.
+//
+//===----------------------------------------------------------------------===//
+
+#include <stdio.h>
+
+int __eqsf2(float, float);
+int __gesf2(float, float);
+int __gtsf2(float, float);
+int __lesf2(float, float);
+int __ltsf2(float, float);
+int __nesf2(float, float);
+int __unordsf2(float, float);
+
+struct TestVector {
+    float a;
+    float b;
+    int eqReference;
+    int geReference;
+    int gtReference;
+    int leReference;
+    int ltReference;
+    int neReference;
+    int unReference;
+};
+
+int test__cmpsf2(const struct TestVector *vector) {
+    
+    if (__eqsf2(vector->a, vector->b) != vector->eqReference) {
+        printf("error in __eqsf2(%a, %a) = %d, expected %d\n",
+               vector->a, vector->b,
+               __eqsf2(vector->a, vector->b),
+               vector->eqReference);
+        return 1;
+    }
+    
+    if (__gesf2(vector->a, vector->b) != vector->geReference) {
+        printf("error in __gesf2(%a, %a) = %d, expected %d\n",
+               vector->a, vector->b,
+               __gesf2(vector->a, vector->b),
+               vector->geReference);
+        return 1;
+    }
+    
+    if (__gtsf2(vector->a, vector->b) != vector->gtReference) {
+        printf("error in __gtsf2(%a, %a) = %d, expected %d\n",
+               vector->a, vector->b,
+               __gtsf2(vector->a, vector->b),
+               vector->gtReference);
+        return 1;
+    }
+    
+    if (__lesf2(vector->a, vector->b) != vector->leReference) {
+        printf("error in __lesf2(%a, %a) = %d, expected %d\n",
+               vector->a, vector->b,
+               __lesf2(vector->a, vector->b),
+               vector->leReference);
+        return 1;
+    }
+    
+    if (__ltsf2(vector->a, vector->b) != vector->ltReference) {
+        printf("error in __ltsf2(%a, %a) = %d, expected %d\n",
+               vector->a, vector->b,
+               __ltsf2(vector->a, vector->b),
+               vector->ltReference);
+        return 1;
+    }
+    
+    if (__nesf2(vector->a, vector->b) != vector->neReference) {
+        printf("error in __nesf2(%a, %a) = %d, expected %d\n",
+               vector->a, vector->b,
+               __nesf2(vector->a, vector->b),
+               vector->neReference);
+        return 1;
+    }
+    
+    if (__unordsf2(vector->a, vector->b) != vector->unReference) {
+        printf("error in __unordsf2(%a, %a) = %d, expected %d\n",
+               vector->a, vector->b,
+               __unordsf2(vector->a, vector->b),
+               vector->unReference);
+        return 1;
+    }
+    
+    return 0;
+}
+
+/*
+void generateVectors() {
+    
+    const float arguments[] = {
+        __builtin_nanf(""),
+        -__builtin_inff(),
+        -0x1.fffffep127,
+        -0x1.000002p0
+        -0x1.000000p0,
+        -0x1.fffffep-1f,
+        -0x1.000000p-126f,
+        -0x0.fffffep-126f,
+        -0x0.000002p-126f,
+        -0.0,
+         0.0,
+         0x0.000002p-126f,
+         0x0.fffffep-126f,
+         0x1.000000p-126f,
+         0x1.fffffep-1f,
+         0x1.000000p0,
+         0x1.000002p0,
+         0x1.fffffep127,
+         __builtin_inff()
+    };
+    
+    int numArguments = sizeof arguments / sizeof arguments[0];
+    
+    for (int i=0; i<numArguments; ++i) {
+        for (int j=0; j<numArguments; ++j) {
+            const float a = arguments[i];
+            const float b = arguments[j];
+            const int leResult = a < b ? -1 : a == b ? 0 :  1;
+            const int geResult = a > b ?  1 : a == b ? 0 : -1;
+            const int unResult = a != a || b != b ? 1 : 0;
+            printf("{%a,%a,%d,%d,%d,%d,%d,%d,%d},\n",
+                   a, b, 
+                   leResult,
+                   geResult,
+                   geResult,
+                   leResult,
+                   leResult,
+                   leResult,
+                   unResult);
+        }
+    }
+} */
+
+static const struct TestVector vectors[] = {
+    {__builtin_nanf(""),__builtin_nanf(""),1,-1,-1,1,1,1,1},
+    {__builtin_nanf(""),-__builtin_inff(),1,-1,-1,1,1,1,1},
+    {__builtin_nanf(""),-0x1.fffffep+127f,1,-1,-1,1,1,1,1},
+    {__builtin_nanf(""),-0x1p0f,1,-1,-1,1,1,1,1},
+    {__builtin_nanf(""),-0x1.fffffep-1f,1,-1,-1,1,1,1,1},
+    {__builtin_nanf(""),-0x1p-126f,1,-1,-1,1,1,1,1},
+    {__builtin_nanf(""),-0x1.fffffcp-127,1,-1,-1,1,1,1,1},
+    {__builtin_nanf(""),-0x1p-149f,1,-1,-1,1,1,1,1},
+    {__builtin_nanf(""),-0x0p0f,1,-1,-1,1,1,1,1},
+    {__builtin_nanf(""),0x0p0f,1,-1,-1,1,1,1,1},
+    {__builtin_nanf(""),0x1p-149f,1,-1,-1,1,1,1,1},
+    {__builtin_nanf(""),0x1.fffffcp-127,1,-1,-1,1,1,1,1},
+    {__builtin_nanf(""),0x1p-126f,1,-1,-1,1,1,1,1},
+    {__builtin_nanf(""),0x1.fffffep-1f,1,-1,-1,1,1,1,1},
+    {__builtin_nanf(""),0x1p0f,1,-1,-1,1,1,1,1},
+    {__builtin_nanf(""),0x1.000002p0f,1,-1,-1,1,1,1,1},
+    {__builtin_nanf(""),0x1.fffffep+127f,1,-1,-1,1,1,1,1},
+    {__builtin_nanf(""),__builtin_inff(),1,-1,-1,1,1,1,1},
+    {-__builtin_inff(),__builtin_nanf(""),1,-1,-1,1,1,1,1},
+    {-__builtin_inff(),-__builtin_inff(),0,0,0,0,0,0,0},
+    {-__builtin_inff(),-0x1.fffffep+127f,-1,-1,-1,-1,-1,-1,0},
+    {-__builtin_inff(),-0x1p0f,-1,-1,-1,-1,-1,-1,0},
+    {-__builtin_inff(),-0x1.fffffep-1f,-1,-1,-1,-1,-1,-1,0},
+    {-__builtin_inff(),-0x1p-126f,-1,-1,-1,-1,-1,-1,0},
+    {-__builtin_inff(),-0x1.fffffcp-127,-1,-1,-1,-1,-1,-1,0},
+    {-__builtin_inff(),-0x1p-149f,-1,-1,-1,-1,-1,-1,0},
+    {-__builtin_inff(),-0x0p0f,-1,-1,-1,-1,-1,-1,0},
+    {-__builtin_inff(),0x0p0f,-1,-1,-1,-1,-1,-1,0},
+    {-__builtin_inff(),0x1p-149f,-1,-1,-1,-1,-1,-1,0},
+    {-__builtin_inff(),0x1.fffffcp-127,-1,-1,-1,-1,-1,-1,0},
+    {-__builtin_inff(),0x1p-126f,-1,-1,-1,-1,-1,-1,0},
+    {-__builtin_inff(),0x1.fffffep-1f,-1,-1,-1,-1,-1,-1,0},
+    {-__builtin_inff(),0x1p0f,-1,-1,-1,-1,-1,-1,0},
+    {-__builtin_inff(),0x1.000002p0f,-1,-1,-1,-1,-1,-1,0},
+    {-__builtin_inff(),0x1.fffffep+127f,-1,-1,-1,-1,-1,-1,0},
+    {-__builtin_inff(),__builtin_inff(),-1,-1,-1,-1,-1,-1,0},
+    {-0x1.fffffep+127f,__builtin_nanf(""),1,-1,-1,1,1,1,1},
+    {-0x1.fffffep+127f,-__builtin_inff(),1,1,1,1,1,1,0},
+    {-0x1.fffffep+127f,-0x1.fffffep+127f,0,0,0,0,0,0,0},
+    {-0x1.fffffep+127f,-0x1p0f,-1,-1,-1,-1,-1,-1,0},
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+    {0x1p0f,-0x0p0f,1,1,1,1,1,1,0},
+    {0x1p0f,0x0p0f,1,1,1,1,1,1,0},
+    {0x1p0f,0x1p-149f,1,1,1,1,1,1,0},
+    {0x1p0f,0x1.fffffcp-127,1,1,1,1,1,1,0},
+    {0x1p0f,0x1p-126f,1,1,1,1,1,1,0},
+    {0x1p0f,0x1.fffffep-1f,1,1,1,1,1,1,0},
+    {0x1p0f,0x1p0f,0,0,0,0,0,0,0},
+    {0x1p0f,0x1.000002p0f,-1,-1,-1,-1,-1,-1,0},
+    {0x1p0f,0x1.fffffep+127f,-1,-1,-1,-1,-1,-1,0},
+    {0x1p0f,__builtin_inff(),-1,-1,-1,-1,-1,-1,0},
+    {0x1.000002p0f,__builtin_nanf(""),1,-1,-1,1,1,1,1},
+    {0x1.000002p0f,-__builtin_inff(),1,1,1,1,1,1,0},
+    {0x1.000002p0f,-0x1.fffffep+127f,1,1,1,1,1,1,0},
+    {0x1.000002p0f,-0x1p0f,1,1,1,1,1,1,0},
+    {0x1.000002p0f,-0x1.fffffep-1f,1,1,1,1,1,1,0},
+    {0x1.000002p0f,-0x1p-126f,1,1,1,1,1,1,0},
+    {0x1.000002p0f,-0x1.fffffcp-127,1,1,1,1,1,1,0},
+    {0x1.000002p0f,-0x1p-149f,1,1,1,1,1,1,0},
+    {0x1.000002p0f,-0x0p0f,1,1,1,1,1,1,0},
+    {0x1.000002p0f,0x0p0f,1,1,1,1,1,1,0},
+    {0x1.000002p0f,0x1p-149f,1,1,1,1,1,1,0},
+    {0x1.000002p0f,0x1.fffffcp-127,1,1,1,1,1,1,0},
+    {0x1.000002p0f,0x1p-126f,1,1,1,1,1,1,0},
+    {0x1.000002p0f,0x1.fffffep-1f,1,1,1,1,1,1,0},
+    {0x1.000002p0f,0x1p0f,1,1,1,1,1,1,0},
+    {0x1.000002p0f,0x1.000002p0f,0,0,0,0,0,0,0},
+    {0x1.000002p0f,0x1.fffffep+127f,-1,-1,-1,-1,-1,-1,0},
+    {0x1.000002p0f,__builtin_inff(),-1,-1,-1,-1,-1,-1,0},
+    {0x1.fffffep+127f,__builtin_nanf(""),1,-1,-1,1,1,1,1},
+    {0x1.fffffep+127f,-__builtin_inff(),1,1,1,1,1,1,0},
+    {0x1.fffffep+127f,-0x1.fffffep+127f,1,1,1,1,1,1,0},
+    {0x1.fffffep+127f,-0x1p0f,1,1,1,1,1,1,0},
+    {0x1.fffffep+127f,-0x1.fffffep-1f,1,1,1,1,1,1,0},
+    {0x1.fffffep+127f,-0x1p-126f,1,1,1,1,1,1,0},
+    {0x1.fffffep+127f,-0x1.fffffcp-127,1,1,1,1,1,1,0},
+    {0x1.fffffep+127f,-0x1p-149f,1,1,1,1,1,1,0},
+    {0x1.fffffep+127f,-0x0p0f,1,1,1,1,1,1,0},
+    {0x1.fffffep+127f,0x0p0f,1,1,1,1,1,1,0},
+    {0x1.fffffep+127f,0x1p-149f,1,1,1,1,1,1,0},
+    {0x1.fffffep+127f,0x1.fffffcp-127,1,1,1,1,1,1,0},
+    {0x1.fffffep+127f,0x1p-126f,1,1,1,1,1,1,0},
+    {0x1.fffffep+127f,0x1.fffffep-1f,1,1,1,1,1,1,0},
+    {0x1.fffffep+127f,0x1p0f,1,1,1,1,1,1,0},
+    {0x1.fffffep+127f,0x1.000002p0f,1,1,1,1,1,1,0},
+    {0x1.fffffep+127f,0x1.fffffep+127f,0,0,0,0,0,0,0},
+    {0x1.fffffep+127f,__builtin_inff(),-1,-1,-1,-1,-1,-1,0},
+    {__builtin_inff(),__builtin_nanf(""),1,-1,-1,1,1,1,1},
+    {__builtin_inff(),-__builtin_inff(),1,1,1,1,1,1,0},
+    {__builtin_inff(),-0x1.fffffep+127f,1,1,1,1,1,1,0},
+    {__builtin_inff(),-0x1p0f,1,1,1,1,1,1,0},
+    {__builtin_inff(),-0x1.fffffep-1f,1,1,1,1,1,1,0},
+    {__builtin_inff(),-0x1p-126f,1,1,1,1,1,1,0},
+    {__builtin_inff(),-0x1.fffffcp-127,1,1,1,1,1,1,0},
+    {__builtin_inff(),-0x1p-149f,1,1,1,1,1,1,0},
+    {__builtin_inff(),-0x0p0f,1,1,1,1,1,1,0},
+    {__builtin_inff(),0x0p0f,1,1,1,1,1,1,0},
+    {__builtin_inff(),0x1p-149f,1,1,1,1,1,1,0},
+    {__builtin_inff(),0x1.fffffcp-127,1,1,1,1,1,1,0},
+    {__builtin_inff(),0x1p-126f,1,1,1,1,1,1,0},
+    {__builtin_inff(),0x1.fffffep-1f,1,1,1,1,1,1,0},
+    {__builtin_inff(),0x1p0f,1,1,1,1,1,1,0},
+    {__builtin_inff(),0x1.000002p0f,1,1,1,1,1,1,0},
+    {__builtin_inff(),0x1.fffffep+127f,1,1,1,1,1,1,0},
+    {__builtin_inff(),__builtin_inff(),0,0,0,0,0,0,0},
+};    
+
+int main(int argc, char *argv[]) {
+    const int numVectors = sizeof vectors / sizeof vectors[0];
+    int i;
+    for (i = 0; i<numVectors; ++i) {
+        if (test__cmpsf2(&vectors[i])) return 1;
+    }
+    return 0;
+}




From clattner at apple.com  Thu Jul  1 14:43:38 2010
From: clattner at apple.com (Chris Lattner)
Date: Thu, 01 Jul 2010 12:43:38 -0700
Subject: [llvm-commits] [llvm] r107205 -
 in	/llvm/trunk:	bindings/ada/llvm/ docs/
 include/llvm-c/	include/llvm/	include/llvm/CodeGen/ include/llvm/MC/
 include/llvm/Target/	lib/AsmParser/ lib/Bitcode/Reader/	lib/Bitcode/Writer/
 lib/CodeGen/ lib/CodeGen/AsmPrinter/	lib/Linker/ lib/MC/	lib/Target/
 lib/Target/CppBackend/	lib/Target/XCore/AsmPrinter/	lib/Transforms/IPO/
 lib/VMCore/	tools/llvm-nm/
In-Reply-To: <7AB97E23-B4AA-4784-83D4-B31C6818EE09@gmail.com>
References: <20100629212400.DABF32A6C12C@llvm.org>
	<C7E3E4A7-A598-4C61-9513-2DFC7C2EC4CC@apple.com>
	<AF811FB0-E72D-44DD-8BBD-1C6D4971F1AF@gmail.com>
	<FA99D48A-0561-420D-AA6C-6983AB1AFEC9@apple.com>
	<9E57AC43-C5F3-418C-8159-F3AF703BA3F1@apple.com>
	<79223963-640D-43E4-BB73-0D3D9DD729D6@gmail.com>
	<CBE117B2-2498-4A1D-8967-0DC60214B58C@apple.com>
	<7AB97E23-B4AA-4784-83D4-B31C6818EE09@gmail.com>
Message-ID: <4A117D6F-C5D4-4FE5-A828-03F7897814E5@apple.com>

Please tailor this for Darwin, there is no reason to speculatively generalize this for targets that don't exist.  If a target starts existing that wants to use this, it will probably need other hooks.  Trying to anticipate this theoretical possibility just clutters the code.

-Chris

On Jul 1, 2010, at 1:35 AM, Bill Wendling <isanbard at gmail.com> wrote:

> On Jun 30, 2010, at 9:06 PM, Chris Lattner wrote:
> 
>> On Jun 30, 2010, at 11:47 AM, Bill Wendling wrote:
>> 
>>>> 
>>>> Unless someone here can really spell out what these things really
>>>> mean, without mentioning assembler directives, without mentioning
>>>> special label naming conventions, without describing it in terms of
>>>> what gcc does for Objective C, and without citing "this is what the
>>>> Objective C people say we need", and without excluding any magical
>>>> semantics, it would be best to avoid confusion.
>>>> 
>>> I view these linkages as being like their non-"linker linkage" counterparts, but that the linker will remove them from the final linked image. So, "linker_private" is "private" but the linker will remove it from the final linked image and so on. "linker_private_weak" has no non-"linker linkage" counterpart, but its semantics are a natural progression maybe?
>> 
>> The semantics are clear to me: "lfoo" labels are stripped by the linker, but cause multiple definition cause redefinition errors.  "weak lfoo" labels are stripped by the linker, but multiple definitions get merged.  This doesn't seem that complicated.
>> 
> It's not. And it's essentially what I wrote in the RFC that I sent to llvmdev. But you just used a special label naming convention in your description, which is one thing Dan asked not be used to define this.
> 
> My remaining concern is that you seem to be asking me to tailor this linkage type for a particular platform (Darwin).
> 
> -bw
> 


From dpatel at apple.com  Thu Jul  1 14:49:20 2010
From: dpatel at apple.com (Devang Patel)
Date: Thu, 01 Jul 2010 19:49:20 -0000
Subject: [llvm-commits] [llvm] r107416 - in /llvm/trunk:
 include/llvm/LinkAllPasses.h include/llvm/Transforms/IPO.h
 lib/Transforms/IPO/StripSymbols.cpp
 test/Transforms/StripSymbols/2010-07-01-DeadDbgInfo.ll
Message-ID: <20100701194920.B0FFB2A6C12C@llvm.org>

Author: dpatel
Date: Thu Jul  1 14:49:20 2010
New Revision: 107416

URL: http://llvm.org/viewvc/llvm-project?rev=107416&view=rev
Log:
Debugging infomration is encoded in llvm IR using metadata. This is designed
such a way that debug info for symbols preserved even if symbols are
optimized away by the optimizer. 

Add new special pass to remove debug info for such symbols.


Added:
    llvm/trunk/test/Transforms/StripSymbols/2010-07-01-DeadDbgInfo.ll
Modified:
    llvm/trunk/include/llvm/LinkAllPasses.h
    llvm/trunk/include/llvm/Transforms/IPO.h
    llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp

Modified: llvm/trunk/include/llvm/LinkAllPasses.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/LinkAllPasses.h?rev=107416&r1=107415&r2=107416&view=diff
==============================================================================
--- llvm/trunk/include/llvm/LinkAllPasses.h (original)
+++ llvm/trunk/include/llvm/LinkAllPasses.h Thu Jul  1 14:49:20 2010
@@ -113,6 +113,7 @@
       (void) llvm::createSingleLoopExtractorPass();
       (void) llvm::createStripSymbolsPass();
       (void) llvm::createStripNonDebugSymbolsPass();
+      (void) llvm::createStripDeadDebugInfoPass();
       (void) llvm::createStripDeadPrototypesPass();
       (void) llvm::createTailCallEliminationPass();
       (void) llvm::createTailDuplicationPass();

Modified: llvm/trunk/include/llvm/Transforms/IPO.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/IPO.h?rev=107416&r1=107415&r2=107416&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Transforms/IPO.h (original)
+++ llvm/trunk/include/llvm/Transforms/IPO.h Thu Jul  1 14:49:20 2010
@@ -45,6 +45,11 @@
 ModulePass *createStripDebugDeclarePass();
 
 //===----------------------------------------------------------------------===//
+//
+// These pass removes unused symbols' debug info.
+ModulePass *createStripDeadDebugInfoPass();
+
+//===----------------------------------------------------------------------===//
 /// createLowerSetJmpPass - This function lowers the setjmp/longjmp intrinsics
 /// to invoke/unwind instructions.  This should really be part of the C/C++
 /// front-end, but it's so much easier to write transformations in LLVM proper.

Modified: llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp?rev=107416&r1=107415&r2=107416&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp (original)
+++ llvm/trunk/lib/Transforms/IPO/StripSymbols.cpp Thu Jul  1 14:49:20 2010
@@ -73,6 +73,19 @@
       AU.setPreservesAll();
     }
   };
+
+  class StripDeadDebugInfo : public ModulePass {
+  public:
+    static char ID; // Pass identification, replacement for typeid
+    explicit StripDeadDebugInfo()
+      : ModulePass(&ID) {}
+
+    virtual bool runOnModule(Module &M);
+
+    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+      AU.setPreservesAll();
+    }
+  };
 }
 
 char StripSymbols::ID = 0;
@@ -99,6 +112,14 @@
   return new StripDebugDeclare();
 }
 
+char StripDeadDebugInfo::ID = 0;
+static RegisterPass<StripDeadDebugInfo>
+A("strip-dead-debug-info", "Strip debug info for unused symbols");
+
+ModulePass *llvm::createStripDeadDebugInfoPass() {
+  return new StripDeadDebugInfo();
+}
+
 /// OnlyUsedBy - Return true if V is only used by Usr.
 static bool OnlyUsedBy(Value *V, Value *Usr) {
   for(Value::use_iterator I = V->use_begin(), E = V->use_end(); I != E; ++I) {
@@ -295,3 +316,83 @@
 
   return true;
 }
+
+/// getRealLinkageName - If special LLVM prefix that is used to inform the asm 
+/// printer to not emit usual symbol prefix before the symbol name is used then
+/// return linkage name after skipping this special LLVM prefix.
+static StringRef getRealLinkageName(StringRef LinkageName) {
+  char One = '\1';
+  if (LinkageName.startswith(StringRef(&One, 1)))
+    return LinkageName.substr(1);
+  return LinkageName;
+}
+
+bool StripDeadDebugInfo::runOnModule(Module &M) {
+  bool Changed = false;
+
+  // Debugging infomration is encoded in llvm IR using metadata. This is designed
+  // such a way that debug info for symbols preserved even if symbols are
+  // optimized away by the optimizer. This special pass removes debug info for 
+  // such symbols.
+
+  // llvm.dbg.gv keeps track of debug info for global variables.
+  if (NamedMDNode *NMD = M.getNamedMetadata("llvm.dbg.gv")) {
+    SmallVector<MDNode *, 8> MDs;
+    for (unsigned i = 0, e = NMD->getNumOperands(); i != e; ++i)
+      if (DIGlobalVariable(NMD->getOperand(i)).Verify())
+        MDs.push_back(NMD->getOperand(i));
+      else
+        Changed = true;
+    NMD->eraseFromParent();
+    NMD = NULL;
+
+    for (SmallVector<MDNode *, 8>::iterator I = MDs.begin(),
+           E = MDs.end(); I != E; ++I) {
+      if (M.getGlobalVariable(DIGlobalVariable(*I).getGlobal()->getName(), 
+                              true)) {
+        if (!NMD)
+          NMD = M.getOrInsertNamedMetadata("llvm.dbg.gv");
+        NMD->addOperand(*I);
+      }
+      else
+        Changed = true;
+    }
+  }
+
+  // llvm.dbg.sp keeps track of debug info for subprograms.
+  if (NamedMDNode *NMD = M.getNamedMetadata("llvm.dbg.sp")) {
+    SmallVector<MDNode *, 8> MDs;
+    for (unsigned i = 0, e = NMD->getNumOperands(); i != e; ++i)
+      if (DISubprogram(NMD->getOperand(i)).Verify())
+        MDs.push_back(NMD->getOperand(i));
+      else
+        Changed = true;
+    NMD->eraseFromParent();
+    NMD = NULL;
+
+    for (SmallVector<MDNode *, 8>::iterator I = MDs.begin(),
+           E = MDs.end(); I != E; ++I) {
+      bool FnIsLive = false;
+      if (Function *F = DISubprogram(*I).getFunction())
+        if (M.getFunction(F->getName()))
+          FnIsLive = true;
+      if (FnIsLive) {
+          if (!NMD)
+            NMD = M.getOrInsertNamedMetadata("llvm.dbg.sp");
+          NMD->addOperand(*I);
+      } else {
+        // Remove llvm.dbg.lv.fnname named mdnode which may have been used
+        // to hold debug info for dead function's local variables.
+        StringRef FName = DISubprogram(*I).getLinkageName();
+        if (FName.empty())
+          FName = DISubprogram(*I).getName();
+        if (NamedMDNode *LVNMD = 
+            M.getNamedMetadata(Twine("llvm.dbg.lv.", 
+                                     getRealLinkageName(FName)))) 
+          LVNMD->eraseFromParent();
+      }
+    }
+  }
+
+  return Changed;
+}

Added: llvm/trunk/test/Transforms/StripSymbols/2010-07-01-DeadDbgInfo.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/StripSymbols/2010-07-01-DeadDbgInfo.ll?rev=107416&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/StripSymbols/2010-07-01-DeadDbgInfo.ll (added)
+++ llvm/trunk/test/Transforms/StripSymbols/2010-07-01-DeadDbgInfo.ll Thu Jul  1 14:49:20 2010
@@ -0,0 +1,47 @@
+; RUN: opt -strip-dead-debug-info | llvm-dis -o %t.ll
+; RUN: grep -v bar %t.ll
+; RUN: grep -v abcd %t.ll
+
+ at xyz = global i32 2                               ; <i32*> [#uses=1]
+
+declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
+
+define i32 @fn() nounwind readnone ssp {
+entry:
+  ret i32 0, !dbg !17
+}
+
+define i32 @foo(i32 %i) nounwind readonly ssp {
+entry:
+  tail call void @llvm.dbg.value(metadata !{i32 %i}, i64 0, metadata !14), !dbg !19
+  %.0 = load i32* @xyz, align 4                   ; <i32> [#uses=1]
+  ret i32 %.0, !dbg !20
+}
+
+!llvm.dbg.sp = !{!0, !5, !9}
+!llvm.dbg.lv.bar = !{!12}
+!llvm.dbg.lv.foo = !{!14}
+!llvm.dbg.gv = !{!15, !16}
+
+!0 = metadata !{i32 524334, i32 0, metadata !1, metadata !"bar", metadata !"bar", metadata !"", metadata !1, i32 5, metadata !3, i1 true, i1 true, i32 0, i32 0, null, i1 false, i1 true, null} ; [ DW_TAG_subprogram ]
+!1 = metadata !{i32 524329, metadata !"g.c", metadata !"/tmp/", metadata !2} ; [ DW_TAG_file_type ]
+!2 = metadata !{i32 524305, i32 0, i32 1, metadata !"g.c", metadata !"/tmp/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
+!3 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!4 = metadata !{null}
+!5 = metadata !{i32 524334, i32 0, metadata !1, metadata !"fn", metadata !"fn", metadata !"fn", metadata !1, i32 6, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, i32 ()* @fn} ; [ DW_TAG_subprogram ]
+!6 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!7 = metadata !{metadata !8}
+!8 = metadata !{i32 524324, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!9 = metadata !{i32 524334, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"foo", metadata !1, i32 7, metadata !10, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, i32 (i32)* @foo} ; [ DW_TAG_subprogram ]
+!10 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!11 = metadata !{metadata !8, metadata !8}
+!12 = metadata !{i32 524544, metadata !13, metadata !"bb", metadata !1, i32 5, metadata !8} ; [ DW_TAG_auto_variable ]
+!13 = metadata !{i32 524299, metadata !0, i32 5, i32 0} ; [ DW_TAG_lexical_block ]
+!14 = metadata !{i32 524545, metadata !9, metadata !"i", metadata !1, i32 7, metadata !8} ; [ DW_TAG_arg_variable ]
+!15 = metadata !{i32 524340, i32 0, metadata !1, metadata !"abcd", metadata !"abcd", metadata !"", metadata !1, i32 2, metadata !8, i1 true, i1 true, null} ; [ DW_TAG_variable ]
+!16 = metadata !{i32 524340, i32 0, metadata !1, metadata !"xyz", metadata !"xyz", metadata !"", metadata !1, i32 3, metadata !8, i1 false, i1 true, i32* @xyz} ; [ DW_TAG_variable ]
+!17 = metadata !{i32 6, i32 0, metadata !18, null}
+!18 = metadata !{i32 524299, metadata !5, i32 6, i32 0} ; [ DW_TAG_lexical_block ]
+!19 = metadata !{i32 7, i32 0, metadata !9, null}
+!20 = metadata !{i32 10, i32 0, metadata !21, null}
+!21 = metadata !{i32 524299, metadata !9, i32 7, i32 0} ; [ DW_TAG_lexical_block ]




From dpatel at apple.com  Thu Jul  1 14:58:05 2010
From: dpatel at apple.com (Devang Patel)
Date: Thu, 01 Jul 2010 19:58:05 -0000
Subject: [llvm-commits] [llvm] r107417 -
	/llvm/trunk/tools/llvm-extract/llvm-extract.cpp
Message-ID: <20100701195805.5D1C52A6C12C@llvm.org>

Author: dpatel
Date: Thu Jul  1 14:58:05 2010
New Revision: 107417

URL: http://llvm.org/viewvc/llvm-project?rev=107417&view=rev
Log:
Preserve debug info for only extracted symbols.

Modified:
    llvm/trunk/tools/llvm-extract/llvm-extract.cpp

Modified: llvm/trunk/tools/llvm-extract/llvm-extract.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-extract/llvm-extract.cpp?rev=107417&r1=107416&r2=107417&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-extract/llvm-extract.cpp (original)
+++ llvm/trunk/tools/llvm-extract/llvm-extract.cpp Thu Jul  1 14:58:05 2010
@@ -112,6 +112,7 @@
   Passes.add(createGVExtractionPass(GVs, DeleteFn, Relink));
   if (!DeleteFn)
     Passes.add(createGlobalDCEPass());           // Delete unreachable globals
+  Passes.add(createStripDeadDebugInfoPass());    // Remove dead debug info
   Passes.add(createDeadTypeEliminationPass());   // Remove dead types...
   Passes.add(createStripDeadPrototypesPass());   // Remove dead func decls
 




From daniel at zuster.org  Thu Jul  1 15:07:24 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 01 Jul 2010 20:07:24 -0000
Subject: [llvm-commits] [llvm] r107418 - in /llvm/trunk:
 include/llvm/MC/MCSectionCOFF.h include/llvm/Support/COFF.h
 lib/CodeGen/TargetLoweringObjectFileImpl.cpp lib/MC/MCSectionCOFF.cpp
Message-ID: <20100701200724.B33432A6C12C@llvm.org>

Author: ddunbar
Date: Thu Jul  1 15:07:24 2010
New Revision: 107418

URL: http://llvm.org/viewvc/llvm-project?rev=107418&view=rev
Log:
MC: Move COFF enumeration constants to llvm/Support/COFF.h, patch by Michael
Spencer!

Added:
    llvm/trunk/include/llvm/Support/COFF.h
Modified:
    llvm/trunk/include/llvm/MC/MCSectionCOFF.h
    llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
    llvm/trunk/lib/MC/MCSectionCOFF.cpp

Modified: llvm/trunk/include/llvm/MC/MCSectionCOFF.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCSectionCOFF.h?rev=107418&r1=107417&r2=107418&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCSectionCOFF.h (original)
+++ llvm/trunk/include/llvm/MC/MCSectionCOFF.h Thu Jul  1 15:07:24 2010
@@ -16,6 +16,8 @@
 
 #include "llvm/MC/MCSection.h"
 
+#include "llvm/Support/COFF.h"
+
 namespace llvm {
   
 /// MCSectionCOFF - This represents a section on Windows
@@ -47,56 +49,6 @@
     /// should be printed before the section name
     bool ShouldOmitSectionDirective(StringRef Name, const MCAsmInfo &MAI) const;
 
-    //FIXME: all COFF enumerations/flags should be standardized into one place...
-    // Target/X86COFF.h doesn't seem right as COFF can be used for other targets,
-    // MC/WinCOFF.h maybe right as it isn't target or entity specific, and it is
-    //   pretty low on the dependancy graph (is there any need to support non
-    //   windows COFF?)
-    // here is good for section stuff, but others should go elsewhere
-
-    /// Valid section flags.
-    enum {
-      IMAGE_SCN_TYPE_NO_PAD                     = 0x00000008,
-      IMAGE_SCN_CNT_CODE                        = 0x00000020,
-      IMAGE_SCN_CNT_INITIALIZED_DATA            = 0x00000040,
-      IMAGE_SCN_CNT_UNINITIALIZED_DATA          = 0x00000080,
-      IMAGE_SCN_LNK_OTHER                       = 0x00000100,
-      IMAGE_SCN_LNK_INFO                        = 0x00000200,
-      IMAGE_SCN_LNK_REMOVE                      = 0x00000800,
-      IMAGE_SCN_LNK_COMDAT                      = 0x00001000,
-      IMAGE_SCN_MEM_FARDATA                     = 0x00008000,
-      IMAGE_SCN_MEM_PURGEABLE                   = 0x00020000,
-      IMAGE_SCN_MEM_16BIT                       = 0x00020000,
-      IMAGE_SCN_MEM_LOCKED                      = 0x00040000,
-      IMAGE_SCN_MEM_PRELOAD                     = 0x00080000,
-      /* these are handled elsewhere
-      IMAGE_SCN_ALIGN_1BYTES                    = 0x00100000,
-      IMAGE_SCN_ALIGN_2BYTES                    = 0x00200000,
-      IMAGE_SCN_ALIGN_4BYTES                    = 0x00300000,
-      IMAGE_SCN_ALIGN_8BYTES                    = 0x00400000,
-      IMAGE_SCN_ALIGN_16BYTES                   = 0x00500000,
-      IMAGE_SCN_ALIGN_32BYTES                   = 0x00600000,
-      IMAGE_SCN_ALIGN_64BYTES                   = 0x00700000,
-      */
-      IMAGE_SCN_LNK_NRELOC_OVFL                 = 0x01000000,
-      IMAGE_SCN_MEM_DISCARDABLE                 = 0x02000000,
-      IMAGE_SCN_MEM_NOT_CACHED                  = 0x04000000,
-      IMAGE_SCN_MEM_NOT_PAGED                   = 0x08000000,
-      IMAGE_SCN_MEM_SHARED                      = 0x10000000,
-      IMAGE_SCN_MEM_EXECUTE                     = 0x20000000,
-      IMAGE_SCN_MEM_READ                        = 0x40000000,
-      IMAGE_SCN_MEM_WRITE                       = 0x80000000
-    };
-
-    enum {
-      IMAGE_COMDAT_SELECT_NODUPLICATES = 1,
-      IMAGE_COMDAT_SELECT_ANY,
-      IMAGE_COMDAT_SELECT_SAME_SIZE,
-      IMAGE_COMDAT_SELECT_EXACT_MATCH,
-      IMAGE_COMDAT_SELECT_ASSOCIATIVE,
-      IMAGE_COMDAT_SELECT_LARGEST
-    };
-
     StringRef getSectionName() const { return SectionName; }
     unsigned getCharacteristics() const { return Characteristics; }
     int getSelection () const { return Selection; }

Added: llvm/trunk/include/llvm/Support/COFF.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/COFF.h?rev=107418&view=auto
==============================================================================
--- llvm/trunk/include/llvm/Support/COFF.h (added)
+++ llvm/trunk/include/llvm/Support/COFF.h Thu Jul  1 15:07:24 2010
@@ -0,0 +1,183 @@
+//===-- llvm/Support/COFF.h -------------------------------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains an definitions used in Windows COFF Files.
+//
+// Structures and enums defined within this file where created using
+// information from Microsofts publicly available PE/COFF format document:
+// 
+// Microsoft Portable Executable and Common Object File Format Specification
+// Revision 8.1 - February 15, 2008
+//
+// As of 5/2/2010, hosted by microsoft at:
+// http://www.microsoft.com/whdc/system/platform/firmware/pecoff.mspx
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_SUPPORT_WIN_COFF_H
+#define LLVM_SUPPORT_WIN_COFF_H
+
+#include "llvm/System/DataTypes.h"
+#include <cstring>
+
+namespace llvm {
+namespace COFF {
+
+  // Sizes in bytes of various things in the COFF format.
+  enum {
+    HeaderSize     = 20,
+    NameSize       = 8,
+    SymbolSize     = 18,
+    SectionSize    = 40,
+    RelocationSize = 10
+  };
+
+  struct header {
+    uint16_t Machine;
+    uint16_t NumberOfSections;
+    uint32_t TimeDateStamp;
+    uint32_t PointerToSymbolTable;
+    uint32_t NumberOfSymbols;
+    uint16_t SizeOfOptionalHeader;
+    uint16_t Characteristics;
+  };
+
+  struct symbol {
+    char     Name[NameSize];
+    uint32_t Value;
+    uint16_t Type;
+    uint8_t  StorageClass;
+    uint16_t SectionNumber;
+    uint8_t  NumberOfAuxSymbols;
+  };
+
+  enum symbol_flags {
+    SF_TypeMask = 0x0000FFFF,
+    SF_TypeShift = 0,
+
+    SF_ClassMask = 0x00FF0000,
+    SF_ClassShift = 16,
+
+    SF_WeakReference = 0x01000000,
+  };
+
+  enum symbol_storage_class {
+    IMAGE_SYM_CLASS_END_OF_FUNCTION  = -1,
+    IMAGE_SYM_CLASS_NULL             = 0,
+    IMAGE_SYM_CLASS_AUTOMATIC        = 1,
+    IMAGE_SYM_CLASS_EXTERNAL         = 2,
+    IMAGE_SYM_CLASS_STATIC           = 3,
+    IMAGE_SYM_CLASS_REGISTER         = 4,
+    IMAGE_SYM_CLASS_EXTERNAL_DEF     = 5,
+    IMAGE_SYM_CLASS_LABEL            = 6,
+    IMAGE_SYM_CLASS_UNDEFINED_LABEL  = 7,
+    IMAGE_SYM_CLASS_MEMBER_OF_STRUCT = 8,
+    IMAGE_SYM_CLASS_ARGUMENT         = 9,
+    IMAGE_SYM_CLASS_STRUCT_TAG       = 10,
+    IMAGE_SYM_CLASS_MEMBER_OF_UNION  = 11,
+    IMAGE_SYM_CLASS_UNION_TAG        = 12,
+    IMAGE_SYM_CLASS_TYPE_DEFINITION  = 13,
+    IMAGE_SYM_CLASS_UNDEFINED_STATIC = 14,
+    IMAGE_SYM_CLASS_ENUM_TAG         = 15,
+    IMAGE_SYM_CLASS_MEMBER_OF_ENUM   = 16,
+    IMAGE_SYM_CLASS_REGISTER_PARAM   = 17,
+    IMAGE_SYM_CLASS_BIT_FIELD        = 18,
+    IMAGE_SYM_CLASS_BLOCK            = 100,
+    IMAGE_SYM_CLASS_FUNCTION         = 101,
+    IMAGE_SYM_CLASS_END_OF_STRUCT    = 102,
+    IMAGE_SYM_CLASS_FILE             = 103,
+    IMAGE_SYM_CLASS_SECTION          = 104,
+    IMAGE_SYM_CLASS_WEAK_EXTERNAL    = 105,
+    IMAGE_SYM_CLASS_CLR_TOKEN        = 107
+  };
+
+  struct section {
+    char     Name[NameSize];
+    uint32_t VirtualSize;
+    uint32_t VirtualAddress;
+    uint32_t SizeOfRawData;
+    uint32_t PointerToRawData;
+    uint32_t PointerToRelocations;
+    uint32_t PointerToLineNumbers;
+    uint16_t NumberOfRelocations;
+    uint16_t NumberOfLineNumbers;
+    uint32_t Characteristics;
+  };
+
+  enum section_characteristics {
+    IMAGE_SCN_TYPE_NO_PAD            = 0x00000008,
+    IMAGE_SCN_CNT_CODE               = 0x00000020,
+    IMAGE_SCN_CNT_INITIALIZED_DATA   = 0x00000040,
+    IMAGE_SCN_CNT_UNINITIALIZED_DATA = 0x00000080,
+    IMAGE_SCN_LNK_OTHER              = 0x00000100,
+    IMAGE_SCN_LNK_INFO               = 0x00000200,
+    IMAGE_SCN_LNK_REMOVE             = 0x00000800,
+    IMAGE_SCN_LNK_COMDAT             = 0x00001000,
+    IMAGE_SCN_GPREL                  = 0x00008000,
+    IMAGE_SCN_MEM_PURGEABLE          = 0x00020000,
+    IMAGE_SCN_MEM_16BIT              = 0x00020000,
+    IMAGE_SCN_MEM_LOCKED             = 0x00040000,
+    IMAGE_SCN_MEM_PRELOAD            = 0x00080000,
+    IMAGE_SCN_ALIGN_1BYTES           = 0x00100000,
+    IMAGE_SCN_ALIGN_2BYTES           = 0x00200000,
+    IMAGE_SCN_ALIGN_4BYTES           = 0x00300000,
+    IMAGE_SCN_ALIGN_8BYTES           = 0x00400000,
+    IMAGE_SCN_ALIGN_16BYTES          = 0x00500000,
+    IMAGE_SCN_ALIGN_32BYTES          = 0x00600000,
+    IMAGE_SCN_ALIGN_64BYTES          = 0x00700000,
+    IMAGE_SCN_ALIGN_128BYTES         = 0x00800000,
+    IMAGE_SCN_ALIGN_256BYTES         = 0x00900000,
+    IMAGE_SCN_ALIGN_512BYTES         = 0x00A00000,
+    IMAGE_SCN_ALIGN_1024BYTES        = 0x00B00000,
+    IMAGE_SCN_ALIGN_2048BYTES        = 0x00C00000,
+    IMAGE_SCN_ALIGN_4096BYTES        = 0x00D00000,
+    IMAGE_SCN_ALIGN_8192BYTES        = 0x00E00000,
+    IMAGE_SCN_LNK_NRELOC_OVFL        = 0x01000000,
+    IMAGE_SCN_MEM_DISCARDABLE        = 0x02000000,
+    IMAGE_SCN_MEM_NOT_CACHED         = 0x04000000,
+    IMAGE_SCN_MEM_NOT_PAGED          = 0x08000000,
+    IMAGE_SCN_MEM_SHARED             = 0x10000000,
+    IMAGE_SCN_MEM_EXECUTE            = 0x20000000,
+    IMAGE_SCN_MEM_READ               = 0x40000000,
+    IMAGE_SCN_MEM_WRITE              = 0x80000000
+  };
+
+  struct relocation {
+    uint32_t VirtualAddress;
+    uint32_t SymbolTableIndex;
+    uint16_t Type;
+  };
+
+  enum relocation_type_x86 {
+    IMAGE_REL_I386_ABSOLUTE = 0x0000,
+    IMAGE_REL_I386_DIR16    = 0x0001,
+    IMAGE_REL_I386_REL16    = 0x0002,
+    IMAGE_REL_I386_DIR32    = 0x0006,
+    IMAGE_REL_I386_DIR32NB  = 0x0007,
+    IMAGE_REL_I386_SEG12    = 0x0009,
+    IMAGE_REL_I386_SECTION  = 0x000A,
+    IMAGE_REL_I386_SECREL   = 0x000B,
+    IMAGE_REL_I386_TOKEN    = 0x000C,
+    IMAGE_REL_I386_SECREL7  = 0x000D,
+    IMAGE_REL_I386_REL32    = 0x0014
+  };
+
+  enum {
+    IMAGE_COMDAT_SELECT_NODUPLICATES = 1,
+    IMAGE_COMDAT_SELECT_ANY,
+    IMAGE_COMDAT_SELECT_SAME_SIZE,
+    IMAGE_COMDAT_SELECT_EXACT_MATCH,
+    IMAGE_COMDAT_SELECT_ASSOCIATIVE,
+    IMAGE_COMDAT_SELECT_LARGEST
+  };
+
+} // End namespace llvm.
+} // End namespace COFF.
+
+#endif

Modified: llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp?rev=107418&r1=107417&r2=107418&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp Thu Jul  1 15:07:24 2010
@@ -825,32 +825,32 @@
   TargetLoweringObjectFile::Initialize(Ctx, TM);
   TextSection =
     getContext().getCOFFSection(".text",
-                                MCSectionCOFF::IMAGE_SCN_CNT_CODE |
-                                MCSectionCOFF::IMAGE_SCN_MEM_EXECUTE |
-                                MCSectionCOFF::IMAGE_SCN_MEM_READ,
+                                COFF::IMAGE_SCN_CNT_CODE |
+                                COFF::IMAGE_SCN_MEM_EXECUTE |
+                                COFF::IMAGE_SCN_MEM_READ,
                                 SectionKind::getText());
   DataSection =
     getContext().getCOFFSection(".data",
-                                MCSectionCOFF::IMAGE_SCN_CNT_INITIALIZED_DATA |
-                                MCSectionCOFF::IMAGE_SCN_MEM_READ |
-                                MCSectionCOFF::IMAGE_SCN_MEM_WRITE,
+                                COFF::IMAGE_SCN_CNT_INITIALIZED_DATA |
+                                COFF::IMAGE_SCN_MEM_READ |
+                                COFF::IMAGE_SCN_MEM_WRITE,
                                 SectionKind::getDataRel());
   ReadOnlySection =
     getContext().getCOFFSection(".rdata",
-                                MCSectionCOFF::IMAGE_SCN_CNT_INITIALIZED_DATA |
-                                MCSectionCOFF::IMAGE_SCN_MEM_READ,
+                                COFF::IMAGE_SCN_CNT_INITIALIZED_DATA |
+                                COFF::IMAGE_SCN_MEM_READ,
                                 SectionKind::getReadOnly());
   StaticCtorSection =
     getContext().getCOFFSection(".ctors",
-                                MCSectionCOFF::IMAGE_SCN_CNT_INITIALIZED_DATA |
-                                MCSectionCOFF::IMAGE_SCN_MEM_READ |
-                                MCSectionCOFF::IMAGE_SCN_MEM_WRITE,
+                                COFF::IMAGE_SCN_CNT_INITIALIZED_DATA |
+                                COFF::IMAGE_SCN_MEM_READ |
+                                COFF::IMAGE_SCN_MEM_WRITE,
                                 SectionKind::getDataRel());
   StaticDtorSection =
     getContext().getCOFFSection(".dtors",
-                                MCSectionCOFF::IMAGE_SCN_CNT_INITIALIZED_DATA |
-                                MCSectionCOFF::IMAGE_SCN_MEM_READ |
-                                MCSectionCOFF::IMAGE_SCN_MEM_WRITE,
+                                COFF::IMAGE_SCN_CNT_INITIALIZED_DATA |
+                                COFF::IMAGE_SCN_MEM_READ |
+                                COFF::IMAGE_SCN_MEM_WRITE,
                                 SectionKind::getDataRel());
 
   // FIXME: We're emitting LSDA info into a readonly section on COFF, even
@@ -859,76 +859,76 @@
   // adjusted or this should be a data section.
   LSDASection =
     getContext().getCOFFSection(".gcc_except_table",
-                                MCSectionCOFF::IMAGE_SCN_CNT_INITIALIZED_DATA |
-                                MCSectionCOFF::IMAGE_SCN_MEM_READ,
+                                COFF::IMAGE_SCN_CNT_INITIALIZED_DATA |
+                                COFF::IMAGE_SCN_MEM_READ,
                                 SectionKind::getReadOnly());
   EHFrameSection =
     getContext().getCOFFSection(".eh_frame",
-                                MCSectionCOFF::IMAGE_SCN_CNT_INITIALIZED_DATA |
-                                MCSectionCOFF::IMAGE_SCN_MEM_READ |
-                                MCSectionCOFF::IMAGE_SCN_MEM_WRITE,
+                                COFF::IMAGE_SCN_CNT_INITIALIZED_DATA |
+                                COFF::IMAGE_SCN_MEM_READ |
+                                COFF::IMAGE_SCN_MEM_WRITE,
                                 SectionKind::getDataRel());
 
   // Debug info.
   DwarfAbbrevSection =
     getContext().getCOFFSection(".debug_abbrev",
-                                MCSectionCOFF::IMAGE_SCN_MEM_DISCARDABLE |
-                                MCSectionCOFF::IMAGE_SCN_MEM_READ,
+                                COFF::IMAGE_SCN_MEM_DISCARDABLE |
+                                COFF::IMAGE_SCN_MEM_READ,
                                 SectionKind::getMetadata());
   DwarfInfoSection =
     getContext().getCOFFSection(".debug_info",
-                                MCSectionCOFF::IMAGE_SCN_MEM_DISCARDABLE |
-                                MCSectionCOFF::IMAGE_SCN_MEM_READ,
+                                COFF::IMAGE_SCN_MEM_DISCARDABLE |
+                                COFF::IMAGE_SCN_MEM_READ,
                                 SectionKind::getMetadata());
   DwarfLineSection =
     getContext().getCOFFSection(".debug_line",
-                                MCSectionCOFF::IMAGE_SCN_MEM_DISCARDABLE |
-                                MCSectionCOFF::IMAGE_SCN_MEM_READ,
+                                COFF::IMAGE_SCN_MEM_DISCARDABLE |
+                                COFF::IMAGE_SCN_MEM_READ,
                                 SectionKind::getMetadata());
   DwarfFrameSection =
     getContext().getCOFFSection(".debug_frame",
-                                MCSectionCOFF::IMAGE_SCN_MEM_DISCARDABLE |
-                                MCSectionCOFF::IMAGE_SCN_MEM_READ,
+                                COFF::IMAGE_SCN_MEM_DISCARDABLE |
+                                COFF::IMAGE_SCN_MEM_READ,
                                 SectionKind::getMetadata());
   DwarfPubNamesSection =
     getContext().getCOFFSection(".debug_pubnames",
-                                MCSectionCOFF::IMAGE_SCN_MEM_DISCARDABLE |
-                                MCSectionCOFF::IMAGE_SCN_MEM_READ,
+                                COFF::IMAGE_SCN_MEM_DISCARDABLE |
+                                COFF::IMAGE_SCN_MEM_READ,
                                 SectionKind::getMetadata());
   DwarfPubTypesSection =
     getContext().getCOFFSection(".debug_pubtypes",
-                                MCSectionCOFF::IMAGE_SCN_MEM_DISCARDABLE |
-                                MCSectionCOFF::IMAGE_SCN_MEM_READ,
+                                COFF::IMAGE_SCN_MEM_DISCARDABLE |
+                                COFF::IMAGE_SCN_MEM_READ,
                                 SectionKind::getMetadata());
   DwarfStrSection =
     getContext().getCOFFSection(".debug_str",
-                                MCSectionCOFF::IMAGE_SCN_MEM_DISCARDABLE |
-                                MCSectionCOFF::IMAGE_SCN_MEM_READ,
+                                COFF::IMAGE_SCN_MEM_DISCARDABLE |
+                                COFF::IMAGE_SCN_MEM_READ,
                                 SectionKind::getMetadata());
   DwarfLocSection =
     getContext().getCOFFSection(".debug_loc",
-                                MCSectionCOFF::IMAGE_SCN_MEM_DISCARDABLE |
-                                MCSectionCOFF::IMAGE_SCN_MEM_READ,
+                                COFF::IMAGE_SCN_MEM_DISCARDABLE |
+                                COFF::IMAGE_SCN_MEM_READ,
                                 SectionKind::getMetadata());
   DwarfARangesSection =
     getContext().getCOFFSection(".debug_aranges",
-                                MCSectionCOFF::IMAGE_SCN_MEM_DISCARDABLE |
-                                MCSectionCOFF::IMAGE_SCN_MEM_READ,
+                                COFF::IMAGE_SCN_MEM_DISCARDABLE |
+                                COFF::IMAGE_SCN_MEM_READ,
                                 SectionKind::getMetadata());
   DwarfRangesSection =
     getContext().getCOFFSection(".debug_ranges",
-                                MCSectionCOFF::IMAGE_SCN_MEM_DISCARDABLE |
-                                MCSectionCOFF::IMAGE_SCN_MEM_READ,
+                                COFF::IMAGE_SCN_MEM_DISCARDABLE |
+                                COFF::IMAGE_SCN_MEM_READ,
                                 SectionKind::getMetadata());
   DwarfMacroInfoSection =
     getContext().getCOFFSection(".debug_macinfo",
-                                MCSectionCOFF::IMAGE_SCN_MEM_DISCARDABLE |
-                                MCSectionCOFF::IMAGE_SCN_MEM_READ,
+                                COFF::IMAGE_SCN_MEM_DISCARDABLE |
+                                COFF::IMAGE_SCN_MEM_READ,
                                 SectionKind::getMetadata());
 
   DrectveSection =
     getContext().getCOFFSection(".drectve",
-                                MCSectionCOFF::IMAGE_SCN_LNK_INFO,
+                                COFF::IMAGE_SCN_LNK_INFO,
                                 SectionKind::getMetadata());
 }
 
@@ -938,25 +938,25 @@
 
   if (!K.isMetadata())
     Flags |=
-      MCSectionCOFF::IMAGE_SCN_MEM_DISCARDABLE;
+      COFF::IMAGE_SCN_MEM_DISCARDABLE;
   else if (K.isText())
     Flags |=
-      MCSectionCOFF::IMAGE_SCN_MEM_EXECUTE |
-      MCSectionCOFF::IMAGE_SCN_CNT_CODE;
+      COFF::IMAGE_SCN_MEM_EXECUTE |
+      COFF::IMAGE_SCN_CNT_CODE;
   else if (K.isBSS ())
     Flags |=
-      MCSectionCOFF::IMAGE_SCN_CNT_UNINITIALIZED_DATA |
-      MCSectionCOFF::IMAGE_SCN_MEM_READ |
-      MCSectionCOFF::IMAGE_SCN_MEM_WRITE;
+      COFF::IMAGE_SCN_CNT_UNINITIALIZED_DATA |
+      COFF::IMAGE_SCN_MEM_READ |
+      COFF::IMAGE_SCN_MEM_WRITE;
   else if (K.isReadOnly())
     Flags |=
-      MCSectionCOFF::IMAGE_SCN_CNT_INITIALIZED_DATA |
-      MCSectionCOFF::IMAGE_SCN_MEM_READ;
+      COFF::IMAGE_SCN_CNT_INITIALIZED_DATA |
+      COFF::IMAGE_SCN_MEM_READ;
   else if (K.isWriteable())
     Flags |=
-      MCSectionCOFF::IMAGE_SCN_CNT_INITIALIZED_DATA |
-      MCSectionCOFF::IMAGE_SCN_MEM_READ |
-      MCSectionCOFF::IMAGE_SCN_MEM_WRITE;
+      COFF::IMAGE_SCN_CNT_INITIALIZED_DATA |
+      COFF::IMAGE_SCN_MEM_READ |
+      COFF::IMAGE_SCN_MEM_WRITE;
 
   return Flags;
 }
@@ -995,10 +995,10 @@
 
     unsigned Characteristics = getCOFFSectionFlags(Kind);
 
-    Characteristics |= MCSectionCOFF::IMAGE_SCN_LNK_COMDAT;
+    Characteristics |= COFF::IMAGE_SCN_LNK_COMDAT;
 
     return getContext().getCOFFSection(Name.str(), Characteristics,
-                          MCSectionCOFF::IMAGE_COMDAT_SELECT_EXACT_MATCH, Kind);
+                          COFF::IMAGE_COMDAT_SELECT_EXACT_MATCH, Kind);
   }
 
   if (Kind.isText())

Modified: llvm/trunk/lib/MC/MCSectionCOFF.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCSectionCOFF.cpp?rev=107418&r1=107417&r2=107418&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCSectionCOFF.cpp (original)
+++ llvm/trunk/lib/MC/MCSectionCOFF.cpp Thu Jul  1 15:07:24 2010
@@ -44,28 +44,28 @@
     OS << 'w';
   else
     OS << 'r';
-  if (getCharacteristics() & MCSectionCOFF::IMAGE_SCN_MEM_DISCARDABLE)
+  if (getCharacteristics() & COFF::IMAGE_SCN_MEM_DISCARDABLE)
     OS << 'n';
   OS << "\"\n";
   
-  if (getCharacteristics() & MCSectionCOFF::IMAGE_SCN_LNK_COMDAT) {
+  if (getCharacteristics() & COFF::IMAGE_SCN_LNK_COMDAT) {
     switch (Selection) {
-      case IMAGE_COMDAT_SELECT_NODUPLICATES:
+      case COFF::IMAGE_COMDAT_SELECT_NODUPLICATES:
         OS << "\t.linkonce one_only\n";
         break;
-      case IMAGE_COMDAT_SELECT_ANY:
+      case COFF::IMAGE_COMDAT_SELECT_ANY:
         OS << "\t.linkonce discard\n";
         break;
-      case IMAGE_COMDAT_SELECT_SAME_SIZE:
+      case COFF::IMAGE_COMDAT_SELECT_SAME_SIZE:
         OS << "\t.linkonce same_size\n";
         break;
-      case IMAGE_COMDAT_SELECT_EXACT_MATCH:
+      case COFF::IMAGE_COMDAT_SELECT_EXACT_MATCH:
         OS << "\t.linkonce same_contents\n";
         break;
     //NOTE: as of binutils 2.20, there is no way to specifiy select largest
     //      with the .linkonce directive. For now, we treat it as an invalid
     //      comdat selection value.
-      case IMAGE_COMDAT_SELECT_LARGEST:
+      case COFF::IMAGE_COMDAT_SELECT_LARGEST:
     //  OS << "\t.linkonce largest\n";
     //  break;
       default:




From gohman at apple.com  Thu Jul  1 15:08:40 2010
From: gohman at apple.com (Dan Gohman)
Date: Thu, 01 Jul 2010 20:08:40 -0000
Subject: [llvm-commits] [llvm] r107420 - in /llvm/trunk:
 lib/Analysis/BasicAliasAnalysis.cpp
 test/Analysis/BasicAA/args-rets-allocas-loads.ll
 test/Analysis/BasicAA/interprocedural.ll
Message-ID: <20100701200840.70FA82A6C12C@llvm.org>

Author: djg
Date: Thu Jul  1 15:08:40 2010
New Revision: 107420

URL: http://llvm.org/viewvc/llvm-project?rev=107420&view=rev
Log:
Remove context sensitivity concerns from interprocedural-basic-aa, and
make it more aggressive in cases where both pointers are known to live
in the same function.

Added:
    llvm/trunk/test/Analysis/BasicAA/args-rets-allocas-loads.ll
Modified:
    llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp
    llvm/trunk/test/Analysis/BasicAA/interprocedural.ll

Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=107420&r1=107419&r2=107420&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original)
+++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Thu Jul  1 15:08:40 2010
@@ -55,10 +55,9 @@
 
 /// isNonEscapingLocalObject - Return true if the pointer is to a function-local
 /// object that never escapes from the function.
-static bool isNonEscapingLocalObject(const Value *V, bool Interprocedural) {
+static bool isNonEscapingLocalObject(const Value *V) {
   // If this is a local allocation, check to see if it escapes.
-  if (isa<AllocaInst>(V) ||
-      (!Interprocedural && isNoAliasCall(V)))
+  if (isa<AllocaInst>(V) || isNoAliasCall(V))
     // Set StoreCaptures to True so that we can assume in our callers that the
     // pointer is not the result of a load instruction. Currently
     // PointerMayBeCaptured doesn't have any special analysis for the
@@ -69,23 +68,21 @@
   // If this is an argument that corresponds to a byval or noalias argument,
   // then it has not escaped before entering the function.  Check if it escapes
   // inside the function.
-  if (!Interprocedural)
-    if (const Argument *A = dyn_cast<Argument>(V))
-      if (A->hasByValAttr() || A->hasNoAliasAttr()) {
-        // Don't bother analyzing arguments already known not to escape.
-        if (A->hasNoCaptureAttr())
-          return true;
-        return !PointerMayBeCaptured(V, false, /*StoreCaptures=*/true);
-      }
+  if (const Argument *A = dyn_cast<Argument>(V))
+    if (A->hasByValAttr() || A->hasNoAliasAttr()) {
+      // Don't bother analyzing arguments already known not to escape.
+      if (A->hasNoCaptureAttr())
+        return true;
+      return !PointerMayBeCaptured(V, false, /*StoreCaptures=*/true);
+    }
   return false;
 }
 
 /// isEscapeSource - Return true if the pointer is one which would have
 /// been considered an escape by isNonEscapingLocalObject.
-static bool isEscapeSource(const Value *V, bool Interprocedural) {
-  if (!Interprocedural)
-    if (isa<CallInst>(V) || isa<InvokeInst>(V) || isa<Argument>(V))
-      return true;
+static bool isEscapeSource(const Value *V) {
+  if (isa<CallInst>(V) || isa<InvokeInst>(V) || isa<Argument>(V))
+    return true;
 
   // The load case works because isNonEscapingLocalObject considers all
   // stores to be escapes (it passes true for the StoreCaptures argument
@@ -197,7 +194,6 @@
 // BasicAliasAnalysis Pass
 //===----------------------------------------------------------------------===//
 
-#ifdef XDEBUG
 static const Function *getParent(const Value *V) {
   if (const Instruction *inst = dyn_cast<Instruction>(V))
     return inst->getParent()->getParent();
@@ -213,6 +209,15 @@
   const Function *F1 = getParent(O1);
   const Function *F2 = getParent(O2);
 
+  return F1 && F1 == F2;
+}
+
+#ifdef XDEBUG
+static bool notDifferentParent(const Value *O1, const Value *O2) {
+
+  const Function *F1 = getParent(O1);
+  const Function *F2 = getParent(O2);
+
   return !F1 || !F2 || F1 == F2;
 }
 #endif
@@ -236,7 +241,7 @@
                       const Value *V2, unsigned V2Size) {
       assert(Visited.empty() && "Visited must be cleared after use!");
 #ifdef XDEBUG
-      assert((Interprocedural || sameParent(V1, V2)) &&
+      assert((Interprocedural || notDifferentParent(V1, V2)) &&
              "BasicAliasAnalysis (-basicaa) doesn't support interprocedural "
              "queries; use InterproceduralAliasAnalysis "
              "(-interprocedural-basic-aa) instead.");
@@ -331,11 +336,17 @@
       if (CI->isTailCall())
         return NoModRef;
   
+  // If we can identify an object and it's known to be within the
+  // same function as the call, we can ignore interprocedural concerns.
+  bool EffectivelyInterprocedural =
+    Interprocedural && !sameParent(Object, CS.getInstruction());
+  
   // If the pointer is to a locally allocated object that does not escape,
   // then the call can not mod/ref the pointer unless the call takes the pointer
   // as an argument, and itself doesn't capture it.
   if (!isa<Constant>(Object) && CS.getInstruction() != Object &&
-      isNonEscapingLocalObject(Object, Interprocedural)) {
+      !EffectivelyInterprocedural &&
+      isNonEscapingLocalObject(Object)) {
     bool PassedAsArg = false;
     unsigned ArgNo = 0;
     for (CallSite::arg_iterator CI = CS.arg_begin(), CE = CS.arg_end();
@@ -754,27 +765,32 @@
     if (CPN->getType()->getAddressSpace() == 0)
       return NoAlias;
 
+  // If we can identify two objects and they're known to be within the
+  // same function, we can ignore interprocedural concerns.
+  bool EffectivelyInterprocedural =
+    Interprocedural && !sameParent(O1, O2);
+
   if (O1 != O2) {
     // If V1/V2 point to two different objects we know that we have no alias.
-    if (isIdentifiedObject(O1, Interprocedural) &&
-        isIdentifiedObject(O2, Interprocedural))
+    if (isIdentifiedObject(O1, EffectivelyInterprocedural) &&
+        isIdentifiedObject(O2, EffectivelyInterprocedural))
       return NoAlias;
 
     // Constant pointers can't alias with non-const isIdentifiedObject objects.
     if ((isa<Constant>(O1) &&
-         isIdentifiedObject(O2, Interprocedural) &&
+         isIdentifiedObject(O2, EffectivelyInterprocedural) &&
          !isa<Constant>(O2)) ||
         (isa<Constant>(O2) &&
-         isIdentifiedObject(O1, Interprocedural) &&
+         isIdentifiedObject(O1, EffectivelyInterprocedural) &&
          !isa<Constant>(O1)))
       return NoAlias;
 
-    // Arguments can't alias with local allocations or noalias calls, unless
-    // we have to consider interprocedural aliasing.
-    if (!Interprocedural)
-      if ((isa<Argument>(O1) && (isa<AllocaInst>(O2) || isNoAliasCall(O2))) ||
-          (isa<Argument>(O2) && (isa<AllocaInst>(O1) || isNoAliasCall(O1))))
-        return NoAlias;
+    // Arguments can't alias with local allocations or noalias calls
+    // in the same function.
+    if (!EffectivelyInterprocedural &&
+        ((isa<Argument>(O1) && (isa<AllocaInst>(O2) || isNoAliasCall(O2))) ||
+         (isa<Argument>(O2) && (isa<AllocaInst>(O1) || isNoAliasCall(O1)))))
+      return NoAlias;
 
     // Most objects can't alias null.
     if ((isa<ConstantPointerNull>(V2) && isKnownNonNull(O1)) ||
@@ -790,14 +806,18 @@
       return NoAlias;
   
   // If one pointer is the result of a call/invoke or load and the other is a
-  // non-escaping local object, then we know the object couldn't escape to a
-  // point where the call could return it.
-  if (O1 != O2) {
-    if (isEscapeSource(O1, Interprocedural) &&
-        isNonEscapingLocalObject(O2, Interprocedural))
+  // non-escaping local object within the same function, then we know the
+  // object couldn't escape to a point where the call could return it.
+  //
+  // Note that if the pointers are in different functions, there are a
+  // variety of complications. A call with a nocapture argument may still
+  // temporary store the nocapture argument's value in a temporary memory
+  // location if that memory location doesn't escape. Or it may pass a
+  // nocapture value to other functions as long as they don't capture it.
+  if (O1 != O2 && !EffectivelyInterprocedural) {
+    if (isEscapeSource(O1) && isNonEscapingLocalObject(O2))
       return NoAlias;
-    if (isEscapeSource(O2, Interprocedural) &&
-        isNonEscapingLocalObject(O1, Interprocedural))
+    if (isEscapeSource(O2) && isNonEscapingLocalObject(O1))
       return NoAlias;
   }
 

Added: llvm/trunk/test/Analysis/BasicAA/args-rets-allocas-loads.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/BasicAA/args-rets-allocas-loads.ll?rev=107420&view=auto
==============================================================================
--- llvm/trunk/test/Analysis/BasicAA/args-rets-allocas-loads.ll (added)
+++ llvm/trunk/test/Analysis/BasicAA/args-rets-allocas-loads.ll Thu Jul  1 15:08:40 2010
@@ -0,0 +1,1722 @@
+; RUN: opt -interprocedural-basic-aa -interprocedural-aa-eval -print-all-alias-modref-info -disable-output < %s |& FileCheck --check-prefix=IPAA %s
+; RUN: opt -basicaa -aa-eval -print-all-alias-modref-info -disable-output < %s |& FileCheck --check-prefix=FUNCAA %s
+
+declare void @callee(double* %callee_arg)
+declare void @nocap_callee(double* nocapture %nocap_callee_arg)
+
+declare double* @normal_returner()
+declare noalias double* @noalias_returner()
+
+define void @caller_a(double* %arg_a0,
+                      double* %arg_a1,
+                      double* noalias %noalias_arg_a0,
+                      double* noalias %noalias_arg_a1,
+                      double** %indirect_a0,
+                      double** %indirect_a1) {
+  %loaded_a0 = load double** %indirect_a0
+  %loaded_a1 = load double** %indirect_a1
+
+  %escape_alloca_a0 = alloca double
+  %escape_alloca_a1 = alloca double
+  %noescape_alloca_a0 = alloca double
+  %noescape_alloca_a1 = alloca double
+
+  %normal_ret_a0 = call double* @normal_returner()
+  %normal_ret_a1 = call double* @normal_returner()
+  %noalias_ret_a0 = call double* @noalias_returner()
+  %noalias_ret_a1 = call double* @noalias_returner()
+
+  call void @callee(double* %escape_alloca_a0)
+  call void @callee(double* %escape_alloca_a1)
+  call void @nocap_callee(double* %noescape_alloca_a0)
+  call void @nocap_callee(double* %noescape_alloca_a1)
+
+  store double 0.0, double* %loaded_a0
+  store double 0.0, double* %loaded_a1
+  store double 0.0, double* %arg_a0
+  store double 0.0, double* %arg_a1
+  store double 0.0, double* %noalias_arg_a0
+  store double 0.0, double* %noalias_arg_a1
+  store double 0.0, double* %escape_alloca_a0
+  store double 0.0, double* %escape_alloca_a1
+  store double 0.0, double* %noescape_alloca_a0
+  store double 0.0, double* %noescape_alloca_a1
+  store double 0.0, double* %normal_ret_a0
+  store double 0.0, double* %normal_ret_a1
+  store double 0.0, double* %noalias_ret_a0
+  store double 0.0, double* %noalias_ret_a1
+  ret void
+}
+
+; caller_b is the same as caller_a but with different names, to test
+; interprocedural queries.
+define void @caller_b(double* %arg_b0,
+                      double* %arg_b1,
+                      double* noalias %noalias_arg_b0,
+                      double* noalias %noalias_arg_b1,
+                      double** %indirect_b0,
+                      double** %indirect_b1) {
+  %loaded_b0 = load double** %indirect_b0
+  %loaded_b1 = load double** %indirect_b1
+
+  %escape_alloca_b0 = alloca double
+  %escape_alloca_b1 = alloca double
+  %noescape_alloca_b0 = alloca double
+  %noescape_alloca_b1 = alloca double
+
+  %normal_ret_b0 = call double* @normal_returner()
+  %normal_ret_b1 = call double* @normal_returner()
+  %noalias_ret_b0 = call double* @noalias_returner()
+  %noalias_ret_b1 = call double* @noalias_returner()
+
+  call void @callee(double* %escape_alloca_b0)
+  call void @callee(double* %escape_alloca_b1)
+  call void @nocap_callee(double* %noescape_alloca_b0)
+  call void @nocap_callee(double* %noescape_alloca_b1)
+
+  store double 0.0, double* %loaded_b0
+  store double 0.0, double* %loaded_b1
+  store double 0.0, double* %arg_b0
+  store double 0.0, double* %arg_b1
+  store double 0.0, double* %noalias_arg_b0
+  store double 0.0, double* %noalias_arg_b1
+  store double 0.0, double* %escape_alloca_b0
+  store double 0.0, double* %escape_alloca_b1
+  store double 0.0, double* %noescape_alloca_b0
+  store double 0.0, double* %noescape_alloca_b1
+  store double 0.0, double* %normal_ret_b0
+  store double 0.0, double* %normal_ret_b1
+  store double 0.0, double* %noalias_ret_b0
+  store double 0.0, double* %noalias_ret_b1
+  ret void
+}
+
+; FUNCAA: Function: caller_a: 16 pointers, 8 call sites
+; FUNCAA:   MayAlias:	double* %arg_a0, double* %arg_a1
+; FUNCAA:   NoAlias:	double* %arg_a0, double* %noalias_arg_a0
+; FUNCAA:   NoAlias:	double* %arg_a1, double* %noalias_arg_a0
+; FUNCAA:   NoAlias:	double* %arg_a0, double* %noalias_arg_a1
+; FUNCAA:   NoAlias:	double* %arg_a1, double* %noalias_arg_a1
+; FUNCAA:   NoAlias:	double* %noalias_arg_a0, double* %noalias_arg_a1
+; FUNCAA:   MayAlias:	double* %arg_a0, double** %indirect_a0
+; FUNCAA:   MayAlias:	double* %arg_a1, double** %indirect_a0
+; FUNCAA:   NoAlias:	double* %noalias_arg_a0, double** %indirect_a0
+; FUNCAA:   NoAlias:	double* %noalias_arg_a1, double** %indirect_a0
+; FUNCAA:   MayAlias:	double* %arg_a0, double** %indirect_a1
+; FUNCAA:   MayAlias:	double* %arg_a1, double** %indirect_a1
+; FUNCAA:   NoAlias:	double* %noalias_arg_a0, double** %indirect_a1
+; FUNCAA:   NoAlias:	double* %noalias_arg_a1, double** %indirect_a1
+; FUNCAA:   MayAlias:	double** %indirect_a0, double** %indirect_a1
+; FUNCAA:   MayAlias:	double* %arg_a0, double* %loaded_a0
+; FUNCAA:   MayAlias:	double* %arg_a1, double* %loaded_a0
+; FUNCAA:   NoAlias:	double* %loaded_a0, double* %noalias_arg_a0
+; FUNCAA:   NoAlias:	double* %loaded_a0, double* %noalias_arg_a1
+; FUNCAA:   MayAlias:	double* %loaded_a0, double** %indirect_a0
+; FUNCAA:   MayAlias:	double* %loaded_a0, double** %indirect_a1
+; FUNCAA:   MayAlias:	double* %arg_a0, double* %loaded_a1
+; FUNCAA:   MayAlias:	double* %arg_a1, double* %loaded_a1
+; FUNCAA:   NoAlias:	double* %loaded_a1, double* %noalias_arg_a0
+; FUNCAA:   NoAlias:	double* %loaded_a1, double* %noalias_arg_a1
+; FUNCAA:   MayAlias:	double* %loaded_a1, double** %indirect_a0
+; FUNCAA:   MayAlias:	double* %loaded_a1, double** %indirect_a1
+; FUNCAA:   MayAlias:	double* %loaded_a0, double* %loaded_a1
+; FUNCAA:   NoAlias:	double* %arg_a0, double* %escape_alloca_a0
+; FUNCAA:   NoAlias:	double* %arg_a1, double* %escape_alloca_a0
+; FUNCAA:   NoAlias:	double* %escape_alloca_a0, double* %noalias_arg_a0
+; FUNCAA:   NoAlias:	double* %escape_alloca_a0, double* %noalias_arg_a1
+; FUNCAA:   NoAlias:	double* %escape_alloca_a0, double** %indirect_a0
+; FUNCAA:   NoAlias:	double* %escape_alloca_a0, double** %indirect_a1
+; FUNCAA:   MayAlias:	double* %escape_alloca_a0, double* %loaded_a0
+; FUNCAA:   MayAlias:	double* %escape_alloca_a0, double* %loaded_a1
+; FUNCAA:   NoAlias:	double* %arg_a0, double* %escape_alloca_a1
+; FUNCAA:   NoAlias:	double* %arg_a1, double* %escape_alloca_a1
+; FUNCAA:   NoAlias:	double* %escape_alloca_a1, double* %noalias_arg_a0
+; FUNCAA:   NoAlias:	double* %escape_alloca_a1, double* %noalias_arg_a1
+; FUNCAA:   NoAlias:	double* %escape_alloca_a1, double** %indirect_a0
+; FUNCAA:   NoAlias:	double* %escape_alloca_a1, double** %indirect_a1
+; FUNCAA:   MayAlias:	double* %escape_alloca_a1, double* %loaded_a0
+; FUNCAA:   MayAlias:	double* %escape_alloca_a1, double* %loaded_a1
+; FUNCAA:   NoAlias:	double* %escape_alloca_a0, double* %escape_alloca_a1
+; FUNCAA:   NoAlias:	double* %arg_a0, double* %noescape_alloca_a0
+; FUNCAA:   NoAlias:	double* %arg_a1, double* %noescape_alloca_a0
+; FUNCAA:   NoAlias:	double* %noalias_arg_a0, double* %noescape_alloca_a0
+; FUNCAA:   NoAlias:	double* %noalias_arg_a1, double* %noescape_alloca_a0
+; FUNCAA:   NoAlias:	double* %noescape_alloca_a0, double** %indirect_a0
+; FUNCAA:   NoAlias:	double* %noescape_alloca_a0, double** %indirect_a1
+; FUNCAA:   NoAlias:	double* %loaded_a0, double* %noescape_alloca_a0
+; FUNCAA:   NoAlias:	double* %loaded_a1, double* %noescape_alloca_a0
+; FUNCAA:   NoAlias:	double* %escape_alloca_a0, double* %noescape_alloca_a0
+; FUNCAA:   NoAlias:	double* %escape_alloca_a1, double* %noescape_alloca_a0
+; FUNCAA:   NoAlias:	double* %arg_a0, double* %noescape_alloca_a1
+; FUNCAA:   NoAlias:	double* %arg_a1, double* %noescape_alloca_a1
+; FUNCAA:   NoAlias:	double* %noalias_arg_a0, double* %noescape_alloca_a1
+; FUNCAA:   NoAlias:	double* %noalias_arg_a1, double* %noescape_alloca_a1
+; FUNCAA:   NoAlias:	double* %noescape_alloca_a1, double** %indirect_a0
+; FUNCAA:   NoAlias:	double* %noescape_alloca_a1, double** %indirect_a1
+; FUNCAA:   NoAlias:	double* %loaded_a0, double* %noescape_alloca_a1
+; FUNCAA:   NoAlias:	double* %loaded_a1, double* %noescape_alloca_a1
+; FUNCAA:   NoAlias:	double* %escape_alloca_a0, double* %noescape_alloca_a1
+; FUNCAA:   NoAlias:	double* %escape_alloca_a1, double* %noescape_alloca_a1
+; FUNCAA:   NoAlias:	double* %noescape_alloca_a0, double* %noescape_alloca_a1
+; FUNCAA:   MayAlias:	double* %arg_a0, double* %normal_ret_a0
+; FUNCAA:   MayAlias:	double* %arg_a1, double* %normal_ret_a0
+; FUNCAA:   NoAlias:	double* %noalias_arg_a0, double* %normal_ret_a0
+; FUNCAA:   NoAlias:	double* %noalias_arg_a1, double* %normal_ret_a0
+; FUNCAA:   MayAlias:	double* %normal_ret_a0, double** %indirect_a0
+; FUNCAA:   MayAlias:	double* %normal_ret_a0, double** %indirect_a1
+; FUNCAA:   MayAlias:	double* %loaded_a0, double* %normal_ret_a0
+; FUNCAA:   MayAlias:	double* %loaded_a1, double* %normal_ret_a0
+; FUNCAA:   MayAlias:	double* %escape_alloca_a0, double* %normal_ret_a0
+; FUNCAA:   MayAlias:	double* %escape_alloca_a1, double* %normal_ret_a0
+; FUNCAA:   NoAlias:	double* %noescape_alloca_a0, double* %normal_ret_a0
+; FUNCAA:   NoAlias:	double* %noescape_alloca_a1, double* %normal_ret_a0
+; FUNCAA:   MayAlias:	double* %arg_a0, double* %normal_ret_a1
+; FUNCAA:   MayAlias:	double* %arg_a1, double* %normal_ret_a1
+; FUNCAA:   NoAlias:	double* %noalias_arg_a0, double* %normal_ret_a1
+; FUNCAA:   NoAlias:	double* %noalias_arg_a1, double* %normal_ret_a1
+; FUNCAA:   MayAlias:	double* %normal_ret_a1, double** %indirect_a0
+; FUNCAA:   MayAlias:	double* %normal_ret_a1, double** %indirect_a1
+; FUNCAA:   MayAlias:	double* %loaded_a0, double* %normal_ret_a1
+; FUNCAA:   MayAlias:	double* %loaded_a1, double* %normal_ret_a1
+; FUNCAA:   MayAlias:	double* %escape_alloca_a0, double* %normal_ret_a1
+; FUNCAA:   MayAlias:	double* %escape_alloca_a1, double* %normal_ret_a1
+; FUNCAA:   NoAlias:	double* %noescape_alloca_a0, double* %normal_ret_a1
+; FUNCAA:   NoAlias:	double* %noescape_alloca_a1, double* %normal_ret_a1
+; FUNCAA:   MayAlias:	double* %normal_ret_a0, double* %normal_ret_a1
+; FUNCAA:   NoAlias:	double* %arg_a0, double* %noalias_ret_a0
+; FUNCAA:   NoAlias:	double* %arg_a1, double* %noalias_ret_a0
+; FUNCAA:   NoAlias:	double* %noalias_arg_a0, double* %noalias_ret_a0
+; FUNCAA:   NoAlias:	double* %noalias_arg_a1, double* %noalias_ret_a0
+; FUNCAA:   NoAlias:	double* %noalias_ret_a0, double** %indirect_a0
+; FUNCAA:   NoAlias:	double* %noalias_ret_a0, double** %indirect_a1
+; FUNCAA:   NoAlias:	double* %loaded_a0, double* %noalias_ret_a0
+; FUNCAA:   NoAlias:	double* %loaded_a1, double* %noalias_ret_a0
+; FUNCAA:   NoAlias:	double* %escape_alloca_a0, double* %noalias_ret_a0
+; FUNCAA:   NoAlias:	double* %escape_alloca_a1, double* %noalias_ret_a0
+; FUNCAA:   NoAlias:	double* %noalias_ret_a0, double* %noescape_alloca_a0
+; FUNCAA:   NoAlias:	double* %noalias_ret_a0, double* %noescape_alloca_a1
+; FUNCAA:   NoAlias:	double* %noalias_ret_a0, double* %normal_ret_a0
+; FUNCAA:   NoAlias:	double* %noalias_ret_a0, double* %normal_ret_a1
+; FUNCAA:   NoAlias:	double* %arg_a0, double* %noalias_ret_a1
+; FUNCAA:   NoAlias:	double* %arg_a1, double* %noalias_ret_a1
+; FUNCAA:   NoAlias:	double* %noalias_arg_a0, double* %noalias_ret_a1
+; FUNCAA:   NoAlias:	double* %noalias_arg_a1, double* %noalias_ret_a1
+; FUNCAA:   NoAlias:	double* %noalias_ret_a1, double** %indirect_a0
+; FUNCAA:   NoAlias:	double* %noalias_ret_a1, double** %indirect_a1
+; FUNCAA:   NoAlias:	double* %loaded_a0, double* %noalias_ret_a1
+; FUNCAA:   NoAlias:	double* %loaded_a1, double* %noalias_ret_a1
+; FUNCAA:   NoAlias:	double* %escape_alloca_a0, double* %noalias_ret_a1
+; FUNCAA:   NoAlias:	double* %escape_alloca_a1, double* %noalias_ret_a1
+; FUNCAA:   NoAlias:	double* %noalias_ret_a1, double* %noescape_alloca_a0
+; FUNCAA:   NoAlias:	double* %noalias_ret_a1, double* %noescape_alloca_a1
+; FUNCAA:   NoAlias:	double* %noalias_ret_a1, double* %normal_ret_a0
+; FUNCAA:   NoAlias:	double* %noalias_ret_a1, double* %normal_ret_a1
+; FUNCAA:   NoAlias:	double* %noalias_ret_a0, double* %noalias_ret_a1
+; FUNCAA:     ModRef:  Ptr: double* %arg_a0	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %arg_a1	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_arg_a0	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_arg_a1	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double** %indirect_a0	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double** %indirect_a1	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %loaded_a0	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %loaded_a1	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %escape_alloca_a0	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %escape_alloca_a1	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noescape_alloca_a0	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noescape_alloca_a1	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %normal_ret_a0	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %normal_ret_a1	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_ret_a0	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_ret_a1	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %arg_a0	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %arg_a1	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_arg_a0	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_arg_a1	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double** %indirect_a0	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double** %indirect_a1	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %loaded_a0	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %loaded_a1	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %escape_alloca_a0	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %escape_alloca_a1	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noescape_alloca_a0	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noescape_alloca_a1	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %normal_ret_a0	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %normal_ret_a1	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_ret_a0	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_ret_a1	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %arg_a0	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %arg_a1	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_arg_a0	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_arg_a1	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double** %indirect_a0	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double** %indirect_a1	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %loaded_a0	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %loaded_a1	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %escape_alloca_a0	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %escape_alloca_a1	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noescape_alloca_a0	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noescape_alloca_a1	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %normal_ret_a0	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %normal_ret_a1	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %noalias_ret_a0	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_ret_a1	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %arg_a0	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %arg_a1	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_arg_a0	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_arg_a1	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double** %indirect_a0	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double** %indirect_a1	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %loaded_a0	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %loaded_a1	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %escape_alloca_a0	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %escape_alloca_a1	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noescape_alloca_a0	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noescape_alloca_a1	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %normal_ret_a0	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %normal_ret_a1	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_ret_a0	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %noalias_ret_a1	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %arg_a0	<->  call void @callee(double* %escape_alloca_a0)
+; FUNCAA:     ModRef:  Ptr: double* %arg_a1	<->  call void @callee(double* %escape_alloca_a0)
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_arg_a0	<->  call void @callee(double* %escape_alloca_a0)
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_arg_a1	<->  call void @callee(double* %escape_alloca_a0)
+; FUNCAA:     ModRef:  Ptr: double** %indirect_a0	<->  call void @callee(double* %escape_alloca_a0)
+; FUNCAA:     ModRef:  Ptr: double** %indirect_a1	<->  call void @callee(double* %escape_alloca_a0)
+; FUNCAA:     ModRef:  Ptr: double* %loaded_a0	<->  call void @callee(double* %escape_alloca_a0)
+; FUNCAA:     ModRef:  Ptr: double* %loaded_a1	<->  call void @callee(double* %escape_alloca_a0)
+; FUNCAA:     ModRef:  Ptr: double* %escape_alloca_a0	<->  call void @callee(double* %escape_alloca_a0)
+; FUNCAA:     ModRef:  Ptr: double* %escape_alloca_a1	<->  call void @callee(double* %escape_alloca_a0)
+; FUNCAA:   NoModRef:  Ptr: double* %noescape_alloca_a0	<->  call void @callee(double* %escape_alloca_a0)
+; FUNCAA:   NoModRef:  Ptr: double* %noescape_alloca_a1	<->  call void @callee(double* %escape_alloca_a0)
+; FUNCAA:     ModRef:  Ptr: double* %normal_ret_a0	<->  call void @callee(double* %escape_alloca_a0)
+; FUNCAA:     ModRef:  Ptr: double* %normal_ret_a1	<->  call void @callee(double* %escape_alloca_a0)
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_ret_a0	<->  call void @callee(double* %escape_alloca_a0)
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_ret_a1	<->  call void @callee(double* %escape_alloca_a0)
+; FUNCAA:     ModRef:  Ptr: double* %arg_a0	<->  call void @callee(double* %escape_alloca_a1)
+; FUNCAA:     ModRef:  Ptr: double* %arg_a1	<->  call void @callee(double* %escape_alloca_a1)
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_arg_a0	<->  call void @callee(double* %escape_alloca_a1)
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_arg_a1	<->  call void @callee(double* %escape_alloca_a1)
+; FUNCAA:     ModRef:  Ptr: double** %indirect_a0	<->  call void @callee(double* %escape_alloca_a1)
+; FUNCAA:     ModRef:  Ptr: double** %indirect_a1	<->  call void @callee(double* %escape_alloca_a1)
+; FUNCAA:     ModRef:  Ptr: double* %loaded_a0	<->  call void @callee(double* %escape_alloca_a1)
+; FUNCAA:     ModRef:  Ptr: double* %loaded_a1	<->  call void @callee(double* %escape_alloca_a1)
+; FUNCAA:     ModRef:  Ptr: double* %escape_alloca_a0	<->  call void @callee(double* %escape_alloca_a1)
+; FUNCAA:     ModRef:  Ptr: double* %escape_alloca_a1	<->  call void @callee(double* %escape_alloca_a1)
+; FUNCAA:   NoModRef:  Ptr: double* %noescape_alloca_a0	<->  call void @callee(double* %escape_alloca_a1)
+; FUNCAA:   NoModRef:  Ptr: double* %noescape_alloca_a1	<->  call void @callee(double* %escape_alloca_a1)
+; FUNCAA:     ModRef:  Ptr: double* %normal_ret_a0	<->  call void @callee(double* %escape_alloca_a1)
+; FUNCAA:     ModRef:  Ptr: double* %normal_ret_a1	<->  call void @callee(double* %escape_alloca_a1)
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_ret_a0	<->  call void @callee(double* %escape_alloca_a1)
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_ret_a1	<->  call void @callee(double* %escape_alloca_a1)
+; FUNCAA:     ModRef:  Ptr: double* %arg_a0	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; FUNCAA:     ModRef:  Ptr: double* %arg_a1	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_arg_a0	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_arg_a1	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; FUNCAA:     ModRef:  Ptr: double** %indirect_a0	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; FUNCAA:     ModRef:  Ptr: double** %indirect_a1	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; FUNCAA:     ModRef:  Ptr: double* %loaded_a0	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; FUNCAA:     ModRef:  Ptr: double* %loaded_a1	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; FUNCAA:     ModRef:  Ptr: double* %escape_alloca_a0	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; FUNCAA:     ModRef:  Ptr: double* %escape_alloca_a1	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; FUNCAA:     ModRef:  Ptr: double* %noescape_alloca_a0	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; FUNCAA:   NoModRef:  Ptr: double* %noescape_alloca_a1	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; FUNCAA:     ModRef:  Ptr: double* %normal_ret_a0	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; FUNCAA:     ModRef:  Ptr: double* %normal_ret_a1	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_ret_a0	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_ret_a1	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; FUNCAA:     ModRef:  Ptr: double* %arg_a0	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; FUNCAA:     ModRef:  Ptr: double* %arg_a1	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_arg_a0	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_arg_a1	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; FUNCAA:     ModRef:  Ptr: double** %indirect_a0	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; FUNCAA:     ModRef:  Ptr: double** %indirect_a1	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; FUNCAA:     ModRef:  Ptr: double* %loaded_a0	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; FUNCAA:     ModRef:  Ptr: double* %loaded_a1	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; FUNCAA:     ModRef:  Ptr: double* %escape_alloca_a0	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; FUNCAA:     ModRef:  Ptr: double* %escape_alloca_a1	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; FUNCAA:   NoModRef:  Ptr: double* %noescape_alloca_a0	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; FUNCAA:     ModRef:  Ptr: double* %noescape_alloca_a1	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; FUNCAA:     ModRef:  Ptr: double* %normal_ret_a0	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; FUNCAA:     ModRef:  Ptr: double* %normal_ret_a1	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_ret_a0	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_ret_a1	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; FUNCAA: Function: caller_b: 16 pointers, 8 call sites
+; FUNCAA:   MayAlias:	double* %arg_b0, double* %arg_b1
+; FUNCAA:   NoAlias:	double* %arg_b0, double* %noalias_arg_b0
+; FUNCAA:   NoAlias:	double* %arg_b1, double* %noalias_arg_b0
+; FUNCAA:   NoAlias:	double* %arg_b0, double* %noalias_arg_b1
+; FUNCAA:   NoAlias:	double* %arg_b1, double* %noalias_arg_b1
+; FUNCAA:   NoAlias:	double* %noalias_arg_b0, double* %noalias_arg_b1
+; FUNCAA:   MayAlias:	double* %arg_b0, double** %indirect_b0
+; FUNCAA:   MayAlias:	double* %arg_b1, double** %indirect_b0
+; FUNCAA:   NoAlias:	double* %noalias_arg_b0, double** %indirect_b0
+; FUNCAA:   NoAlias:	double* %noalias_arg_b1, double** %indirect_b0
+; FUNCAA:   MayAlias:	double* %arg_b0, double** %indirect_b1
+; FUNCAA:   MayAlias:	double* %arg_b1, double** %indirect_b1
+; FUNCAA:   NoAlias:	double* %noalias_arg_b0, double** %indirect_b1
+; FUNCAA:   NoAlias:	double* %noalias_arg_b1, double** %indirect_b1
+; FUNCAA:   MayAlias:	double** %indirect_b0, double** %indirect_b1
+; FUNCAA:   MayAlias:	double* %arg_b0, double* %loaded_b0
+; FUNCAA:   MayAlias:	double* %arg_b1, double* %loaded_b0
+; FUNCAA:   NoAlias:	double* %loaded_b0, double* %noalias_arg_b0
+; FUNCAA:   NoAlias:	double* %loaded_b0, double* %noalias_arg_b1
+; FUNCAA:   MayAlias:	double* %loaded_b0, double** %indirect_b0
+; FUNCAA:   MayAlias:	double* %loaded_b0, double** %indirect_b1
+; FUNCAA:   MayAlias:	double* %arg_b0, double* %loaded_b1
+; FUNCAA:   MayAlias:	double* %arg_b1, double* %loaded_b1
+; FUNCAA:   NoAlias:	double* %loaded_b1, double* %noalias_arg_b0
+; FUNCAA:   NoAlias:	double* %loaded_b1, double* %noalias_arg_b1
+; FUNCAA:   MayAlias:	double* %loaded_b1, double** %indirect_b0
+; FUNCAA:   MayAlias:	double* %loaded_b1, double** %indirect_b1
+; FUNCAA:   MayAlias:	double* %loaded_b0, double* %loaded_b1
+; FUNCAA:   NoAlias:	double* %arg_b0, double* %escape_alloca_b0
+; FUNCAA:   NoAlias:	double* %arg_b1, double* %escape_alloca_b0
+; FUNCAA:   NoAlias:	double* %escape_alloca_b0, double* %noalias_arg_b0
+; FUNCAA:   NoAlias:	double* %escape_alloca_b0, double* %noalias_arg_b1
+; FUNCAA:   NoAlias:	double* %escape_alloca_b0, double** %indirect_b0
+; FUNCAA:   NoAlias:	double* %escape_alloca_b0, double** %indirect_b1
+; FUNCAA:   MayAlias:	double* %escape_alloca_b0, double* %loaded_b0
+; FUNCAA:   MayAlias:	double* %escape_alloca_b0, double* %loaded_b1
+; FUNCAA:   NoAlias:	double* %arg_b0, double* %escape_alloca_b1
+; FUNCAA:   NoAlias:	double* %arg_b1, double* %escape_alloca_b1
+; FUNCAA:   NoAlias:	double* %escape_alloca_b1, double* %noalias_arg_b0
+; FUNCAA:   NoAlias:	double* %escape_alloca_b1, double* %noalias_arg_b1
+; FUNCAA:   NoAlias:	double* %escape_alloca_b1, double** %indirect_b0
+; FUNCAA:   NoAlias:	double* %escape_alloca_b1, double** %indirect_b1
+; FUNCAA:   MayAlias:	double* %escape_alloca_b1, double* %loaded_b0
+; FUNCAA:   MayAlias:	double* %escape_alloca_b1, double* %loaded_b1
+; FUNCAA:   NoAlias:	double* %escape_alloca_b0, double* %escape_alloca_b1
+; FUNCAA:   NoAlias:	double* %arg_b0, double* %noescape_alloca_b0
+; FUNCAA:   NoAlias:	double* %arg_b1, double* %noescape_alloca_b0
+; FUNCAA:   NoAlias:	double* %noalias_arg_b0, double* %noescape_alloca_b0
+; FUNCAA:   NoAlias:	double* %noalias_arg_b1, double* %noescape_alloca_b0
+; FUNCAA:   NoAlias:	double* %noescape_alloca_b0, double** %indirect_b0
+; FUNCAA:   NoAlias:	double* %noescape_alloca_b0, double** %indirect_b1
+; FUNCAA:   NoAlias:	double* %loaded_b0, double* %noescape_alloca_b0
+; FUNCAA:   NoAlias:	double* %loaded_b1, double* %noescape_alloca_b0
+; FUNCAA:   NoAlias:	double* %escape_alloca_b0, double* %noescape_alloca_b0
+; FUNCAA:   NoAlias:	double* %escape_alloca_b1, double* %noescape_alloca_b0
+; FUNCAA:   NoAlias:	double* %arg_b0, double* %noescape_alloca_b1
+; FUNCAA:   NoAlias:	double* %arg_b1, double* %noescape_alloca_b1
+; FUNCAA:   NoAlias:	double* %noalias_arg_b0, double* %noescape_alloca_b1
+; FUNCAA:   NoAlias:	double* %noalias_arg_b1, double* %noescape_alloca_b1
+; FUNCAA:   NoAlias:	double* %noescape_alloca_b1, double** %indirect_b0
+; FUNCAA:   NoAlias:	double* %noescape_alloca_b1, double** %indirect_b1
+; FUNCAA:   NoAlias:	double* %loaded_b0, double* %noescape_alloca_b1
+; FUNCAA:   NoAlias:	double* %loaded_b1, double* %noescape_alloca_b1
+; FUNCAA:   NoAlias:	double* %escape_alloca_b0, double* %noescape_alloca_b1
+; FUNCAA:   NoAlias:	double* %escape_alloca_b1, double* %noescape_alloca_b1
+; FUNCAA:   NoAlias:	double* %noescape_alloca_b0, double* %noescape_alloca_b1
+; FUNCAA:   MayAlias:	double* %arg_b0, double* %normal_ret_b0
+; FUNCAA:   MayAlias:	double* %arg_b1, double* %normal_ret_b0
+; FUNCAA:   NoAlias:	double* %noalias_arg_b0, double* %normal_ret_b0
+; FUNCAA:   NoAlias:	double* %noalias_arg_b1, double* %normal_ret_b0
+; FUNCAA:   MayAlias:	double* %normal_ret_b0, double** %indirect_b0
+; FUNCAA:   MayAlias:	double* %normal_ret_b0, double** %indirect_b1
+; FUNCAA:   MayAlias:	double* %loaded_b0, double* %normal_ret_b0
+; FUNCAA:   MayAlias:	double* %loaded_b1, double* %normal_ret_b0
+; FUNCAA:   MayAlias:	double* %escape_alloca_b0, double* %normal_ret_b0
+; FUNCAA:   MayAlias:	double* %escape_alloca_b1, double* %normal_ret_b0
+; FUNCAA:   NoAlias:	double* %noescape_alloca_b0, double* %normal_ret_b0
+; FUNCAA:   NoAlias:	double* %noescape_alloca_b1, double* %normal_ret_b0
+; FUNCAA:   MayAlias:	double* %arg_b0, double* %normal_ret_b1
+; FUNCAA:   MayAlias:	double* %arg_b1, double* %normal_ret_b1
+; FUNCAA:   NoAlias:	double* %noalias_arg_b0, double* %normal_ret_b1
+; FUNCAA:   NoAlias:	double* %noalias_arg_b1, double* %normal_ret_b1
+; FUNCAA:   MayAlias:	double* %normal_ret_b1, double** %indirect_b0
+; FUNCAA:   MayAlias:	double* %normal_ret_b1, double** %indirect_b1
+; FUNCAA:   MayAlias:	double* %loaded_b0, double* %normal_ret_b1
+; FUNCAA:   MayAlias:	double* %loaded_b1, double* %normal_ret_b1
+; FUNCAA:   MayAlias:	double* %escape_alloca_b0, double* %normal_ret_b1
+; FUNCAA:   MayAlias:	double* %escape_alloca_b1, double* %normal_ret_b1
+; FUNCAA:   NoAlias:	double* %noescape_alloca_b0, double* %normal_ret_b1
+; FUNCAA:   NoAlias:	double* %noescape_alloca_b1, double* %normal_ret_b1
+; FUNCAA:   MayAlias:	double* %normal_ret_b0, double* %normal_ret_b1
+; FUNCAA:   NoAlias:	double* %arg_b0, double* %noalias_ret_b0
+; FUNCAA:   NoAlias:	double* %arg_b1, double* %noalias_ret_b0
+; FUNCAA:   NoAlias:	double* %noalias_arg_b0, double* %noalias_ret_b0
+; FUNCAA:   NoAlias:	double* %noalias_arg_b1, double* %noalias_ret_b0
+; FUNCAA:   NoAlias:	double* %noalias_ret_b0, double** %indirect_b0
+; FUNCAA:   NoAlias:	double* %noalias_ret_b0, double** %indirect_b1
+; FUNCAA:   NoAlias:	double* %loaded_b0, double* %noalias_ret_b0
+; FUNCAA:   NoAlias:	double* %loaded_b1, double* %noalias_ret_b0
+; FUNCAA:   NoAlias:	double* %escape_alloca_b0, double* %noalias_ret_b0
+; FUNCAA:   NoAlias:	double* %escape_alloca_b1, double* %noalias_ret_b0
+; FUNCAA:   NoAlias:	double* %noalias_ret_b0, double* %noescape_alloca_b0
+; FUNCAA:   NoAlias:	double* %noalias_ret_b0, double* %noescape_alloca_b1
+; FUNCAA:   NoAlias:	double* %noalias_ret_b0, double* %normal_ret_b0
+; FUNCAA:   NoAlias:	double* %noalias_ret_b0, double* %normal_ret_b1
+; FUNCAA:   NoAlias:	double* %arg_b0, double* %noalias_ret_b1
+; FUNCAA:   NoAlias:	double* %arg_b1, double* %noalias_ret_b1
+; FUNCAA:   NoAlias:	double* %noalias_arg_b0, double* %noalias_ret_b1
+; FUNCAA:   NoAlias:	double* %noalias_arg_b1, double* %noalias_ret_b1
+; FUNCAA:   NoAlias:	double* %noalias_ret_b1, double** %indirect_b0
+; FUNCAA:   NoAlias:	double* %noalias_ret_b1, double** %indirect_b1
+; FUNCAA:   NoAlias:	double* %loaded_b0, double* %noalias_ret_b1
+; FUNCAA:   NoAlias:	double* %loaded_b1, double* %noalias_ret_b1
+; FUNCAA:   NoAlias:	double* %escape_alloca_b0, double* %noalias_ret_b1
+; FUNCAA:   NoAlias:	double* %escape_alloca_b1, double* %noalias_ret_b1
+; FUNCAA:   NoAlias:	double* %noalias_ret_b1, double* %noescape_alloca_b0
+; FUNCAA:   NoAlias:	double* %noalias_ret_b1, double* %noescape_alloca_b1
+; FUNCAA:   NoAlias:	double* %noalias_ret_b1, double* %normal_ret_b0
+; FUNCAA:   NoAlias:	double* %noalias_ret_b1, double* %normal_ret_b1
+; FUNCAA:   NoAlias:	double* %noalias_ret_b0, double* %noalias_ret_b1
+; FUNCAA:     ModRef:  Ptr: double* %arg_b0	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %arg_b1	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_arg_b0	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_arg_b1	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double** %indirect_b0	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double** %indirect_b1	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %loaded_b0	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %loaded_b1	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %escape_alloca_b0	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %escape_alloca_b1	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noescape_alloca_b0	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noescape_alloca_b1	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %normal_ret_b0	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %normal_ret_b1	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_ret_b0	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_ret_b1	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %arg_b0	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %arg_b1	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_arg_b0	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_arg_b1	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double** %indirect_b0	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double** %indirect_b1	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %loaded_b0	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %loaded_b1	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %escape_alloca_b0	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %escape_alloca_b1	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noescape_alloca_b0	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noescape_alloca_b1	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %normal_ret_b0	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %normal_ret_b1	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_ret_b0	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_ret_b1	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %arg_b0	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %arg_b1	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_arg_b0	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_arg_b1	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double** %indirect_b0	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double** %indirect_b1	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %loaded_b0	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %loaded_b1	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %escape_alloca_b0	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %escape_alloca_b1	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noescape_alloca_b0	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noescape_alloca_b1	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %normal_ret_b0	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %normal_ret_b1	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %noalias_ret_b0	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_ret_b1	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %arg_b0	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %arg_b1	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_arg_b0	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_arg_b1	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double** %indirect_b0	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double** %indirect_b1	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %loaded_b0	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %loaded_b1	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %escape_alloca_b0	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %escape_alloca_b1	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noescape_alloca_b0	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noescape_alloca_b1	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %normal_ret_b0	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %normal_ret_b1	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_ret_b0	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %noalias_ret_b1	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; FUNCAA:     ModRef:  Ptr: double* %arg_b0	<->  call void @callee(double* %escape_alloca_b0)
+; FUNCAA:     ModRef:  Ptr: double* %arg_b1	<->  call void @callee(double* %escape_alloca_b0)
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_arg_b0	<->  call void @callee(double* %escape_alloca_b0)
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_arg_b1	<->  call void @callee(double* %escape_alloca_b0)
+; FUNCAA:     ModRef:  Ptr: double** %indirect_b0	<->  call void @callee(double* %escape_alloca_b0)
+; FUNCAA:     ModRef:  Ptr: double** %indirect_b1	<->  call void @callee(double* %escape_alloca_b0)
+; FUNCAA:     ModRef:  Ptr: double* %loaded_b0	<->  call void @callee(double* %escape_alloca_b0)
+; FUNCAA:     ModRef:  Ptr: double* %loaded_b1	<->  call void @callee(double* %escape_alloca_b0)
+; FUNCAA:     ModRef:  Ptr: double* %escape_alloca_b0	<->  call void @callee(double* %escape_alloca_b0)
+; FUNCAA:     ModRef:  Ptr: double* %escape_alloca_b1	<->  call void @callee(double* %escape_alloca_b0)
+; FUNCAA:   NoModRef:  Ptr: double* %noescape_alloca_b0	<->  call void @callee(double* %escape_alloca_b0)
+; FUNCAA:   NoModRef:  Ptr: double* %noescape_alloca_b1	<->  call void @callee(double* %escape_alloca_b0)
+; FUNCAA:     ModRef:  Ptr: double* %normal_ret_b0	<->  call void @callee(double* %escape_alloca_b0)
+; FUNCAA:     ModRef:  Ptr: double* %normal_ret_b1	<->  call void @callee(double* %escape_alloca_b0)
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_ret_b0	<->  call void @callee(double* %escape_alloca_b0)
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_ret_b1	<->  call void @callee(double* %escape_alloca_b0)
+; FUNCAA:     ModRef:  Ptr: double* %arg_b0	<->  call void @callee(double* %escape_alloca_b1)
+; FUNCAA:     ModRef:  Ptr: double* %arg_b1	<->  call void @callee(double* %escape_alloca_b1)
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_arg_b0	<->  call void @callee(double* %escape_alloca_b1)
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_arg_b1	<->  call void @callee(double* %escape_alloca_b1)
+; FUNCAA:     ModRef:  Ptr: double** %indirect_b0	<->  call void @callee(double* %escape_alloca_b1)
+; FUNCAA:     ModRef:  Ptr: double** %indirect_b1	<->  call void @callee(double* %escape_alloca_b1)
+; FUNCAA:     ModRef:  Ptr: double* %loaded_b0	<->  call void @callee(double* %escape_alloca_b1)
+; FUNCAA:     ModRef:  Ptr: double* %loaded_b1	<->  call void @callee(double* %escape_alloca_b1)
+; FUNCAA:     ModRef:  Ptr: double* %escape_alloca_b0	<->  call void @callee(double* %escape_alloca_b1)
+; FUNCAA:     ModRef:  Ptr: double* %escape_alloca_b1	<->  call void @callee(double* %escape_alloca_b1)
+; FUNCAA:   NoModRef:  Ptr: double* %noescape_alloca_b0	<->  call void @callee(double* %escape_alloca_b1)
+; FUNCAA:   NoModRef:  Ptr: double* %noescape_alloca_b1	<->  call void @callee(double* %escape_alloca_b1)
+; FUNCAA:     ModRef:  Ptr: double* %normal_ret_b0	<->  call void @callee(double* %escape_alloca_b1)
+; FUNCAA:     ModRef:  Ptr: double* %normal_ret_b1	<->  call void @callee(double* %escape_alloca_b1)
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_ret_b0	<->  call void @callee(double* %escape_alloca_b1)
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_ret_b1	<->  call void @callee(double* %escape_alloca_b1)
+; FUNCAA:     ModRef:  Ptr: double* %arg_b0	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; FUNCAA:     ModRef:  Ptr: double* %arg_b1	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_arg_b0	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_arg_b1	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; FUNCAA:     ModRef:  Ptr: double** %indirect_b0	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; FUNCAA:     ModRef:  Ptr: double** %indirect_b1	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; FUNCAA:     ModRef:  Ptr: double* %loaded_b0	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; FUNCAA:     ModRef:  Ptr: double* %loaded_b1	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; FUNCAA:     ModRef:  Ptr: double* %escape_alloca_b0	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; FUNCAA:     ModRef:  Ptr: double* %escape_alloca_b1	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; FUNCAA:     ModRef:  Ptr: double* %noescape_alloca_b0	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; FUNCAA:   NoModRef:  Ptr: double* %noescape_alloca_b1	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; FUNCAA:     ModRef:  Ptr: double* %normal_ret_b0	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; FUNCAA:     ModRef:  Ptr: double* %normal_ret_b1	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_ret_b0	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_ret_b1	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; FUNCAA:     ModRef:  Ptr: double* %arg_b0	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; FUNCAA:     ModRef:  Ptr: double* %arg_b1	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_arg_b0	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_arg_b1	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; FUNCAA:     ModRef:  Ptr: double** %indirect_b0	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; FUNCAA:     ModRef:  Ptr: double** %indirect_b1	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; FUNCAA:     ModRef:  Ptr: double* %loaded_b0	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; FUNCAA:     ModRef:  Ptr: double* %loaded_b1	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; FUNCAA:     ModRef:  Ptr: double* %escape_alloca_b0	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; FUNCAA:     ModRef:  Ptr: double* %escape_alloca_b1	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; FUNCAA:   NoModRef:  Ptr: double* %noescape_alloca_b0	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; FUNCAA:     ModRef:  Ptr: double* %noescape_alloca_b1	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; FUNCAA:     ModRef:  Ptr: double* %normal_ret_b0	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; FUNCAA:     ModRef:  Ptr: double* %normal_ret_b1	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_ret_b0	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; FUNCAA:   NoModRef:  Ptr: double* %noalias_ret_b1	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; FUNCAA: ===== Alias Analysis Evaluator Report =====
+; FUNCAA:   240 Total Alias Queries Performed
+; FUNCAA:   168 no alias responses (70.0%)
+; FUNCAA:   72 may alias responses (30.0%)
+; FUNCAA:   0 must alias responses (0.0%)
+; FUNCAA:   Alias Analysis Evaluator Pointer Alias Summary: 70%/30%/0%
+; FUNCAA:   256 Total ModRef Queries Performed
+; FUNCAA:   88 no mod/ref responses (34.3%)
+; FUNCAA:   0 mod responses (0.0%)
+; FUNCAA:   0 ref responses (0.0%)
+; FUNCAA:   168 mod & ref responses (65.6%)
+; FUNCAA:   Alias Analysis Evaluator Mod/Ref Summary: 34%/0%/0%/65%
+
+; IPAA: Module: 34 pointers, 16 call sites
+; IPAA:   MayAlias:	double* %callee_arg, double* %nocap_callee_arg
+; IPAA:   MayAlias:	double* %arg_a0, double* %callee_arg
+; IPAA:   MayAlias:	double* %arg_a0, double* %nocap_callee_arg
+; IPAA:   MayAlias:	double* %arg_a1, double* %callee_arg
+; IPAA:   MayAlias:	double* %arg_a1, double* %nocap_callee_arg
+; IPAA:   MayAlias:	double* %arg_a0, double* %arg_a1
+; IPAA:   MayAlias:	double* %callee_arg, double* %noalias_arg_a0
+; IPAA:   MayAlias:	double* %noalias_arg_a0, double* %nocap_callee_arg
+; IPAA:   NoAlias:	double* %arg_a0, double* %noalias_arg_a0
+; IPAA:   NoAlias:	double* %arg_a1, double* %noalias_arg_a0
+; IPAA:   MayAlias:	double* %callee_arg, double* %noalias_arg_a1
+; IPAA:   MayAlias:	double* %noalias_arg_a1, double* %nocap_callee_arg
+; IPAA:   NoAlias:	double* %arg_a0, double* %noalias_arg_a1
+; IPAA:   NoAlias:	double* %arg_a1, double* %noalias_arg_a1
+; IPAA:   NoAlias:	double* %noalias_arg_a0, double* %noalias_arg_a1
+; IPAA:   MayAlias:	double* %callee_arg, double** %indirect_a0
+; IPAA:   MayAlias:	double* %nocap_callee_arg, double** %indirect_a0
+; IPAA:   MayAlias:	double* %arg_a0, double** %indirect_a0
+; IPAA:   MayAlias:	double* %arg_a1, double** %indirect_a0
+; IPAA:   NoAlias:	double* %noalias_arg_a0, double** %indirect_a0
+; IPAA:   NoAlias:	double* %noalias_arg_a1, double** %indirect_a0
+; IPAA:   MayAlias:	double* %callee_arg, double** %indirect_a1
+; IPAA:   MayAlias:	double* %nocap_callee_arg, double** %indirect_a1
+; IPAA:   MayAlias:	double* %arg_a0, double** %indirect_a1
+; IPAA:   MayAlias:	double* %arg_a1, double** %indirect_a1
+; IPAA:   NoAlias:	double* %noalias_arg_a0, double** %indirect_a1
+; IPAA:   NoAlias:	double* %noalias_arg_a1, double** %indirect_a1
+; IPAA:   MayAlias:	double** %indirect_a0, double** %indirect_a1
+; IPAA:   MayAlias:	double* %callee_arg, double* %loaded_a0
+; IPAA:   MayAlias:	double* %loaded_a0, double* %nocap_callee_arg
+; IPAA:   MayAlias:	double* %arg_a0, double* %loaded_a0
+; IPAA:   MayAlias:	double* %arg_a1, double* %loaded_a0
+; IPAA:   NoAlias:	double* %loaded_a0, double* %noalias_arg_a0
+; IPAA:   NoAlias:	double* %loaded_a0, double* %noalias_arg_a1
+; IPAA:   MayAlias:	double* %loaded_a0, double** %indirect_a0
+; IPAA:   MayAlias:	double* %loaded_a0, double** %indirect_a1
+; IPAA:   MayAlias:	double* %callee_arg, double* %loaded_a1
+; IPAA:   MayAlias:	double* %loaded_a1, double* %nocap_callee_arg
+; IPAA:   MayAlias:	double* %arg_a0, double* %loaded_a1
+; IPAA:   MayAlias:	double* %arg_a1, double* %loaded_a1
+; IPAA:   NoAlias:	double* %loaded_a1, double* %noalias_arg_a0
+; IPAA:   NoAlias:	double* %loaded_a1, double* %noalias_arg_a1
+; IPAA:   MayAlias:	double* %loaded_a1, double** %indirect_a0
+; IPAA:   MayAlias:	double* %loaded_a1, double** %indirect_a1
+; IPAA:   MayAlias:	double* %loaded_a0, double* %loaded_a1
+; IPAA:   MayAlias:	double* %callee_arg, double* %escape_alloca_a0
+; IPAA:   MayAlias:	double* %escape_alloca_a0, double* %nocap_callee_arg
+; IPAA:   NoAlias:	double* %arg_a0, double* %escape_alloca_a0
+; IPAA:   NoAlias:	double* %arg_a1, double* %escape_alloca_a0
+; IPAA:   NoAlias:	double* %escape_alloca_a0, double* %noalias_arg_a0
+; IPAA:   NoAlias:	double* %escape_alloca_a0, double* %noalias_arg_a1
+; IPAA:   NoAlias:	double* %escape_alloca_a0, double** %indirect_a0
+; IPAA:   NoAlias:	double* %escape_alloca_a0, double** %indirect_a1
+; IPAA:   MayAlias:	double* %escape_alloca_a0, double* %loaded_a0
+; IPAA:   MayAlias:	double* %escape_alloca_a0, double* %loaded_a1
+; IPAA:   MayAlias:	double* %callee_arg, double* %escape_alloca_a1
+; IPAA:   MayAlias:	double* %escape_alloca_a1, double* %nocap_callee_arg
+; IPAA:   NoAlias:	double* %arg_a0, double* %escape_alloca_a1
+; IPAA:   NoAlias:	double* %arg_a1, double* %escape_alloca_a1
+; IPAA:   NoAlias:	double* %escape_alloca_a1, double* %noalias_arg_a0
+; IPAA:   NoAlias:	double* %escape_alloca_a1, double* %noalias_arg_a1
+; IPAA:   NoAlias:	double* %escape_alloca_a1, double** %indirect_a0
+; IPAA:   NoAlias:	double* %escape_alloca_a1, double** %indirect_a1
+; IPAA:   MayAlias:	double* %escape_alloca_a1, double* %loaded_a0
+; IPAA:   MayAlias:	double* %escape_alloca_a1, double* %loaded_a1
+; IPAA:   NoAlias:	double* %escape_alloca_a0, double* %escape_alloca_a1
+; IPAA:   MayAlias:	double* %callee_arg, double* %noescape_alloca_a0
+; IPAA:   MayAlias:	double* %nocap_callee_arg, double* %noescape_alloca_a0
+; IPAA:   NoAlias:	double* %arg_a0, double* %noescape_alloca_a0
+; IPAA:   NoAlias:	double* %arg_a1, double* %noescape_alloca_a0
+; IPAA:   NoAlias:	double* %noalias_arg_a0, double* %noescape_alloca_a0
+; IPAA:   NoAlias:	double* %noalias_arg_a1, double* %noescape_alloca_a0
+; IPAA:   NoAlias:	double* %noescape_alloca_a0, double** %indirect_a0
+; IPAA:   NoAlias:	double* %noescape_alloca_a0, double** %indirect_a1
+; IPAA:   NoAlias:	double* %loaded_a0, double* %noescape_alloca_a0
+; IPAA:   NoAlias:	double* %loaded_a1, double* %noescape_alloca_a0
+; IPAA:   NoAlias:	double* %escape_alloca_a0, double* %noescape_alloca_a0
+; IPAA:   NoAlias:	double* %escape_alloca_a1, double* %noescape_alloca_a0
+; IPAA:   MayAlias:	double* %callee_arg, double* %noescape_alloca_a1
+; IPAA:   MayAlias:	double* %nocap_callee_arg, double* %noescape_alloca_a1
+; IPAA:   NoAlias:	double* %arg_a0, double* %noescape_alloca_a1
+; IPAA:   NoAlias:	double* %arg_a1, double* %noescape_alloca_a1
+; IPAA:   NoAlias:	double* %noalias_arg_a0, double* %noescape_alloca_a1
+; IPAA:   NoAlias:	double* %noalias_arg_a1, double* %noescape_alloca_a1
+; IPAA:   NoAlias:	double* %noescape_alloca_a1, double** %indirect_a0
+; IPAA:   NoAlias:	double* %noescape_alloca_a1, double** %indirect_a1
+; IPAA:   NoAlias:	double* %loaded_a0, double* %noescape_alloca_a1
+; IPAA:   NoAlias:	double* %loaded_a1, double* %noescape_alloca_a1
+; IPAA:   NoAlias:	double* %escape_alloca_a0, double* %noescape_alloca_a1
+; IPAA:   NoAlias:	double* %escape_alloca_a1, double* %noescape_alloca_a1
+; IPAA:   NoAlias:	double* %noescape_alloca_a0, double* %noescape_alloca_a1
+; IPAA:   MayAlias:	double* %callee_arg, double* %normal_ret_a0
+; IPAA:   MayAlias:	double* %nocap_callee_arg, double* %normal_ret_a0
+; IPAA:   MayAlias:	double* %arg_a0, double* %normal_ret_a0
+; IPAA:   MayAlias:	double* %arg_a1, double* %normal_ret_a0
+; IPAA:   NoAlias:	double* %noalias_arg_a0, double* %normal_ret_a0
+; IPAA:   NoAlias:	double* %noalias_arg_a1, double* %normal_ret_a0
+; IPAA:   MayAlias:	double* %normal_ret_a0, double** %indirect_a0
+; IPAA:   MayAlias:	double* %normal_ret_a0, double** %indirect_a1
+; IPAA:   MayAlias:	double* %loaded_a0, double* %normal_ret_a0
+; IPAA:   MayAlias:	double* %loaded_a1, double* %normal_ret_a0
+; IPAA:   MayAlias:	double* %escape_alloca_a0, double* %normal_ret_a0
+; IPAA:   MayAlias:	double* %escape_alloca_a1, double* %normal_ret_a0
+; IPAA:   NoAlias:	double* %noescape_alloca_a0, double* %normal_ret_a0
+; IPAA:   NoAlias:	double* %noescape_alloca_a1, double* %normal_ret_a0
+; IPAA:   MayAlias:	double* %callee_arg, double* %normal_ret_a1
+; IPAA:   MayAlias:	double* %nocap_callee_arg, double* %normal_ret_a1
+; IPAA:   MayAlias:	double* %arg_a0, double* %normal_ret_a1
+; IPAA:   MayAlias:	double* %arg_a1, double* %normal_ret_a1
+; IPAA:   NoAlias:	double* %noalias_arg_a0, double* %normal_ret_a1
+; IPAA:   NoAlias:	double* %noalias_arg_a1, double* %normal_ret_a1
+; IPAA:   MayAlias:	double* %normal_ret_a1, double** %indirect_a0
+; IPAA:   MayAlias:	double* %normal_ret_a1, double** %indirect_a1
+; IPAA:   MayAlias:	double* %loaded_a0, double* %normal_ret_a1
+; IPAA:   MayAlias:	double* %loaded_a1, double* %normal_ret_a1
+; IPAA:   MayAlias:	double* %escape_alloca_a0, double* %normal_ret_a1
+; IPAA:   MayAlias:	double* %escape_alloca_a1, double* %normal_ret_a1
+; IPAA:   NoAlias:	double* %noescape_alloca_a0, double* %normal_ret_a1
+; IPAA:   NoAlias:	double* %noescape_alloca_a1, double* %normal_ret_a1
+; IPAA:   MayAlias:	double* %normal_ret_a0, double* %normal_ret_a1
+; IPAA:   MayAlias:	double* %callee_arg, double* %noalias_ret_a0
+; IPAA:   MayAlias:	double* %noalias_ret_a0, double* %nocap_callee_arg
+; IPAA:   NoAlias:	double* %arg_a0, double* %noalias_ret_a0
+; IPAA:   NoAlias:	double* %arg_a1, double* %noalias_ret_a0
+; IPAA:   NoAlias:	double* %noalias_arg_a0, double* %noalias_ret_a0
+; IPAA:   NoAlias:	double* %noalias_arg_a1, double* %noalias_ret_a0
+; IPAA:   NoAlias:	double* %noalias_ret_a0, double** %indirect_a0
+; IPAA:   NoAlias:	double* %noalias_ret_a0, double** %indirect_a1
+; IPAA:   NoAlias:	double* %loaded_a0, double* %noalias_ret_a0
+; IPAA:   NoAlias:	double* %loaded_a1, double* %noalias_ret_a0
+; IPAA:   NoAlias:	double* %escape_alloca_a0, double* %noalias_ret_a0
+; IPAA:   NoAlias:	double* %escape_alloca_a1, double* %noalias_ret_a0
+; IPAA:   NoAlias:	double* %noalias_ret_a0, double* %noescape_alloca_a0
+; IPAA:   NoAlias:	double* %noalias_ret_a0, double* %noescape_alloca_a1
+; IPAA:   NoAlias:	double* %noalias_ret_a0, double* %normal_ret_a0
+; IPAA:   NoAlias:	double* %noalias_ret_a0, double* %normal_ret_a1
+; IPAA:   MayAlias:	double* %callee_arg, double* %noalias_ret_a1
+; IPAA:   MayAlias:	double* %noalias_ret_a1, double* %nocap_callee_arg
+; IPAA:   NoAlias:	double* %arg_a0, double* %noalias_ret_a1
+; IPAA:   NoAlias:	double* %arg_a1, double* %noalias_ret_a1
+; IPAA:   NoAlias:	double* %noalias_arg_a0, double* %noalias_ret_a1
+; IPAA:   NoAlias:	double* %noalias_arg_a1, double* %noalias_ret_a1
+; IPAA:   NoAlias:	double* %noalias_ret_a1, double** %indirect_a0
+; IPAA:   NoAlias:	double* %noalias_ret_a1, double** %indirect_a1
+; IPAA:   NoAlias:	double* %loaded_a0, double* %noalias_ret_a1
+; IPAA:   NoAlias:	double* %loaded_a1, double* %noalias_ret_a1
+; IPAA:   NoAlias:	double* %escape_alloca_a0, double* %noalias_ret_a1
+; IPAA:   NoAlias:	double* %escape_alloca_a1, double* %noalias_ret_a1
+; IPAA:   NoAlias:	double* %noalias_ret_a1, double* %noescape_alloca_a0
+; IPAA:   NoAlias:	double* %noalias_ret_a1, double* %noescape_alloca_a1
+; IPAA:   NoAlias:	double* %noalias_ret_a1, double* %normal_ret_a0
+; IPAA:   NoAlias:	double* %noalias_ret_a1, double* %normal_ret_a1
+; IPAA:   NoAlias:	double* %noalias_ret_a0, double* %noalias_ret_a1
+; IPAA:   MayAlias:	double* %arg_b0, double* %callee_arg
+; IPAA:   MayAlias:	double* %arg_b0, double* %nocap_callee_arg
+; IPAA:   MayAlias:	double* %arg_a0, double* %arg_b0
+; IPAA:   MayAlias:	double* %arg_a1, double* %arg_b0
+; IPAA:   MayAlias:	double* %arg_b0, double* %noalias_arg_a0
+; IPAA:   MayAlias:	double* %arg_b0, double* %noalias_arg_a1
+; IPAA:   MayAlias:	double* %arg_b0, double** %indirect_a0
+; IPAA:   MayAlias:	double* %arg_b0, double** %indirect_a1
+; IPAA:   MayAlias:	double* %arg_b0, double* %loaded_a0
+; IPAA:   MayAlias:	double* %arg_b0, double* %loaded_a1
+; IPAA:   MayAlias:	double* %arg_b0, double* %escape_alloca_a0
+; IPAA:   MayAlias:	double* %arg_b0, double* %escape_alloca_a1
+; IPAA:   MayAlias:	double* %arg_b0, double* %noescape_alloca_a0
+; IPAA:   MayAlias:	double* %arg_b0, double* %noescape_alloca_a1
+; IPAA:   MayAlias:	double* %arg_b0, double* %normal_ret_a0
+; IPAA:   MayAlias:	double* %arg_b0, double* %normal_ret_a1
+; IPAA:   MayAlias:	double* %arg_b0, double* %noalias_ret_a0
+; IPAA:   MayAlias:	double* %arg_b0, double* %noalias_ret_a1
+; IPAA:   MayAlias:	double* %arg_b1, double* %callee_arg
+; IPAA:   MayAlias:	double* %arg_b1, double* %nocap_callee_arg
+; IPAA:   MayAlias:	double* %arg_a0, double* %arg_b1
+; IPAA:   MayAlias:	double* %arg_a1, double* %arg_b1
+; IPAA:   MayAlias:	double* %arg_b1, double* %noalias_arg_a0
+; IPAA:   MayAlias:	double* %arg_b1, double* %noalias_arg_a1
+; IPAA:   MayAlias:	double* %arg_b1, double** %indirect_a0
+; IPAA:   MayAlias:	double* %arg_b1, double** %indirect_a1
+; IPAA:   MayAlias:	double* %arg_b1, double* %loaded_a0
+; IPAA:   MayAlias:	double* %arg_b1, double* %loaded_a1
+; IPAA:   MayAlias:	double* %arg_b1, double* %escape_alloca_a0
+; IPAA:   MayAlias:	double* %arg_b1, double* %escape_alloca_a1
+; IPAA:   MayAlias:	double* %arg_b1, double* %noescape_alloca_a0
+; IPAA:   MayAlias:	double* %arg_b1, double* %noescape_alloca_a1
+; IPAA:   MayAlias:	double* %arg_b1, double* %normal_ret_a0
+; IPAA:   MayAlias:	double* %arg_b1, double* %normal_ret_a1
+; IPAA:   MayAlias:	double* %arg_b1, double* %noalias_ret_a0
+; IPAA:   MayAlias:	double* %arg_b1, double* %noalias_ret_a1
+; IPAA:   MayAlias:	double* %arg_b0, double* %arg_b1
+; IPAA:   MayAlias:	double* %callee_arg, double* %noalias_arg_b0
+; IPAA:   MayAlias:	double* %noalias_arg_b0, double* %nocap_callee_arg
+; IPAA:   MayAlias:	double* %arg_a0, double* %noalias_arg_b0
+; IPAA:   MayAlias:	double* %arg_a1, double* %noalias_arg_b0
+; IPAA:   MayAlias:	double* %noalias_arg_a0, double* %noalias_arg_b0
+; IPAA:   MayAlias:	double* %noalias_arg_a1, double* %noalias_arg_b0
+; IPAA:   MayAlias:	double* %noalias_arg_b0, double** %indirect_a0
+; IPAA:   MayAlias:	double* %noalias_arg_b0, double** %indirect_a1
+; IPAA:   MayAlias:	double* %loaded_a0, double* %noalias_arg_b0
+; IPAA:   MayAlias:	double* %loaded_a1, double* %noalias_arg_b0
+; IPAA:   MayAlias:	double* %escape_alloca_a0, double* %noalias_arg_b0
+; IPAA:   MayAlias:	double* %escape_alloca_a1, double* %noalias_arg_b0
+; IPAA:   MayAlias:	double* %noalias_arg_b0, double* %noescape_alloca_a0
+; IPAA:   MayAlias:	double* %noalias_arg_b0, double* %noescape_alloca_a1
+; IPAA:   MayAlias:	double* %noalias_arg_b0, double* %normal_ret_a0
+; IPAA:   MayAlias:	double* %noalias_arg_b0, double* %normal_ret_a1
+; IPAA:   MayAlias:	double* %noalias_arg_b0, double* %noalias_ret_a0
+; IPAA:   MayAlias:	double* %noalias_arg_b0, double* %noalias_ret_a1
+; IPAA:   NoAlias:	double* %arg_b0, double* %noalias_arg_b0
+; IPAA:   NoAlias:	double* %arg_b1, double* %noalias_arg_b0
+; IPAA:   MayAlias:	double* %callee_arg, double* %noalias_arg_b1
+; IPAA:   MayAlias:	double* %noalias_arg_b1, double* %nocap_callee_arg
+; IPAA:   MayAlias:	double* %arg_a0, double* %noalias_arg_b1
+; IPAA:   MayAlias:	double* %arg_a1, double* %noalias_arg_b1
+; IPAA:   MayAlias:	double* %noalias_arg_a0, double* %noalias_arg_b1
+; IPAA:   MayAlias:	double* %noalias_arg_a1, double* %noalias_arg_b1
+; IPAA:   MayAlias:	double* %noalias_arg_b1, double** %indirect_a0
+; IPAA:   MayAlias:	double* %noalias_arg_b1, double** %indirect_a1
+; IPAA:   MayAlias:	double* %loaded_a0, double* %noalias_arg_b1
+; IPAA:   MayAlias:	double* %loaded_a1, double* %noalias_arg_b1
+; IPAA:   MayAlias:	double* %escape_alloca_a0, double* %noalias_arg_b1
+; IPAA:   MayAlias:	double* %escape_alloca_a1, double* %noalias_arg_b1
+; IPAA:   MayAlias:	double* %noalias_arg_b1, double* %noescape_alloca_a0
+; IPAA:   MayAlias:	double* %noalias_arg_b1, double* %noescape_alloca_a1
+; IPAA:   MayAlias:	double* %noalias_arg_b1, double* %normal_ret_a0
+; IPAA:   MayAlias:	double* %noalias_arg_b1, double* %normal_ret_a1
+; IPAA:   MayAlias:	double* %noalias_arg_b1, double* %noalias_ret_a0
+; IPAA:   MayAlias:	double* %noalias_arg_b1, double* %noalias_ret_a1
+; IPAA:   NoAlias:	double* %arg_b0, double* %noalias_arg_b1
+; IPAA:   NoAlias:	double* %arg_b1, double* %noalias_arg_b1
+; IPAA:   NoAlias:	double* %noalias_arg_b0, double* %noalias_arg_b1
+; IPAA:   MayAlias:	double* %callee_arg, double** %indirect_b0
+; IPAA:   MayAlias:	double* %nocap_callee_arg, double** %indirect_b0
+; IPAA:   MayAlias:	double* %arg_a0, double** %indirect_b0
+; IPAA:   MayAlias:	double* %arg_a1, double** %indirect_b0
+; IPAA:   MayAlias:	double* %noalias_arg_a0, double** %indirect_b0
+; IPAA:   MayAlias:	double* %noalias_arg_a1, double** %indirect_b0
+; IPAA:   MayAlias:	double** %indirect_a0, double** %indirect_b0
+; IPAA:   MayAlias:	double** %indirect_a1, double** %indirect_b0
+; IPAA:   MayAlias:	double* %loaded_a0, double** %indirect_b0
+; IPAA:   MayAlias:	double* %loaded_a1, double** %indirect_b0
+; IPAA:   MayAlias:	double* %escape_alloca_a0, double** %indirect_b0
+; IPAA:   MayAlias:	double* %escape_alloca_a1, double** %indirect_b0
+; IPAA:   MayAlias:	double* %noescape_alloca_a0, double** %indirect_b0
+; IPAA:   MayAlias:	double* %noescape_alloca_a1, double** %indirect_b0
+; IPAA:   MayAlias:	double* %normal_ret_a0, double** %indirect_b0
+; IPAA:   MayAlias:	double* %normal_ret_a1, double** %indirect_b0
+; IPAA:   MayAlias:	double* %noalias_ret_a0, double** %indirect_b0
+; IPAA:   MayAlias:	double* %noalias_ret_a1, double** %indirect_b0
+; IPAA:   MayAlias:	double* %arg_b0, double** %indirect_b0
+; IPAA:   MayAlias:	double* %arg_b1, double** %indirect_b0
+; IPAA:   NoAlias:	double* %noalias_arg_b0, double** %indirect_b0
+; IPAA:   NoAlias:	double* %noalias_arg_b1, double** %indirect_b0
+; IPAA:   MayAlias:	double* %callee_arg, double** %indirect_b1
+; IPAA:   MayAlias:	double* %nocap_callee_arg, double** %indirect_b1
+; IPAA:   MayAlias:	double* %arg_a0, double** %indirect_b1
+; IPAA:   MayAlias:	double* %arg_a1, double** %indirect_b1
+; IPAA:   MayAlias:	double* %noalias_arg_a0, double** %indirect_b1
+; IPAA:   MayAlias:	double* %noalias_arg_a1, double** %indirect_b1
+; IPAA:   MayAlias:	double** %indirect_a0, double** %indirect_b1
+; IPAA:   MayAlias:	double** %indirect_a1, double** %indirect_b1
+; IPAA:   MayAlias:	double* %loaded_a0, double** %indirect_b1
+; IPAA:   MayAlias:	double* %loaded_a1, double** %indirect_b1
+; IPAA:   MayAlias:	double* %escape_alloca_a0, double** %indirect_b1
+; IPAA:   MayAlias:	double* %escape_alloca_a1, double** %indirect_b1
+; IPAA:   MayAlias:	double* %noescape_alloca_a0, double** %indirect_b1
+; IPAA:   MayAlias:	double* %noescape_alloca_a1, double** %indirect_b1
+; IPAA:   MayAlias:	double* %normal_ret_a0, double** %indirect_b1
+; IPAA:   MayAlias:	double* %normal_ret_a1, double** %indirect_b1
+; IPAA:   MayAlias:	double* %noalias_ret_a0, double** %indirect_b1
+; IPAA:   MayAlias:	double* %noalias_ret_a1, double** %indirect_b1
+; IPAA:   MayAlias:	double* %arg_b0, double** %indirect_b1
+; IPAA:   MayAlias:	double* %arg_b1, double** %indirect_b1
+; IPAA:   NoAlias:	double* %noalias_arg_b0, double** %indirect_b1
+; IPAA:   NoAlias:	double* %noalias_arg_b1, double** %indirect_b1
+; IPAA:   MayAlias:	double** %indirect_b0, double** %indirect_b1
+; IPAA:   MayAlias:	double* %callee_arg, double* %loaded_b0
+; IPAA:   MayAlias:	double* %loaded_b0, double* %nocap_callee_arg
+; IPAA:   MayAlias:	double* %arg_a0, double* %loaded_b0
+; IPAA:   MayAlias:	double* %arg_a1, double* %loaded_b0
+; IPAA:   MayAlias:	double* %loaded_b0, double* %noalias_arg_a0
+; IPAA:   MayAlias:	double* %loaded_b0, double* %noalias_arg_a1
+; IPAA:   MayAlias:	double* %loaded_b0, double** %indirect_a0
+; IPAA:   MayAlias:	double* %loaded_b0, double** %indirect_a1
+; IPAA:   MayAlias:	double* %loaded_a0, double* %loaded_b0
+; IPAA:   MayAlias:	double* %loaded_a1, double* %loaded_b0
+; IPAA:   MayAlias:	double* %escape_alloca_a0, double* %loaded_b0
+; IPAA:   MayAlias:	double* %escape_alloca_a1, double* %loaded_b0
+; IPAA:   MayAlias:	double* %loaded_b0, double* %noescape_alloca_a0
+; IPAA:   MayAlias:	double* %loaded_b0, double* %noescape_alloca_a1
+; IPAA:   MayAlias:	double* %loaded_b0, double* %normal_ret_a0
+; IPAA:   MayAlias:	double* %loaded_b0, double* %normal_ret_a1
+; IPAA:   MayAlias:	double* %loaded_b0, double* %noalias_ret_a0
+; IPAA:   MayAlias:	double* %loaded_b0, double* %noalias_ret_a1
+; IPAA:   MayAlias:	double* %arg_b0, double* %loaded_b0
+; IPAA:   MayAlias:	double* %arg_b1, double* %loaded_b0
+; IPAA:   NoAlias:	double* %loaded_b0, double* %noalias_arg_b0
+; IPAA:   NoAlias:	double* %loaded_b0, double* %noalias_arg_b1
+; IPAA:   MayAlias:	double* %loaded_b0, double** %indirect_b0
+; IPAA:   MayAlias:	double* %loaded_b0, double** %indirect_b1
+; IPAA:   MayAlias:	double* %callee_arg, double* %loaded_b1
+; IPAA:   MayAlias:	double* %loaded_b1, double* %nocap_callee_arg
+; IPAA:   MayAlias:	double* %arg_a0, double* %loaded_b1
+; IPAA:   MayAlias:	double* %arg_a1, double* %loaded_b1
+; IPAA:   MayAlias:	double* %loaded_b1, double* %noalias_arg_a0
+; IPAA:   MayAlias:	double* %loaded_b1, double* %noalias_arg_a1
+; IPAA:   MayAlias:	double* %loaded_b1, double** %indirect_a0
+; IPAA:   MayAlias:	double* %loaded_b1, double** %indirect_a1
+; IPAA:   MayAlias:	double* %loaded_a0, double* %loaded_b1
+; IPAA:   MayAlias:	double* %loaded_a1, double* %loaded_b1
+; IPAA:   MayAlias:	double* %escape_alloca_a0, double* %loaded_b1
+; IPAA:   MayAlias:	double* %escape_alloca_a1, double* %loaded_b1
+; IPAA:   MayAlias:	double* %loaded_b1, double* %noescape_alloca_a0
+; IPAA:   MayAlias:	double* %loaded_b1, double* %noescape_alloca_a1
+; IPAA:   MayAlias:	double* %loaded_b1, double* %normal_ret_a0
+; IPAA:   MayAlias:	double* %loaded_b1, double* %normal_ret_a1
+; IPAA:   MayAlias:	double* %loaded_b1, double* %noalias_ret_a0
+; IPAA:   MayAlias:	double* %loaded_b1, double* %noalias_ret_a1
+; IPAA:   MayAlias:	double* %arg_b0, double* %loaded_b1
+; IPAA:   MayAlias:	double* %arg_b1, double* %loaded_b1
+; IPAA:   NoAlias:	double* %loaded_b1, double* %noalias_arg_b0
+; IPAA:   NoAlias:	double* %loaded_b1, double* %noalias_arg_b1
+; IPAA:   MayAlias:	double* %loaded_b1, double** %indirect_b0
+; IPAA:   MayAlias:	double* %loaded_b1, double** %indirect_b1
+; IPAA:   MayAlias:	double* %loaded_b0, double* %loaded_b1
+; IPAA:   MayAlias:	double* %callee_arg, double* %escape_alloca_b0
+; IPAA:   MayAlias:	double* %escape_alloca_b0, double* %nocap_callee_arg
+; IPAA:   MayAlias:	double* %arg_a0, double* %escape_alloca_b0
+; IPAA:   MayAlias:	double* %arg_a1, double* %escape_alloca_b0
+; IPAA:   MayAlias:	double* %escape_alloca_b0, double* %noalias_arg_a0
+; IPAA:   MayAlias:	double* %escape_alloca_b0, double* %noalias_arg_a1
+; IPAA:   MayAlias:	double* %escape_alloca_b0, double** %indirect_a0
+; IPAA:   MayAlias:	double* %escape_alloca_b0, double** %indirect_a1
+; IPAA:   MayAlias:	double* %escape_alloca_b0, double* %loaded_a0
+; IPAA:   MayAlias:	double* %escape_alloca_b0, double* %loaded_a1
+; IPAA:   NoAlias:	double* %escape_alloca_a0, double* %escape_alloca_b0
+; IPAA:   NoAlias:	double* %escape_alloca_a1, double* %escape_alloca_b0
+; IPAA:   NoAlias:	double* %escape_alloca_b0, double* %noescape_alloca_a0
+; IPAA:   NoAlias:	double* %escape_alloca_b0, double* %noescape_alloca_a1
+; IPAA:   MayAlias:	double* %escape_alloca_b0, double* %normal_ret_a0
+; IPAA:   MayAlias:	double* %escape_alloca_b0, double* %normal_ret_a1
+; IPAA:   MayAlias:	double* %escape_alloca_b0, double* %noalias_ret_a0
+; IPAA:   MayAlias:	double* %escape_alloca_b0, double* %noalias_ret_a1
+; IPAA:   NoAlias:	double* %arg_b0, double* %escape_alloca_b0
+; IPAA:   NoAlias:	double* %arg_b1, double* %escape_alloca_b0
+; IPAA:   NoAlias:	double* %escape_alloca_b0, double* %noalias_arg_b0
+; IPAA:   NoAlias:	double* %escape_alloca_b0, double* %noalias_arg_b1
+; IPAA:   NoAlias:	double* %escape_alloca_b0, double** %indirect_b0
+; IPAA:   NoAlias:	double* %escape_alloca_b0, double** %indirect_b1
+; IPAA:   MayAlias:	double* %escape_alloca_b0, double* %loaded_b0
+; IPAA:   MayAlias:	double* %escape_alloca_b0, double* %loaded_b1
+; IPAA:   MayAlias:	double* %callee_arg, double* %escape_alloca_b1
+; IPAA:   MayAlias:	double* %escape_alloca_b1, double* %nocap_callee_arg
+; IPAA:   MayAlias:	double* %arg_a0, double* %escape_alloca_b1
+; IPAA:   MayAlias:	double* %arg_a1, double* %escape_alloca_b1
+; IPAA:   MayAlias:	double* %escape_alloca_b1, double* %noalias_arg_a0
+; IPAA:   MayAlias:	double* %escape_alloca_b1, double* %noalias_arg_a1
+; IPAA:   MayAlias:	double* %escape_alloca_b1, double** %indirect_a0
+; IPAA:   MayAlias:	double* %escape_alloca_b1, double** %indirect_a1
+; IPAA:   MayAlias:	double* %escape_alloca_b1, double* %loaded_a0
+; IPAA:   MayAlias:	double* %escape_alloca_b1, double* %loaded_a1
+; IPAA:   NoAlias:	double* %escape_alloca_a0, double* %escape_alloca_b1
+; IPAA:   NoAlias:	double* %escape_alloca_a1, double* %escape_alloca_b1
+; IPAA:   NoAlias:	double* %escape_alloca_b1, double* %noescape_alloca_a0
+; IPAA:   NoAlias:	double* %escape_alloca_b1, double* %noescape_alloca_a1
+; IPAA:   MayAlias:	double* %escape_alloca_b1, double* %normal_ret_a0
+; IPAA:   MayAlias:	double* %escape_alloca_b1, double* %normal_ret_a1
+; IPAA:   MayAlias:	double* %escape_alloca_b1, double* %noalias_ret_a0
+; IPAA:   MayAlias:	double* %escape_alloca_b1, double* %noalias_ret_a1
+; IPAA:   NoAlias:	double* %arg_b0, double* %escape_alloca_b1
+; IPAA:   NoAlias:	double* %arg_b1, double* %escape_alloca_b1
+; IPAA:   NoAlias:	double* %escape_alloca_b1, double* %noalias_arg_b0
+; IPAA:   NoAlias:	double* %escape_alloca_b1, double* %noalias_arg_b1
+; IPAA:   NoAlias:	double* %escape_alloca_b1, double** %indirect_b0
+; IPAA:   NoAlias:	double* %escape_alloca_b1, double** %indirect_b1
+; IPAA:   MayAlias:	double* %escape_alloca_b1, double* %loaded_b0
+; IPAA:   MayAlias:	double* %escape_alloca_b1, double* %loaded_b1
+; IPAA:   NoAlias:	double* %escape_alloca_b0, double* %escape_alloca_b1
+; IPAA:   MayAlias:	double* %callee_arg, double* %noescape_alloca_b0
+; IPAA:   MayAlias:	double* %nocap_callee_arg, double* %noescape_alloca_b0
+; IPAA:   MayAlias:	double* %arg_a0, double* %noescape_alloca_b0
+; IPAA:   MayAlias:	double* %arg_a1, double* %noescape_alloca_b0
+; IPAA:   MayAlias:	double* %noalias_arg_a0, double* %noescape_alloca_b0
+; IPAA:   MayAlias:	double* %noalias_arg_a1, double* %noescape_alloca_b0
+; IPAA:   MayAlias:	double* %noescape_alloca_b0, double** %indirect_a0
+; IPAA:   MayAlias:	double* %noescape_alloca_b0, double** %indirect_a1
+; IPAA:   MayAlias:	double* %loaded_a0, double* %noescape_alloca_b0
+; IPAA:   MayAlias:	double* %loaded_a1, double* %noescape_alloca_b0
+; IPAA:   NoAlias:	double* %escape_alloca_a0, double* %noescape_alloca_b0
+; IPAA:   NoAlias:	double* %escape_alloca_a1, double* %noescape_alloca_b0
+; IPAA:   NoAlias:	double* %noescape_alloca_a0, double* %noescape_alloca_b0
+; IPAA:   NoAlias:	double* %noescape_alloca_a1, double* %noescape_alloca_b0
+; IPAA:   MayAlias:	double* %noescape_alloca_b0, double* %normal_ret_a0
+; IPAA:   MayAlias:	double* %noescape_alloca_b0, double* %normal_ret_a1
+; IPAA:   MayAlias:	double* %noalias_ret_a0, double* %noescape_alloca_b0
+; IPAA:   MayAlias:	double* %noalias_ret_a1, double* %noescape_alloca_b0
+; IPAA:   NoAlias:	double* %arg_b0, double* %noescape_alloca_b0
+; IPAA:   NoAlias:	double* %arg_b1, double* %noescape_alloca_b0
+; IPAA:   NoAlias:	double* %noalias_arg_b0, double* %noescape_alloca_b0
+; IPAA:   NoAlias:	double* %noalias_arg_b1, double* %noescape_alloca_b0
+; IPAA:   NoAlias:	double* %noescape_alloca_b0, double** %indirect_b0
+; IPAA:   NoAlias:	double* %noescape_alloca_b0, double** %indirect_b1
+; IPAA:   NoAlias:	double* %loaded_b0, double* %noescape_alloca_b0
+; IPAA:   NoAlias:	double* %loaded_b1, double* %noescape_alloca_b0
+; IPAA:   NoAlias:	double* %escape_alloca_b0, double* %noescape_alloca_b0
+; IPAA:   NoAlias:	double* %escape_alloca_b1, double* %noescape_alloca_b0
+; IPAA:   MayAlias:	double* %callee_arg, double* %noescape_alloca_b1
+; IPAA:   MayAlias:	double* %nocap_callee_arg, double* %noescape_alloca_b1
+; IPAA:   MayAlias:	double* %arg_a0, double* %noescape_alloca_b1
+; IPAA:   MayAlias:	double* %arg_a1, double* %noescape_alloca_b1
+; IPAA:   MayAlias:	double* %noalias_arg_a0, double* %noescape_alloca_b1
+; IPAA:   MayAlias:	double* %noalias_arg_a1, double* %noescape_alloca_b1
+; IPAA:   MayAlias:	double* %noescape_alloca_b1, double** %indirect_a0
+; IPAA:   MayAlias:	double* %noescape_alloca_b1, double** %indirect_a1
+; IPAA:   MayAlias:	double* %loaded_a0, double* %noescape_alloca_b1
+; IPAA:   MayAlias:	double* %loaded_a1, double* %noescape_alloca_b1
+; IPAA:   NoAlias:	double* %escape_alloca_a0, double* %noescape_alloca_b1
+; IPAA:   NoAlias:	double* %escape_alloca_a1, double* %noescape_alloca_b1
+; IPAA:   NoAlias:	double* %noescape_alloca_a0, double* %noescape_alloca_b1
+; IPAA:   NoAlias:	double* %noescape_alloca_a1, double* %noescape_alloca_b1
+; IPAA:   MayAlias:	double* %noescape_alloca_b1, double* %normal_ret_a0
+; IPAA:   MayAlias:	double* %noescape_alloca_b1, double* %normal_ret_a1
+; IPAA:   MayAlias:	double* %noalias_ret_a0, double* %noescape_alloca_b1
+; IPAA:   MayAlias:	double* %noalias_ret_a1, double* %noescape_alloca_b1
+; IPAA:   NoAlias:	double* %arg_b0, double* %noescape_alloca_b1
+; IPAA:   NoAlias:	double* %arg_b1, double* %noescape_alloca_b1
+; IPAA:   NoAlias:	double* %noalias_arg_b0, double* %noescape_alloca_b1
+; IPAA:   NoAlias:	double* %noalias_arg_b1, double* %noescape_alloca_b1
+; IPAA:   NoAlias:	double* %noescape_alloca_b1, double** %indirect_b0
+; IPAA:   NoAlias:	double* %noescape_alloca_b1, double** %indirect_b1
+; IPAA:   NoAlias:	double* %loaded_b0, double* %noescape_alloca_b1
+; IPAA:   NoAlias:	double* %loaded_b1, double* %noescape_alloca_b1
+; IPAA:   NoAlias:	double* %escape_alloca_b0, double* %noescape_alloca_b1
+; IPAA:   NoAlias:	double* %escape_alloca_b1, double* %noescape_alloca_b1
+; IPAA:   NoAlias:	double* %noescape_alloca_b0, double* %noescape_alloca_b1
+; IPAA:   MayAlias:	double* %callee_arg, double* %normal_ret_b0
+; IPAA:   MayAlias:	double* %nocap_callee_arg, double* %normal_ret_b0
+; IPAA:   MayAlias:	double* %arg_a0, double* %normal_ret_b0
+; IPAA:   MayAlias:	double* %arg_a1, double* %normal_ret_b0
+; IPAA:   MayAlias:	double* %noalias_arg_a0, double* %normal_ret_b0
+; IPAA:   MayAlias:	double* %noalias_arg_a1, double* %normal_ret_b0
+; IPAA:   MayAlias:	double* %normal_ret_b0, double** %indirect_a0
+; IPAA:   MayAlias:	double* %normal_ret_b0, double** %indirect_a1
+; IPAA:   MayAlias:	double* %loaded_a0, double* %normal_ret_b0
+; IPAA:   MayAlias:	double* %loaded_a1, double* %normal_ret_b0
+; IPAA:   MayAlias:	double* %escape_alloca_a0, double* %normal_ret_b0
+; IPAA:   MayAlias:	double* %escape_alloca_a1, double* %normal_ret_b0
+; IPAA:   MayAlias:	double* %noescape_alloca_a0, double* %normal_ret_b0
+; IPAA:   MayAlias:	double* %noescape_alloca_a1, double* %normal_ret_b0
+; IPAA:   MayAlias:	double* %normal_ret_a0, double* %normal_ret_b0
+; IPAA:   MayAlias:	double* %normal_ret_a1, double* %normal_ret_b0
+; IPAA:   MayAlias:	double* %noalias_ret_a0, double* %normal_ret_b0
+; IPAA:   MayAlias:	double* %noalias_ret_a1, double* %normal_ret_b0
+; IPAA:   MayAlias:	double* %arg_b0, double* %normal_ret_b0
+; IPAA:   MayAlias:	double* %arg_b1, double* %normal_ret_b0
+; IPAA:   NoAlias:	double* %noalias_arg_b0, double* %normal_ret_b0
+; IPAA:   NoAlias:	double* %noalias_arg_b1, double* %normal_ret_b0
+; IPAA:   MayAlias:	double* %normal_ret_b0, double** %indirect_b0
+; IPAA:   MayAlias:	double* %normal_ret_b0, double** %indirect_b1
+; IPAA:   MayAlias:	double* %loaded_b0, double* %normal_ret_b0
+; IPAA:   MayAlias:	double* %loaded_b1, double* %normal_ret_b0
+; IPAA:   MayAlias:	double* %escape_alloca_b0, double* %normal_ret_b0
+; IPAA:   MayAlias:	double* %escape_alloca_b1, double* %normal_ret_b0
+; IPAA:   NoAlias:	double* %noescape_alloca_b0, double* %normal_ret_b0
+; IPAA:   NoAlias:	double* %noescape_alloca_b1, double* %normal_ret_b0
+; IPAA:   MayAlias:	double* %callee_arg, double* %normal_ret_b1
+; IPAA:   MayAlias:	double* %nocap_callee_arg, double* %normal_ret_b1
+; IPAA:   MayAlias:	double* %arg_a0, double* %normal_ret_b1
+; IPAA:   MayAlias:	double* %arg_a1, double* %normal_ret_b1
+; IPAA:   MayAlias:	double* %noalias_arg_a0, double* %normal_ret_b1
+; IPAA:   MayAlias:	double* %noalias_arg_a1, double* %normal_ret_b1
+; IPAA:   MayAlias:	double* %normal_ret_b1, double** %indirect_a0
+; IPAA:   MayAlias:	double* %normal_ret_b1, double** %indirect_a1
+; IPAA:   MayAlias:	double* %loaded_a0, double* %normal_ret_b1
+; IPAA:   MayAlias:	double* %loaded_a1, double* %normal_ret_b1
+; IPAA:   MayAlias:	double* %escape_alloca_a0, double* %normal_ret_b1
+; IPAA:   MayAlias:	double* %escape_alloca_a1, double* %normal_ret_b1
+; IPAA:   MayAlias:	double* %noescape_alloca_a0, double* %normal_ret_b1
+; IPAA:   MayAlias:	double* %noescape_alloca_a1, double* %normal_ret_b1
+; IPAA:   MayAlias:	double* %normal_ret_a0, double* %normal_ret_b1
+; IPAA:   MayAlias:	double* %normal_ret_a1, double* %normal_ret_b1
+; IPAA:   MayAlias:	double* %noalias_ret_a0, double* %normal_ret_b1
+; IPAA:   MayAlias:	double* %noalias_ret_a1, double* %normal_ret_b1
+; IPAA:   MayAlias:	double* %arg_b0, double* %normal_ret_b1
+; IPAA:   MayAlias:	double* %arg_b1, double* %normal_ret_b1
+; IPAA:   NoAlias:	double* %noalias_arg_b0, double* %normal_ret_b1
+; IPAA:   NoAlias:	double* %noalias_arg_b1, double* %normal_ret_b1
+; IPAA:   MayAlias:	double* %normal_ret_b1, double** %indirect_b0
+; IPAA:   MayAlias:	double* %normal_ret_b1, double** %indirect_b1
+; IPAA:   MayAlias:	double* %loaded_b0, double* %normal_ret_b1
+; IPAA:   MayAlias:	double* %loaded_b1, double* %normal_ret_b1
+; IPAA:   MayAlias:	double* %escape_alloca_b0, double* %normal_ret_b1
+; IPAA:   MayAlias:	double* %escape_alloca_b1, double* %normal_ret_b1
+; IPAA:   NoAlias:	double* %noescape_alloca_b0, double* %normal_ret_b1
+; IPAA:   NoAlias:	double* %noescape_alloca_b1, double* %normal_ret_b1
+; IPAA:   MayAlias:	double* %normal_ret_b0, double* %normal_ret_b1
+; IPAA:   MayAlias:	double* %callee_arg, double* %noalias_ret_b0
+; IPAA:   MayAlias:	double* %noalias_ret_b0, double* %nocap_callee_arg
+; IPAA:   MayAlias:	double* %arg_a0, double* %noalias_ret_b0
+; IPAA:   MayAlias:	double* %arg_a1, double* %noalias_ret_b0
+; IPAA:   MayAlias:	double* %noalias_arg_a0, double* %noalias_ret_b0
+; IPAA:   MayAlias:	double* %noalias_arg_a1, double* %noalias_ret_b0
+; IPAA:   MayAlias:	double* %noalias_ret_b0, double** %indirect_a0
+; IPAA:   MayAlias:	double* %noalias_ret_b0, double** %indirect_a1
+; IPAA:   MayAlias:	double* %loaded_a0, double* %noalias_ret_b0
+; IPAA:   MayAlias:	double* %loaded_a1, double* %noalias_ret_b0
+; IPAA:   MayAlias:	double* %escape_alloca_a0, double* %noalias_ret_b0
+; IPAA:   MayAlias:	double* %escape_alloca_a1, double* %noalias_ret_b0
+; IPAA:   MayAlias:	double* %noalias_ret_b0, double* %noescape_alloca_a0
+; IPAA:   MayAlias:	double* %noalias_ret_b0, double* %noescape_alloca_a1
+; IPAA:   MayAlias:	double* %noalias_ret_b0, double* %normal_ret_a0
+; IPAA:   MayAlias:	double* %noalias_ret_b0, double* %normal_ret_a1
+; IPAA:   MayAlias:	double* %noalias_ret_a0, double* %noalias_ret_b0
+; IPAA:   MayAlias:	double* %noalias_ret_a1, double* %noalias_ret_b0
+; IPAA:   NoAlias:	double* %arg_b0, double* %noalias_ret_b0
+; IPAA:   NoAlias:	double* %arg_b1, double* %noalias_ret_b0
+; IPAA:   NoAlias:	double* %noalias_arg_b0, double* %noalias_ret_b0
+; IPAA:   NoAlias:	double* %noalias_arg_b1, double* %noalias_ret_b0
+; IPAA:   NoAlias:	double* %noalias_ret_b0, double** %indirect_b0
+; IPAA:   NoAlias:	double* %noalias_ret_b0, double** %indirect_b1
+; IPAA:   NoAlias:	double* %loaded_b0, double* %noalias_ret_b0
+; IPAA:   NoAlias:	double* %loaded_b1, double* %noalias_ret_b0
+; IPAA:   NoAlias:	double* %escape_alloca_b0, double* %noalias_ret_b0
+; IPAA:   NoAlias:	double* %escape_alloca_b1, double* %noalias_ret_b0
+; IPAA:   NoAlias:	double* %noalias_ret_b0, double* %noescape_alloca_b0
+; IPAA:   NoAlias:	double* %noalias_ret_b0, double* %noescape_alloca_b1
+; IPAA:   NoAlias:	double* %noalias_ret_b0, double* %normal_ret_b0
+; IPAA:   NoAlias:	double* %noalias_ret_b0, double* %normal_ret_b1
+; IPAA:   MayAlias:	double* %callee_arg, double* %noalias_ret_b1
+; IPAA:   MayAlias:	double* %noalias_ret_b1, double* %nocap_callee_arg
+; IPAA:   MayAlias:	double* %arg_a0, double* %noalias_ret_b1
+; IPAA:   MayAlias:	double* %arg_a1, double* %noalias_ret_b1
+; IPAA:   MayAlias:	double* %noalias_arg_a0, double* %noalias_ret_b1
+; IPAA:   MayAlias:	double* %noalias_arg_a1, double* %noalias_ret_b1
+; IPAA:   MayAlias:	double* %noalias_ret_b1, double** %indirect_a0
+; IPAA:   MayAlias:	double* %noalias_ret_b1, double** %indirect_a1
+; IPAA:   MayAlias:	double* %loaded_a0, double* %noalias_ret_b1
+; IPAA:   MayAlias:	double* %loaded_a1, double* %noalias_ret_b1
+; IPAA:   MayAlias:	double* %escape_alloca_a0, double* %noalias_ret_b1
+; IPAA:   MayAlias:	double* %escape_alloca_a1, double* %noalias_ret_b1
+; IPAA:   MayAlias:	double* %noalias_ret_b1, double* %noescape_alloca_a0
+; IPAA:   MayAlias:	double* %noalias_ret_b1, double* %noescape_alloca_a1
+; IPAA:   MayAlias:	double* %noalias_ret_b1, double* %normal_ret_a0
+; IPAA:   MayAlias:	double* %noalias_ret_b1, double* %normal_ret_a1
+; IPAA:   MayAlias:	double* %noalias_ret_a0, double* %noalias_ret_b1
+; IPAA:   MayAlias:	double* %noalias_ret_a1, double* %noalias_ret_b1
+; IPAA:   NoAlias:	double* %arg_b0, double* %noalias_ret_b1
+; IPAA:   NoAlias:	double* %arg_b1, double* %noalias_ret_b1
+; IPAA:   NoAlias:	double* %noalias_arg_b0, double* %noalias_ret_b1
+; IPAA:   NoAlias:	double* %noalias_arg_b1, double* %noalias_ret_b1
+; IPAA:   NoAlias:	double* %noalias_ret_b1, double** %indirect_b0
+; IPAA:   NoAlias:	double* %noalias_ret_b1, double** %indirect_b1
+; IPAA:   NoAlias:	double* %loaded_b0, double* %noalias_ret_b1
+; IPAA:   NoAlias:	double* %loaded_b1, double* %noalias_ret_b1
+; IPAA:   NoAlias:	double* %escape_alloca_b0, double* %noalias_ret_b1
+; IPAA:   NoAlias:	double* %escape_alloca_b1, double* %noalias_ret_b1
+; IPAA:   NoAlias:	double* %noalias_ret_b1, double* %noescape_alloca_b0
+; IPAA:   NoAlias:	double* %noalias_ret_b1, double* %noescape_alloca_b1
+; IPAA:   NoAlias:	double* %noalias_ret_b1, double* %normal_ret_b0
+; IPAA:   NoAlias:	double* %noalias_ret_b1, double* %normal_ret_b1
+; IPAA:   NoAlias:	double* %noalias_ret_b0, double* %noalias_ret_b1
+; IPAA:     ModRef:  Ptr: double* %callee_arg	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %nocap_callee_arg	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %arg_a0	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %arg_a1	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noalias_arg_a0	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noalias_arg_a1	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double** %indirect_a0	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double** %indirect_a1	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %loaded_a0	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %loaded_a1	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_a0	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_a1	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noescape_alloca_a0	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noescape_alloca_a1	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %normal_ret_a0	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %normal_ret_a1	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noalias_ret_a0	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noalias_ret_a1	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %arg_b0	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %arg_b1	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noalias_arg_b0	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noalias_arg_b1	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double** %indirect_b0	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double** %indirect_b1	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %loaded_b0	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %loaded_b1	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_b0	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_b1	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noescape_alloca_b0	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noescape_alloca_b1	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %normal_ret_b0	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %normal_ret_b1	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noalias_ret_b0	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noalias_ret_b1	<->  %normal_ret_a0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %callee_arg	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %nocap_callee_arg	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %arg_a0	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %arg_a1	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noalias_arg_a0	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noalias_arg_a1	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double** %indirect_a0	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double** %indirect_a1	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %loaded_a0	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %loaded_a1	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_a0	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_a1	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noescape_alloca_a0	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noescape_alloca_a1	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %normal_ret_a0	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %normal_ret_a1	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noalias_ret_a0	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noalias_ret_a1	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %arg_b0	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %arg_b1	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noalias_arg_b0	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noalias_arg_b1	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double** %indirect_b0	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double** %indirect_b1	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %loaded_b0	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %loaded_b1	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_b0	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_b1	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noescape_alloca_b0	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noescape_alloca_b1	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %normal_ret_b0	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %normal_ret_b1	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noalias_ret_b0	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noalias_ret_b1	<->  %normal_ret_a1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %callee_arg	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %nocap_callee_arg	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %arg_a0	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %arg_a1	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noalias_arg_a0	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noalias_arg_a1	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double** %indirect_a0	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double** %indirect_a1	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %loaded_a0	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %loaded_a1	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_a0	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_a1	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noescape_alloca_a0	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noescape_alloca_a1	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %normal_ret_a0	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %normal_ret_a1	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noalias_ret_a0	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noalias_ret_a1	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %arg_b0	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %arg_b1	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noalias_arg_b0	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noalias_arg_b1	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double** %indirect_b0	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double** %indirect_b1	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %loaded_b0	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %loaded_b1	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_b0	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_b1	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noescape_alloca_b0	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noescape_alloca_b1	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %normal_ret_b0	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %normal_ret_b1	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noalias_ret_b0	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noalias_ret_b1	<->  %noalias_ret_a0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %callee_arg	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %nocap_callee_arg	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %arg_a0	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %arg_a1	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noalias_arg_a0	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noalias_arg_a1	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double** %indirect_a0	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double** %indirect_a1	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %loaded_a0	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %loaded_a1	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_a0	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_a1	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noescape_alloca_a0	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noescape_alloca_a1	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %normal_ret_a0	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %normal_ret_a1	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noalias_ret_a0	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noalias_ret_a1	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %arg_b0	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %arg_b1	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noalias_arg_b0	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noalias_arg_b1	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double** %indirect_b0	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double** %indirect_b1	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %loaded_b0	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %loaded_b1	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_b0	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_b1	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noescape_alloca_b0	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noescape_alloca_b1	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %normal_ret_b0	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %normal_ret_b1	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noalias_ret_b0	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noalias_ret_b1	<->  %noalias_ret_a1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %callee_arg	<->  call void @callee(double* %escape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %nocap_callee_arg	<->  call void @callee(double* %escape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %arg_a0	<->  call void @callee(double* %escape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %arg_a1	<->  call void @callee(double* %escape_alloca_a0)
+; IPAA:   NoModRef:  Ptr: double* %noalias_arg_a0	<->  call void @callee(double* %escape_alloca_a0)
+; IPAA:   NoModRef:  Ptr: double* %noalias_arg_a1	<->  call void @callee(double* %escape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double** %indirect_a0	<->  call void @callee(double* %escape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double** %indirect_a1	<->  call void @callee(double* %escape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %loaded_a0	<->  call void @callee(double* %escape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %loaded_a1	<->  call void @callee(double* %escape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_a0	<->  call void @callee(double* %escape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_a1	<->  call void @callee(double* %escape_alloca_a0)
+; IPAA:   NoModRef:  Ptr: double* %noescape_alloca_a0	<->  call void @callee(double* %escape_alloca_a0)
+; IPAA:   NoModRef:  Ptr: double* %noescape_alloca_a1	<->  call void @callee(double* %escape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %normal_ret_a0	<->  call void @callee(double* %escape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %normal_ret_a1	<->  call void @callee(double* %escape_alloca_a0)
+; IPAA:   NoModRef:  Ptr: double* %noalias_ret_a0	<->  call void @callee(double* %escape_alloca_a0)
+; IPAA:   NoModRef:  Ptr: double* %noalias_ret_a1	<->  call void @callee(double* %escape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %arg_b0	<->  call void @callee(double* %escape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %arg_b1	<->  call void @callee(double* %escape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %noalias_arg_b0	<->  call void @callee(double* %escape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %noalias_arg_b1	<->  call void @callee(double* %escape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double** %indirect_b0	<->  call void @callee(double* %escape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double** %indirect_b1	<->  call void @callee(double* %escape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %loaded_b0	<->  call void @callee(double* %escape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %loaded_b1	<->  call void @callee(double* %escape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_b0	<->  call void @callee(double* %escape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_b1	<->  call void @callee(double* %escape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %noescape_alloca_b0	<->  call void @callee(double* %escape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %noescape_alloca_b1	<->  call void @callee(double* %escape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %normal_ret_b0	<->  call void @callee(double* %escape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %normal_ret_b1	<->  call void @callee(double* %escape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %noalias_ret_b0	<->  call void @callee(double* %escape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %noalias_ret_b1	<->  call void @callee(double* %escape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %callee_arg	<->  call void @callee(double* %escape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %nocap_callee_arg	<->  call void @callee(double* %escape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %arg_a0	<->  call void @callee(double* %escape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %arg_a1	<->  call void @callee(double* %escape_alloca_a1)
+; IPAA:   NoModRef:  Ptr: double* %noalias_arg_a0	<->  call void @callee(double* %escape_alloca_a1)
+; IPAA:   NoModRef:  Ptr: double* %noalias_arg_a1	<->  call void @callee(double* %escape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double** %indirect_a0	<->  call void @callee(double* %escape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double** %indirect_a1	<->  call void @callee(double* %escape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %loaded_a0	<->  call void @callee(double* %escape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %loaded_a1	<->  call void @callee(double* %escape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_a0	<->  call void @callee(double* %escape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_a1	<->  call void @callee(double* %escape_alloca_a1)
+; IPAA:   NoModRef:  Ptr: double* %noescape_alloca_a0	<->  call void @callee(double* %escape_alloca_a1)
+; IPAA:   NoModRef:  Ptr: double* %noescape_alloca_a1	<->  call void @callee(double* %escape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %normal_ret_a0	<->  call void @callee(double* %escape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %normal_ret_a1	<->  call void @callee(double* %escape_alloca_a1)
+; IPAA:   NoModRef:  Ptr: double* %noalias_ret_a0	<->  call void @callee(double* %escape_alloca_a1)
+; IPAA:   NoModRef:  Ptr: double* %noalias_ret_a1	<->  call void @callee(double* %escape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %arg_b0	<->  call void @callee(double* %escape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %arg_b1	<->  call void @callee(double* %escape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %noalias_arg_b0	<->  call void @callee(double* %escape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %noalias_arg_b1	<->  call void @callee(double* %escape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double** %indirect_b0	<->  call void @callee(double* %escape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double** %indirect_b1	<->  call void @callee(double* %escape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %loaded_b0	<->  call void @callee(double* %escape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %loaded_b1	<->  call void @callee(double* %escape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_b0	<->  call void @callee(double* %escape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_b1	<->  call void @callee(double* %escape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %noescape_alloca_b0	<->  call void @callee(double* %escape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %noescape_alloca_b1	<->  call void @callee(double* %escape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %normal_ret_b0	<->  call void @callee(double* %escape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %normal_ret_b1	<->  call void @callee(double* %escape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %noalias_ret_b0	<->  call void @callee(double* %escape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %noalias_ret_b1	<->  call void @callee(double* %escape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %callee_arg	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %nocap_callee_arg	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %arg_a0	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %arg_a1	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; IPAA:   NoModRef:  Ptr: double* %noalias_arg_a0	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; IPAA:   NoModRef:  Ptr: double* %noalias_arg_a1	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double** %indirect_a0	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double** %indirect_a1	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %loaded_a0	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %loaded_a1	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_a0	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_a1	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %noescape_alloca_a0	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; IPAA:   NoModRef:  Ptr: double* %noescape_alloca_a1	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %normal_ret_a0	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %normal_ret_a1	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; IPAA:   NoModRef:  Ptr: double* %noalias_ret_a0	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; IPAA:   NoModRef:  Ptr: double* %noalias_ret_a1	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %arg_b0	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %arg_b1	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %noalias_arg_b0	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %noalias_arg_b1	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double** %indirect_b0	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double** %indirect_b1	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %loaded_b0	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %loaded_b1	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_b0	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_b1	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %noescape_alloca_b0	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %noescape_alloca_b1	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %normal_ret_b0	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %normal_ret_b1	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %noalias_ret_b0	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %noalias_ret_b1	<->  call void @nocap_callee(double* %noescape_alloca_a0)
+; IPAA:     ModRef:  Ptr: double* %callee_arg	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %nocap_callee_arg	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %arg_a0	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %arg_a1	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; IPAA:   NoModRef:  Ptr: double* %noalias_arg_a0	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; IPAA:   NoModRef:  Ptr: double* %noalias_arg_a1	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double** %indirect_a0	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double** %indirect_a1	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %loaded_a0	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %loaded_a1	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_a0	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_a1	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; IPAA:   NoModRef:  Ptr: double* %noescape_alloca_a0	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %noescape_alloca_a1	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %normal_ret_a0	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %normal_ret_a1	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; IPAA:   NoModRef:  Ptr: double* %noalias_ret_a0	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; IPAA:   NoModRef:  Ptr: double* %noalias_ret_a1	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %arg_b0	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %arg_b1	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %noalias_arg_b0	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %noalias_arg_b1	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double** %indirect_b0	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double** %indirect_b1	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %loaded_b0	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %loaded_b1	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_b0	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_b1	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %noescape_alloca_b0	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %noescape_alloca_b1	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %normal_ret_b0	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %normal_ret_b1	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %noalias_ret_b0	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %noalias_ret_b1	<->  call void @nocap_callee(double* %noescape_alloca_a1)
+; IPAA:     ModRef:  Ptr: double* %callee_arg	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %nocap_callee_arg	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %arg_a0	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %arg_a1	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noalias_arg_a0	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noalias_arg_a1	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double** %indirect_a0	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double** %indirect_a1	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %loaded_a0	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %loaded_a1	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_a0	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_a1	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noescape_alloca_a0	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noescape_alloca_a1	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %normal_ret_a0	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %normal_ret_a1	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noalias_ret_a0	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noalias_ret_a1	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %arg_b0	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %arg_b1	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noalias_arg_b0	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noalias_arg_b1	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double** %indirect_b0	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double** %indirect_b1	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %loaded_b0	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %loaded_b1	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_b0	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_b1	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noescape_alloca_b0	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noescape_alloca_b1	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %normal_ret_b0	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %normal_ret_b1	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noalias_ret_b0	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noalias_ret_b1	<->  %normal_ret_b0 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %callee_arg	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %nocap_callee_arg	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %arg_a0	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %arg_a1	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noalias_arg_a0	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noalias_arg_a1	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double** %indirect_a0	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double** %indirect_a1	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %loaded_a0	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %loaded_a1	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_a0	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_a1	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noescape_alloca_a0	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noescape_alloca_a1	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %normal_ret_a0	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %normal_ret_a1	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noalias_ret_a0	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noalias_ret_a1	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %arg_b0	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %arg_b1	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noalias_arg_b0	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noalias_arg_b1	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double** %indirect_b0	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double** %indirect_b1	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %loaded_b0	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %loaded_b1	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_b0	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_b1	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noescape_alloca_b0	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noescape_alloca_b1	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %normal_ret_b0	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %normal_ret_b1	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noalias_ret_b0	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noalias_ret_b1	<->  %normal_ret_b1 = call double* @normal_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %callee_arg	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %nocap_callee_arg	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %arg_a0	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %arg_a1	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noalias_arg_a0	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noalias_arg_a1	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double** %indirect_a0	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double** %indirect_a1	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %loaded_a0	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %loaded_a1	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_a0	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_a1	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noescape_alloca_a0	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noescape_alloca_a1	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %normal_ret_a0	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %normal_ret_a1	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noalias_ret_a0	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noalias_ret_a1	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %arg_b0	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %arg_b1	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noalias_arg_b0	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noalias_arg_b1	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double** %indirect_b0	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double** %indirect_b1	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %loaded_b0	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %loaded_b1	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_b0	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_b1	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noescape_alloca_b0	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noescape_alloca_b1	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %normal_ret_b0	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %normal_ret_b1	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noalias_ret_b0	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noalias_ret_b1	<->  %noalias_ret_b0 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %callee_arg	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %nocap_callee_arg	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %arg_a0	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %arg_a1	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noalias_arg_a0	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noalias_arg_a1	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double** %indirect_a0	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double** %indirect_a1	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %loaded_a0	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %loaded_a1	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_a0	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_a1	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noescape_alloca_a0	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noescape_alloca_a1	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %normal_ret_a0	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %normal_ret_a1	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noalias_ret_a0	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noalias_ret_a1	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %arg_b0	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %arg_b1	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noalias_arg_b0	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noalias_arg_b1	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double** %indirect_b0	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double** %indirect_b1	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %loaded_b0	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %loaded_b1	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_b0	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_b1	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noescape_alloca_b0	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noescape_alloca_b1	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %normal_ret_b0	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %normal_ret_b1	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:   NoModRef:  Ptr: double* %noalias_ret_b0	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %noalias_ret_b1	<->  %noalias_ret_b1 = call double* @noalias_returner() ; <double*> [#uses=1]
+; IPAA:     ModRef:  Ptr: double* %callee_arg	<->  call void @callee(double* %escape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %nocap_callee_arg	<->  call void @callee(double* %escape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %arg_a0	<->  call void @callee(double* %escape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %arg_a1	<->  call void @callee(double* %escape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %noalias_arg_a0	<->  call void @callee(double* %escape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %noalias_arg_a1	<->  call void @callee(double* %escape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double** %indirect_a0	<->  call void @callee(double* %escape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double** %indirect_a1	<->  call void @callee(double* %escape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %loaded_a0	<->  call void @callee(double* %escape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %loaded_a1	<->  call void @callee(double* %escape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_a0	<->  call void @callee(double* %escape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_a1	<->  call void @callee(double* %escape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %noescape_alloca_a0	<->  call void @callee(double* %escape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %noescape_alloca_a1	<->  call void @callee(double* %escape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %normal_ret_a0	<->  call void @callee(double* %escape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %normal_ret_a1	<->  call void @callee(double* %escape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %noalias_ret_a0	<->  call void @callee(double* %escape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %noalias_ret_a1	<->  call void @callee(double* %escape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %arg_b0	<->  call void @callee(double* %escape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %arg_b1	<->  call void @callee(double* %escape_alloca_b0)
+; IPAA:   NoModRef:  Ptr: double* %noalias_arg_b0	<->  call void @callee(double* %escape_alloca_b0)
+; IPAA:   NoModRef:  Ptr: double* %noalias_arg_b1	<->  call void @callee(double* %escape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double** %indirect_b0	<->  call void @callee(double* %escape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double** %indirect_b1	<->  call void @callee(double* %escape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %loaded_b0	<->  call void @callee(double* %escape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %loaded_b1	<->  call void @callee(double* %escape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_b0	<->  call void @callee(double* %escape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_b1	<->  call void @callee(double* %escape_alloca_b0)
+; IPAA:   NoModRef:  Ptr: double* %noescape_alloca_b0	<->  call void @callee(double* %escape_alloca_b0)
+; IPAA:   NoModRef:  Ptr: double* %noescape_alloca_b1	<->  call void @callee(double* %escape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %normal_ret_b0	<->  call void @callee(double* %escape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %normal_ret_b1	<->  call void @callee(double* %escape_alloca_b0)
+; IPAA:   NoModRef:  Ptr: double* %noalias_ret_b0	<->  call void @callee(double* %escape_alloca_b0)
+; IPAA:   NoModRef:  Ptr: double* %noalias_ret_b1	<->  call void @callee(double* %escape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %callee_arg	<->  call void @callee(double* %escape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %nocap_callee_arg	<->  call void @callee(double* %escape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %arg_a0	<->  call void @callee(double* %escape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %arg_a1	<->  call void @callee(double* %escape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %noalias_arg_a0	<->  call void @callee(double* %escape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %noalias_arg_a1	<->  call void @callee(double* %escape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double** %indirect_a0	<->  call void @callee(double* %escape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double** %indirect_a1	<->  call void @callee(double* %escape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %loaded_a0	<->  call void @callee(double* %escape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %loaded_a1	<->  call void @callee(double* %escape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_a0	<->  call void @callee(double* %escape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_a1	<->  call void @callee(double* %escape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %noescape_alloca_a0	<->  call void @callee(double* %escape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %noescape_alloca_a1	<->  call void @callee(double* %escape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %normal_ret_a0	<->  call void @callee(double* %escape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %normal_ret_a1	<->  call void @callee(double* %escape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %noalias_ret_a0	<->  call void @callee(double* %escape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %noalias_ret_a1	<->  call void @callee(double* %escape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %arg_b0	<->  call void @callee(double* %escape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %arg_b1	<->  call void @callee(double* %escape_alloca_b1)
+; IPAA:   NoModRef:  Ptr: double* %noalias_arg_b0	<->  call void @callee(double* %escape_alloca_b1)
+; IPAA:   NoModRef:  Ptr: double* %noalias_arg_b1	<->  call void @callee(double* %escape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double** %indirect_b0	<->  call void @callee(double* %escape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double** %indirect_b1	<->  call void @callee(double* %escape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %loaded_b0	<->  call void @callee(double* %escape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %loaded_b1	<->  call void @callee(double* %escape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_b0	<->  call void @callee(double* %escape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_b1	<->  call void @callee(double* %escape_alloca_b1)
+; IPAA:   NoModRef:  Ptr: double* %noescape_alloca_b0	<->  call void @callee(double* %escape_alloca_b1)
+; IPAA:   NoModRef:  Ptr: double* %noescape_alloca_b1	<->  call void @callee(double* %escape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %normal_ret_b0	<->  call void @callee(double* %escape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %normal_ret_b1	<->  call void @callee(double* %escape_alloca_b1)
+; IPAA:   NoModRef:  Ptr: double* %noalias_ret_b0	<->  call void @callee(double* %escape_alloca_b1)
+; IPAA:   NoModRef:  Ptr: double* %noalias_ret_b1	<->  call void @callee(double* %escape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %callee_arg	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %nocap_callee_arg	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %arg_a0	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %arg_a1	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %noalias_arg_a0	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %noalias_arg_a1	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double** %indirect_a0	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double** %indirect_a1	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %loaded_a0	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %loaded_a1	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_a0	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_a1	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %noescape_alloca_a0	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %noescape_alloca_a1	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %normal_ret_a0	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %normal_ret_a1	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %noalias_ret_a0	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %noalias_ret_a1	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %arg_b0	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %arg_b1	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; IPAA:   NoModRef:  Ptr: double* %noalias_arg_b0	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; IPAA:   NoModRef:  Ptr: double* %noalias_arg_b1	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double** %indirect_b0	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double** %indirect_b1	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %loaded_b0	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %loaded_b1	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_b0	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_b1	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %noescape_alloca_b0	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; IPAA:   NoModRef:  Ptr: double* %noescape_alloca_b1	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %normal_ret_b0	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %normal_ret_b1	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; IPAA:   NoModRef:  Ptr: double* %noalias_ret_b0	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; IPAA:   NoModRef:  Ptr: double* %noalias_ret_b1	<->  call void @nocap_callee(double* %noescape_alloca_b0)
+; IPAA:     ModRef:  Ptr: double* %callee_arg	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %nocap_callee_arg	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %arg_a0	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %arg_a1	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %noalias_arg_a0	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %noalias_arg_a1	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double** %indirect_a0	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double** %indirect_a1	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %loaded_a0	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %loaded_a1	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_a0	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_a1	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %noescape_alloca_a0	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %noescape_alloca_a1	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %normal_ret_a0	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %normal_ret_a1	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %noalias_ret_a0	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %noalias_ret_a1	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %arg_b0	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %arg_b1	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; IPAA:   NoModRef:  Ptr: double* %noalias_arg_b0	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; IPAA:   NoModRef:  Ptr: double* %noalias_arg_b1	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double** %indirect_b0	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double** %indirect_b1	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %loaded_b0	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %loaded_b1	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_b0	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %escape_alloca_b1	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; IPAA:   NoModRef:  Ptr: double* %noescape_alloca_b0	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %noescape_alloca_b1	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %normal_ret_b0	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; IPAA:     ModRef:  Ptr: double* %normal_ret_b1	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; IPAA:   NoModRef:  Ptr: double* %noalias_ret_b0	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; IPAA:   NoModRef:  Ptr: double* %noalias_ret_b1	<->  call void @nocap_callee(double* %noescape_alloca_b1)
+; IPAA: ===== Alias Analysis Evaluator Report =====
+; IPAA:   561 Total Alias Queries Performed
+; IPAA:   184 no alias responses (32.7%)
+; IPAA:   377 may alias responses (67.2%)
+; IPAA:   0 must alias responses (0.0%)
+; IPAA:   Alias Analysis Evaluator Pointer Alias Summary: 32%/67%/0%
+; IPAA:   544 Total ModRef Queries Performed
+; IPAA:   88 no mod/ref responses (16.1%)
+; IPAA:   0 mod responses (0.0%)
+; IPAA:   0 ref responses (0.0%)
+; IPAA:   456 mod & ref responses (83.8%)
+; IPAA:   Alias Analysis Evaluator Mod/Ref Summary: 16%/0%/0%/83%

Modified: llvm/trunk/test/Analysis/BasicAA/interprocedural.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/BasicAA/interprocedural.ll?rev=107420&r1=107419&r2=107420&view=diff
==============================================================================
--- llvm/trunk/test/Analysis/BasicAA/interprocedural.ll (original)
+++ llvm/trunk/test/Analysis/BasicAA/interprocedural.ll Thu Jul  1 15:08:40 2010
@@ -27,23 +27,33 @@
   ret void
 }
 
-; An alloca can alias an argument in a recursive function.
-; CHECK: MayAlias: i64* %t, i64* %u
+; An alloca does not alias an argument in the same function.
+; CHECK: NoAlias: i64* %t, i64* %u
+; CHECK: NoAlias: i64* %a, i64* %u
+; CHECK: NoAlias: i64* %a, i64* %t
 ; CHECK: MayAlias: i64* %u, i64* %v
 ; CHECK: MayAlias: i64* %t, i64* %v
-
+; CHECK: NoAlias: i64* %a, i64* %v
+; CHECK: MayAlias: i64* %b, i64* %u
+; CHECK: MayAlias: i64* %b, i64* %t
+; CHECK: MayAlias: i64* %b, i64* %v
+declare i64* @r0_callee(i64*)
 define i64* @r0(i64* %u) {
   %t = alloca i64, i32 10
-  %v = call i64* @r0(i64* %t)
+  %a = alloca i64, i32 10
+  %v = call i64* @r0_callee(i64* %t)
+  %b = call i64* @r0_callee(i64* %t)
   store i64 0, i64* %t
   store i64 0, i64* %u
   store i64 0, i64* %v
+  store i64 0, i64* %a
+  store i64 0, i64* %b
   ret i64* %t
 }
 
-; The noalias attribute is not necessarily safe in an interprocedural context even
-; in comparison to other noalias arguments in the same function.
-; CHECK: MayAlias: i8* %w, i8* %x
+; The noalias attribute is safe when both arguments belong to the same function
+; even in an interprocedural context.
+; CHECK: NoAlias: i8* %w, i8* %x
 
 define void @q0(i8* noalias %w, i8* noalias %x) {
   store i8 0, i8* %w




From isanbard at gmail.com  Thu Jul  1 15:13:33 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 1 Jul 2010 13:13:33 -0700
Subject: [llvm-commits] [llvm] r107205 -
	in	/llvm/trunk:	bindings/ada/llvm/ docs/
	include/llvm-c/	include/llvm/	include/llvm/CodeGen/
	include/llvm/MC/ include/llvm/Target/	lib/AsmParser/
	lib/Bitcode/Reader/	lib/Bitcode/Writer/ lib/CodeGen/
	lib/CodeGen/AsmPrinter/	lib/Linker/ lib/MC/	lib/Target/
	lib/Target/CppBackend/	lib/Target/XCore/AsmPrinter/	lib/Transforms/IPO/
	lib/VMCore/	tools/llvm-nm/
In-Reply-To: <4A117D6F-C5D4-4FE5-A828-03F7897814E5@apple.com>
References: <20100629212400.DABF32A6C12C@llvm.org>
	<C7E3E4A7-A598-4C61-9513-2DFC7C2EC4CC@apple.com>
	<AF811FB0-E72D-44DD-8BBD-1C6D4971F1AF@gmail.com>
	<FA99D48A-0561-420D-AA6C-6983AB1AFEC9@apple.com>
	<9E57AC43-C5F3-418C-8159-F3AF703BA3F1@apple.com>
	<79223963-640D-43E4-BB73-0D3D9DD729D6@gmail.com>
	<CBE117B2-2498-4A1D-8967-0DC60214B58C@apple.com>
	<7AB97E23-B4AA-4784-83D4-B31C6818EE09@gmail.com>
	<4A117D6F-C5D4-4FE5-A828-03F7897814E5@apple.com>
Message-ID: <B90110C0-2F42-49B7-B4EB-9B9127F9CD5D@gmail.com>

On Jul 1, 2010, at 12:43 PM, Chris Lattner wrote:

> Please tailor this for Darwin, there is no reason to speculatively generalize this for targets that don't exist.  If a target starts existing that wants to use this, it will probably need other hooks.  Trying to anticipate this theoretical possibility just clutters the code.
> 
I can't see how this is cluttering the code. It's consistent with how the rest of the linkage code works, which isn't clutter. And there is a long tradition of wanting to anticipate for theoretical possibilities -- for example, allowing for the (unlikely) possibility of having multiple personality functions for one function with the new exception handling proposal.

I will make the change.

-bw




From daniel at zuster.org  Thu Jul  1 15:20:02 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 01 Jul 2010 20:20:02 -0000
Subject: [llvm-commits] [llvm] r107424 -
	/llvm/trunk/lib/MC/MCParser/AsmParser.cpp
Message-ID: <20100701202002.17F772A6C12C@llvm.org>

Author: ddunbar
Date: Thu Jul  1 15:20:01 2010
New Revision: 107424

URL: http://llvm.org/viewvc/llvm-project?rev=107424&view=rev
Log:
MC: Fix an error message.

Modified:
    llvm/trunk/lib/MC/MCParser/AsmParser.cpp

Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=107424&r1=107423&r2=107424&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original)
+++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Thu Jul  1 15:20:01 2010
@@ -1938,7 +1938,7 @@
   }
 
   if (Lexer.isNot(AsmToken::EndOfStatement))
-    return TokError("unexpected token in '.file' directive");
+    return TokError("unexpected token in '.line' directive");
 
   return false;
 }




From daniel at zuster.org  Thu Jul  1 15:20:05 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 01 Jul 2010 20:20:05 -0000
Subject: [llvm-commits] [llvm] r107425 -
	/llvm/trunk/include/llvm/Support/COFF.h
Message-ID: <20100701202005.4F8C32A6C12D@llvm.org>

Author: ddunbar
Date: Thu Jul  1 15:20:05 2010
New Revision: 107425

URL: http://llvm.org/viewvc/llvm-project?rev=107425&view=rev
Log:
Remove stray comma.

Modified:
    llvm/trunk/include/llvm/Support/COFF.h

Modified: llvm/trunk/include/llvm/Support/COFF.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/COFF.h?rev=107425&r1=107424&r2=107425&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/COFF.h (original)
+++ llvm/trunk/include/llvm/Support/COFF.h Thu Jul  1 15:20:05 2010
@@ -64,7 +64,7 @@
     SF_ClassMask = 0x00FF0000,
     SF_ClassShift = 16,
 
-    SF_WeakReference = 0x01000000,
+    SF_WeakReference = 0x01000000
   };
 
   enum symbol_storage_class {




From daniel at zuster.org  Thu Jul  1 15:41:56 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 01 Jul 2010 20:41:56 -0000
Subject: [llvm-commits] [llvm] r107426 - in /llvm/trunk:
 include/llvm/MC/MCParser/AsmParser.h
 lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
 lib/MC/MCParser/AsmParser.cpp tools/edis/EDDisassembler.cpp
 tools/llvm-mc/llvm-mc.cpp
Message-ID: <20100701204156.941F02A6C12C@llvm.org>

Author: ddunbar
Date: Thu Jul  1 15:41:56 2010
New Revision: 107426

URL: http://llvm.org/viewvc/llvm-project?rev=107426&view=rev
Log:
MC: Pass the target instance to the AsmParser constructor.

Modified:
    llvm/trunk/include/llvm/MC/MCParser/AsmParser.h
    llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
    llvm/trunk/lib/MC/MCParser/AsmParser.cpp
    llvm/trunk/tools/edis/EDDisassembler.cpp
    llvm/trunk/tools/llvm-mc/llvm-mc.cpp

Modified: llvm/trunk/include/llvm/MC/MCParser/AsmParser.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/AsmParser.h?rev=107426&r1=107425&r2=107426&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCParser/AsmParser.h (original)
+++ llvm/trunk/include/llvm/MC/MCParser/AsmParser.h Thu Jul  1 15:41:56 2010
@@ -36,11 +36,14 @@
 class Twine;
 
 class AsmParser : public MCAsmParser {
+  AsmParser(const AsmParser &);   // DO NOT IMPLEMENT
+  void operator=(const AsmParser &);  // DO NOT IMPLEMENT
 private:
   AsmLexer Lexer;
   MCContext &Ctx;
   MCStreamer &Out;
   SourceMgr &SrcMgr;
+  TargetAsmParser *GenericTargetParser;
   TargetAsmParser *TargetParser;
   
   /// This is the current buffer index we're lexing from as managed by the
@@ -56,7 +59,7 @@
   /// in the directive name and the location of the directive keyword.
   StringMap<bool(AsmParser::*)(StringRef, SMLoc)> DirectiveMap;
 public:
-  AsmParser(SourceMgr &SM, MCContext &Ctx, MCStreamer &Out,
+  AsmParser(const Target &T, SourceMgr &SM, MCContext &Ctx, MCStreamer &Out,
             const MCAsmInfo &MAI);
   ~AsmParser();
 

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp?rev=107426&r1=107425&r2=107426&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp Thu Jul  1 15:41:56 2010
@@ -83,7 +83,7 @@
   // Tell SrcMgr about this buffer, it takes ownership of the buffer.
   SrcMgr.AddNewSourceBuffer(Buffer, SMLoc());
   
-  AsmParser Parser(SrcMgr, OutContext, OutStreamer, *MAI);
+  AsmParser Parser(TM.getTarget(), SrcMgr, OutContext, OutStreamer, *MAI);
   OwningPtr<TargetAsmParser> TAP(TM.getTarget().createAsmParser(Parser));
   if (!TAP)
     report_fatal_error("Inline asm not supported by this streamer because"

Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=107426&r1=107425&r2=107426&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original)
+++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Thu Jul  1 15:41:56 2010
@@ -32,10 +32,9 @@
 
 enum { DEFAULT_ADDRSPACE = 0 };
 
-AsmParser::AsmParser(SourceMgr &_SM, MCContext &_Ctx, MCStreamer &_Out,
-                     const MCAsmInfo &_MAI) 
-  : Lexer(_MAI), Ctx(_Ctx), Out(_Out), SrcMgr(_SM), TargetParser(0),
-    CurBuffer(0) {
+AsmParser::AsmParser(const Target &T, SourceMgr &_SM, MCContext &_Ctx,
+                     MCStreamer &_Out, const MCAsmInfo &_MAI)
+  : Lexer(_MAI), Ctx(_Ctx), Out(_Out), SrcMgr(_SM), CurBuffer(0) {
   Lexer.setBuffer(SrcMgr.getMemoryBuffer(CurBuffer));
   
   // Debugging directives.
@@ -44,8 +43,6 @@
   AddDirectiveHandler(".loc", &AsmParser::ParseDirectiveLoc);
 }
 
-
-
 AsmParser::~AsmParser() {
 }
 

Modified: llvm/trunk/tools/edis/EDDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/edis/EDDisassembler.cpp?rev=107426&r1=107425&r2=107426&view=diff
==============================================================================
--- llvm/trunk/tools/edis/EDDisassembler.cpp (original)
+++ llvm/trunk/tools/edis/EDDisassembler.cpp Thu Jul  1 15:41:56 2010
@@ -364,7 +364,7 @@
   sourceMgr.AddNewSourceBuffer(buf, SMLoc()); // ownership of buf handed over
   MCContext context(*AsmInfo);
   OwningPtr<MCStreamer> streamer(createNullStreamer(context));
-  AsmParser genericParser(sourceMgr, context, *streamer, *AsmInfo);
+  AsmParser genericParser(*Tgt, sourceMgr, context, *streamer, *AsmInfo);
   OwningPtr<TargetAsmParser> TargetParser(Tgt->createAsmParser(genericParser));
   
   AsmToken OpcodeToken = genericParser.Lex();

Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=107426&r1=107425&r2=107426&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original)
+++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Thu Jul  1 15:41:56 2010
@@ -312,7 +312,7 @@
     Str.reset(createLoggingStreamer(Str.take(), errs()));
   }
 
-  AsmParser Parser(SrcMgr, Ctx, *Str.get(), *MAI);
+  AsmParser Parser(*TheTarget, SrcMgr, Ctx, *Str.get(), *MAI);
   OwningPtr<TargetAsmParser> TAP(TheTarget->createAsmParser(Parser));
   if (!TAP) {
     errs() << ProgName 




From daniel at zuster.org  Thu Jul  1 15:48:51 2010
From: daniel at zuster.org (Daniel Dunbar)
Date: Thu, 01 Jul 2010 20:48:51 -0000
Subject: [llvm-commits] [llvm] r107428 - in /llvm/trunk:
 include/llvm/MC/MCParser/AsmParser.h lib/MC/MCParser/AsmParser.cpp
Message-ID: <20100701204851.DC83F2A6C12C@llvm.org>

Author: ddunbar
Date: Thu Jul  1 15:48:51 2010
New Revision: 107428

URL: http://llvm.org/viewvc/llvm-project?rev=107428&view=rev
Log:
MC: Fix some stray hunks I didn't intend to commit.

Modified:
    llvm/trunk/include/llvm/MC/MCParser/AsmParser.h
    llvm/trunk/lib/MC/MCParser/AsmParser.cpp

Modified: llvm/trunk/include/llvm/MC/MCParser/AsmParser.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/AsmParser.h?rev=107428&r1=107427&r2=107428&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCParser/AsmParser.h (original)
+++ llvm/trunk/include/llvm/MC/MCParser/AsmParser.h Thu Jul  1 15:48:51 2010
@@ -43,7 +43,6 @@
   MCContext &Ctx;
   MCStreamer &Out;
   SourceMgr &SrcMgr;
-  TargetAsmParser *GenericTargetParser;
   TargetAsmParser *TargetParser;
   
   /// This is the current buffer index we're lexing from as managed by the

Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=107428&r1=107427&r2=107428&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original)
+++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Thu Jul  1 15:48:51 2010
@@ -34,7 +34,8 @@
 
 AsmParser::AsmParser(const Target &T, SourceMgr &_SM, MCContext &_Ctx,
                      MCStreamer &_Out, const MCAsmInfo &_MAI)
-  : Lexer(_MAI), Ctx(_Ctx), Out(_Out), SrcMgr(_SM), CurBuffer(0) {
+  : Lexer(_MAI), Ctx(_Ctx), Out(_Out), SrcMgr(_SM), TargetParser(0),
+    CurBuffer(0) {
   Lexer.setBuffer(SrcMgr.getMemoryBuffer(CurBuffer));
   
   // Debugging directives.




From gohman at apple.com  Thu Jul  1 16:29:13 2010
From: gohman at apple.com (Dan Gohman)
Date: Thu, 1 Jul 2010 14:29:13 -0700
Subject: [llvm-commits] [llvm] r107109 - in /llvm/trunk:
	include/llvm/Analysis/AliasAnalysis.h	include/llvm/Analysis/Passes.h
	lib/Analysis/AliasAnalysis.cpp	lib/Analysis/BasicAliasAnalysis.cpp
	test/Analysis/BasicAA/interprocedural.ll
In-Reply-To: <0EAA395C-1A7A-45D2-A6F9-F3B837A0F91C@apple.com>
References: <20100629005039.39B192A6C12C@llvm.org> <4C298317.7050002@mxc.ca>
	<5E31E70D-BC94-4545-BE28-F8927D72097F@apple.com>
	<0EAA395C-1A7A-45D2-A6F9-F3B837A0F91C@apple.com>
Message-ID: <92C98C7C-831E-4021-964E-B20289FB8BAB@apple.com>


On Jun 30, 2010, at 9:21 PM, Chris Lattner wrote:

> On Jun 29, 2010, at 11:09 AM, Dan Gohman wrote:
>>> Why is this an additional pass? Why not infer Interprocedural from SameParent()? The idempotents that basicaa was testing for should still hold true whenever SameParent() is true. It looks like the 'Interprocedural BasicAA' is basically a bugfix on BasicAA.
>> 
>> "noalias" is only meaningful from a single-procedure perspective.
>> For example:
>> 
>> @G = external global i32
>> define void @foo(i32* noalias %p) {
>> ...
>> }
>> ...
>> call void @foo(i32* @G)
>> 
>> If you're working exclusively within the body of @foo, then alias(@G, %p)
>> can be NoAlias. From an interprocedural perspective, it can be MustAlias.
>> Even with something like
>> 
>> define void @bar(double* noalias %a, double* noalias %b) {
>> 
>> it isn't trivial to say that %a doesn't alias %b because if it goes on to do
>> 
>> call void @bar(double* %b, double* %a)
>> 
>> then there is a sense in which %a could MustAlias %b, interprocedurally.
> 
> I don't buy this at all.  The current interface to AA (even for interprocedural clients) is context insensitive.  If you want a path or context-sensitive query interface, you'd need a substantially richer and more complex (aka slower) interface.  DSA provides this sort of interface for example.

You're right, I was mistaken about recursive functions; that's a class of
cases which are a lot more complicated and do bring in context sensitivity
concerns. I've removed these considerations in r107420.

However, beyond classic path and context scoping, there's another sense of
scope that an alias query can have, the scope of a noalias keyword. noalias
on an argument indicates that argument's relationship with other pointers
within that function, but it isn't meaningful when considering pointers
from an interprocedural perspective. An example of this is this is the first
example I gave above, with alias(@G, %p).

Dan




From dpatel at apple.com  Thu Jul  1 16:38:08 2010
From: dpatel at apple.com (Devang Patel)
Date: Thu, 01 Jul 2010 21:38:08 -0000
Subject: [llvm-commits] [llvm] r107430 -
	/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
Message-ID: <20100701213809.096232A6C12C@llvm.org>

Author: dpatel
Date: Thu Jul  1 16:38:08 2010
New Revision: 107430

URL: http://llvm.org/viewvc/llvm-project?rev=107430&view=rev
Log:
Do not require line number entry for undefined local variable.
This is a regression caused by r106792 and caught by gdb testsuite.

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=107430&r1=107429&r2=107430&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Thu Jul  1 16:38:08 2010
@@ -2690,10 +2690,12 @@
         DIVariable DV(MI->getOperand(MI->getNumOperands() - 1).getMetadata());
         if (!DV.Verify()) continue;
         // If DBG_VALUE is for a local variable then it needs a label.
-        if (DV.getTag() != dwarf::DW_TAG_arg_variable)
+        if (DV.getTag() != dwarf::DW_TAG_arg_variable 
+            && isDbgValueInUndefinedReg(MI) == false)
           InsnNeedsLabel.insert(MI);
         // DBG_VALUE for inlined functions argument needs a label.
-        else if (!DISubprogram(DV.getContext()).describes(MF->getFunction()))
+        else if (!DISubprogram(getDISubprogram(DV.getContext())).
+                 describes(MF->getFunction()))
           InsnNeedsLabel.insert(MI);
         // DBG_VALUE indicating argument location change needs a label.
         else if (isDbgValueInUndefinedReg(MI) == false && !ProcessedArgs.insert(DV))




From ggreif at gmail.com  Thu Jul  1 16:46:41 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Thu, 01 Jul 2010 21:46:41 -0000
Subject: [llvm-commits] [llvm] r107432 -
	/llvm/trunk/include/llvm/Instructions.h
Message-ID: <20100701214641.BF4082A6C12C@llvm.org>

Author: ggreif
Date: Thu Jul  1 16:46:41 2010
New Revision: 107432

URL: http://llvm.org/viewvc/llvm-project?rev=107432&view=rev
Log:
evil hack to coerce external users (projects)
to update their code to high-level interfaces

If you get compile errors in your project
please update your code according to the
comments.

This is a re-commit of r107396 which causes
compile errors for the indicated usage patterns
instead of link errors (which are less easy to
fix because of missing source location).

If you get compile errors please perform
following functionally equivalent transformations:
  - getOperand(0)  --->  getCalledValue()
  - setOperand(0, V)  --->  setCalledFunction(V)

This will make your code more future-proof
and avoid potentially hard-to-debug bugs.

please refer to this thread on llvm-dev:

<http://groups.google.com/group/llvm-dev/browse_thread/thread/64650cf343b28271>


Modified:
    llvm/trunk/include/llvm/Instructions.h

Modified: llvm/trunk/include/llvm/Instructions.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=107432&r1=107431&r2=107432&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Instructions.h (original)
+++ llvm/trunk/include/llvm/Instructions.h Thu Jul  1 16:46:41 2010
@@ -948,6 +948,17 @@
   Value *getArgOperand(unsigned i) const { return getOperand(i + ArgOffset); }
   void setArgOperand(unsigned i, Value *v) { setOperand(i + ArgOffset, v); }
 
+  /// Provide compile-time errors for accessing operand 0
+  /// @deprecated these will go away soon
+  /// @detail see below comments and update your code to high-level interfaces
+  ///    - getOperand(0)  --->  getCalledValue()
+  ///    - setOperand(0, V)  --->  setCalledFunction(V)
+  ///
+private:
+  void getOperand(void*); // NO IMPL ---> use getCalledValue (or possibly getCalledFunction) instead
+  void setOperand(void*, Value*); // NO IMPL ---> use setCalledFunction instead
+public:
+
   /// getCallingConv/setCallingConv - Get or set the calling convention of this
   /// function call.
   CallingConv::ID getCallingConv() const {




From isanbard at gmail.com  Thu Jul  1 16:55:59 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 01 Jul 2010 21:55:59 -0000
Subject: [llvm-commits] [llvm] r107433 - in /llvm/trunk: bindings/ada/llvm/
 docs/ include/llvm-c/ include/llvm/ lib/AsmParser/ lib/Bitcode/Reader/
 lib/Bitcode/Writer/ lib/CodeGen/AsmPrinter/ lib/Target/
 lib/Target/CppBackend/ lib/Target/XCore/AsmPrinter/ lib/Transforms/IPO/
 lib/VMCore/ test/CodeGen/ARM/ test/CodeGen/PowerPC/ test/CodeGen/X86/
 test/Feature/ tools/llvm-nm/
Message-ID: <20100701215600.43DD52A6C12C@llvm.org>

Author: void
Date: Thu Jul  1 16:55:59 2010
New Revision: 107433

URL: http://llvm.org/viewvc/llvm-project?rev=107433&view=rev
Log:
Implement the "linker_private_weak" linkage type. This will be used for
Objective-C metadata types which should be marked as "weak", but which the
linker will remove upon final linkage. However, this linkage isn't specific to
Objective-C.

For example, the "objc_msgSend_fixup_alloc" symbol is defined like this:

      .globl l_objc_msgSend_fixup_alloc
      .weak_definition l_objc_msgSend_fixup_alloc
      .section __DATA, __objc_msgrefs, coalesced
      .align 3
l_objc_msgSend_fixup_alloc:
       .quad   _objc_msgSend_fixup
       .quad   L_OBJC_METH_VAR_NAME_1

This is different from the "linker_private" linkage type, because it can't have
the metadata defined with ".weak_definition".

Currently only supported on Darwin platforms.

Added:
    llvm/trunk/test/Feature/linker_private_linkages.ll
Modified:
    llvm/trunk/bindings/ada/llvm/llvm.ads
    llvm/trunk/docs/LangRef.html
    llvm/trunk/include/llvm-c/Core.h
    llvm/trunk/include/llvm/GlobalValue.h
    llvm/trunk/lib/AsmParser/LLLexer.cpp
    llvm/trunk/lib/AsmParser/LLParser.cpp
    llvm/trunk/lib/AsmParser/LLToken.h
    llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp
    llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
    llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
    llvm/trunk/lib/Target/Mangler.cpp
    llvm/trunk/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp
    llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp
    llvm/trunk/lib/VMCore/AsmWriter.cpp
    llvm/trunk/lib/VMCore/Core.cpp
    llvm/trunk/test/CodeGen/ARM/2009-08-23-linkerprivate.ll
    llvm/trunk/test/CodeGen/PowerPC/2009-08-23-linkerprivate.ll
    llvm/trunk/test/CodeGen/X86/2009-08-23-linkerprivate.ll
    llvm/trunk/tools/llvm-nm/llvm-nm.cpp

Modified: llvm/trunk/bindings/ada/llvm/llvm.ads
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/bindings/ada/llvm/llvm.ads?rev=107433&r1=107432&r2=107433&view=diff
==============================================================================
--- llvm/trunk/bindings/ada/llvm/llvm.ads (original)
+++ llvm/trunk/bindings/ada/llvm/llvm.ads Thu Jul  1 16:55:59 2010
@@ -316,7 +316,8 @@
       LLVMExternalWeakLinkage,
       LLVMGhostLinkage,
       LLVMCommonLinkage,
-      LLVMLinkerPrivateLinkage);
+      LLVMLinkerPrivateLinkage,
+      LLVMLinkerPrivateWeakLinkage);
 
    for LLVMLinkage use
      (LLVMExternalLinkage            => 0,
@@ -333,7 +334,8 @@
       LLVMExternalWeakLinkage        => 11,
       LLVMGhostLinkage               => 12,
       LLVMCommonLinkage              => 13,
-      LLVMLinkerPrivateLinkage       => 14);
+      LLVMLinkerPrivateLinkage       => 14,
+      LLVMLinkerPrivateWeakLinkage   => 15);
 
    pragma Convention (C, LLVMLinkage);
 

Modified: llvm/trunk/docs/LangRef.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=107433&r1=107432&r2=107433&view=diff
==============================================================================
--- llvm/trunk/docs/LangRef.html (original)
+++ llvm/trunk/docs/LangRef.html Thu Jul  1 16:55:59 2010
@@ -24,6 +24,7 @@
         <ol>
           <li><a href="#linkage_private">'<tt>private</tt>' Linkage</a></li>
           <li><a href="#linkage_linker_private">'<tt>linker_private</tt>' Linkage</a></li>
+          <li><a href="#linkage_linker_private_weak">'<tt>linker_private_weak</tt>' Linkage</a></li>
           <li><a href="#linkage_internal">'<tt>internal</tt>' Linkage</a></li>
           <li><a href="#linkage_available_externally">'<tt>available_externally</tt>' Linkage</a></li>
           <li><a href="#linkage_linkonce">'<tt>linkonce</tt>' Linkage</a></li>
@@ -546,20 +547,24 @@
 
 <dl>
   <dt><tt><b><a name="linkage_private">private</a></b></tt></dt>
-  <dd>Global values with private linkage are only directly accessible by objects
-      in the current module.  In particular, linking code into a module with an
-      private global value may cause the private to be renamed as necessary to
-      avoid collisions.  Because the symbol is private to the module, all
-      references can be updated. This doesn't show up in any symbol table in the
-      object file.</dd>
+  <dd>Global values with "<tt>private</tt>" linkage are only directly accessible
+      by objects in the current module. In particular, linking code into a
+      module with an private global value may cause the private to be renamed as
+      necessary to avoid collisions.  Because the symbol is private to the
+      module, all references can be updated. This doesn't show up in any symbol
+      table in the object file.</dd>
 
   <dt><tt><b><a name="linkage_linker_private">linker_private</a></b></tt></dt>
-  <dd>Similar to private, but the symbol is passed through the assembler and
-      removed by the linker after evaluation.  Note that (unlike private
-      symbols) linker_private symbols are subject to coalescing by the linker:
-      weak symbols get merged and redefinitions are rejected.  However, unlike
-      normal strong symbols, they are removed by the linker from the final
-      linked image (executable or dynamic library).</dd>
+  <dd>Similar to <tt>private</tt>, but the symbol is passed through the
+      assembler and evaluated by the linker. Unlike normal strong symbols, they
+      are removed by the linker from the final linked image (executable or
+      dynamic library).</dd>
+
+  <dt><tt><b><a name="linkage_linker_private_weak">linker_private_weak</a></b></tt></dt>
+  <dd>Similar to "<tt>linker_private</tt>", but the symbol is weak. Note that
+      <tt>linker_private_weak</tt> symbols are subject to coalescing by the
+      linker. The symbols are removed by the linker from the final linked image
+      (executable or dynamic library).</dd>
 
   <dt><tt><b><a name="linkage_internal">internal</a></b></tt></dt>
   <dd>Similar to private, but the value shows as a local symbol
@@ -623,8 +628,8 @@
   <dt><tt><b><a name="linkage_weak_odr">weak_odr</a></b></tt></dt>
   <dd>Some languages allow differing globals to be merged, such as two functions
       with different semantics.  Other languages, such as <tt>C++</tt>, ensure
-      that only equivalent globals are ever merged (the "one definition rule" -
-      "ODR").  Such languages can use the <tt>linkonce_odr</tt>
+      that only equivalent globals are ever merged (the "one definition rule"
+      &mdash; "ODR").  Such languages can use the <tt>linkonce_odr</tt>
       and <tt>weak_odr</tt> linkage types to indicate that the global will only
       be merged with equivalent globals.  These linkage types are otherwise the
       same as their non-<tt>odr</tt> versions.</dd>

Modified: llvm/trunk/include/llvm-c/Core.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm-c/Core.h?rev=107433&r1=107432&r2=107433&view=diff
==============================================================================
--- llvm/trunk/include/llvm-c/Core.h (original)
+++ llvm/trunk/include/llvm-c/Core.h Thu Jul  1 16:55:59 2010
@@ -226,7 +226,8 @@
   LLVMExternalWeakLinkage,/**< ExternalWeak linkage description */
   LLVMGhostLinkage,       /**< Obsolete */
   LLVMCommonLinkage,      /**< Tentative definitions */
-  LLVMLinkerPrivateLinkage /**< Like Private, but linker removes. */
+  LLVMLinkerPrivateLinkage, /**< Like Private, but linker removes. */
+  LLVMLinkerPrivateWeakLinkage /**< Like LinkerPrivate, but is weak. */
 } LLVMLinkage;
 
 typedef enum {

Modified: llvm/trunk/include/llvm/GlobalValue.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/GlobalValue.h?rev=107433&r1=107432&r2=107433&view=diff
==============================================================================
--- llvm/trunk/include/llvm/GlobalValue.h (original)
+++ llvm/trunk/include/llvm/GlobalValue.h Thu Jul  1 16:55:59 2010
@@ -40,6 +40,7 @@
     InternalLinkage,    ///< Rename collisions when linking (static functions).
     PrivateLinkage,     ///< Like Internal, but omit from symbol table.
     LinkerPrivateLinkage, ///< Like Private, but linker removes.
+    LinkerPrivateWeakLinkage, ///< Like LinkerPrivate, but weak.
     DLLImportLinkage,   ///< Function to be imported from DLL
     DLLExportLinkage,   ///< Function to be accessible from DLL.
     ExternalWeakLinkage,///< ExternalWeak linkage description.
@@ -132,11 +133,14 @@
     return Linkage == PrivateLinkage;
   }
   static bool isLinkerPrivateLinkage(LinkageTypes Linkage) {
-    return Linkage==LinkerPrivateLinkage;
+    return Linkage == LinkerPrivateLinkage;
+  }
+  static bool isLinkerPrivateWeakLinkage(LinkageTypes Linkage) {
+    return Linkage == LinkerPrivateWeakLinkage;
   }
   static bool isLocalLinkage(LinkageTypes Linkage) {
     return isInternalLinkage(Linkage) || isPrivateLinkage(Linkage) ||
-      isLinkerPrivateLinkage(Linkage);
+      isLinkerPrivateLinkage(Linkage) || isLinkerPrivateWeakLinkage(Linkage);
   }
   static bool isDLLImportLinkage(LinkageTypes Linkage) {
     return Linkage == DLLImportLinkage;
@@ -158,7 +162,8 @@
     return (Linkage == WeakAnyLinkage ||
             Linkage == LinkOnceAnyLinkage ||
             Linkage == CommonLinkage ||
-            Linkage == ExternalWeakLinkage);
+            Linkage == ExternalWeakLinkage ||
+            Linkage == LinkerPrivateWeakLinkage);
   }
 
   /// isWeakForLinker - Whether the definition of this global may be replaced at
@@ -170,7 +175,8 @@
             Linkage == LinkOnceAnyLinkage ||
             Linkage == LinkOnceODRLinkage ||
             Linkage == CommonLinkage ||
-            Linkage == ExternalWeakLinkage);
+            Linkage == ExternalWeakLinkage ||
+            Linkage == LinkerPrivateWeakLinkage);
   }
 
   bool hasExternalLinkage() const { return isExternalLinkage(Linkage); }
@@ -187,6 +193,9 @@
   bool hasInternalLinkage() const { return isInternalLinkage(Linkage); }
   bool hasPrivateLinkage() const { return isPrivateLinkage(Linkage); }
   bool hasLinkerPrivateLinkage() const { return isLinkerPrivateLinkage(Linkage); }
+  bool hasLinkerPrivateWeakLinkage() const {
+    return isLinkerPrivateWeakLinkage(Linkage);
+  }
   bool hasLocalLinkage() const { return isLocalLinkage(Linkage); }
   bool hasDLLImportLinkage() const { return isDLLImportLinkage(Linkage); }
   bool hasDLLExportLinkage() const { return isDLLExportLinkage(Linkage); }

Modified: llvm/trunk/lib/AsmParser/LLLexer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLLexer.cpp?rev=107433&r1=107432&r2=107433&view=diff
==============================================================================
--- llvm/trunk/lib/AsmParser/LLLexer.cpp (original)
+++ llvm/trunk/lib/AsmParser/LLLexer.cpp Thu Jul  1 16:55:59 2010
@@ -492,6 +492,7 @@
 
   KEYWORD(private);
   KEYWORD(linker_private);
+  KEYWORD(linker_private_weak);
   KEYWORD(internal);
   KEYWORD(available_externally);
   KEYWORD(linkonce);

Modified: llvm/trunk/lib/AsmParser/LLParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=107433&r1=107432&r2=107433&view=diff
==============================================================================
--- llvm/trunk/lib/AsmParser/LLParser.cpp (original)
+++ llvm/trunk/lib/AsmParser/LLParser.cpp Thu Jul  1 16:55:59 2010
@@ -196,19 +196,20 @@
     // optional leading prefixes, the production is:
     // GlobalVar ::= OptionalLinkage OptionalVisibility OptionalThreadLocal
     //               OptionalAddrSpace ('constant'|'global') ...
-    case lltok::kw_private :       // OptionalLinkage
-    case lltok::kw_linker_private: // OptionalLinkage
-    case lltok::kw_internal:       // OptionalLinkage
-    case lltok::kw_weak:           // OptionalLinkage
-    case lltok::kw_weak_odr:       // OptionalLinkage
-    case lltok::kw_linkonce:       // OptionalLinkage
-    case lltok::kw_linkonce_odr:   // OptionalLinkage
-    case lltok::kw_appending:      // OptionalLinkage
-    case lltok::kw_dllexport:      // OptionalLinkage
-    case lltok::kw_common:         // OptionalLinkage
-    case lltok::kw_dllimport:      // OptionalLinkage
-    case lltok::kw_extern_weak:    // OptionalLinkage
-    case lltok::kw_external: {     // OptionalLinkage
+    case lltok::kw_private:             // OptionalLinkage
+    case lltok::kw_linker_private:      // OptionalLinkage
+    case lltok::kw_linker_private_weak: // OptionalLinkage
+    case lltok::kw_internal:            // OptionalLinkage
+    case lltok::kw_weak:                // OptionalLinkage
+    case lltok::kw_weak_odr:            // OptionalLinkage
+    case lltok::kw_linkonce:            // OptionalLinkage
+    case lltok::kw_linkonce_odr:        // OptionalLinkage
+    case lltok::kw_appending:           // OptionalLinkage
+    case lltok::kw_dllexport:           // OptionalLinkage
+    case lltok::kw_common:              // OptionalLinkage
+    case lltok::kw_dllimport:           // OptionalLinkage
+    case lltok::kw_extern_weak:         // OptionalLinkage
+    case lltok::kw_external: {          // OptionalLinkage
       unsigned Linkage, Visibility;
       if (ParseOptionalLinkage(Linkage) ||
           ParseOptionalVisibility(Visibility) ||
@@ -629,7 +630,8 @@
       Linkage != GlobalValue::WeakODRLinkage &&
       Linkage != GlobalValue::InternalLinkage &&
       Linkage != GlobalValue::PrivateLinkage &&
-      Linkage != GlobalValue::LinkerPrivateLinkage)
+      Linkage != GlobalValue::LinkerPrivateLinkage &&
+      Linkage != GlobalValue::LinkerPrivateWeakLinkage)
     return Error(LinkageLoc, "invalid linkage type for alias");
 
   Constant *Aliasee;
@@ -1013,11 +1015,13 @@
 ///   ::= /*empty*/
 ///   ::= 'private'
 ///   ::= 'linker_private'
+///   ::= 'linker_private_weak'
 ///   ::= 'internal'
 ///   ::= 'weak'
 ///   ::= 'weak_odr'
 ///   ::= 'linkonce'
 ///   ::= 'linkonce_odr'
+///   ::= 'available_externally'
 ///   ::= 'appending'
 ///   ::= 'dllexport'
 ///   ::= 'common'
@@ -1030,6 +1034,9 @@
   default:                       Res=GlobalValue::ExternalLinkage; return false;
   case lltok::kw_private:        Res = GlobalValue::PrivateLinkage;       break;
   case lltok::kw_linker_private: Res = GlobalValue::LinkerPrivateLinkage; break;
+  case lltok::kw_linker_private_weak:
+    Res = GlobalValue::LinkerPrivateWeakLinkage;
+    break;
   case lltok::kw_internal:       Res = GlobalValue::InternalLinkage;      break;
   case lltok::kw_weak:           Res = GlobalValue::WeakAnyLinkage;       break;
   case lltok::kw_weak_odr:       Res = GlobalValue::WeakODRLinkage;       break;
@@ -2704,6 +2711,7 @@
     break;
   case GlobalValue::PrivateLinkage:
   case GlobalValue::LinkerPrivateLinkage:
+  case GlobalValue::LinkerPrivateWeakLinkage:
   case GlobalValue::InternalLinkage:
   case GlobalValue::AvailableExternallyLinkage:
   case GlobalValue::LinkOnceAnyLinkage:

Modified: llvm/trunk/lib/AsmParser/LLToken.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLToken.h?rev=107433&r1=107432&r2=107433&view=diff
==============================================================================
--- llvm/trunk/lib/AsmParser/LLToken.h (original)
+++ llvm/trunk/lib/AsmParser/LLToken.h Thu Jul  1 16:55:59 2010
@@ -37,9 +37,9 @@
     kw_declare, kw_define,
     kw_global,  kw_constant,
 
-    kw_private, kw_linker_private, kw_internal, kw_linkonce, kw_linkonce_odr,
-    kw_weak, kw_weak_odr, kw_appending, kw_dllimport, kw_dllexport, kw_common,
-    kw_available_externally,
+    kw_private, kw_linker_private, kw_linker_private_weak, kw_internal,
+    kw_linkonce, kw_linkonce_odr, kw_weak, kw_weak_odr, kw_appending,
+    kw_dllimport, kw_dllexport, kw_common, kw_available_externally,
     kw_default, kw_hidden, kw_protected,
     kw_extern_weak,
     kw_external, kw_thread_local,

Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp?rev=107433&r1=107432&r2=107433&view=diff
==============================================================================
--- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp (original)
+++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp Thu Jul  1 16:55:59 2010
@@ -75,6 +75,7 @@
   case 11: return GlobalValue::LinkOnceODRLinkage;
   case 12: return GlobalValue::AvailableExternallyLinkage;
   case 13: return GlobalValue::LinkerPrivateLinkage;
+  case 14: return GlobalValue::LinkerPrivateWeakLinkage;
   }
 }
 

Modified: llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp?rev=107433&r1=107432&r2=107433&view=diff
==============================================================================
--- llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp (original)
+++ llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp Thu Jul  1 16:55:59 2010
@@ -313,6 +313,7 @@
   case GlobalValue::LinkOnceODRLinkage:         return 11;
   case GlobalValue::AvailableExternallyLinkage: return 12;
   case GlobalValue::LinkerPrivateLinkage:       return 13;
+  case GlobalValue::LinkerPrivateWeakLinkage:   return 14;
   }
 }
 

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=107433&r1=107432&r2=107433&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Thu Jul  1 16:55:59 2010
@@ -200,6 +200,7 @@
   case GlobalValue::WeakAnyLinkage:
   case GlobalValue::WeakODRLinkage:
   case GlobalValue::LinkerPrivateLinkage:
+  case GlobalValue::LinkerPrivateWeakLinkage:
     if (MAI->getWeakDefDirective() != 0) {
       // .globl _foo
       OutStreamer.EmitSymbolAttribute(GVSym, MCSA_Global);

Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp?rev=107433&r1=107432&r2=107433&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp (original)
+++ llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Thu Jul  1 16:55:59 2010
@@ -286,6 +286,8 @@
     Out << "GlobalValue::PrivateLinkage"; break;
   case GlobalValue::LinkerPrivateLinkage:
     Out << "GlobalValue::LinkerPrivateLinkage"; break;
+  case GlobalValue::LinkerPrivateWeakLinkage:
+    Out << "GlobalValue::LinkerPrivateWeakLinkage"; break;
   case GlobalValue::AvailableExternallyLinkage:
     Out << "GlobalValue::AvailableExternallyLinkage "; break;
   case GlobalValue::LinkOnceAnyLinkage:

Modified: llvm/trunk/lib/Target/Mangler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mangler.cpp?rev=107433&r1=107432&r2=107433&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mangler.cpp (original)
+++ llvm/trunk/lib/Target/Mangler.cpp Thu Jul  1 16:55:59 2010
@@ -180,7 +180,7 @@
   ManglerPrefixTy PrefixTy = Mangler::Default;
   if (GV->hasPrivateLinkage() || isImplicitlyPrivate)
     PrefixTy = Mangler::Private;
-  else if (GV->hasLinkerPrivateLinkage())
+  else if (GV->hasLinkerPrivateLinkage() || GV->hasLinkerPrivateWeakLinkage())
     PrefixTy = Mangler::LinkerPrivate;
   
   // If this global has a name, handle it simply.

Modified: llvm/trunk/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp?rev=107433&r1=107432&r2=107433&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp Thu Jul  1 16:55:59 2010
@@ -138,7 +138,6 @@
     // FALL THROUGH
   case GlobalValue::InternalLinkage:
   case GlobalValue::PrivateLinkage:
-  case GlobalValue::LinkerPrivateLinkage:
     break;
   case GlobalValue::DLLImportLinkage:
     llvm_unreachable("DLLImport linkage is not supported by this target!");

Modified: llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp?rev=107433&r1=107432&r2=107433&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp (original)
+++ llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp Thu Jul  1 16:55:59 2010
@@ -535,6 +535,7 @@
   case GlobalValue::WeakAnyLinkage:
   case GlobalValue::WeakODRLinkage:
   case GlobalValue::ExternalWeakLinkage:
+  case GlobalValue::LinkerPrivateWeakLinkage:
     return ExternalWeak;
 
   case GlobalValue::ExternalLinkage:

Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=107433&r1=107432&r2=107433&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/AsmWriter.cpp (original)
+++ llvm/trunk/lib/VMCore/AsmWriter.cpp Thu Jul  1 16:55:59 2010
@@ -1419,6 +1419,9 @@
   case GlobalValue::ExternalLinkage: break;
   case GlobalValue::PrivateLinkage:       Out << "private ";        break;
   case GlobalValue::LinkerPrivateLinkage: Out << "linker_private "; break;
+  case GlobalValue::LinkerPrivateWeakLinkage:
+    Out << "linker_private_weak ";
+    break;
   case GlobalValue::InternalLinkage:      Out << "internal ";       break;
   case GlobalValue::LinkOnceAnyLinkage:   Out << "linkonce ";       break;
   case GlobalValue::LinkOnceODRLinkage:   Out << "linkonce_odr ";   break;

Modified: llvm/trunk/lib/VMCore/Core.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Core.cpp?rev=107433&r1=107432&r2=107433&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Core.cpp (original)
+++ llvm/trunk/lib/VMCore/Core.cpp Thu Jul  1 16:55:59 2010
@@ -1058,6 +1058,8 @@
     return LLVMPrivateLinkage;
   case GlobalValue::LinkerPrivateLinkage:
     return LLVMLinkerPrivateLinkage;
+  case GlobalValue::LinkerPrivateWeakLinkage:
+    return LLVMLinkerPrivateWeakLinkage;
   case GlobalValue::DLLImportLinkage:
     return LLVMDLLImportLinkage;
   case GlobalValue::DLLExportLinkage:
@@ -1108,6 +1110,9 @@
   case LLVMLinkerPrivateLinkage:
     GV->setLinkage(GlobalValue::LinkerPrivateLinkage);
     break;
+  case LLVMLinkerPrivateWeakLinkage:
+    GV->setLinkage(GlobalValue::LinkerPrivateWeakLinkage);
+    break;
   case LLVMDLLImportLinkage:
     GV->setLinkage(GlobalValue::DLLImportLinkage);
     break;

Modified: llvm/trunk/test/CodeGen/ARM/2009-08-23-linkerprivate.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-08-23-linkerprivate.ll?rev=107433&r1=107432&r2=107433&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2009-08-23-linkerprivate.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2009-08-23-linkerprivate.ll Thu Jul  1 16:55:59 2010
@@ -2,7 +2,7 @@
 
 ; ModuleID = '/Volumes/MacOS9/tests/WebKit/JavaScriptCore/profiler/ProfilerServer.mm'
 
-@"\01l_objc_msgSend_fixup_alloc" = linker_private hidden global i32 0, section "__DATA, __objc_msgrefs, coalesced", align 16		; <i32*> [#uses=0]
+@"\01l_objc_msgSend_fixup_alloc" = linker_private_weak hidden global i32 0, section "__DATA, __objc_msgrefs, coalesced", align 16
 
 ; CHECK: .globl l_objc_msgSend_fixup_alloc
 ; CHECK: .weak_definition l_objc_msgSend_fixup_alloc

Modified: llvm/trunk/test/CodeGen/PowerPC/2009-08-23-linkerprivate.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2009-08-23-linkerprivate.ll?rev=107433&r1=107432&r2=107433&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/2009-08-23-linkerprivate.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/2009-08-23-linkerprivate.ll Thu Jul  1 16:55:59 2010
@@ -2,7 +2,7 @@
 
 ; ModuleID = '/Volumes/MacOS9/tests/WebKit/JavaScriptCore/profiler/ProfilerServer.mm'
 
-@"\01l_objc_msgSend_fixup_alloc" = linker_private hidden global i32 0, section "__DATA, __objc_msgrefs, coalesced", align 16		; <i32*> [#uses=0]
+@"\01l_objc_msgSend_fixup_alloc" = linker_private_weak hidden global i32 0, section "__DATA, __objc_msgrefs, coalesced", align 16
 
 ; CHECK: .globl l_objc_msgSend_fixup_alloc
 ; CHECK: .weak_definition l_objc_msgSend_fixup_alloc

Modified: llvm/trunk/test/CodeGen/X86/2009-08-23-linkerprivate.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-08-23-linkerprivate.ll?rev=107433&r1=107432&r2=107433&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2009-08-23-linkerprivate.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2009-08-23-linkerprivate.ll Thu Jul  1 16:55:59 2010
@@ -2,7 +2,7 @@
 
 ; ModuleID = '/Volumes/MacOS9/tests/WebKit/JavaScriptCore/profiler/ProfilerServer.mm'
 
-@"\01l_objc_msgSend_fixup_alloc" = linker_private hidden global i32 0, section "__DATA, __objc_msgrefs, coalesced", align 16		; <i32*> [#uses=0]
+@"\01l_objc_msgSend_fixup_alloc" = linker_private_weak hidden global i32 0, section "__DATA, __objc_msgrefs, coalesced", align 16
 
 ; CHECK: .globl l_objc_msgSend_fixup_alloc
 ; CHECK: .weak_definition l_objc_msgSend_fixup_alloc

Added: llvm/trunk/test/Feature/linker_private_linkages.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Feature/linker_private_linkages.ll?rev=107433&view=auto
==============================================================================
--- llvm/trunk/test/Feature/linker_private_linkages.ll (added)
+++ llvm/trunk/test/Feature/linker_private_linkages.ll Thu Jul  1 16:55:59 2010
@@ -0,0 +1,6 @@
+; RUN: llvm-as < %s | llvm-dis > %t1.ll
+; RUN: llvm-as %t1.ll -o - | llvm-dis > %t2.ll
+; RUN: diff %t1.ll %t2.ll
+
+ at foo = linker_private hidden global i32 0
+ at bar = linker_private_weak hidden global i32 0

Modified: llvm/trunk/tools/llvm-nm/llvm-nm.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-nm/llvm-nm.cpp?rev=107433&r1=107432&r2=107433&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-nm/llvm-nm.cpp (original)
+++ llvm/trunk/tools/llvm-nm/llvm-nm.cpp Thu Jul  1 16:55:59 2010
@@ -89,7 +89,8 @@
 static void DumpSymbolNameForGlobalValue(GlobalValue &GV) {
   // Private linkage and available_externally linkage don't exist in symtab.
   if (GV.hasPrivateLinkage() || GV.hasLinkerPrivateLinkage() ||
-      GV.hasAvailableExternallyLinkage()) return;
+      GV.hasLinkerPrivateWeakLinkage() || GV.hasAvailableExternallyLinkage())
+    return;
   
   const std::string SymbolAddrStr = "        "; // Not used yet...
   char TypeChar = TypeCharForSymbol(GV);




From matt at console-pimps.org  Thu Jul  1 17:02:41 2010
From: matt at console-pimps.org (Matt Fleming)
Date: Thu, 01 Jul 2010 23:02:41 +0100
Subject: [llvm-commits] [PATCH] Add some more ELF OSABI values.
In-Reply-To: <77331FDA-6D14-4962-A88F-84E80040563B@apple.com>
References: <8806a9216ebe6844ecf8f510b1187ebc4d6e8345.1277924817.git.matt@console-pimps.org>
	<77331FDA-6D14-4962-A88F-84E80040563B@apple.com>
Message-ID: <87wrtezwqm.fsf@linux-g6p1.site>

On Wed, 30 Jun 2010 15:41:03 -0700, Bill Wendling <wendling at apple.com> wrote:
> Seems okay. Though why not change ELFOSABI_NONE to something that reflects what the comment says. Maybe ELFOSABI_SYSV or something?
> 
> -bw

I wanted to stick to the names defined in the System V ABI spec. The
ELFOSABI values specify any ABI/OS extensions to the Sys V ABI, so the
"NONE" part indicates that there is no extension to the vanilla Sys V
ABI. If possible I'd like to use the names from the spec to makes things
easier to lookup.


From matt at console-pimps.org  Thu Jul  1 17:04:27 2010
From: matt at console-pimps.org (Matt Fleming)
Date: Thu, 01 Jul 2010 23:04:27 +0100
Subject: [llvm-commits] [PATCH] add X86_64 relocation entries
In-Reply-To: <5E54E91E-1A43-4913-8046-CF63EC4342E0@apple.com>
References: <4dfdc3f12a1a3a254f22b03f8d26a382c3424391.1277925479.git.matt@console-pimps.org>
	<5E54E91E-1A43-4913-8046-CF63EC4342E0@apple.com>
Message-ID: <87tyoizwno.fsf@linux-g6p1.site>

On Wed, 30 Jun 2010 21:12:10 -0700, Chris Lattner <clattner at apple.com> wrote:
> 
> On Jun 30, 2010, at 12:22 PM, Matt Fleming wrote:
> 
> > From: Roman Divacky <rdivacky at pes.vlakno.cz>
> > 
> > Here's another patch that adds some ELF values, this one from Roman
> > Divacky. If no one yells I'll commit this later this week.
> 
> Looks ok to me, but please stay in 80 columns and punctuate your comments (end with ".").

Whoops, sorry. I should have picked up on that. I'll fix it up before I
commit.


From wendling at apple.com  Thu Jul  1 17:05:02 2010
From: wendling at apple.com (Bill Wendling)
Date: Thu, 1 Jul 2010 15:05:02 -0700
Subject: [llvm-commits] [PATCH] Add some more ELF OSABI values.
In-Reply-To: <87wrtezwqm.fsf@linux-g6p1.site>
References: <8806a9216ebe6844ecf8f510b1187ebc4d6e8345.1277924817.git.matt@console-pimps.org>
	<77331FDA-6D14-4962-A88F-84E80040563B@apple.com>
	<87wrtezwqm.fsf@linux-g6p1.site>
Message-ID: <27AB4005-F30B-4677-B726-9799A5D84292@apple.com>

On Jul 1, 2010, at 3:02 PM, Matt Fleming wrote:

> On Wed, 30 Jun 2010 15:41:03 -0700, Bill Wendling <wendling at apple.com> wrote:
>> Seems okay. Though why not change ELFOSABI_NONE to something that reflects what the comment says. Maybe ELFOSABI_SYSV or something?
>> 
>> -bw
> 
> I wanted to stick to the names defined in the System V ABI spec. The
> ELFOSABI values specify any ABI/OS extensions to the Sys V ABI, so the
> "NONE" part indicates that there is no extension to the vanilla Sys V
> ABI. If possible I'd like to use the names from the spec to makes things
> easier to lookup.

Okay.

-bw




From bob.wilson at apple.com  Thu Jul  1 17:26:26 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Thu, 01 Jul 2010 22:26:26 -0000
Subject: [llvm-commits] [llvm] r107435 - in /llvm/trunk:
 lib/Target/ARM/ARMISelLowering.cpp
 test/CodeGen/Thumb/2010-07-01-FuncAlign.ll
Message-ID: <20100701222626.3CD6F2A6C12C@llvm.org>

Author: bwilson
Date: Thu Jul  1 17:26:26 2010
New Revision: 107435

URL: http://llvm.org/viewvc/llvm-project?rev=107435&view=rev
Log:
ARM function alignments were off by a power of two.  svn 83242 changed
getFunctionAlignment and the corresponding use of that value in the ARM
asm printer, but now we're using the standard asm printer.  The result of
this was that function alignments were dropped completely for Thumb functions.
Radar 8143571.

Added:
    llvm/trunk/test/CodeGen/Thumb/2010-07-01-FuncAlign.ll
Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=107435&r1=107434&r2=107435&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Jul  1 17:26:26 2010
@@ -647,7 +647,7 @@
 
 /// getFunctionAlignment - Return the Log2 alignment of this function.
 unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
-  return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 0 : 1;
+  return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 1 : 2;
 }
 
 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {

Added: llvm/trunk/test/CodeGen/Thumb/2010-07-01-FuncAlign.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/2010-07-01-FuncAlign.ll?rev=107435&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb/2010-07-01-FuncAlign.ll (added)
+++ llvm/trunk/test/CodeGen/Thumb/2010-07-01-FuncAlign.ll Thu Jul  1 17:26:26 2010
@@ -0,0 +1,6 @@
+; RUN: llc < %s -mtriple=thumb-apple-darwin | FileCheck %s
+; Radar 8143571: Function alignments were off by a power of two.
+; CHECK: .align 1
+define void @test() {
+  ret void
+}




From bruno.cardoso at gmail.com  Thu Jul  1 17:33:18 2010
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Thu, 01 Jul 2010 22:33:18 -0000
Subject: [llvm-commits] [llvm] r107438 -
	/llvm/trunk/lib/Target/X86/X86InstrSSE.td
Message-ID: <20100701223318.B227C2A6C12C@llvm.org>

Author: bruno
Date: Thu Jul  1 17:33:18 2010
New Revision: 107438

URL: http://llvm.org/viewvc/llvm-project?rev=107438&view=rev
Log:
Shrink down SSE3 code by some multiclass refactoring - 1st part

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=107438&r1=107437&r2=107438&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Jul  1 17:33:18 2010
@@ -3359,9 +3359,10 @@
 def MWAIT   : I<0x01, MRM_C9, (outs), (ins), "mwait",
                 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
 
-/// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8.
-multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr,
-                              Intrinsic IntId64, Intrinsic IntId128> {
+/// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
+multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
+                            PatFrag mem_frag64, PatFrag mem_frag128,
+                            Intrinsic IntId64, Intrinsic IntId128> {
   def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
                    !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
                    [(set VR64:$dst, (IntId64 VR64:$src))]>;
@@ -3369,7 +3370,7 @@
   def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
                    !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
                    [(set VR64:$dst,
-                     (IntId64 (bitconvert (memopv8i8 addr:$src))))]>;
+                     (IntId64 (bitconvert (mem_frag64 addr:$src))))]>;
 
   def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
                     (ins VR128:$src),
@@ -3382,76 +3383,18 @@
                     !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
                     [(set VR128:$dst,
                       (IntId128
-                       (bitconvert (memopv16i8 addr:$src))))]>, OpSize;
+                       (bitconvert (mem_frag128 addr:$src))))]>, OpSize;
 }
 
-/// SS3I_unop_rm_int_16 - Simple SSSE3 unary operator whose type is v*i16.
-multiclass SS3I_unop_rm_int_16<bits<8> opc, string OpcodeStr,
-                               Intrinsic IntId64, Intrinsic IntId128> {
-  def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
-                   (ins VR64:$src),
-                   !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
-                   [(set VR64:$dst, (IntId64 VR64:$src))]>;
-
-  def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
-                   (ins i64mem:$src),
-                   !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
-                   [(set VR64:$dst,
-                     (IntId64
-                      (bitconvert (memopv4i16 addr:$src))))]>;
-
-  def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
-                    (ins VR128:$src),
-                    !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
-                    [(set VR128:$dst, (IntId128 VR128:$src))]>,
-                    OpSize;
-
-  def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
-                    (ins i128mem:$src),
-                    !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
-                    [(set VR128:$dst,
-                      (IntId128
-                       (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
-}
-
-/// SS3I_unop_rm_int_32 - Simple SSSE3 unary operator whose type is v*i32.
-multiclass SS3I_unop_rm_int_32<bits<8> opc, string OpcodeStr,
-                               Intrinsic IntId64, Intrinsic IntId128> {
-  def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
-                   (ins VR64:$src),
-                   !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
-                   [(set VR64:$dst, (IntId64 VR64:$src))]>;
-
-  def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
-                   (ins i64mem:$src),
-                   !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
-                   [(set VR64:$dst,
-                     (IntId64
-                      (bitconvert (memopv2i32 addr:$src))))]>;
-
-  def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
-                    (ins VR128:$src),
-                    !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
-                    [(set VR128:$dst, (IntId128 VR128:$src))]>,
-                    OpSize;
-
-  def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
-                    (ins i128mem:$src),
-                    !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
-                    [(set VR128:$dst,
-                      (IntId128
-                       (bitconvert (memopv4i32 addr:$src))))]>, OpSize;
-}
-
-defm PABSB       : SS3I_unop_rm_int_8 <0x1C, "pabsb",
-                                       int_x86_ssse3_pabs_b,
-                                       int_x86_ssse3_pabs_b_128>;
-defm PABSW       : SS3I_unop_rm_int_16<0x1D, "pabsw",
-                                       int_x86_ssse3_pabs_w,
-                                       int_x86_ssse3_pabs_w_128>;
-defm PABSD       : SS3I_unop_rm_int_32<0x1E, "pabsd",
-                                       int_x86_ssse3_pabs_d,
-                                       int_x86_ssse3_pabs_d_128>;
+defm PABSB       : SS3I_unop_rm_int<0x1C, "pabsb", memopv8i8, memopv16i8,
+                                    int_x86_ssse3_pabs_b,
+                                    int_x86_ssse3_pabs_b_128>;
+defm PABSW       : SS3I_unop_rm_int<0x1D, "pabsw", memopv4i16, memopv8i16,
+                                    int_x86_ssse3_pabs_w,
+                                    int_x86_ssse3_pabs_w_128>;
+defm PABSD       : SS3I_unop_rm_int<0x1E, "pabsd", memopv2i32, memopv4i32,
+                                    int_x86_ssse3_pabs_d,
+                                    int_x86_ssse3_pabs_d_128>;
 
 /// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8.
 let Constraints = "$src1 = $dst" in {




From isanbard at gmail.com  Thu Jul  1 17:37:32 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 01 Jul 2010 22:37:32 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r107439 - in /llvm-gcc-4.2/trunk/gcc:
 llvm-backend.cpp tree.h varasm.c
Message-ID: <20100701223732.320262A6C12C@llvm.org>

Author: void
Date: Thu Jul  1 17:37:31 2010
New Revision: 107439

URL: http://llvm.org/viewvc/llvm-project?rev=107439&view=rev
Log:
Add the "DECL_LLVM_LINKER_PRIVATE_WEAK" macro. This uses the new
"linker_private_weak" linkage type if the variable is "linker_private" (begins
with an 'l' (ell)) but is also weak.

Modified:
    llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
    llvm-gcc-4.2/trunk/gcc/tree.h
    llvm-gcc-4.2/trunk/gcc/varasm.c

Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=107439&r1=107438&r2=107439&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Thu Jul  1 17:37:31 2010
@@ -1165,6 +1165,8 @@
     Linkage = GlobalValue::PrivateLinkage;
   else if (DECL_LLVM_LINKER_PRIVATE(decl))
     Linkage = GlobalValue::LinkerPrivateLinkage;
+  else if (DECL_LLVM_LINKER_PRIVATE_WEAK(decl))
+    Linkage = GlobalValue::LinkerPrivateWeakLinkage;
   else if (DECL_WEAK(decl))
     // The user may have explicitly asked for weak linkage - ignore flag_odr.
     Linkage = GlobalValue::WeakAnyLinkage;
@@ -1431,6 +1433,9 @@
   } else if (CODE_CONTAINS_STRUCT (TREE_CODE (decl), TS_DECL_WITH_VIS)
              && DECL_LLVM_LINKER_PRIVATE(decl)) {
     Linkage = GlobalValue::LinkerPrivateLinkage;
+  } else if (CODE_CONTAINS_STRUCT (TREE_CODE (decl), TS_DECL_WITH_VIS)
+             && DECL_LLVM_LINKER_PRIVATE_WEAK(decl)) {
+    Linkage = GlobalValue::LinkerPrivateWeakLinkage;
   } else if (!TREE_PUBLIC(decl)) {
     Linkage = GlobalValue::InternalLinkage;
   } else if (DECL_WEAK(decl)) {
@@ -1499,7 +1504,8 @@
 
     // Handle used decls
     if (DECL_PRESERVE_P (decl)) {
-      if (DECL_LLVM_LINKER_PRIVATE (decl))
+      if (DECL_LLVM_LINKER_PRIVATE (decl) ||
+          DECL_LLVM_LINKER_PRIVATE_WEAK (decl))
         AttributeCompilerUsedGlobals.insert(GV);
       else
         AttributeUsedGlobals.insert(GV);

Modified: llvm-gcc-4.2/trunk/gcc/tree.h
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/tree.h?rev=107439&r1=107438&r2=107439&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/tree.h (original)
+++ llvm-gcc-4.2/trunk/gcc/tree.h Thu Jul  1 17:37:31 2010
@@ -2937,6 +2937,9 @@
   (DECL_WITH_VIS_CHECK (NODE)->decl_with_vis.llvm_private_flag)
 #define DECL_LLVM_LINKER_PRIVATE(NODE) \
   (DECL_WITH_VIS_CHECK (NODE)->decl_with_vis.llvm_linker_private_flag)
+/* LLVM LOCAL - linker_private_weak <rdar://problem/7907014> */
+#define DECL_LLVM_LINKER_PRIVATE_WEAK(NODE) \
+  (DECL_WITH_VIS_CHECK (NODE)->decl_with_vis.llvm_linker_private_weak_flag)
 #endif
 /* LLVM LOCAL end */
 
@@ -3080,6 +3083,8 @@
  /* LLVM LOCAL begin */
  unsigned llvm_private_flag : 1;
  unsigned llvm_linker_private_flag : 1;
+ /* LLVM LOCAL - linker_private_weak <rdar://problem/7907014> */
+ unsigned llvm_linker_private_weak_flag : 1;
  /* LLVM LOCAL end */
 
  ENUM_BITFIELD(symbol_visibility) visibility : 2;

Modified: llvm-gcc-4.2/trunk/gcc/varasm.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/varasm.c?rev=107439&r1=107438&r2=107439&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/varasm.c (original)
+++ llvm-gcc-4.2/trunk/gcc/varasm.c Thu Jul  1 17:37:31 2010
@@ -787,7 +787,8 @@
 
       if (has_objc_prefix) {
         DECL_LLVM_PRIVATE (decl) = (name[0] == 'L');
-        DECL_LLVM_LINKER_PRIVATE (decl) = (name[0] == 'l');
+        DECL_LLVM_LINKER_PRIVATE (decl) = (name[0] == 'l' && !DECL_WEAK (decl));
+        DECL_LLVM_LINKER_PRIVATE_WEAK(decl)=(name[0] == 'l' && DECL_WEAK(decl));
 
         /* Remove the "[Ll]_" prefix. The LLVM assembly printer is now
            intelligent enough to add the appropriate prefix to the name.  */




From isanbard at gmail.com  Thu Jul  1 17:38:24 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 01 Jul 2010 22:38:24 -0000
Subject: [llvm-commits] [llvm] r107440 -
	/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
Message-ID: <20100701223824.BC12F2A6C12C@llvm.org>

Author: void
Date: Thu Jul  1 17:38:24 2010
New Revision: 107440

URL: http://llvm.org/viewvc/llvm-project?rev=107440&view=rev
Log:
Make the "linker_private" linkage type emit a non-weak symbol to the file. It
will still be stripped by the linker when it generates the final image.

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=107440&r1=107439&r2=107440&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Thu Jul  1 17:38:24 2010
@@ -199,7 +199,6 @@
   case GlobalValue::LinkOnceODRLinkage:
   case GlobalValue::WeakAnyLinkage:
   case GlobalValue::WeakODRLinkage:
-  case GlobalValue::LinkerPrivateLinkage:
   case GlobalValue::LinkerPrivateWeakLinkage:
     if (MAI->getWeakDefDirective() != 0) {
       // .globl _foo
@@ -226,6 +225,7 @@
     break;
   case GlobalValue::PrivateLinkage:
   case GlobalValue::InternalLinkage:
+  case GlobalValue::LinkerPrivateLinkage:
     break;
   default:
     llvm_unreachable("Unknown linkage type!");




From isanbard at gmail.com  Thu Jul  1 17:45:06 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 01 Jul 2010 22:45:06 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r107443 -
	/llvm-gcc-4.2/trunk/gcc/tree.h
Message-ID: <20100701224506.986B72A6C12C@llvm.org>

Author: void
Date: Thu Jul  1 17:45:06 2010
New Revision: 107443

URL: http://llvm.org/viewvc/llvm-project?rev=107443&view=rev
Log:
Update bit count.

Modified:
    llvm-gcc-4.2/trunk/gcc/tree.h

Modified: llvm-gcc-4.2/trunk/gcc/tree.h
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/tree.h?rev=107443&r1=107442&r2=107443&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/tree.h (original)
+++ llvm-gcc-4.2/trunk/gcc/tree.h Thu Jul  1 17:45:06 2010
@@ -3107,7 +3107,7 @@
  unsigned block_synthesized_function : 1;
  /* APPLE LOCAL radar 5847976 */
  unsigned block_weak : 1;
- /* 3 unused bits (llvm). */
+ /* 2 unused bits (llvm). */
  /* APPLE LOCAL end radar 5932809 - copyable byref blocks */
  /* APPLE LOCAL end radar 5732232 - blocks */
 };




From dalej at apple.com  Thu Jul  1 17:57:11 2010
From: dalej at apple.com (Dale Johannesen)
Date: Thu, 01 Jul 2010 22:57:11 -0000
Subject: [llvm-commits] [llvm] r107446 -
 /llvm/trunk/test/Transforms/StripSymbols/2010-07-01-DeadDbgInfo.ll
Message-ID: <20100701225711.369712A6C12C@llvm.org>

Author: johannes
Date: Thu Jul  1 17:57:11 2010
New Revision: 107446

URL: http://llvm.org/viewvc/llvm-project?rev=107446&view=rev
Log:
Prevent test from hanging waiting for input.


Modified:
    llvm/trunk/test/Transforms/StripSymbols/2010-07-01-DeadDbgInfo.ll

Modified: llvm/trunk/test/Transforms/StripSymbols/2010-07-01-DeadDbgInfo.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/StripSymbols/2010-07-01-DeadDbgInfo.ll?rev=107446&r1=107445&r2=107446&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/StripSymbols/2010-07-01-DeadDbgInfo.ll (original)
+++ llvm/trunk/test/Transforms/StripSymbols/2010-07-01-DeadDbgInfo.ll Thu Jul  1 17:57:11 2010
@@ -1,4 +1,4 @@
-; RUN: opt -strip-dead-debug-info | llvm-dis -o %t.ll
+; RUN: opt -strip-dead-debug-info < %s | llvm-dis -o %t.ll
 ; RUN: grep -v bar %t.ll
 ; RUN: grep -v abcd %t.ll
 




From bruno.cardoso at gmail.com  Thu Jul  1 18:10:49 2010
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Thu, 01 Jul 2010 23:10:49 -0000
Subject: [llvm-commits] [llvm] r107448 -
	/llvm/trunk/lib/Target/X86/X86InstrSSE.td
Message-ID: <20100701231049.E3F132A6C12C@llvm.org>

Author: bruno
Date: Thu Jul  1 18:10:49 2010
New Revision: 107448

URL: http://llvm.org/viewvc/llvm-project?rev=107448&view=rev
Log:
Shrink down SSE3 code by more multiclass refactoring

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=107448&r1=107447&r2=107448&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Jul  1 18:10:49 2010
@@ -3350,15 +3350,9 @@
 }
 
 //===---------------------------------------------------------------------===//
-// SSSE3 Instructions
+// SSSE3 - Packed Absolute Instructions
 //===---------------------------------------------------------------------===//
 
-// Thread synchronization
-def MONITOR : I<0x01, MRM_C8, (outs), (ins), "monitor",
-                [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
-def MWAIT   : I<0x01, MRM_C9, (outs), (ins), "mwait",
-                [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
-
 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
                             PatFrag mem_frag64, PatFrag mem_frag128,
@@ -3396,149 +3390,100 @@
                                     int_x86_ssse3_pabs_d,
                                     int_x86_ssse3_pabs_d_128>;
 
-/// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8.
-let Constraints = "$src1 = $dst" in {
-  multiclass SS3I_binop_rm_int_8<bits<8> opc, string OpcodeStr,
-                                 Intrinsic IntId64, Intrinsic IntId128,
-                                 bit Commutable = 0> {
-    def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
-                     (ins VR64:$src1, VR64:$src2),
-                     !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
-                     [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
-      let isCommutable = Commutable;
-    }
-    def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
-                     (ins VR64:$src1, i64mem:$src2),
-                     !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
-                     [(set VR64:$dst,
-                       (IntId64 VR64:$src1,
-                        (bitconvert (memopv8i8 addr:$src2))))]>;
-
-    def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
-                      (ins VR128:$src1, VR128:$src2),
-                      !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
-                      [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
-                      OpSize {
-      let isCommutable = Commutable;
-    }
-    def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
-                      (ins VR128:$src1, i128mem:$src2),
-                      !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
-                      [(set VR128:$dst,
-                        (IntId128 VR128:$src1,
-                         (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
-  }
-}
+//===---------------------------------------------------------------------===//
+// SSSE3 - Packed Binary Operator Instructions
+//===---------------------------------------------------------------------===//
 
-/// SS3I_binop_rm_int_16 - Simple SSSE3 binary operator whose type is v*i16.
-let Constraints = "$src1 = $dst" in {
-  multiclass SS3I_binop_rm_int_16<bits<8> opc, string OpcodeStr,
-                                  Intrinsic IntId64, Intrinsic IntId128,
-                                  bit Commutable = 0> {
-    def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
-                     (ins VR64:$src1, VR64:$src2),
-                     !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
-                     [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
-      let isCommutable = Commutable;
-    }
-    def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
-                     (ins VR64:$src1, i64mem:$src2),
-                     !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
-                     [(set VR64:$dst,
-                       (IntId64 VR64:$src1,
-                        (bitconvert (memopv4i16 addr:$src2))))]>;
+/// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
+multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
+                             PatFrag mem_frag64, PatFrag mem_frag128,
+                             Intrinsic IntId64, Intrinsic IntId128,
+                             bit Is2Addr = 1> {
+  let isCommutable = 1 in
+  def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
+       (ins VR64:$src1, VR64:$src2),
+       !if(Is2Addr,
+         !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
+         !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
+       [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]>;
+  def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
+       (ins VR64:$src1, i64mem:$src2),
+       !if(Is2Addr,
+         !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
+         !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
+       [(set VR64:$dst,
+         (IntId64 VR64:$src1,
+          (bitconvert (memopv8i8 addr:$src2))))]>;
 
-    def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
-                      (ins VR128:$src1, VR128:$src2),
-                      !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
-                      [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
-                      OpSize {
-      let isCommutable = Commutable;
-    }
-    def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
-                      (ins VR128:$src1, i128mem:$src2),
-                      !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
-                      [(set VR128:$dst,
-                        (IntId128 VR128:$src1,
-                         (bitconvert (memopv8i16 addr:$src2))))]>, OpSize;
-  }
+  let isCommutable = 1 in
+  def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
+       (ins VR128:$src1, VR128:$src2),
+       !if(Is2Addr,
+         !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
+         !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
+       [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
+       OpSize;
+  def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
+       (ins VR128:$src1, i128mem:$src2),
+       !if(Is2Addr,
+         !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
+         !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
+       [(set VR128:$dst,
+         (IntId128 VR128:$src1,
+          (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
 }
 
-/// SS3I_binop_rm_int_32 - Simple SSSE3 binary operator whose type is v*i32.
-let Constraints = "$src1 = $dst" in {
-  multiclass SS3I_binop_rm_int_32<bits<8> opc, string OpcodeStr,
-                                  Intrinsic IntId64, Intrinsic IntId128,
-                                  bit Commutable = 0> {
-    def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
-                     (ins VR64:$src1, VR64:$src2),
-                     !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
-                     [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
-      let isCommutable = Commutable;
-    }
-    def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
-                     (ins VR64:$src1, i64mem:$src2),
-                     !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
-                     [(set VR64:$dst,
-                       (IntId64 VR64:$src1,
-                        (bitconvert (memopv2i32 addr:$src2))))]>;
-
-    def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
-                      (ins VR128:$src1, VR128:$src2),
-                      !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
-                      [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
-                      OpSize {
-      let isCommutable = Commutable;
-    }
-    def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
-                      (ins VR128:$src1, i128mem:$src2),
-                      !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
-                      [(set VR128:$dst,
-                        (IntId128 VR128:$src1,
-                         (bitconvert (memopv4i32 addr:$src2))))]>, OpSize;
-  }
+// None of these have i8 immediate fields.
+let ImmT = NoImm, Constraints = "$src1 = $dst" in {
+let isCommutable = 0 in {
+  defm PHADDW    : SS3I_binop_rm_int<0x01, "phaddw", memopv4i16, memopv8i16,
+                                     int_x86_ssse3_phadd_w,
+                                     int_x86_ssse3_phadd_w_128>;
+  defm PHADDD    : SS3I_binop_rm_int<0x02, "phaddd", memopv2i32, memopv4i32,
+                                     int_x86_ssse3_phadd_d,
+                                     int_x86_ssse3_phadd_d_128>;
+  defm PHADDSW   : SS3I_binop_rm_int<0x03, "phaddsw", memopv4i16, memopv8i16,
+                                     int_x86_ssse3_phadd_sw,
+                                     int_x86_ssse3_phadd_sw_128>;
+  defm PHSUBW    : SS3I_binop_rm_int<0x05, "phsubw", memopv4i16, memopv8i16,
+                                     int_x86_ssse3_phsub_w,
+                                     int_x86_ssse3_phsub_w_128>;
+  defm PHSUBD    : SS3I_binop_rm_int<0x06, "phsubd", memopv2i32, memopv4i32,
+                                     int_x86_ssse3_phsub_d,
+                                     int_x86_ssse3_phsub_d_128>;
+  defm PHSUBSW   : SS3I_binop_rm_int<0x07, "phsubsw", memopv4i16, memopv8i16,
+                                     int_x86_ssse3_phsub_sw,
+                                     int_x86_ssse3_phsub_sw_128>;
+  defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv8i8, memopv16i8,
+                                     int_x86_ssse3_pmadd_ub_sw,
+                                     int_x86_ssse3_pmadd_ub_sw_128>;
+  defm PSHUFB    : SS3I_binop_rm_int<0x00, "pshufb", memopv8i8, memopv16i8,
+                                     int_x86_ssse3_pshuf_b,
+                                     int_x86_ssse3_pshuf_b_128>;
+  defm PSIGNB    : SS3I_binop_rm_int<0x08, "psignb", memopv8i8, memopv16i8,
+                                     int_x86_ssse3_psign_b,
+                                     int_x86_ssse3_psign_b_128>;
+  defm PSIGNW    : SS3I_binop_rm_int<0x09, "psignw", memopv4i16, memopv8i16,
+                                     int_x86_ssse3_psign_w,
+                                     int_x86_ssse3_psign_w_128>;
+  defm PSIGND    : SS3I_binop_rm_int<0x0A, "psignd", memopv2i32, memopv4i32,
+                                       int_x86_ssse3_psign_d,
+                                       int_x86_ssse3_psign_d_128>;
+}
+defm PMULHRSW    : SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv4i16, memopv8i16,
+                                     int_x86_ssse3_pmul_hr_sw,
+                                     int_x86_ssse3_pmul_hr_sw_128>;
 }
 
-let ImmT = NoImm in {  // None of these have i8 immediate fields.
-defm PHADDW      : SS3I_binop_rm_int_16<0x01, "phaddw",
-                                        int_x86_ssse3_phadd_w,
-                                        int_x86_ssse3_phadd_w_128>;
-defm PHADDD      : SS3I_binop_rm_int_32<0x02, "phaddd",
-                                        int_x86_ssse3_phadd_d,
-                                        int_x86_ssse3_phadd_d_128>;
-defm PHADDSW     : SS3I_binop_rm_int_16<0x03, "phaddsw",
-                                        int_x86_ssse3_phadd_sw,
-                                        int_x86_ssse3_phadd_sw_128>;
-defm PHSUBW      : SS3I_binop_rm_int_16<0x05, "phsubw",
-                                        int_x86_ssse3_phsub_w,
-                                        int_x86_ssse3_phsub_w_128>;
-defm PHSUBD      : SS3I_binop_rm_int_32<0x06, "phsubd",
-                                        int_x86_ssse3_phsub_d,
-                                        int_x86_ssse3_phsub_d_128>;
-defm PHSUBSW     : SS3I_binop_rm_int_16<0x07, "phsubsw",
-                                        int_x86_ssse3_phsub_sw,
-                                        int_x86_ssse3_phsub_sw_128>;
-defm PMADDUBSW   : SS3I_binop_rm_int_8 <0x04, "pmaddubsw",
-                                        int_x86_ssse3_pmadd_ub_sw,
-                                        int_x86_ssse3_pmadd_ub_sw_128>;
-defm PMULHRSW    : SS3I_binop_rm_int_16<0x0B, "pmulhrsw",
-                                        int_x86_ssse3_pmul_hr_sw,
-                                        int_x86_ssse3_pmul_hr_sw_128, 1>;
-
-defm PSHUFB      : SS3I_binop_rm_int_8 <0x00, "pshufb",
-                                        int_x86_ssse3_pshuf_b,
-                                        int_x86_ssse3_pshuf_b_128>;
-defm PSIGNB      : SS3I_binop_rm_int_8 <0x08, "psignb",
-                                        int_x86_ssse3_psign_b,
-                                        int_x86_ssse3_psign_b_128>;
-defm PSIGNW      : SS3I_binop_rm_int_16<0x09, "psignw",
-                                        int_x86_ssse3_psign_w,
-                                        int_x86_ssse3_psign_w_128>;
-defm PSIGND      : SS3I_binop_rm_int_32<0x0A, "psignd",
-                                        int_x86_ssse3_psign_d,
-                                        int_x86_ssse3_psign_d_128>;
-}
+def : Pat<(X86pshufb VR128:$src, VR128:$mask),
+          (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
+def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
+          (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
+
+//===---------------------------------------------------------------------===//
+// SSSE3 - Packed Align Instruction Patterns
+//===---------------------------------------------------------------------===//
 
-// palignr patterns.
 let Constraints = "$src1 = $dst" in {
   def PALIGNR64rr  : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
                            (ins VR64:$src1, VR64:$src2, i8imm:$src3),
@@ -3600,10 +3545,15 @@
       Requires<[HasSSSE3]>;
 }
 
-def : Pat<(X86pshufb VR128:$src, VR128:$mask),
-          (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
-def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
-          (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
+//===---------------------------------------------------------------------===//
+// SSSE3 Misc Instructions
+//===---------------------------------------------------------------------===//
+
+// Thread synchronization
+def MONITOR : I<0x01, MRM_C8, (outs), (ins), "monitor",
+                [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
+def MWAIT   : I<0x01, MRM_C9, (outs), (ins), "mwait",
+                [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
 
 //===---------------------------------------------------------------------===//
 // Non-Instruction Patterns




From gohman at apple.com  Thu Jul  1 19:10:16 2010
From: gohman at apple.com (Dan Gohman)
Date: Fri, 02 Jul 2010 00:10:16 -0000
Subject: [llvm-commits] [llvm] r107451 - in
 /llvm/trunk/lib/CodeGen/SelectionDAG: FastISel.cpp FunctionLoweringInfo.cpp
 FunctionLoweringInfo.h SelectionDAGBuilder.cpp SelectionDAGISel.cpp
Message-ID: <20100702001016.95CB42A6C12C@llvm.org>

Author: djg
Date: Thu Jul  1 19:10:16 2010
New Revision: 107451

URL: http://llvm.org/viewvc/llvm-project?rev=107451&view=rev
Log:
Rename CreateReg to CreateRegs, and MakeReg to CreateReg.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.h
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=107451&r1=107450&r2=107451&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Thu Jul  1 19:10:16 2010
@@ -1211,7 +1211,7 @@
       // by bailing out early, we may leave behind some dead instructions,
       // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
       // own moves. Second, this check is necessary becuase FastISel doesn't
-      // use CreateReg to create registers, so it always creates
+      // use CreateRegs to create registers, so it always creates
       // exactly one register for each non-void instruction.
       EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
       if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp?rev=107451&r1=107450&r2=107451&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp Thu Jul  1 19:10:16 2010
@@ -172,18 +172,19 @@
   ArgDbgValues.clear();
 }
 
-unsigned FunctionLoweringInfo::MakeReg(EVT VT) {
+/// CreateReg - Allocate a single virtual register for the given type.
+unsigned FunctionLoweringInfo::CreateReg(EVT VT) {
   return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
 }
 
-/// CreateReg - Allocate the appropriate number of virtual registers of
+/// CreateRegs - Allocate the appropriate number of virtual registers of
 /// the correctly promoted or expanded types.  Assign these registers
 /// consecutive vreg numbers and return the first assigned number.
 ///
 /// In the case that the given value has struct or array type, this function
 /// will assign registers for each member or element.
 ///
-unsigned FunctionLoweringInfo::CreateReg(const Type *Ty) {
+unsigned FunctionLoweringInfo::CreateRegs(const Type *Ty) {
   SmallVector<EVT, 4> ValueVTs;
   ComputeValueVTs(TLI, Ty, ValueVTs);
 
@@ -194,7 +195,7 @@
 
     unsigned NumRegs = TLI.getNumRegisters(Ty->getContext(), ValueVT);
     for (unsigned i = 0; i != NumRegs; ++i) {
-      unsigned R = MakeReg(RegisterVT);
+      unsigned R = CreateReg(RegisterVT);
       if (!FirstReg) FirstReg = R;
     }
   }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.h?rev=107451&r1=107450&r2=107451&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.h (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.h Thu Jul  1 19:10:16 2010
@@ -113,20 +113,20 @@
   /// different function.
   void clear();
 
-  unsigned MakeReg(EVT VT);
-  
   /// isExportedInst - Return true if the specified value is an instruction
   /// exported from its block.
   bool isExportedInst(const Value *V) {
     return ValueMap.count(V);
   }
 
-  unsigned CreateReg(const Type *Ty);
+  unsigned CreateReg(EVT VT);
+  
+  unsigned CreateRegs(const Type *Ty);
   
   unsigned InitializeRegForValue(const Value *V) {
     unsigned &R = ValueMap[V];
     assert(R == 0 && "Already initialized this value register!");
-    return R = CreateReg(V->getType());
+    return R = CreateRegs(V->getType());
   }
 };
 

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=107451&r1=107450&r2=107451&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Thu Jul  1 19:10:16 2010
@@ -1508,7 +1508,7 @@
   // therefore require extension or truncating.
   SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy());
 
-  unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
+  unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
   SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
                                     JumpTableReg, SwitchOp);
   JT.Reg = JumpTableReg;
@@ -1559,7 +1559,7 @@
   SDValue ShiftOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(),
                                        TLI.getPointerTy());
 
-  B.Reg = FuncInfo.MakeReg(TLI.getPointerTy());
+  B.Reg = FuncInfo.CreateReg(TLI.getPointerTy());
   SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
                                     B.Reg, ShiftOp);
 
@@ -6164,7 +6164,7 @@
       if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
         unsigned &RegOut = ConstantsOut[C];
         if (RegOut == 0) {
-          RegOut = FuncInfo.CreateReg(C->getType());
+          RegOut = FuncInfo.CreateRegs(C->getType());
           CopyValueToVirtualRegister(C, RegOut);
         }
         Reg = RegOut;
@@ -6177,7 +6177,7 @@
           assert(isa<AllocaInst>(PHIOp) &&
                  FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
                  "Didn't codegen value into a register!??");
-          Reg = FuncInfo.CreateReg(PHIOp->getType());
+          Reg = FuncInfo.CreateRegs(PHIOp->getType());
           CopyValueToVirtualRegister(PHIOp, Reg);
         }
       }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=107451&r1=107450&r2=107451&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Jul  1 19:10:16 2010
@@ -732,7 +732,7 @@
           if (!BI->getType()->isVoidTy() && !BI->use_empty()) {
             unsigned &R = FuncInfo->ValueMap[BI];
             if (!R)
-              R = FuncInfo->CreateReg(BI->getType());
+              R = FuncInfo->CreateRegs(BI->getType());
           }
 
           bool HadTailCall = false;




From dalej at apple.com  Thu Jul  1 19:19:22 2010
From: dalej at apple.com (Dale Johannesen)
Date: Fri, 02 Jul 2010 00:19:22 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r107452 -
	/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/
Message-ID: <20100702001922.D2F312A6C12C@llvm.org>

Author: johannes
Date: Thu Jul  1 19:19:22 2010
New Revision: 107452

URL: http://llvm.org/viewvc/llvm-project?rev=107452&view=rev
Log:
Make these tests run on x86-64 Darwin builds.
We haven't been testing asm blocks recently...


Modified:
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-10.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-11.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-12.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-13.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-14.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-15.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-16.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-17.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-18.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-19.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-20.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-21.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-22.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-23.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-24.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-25.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-26.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-27.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-28.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-29.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-3.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-30.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-31.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-32.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-33.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-34.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-35.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-36.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-37.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-38.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-39.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-41.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-42.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-43.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-44.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-45.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-46.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-49.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-50.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-51.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-52.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-53.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-54.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-55.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-56.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-57.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-58.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-59.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-6.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-60.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-61.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-62.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-63.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-64.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-65.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-66.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-67.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-68.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-7.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-8.c
    llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-function-19.c

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-10.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-10.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-10.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-10.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin*} } */
 /* { dg-options { "-fasm-blocks" } } */
 /* Radar 4211954 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-11.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-11.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-11.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-11.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4211971 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-12.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-12.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-12.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-12.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4259442 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-13.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-13.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-13.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-13.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-require-effective-target ilp32 } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4259442 */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-14.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-14.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-14.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-14.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4271787 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-15.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-15.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-15.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-15.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4248159 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-16.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-16.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-16.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-16.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4273781 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-17.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-17.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-17.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-17.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-require-effective-target ilp32 } */
 /* { dg-options { -fasm-blocks -msse3 -O2 } } */
 /* Radar  */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-18.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-18.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-18.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-18.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-require-effective-target ilp32 } */
 /* { dg-options { -fasm-blocks -msse3 -O2 } } */
 /* Radar 4248228 */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-19.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-19.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-19.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-19.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4236553 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-20.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-20.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-20.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-20.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 
 void foo() {

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-21.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-21.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-21.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-21.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -m64 -fasm-blocks -msse3 } } */
 /* Radar 4249602 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-22.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-22.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-22.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-22.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4248205 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-23.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-23.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-23.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-23.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4248139 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-24.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-24.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-24.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-24.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-require-effective-target ilp32 } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4300095 */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-25.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-25.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-25.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-25.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-require-effective-target ilp32 } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4309942 */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-26.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-26.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-26.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-26.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4300138 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-27.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-27.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-27.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-27.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 
 void foo() {

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-28.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-28.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-28.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-28.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 -O } } */
 /* Radar 4300156 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-29.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-29.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-29.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-29.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target powerpc*-*-darwin* i?86*-*-darwin* } } */
+/* { dg-do assemble { target powerpc*-*-darwin* i?86*-*-darwin* x86_64*-*-darwin*} } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4298005 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-3.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-3.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-3.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-3.c Thu Jul  1 19:19:22 2010
@@ -1,7 +1,7 @@
 /* APPLE LOCAL file CW asm blocks */
 /* Test single line asms */
 
-/* { dg-do compile { target powerpc*-*-darwin* i?86*-*-darwin* } } */
+/* { dg-do compile { target powerpc*-*-darwin* i?86*-*-darwin* x86_64*-*-darwin*} } */
 /* { dg-options "-fasm-blocks" } */
 
 void

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-30.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-30.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-30.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-30.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Shouldn't be necessary, but it doesn't work yet.  */
 /* { dg-require-effective-target ilp32 } */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-31.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-31.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-31.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-31.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-require-effective-target ilp32 } */
 /* { dg-options { -fasm-blocks -msse3 -mdynamic-no-pic } } */
 /* Radar 4319881 */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-32.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-32.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-32.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-32.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-require-effective-target ilp32 } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4319887 */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-33.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-33.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-33.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-33.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-require-effective-target ilp32 } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4300193 */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-34.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-34.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-34.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-34.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4363798 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-35.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-35.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-35.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-35.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-require-effective-target ilp32 } */
 /* { dg-options { -fasm-blocks -msse3 -mdynamic-no-pic } } */
 /* Radar 4371551 */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-36.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-36.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-36.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-36.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-require-effective-target ilp32 } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4371958 */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-37.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-37.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-37.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-37.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 -O1 } } */
 /* Radar 4433955 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-38.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-38.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-38.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-38.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4433955 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-39.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-39.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-39.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-39.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4432782 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-41.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-41.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-41.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-41.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-require-effective-target ilp32 } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4429851 */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-42.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-42.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-42.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-42.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4399388 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-43.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-43.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-43.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-43.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4415216 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-44.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-44.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-44.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-44.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4443942 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-45.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-45.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-45.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-45.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-require-effective-target ilp32 } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4419735 */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-46.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-46.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-46.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-46.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do compile { target i?86*-*-darwin* } } */
+/* { dg-do compile { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4419735 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-49.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-49.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-49.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-49.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target powerpc*-*-darwin* i?86*-*-darwin* } } */
+/* { dg-do assemble { target powerpc*-*-darwin* i?86*-*-darwin* x86_64*-*-darwin*} } */
 /* { dg-options { -fasm-blocks } } */
 /* Radar 4477426 4466768 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-50.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-50.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-50.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-50.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin*} } */
 /* { dg-require-effective-target ilp32 } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4505741 */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-51.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-51.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-51.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-51.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin*} } */
 /* { dg-options { -fasm-blocks } } */
 /* Radar 4505697 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-52.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-52.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-52.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-52.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin*} } */
 /* { dg-options { -fasm-blocks -O } } */
 /* Radar 4527214 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-53.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-53.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-53.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-53.c Thu Jul  1 19:19:22 2010
@@ -1,4 +1,4 @@
-/* { dg-do compile { target i?86*-*-darwin* } } */
+/* { dg-do compile { target i?86*-*-darwin* x86_64*-*-darwin*} } */
 /* { dg-options { -fasm-blocks } } */
 /* { dg-final { scan-assembler "0\\\(%eax,%eax,2\\\), %edx" } } */
 /* Radar 4560301 */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-54.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-54.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-54.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-54.c Thu Jul  1 19:19:22 2010
@@ -1,4 +1,4 @@
-/* { dg-do compile { target i?86*-*-darwin* } } */
+/* { dg-do compile { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-require-effective-target ilp32 } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* LLVM LOCAL */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-55.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-55.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-55.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-55.c Thu Jul  1 19:19:22 2010
@@ -1,4 +1,4 @@
-/* { dg-do compile { target i?86*-*-darwin* } } */
+/* { dg-do compile { target i?86*-*-darwin* x86_64*-*-darwin*} } */
 /* { dg-require-effective-target ilp32 } */
 /* { dg-options { -fasm-blocks -msse3 -mdynamic-no-pic } } */
 /* { dg-final { scan-assembler "movq _packedw1.*, %mm0" } } */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-56.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-56.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-56.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-56.c Thu Jul  1 19:19:22 2010
@@ -1,4 +1,4 @@
-/* { dg-do compile { target i?86*-*-darwin* } } */
+/* { dg-do compile { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks } } */
 /* Radar 4653181 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-57.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-57.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-57.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-57.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do run { target i?86*-*-darwin* } } */
+/* { dg-do run { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-require-effective-target ilp32 } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4682427 */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-58.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-58.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-58.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-58.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin*} } */
 /* { dg-options { -m64 -fasm-blocks -msse3 } } */
 /* Radar 4699524 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-59.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-59.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-59.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-59.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do compile { target i?86*-*-darwin* } } */
+/* { dg-do compile { target i?86*-*-darwin* x86_64*-*-darwin*} } */
 /* { dg-options { -fasm-blocks -msse3 -O2 } } */
 /* { dg-require-effective-target ilp32 } */
 /* { dg-final { scan-assembler "-\(40|44\)\\\(%ebp,%edx,2\\\), %ebx" } } */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-6.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-6.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-6.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-6.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin*} } */
 /* { dg-require-effective-target ilp32 } */
 /* { dg-options { "-fasm-blocks" } } */
 /* Radar 4211978 */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-60.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-60.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-60.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-60.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do compile { target i?86*-*-darwin* } } */
+/* { dg-do compile { target i?86*-*-darwin* x86_64*-*-darwin*} } */
 /* { dg-options { -fasm-blocks -msse3 -O2 } } */
 /* { dg-final { scan-assembler "movsl \n" } } */
 /* Radar 4736998 */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-61.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-61.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-61.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-61.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do compile { target i?86*-*-darwin* } } */
+/* { dg-do compile { target i?86*-*-darwin* x86_64*-*-darwin*} } */
 /* { dg-options { -fasm-blocks } } */
 /* Radar 4739936 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-62.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-62.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-62.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-62.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do compile { target powerpc*-*-darwin* i?86*-*-darwin* } } */
+/* { dg-do compile { target powerpc*-*-darwin* i?86*-*-darwin* x86_64*-*-darwin*} } */
 /* { dg-options { -fasm-blocks } } */
 /* Radar 4197305 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-63.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-63.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-63.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-63.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do compile { target powerpc*-*-darwin* i?86*-*-darwin* } } */
+/* { dg-do compile { target powerpc*-*-darwin* i?86*-*-darwin* x86_64*-*-darwin*} } */
 /* { dg-options { -fasm-blocks } } */
 /* Radar 4766972 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-64.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-64.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-64.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-64.c Thu Jul  1 19:19:22 2010
@@ -1,4 +1,4 @@
-/* { dg-do compile { target i?86*-*-darwin* } } */
+/* { dg-do compile { target i?86*-*-darwin* x86_64*-*-darwin*} } */
 /* { dg-options { -fasm-blocks -O2 } } */
 /* Radar 5315594 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-65.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-65.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-65.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-65.c Thu Jul  1 19:19:22 2010
@@ -1,4 +1,4 @@
-/* { dg-do compile { target powerpc*-*-darwin* i?86*-*-darwin* } } */
+/* { dg-do compile { target powerpc*-*-darwin* i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks } } */
 /* Radar 5474682 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-66.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-66.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-66.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-66.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do compile { target i?86*-*-darwin* } } */
+/* { dg-do compile { target i?86*-*-darwin* x86_64*-*-darwin*} } */
 /* { dg-options { -fasm-blocks } } */
 /* { dg-final { scan-assembler "filds" } } */
 /* { dg-final { scan-assembler "fstps" } } */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-67.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-67.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-67.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-67.c Thu Jul  1 19:19:22 2010
@@ -1,4 +1,4 @@
-/* { dg-do compile { target powerpc*-*-darwin* i?86*-*-darwin* } } */
+/* { dg-do compile { target powerpc*-*-darwin* i?86*-*-darwin* x86_64*-*-darwin*} } */
 /* { dg-options "-fasm-blocks" } */
 
 int i = 1st;	/* { dg-error "invalid suffix \"st\" on integer constant" } */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-68.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-68.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-68.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-68.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin*} } */
 /* { dg-options { -fasm-blocks } } */
 /* <rdar://problem/7763139> */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-7.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-7.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-7.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-7.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-require-effective-target ilp32 } */
 /* { dg-options { "-fasm-blocks" } } */
 /* Radar 4214021 */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-8.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-8.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-8.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-block-8.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin*} } */
 /* { dg-options { "-fasm-blocks" } } */
 /* Radar 4211947 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-function-19.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-function-19.c?rev=107452&r1=107451&r2=107452&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-function-19.c (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/gcc.apple/asm-function-19.c Thu Jul  1 19:19:22 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin*} } */
 /* { dg-options { -fasm-blocks -msse3 -O3 -Winline -Wall } } */
 /* Radar 4381918 */
 




From gohman at apple.com  Thu Jul  1 19:35:34 2010
From: gohman at apple.com (Dan Gohman)
Date: Fri, 02 Jul 2010 00:35:34 -0000
Subject: [llvm-commits] [llvm] r107454 -
	/llvm/trunk/lib/VMCore/Instruction.cpp
Message-ID: <20100702003534.D7AE22A6C12C@llvm.org>

Author: djg
Date: Thu Jul  1 19:35:34 2010
New Revision: 107454

URL: http://llvm.org/viewvc/llvm-project?rev=107454&view=rev
Log:
IndirectBr is not safe to speculatively execute (!)

Modified:
    llvm/trunk/lib/VMCore/Instruction.cpp

Modified: llvm/trunk/lib/VMCore/Instruction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instruction.cpp?rev=107454&r1=107453&r2=107454&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Instruction.cpp (original)
+++ llvm/trunk/lib/VMCore/Instruction.cpp Thu Jul  1 19:35:34 2010
@@ -421,6 +421,7 @@
   case Store:
   case Ret:
   case Br:
+  case IndirectBr:
   case Switch:
   case Unwind:
   case Unreachable:




From gohman at apple.com  Thu Jul  1 20:20:16 2010
From: gohman at apple.com (Dan Gohman)
Date: Fri, 02 Jul 2010 01:20:16 -0000
Subject: [llvm-commits] [llvm] r107458 -
	/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
Message-ID: <20100702012016.6C8052A6C12C@llvm.org>

Author: djg
Date: Thu Jul  1 20:20:16 2010
New Revision: 107458

URL: http://llvm.org/viewvc/llvm-project?rev=107458&view=rev
Log:
Comment a non-obvious member variable.

Modified:
    llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h

Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=107458&r1=107457&r2=107458&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Thu Jul  1 20:20:16 2010
@@ -1572,6 +1572,8 @@
   struct OutputArg {
     ArgFlagsTy Flags;
     SDValue Val;
+
+    /// IsFixed - Is this a "fixed" value, ie not passed through a vararg "...".
     bool IsFixed;
 
     OutputArg() : IsFixed(false) {}




From echristo at apple.com  Fri Jul  2 00:01:53 2010
From: echristo at apple.com (Eric Christopher)
Date: Thu, 1 Jul 2010 22:01:53 -0700
Subject: [llvm-commits] [llvm] r107438 -
	/llvm/trunk/lib/Target/X86/X86InstrSSE.td
In-Reply-To: <20100701223318.B227C2A6C12C@llvm.org>
References: <20100701223318.B227C2A6C12C@llvm.org>
Message-ID: <5B6FD7BD-BA5A-4871-9555-786F098C5700@apple.com>


On Jul 1, 2010, at 3:33 PM, Bruno Cardoso Lopes wrote:

> Shrink down SSE3 code by some multiclass refactoring - 1st part

I love all the shrinking and refactoring, but unfortunately the refactored stuff isn't quite as obvious as the great stuff you've been putting in - mind if I bug you for a few more comments over the big multiclasses?

-eric


From nicholas at mxc.ca  Fri Jul  2 01:52:47 2010
From: nicholas at mxc.ca (Nick Lewycky)
Date: Thu, 01 Jul 2010 23:52:47 -0700
Subject: [llvm-commits] [llvm] r107109 - in /llvm/trunk:
 include/llvm/Analysis/AliasAnalysis.h include/llvm/Analysis/Passes.h
 lib/Analysis/AliasAnalysis.cpp	lib/Analysis/BasicAliasAnalysis.cpp
 test/Analysis/BasicAA/interprocedural.ll
In-Reply-To: <92C98C7C-831E-4021-964E-B20289FB8BAB@apple.com>
References: <20100629005039.39B192A6C12C@llvm.org> <4C298317.7050002@mxc.ca>
	<5E31E70D-BC94-4545-BE28-F8927D72097F@apple.com>
	<0EAA395C-1A7A-45D2-A6F9-F3B837A0F91C@apple.com>
	<92C98C7C-831E-4021-964E-B20289FB8BAB@apple.com>
Message-ID: <4C2D8CBF.7070500@mxc.ca>

Dan Gohman wrote:
>
> On Jun 30, 2010, at 9:21 PM, Chris Lattner wrote:
>
>> On Jun 29, 2010, at 11:09 AM, Dan Gohman wrote:
>>>> Why is this an additional pass? Why not infer Interprocedural from SameParent()? The idempotents that basicaa was testing for should still hold true whenever SameParent() is true. It looks like the 'Interprocedural BasicAA' is basically a bugfix on BasicAA.
>>>
>>> "noalias" is only meaningful from a single-procedure perspective.
>>> For example:
>>>
>>> @G = external global i32
>>> define void @foo(i32* noalias %p) {
>>> ...
>>> }
>>> ...
>>> call void @foo(i32* @G)
>>>
>>> If you're working exclusively within the body of @foo, then alias(@G, %p)
>>> can be NoAlias. From an interprocedural perspective, it can be MustAlias.
>>> Even with something like
>>>
>>> define void @bar(double* noalias %a, double* noalias %b) {
>>>
>>> it isn't trivial to say that %a doesn't alias %b because if it goes on to do
>>>
>>> call void @bar(double* %b, double* %a)
>>>
>>> then there is a sense in which %a could MustAlias %b, interprocedurally.
>>
>> I don't buy this at all.  The current interface to AA (even for interprocedural clients) is context insensitive.  If you want a path or context-sensitive query interface, you'd need a substantially richer and more complex (aka slower) interface.  DSA provides this sort of interface for example.
>
> You're right, I was mistaken about recursive functions; that's a class of
> cases which are a lot more complicated and do bring in context sensitivity
> concerns. I've removed these considerations in r107420.
>
> However, beyond classic path and context scoping, there's another sense of
> scope that an alias query can have, the scope of a noalias keyword. noalias
> on an argument indicates that argument's relationship with other pointers
> within that function, but it isn't meaningful when considering pointers
> from an interprocedural perspective. An example of this is this is the first
> example I gave above, with alias(@G, %p).

I don't believe you. From the LangRef.html#paramattrs

"*noalias:* This indicates that the pointer does not alias any global or 
any other parameter. The caller is responsible for ensuring that this is 
the case. ..."

Nick


From ggreif at gmail.com  Fri Jul  2 08:21:55 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Fri, 02 Jul 2010 13:21:55 -0000
Subject: [llvm-commits] [llvm] r107480 -
	/llvm/trunk/include/llvm/Instructions.h
Message-ID: <20100702132155.AFC942A6C12E@llvm.org>

Author: ggreif
Date: Fri Jul  2 08:21:55 2010
New Revision: 107480

URL: http://llvm.org/viewvc/llvm-project?rev=107480&view=rev
Log:
[test commit, just to tickle the selfhost buildbots; I'll back out in a few minutes]

second round of low-level interface squeeze-out:
making all of CallInst's low-level operand accessors
private

If you get compile errors I strongly urge you to
update your code.


I tried to write the necessary clues into the
header where the compiler may point to, but no
guarantees. It works for my GCC.

You have several options to update your code:

- you can use the v2.8 ArgOperand accessors
- you can go via a temporary CallSite
- you can upcast to, say, User and call its
  low-level accessors if your code is definitely
  operand-order agnostic.

If you run into serious problems, please
comment in below thread (and back out this
revision only if absolutely necessary):

<http://groups.google.com/group/llvm-dev/browse_thread/thread/64650cf343b28271>

Modified:
    llvm/trunk/include/llvm/Instructions.h

Modified: llvm/trunk/include/llvm/Instructions.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=107480&r1=107479&r2=107480&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Instructions.h (original)
+++ llvm/trunk/include/llvm/Instructions.h Fri Jul  2 08:21:55 2010
@@ -940,8 +940,24 @@
                                unsigned(isTC));
   }
 
+  /// @deprecated these "define hacks" will go away soon
+  /// @brief coerce out-of-tree code to abandon the low-level interfaces
+  /// @detail see below comments and update your code to high-level interfaces
+  ///    in LLVM v2.8-only code
+  ///    - getOperand(N+1)  --->  getArgOperand(N)
+  ///    - setOperand(N+1, V)  --->  setArgOperand(N, V)
+  ///    - getNumOperands()  --->  getNumArgOperands()+1  // note the "+1"!
+  ///
+  ///    in backward compatible code please consult llvm/Support/CallSite.h,
+  ///    you should create a callsite using the CallInst pointer and call its methods
+  ///
+# define public private
+# define protected private
   /// Provide fast operand accessors
   DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
+# undef public
+# undef protected
+public:
 
   enum { ArgOffset = 1 }; ///< temporary, do not use for new code!
   unsigned getNumArgOperands() const { return getNumOperands() - 1; }
@@ -951,7 +967,7 @@
   /// Provide compile-time errors for accessing operand 0
   /// @deprecated these will go away soon
   /// @detail see below comments and update your code to high-level interfaces
-  ///    - getOperand(0)  --->  getCalledValue()
+  ///    - getOperand(0)  --->  getCalledValue(), or possibly getCalledFunction()
   ///    - setOperand(0, V)  --->  setCalledFunction(V)
   ///
 private:
@@ -1107,6 +1123,10 @@
        typename std::iterator_traits<InputIterator>::iterator_category());
 }
 
+
+// Note: if you get compile errors about private methods then
+//       please update your code to use the high-level operand
+//       interfaces. See line 943 above.
 DEFINE_TRANSPARENT_OPERAND_ACCESSORS(CallInst, Value)
 
 //===----------------------------------------------------------------------===//




From ggreif at gmail.com  Fri Jul  2 08:27:50 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Fri, 02 Jul 2010 13:27:50 -0000
Subject: [llvm-commits] [llvm] r107481 -
	/llvm/trunk/include/llvm/Instructions.h
Message-ID: <20100702132750.C9A5D2A6C12E@llvm.org>

Author: ggreif
Date: Fri Jul  2 08:27:50 2010
New Revision: 107481

URL: http://llvm.org/viewvc/llvm-project?rev=107481&view=rev
Log:
back out r107480, it was just testing the waters anyway...

Modified:
    llvm/trunk/include/llvm/Instructions.h

Modified: llvm/trunk/include/llvm/Instructions.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=107481&r1=107480&r2=107481&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Instructions.h (original)
+++ llvm/trunk/include/llvm/Instructions.h Fri Jul  2 08:27:50 2010
@@ -940,24 +940,8 @@
                                unsigned(isTC));
   }
 
-  /// @deprecated these "define hacks" will go away soon
-  /// @brief coerce out-of-tree code to abandon the low-level interfaces
-  /// @detail see below comments and update your code to high-level interfaces
-  ///    in LLVM v2.8-only code
-  ///    - getOperand(N+1)  --->  getArgOperand(N)
-  ///    - setOperand(N+1, V)  --->  setArgOperand(N, V)
-  ///    - getNumOperands()  --->  getNumArgOperands()+1  // note the "+1"!
-  ///
-  ///    in backward compatible code please consult llvm/Support/CallSite.h,
-  ///    you should create a callsite using the CallInst pointer and call its methods
-  ///
-# define public private
-# define protected private
   /// Provide fast operand accessors
   DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
-# undef public
-# undef protected
-public:
 
   enum { ArgOffset = 1 }; ///< temporary, do not use for new code!
   unsigned getNumArgOperands() const { return getNumOperands() - 1; }
@@ -967,7 +951,7 @@
   /// Provide compile-time errors for accessing operand 0
   /// @deprecated these will go away soon
   /// @detail see below comments and update your code to high-level interfaces
-  ///    - getOperand(0)  --->  getCalledValue(), or possibly getCalledFunction()
+  ///    - getOperand(0)  --->  getCalledValue()
   ///    - setOperand(0, V)  --->  setCalledFunction(V)
   ///
 private:
@@ -1123,10 +1107,6 @@
        typename std::iterator_traits<InputIterator>::iterator_category());
 }
 
-
-// Note: if you get compile errors about private methods then
-//       please update your code to use the high-level operand
-//       interfaces. See line 943 above.
 DEFINE_TRANSPARENT_OPERAND_ACCESSORS(CallInst, Value)
 
 //===----------------------------------------------------------------------===//




From ggreif at gmail.com  Fri Jul  2 08:37:16 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Fri, 02 Jul 2010 13:37:16 -0000
Subject: [llvm-commits] [llvm] r107482 -
	/llvm/trunk/lib/Target/MSIL/MSILWriter.cpp
Message-ID: <20100702133716.A51D92A6C12C@llvm.org>

Author: ggreif
Date: Fri Jul  2 08:37:16 2010
New Revision: 107482

URL: http://llvm.org/viewvc/llvm-project?rev=107482&view=rev
Log:
use ArgOperand API (found by my previous commit)

Modified:
    llvm/trunk/lib/Target/MSIL/MSILWriter.cpp

Modified: llvm/trunk/lib/Target/MSIL/MSILWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSIL/MSILWriter.cpp?rev=107482&r1=107481&r2=107482&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSIL/MSILWriter.cpp (original)
+++ llvm/trunk/lib/Target/MSIL/MSILWriter.cpp Fri Jul  2 08:37:16 2010
@@ -808,7 +808,7 @@
   std::string Name;
   switch (Inst->getIntrinsicID()) {
   case Intrinsic::vastart:
-    Name = getValueName(Inst->getOperand(1));
+    Name = getValueName(Inst->getArgOperand(0));
     Name.insert(Name.length()-1,"$valist");
     // Obtain the argument handle.
     printSimpleInstruction("ldloca",Name.c_str());
@@ -817,20 +817,20 @@
       "instance void [mscorlib]System.ArgIterator::.ctor"
       "(valuetype [mscorlib]System.RuntimeArgumentHandle)");
     // Save as pointer type "void*"
-    printValueLoad(Inst->getOperand(1));
+    printValueLoad(Inst->getArgOperand(0));
     printSimpleInstruction("ldloca",Name.c_str());
     printIndirectSave(PointerType::getUnqual(
           IntegerType::get(Inst->getContext(), 8)));
     break;
   case Intrinsic::vaend:
     // Close argument list handle.
-    printIndirectLoad(Inst->getOperand(1));
+    printIndirectLoad(Inst->getArgOperand(0));
     printSimpleInstruction("call","instance void [mscorlib]System.ArgIterator::End()");
     break;
   case Intrinsic::vacopy:
     // Copy "ArgIterator" valuetype.
-    printIndirectLoad(Inst->getOperand(1));
-    printIndirectLoad(Inst->getOperand(2));
+    printIndirectLoad(Inst->getArgOperand(0));
+    printIndirectLoad(Inst->getArgOperand(1));
     printSimpleInstruction("cpobj","[mscorlib]System.ArgIterator");
     break;        
   default:
@@ -1281,7 +1281,7 @@
       case Intrinsic::vaend:
       case Intrinsic::vacopy:
         isVaList = true;
-        VaList = Inst->getOperand(1);
+        VaList = Inst->getArgOperand(0);
         break;
       default:
         isVaList = false;




From criswell at cs.uiuc.edu  Fri Jul  2 10:14:37 2010
From: criswell at cs.uiuc.edu (John Criswell)
Date: Fri, 2 Jul 2010 10:14:37 -0500
Subject: [llvm-commits] CVS: llvm-www/safecode/menagerie/links.html
Message-ID: <201007021514.o62FEbhR002013@maute.cs.uiuc.edu>



Changes in directory llvm-www/safecode/menagerie:

links.html updated: 1.1 -> 1.2
---
Log message:

Added a link to the DHard memory allocator.


---
Diffs of the changes:  (+4 -0)

 links.html |    4 ++++
 1 file changed, 4 insertions(+)


Index: llvm-www/safecode/menagerie/links.html
diff -u llvm-www/safecode/menagerie/links.html:1.1 llvm-www/safecode/menagerie/links.html:1.2
--- llvm-www/safecode/menagerie/links.html:1.1	Thu Jun 10 17:32:43 2010
+++ llvm-www/safecode/menagerie/links.html	Fri Jul  2 10:14:04 2010
@@ -61,6 +61,10 @@
         <li>
         <a href="http://www.cis.upenn.edu/acg/softbound/">SoftBound</a>
         </li>
+
+        <li>
+        <a href="http://prisms.cs.umass.edu/emery/index.php?page=diehard">DHard</a>
+        </li>
         </ul>
 		</div>
 





From wdietz2 at illinois.edu  Fri Jul  2 11:16:58 2010
From: wdietz2 at illinois.edu (Will Dietz)
Date: Fri, 02 Jul 2010 16:16:58 -0000
Subject: [llvm-commits] [poolalloc] r107484 -
	/poolalloc/trunk/lib/DSA/DataStructureAA.cpp
Message-ID: <20100702161658.5C5492A6C12C@llvm.org>

Author: wdietz2
Date: Fri Jul  2 11:16:58 2010
New Revision: 107484

URL: http://llvm.org/viewvc/llvm-project?rev=107484&view=rev
Log:
temporarily remove the copy/deleteValue chaining

Modified:
    poolalloc/trunk/lib/DSA/DataStructureAA.cpp

Modified: poolalloc/trunk/lib/DSA/DataStructureAA.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DataStructureAA.cpp?rev=107484&r1=107483&r2=107484&view=diff
==============================================================================
--- poolalloc/trunk/lib/DSA/DataStructureAA.cpp (original)
+++ poolalloc/trunk/lib/DSA/DataStructureAA.cpp Fri Jul  2 11:16:58 2010
@@ -108,7 +108,11 @@
       InvalidateCache();
       BU->deleteValue(V);
       TD->deleteValue(V);
-      AliasAnalysis::deleteValue(V);
+      // FIXME: In the case that we chain to another ds-aa
+      // (and since we share the same TD/BU with that instance)
+      // we end up trying to delete the value twice.
+      // We *should* chain, but we also need to handle that case well.
+      //AliasAnalysis::deleteValue(V);
     }
 
     virtual void copyValue(Value *From, Value *To) {
@@ -117,7 +121,11 @@
       InvalidateCache();
       BU->copyValue(From, To);
       TD->copyValue(From, To);
-      AliasAnalysis::copyValue(From, To);
+      // FIXME: In the case that we chain to another ds-aa
+      // (and since we share the same TD/BU with that instance)
+      // we end up trying to copy the value twice.
+      // We *should* chain, but we also need to handle that case well.
+      //AliasAnalysis::copyValue(From, To);
     }
 
   private:




From wdietz2 at illinois.edu  Fri Jul  2 11:18:31 2010
From: wdietz2 at illinois.edu (Will Dietz)
Date: Fri, 02 Jul 2010 16:18:31 -0000
Subject: [llvm-commits] [poolalloc] r107486 -
	/poolalloc/trunk/lib/DSA/DataStructure.cpp
Message-ID: <20100702161831.A63B62A6C12C@llvm.org>

Author: wdietz2
Date: Fri Jul  2 11:18:31 2010
New Revision: 107486

URL: http://llvm.org/viewvc/llvm-project?rev=107486&view=rev
Log:
initial support for copying/removing functions that are part of SCC's of size > 1

Modified:
    poolalloc/trunk/lib/DSA/DataStructure.cpp

Modified: poolalloc/trunk/lib/DSA/DataStructure.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DataStructure.cpp?rev=107486&r1=107485&r2=107486&view=diff
==============================================================================
--- poolalloc/trunk/lib/DSA/DataStructure.cpp (original)
+++ poolalloc/trunk/lib/DSA/DataStructure.cpp Fri Jul  2 11:18:31 2010
@@ -1082,6 +1082,8 @@
 
 /// deleteValue/copyValue - Interfaces to update the DSGraphs in the program.
 /// These correspond to the interfaces defined in the AliasAnalysis class.
+/// FIXME: Do these update all the datastructures needed?
+/// FIXME: What exactly does it mean to tell DSA to 'copy' a value? or delete it? (particularly a function)
 void DataStructures::deleteValue(Value *V) {
   if (const Function *F = getFnForValue(V)) {  // Function local value?
     // If this is a function local value, just delete it from the scalar map!
@@ -1090,14 +1092,33 @@
   }
   
   if (Function *F = dyn_cast<Function>(V)) {
-    assert(getDSGraph(*F)->getReturnNodes().size() == 1 &&
-           "cannot handle scc's");
-    delete DSInfo[F];
-    DSInfo.erase(F);
+    DSGraph *G = getDSGraph(*F);
+    if (G->getReturnNodes().size() == 1) {
+      // If this is function is part of its own SCC, just delete the graph for it
+      delete G;
+      DSInfo.erase(F);
+    } else {
+      // SCC case
+
+      // Remove some of the graph's information about this function since it's no longer needed
+      G->getReturnNodes().erase(F);
+      G->getVANodes().erase(F);
+
+      // Remove entry for the function, but don't delete the graph since others need it
+      DSInfo.erase(F);
+
+      // FIXME: Can more be done here? Is there a good way to remove from the SCC's graph more
+      // of the information this function contributed?
+
+    }
+
     return;
   }
   
   assert(!isa<GlobalVariable>(V) && "Do not know how to delete GV's yet!");
+
+  assert(0 && "Unrecognized value!");
+  abort();
 }
 
 void DataStructures::copyValue(Value *From, Value *To) {
@@ -1111,18 +1132,33 @@
   if (Function *FromF = dyn_cast<Function>(From)) {
     Function *ToF = cast<Function>(To);
     assert(!DSInfo.count(ToF) && "New Function already exists!");
-    DSGraph *NG = new DSGraph(getDSGraph(*FromF), GlobalECs, *TypeSS);
-    DSInfo[ToF] = NG;
-    assert(NG->getReturnNodes().size() == 1 && "Cannot copy SCC's yet!");
-    
-    // Change the Function* is the returnnodes map to the ToF.
-    DSNodeHandle Ret = NG->retnodes_begin()->second;
-    NG->getReturnNodes().clear();
-    NG->getReturnNodes()[ToF] = Ret;
-    // Change the Function* in the vanodes map to the ToF
-    DSNodeHandle VA = NG->vanodes_begin()->second;
-    NG->getVANodes().clear();
-    NG->getVANodes()[ToF] = VA;
+    DSGraph *G = getDSGraph(*FromF);
+    if (G->getReturnNodes().size() == 1) {
+      // Copy a single function by duplicating its dsgraph
+
+      DSGraph *NG = new DSGraph(getDSGraph(*FromF), GlobalECs, *TypeSS);
+      DSInfo[ToF] = NG;
+
+      // Change the Function* is the returnnodes map to the ToF.
+      DSNodeHandle Ret = NG->retnodes_begin()->second;
+      NG->getReturnNodes().clear();
+      NG->getReturnNodes()[ToF] = Ret;
+
+      // Change the Function* in the vanodes map to the ToF
+      DSNodeHandle VA = NG->vanodes_begin()->second;
+      NG->getVANodes().clear();
+      NG->getVANodes()[ToF] = VA;
+    } else {
+      // A copy request on a function that's part of an SCC, we just map the new function to the same information
+
+      // G is the graph for ToF as well (add it to the SCC)
+      setDSGraph(*ToF,G);
+
+      // Map ToF to the same return/va nodes as FromF
+      G->getReturnNodes()[ToF] = G->getReturnNodes()[FromF];
+      G->getVANodes()[ToF] = G->getVANodes()[FromF];
+    }
+
     return;
   }
   




From bob.wilson at apple.com  Fri Jul  2 12:23:44 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Fri, 02 Jul 2010 17:23:44 -0000
Subject: [llvm-commits] [llvm] r107487 - in /llvm/trunk:
 lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
 lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp test/CodeGen/ARM/vmov.ll
Message-ID: <20100702172344.617432A6C12C@llvm.org>

Author: bwilson
Date: Fri Jul  2 12:23:44 2010
New Revision: 107487

URL: http://llvm.org/viewvc/llvm-project?rev=107487&view=rev
Log:
Fix incorrect asm-printing of some NEON immediates.  Fix weak testcase so
that it checks the immediate values, not just the instructions opcodes.
Radar 8110263.

Modified:
    llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
    llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp
    llvm/trunk/test/CodeGen/ARM/vmov.ll

Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=107487&r1=107486&r2=107487&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Fri Jul  2 12:23:44 2010
@@ -1044,8 +1044,8 @@
     Val = Imm8 << (8 * ByteNum);
   } else if ((OpCmode & 0xe) == 0xc) {
     // 32-bit vector elements, one byte with low bits set
-    unsigned ByteNum = (OpCmode & 0x1);
-    Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (1 - ByteNum)));
+    unsigned ByteNum = 1 + (OpCmode & 0x1);
+    Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum)));
   } else if (OpCmode == 0x1e) {
     // 64-bit vector elements
     for (unsigned ByteNum = 0; ByteNum < 8; ++ByteNum) {

Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp?rev=107487&r1=107486&r2=107487&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Fri Jul  2 12:23:44 2010
@@ -799,8 +799,8 @@
     Val = Imm8 << (8 * ByteNum);
   } else if ((OpCmode & 0xe) == 0xc) {
     // 32-bit vector elements, one byte with low bits set
-    unsigned ByteNum = (OpCmode & 0x1);
-    Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (1 - ByteNum)));
+    unsigned ByteNum = 1 + (OpCmode & 0x1);
+    Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum)));
   } else if (OpCmode == 0x1e) {
     // 64-bit vector elements
     for (unsigned ByteNum = 0; ByteNum < 8; ++ByteNum) {

Modified: llvm/trunk/test/CodeGen/ARM/vmov.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vmov.ll?rev=107487&r1=107486&r2=107487&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vmov.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vmov.ll Fri Jul  2 12:23:44 2010
@@ -2,135 +2,121 @@
 
 define <8 x i8> @v_movi8() nounwind {
 ;CHECK: v_movi8:
-;CHECK: vmov.i8
+;CHECK: vmov.i8 d0, #0x8
 	ret <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
 }
 
 define <4 x i16> @v_movi16a() nounwind {
 ;CHECK: v_movi16a:
-;CHECK: vmov.i16
+;CHECK: vmov.i16 d0, #0x10
 	ret <4 x i16> < i16 16, i16 16, i16 16, i16 16 >
 }
 
-; 0x1000 = 4096
 define <4 x i16> @v_movi16b() nounwind {
 ;CHECK: v_movi16b:
-;CHECK: vmov.i16
+;CHECK: vmov.i16 d0, #0x1000
 	ret <4 x i16> < i16 4096, i16 4096, i16 4096, i16 4096 >
 }
 
 define <2 x i32> @v_movi32a() nounwind {
 ;CHECK: v_movi32a:
-;CHECK: vmov.i32
+;CHECK: vmov.i32 d0, #0x20
 	ret <2 x i32> < i32 32, i32 32 >
 }
 
-; 0x2000 = 8192
 define <2 x i32> @v_movi32b() nounwind {
 ;CHECK: v_movi32b:
-;CHECK: vmov.i32
+;CHECK: vmov.i32 d0, #0x2000
 	ret <2 x i32> < i32 8192, i32 8192 >
 }
 
-; 0x200000 = 2097152
 define <2 x i32> @v_movi32c() nounwind {
 ;CHECK: v_movi32c:
-;CHECK: vmov.i32
+;CHECK: vmov.i32 d0, #0x200000
 	ret <2 x i32> < i32 2097152, i32 2097152 >
 }
 
-; 0x20000000 = 536870912
 define <2 x i32> @v_movi32d() nounwind {
 ;CHECK: v_movi32d:
-;CHECK: vmov.i32
+;CHECK: vmov.i32 d0, #0x20000000
 	ret <2 x i32> < i32 536870912, i32 536870912 >
 }
 
-; 0x20ff = 8447
 define <2 x i32> @v_movi32e() nounwind {
 ;CHECK: v_movi32e:
-;CHECK: vmov.i32
+;CHECK: vmov.i32 d0, #0x20FF
 	ret <2 x i32> < i32 8447, i32 8447 >
 }
 
-; 0x20ffff = 2162687
 define <2 x i32> @v_movi32f() nounwind {
 ;CHECK: v_movi32f:
-;CHECK: vmov.i32
+;CHECK: vmov.i32 d0, #0x20FFFF
 	ret <2 x i32> < i32 2162687, i32 2162687 >
 }
 
-; 0xff0000ff0000ffff = 18374687574888349695
 define <1 x i64> @v_movi64() nounwind {
 ;CHECK: v_movi64:
-;CHECK: vmov.i64
+;CHECK: vmov.i64 d0, #0xFF0000FF0000FFFF
 	ret <1 x i64> < i64 18374687574888349695 >
 }
 
 define <16 x i8> @v_movQi8() nounwind {
 ;CHECK: v_movQi8:
-;CHECK: vmov.i8
+;CHECK: vmov.i8 q0, #0x8
 	ret <16 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
 }
 
 define <8 x i16> @v_movQi16a() nounwind {
 ;CHECK: v_movQi16a:
-;CHECK: vmov.i16
+;CHECK: vmov.i16 q0, #0x10
 	ret <8 x i16> < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
 }
 
-; 0x1000 = 4096
 define <8 x i16> @v_movQi16b() nounwind {
 ;CHECK: v_movQi16b:
-;CHECK: vmov.i16
+;CHECK: vmov.i16 q0, #0x1000
 	ret <8 x i16> < i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096 >
 }
 
 define <4 x i32> @v_movQi32a() nounwind {
 ;CHECK: v_movQi32a:
-;CHECK: vmov.i32
+;CHECK: vmov.i32 q0, #0x20
 	ret <4 x i32> < i32 32, i32 32, i32 32, i32 32 >
 }
 
-; 0x2000 = 8192
 define <4 x i32> @v_movQi32b() nounwind {
 ;CHECK: v_movQi32b:
-;CHECK: vmov.i32
+;CHECK: vmov.i32 q0, #0x2000
 	ret <4 x i32> < i32 8192, i32 8192, i32 8192, i32 8192 >
 }
 
-; 0x200000 = 2097152
 define <4 x i32> @v_movQi32c() nounwind {
 ;CHECK: v_movQi32c:
-;CHECK: vmov.i32
+;CHECK: vmov.i32 q0, #0x200000
 	ret <4 x i32> < i32 2097152, i32 2097152, i32 2097152, i32 2097152 >
 }
 
-; 0x20000000 = 536870912
 define <4 x i32> @v_movQi32d() nounwind {
 ;CHECK: v_movQi32d:
-;CHECK: vmov.i32
+;CHECK: vmov.i32 q0, #0x20000000
 	ret <4 x i32> < i32 536870912, i32 536870912, i32 536870912, i32 536870912 >
 }
 
-; 0x20ff = 8447
 define <4 x i32> @v_movQi32e() nounwind {
 ;CHECK: v_movQi32e:
-;CHECK: vmov.i32
+;CHECK: vmov.i32 q0, #0x20FF
 	ret <4 x i32> < i32 8447, i32 8447, i32 8447, i32 8447 >
 }
 
-; 0x20ffff = 2162687
 define <4 x i32> @v_movQi32f() nounwind {
 ;CHECK: v_movQi32f:
-;CHECK: vmov.i32
+;CHECK: vmov.i32 q0, #0x20FFFF
 	ret <4 x i32> < i32 2162687, i32 2162687, i32 2162687, i32 2162687 >
 }
 
-; 0xff0000ff0000ffff = 18374687574888349695
 define <2 x i64> @v_movQi64() nounwind {
 ;CHECK: v_movQi64:
-;CHECK: vmov.i64
+;CHECK: vmov.i64 q0, #0xFF0000FF0000FFFF
 	ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 >
 }
 




From grosbach at apple.com  Fri Jul  2 12:38:34 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 02 Jul 2010 17:38:34 -0000
Subject: [llvm-commits] [llvm] r107489 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Message-ID: <20100702173834.748DA2A6C12C@llvm.org>

Author: grosbach
Date: Fri Jul  2 12:38:34 2010
New Revision: 107489

URL: http://llvm.org/viewvc/llvm-project?rev=107489&view=rev
Log:
grammar tweaks

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=107489&r1=107488&r2=107489&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Jul  2 12:38:34 2010
@@ -1007,11 +1007,11 @@
                                    NodesLeadingTo);
     }
 
-    // Now that we legalized all of the inputs (which may have inserted
-    // libcalls) create the new CALLSEQ_START node.
+    // Now that we have legalized all of the inputs (which may have inserted
+    // libcalls), create the new CALLSEQ_START node.
     Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
 
-    // Merge in the last call, to ensure that this call start after the last
+    // Merge in the last call to ensure that this call starts after the last
     // call ended.
     if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
       Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,




From grosbach at apple.com  Fri Jul  2 12:42:00 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 02 Jul 2010 17:42:00 -0000
Subject: [llvm-commits] [llvm] r107490 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Message-ID: <20100702174200.2B7BC2A6C12C@llvm.org>

Author: grosbach
Date: Fri Jul  2 12:41:59 2010
New Revision: 107490

URL: http://llvm.org/viewvc/llvm-project?rev=107490&view=rev
Log:
80-column and trailing whitespace cleanup.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=107490&r1=107489&r2=107490&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Jul  2 12:41:59 2010
@@ -134,7 +134,7 @@
   /// whose vector element type is narrower than the original shuffle type.
   /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
   SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
-                                     SDValue N1, SDValue N2, 
+                                     SDValue N1, SDValue N2,
                                      SmallVectorImpl<int> &Mask) const;
 
   bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
@@ -186,8 +186,8 @@
 /// performs the same shuffe in terms of order or result bytes, but on a type
 /// whose vector element type is narrower than the original shuffle type.
 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
-SDValue 
-SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT,  DebugLoc dl, 
+SDValue
+SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT,  DebugLoc dl,
                                                  SDValue N1, SDValue N2,
                                              SmallVectorImpl<int> &Mask) const {
   unsigned NumMaskElts = VT.getVectorNumElements();
@@ -198,12 +198,12 @@
 
   if (NumEltsGrowth == 1)
     return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
-  
+
   SmallVector<int, 8> NewMask;
   for (unsigned i = 0; i != NumMaskElts; ++i) {
     int Idx = Mask[i];
     for (unsigned j = 0; j != NumEltsGrowth; ++j) {
-      if (Idx < 0) 
+      if (Idx < 0)
         NewMask.push_back(-1);
       else
         NewMask.push_back(Idx * NumEltsGrowth + j);
@@ -325,7 +325,8 @@
   bool OperandsLeadToDest = false;
   for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
     OperandsLeadToDest |=     // If an operand leads to Dest, so do we.
-      LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo);
+      LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest,
+                                   NodesLeadingTo);
 
   if (OperandsLeadToDest) {
     NodesLeadingTo.insert(N);
@@ -609,7 +610,7 @@
                       DAG.getConstant(IncrementSize, TLI.getPointerTy()));
     Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
                         SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
-                        LD->isNonTemporal(), MinAlign(Alignment, IncrementSize));
+                        LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
   } else {
     Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
                         SVOffset, NewLoadedVT, LD->isVolatile(),
@@ -618,7 +619,7 @@
                       DAG.getConstant(IncrementSize, TLI.getPointerTy()));
     Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
                         SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
-                        LD->isNonTemporal(), MinAlign(Alignment, IncrementSize));
+                        LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
   }
 
   // aggregate the two parts
@@ -778,7 +779,7 @@
            "Unexpected illegal type!");
 
   for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
-    assert((isTypeLegal(Node->getOperand(i).getValueType()) || 
+    assert((isTypeLegal(Node->getOperand(i).getValueType()) ||
             Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
            "Unexpected illegal type!");
 
@@ -1023,8 +1024,8 @@
     if (Tmp1 != Node->getOperand(0)) {
       SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
       Ops[0] = Tmp1;
-      Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), &Ops[0], Ops.size()),
-                       Result.getResNo());
+      Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), &Ops[0],
+                                              Ops.size()), Result.getResNo());
     }
 
     // Remember that the CALLSEQ_START is legalized.
@@ -1114,7 +1115,7 @@
           const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
           unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
           if (LD->getAlignment() < ABIAlignment){
-            Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), 
+            Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
                                          DAG, TLI);
             Tmp3 = Result.getOperand(0);
             Tmp4 = Result.getOperand(1);
@@ -1230,8 +1231,8 @@
                               ExtraVT, isVolatile, isNonTemporal,
                               MinAlign(Alignment, IncrementSize));
 
-          // Build a factor node to remember that this load is independent of the
-          // other one.
+          // Build a factor node to remember that this load is independent of
+          // the other one.
           Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
                            Hi.getValue(1));
 
@@ -1259,8 +1260,8 @@
                               ExtraVT, isVolatile, isNonTemporal,
                               MinAlign(Alignment, IncrementSize));
 
-          // Build a factor node to remember that this load is independent of the
-          // other one.
+          // Build a factor node to remember that this load is independent of
+          // the other one.
           Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
                            Hi.getValue(1));
 
@@ -1297,10 +1298,12 @@
             // If this is an unaligned load and the target doesn't support it,
             // expand it.
             if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
-              const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
-              unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
+              const Type *Ty =
+                LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
+              unsigned ABIAlignment =
+                TLI.getTargetData()->getABITypeAlignment(Ty);
               if (LD->getAlignment() < ABIAlignment){
-                Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), 
+                Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
                                              DAG, TLI);
                 Tmp1 = Result.getOperand(0);
                 Tmp2 = Result.getOperand(1);
@@ -1326,7 +1329,8 @@
             Tmp2 = LegalizeOp(Load.getValue(1));
             break;
           }
-          assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
+          assert(ExtType != ISD::EXTLOAD &&
+                 "EXTLOAD should always be supported!");
           // Turn the unsupported load into an EXTLOAD followed by an explicit
           // zero/sign extend inreg.
           Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
@@ -1384,7 +1388,7 @@
           // expand it.
           if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
             const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
-            unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
+            unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
             if (ST->getAlignment() < ABIAlignment)
               Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
                                             DAG, TLI);
@@ -1489,7 +1493,7 @@
           // expand it.
           if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
             const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
-            unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
+            unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
             if (ST->getAlignment() < ABIAlignment)
               Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
                                             DAG, TLI);
@@ -1588,7 +1592,7 @@
                                          Node->getOperand(i), Idx, SV, Offset,
                                          EltVT, false, false, 0));
     } else
-      Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, 
+      Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
                                     Node->getOperand(i), Idx, SV, Offset,
                                     false, false, 0));
   }
@@ -2106,7 +2110,8 @@
     SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
     SDValue LoFlt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, LoOr);
     SDValue HiFlt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, HiOr);
-    SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt, TwoP84PlusTwoP52);
+    SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
+                                TwoP84PlusTwoP52);
     return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
   }
 
@@ -2116,11 +2121,11 @@
   if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
     EVT SHVT = TLI.getShiftAmountTy();
 
-    SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, 
+    SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
          DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64));
     SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
          DAG.getConstant(UINT64_C(0x800), MVT::i64));
-    SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, 
+    SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
          DAG.getConstant(UINT64_C(0x7ff), MVT::i64));
     SDValue Ne = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
                    And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
@@ -2687,7 +2692,7 @@
   case ISD::EXTRACT_VECTOR_ELT:
     if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
       // This must be an access of the only element.  Return it.
-      Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0), 
+      Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0),
                          Node->getOperand(0));
     else
       Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
@@ -3139,7 +3144,7 @@
     const TargetData &TD = *TLI.getTargetData();
     unsigned EntrySize =
       DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
-    
+
     Index = DAG.getNode(ISD::MUL, dl, PTy,
                         Index, DAG.getConstant(EntrySize, PTy));
     SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);




From stoklund at 2pi.dk  Fri Jul  2 12:44:57 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Fri, 02 Jul 2010 17:44:57 -0000
Subject: [llvm-commits] [llvm] r107492 - in /llvm/trunk:
 include/llvm/CodeGen/LiveInterval.h lib/CodeGen/InlineSpiller.cpp
Message-ID: <20100702174457.79FBD2A6C12C@llvm.org>

Author: stoklund
Date: Fri Jul  2 12:44:57 2010
New Revision: 107492

URL: http://llvm.org/viewvc/llvm-project?rev=107492&view=rev
Log:
Rematerialize as much as possible before inserting spills and reloads.

This allows us to recognize the common case where all uses could be
rematerialized, and no stack slot allocation is necessary.

If some values could be fully rematerialized, remove them from the live range
before allocating a stack slot for the rest.

Modified:
    llvm/trunk/include/llvm/CodeGen/LiveInterval.h
    llvm/trunk/lib/CodeGen/InlineSpiller.cpp

Modified: llvm/trunk/include/llvm/CodeGen/LiveInterval.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveInterval.h?rev=107492&r1=107491&r2=107492&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/LiveInterval.h (original)
+++ llvm/trunk/include/llvm/CodeGen/LiveInterval.h Fri Jul  2 12:44:57 2010
@@ -439,6 +439,12 @@
       return I == end() ? 0 : &*I;
     }
 
+    /// getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
+    VNInfo *getVNInfoAt(SlotIndex Idx) const {
+      const_iterator I = FindLiveRangeContaining(Idx);
+      return I == end() ? 0 : I->valno;
+    }
+
     /// FindLiveRangeContaining - Return an iterator to the live range that
     /// contains the specified index, or end() if there is none.
     const_iterator FindLiveRangeContaining(SlotIndex Idx) const;

Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/InlineSpiller.cpp?rev=107492&r1=107491&r2=107492&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/InlineSpiller.cpp (original)
+++ llvm/trunk/lib/CodeGen/InlineSpiller.cpp Fri Jul  2 12:44:57 2010
@@ -39,10 +39,17 @@
 
   // Variables that are valid during spill(), but used by multiple methods.
   LiveInterval *li_;
+  std::vector<LiveInterval*> *newIntervals_;
   const TargetRegisterClass *rc_;
   int stackSlot_;
   const SmallVectorImpl<LiveInterval*> *spillIs_;
 
+  // Values of the current interval that can potentially remat.
+  SmallPtrSet<VNInfo*, 8> reMattable_;
+
+  // Values in reMattable_ that failed to remat at some point.
+  SmallPtrSet<VNInfo*, 8> usedValues_;
+
   ~InlineSpiller() {}
 
 public:
@@ -58,7 +65,13 @@
              std::vector<LiveInterval*> &newIntervals,
              SmallVectorImpl<LiveInterval*> &spillIs,
              SlotIndex *earliestIndex);
-  bool reMaterialize(LiveInterval &NewLI, MachineBasicBlock::iterator MI);
+
+private:
+  bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx,
+                          SlotIndex UseIdx);
+  bool reMaterializeFor(MachineBasicBlock::iterator MI);
+  void reMaterializeAll();
+
   bool foldMemoryOperand(MachineBasicBlock::iterator MI,
                          const SmallVectorImpl<unsigned> &Ops);
   void insertReload(LiveInterval &NewLI, MachineBasicBlock::iterator MI);
@@ -75,79 +88,180 @@
 }
 }
 
-/// reMaterialize - Attempt to rematerialize li_->reg before MI instead of
+/// allUsesAvailableAt - Return true if all registers used by OrigMI at
+/// OrigIdx are also available with the same value at UseIdx.
+bool InlineSpiller::allUsesAvailableAt(const MachineInstr *OrigMI,
+                                       SlotIndex OrigIdx,
+                                       SlotIndex UseIdx) {
+  OrigIdx = OrigIdx.getUseIndex();
+  UseIdx = UseIdx.getUseIndex();
+  for (unsigned i = 0, e = OrigMI->getNumOperands(); i != e; ++i) {
+    const MachineOperand &MO = OrigMI->getOperand(i);
+    if (!MO.isReg() || !MO.getReg() || MO.getReg() == li_->reg)
+      continue;
+    // Reserved registers are OK.
+    if (MO.isUndef() || !lis_.hasInterval(MO.getReg()))
+      continue;
+    // We don't want to move any defs.
+    if (MO.isDef())
+      return false;
+    // We cannot depend on virtual registers in spillIs_. They will be spilled.
+    for (unsigned si = 0, se = spillIs_->size(); si != se; ++si)
+      if ((*spillIs_)[si]->reg == MO.getReg())
+        return false;
+
+    LiveInterval &LI = lis_.getInterval(MO.getReg());
+    const VNInfo *OVNI = LI.getVNInfoAt(OrigIdx);
+    if (!OVNI)
+      continue;
+    if (OVNI != LI.getVNInfoAt(UseIdx))
+      return false;
+  }
+  return true;
+}
+
+/// reMaterializeFor - Attempt to rematerialize li_->reg before MI instead of
 /// reloading it.
-bool InlineSpiller::reMaterialize(LiveInterval &NewLI,
-                                  MachineBasicBlock::iterator MI) {
+bool InlineSpiller::reMaterializeFor(MachineBasicBlock::iterator MI) {
   SlotIndex UseIdx = lis_.getInstructionIndex(MI).getUseIndex();
-  LiveRange *LR = li_->getLiveRangeContaining(UseIdx);
-  if (!LR) {
-    DEBUG(dbgs() << "\tundef at " << UseIdx << ", adding <undef> flags.\n");
+  VNInfo *OrigVNI = li_->getVNInfoAt(UseIdx);
+  if (!OrigVNI) {
+    DEBUG(dbgs() << "\tadding <undef> flags: ");
     for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
       MachineOperand &MO = MI->getOperand(i);
       if (MO.isReg() && MO.isUse() && MO.getReg() == li_->reg)
         MO.setIsUndef();
     }
+    DEBUG(dbgs() << UseIdx << '\t' << *MI);
     return true;
   }
-
-  // Find the instruction that defined this value of li_->reg.
-  if (!LR->valno->isDefAccurate())
+  if (!reMattable_.count(OrigVNI)) {
+    DEBUG(dbgs() << "\tusing non-remat valno " << OrigVNI->id << ": "
+                 << UseIdx << '\t' << *MI);
     return false;
-  SlotIndex OrigDefIdx = LR->valno->def;
-  MachineInstr *OrigDefMI = lis_.getInstructionFromIndex(OrigDefIdx);
-  if (!OrigDefMI)
-    return false;
-
-  // FIXME: Provide AliasAnalysis argument.
-  if (!tii_.isTriviallyReMaterializable(OrigDefMI))
+  }
+  MachineInstr *OrigMI = lis_.getInstructionFromIndex(OrigVNI->def);
+  if (!allUsesAvailableAt(OrigMI, OrigVNI->def, UseIdx)) {
+    usedValues_.insert(OrigVNI);
+    DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << *MI);
     return false;
+  }
 
-  // A rematerializable instruction may be using other virtual registers.
-  // Make sure they are available at the new location.
-  for (unsigned i = 0, e = OrigDefMI->getNumOperands(); i != e; ++i) {
-    MachineOperand &MO = OrigDefMI->getOperand(i);
-    if (!MO.isReg() || !MO.getReg() || MO.getReg() == li_->reg)
-      continue;
-    // Reserved physregs are OK. Others are not (probably from coalescing).
-    if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
-      if (reserved_.test(MO.getReg()))
-        continue;
-      else
+  // If the instruction also writes li_->reg, it had better not require the same
+  // register for uses and defs.
+  bool Reads, Writes;
+  SmallVector<unsigned, 8> Ops;
+  tie(Reads, Writes) = MI->readsWritesVirtualRegister(li_->reg, &Ops);
+  if (Writes) {
+    for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
+      MachineOperand &MO = MI->getOperand(Ops[i]);
+      if (MO.isUse() ? MI->isRegTiedToDefOperand(Ops[i]) : MO.getSubReg()) {
+        usedValues_.insert(OrigVNI);
+        DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << *MI);
         return false;
+      }
     }
-    // We don't want to move any virtual defs.
-    if (MO.isDef())
-      return false;
-    // We have a use of a virtual register other than li_->reg.
-    if (MO.isUndef())
-      continue;
-    // We cannot depend on virtual registers in spillIs_. They will be spilled.
-    for (unsigned si = 0, se = spillIs_->size(); si != se; ++si)
-      if ((*spillIs_)[si]->reg == MO.getReg())
-        return false;
-
-    // Is the register available here with the same value as at OrigDefMI?
-    LiveInterval &ULI = lis_.getInterval(MO.getReg());
-    LiveRange *HereLR = ULI.getLiveRangeContaining(UseIdx);
-    if (!HereLR)
-      return false;
-    LiveRange *DefLR = ULI.getLiveRangeContaining(OrigDefIdx.getUseIndex());
-    if (!DefLR || DefLR->valno != HereLR->valno)
-      return false;
   }
 
-  // Finally we can rematerialize OrigDefMI before MI.
+  // Alocate a new register for the remat.
+  unsigned NewVReg = mri_.createVirtualRegister(rc_);
+  vrm_.grow();
+  LiveInterval &NewLI = lis_.getOrCreateInterval(NewVReg);
+  NewLI.markNotSpillable();
+  newIntervals_->push_back(&NewLI);
+
+  // Finally we can rematerialize OrigMI before MI.
   MachineBasicBlock &MBB = *MI->getParent();
-  tii_.reMaterialize(MBB, MI, NewLI.reg, 0, OrigDefMI, tri_);
-  SlotIndex DefIdx = lis_.InsertMachineInstrInMaps(--MI).getDefIndex();
-  DEBUG(dbgs() << "\tremat:  " << DefIdx << '\t' << *MI);
+  tii_.reMaterialize(MBB, MI, NewLI.reg, 0, OrigMI, tri_);
+  MachineBasicBlock::iterator RematMI = MI;
+  SlotIndex DefIdx = lis_.InsertMachineInstrInMaps(--RematMI).getDefIndex();
+  DEBUG(dbgs() << "\tremat:  " << DefIdx << '\t' << *RematMI);
+
+  // Replace operands
+  for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
+    MachineOperand &MO = MI->getOperand(Ops[i]);
+    if (MO.isReg() && MO.isUse() && MO.getReg() == li_->reg) {
+      MO.setReg(NewVReg);
+      MO.setIsKill();
+    }
+  }
+  DEBUG(dbgs() << "\t        " << UseIdx << '\t' << *MI);
+
   VNInfo *DefVNI = NewLI.getNextValue(DefIdx, 0, true,
                                        lis_.getVNInfoAllocator());
   NewLI.addRange(LiveRange(DefIdx, UseIdx.getDefIndex(), DefVNI));
+  DEBUG(dbgs() << "\tinterval: " << NewLI << '\n');
   return true;
 }
 
+/// reMaterializeAll - Try to rematerialize as many uses of li_ as possible,
+/// and trim the live ranges after.
+void InlineSpiller::reMaterializeAll() {
+  // Do a quick scan of the interval values to find if any are remattable.
+  reMattable_.clear();
+  usedValues_.clear();
+  for (LiveInterval::const_vni_iterator I = li_->vni_begin(),
+       E = li_->vni_end(); I != E; ++I) {
+    VNInfo *VNI = *I;
+    if (VNI->isUnused() || !VNI->isDefAccurate())
+      continue;
+    MachineInstr *DefMI = lis_.getInstructionFromIndex(VNI->def);
+    if (!DefMI || !tii_.isTriviallyReMaterializable(DefMI))
+      continue;
+    reMattable_.insert(VNI);
+  }
+
+  // Often, no defs are remattable.
+  if (reMattable_.empty())
+    return;
+
+  // Try to remat before all uses of li_->reg.
+  bool anyRemat = false;
+  for (MachineRegisterInfo::use_nodbg_iterator
+       RI = mri_.use_nodbg_begin(li_->reg);
+       MachineInstr *MI = RI.skipInstruction();)
+     anyRemat |= reMaterializeFor(MI);
+
+  if (!anyRemat)
+    return;
+
+  // Remove any values that were completely rematted.
+  bool anyRemoved = false;
+  for (SmallPtrSet<VNInfo*, 8>::iterator I = reMattable_.begin(),
+       E = reMattable_.end(); I != E; ++I) {
+    VNInfo *VNI = *I;
+    if (VNI->hasPHIKill() || usedValues_.count(VNI))
+      continue;
+    MachineInstr *DefMI = lis_.getInstructionFromIndex(VNI->def);
+    DEBUG(dbgs() << "\tremoving dead def: " << VNI->def << '\t' << *DefMI);
+    lis_.RemoveMachineInstrFromMaps(DefMI);
+    vrm_.RemoveMachineInstrFromMaps(DefMI);
+    DefMI->eraseFromParent();
+    li_->removeValNo(VNI);
+    anyRemoved = true;
+  }
+
+  if (!anyRemoved)
+    return;
+
+  // Removing values may cause debug uses where li_ is not live.
+  for (MachineRegisterInfo::use_iterator
+       RI = mri_.use_begin(li_->reg), RE = mri_.use_end(); RI != RE;) {
+    MachineOperand &MO = RI.getOperand();
+    MachineInstr *MI = MO.getParent();
+    ++RI;
+    SlotIndex UseIdx = lis_.getInstructionIndex(MI).getUseIndex();
+    DEBUG(dbgs() << "\tremaining use: " << UseIdx << '\t' << *MI);
+    if (li_->liveAt(UseIdx))
+      continue;
+    assert(MI->isDebugValue() && "Remaining non-debug use after remat dead.");
+    if (li_->empty())
+      MO.setIsUndef();
+    else
+      MO.setReg(0);
+  }
+}
+
 /// foldMemoryOperand - Try folding stack slot references in Ops into MI.
 /// Return true on success, and MI will be erased.
 bool InlineSpiller::foldMemoryOperand(MachineBasicBlock::iterator MI,
@@ -218,10 +332,18 @@
   assert(!li->isStackSlot() && "Trying to spill a stack slot.");
 
   li_ = li;
+  newIntervals_ = &newIntervals;
   rc_ = mri_.getRegClass(li->reg);
-  stackSlot_ = vrm_.assignVirt2StackSlot(li->reg);
   spillIs_ = &spillIs;
 
+  reMaterializeAll();
+
+  // Remat may handle everything.
+  if (li_->empty())
+    return;
+
+  stackSlot_ = vrm_.assignVirt2StackSlot(li->reg);
+
   // Iterate over instructions using register.
   for (MachineRegisterInfo::reg_iterator RI = mri_.reg_begin(li->reg);
        MachineInstr *MI = RI.skipInstruction();) {
@@ -231,6 +353,10 @@
     SmallVector<unsigned, 8> Ops;
     tie(Reads, Writes) = MI->readsWritesVirtualRegister(li->reg, &Ops);
 
+    // Attempt to fold memory ops.
+    if (foldMemoryOperand(MI, Ops))
+      continue;
+
     // Allocate interval around instruction.
     // FIXME: Infer regclass from instruction alone.
     unsigned NewVReg = mri_.createVirtualRegister(rc_);
@@ -238,14 +364,7 @@
     LiveInterval &NewLI = lis_.getOrCreateInterval(NewVReg);
     NewLI.markNotSpillable();
 
-    // Attempt remat instead of reload.
-    bool NeedsReload = Reads && !reMaterialize(NewLI, MI);
-
-    // Attempt to fold memory ops.
-    if (NewLI.empty() && foldMemoryOperand(MI, Ops))
-      continue;
-
-    if (NeedsReload)
+    if (Reads)
       insertReload(NewLI, MI);
 
     // Rewrite instruction operands.




From dalej at apple.com  Fri Jul  2 12:52:51 2010
From: dalej at apple.com (Dale Johannesen)
Date: Fri, 02 Jul 2010 17:52:51 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r107493 -
	/llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/
Message-ID: <20100702175251.DC5562A6C12C@llvm.org>

Author: johannes
Date: Fri Jul  2 12:52:51 2010
New Revision: 107493

URL: http://llvm.org/viewvc/llvm-project?rev=107493&view=rev
Log:
Run these tests on x86-64 Darwin.


Modified:
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-10.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-11.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-12.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-13.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-14.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-15.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-16.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-17.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-18.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-19.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-20.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-21.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-22.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-23.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-24.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-25.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-26.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-27.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-28.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-30.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-31.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-32.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-33.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-34.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-35.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-36.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-37.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-38.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-39.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-41.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-42.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-43.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-44.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-45.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-46.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-47.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-50.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-51.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-52.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-53.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-54.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-55.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-56.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-57.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-58.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-59.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-60.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-61.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-64.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-66.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-7.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-8.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-function-19.C

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-10.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-10.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-10.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-10.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { "-fasm-blocks" } } */
 /* Radar 4211954 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-11.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-11.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-11.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-11.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4211971 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-12.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-12.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-12.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-12.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4259442 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-13.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-13.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-13.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-13.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-require-effective-target ilp32 } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4259442 */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-14.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-14.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-14.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-14.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4271787 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-15.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-15.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-15.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-15.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4248159 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-16.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-16.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-16.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-16.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4273781 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-17.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-17.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-17.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-17.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* APPLE LOCAL x86_64 */
 /* { dg-require-effective-target ilp32 } */
 /* { dg-options { -fasm-blocks -msse3 -O2 } } */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-18.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-18.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-18.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-18.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* APPLE LOCAL x86_64 */
 /* { dg-require-effective-target ilp32 } */
 /* { dg-options { -fasm-blocks -msse3 -O2 } } */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-19.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-19.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-19.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-19.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4236553 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-20.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-20.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-20.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-20.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 
 void foo() {

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-21.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-21.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-21.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-21.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -m64 -fasm-blocks -msse3 } } */
 /* Radar 4249602 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-22.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-22.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-22.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-22.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4248205 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-23.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-23.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-23.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-23.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4248139 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-24.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-24.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-24.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-24.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* APPLE LOCAL x86_64 */
 /* { dg-require-effective-target ilp32 } */
 /* { dg-options { -fasm-blocks -msse3 } } */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-25.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-25.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-25.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-25.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* APPLE LOCAL x86_64 */
 /* { dg-require-effective-target ilp32 } */
 /* { dg-options { -fasm-blocks -msse3 } } */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-26.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-26.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-26.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-26.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4300138 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-27.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-27.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-27.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-27.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 
 void foo() {

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-28.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-28.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-28.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-28.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 -O } } */
 /* Radar 4300156 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-30.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-30.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-30.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-30.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Shouldn't be necessary, but it doesn't work yet.  */
 /* { dg-require-effective-target ilp32 } */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-31.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-31.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-31.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-31.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* APPLE LOCAL x86_64 */
 /* { dg-require-effective-target ilp32 } */
 /* { dg-options { -fasm-blocks -msse3 -mdynamic-no-pic } } */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-32.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-32.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-32.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-32.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* APPLE LOCAL x86_64 */
 /* { dg-require-effective-target ilp32 } */
 /* { dg-options { -fasm-blocks -msse3 } } */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-33.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-33.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-33.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-33.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* APPLE LOCAL x86_64 */
 /* { dg-require-effective-target ilp32 } */
 /* { dg-options { -fasm-blocks -msse3 } } */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-34.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-34.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-34.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-34.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4363798 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-35.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-35.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-35.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-35.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* APPLE LOCAL x86_64 */
 /* { dg-require-effective-target ilp32 } */
 /* { dg-options { -fasm-blocks -msse3 -mdynamic-no-pic } } */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-36.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-36.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-36.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-36.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* APPLE LOCAL x86_64 */
 /* { dg-require-effective-target ilp32 } */
 /* { dg-options { -fasm-blocks -msse3 } } */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-37.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-37.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-37.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-37.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 -O1 } } */
 /* Radar 4433955 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-38.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-38.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-38.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-38.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4433955 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-39.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-39.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-39.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-39.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4432782 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-41.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-41.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-41.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-41.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* APPLE LOCAL x86_64 */
 /* { dg-require-effective-target ilp32 } */
 /* { dg-options { -fasm-blocks -msse3 } } */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-42.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-42.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-42.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-42.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4399388 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-43.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-43.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-43.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-43.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4415216 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-44.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-44.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-44.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-44.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4443942 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-45.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-45.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-45.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-45.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* APPLE LOCAL x86_64 */
 /* { dg-require-effective-target ilp32 } */
 /* { dg-options { -fasm-blocks -msse3 } } */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-46.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-46.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-46.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-46.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do compile { target i?86*-*-darwin* } } */
+/* { dg-do compile { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4419735 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-47.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-47.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-47.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-47.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4298040 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-50.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-50.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-50.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-50.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* APPLE LOCAL x86_64 */
 /* { dg-require-effective-target ilp32 } */
 /* { dg-options { -fasm-blocks -msse3 } } */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-51.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-51.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-51.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-51.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks } } */
 /* Radar 4505697 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-52.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-52.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-52.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-52.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -O } } */
 /* Radar 4527214 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-53.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-53.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-53.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-53.C Fri Jul  2 12:52:51 2010
@@ -1,4 +1,4 @@
-/* { dg-do compile { target i?86*-*-darwin* } } */
+/* { dg-do compile { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks } } */
 /* { dg-final { scan-assembler "0\\\(%eax,%eax,2\\\), %edx" } } */
 /* Radar 4560301 */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-54.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-54.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-54.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-54.C Fri Jul  2 12:52:51 2010
@@ -1,4 +1,4 @@
-/* { dg-do compile { target i?86*-*-darwin* } } */
+/* { dg-do compile { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* APPLE LOCAL x86_64 */
 /* { dg-require-effective-target ilp32 } */
 /* { dg-options { -fasm-blocks -msse3 } } */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-55.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-55.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-55.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-55.C Fri Jul  2 12:52:51 2010
@@ -1,4 +1,4 @@
-/* { dg-do compile { target i?86*-*-darwin* } } */
+/* { dg-do compile { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* APPLE LOCAL x86_64 */
 /* { dg-require-effective-target ilp32 } */
 /* { dg-options { -fasm-blocks -msse3 -mdynamic-no-pic } } */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-56.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-56.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-56.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-56.C Fri Jul  2 12:52:51 2010
@@ -1,4 +1,4 @@
-/* { dg-do compile { target i?86*-*-darwin* } } */
+/* { dg-do compile { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks } } */
 /* Radar 4653181 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-57.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-57.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-57.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-57.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do run { target i?86*-*-darwin* } } */
+/* { dg-do run { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-require-effective-target ilp32 } */
 /* { dg-options { -fasm-blocks -msse3 } } */
 /* Radar 4682427 */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-58.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-58.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-58.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-58.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -m64 -fasm-blocks -msse3 } } */
 /* Radar 4699524 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-59.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-59.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-59.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-59.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do compile { target i?86*-*-darwin* } } */
+/* { dg-do compile { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 -O2 } } */
 /* { dg-require-effective-target ilp32 } */
 /* { dg-final { scan-assembler "-\(40|44\)\\\(%ebp,%edx,2\\\), %ebx" } } */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-60.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-60.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-60.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-60.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do compile { target i?86*-*-darwin* } } */
+/* { dg-do compile { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -msse3 -O2 } } */
 /* { dg-final { scan-assembler "movsl \n" } } */
 /* Radar 4736998 */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-61.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-61.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-61.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-61.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do compile { target i?86*-*-darwin* } } */
+/* { dg-do compile { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks } } */
 /* Radar 4739936 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-64.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-64.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-64.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-64.C Fri Jul  2 12:52:51 2010
@@ -1,4 +1,4 @@
-/* { dg-do compile { target i?86*-*-darwin* } } */
+/* { dg-do compile { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks -O2 } } */
 /* Radar 5315594 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-66.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-66.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-66.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-66.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks 6276214 */
-/* { dg-do compile { target i?86*-*-darwin* } } */
+/* { dg-do compile { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { -fasm-blocks } } */
 /* Radar 6276214 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-7.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-7.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-7.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-7.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* APPLE LOCAL x86_64 */
 /* { dg-require-effective-target ilp32 } */
 /* { dg-options { "-fasm-blocks" } } */

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-8.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-block-8.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-8.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-block-8.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin* } } */
 /* { dg-options { "-fasm-blocks" } } */
 /* Radar 4211947 */
 

Modified: llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-function-19.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.apple/asm-function-19.C?rev=107493&r1=107492&r2=107493&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-function-19.C (original)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.apple/asm-function-19.C Fri Jul  2 12:52:51 2010
@@ -1,5 +1,5 @@
 /* APPLE LOCAL file CW asm blocks */
-/* { dg-do assemble { target i?86*-*-darwin* } } */
+/* { dg-do assemble { target i?86*-*-darwin* x86_64*-*-darwin*} } */
 /* { dg-options { -fasm-blocks -msse3 -O3 -Winline -Wall } } */
 /* Radar 4381918 */
 




From bruno.cardoso at gmail.com  Fri Jul  2 13:11:36 2010
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Fri, 2 Jul 2010 11:11:36 -0700
Subject: [llvm-commits] [llvm] r107438 -
	/llvm/trunk/lib/Target/X86/X86InstrSSE.td
In-Reply-To: <5B6FD7BD-BA5A-4871-9555-786F098C5700@apple.com>
References: <20100701223318.B227C2A6C12C@llvm.org>
	<5B6FD7BD-BA5A-4871-9555-786F098C5700@apple.com>
Message-ID: <AANLkTimY32ZcjT59bZP9TckStuoW7WVIRNk__21yTXem@mail.gmail.com>

On Thu, Jul 1, 2010 at 10:01 PM, Eric Christopher <echristo at apple.com> wrote:
>
> On Jul 1, 2010, at 3:33 PM, Bruno Cardoso Lopes wrote:
>
>> Shrink down SSE3 code by some multiclass refactoring - 1st part
>
> I love all the shrinking and refactoring, but unfortunately the refactored stuff isn't quite as obvious as the great stuff you've been putting in - mind if I bug you for a few more comments over the big multiclasses?
>
> -eric

No problem Eric, ideas to improve are always welcome! :)
It's a work in progress tough, so you could have hit something that
isn't ready yet.

-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc


From gohman at apple.com  Fri Jul  2 13:41:32 2010
From: gohman at apple.com (Dan Gohman)
Date: Fri, 02 Jul 2010 18:41:32 -0000
Subject: [llvm-commits] [llvm] r107495 - in /llvm/trunk/docs:
	AliasAnalysis.html LangRef.html
Message-ID: <20100702184132.A27832A6C12C@llvm.org>

Author: djg
Date: Fri Jul  2 13:41:32 2010
New Revision: 107495

URL: http://llvm.org/viewvc/llvm-project?rev=107495&view=rev
Log:
Reword the definition of the noalias attribute. The intention is for
the noalias argument on function attributes be usable to model the
C99 restrict keyword on arguments, and to allow AliasAnalysis to
consider a noalias-attributed argument to be an "identified object".

To support this, refactor a new "based on" concept out of the current
pointer aliasing "associated" concept. This "based on" concept is very
similar to (though it is not identical with) the "based on" concept
in C99.

Also, reword the definition of NoAlias to more closely describe the
concept that the optimizer uses.

Modified:
    llvm/trunk/docs/AliasAnalysis.html
    llvm/trunk/docs/LangRef.html

Modified: llvm/trunk/docs/AliasAnalysis.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/AliasAnalysis.html?rev=107495&r1=107494&r2=107495&view=diff
==============================================================================
--- llvm/trunk/docs/AliasAnalysis.html (original)
+++ llvm/trunk/docs/AliasAnalysis.html Fri Jul  2 13:41:32 2010
@@ -192,12 +192,14 @@
 </div>
 
 <div class="doc_text">
-<p>The NoAlias response is used when the two pointers refer to distinct objects,
-regardless of whether the pointers compare equal.  For example, freed pointers
-don't alias any pointers that were allocated afterwards.  As a degenerate case,
-pointers returned by malloc(0) have no bytes for an object, and are considered
-NoAlias even when malloc returns the same pointer.  The same rule applies to
-NULL pointers.</p>
+<p>The NoAlias response may be used when there is never an immediate dependence
+between any memory reference <i>based</i> on one pointer and any memory
+reference <i>based</i> the other. The most obvious example is when the two
+pointers point to non-overlapping memory ranges. Another is when the two
+pointers are only ever used for reading memory. Another is when the memory is
+freed and reallocated between accesses through one pointer and accesses through
+the other -- in this case, there is a dependence, but it's mediated by the free
+and reallocation.</p>
 
 <p>The MayAlias response is used whenever the two pointers might refer to the
 same object.  If the two memory objects overlap, but do not start at the same

Modified: llvm/trunk/docs/LangRef.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=107495&r1=107494&r2=107495&view=diff
==============================================================================
--- llvm/trunk/docs/LangRef.html (original)
+++ llvm/trunk/docs/LangRef.html Fri Jul  2 13:41:32 2010
@@ -1051,14 +1051,13 @@
       for return values. </dd>
 
   <dt><tt><b>noalias</b></tt></dt>
-  <dd>This indicates that the pointer does not alias any global or any other
-      parameter.  The caller is responsible for ensuring that this is the
-      case. On a function return value, <tt>noalias</tt> additionally indicates
-      that the pointer does not alias any other pointers visible to the
-      caller. For further details, please see the discussion of the NoAlias
-      response in
-      <a href="http://llvm.org/docs/AliasAnalysis.html#MustMayNo">alias
-      analysis</a>.</dd>
+  <dd>This indicates that pointer values
+      <a href="#pointeraliasing"><i>based</i></a> on the argument or return
+      value do not alias pointer values which are not <i>based</i> on it.
+      The caller shares the responsibility with the callee for ensuring that
+      these requirements are met.
+      For further details, please see the discussion of the NoAlias response in
+      <a href="AliasAnalysis.html#MustMayNo">alias analysis</a>.</dd>
 
   <dt><tt><b>nocapture</b></tt></dt>
   <dd>This indicates that the callee does not make any copies of the pointer
@@ -1367,29 +1366,41 @@
 according to the following rules:</p>
 
 <ul>
-  <li>A pointer value formed from a
-      <tt><a href="#i_getelementptr">getelementptr</a></tt> instruction
-      is associated with the addresses associated with the first operand
-      of the <tt>getelementptr</tt>.</li>
+  <li>A pointer value is associated with the addresses associated with
+      any value it is <i>based</i> on.
   <li>An address of a global variable is associated with the address
       range of the variable's storage.</li>
   <li>The result value of an allocation instruction is associated with
       the address range of the allocated storage.</li>
   <li>A null pointer in the default address-space is associated with
       no address.</li>
-  <li>A pointer value formed by an
-      <tt><a href="#i_inttoptr">inttoptr</a></tt> is associated with all
-      address ranges of all pointer values that contribute (directly or
-      indirectly) to the computation of the pointer's value.</li>
-  <li>The result value of a
-      <tt><a href="#i_bitcast">bitcast</a></tt> is associated with all
-      addresses associated with the operand of the <tt>bitcast</tt>.</li>
   <li>An integer constant other than zero or a pointer value returned
       from a function not defined within LLVM may be associated with address
       ranges allocated through mechanisms other than those provided by
       LLVM. Such ranges shall not overlap with any ranges of addresses
       allocated by mechanisms provided by LLVM.</li>
-  </ul>
+</ul>
+
+<p>A pointer value is <i>based</i> on another pointer value according
+   to the following rules:</p>
+
+<ul>
+  <li>A pointer value formed from a
+      <tt><a href="#i_getelementptr">getelementptr</a></tt> operation
+      is <i>based</i> on the first operand of the <tt>getelementptr</tt>.</li>
+  <li>The result value of a
+      <tt><a href="#i_bitcast">bitcast</a></tt> is <i>based</i> on the operand
+      of the <tt>bitcast</tt>.</li>
+  <li>A pointer value formed by an
+      <tt><a href="#i_inttoptr">inttoptr</a></tt> is <i>based</i> on all
+      pointer values that contribute (directly or indirectly) to the
+      computation of the pointer's value.</li>
+  <li>The "<i>based</i> on" relationship is transitive.</li>
+</ul>
+
+<p>Note that this definition of <i>"based"</i> is intentionally
+   similar to the definition of <i>"based"</i> in C99, though it is
+   slightly weaker.</p>
 
 <p>LLVM IR does not associate types with memory. The result type of a
 <tt><a href="#i_load">load</a></tt> merely indicates the size and




From gohman at apple.com  Fri Jul  2 13:43:05 2010
From: gohman at apple.com (Dan Gohman)
Date: Fri, 02 Jul 2010 18:43:05 -0000
Subject: [llvm-commits] [llvm] r107496 -
	/llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp
Message-ID: <20100702184305.CD6C82A6C12C@llvm.org>

Author: djg
Date: Fri Jul  2 13:43:05 2010
New Revision: 107496

URL: http://llvm.org/viewvc/llvm-project?rev=107496&view=rev
Log:
Don't claim to preserve AliasAnalysis. First, this is doesn't actually
have any effect, and second, deleting stores can potentially invalidate
an AliasAnalysis, and there's currently no notification for this.

Modified:
    llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp?rev=107496&r1=107495&r2=107496&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp Fri Jul  2 13:43:05 2010
@@ -74,7 +74,6 @@
       AU.addRequired<AliasAnalysis>();
       AU.addRequired<MemoryDependenceAnalysis>();
       AU.addPreserved<DominatorTree>();
-      AU.addPreserved<AliasAnalysis>();
       AU.addPreserved<MemoryDependenceAnalysis>();
     }
 




From ggreif at gmail.com  Fri Jul  2 14:08:46 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Fri, 02 Jul 2010 19:08:46 -0000
Subject: [llvm-commits] [llvm] r107498 -
	/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
Message-ID: <20100702190847.02E3B2A6C12C@llvm.org>

Author: ggreif
Date: Fri Jul  2 14:08:46 2010
New Revision: 107498

URL: http://llvm.org/viewvc/llvm-project?rev=107498&view=rev
Log:
use ArgOperand API

Modified:
    llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp

Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp?rev=107498&r1=107497&r2=107498&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp (original)
+++ llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Fri Jul  2 14:08:46 2010
@@ -1399,8 +1399,8 @@
     if (call->getNumArgOperands() > 1) {
       Out << "std::vector<Value*> " << iName << "_params;";
       nl(Out);
-      for (unsigned i = 1; i < call->getNumOperands(); ++i) {
-        Out << iName << "_params.push_back(" << opNames[i] << ");";
+      for (unsigned i = 0; i < call->getNumArgOperands(); ++i) {
+        Out << iName << "_params.push_back(" << opNames[i+1] << ");";
         nl(Out);
       }
       Out << "CallInst* " << iName << " = CallInst::Create("




From criswell at cs.uiuc.edu  Fri Jul  2 14:15:16 2010
From: criswell at cs.uiuc.edu (John Criswell)
Date: Fri, 2 Jul 2010 14:15:16 -0500
Subject: [llvm-commits] CVS: llvm-www/safecode/menagerie/other.html
Message-ID: <201007021915.o62JFGkW013352@maute.cs.uiuc.edu>



Changes in directory llvm-www/safecode/menagerie:

other.html updated: 1.6 -> 1.7
---
Log message:

Added Professor Iyer's Address Obfuscation paper.


---
Diffs of the changes:  (+15 -0)

 other.html |   15 +++++++++++++++
 1 file changed, 15 insertions(+)


Index: llvm-www/safecode/menagerie/other.html
diff -u llvm-www/safecode/menagerie/other.html:1.6 llvm-www/safecode/menagerie/other.html:1.7
--- llvm-www/safecode/menagerie/other.html:1.6	Sat Jun 26 00:51:09 2010
+++ llvm-www/safecode/menagerie/other.html	Fri Jul  2 14:15:04 2010
@@ -170,6 +170,21 @@
         </li>
 
         <br>
+
+        <li><a href="http://seclab.cs.sunysb.edu/seclab/pubs/usenix03.pdf">
+        <b>
+        Address Obfuscation: An Efficient Approach to Combat a Broad Range of
+        Memory Error Exploits
+        </b></a>
+        <br>
+        Sandeep Bhatkar, Daniel DuVarney and R. Sekar
+        <br>
+        <i>Proceedings of the Twelfth Usenix Security Symposium</i>,
+        Washington, D.C., August 2003.
+        <br>
+        </li>
+
+        <br>
         <li><a href="http://www.usenix.org/publications/library/proceedings/sec98/full_papers/cowan/cowan.pdf">
         <b>
         StackGuard: Automatic Adaptive Detection and Prevention of





From criswell at cs.uiuc.edu  Fri Jul  2 14:15:51 2010
From: criswell at cs.uiuc.edu (John Criswell)
Date: Fri, 2 Jul 2010 14:15:51 -0500
Subject: [llvm-commits] CVS: llvm-www/safecode/menagerie/attacks.html
Message-ID: <201007021915.o62JFpVV013416@maute.cs.uiuc.edu>



Changes in directory llvm-www/safecode/menagerie:

attacks.html updated: 1.6 -> 1.7
---
Log message:

Added the paper on buffer overread attacks.


---
Diffs of the changes:  (+16 -0)

 attacks.html |   16 ++++++++++++++++
 1 file changed, 16 insertions(+)


Index: llvm-www/safecode/menagerie/attacks.html
diff -u llvm-www/safecode/menagerie/attacks.html:1.6 llvm-www/safecode/menagerie/attacks.html:1.7
--- llvm-www/safecode/menagerie/attacks.html:1.6	Mon Jun 21 10:54:29 2010
+++ llvm-www/safecode/menagerie/attacks.html	Fri Jul  2 14:15:39 2010
@@ -80,6 +80,7 @@
 			<a name="Papers"></a>
 			<h1>Memory Safety Exploit Papers</h1>
 				<ul>
+
         <li>
         <a href="https://www.usenix.org/events/sec09/tech/full_papers/hund.pdf">
         <b>
@@ -96,6 +97,21 @@
         <br>
 
         <li>
+        <a href="http://portal.acm.org/citation.cfm?id=1519145">
+        <b>
+        Breaking the Memory Secrecy Assumption</b></a>
+        <br>
+        Raoul Strackx, Yves Younan, Pieter Philippaerts, Frank Piessens,
+        Sven Lachmund, and Thomas Walter
+        <br>
+        <i>Proceedings of the Second European Workshop on System Security</i>,
+        Nuremburg, Germany, March 2009.
+        <br>
+        </li>
+
+        <br>
+
+        <li>
         <a href="http://portal.acm.org/citation.cfm?id=1315313&dl=GUIDE&coll=GUIDE&CFID=92170544&CFTOKEN=45753783#">
         <b>
         The Geometry of Innocent Flesh on the Bone: Return-into-libc without





From criswell at cs.uiuc.edu  Fri Jul  2 14:16:47 2010
From: criswell at cs.uiuc.edu (John Criswell)
Date: Fri, 2 Jul 2010 14:16:47 -0500
Subject: [llvm-commits] CVS: llvm-www/safecode/menagerie/memsafety.html
Message-ID: <201007021916.o62JGloj013486@maute.cs.uiuc.edu>



Changes in directory llvm-www/safecode/menagerie:

memsafety.html updated: 1.7 -> 1.8
---
Log message:

Added papers on run-time type checking.
Added the Valgrind bounds-checking paper.
Corrected capitalization of the CCured paper title.


---
Diffs of the changes:  (+48 -6)

 memsafety.html |   54 ++++++++++++++++++++++++++++++++++++++++++++++++------
 1 file changed, 48 insertions(+), 6 deletions(-)


Index: llvm-www/safecode/menagerie/memsafety.html
diff -u llvm-www/safecode/menagerie/memsafety.html:1.7 llvm-www/safecode/menagerie/memsafety.html:1.8
--- llvm-www/safecode/menagerie/memsafety.html:1.7	Fri Jun 25 12:18:16 2010
+++ llvm-www/safecode/menagerie/memsafety.html	Fri Jul  2 14:16:34 2010
@@ -192,7 +192,7 @@
 
         <li>
         <a href="http://portal.acm.org/citation.cfm?id=1065892"><b>
-        CCured: type-safe retrofitting of legacy software
+        CCured: Type-safe Retrofitting of Legacy Software
         </b></a>
         <br>
         George C. Necula, Jeremy Condit, Matthew Harren, Scott McPeak, and
@@ -235,7 +235,6 @@
 
         <br>
 
-
         <li>
         <a href="http://www.isoc.org/isoc/conferences/ndss/04/proceedings/Papers/Ruwase.pdf"><b>
         A Practical Dynamic Buffer Overflow Detector
@@ -250,6 +249,20 @@
         <br>
 
         <li>
+        <a href="http://valgrind.org/docs/bounds-checking2004.ps"><b>
+        Bounds-Checking Entire Programs Without Recompiling
+        </b></a>
+        <br>
+         Nicholas Nethercote and Jeremy Fitzhardinge.
+        <br>
+        <i> Informal Proceedings of the Second Workshop on Semantics, Program
+        Analysis, and Computing Environments for Memory Management
+        (SPACE 2004)</i>, Venice, Italy, January 2004.
+        </li>
+
+        <br>
+
+        <li>
         <a href="http://llvm.org/pubs/2003-05-05-LCTES03-CodeSafety.html"><b>
         Memory Safety without Runtime Checks or Garbage Collection for Embedded
         Systems
@@ -257,7 +270,22 @@
         <br>
         Dinakar Dhurjati, Sumant Kowshik, Vikram Adve and Chris Lattner.
         <br>
-        <i>Languages Compilers and Tools for Embedded Systems (LCTES 2003)</i>, June 2003.
+        <i>Languages Compilers and Tools for Embedded Systems (LCTES 2003)</i>,
+        June 2003.
+        </li>
+
+        <br>
+
+        <li>
+        <a href="http://www.springerlink.com/content/60ml9qpl3u2lag4x/"><b>
+        Run-Time Type Checking for Binary Programs
+        </b></a>
+        <br>
+        Michael Burrows, Stephen N. Freund, and Janet L. Wiener.
+        <br>
+        <i>Proceedings of the Twelfth International Conference on Compiler
+        Construction</i>,
+        Warsaw, Poland, April 2003.
         </li>
 
         <br>
@@ -270,8 +298,22 @@
         <br>
         Sumant Kowshik, Dinakar Dhurjati, Vikram Adve.
         <br>
-        International Conference on Compilers, Architecture and Synthesis for
-        Embedded Systems (CASES), October 2002.
+        <i>International Conference on Compilers, Architecture and Synthesis for
+        Embedded Systems (CASES)</i>, October 2002.
+        </li>
+
+        <br>
+
+        <li>
+        <a href="http://www.springerlink.com/content/tldy4a7y5l22bc1m/"><b>
+        Debugging via Run-Time Type Checking
+        </b></a>
+        <br>
+        Alexey Loginov, Suan Hsi Yong, Susan Horwitz, and Thomas W. Reps
+        <br>
+        <i>Proceedings of the Fourth International Conference on Fundamental
+        Approaches to Software Engineering (FASE 2001)</i>,
+        Genova, Italy, April 2001.
         </li>
 
         <br>
@@ -284,7 +326,7 @@
         <br>
         Richard W. M. Jones and Paul H. J. Kelly.
         <br>
-        Third International Workshop on Automated Debugging, May 1997.
+        <i>Third International Workshop on Automated Debugging</i>, May 1997.
         </li>
 
         <br>





From ggreif at gmail.com  Fri Jul  2 14:26:28 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Fri, 02 Jul 2010 19:26:28 -0000
Subject: [llvm-commits] [llvm] r107500 -
	/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
Message-ID: <20100702192628.EC6952A6C12C@llvm.org>

Author: ggreif
Date: Fri Jul  2 14:26:28 2010
New Revision: 107500

URL: http://llvm.org/viewvc/llvm-project?rev=107500&view=rev
Log:
beautify output

Modified:
    llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp

Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp?rev=107500&r1=107499&r2=107500&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp (original)
+++ llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Fri Jul  2 14:26:28 2010
@@ -1421,6 +1421,7 @@
     nl(Out) << iName << "->setTailCall("
         << (call->isTailCall() ? "true" : "false");
     Out << ");";
+    nl(Out);
     printAttributes(call->getAttributes(), iName);
     Out << iName << "->setAttributes(" << iName << "_PAL);";
     nl(Out);




From stoklund at 2pi.dk  Fri Jul  2 14:54:40 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Fri, 02 Jul 2010 19:54:40 -0000
Subject: [llvm-commits] [llvm] r107503 -
	/llvm/trunk/lib/CodeGen/InlineSpiller.cpp
Message-ID: <20100702195440.C07442A6C12C@llvm.org>

Author: stoklund
Date: Fri Jul  2 14:54:40 2010
New Revision: 107503

URL: http://llvm.org/viewvc/llvm-project?rev=107503&view=rev
Log:
Properly handle debug values during inline spilling.

Modified:
    llvm/trunk/lib/CodeGen/InlineSpiller.cpp

Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/InlineSpiller.cpp?rev=107503&r1=107502&r2=107503&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/InlineSpiller.cpp (original)
+++ llvm/trunk/lib/CodeGen/InlineSpiller.cpp Fri Jul  2 14:54:40 2010
@@ -245,20 +245,21 @@
     return;
 
   // Removing values may cause debug uses where li_ is not live.
-  for (MachineRegisterInfo::use_iterator
-       RI = mri_.use_begin(li_->reg), RE = mri_.use_end(); RI != RE;) {
-    MachineOperand &MO = RI.getOperand();
-    MachineInstr *MI = MO.getParent();
-    ++RI;
-    SlotIndex UseIdx = lis_.getInstructionIndex(MI).getUseIndex();
-    DEBUG(dbgs() << "\tremaining use: " << UseIdx << '\t' << *MI);
-    if (li_->liveAt(UseIdx))
+  for (MachineRegisterInfo::use_iterator RI = mri_.use_begin(li_->reg);
+       MachineInstr *MI = RI.skipInstruction();) {
+    if (!MI->isDebugValue())
       continue;
-    assert(MI->isDebugValue() && "Remaining non-debug use after remat dead.");
-    if (li_->empty())
-      MO.setIsUndef();
-    else
-      MO.setReg(0);
+    // Try to preserve the debug value if li_ is live immediately after it.
+    MachineBasicBlock::iterator NextMI = MI;
+    ++NextMI;
+    if (NextMI != MI->getParent()->end() && !lis_.isNotInMIMap(NextMI)) {
+      SlotIndex NearIdx = lis_.getInstructionIndex(NextMI);
+      if (li_->liveAt(NearIdx))
+        continue;
+    }
+    DEBUG(dbgs() << "Removing debug info due to remat:" << "\t" << *MI);
+    assert(&*RI != MI && "Multiple register operands on debug value");
+    MI->eraseFromParent();
   }
 }
 
@@ -348,6 +349,24 @@
   for (MachineRegisterInfo::reg_iterator RI = mri_.reg_begin(li->reg);
        MachineInstr *MI = RI.skipInstruction();) {
 
+    // Debug values are not allowed to affect codegen.
+    if (MI->isDebugValue()) {
+      // Modify DBG_VALUE now that the value is in a spill slot.
+      uint64_t Offset = MI->getOperand(1).getImm();
+      const MDNode *MDPtr = MI->getOperand(2).getMetadata();
+      DebugLoc DL = MI->getDebugLoc();
+      if (MachineInstr *NewDV = tii_.emitFrameIndexDebugValue(mf_, stackSlot_,
+                                                           Offset, MDPtr, DL)) {
+        DEBUG(dbgs() << "Modifying debug info due to spill:" << "\t" << *MI);
+        MachineBasicBlock *MBB = MI->getParent();
+        MBB->insert(MBB->erase(MI), NewDV);
+      } else {
+        DEBUG(dbgs() << "Removing debug info due to spill:" << "\t" << *MI);
+        MI->eraseFromParent();
+      }
+      continue;
+    }
+
     // Analyze instruction.
     bool Reads, Writes;
     SmallVector<unsigned, 8> Ops;




From stoklund at 2pi.dk  Fri Jul  2 14:54:45 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Fri, 02 Jul 2010 19:54:45 -0000
Subject: [llvm-commits] [llvm] r107504 -
	/llvm/trunk/include/llvm/CodeGen/SlotIndexes.h
Message-ID: <20100702195445.68CD62A6C12D@llvm.org>

Author: stoklund
Date: Fri Jul  2 14:54:45 2010
New Revision: 107504

URL: http://llvm.org/viewvc/llvm-project?rev=107504&view=rev
Log:
Handle unindexed instructions in SlotIndices.

SlotIndexes::insertMachineInstrInMaps would crash when trying to insert an
instruction imediately after an unmapped debug value.

Modified:
    llvm/trunk/include/llvm/CodeGen/SlotIndexes.h

Modified: llvm/trunk/include/llvm/CodeGen/SlotIndexes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SlotIndexes.h?rev=107504&r1=107503&r2=107504&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SlotIndexes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SlotIndexes.h Fri Jul  2 14:54:45 2010
@@ -663,15 +663,20 @@
       MachineBasicBlock::iterator miItr(mi);
       bool needRenumber = false;
       IndexListEntry *newEntry;
-
+      // Get previous index, considering that not all instructions are indexed.
       IndexListEntry *prevEntry;
-      if (miItr == mbb->begin()) {
+      for (;;) {
         // If mi is at the mbb beginning, get the prev index from the mbb.
-        prevEntry = &mbbRangeItr->second.first.entry();
-      } else {
-        // Otherwise get it from the previous instr.
-        MachineBasicBlock::iterator pItr(prior(miItr));
-        prevEntry = &getInstructionIndex(pItr).entry();
+        if (miItr == mbb->begin()) {
+          prevEntry = &mbbRangeItr->second.first.entry();
+          break;
+        }
+        // Otherwise rewind until we find a mapped instruction.
+        Mi2IndexMap::const_iterator itr = mi2iMap.find(--miItr);
+        if (itr != mi2iMap.end()) {
+          prevEntry = &itr->second.entry();
+          break;
+        }
       }
 
       // Get next entry from previous entry.




From stoklund at 2pi.dk  Fri Jul  2 14:54:47 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Fri, 02 Jul 2010 19:54:47 -0000
Subject: [llvm-commits] [llvm] r107505 -
	/llvm/trunk/lib/CodeGen/InlineSpiller.cpp
Message-ID: <20100702195447.925142A6C12E@llvm.org>

Author: stoklund
Date: Fri Jul  2 14:54:47 2010
New Revision: 107505

URL: http://llvm.org/viewvc/llvm-project?rev=107505&view=rev
Log:
Remove invalid assert

Modified:
    llvm/trunk/lib/CodeGen/InlineSpiller.cpp

Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/InlineSpiller.cpp?rev=107505&r1=107504&r2=107505&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/InlineSpiller.cpp (original)
+++ llvm/trunk/lib/CodeGen/InlineSpiller.cpp Fri Jul  2 14:54:47 2010
@@ -258,7 +258,6 @@
         continue;
     }
     DEBUG(dbgs() << "Removing debug info due to remat:" << "\t" << *MI);
-    assert(&*RI != MI && "Multiple register operands on debug value");
     MI->eraseFromParent();
   }
 }




From dalej at apple.com  Fri Jul  2 15:16:09 2010
From: dalej at apple.com (Dale Johannesen)
Date: Fri, 02 Jul 2010 20:16:09 -0000
Subject: [llvm-commits] [llvm] r107506 - in /llvm/trunk:
 include/llvm/InlineAsm.h lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
 lib/CodeGen/MachineInstr.cpp lib/CodeGen/PrologEpilogInserter.cpp
 lib/CodeGen/SelectionDAG/InstrEmitter.cpp
 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
 lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp test/CodeGen/Thumb/push.ll
 test/CodeGen/X86/2009-04-20-LinearScanOpt.ll
 test/CodeGen/X86/2010-07-02-asm-alignstack.ll
 test/CodeGen/X86/inline-asm-tied.ll
 test/CodeGen/X86/iv-users-in-other-loops.ll
Message-ID: <20100702201609.8087B2A6C12C@llvm.org>

Author: johannes
Date: Fri Jul  2 15:16:09 2010
New Revision: 107506

URL: http://llvm.org/viewvc/llvm-project?rev=107506&view=rev
Log:
Propagate the AlignStack bit in InlineAsm's to the 
PrologEpilog code, and use it to determine whether
the asm forces stack alignment or not.  gcc consistently
does not do this for GCC-style asms; Apple gcc inconsistently
sometimes does it for asm blocks.  There is no
convenient place to put a bit in either the SDNode or
the MachineInstr form, so I've added an extra operand
to each; unlovely, but it does allow for expansion for
more bits, should we need it.  PR 5125.  Some
existing testcases are affected.
The operand lists of the SDNode and MachineInstr forms
are indexed with awesome mnemonics, like "2"; I may
fix this someday, but not now.  I'm not making it any
worse.  If anyone is inspired I think you can find all
the right places from this patch.


Added:
    llvm/trunk/test/CodeGen/X86/2010-07-02-asm-alignstack.ll
Modified:
    llvm/trunk/include/llvm/InlineAsm.h
    llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
    llvm/trunk/lib/CodeGen/MachineInstr.cpp
    llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
    llvm/trunk/test/CodeGen/Thumb/push.ll
    llvm/trunk/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll
    llvm/trunk/test/CodeGen/X86/inline-asm-tied.ll
    llvm/trunk/test/CodeGen/X86/iv-users-in-other-loops.ll

Modified: llvm/trunk/include/llvm/InlineAsm.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/InlineAsm.h?rev=107506&r1=107505&r2=107506&view=diff
==============================================================================
--- llvm/trunk/include/llvm/InlineAsm.h (original)
+++ llvm/trunk/include/llvm/InlineAsm.h Fri Jul  2 15:16:09 2010
@@ -154,7 +154,8 @@
     Op_InputChain = 0,
     Op_AsmString = 1,
     Op_MDNode = 2,
-    Op_FirstOperand = 3,
+    Op_IsAlignStack = 3,
+    Op_FirstOperand = 4,
     
     Kind_RegUse = 1,
     Kind_RegDef = 2,

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp?rev=107506&r1=107505&r2=107506&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp Fri Jul  2 15:16:09 2010
@@ -279,7 +279,7 @@
       // Okay, we finally have a value number.  Ask the target to print this
       // operand!
       if (CurVariant == -1 || CurVariant == AsmPrinterVariant) {
-        unsigned OpNo = 1;
+        unsigned OpNo = 2;
 
         bool Error = false;
 

Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=107506&r1=107505&r2=107506&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Fri Jul  2 15:16:09 2010
@@ -881,14 +881,14 @@
 bool MachineInstr::
 isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const {
   if (isInlineAsm()) {
-    assert(DefOpIdx >= 2);
+    assert(DefOpIdx >= 3);
     const MachineOperand &MO = getOperand(DefOpIdx);
     if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
       return false;
     // Determine the actual operand index that corresponds to this index.
     unsigned DefNo = 0;
     unsigned DefPart = 0;
-    for (unsigned i = 1, e = getNumOperands(); i < e; ) {
+    for (unsigned i = 2, e = getNumOperands(); i < e; ) {
       const MachineOperand &FMO = getOperand(i);
       // After the normal asm operands there may be additional imp-def regs.
       if (!FMO.isImm())
@@ -903,7 +903,7 @@
       }
       ++DefNo;
     }
-    for (unsigned i = 1, e = getNumOperands(); i != e; ++i) {
+    for (unsigned i = 2, e = getNumOperands(); i != e; ++i) {
       const MachineOperand &FMO = getOperand(i);
       if (!FMO.isImm())
         continue;
@@ -946,7 +946,7 @@
 
     // Find the flag operand corresponding to UseOpIdx
     unsigned FlagIdx, NumOps=0;
-    for (FlagIdx = 1; FlagIdx < UseOpIdx; FlagIdx += NumOps+1) {
+    for (FlagIdx = 2; FlagIdx < UseOpIdx; FlagIdx += NumOps+1) {
       const MachineOperand &UFMO = getOperand(FlagIdx);
       // After the normal asm operands there may be additional imp-def regs.
       if (!UFMO.isImm())
@@ -964,9 +964,9 @@
       if (!DefOpIdx)
         return true;
 
-      unsigned DefIdx = 1;
-      // Remember to adjust the index. First operand is asm string, then there
-      // is a flag for each.
+      unsigned DefIdx = 2;
+      // Remember to adjust the index. First operand is asm string, second is
+      // the AlignStack bit, then there is a flag for each.
       while (DefNo) {
         const MachineOperand &FMO = getOperand(DefIdx);
         assert(FMO.isImm());

Modified: llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp?rev=107506&r1=107505&r2=107506&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp (original)
+++ llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp Fri Jul  2 15:16:09 2010
@@ -158,9 +158,9 @@
         AdjustsStack = true;
         FrameSDOps.push_back(I);
       } else if (I->isInlineAsm()) {
-        // An InlineAsm might be a call; assume it is to get the stack frame
-        // aligned correctly for calls.
-        AdjustsStack = true;
+        // Some inline asm's need a stack frame, as indicated by operand 1.
+        if (I->getOperand(1).getImm())
+          AdjustsStack = true;
       }
 
   MFI->setAdjustsStack(AdjustsStack);

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp?rev=107506&r1=107505&r2=107506&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp Fri Jul  2 15:16:09 2010
@@ -834,6 +834,12 @@
     const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
     MI->addOperand(MachineOperand::CreateES(AsmStr));
       
+    // Add the isAlignStack bit.
+    int64_t isAlignStack =
+      cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_IsAlignStack))->
+                          getZExtValue();
+    MI->addOperand(MachineOperand::CreateImm(isAlignStack));
+
     // Add all of the operand registers to the instruction.
     for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
       unsigned Flags =

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=107506&r1=107505&r2=107506&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Fri Jul  2 15:16:09 2010
@@ -5454,6 +5454,10 @@
   const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
   AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
 
+  // Remember the AlignStack bit as operand 3.
+  AsmNodeOperands.push_back(DAG.getTargetConstant(IA->isAlignStack() ? 1 : 0,
+                                            MVT::i1));
+
   // Loop over all of the inputs, copying the operand values into the
   // appropriate registers and processing the output regs.
   RegsForValue RetValRegs;
@@ -5642,7 +5646,7 @@
   }
 
   // Finish up input operands.  Set the input chain and add the flag last.
-  AsmNodeOperands[0] = Chain;
+  AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
   if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
 
   Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=107506&r1=107505&r2=107506&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Fri Jul  2 15:16:09 2010
@@ -1089,6 +1089,7 @@
   Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
   Ops.push_back(InOps[InlineAsm::Op_AsmString]);  // 1
   Ops.push_back(InOps[InlineAsm::Op_MDNode]);     // 2, !srcloc
+  Ops.push_back(InOps[InlineAsm::Op_IsAlignStack]);  // 3
 
   unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
   if (InOps[e-1].getValueType() == MVT::Flag)

Modified: llvm/trunk/test/CodeGen/Thumb/push.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/push.ll?rev=107506&r1=107505&r2=107506&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb/push.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb/push.ll Fri Jul  2 15:16:09 2010
@@ -5,6 +5,6 @@
 ; CHECK: t:
 ; CHECK: push {r7}
 entry:
-  call void asm sideeffect ".long 0xe7ffdefe", ""() nounwind
+  call void asm sideeffect alignstack ".long 0xe7ffdefe", ""() nounwind
   ret void
 }

Modified: llvm/trunk/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll?rev=107506&r1=107505&r2=107506&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll Fri Jul  2 15:16:09 2010
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin10.0 -relocation-model=pic -disable-fp-elim -stats |& grep asm-printer | grep 83
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10.0 -relocation-model=pic -disable-fp-elim -stats |& grep asm-printer | grep 82
 ; rdar://6802189
 
 ; Test if linearscan is unfavoring registers for allocation to allow more reuse

Added: llvm/trunk/test/CodeGen/X86/2010-07-02-asm-alignstack.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-07-02-asm-alignstack.ll?rev=107506&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2010-07-02-asm-alignstack.ll (added)
+++ llvm/trunk/test/CodeGen/X86/2010-07-02-asm-alignstack.ll Fri Jul  2 15:16:09 2010
@@ -0,0 +1,31 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s
+
+define void @foo() nounwind ssp {
+entry:
+; CHECK: foo
+; CHECK: subq $8, %rsp
+; CHECK: int $3
+  call void asm sideeffect alignstack "# top of block", "~{dirflag},~{fpsr},~{flags},~{edi},~{esi},~{edx},~{ecx},~{eax}"() nounwind
+  call void asm sideeffect alignstack ".file \22small.c\22", "~{dirflag},~{fpsr},~{flags}"() nounwind
+  call void asm sideeffect alignstack ".line 3", "~{dirflag},~{fpsr},~{flags}"() nounwind
+  call void asm sideeffect alignstack "int $$3", "~{dirflag},~{fpsr},~{flags},~{memory}"() nounwind
+  br label %return
+
+return:                                           ; preds = %entry
+  ret void
+}
+
+define void @bar() nounwind ssp {
+entry:
+; CHECK: bar
+; CHECK-NOT: subq $8, %rsp
+; CHECK: int $3
+  call void asm sideeffect "# top of block", "~{dirflag},~{fpsr},~{flags},~{edi},~{esi},~{edx},~{ecx},~{eax}"() nounwind
+  call void asm sideeffect ".file \22small.c\22", "~{dirflag},~{fpsr},~{flags}"() nounwind
+  call void asm sideeffect ".line 3", "~{dirflag},~{fpsr},~{flags}"() nounwind
+  call void asm sideeffect "int $$3", "~{dirflag},~{fpsr},~{flags},~{memory}"() nounwind
+  br label %return
+
+return:                                           ; preds = %entry
+  ret void
+}

Modified: llvm/trunk/test/CodeGen/X86/inline-asm-tied.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/inline-asm-tied.ll?rev=107506&r1=107505&r2=107506&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/inline-asm-tied.ll (original)
+++ llvm/trunk/test/CodeGen/X86/inline-asm-tied.ll Fri Jul  2 15:16:09 2010
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=i386-apple-darwin9 -O0 -regalloc=linearscan | grep {movl	%edx, 12(%esp)} | count 2
+; RUN: llc < %s -mtriple=i386-apple-darwin9 -O0 -regalloc=linearscan | grep {movl	%edx, 4(%esp)} | count 2
 ; rdar://6992609
 
 target triple = "i386-apple-darwin9.0"

Modified: llvm/trunk/test/CodeGen/X86/iv-users-in-other-loops.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/iv-users-in-other-loops.ll?rev=107506&r1=107505&r2=107506&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/iv-users-in-other-loops.ll (original)
+++ llvm/trunk/test/CodeGen/X86/iv-users-in-other-loops.ll Fri Jul  2 15:16:09 2010
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=x86-64 -o %t
 ; RUN: not grep inc %t
 ; RUN: grep dec %t | count 2
-; RUN: grep addq %t | count 13
+; RUN: grep addq %t | count 12
 ; RUN: not grep addb %t
 ; RUN: not grep leaq %t
 ; RUN: not grep leal %t




From gohman at apple.com  Fri Jul  2 15:20:50 2010
From: gohman at apple.com (Dan Gohman)
Date: Fri, 02 Jul 2010 20:20:50 -0000
Subject: [llvm-commits] [llvm] r107507 -
	/llvm/trunk/include/llvm/Analysis/AliasAnalysis.h
Message-ID: <20100702202050.7FF052A6C12C@llvm.org>

Author: djg
Date: Fri Jul  2 15:20:50 2010
New Revision: 107507

URL: http://llvm.org/viewvc/llvm-project?rev=107507&view=rev
Log:
Remove an unused enum.

Modified:
    llvm/trunk/include/llvm/Analysis/AliasAnalysis.h

Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/AliasAnalysis.h?rev=107507&r1=107506&r2=107507&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/AliasAnalysis.h (original)
+++ llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Fri Jul  2 15:20:50 2010
@@ -165,27 +165,6 @@
     /// ModRefInfo - Whether the pointer is loaded or stored to/from.
     ///
     ModRefResult ModRefInfo;
-
-    /// AccessType - Specific fine-grained access information for the argument.
-    /// If none of these classifications is general enough, the
-    /// getModRefBehavior method should not return AccessesArguments*.  If a
-    /// record is not returned for a particular argument, the argument is never
-    /// dead and never dereferenced.
-    enum AccessType {
-      /// ScalarAccess - The pointer is dereferenced.
-      ///
-      ScalarAccess,
-
-      /// ArrayAccess - The pointer is indexed through as an array of elements.
-      ///
-      ArrayAccess,
-
-      /// ElementAccess ?? P->F only?
-
-      /// CallsThrough - Indirect calls are made through the specified function
-      /// pointer.
-      CallsThrough
-    };
   };
 
   /// getModRefBehavior - Return the behavior when calling the given call site.




From evan.cheng at apple.com  Fri Jul  2 15:36:18 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 02 Jul 2010 20:36:18 -0000
Subject: [llvm-commits] [llvm] r107509 - in /llvm/trunk:
 lib/CodeGen/TwoAddressInstructionPass.cpp lib/Target/X86/X86InstrInfo.cpp
 test/CodeGen/X86/2010-07-02-UnfoldBug.ll
Message-ID: <20100702203618.707EC2A6C12C@llvm.org>

Author: evancheng
Date: Fri Jul  2 15:36:18 2010
New Revision: 107509

URL: http://llvm.org/viewvc/llvm-project?rev=107509&view=rev
Log:
- Two-address pass should not assume unfolding is always successful.
- X86 unfolding should check if the instructions being unfolded has memoperands.
  If there is no memoperands, then it must assume conservative alignment. If this
  would introduce an expensive sse unaligned load / store, then unfoldMemoryOperand
  etc. should not unfold the instruction.

Added:
    llvm/trunk/test/CodeGen/X86/2010-07-02-UnfoldBug.ll
Modified:
    llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp

Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=107509&r1=107508&r2=107509&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original)
+++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Fri Jul  2 15:36:18 2010
@@ -926,14 +926,12 @@
           UnfoldTID.OpInfo[LoadRegIndex].getRegClass(TRI);
         unsigned Reg = MRI->createVirtualRegister(RC);
         SmallVector<MachineInstr *, 2> NewMIs;
-        bool Success =
-          TII->unfoldMemoryOperand(MF, mi, Reg,
-                                   /*UnfoldLoad=*/true, /*UnfoldStore=*/false,
-                                   NewMIs);
-        (void)Success;
-        assert(Success &&
-               "unfoldMemoryOperand failed when getOpcodeAfterMemoryUnfold "
-               "succeeded!");
+        if (!TII->unfoldMemoryOperand(MF, mi, Reg,
+                                      /*UnfoldLoad=*/true,/*UnfoldStore=*/false,
+                                      NewMIs)) {
+          DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
+          return false;
+        }
         assert(NewMIs.size() == 2 &&
                "Unfolded a load into multiple instructions!");
         // The load was previously folded, so this is the only use.

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=107509&r1=107508&r2=107509&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Fri Jul  2 15:36:18 2010
@@ -2159,7 +2159,7 @@
                                   MachineInstr::mmo_iterator MMOBegin,
                                   MachineInstr::mmo_iterator MMOEnd,
                                   SmallVectorImpl<MachineInstr*> &NewMIs) const {
-  bool isAligned = (*MMOBegin)->getAlignment() >= 16;
+  bool isAligned = *MMOBegin && (*MMOBegin)->getAlignment() >= 16;
   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
   DebugLoc DL;
   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
@@ -2189,7 +2189,7 @@
                                  MachineInstr::mmo_iterator MMOBegin,
                                  MachineInstr::mmo_iterator MMOEnd,
                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
-  bool isAligned = (*MMOBegin)->getAlignment() >= 16;
+  bool isAligned = *MMOBegin && (*MMOBegin)->getAlignment() >= 16;
   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
   DebugLoc DL;
   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
@@ -2693,6 +2693,13 @@
   const TargetInstrDesc &TID = get(Opc);
   const TargetOperandInfo &TOI = TID.OpInfo[Index];
   const TargetRegisterClass *RC = TOI.getRegClass(&RI);
+  if (!MI->hasOneMemOperand() &&
+      RC == &X86::VR128RegClass &&
+      !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
+    // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
+    // conservatively assume the address is unaligned. That's bad for
+    // performance.
+    return false;
   SmallVector<MachineOperand, X86AddrNumOperands> AddrOps;
   SmallVector<MachineOperand,2> BeforeOps;
   SmallVector<MachineOperand,2> AfterOps;
@@ -2834,7 +2841,12 @@
               MachineInstr::mmo_iterator> MMOs =
       MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
                             cast<MachineSDNode>(N)->memoperands_end());
-    bool isAligned = (*MMOs.first)->getAlignment() >= 16;
+    if (!(*MMOs.first) &&
+        RC == &X86::VR128RegClass &&
+        !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
+      // Do not introduce a slow unaligned load.
+      return false;
+    bool isAligned = (*MMOs.first) && (*MMOs.first)->getAlignment() >= 16;
     Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
                               VT, MVT::Other, &AddrOps[0], AddrOps.size());
     NewNodes.push_back(Load);
@@ -2871,7 +2883,12 @@
               MachineInstr::mmo_iterator> MMOs =
       MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
                              cast<MachineSDNode>(N)->memoperands_end());
-    bool isAligned = (*MMOs.first)->getAlignment() >= 16;
+    if (!(*MMOs.first) &&
+        RC == &X86::VR128RegClass &&
+        !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
+      // Do not introduce a slow unaligned store.
+      return false;
+    bool isAligned = (*MMOs.first) && (*MMOs.first)->getAlignment() >= 16;
     SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
                                                          isAligned, TM),
                                        dl, MVT::Other,

Added: llvm/trunk/test/CodeGen/X86/2010-07-02-UnfoldBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-07-02-UnfoldBug.ll?rev=107509&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2010-07-02-UnfoldBug.ll (added)
+++ llvm/trunk/test/CodeGen/X86/2010-07-02-UnfoldBug.ll Fri Jul  2 15:36:18 2010
@@ -0,0 +1,99 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin
+; rdar://8154265
+
+declare <4 x float> @llvm.x86.sse.max.ss(<4 x float>, <4 x float>) nounwind readnone
+
+declare <4 x float> @llvm.x86.sse.min.ss(<4 x float>, <4 x float>) nounwind readnone
+
+define void @_ZN2CA3OGL20fill_surface_mesh_3dERNS0_7ContextEPKNS_6Render13MeshTransformEPKNS0_5LayerEPNS0_7SurfaceEfNS0_13TextureFilterESC_f() nounwind optsize ssp {
+entry:
+  br i1 undef, label %bb2.thread, label %bb2
+
+bb2.thread:                                       ; preds = %entry
+  br i1 undef, label %bb41, label %bb10.preheader
+
+bb2:                                              ; preds = %entry
+  unreachable
+
+bb10.preheader:                                   ; preds = %bb2.thread
+  br i1 undef, label %bb9, label %bb12
+
+bb9:                                              ; preds = %bb9, %bb10.preheader
+  br i1 undef, label %bb9, label %bb12
+
+bb12:                                             ; preds = %bb9, %bb10.preheader
+  br i1 undef, label %bb4.i.i, label %bb3.i.i
+
+bb3.i.i:                                          ; preds = %bb12
+  unreachable
+
+bb4.i.i:                                          ; preds = %bb12
+  br i1 undef, label %bb8.i.i, label %_ZN2CA3OGL12_GLOBAL__N_16LightsC1ERNS0_7ContextEPKNS0_5LayerEPKNS_6Render13MeshTransformERKNS_4Vec3IfEESF_.exit
+
+bb8.i.i:                                          ; preds = %bb4.i.i
+  br i1 undef, label %_ZN2CA3OGL12_GLOBAL__N_16LightsC1ERNS0_7ContextEPKNS0_5LayerEPKNS_6Render13MeshTransformERKNS_4Vec3IfEESF_.exit, label %bb9.i.i
+
+bb9.i.i:                                          ; preds = %bb8.i.i
+  br i1 undef, label %bb11.i.i, label %bb10.i.i
+
+bb10.i.i:                                         ; preds = %bb9.i.i
+  unreachable
+
+bb11.i.i:                                         ; preds = %bb9.i.i
+  unreachable
+
+_ZN2CA3OGL12_GLOBAL__N_16LightsC1ERNS0_7ContextEPKNS0_5LayerEPKNS_6Render13MeshTransformERKNS_4Vec3IfEESF_.exit: ; preds = %bb8.i.i, %bb4.i.i
+  br i1 undef, label %bb19, label %bb14
+
+bb14:                                             ; preds = %_ZN2CA3OGL12_GLOBAL__N_16LightsC1ERNS0_7ContextEPKNS0_5LayerEPKNS_6Render13MeshTransformERKNS_4Vec3IfEESF_.exit
+  unreachable
+
+bb19:                                             ; preds = %_ZN2CA3OGL12_GLOBAL__N_16LightsC1ERNS0_7ContextEPKNS0_5LayerEPKNS_6Render13MeshTransformERKNS_4Vec3IfEESF_.exit
+  br i1 undef, label %bb.i50, label %bb6.i
+
+bb.i50:                                           ; preds = %bb19
+  unreachable
+
+bb6.i:                                            ; preds = %bb19
+  br i1 undef, label %bb28, label %bb.nph106
+
+bb22:                                             ; preds = %bb24.preheader
+  br i1 undef, label %bb2.i.i, label %bb.i.i49
+
+bb.i.i49:                                         ; preds = %bb22
+  %0 = load float* undef, align 4                 ; <float> [#uses=1]
+  %1 = insertelement <4 x float> undef, float %0, i32 0 ; <<4 x float>> [#uses=1]
+  %2 = call <4 x float> @llvm.x86.sse.min.ss(<4 x float> <float 1.000000e+00, float undef, float undef, float undef>, <4 x float> %1) nounwind readnone ; <<4 x float>> [#uses=1]
+  %3 = call <4 x float> @llvm.x86.sse.max.ss(<4 x float> %2, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>) nounwind readnone ; <<4 x float>> [#uses=1]
+  %4 = extractelement <4 x float> %3, i32 0       ; <float> [#uses=1]
+  store float %4, float* undef, align 4
+  %5 = call <4 x float> @llvm.x86.sse.min.ss(<4 x float> <float 1.000000e+00, float undef, float undef, float undef>, <4 x float> undef) nounwind readnone ; <<4 x float>> [#uses=1]
+  %6 = call <4 x float> @llvm.x86.sse.max.ss(<4 x float> %5, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>) nounwind readnone ; <<4 x float>> [#uses=1]
+  %7 = extractelement <4 x float> %6, i32 0       ; <float> [#uses=1]
+  store float %7, float* undef, align 4
+  unreachable
+
+bb2.i.i:                                          ; preds = %bb22
+  unreachable
+
+bb26.loopexit:                                    ; preds = %bb24.preheader
+  br i1 undef, label %bb28, label %bb24.preheader
+
+bb.nph106:                                        ; preds = %bb6.i
+  br label %bb24.preheader
+
+bb24.preheader:                                   ; preds = %bb.nph106, %bb26.loopexit
+  br i1 undef, label %bb22, label %bb26.loopexit
+
+bb28:                                             ; preds = %bb26.loopexit, %bb6.i
+  unreachable
+
+bb41:                                             ; preds = %bb2.thread
+  br i1 undef, label %return, label %bb46
+
+bb46:                                             ; preds = %bb41
+  ret void
+
+return:                                           ; preds = %bb41
+  ret void
+}




From evan.cheng at apple.com  Fri Jul  2 16:07:09 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 02 Jul 2010 21:07:09 -0000
Subject: [llvm-commits] [llvm] r107513 - in /llvm/trunk/lib/Target/ARM:
 ARM.h ARMTargetMachine.cpp Thumb2ITBlockPass.cpp
Message-ID: <20100702210709.C4CA62A6C12F@llvm.org>

Author: evancheng
Date: Fri Jul  2 16:07:09 2010
New Revision: 107513

URL: http://llvm.org/viewvc/llvm-project?rev=107513&view=rev
Log:
Remove early IT block formation. It's not used.

Modified:
    llvm/trunk/lib/Target/ARM/ARM.h
    llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
    llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp

Modified: llvm/trunk/lib/Target/ARM/ARM.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.h?rev=107513&r1=107512&r2=107513&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARM.h (original)
+++ llvm/trunk/lib/Target/ARM/ARM.h Fri Jul  2 16:07:09 2010
@@ -101,7 +101,7 @@
 FunctionPass *createARMConstantIslandPass();
 FunctionPass *createNEONPreAllocPass();
 FunctionPass *createNEONMoveFixPass();
-FunctionPass *createThumb2ITBlockPass(bool PreAlloc = false);
+FunctionPass *createThumb2ITBlockPass();
 FunctionPass *createThumb2SizeReductionPass();
 
 extern Target TheARMTarget, TheThumbTarget;

Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=107513&r1=107512&r2=107513&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Fri Jul  2 16:07:09 2010
@@ -16,17 +16,11 @@
 #include "ARM.h"
 #include "llvm/PassManager.h"
 #include "llvm/CodeGen/Passes.h"
-#include "llvm/Support/CommandLine.h"
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/Target/TargetRegistry.h"
 using namespace llvm;
 
-static cl::opt<bool>
-EarlyITBlockFormation("thumb2-early-it-blocks", cl::Hidden,
-  cl::desc("Form IT blocks early before register allocation"),
-  cl::init(false));
-
 static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
   Triple TheTriple(TT);
   switch (TheTriple.getOS()) {
@@ -109,8 +103,6 @@
   if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
     PM.add(createARMLoadStoreOptimizationPass(true));
 
-  if (Subtarget.isThumb2() && EarlyITBlockFormation)
-    PM.add(createThumb2ITBlockPass(true));
   return true;
 }
 

Modified: llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp?rev=107513&r1=107512&r2=107513&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp Fri Jul  2 16:07:09 2010
@@ -27,8 +27,7 @@
 
   public:
     static char ID;
-    Thumb2ITBlockPass(bool PreRA) :
-      MachineFunctionPass(&ID), PreRegAlloc(PreRA) {}
+    Thumb2ITBlockPass() : MachineFunctionPass(&ID) {}
 
     const Thumb2InstrInfo *TII;
     const TargetRegisterInfo *TRI;
@@ -41,18 +40,6 @@
     }
 
   private:
-    bool MoveCPSRUseUp(MachineBasicBlock &MBB,
-                       MachineBasicBlock::iterator MBBI,
-                       MachineBasicBlock::iterator E,
-                       unsigned PredReg,
-                       ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
-                       bool &Done);
-
-    void FindITBlockRanges(MachineBasicBlock &MBB,
-                           SmallVector<MachineInstr*,4> &FirstUses,
-                           SmallVector<MachineInstr*,4> &LastUses);
-    bool InsertITBlock(MachineInstr *First, MachineInstr *Last);
-    bool InsertITBlocks(MachineBasicBlock &MBB);
     bool MoveCopyOutOfITBlock(MachineInstr *MI,
                               ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
                               SmallSet<unsigned, 4> &Defs,
@@ -62,189 +49,6 @@
   char Thumb2ITBlockPass::ID = 0;
 }
 
-bool
-Thumb2ITBlockPass::MoveCPSRUseUp(MachineBasicBlock &MBB,
-                                 MachineBasicBlock::iterator MBBI,
-                                 MachineBasicBlock::iterator E,
-                                 unsigned PredReg,
-                                 ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
-                                 bool &Done) {
-  SmallSet<unsigned, 4> Defs, Uses;
-  MachineBasicBlock::iterator I = MBBI;
-  // Look for next CPSR use by scanning up to 4 instructions.
-  for (unsigned i = 0; i < 4; ++i) {
-    MachineInstr *MI = &*I;
-    unsigned MPredReg = 0;
-    ARMCC::CondCodes MCC = llvm::getITInstrPredicate(MI, MPredReg);
-    if (MCC != ARMCC::AL) {
-      if (MPredReg != PredReg || (MCC != CC && MCC != OCC))
-        return false;
-
-      // Check if the instruction is using any register that's defined
-      // below the previous predicated instruction. Also return false if
-      // it defines any register which is used in between.
-      for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
-        const MachineOperand &MO = MI->getOperand(i);
-        if (!MO.isReg())
-          continue;
-        unsigned Reg = MO.getReg();
-        if (!Reg)
-          continue;
-        if (MO.isDef()) {
-          if (Reg == PredReg || Uses.count(Reg))
-            return false;
-        } else {
-          if (Defs.count(Reg))
-            return false;
-        }
-      }
-
-      Done = (I == E);
-      MBB.remove(MI);
-      MBB.insert(MBBI, MI);
-      ++NumMovedInsts;
-      return true;
-    }
-
-    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
-      const MachineOperand &MO = MI->getOperand(i);
-      if (!MO.isReg())
-        continue;
-      unsigned Reg = MO.getReg();
-      if (!Reg)
-        continue;
-      if (MO.isDef()) {
-        if (Reg == PredReg)
-          return false;
-        Defs.insert(Reg);
-      } else
-        Uses.insert(Reg);
-    }
-
-    if (I == E)
-      break;
-    ++I;
-  }
-  return false;
-}
-
-static bool isCPSRLiveout(MachineBasicBlock &MBB) {
-  for (MachineBasicBlock::succ_iterator I = MBB.succ_begin(),
-         E = MBB.succ_end(); I != E; ++I) {
-    if ((*I)->isLiveIn(ARM::CPSR))
-      return true;
-  }
-  return false;
-}
-
-void Thumb2ITBlockPass::FindITBlockRanges(MachineBasicBlock &MBB,
-                                       SmallVector<MachineInstr*,4> &FirstUses,
-                                       SmallVector<MachineInstr*,4> &LastUses) {
-  bool SeenUse = false;
-  MachineOperand *LastUse = 0;
-  MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
-  while (MBBI != E) {
-    MachineInstr *MI = &*MBBI;
-    ++MBBI;
-
-    MachineOperand *Def = 0;
-    MachineOperand *Use = 0;
-    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
-      MachineOperand &MO = MI->getOperand(i);
-      if (!MO.isReg() || MO.getReg() != ARM::CPSR)
-        continue;
-      if (MO.isDef()) {
-        assert(Def == 0 && "Multiple defs of CPSR?");
-        Def = &MO;
-      } else {
-        assert(Use == 0 && "Multiple uses of CPSR?");
-        Use = &MO;
-      }
-    }
-
-    if (Use) {
-      LastUse = Use;
-      if (!SeenUse) {
-        FirstUses.push_back(MI);
-        SeenUse = true;
-      }
-    }
-    if (Def) {
-      if (LastUse) {
-        LastUses.push_back(LastUse->getParent());
-        LastUse = 0;
-      }
-      SeenUse = false;
-    }
-  }
-
-  if (LastUse) {
-    // Is the last use a kill?
-    if (isCPSRLiveout(MBB))
-      LastUses.push_back(0);
-    else
-      LastUses.push_back(LastUse->getParent());
-  }
-}
-
-bool Thumb2ITBlockPass::InsertITBlock(MachineInstr *First, MachineInstr *Last) {
-  if (First == Last)
-    return false;
-
-  bool Modified = false;
-  MachineBasicBlock *MBB = First->getParent();
-  MachineBasicBlock::iterator MBBI = First;
-  MachineBasicBlock::iterator E = Last;
-
-  if (First->getDesc().isBranch() || First->getDesc().isReturn())
-    return false;
-
-  unsigned PredReg = 0;
-  ARMCC::CondCodes CC = llvm::getITInstrPredicate(First, PredReg);
-  if (CC == ARMCC::AL)
-    return Modified;
-
-  // Move uses of the CPSR together if possible.
-  ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
-
-  do {
-    ++MBBI;
-    if (MBBI->getDesc().isBranch() || MBBI->getDesc().isReturn())
-      return Modified;
-    MachineInstr *NMI = &*MBBI;
-    unsigned NPredReg = 0;
-    ARMCC::CondCodes NCC = llvm::getITInstrPredicate(NMI, NPredReg);
-    if (NCC != CC && NCC != OCC) {
-      if (NCC != ARMCC::AL)
-        return Modified;
-      assert(MBBI != E);
-      bool Done = false;
-      if (!MoveCPSRUseUp(*MBB, MBBI, E, PredReg, CC, OCC, Done))
-        return Modified;
-      Modified = true;
-      if (Done)
-        MBBI = E;
-    }
-  } while (MBBI != E);
-  return true;
-}
-
-bool Thumb2ITBlockPass::InsertITBlocks(MachineBasicBlock &MBB) {
-  SmallVector<MachineInstr*, 4> FirstUses;
-  SmallVector<MachineInstr*, 4> LastUses;
-  FindITBlockRanges(MBB, FirstUses, LastUses);
-  assert(FirstUses.size() == LastUses.size() && "Incorrect range information!");
-
-  bool Modified = false;
-  for (unsigned i = 0, e = FirstUses.size(); i != e; ++i) {
-    if (LastUses[i] == 0)
-      // Must be the last pair where CPSR is live out of the block.
-      return Modified;
-    Modified |= InsertITBlock(FirstUses[i], LastUses[i]);
-  }
-  return Modified;
-}
-
 /// TrackDefUses - Tracking what registers are being defined and used by
 /// instructions in the IT block. This also tracks "dependencies", i.e. uses
 /// in the IT block that are defined before the IT instruction.
@@ -417,13 +221,10 @@
   for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E; ) {
     MachineBasicBlock &MBB = *MFI;
     ++MFI;
-    if (PreRegAlloc)
-      Modified |= InsertITBlocks(MBB);
-    else
-      Modified |= InsertITInstructions(MBB);
+    Modified |= InsertITInstructions(MBB);
   }
 
-  if (Modified && !PreRegAlloc)
+  if (Modified)
     AFI->setHasITBlocks(true);
 
   return Modified;
@@ -431,6 +232,6 @@
 
 /// createThumb2ITBlockPass - Returns an instance of the Thumb2 IT blocks
 /// insertion pass.
-FunctionPass *llvm::createThumb2ITBlockPass(bool PreAlloc) {
-  return new Thumb2ITBlockPass(PreAlloc);
+FunctionPass *llvm::createThumb2ITBlockPass() {
+  return new Thumb2ITBlockPass();
 }




From dpatel at apple.com  Fri Jul  2 16:13:23 2010
From: dpatel at apple.com (Devang Patel)
Date: Fri, 02 Jul 2010 21:13:23 -0000
Subject: [llvm-commits] [llvm] r107516 -
	/llvm/trunk/lib/Transforms/Utils/ValueMapper.cpp
Message-ID: <20100702211323.37C572A6C12F@llvm.org>

Author: dpatel
Date: Fri Jul  2 16:13:23 2010
New Revision: 107516

URL: http://llvm.org/viewvc/llvm-project?rev=107516&view=rev
Log:
MDString is already checked earlier.

Modified:
    llvm/trunk/lib/Transforms/Utils/ValueMapper.cpp

Modified: llvm/trunk/lib/Transforms/Utils/ValueMapper.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/ValueMapper.cpp?rev=107516&r1=107515&r2=107516&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/ValueMapper.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/ValueMapper.cpp Fri Jul  2 16:13:23 2010
@@ -45,7 +45,7 @@
   
   if (isa<ConstantInt>(C) || isa<ConstantFP>(C) ||
       isa<ConstantPointerNull>(C) || isa<ConstantAggregateZero>(C) ||
-      isa<UndefValue>(C) || isa<MDString>(C))
+      isa<UndefValue>(C))
     return VMSlot = C;           // Primitive constants map directly
   
   if (ConstantArray *CA = dyn_cast<ConstantArray>(C)) {




From grosbach at apple.com  Fri Jul  2 16:23:37 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 02 Jul 2010 21:23:37 -0000
Subject: [llvm-commits] [llvm] r107517 -
	/llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp
Message-ID: <20100702212337.4AF9C2A6C12D@llvm.org>

Author: grosbach
Date: Fri Jul  2 16:23:37 2010
New Revision: 107517

URL: http://llvm.org/viewvc/llvm-project?rev=107517&view=rev
Log:
Custom inserters (e.g., conditional moves in Thumb1 can introduce
new basic blocks, and if used as a function argument, that can cause call frame
setup / destroy pairs to be split across a basic block boundary. That prevents
us from doing a simple assertion to check that the pairs match and alloc/
dealloc the same amount of space. Modify the assertion to only check the
amount allocated when there are matching pairs in the same basic block.

rdar://8022442

Modified:
    llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp

Modified: llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp?rev=107517&r1=107516&r2=107517&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp (original)
+++ llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp Fri Jul  2 16:23:37 2010
@@ -642,6 +642,9 @@
 
   for (MachineFunction::iterator BB = Fn.begin(),
          E = Fn.end(); BB != E; ++BB) {
+#ifndef NDEBUG
+    int SPAdjCount = 0; // frame setup / destroy count.
+#endif
     int SPAdj = 0;  // SP offset due to call frame setup / destroy.
     if (RS && !FrameIndexVirtualScavenging) RS->enterBasicBlock(BB);
 
@@ -649,6 +652,10 @@
 
       if (I->getOpcode() == FrameSetupOpcode ||
           I->getOpcode() == FrameDestroyOpcode) {
+#ifndef NDEBUG
+        // Track whether we see even pairs of them
+        SPAdjCount += I->getOpcode() == FrameSetupOpcode ? 1 : -1;
+#endif
         // Remember how much SP has been adjusted to create the call
         // frame.
         int Size = I->getOperand(0).getImm();
@@ -715,7 +722,13 @@
       if (RS && !FrameIndexVirtualScavenging && MI) RS->forward(MI);
     }
 
-    assert(SPAdj == 0 && "Unbalanced call frame setup / destroy pairs?");
+    // If we have evenly matched pairs of frame setup / destroy instructions,
+    // make sure the adjustments come out to zero. If we don't have matched
+    // pairs, we can't be sure the missing bit isn't in another basic block
+    // due to a custom inserter playing tricks, so just asserting SPAdj==0
+    // isn't sufficient. See tMOVCC on Thumb1, for example.
+    assert((SPAdjCount || SPAdj == 0) &&
+           "Unbalanced call frame setup / destroy pairs?");
   }
 }
 




From bob.wilson at apple.com  Fri Jul  2 16:29:29 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Fri, 02 Jul 2010 21:29:29 -0000
Subject: [llvm-commits] [test-suite] r107519 -
	/test-suite/trunk/Makefile.rules
Message-ID: <20100702212929.755DE2A6C12C@llvm.org>

Author: bwilson
Date: Fri Jul  2 16:29:29 2010
New Revision: 107519

URL: http://llvm.org/viewvc/llvm-project?rev=107519&view=rev
Log:
Set CONFIGURATION variable to match the BuildMode variable in llvm's top-level
Makefile.rules.  It was inconsistent for "Release+Debug" builds.

Modified:
    test-suite/trunk/Makefile.rules

Modified: test-suite/trunk/Makefile.rules
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/Makefile.rules?rev=107519&r1=107518&r2=107519&view=diff
==============================================================================
--- test-suite/trunk/Makefile.rules (original)
+++ test-suite/trunk/Makefile.rules Fri Jul  2 16:29:29 2010
@@ -137,13 +137,19 @@
 
 ifeq ($(ENABLE_PROFILING),1)
   ENABLE_OPTIMIZED = 1
-  CONFIGURATION := Profile
-else
-  ifeq ($(ENABLE_OPTIMIZED),1)
-    CONFIGURATION := Release
-  else
-    CONFIGURATION := Debug
+endif
+
+ifeq ($(ENABLE_OPTIMIZED),1)
+  CONFIGURATION := Release
+  ifdef DEBUG_SYMBOLS
+    CONFIGURATION := $(CONFIGURATION)+Debug
   endif
+else
+  CONFIGURATION := Debug
+endif
+
+ifeq ($(ENABLE_PROFILING),1)
+  CONFIGURATION := $(CONFIGURATION)+Profile
 endif
 
 # If ENABLE_ASSERTIONS=1 is specified (make command line or configured),




From stoklund at 2pi.dk  Fri Jul  2 16:44:22 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Fri, 02 Jul 2010 21:44:22 -0000
Subject: [llvm-commits] [llvm] r107520 - in /llvm/trunk:
 include/llvm/Target/Target.td include/llvm/Target/TargetOpcodes.h
 utils/TableGen/CodeEmitterGen.cpp utils/TableGen/CodeGenTarget.cpp
Message-ID: <20100702214422.765152A6C12C@llvm.org>

Author: stoklund
Date: Fri Jul  2 16:44:22 2010
New Revision: 107520

URL: http://llvm.org/viewvc/llvm-project?rev=107520&view=rev
Log:
Clean up TargetOpcodes.h a bit, and limit the number of places where the full
list of predefined instructions appear. Add some consistency checks.

Ideally, TargetOpcodes.h should be produced by TableGen from Target.td, but it
is hardly worth the effort.

Modified:
    llvm/trunk/include/llvm/Target/Target.td
    llvm/trunk/include/llvm/Target/TargetOpcodes.h
    llvm/trunk/utils/TableGen/CodeEmitterGen.cpp
    llvm/trunk/utils/TableGen/CodeGenTarget.cpp

Modified: llvm/trunk/include/llvm/Target/Target.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=107520&r1=107519&r2=107520&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/Target.td (original)
+++ llvm/trunk/include/llvm/Target/Target.td Fri Jul  2 16:44:22 2010
@@ -396,24 +396,23 @@
 }
 
 // Standard Pseudo Instructions.
-let isCodeGenOnly = 1 in {
+// This list must match TargetOpcodes.h and CodeGenTarget.cpp.
+// Only these instructions are allowed in the TargetOpcode namespace.
+let isCodeGenOnly = 1, Namespace = "TargetOpcode" in {
 def PHI : Instruction {
   let OutOperandList = (outs);
   let InOperandList = (ins variable_ops);
   let AsmString = "PHINODE";
-  let Namespace = "TargetOpcode";
 }
 def INLINEASM : Instruction {
   let OutOperandList = (outs);
   let InOperandList = (ins variable_ops);
   let AsmString = "";
-  let Namespace = "TargetOpcode";
 }
 def DBG_LABEL : Instruction {
   let OutOperandList = (outs);
   let InOperandList = (ins i32imm:$id);
   let AsmString = "";
-  let Namespace = "TargetOpcode";
   let hasCtrlDep = 1;
   let isNotDuplicable = 1;
 }
@@ -421,7 +420,6 @@
   let OutOperandList = (outs);
   let InOperandList = (ins i32imm:$id);
   let AsmString = "";
-  let Namespace = "TargetOpcode";
   let hasCtrlDep = 1;
   let isNotDuplicable = 1;
 }
@@ -429,7 +427,6 @@
   let OutOperandList = (outs);
   let InOperandList = (ins i32imm:$id);
   let AsmString = "";
-  let Namespace = "TargetOpcode";
   let hasCtrlDep = 1;
   let isNotDuplicable = 1;
 }
@@ -437,21 +434,18 @@
   let OutOperandList = (outs);
   let InOperandList = (ins variable_ops);
   let AsmString = "";
-  let Namespace = "TargetOpcode";
   let neverHasSideEffects = 1;
 }
 def EXTRACT_SUBREG : Instruction {
   let OutOperandList = (outs unknown:$dst);
   let InOperandList = (ins unknown:$supersrc, i32imm:$subidx);
   let AsmString = "";
-  let Namespace = "TargetOpcode";
   let neverHasSideEffects = 1;
 }
 def INSERT_SUBREG : Instruction {
   let OutOperandList = (outs unknown:$dst);
   let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
   let AsmString = "";
-  let Namespace = "TargetOpcode";
   let neverHasSideEffects = 1;
   let Constraints = "$supersrc = $dst";
 }
@@ -459,7 +453,6 @@
   let OutOperandList = (outs unknown:$dst);
   let InOperandList = (ins);
   let AsmString = "";
-  let Namespace = "TargetOpcode";
   let neverHasSideEffects = 1;
   let isReMaterializable = 1;
   let isAsCheapAsAMove = 1;
@@ -468,14 +461,12 @@
   let OutOperandList = (outs unknown:$dst);
   let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
   let AsmString = "";
-  let Namespace = "TargetOpcode";
   let neverHasSideEffects = 1;
 }
 def COPY_TO_REGCLASS : Instruction {
   let OutOperandList = (outs unknown:$dst);
   let InOperandList = (ins unknown:$src, i32imm:$regclass);
   let AsmString = "";
-  let Namespace = "TargetOpcode";
   let neverHasSideEffects = 1;
   let isAsCheapAsAMove = 1;
 }
@@ -483,7 +474,6 @@
   let OutOperandList = (outs);
   let InOperandList = (ins variable_ops);
   let AsmString = "DBG_VALUE";
-  let Namespace = "TargetOpcode";
   let isAsCheapAsAMove = 1;
 }
 
@@ -491,7 +481,6 @@
   let OutOperandList = (outs unknown:$dst);
   let InOperandList = (ins variable_ops);
   let AsmString = "";
-  let Namespace = "TargetOpcode";
   let neverHasSideEffects = 1;
   let isAsCheapAsAMove = 1;
 }

Modified: llvm/trunk/include/llvm/Target/TargetOpcodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetOpcodes.h?rev=107520&r1=107519&r2=107520&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetOpcodes.h (original)
+++ llvm/trunk/include/llvm/Target/TargetOpcodes.h Fri Jul  2 16:44:22 2010
@@ -15,27 +15,31 @@
 #define LLVM_TARGET_TARGETOPCODES_H
 
 namespace llvm {
-  
+
 /// Invariant opcodes: All instruction sets have these as their low opcodes.
+///
+/// Every instruction defined here must also appear in Target.td and the order
+/// must be the same as in CodeGenTarget.cpp.
+///
 namespace TargetOpcode {
-  enum { 
+  enum {
     PHI = 0,
     INLINEASM = 1,
     DBG_LABEL = 2,
     EH_LABEL = 3,
     GC_LABEL = 4,
-    
+
     /// KILL - This instruction is a noop that is used only to adjust the
     /// liveness of registers. This can be useful when dealing with
     /// sub-registers.
     KILL = 5,
-    
+
     /// EXTRACT_SUBREG - This instruction takes two operands: a register
     /// that has subregisters, and a subregister index. It returns the
     /// extracted subregister value. This is commonly used to implement
     /// truncation operations on target architectures which support it.
     EXTRACT_SUBREG = 6,
-    
+
     /// INSERT_SUBREG - This instruction takes three operands: a register that
     /// has subregisters, a register providing an insert value, and a
     /// subregister index. It returns the value of the first register with the
@@ -43,16 +47,16 @@
     /// defined by an IMPLICIT_DEF, because it is commonly used to implement
     /// anyext operations on target architectures which support it.
     INSERT_SUBREG = 7,
-    
+
     /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
     IMPLICIT_DEF = 8,
-    
+
     /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that
     /// the first operand is an immediate integer constant. This constant is
     /// often zero, because it is commonly used to assert that the instruction
     /// defining the register implicitly clears the high bits.
     SUBREG_TO_REG = 9,
-    
+
     /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain
     /// register-to-register copy into a specific register class. This is only
     /// used between instruction selection and MachineInstr creation, before

Modified: llvm/trunk/utils/TableGen/CodeEmitterGen.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeEmitterGen.cpp?rev=107520&r1=107519&r2=107520&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeEmitterGen.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeEmitterGen.cpp Fri Jul  2 16:44:22 2010
@@ -24,19 +24,8 @@
   for (std::vector<Record*>::iterator I = Insts.begin(), E = Insts.end();
        I != E; ++I) {
     Record *R = *I;
-    if (R->getName() == "PHI" ||
-        R->getName() == "INLINEASM" ||
-        R->getName() == "DBG_LABEL" ||
-        R->getName() == "EH_LABEL" ||
-        R->getName() == "GC_LABEL" ||
-        R->getName() == "KILL" ||
-        R->getName() == "EXTRACT_SUBREG" ||
-        R->getName() == "INSERT_SUBREG" ||
-        R->getName() == "IMPLICIT_DEF" ||
-        R->getName() == "SUBREG_TO_REG" ||
-        R->getName() == "COPY_TO_REGCLASS" ||
-        R->getName() == "DBG_VALUE" ||
-        R->getName() == "REG_SEQUENCE") continue;
+    if (R->getValueAsString("Namespace") == "TargetOpcode")
+      continue;
 
     BitsInit *BI = R->getValueAsBitsInit("Inst");
 
@@ -103,19 +92,7 @@
     const CodeGenInstruction *CGI = *IN;
     Record *R = CGI->TheDef;
     
-    if (R->getName() == "PHI" ||
-        R->getName() == "INLINEASM" ||
-        R->getName() == "DBG_LABEL" ||
-        R->getName() == "EH_LABEL" ||
-        R->getName() == "GC_LABEL" ||
-        R->getName() == "KILL" ||
-        R->getName() == "EXTRACT_SUBREG" ||
-        R->getName() == "INSERT_SUBREG" ||
-        R->getName() == "IMPLICIT_DEF" ||
-        R->getName() == "SUBREG_TO_REG" ||
-        R->getName() == "COPY_TO_REGCLASS" ||
-        R->getName() == "DBG_VALUE" ||
-        R->getName() == "REG_SEQUENCE") {
+    if (R->getValueAsString("Namespace") == "TargetOpcode") {
       o << "    0U,\n";
       continue;
     }
@@ -140,22 +117,10 @@
   for (std::vector<Record*>::iterator IC = Insts.begin(), EC = Insts.end();
         IC != EC; ++IC) {
     Record *R = *IC;
+    if (R->getValueAsString("Namespace") == "TargetOpcode")
+      continue;
     const std::string &InstName = R->getName();
     std::string Case("");
-    
-    if (InstName == "PHI" ||
-        InstName == "INLINEASM" ||
-        InstName == "DBG_LABEL"||
-        InstName == "EH_LABEL"||
-        InstName == "GC_LABEL"||
-        InstName == "KILL"||
-        InstName == "EXTRACT_SUBREG" ||
-        InstName == "INSERT_SUBREG" ||
-        InstName == "IMPLICIT_DEF" ||
-        InstName == "SUBREG_TO_REG" ||
-        InstName == "COPY_TO_REGCLASS" ||
-        InstName == "DBG_VALUE" ||
-        InstName == "REG_SEQUENCE") continue;
 
     BitsInit *BI = R->getValueAsBitsInit("Inst");
     const std::vector<RecordVal> &Vals = R->getValues();

Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=107520&r1=107519&r2=107520&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Fri Jul  2 16:44:22 2010
@@ -329,61 +329,41 @@
 /// getInstructionsByEnumValue - Return all of the instructions defined by the
 /// target, ordered by their enum value.
 void CodeGenTarget::ComputeInstrsByEnum() const {
+  // The ordering here must match the ordering in TargetOpcodes.h.
+  const char *const FixedInstrs[] = {
+    "PHI",
+    "INLINEASM",
+    "DBG_LABEL",
+    "EH_LABEL",
+    "GC_LABEL",
+    "KILL",
+    "EXTRACT_SUBREG",
+    "INSERT_SUBREG",
+    "IMPLICIT_DEF",
+    "SUBREG_TO_REG",
+    "COPY_TO_REGCLASS",
+    "DBG_VALUE",
+    "REG_SEQUENCE",
+    0
+  };
   const DenseMap<const Record*, CodeGenInstruction*> &Insts = getInstructions();
-  const CodeGenInstruction *PHI = GetInstByName("PHI", Insts);
-  const CodeGenInstruction *INLINEASM = GetInstByName("INLINEASM", Insts);
-  const CodeGenInstruction *DBG_LABEL = GetInstByName("DBG_LABEL", Insts);
-  const CodeGenInstruction *EH_LABEL = GetInstByName("EH_LABEL", Insts);
-  const CodeGenInstruction *GC_LABEL = GetInstByName("GC_LABEL", Insts);
-  const CodeGenInstruction *KILL = GetInstByName("KILL", Insts);
-  const CodeGenInstruction *EXTRACT_SUBREG =
-    GetInstByName("EXTRACT_SUBREG", Insts);
-  const CodeGenInstruction *INSERT_SUBREG =
-    GetInstByName("INSERT_SUBREG", Insts);
-  const CodeGenInstruction *IMPLICIT_DEF = GetInstByName("IMPLICIT_DEF", Insts);
-  const CodeGenInstruction *SUBREG_TO_REG =
-    GetInstByName("SUBREG_TO_REG", Insts);
-  const CodeGenInstruction *COPY_TO_REGCLASS =
-    GetInstByName("COPY_TO_REGCLASS", Insts);
-  const CodeGenInstruction *DBG_VALUE = GetInstByName("DBG_VALUE", Insts);
-  const CodeGenInstruction *REG_SEQUENCE = GetInstByName("REG_SEQUENCE", Insts);
-
-  // Print out the rest of the instructions now.
-  InstrsByEnum.push_back(PHI);
-  InstrsByEnum.push_back(INLINEASM);
-  InstrsByEnum.push_back(DBG_LABEL);
-  InstrsByEnum.push_back(EH_LABEL);
-  InstrsByEnum.push_back(GC_LABEL);
-  InstrsByEnum.push_back(KILL);
-  InstrsByEnum.push_back(EXTRACT_SUBREG);
-  InstrsByEnum.push_back(INSERT_SUBREG);
-  InstrsByEnum.push_back(IMPLICIT_DEF);
-  InstrsByEnum.push_back(SUBREG_TO_REG);
-  InstrsByEnum.push_back(COPY_TO_REGCLASS);
-  InstrsByEnum.push_back(DBG_VALUE);
-  InstrsByEnum.push_back(REG_SEQUENCE);
-  
+  for (const char *const *p = FixedInstrs; *p; ++p) {
+    const CodeGenInstruction *Instr = GetInstByName(*p, Insts);
+    assert(Instr && "Missing target independent instruction");
+    assert(Instr->Namespace == "TargetOpcode" && "Bad namespace");
+    InstrsByEnum.push_back(Instr);
+  }
   unsigned EndOfPredefines = InstrsByEnum.size();
-  
+
   for (DenseMap<const Record*, CodeGenInstruction*>::const_iterator
        I = Insts.begin(), E = Insts.end(); I != E; ++I) {
     const CodeGenInstruction *CGI = I->second;
-    if (CGI != PHI &&
-        CGI != INLINEASM &&
-        CGI != DBG_LABEL &&
-        CGI != EH_LABEL &&
-        CGI != GC_LABEL &&
-        CGI != KILL &&
-        CGI != EXTRACT_SUBREG &&
-        CGI != INSERT_SUBREG &&
-        CGI != IMPLICIT_DEF &&
-        CGI != SUBREG_TO_REG &&
-        CGI != COPY_TO_REGCLASS &&
-        CGI != DBG_VALUE &&
-        CGI != REG_SEQUENCE)
+    if (CGI->Namespace != "TargetOpcode")
       InstrsByEnum.push_back(CGI);
   }
-  
+
+  assert(InstrsByEnum.size() == Insts.size() && "Missing predefined instr");
+
   // All of the instructions are now in random order based on the map iteration.
   // Sort them by name.
   std::sort(InstrsByEnum.begin()+EndOfPredefines, InstrsByEnum.end(),




From bruno.cardoso at gmail.com  Fri Jul  2 17:06:54 2010
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Fri, 02 Jul 2010 22:06:54 -0000
Subject: [llvm-commits] [llvm] r107523 - in /llvm/trunk:
 lib/Target/X86/X86InstrSSE.td lib/Target/X86/X86MCCodeEmitter.cpp
 test/MC/AsmParser/X86/x86_32-encoding.s
 test/MC/AsmParser/X86/x86_64-encoding.s
Message-ID: <20100702220654.CBBE52A6C12C@llvm.org>

Author: bruno
Date: Fri Jul  2 17:06:54 2010
New Revision: 107523

URL: http://llvm.org/viewvc/llvm-project?rev=107523&view=rev
Log:
- Add support for the rest of AVX SSE3 instructions
- Fix VEX prefix to be emitted with 3 bytes whenever VEX_5M
represents a REX equivalent two byte leading opcode


Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp
    llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
    llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=107523&r1=107522&r2=107523&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Fri Jul  2 17:06:54 2010
@@ -3380,6 +3380,18 @@
                        (bitconvert (mem_frag128 addr:$src))))]>, OpSize;
 }
 
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE3] in {
+  defm VPABSB  : SS3I_unop_rm_int<0x1C, "vpabsb", memopv8i8, memopv16i8,
+                                  int_x86_ssse3_pabs_b,
+                                  int_x86_ssse3_pabs_b_128>, VEX;
+  defm VPABSW  : SS3I_unop_rm_int<0x1D, "vpabsw", memopv4i16, memopv8i16,
+                                  int_x86_ssse3_pabs_w,
+                                  int_x86_ssse3_pabs_w_128>, VEX;
+  defm VPABSD  : SS3I_unop_rm_int<0x1E, "vpabsd", memopv2i32, memopv4i32,
+                                  int_x86_ssse3_pabs_d,
+                                  int_x86_ssse3_pabs_d_128>, VEX;
+}
+
 defm PABSB       : SS3I_unop_rm_int<0x1C, "pabsb", memopv8i8, memopv16i8,
                                     int_x86_ssse3_pabs_b,
                                     int_x86_ssse3_pabs_b_128>;
@@ -3433,6 +3445,47 @@
           (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
 }
 
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE3] in {
+let isCommutable = 0 in {
+  defm VPHADDW    : SS3I_binop_rm_int<0x01, "vphaddw", memopv4i16, memopv8i16,
+                                      int_x86_ssse3_phadd_w,
+                                      int_x86_ssse3_phadd_w_128, 0>, VEX_4V;
+  defm VPHADDD    : SS3I_binop_rm_int<0x02, "vphaddd", memopv2i32, memopv4i32,
+                                      int_x86_ssse3_phadd_d,
+                                      int_x86_ssse3_phadd_d_128, 0>, VEX_4V;
+  defm VPHADDSW   : SS3I_binop_rm_int<0x03, "vphaddsw", memopv4i16, memopv8i16,
+                                      int_x86_ssse3_phadd_sw,
+                                      int_x86_ssse3_phadd_sw_128, 0>, VEX_4V;
+  defm VPHSUBW    : SS3I_binop_rm_int<0x05, "vphsubw", memopv4i16, memopv8i16,
+                                      int_x86_ssse3_phsub_w,
+                                      int_x86_ssse3_phsub_w_128, 0>, VEX_4V;
+  defm VPHSUBD    : SS3I_binop_rm_int<0x06, "vphsubd", memopv2i32, memopv4i32,
+                                      int_x86_ssse3_phsub_d,
+                                      int_x86_ssse3_phsub_d_128, 0>, VEX_4V;
+  defm VPHSUBSW   : SS3I_binop_rm_int<0x07, "vphsubsw", memopv4i16, memopv8i16,
+                                      int_x86_ssse3_phsub_sw,
+                                      int_x86_ssse3_phsub_sw_128, 0>, VEX_4V;
+  defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", memopv8i8, memopv16i8,
+                                      int_x86_ssse3_pmadd_ub_sw,
+                                      int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V;
+  defm VPSHUFB    : SS3I_binop_rm_int<0x00, "vpshufb", memopv8i8, memopv16i8,
+                                      int_x86_ssse3_pshuf_b,
+                                      int_x86_ssse3_pshuf_b_128, 0>, VEX_4V;
+  defm VPSIGNB    : SS3I_binop_rm_int<0x08, "vpsignb", memopv8i8, memopv16i8,
+                                      int_x86_ssse3_psign_b,
+                                      int_x86_ssse3_psign_b_128, 0>, VEX_4V;
+  defm VPSIGNW    : SS3I_binop_rm_int<0x09, "vpsignw", memopv4i16, memopv8i16,
+                                      int_x86_ssse3_psign_w,
+                                      int_x86_ssse3_psign_w_128, 0>, VEX_4V;
+  defm VPSIGND    : SS3I_binop_rm_int<0x0A, "vpsignd", memopv2i32, memopv4i32,
+                                      int_x86_ssse3_psign_d,
+                                      int_x86_ssse3_psign_d_128, 0>, VEX_4V;
+}
+defm VPMULHRSW    : SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv4i16, memopv8i16,
+                                      int_x86_ssse3_pmul_hr_sw,
+                                      int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V;
+}
+
 // None of these have i8 immediate fields.
 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
 let isCommutable = 0 in {
@@ -3484,26 +3537,43 @@
 // SSSE3 - Packed Align Instruction Patterns
 //===---------------------------------------------------------------------===//
 
-let Constraints = "$src1 = $dst" in {
-  def PALIGNR64rr  : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
-                           (ins VR64:$src1, VR64:$src2, i8imm:$src3),
-                           "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
-                           []>;
-  def PALIGNR64rm  : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
-                           (ins VR64:$src1, i64mem:$src2, i8imm:$src3),
-                           "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
-                           []>;
-
-  def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
-                           (ins VR128:$src1, VR128:$src2, i8imm:$src3),
-                           "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
-                           []>, OpSize;
-  def PALIGNR128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
-                           (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
-                           "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
-                           []>, OpSize;
+multiclass sse3_palign<string asm, bit Is2Addr = 1> {
+  def R64rr  : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
+      (ins VR64:$src1, VR64:$src2, i8imm:$src3),
+      !if(Is2Addr,
+        !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
+        !strconcat(asm,
+                  "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
+      []>;
+  def R64rm  : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
+      (ins VR64:$src1, i64mem:$src2, i8imm:$src3),
+      !if(Is2Addr,
+        !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
+        !strconcat(asm,
+                  "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
+      []>;
+
+  def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
+      (ins VR128:$src1, VR128:$src2, i8imm:$src3),
+      !if(Is2Addr,
+        !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
+        !strconcat(asm,
+                  "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
+      []>, OpSize;
+  def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
+      (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
+      !if(Is2Addr,
+        !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
+        !strconcat(asm,
+                  "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
+      []>, OpSize;
 }
 
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE3] in
+  defm VPALIGN : sse3_palign<"vpalignr", 0>, VEX_4V;
+let Constraints = "$src1 = $dst" in
+  defm PALIGN : sse3_palign<"palignr">;
+
 let AddedComplexity = 5 in {
 
 def : Pat<(v1i64 (palign:$src3 VR64:$src1, VR64:$src2)),

Modified: llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp?rev=107523&r1=107522&r2=107523&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp Fri Jul  2 17:06:54 2010
@@ -543,7 +543,7 @@
   //
   unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
 
-  if (VEX_B && VEX_X && !VEX_W) { // 2 byte VEX prefix
+  if (VEX_B && VEX_X && !VEX_W && (VEX_5M == 1)) { // 2 byte VEX prefix
     EmitByte(0xC5, CurByte, OS);
     EmitByte(LastByte | (VEX_R << 7), CurByte, OS);
     return;

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s?rev=107523&r1=107522&r2=107523&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s Fri Jul  2 17:06:54 2010
@@ -11614,3 +11614,131 @@
 // CHECK: encoding: [0xc5,0xe9,0x7d,0x18]
           vhsubpd  (%eax), %xmm2, %xmm3
 
+// CHECK: vpabsb  %xmm1, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x79,0x1c,0xd1]
+          vpabsb  %xmm1, %xmm2
+
+// CHECK: vpabsb  (%eax), %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x79,0x1c,0x10]
+          vpabsb  (%eax), %xmm2
+
+// CHECK: vpabsw  %xmm1, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x79,0x1d,0xd1]
+          vpabsw  %xmm1, %xmm2
+
+// CHECK: vpabsw  (%eax), %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x79,0x1d,0x10]
+          vpabsw  (%eax), %xmm2
+
+// CHECK: vpabsd  %xmm1, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x79,0x1e,0xd1]
+          vpabsd  %xmm1, %xmm2
+
+// CHECK: vpabsd  (%eax), %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x79,0x1e,0x10]
+          vpabsd  (%eax), %xmm2
+
+// CHECK: vphaddw  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x01,0xd9]
+          vphaddw  %xmm1, %xmm2, %xmm3
+
+// CHECK: vphaddw  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x01,0x18]
+          vphaddw  (%eax), %xmm2, %xmm3
+
+// CHECK: vphaddd  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x02,0xd9]
+          vphaddd  %xmm1, %xmm2, %xmm3
+
+// CHECK: vphaddd  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x02,0x18]
+          vphaddd  (%eax), %xmm2, %xmm3
+
+// CHECK: vphaddsw  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x03,0xd9]
+          vphaddsw  %xmm1, %xmm2, %xmm3
+
+// CHECK: vphaddsw  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x03,0x18]
+          vphaddsw  (%eax), %xmm2, %xmm3
+
+// CHECK: vphsubw  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x05,0xd9]
+          vphsubw  %xmm1, %xmm2, %xmm3
+
+// CHECK: vphsubw  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x05,0x18]
+          vphsubw  (%eax), %xmm2, %xmm3
+
+// CHECK: vphsubd  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x06,0xd9]
+          vphsubd  %xmm1, %xmm2, %xmm3
+
+// CHECK: vphsubd  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x06,0x18]
+          vphsubd  (%eax), %xmm2, %xmm3
+
+// CHECK: vphsubsw  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x07,0xd9]
+          vphsubsw  %xmm1, %xmm2, %xmm3
+
+// CHECK: vphsubsw  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x07,0x18]
+          vphsubsw  (%eax), %xmm2, %xmm3
+
+// CHECK: vpmaddubsw  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x04,0xd9]
+          vpmaddubsw  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpmaddubsw  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x04,0x18]
+          vpmaddubsw  (%eax), %xmm2, %xmm3
+
+// CHECK: vpshufb  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x00,0xd9]
+          vpshufb  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpshufb  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x00,0x18]
+          vpshufb  (%eax), %xmm2, %xmm3
+
+// CHECK: vpsignb  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x08,0xd9]
+          vpsignb  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpsignb  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x08,0x18]
+          vpsignb  (%eax), %xmm2, %xmm3
+
+// CHECK: vpsignw  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x09,0xd9]
+          vpsignw  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpsignw  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x09,0x18]
+          vpsignw  (%eax), %xmm2, %xmm3
+
+// CHECK: vpsignd  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x0a,0xd9]
+          vpsignd  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpsignd  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x0a,0x18]
+          vpsignd  (%eax), %xmm2, %xmm3
+
+// CHECK: vpmulhrsw  %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x0b,0xd9]
+          vpmulhrsw  %xmm1, %xmm2, %xmm3
+
+// CHECK: vpmulhrsw  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x0b,0x18]
+          vpmulhrsw  (%eax), %xmm2, %xmm3
+
+// CHECK: vpalignr  $7, %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe3,0x69,0x0f,0xd9,0x07]
+          vpalignr  $7, %xmm1, %xmm2, %xmm3
+
+// CHECK: vpalignr  $7, (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe3,0x69,0x0f,0x18,0x07]
+          vpalignr  $7, (%eax), %xmm2, %xmm3
+

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s?rev=107523&r1=107522&r2=107523&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s Fri Jul  2 17:06:54 2010
@@ -1662,3 +1662,131 @@
 // CHECK: encoding: [0xc5,0x19,0x7d,0x28]
           vhsubpd  (%rax), %xmm12, %xmm13
 
+// CHECK: vpabsb  %xmm11, %xmm12
+// CHECK: encoding: [0xc4,0x42,0x79,0x1c,0xe3]
+          vpabsb  %xmm11, %xmm12
+
+// CHECK: vpabsb  (%rax), %xmm12
+// CHECK: encoding: [0xc4,0x62,0x79,0x1c,0x20]
+          vpabsb  (%rax), %xmm12
+
+// CHECK: vpabsw  %xmm11, %xmm12
+// CHECK: encoding: [0xc4,0x42,0x79,0x1d,0xe3]
+          vpabsw  %xmm11, %xmm12
+
+// CHECK: vpabsw  (%rax), %xmm12
+// CHECK: encoding: [0xc4,0x62,0x79,0x1d,0x20]
+          vpabsw  (%rax), %xmm12
+
+// CHECK: vpabsd  %xmm11, %xmm12
+// CHECK: encoding: [0xc4,0x42,0x79,0x1e,0xe3]
+          vpabsd  %xmm11, %xmm12
+
+// CHECK: vpabsd  (%rax), %xmm12
+// CHECK: encoding: [0xc4,0x62,0x79,0x1e,0x20]
+          vpabsd  (%rax), %xmm12
+
+// CHECK: vphaddw  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x42,0x19,0x01,0xeb]
+          vphaddw  %xmm11, %xmm12, %xmm13
+
+// CHECK: vphaddw  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x01,0x28]
+          vphaddw  (%rax), %xmm12, %xmm13
+
+// CHECK: vphaddd  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x42,0x19,0x02,0xeb]
+          vphaddd  %xmm11, %xmm12, %xmm13
+
+// CHECK: vphaddd  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x02,0x28]
+          vphaddd  (%rax), %xmm12, %xmm13
+
+// CHECK: vphaddsw  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x42,0x19,0x03,0xeb]
+          vphaddsw  %xmm11, %xmm12, %xmm13
+
+// CHECK: vphaddsw  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x03,0x28]
+          vphaddsw  (%rax), %xmm12, %xmm13
+
+// CHECK: vphsubw  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x42,0x19,0x05,0xeb]
+          vphsubw  %xmm11, %xmm12, %xmm13
+
+// CHECK: vphsubw  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x05,0x28]
+          vphsubw  (%rax), %xmm12, %xmm13
+
+// CHECK: vphsubd  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x42,0x19,0x06,0xeb]
+          vphsubd  %xmm11, %xmm12, %xmm13
+
+// CHECK: vphsubd  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x06,0x28]
+          vphsubd  (%rax), %xmm12, %xmm13
+
+// CHECK: vphsubsw  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x42,0x19,0x07,0xeb]
+          vphsubsw  %xmm11, %xmm12, %xmm13
+
+// CHECK: vphsubsw  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x07,0x28]
+          vphsubsw  (%rax), %xmm12, %xmm13
+
+// CHECK: vpmaddubsw  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x42,0x19,0x04,0xeb]
+          vpmaddubsw  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpmaddubsw  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x04,0x28]
+          vpmaddubsw  (%rax), %xmm12, %xmm13
+
+// CHECK: vpshufb  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x42,0x19,0x00,0xeb]
+          vpshufb  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpshufb  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x00,0x28]
+          vpshufb  (%rax), %xmm12, %xmm13
+
+// CHECK: vpsignb  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x42,0x19,0x08,0xeb]
+          vpsignb  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpsignb  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x08,0x28]
+          vpsignb  (%rax), %xmm12, %xmm13
+
+// CHECK: vpsignw  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x42,0x19,0x09,0xeb]
+          vpsignw  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpsignw  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x09,0x28]
+          vpsignw  (%rax), %xmm12, %xmm13
+
+// CHECK: vpsignd  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x42,0x19,0x0a,0xeb]
+          vpsignd  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpsignd  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x0a,0x28]
+          vpsignd  (%rax), %xmm12, %xmm13
+
+// CHECK: vpmulhrsw  %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x42,0x19,0x0b,0xeb]
+          vpmulhrsw  %xmm11, %xmm12, %xmm13
+
+// CHECK: vpmulhrsw  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x0b,0x28]
+          vpmulhrsw  (%rax), %xmm12, %xmm13
+
+// CHECK: vpalignr  $7, %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x43,0x19,0x0f,0xeb,0x07]
+          vpalignr  $7, %xmm11, %xmm12, %xmm13
+
+// CHECK: vpalignr  $7, (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x63,0x19,0x0f,0x28,0x07]
+          vpalignr  $7, (%rax), %xmm12, %xmm13
+




From scanon at apple.com  Fri Jul  2 17:10:59 2010
From: scanon at apple.com (Stephen Canon)
Date: Fri, 02 Jul 2010 22:10:59 -0000
Subject: [llvm-commits] [compiler-rt] r107524 - in /compiler-rt/trunk/lib:
	fixdfsi.c fixsfsi.c
Message-ID: <20100702221059.131492A6C12C@llvm.org>

Author: scanon
Date: Fri Jul  2 17:10:58 2010
New Revision: 107524

URL: http://llvm.org/viewvc/llvm-project?rev=107524&view=rev
Log:
float- and double-to-integer soft-float conversions for compiler-rt

Added:
    compiler-rt/trunk/lib/fixdfsi.c
    compiler-rt/trunk/lib/fixsfsi.c

Added: compiler-rt/trunk/lib/fixdfsi.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/fixdfsi.c?rev=107524&view=auto
==============================================================================
--- compiler-rt/trunk/lib/fixdfsi.c (added)
+++ compiler-rt/trunk/lib/fixdfsi.c Fri Jul  2 17:10:58 2010
@@ -0,0 +1,45 @@
+//===-- lib/fixdfsi.c - Double-precision -> integer conversion ----*- C -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements double-precision to integer conversion for the
+// compiler-rt library.  No range checking is performed; the behavior of this
+// conversion is undefined for out of range values in the C standard.
+//
+//===----------------------------------------------------------------------===//
+
+#define DOUBLE_PRECISION
+#include "fp_lib.h"
+
+int __fixdfsi(fp_t a) {
+    
+    // Break a into sign, exponent, significand
+    const rep_t aRep = toRep(a);
+    const rep_t aAbs = aRep & absMask;
+    const int sign = aRep & signBit ? -1 : 1;
+    const int exponent = (aAbs >> significandBits) - exponentBias;
+    const rep_t significand = (aAbs & significandMask) | implicitBit;
+    
+    // If 0 < exponent < significandBits, right shift to get the result.
+    if ((unsigned int)exponent < significandBits) {
+        return sign * (significand >> (significandBits - exponent));
+    }
+    
+    // If exponent is negative, the result is zero.
+    else if (exponent < 0) {
+        return 0;
+    }
+    
+    // If significandBits < exponent, left shift to get the result.  This shift
+    // may end up being larger than the type width, which incurs undefined
+    // behavior, but the conversion itself is undefined in that case, so
+    // whatever the compiler decides to do is fine.
+    else {
+        return sign * (significand << (exponent - significandBits));
+    }
+}

Added: compiler-rt/trunk/lib/fixsfsi.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/fixsfsi.c?rev=107524&view=auto
==============================================================================
--- compiler-rt/trunk/lib/fixsfsi.c (added)
+++ compiler-rt/trunk/lib/fixsfsi.c Fri Jul  2 17:10:58 2010
@@ -0,0 +1,45 @@
+//===-- lib/fixsfsi.c - Single-precision -> integer conversion ----*- C -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements single-precision to integer conversion for the
+// compiler-rt library.  No range checking is performed; the behavior of this
+// conversion is undefined for out of range values in the C standard.
+//
+//===----------------------------------------------------------------------===//
+
+#define SINGLE_PRECISION
+#include "fp_lib.h"
+
+int __fixsfsi(fp_t a) {
+    
+    // Break a into sign, exponent, significand
+    const rep_t aRep = toRep(a);
+    const rep_t aAbs = aRep & absMask;
+    const int sign = aRep & signBit ? -1 : 1;
+    const int exponent = (aAbs >> significandBits) - exponentBias;
+    const rep_t significand = (aAbs & significandMask) | implicitBit;
+    
+    // If 0 < exponent < significandBits, right shift to get the result.
+    if ((unsigned int)exponent < significandBits) {
+        return sign * (significand >> (significandBits - exponent));
+    }
+    
+    // If exponent is negative, the result is zero.
+    else if (exponent < 0) {
+        return 0;
+    }
+    
+    // If significandBits < exponent, left shift to get the result.  This shift
+    // may end up being larger than the type width, which incurs undefined
+    // behavior, but the conversion itself is undefined in that case, so
+    // whatever the compiler decides to do is fine.
+    else {
+        return sign * (significand << (exponent - significandBits));
+    }
+}




From stoklund at 2pi.dk  Fri Jul  2 17:29:50 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Fri, 02 Jul 2010 22:29:50 -0000
Subject: [llvm-commits] [llvm] r107529 - in /llvm/trunk:
 include/llvm/CodeGen/MachineInstr.h include/llvm/Target/Target.td
 include/llvm/Target/TargetOpcodes.h lib/CodeGen/LowerSubregs.cpp
 utils/TableGen/CodeGenTarget.cpp
Message-ID: <20100702222950.DC0692A6C12C@llvm.org>

Author: stoklund
Date: Fri Jul  2 17:29:50 2010
New Revision: 107529

URL: http://llvm.org/viewvc/llvm-project?rev=107529&view=rev
Log:
Add a new target independent COPY instruction and code to lower it.

The COPY instruction is intended to replace the target specific copy
instructions for virtual registers as well as the EXTRACT_SUBREG and
INSERT_SUBREG instructions in MachineFunctions. It won't we used in a selection
DAG.

COPY is lowered to native register copies by LowerSubregs.

Modified:
    llvm/trunk/include/llvm/CodeGen/MachineInstr.h
    llvm/trunk/include/llvm/Target/Target.td
    llvm/trunk/include/llvm/Target/TargetOpcodes.h
    llvm/trunk/lib/CodeGen/LowerSubregs.cpp
    llvm/trunk/utils/TableGen/CodeGenTarget.cpp

Modified: llvm/trunk/include/llvm/CodeGen/MachineInstr.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstr.h?rev=107529&r1=107528&r2=107529&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineInstr.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineInstr.h Fri Jul  2 17:29:50 2010
@@ -227,7 +227,10 @@
   bool isRegSequence() const {
     return getOpcode() == TargetOpcode::REG_SEQUENCE;
   }
-  
+  bool isCopy() const {
+    return getOpcode() == TargetOpcode::COPY;
+  }
+
   /// readsRegister - Return true if the MachineInstr reads the specified
   /// register. If TargetRegisterInfo is passed, then it also checks if there
   /// is a read of a super-register.

Modified: llvm/trunk/include/llvm/Target/Target.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=107529&r1=107528&r2=107529&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/Target.td (original)
+++ llvm/trunk/include/llvm/Target/Target.td Fri Jul  2 17:29:50 2010
@@ -476,7 +476,6 @@
   let AsmString = "DBG_VALUE";
   let isAsCheapAsAMove = 1;
 }
-
 def REG_SEQUENCE : Instruction {
   let OutOperandList = (outs unknown:$dst);
   let InOperandList = (ins variable_ops);
@@ -484,6 +483,13 @@
   let neverHasSideEffects = 1;
   let isAsCheapAsAMove = 1;
 }
+def COPY : Instruction {
+  let OutOperandList = (outs unknown:$dst);
+  let InOperandList = (ins unknown:$src);
+  let AsmString = "";
+  let neverHasSideEffects = 1;
+  let isAsCheapAsAMove = 1;
+}
 }
 
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/include/llvm/Target/TargetOpcodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetOpcodes.h?rev=107529&r1=107528&r2=107529&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetOpcodes.h (original)
+++ llvm/trunk/include/llvm/Target/TargetOpcodes.h Fri Jul  2 17:29:50 2010
@@ -75,7 +75,11 @@
     /// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5
     /// After register coalescing references of v1024 should be replace with
     /// v1027:3, v1025 with v1027:4, etc.
-    REG_SEQUENCE = 12
+    REG_SEQUENCE = 12,
+
+    /// COPY - Target-independent register copy. This instruction can also be
+    /// used to copy between subregisters of virtual registers.
+    COPY = 13
   };
 } // end namespace TargetOpcode
 } // end namespace llvm

Modified: llvm/trunk/lib/CodeGen/LowerSubregs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LowerSubregs.cpp?rev=107529&r1=107528&r2=107529&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LowerSubregs.cpp (original)
+++ llvm/trunk/lib/CodeGen/LowerSubregs.cpp Fri Jul  2 17:29:50 2010
@@ -56,6 +56,7 @@
     bool LowerExtract(MachineInstr *MI);
     bool LowerInsert(MachineInstr *MI);
     bool LowerSubregToReg(MachineInstr *MI);
+    bool LowerCopy(MachineInstr *MI);
 
     void TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
                           const TargetRegisterInfo *TRI);
@@ -321,6 +322,52 @@
   return true;
 }
 
+bool LowerSubregsInstructionPass::LowerCopy(MachineInstr *MI) {
+  MachineOperand &DstMO = MI->getOperand(0);
+  MachineOperand &SrcMO = MI->getOperand(1);
+
+  if (SrcMO.getReg() == DstMO.getReg()) {
+    DEBUG(dbgs() << "identity copy: " << *MI);
+    // No need to insert an identity copy instruction, but replace with a KILL
+    // if liveness is changed.
+    if (DstMO.isDead() || SrcMO.isUndef() || MI->getNumOperands() > 2) {
+      // We must make sure the super-register gets killed. Replace the
+      // instruction with KILL.
+      MI->setDesc(TII->get(TargetOpcode::KILL));
+      DEBUG(dbgs() << "replaced by:   " << *MI);
+      return true;
+    }
+    // Vanilla identity copy.
+    MI->eraseFromParent();
+    return true;
+  }
+
+  DEBUG(dbgs() << "real copy:   " << *MI);
+  // Ask target for a lowered copy instruction.
+  const TargetRegisterClass *DstRC =
+    TRI->getPhysicalRegisterRegClass(DstMO.getReg());
+  const TargetRegisterClass *SrcRC =
+    TRI->getPhysicalRegisterRegClass(SrcMO.getReg());
+  bool Emitted = TII->copyRegToReg(*MI->getParent(), MI,
+                                   DstMO.getReg(), SrcMO.getReg(),
+                                   DstRC, SrcRC, MI->getDebugLoc());
+  (void)Emitted;
+  assert(Emitted && "Cannot emit copy");
+
+  if (DstMO.isDead())
+    TransferDeadFlag(MI, DstMO.getReg(), TRI);
+  if (SrcMO.isKill())
+    TransferKillFlag(MI, SrcMO.getReg(), TRI, true);
+  if (MI->getNumOperands() > 2)
+    TransferImplicitDefs(MI);
+  DEBUG({
+    MachineBasicBlock::iterator dMI = MI;
+    dbgs() << "replaced by: " << *(--dMI);
+  });
+  MI->eraseFromParent();
+  return true;
+}
+
 /// runOnMachineFunction - Reduce subregister inserts and extracts to register
 /// copies.
 ///
@@ -346,6 +393,8 @@
         MadeChange |= LowerInsert(MI);
       } else if (MI->isSubregToReg()) {
         MadeChange |= LowerSubregToReg(MI);
+      } else if (MI->isCopy()) {
+        MadeChange |= LowerCopy(MI);
       }
       mi = nmi;
     }

Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=107529&r1=107528&r2=107529&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Fri Jul  2 17:29:50 2010
@@ -344,6 +344,7 @@
     "COPY_TO_REGCLASS",
     "DBG_VALUE",
     "REG_SEQUENCE",
+    "COPY",
     0
   };
   const DenseMap<const Record*, CodeGenInstruction*> &Insts = getInstructions();




From scanon at apple.com  Fri Jul  2 18:05:46 2010
From: scanon at apple.com (Stephen Canon)
Date: Fri, 02 Jul 2010 23:05:46 -0000
Subject: [llvm-commits] [compiler-rt] r107535 - in /compiler-rt/trunk/lib:
 floatsidf.c floatsisf.c floatunssidf.c floatunssisf.c
Message-ID: <20100702230546.3C13C2A6C12C@llvm.org>

Author: scanon
Date: Fri Jul  2 18:05:46 2010
New Revision: 107535

URL: http://llvm.org/viewvc/llvm-project?rev=107535&view=rev
Log:
[unsigned] int -> float soft-float conversions for single- and double-precision

Added:
    compiler-rt/trunk/lib/floatsidf.c
    compiler-rt/trunk/lib/floatsisf.c
    compiler-rt/trunk/lib/floatunssidf.c
    compiler-rt/trunk/lib/floatunssisf.c

Added: compiler-rt/trunk/lib/floatsidf.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/floatsidf.c?rev=107535&view=auto
==============================================================================
--- compiler-rt/trunk/lib/floatsidf.c (added)
+++ compiler-rt/trunk/lib/floatsidf.c Fri Jul  2 18:05:46 2010
@@ -0,0 +1,54 @@
+//===-- lib/floatsidf.c - integer -> double-precision conversion --*- C -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements integer to double-precision conversion for the
+// compiler-rt library in the IEEE-754 default round-to-nearest, ties-to-even
+// mode.
+//
+//===----------------------------------------------------------------------===//
+
+#define DOUBLE_PRECISION
+#include "fp_lib.h"
+
+fp_t __floatsidf(int a) {
+    
+    const int aWidth = sizeof a * CHAR_BIT;
+    
+    // Handle zero as a special case to protect clz
+    if (a == 0)
+        return fromRep(0);
+    
+    // All other cases begin by extracting the sign and absolute value of a
+    rep_t sign = 0;
+    if (a < 0) {
+        sign = signBit;
+        a = -a;
+    }
+    
+    // Exponent of (fp_t)a is the width of abs(a).
+    const int exponent = (aWidth - 1) - __builtin_clz(a);
+    rep_t result;
+    
+    // Shift a into the significand field, rounding if it is a right-shift
+    if (exponent <= significandBits) {
+        const int shift = significandBits - exponent;
+        result = (rep_t)a << shift ^ implicitBit;
+    } else {
+        const int shift = exponent - significandBits;
+        result = (rep_t)a >> shift ^ implicitBit;
+        rep_t round = (rep_t)a << (typeWidth - shift);
+        if (round > signBit) result++;
+        if (round == signBit) result += result & 1;
+    }
+    
+    // Insert the exponent
+    result += (rep_t)(exponent + exponentBias) << significandBits;
+    // Insert the sign bit and return
+    return fromRep(result | sign);
+}

Added: compiler-rt/trunk/lib/floatsisf.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/floatsisf.c?rev=107535&view=auto
==============================================================================
--- compiler-rt/trunk/lib/floatsisf.c (added)
+++ compiler-rt/trunk/lib/floatsisf.c Fri Jul  2 18:05:46 2010
@@ -0,0 +1,54 @@
+//===-- lib/floatsisf.c - integer -> single-precision conversion --*- C -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements integer to single-precision conversion for the
+// compiler-rt library in the IEEE-754 default round-to-nearest, ties-to-even
+// mode.
+//
+//===----------------------------------------------------------------------===//
+
+#define SINGLE_PRECISION
+#include "fp_lib.h"
+
+fp_t __floatsisf(int a) {
+    
+    const int aWidth = sizeof a * CHAR_BIT;
+    
+    // Handle zero as a special case to protect clz
+    if (a == 0)
+        return fromRep(0);
+    
+    // All other cases begin by extracting the sign and absolute value of a
+    rep_t sign = 0;
+    if (a < 0) {
+        sign = signBit;
+        a = -a;
+    }
+    
+    // Exponent of (fp_t)a is the width of abs(a).
+    const int exponent = (aWidth - 1) - __builtin_clz(a);
+    rep_t result;
+    
+    // Shift a into the significand field, rounding if it is a right-shift
+    if (exponent <= significandBits) {
+        const int shift = significandBits - exponent;
+        result = (rep_t)a << shift ^ implicitBit;
+    } else {
+        const int shift = exponent - significandBits;
+        result = (rep_t)a >> shift ^ implicitBit;
+        rep_t round = (rep_t)a << (typeWidth - shift);
+        if (round > signBit) result++;
+        if (round == signBit) result += result & 1;
+    }
+    
+    // Insert the exponent
+    result += (rep_t)(exponent + exponentBias) << significandBits;
+    // Insert the sign bit and return
+    return fromRep(result | sign);
+}

Added: compiler-rt/trunk/lib/floatunssidf.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/floatunssidf.c?rev=107535&view=auto
==============================================================================
--- compiler-rt/trunk/lib/floatunssidf.c (added)
+++ compiler-rt/trunk/lib/floatunssidf.c Fri Jul  2 18:05:46 2010
@@ -0,0 +1,45 @@
+//===-- lib/floatunssidf.c - uint -> double-precision conversion --*- C -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements unsigned integer to double-precision conversion for the
+// compiler-rt library in the IEEE-754 default round-to-nearest, ties-to-even
+// mode.
+//
+//===----------------------------------------------------------------------===//
+
+#define DOUBLE_PRECISION
+#include "fp_lib.h"
+
+fp_t __floatunssidf(unsigned int a) {
+    
+    const int aWidth = sizeof a * CHAR_BIT;
+    
+    // Handle zero as a special case to protect clz
+    if (a == 0) return fromRep(0);
+    
+    // Exponent of (fp_t)a is the width of abs(a).
+    const int exponent = (aWidth - 1) - __builtin_clz(a);
+    rep_t result;
+    
+    // Shift a into the significand field, rounding if it is a right-shift
+    if (exponent <= significandBits) {
+        const int shift = significandBits - exponent;
+        result = (rep_t)a << shift ^ implicitBit;
+    } else {
+        const int shift = exponent - significandBits;
+        result = (rep_t)a >> shift ^ implicitBit;
+        rep_t round = (rep_t)a << (typeWidth - shift);
+        if (round > signBit) result++;
+        if (round == signBit) result += result & 1;
+    }
+    
+    // Insert the exponent
+    result += (rep_t)(exponent + exponentBias) << significandBits;
+    return fromRep(result);
+}

Added: compiler-rt/trunk/lib/floatunssisf.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/floatunssisf.c?rev=107535&view=auto
==============================================================================
--- compiler-rt/trunk/lib/floatunssisf.c (added)
+++ compiler-rt/trunk/lib/floatunssisf.c Fri Jul  2 18:05:46 2010
@@ -0,0 +1,45 @@
+//===-- lib/floatunssisf.c - uint -> single-precision conversion --*- C -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements unsigned integer to single-precision conversion for the
+// compiler-rt library in the IEEE-754 default round-to-nearest, ties-to-even
+// mode.
+//
+//===----------------------------------------------------------------------===//
+
+#define SINGLE_PRECISION
+#include "fp_lib.h"
+
+fp_t __floatunssisf(unsigned int a) {
+    
+    const int aWidth = sizeof a * CHAR_BIT;
+    
+    // Handle zero as a special case to protect clz
+    if (a == 0) return fromRep(0);
+    
+    // Exponent of (fp_t)a is the width of abs(a).
+    const int exponent = (aWidth - 1) - __builtin_clz(a);
+    rep_t result;
+    
+    // Shift a into the significand field, rounding if it is a right-shift
+    if (exponent <= significandBits) {
+        const int shift = significandBits - exponent;
+        result = (rep_t)a << shift ^ implicitBit;
+    } else {
+        const int shift = exponent - significandBits;
+        result = (rep_t)a >> shift ^ implicitBit;
+        rep_t round = (rep_t)a << (typeWidth - shift);
+        if (round > signBit) result++;
+        if (round == signBit) result += result & 1;
+    }
+    
+    // Insert the exponent
+    result += (rep_t)(exponent + exponentBias) << significandBits;
+    return fromRep(result);
+}




From echristo at apple.com  Fri Jul  2 18:17:38 2010
From: echristo at apple.com (Eric Christopher)
Date: Fri, 02 Jul 2010 23:17:38 -0000
Subject: [llvm-commits] [llvm] r107537 -
	/llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp
Message-ID: <20100702231738.380832A6C12C@llvm.org>

Author: echristo
Date: Fri Jul  2 18:17:38 2010
New Revision: 107537

URL: http://llvm.org/viewvc/llvm-project?rev=107537&view=rev
Log:
80-col fixup.

Modified:
    llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp

Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp?rev=107537&r1=107536&r2=107537&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Fri Jul  2 18:17:38 2010
@@ -83,7 +83,8 @@
   // pressure, it can caused fewer GPRs to be held in the queue.
   static cl::opt<unsigned>
   NumRecentlyUsedRegs("linearscan-skip-count",
-                      cl::desc("Number of registers for linearscan to remember to skip."),
+                      cl::desc("Number of registers for linearscan to remember"
+                               "to skip."),
                       cl::init(0),
                       cl::Hidden);
  




From gohman at apple.com  Fri Jul  2 18:18:08 2010
From: gohman at apple.com (Dan Gohman)
Date: Fri, 02 Jul 2010 23:18:08 -0000
Subject: [llvm-commits] [llvm] r107538 - /llvm/trunk/docs/LangRef.html
Message-ID: <20100702231808.8E59E2A6C12C@llvm.org>

Author: djg
Date: Fri Jul  2 18:18:08 2010
New Revision: 107538

URL: http://llvm.org/viewvc/llvm-project?rev=107538&view=rev
Log:
Add some html anchors, to allow attributes to be linked to directly.

Modified:
    llvm/trunk/docs/LangRef.html

Modified: llvm/trunk/docs/LangRef.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=107538&r1=107537&r2=107538&view=diff
==============================================================================
--- llvm/trunk/docs/LangRef.html (original)
+++ llvm/trunk/docs/LangRef.html Fri Jul  2 18:18:08 2010
@@ -1042,7 +1042,7 @@
       generator that usually indicates a desired alignment for the synthesized
       stack slot.</dd>
 
-  <dt><tt><b>sret</b></tt></dt>
+  <dt><tt><b><a name="sret">sret</a></b></tt></dt>
   <dd>This indicates that the pointer parameter specifies the address of a
       structure that is the return value of the function in the source program.
       This pointer must be guaranteed by the caller to be valid: loads and
@@ -1050,7 +1050,7 @@
       may only be applied to the first parameter. This is not a valid attribute
       for return values. </dd>
 
-  <dt><tt><b>noalias</b></tt></dt>
+  <dt><tt><b><a name="noalias">noalias</a></b></tt></dt>
   <dd>This indicates that pointer values
       <a href="#pointeraliasing"><i>based</i></a> on the argument or return
       value do not alias pointer values which are not <i>based</i> on it.
@@ -1059,12 +1059,12 @@
       For further details, please see the discussion of the NoAlias response in
       <a href="AliasAnalysis.html#MustMayNo">alias analysis</a>.</dd>
 
-  <dt><tt><b>nocapture</b></tt></dt>
+  <dt><tt><b><a name="nocapture">nocapture</a></b></tt></dt>
   <dd>This indicates that the callee does not make any copies of the pointer
       that outlive the callee itself. This is not a valid attribute for return
       values.</dd>
 
-  <dt><tt><b>nest</b></tt></dt>
+  <dt><tt><b><a name="nest">nest</a></b></tt></dt>
   <dd>This indicates that the pointer parameter can be excised using the
       <a href="#int_trampoline">trampoline intrinsics</a>. This is not a valid
       attribute for return values.</dd>
@@ -6952,7 +6952,8 @@
 <div class="doc_text">
 
 <p>This intrinsic makes it possible to excise one parameter, marked with
-   the <tt>nest</tt> attribute, from a function.  The result is a callable
+   the <a href="#nest"><tt>nest</tt></a> attribute, from a function.
+   The result is a callable
    function pointer lacking the nest parameter - the caller does not need to
    provide a value for it.  Instead, the value to use is stored in advance in a
    "trampoline", a block of memory usually allocated on the stack, which also




From bruno.cardoso at gmail.com  Fri Jul  2 18:27:59 2010
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Fri, 02 Jul 2010 23:27:59 -0000
Subject: [llvm-commits] [llvm] r107540 -
	/llvm/trunk/lib/Target/X86/X86InstrSSE.td
Message-ID: <20100702232759.3B8322A6C12C@llvm.org>

Author: bruno
Date: Fri Jul  2 18:27:59 2010
New Revision: 107540

URL: http://llvm.org/viewvc/llvm-project?rev=107540&view=rev
Log:
Simple refactoring of SSE4.1 instructions, making room for the AVX forms

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=107540&r1=107539&r2=107540&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Fri Jul  2 18:27:59 2010
@@ -3904,7 +3904,7 @@
           (MOVUPSmr addr:$dst, VR128:$src)>;
 
 //===----------------------------------------------------------------------===//
-// SSE4.1 Instructions
+// SSE4.1 - Misc Instructions
 //===----------------------------------------------------------------------===//
 
 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd,
@@ -3948,56 +3948,61 @@
                     OpSize;
 }
 
-let Constraints = "$src1 = $dst" in {
 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
                             string OpcodeStr,
                             Intrinsic F32Int,
-                            Intrinsic F64Int> {
+                            Intrinsic F64Int, bit Is2Addr = 1> {
   // Intrinsic operation, reg.
   def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
-                    (outs VR128:$dst),
-                                 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
-                    !strconcat(OpcodeStr,
-                    "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
-                    [(set VR128:$dst,
-                            (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
-                    OpSize;
+        (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
+        !if(Is2Addr,
+            !strconcat(OpcodeStr,
+                "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
+            !strconcat(OpcodeStr,
+                "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
+        [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
+        OpSize;
 
   // Intrinsic operation, mem.
   def SSm_Int : SS4AIi8<opcss, MRMSrcMem,
-                    (outs VR128:$dst),
-                                (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
-                    !strconcat(OpcodeStr,
-                    "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
-                    [(set VR128:$dst,
-                         (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
-                    OpSize;
+        (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
+        !if(Is2Addr,
+            !strconcat(OpcodeStr,
+                "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
+            !strconcat(OpcodeStr,
+                "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
+        [(set VR128:$dst,
+             (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
+        OpSize;
 
   // Intrinsic operation, reg.
   def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
-                    (outs VR128:$dst),
-                            (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
-                    !strconcat(OpcodeStr,
-                    "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
-                    [(set VR128:$dst,
-                            (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
-                    OpSize;
+        (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
+        !if(Is2Addr,
+            !strconcat(OpcodeStr,
+                "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
+            !strconcat(OpcodeStr,
+                "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
+        [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
+        OpSize;
 
   // Intrinsic operation, mem.
   def SDm_Int : SS4AIi8<opcsd, MRMSrcMem,
-                    (outs VR128:$dst),
-                            (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
-                    !strconcat(OpcodeStr,
-                    "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
-                    [(set VR128:$dst,
-                        (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
-                    OpSize;
-}
+        (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
+        !if(Is2Addr,
+            !strconcat(OpcodeStr,
+                "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
+            !strconcat(OpcodeStr,
+                "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
+        [(set VR128:$dst,
+              (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
+        OpSize;
 }
 
 // FP round - roundss, roundps, roundsd, roundpd
 defm ROUND  : sse41_fp_unop_rm<0x08, 0x09, "round",
                                int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
+let Constraints = "$src1 = $dst" in
 defm ROUND  : sse41_fp_binop_rm<0x0A, 0x0B, "round",
                                int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
 
@@ -4020,146 +4025,107 @@
                                          int_x86_sse41_phminposuw>;
 
 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
-let Constraints = "$src1 = $dst" in {
-  multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
-                                Intrinsic IntId128, bit Commutable = 0> {
-    def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
-                   (ins VR128:$src1, VR128:$src2),
-                   !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
-                   [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
-                   OpSize {
-      let isCommutable = Commutable;
-    }
-    def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
-                   (ins VR128:$src1, i128mem:$src2),
-                   !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
-                   [(set VR128:$dst,
-                     (IntId128 VR128:$src1,
-                      (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
-  }
+multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
+                              Intrinsic IntId128, bit Is2Addr = 1> {
+  let isCommutable = 1 in
+  def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
+       (ins VR128:$src1, VR128:$src2),
+       !if(Is2Addr,
+           !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
+           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
+       [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
+  def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
+       (ins VR128:$src1, i128mem:$src2),
+       !if(Is2Addr,
+           !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
+           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
+       [(set VR128:$dst,
+         (IntId128 VR128:$src1,
+          (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
 }
 
-defm PCMPEQQ      : SS41I_binop_rm_int<0x29, "pcmpeqq",
-                                       int_x86_sse41_pcmpeqq, 1>;
-defm PACKUSDW     : SS41I_binop_rm_int<0x2B, "packusdw",
-                                       int_x86_sse41_packusdw, 0>;
-defm PMINSB       : SS41I_binop_rm_int<0x38, "pminsb",
-                                       int_x86_sse41_pminsb, 1>;
-defm PMINSD       : SS41I_binop_rm_int<0x39, "pminsd",
-                                       int_x86_sse41_pminsd, 1>;
-defm PMINUD       : SS41I_binop_rm_int<0x3B, "pminud",
-                                       int_x86_sse41_pminud, 1>;
-defm PMINUW       : SS41I_binop_rm_int<0x3A, "pminuw",
-                                       int_x86_sse41_pminuw, 1>;
-defm PMAXSB       : SS41I_binop_rm_int<0x3C, "pmaxsb",
-                                       int_x86_sse41_pmaxsb, 1>;
-defm PMAXSD       : SS41I_binop_rm_int<0x3D, "pmaxsd",
-                                       int_x86_sse41_pmaxsd, 1>;
-defm PMAXUD       : SS41I_binop_rm_int<0x3F, "pmaxud",
-                                       int_x86_sse41_pmaxud, 1>;
-defm PMAXUW       : SS41I_binop_rm_int<0x3E, "pmaxuw",
-                                       int_x86_sse41_pmaxuw, 1>;
-
-defm PMULDQ       : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq, 1>;
+let Constraints = "$src1 = $dst" in {
+  let isCommutable = 0 in
+  defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
+  defm PCMPEQQ  : SS41I_binop_rm_int<0x29, "pcmpeqq",  int_x86_sse41_pcmpeqq>;
+  defm PMINSB   : SS41I_binop_rm_int<0x38, "pminsb",   int_x86_sse41_pminsb>;
+  defm PMINSD   : SS41I_binop_rm_int<0x39, "pminsd",   int_x86_sse41_pminsd>;
+  defm PMINUD   : SS41I_binop_rm_int<0x3B, "pminud",   int_x86_sse41_pminud>;
+  defm PMINUW   : SS41I_binop_rm_int<0x3A, "pminuw",   int_x86_sse41_pminuw>;
+  defm PMAXSB   : SS41I_binop_rm_int<0x3C, "pmaxsb",   int_x86_sse41_pmaxsb>;
+  defm PMAXSD   : SS41I_binop_rm_int<0x3D, "pmaxsd",   int_x86_sse41_pmaxsd>;
+  defm PMAXUD   : SS41I_binop_rm_int<0x3F, "pmaxud",   int_x86_sse41_pmaxud>;
+  defm PMAXUW   : SS41I_binop_rm_int<0x3E, "pmaxuw",   int_x86_sse41_pmaxuw>;
+  defm PMULDQ   : SS41I_binop_rm_int<0x28, "pmuldq",   int_x86_sse41_pmuldq>;
+}
 
 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
           (PCMPEQQrr VR128:$src1, VR128:$src2)>;
 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
           (PCMPEQQrm VR128:$src1, addr:$src2)>;
 
-/// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
-let Constraints = "$src1 = $dst" in {
-  multiclass SS41I_binop_patint<bits<8> opc, string OpcodeStr, ValueType OpVT,
-                                SDNode OpNode, Intrinsic IntId128,
-                                bit Commutable = 0> {
-    def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
-                   (ins VR128:$src1, VR128:$src2),
-                   !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
-                   [(set VR128:$dst, (OpNode (OpVT VR128:$src1),
-                                                   VR128:$src2))]>, OpSize {
-      let isCommutable = Commutable;
-    }
-    def rr_int : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
-                      (ins VR128:$src1, VR128:$src2),
-                      !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
-                      [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
-                      OpSize {
-      let isCommutable = Commutable;
-    }
-    def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
-                   (ins VR128:$src1, i128mem:$src2),
-                   !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
-                   [(set VR128:$dst,
-                     (OpVT (OpNode VR128:$src1, (memop addr:$src2))))]>, OpSize;
-    def rm_int : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
-                       (ins VR128:$src1, i128mem:$src2),
-                       !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
-                       [(set VR128:$dst,
-                        (IntId128 VR128:$src1, (memop addr:$src2)))]>,
-                       OpSize;
-  }
-}
-
 /// SS48I_binop_rm - Simple SSE41 binary operator.
-let Constraints = "$src1 = $dst" in {
 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
-                        ValueType OpVT, bit Commutable = 0> {
+                        ValueType OpVT, bit Is2Addr = 1> {
+  let isCommutable = 1 in
   def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
-                                 (ins VR128:$src1, VR128:$src2),
-               !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
-               [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
-               OpSize {
-    let isCommutable = Commutable;
-  }
+       (ins VR128:$src1, VR128:$src2),
+       !if(Is2Addr,
+           !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
+           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
+       [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
+       OpSize;
   def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
-                                 (ins VR128:$src1, i128mem:$src2),
-               !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
-               [(set VR128:$dst, (OpNode VR128:$src1,
+       (ins VR128:$src1, i128mem:$src2),
+       !if(Is2Addr,
+           !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
+           !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
+       [(set VR128:$dst, (OpNode VR128:$src1,
                                   (bc_v4i32 (memopv2i64 addr:$src2))))]>,
-               OpSize;
-}
+       OpSize;
 }
 
-defm PMULLD         : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, 1>;
+let Constraints = "$src1 = $dst" in
+  defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32>;
 
 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
+multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
+                               Intrinsic IntId128, bit Is2Addr = 1> {
+  let isCommutable = 1 in
+  def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
+        (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
+        !if(Is2Addr,
+            !strconcat(OpcodeStr,
+                "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
+            !strconcat(OpcodeStr,
+                "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
+        [(set VR128:$dst,
+          (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
+        OpSize;
+  def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
+        (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
+        !if(Is2Addr,
+            !strconcat(OpcodeStr,
+                "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
+            !strconcat(OpcodeStr,
+                "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
+        [(set VR128:$dst,
+          (IntId128 VR128:$src1,
+           (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
+        OpSize;
+}
+
 let Constraints = "$src1 = $dst" in {
-  multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
-                                 Intrinsic IntId128, bit Commutable = 0> {
-    def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
-                    (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
-                    !strconcat(OpcodeStr,
-                     "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
-                    [(set VR128:$dst,
-                      (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
-                    OpSize {
-      let isCommutable = Commutable;
-    }
-    def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
-                    (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
-                    !strconcat(OpcodeStr,
-                     "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
-                    [(set VR128:$dst,
-                      (IntId128 VR128:$src1,
-                       (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
-                    OpSize;
+  let isCommutable = 0 in {
+  defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps>;
+  defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd>;
+  defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw>;
+  defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw>;
   }
+  defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps>;
+  defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd>;
 }
 
-defm BLENDPS      : SS41I_binop_rmi_int<0x0C, "blendps",
-                                        int_x86_sse41_blendps, 0>;
-defm BLENDPD      : SS41I_binop_rmi_int<0x0D, "blendpd",
-                                        int_x86_sse41_blendpd, 0>;
-defm PBLENDW      : SS41I_binop_rmi_int<0x0E, "pblendw",
-                                        int_x86_sse41_pblendw, 0>;
-defm DPPS         : SS41I_binop_rmi_int<0x40, "dpps",
-                                        int_x86_sse41_dpps, 1>;
-defm DPPD         : SS41I_binop_rmi_int<0x41, "dppd",
-                                        int_x86_sse41_dppd, 1>;
-defm MPSADBW      : SS41I_binop_rmi_int<0x42, "mpsadbw",
-                                        int_x86_sse41_mpsadbw, 0>;
-
-
 /// SS41I_ternary_int - SSE 4.1 ternary operator
 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
   multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {




From gohman at apple.com  Fri Jul  2 18:46:54 2010
From: gohman at apple.com (Dan Gohman)
Date: Fri, 02 Jul 2010 23:46:54 -0000
Subject: [llvm-commits] [llvm] r107544 - in /llvm/trunk/docs:
	AliasAnalysis.html LangRef.html
Message-ID: <20100702234654.9D7502A6C12C@llvm.org>

Author: djg
Date: Fri Jul  2 18:46:54 2010
New Revision: 107544

URL: http://llvm.org/viewvc/llvm-project?rev=107544&view=rev
Log:
Describe which dependencies are relevant to noalias, and document how
AliasAnalyses have the choice to respect noalias.

Modified:
    llvm/trunk/docs/AliasAnalysis.html
    llvm/trunk/docs/LangRef.html

Modified: llvm/trunk/docs/AliasAnalysis.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/AliasAnalysis.html?rev=107544&r1=107543&r2=107544&view=diff
==============================================================================
--- llvm/trunk/docs/AliasAnalysis.html (original)
+++ llvm/trunk/docs/AliasAnalysis.html Fri Jul  2 18:46:54 2010
@@ -201,6 +201,11 @@
 the other -- in this case, there is a dependence, but it's mediated by the free
 and reallocation.</p>
 
+<p>As an exception to this is with the
+<a href="LangRef.html#noalias"><tt>noalias</tt></a> keyword. AliasAnalysis
+implementations may choose to ignore the "irrelevant" dependencies, provided
+their clients do not need to be aware of these dependencies for correctness.</p>
+
 <p>The MayAlias response is used whenever the two pointers might refer to the
 same object.  If the two memory objects overlap, but do not start at the same
 location, return MayAlias.</p>

Modified: llvm/trunk/docs/LangRef.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=107544&r1=107543&r2=107544&view=diff
==============================================================================
--- llvm/trunk/docs/LangRef.html (original)
+++ llvm/trunk/docs/LangRef.html Fri Jul  2 18:46:54 2010
@@ -1053,7 +1053,12 @@
   <dt><tt><b><a name="noalias">noalias</a></b></tt></dt>
   <dd>This indicates that pointer values
       <a href="#pointeraliasing"><i>based</i></a> on the argument or return
-      value do not alias pointer values which are not <i>based</i> on it.
+      value do not alias pointer values which are not <i>based</i> on it,
+      ignoring certain "irrelevant" dependencies.
+      For a call to the parent function, dependencies between memory
+      references from before or after the call and from those during the call
+      are "irrelevant" to the <tt>noalias</tt> keyword for the arguments and
+      return value used in that call.
       The caller shares the responsibility with the callee for ensuring that
       these requirements are met.
       For further details, please see the discussion of the NoAlias response in




From gohman at apple.com  Fri Jul  2 18:52:36 2010
From: gohman at apple.com (Dan Gohman)
Date: Fri, 02 Jul 2010 23:52:36 -0000
Subject: [llvm-commits] [llvm] r107546 - in /llvm/trunk:
 docs/AliasAnalysis.html include/llvm/Analysis/Passes.h
Message-ID: <20100702235236.EA48F2A6C12C@llvm.org>

Author: djg
Date: Fri Jul  2 18:52:36 2010
New Revision: 107546

URL: http://llvm.org/viewvc/llvm-project?rev=107546&view=rev
Log:
Document that BasicAA respects noalias, while InterproceduralBasicAA
does not.

Modified:
    llvm/trunk/docs/AliasAnalysis.html
    llvm/trunk/include/llvm/Analysis/Passes.h

Modified: llvm/trunk/docs/AliasAnalysis.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/AliasAnalysis.html?rev=107546&r1=107545&r2=107546&view=diff
==============================================================================
--- llvm/trunk/docs/AliasAnalysis.html (original)
+++ llvm/trunk/docs/AliasAnalysis.html Fri Jul  2 18:52:36 2010
@@ -203,8 +203,9 @@
 
 <p>As an exception to this is with the
 <a href="LangRef.html#noalias"><tt>noalias</tt></a> keyword. AliasAnalysis
-implementations may choose to ignore the "irrelevant" dependencies, provided
-their clients do not need to be aware of these dependencies for correctness.</p>
+implementations may choose to respect the <tt>noalias</tt> keyword and ignore
+the "irrelevant" dependencies, provided their clients do not need to be aware
+of these dependencies for correctness.</p>
 
 <p>The MayAlias response is used whenever the two pointers might refer to the
 same object.  If the two memory objects overlap, but do not start at the same

Modified: llvm/trunk/include/llvm/Analysis/Passes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/Passes.h?rev=107546&r1=107545&r2=107546&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/Passes.h (original)
+++ llvm/trunk/include/llvm/Analysis/Passes.h Fri Jul  2 18:52:36 2010
@@ -67,7 +67,9 @@
   //===--------------------------------------------------------------------===//
   //
   // createBasicAliasAnalysisPass - This pass implements the default alias
-  // analysis.
+  // analysis.  This analysis respects the noalias attribute, so it is not
+  // suitable for some interprocedural uses (see the discussion of noalias
+  // in AliasAnalysis.html for details).
   //
   ImmutablePass *createBasicAliasAnalysisPass();
 
@@ -75,7 +77,8 @@
   //
   // createInterproceduralBasicAliasAnalysisPass - This pass is similar to
   // baiscaa, except that it properly supports queries to values which live
-  // in different functions.
+  // in different functions.  Unlike the regular BasicAliasAnalysis, this
+  // implementation does not respect the noalias attribute.
   //
   ImmutablePass *createInterproceduralBasicAliasAnalysisPass();
 




From gohman at apple.com  Fri Jul  2 19:04:50 2010
From: gohman at apple.com (Dan Gohman)
Date: Fri, 2 Jul 2010 17:04:50 -0700
Subject: [llvm-commits] [llvm] r107109 - in /llvm/trunk:
	include/llvm/Analysis/AliasAnalysis.h include/llvm/Analysis/Passes.h
	lib/Analysis/AliasAnalysis.cpp	lib/Analysis/BasicAliasAnalysis.cpp
	test/Analysis/BasicAA/interprocedural.ll
In-Reply-To: <4C2D8CBF.7070500@mxc.ca>
References: <20100629005039.39B192A6C12C@llvm.org> <4C298317.7050002@mxc.ca>
	<5E31E70D-BC94-4545-BE28-F8927D72097F@apple.com>
	<0EAA395C-1A7A-45D2-A6F9-F3B837A0F91C@apple.com>
	<92C98C7C-831E-4021-964E-B20289FB8BAB@apple.com>
	<4C2D8CBF.7070500@mxc.ca>
Message-ID: <D1588C63-6CC2-4A45-9EE7-2E98EEB4202F@apple.com>


On Jul 1, 2010, at 11:52 PM, Nick Lewycky wrote:

> Dan Gohman wrote:
>> 
>> However, beyond classic path and context scoping, there's another sense of
>> scope that an alias query can have, the scope of a noalias keyword. noalias
>> on an argument indicates that argument's relationship with other pointers
>> within that function, but it isn't meaningful when considering pointers
>> from an interprocedural perspective. An example of this is this is the first
>> example I gave above, with alias(@G, %p).
> 
> I don't believe you. From the LangRef.html#paramattrs
> 
> "*noalias:* This indicates that the pointer does not alias any global or any other parameter. The caller is responsible for ensuring that this is the case. ..."


But clearly it's valid to call memcpy on a global variable. This works
because noalias doesn't care about things within the call interfering
with things outside the call.

I've now updated the documentation to more closely reflect reality;
feedback on these changes is welcome.

Dan




From stoklund at 2pi.dk  Fri Jul  2 19:04:37 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Sat, 03 Jul 2010 00:04:37 -0000
Subject: [llvm-commits] [llvm] r107547 - in /llvm/trunk:
 include/llvm/CodeGen/MachineInstr.h lib/CodeGen/LiveIntervalAnalysis.cpp
 lib/CodeGen/MachineCSE.cpp lib/CodeGen/OptimizePHIs.cpp
 lib/CodeGen/PreAllocSplitting.cpp lib/CodeGen/ProcessImplicitDefs.cpp
 lib/CodeGen/RegAllocFast.cpp lib/CodeGen/RegisterCoalescer.cpp
 lib/CodeGen/SimpleRegisterCoalescing.cpp
 lib/CodeGen/TwoAddressInstructionPass.cpp
Message-ID: <20100703000437.CB5F12A6C12C@llvm.org>

Author: stoklund
Date: Fri Jul  2 19:04:37 2010
New Revision: 107547

URL: http://llvm.org/viewvc/llvm-project?rev=107547&view=rev
Log:
Detect and handle COPY in many places.

This code is transitional, it will soon be possible to eliminate
isExtractSubreg, isInsertSubreg, and isMoveInstr in most places.

Modified:
    llvm/trunk/include/llvm/CodeGen/MachineInstr.h
    llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
    llvm/trunk/lib/CodeGen/MachineCSE.cpp
    llvm/trunk/lib/CodeGen/OptimizePHIs.cpp
    llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp
    llvm/trunk/lib/CodeGen/ProcessImplicitDefs.cpp
    llvm/trunk/lib/CodeGen/RegAllocFast.cpp
    llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
    llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
    llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp

Modified: llvm/trunk/include/llvm/CodeGen/MachineInstr.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstr.h?rev=107547&r1=107546&r2=107547&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineInstr.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineInstr.h Fri Jul  2 19:04:37 2010
@@ -231,6 +231,12 @@
     return getOpcode() == TargetOpcode::COPY;
   }
 
+  /// isCopyLike - Return true if the instruction behaves like a copy.
+  /// This does not include native copy instructions.
+  bool isCopyLike() const {
+    return isCopy() || isSubregToReg() || isExtractSubreg() || isInsertSubreg();
+  }
+
   /// readsRegister - Return true if the MachineInstr reads the specified
   /// register. If TargetRegisterInfo is passed, then it also checks if there
   /// is a read of a super-register.

Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=107547&r1=107546&r2=107547&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Fri Jul  2 19:04:37 2010
@@ -321,7 +321,7 @@
 
     MachineInstr *CopyMI = NULL;
     unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
-    if (mi->isExtractSubreg() || mi->isInsertSubreg() || mi->isSubregToReg() ||
+    if (mi->isCopyLike() ||
         tii_->isMoveInstr(*mi, SrcReg, DstReg, SrcSubReg, DstSubReg)) {
       CopyMI = mi;
 
@@ -457,8 +457,8 @@
 
       // A re-def may be a copy. e.g. %reg1030:6<def> = VMOVD %reg1026, ...
       unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
-      if (PartReDef &&
-          tii_->isMoveInstr(*mi, SrcReg, DstReg, SrcSubReg, DstSubReg))
+      if (PartReDef && (mi->isCopyLike() ||
+          tii_->isMoveInstr(*mi, SrcReg, DstReg, SrcSubReg, DstSubReg)))
         OldValNo->setCopy(&*mi);
       
       // Add the new live interval which replaces the range for the input copy.
@@ -488,7 +488,7 @@
       VNInfo *ValNo;
       MachineInstr *CopyMI = NULL;
       unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
-      if (mi->isExtractSubreg() || mi->isInsertSubreg() || mi->isSubregToReg()||
+      if (mi->isCopyLike() ||
           tii_->isMoveInstr(*mi, SrcReg, DstReg, SrcSubReg, DstSubReg))
         CopyMI = mi;
       ValNo = interval.getNextValue(defIndex, CopyMI, true, VNInfoAllocator);
@@ -605,7 +605,7 @@
   else if (allocatableRegs_[MO.getReg()]) {
     MachineInstr *CopyMI = NULL;
     unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
-    if (MI->isExtractSubreg() || MI->isInsertSubreg() || MI->isSubregToReg() ||
+    if (MI->isCopyLike() ||
         tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg))
       CopyMI = MI;
     handlePhysicalRegisterDef(MBB, MI, MIIdx, MO,

Modified: llvm/trunk/lib/CodeGen/MachineCSE.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineCSE.cpp?rev=107547&r1=107546&r2=107547&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineCSE.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineCSE.cpp Fri Jul  2 19:04:37 2010
@@ -241,8 +241,8 @@
 
 static bool isCopy(const MachineInstr *MI, const TargetInstrInfo *TII) {
   unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
-  return TII->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) ||
-    MI->isExtractSubreg() || MI->isInsertSubreg() || MI->isSubregToReg();
+  return MI->isCopyLike() ||
+    TII->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx);
 }
 
 bool MachineCSE::isCSECandidate(MachineInstr *MI) {

Modified: llvm/trunk/lib/CodeGen/OptimizePHIs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/OptimizePHIs.cpp?rev=107547&r1=107546&r2=107547&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/OptimizePHIs.cpp (original)
+++ llvm/trunk/lib/CodeGen/OptimizePHIs.cpp Fri Jul  2 19:04:37 2010
@@ -107,6 +107,11 @@
         SrcSubIdx == 0 && DstSubIdx == 0 &&
         TargetRegisterInfo::isVirtualRegister(MvSrcReg))
       SrcMI = MRI->getVRegDef(MvSrcReg);
+    else if (SrcMI && SrcMI->isCopy() &&
+             !SrcMI->getOperand(0).getSubReg() &&
+             !SrcMI->getOperand(1).getSubReg() &&
+           TargetRegisterInfo::isVirtualRegister(SrcMI->getOperand(1).getReg()))
+      SrcMI = MRI->getVRegDef(SrcMI->getOperand(1).getReg());
     if (!SrcMI)
       return false;
 

Modified: llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp?rev=107547&r1=107546&r2=107547&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp (original)
+++ llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp Fri Jul  2 19:04:37 2010
@@ -677,10 +677,12 @@
     
     // If the def is a move, set the copy field.
     unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
-    if (TII->isMoveInstr(*DI, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
+    if (TII->isMoveInstr(*DI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
       if (DstReg == LI->reg)
         NewVN->setCopy(&*DI);
-    
+    } else if (DI->isCopyLike() && DI->getOperand(0).getReg() == LI->reg)
+      NewVN->setCopy(&*DI);
+
     NewVNs[&*DI] = NewVN;
   }
   

Modified: llvm/trunk/lib/CodeGen/ProcessImplicitDefs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ProcessImplicitDefs.cpp?rev=107547&r1=107546&r2=107547&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ProcessImplicitDefs.cpp (original)
+++ llvm/trunk/lib/CodeGen/ProcessImplicitDefs.cpp Fri Jul  2 19:04:37 2010
@@ -46,14 +46,15 @@
                                                  const TargetInstrInfo *tii_) {
   unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
   if (tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
-      Reg == SrcReg && SrcSubReg == 0 && DstSubReg == 0)
+      Reg == SrcReg && DstSubReg == 0)
     return true;
 
-  if (OpIdx == 2 && MI->isSubregToReg())
-    return true;
-  if (OpIdx == 1 && MI->isExtractSubreg())
-    return true;
-  return false;
+  switch(OpIdx) {
+    case 1: return (MI->isExtractSubreg() || MI->isCopy()) &&
+                   MI->getOperand(0).getSubReg() == 0;
+    case 2: return MI->isSubregToReg() && MI->getOperand(0).getSubReg() == 0;
+    default: return false;
+  }
 }
 
 /// processImplicitDefs - Process IMPLICIT_DEF instructions and make sure
@@ -219,8 +220,10 @@
 
         // Turn a copy use into an implicit_def.
         unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
-        if (tii_->isMoveInstr(*RMI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
-            Reg == SrcReg && SrcSubReg == 0 && DstSubReg == 0) {
+        if ((RMI->isCopy() && RMI->getOperand(1).getReg() == Reg &&
+             RMI->getOperand(0).getSubReg() == 0) ||
+            (tii_->isMoveInstr(*RMI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
+             Reg == SrcReg && DstSubReg == 0)) {
           RMI->setDesc(tii_->get(TargetOpcode::IMPLICIT_DEF));
 
           bool isKill = false;

Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=107547&r1=107546&r2=107547&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocFast.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp Fri Jul  2 19:04:37 2010
@@ -519,10 +519,12 @@
     // If there is no hint, peek at the only use of this register.
     if ((!Hint || !TargetRegisterInfo::isPhysicalRegister(Hint)) &&
         MRI->hasOneNonDBGUse(VirtReg)) {
+      const MachineInstr &UseMI = *MRI->use_nodbg_begin(VirtReg);
       unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
       // It's a copy, use the destination register as a hint.
-      if (TII->isMoveInstr(*MRI->use_nodbg_begin(VirtReg),
-                           SrcReg, DstReg, SrcSubReg, DstSubReg))
+      if (UseMI.isCopyLike())
+        Hint = UseMI.getOperand(0).getReg();
+      else if (TII->isMoveInstr(UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg))
         Hint = DstReg;
     }
     allocVirtReg(MI, *LRI, Hint);
@@ -771,7 +773,12 @@
 
     // If this is a copy, we may be able to coalesce.
     unsigned CopySrc, CopyDst, CopySrcSub, CopyDstSub;
-    if (!TII->isMoveInstr(*MI, CopySrc, CopyDst, CopySrcSub, CopyDstSub))
+    if (MI->isCopy()) {
+      CopyDst = MI->getOperand(0).getReg();
+      CopySrc = MI->getOperand(1).getReg();
+      CopyDstSub = MI->getOperand(0).getSubReg();
+      CopySrcSub = MI->getOperand(1).getSubReg();
+    } else if (!TII->isMoveInstr(*MI, CopySrc, CopyDst, CopySrcSub, CopyDstSub))
       CopySrc = CopyDst = 0;
 
     // Track registers used by instruction.

Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp?rev=107547&r1=107546&r2=107547&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp Fri Jul  2 19:04:37 2010
@@ -44,7 +44,12 @@
 bool CoalescerPair::isMoveInstr(const MachineInstr *MI,
                                 unsigned &Src, unsigned &Dst,
                                 unsigned &SrcSub, unsigned &DstSub) const {
-  if (MI->isExtractSubreg()) {
+  if (MI->isCopy()) {
+    Dst = MI->getOperand(0).getReg();
+    DstSub = MI->getOperand(0).getSubReg();
+    Src = MI->getOperand(1).getReg();
+    SrcSub = MI->getOperand(1).getSubReg();
+  } else if (MI->isExtractSubreg()) {
     Dst = MI->getOperand(0).getReg();
     DstSub = MI->getOperand(0).getSubReg();
     Src = MI->getOperand(1).getReg();

Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=107547&r1=107546&r2=107547&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
+++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Fri Jul  2 19:04:37 2010
@@ -450,20 +450,25 @@
         UseMO.setIsKill(false);
     }
     unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
-    if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
+    if (UseMI->isCopy()) {
+      if (UseMI->getOperand(0).getReg() != IntB.reg ||
+          UseMI->getOperand(0).getSubReg())
+        continue;
+    } else if (tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)){
+      if (DstReg != IntB.reg || DstSubIdx)
+        continue;
+    } else
       continue;
-    if (DstReg == IntB.reg && DstSubIdx == 0) {
-      // This copy will become a noop. If it's defining a new val#,
-      // remove that val# as well. However this live range is being
-      // extended to the end of the existing live range defined by the copy.
-      SlotIndex DefIdx = UseIdx.getDefIndex();
-      const LiveRange *DLR = IntB.getLiveRangeContaining(DefIdx);
-      BHasPHIKill |= DLR->valno->hasPHIKill();
-      assert(DLR->valno->def == DefIdx);
-      BDeadValNos.push_back(DLR->valno);
-      BExtend[DLR->start] = DLR->end;
-      JoinedCopies.insert(UseMI);
-    }
+    // This copy will become a noop. If it's defining a new val#,
+    // remove that val# as well. However this live range is being
+    // extended to the end of the existing live range defined by the copy.
+    SlotIndex DefIdx = UseIdx.getDefIndex();
+    const LiveRange *DLR = IntB.getLiveRangeContaining(DefIdx);
+    BHasPHIKill |= DLR->valno->hasPHIKill();
+    assert(DLR->valno->def == DefIdx);
+    BDeadValNos.push_back(DLR->valno);
+    BExtend[DLR->start] = DLR->end;
+    JoinedCopies.insert(UseMI);
   }
 
   // We need to insert a new liverange: [ALR.start, LastUse). It may be we can
@@ -604,8 +609,9 @@
     LastUse->setIsKill();
     removeRange(li, LastUseIdx.getDefIndex(), LR->end, li_, tri_);
     unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
-    if (tii_->isMoveInstr(*LastUseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
-        DstReg == li.reg && DstSubIdx == 0) {
+    if ((LastUseMI->isCopy() && !LastUseMI->getOperand(0).getSubReg()) ||
+        (tii_->isMoveInstr(*LastUseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
+         DstReg == li.reg && DstSubIdx == 0)) {
       // Last use is itself an identity code.
       int DeadIdx = LastUseMI->findRegisterDefOperandIdx(li.reg,
                                                          false, false, tri_);
@@ -1556,7 +1562,7 @@
     // If this isn't a copy nor a extract_subreg, we can't join intervals.
     unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
     bool isInsUndef = false;
-    if (Inst->isExtractSubreg()) {
+    if (Inst->isCopy() || Inst->isExtractSubreg()) {
       DstReg = Inst->getOperand(0).getReg();
       SrcReg = Inst->getOperand(1).getReg();
     } else if (Inst->isInsertSubreg()) {
@@ -1793,8 +1799,7 @@
         // Delete all coalesced copies.
         bool DoDelete = true;
         if (!tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
-          assert((MI->isExtractSubreg() || MI->isInsertSubreg() ||
-                  MI->isSubregToReg()) && "Unrecognized copy instruction");
+          assert(MI->isCopyLike() && "Unrecognized copy instruction");
           SrcReg = MI->getOperand(MI->isSubregToReg() ? 2 : 1).getReg();
           if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
             // Do not delete extract_subreg, insert_subreg of physical

Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=107547&r1=107546&r2=107547&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original)
+++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Fri Jul  2 19:04:37 2010
@@ -382,7 +382,7 @@
   DstReg = 0;
   unsigned SrcSubIdx, DstSubIdx;
   if (!TII->isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
-    if (MI.isExtractSubreg()) {
+    if (MI.isCopy() || MI.isExtractSubreg()) {
       DstReg = MI.getOperand(0).getReg();
       SrcReg = MI.getOperand(1).getReg();
     } else if (MI.isInsertSubreg()) {




From kledzik at apple.com  Fri Jul  2 19:12:48 2010
From: kledzik at apple.com (Nick Kledzik)
Date: Sat, 03 Jul 2010 00:12:48 -0000
Subject: [llvm-commits] [compiler-rt] r107548 - in
	/compiler-rt/trunk/lib/arm: bswapdi2.S bswapsi2.S
Message-ID: <20100703001248.1B8D52A6C12C@llvm.org>

Author: kledzik
Date: Fri Jul  2 19:12:47 2010
New Revision: 107548

URL: http://llvm.org/viewvc/llvm-project?rev=107548&view=rev
Log:
ARM before armv6 did not supprt 'rev' instruction

Modified:
    compiler-rt/trunk/lib/arm/bswapdi2.S
    compiler-rt/trunk/lib/arm/bswapsi2.S

Modified: compiler-rt/trunk/lib/arm/bswapdi2.S
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/bswapdi2.S?rev=107548&r1=107547&r2=107548&view=diff
==============================================================================
--- compiler-rt/trunk/lib/arm/bswapdi2.S (original)
+++ compiler-rt/trunk/lib/arm/bswapdi2.S Fri Jul  2 19:12:47 2010
@@ -16,8 +16,28 @@
 //
 	.align 2
 DEFINE_COMPILERRT_FUNCTION(__bswapdi2)
+#if __ARM_ARCH_5TEJ__ || __ARM_ARCH_4T__
+	// before armv6 does not have "rev" instruction
+	stmfd	sp!, {r7, lr}
+	mov	r7, sp
+	mov	r2, #255, 24
+	and	r3, r2, r1, lsr #8
+	mov	r12, #255, 16
+	and	lr, r12, r1, lsl #8
+	orr	r3, r3, r1, lsr #24
+	orr	r1, lr, r1, lsl #24
+	and	r2, r2, r0, lsr #8
+	orr	r3, r1, r3
+	orr	r1, r2, r0, lsr #24
+	and	r2, r12, r0, lsl #8
+	orr	r0, r2, r0, lsl #24
+	orr	r1, r0, r1
+	mov	r0, r3
+	ldmfd	sp!, {r7, pc}
+#else
 	rev	r2, r1		// reverse bytes in high 32-bits into temp2
 	rev	r3, r0		// reverse bytes in low 32-bit into temp3
 	mov	r0, r2		// set low 32-bits of result to temp2
 	mov	r1, r3		// set high 32-bits of result to temp3
 	bx	lr
+#endif

Modified: compiler-rt/trunk/lib/arm/bswapsi2.S
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/bswapsi2.S?rev=107548&r1=107547&r2=107548&view=diff
==============================================================================
--- compiler-rt/trunk/lib/arm/bswapsi2.S (original)
+++ compiler-rt/trunk/lib/arm/bswapsi2.S Fri Jul  2 19:12:47 2010
@@ -16,5 +16,16 @@
 //
 	.align 2
 DEFINE_COMPILERRT_FUNCTION(__bswapsi2)
+#if __ARM_ARCH_5TEJ__ || __ARM_ARCH_4T__
+	// before armv6 does not have "rev" instruction
+	mov	r1, #255, 24
+	mov	r2, #255, 16
+	and	r1, r1, r0, lsr #8
+	and	r2, r2, r0, lsl #8
+	orr	r1, r1, r0, lsr #24
+	orr	r0, r2, r0, lsl #24
+	orr	r0, r0, r1
+#else
 	rev	r0, r0		// reverse bytes in parameter and put into result register
+#endif
 	bx	lr




From bruno.cardoso at gmail.com  Fri Jul  2 19:37:44 2010
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Sat, 03 Jul 2010 00:37:44 -0000
Subject: [llvm-commits] [llvm] r107549 - in /llvm/trunk:
 lib/Target/X86/X86InstrSSE.td test/MC/AsmParser/X86/x86_32-encoding.s
 test/MC/AsmParser/X86/x86_64-encoding.s
Message-ID: <20100703003744.C3DED2A6C12C@llvm.org>

Author: bruno
Date: Fri Jul  2 19:37:44 2010
New Revision: 107549

URL: http://llvm.org/viewvc/llvm-project?rev=107549&view=rev
Log:
Add AVX SSE4.1 round instructions

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
    llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=107549&r1=107548&r2=107549&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Fri Jul  2 19:37:44 2010
@@ -3948,6 +3948,38 @@
                     OpSize;
 }
 
+multiclass sse41_fp_unop_rm_avx<bits<8> opcps, bits<8> opcpd,
+                                string OpcodeStr> {
+  // Intrinsic operation, reg.
+  // Vector intrinsic operation, reg
+  def PSr : SS4AIi8<opcps, MRMSrcReg,
+                    (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
+                    !strconcat(OpcodeStr,
+                    "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+                    []>, OpSize;
+
+  // Vector intrinsic operation, mem
+  def PSm : Ii8<opcps, MRMSrcMem,
+                    (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
+                    !strconcat(OpcodeStr,
+                    "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+                    []>, TA, OpSize, Requires<[HasSSE41]>;
+
+  // Vector intrinsic operation, reg
+  def PDr : SS4AIi8<opcpd, MRMSrcReg,
+                    (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
+                    !strconcat(OpcodeStr,
+                    "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+                    []>, OpSize;
+
+  // Vector intrinsic operation, mem
+  def PDm : SS4AIi8<opcpd, MRMSrcMem,
+                    (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
+                    !strconcat(OpcodeStr,
+                    "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+                    []>, OpSize;
+}
+
 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
                             string OpcodeStr,
                             Intrinsic F32Int,
@@ -3999,7 +4031,51 @@
         OpSize;
 }
 
+multiclass sse41_fp_binop_rm_avx<bits<8> opcss, bits<8> opcsd,
+                                 string OpcodeStr> {
+  // Intrinsic operation, reg.
+  def SSr : SS4AIi8<opcss, MRMSrcReg,
+        (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
+        !strconcat(OpcodeStr,
+                "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
+        []>, OpSize;
+
+  // Intrinsic operation, mem.
+  def SSm : SS4AIi8<opcss, MRMSrcMem,
+        (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
+        !strconcat(OpcodeStr,
+                "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
+        []>, OpSize;
+
+  // Intrinsic operation, reg.
+  def SDr : SS4AIi8<opcsd, MRMSrcReg,
+        (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
+            !strconcat(OpcodeStr,
+                "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
+        []>, OpSize;
+
+  // Intrinsic operation, mem.
+  def SDm : SS4AIi8<opcsd, MRMSrcMem,
+        (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
+            !strconcat(OpcodeStr,
+                "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
+        []>, OpSize;
+}
+
 // FP round - roundss, roundps, roundsd, roundpd
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in {
+  // Intrinsic form
+  defm VROUND  : sse41_fp_unop_rm<0x08, 0x09, "vround",
+                                int_x86_sse41_round_ps, int_x86_sse41_round_pd>,
+                                VEX;
+  defm VROUND  : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
+                                int_x86_sse41_round_ss, int_x86_sse41_round_sd,
+                                0>, VEX_4V;
+  // Instructions for the assembler
+  defm VROUND  : sse41_fp_unop_rm_avx<0x08, 0x09, "vround">, VEX;
+  defm VROUND  : sse41_fp_binop_rm_avx<0x0A, 0x0B, "vround">, VEX_4V;
+}
+
 defm ROUND  : sse41_fp_unop_rm<0x08, 0x09, "round",
                                int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
 let Constraints = "$src1 = $dst" in

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s?rev=107549&r1=107548&r2=107549&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s Fri Jul  2 19:37:44 2010
@@ -11742,3 +11742,35 @@
 // CHECK: encoding: [0xc4,0xe3,0x69,0x0f,0x18,0x07]
           vpalignr  $7, (%eax), %xmm2, %xmm3
 
+// CHECK: vroundsd  $7, %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe3,0x69,0x0b,0xd9,0x07]
+          vroundsd  $7, %xmm1, %xmm2, %xmm3
+
+// CHECK: vroundsd  $7, (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe3,0x69,0x0b,0x18,0x07]
+          vroundsd  $7, (%eax), %xmm2, %xmm3
+
+// CHECK: vroundss  $7, %xmm1, %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe3,0x69,0x0a,0xd9,0x07]
+          vroundss  $7, %xmm1, %xmm2, %xmm3
+
+// CHECK: vroundss  $7, (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe3,0x69,0x0a,0x18,0x07]
+          vroundss  $7, (%eax), %xmm2, %xmm3
+
+// CHECK: vroundpd  $7, %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe3,0x79,0x09,0xda,0x07]
+          vroundpd  $7, %xmm2, %xmm3
+
+// CHECK: vroundpd  $7, (%eax), %xmm3
+// CHECK: encoding: [0xc4,0xe3,0x79,0x09,0x18,0x07]
+          vroundpd  $7, (%eax), %xmm3
+
+// CHECK: vroundps  $7, %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe3,0x79,0x08,0xda,0x07]
+          vroundps  $7, %xmm2, %xmm3
+
+// CHECK: vroundps  $7, (%eax), %xmm3
+// CHECK: encoding: [0xc4,0xe3,0x79,0x08,0x18,0x07]
+          vroundps  $7, (%eax), %xmm3
+

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s?rev=107549&r1=107548&r2=107549&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s Fri Jul  2 19:37:44 2010
@@ -1790,3 +1790,35 @@
 // CHECK: encoding: [0xc4,0x63,0x19,0x0f,0x28,0x07]
           vpalignr  $7, (%rax), %xmm12, %xmm13
 
+// CHECK: vroundsd  $7, %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x43,0x19,0x0b,0xeb,0x07]
+          vroundsd  $7, %xmm11, %xmm12, %xmm13
+
+// CHECK: vroundsd  $7, (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x63,0x19,0x0b,0x28,0x07]
+          vroundsd  $7, (%rax), %xmm12, %xmm13
+
+// CHECK: vroundss  $7, %xmm11, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x43,0x19,0x0a,0xeb,0x07]
+          vroundss  $7, %xmm11, %xmm12, %xmm13
+
+// CHECK: vroundss  $7, (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x63,0x19,0x0a,0x28,0x07]
+          vroundss  $7, (%rax), %xmm12, %xmm13
+
+// CHECK: vroundpd  $7, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x43,0x79,0x09,0xec,0x07]
+          vroundpd  $7, %xmm12, %xmm13
+
+// CHECK: vroundpd  $7, (%rax), %xmm13
+// CHECK: encoding: [0xc4,0x63,0x79,0x09,0x28,0x07]
+          vroundpd  $7, (%rax), %xmm13
+
+// CHECK: vroundps  $7, %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x43,0x79,0x08,0xec,0x07]
+          vroundps  $7, %xmm12, %xmm13
+
+// CHECK: vroundps  $7, (%rax), %xmm13
+// CHECK: encoding: [0xc4,0x63,0x79,0x08,0x28,0x07]
+          vroundps  $7, (%rax), %xmm13
+




From evan.cheng at apple.com  Fri Jul  2 19:40:23 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Sat, 03 Jul 2010 00:40:23 -0000
Subject: [llvm-commits] [llvm] r107550 - in /llvm/trunk:
 include/llvm/CodeGen/ lib/CodeGen/ lib/Target/ARM/ lib/Target/Alpha/
 lib/Target/Blackfin/ lib/Target/CellSPU/ lib/Target/MBlaze/
 lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PowerPC/ lib/Target/Sparc/
 lib/Target/SystemZ/ lib/Target/X86/ lib/Target/XCore/
Message-ID: <20100703004024.58E942A6C12C@llvm.org>

Author: evancheng
Date: Fri Jul  2 19:40:23 2010
New Revision: 107550

URL: http://llvm.org/viewvc/llvm-project?rev=107550&view=rev
Log:
Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill slots so it's always false.

Modified:
    llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h
    llvm/trunk/lib/CodeGen/MachineFunction.cpp
    llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp
    llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp
    llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
    llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp
    llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp
    llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
    llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
    llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
    llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
    llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp
    llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp

Modified: llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h?rev=107550&r1=107549&r2=107550&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h Fri Jul  2 19:40:23 2010
@@ -98,8 +98,7 @@
     // cannot alias any other memory objects.
     bool isSpillSlot;
 
-    StackObject(uint64_t Sz, unsigned Al, int64_t SP, bool IM,
-                bool isSS)
+    StackObject(uint64_t Sz, unsigned Al, int64_t SP, bool IM, bool isSS)
       : SPOffset(SP), Size(Sz), Alignment(Al), isImmutable(IM),
         isSpillSlot(isSS) {}
   };
@@ -350,8 +349,7 @@
   /// efficiency. By default, fixed objects are immutable. This returns an
   /// index with a negative value.
   ///
-  int CreateFixedObject(uint64_t Size, int64_t SPOffset,
-                        bool Immutable, bool isSS);
+  int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool Immutable);
   
   
   /// isFixedObjectIndex - Returns true if the specified index corresponds to a

Modified: llvm/trunk/lib/CodeGen/MachineFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFunction.cpp?rev=107550&r1=107549&r2=107550&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineFunction.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineFunction.cpp Fri Jul  2 19:40:23 2010
@@ -438,10 +438,10 @@
 /// index with a negative value.
 ///
 int MachineFrameInfo::CreateFixedObject(uint64_t Size, int64_t SPOffset,
-                                        bool Immutable, bool isSS) {
+                                        bool Immutable) {
   assert(Size != 0 && "Cannot allocate zero size fixed stack objects!");
   Objects.insert(Objects.begin(), StackObject(Size, 1, SPOffset, Immutable,
-                                              isSS));
+                                              /*isSS*/false));
   return -++NumFixedObjects;
 }
 

Modified: llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp?rev=107550&r1=107549&r2=107550&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp (original)
+++ llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp Fri Jul  2 19:40:23 2010
@@ -260,8 +260,7 @@
       if ((unsigned)FrameIdx > MaxCSFrameIndex) MaxCSFrameIndex = FrameIdx;
     } else {
       // Spill it to the stack where we must.
-      FrameIdx = MFI->CreateFixedObject(RC->getSize(), FixedSlot->Offset,
-                                        true, false);
+      FrameIdx = MFI->CreateFixedObject(RC->getSize(), FixedSlot->Offset, true);
     }
 
     I->setFrameIdx(FrameIdx);

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=107550&r1=107549&r2=107550&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri Jul  2 19:40:23 2010
@@ -1996,7 +1996,7 @@
   SDValue ArgValue2;
   if (NextVA.isMemLoc()) {
     MachineFrameInfo *MFI = MF.getFrameInfo();
-    int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true, false);
+    int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
 
     // Create load node to retrieve arguments from the stack.
     SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
@@ -2052,8 +2052,7 @@
           VA = ArgLocs[++i]; // skip ahead to next loc
           SDValue ArgValue2;
           if (VA.isMemLoc()) {
-            int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(),
-                                            true, false);
+            int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
             SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
             ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
                                     PseudoSourceValue::getFixedStack(FI), 0,
@@ -2120,8 +2119,7 @@
       assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
 
       unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
-      int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
-                                      true, false);
+      int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(), true);
 
       // Create load nodes to retrieve arguments from the stack.
       SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
@@ -2152,7 +2150,7 @@
       AFI->setVarArgsFrameIndex(
         MFI->CreateFixedObject(VARegSaveSize,
                                ArgOffset + VARegSaveSize - VARegSize,
-                               true, false));
+                               true));
       SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(),
                                       getPointerTy());
 
@@ -2179,8 +2177,7 @@
                             &MemOps[0], MemOps.size());
     } else
       // This will point to the next argument passed via stack.
-      AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset,
-                                                       true, false));
+      AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true));
   }
 
   return Chain;

Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp?rev=107550&r1=107549&r2=107550&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Fri Jul  2 19:40:23 2010
@@ -425,7 +425,7 @@
       }
     } else { //more args
       // Create the frame index object for this incoming parameter...
-      int FI = MFI->CreateFixedObject(8, 8 * (ArgNo - 6), true, false);
+      int FI = MFI->CreateFixedObject(8, 8 * (ArgNo - 6), true);
 
       // Create the SelectionDAG nodes corresponding to a load
       //from this parameter
@@ -444,7 +444,7 @@
       if (TargetRegisterInfo::isPhysicalRegister(args_int[i]))
         args_int[i] = AddLiveIn(MF, args_int[i], &Alpha::GPRCRegClass);
       SDValue argt = DAG.getCopyFromReg(Chain, dl, args_int[i], MVT::i64);
-      int FI = MFI->CreateFixedObject(8, -8 * (6 - i), true, false);
+      int FI = MFI->CreateFixedObject(8, -8 * (6 - i), true);
       if (i == 0) FuncInfo->setVarArgsBase(FI);
       SDValue SDFI = DAG.getFrameIndex(FI, MVT::i64);
       LS.push_back(DAG.getStore(Chain, dl, argt, SDFI, NULL, 0,
@@ -453,7 +453,7 @@
       if (TargetRegisterInfo::isPhysicalRegister(args_float[i]))
         args_float[i] = AddLiveIn(MF, args_float[i], &Alpha::F8RCRegClass);
       argt = DAG.getCopyFromReg(Chain, dl, args_float[i], MVT::f64);
-      FI = MFI->CreateFixedObject(8, - 8 * (12 - i), true, false);
+      FI = MFI->CreateFixedObject(8, - 8 * (12 - i), true);
       SDFI = DAG.getFrameIndex(FI, MVT::i64);
       LS.push_back(DAG.getStore(Chain, dl, argt, SDFI, NULL, 0,
                                 false, false, 0));

Modified: llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp?rev=107550&r1=107549&r2=107550&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp Fri Jul  2 19:40:23 2010
@@ -205,8 +205,7 @@
     } else {
       assert(VA.isMemLoc() && "CCValAssign must be RegLoc or MemLoc");
       unsigned ObjSize = VA.getLocVT().getStoreSize();
-      int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(),
-                                      true, false);
+      int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
       SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
       InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0,
                                    false, false, 0));

Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=107550&r1=107549&r2=107550&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Fri Jul  2 19:40:23 2010
@@ -1074,7 +1074,7 @@
       // We need to load the argument to a virtual register if we determined
       // above that we ran out of physical registers of the appropriate type
       // or we're forced to do vararg
-      int FI = MFI->CreateFixedObject(ObjSize, ArgOffset, true, false);
+      int FI = MFI->CreateFixedObject(ObjSize, ArgOffset, true);
       SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
       ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, NULL, 0, false, false, 0);
       ArgOffset += StackSlotSize;
@@ -1095,8 +1095,7 @@
 
     for (; ArgRegIdx != NumArgRegs; ++ArgRegIdx) {
       FuncInfo->setVarArgsFrameIndex(
-        MFI->CreateFixedObject(StackSlotSize, ArgOffset,
-                               true, false));
+        MFI->CreateFixedObject(StackSlotSize, ArgOffset, true));
       SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
       unsigned VReg = MF.addLiveIn(ArgRegs[ArgRegIdx], &SPU::R32CRegClass);
       SDValue ArgVal = DAG.getRegister(VReg, MVT::v16i8);

Modified: llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp?rev=107550&r1=107549&r2=107550&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp Fri Jul  2 19:40:23 2010
@@ -588,7 +588,7 @@
       // Create the frame index object for this incoming parameter
       LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset());
       int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
-                                      LastArgStackLoc, true, false);
+                                      LastArgStackLoc, true);
 
       SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
 
@@ -777,7 +777,7 @@
       // offset on PEI::calculateFrameObjectOffsets.
       // Arguments are always 32-bit.
       unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
-      int FI = MFI->CreateFixedObject(ArgSize, 0, true, false);
+      int FI = MFI->CreateFixedObject(ArgSize, 0, true);
       MBlazeFI->recordLoadArgsFI(FI, -(ArgSize+
         (FirstStackArgLoc + VA.getLocMemOffset())));
 
@@ -808,7 +808,7 @@
       unsigned LiveReg = MF.addLiveIn(Reg, RC);
       SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, LiveReg, MVT::i32);
 
-      int FI = MFI->CreateFixedObject(4, 0, true, false);
+      int FI = MFI->CreateFixedObject(4, 0, true);
       MBlazeFI->recordStoreVarArgsFI(FI, -(4+(StackLoc*4)));
       SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
       OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff, NULL, 0,

Modified: llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp?rev=107550&r1=107549&r2=107550&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp Fri Jul  2 19:40:23 2010
@@ -369,7 +369,7 @@
              << "\n";
       }
       // Create the frame index object for this incoming parameter...
-      int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true, false);
+      int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
 
       // Create the SelectionDAG nodes corresponding to a load
       //from this parameter
@@ -888,7 +888,7 @@
     // Set up a frame object for the return address.
     uint64_t SlotSize = TD->getPointerSize();
     ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
-                                                           true, false);
+                                                           true);
     FuncInfo->setRAIndex(ReturnAddrIndex);
   }
 

Modified: llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp?rev=107550&r1=107549&r2=107550&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp Fri Jul  2 19:40:23 2010
@@ -229,7 +229,7 @@
   // Create a frame entry for the FPW register that must be saved.
   if (hasFP(MF)) {
     int ATTRIBUTE_UNUSED FrameIdx =
-      MF.getFrameInfo()->CreateFixedObject(2, -4, true, false);
+      MF.getFrameInfo()->CreateFixedObject(2, -4, true);
     assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
            "Slot for FPW register must be last in order to be found!");
   }

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=107550&r1=107549&r2=107550&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Fri Jul  2 19:40:23 2010
@@ -787,7 +787,7 @@
   // the stack (even if less than 4 are used as arguments)
   if (Subtarget->isABI_O32()) {
     int VTsize = EVT(MVT::i32).getSizeInBits()/8;
-    MFI->CreateFixedObject(VTsize, (VTsize*3), true, false);
+    MFI->CreateFixedObject(VTsize, (VTsize*3), true);
     CCInfo.AnalyzeCallOperands(Outs, 
                      isVarArg ? CC_MipsO32_VarArgs : CC_MipsO32);
   } else
@@ -857,7 +857,7 @@
     // if O32 ABI is used. For EABI the first address is zero.
     LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset());
     int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
-                                    LastArgStackLoc, true, false);
+                                    LastArgStackLoc, true);
 
     SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
 
@@ -929,7 +929,7 @@
         // Create the frame index only once. SPOffset here can be anything 
         // (this will be fixed on processFunctionBeforeFrameFinalized)
         if (MipsFI->getGPStackOffset() == -1) {
-          FI = MFI->CreateFixedObject(4, 0, true, false);
+          FI = MFI->CreateFixedObject(4, 0, true);
           MipsFI->setGPFI(FI);
         }
         MipsFI->setGPStackOffset(LastArgStackLoc);
@@ -1098,7 +1098,7 @@
       // offset on PEI::calculateFrameObjectOffsets.
       // Arguments are always 32-bit.
       unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
-      int FI = MFI->CreateFixedObject(ArgSize, 0, true, false);
+      int FI = MFI->CreateFixedObject(ArgSize, 0, true);
       MipsFI->recordLoadArgsFI(FI, -(ArgSize+
         (FirstStackArgLoc + VA.getLocMemOffset())));
 
@@ -1137,7 +1137,7 @@
       unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgRegEnd, RC);
       SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, MVT::i32);
 
-      int FI = MFI->CreateFixedObject(4, 0, true, false);
+      int FI = MFI->CreateFixedObject(4, 0, true);
       MipsFI->recordStoreVarArgsFI(FI, -(4+(StackLoc*4)));
       SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
       OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff, NULL, 0,

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=107550&r1=107549&r2=107550&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Fri Jul  2 19:40:23 2010
@@ -1631,7 +1631,7 @@
 
       unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
       int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
-                                      isImmutable, false);
+                                      isImmutable);
 
       // Create load nodes to retrieve arguments from the stack.
       SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
@@ -1700,8 +1700,7 @@
 
     FuncInfo->setVarArgsStackOffset(
       MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
-                             CCInfo.getNextStackOffset(),
-                             true, false));
+                             CCInfo.getNextStackOffset(), true));
 
     FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
     SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
@@ -1911,7 +1910,7 @@
         CurArgOffset = CurArgOffset + (4 - ObjSize);
       }
       // The value of the object is its address.
-      int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true, false);
+      int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
       SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
       InVals.push_back(FIN);
       if (ObjSize==1 || ObjSize==2) {
@@ -1936,7 +1935,7 @@
         // the object.
         if (GPR_idx != Num_GPR_Regs) {
           unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
-          int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true, false);
+          int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
           SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
           SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
           SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0,
@@ -2062,7 +2061,7 @@
     if (needsLoad) {
       int FI = MFI->CreateFixedObject(ObjSize,
                                       CurArgOffset + (ArgSize - ObjSize),
-                                      isImmutable, false);
+                                      isImmutable);
       SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
       ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, NULL, 0,
                            false, false, 0);
@@ -2097,7 +2096,7 @@
 
     FuncInfo->setVarArgsFrameIndex(
       MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
-                             Depth, true, false));
+                             Depth, true));
     SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
 
     // If this function is vararg, store any remaining integer argument regs
@@ -2314,8 +2313,7 @@
     int NewRetAddrLoc = SPDiff + PPCFrameInfo::getReturnSaveOffset(isPPC64,
                                                                    isDarwinABI);
     int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
-                                                          NewRetAddrLoc,
-                                                          true, false);
+                                                          NewRetAddrLoc, true);
     EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
     SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
     Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
@@ -2328,7 +2326,7 @@
       int NewFPLoc =
         SPDiff + PPCFrameInfo::getFramePointerSaveOffset(isPPC64, isDarwinABI);
       int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
-                                                          true, false);
+                                                          true);
       SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
       Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
                            PseudoSourceValue::getFixedStack(NewFPIdx), 0,
@@ -2346,7 +2344,7 @@
                       SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
   int Offset = ArgOffset + SPDiff;
   uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
-  int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true,false);
+  int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
   EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
   SDValue FIN = DAG.getFrameIndex(FI, VT);
   TailCallArgumentInfo Info;
@@ -3375,8 +3373,7 @@
     // Find out what the fix offset of the frame pointer save area.
     int LROffset = PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI);
     // Allocate the frame index for frame pointer save area.
-    RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset,
-                                                true, false);
+    RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
     // Save the result.
     FI->setReturnAddrSaveIndex(RASI);
   }
@@ -3402,8 +3399,7 @@
                                                            isDarwinABI);
 
     // Allocate the frame index for frame pointer save area.
-    FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset,
-                                                true, false);
+    FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
     // Save the result.
     FI->setFramePointerSaveIndex(FPSI);
   }

Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=107550&r1=107549&r2=107550&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Fri Jul  2 19:40:23 2010
@@ -926,8 +926,7 @@
     int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64,
                                                            isDarwinABI);
     // Allocate the frame index for frame pointer save area.
-    FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset,
-                                                true, false);
+    FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
     // Save the result.
     FI->setFramePointerSaveIndex(FPSI);                      
   }
@@ -935,8 +934,7 @@
   // Reserve stack space to move the linkage area to in case of a tail call.
   int TCSPDelta = 0;
   if (GuaranteedTailCallOpt && (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
-    MF.getFrameInfo()->CreateFixedObject(-1 * TCSPDelta, TCSPDelta,
-                                         true, false);
+    MF.getFrameInfo()->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
   }
   
   // Reserve a slot closest to SP or frame pointer if we have a dynalloc or

Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=107550&r1=107549&r2=107550&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Fri Jul  2 19:40:23 2010
@@ -133,7 +133,7 @@
         InVals.push_back(Arg);
       } else {
         int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset,
-                                                            true, false);
+                                                            true);
         SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
         SDValue Load;
         if (ObjectVT == MVT::i32) {
@@ -169,7 +169,7 @@
         InVals.push_back(Arg);
       } else {
         int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset,
-                                                            true, false);
+                                                            true);
         SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
         SDValue Load = DAG.getLoad(MVT::f32, dl, Chain, FIPtr, NULL, 0,
                                    false, false, 0);
@@ -192,7 +192,7 @@
           HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32);
         } else {
           int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset,
-                                                              true, false);
+                                                              true);
           SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
           HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, NULL, 0,
                               false, false, 0);
@@ -205,7 +205,7 @@
           LoVal = DAG.getCopyFromReg(Chain, dl, VRegLo, MVT::i32);
         } else {
           int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4,
-                                                              true, false);
+                                                              true);
           SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
           LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, NULL, 0,
                               false, false, 0);
@@ -239,7 +239,7 @@
       SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32);
 
       int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset,
-                                                          true, false);
+                                                          true);
       SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
 
       OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr, NULL, 0,

Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp?rev=107550&r1=107549&r2=107550&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp Fri Jul  2 19:40:23 2010
@@ -334,7 +334,7 @@
       // Create the nodes corresponding to a load from this parameter slot.
       // Create the frame index object for this incoming parameter...
       int FI = MFI->CreateFixedObject(LocVT.getSizeInBits()/8,
-                                      VA.getLocMemOffset(), true, false);
+                                      VA.getLocMemOffset(), true);
 
       // Create the SelectionDAG nodes corresponding to a load
       // from this parameter

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=107550&r1=107549&r2=107550&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Jul  2 19:40:23 2010
@@ -1485,11 +1485,11 @@
   // could be overwritten by lowering of arguments in case of a tail call.
   if (Flags.isByVal()) {
     int FI = MFI->CreateFixedObject(Flags.getByValSize(),
-                                    VA.getLocMemOffset(), isImmutable, false);
+                                    VA.getLocMemOffset(), isImmutable);
     return DAG.getFrameIndex(FI, getPointerTy());
   } else {
     int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
-                                    VA.getLocMemOffset(), isImmutable, false);
+                                    VA.getLocMemOffset(), isImmutable);
     SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
     return DAG.getLoad(ValVT, dl, Chain, FIN,
                        PseudoSourceValue::getFixedStack(FI), 0,
@@ -1617,8 +1617,7 @@
   if (isVarArg) {
     if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
                     CallConv != CallingConv::X86_ThisCall)) {
-      FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,
-                                                            true, false));
+      FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
     }
     if (Is64Bit) {
       unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
@@ -1790,7 +1789,7 @@
   // Calculate the new stack slot for the return address.
   int SlotSize = Is64Bit ? 8 : 4;
   int NewReturnAddrFI =
-    MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false, false);
+    MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
   EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
   SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
   Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
@@ -2020,7 +2019,7 @@
         // Create frame index.
         int32_t Offset = VA.getLocMemOffset()+FPDiff;
         uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
-        FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true, false);
+        FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
         FIN = DAG.getFrameIndex(FI, getPointerTy());
 
         if (Flags.isByVal()) {
@@ -2487,7 +2486,7 @@
     // Set up a frame object for the return address.
     uint64_t SlotSize = TD->getPointerSize();
     ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
-                                                           false, false);
+                                                           false);
     FuncInfo->setRAIndex(ReturnAddrIndex);
   }
 

Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=107550&r1=107549&r2=107550&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Fri Jul  2 19:40:23 2010
@@ -674,8 +674,7 @@
     //   }
     //   [EBP]
     MFI->CreateFixedObject(-TailCallReturnAddrDelta,
-                           (-1U*SlotSize)+TailCallReturnAddrDelta,
-                           true, false);
+                           (-1U*SlotSize)+TailCallReturnAddrDelta, true);
   }
 
   if (hasFP(MF)) {
@@ -688,7 +687,7 @@
                                           -(int)SlotSize +
                                           TFI.getOffsetOfLocalArea() +
                                           TailCallReturnAddrDelta,
-                                          true, false);
+                                          true);
     assert(FrameIdx == MFI->getObjectIndexBegin() &&
            "Slot for EBP register must be last in order to be found!");
     FrameIdx = 0;

Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp?rev=107550&r1=107549&r2=107550&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Fri Jul  2 19:40:23 2010
@@ -1072,7 +1072,7 @@
       // Create the frame index object for this incoming parameter...
       int FI = MFI->CreateFixedObject(ObjSize,
                                       LRSaveSize + VA.getLocMemOffset(),
-                                      true, false);
+                                      true);
 
       // Create the SelectionDAG nodes corresponding to a load
       //from this parameter
@@ -1097,7 +1097,7 @@
       // address
       for (unsigned i = array_lengthof(ArgRegs) - 1; i >= FirstVAReg; --i) {
         // Create a stack slot
-        int FI = MFI->CreateFixedObject(4, offset, true, false);
+        int FI = MFI->CreateFixedObject(4, offset, true);
         if (i == FirstVAReg) {
           XFI->setVarArgsFrameIndex(FI);
         }
@@ -1120,7 +1120,7 @@
       // This will point to the next argument passed via stack.
       XFI->setVarArgsFrameIndex(
         MFI->CreateFixedObject(4, LRSaveSize + CCInfo.getNextStackOffset(),
-                               true, false));
+                               true));
     }
   }
   

Modified: llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp?rev=107550&r1=107549&r2=107550&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp Fri Jul  2 19:40:23 2010
@@ -308,7 +308,7 @@
     int FrameIdx;
     if (! isVarArg) {
       // A fixed offset of 0 allows us to save / restore LR using entsp / retsp.
-      FrameIdx = MFI->CreateFixedObject(RC->getSize(), 0, true, false);
+      FrameIdx = MFI->CreateFixedObject(RC->getSize(), 0, true);
     } else {
       FrameIdx = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(),
                                         false);




From bruno.cardoso at gmail.com  Fri Jul  2 19:49:21 2010
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Sat, 03 Jul 2010 00:49:21 -0000
Subject: [llvm-commits] [llvm] r107552 - in /llvm/trunk:
 lib/Target/X86/X86InstrSSE.td test/MC/AsmParser/X86/x86_32-encoding.s
 test/MC/AsmParser/X86/x86_64-encoding.s
Message-ID: <20100703004921.5B3712A6C12C@llvm.org>

Author: bruno
Date: Fri Jul  2 19:49:21 2010
New Revision: 107552

URL: http://llvm.org/viewvc/llvm-project?rev=107552&view=rev
Log:
Add AVX SSE4.1 Horizontal Minimum and Position instruction

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
    llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=107552&r1=107551&r2=107552&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Fri Jul  2 19:49:21 2010
@@ -4097,6 +4097,9 @@
                        (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
 }
 
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in
+defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
+                                         int_x86_sse41_phminposuw>, VEX;
 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
                                          int_x86_sse41_phminposuw>;
 

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s?rev=107552&r1=107551&r2=107552&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s Fri Jul  2 19:49:21 2010
@@ -11774,3 +11774,11 @@
 // CHECK: encoding: [0xc4,0xe3,0x79,0x08,0x18,0x07]
           vroundps  $7, (%eax), %xmm3
 
+// CHECK: vphminposuw  %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x79,0x41,0xda]
+          vphminposuw  %xmm2, %xmm3
+
+// CHECK: vphminposuw  (%eax), %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x79,0x41,0x10]
+          vphminposuw  (%eax), %xmm2
+

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s?rev=107552&r1=107551&r2=107552&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s Fri Jul  2 19:49:21 2010
@@ -1822,3 +1822,11 @@
 // CHECK: encoding: [0xc4,0x63,0x79,0x08,0x28,0x07]
           vroundps  $7, (%rax), %xmm13
 
+// CHECK: vphminposuw  %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x42,0x79,0x41,0xec]
+          vphminposuw  %xmm12, %xmm13
+
+// CHECK: vphminposuw  (%rax), %xmm12
+// CHECK: encoding: [0xc4,0x62,0x79,0x41,0x20]
+          vphminposuw  (%rax), %xmm12
+




From gkistanova at gmail.com  Fri Jul  2 19:51:35 2010
From: gkistanova at gmail.com (Galina Kistanova)
Date: Sat, 03 Jul 2010 00:51:35 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r107553 - in
 /llvm-gcc-4.2/trunk/extras: build-4-mingw32 build-self-4-mingw32
 build-x-4-linux build-x-4-mingw32
Message-ID: <20100703005135.91F702A6C12C@llvm.org>

Author: gkistanova
Date: Fri Jul  2 19:51:35 2010
New Revision: 107553

URL: http://llvm.org/viewvc/llvm-project?rev=107553&view=rev
Log:
Cosmetic change in scripts for ScriptedBuilder.

Modified:
    llvm-gcc-4.2/trunk/extras/build-4-mingw32
    llvm-gcc-4.2/trunk/extras/build-self-4-mingw32
    llvm-gcc-4.2/trunk/extras/build-x-4-linux
    llvm-gcc-4.2/trunk/extras/build-x-4-mingw32

Modified: llvm-gcc-4.2/trunk/extras/build-4-mingw32
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/extras/build-4-mingw32?rev=107553&r1=107552&r2=107553&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/extras/build-4-mingw32 (original)
+++ llvm-gcc-4.2/trunk/extras/build-4-mingw32 Fri Jul  2 19:51:35 2010
@@ -171,7 +171,6 @@
 if [ "$do_make_llvmgcc" == "yes" ] ; then
 
    cd ${BUILD_ROOT}/${LLVM_GCC_obj}
-   # NOTE: Do not build in parallel! It doesn't build.
    nice -n 20 make          \
       $@  # Extra args if any
 

Modified: llvm-gcc-4.2/trunk/extras/build-self-4-mingw32
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/extras/build-self-4-mingw32?rev=107553&r1=107552&r2=107553&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/extras/build-self-4-mingw32 (original)
+++ llvm-gcc-4.2/trunk/extras/build-self-4-mingw32 Fri Jul  2 19:51:35 2010
@@ -224,7 +224,6 @@
 if [ "$do_make_llvmgcc_1" == "yes" ] ; then
 
    cd ${BUILD_ROOT}/${LLVM_GCC_obj_1}
-   # NOTE: Do not build in parallel! It doesn't build.
    nice -n 20 make          \
       $@  # Extra args if any
 
@@ -341,7 +340,6 @@
    fi
 
    cd ${BUILD_ROOT}/${LLVM_GCC_obj_2}
-   # NOTE: Do not build in parallel! It doesn't build.
    nice -n 20 make          \
       $@  # Extra args if any
 

Modified: llvm-gcc-4.2/trunk/extras/build-x-4-linux
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/extras/build-x-4-linux?rev=107553&r1=107552&r2=107553&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/extras/build-x-4-linux (original)
+++ llvm-gcc-4.2/trunk/extras/build-x-4-linux Fri Jul  2 19:51:35 2010
@@ -189,7 +189,6 @@
 if [ "$do_make_llvmgcc" == "yes" ] ; then
 
    cd ${BUILD_ROOT}/${LLVM_GCC_obj}
-   # NOTE: Do not build in parallel! It doesn't build.
    nice -n 20 make          \
       $@  # Extra args if any
 

Modified: llvm-gcc-4.2/trunk/extras/build-x-4-mingw32
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/extras/build-x-4-mingw32?rev=107553&r1=107552&r2=107553&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/extras/build-x-4-mingw32 (original)
+++ llvm-gcc-4.2/trunk/extras/build-x-4-mingw32 Fri Jul  2 19:51:35 2010
@@ -195,7 +195,6 @@
 if [ "$do_make_llvmgcc" == "yes" ] ; then
 
    cd ${BUILD_ROOT}/${LLVM_GCC_obj}
-   # NOTE: Do not build in parallel! It doesn't build.
    nice -n 20 make          \
       $@  # Extra args if any
 




From evan.cheng at apple.com  Fri Jul  2 19:54:37 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 2 Jul 2010 17:54:37 -0700
Subject: [llvm-commits] [llvm] r107114 -
	/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
In-Reply-To: <0F336F91-F80B-425F-B3AD-DCFAB44E6F16@apple.com>
References: <20100629011307.645212A6C12C@llvm.org>
	<04D10EF1-91D9-44D6-9161-161B70493ED7@apple.com>
	<5F342D90-DC02-47A6-A825-EAD20CBFA547@2pi.dk>
	<0BC7E25D-4488-4954-A149-0D27BF55BBAE@apple.com>
	<58535D1C-837D-4136-A1D6-9809389E70F3@2pi.dk>
	<0F336F91-F80B-425F-B3AD-DCFAB44E6F16@apple.com>
Message-ID: <8790C1B7-44AF-446B-AFAE-563E00DFD3C6@apple.com>

I've looked into this. The main issue is when the register allocator folded reloads from fixed slots the loads ended up with alignment 1. That's because by default all fixed slots have alignment of 1. This is overly conservative. DAG combiner will infer the correct alignments from stack pointer alignments and frame offset. But at register allocation time we are simply taking the frame object's alignments.

I think the right fix is to make sure the fixed objects have the inferred alignments when they are created. Does anyone see a problem with that?

Evan

On Jun 29, 2010, at 6:03 PM, Evan Cheng wrote:

> 
> On Jun 29, 2010, at 1:39 PM, Jakob Stoklund Olesen wrote:
> 
>> 
>> On Jun 28, 2010, at 10:46 PM, Evan Cheng wrote:
>> 
>>> 
>>> On Jun 28, 2010, at 10:09 PM, Jakob Stoklund Olesen wrote:
>>> 
>>>> 
>>>> On Jun 28, 2010, at 10:00 PM, Evan Cheng wrote:
>>>> 
>>>>> 
>>>>> On Jun 28, 2010, at 6:13 PM, Jakob Stoklund Olesen wrote:
>>>>> 
>>>>>> Author: stoklund
>>>>>> Date: Mon Jun 28 20:13:07 2010
>>>>>> New Revision: 107114
>>>>>> 
>>>>>> URL: http://llvm.org/viewvc/llvm-project?rev=107114&view=rev
>>>>>> Log:
>>>>>> When no memoperands are present, assume unaligned, volatile.
>>>>> 
>>>>> Have you checked if this disabled a lot of potential optimizations? I am afraid assuming volatileness is overly conservative.
>>>> 
>>>> I haven't checked anything but running unit tests.
>>>> 
>>>> We need both non-volatile and 4-byte alignment to safely combine loads and stores. If memoperands are missing, I don't see any alternative. How else can we guarantee the optimization is valid?
>>>> 
>>>> If this causes missed optimizations, we should ensure that memory operands are present.
>>> 
>>> I agree. I am just wondering if that's indeed the case. Can you add a llc beta check to look for differences in # of load / store multiple optimizations?
>> 
>> I ran an assembly diff across the entire nightly test suite.
>> 
>> We lost 117 of 56783 ldms and 40 of 47702 stms.
> 
> Thanks. Can you file a bug about this? We should take a look.
> 
> Evan
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

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From scanon at apple.com  Fri Jul  2 19:56:04 2010
From: scanon at apple.com (Stephen Canon)
Date: Sat, 03 Jul 2010 00:56:04 -0000
Subject: [llvm-commits] [compiler-rt] r107554 - in /compiler-rt/trunk/lib:
 floatunsidf.c floatunsisf.c floatunssidf.c floatunssisf.c negdf2.c negsf2.c
Message-ID: <20100703005604.199E72A6C12C@llvm.org>

Author: scanon
Date: Fri Jul  2 19:56:03 2010
New Revision: 107554

URL: http://llvm.org/viewvc/llvm-project?rev=107554&view=rev
Log:
Renamed unsigned->float routines to match GCC convention

Added:
    compiler-rt/trunk/lib/floatunsidf.c
      - copied, changed from r107535, compiler-rt/trunk/lib/floatunssidf.c
    compiler-rt/trunk/lib/floatunsisf.c
      - copied, changed from r107535, compiler-rt/trunk/lib/floatunssisf.c
Removed:
    compiler-rt/trunk/lib/floatunssidf.c
    compiler-rt/trunk/lib/floatunssisf.c
Modified:
    compiler-rt/trunk/lib/negdf2.c
    compiler-rt/trunk/lib/negsf2.c

Copied: compiler-rt/trunk/lib/floatunsidf.c (from r107535, compiler-rt/trunk/lib/floatunssidf.c)
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/floatunsidf.c?p2=compiler-rt/trunk/lib/floatunsidf.c&p1=compiler-rt/trunk/lib/floatunssidf.c&r1=107535&r2=107554&rev=107554&view=diff
==============================================================================
--- compiler-rt/trunk/lib/floatunssidf.c (original)
+++ compiler-rt/trunk/lib/floatunsidf.c Fri Jul  2 19:56:03 2010
@@ -1,4 +1,4 @@
-//===-- lib/floatunssidf.c - uint -> double-precision conversion --*- C -*-===//
+//===-- lib/floatunsidf.c - uint -> double-precision conversion ---*- C -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -16,7 +16,7 @@
 #define DOUBLE_PRECISION
 #include "fp_lib.h"
 
-fp_t __floatunssidf(unsigned int a) {
+fp_t __floatunsidf(unsigned int a) {
     
     const int aWidth = sizeof a * CHAR_BIT;
     

Copied: compiler-rt/trunk/lib/floatunsisf.c (from r107535, compiler-rt/trunk/lib/floatunssisf.c)
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/floatunsisf.c?p2=compiler-rt/trunk/lib/floatunsisf.c&p1=compiler-rt/trunk/lib/floatunssisf.c&r1=107535&r2=107554&rev=107554&view=diff
==============================================================================
--- compiler-rt/trunk/lib/floatunssisf.c (original)
+++ compiler-rt/trunk/lib/floatunsisf.c Fri Jul  2 19:56:03 2010
@@ -1,4 +1,4 @@
-//===-- lib/floatunssisf.c - uint -> single-precision conversion --*- C -*-===//
+//===-- lib/floatunsisf.c - uint -> single-precision conversion ---*- C -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -16,7 +16,7 @@
 #define SINGLE_PRECISION
 #include "fp_lib.h"
 
-fp_t __floatunssisf(unsigned int a) {
+fp_t __floatunsisf(unsigned int a) {
     
     const int aWidth = sizeof a * CHAR_BIT;
     

Removed: compiler-rt/trunk/lib/floatunssidf.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/floatunssidf.c?rev=107553&view=auto
==============================================================================
--- compiler-rt/trunk/lib/floatunssidf.c (original)
+++ compiler-rt/trunk/lib/floatunssidf.c (removed)
@@ -1,45 +0,0 @@
-//===-- lib/floatunssidf.c - uint -> double-precision conversion --*- C -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file implements unsigned integer to double-precision conversion for the
-// compiler-rt library in the IEEE-754 default round-to-nearest, ties-to-even
-// mode.
-//
-//===----------------------------------------------------------------------===//
-
-#define DOUBLE_PRECISION
-#include "fp_lib.h"
-
-fp_t __floatunssidf(unsigned int a) {
-    
-    const int aWidth = sizeof a * CHAR_BIT;
-    
-    // Handle zero as a special case to protect clz
-    if (a == 0) return fromRep(0);
-    
-    // Exponent of (fp_t)a is the width of abs(a).
-    const int exponent = (aWidth - 1) - __builtin_clz(a);
-    rep_t result;
-    
-    // Shift a into the significand field, rounding if it is a right-shift
-    if (exponent <= significandBits) {
-        const int shift = significandBits - exponent;
-        result = (rep_t)a << shift ^ implicitBit;
-    } else {
-        const int shift = exponent - significandBits;
-        result = (rep_t)a >> shift ^ implicitBit;
-        rep_t round = (rep_t)a << (typeWidth - shift);
-        if (round > signBit) result++;
-        if (round == signBit) result += result & 1;
-    }
-    
-    // Insert the exponent
-    result += (rep_t)(exponent + exponentBias) << significandBits;
-    return fromRep(result);
-}

Removed: compiler-rt/trunk/lib/floatunssisf.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/floatunssisf.c?rev=107553&view=auto
==============================================================================
--- compiler-rt/trunk/lib/floatunssisf.c (original)
+++ compiler-rt/trunk/lib/floatunssisf.c (removed)
@@ -1,45 +0,0 @@
-//===-- lib/floatunssisf.c - uint -> single-precision conversion --*- C -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file implements unsigned integer to single-precision conversion for the
-// compiler-rt library in the IEEE-754 default round-to-nearest, ties-to-even
-// mode.
-//
-//===----------------------------------------------------------------------===//
-
-#define SINGLE_PRECISION
-#include "fp_lib.h"
-
-fp_t __floatunssisf(unsigned int a) {
-    
-    const int aWidth = sizeof a * CHAR_BIT;
-    
-    // Handle zero as a special case to protect clz
-    if (a == 0) return fromRep(0);
-    
-    // Exponent of (fp_t)a is the width of abs(a).
-    const int exponent = (aWidth - 1) - __builtin_clz(a);
-    rep_t result;
-    
-    // Shift a into the significand field, rounding if it is a right-shift
-    if (exponent <= significandBits) {
-        const int shift = significandBits - exponent;
-        result = (rep_t)a << shift ^ implicitBit;
-    } else {
-        const int shift = exponent - significandBits;
-        result = (rep_t)a >> shift ^ implicitBit;
-        rep_t round = (rep_t)a << (typeWidth - shift);
-        if (round > signBit) result++;
-        if (round == signBit) result += result & 1;
-    }
-    
-    // Insert the exponent
-    result += (rep_t)(exponent + exponentBias) << significandBits;
-    return fromRep(result);
-}

Modified: compiler-rt/trunk/lib/negdf2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/negdf2.c?rev=107554&r1=107553&r2=107554&view=diff
==============================================================================
--- compiler-rt/trunk/lib/negdf2.c (original)
+++ compiler-rt/trunk/lib/negdf2.c Fri Jul  2 19:56:03 2010
@@ -1,4 +1,4 @@
-//===-- lib/negdf3.c - double-precision negation ------------------*- C -*-===//
+//===-- lib/negdf2.c - double-precision negation ------------------*- C -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //

Modified: compiler-rt/trunk/lib/negsf2.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/negsf2.c?rev=107554&r1=107553&r2=107554&view=diff
==============================================================================
--- compiler-rt/trunk/lib/negsf2.c (original)
+++ compiler-rt/trunk/lib/negsf2.c Fri Jul  2 19:56:03 2010
@@ -1,4 +1,4 @@
-//===-- lib/negsf3.c - single-precision negation ------------------*- C -*-===//
+//===-- lib/negsf2.c - single-precision negation ------------------*- C -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //




From scanon at apple.com  Fri Jul  2 20:00:49 2010
From: scanon at apple.com (Stephen Canon)
Date: Sat, 03 Jul 2010 01:00:49 -0000
Subject: [llvm-commits] [compiler-rt] r107555 - in
	/compiler-rt/trunk/lib/arm: bswapdi2.S bswapsi2.S
Message-ID: <20100703010049.D01E92A6C12C@llvm.org>

Author: scanon
Date: Fri Jul  2 20:00:49 2010
New Revision: 107555

URL: http://llvm.org/viewvc/llvm-project?rev=107555&view=rev
Log:
Marginally smaller implementations of bswap for ARMv4, ARMv5 that avoid the need to establish a frame

Modified:
    compiler-rt/trunk/lib/arm/bswapdi2.S
    compiler-rt/trunk/lib/arm/bswapsi2.S

Modified: compiler-rt/trunk/lib/arm/bswapdi2.S
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/bswapdi2.S?rev=107555&r1=107554&r2=107555&view=diff
==============================================================================
--- compiler-rt/trunk/lib/arm/bswapdi2.S (original)
+++ compiler-rt/trunk/lib/arm/bswapdi2.S Fri Jul  2 20:00:49 2010
@@ -1,4 +1,4 @@
-//===------- bswapdi2 - Implement bswapdi2 ---------------------------------===//
+//===------- bswapdi2 - Implement bswapdi2 --------------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -14,30 +14,25 @@
 //
 // Reverse all the bytes in a 64-bit integer.
 //
-	.align 2
+    .align 2
 DEFINE_COMPILERRT_FUNCTION(__bswapdi2)
 #if __ARM_ARCH_5TEJ__ || __ARM_ARCH_4T__
-	// before armv6 does not have "rev" instruction
-	stmfd	sp!, {r7, lr}
-	mov	r7, sp
-	mov	r2, #255, 24
-	and	r3, r2, r1, lsr #8
-	mov	r12, #255, 16
-	and	lr, r12, r1, lsl #8
-	orr	r3, r3, r1, lsr #24
-	orr	r1, lr, r1, lsl #24
-	and	r2, r2, r0, lsr #8
-	orr	r3, r1, r3
-	orr	r1, r2, r0, lsr #24
-	and	r2, r12, r0, lsl #8
-	orr	r0, r2, r0, lsl #24
-	orr	r1, r0, r1
-	mov	r0, r3
-	ldmfd	sp!, {r7, pc}
+    mov r12, #0xff00
+    
+    and r3,  r12, r0, lsr #8
+    and r2,  r12, r0    
+    orr r3,   r3, r0, lsr #24   
+    orr r3,   r3, r0, lsl #24
+    orr r2,   r3, r2, lsl #8  // r2 = rev(r0)
+    
+    and r3,  r12, r1, lsr #8
+    and r0,  r12, r1
+    orr r3,   r3, r1, lsr #24
+    orr r3,   r3, r1, lsl #24
+    orr r0,   r3, r0, lsl #8  // r0 = rev(r1)
 #else
-	rev	r2, r1		// reverse bytes in high 32-bits into temp2
-	rev	r3, r0		// reverse bytes in low 32-bit into temp3
-	mov	r0, r2		// set low 32-bits of result to temp2
-	mov	r1, r3		// set high 32-bits of result to temp3
-	bx	lr
+    rev r2,   r0  // r2 = rev(r0)
+    rev r0,   r1  // r0 = rev(r1)
 #endif
+    mov r1,   r2  // r1 = r2 = rev(r0)
+    bx  lr

Modified: compiler-rt/trunk/lib/arm/bswapsi2.S
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/bswapsi2.S?rev=107555&r1=107554&r2=107555&view=diff
==============================================================================
--- compiler-rt/trunk/lib/arm/bswapsi2.S (original)
+++ compiler-rt/trunk/lib/arm/bswapsi2.S Fri Jul  2 20:00:49 2010
@@ -1,4 +1,4 @@
-//===------- bswapsi2 - Implement bswapsi2 ---------------------------------===//
+//===------- bswapsi2 - Implement bswapsi2 --------------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -18,13 +18,12 @@
 DEFINE_COMPILERRT_FUNCTION(__bswapsi2)
 #if __ARM_ARCH_5TEJ__ || __ARM_ARCH_4T__
 	// before armv6 does not have "rev" instruction
-	mov	r1, #255, 24
-	mov	r2, #255, 16
-	and	r1, r1, r0, lsr #8
-	and	r2, r2, r0, lsl #8
-	orr	r1, r1, r0, lsr #24
-	orr	r0, r2, r0, lsl #24
-	orr	r0, r0, r1
+    mov r1, #0xff00
+    and r2, r1, r0, lsr #8 
+    and r1, r1, r0   
+    orr r2, r2, r0, lsr #24
+    orr r2, r2, r0, lsl #24
+    orr r0, r2, r1, lsl #8
 #else
 	rev	r0, r0		// reverse bytes in parameter and put into result register
 #endif




From stoklund at 2pi.dk  Fri Jul  2 20:01:24 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Fri, 2 Jul 2010 18:01:24 -0700
Subject: [llvm-commits] [llvm] r107114 -
	/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
In-Reply-To: <8790C1B7-44AF-446B-AFAE-563E00DFD3C6@apple.com>
References: <20100629011307.645212A6C12C@llvm.org>
	<04D10EF1-91D9-44D6-9161-161B70493ED7@apple.com>
	<5F342D90-DC02-47A6-A825-EAD20CBFA547@2pi.dk>
	<0BC7E25D-4488-4954-A149-0D27BF55BBAE@apple.com>
	<58535D1C-837D-4136-A1D6-9809389E70F3@2pi.dk>
	<0F336F91-F80B-425F-B3AD-DCFAB44E6F16@apple.com>
	<8790C1B7-44AF-446B-AFAE-563E00DFD3C6@apple.com>
Message-ID: <A09A1B14-CBF7-4203-AF81-FFAD0E86BEBC@2pi.dk>


On Jul 2, 2010, at 5:54 PM, Evan Cheng wrote:

> I've looked into this. The main issue is when the register allocator folded reloads from fixed slots the loads ended up with alignment 1. That's because by default all fixed slots have alignment of 1. This is overly conservative. DAG combiner will infer the correct alignments from stack pointer alignments and frame offset. But at register allocation time we are simply taking the frame object's alignments.
> 
> I think the right fix is to make sure the fixed objects have the inferred alignments when they are created. Does anyone see a problem with that?

That sounds reasonable to me.


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From echristo at apple.com  Fri Jul  2 20:06:41 2010
From: echristo at apple.com (Eric Christopher)
Date: Fri, 2 Jul 2010 18:06:41 -0700
Subject: [llvm-commits] [llvm] r107114 -
	/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
In-Reply-To: <8790C1B7-44AF-446B-AFAE-563E00DFD3C6@apple.com>
References: <20100629011307.645212A6C12C@llvm.org>
	<04D10EF1-91D9-44D6-9161-161B70493ED7@apple.com>
	<5F342D90-DC02-47A6-A825-EAD20CBFA547@2pi.dk>
	<0BC7E25D-4488-4954-A149-0D27BF55BBAE@apple.com>
	<58535D1C-837D-4136-A1D6-9809389E70F3@2pi.dk>
	<0F336F91-F80B-425F-B3AD-DCFAB44E6F16@apple.com>
	<8790C1B7-44AF-446B-AFAE-563E00DFD3C6@apple.com>
Message-ID: <DD0A26AE-D457-402E-BCAD-7BB97FAC252C@apple.com>


On Jul 2, 2010, at 5:54 PM, Evan Cheng wrote:

> I think the right fix is to make sure the fixed objects have the inferred alignments when they are created. Does anyone see a problem with that?

I can't think of a time when we wouldn't want the inferred alignment.

-eric


From echristo at apple.com  Fri Jul  2 20:09:19 2010
From: echristo at apple.com (Eric Christopher)
Date: Sat, 03 Jul 2010 01:09:19 -0000
Subject: [llvm-commits] [llvm] r107556 -
	/llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp
Message-ID: <20100703010919.0D2F92A6C12C@llvm.org>

Author: echristo
Date: Fri Jul  2 20:09:18 2010
New Revision: 107556

URL: http://llvm.org/viewvc/llvm-project?rev=107556&view=rev
Log:
Fix typo.

Modified:
    llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp

Modified: llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp?rev=107556&r1=107555&r2=107556&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp (original)
+++ llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp Fri Jul  2 20:09:18 2010
@@ -116,7 +116,7 @@
       SmallVector<LiveInterval*, 4> spillIs;
       if (lis->isReMaterializable(li, spillIs, isLoad)) {
         // If all of the definitions of the interval are re-materializable,
-        // it is a preferred candidate for spilling. If non of the defs are
+        // it is a preferred candidate for spilling. If none of the defs are
         // loads, then it's potentially very cheap to re-materialize.
         // FIXME: this gets much more complicated once we support non-trivial
         // re-materialization.




From echristo at apple.com  Fri Jul  2 20:12:09 2010
From: echristo at apple.com (Eric Christopher)
Date: Sat, 03 Jul 2010 01:12:09 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r107557 -
	/llvm-gcc-4.2/trunk/gcc/config/i386/x-mingw32
Message-ID: <20100703011209.1099D2A6C12C@llvm.org>

Author: echristo
Date: Fri Jul  2 20:12:08 2010
New Revision: 107557

URL: http://llvm.org/viewvc/llvm-project?rev=107557&view=rev
Log:
Add proper dependency for diagnostic.h.

Patch by Alex Rosenberg!

Modified:
    llvm-gcc-4.2/trunk/gcc/config/i386/x-mingw32

Modified: llvm-gcc-4.2/trunk/gcc/config/i386/x-mingw32
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/x-mingw32?rev=107557&r1=107556&r2=107557&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/config/i386/x-mingw32 (original)
+++ llvm-gcc-4.2/trunk/gcc/config/i386/x-mingw32 Fri Jul  2 20:12:08 2010
@@ -8,6 +8,6 @@
 WERROR_FLAGS += -Wno-format
 
 host-mingw32.o : $(srcdir)/config/i386/host-mingw32.c $(CONFIG_H) $(SYSTEM_H) \
-  coretypes.h hosthooks.h hosthooks-def.h toplev.h diagnostic.h $(HOOKS_H)
+  coretypes.h hosthooks.h hosthooks-def.h toplev.h $(DIAGNOSTIC_H) $(HOOKS_H)
 	$(CC) -c $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
 		$(srcdir)/config/i386/host-mingw32.c




From bruno.cardoso at gmail.com  Fri Jul  2 20:15:47 2010
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Sat, 03 Jul 2010 01:15:47 -0000
Subject: [llvm-commits] [llvm] r107558 - in /llvm/trunk:
 lib/Target/X86/X86InstrSSE.td test/MC/AsmParser/X86/x86_32-encoding.s
 test/MC/AsmParser/X86/x86_64-encoding.s
Message-ID: <20100703011547.7D6052A6C12C@llvm.org>

Author: bruno
Date: Fri Jul  2 20:15:47 2010
New Revision: 107558

URL: http://llvm.org/viewvc/llvm-project?rev=107558&view=rev
Log:
Add AVX SSE4.1 binop (some forms of packed max,min,mul,pack,cmp) instructions

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
    llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=107558&r1=107557&r2=107558&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Fri Jul  2 20:15:47 2010
@@ -4123,6 +4123,32 @@
           (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
 }
 
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in {
+  let isCommutable = 0 in
+  defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
+                                                         0>, VEX_4V;
+  defm VPCMPEQQ  : SS41I_binop_rm_int<0x29, "vpcmpeqq",  int_x86_sse41_pcmpeqq,
+                                                         0>, VEX_4V;
+  defm VPMINSB   : SS41I_binop_rm_int<0x38, "vpminsb",   int_x86_sse41_pminsb,
+                                                         0>, VEX_4V;
+  defm VPMINSD   : SS41I_binop_rm_int<0x39, "vpminsd",   int_x86_sse41_pminsd,
+                                                         0>, VEX_4V;
+  defm VPMINUD   : SS41I_binop_rm_int<0x3B, "vpminud",   int_x86_sse41_pminud,
+                                                         0>, VEX_4V;
+  defm VPMINUW   : SS41I_binop_rm_int<0x3A, "vpminuw",   int_x86_sse41_pminuw,
+                                                         0>, VEX_4V;
+  defm VPMAXSB   : SS41I_binop_rm_int<0x3C, "vpmaxsb",   int_x86_sse41_pmaxsb,
+                                                         0>, VEX_4V;
+  defm VPMAXSD   : SS41I_binop_rm_int<0x3D, "vpmaxsd",   int_x86_sse41_pmaxsd,
+                                                         0>, VEX_4V;
+  defm VPMAXUD   : SS41I_binop_rm_int<0x3F, "vpmaxud",   int_x86_sse41_pmaxud,
+                                                         0>, VEX_4V;
+  defm VPMAXUW   : SS41I_binop_rm_int<0x3E, "vpmaxuw",   int_x86_sse41_pmaxuw,
+                                                         0>, VEX_4V;
+  defm VPMULDQ   : SS41I_binop_rm_int<0x28, "vpmuldq",   int_x86_sse41_pmuldq,
+                                                         0>, VEX_4V;
+}
+
 let Constraints = "$src1 = $dst" in {
   let isCommutable = 0 in
   defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s?rev=107558&r1=107557&r2=107558&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s Fri Jul  2 20:15:47 2010
@@ -11782,3 +11782,91 @@
 // CHECK: encoding: [0xc4,0xe2,0x79,0x41,0x10]
           vphminposuw  (%eax), %xmm2
 
+// CHECK: vpackusdw  %xmm2, %xmm3, %xmm1
+// CHECK: encoding: [0xc4,0xe2,0x61,0x2b,0xca]
+          vpackusdw  %xmm2, %xmm3, %xmm1
+
+// CHECK: vpackusdw  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x2b,0x18]
+          vpackusdw  (%eax), %xmm2, %xmm3
+
+// CHECK: vpcmpeqq  %xmm2, %xmm3, %xmm1
+// CHECK: encoding: [0xc4,0xe2,0x61,0x29,0xca]
+          vpcmpeqq  %xmm2, %xmm3, %xmm1
+
+// CHECK: vpcmpeqq  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x29,0x18]
+          vpcmpeqq  (%eax), %xmm2, %xmm3
+
+// CHECK: vpminsb  %xmm2, %xmm3, %xmm1
+// CHECK: encoding: [0xc4,0xe2,0x61,0x38,0xca]
+          vpminsb  %xmm2, %xmm3, %xmm1
+
+// CHECK: vpminsb  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x38,0x18]
+          vpminsb  (%eax), %xmm2, %xmm3
+
+// CHECK: vpminsd  %xmm2, %xmm3, %xmm1
+// CHECK: encoding: [0xc4,0xe2,0x61,0x39,0xca]
+          vpminsd  %xmm2, %xmm3, %xmm1
+
+// CHECK: vpminsd  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x39,0x18]
+          vpminsd  (%eax), %xmm2, %xmm3
+
+// CHECK: vpminud  %xmm2, %xmm3, %xmm1
+// CHECK: encoding: [0xc4,0xe2,0x61,0x3b,0xca]
+          vpminud  %xmm2, %xmm3, %xmm1
+
+// CHECK: vpminud  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x3b,0x18]
+          vpminud  (%eax), %xmm2, %xmm3
+
+// CHECK: vpminuw  %xmm2, %xmm3, %xmm1
+// CHECK: encoding: [0xc4,0xe2,0x61,0x3a,0xca]
+          vpminuw  %xmm2, %xmm3, %xmm1
+
+// CHECK: vpminuw  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x3a,0x18]
+          vpminuw  (%eax), %xmm2, %xmm3
+
+// CHECK: vpmaxsb  %xmm2, %xmm3, %xmm1
+// CHECK: encoding: [0xc4,0xe2,0x61,0x3c,0xca]
+          vpmaxsb  %xmm2, %xmm3, %xmm1
+
+// CHECK: vpmaxsb  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x3c,0x18]
+          vpmaxsb  (%eax), %xmm2, %xmm3
+
+// CHECK: vpmaxsd  %xmm2, %xmm3, %xmm1
+// CHECK: encoding: [0xc4,0xe2,0x61,0x3d,0xca]
+          vpmaxsd  %xmm2, %xmm3, %xmm1
+
+// CHECK: vpmaxsd  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x3d,0x18]
+          vpmaxsd  (%eax), %xmm2, %xmm3
+
+// CHECK: vpmaxud  %xmm2, %xmm3, %xmm1
+// CHECK: encoding: [0xc4,0xe2,0x61,0x3f,0xca]
+          vpmaxud  %xmm2, %xmm3, %xmm1
+
+// CHECK: vpmaxud  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x3f,0x18]
+          vpmaxud  (%eax), %xmm2, %xmm3
+
+// CHECK: vpmaxuw  %xmm2, %xmm3, %xmm1
+// CHECK: encoding: [0xc4,0xe2,0x61,0x3e,0xca]
+          vpmaxuw  %xmm2, %xmm3, %xmm1
+
+// CHECK: vpmaxuw  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x3e,0x18]
+          vpmaxuw  (%eax), %xmm2, %xmm3
+
+// CHECK: vpmuldq  %xmm2, %xmm3, %xmm1
+// CHECK: encoding: [0xc4,0xe2,0x61,0x28,0xca]
+          vpmuldq  %xmm2, %xmm3, %xmm1
+
+// CHECK: vpmuldq  (%eax), %xmm2, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x69,0x28,0x18]
+          vpmuldq  (%eax), %xmm2, %xmm3
+

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s?rev=107558&r1=107557&r2=107558&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s Fri Jul  2 20:15:47 2010
@@ -1830,3 +1830,91 @@
 // CHECK: encoding: [0xc4,0x62,0x79,0x41,0x20]
           vphminposuw  (%rax), %xmm12
 
+// CHECK: vpackusdw  %xmm12, %xmm13, %xmm11
+// CHECK: encoding: [0xc4,0x42,0x11,0x2b,0xdc]
+          vpackusdw  %xmm12, %xmm13, %xmm11
+
+// CHECK: vpackusdw  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x2b,0x28]
+          vpackusdw  (%rax), %xmm12, %xmm13
+
+// CHECK: vpcmpeqq  %xmm12, %xmm13, %xmm11
+// CHECK: encoding: [0xc4,0x42,0x11,0x29,0xdc]
+          vpcmpeqq  %xmm12, %xmm13, %xmm11
+
+// CHECK: vpcmpeqq  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x29,0x28]
+          vpcmpeqq  (%rax), %xmm12, %xmm13
+
+// CHECK: vpminsb  %xmm12, %xmm13, %xmm11
+// CHECK: encoding: [0xc4,0x42,0x11,0x38,0xdc]
+          vpminsb  %xmm12, %xmm13, %xmm11
+
+// CHECK: vpminsb  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x38,0x28]
+          vpminsb  (%rax), %xmm12, %xmm13
+
+// CHECK: vpminsd  %xmm12, %xmm13, %xmm11
+// CHECK: encoding: [0xc4,0x42,0x11,0x39,0xdc]
+          vpminsd  %xmm12, %xmm13, %xmm11
+
+// CHECK: vpminsd  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x39,0x28]
+          vpminsd  (%rax), %xmm12, %xmm13
+
+// CHECK: vpminud  %xmm12, %xmm13, %xmm11
+// CHECK: encoding: [0xc4,0x42,0x11,0x3b,0xdc]
+          vpminud  %xmm12, %xmm13, %xmm11
+
+// CHECK: vpminud  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x3b,0x28]
+          vpminud  (%rax), %xmm12, %xmm13
+
+// CHECK: vpminuw  %xmm12, %xmm13, %xmm11
+// CHECK: encoding: [0xc4,0x42,0x11,0x3a,0xdc]
+          vpminuw  %xmm12, %xmm13, %xmm11
+
+// CHECK: vpminuw  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x3a,0x28]
+          vpminuw  (%rax), %xmm12, %xmm13
+
+// CHECK: vpmaxsb  %xmm12, %xmm13, %xmm11
+// CHECK: encoding: [0xc4,0x42,0x11,0x3c,0xdc]
+          vpmaxsb  %xmm12, %xmm13, %xmm11
+
+// CHECK: vpmaxsb  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x3c,0x28]
+          vpmaxsb  (%rax), %xmm12, %xmm13
+
+// CHECK: vpmaxsd  %xmm12, %xmm13, %xmm11
+// CHECK: encoding: [0xc4,0x42,0x11,0x3d,0xdc]
+          vpmaxsd  %xmm12, %xmm13, %xmm11
+
+// CHECK: vpmaxsd  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x3d,0x28]
+          vpmaxsd  (%rax), %xmm12, %xmm13
+
+// CHECK: vpmaxud  %xmm12, %xmm13, %xmm11
+// CHECK: encoding: [0xc4,0x42,0x11,0x3f,0xdc]
+          vpmaxud  %xmm12, %xmm13, %xmm11
+
+// CHECK: vpmaxud  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x3f,0x28]
+          vpmaxud  (%rax), %xmm12, %xmm13
+
+// CHECK: vpmaxuw  %xmm12, %xmm13, %xmm11
+// CHECK: encoding: [0xc4,0x42,0x11,0x3e,0xdc]
+          vpmaxuw  %xmm12, %xmm13, %xmm11
+
+// CHECK: vpmaxuw  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x3e,0x28]
+          vpmaxuw  (%rax), %xmm12, %xmm13
+
+// CHECK: vpmuldq  %xmm12, %xmm13, %xmm11
+// CHECK: encoding: [0xc4,0x42,0x11,0x28,0xdc]
+          vpmuldq  %xmm12, %xmm13, %xmm11
+
+// CHECK: vpmuldq  (%rax), %xmm12, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x19,0x28,0x28]
+          vpmuldq  (%rax), %xmm12, %xmm13
+




From bruno.cardoso at gmail.com  Fri Jul  2 20:37:04 2010
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Sat, 03 Jul 2010 01:37:04 -0000
Subject: [llvm-commits] [llvm] r107560 - in /llvm/trunk:
 lib/Target/X86/X86InstrSSE.td test/MC/AsmParser/X86/x86_32-encoding.s
 test/MC/AsmParser/X86/x86_64-encoding.s
Message-ID: <20100703013704.2BC3E2A6C12C@llvm.org>

Author: bruno
Date: Fri Jul  2 20:37:03 2010
New Revision: 107560

URL: http://llvm.org/viewvc/llvm-project?rev=107560&view=rev
Log:
Add AVX SSE4.1 blend, mpsadbw and vdp

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
    llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=107560&r1=107559&r2=107560&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Fri Jul  2 20:37:03 2010
@@ -4190,6 +4190,8 @@
        OpSize;
 }
 
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in
+  defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, 0>, VEX_4V;
 let Constraints = "$src1 = $dst" in
   defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32>;
 
@@ -4220,6 +4222,23 @@
         OpSize;
 }
 
+let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in {
+  let isCommutable = 0 in {
+  defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
+                                                        0>, VEX_4V;
+  defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
+                                                        0>, VEX_4V;
+  defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
+                                                        0>, VEX_4V;
+  defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
+                                                        0>, VEX_4V;
+  }
+  defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
+                                                        0>, VEX_4V;
+  defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
+                                                        0>, VEX_4V;
+}
+
 let Constraints = "$src1 = $dst" in {
   let isCommutable = 0 in {
   defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps>;

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s?rev=107560&r1=107559&r2=107560&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s Fri Jul  2 20:37:03 2010
@@ -11870,3 +11870,60 @@
 // CHECK: encoding: [0xc4,0xe2,0x69,0x28,0x18]
           vpmuldq  (%eax), %xmm2, %xmm3
 
+// CHECK: vpmulld  %xmm2, %xmm5, %xmm1
+// CHECK: encoding: [0xc4,0xe2,0x51,0x40,0xca]
+          vpmulld  %xmm2, %xmm5, %xmm1
+
+// CHECK: vpmulld  (%eax), %xmm5, %xmm3
+// CHECK: encoding: [0xc4,0xe2,0x51,0x40,0x18]
+          vpmulld  (%eax), %xmm5, %xmm3
+
+// CHECK: vblendps  $3, %xmm2, %xmm5, %xmm1
+// CHECK: encoding: [0xc4,0xe3,0x51,0x0c,0xca,0x03]
+          vblendps  $3, %xmm2, %xmm5, %xmm1
+
+// CHECK: vblendps  $3, (%eax), %xmm5, %xmm1
+// CHECK: encoding: [0xc4,0xe3,0x51,0x0c,0x08,0x03]
+          vblendps  $3, (%eax), %xmm5, %xmm1
+
+// CHECK: vblendpd  $3, %xmm2, %xmm5, %xmm1
+// CHECK: encoding: [0xc4,0xe3,0x51,0x0d,0xca,0x03]
+          vblendpd  $3, %xmm2, %xmm5, %xmm1
+
+// CHECK: vblendpd  $3, (%eax), %xmm5, %xmm1
+// CHECK: encoding: [0xc4,0xe3,0x51,0x0d,0x08,0x03]
+          vblendpd  $3, (%eax), %xmm5, %xmm1
+
+// CHECK: vpblendw  $3, %xmm2, %xmm5, %xmm1
+// CHECK: encoding: [0xc4,0xe3,0x51,0x0e,0xca,0x03]
+          vpblendw  $3, %xmm2, %xmm5, %xmm1
+
+// CHECK: vpblendw  $3, (%eax), %xmm5, %xmm1
+// CHECK: encoding: [0xc4,0xe3,0x51,0x0e,0x08,0x03]
+          vpblendw  $3, (%eax), %xmm5, %xmm1
+
+// CHECK: vmpsadbw  $3, %xmm2, %xmm5, %xmm1
+// CHECK: encoding: [0xc4,0xe3,0x51,0x42,0xca,0x03]
+          vmpsadbw  $3, %xmm2, %xmm5, %xmm1
+
+// CHECK: vmpsadbw  $3, (%eax), %xmm5, %xmm1
+// CHECK: encoding: [0xc4,0xe3,0x51,0x42,0x08,0x03]
+          vmpsadbw  $3, (%eax), %xmm5, %xmm1
+
+// CHECK: vdpps  $3, %xmm2, %xmm5, %xmm1
+// CHECK: encoding: [0xc4,0xe3,0x51,0x40,0xca,0x03]
+          vdpps  $3, %xmm2, %xmm5, %xmm1
+
+// CHECK: vdpps  $3, (%eax), %xmm5, %xmm1
+// CHECK: encoding: [0xc4,0xe3,0x51,0x40,0x08,0x03]
+          vdpps  $3, (%eax), %xmm5, %xmm1
+
+// CHECK: vdppd  $3, %xmm2, %xmm5, %xmm1
+// CHECK: encoding: [0xc4,0xe3,0x51,0x41,0xca,0x03]
+          vdppd  $3, %xmm2, %xmm5, %xmm1
+
+// CHECK: vdppd  $3, (%eax), %xmm5, %xmm1
+// CHECK: encoding: [0xc4,0xe3,0x51,0x41,0x08,0x03]
+          vdppd  $3, (%eax), %xmm5, %xmm1
+
+

Modified: llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s?rev=107560&r1=107559&r2=107560&view=diff
==============================================================================
--- llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s (original)
+++ llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s Fri Jul  2 20:37:03 2010
@@ -1918,3 +1918,59 @@
 // CHECK: encoding: [0xc4,0x62,0x19,0x28,0x28]
           vpmuldq  (%rax), %xmm12, %xmm13
 
+// CHECK: vpmulld  %xmm12, %xmm5, %xmm11
+// CHECK: encoding: [0xc4,0x42,0x51,0x40,0xdc]
+          vpmulld  %xmm12, %xmm5, %xmm11
+
+// CHECK: vpmulld  (%rax), %xmm5, %xmm13
+// CHECK: encoding: [0xc4,0x62,0x51,0x40,0x28]
+          vpmulld  (%rax), %xmm5, %xmm13
+
+// CHECK: vblendps  $3, %xmm12, %xmm5, %xmm11
+// CHECK: encoding: [0xc4,0x43,0x51,0x0c,0xdc,0x03]
+          vblendps  $3, %xmm12, %xmm5, %xmm11
+
+// CHECK: vblendps  $3, (%rax), %xmm5, %xmm11
+// CHECK: encoding: [0xc4,0x63,0x51,0x0c,0x18,0x03]
+          vblendps  $3, (%rax), %xmm5, %xmm11
+
+// CHECK: vblendpd  $3, %xmm12, %xmm5, %xmm11
+// CHECK: encoding: [0xc4,0x43,0x51,0x0d,0xdc,0x03]
+          vblendpd  $3, %xmm12, %xmm5, %xmm11
+
+// CHECK: vblendpd  $3, (%rax), %xmm5, %xmm11
+// CHECK: encoding: [0xc4,0x63,0x51,0x0d,0x18,0x03]
+          vblendpd  $3, (%rax), %xmm5, %xmm11
+
+// CHECK: vpblendw  $3, %xmm12, %xmm5, %xmm11
+// CHECK: encoding: [0xc4,0x43,0x51,0x0e,0xdc,0x03]
+          vpblendw  $3, %xmm12, %xmm5, %xmm11
+
+// CHECK: vpblendw  $3, (%rax), %xmm5, %xmm11
+// CHECK: encoding: [0xc4,0x63,0x51,0x0e,0x18,0x03]
+          vpblendw  $3, (%rax), %xmm5, %xmm11
+
+// CHECK: vmpsadbw  $3, %xmm12, %xmm5, %xmm11
+// CHECK: encoding: [0xc4,0x43,0x51,0x42,0xdc,0x03]
+          vmpsadbw  $3, %xmm12, %xmm5, %xmm11
+
+// CHECK: vmpsadbw  $3, (%rax), %xmm5, %xmm11
+// CHECK: encoding: [0xc4,0x63,0x51,0x42,0x18,0x03]
+          vmpsadbw  $3, (%rax), %xmm5, %xmm11
+
+// CHECK: vdpps  $3, %xmm12, %xmm5, %xmm11
+// CHECK: encoding: [0xc4,0x43,0x51,0x40,0xdc,0x03]
+          vdpps  $3, %xmm12, %xmm5, %xmm11
+
+// CHECK: vdpps  $3, (%rax), %xmm5, %xmm11
+// CHECK: encoding: [0xc4,0x63,0x51,0x40,0x18,0x03]
+          vdpps  $3, (%rax), %xmm5, %xmm11
+
+// CHECK: vdppd  $3, %xmm12, %xmm5, %xmm11
+// CHECK: encoding: [0xc4,0x43,0x51,0x41,0xdc,0x03]
+          vdppd  $3, %xmm12, %xmm5, %xmm11
+
+// CHECK: vdppd  $3, (%rax), %xmm5, %xmm11
+// CHECK: encoding: [0xc4,0x63,0x51,0x41,0x18,0x03]
+          vdppd  $3, (%rax), %xmm5, %xmm11
+




From dalej at apple.com  Fri Jul  2 21:46:24 2010
From: dalej at apple.com (Dale Johannesen)
Date: Fri, 2 Jul 2010 19:46:24 -0700
Subject: [llvm-commits] [llvm] r107114 -
	/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
In-Reply-To: <A09A1B14-CBF7-4203-AF81-FFAD0E86BEBC@2pi.dk>
References: <20100629011307.645212A6C12C@llvm.org>
	<04D10EF1-91D9-44D6-9161-161B70493ED7@apple.com>
	<5F342D90-DC02-47A6-A825-EAD20CBFA547@2pi.dk>
	<0BC7E25D-4488-4954-A149-0D27BF55BBAE@apple.com>
	<58535D1C-837D-4136-A1D6-9809389E70F3@2pi.dk>
	<0F336F91-F80B-425F-B3AD-DCFAB44E6F16@apple.com>
	<8790C1B7-44AF-446B-AFAE-563E00DFD3C6@apple.com>
	<A09A1B14-CBF7-4203-AF81-FFAD0E86BEBC@2pi.dk>
Message-ID: <95705F15-DBC8-40AB-8FCC-17072012F09E@apple.com>


On Jul 2, 2010, at 5:54 PM, Evan Cheng wrote:

> I've looked into this. The main issue is when the register allocator  
> folded reloads from fixed slots the loads ended up with alignment 1.  
> That's because by default all fixed slots have alignment of 1. This  
> is overly conservative. DAG combiner will infer the correct  
> alignments from stack pointer alignments and frame offset. But at  
> register allocation time we are simply taking the frame object's  
> alignments.
>
> I think the right fix is to make sure the fixed objects have the  
> inferred alignments when they are created. Does anyone see a problem  
> with that?

Seems right in theory.  I bet doing this will expose bugs elsewhere,  
though.



From eli.friedman at gmail.com  Sat Jul  3 02:38:13 2010
From: eli.friedman at gmail.com (Eli Friedman)
Date: Sat, 03 Jul 2010 07:38:13 -0000
Subject: [llvm-commits] [llvm] r107565 - /llvm/trunk/lib/Target/README.txt
Message-ID: <20100703073813.284FB2A6C12D@llvm.org>

Author: efriedma
Date: Sat Jul  3 02:38:12 2010
New Revision: 107565

URL: http://llvm.org/viewvc/llvm-project?rev=107565&view=rev
Log:
Note switch-lowering inefficiency.


Modified:
    llvm/trunk/lib/Target/README.txt

Modified: llvm/trunk/lib/Target/README.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/README.txt?rev=107565&r1=107564&r2=107565&view=diff
==============================================================================
--- llvm/trunk/lib/Target/README.txt (original)
+++ llvm/trunk/lib/Target/README.txt Sat Jul  3 02:38:12 2010
@@ -1888,3 +1888,39 @@
 (That said, we are doing a lot better than gcc on this testcase. :) )
 
 //===---------------------------------------------------------------------===//
+
+Switch lowering generates less than ideal code for the following switch:
+define void @a(i32 %x) nounwind {
+entry:
+  switch i32 %x, label %if.end [
+    i32 0, label %if.then
+    i32 1, label %if.then
+    i32 2, label %if.then
+    i32 3, label %if.then
+    i32 5, label %if.then
+  ]
+if.then:
+  tail call void @foo() nounwind
+  ret void
+if.end:
+  ret void
+}
+declare void @foo()
+
+Generated code on x86-64 (other platforms give similar results):
+a:
+	cmpl	$5, %edi
+	ja	.LBB0_2
+	movl	%edi, %eax
+	movl	$47, %ecx
+	btq	%rax, %rcx
+	jb	.LBB0_3
+.LBB0_2:
+	ret
+.LBB0_3:
+	xorb	%al, %al
+	jmp	foo at PLT  # TAILCALL
+
+The movl+movl+btq+jb could be simplified to a cmpl+jne.
+
+//===---------------------------------------------------------------------===//




From eli.friedman at gmail.com  Sat Jul  3 03:43:32 2010
From: eli.friedman at gmail.com (Eli Friedman)
Date: Sat, 03 Jul 2010 08:43:32 -0000
Subject: [llvm-commits] [llvm] r107569 - /llvm/trunk/lib/Target/README.txt
Message-ID: <20100703084332.E3FD62A6C12C@llvm.org>

Author: efriedma
Date: Sat Jul  3 03:43:32 2010
New Revision: 107569

URL: http://llvm.org/viewvc/llvm-project?rev=107569&view=rev
Log:
Minor amendment to switch-lowering improvement.


Modified:
    llvm/trunk/lib/Target/README.txt

Modified: llvm/trunk/lib/Target/README.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/README.txt?rev=107569&r1=107568&r2=107569&view=diff
==============================================================================
--- llvm/trunk/lib/Target/README.txt (original)
+++ llvm/trunk/lib/Target/README.txt Sat Jul  3 03:43:32 2010
@@ -1918,9 +1918,17 @@
 .LBB0_2:
 	ret
 .LBB0_3:
-	xorb	%al, %al
-	jmp	foo at PLT  # TAILCALL
+	jmp	foo  # TAILCALL
 
 The movl+movl+btq+jb could be simplified to a cmpl+jne.
 
+Or, if we wanted to be really clever, we could simplify the whole thing to
+something like the following, which eliminates a branch:
+	xorl    $1, %edi
+	cmpl	$4, %edi
+	ja	.LBB0_2
+	ret
+.LBB0_2:
+	jmp	foo  # TAILCALL
+
 //===---------------------------------------------------------------------===//




From anton at korobeynikov.info  Sat Jul  3 04:39:45 2010
From: anton at korobeynikov.info (Anton Korobeynikov)
Date: Sat, 3 Jul 2010 13:39:45 +0400
Subject: [llvm-commits] [llvm] r107565 -
	/llvm/trunk/lib/Target/README.txt
In-Reply-To: <20100703073813.284FB2A6C12D@llvm.org>
References: <20100703073813.284FB2A6C12D@llvm.org>
Message-ID: <AANLkTinXxJN-lxYwoToe5MjkinblrxeylfxFl5BAO6vr@mail.gmail.com>

> +The movl+movl+btq+jb could be simplified to a cmpl+jne.
This sounds like a missed DAG combiner opportunity: switch lowering
produces 'and' with a mask and then jump if the result is not zero.
When the mask is 2^N-1 -2^M this should be simplified as stated.

-- 
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University


From baldrick at free.fr  Sat Jul  3 05:05:42 2010
From: baldrick at free.fr (Duncan Sands)
Date: Sat, 03 Jul 2010 12:05:42 +0200
Subject: [llvm-commits] [llvm] r107546 - in /llvm/trunk:
 docs/AliasAnalysis.html include/llvm/Analysis/Passes.h
In-Reply-To: <20100702235236.EA48F2A6C12C@llvm.org>
References: <20100702235236.EA48F2A6C12C@llvm.org>
Message-ID: <4C2F0B76.2000807@free.fr>

Hi Dan,

>     // createBasicAliasAnalysisPass - This pass implements the default alias
> -  // analysis.
> +  // analysis.  This analysis respects the noalias attribute, so it is not
> +  // suitable for some interprocedural uses (see the discussion of noalias
> +  // in AliasAnalysis.html for details).

this sounds more like a bug than a feature.  If BasicAliasAnalysis can return
wrong results, shouldn't it be fixed?

Ciao,

Duncan.


From baldrick at free.fr  Sat Jul  3 07:37:40 2010
From: baldrick at free.fr (Duncan Sands)
Date: Sat, 03 Jul 2010 12:37:40 -0000
Subject: [llvm-commits] [dragonegg] r107571 -
	/dragonegg/trunk/llvm-backend.cpp
Message-ID: <20100703123740.444732A6C12C@llvm.org>

Author: baldrick
Date: Sat Jul  3 07:37:40 2010
New Revision: 107571

URL: http://llvm.org/viewvc/llvm-project?rev=107571&view=rev
Log:
There seems to be some interest in being able to run all GCC
optimizations before outputting LLVM IR.  While dragonegg has
a flag (-fplugin-arg-dragonegg-enable-gcc-optzns) that turns
GCC optimizations on, it is not very effective because gimple
to LLVM conversion occurs quite early, before most GCC passes
have run.  Make it more effective by delaying gimple to IR
conversion till after all tree optimizers have run if the user
has specified -fplugin-arg-dragonegg-enable-gcc-optzns.  This
works, but currently not that well because the gcc optimizers
introduce some funky new nodes that aren't currently handled
(not to mention that they sometimes create what seems to be
invalid gimple).

Modified:
    dragonegg/trunk/llvm-backend.cpp

Modified: dragonegg/trunk/llvm-backend.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/llvm-backend.cpp?rev=107571&r1=107570&r2=107571&view=diff
==============================================================================
--- dragonegg/trunk/llvm-backend.cpp (original)
+++ dragonegg/trunk/llvm-backend.cpp Sat Jul  3 07:37:40 2010
@@ -1583,23 +1583,11 @@
   return !errorcount && !sorrycount; // Do not process broken code.
 }
 
-/// emit_function - Turn a gimple function into LLVM IR.  This is called once
-/// for each function in the compilation unit.
-static void emit_function(struct cgraph_node *node) {
-  if (errorcount || sorrycount)
-    return; // Do not process broken code.
-
-  tree function = node->decl;
-  struct function *fn = DECL_STRUCT_FUNCTION(function);
-  if (!quiet_flag && DECL_NAME(function))
-    errs() << IDENTIFIER_POINTER(DECL_NAME(function));
-
-  // Set the current function to this one.
-  // TODO: Make it so we don't need to do this.
-  assert(current_function_decl == NULL_TREE && cfun == NULL &&
-         "Current function already set!");
-  current_function_decl = function;
-  push_cfun (fn);
+/// emit_current_function - Turn the current gimple function into LLVM IR.  This
+/// is called once for each function in the compilation unit.
+static void emit_current_function() {
+  if (!quiet_flag && DECL_NAME(current_function_decl))
+    errs() << IDENTIFIER_POINTER(DECL_NAME(current_function_decl));
 
   // Convert the AST to raw/ugly LLVM code.
   Function *Fn;
@@ -1617,6 +1605,26 @@
     // TODO: Nuke the .ll code for the function at -O[01] if we don't want to
     // inline it or something else.
   }
+}
+
+/// emit_function - Turn a gimple function into LLVM IR.  This is called once
+/// for each function in the compilation unit if GCC optimizations are disabled.
+static void emit_function(struct cgraph_node *node) {
+  if (errorcount || sorrycount)
+    return; // Do not process broken code.
+
+  tree function = node->decl;
+  struct function *fn = DECL_STRUCT_FUNCTION(function);
+
+  // Set the current function to this one.
+  // TODO: Make it so we don't need to do this.
+  assert(current_function_decl == NULL_TREE && cfun == NULL &&
+         "Current function already set!");
+  current_function_decl = function;
+  push_cfun (fn);
+
+  // Convert the function.
+  emit_current_function();
 
   // Done with this function.
   current_function_decl = NULL;
@@ -1898,7 +1906,10 @@
        csi_next(&csi)) {
     struct cgraph_node *node = csi_node(csi);
     if (node->analyzed && Visited.insert(node->decl))
-      emit_function(node);
+      // If GCC optimizations are enabled then functions are output later, in
+      // place of gimple to RTL conversion.
+      if (!EnableGCCOptimizations)
+        emit_function(node);
 
     // Output any same-body aliases or thunks in the order they were created.
     struct cgraph_node *alias, *next;
@@ -2046,6 +2057,45 @@
     }
 };
 
+/// rtl_emit_function - Turn a gimple function into LLVM IR.  This is called
+/// once for each function in the compilation unit if GCC optimizations are
+/// enabled.
+static unsigned int rtl_emit_function (void) {
+  InitializeBackend();
+
+  // Convert the function.
+  emit_current_function();
+
+  // Free any data structures.
+  execute_free_datastructures();
+
+  // Finally, we have written out this function!
+  TREE_ASM_WRITTEN(current_function_decl) = 1;
+  return 0;
+}
+
+/// pass_rtl_emit_function - RTL pass that converts a function to LLVM IR.
+static struct rtl_opt_pass pass_rtl_emit_function =
+{
+    {
+      RTL_PASS,
+      "rtl_emit_function",	/* name */
+      gate_emission,		/* gate */
+      rtl_emit_function,	/* execute */
+      NULL,			/* sub */
+      NULL,			/* next */
+      0,			/* static_pass_number */
+      TV_NONE,			/* tv_id */
+      PROP_ssa | PROP_gimple_leh | PROP_gimple_lomp
+        | PROP_cfg,		/* properties_required */
+      0,			/* properties_provided */
+      PROP_ssa | PROP_trees,	/* properties_destroyed */
+      TODO_verify_ssa | TODO_verify_flow
+        | TODO_verify_stmts,	/* todo_flags_start */
+      TODO_ggc_collect		/* todo_flags_finish */
+    }
+};
+
 
 /// llvm_finish - Run shutdown code when GCC exits.
 static void llvm_finish(void *gcc_data, void *user_data) {
@@ -2519,13 +2569,17 @@
     register_callback (plugin_name, PLUGIN_PASS_MANAGER_SETUP, NULL, &pass_info);
   }
 
-  // Replace LTO generation with gimple to LLVM conversion.
+  // Replace the LTO gimple pass.  If GCC optimizations are disabled then this
+  // is where functions are converted to LLVM IR.  When GCC optimizations are
+  // enabled then only aliases and thunks are output here, with functions being
+  // converted later after all tree optimizers have run.
   pass_info.pass = &pass_emit_functions.pass;
   pass_info.reference_pass_name = "lto_gimple_out";
   pass_info.ref_pass_instance_number = 0;
   pass_info.pos_op = PASS_POS_REPLACE;
   register_callback (plugin_name, PLUGIN_PASS_MANAGER_SETUP, NULL, &pass_info);
 
+  // Replace the LTO decls pass with conversion of global variables to LLVM IR.
   pass_info.pass = &pass_emit_variables.pass;
   pass_info.reference_pass_name = "lto_decls_out";
   pass_info.ref_pass_instance_number = 0;
@@ -2541,79 +2595,85 @@
   register_callback (plugin_name, PLUGIN_PASS_MANAGER_SETUP, NULL, &pass_info);
 #endif
 
-  // Disable pass_lower_eh_dispatch, which runs after LLVM conversion.
-  pass_info.pass = &pass_gimple_null.pass;
-  pass_info.reference_pass_name = "ehdisp";
-  pass_info.ref_pass_instance_number = 0;
-  pass_info.pos_op = PASS_POS_REPLACE;
-  register_callback (plugin_name, PLUGIN_PASS_MANAGER_SETUP, NULL, &pass_info);
+  if (!EnableGCCOptimizations) {
+    // Disable pass_lower_eh_dispatch, which runs after LLVM conversion.
+    pass_info.pass = &pass_gimple_null.pass;
+    pass_info.reference_pass_name = "ehdisp";
+    pass_info.ref_pass_instance_number = 0;
+    pass_info.pos_op = PASS_POS_REPLACE;
+    register_callback (plugin_name, PLUGIN_PASS_MANAGER_SETUP, NULL, &pass_info);
 
-  // Disable pass_all_optimizations, which runs after LLVM conversion.
-  pass_info.pass = &pass_gimple_null.pass;
-  pass_info.reference_pass_name = "*all_optimizations";
-  pass_info.ref_pass_instance_number = 0;
-  pass_info.pos_op = PASS_POS_REPLACE;
-  register_callback (plugin_name, PLUGIN_PASS_MANAGER_SETUP, NULL, &pass_info);
+    // Disable pass_all_optimizations, which runs after LLVM conversion.
+    pass_info.pass = &pass_gimple_null.pass;
+    pass_info.reference_pass_name = "*all_optimizations";
+    pass_info.ref_pass_instance_number = 0;
+    pass_info.pos_op = PASS_POS_REPLACE;
+    register_callback (plugin_name, PLUGIN_PASS_MANAGER_SETUP, NULL, &pass_info);
 
-  // Disable pass_lower_complex_O0, which runs after LLVM conversion.
-  pass_info.pass = &pass_gimple_null.pass;
-  pass_info.reference_pass_name = "cplxlower0";
-  pass_info.ref_pass_instance_number = 0;
-  pass_info.pos_op = PASS_POS_REPLACE;
-  register_callback (plugin_name, PLUGIN_PASS_MANAGER_SETUP, NULL, &pass_info);
+    // Disable pass_lower_complex_O0, which runs after LLVM conversion.
+    pass_info.pass = &pass_gimple_null.pass;
+    pass_info.reference_pass_name = "cplxlower0";
+    pass_info.ref_pass_instance_number = 0;
+    pass_info.pos_op = PASS_POS_REPLACE;
+    register_callback (plugin_name, PLUGIN_PASS_MANAGER_SETUP, NULL, &pass_info);
 
-  // Disable pass_cleanup_eh, which runs after LLVM conversion.
-  // This pass is scheduled twice, once before LLVM conversion and once after.
-  // If GCC optimizations are enabled, then we should keep the first instance
-  // and only disable the second.  There does not seem to be a good way to do
-  // this, so just allow both instances to run in this case.
-  if (!EnableGCCOptimizations) {
+    // Disable pass_cleanup_eh, which runs after LLVM conversion.
     pass_info.pass = &pass_gimple_null.pass;
     pass_info.reference_pass_name = "ehcleanup";
     pass_info.ref_pass_instance_number = 0;
     pass_info.pos_op = PASS_POS_REPLACE;
     register_callback (plugin_name, PLUGIN_PASS_MANAGER_SETUP, NULL, &pass_info);
-  }
 
-  // Disable pass_lower_resx, which runs after LLVM conversion.
-  pass_info.pass = &pass_gimple_null.pass;
-  pass_info.reference_pass_name = "resx";
-  pass_info.ref_pass_instance_number = 0;
-  pass_info.pos_op = PASS_POS_REPLACE;
-  register_callback (plugin_name, PLUGIN_PASS_MANAGER_SETUP, NULL, &pass_info);
+    // Disable pass_lower_resx, which runs after LLVM conversion.
+    pass_info.pass = &pass_gimple_null.pass;
+    pass_info.reference_pass_name = "resx";
+    pass_info.ref_pass_instance_number = 0;
+    pass_info.pos_op = PASS_POS_REPLACE;
+    register_callback (plugin_name, PLUGIN_PASS_MANAGER_SETUP, NULL, &pass_info);
 
-  // Disable pass_nrv, which runs after LLVM conversion.
-  pass_info.pass = &pass_gimple_null.pass;
-  pass_info.reference_pass_name = "nrv";
-  pass_info.ref_pass_instance_number = 0;
-  pass_info.pos_op = PASS_POS_REPLACE;
-  register_callback (plugin_name, PLUGIN_PASS_MANAGER_SETUP, NULL, &pass_info);
+    // Disable pass_nrv, which runs after LLVM conversion.
+    pass_info.pass = &pass_gimple_null.pass;
+    pass_info.reference_pass_name = "nrv";
+    pass_info.ref_pass_instance_number = 0;
+    pass_info.pos_op = PASS_POS_REPLACE;
+    register_callback (plugin_name, PLUGIN_PASS_MANAGER_SETUP, NULL, &pass_info);
 
-  // Disable pass_mudflap_2, which runs after LLVM conversion.
-  pass_info.pass = &pass_gimple_null.pass;
-  pass_info.reference_pass_name = "mudflap2";
-  pass_info.ref_pass_instance_number = 0;
-  pass_info.pos_op = PASS_POS_REPLACE;
-  register_callback (plugin_name, PLUGIN_PASS_MANAGER_SETUP, NULL, &pass_info);
+    // Disable pass_mudflap_2, which runs after LLVM conversion.
+    pass_info.pass = &pass_gimple_null.pass;
+    pass_info.reference_pass_name = "mudflap2";
+    pass_info.ref_pass_instance_number = 0;
+    pass_info.pos_op = PASS_POS_REPLACE;
+    register_callback (plugin_name, PLUGIN_PASS_MANAGER_SETUP, NULL, &pass_info);
 
-  // Disable pass_cleanup_cfg_post_optimizing, which runs after LLVM conversion.
-  pass_info.pass = &pass_gimple_null.pass;
-  pass_info.reference_pass_name = "optimized";
-  pass_info.ref_pass_instance_number = 0;
-  pass_info.pos_op = PASS_POS_REPLACE;
-  register_callback (plugin_name, PLUGIN_PASS_MANAGER_SETUP, NULL, &pass_info);
+    // Disable pass_cleanup_cfg_post_optimizing, which runs after LLVM conversion.
+    pass_info.pass = &pass_gimple_null.pass;
+    pass_info.reference_pass_name = "optimized";
+    pass_info.ref_pass_instance_number = 0;
+    pass_info.pos_op = PASS_POS_REPLACE;
+    register_callback (plugin_name, PLUGIN_PASS_MANAGER_SETUP, NULL, &pass_info);
 
-  // TODO: Disable pass_warn_function_noreturn?
+    // TODO: Disable pass_warn_function_noreturn?
+  }
 
-  // Replace rtl expansion with a pass that pretends to codegen functions, but
-  // actually only does the hoop jumping that GCC requires at this point.
-  pass_info.pass = &pass_disable_rtl.pass;
-  pass_info.reference_pass_name = "expand";
-  pass_info.ref_pass_instance_number = 0;
-  pass_info.pos_op = PASS_POS_REPLACE;
-  register_callback (plugin_name, PLUGIN_PASS_MANAGER_SETUP, NULL, &pass_info);
+  // Replace rtl expansion.
+  if (!EnableGCCOptimizations) {
+    // Replace rtl expansion with a pass that pretends to codegen functions, but
+    // actually only does the hoop jumping that GCC requires at this point.
+    pass_info.pass = &pass_disable_rtl.pass;
+    pass_info.reference_pass_name = "expand";
+    pass_info.ref_pass_instance_number = 0;
+    pass_info.pos_op = PASS_POS_REPLACE;
+    register_callback (plugin_name, PLUGIN_PASS_MANAGER_SETUP, NULL, &pass_info);
+  } else {
+    // Replace rtl expansion with a pass that converts functions to LLVM IR.
+    pass_info.pass = &pass_rtl_emit_function.pass;
+    pass_info.reference_pass_name = "expand";
+    pass_info.ref_pass_instance_number = 0;
+    pass_info.pos_op = PASS_POS_REPLACE;
+    register_callback (plugin_name, PLUGIN_PASS_MANAGER_SETUP, NULL, &pass_info);
+  }
 
-  // Turn off all rtl passes.
+  // Turn off all other rtl passes.
   pass_info.pass = &pass_gimple_null.pass;
   pass_info.reference_pass_name = "*rest_of_compilation";
   pass_info.ref_pass_instance_number = 0;




From john at bass-software.com  Sat Jul  3 08:28:23 2010
From: john at bass-software.com (John Tytgat)
Date: Sat, 03 Jul 2010 14:28:23 +0100
Subject: [llvm-commits] [compiler-rt] r107555 - in
	/compiler-rt/trunk/lib/arm: bswapdi2.S bswapsi2.S
In-Reply-To: <20100703010049.D01E92A6C12C@llvm.org>
References: <20100703010049.D01E92A6C12C@llvm.org>
Message-ID: <89720c3151.Jo@hobbes.bass-software.com>

In message <20100703010049.D01E92A6C12C at llvm.org>
          Stephen Canon <scanon at apple.com> wrote:

> Author: scanon
> Date: Fri Jul  2 20:00:49 2010
> New Revision: 107555
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=107555&view=rev
> Log:
> Marginally smaller implementations of bswap for ARMv4, ARMv5 that avoid the need to establish a frame
> 
> Modified:
>     compiler-rt/trunk/lib/arm/bswapdi2.S
>     compiler-rt/trunk/lib/arm/bswapsi2.S

This can be further optimised using a well known endian swap 4 instruction
idiom.  Patch attached.

John.
-- 
John Tytgat
John at bass-software.com
-------------- next part --------------
Index: bswapdi2.S
===================================================================
--- bswapdi2.S	(revision 107570)
+++ bswapdi2.S	(working copy)
@@ -14,25 +14,23 @@
 //
 // Reverse all the bytes in a 64-bit integer.
 //
-    .align 2
+	.align 2
 DEFINE_COMPILERRT_FUNCTION(__bswapdi2)
 #if __ARM_ARCH_5TEJ__ || __ARM_ARCH_4T__
-    mov r12, #0xff00
-    
-    and r3,  r12, r0, lsr #8
-    and r2,  r12, r0    
-    orr r3,   r3, r0, lsr #24   
-    orr r3,   r3, r0, lsl #24
-    orr r2,   r3, r2, lsl #8  // r2 = rev(r0)
-    
-    and r3,  r12, r1, lsr #8
-    and r0,  r12, r1
-    orr r3,   r3, r1, lsr #24
-    orr r3,   r3, r1, lsl #24
-    orr r0,   r3, r0, lsl #8  // r0 = rev(r1)
+	eor	r2, r0, r0, ror #16
+	bic	r2, r2, #0xff0000
+	mov	r2, r2, lsr #8
+	eor	r2, r2, r0, ror #8
+
+	eor	r0, r1, r1, ror #16
+	bic	r0, r0, #0xff0000
+	mov	r0, r0, lsr #8
+	eor	r0, r0, r1, ror #8
+
+	mov	r1, r2
 #else
-    rev r2,   r0  // r2 = rev(r0)
-    rev r0,   r1  // r0 = rev(r1)
+	rev r2,   r0  // r2 = rev(r0)
+	rev r0,   r1  // r0 = rev(r1)
 #endif
-    mov r1,   r2  // r1 = r2 = rev(r0)
-    bx  lr
+	mov r1,   r2  // r1 = r2 = rev(r0)
+	bx  lr
Index: bswapsi2.S
===================================================================
--- bswapsi2.S	(revision 107570)
+++ bswapsi2.S	(working copy)
@@ -18,12 +18,10 @@
 DEFINE_COMPILERRT_FUNCTION(__bswapsi2)
 #if __ARM_ARCH_5TEJ__ || __ARM_ARCH_4T__
 	// before armv6 does not have "rev" instruction
-    mov r1, #0xff00
-    and r2, r1, r0, lsr #8 
-    and r1, r1, r0   
-    orr r2, r2, r0, lsr #24
-    orr r2, r2, r0, lsl #24
-    orr r0, r2, r1, lsl #8
+	eor	r1, r0, r0, ror #16
+	bic	r1, r1, #0xff0000
+	mov	r1, r1, lsr #8
+	eor	r0, r1, r0, ror #8
 #else
 	rev	r0, r0		// reverse bytes in parameter and put into result register
 #endif

From eli.friedman at gmail.com  Sat Jul  3 10:33:36 2010
From: eli.friedman at gmail.com (Eli Friedman)
Date: Sat, 3 Jul 2010 08:33:36 -0700
Subject: [llvm-commits] [llvm] r107565 -
	/llvm/trunk/lib/Target/README.txt
In-Reply-To: <AANLkTinXxJN-lxYwoToe5MjkinblrxeylfxFl5BAO6vr@mail.gmail.com>
References: <20100703073813.284FB2A6C12D@llvm.org>
	<AANLkTinXxJN-lxYwoToe5MjkinblrxeylfxFl5BAO6vr@mail.gmail.com>
Message-ID: <AANLkTingZ1mkvK3T8CtOAJ8PX17URImqdYXPHreVJbjR@mail.gmail.com>

On Sat, Jul 3, 2010 at 2:39 AM, Anton Korobeynikov
<anton at korobeynikov.info> wrote:
>> +The movl+movl+btq+jb could be simplified to a cmpl+jne.
> This sounds like a missed DAG combiner opportunity: switch lowering
> produces 'and' with a mask and then jump if the result is not zero.
> When the mask is 2^N-1 -2^M this should be simplified as stated.

The DAG combiner doesn't have the sort of knowledge necessary: the
optimization is only safe because of the earlier branch.  In
isolation, the btq branches one way if EDI is 0, 1, 2, 3, or 5, and
the other way if it is some other number less than 64.

-Eli


From scanon at apple.com  Sat Jul  3 16:47:51 2010
From: scanon at apple.com (Stephen Canon)
Date: Sat, 03 Jul 2010 21:47:51 -0000
Subject: [llvm-commits] [compiler-rt] r107576 - in
	/compiler-rt/trunk/lib/arm: bswapdi2.S bswapsi2.S
Message-ID: <20100703214751.2B7FF2A6C12C@llvm.org>

Author: scanon
Date: Sat Jul  3 16:47:50 2010
New Revision: 107576

URL: http://llvm.org/viewvc/llvm-project?rev=107576&view=rev
Log:
Further cleanup of ARM bswap implementations, thanks to John Tytgat

Modified:
    compiler-rt/trunk/lib/arm/bswapdi2.S
    compiler-rt/trunk/lib/arm/bswapsi2.S

Modified: compiler-rt/trunk/lib/arm/bswapdi2.S
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/bswapdi2.S?rev=107576&r1=107575&r2=107576&view=diff
==============================================================================
--- compiler-rt/trunk/lib/arm/bswapdi2.S (original)
+++ compiler-rt/trunk/lib/arm/bswapdi2.S Sat Jul  3 16:47:50 2010
@@ -14,25 +14,23 @@
 //
 // Reverse all the bytes in a 64-bit integer.
 //
-    .align 2
+.align 2
 DEFINE_COMPILERRT_FUNCTION(__bswapdi2)
 #if __ARM_ARCH_5TEJ__ || __ARM_ARCH_4T__
-    mov r12, #0xff00
-    
-    and r3,  r12, r0, lsr #8
-    and r2,  r12, r0    
-    orr r3,   r3, r0, lsr #24   
-    orr r3,   r3, r0, lsl #24
-    orr r2,   r3, r2, lsl #8  // r2 = rev(r0)
-    
-    and r3,  r12, r1, lsr #8
-    and r0,  r12, r1
-    orr r3,   r3, r1, lsr #24
-    orr r3,   r3, r1, lsl #24
-    orr r0,   r3, r0, lsl #8  // r0 = rev(r1)
+    // before armv6 does not have "rev" instruction
+    // r2 = rev(r0)
+    eor r2, r0, r0, ror #16
+    bic r2, r2, #0xff0000
+    mov r2, r2, lsr #8
+    eor r2, r2, r0, ror #8
+    // r0 = rev(r1)
+    eor r0, r1, r1, ror #16
+    bic r0, r0, #0xff0000
+    mov r0, r0, lsr #8
+    eor r0, r0, r1, ror #8
 #else
-    rev r2,   r0  // r2 = rev(r0)
-    rev r0,   r1  // r0 = rev(r1)
+    rev r2, r0  // r2 = rev(r0)
+    rev r0, r1  // r0 = rev(r1)
 #endif
-    mov r1,   r2  // r1 = r2 = rev(r0)
+    mov r1, r2  // r1 = r2 = rev(r0)
     bx  lr

Modified: compiler-rt/trunk/lib/arm/bswapsi2.S
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/bswapsi2.S?rev=107576&r1=107575&r2=107576&view=diff
==============================================================================
--- compiler-rt/trunk/lib/arm/bswapsi2.S (original)
+++ compiler-rt/trunk/lib/arm/bswapsi2.S Sat Jul  3 16:47:50 2010
@@ -14,17 +14,15 @@
 //
 // Reverse all the bytes in a 32-bit integer.
 //
-	.align 2
+.align 2
 DEFINE_COMPILERRT_FUNCTION(__bswapsi2)
 #if __ARM_ARCH_5TEJ__ || __ARM_ARCH_4T__
-	// before armv6 does not have "rev" instruction
-    mov r1, #0xff00
-    and r2, r1, r0, lsr #8 
-    and r1, r1, r0   
-    orr r2, r2, r0, lsr #24
-    orr r2, r2, r0, lsl #24
-    orr r0, r2, r1, lsl #8
+    // before armv6 does not have "rev" instruction
+ 	eor	r1, r0, r0, ror #16
+ 	bic	r1, r1, #0xff0000
+ 	mov	r1, r1, lsr #8
+ 	eor	r0, r1, r0, ror #8
 #else
-	rev	r0, r0		// reverse bytes in parameter and put into result register
+    rev r0, r0
 #endif
-	bx	lr
+    bx  lr




From eli.friedman at gmail.com  Sat Jul  3 17:38:54 2010
From: eli.friedman at gmail.com (Eli Friedman)
Date: Sat, 3 Jul 2010 15:38:54 -0700
Subject: [llvm-commits] [PATCH] Add DAGCombine for A-(-B) -> A+B
Message-ID: <AANLkTilf_RKgm_4GkS8FUe4prlQteN3HC3R3dkGvDxhW@mail.gmail.com>

Attached.  I wanted to ask before committing because there might be
some non-obvious reason we don't already do this transformation...

This affects IR like the following:
define i32 @a(i32 %x, i32 %y) nounwind readnone {
entry:
  %mul = mul i32 %y, -8
  %sub = sub i32 %x, %mul
  ret i32 %sub
}

-Eli
-------------- next part --------------
Index: DAGCombiner.cpp
===================================================================
--- DAGCombiner.cpp	(revision 106979)
+++ DAGCombiner.cpp	(working copy)
@@ -1540,6 +1540,13 @@
       N0.getOperand(1).getOperand(1) == N1)
     return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
                        N0.getOperand(0), N0.getOperand(1).getOperand(0));
+  // fold A-(0-B) -> A+B
+  if (N1.getOpcode() == ISD::SUB)
+    if (ConstantSDNode *N01C =
+        dyn_cast<ConstantSDNode>(N1.getOperand(0).getNode()))
+      if (N01C->isNullValue())
+        return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0,
+                           N1.getOperand(1));
 
   // If either operand of a sub is undef, the result is undef
   if (N0.getOpcode() == ISD::UNDEF)

From clattner at apple.com  Sat Jul  3 23:33:22 2010
From: clattner at apple.com (Chris Lattner)
Date: Sat, 3 Jul 2010 21:33:22 -0700
Subject: [llvm-commits] [PATCH] Add DAGCombine for A-(-B) -> A+B
In-Reply-To: <AANLkTilf_RKgm_4GkS8FUe4prlQteN3HC3R3dkGvDxhW@mail.gmail.com>
References: <AANLkTilf_RKgm_4GkS8FUe4prlQteN3HC3R3dkGvDxhW@mail.gmail.com>
Message-ID: <9BD72CF0-187A-41BF-80B5-B5C72978C2AB@apple.com>


On Jul 3, 2010, at 3:38 PM, Eli Friedman wrote:

> Attached.  I wanted to ask before committing because there might be
> some non-obvious reason we don't already do this transformation...
> 
> This affects IR like the following:
> define i32 @a(i32 %x, i32 %y) nounwind readnone {
> entry:
>  %mul = mul i32 %y, -8
>  %sub = sub i32 %x, %mul
>  ret i32 %sub
> }

Looks fine to me.  It is probably missing because instcombine generally does it.

-Chris




From scanon at apple.com  Sun Jul  4 01:15:45 2010
From: scanon at apple.com (Stephen Canon)
Date: Sun, 04 Jul 2010 06:15:45 -0000
Subject: [llvm-commits] [compiler-rt] r107579 -
	/compiler-rt/trunk/lib/divsf3.c
Message-ID: <20100704061545.1A6BA2A6C12C@llvm.org>

Author: scanon
Date: Sun Jul  4 01:15:44 2010
New Revision: 107579

URL: http://llvm.org/viewvc/llvm-project?rev=107579&view=rev
Log:
Single-precision soft-float division

Added:
    compiler-rt/trunk/lib/divsf3.c

Added: compiler-rt/trunk/lib/divsf3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/divsf3.c?rev=107579&view=auto
==============================================================================
--- compiler-rt/trunk/lib/divsf3.c (added)
+++ compiler-rt/trunk/lib/divsf3.c Sun Jul  4 01:15:44 2010
@@ -0,0 +1,193 @@
+//===-- lib/divsf3.c - Single-precision division ------------------*- C -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements single-precision soft-float division
+// with the IEEE-754 default rounding (to nearest, ties to even).
+//
+// For simplicity, this implementation currently flushes denormals to zero.
+// It should be a fairly straightforward exercise to implement gradual
+// underflow with correct rounding.
+//
+//===----------------------------------------------------------------------===//
+
+#define SINGLE_PRECISION
+#include "fp_lib.h"
+
+#include <stdio.h>
+
+fp_t __divsf3(fp_t a, fp_t b) {
+    
+    const unsigned int aExponent = toRep(a) >> significandBits & maxExponent;
+    const unsigned int bExponent = toRep(b) >> significandBits & maxExponent;
+    const rep_t quotientSign = (toRep(a) ^ toRep(b)) & signBit;
+    
+    rep_t aSignificand = toRep(a) & significandMask;
+    rep_t bSignificand = toRep(b) & significandMask;
+    int scale = 0;
+    
+    // Detect if a or b is zero, denormal, infinity, or NaN.
+    if (aExponent-1U >= maxExponent-1U || bExponent-1U >= maxExponent-1U) {
+        
+        const rep_t aAbs = toRep(a) & absMask;
+        const rep_t bAbs = toRep(b) & absMask;
+        
+        // NaN / anything = qNaN
+        if (aAbs > infRep) return fromRep(toRep(a) | quietBit);
+        // anything / NaN = qNaN
+        if (bAbs > infRep) return fromRep(toRep(b) | quietBit);
+        
+        if (aAbs == infRep) {
+            // infinity / infinity = NaN
+            if (bAbs == infRep) return fromRep(qnanRep);
+            // infinity / anything else = +/- infinity
+            else return fromRep(aAbs | quotientSign);
+        }
+        
+        // anything else / infinity = +/- 0
+        if (bAbs == infRep) return fromRep(quotientSign);
+        
+        if (!aAbs) {
+            // zero / zero = NaN
+            if (!bAbs) return fromRep(qnanRep);
+            // zero / anything else = +/- zero
+            else return fromRep(quotientSign);
+        }
+        // anything else / zero = +/- infinity
+        if (!bAbs) return fromRep(infRep | quotientSign);
+        
+        // one or both of a or b is denormal, the other (if applicable) is a
+        // normal number.  Renormalize one or both of a and b, and set scale to
+        // include the necessary exponent adjustment.
+        if (aAbs < implicitBit) scale += normalize(&aSignificand);
+        if (bAbs < implicitBit) scale -= normalize(&bSignificand);
+    }
+    
+    // Or in the implicit significand bit.  (If we fell through from the
+    // denormal path it was already set by normalize( ), but setting it twice
+    // won't hurt anything.)
+    aSignificand |= implicitBit;
+    bSignificand |= implicitBit;
+    int quotientExponent = aExponent - bExponent + scale;
+    
+    // Align the significand of b as a Q31 fixed-point number in the range
+    // [1, 2.0) and get a Q32 approximate reciprocal using a small minimax
+    // polynomial approximation: reciprocal = 3/4 + 1/sqrt(2) - b/2.  This
+    // is accurate to about 3.5 binary digits.
+    uint32_t q31b = bSignificand << 8;
+    uint32_t reciprocal = UINT32_C(0x7504f333) - q31b;
+    
+    // Now refine the reciprocal estimate using a Newton-Raphson iteration:
+    //
+    //     x1 = x0 * (2 - x0 * b)
+    //
+    // This doubles the number of correct binary digits in the approximation
+    // with each iteration, so after three iterations, we have about 28 binary
+    // digits of accuracy.
+    uint32_t correction;
+    correction = -((uint64_t)reciprocal * q31b >> 32);
+    reciprocal = (uint64_t)reciprocal * correction >> 31;
+    correction = -((uint64_t)reciprocal * q31b >> 32);
+    reciprocal = (uint64_t)reciprocal * correction >> 31;
+    correction = -((uint64_t)reciprocal * q31b >> 32);
+    reciprocal = (uint64_t)reciprocal * correction >> 31;
+    
+    // Exhaustive testing shows that the error in reciprocal after three steps
+    // is in the interval [-0x1.f58108p-31, 0x1.d0e48cp-29], in line with our
+    // expectations.  We bump the reciprocal by a tiny value to force the error
+    // to be strictly positive (in the range [0x1.4fdfp-37,0x1.287246p-29], to
+    // be specific).  This also causes 1/1 to give a sensible approximation
+    // instead of zero (due to overflow).
+    reciprocal -= 2;
+    
+    // The numerical reciprocal is accurate to within 2^-28, lies in the
+    // interval [0x1.000000eep-1, 0x1.fffffffcp-1], and is strictly smaller
+    // than the true reciprocal of b.  Multiplying a by this reciprocal thus
+    // gives a numerical q = a/b in Q24 with the following properties:
+    //
+    //    1. q < a/b
+    //    2. q is in the interval [0x1.000000eep-1, 0x1.fffffffcp0)
+    //    3. the error in q is at most 2^-24 + 2^-27 -- the 2^24 term comes
+    //       from the fact that we truncate the product, and the 2^27 term
+    //       is the error in the reciprocal of b scaled by the maximum
+    //       possible value of a.  As a consequence of this error bound,
+    //       either q or nextafter(q) is the correctly rounded 
+    rep_t quotient = (uint64_t)reciprocal*(aSignificand << 1) >> 32;
+    
+    // Two cases: quotient is in [0.5, 1.0) or quotient is in [1.0, 2.0).
+    // In either case, we are going to compute a residual of the form
+    //
+    //     r = a - q*b
+    //
+    // We know from the construction of q that r satisfies:
+    //
+    //     0 <= r < ulp(q)*b
+    // 
+    // if r is greater than 1/2 ulp(q)*b, then q rounds up.  Otherwise, we
+    // already have the correct result.  The exact halfway case cannot occur.
+    // We also take this time to right shift quotient if it falls in the [1,2)
+    // range and adjust the exponent accordingly.
+    rep_t residual;
+    if (quotient < (implicitBit << 1)) {
+        residual = (aSignificand << 24) - quotient * bSignificand;
+        quotientExponent--;
+    } else {
+        quotient >>= 1;
+        residual = (aSignificand << 23) - quotient * bSignificand;
+    }
+
+    const int writtenExponent = quotientExponent + exponentBias;
+    
+    if (writtenExponent >= maxExponent) {
+        // If we have overflowed the exponent, return infinity.
+        return fromRep(infRep | quotientSign);
+    }
+    
+    else if (writtenExponent < 1) {
+        // Flush denormals to zero.  In the future, it would be nice to add
+        // code to round them correctly.
+        return fromRep(quotientSign);
+    }
+    
+    else {
+        const bool round = (residual << 1) > bSignificand;
+        // Clear the implicit bit
+        rep_t absResult = quotient & significandMask;
+        // Insert the exponent
+        absResult |= (rep_t)writtenExponent << significandBits;
+        // Round
+        absResult += round;
+        // Insert the sign and return
+        return fromRep(absResult | quotientSign);
+    }
+}
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+




From ggreif at gmail.com  Sun Jul  4 02:42:31 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Sun, 04 Jul 2010 07:42:31 -0000
Subject: [llvm-commits] [llvm] r107580 -
	/llvm/trunk/include/llvm/Instructions.h
Message-ID: <20100704074231.AB8402A6C12D@llvm.org>

Author: ggreif
Date: Sun Jul  4 02:42:31 2010
New Revision: 107580

URL: http://llvm.org/viewvc/llvm-project?rev=107580&view=rev
Log:
[another test commit, just to tickle the selfhost buildbots; I'll back out in a few minutes]

second round of low-level interface squeeze-out:
making all of CallInst's low-level operand accessors
private

If you get compile errors I strongly urge you to
update your code.


I tried to write the necessary clues into the
header where the compiler may point to, but no
guarantees. It works for my GCC.

You have several options to update your code:

- you can use the v2.8 ArgOperand accessors
- you can go via a temporary CallSite
- you can upcast to, say, User and call its
  low-level accessors if your code is definitely
  operand-order agnostic.

If you run into serious problems, please
comment in below thread (and back out this
revision only if absolutely necessary):

<http://groups.google.com/group/llvm-dev/browse_thread/thread/64650cf343b28271>

Modified:
    llvm/trunk/include/llvm/Instructions.h

Modified: llvm/trunk/include/llvm/Instructions.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=107580&r1=107579&r2=107580&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Instructions.h (original)
+++ llvm/trunk/include/llvm/Instructions.h Sun Jul  4 02:42:31 2010
@@ -940,8 +940,24 @@
                                unsigned(isTC));
   }
 
+  /// @deprecated these "define hacks" will go away soon
+  /// @brief coerce out-of-tree code to abandon the low-level interfaces
+  /// @detail see below comments and update your code to high-level interfaces
+  ///    in LLVM v2.8-only code
+  ///    - getOperand(N+1)  --->  getArgOperand(N)
+  ///    - setOperand(N+1, V)  --->  setArgOperand(N, V)
+  ///    - getNumOperands()  --->  getNumArgOperands()+1  // note the "+1"!
+  ///
+  ///    in backward compatible code please consult llvm/Support/CallSite.h,
+  ///    you should create a callsite using the CallInst pointer and call its methods
+  ///
+# define public private
+# define protected private
   /// Provide fast operand accessors
   DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
+# undef public
+# undef protected
+public:
 
   enum { ArgOffset = 1 }; ///< temporary, do not use for new code!
   unsigned getNumArgOperands() const { return getNumOperands() - 1; }
@@ -951,7 +967,7 @@
   /// Provide compile-time errors for accessing operand 0
   /// @deprecated these will go away soon
   /// @detail see below comments and update your code to high-level interfaces
-  ///    - getOperand(0)  --->  getCalledValue()
+  ///    - getOperand(0)  --->  getCalledValue(), or possibly getCalledFunction()
   ///    - setOperand(0, V)  --->  setCalledFunction(V)
   ///
 private:
@@ -1107,6 +1123,10 @@
        typename std::iterator_traits<InputIterator>::iterator_category());
 }
 
+
+// Note: if you get compile errors about private methods then
+//       please update your code to use the high-level operand
+//       interfaces. See line 943 above.
 DEFINE_TRANSPARENT_OPERAND_ACCESSORS(CallInst, Value)
 
 //===----------------------------------------------------------------------===//




From isanbard at gmail.com  Sun Jul  4 03:58:43 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Sun, 04 Jul 2010 08:58:43 -0000
Subject: [llvm-commits] [llvm] r107581 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Message-ID: <20100704085843.36D8E2A6C12C@llvm.org>

Author: void
Date: Sun Jul  4 03:58:43 2010
New Revision: 107581

URL: http://llvm.org/viewvc/llvm-project?rev=107581&view=rev
Log:
Proper indentation.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=107581&r1=107580&r2=107581&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sun Jul  4 03:58:43 2010
@@ -1586,7 +1586,7 @@
                                       SDValue(Res, ResNumResults-1));
 
   if ((EmitNodeInfo & OPFL_FlagOutput) != 0)
-  --ResNumResults;
+    --ResNumResults;
 
   // Move the chain reference if needed.
   if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&




From ggreif at gmail.com  Sun Jul  4 03:59:25 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Sun, 04 Jul 2010 08:59:25 -0000
Subject: [llvm-commits] [llvm] r107582 -
	/llvm/trunk/include/llvm/Instructions.h
Message-ID: <20100704085925.B8ABB2A6C12C@llvm.org>

Author: ggreif
Date: Sun Jul  4 03:59:25 2010
New Revision: 107582

URL: http://llvm.org/viewvc/llvm-project?rev=107582&view=rev
Log:
back out r107580, I have seen what I wanted

Modified:
    llvm/trunk/include/llvm/Instructions.h

Modified: llvm/trunk/include/llvm/Instructions.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=107582&r1=107581&r2=107582&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Instructions.h (original)
+++ llvm/trunk/include/llvm/Instructions.h Sun Jul  4 03:59:25 2010
@@ -940,24 +940,8 @@
                                unsigned(isTC));
   }
 
-  /// @deprecated these "define hacks" will go away soon
-  /// @brief coerce out-of-tree code to abandon the low-level interfaces
-  /// @detail see below comments and update your code to high-level interfaces
-  ///    in LLVM v2.8-only code
-  ///    - getOperand(N+1)  --->  getArgOperand(N)
-  ///    - setOperand(N+1, V)  --->  setArgOperand(N, V)
-  ///    - getNumOperands()  --->  getNumArgOperands()+1  // note the "+1"!
-  ///
-  ///    in backward compatible code please consult llvm/Support/CallSite.h,
-  ///    you should create a callsite using the CallInst pointer and call its methods
-  ///
-# define public private
-# define protected private
   /// Provide fast operand accessors
   DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
-# undef public
-# undef protected
-public:
 
   enum { ArgOffset = 1 }; ///< temporary, do not use for new code!
   unsigned getNumArgOperands() const { return getNumOperands() - 1; }
@@ -967,7 +951,7 @@
   /// Provide compile-time errors for accessing operand 0
   /// @deprecated these will go away soon
   /// @detail see below comments and update your code to high-level interfaces
-  ///    - getOperand(0)  --->  getCalledValue(), or possibly getCalledFunction()
+  ///    - getOperand(0)  --->  getCalledValue()
   ///    - setOperand(0, V)  --->  setCalledFunction(V)
   ///
 private:
@@ -1123,10 +1107,6 @@
        typename std::iterator_traits<InputIterator>::iterator_category());
 }
 
-
-// Note: if you get compile errors about private methods then
-//       please update your code to use the high-level operand
-//       interfaces. See line 943 above.
 DEFINE_TRANSPARENT_OPERAND_ACCESSORS(CallInst, Value)
 
 //===----------------------------------------------------------------------===//




From isanbard at gmail.com  Sun Jul  4 03:59:55 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Sun, 04 Jul 2010 08:59:55 -0000
Subject: [llvm-commits] [llvm] r107583 -
	/llvm/trunk/lib/Target/X86/X86InstrSSE.td
Message-ID: <20100704085955.7082A2A6C12C@llvm.org>

Author: void
Date: Sun Jul  4 03:59:55 2010
New Revision: 107583

URL: http://llvm.org/viewvc/llvm-project?rev=107583&view=rev
Log:
Mark sse_load_f32 and sse_load_f64 as having memory operands
(SDNPMemOperand). This way when they're morphed the memory operands will be
copied as well.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=107583&r1=107582&r2=107583&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Sun Jul  4 03:59:55 2010
@@ -82,9 +82,9 @@
 // the top elements.  These are used for the SSE 'ss' and 'sd' instruction
 // forms.
 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
-                                  [SDNPHasChain, SDNPMayLoad]>;
+                                  [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
-                                  [SDNPHasChain, SDNPMayLoad]>;
+                                  [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 
 def ssmem : Operand<v4f32> {
   let PrintMethod = "printf32mem";




From isanbard at gmail.com  Sun Jul  4 04:16:57 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Sun, 04 Jul 2010 09:16:57 -0000
Subject: [llvm-commits] [llvm] r107585 -
	/llvm/trunk/lib/Target/X86/X86InstrSSE.td
Message-ID: <20100704091657.3DD8A2A6C12C@llvm.org>

Author: void
Date: Sun Jul  4 04:16:57 2010
New Revision: 107585

URL: http://llvm.org/viewvc/llvm-project?rev=107585&view=rev
Log:
Revert r107583. I no longer think that this is the way to solve the problem.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=107585&r1=107584&r2=107585&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Sun Jul  4 04:16:57 2010
@@ -82,9 +82,9 @@
 // the top elements.  These are used for the SSE 'ss' and 'sd' instruction
 // forms.
 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
-                                  [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
+                                  [SDNPHasChain, SDNPMayLoad]>;
 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
-                                  [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
+                                  [SDNPHasChain, SDNPMayLoad]>;
 
 def ssmem : Operand<v4f32> {
   let PrintMethod = "printf32mem";




From scanon at apple.com  Sun Jul  4 11:53:39 2010
From: scanon at apple.com (Stephen Canon)
Date: Sun, 04 Jul 2010 16:53:39 -0000
Subject: [llvm-commits] [compiler-rt] r107586 - in /compiler-rt/trunk/lib:
 divdf3.c divsf3.c fp_lib.h muldf3.c mulsf3.c
Message-ID: <20100704165339.BE1862A6C12C@llvm.org>

Author: scanon
Date: Sun Jul  4 11:53:39 2010
New Revision: 107586

URL: http://llvm.org/viewvc/llvm-project?rev=107586&view=rev
Log:
Initial implementation of double-precision soft-float division, moved a couple utility functions from the multiplications into the utility header

Added:
    compiler-rt/trunk/lib/divdf3.c
Modified:
    compiler-rt/trunk/lib/divsf3.c
    compiler-rt/trunk/lib/fp_lib.h
    compiler-rt/trunk/lib/muldf3.c
    compiler-rt/trunk/lib/mulsf3.c

Added: compiler-rt/trunk/lib/divdf3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/divdf3.c?rev=107586&view=auto
==============================================================================
--- compiler-rt/trunk/lib/divdf3.c (added)
+++ compiler-rt/trunk/lib/divdf3.c Sun Jul  4 11:53:39 2010
@@ -0,0 +1,182 @@
+//===-- lib/divdf3.c - Double-precision division ------------------*- C -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements double-precision soft-float division
+// with the IEEE-754 default rounding (to nearest, ties to even).
+//
+// For simplicity, this implementation currently flushes denormals to zero.
+// It should be a fairly straightforward exercise to implement gradual
+// underflow with correct rounding.
+//
+//===----------------------------------------------------------------------===//
+
+#define DOUBLE_PRECISION
+#include "fp_lib.h"
+
+fp_t __divdf3(fp_t a, fp_t b) {
+    
+    const unsigned int aExponent = toRep(a) >> significandBits & maxExponent;
+    const unsigned int bExponent = toRep(b) >> significandBits & maxExponent;
+    const rep_t quotientSign = (toRep(a) ^ toRep(b)) & signBit;
+    
+    rep_t aSignificand = toRep(a) & significandMask;
+    rep_t bSignificand = toRep(b) & significandMask;
+    int scale = 0;
+    
+    // Detect if a or b is zero, denormal, infinity, or NaN.
+    if (aExponent-1U >= maxExponent-1U || bExponent-1U >= maxExponent-1U) {
+        
+        const rep_t aAbs = toRep(a) & absMask;
+        const rep_t bAbs = toRep(b) & absMask;
+        
+        // NaN / anything = qNaN
+        if (aAbs > infRep) return fromRep(toRep(a) | quietBit);
+        // anything / NaN = qNaN
+        if (bAbs > infRep) return fromRep(toRep(b) | quietBit);
+        
+        if (aAbs == infRep) {
+            // infinity / infinity = NaN
+            if (bAbs == infRep) return fromRep(qnanRep);
+            // infinity / anything else = +/- infinity
+            else return fromRep(aAbs | quotientSign);
+        }
+        
+        // anything else / infinity = +/- 0
+        if (bAbs == infRep) return fromRep(quotientSign);
+        
+        if (!aAbs) {
+            // zero / zero = NaN
+            if (!bAbs) return fromRep(qnanRep);
+            // zero / anything else = +/- zero
+            else return fromRep(quotientSign);
+        }
+        // anything else / zero = +/- infinity
+        if (!bAbs) return fromRep(infRep | quotientSign);
+        
+        // one or both of a or b is denormal, the other (if applicable) is a
+        // normal number.  Renormalize one or both of a and b, and set scale to
+        // include the necessary exponent adjustment.
+        if (aAbs < implicitBit) scale += normalize(&aSignificand);
+        if (bAbs < implicitBit) scale -= normalize(&bSignificand);
+    }
+    
+    // Or in the implicit significand bit.  (If we fell through from the
+    // denormal path it was already set by normalize( ), but setting it twice
+    // won't hurt anything.)
+    aSignificand |= implicitBit;
+    bSignificand |= implicitBit;
+    int quotientExponent = aExponent - bExponent + scale;
+    
+    // Align the significand of b as a Q31 fixed-point number in the range
+    // [1, 2.0) and get a Q32 approximate reciprocal using a small minimax
+    // polynomial approximation: reciprocal = 3/4 + 1/sqrt(2) - b/2.  This
+    // is accurate to about 3.5 binary digits.
+    const uint32_t q31b = bSignificand >> 21;
+    uint32_t recip32 = UINT32_C(0x7504f333) - q31b;
+    
+    // Now refine the reciprocal estimate using a Newton-Raphson iteration:
+    //
+    //     x1 = x0 * (2 - x0 * b)
+    //
+    // This doubles the number of correct binary digits in the approximation
+    // with each iteration, so after three iterations, we have about 28 binary
+    // digits of accuracy.
+    uint32_t correction32;
+    correction32 = -((uint64_t)recip32 * q31b >> 32);
+    recip32 = (uint64_t)recip32 * correction32 >> 31;
+    correction32 = -((uint64_t)recip32 * q31b >> 32);
+    recip32 = (uint64_t)recip32 * correction32 >> 31;
+    correction32 = -((uint64_t)recip32 * q31b >> 32);
+    recip32 = (uint64_t)recip32 * correction32 >> 31;
+    
+    // recip32 might have overflowed to exactly zero in the preceeding
+    // computation if the high word of b is exactly 1.0.  This would sabotage
+    // the full-width final stage of the computation that follows, so we adjust
+    // recip32 downward by one bit.
+    recip32--;
+    
+    // We need to perform one more iteration to get us to 56 binary digits;
+    // The last iteration needs to happen with extra precision.
+    const uint32_t q63blo = bSignificand << 11;
+    uint64_t correction, reciprocal;
+    correction = -((uint64_t)recip32*q31b + ((uint64_t)recip32*q63blo >> 32));
+    uint32_t cHi = correction >> 32;
+    uint32_t cLo = correction;
+    reciprocal = (uint64_t)recip32*cHi + ((uint64_t)recip32*cLo >> 32);
+    
+    // We already adjusted the 32-bit estimate, now we need to adjust the final
+    // 64-bit reciprocal estimate downward to ensure that it is strictly smaller
+    // than the infinitely precise exact reciprocal.  Because the computation
+    // of the Newton-Raphson step is truncating at every step, this adjustment
+    // is small; most of the work is already done.
+    reciprocal -= 2;
+    
+    // The numerical reciprocal is accurate to within 2^-56, lies in the
+    // interval [0.5, 1.0), and is strictly smaller than the true reciprocal
+    // of b.  Multiplying a by this reciprocal thus gives a numerical q = a/b
+    // in Q53 with the following properties:
+    //
+    //    1. q < a/b
+    //    2. q is in the interval [0.5, 2.0)
+    //    3. the error in q is bounded away from 2^-53 (actually, we have a
+    //       couple of bits to spare, but this is all we need).
+    
+    // We need a 64 x 64 multiply high to compute q, which isn't a basic
+    // operation in C, so we need to be a little bit fussy.
+    rep_t quotient, quotientLo;
+    wideMultiply(aSignificand << 2, reciprocal, &quotient, &quotientLo);
+    
+    // Two cases: quotient is in [0.5, 1.0) or quotient is in [1.0, 2.0).
+    // In either case, we are going to compute a residual of the form
+    //
+    //     r = a - q*b
+    //
+    // We know from the construction of q that r satisfies:
+    //
+    //     0 <= r < ulp(q)*b
+    // 
+    // if r is greater than 1/2 ulp(q)*b, then q rounds up.  Otherwise, we
+    // already have the correct result.  The exact halfway case cannot occur.
+    // We also take this time to right shift quotient if it falls in the [1,2)
+    // range and adjust the exponent accordingly.
+    rep_t residual;
+    if (quotient < (implicitBit << 1)) {
+        residual = (aSignificand << 53) - quotient * bSignificand;
+        quotientExponent--;
+    } else {
+        quotient >>= 1;
+        residual = (aSignificand << 52) - quotient * bSignificand;
+    }
+    
+    const int writtenExponent = quotientExponent + exponentBias;
+    
+    if (writtenExponent >= maxExponent) {
+        // If we have overflowed the exponent, return infinity.
+        return fromRep(infRep | quotientSign);
+    }
+    
+    else if (writtenExponent < 1) {
+        // Flush denormals to zero.  In the future, it would be nice to add
+        // code to round them correctly.
+        return fromRep(quotientSign);
+    }
+    
+    else {
+        const bool round = (residual << 1) > bSignificand;
+        // Clear the implicit bit
+        rep_t absResult = quotient & significandMask;
+        // Insert the exponent
+        absResult |= (rep_t)writtenExponent << significandBits;
+        // Round
+        absResult += round;
+        // Insert the sign and return
+        const double result = fromRep(absResult | quotientSign);
+        return result;
+    }
+}

Modified: compiler-rt/trunk/lib/divsf3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/divsf3.c?rev=107586&r1=107585&r2=107586&view=diff
==============================================================================
--- compiler-rt/trunk/lib/divsf3.c (original)
+++ compiler-rt/trunk/lib/divsf3.c Sun Jul  4 11:53:39 2010
@@ -19,8 +19,6 @@
 #define SINGLE_PRECISION
 #include "fp_lib.h"
 
-#include <stdio.h>
-
 fp_t __divsf3(fp_t a, fp_t b) {
     
     const unsigned int aExponent = toRep(a) >> significandBits & maxExponent;
@@ -166,28 +164,3 @@
         return fromRep(absResult | quotientSign);
     }
 }
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-

Modified: compiler-rt/trunk/lib/fp_lib.h
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/fp_lib.h?rev=107586&r1=107585&r2=107586&view=diff
==============================================================================
--- compiler-rt/trunk/lib/fp_lib.h (original)
+++ compiler-rt/trunk/lib/fp_lib.h Sun Jul  4 11:53:39 2010
@@ -37,6 +37,13 @@
     return __builtin_clz(a);
 }
 
+// 32x32 --> 64 bit multiply
+static inline void wideMultiply(rep_t a, rep_t b, rep_t *hi, rep_t *lo) {
+    const uint64_t product = (uint64_t)a*b;
+    *hi = product >> 32;
+    *lo = product;
+}
+
 #elif defined DOUBLE_PRECISION
 
 typedef uint64_t rep_t;
@@ -56,6 +63,26 @@
 #endif
 }
 
+#define loWord(a) (a & 0xffffffffU)
+#define hiWord(a) (a >> 32)
+
+// 64x64 -> 128 wide multiply for platforms that don't have such an operation;
+// many 64-bit platforms have this operation, but they tend to have hardware
+// floating-point, so we don't bother with a special case for them here.
+static inline void wideMultiply(rep_t a, rep_t b, rep_t *hi, rep_t *lo) {
+    // Each of the component 32x32 -> 64 products
+    const uint64_t plolo = loWord(a) * loWord(b);
+    const uint64_t plohi = loWord(a) * hiWord(b);
+    const uint64_t philo = hiWord(a) * loWord(b);
+    const uint64_t phihi = hiWord(a) * hiWord(b);
+    // Sum terms that contribute to lo in a way that allows us to get the carry
+    const uint64_t r0 = loWord(plolo);
+    const uint64_t r1 = hiWord(plolo) + loWord(plohi) + loWord(philo);
+    *lo = r0 + (r1 << 32);
+    // Sum terms contributing to hi with the carry from lo
+    *hi = hiWord(plohi) + hiWord(philo) + hiWord(r1) + phihi;
+}
+
 #else
 #error Either SINGLE_PRECISION or DOUBLE_PRECISION must be defined.
 #endif

Modified: compiler-rt/trunk/lib/muldf3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/muldf3.c?rev=107586&r1=107585&r2=107586&view=diff
==============================================================================
--- compiler-rt/trunk/lib/muldf3.c (original)
+++ compiler-rt/trunk/lib/muldf3.c Sun Jul  4 11:53:39 2010
@@ -15,26 +15,6 @@
 #define DOUBLE_PRECISION
 #include "fp_lib.h"
 
-#define loWord(a) (a & 0xffffffffU)
-#define hiWord(a) (a >> 32)
-
-// 64x64 -> 128 wide multiply for platforms that don't have such an operation;
-// many 64-bit platforms have this operation, but they tend to have hardware
-// floating-point, so we don't bother with a special case for them here.
-static inline void wideMultiply(rep_t a, rep_t b, rep_t *hi, rep_t *lo) {
-    // Each of the component 32x32 -> 64 products
-    const uint64_t plolo = loWord(a) * loWord(b);
-    const uint64_t plohi = loWord(a) * hiWord(b);
-    const uint64_t philo = hiWord(a) * loWord(b);
-    const uint64_t phihi = hiWord(a) * hiWord(b);
-    // Sum terms that contribute to lo in a way that allows us to get the carry
-    const uint64_t r0 = loWord(plolo);
-    const uint64_t r1 = hiWord(plolo) + loWord(plohi) + loWord(philo);
-    *lo = r0 + (r1 << 32);
-    // Sum terms contributing to hi with the carry from lo
-    *hi = hiWord(plohi) + hiWord(philo) + hiWord(r1) + phihi;
-}
-
 fp_t __muldf3(fp_t a, fp_t b) {
     
     const unsigned int aExponent = toRep(a) >> significandBits & maxExponent;

Modified: compiler-rt/trunk/lib/mulsf3.c
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/mulsf3.c?rev=107586&r1=107585&r2=107586&view=diff
==============================================================================
--- compiler-rt/trunk/lib/mulsf3.c (original)
+++ compiler-rt/trunk/lib/mulsf3.c Sun Jul  4 11:53:39 2010
@@ -15,13 +15,6 @@
 #define SINGLE_PRECISION
 #include "fp_lib.h"
 
-// 32x32 --> 64 bit multiply
-static inline void wideMultiply(rep_t a, rep_t b, rep_t *hi, rep_t *lo) {
-    const uint64_t product = (uint64_t)a*b;
-    *hi = product >> 32;
-    *lo = product;
-}
-
 fp_t __mulsf3(fp_t a, fp_t b) {
     
     const unsigned int aExponent = toRep(a) >> significandBits & maxExponent;




From clattner at apple.com  Sun Jul  4 12:09:04 2010
From: clattner at apple.com (Chris Lattner)
Date: Sun, 4 Jul 2010 10:09:04 -0700
Subject: [llvm-commits] [llvm] r107496 -
	/llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp
In-Reply-To: <20100702184305.CD6C82A6C12C@llvm.org>
References: <20100702184305.CD6C82A6C12C@llvm.org>
Message-ID: <536044D1-48E0-4E40-A948-4BF558626458@apple.com>


On Jul 2, 2010, at 11:43 AM, Dan Gohman wrote:

> Author: djg
> Date: Fri Jul  2 13:43:05 2010
> New Revision: 107496
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=107496&view=rev
> Log:
> Don't claim to preserve AliasAnalysis. First, this is doesn't actually
> have any effect, and second, deleting stores can potentially invalidate
> an AliasAnalysis, and there's currently no notification for this.

Alias analysis is preserved.  Through statements like this:
  MDA.removeInstruction(DeadInst);

Memdep updates AA.

-Chris


> 
> Modified:
>    llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp
> 
> Modified: llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp?rev=107496&r1=107495&r2=107496&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp (original)
> +++ llvm/trunk/lib/Transforms/Scalar/DeadStoreElimination.cpp Fri Jul  2 13:43:05 2010
> @@ -74,7 +74,6 @@
>       AU.addRequired<AliasAnalysis>();
>       AU.addRequired<MemoryDependenceAnalysis>();
>       AU.addPreserved<DominatorTree>();
> -      AU.addPreserved<AliasAnalysis>();
>       AU.addPreserved<MemoryDependenceAnalysis>();
>     }
> 
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits




From clattner at apple.com  Sun Jul  4 12:10:51 2010
From: clattner at apple.com (Chris Lattner)
Date: Sun, 4 Jul 2010 10:10:51 -0700
Subject: [llvm-commits] [llvm-gcc-4.2] r107439 - in
	/llvm-gcc-4.2/trunk/gcc: llvm-backend.cpp tree.h varasm.c
In-Reply-To: <20100701223732.320262A6C12C@llvm.org>
References: <20100701223732.320262A6C12C@llvm.org>
Message-ID: <D773ECC1-804A-40DE-99AC-A39CF3DAE774@apple.com>

On Jul 1, 2010, at 3:37 PM, Bill Wendling wrote:
> +++ llvm-gcc-4.2/trunk/gcc/tree.h Thu Jul  1 17:37:31 2010
> @@ -2937,6 +2937,9 @@
>   (DECL_WITH_VIS_CHECK (NODE)->decl_with_vis.llvm_private_flag)
> #define DECL_LLVM_LINKER_PRIVATE(NODE) \
>   (DECL_WITH_VIS_CHECK (NODE)->decl_with_vis.llvm_linker_private_flag)
> +/* LLVM LOCAL - linker_private_weak <rdar://problem/7907014> */
> +#define DECL_LLVM_LINKER_PRIVATE_WEAK(NODE) \
> +  (DECL_WITH_VIS_CHECK (NODE)->decl_with_vis.llvm_linker_private_weak_flag)
> #endif
> /* LLVM LOCAL end */
> 
> @@ -3080,6 +3083,8 @@
>  /* LLVM LOCAL begin */
>  unsigned llvm_private_flag : 1;
>  unsigned llvm_linker_private_flag : 1;
> + /* LLVM LOCAL - linker_private_weak <rdar://problem/7907014> */
> + unsigned llvm_linker_private_weak_flag : 1;
>  /* LLVM LOCAL end */

Please update the /* 3 unused bits (llvm). */ comment at the end of this struct, thanks Bill!

-Chris


From clattner at apple.com  Sun Jul  4 12:15:00 2010
From: clattner at apple.com (Chris Lattner)
Date: Sun, 4 Jul 2010 10:15:00 -0700
Subject: [llvm-commits] [llvm] r107529 - in /llvm/trunk:
	include/llvm/CodeGen/MachineInstr.h include/llvm/Target/Target.td
	include/llvm/Target/TargetOpcodes.h
	lib/CodeGen/LowerSubregs.cpp utils/TableGen/CodeGenTarget.cpp
In-Reply-To: <20100702222950.DC0692A6C12C@llvm.org>
References: <20100702222950.DC0692A6C12C@llvm.org>
Message-ID: <762A630F-61FD-4DE1-993F-13A0AE1BFC4E@apple.com>


On Jul 2, 2010, at 3:29 PM, Jakob Stoklund Olesen wrote:

> Author: stoklund
> Date: Fri Jul  2 17:29:50 2010
> New Revision: 107529
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=107529&view=rev
> Log:
> Add a new target independent COPY instruction and code to lower it.
> 
> The COPY instruction is intended to replace the target specific copy
> instructions for virtual registers as well as the EXTRACT_SUBREG and
> INSERT_SUBREG instructions in MachineFunctions. It won't we used in a selection
> DAG.
> 
> COPY is lowered to native register copies by LowerSubregs.

Very interesting!  This means that the early code generator won't need to call the virtual method to determine if something is a copy?  This will also make targets that forget to implement the 'is copy' hook generate better code by default.

This sounds like a great plan to me.  What is the migration plan for existing targets and existing codegen passes?  Do they need to do anything?  Do you think the "isMove" target hook can go away completely?

-Chris


> 
> Modified:
>    llvm/trunk/include/llvm/CodeGen/MachineInstr.h
>    llvm/trunk/include/llvm/Target/Target.td
>    llvm/trunk/include/llvm/Target/TargetOpcodes.h
>    llvm/trunk/lib/CodeGen/LowerSubregs.cpp
>    llvm/trunk/utils/TableGen/CodeGenTarget.cpp
> 
> Modified: llvm/trunk/include/llvm/CodeGen/MachineInstr.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstr.h?rev=107529&r1=107528&r2=107529&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/CodeGen/MachineInstr.h (original)
> +++ llvm/trunk/include/llvm/CodeGen/MachineInstr.h Fri Jul  2 17:29:50 2010
> @@ -227,7 +227,10 @@
>   bool isRegSequence() const {
>     return getOpcode() == TargetOpcode::REG_SEQUENCE;
>   }
> -  
> +  bool isCopy() const {
> +    return getOpcode() == TargetOpcode::COPY;
> +  }
> +
>   /// readsRegister - Return true if the MachineInstr reads the specified
>   /// register. If TargetRegisterInfo is passed, then it also checks if there
>   /// is a read of a super-register.
> 
> Modified: llvm/trunk/include/llvm/Target/Target.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=107529&r1=107528&r2=107529&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Target/Target.td (original)
> +++ llvm/trunk/include/llvm/Target/Target.td Fri Jul  2 17:29:50 2010
> @@ -476,7 +476,6 @@
>   let AsmString = "DBG_VALUE";
>   let isAsCheapAsAMove = 1;
> }
> -
> def REG_SEQUENCE : Instruction {
>   let OutOperandList = (outs unknown:$dst);
>   let InOperandList = (ins variable_ops);
> @@ -484,6 +483,13 @@
>   let neverHasSideEffects = 1;
>   let isAsCheapAsAMove = 1;
> }
> +def COPY : Instruction {
> +  let OutOperandList = (outs unknown:$dst);
> +  let InOperandList = (ins unknown:$src);
> +  let AsmString = "";
> +  let neverHasSideEffects = 1;
> +  let isAsCheapAsAMove = 1;
> +}
> }
> 
> //===----------------------------------------------------------------------===//
> 
> Modified: llvm/trunk/include/llvm/Target/TargetOpcodes.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetOpcodes.h?rev=107529&r1=107528&r2=107529&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Target/TargetOpcodes.h (original)
> +++ llvm/trunk/include/llvm/Target/TargetOpcodes.h Fri Jul  2 17:29:50 2010
> @@ -75,7 +75,11 @@
>     /// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5
>     /// After register coalescing references of v1024 should be replace with
>     /// v1027:3, v1025 with v1027:4, etc.
> -    REG_SEQUENCE = 12
> +    REG_SEQUENCE = 12,
> +
> +    /// COPY - Target-independent register copy. This instruction can also be
> +    /// used to copy between subregisters of virtual registers.
> +    COPY = 13
>   };
> } // end namespace TargetOpcode
> } // end namespace llvm
> 
> Modified: llvm/trunk/lib/CodeGen/LowerSubregs.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LowerSubregs.cpp?rev=107529&r1=107528&r2=107529&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/LowerSubregs.cpp (original)
> +++ llvm/trunk/lib/CodeGen/LowerSubregs.cpp Fri Jul  2 17:29:50 2010
> @@ -56,6 +56,7 @@
>     bool LowerExtract(MachineInstr *MI);
>     bool LowerInsert(MachineInstr *MI);
>     bool LowerSubregToReg(MachineInstr *MI);
> +    bool LowerCopy(MachineInstr *MI);
> 
>     void TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
>                           const TargetRegisterInfo *TRI);
> @@ -321,6 +322,52 @@
>   return true;
> }
> 
> +bool LowerSubregsInstructionPass::LowerCopy(MachineInstr *MI) {
> +  MachineOperand &DstMO = MI->getOperand(0);
> +  MachineOperand &SrcMO = MI->getOperand(1);
> +
> +  if (SrcMO.getReg() == DstMO.getReg()) {
> +    DEBUG(dbgs() << "identity copy: " << *MI);
> +    // No need to insert an identity copy instruction, but replace with a KILL
> +    // if liveness is changed.
> +    if (DstMO.isDead() || SrcMO.isUndef() || MI->getNumOperands() > 2) {
> +      // We must make sure the super-register gets killed. Replace the
> +      // instruction with KILL.
> +      MI->setDesc(TII->get(TargetOpcode::KILL));
> +      DEBUG(dbgs() << "replaced by:   " << *MI);
> +      return true;
> +    }
> +    // Vanilla identity copy.
> +    MI->eraseFromParent();
> +    return true;
> +  }
> +
> +  DEBUG(dbgs() << "real copy:   " << *MI);
> +  // Ask target for a lowered copy instruction.
> +  const TargetRegisterClass *DstRC =
> +    TRI->getPhysicalRegisterRegClass(DstMO.getReg());
> +  const TargetRegisterClass *SrcRC =
> +    TRI->getPhysicalRegisterRegClass(SrcMO.getReg());
> +  bool Emitted = TII->copyRegToReg(*MI->getParent(), MI,
> +                                   DstMO.getReg(), SrcMO.getReg(),
> +                                   DstRC, SrcRC, MI->getDebugLoc());
> +  (void)Emitted;
> +  assert(Emitted && "Cannot emit copy");
> +
> +  if (DstMO.isDead())
> +    TransferDeadFlag(MI, DstMO.getReg(), TRI);
> +  if (SrcMO.isKill())
> +    TransferKillFlag(MI, SrcMO.getReg(), TRI, true);
> +  if (MI->getNumOperands() > 2)
> +    TransferImplicitDefs(MI);
> +  DEBUG({
> +    MachineBasicBlock::iterator dMI = MI;
> +    dbgs() << "replaced by: " << *(--dMI);
> +  });
> +  MI->eraseFromParent();
> +  return true;
> +}
> +
> /// runOnMachineFunction - Reduce subregister inserts and extracts to register
> /// copies.
> ///
> @@ -346,6 +393,8 @@
>         MadeChange |= LowerInsert(MI);
>       } else if (MI->isSubregToReg()) {
>         MadeChange |= LowerSubregToReg(MI);
> +      } else if (MI->isCopy()) {
> +        MadeChange |= LowerCopy(MI);
>       }
>       mi = nmi;
>     }
> 
> Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=107529&r1=107528&r2=107529&view=diff
> ==============================================================================
> --- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original)
> +++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Fri Jul  2 17:29:50 2010
> @@ -344,6 +344,7 @@
>     "COPY_TO_REGCLASS",
>     "DBG_VALUE",
>     "REG_SEQUENCE",
> +    "COPY",
>     0
>   };
>   const DenseMap<const Record*, CodeGenInstruction*> &Insts = getInstructions();
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits




From clattner at apple.com  Sun Jul  4 12:23:46 2010
From: clattner at apple.com (Chris Lattner)
Date: Sun, 4 Jul 2010 10:23:46 -0700
Subject: [llvm-commits] [llvm] r107109 - in /llvm/trunk:
	include/llvm/Analysis/AliasAnalysis.h	include/llvm/Analysis/Passes.h
	lib/Analysis/AliasAnalysis.cpp	lib/Analysis/BasicAliasAnalysis.cpp
	test/Analysis/BasicAA/interprocedural.ll
In-Reply-To: <92C98C7C-831E-4021-964E-B20289FB8BAB@apple.com>
References: <20100629005039.39B192A6C12C@llvm.org> <4C298317.7050002@mxc.ca>
	<5E31E70D-BC94-4545-BE28-F8927D72097F@apple.com>
	<0EAA395C-1A7A-45D2-A6F9-F3B837A0F91C@apple.com>
	<92C98C7C-831E-4021-964E-B20289FB8BAB@apple.com>
Message-ID: <223AACF7-5C47-45C5-9432-5126BF018B71@apple.com>

On Jul 1, 2010, at 2:29 PM, Dan Gohman wrote:
>>> "noalias" is only meaningful from a single-procedure perspective.
>>> For example:
>>> 
>>> @G = external global i32
>>> define void @foo(i32* noalias %p) {
>>> ...
>>> }
>>> ...
>>> call void @foo(i32* @G)
>>> If you're working exclusively within the body of @foo, then alias(@G, %p)
>>> can be NoAlias. From an interprocedural perspective, it can be MustAlias.
>>> 
>> 
>> I don't buy this at all.  The current interface to AA (even for interprocedural clients) is context insensitive.  If you want a path or context-sensitive query interface, you'd need a substantially richer and more complex (aka slower) interface.  DSA provides this sort of interface for example.
> 
> You're right, I was mistaken about recursive functions; that's a class of
> cases which are a lot more complicated and do bring in context sensitivity
> concerns. I've removed these considerations in r107420.

Thanks.  I'm still confused about why we need a separate pass for IPA basicaa...

> However, beyond classic path and context scoping, there's another sense of
> scope that an alias query can have, the scope of a noalias keyword. noalias
> on an argument indicates that argument's relationship with other pointers
> within that function, but it isn't meaningful when considering pointers
> from an interprocedural perspective. An example of this is this is the first
> example I gave above, with alias(@G, %p).

I don't understand this.  The interface provided by AliasAnalysis (which is independent of whether the implementation uses IP information or not) assumes the client is a) asking about relations between globals, or b) is in the context of a function.

In the first example above, alias(@G, %p) is false whether the implementation is single or interprocedural.  Because the client is asking about "p", the query is implicitly scoped to the body of the function.

The AliasAnalysis *interface* has this implicit scoping.  The treatment of noalias *cannot* be semantically different between two different implementations of AliasAnalysis, because the clients haven't changed.  The contract of the AliasAnalysis interface is fixed.

That said, I completely believe that it would be invalid for an interprocedural client to infer properties in a caller of a function with no-alias based on the no-alias properties in the callee.  This is separate from reporting on queries scoped to the callee though.

-Chris
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From clattner at apple.com  Sun Jul  4 12:26:17 2010
From: clattner at apple.com (Chris Lattner)
Date: Sun, 4 Jul 2010 10:26:17 -0700
Subject: [llvm-commits] [llvm] r107013 - in /llvm/trunk:
	include/llvm/Analysis/Passes.h
	lib/Analysis/AliasAnalysisEvaluator.cpp
In-Reply-To: <20100628160137.80B092A6C12C@llvm.org>
References: <20100628160137.80B092A6C12C@llvm.org>
Message-ID: <236E84AB-B19C-4A55-A568-E4A28BEDC89C@apple.com>


On Jun 28, 2010, at 9:01 AM, Dan Gohman wrote:

> Author: djg
> Date: Mon Jun 28 11:01:37 2010
> New Revision: 107013
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=107013&view=rev
> Log:
> Generalize AAEval so that it can be used both per-function and
> interprocedurally. Note that as of this writing, existing alias
> analysis passes are not prepared to be used interprocedurally.

Please revert this patch.  It is a) making the code uglier, and b) not a valid use of the AliasAnalysis interface.  Querying whether two pointers in different functions can alias isn't valid.

-Chris

> 
> Modified:
>    llvm/trunk/include/llvm/Analysis/Passes.h
>    llvm/trunk/lib/Analysis/AliasAnalysisEvaluator.cpp
> 
> Modified: llvm/trunk/include/llvm/Analysis/Passes.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/Passes.h?rev=107013&r1=107012&r2=107013&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Analysis/Passes.h (original)
> +++ llvm/trunk/include/llvm/Analysis/Passes.h Mon Jun 28 11:01:37 2010
> @@ -53,6 +53,13 @@
> 
>   //===--------------------------------------------------------------------===//
>   //
> +  // createInterproceduralAAEvalPass - This pass implements a simple
> +  // N^2 interprocedural alias analysis accuracy evaluator.
> +  //
> +  Pass *createInterproceduralAAEvalPass();
> +
> +  //===--------------------------------------------------------------------===//
> +  //
>   // createNoAAPass - This pass implements a "I don't know" alias analysis.
>   //
>   ImmutablePass *createNoAAPass();
> 
> Modified: llvm/trunk/lib/Analysis/AliasAnalysisEvaluator.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasAnalysisEvaluator.cpp?rev=107013&r1=107012&r2=107013&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Analysis/AliasAnalysisEvaluator.cpp (original)
> +++ llvm/trunk/lib/Analysis/AliasAnalysisEvaluator.cpp Mon Jun 28 11:01:37 2010
> @@ -21,11 +21,11 @@
> #include "llvm/DerivedTypes.h"
> #include "llvm/Function.h"
> #include "llvm/Instructions.h"
> +#include "llvm/Module.h"
> #include "llvm/Pass.h"
> #include "llvm/Analysis/Passes.h"
> #include "llvm/Analysis/AliasAnalysis.h"
> #include "llvm/Assembly/Writer.h"
> -#include "llvm/Target/TargetData.h"
> #include "llvm/Support/Debug.h"
> #include "llvm/Support/InstIterator.h"
> #include "llvm/Support/CommandLine.h"
> @@ -45,20 +45,21 @@
> static cl::opt<bool> PrintModRef("print-modref", cl::ReallyHidden);
> 
> namespace {
> -  class AAEval : public FunctionPass {
> +  /// AAEval - Base class for exhaustive alias analysis evaluators.
> +  class AAEval {
> +  protected:
>     unsigned NoAlias, MayAlias, MustAlias;
>     unsigned NoModRef, Mod, Ref, ModRef;
> 
> -  public:
> -    static char ID; // Pass identification, replacement for typeid
> -    AAEval() : FunctionPass(&ID) {}
> +    SetVector<Value *> Pointers;
> +    SetVector<CallSite> CallSites;
> 
> -    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
> +    void getAnalysisUsage(AnalysisUsage &AU) const {
>       AU.addRequired<AliasAnalysis>();
>       AU.setPreservesAll();
>     }
> 
> -    bool doInitialization(Module &M) {
> +    void doInitialization(Module &M) {
>       NoAlias = MayAlias = MustAlias = 0;
>       NoModRef = Mod = Ref = ModRef = 0;
> 
> @@ -66,19 +67,85 @@
>         PrintNoAlias = PrintMayAlias = PrintMustAlias = true;
>         PrintNoModRef = PrintMod = PrintRef = PrintModRef = true;
>       }
> +    }
> +
> +    void runOnFunction(Function &F);
> +    void evaluate(AliasAnalysis *AA, Module *M);
> +    void doFinalization(Module &M);
> +  };
> +
> +  class FunctionAAEval : public FunctionPass, AAEval {
> +  public:
> +    static char ID; // Pass identification, replacement for typeid
> +    FunctionAAEval() : FunctionPass(&ID) {}
> +
> +    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
> +      return AAEval::getAnalysisUsage(AU);
> +    }
> +
> +    virtual bool doInitialization(Module &M) {
> +      AAEval::doInitialization(M);
> +      return false;
> +    }
> +
> +    virtual bool runOnFunction(Function &F) {
> +      AAEval::runOnFunction(F);
> +
> +      if (PrintNoAlias || PrintMayAlias || PrintMustAlias ||
> +          PrintNoModRef || PrintMod || PrintRef || PrintModRef)
> +        errs() << "Function: " << F.getName() << ": " << Pointers.size()
> +               << " pointers, " << CallSites.size() << " call sites\n";
> +
> +      AAEval::evaluate(&getAnalysis<AliasAnalysis>(), F.getParent());
> +      return false;
> +    }
> +
> +    virtual bool doFinalization(Module &M) {
> +      AAEval::doFinalization(M);
>       return false;
>     }
> +  };
> +
> +  class InterproceduralAAEval : public ModulePass, AAEval {
> +  public:
> +    static char ID; // Pass identification, replacement for typeid
> +    InterproceduralAAEval() : ModulePass(&ID) {}
> +
> +    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
> +      return AAEval::getAnalysisUsage(AU);
> +    }
> +
> +    virtual bool runOnModule(Module &M) {
> +      AAEval::doInitialization(M);
> +      for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I)
> +        AAEval::runOnFunction(*I);
> +
> +      if (PrintNoAlias || PrintMayAlias || PrintMustAlias ||
> +          PrintNoModRef || PrintMod || PrintRef || PrintModRef)
> +        errs() << "Module: " << Pointers.size()
> +               << " pointers, " << CallSites.size() << " call sites\n";
> 
> -    bool runOnFunction(Function &F);
> -    bool doFinalization(Module &M);
> +      AAEval::evaluate(&getAnalysis<AliasAnalysis>(), &M);
> +      AAEval::doFinalization(M);
> +      return false;
> +    }
>   };
> }
> 
> -char AAEval::ID = 0;
> -static RegisterPass<AAEval>
> +char FunctionAAEval::ID = 0;
> +static RegisterPass<FunctionAAEval>
> X("aa-eval", "Exhaustive Alias Analysis Precision Evaluator", false, true);
> 
> -FunctionPass *llvm::createAAEvalPass() { return new AAEval(); }
> +FunctionPass *llvm::createAAEvalPass() { return new FunctionAAEval(); }
> +
> +char InterproceduralAAEval::ID = 0;
> +static RegisterPass<InterproceduralAAEval>
> +Y("interprocedural-aa-eval",
> +  "Exhaustive Interprocedural Alias Analysis Precision Evaluator", false, true);
> +
> +Pass *llvm::createInterproceduralAAEvalPass() {
> +  return new InterproceduralAAEval();
> +}
> 
> static void PrintResults(const char *Msg, bool P, const Value *V1,
>                          const Value *V2, const Module *M) {
> @@ -113,12 +180,7 @@
>       && !isa<ConstantPointerNull>(V);
> }
> 
> -bool AAEval::runOnFunction(Function &F) {
> -  AliasAnalysis &AA = getAnalysis<AliasAnalysis>();
> -
> -  SetVector<Value *> Pointers;
> -  SetVector<CallSite> CallSites;
> -
> +void AAEval::runOnFunction(Function &F) {
>   for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I)
>     if (I->getType()->isPointerTy())    // Add all pointer arguments.
>       Pointers.insert(I);
> @@ -148,33 +210,31 @@
> 
>     if (CS.getInstruction()) CallSites.insert(CS);
>   }
> +}
> 
> -  if (PrintNoAlias || PrintMayAlias || PrintMustAlias ||
> -      PrintNoModRef || PrintMod || PrintRef || PrintModRef)
> -    errs() << "Function: " << F.getName() << ": " << Pointers.size()
> -           << " pointers, " << CallSites.size() << " call sites\n";
> +void AAEval::evaluate(AliasAnalysis *AA, Module *M) {
> 
>   // iterate over the worklist, and run the full (n^2)/2 disambiguations
>   for (SetVector<Value *>::iterator I1 = Pointers.begin(), E = Pointers.end();
>        I1 != E; ++I1) {
>     unsigned I1Size = ~0u;
>     const Type *I1ElTy = cast<PointerType>((*I1)->getType())->getElementType();
> -    if (I1ElTy->isSized()) I1Size = AA.getTypeStoreSize(I1ElTy);
> +    if (I1ElTy->isSized()) I1Size = AA->getTypeStoreSize(I1ElTy);
> 
>     for (SetVector<Value *>::iterator I2 = Pointers.begin(); I2 != I1; ++I2) {
>       unsigned I2Size = ~0u;
>       const Type *I2ElTy =cast<PointerType>((*I2)->getType())->getElementType();
> -      if (I2ElTy->isSized()) I2Size = AA.getTypeStoreSize(I2ElTy);
> +      if (I2ElTy->isSized()) I2Size = AA->getTypeStoreSize(I2ElTy);
> 
> -      switch (AA.alias(*I1, I1Size, *I2, I2Size)) {
> +      switch (AA->alias(*I1, I1Size, *I2, I2Size)) {
>       case AliasAnalysis::NoAlias:
> -        PrintResults("NoAlias", PrintNoAlias, *I1, *I2, F.getParent());
> +        PrintResults("NoAlias", PrintNoAlias, *I1, *I2, M);
>         ++NoAlias; break;
>       case AliasAnalysis::MayAlias:
> -        PrintResults("MayAlias", PrintMayAlias, *I1, *I2, F.getParent());
> +        PrintResults("MayAlias", PrintMayAlias, *I1, *I2, M);
>         ++MayAlias; break;
>       case AliasAnalysis::MustAlias:
> -        PrintResults("MustAlias", PrintMustAlias, *I1, *I2, F.getParent());
> +        PrintResults("MustAlias", PrintMustAlias, *I1, *I2, M);
>         ++MustAlias; break;
>       default:
>         errs() << "Unknown alias query result!\n";
> @@ -191,20 +251,20 @@
>          V != Ve; ++V) {
>       unsigned Size = ~0u;
>       const Type *ElTy = cast<PointerType>((*V)->getType())->getElementType();
> -      if (ElTy->isSized()) Size = AA.getTypeStoreSize(ElTy);
> +      if (ElTy->isSized()) Size = AA->getTypeStoreSize(ElTy);
> 
> -      switch (AA.getModRefInfo(*C, *V, Size)) {
> +      switch (AA->getModRefInfo(*C, *V, Size)) {
>       case AliasAnalysis::NoModRef:
> -        PrintModRefResults("NoModRef", PrintNoModRef, I, *V, F.getParent());
> +        PrintModRefResults("NoModRef", PrintNoModRef, I, *V, M);
>         ++NoModRef; break;
>       case AliasAnalysis::Mod:
> -        PrintModRefResults("     Mod", PrintMod, I, *V, F.getParent());
> +        PrintModRefResults("     Mod", PrintMod, I, *V, M);
>         ++Mod; break;
>       case AliasAnalysis::Ref:
> -        PrintModRefResults("     Ref", PrintRef, I, *V, F.getParent());
> +        PrintModRefResults("     Ref", PrintRef, I, *V, M);
>         ++Ref; break;
>       case AliasAnalysis::ModRef:
> -        PrintModRefResults("  ModRef", PrintModRef, I, *V, F.getParent());
> +        PrintModRefResults("  ModRef", PrintModRef, I, *V, M);
>         ++ModRef; break;
>       default:
>         errs() << "Unknown alias query result!\n";
> @@ -212,7 +272,8 @@
>     }
>   }
> 
> -  return false;
> +  Pointers.clear();
> +  CallSites.clear();
> }
> 
> static void PrintPercent(unsigned Num, unsigned Sum) {
> @@ -220,7 +281,7 @@
>          << ((Num*1000ULL/Sum) % 10) << "%)\n";
> }
> 
> -bool AAEval::doFinalization(Module &M) {
> +void AAEval::doFinalization(Module &M) {
>   unsigned AliasSum = NoAlias + MayAlias + MustAlias;
>   errs() << "===== Alias Analysis Evaluator Report =====\n";
>   if (AliasSum == 0) {
> @@ -256,6 +317,4 @@
>            << NoModRef*100/ModRefSum  << "%/" << Mod*100/ModRefSum << "%/"
>            << Ref*100/ModRefSum << "%/" << ModRef*100/ModRefSum << "%\n";
>   }
> -
> -  return false;
> }
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits




From clattner at apple.com  Sun Jul  4 12:27:03 2010
From: clattner at apple.com (Chris Lattner)
Date: Sun, 4 Jul 2010 10:27:03 -0700
Subject: [llvm-commits] [llvm] r107432
	-	/llvm/trunk/include/llvm/Instructions.h
In-Reply-To: <20100701214641.BF4082A6C12C@llvm.org>
References: <20100701214641.BF4082A6C12C@llvm.org>
Message-ID: <59702091-161E-48DC-B001-6B196C7993FF@apple.com>

Alright, but please stay in 80 columns.

-Chris

On Jul 1, 2010, at 2:46 PM, Gabor Greif wrote:

> Author: ggreif
> Date: Thu Jul  1 16:46:41 2010
> New Revision: 107432
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=107432&view=rev
> Log:
> evil hack to coerce external users (projects)
> to update their code to high-level interfaces
> 
> If you get compile errors in your project
> please update your code according to the
> comments.
> 
> This is a re-commit of r107396 which causes
> compile errors for the indicated usage patterns
> instead of link errors (which are less easy to
> fix because of missing source location).
> 
> If you get compile errors please perform
> following functionally equivalent transformations:
>  - getOperand(0)  --->  getCalledValue()
>  - setOperand(0, V)  --->  setCalledFunction(V)
> 
> This will make your code more future-proof
> and avoid potentially hard-to-debug bugs.
> 
> please refer to this thread on llvm-dev:
> 
> <http://groups.google.com/group/llvm-dev/browse_thread/thread/64650cf343b28271>
> 
> 
> Modified:
>    llvm/trunk/include/llvm/Instructions.h
> 
> Modified: llvm/trunk/include/llvm/Instructions.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=107432&r1=107431&r2=107432&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Instructions.h (original)
> +++ llvm/trunk/include/llvm/Instructions.h Thu Jul  1 16:46:41 2010
> @@ -948,6 +948,17 @@
>   Value *getArgOperand(unsigned i) const { return getOperand(i + ArgOffset); }
>   void setArgOperand(unsigned i, Value *v) { setOperand(i + ArgOffset, v); }
> 
> +  /// Provide compile-time errors for accessing operand 0
> +  /// @deprecated these will go away soon
> +  /// @detail see below comments and update your code to high-level interfaces
> +  ///    - getOperand(0)  --->  getCalledValue()
> +  ///    - setOperand(0, V)  --->  setCalledFunction(V)
> +  ///
> +private:
> +  void getOperand(void*); // NO IMPL ---> use getCalledValue (or possibly getCalledFunction) instead
> +  void setOperand(void*, Value*); // NO IMPL ---> use setCalledFunction instead
> +public:
> +
>   /// getCallingConv/setCallingConv - Get or set the calling convention of this
>   /// function call.
>   CallingConv::ID getCallingConv() const {
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits




From sabre at nondot.org  Sun Jul  4 12:36:43 2010
From: sabre at nondot.org (Chris Lattner)
Date: Sun, 04 Jul 2010 17:36:43 -0000
Subject: [llvm-commits] [llvm] r107587 - /llvm/trunk/docs/Passes.html
Message-ID: <20100704173644.0A6A22A6C12C@llvm.org>

Author: lattner
Date: Sun Jul  4 12:36:43 2010
New Revision: 107587

URL: http://llvm.org/viewvc/llvm-project?rev=107587&view=rev
Log:
indmemrem and lowerallocs are gone.

Modified:
    llvm/trunk/docs/Passes.html

Modified: llvm/trunk/docs/Passes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/Passes.html?rev=107587&r1=107586&r2=107587&view=diff
==============================================================================
--- llvm/trunk/docs/Passes.html (original)
+++ llvm/trunk/docs/Passes.html Sun Jul  4 12:36:43 2010
@@ -128,7 +128,6 @@
 <tr><td><a href="#globaldce">-globaldce</a></td><td>Dead Global Elimination</td></tr>
 <tr><td><a href="#globalopt">-globalopt</a></td><td>Global Variable Optimizer</td></tr>
 <tr><td><a href="#gvn">-gvn</a></td><td>Global Value Numbering</td></tr>
-<tr><td><a href="#indmemrem">-indmemrem</a></td><td>Indirect Malloc and Free Removal</td></tr>
 <tr><td><a href="#indvars">-indvars</a></td><td>Canonicalize Induction Variables</td></tr>
 <tr><td><a href="#inline">-inline</a></td><td>Function Integration/Inlining</td></tr>
 <tr><td><a href="#insert-block-profiling">-insert-block-profiling</a></td><td>Insert instrumentation for block profiling</td></tr>
@@ -152,7 +151,6 @@
 <tr><td><a href="#loop-unroll">-loop-unroll</a></td><td>Unroll loops</td></tr>
 <tr><td><a href="#loop-unswitch">-loop-unswitch</a></td><td>Unswitch loops</td></tr>
 <tr><td><a href="#loopsimplify">-loopsimplify</a></td><td>Canonicalize natural loops</td></tr>
-<tr><td><a href="#lowerallocs">-lowerallocs</a></td><td>Lower allocations from instructions to calls</td></tr>
 <tr><td><a href="#lowerinvoke">-lowerinvoke</a></td><td>Lower invoke and unwind, for unwindless code generators</td></tr>
 <tr><td><a href="#lowersetjmp">-lowersetjmp</a></td><td>Lower Set Jump</td></tr>
 <tr><td><a href="#lowerswitch">-lowerswitch</a></td><td>Lower SwitchInst's to branches</td></tr>
@@ -831,23 +829,6 @@
 
 <!-------------------------------------------------------------------------- -->
 <div class="doc_subsection">
-  <a name="indmemrem">Indirect Malloc and Free Removal</a>
-</div>
-<div class="doc_text">
-  <p>
-  This pass finds places where memory allocation functions may escape into
-  indirect land.  Some transforms are much easier (aka possible) only if free 
-  or malloc are not called indirectly.
-  </p>
-  
-  <p>
-  Thus find places where the address of memory functions are taken and construct
-  bounce functions with direct calls of those functions.
-  </p>
-</div>
-
-<!-------------------------------------------------------------------------- -->
-<div class="doc_subsection">
   <a name="indvars">Canonicalize Induction Variables</a>
 </div>
 <div class="doc_text">
@@ -1329,22 +1310,6 @@
 
 <!-------------------------------------------------------------------------- -->
 <div class="doc_subsection">
-  <a name="lowerallocs">Lower allocations from instructions to calls</a>
-</div>
-<div class="doc_text">
-  <p>
-  Turn <tt>malloc</tt> and <tt>free</tt> instructions into <tt>@malloc</tt> and
-  <tt>@free</tt> calls.
-  </p>
-
-  <p>
-  This is a target-dependent tranformation because it depends on the size of
-  data types and alignment constraints.
-  </p>
-</div>
-
-<!-------------------------------------------------------------------------- -->
-<div class="doc_subsection">
   <a name="lowerinvoke">Lower invoke and unwind, for unwindless code generators</a>
 </div>
 <div class="doc_text">




From kledzik at apple.com  Sun Jul  4 13:29:01 2010
From: kledzik at apple.com (Nick Kledzik)
Date: Sun, 04 Jul 2010 18:29:01 -0000
Subject: [llvm-commits] [compiler-rt] r107588 - in /compiler-rt/trunk:
 lib/arm/Makefile.mk make/platform/darwin_bni.mk make/platform/darwin_fat.mk
Message-ID: <20100704182901.3AB472A6C12C@llvm.org>

Author: kledzik
Date: Sun Jul  4 13:29:01 2010
New Revision: 107588

URL: http://llvm.org/viewvc/llvm-project?rev=107588&view=rev
Log:
fix arvm5 builds

Modified:
    compiler-rt/trunk/lib/arm/Makefile.mk
    compiler-rt/trunk/make/platform/darwin_bni.mk
    compiler-rt/trunk/make/platform/darwin_fat.mk

Modified: compiler-rt/trunk/lib/arm/Makefile.mk
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/Makefile.mk?rev=107588&r1=107587&r2=107588&view=diff
==============================================================================
--- compiler-rt/trunk/lib/arm/Makefile.mk (original)
+++ compiler-rt/trunk/lib/arm/Makefile.mk Sun Jul  4 13:29:01 2010
@@ -8,7 +8,7 @@
 #===------------------------------------------------------------------------===#
 
 SubDirs := 
-OnlyArchs := armv6 armv7
+OnlyArchs := armv5 armv6 armv7
 
 AsmSources := $(foreach file,$(wildcard $(Dir)/*.S),$(notdir $(file)))
 Sources := $(foreach file,$(wildcard $(Dir)/*.c),$(notdir $(file)))

Modified: compiler-rt/trunk/make/platform/darwin_bni.mk
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/make/platform/darwin_bni.mk?rev=107588&r1=107587&r2=107588&view=diff
==============================================================================
--- compiler-rt/trunk/make/platform/darwin_bni.mk (original)
+++ compiler-rt/trunk/make/platform/darwin_bni.mk Sun Jul  4 13:29:01 2010
@@ -52,6 +52,19 @@
                 mulvti3 mulxc3 negti2 negvti2 parityti2 \
                 popcountti2 powixf2 subvti3 ucmpti2 udivmodti4 \
                 udivti3 umodti3 clear_cache enable_execute_stack
+FUNCTIONS.armv5 := $(FUNCTIONS) \
+                adddf3 addsf3 bswapdi2 bswapsi2  \
+                comparedf2 comparesf2 extendsfdf2 \
+                divdf3 divsf3 \
+                fixdfsi fixsfsi fixunsdfsi fixunssfsi \
+                floatsidf floatsisf floatunsidf floatunsisf \
+                muldf3 mulsf3 \
+                negdf2 negsf2 \
+                truncdfsf2  \
+                modsi3 umodsi3 udivsi3 divsi3 \
+                switch8 switchu8 switch16 switch32 \
+                sync_synchronize 
+			
 FUNCTIONS.armv6 := $(FUNCTIONS) \
                 adddf3vfp addsf3vfp bswapdi2 bswapsi2 divdf3vfp \
                 divsf3vfp eqdf2vfp eqsf2vfp extendsfdf2vfp \

Modified: compiler-rt/trunk/make/platform/darwin_fat.mk
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/make/platform/darwin_fat.mk?rev=107588&r1=107587&r2=107588&view=diff
==============================================================================
--- compiler-rt/trunk/make/platform/darwin_fat.mk (original)
+++ compiler-rt/trunk/make/platform/darwin_fat.mk Sun Jul  4 13:29:01 2010
@@ -47,6 +47,7 @@
 FUNCTIONS.i386 := $(CommonFunctions) $(ArchFunctions.i386)
 FUNCTIONS.ppc := $(CommonFunctions) $(ArchFunctions.ppc)
 FUNCTIONS.x86_64 := $(CommonFunctions) $(ArchFunctions.x86_64)
+FUNCTIONS.armv5 := $(CommonFunctions) $(ArchFunctions.armv5)
 FUNCTIONS.armv6 := $(CommonFunctions) $(ArchFunctions.armv6)
 FUNCTIONS.armv7 := $(CommonFunctions) $(ArchFunctions.armv7)
 




From kledzik at apple.com  Sun Jul  4 13:29:23 2010
From: kledzik at apple.com (Nick Kledzik)
Date: Sun, 04 Jul 2010 18:29:23 -0000
Subject: [llvm-commits] [compiler-rt] r107589 -
	/compiler-rt/trunk/make/AppleBI.mk
Message-ID: <20100704182923.DE36F2A6C12C@llvm.org>

Author: kledzik
Date: Sun Jul  4 13:29:23 2010
New Revision: 107589

URL: http://llvm.org/viewvc/llvm-project?rev=107589&view=rev
Log:
fix install location

Modified:
    compiler-rt/trunk/make/AppleBI.mk

Modified: compiler-rt/trunk/make/AppleBI.mk
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/make/AppleBI.mk?rev=107589&r1=107588&r2=107589&view=diff
==============================================================================
--- compiler-rt/trunk/make/AppleBI.mk (original)
+++ compiler-rt/trunk/make/AppleBI.mk Sun Jul  4 13:29:23 2010
@@ -15,7 +15,7 @@
 ifeq (,$(SDKROOT))
 	INSTALL_TARGET = install-MacOSX
 else
-	INSTALL_TARGET = install-iPhoneOS
+	INSTALL_TARGET = install-iOS
 endif
 
 
@@ -63,13 +63,13 @@
 
 
 # Copy results to DSTROOT.
-install-iPhoneOS: $(SYMROOT)/libcompiler_rt.a $(SYMROOT)/libcompiler_rt-static.a 
-	mkdir -p $(DSTROOT)/$(SDKROOT)/usr/local/lib/libgcc
+install-iOS: $(SYMROOT)/libcompiler_rt.a $(SYMROOT)/libcompiler_rt-static.a 
+	mkdir -p $(DSTROOT)/usr/local/lib/libgcc
 	cp $(SYMROOT)/libcompiler_rt.a \
-				    $(DSTROOT)/$(SDKROOT)/usr/local/lib/libgcc/libcompiler_rt.a
-	mkdir -p $(DSTROOT)/$(SDKROOT)/usr/local/
+				    $(DSTROOT)/usr/local/lib/libgcc/libcompiler_rt.a
+	mkdir -p $(DSTROOT)/usr/local/
 	cp $(SYMROOT)/libcompiler_rt-static.a  \
-				    $(DSTROOT)/$(SDKROOT)/usr/local/lib/libcompiler_rt-static.a
+				    $(DSTROOT)/usr/local/lib/libcompiler_rt-static.a
 
 
 # Rule to make fat archive




From kledzik at apple.com  Sun Jul  4 13:45:21 2010
From: kledzik at apple.com (Nick Kledzik)
Date: Sun, 04 Jul 2010 18:45:21 -0000
Subject: [llvm-commits] [compiler-rt] r107590 -
	/compiler-rt/tags/Apple/Libcompiler_rt-8/
Message-ID: <20100704184521.4C7A52A6C12C@llvm.org>

Author: kledzik
Date: Sun Jul  4 13:45:21 2010
New Revision: 107590

URL: http://llvm.org/viewvc/llvm-project?rev=107590&view=rev
Log:
Libcompiler_rt-8

Added:
    compiler-rt/tags/Apple/Libcompiler_rt-8/
      - copied from r107589, compiler-rt/trunk/



From evan.cheng at apple.com  Sun Jul  4 13:52:05 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Sun, 04 Jul 2010 18:52:05 -0000
Subject: [llvm-commits] [llvm] r107591 - in /llvm/trunk/lib/CodeGen:
 MachineFunction.cpp SelectionDAG/SelectionDAG.cpp
Message-ID: <20100704185205.4F2E42A6C12C@llvm.org>

Author: evancheng
Date: Sun Jul  4 13:52:05 2010
New Revision: 107591

URL: http://llvm.org/viewvc/llvm-project?rev=107591&view=rev
Log:
Infer alignments of fixed frame objects when they are constructed. This ensures remat'ed loads from fixed slots have the right alignments.

Modified:
    llvm/trunk/lib/CodeGen/MachineFunction.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Modified: llvm/trunk/lib/CodeGen/MachineFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFunction.cpp?rev=107591&r1=107590&r2=107591&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineFunction.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineFunction.cpp Sun Jul  4 13:52:05 2010
@@ -440,7 +440,13 @@
 int MachineFrameInfo::CreateFixedObject(uint64_t Size, int64_t SPOffset,
                                         bool Immutable) {
   assert(Size != 0 && "Cannot allocate zero size fixed stack objects!");
-  Objects.insert(Objects.begin(), StackObject(Size, 1, SPOffset, Immutable,
+  // The alignment of the frame index can be determined from its offset from
+  // the incoming frame position.  If the frame object is at offset 32 and
+  // the stack is guaranteed to be 16-byte aligned, then we know that the
+  // object is 16-byte aligned.
+  unsigned StackAlign = TFI.getStackAlignment();
+  unsigned Align = MinAlign(SPOffset, StackAlign);
+  Objects.insert(Objects.begin(), StackObject(Size, Align, SPOffset, Immutable,
                                               /*isSS*/false));
   return -++NumFixedObjects;
 }

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=107591&r1=107590&r2=107591&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Sun Jul  4 13:52:05 2010
@@ -6262,23 +6262,6 @@
     const MachineFrameInfo &MFI = *getMachineFunction().getFrameInfo();
     unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx),
                                     FrameOffset);
-    if (MFI.isFixedObjectIndex(FrameIdx)) {
-      int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx) + FrameOffset;
-
-      // The alignment of the frame index can be determined from its offset from
-      // the incoming frame position.  If the frame object is at offset 32 and
-      // the stack is guaranteed to be 16-byte aligned, then we know that the
-      // object is 16-byte aligned.
-      unsigned StackAlign = getTarget().getFrameInfo()->getStackAlignment();
-      unsigned Align = MinAlign(ObjectOffset, StackAlign);
-
-      // Finally, the frame object itself may have a known alignment.  Factor
-      // the alignment + offset into a new alignment.  For example, if we know
-      // the FI is 8 byte aligned, but the pointer is 4 off, we really have a
-      // 4-byte alignment of the resultant pointer.  Likewise align 4 + 4-byte
-      // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc.
-      return std::max(Align, FIInfoAlign);
-    }
     return FIInfoAlign;
   }
 




From stoklund at 2pi.dk  Sun Jul  4 14:08:07 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Sun, 4 Jul 2010 12:08:07 -0700
Subject: [llvm-commits] [llvm] r107529 - in /llvm/trunk:
	include/llvm/CodeGen/MachineInstr.h include/llvm/Target/Target.td
	include/llvm/Target/TargetOpcodes.h
	lib/CodeGen/LowerSubregs.cpp utils/TableGen/CodeGenTarget.cpp
In-Reply-To: <762A630F-61FD-4DE1-993F-13A0AE1BFC4E@apple.com>
References: <20100702222950.DC0692A6C12C@llvm.org>
	<762A630F-61FD-4DE1-993F-13A0AE1BFC4E@apple.com>
Message-ID: <954B917F-C386-42B9-8561-A38B8608E429@2pi.dk>


On Jul 4, 2010, at 10:15 AM, Chris Lattner wrote:

> 
> On Jul 2, 2010, at 3:29 PM, Jakob Stoklund Olesen wrote:
> 
>> Author: stoklund
>> Date: Fri Jul  2 17:29:50 2010
>> New Revision: 107529
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=107529&view=rev
>> Log:
>> Add a new target independent COPY instruction and code to lower it.
>> 
>> The COPY instruction is intended to replace the target specific copy
>> instructions for virtual registers as well as the EXTRACT_SUBREG and
>> INSERT_SUBREG instructions in MachineFunctions. It won't we used in a selection
>> DAG.
>> 
>> COPY is lowered to native register copies by LowerSubregs.
> 
> Very interesting!  This means that the early code generator won't need to call the virtual method to determine if something is a copy?

Yes. I have clocked X86::isMoveInstr at around 5% CPU for both the fast register allocator and the coalescer.

There is a longer rationale here: http://lists.cs.uiuc.edu/pipermail/llvmdev/2010-June/032448.html

>  This will also make targets that forget to implement the 'is copy' hook generate better code by default.

Yes. You also get foldMemoryOperand(COPY) --> storeToStackSlot / loadFromStackSlot for free. That is the only folding PowerPC does, for instance.

I also intend to change the copyRegToReg hook to only allow physical register arguments, and eliminate the register class arguments.

> This sounds like a great plan to me.  What is the migration plan for existing targets and existing codegen passes?  Do they need to do anything?

First I am going to emit EXTRACT_SUBREG as COPY so that instruction becomes selection DAG only. This is fairly easy since both are lowered by LowerSubregs. The problem is dealing with the FIXME in SimpleRegisterCoalescing::JoinIntervals regarding physical register live intervals.

Second, INSERT_SUBREG is converted to COPY by TwoAddressInstructionPass. It is still needed while the machine code is in SSA form.

Then it is a simple issue of replacing copyRegToReg with COPY instructions, and TII::isMoveInstr() with MI->isCopy.

Existing codegen passes need to use isCopy() instead of isExtractSubreg/isInsertSubreg/isMoveInstr. I am migrating  them by first adding isCopy, and later removing the other checks.

Targets need a new copyRegToReg implementation that takes no register class arguments but requires physical registers. I will start by providing a new version that falls back to the old one, so no target changes will be necessary initially.

>  Do you think the "isMove" target hook can go away completely?

Yes, I think so. It depends on whether it is needed after LowerSubregs. A quick grep says that it isn't.

/jakob


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From kenneth.hoste at elis.ugent.be  Sun Jul  4 14:20:50 2010
From: kenneth.hoste at elis.ugent.be (Kenneth Hoste)
Date: Sun, 4 Jul 2010 21:20:50 +0200
Subject: [llvm-commits] patch that brings Passes.html up to speed with the
	opt tool
Message-ID: <3F08FE96-DB65-40BC-8F9B-617EC47626B2@elis.ugent.be>

Hi,

In attachment a patch that brings the Passes.html documentation up to speed with 
the current state of the opt tool. Some passes that are no longer available are removed,
a lot of passes are added, with appropriate documentation taken from the respective source files.

(I don't have commit access, so if this patch is approved, someone will have to commit it for me)

greetings,

Kenneth

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From isanbard at gmail.com  Sun Jul  4 15:50:33 2010
From: isanbard at gmail.com (Bill Wendling)
Date: Sun, 4 Jul 2010 13:50:33 -0700
Subject: [llvm-commits] [llvm-gcc-4.2] r107439 - in
	/llvm-gcc-4.2/trunk/gcc: llvm-backend.cpp tree.h varasm.c
In-Reply-To: <D773ECC1-804A-40DE-99AC-A39CF3DAE774@apple.com>
References: <20100701223732.320262A6C12C@llvm.org>
	<D773ECC1-804A-40DE-99AC-A39CF3DAE774@apple.com>
Message-ID: <07C2C41E-3B20-462C-B56D-342481320181@gmail.com>

On Jul 4, 2010, at 10:10 AM, Chris Lattner wrote:

> On Jul 1, 2010, at 3:37 PM, Bill Wendling wrote:
>> +++ llvm-gcc-4.2/trunk/gcc/tree.h Thu Jul  1 17:37:31 2010
>> @@ -2937,6 +2937,9 @@
>>  (DECL_WITH_VIS_CHECK (NODE)->decl_with_vis.llvm_private_flag)
>> #define DECL_LLVM_LINKER_PRIVATE(NODE) \
>>  (DECL_WITH_VIS_CHECK (NODE)->decl_with_vis.llvm_linker_private_flag)
>> +/* LLVM LOCAL - linker_private_weak <rdar://problem/7907014> */
>> +#define DECL_LLVM_LINKER_PRIVATE_WEAK(NODE) \
>> +  (DECL_WITH_VIS_CHECK (NODE)->decl_with_vis.llvm_linker_private_weak_flag)
>> #endif
>> /* LLVM LOCAL end */
>> 
>> @@ -3080,6 +3083,8 @@
>> /* LLVM LOCAL begin */
>> unsigned llvm_private_flag : 1;
>> unsigned llvm_linker_private_flag : 1;
>> + /* LLVM LOCAL - linker_private_weak <rdar://problem/7907014> */
>> + unsigned llvm_linker_private_weak_flag : 1;
>> /* LLVM LOCAL end */
> 
> Please update the /* 3 unused bits (llvm). */ comment at the end of this struct, thanks Bill!
> 
Already done. :)

-bw





From clattner at apple.com  Sun Jul  4 17:06:44 2010
From: clattner at apple.com (Chris Lattner)
Date: Sun, 4 Jul 2010 15:06:44 -0700
Subject: [llvm-commits] [llvm] r107529 - in /llvm/trunk:
	include/llvm/CodeGen/MachineInstr.h include/llvm/Target/Target.td
	include/llvm/Target/TargetOpcodes.h
	lib/CodeGen/LowerSubregs.cpp utils/TableGen/CodeGenTarget.cpp
In-Reply-To: <954B917F-C386-42B9-8561-A38B8608E429@2pi.dk>
References: <20100702222950.DC0692A6C12C@llvm.org>
	<762A630F-61FD-4DE1-993F-13A0AE1BFC4E@apple.com>
	<954B917F-C386-42B9-8561-A38B8608E429@2pi.dk>
Message-ID: <7EEA3D26-DB63-4A35-B5FB-704B18C8CDCD@apple.com>

On Jul 4, 2010, at 12:08 PM, Jakob Stoklund Olesen wrote:

>>> Add a new target independent COPY instruction and code to lower it.
>> 
>> Very interesting!  This means that the early code generator won't need to call the virtual method to determine if something is a copy?
> 
> Yes. I have clocked X86::isMoveInstr at around 5% CPU for both the fast register allocator and the coalescer.

Yeah, I can imagine it is expensive.  It is also annoying for target authors and is a poor abstraction.  It also makes it hard to read -print-machineinstr dumps on targets like ppc.

> There is a longer rationale here: http://lists.cs.uiuc.edu/pipermail/llvmdev/2010-June/032448.html

Ah, thanks I missed that in the post-wwdc surge :)

> 
>> This will also make targets that forget to implement the 'is copy' hook generate better code by default.
> 
> Yes. You also get foldMemoryOperand(COPY) --> storeToStackSlot / loadFromStackSlot for free. That is the only folding PowerPC does, for instance.

Right.  It is also non-obvious to target authors that they need to add this.

> I also intend to change the copyRegToReg hook to only allow physical register arguments, and eliminate the register class arguments.

Ok.  By virtue of taking vregs, the new COPY instruction will have regclass info.  I assume that COPY will also allow physregs, how will it (or will it?) represent regclass info for physregs?

>> This sounds like a great plan to me.  What is the migration plan for existing targets and existing codegen passes?  Do they need to do anything?
> 
> First I am going to emit EXTRACT_SUBREG as COPY so that instruction becomes selection DAG only. This is fairly easy since both are lowered by LowerSubregs. The problem is dealing with the FIXME in SimpleRegisterCoalescing::JoinIntervals regarding physical register live intervals.
> 
> Second, INSERT_SUBREG is converted to COPY by TwoAddressInstructionPass. It is still needed while the machine code is in SSA form.
> 
> Then it is a simple issue of replacing copyRegToReg with COPY instructions, and TII::isMoveInstr() with MI->isCopy.
> 
> Existing codegen passes need to use isCopy() instead of isExtractSubreg/isInsertSubreg/isMoveInstr. I am migrating  them by first adding isCopy, and later removing the other checks.
> 
> Targets need a new copyRegToReg implementation that takes no register class arguments but requires physical registers. I will start by providing a new version that falls back to the old one, so no target changes will be necessary initially.

This plan sounds great to me!

>> Do you think the "isMove" target hook can go away completely?
> 
> Yes, I think so. It depends on whether it is needed after LowerSubregs. A quick grep says that it isn't.

Nice.  Thanks for working on this,

-Chris


From stoklund at 2pi.dk  Sun Jul  4 17:20:02 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Sun, 4 Jul 2010 15:20:02 -0700
Subject: [llvm-commits] [llvm] r107529 - in /llvm/trunk:
	include/llvm/CodeGen/MachineInstr.h include/llvm/Target/Target.td
	include/llvm/Target/TargetOpcodes.h
	lib/CodeGen/LowerSubregs.cpp utils/TableGen/CodeGenTarget.cpp
In-Reply-To: <7EEA3D26-DB63-4A35-B5FB-704B18C8CDCD@apple.com>
References: <20100702222950.DC0692A6C12C@llvm.org>
	<762A630F-61FD-4DE1-993F-13A0AE1BFC4E@apple.com>
	<954B917F-C386-42B9-8561-A38B8608E429@2pi.dk>
	<7EEA3D26-DB63-4A35-B5FB-704B18C8CDCD@apple.com>
Message-ID: <A7427FA6-FF34-4D30-BEE8-C61440C99E9E@2pi.dk>


On Jul 4, 2010, at 3:06 PM, Chris Lattner wrote:

>> I also intend to change the copyRegToReg hook to only allow physical register arguments, and eliminate the register class arguments.
> 
> Ok.  By virtue of taking vregs, the new COPY instruction will have regclass info.  I assume that COPY will also allow physregs, how will it (or will it?) represent regclass info for physregs?

COPY allows physregs, and it holds no register class information in that case.

Knowing the actual physreg should be enough to choose the proper copy instruction. Only extremely exotic architectures like x86 will have trouble.

When copying an xmm register, x86 will be forced to use a movaps instruction instead of movss/movsd because register class information is not available. I don't think that is going to cause performance problems, but it might depending on the specific microarchitecture.

If a microarchitecture turns up where movaps is not the right choice, I would argue we need to model the xmm scalar sub-registers explicitly.

/jakob

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From sabre at nondot.org  Sun Jul  4 17:56:10 2010
From: sabre at nondot.org (Chris Lattner)
Date: Sun, 04 Jul 2010 22:56:10 -0000
Subject: [llvm-commits] [llvm] r107599 -
	/llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp
Message-ID: <20100704225610.822092A6C12C@llvm.org>

Author: lattner
Date: Sun Jul  4 17:56:10 2010
New Revision: 107599

URL: http://llvm.org/viewvc/llvm-project?rev=107599&view=rev
Log:
indentation

Modified:
    llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp

Modified: llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp?rev=107599&r1=107598&r2=107599&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp Sun Jul  4 17:56:10 2010
@@ -655,8 +655,9 @@
 
 /// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode.
 void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
-                            const MCInst &MI, const TargetInstrDesc &Desc,
-                            raw_ostream &OS) const {
+                                        const MCInst &MI, 
+                                        const TargetInstrDesc &Desc,
+                                        raw_ostream &OS) const {
 
   // Emit the lock opcode prefix as needed.
   if (TSFlags & X86II::LOCK)




From sabre at nondot.org  Sun Jul  4 17:57:10 2010
From: sabre at nondot.org (Chris Lattner)
Date: Sun, 04 Jul 2010 22:57:10 -0000
Subject: [llvm-commits] [llvm] r107600 - in /llvm/trunk:
 lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/v2f32.ll
Message-ID: <20100704225710.94C882A6C12C@llvm.org>

Author: lattner
Date: Sun Jul  4 17:57:10 2010
New Revision: 107600

URL: http://llvm.org/viewvc/llvm-project?rev=107600&view=rev
Log:
fix PR7518 - terrible codegen of <2 x float>, by only marking
v2f32 as legal in 32-bit mode.  It is just as terrible there,
but I just care about x86-64 and noone claims it is valuable
in 64-bit mode.

Added:
    llvm/trunk/test/CodeGen/X86/v2f32.ll
Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=107600&r1=107599&r2=107600&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sun Jul  4 17:57:10 2010
@@ -617,7 +617,12 @@
     addRegisterClass(MVT::v8i8,  X86::VR64RegisterClass, false);
     addRegisterClass(MVT::v4i16, X86::VR64RegisterClass, false);
     addRegisterClass(MVT::v2i32, X86::VR64RegisterClass, false);
-    addRegisterClass(MVT::v2f32, X86::VR64RegisterClass, false);
+    
+    // FIXME: v2f32 isn't an MMX type.  We currently claim that it is legal
+    // because of some ABI issue, but this isn't the right fix.
+    bool IsV2F32Legal = !Subtarget->is64Bit();
+    if (IsV2F32Legal)
+      addRegisterClass(MVT::v2f32, X86::VR64RegisterClass, false);
     addRegisterClass(MVT::v1i64, X86::VR64RegisterClass, false);
 
     setOperationAction(ISD::ADD,                MVT::v8i8,  Legal);
@@ -663,14 +668,17 @@
     AddPromotedToType (ISD::LOAD,               MVT::v4i16, MVT::v1i64);
     setOperationAction(ISD::LOAD,               MVT::v2i32, Promote);
     AddPromotedToType (ISD::LOAD,               MVT::v2i32, MVT::v1i64);
-    setOperationAction(ISD::LOAD,               MVT::v2f32, Promote);
-    AddPromotedToType (ISD::LOAD,               MVT::v2f32, MVT::v1i64);
+    if (IsV2F32Legal) {
+      setOperationAction(ISD::LOAD,             MVT::v2f32, Promote);
+      AddPromotedToType (ISD::LOAD,             MVT::v2f32, MVT::v1i64);
+    }
     setOperationAction(ISD::LOAD,               MVT::v1i64, Legal);
 
     setOperationAction(ISD::BUILD_VECTOR,       MVT::v8i8,  Custom);
     setOperationAction(ISD::BUILD_VECTOR,       MVT::v4i16, Custom);
     setOperationAction(ISD::BUILD_VECTOR,       MVT::v2i32, Custom);
-    setOperationAction(ISD::BUILD_VECTOR,       MVT::v2f32, Custom);
+    if (IsV2F32Legal)
+      setOperationAction(ISD::BUILD_VECTOR,     MVT::v2f32, Custom);
     setOperationAction(ISD::BUILD_VECTOR,       MVT::v1i64, Custom);
 
     setOperationAction(ISD::VECTOR_SHUFFLE,     MVT::v8i8,  Custom);
@@ -678,7 +686,8 @@
     setOperationAction(ISD::VECTOR_SHUFFLE,     MVT::v2i32, Custom);
     setOperationAction(ISD::VECTOR_SHUFFLE,     MVT::v1i64, Custom);
 
-    setOperationAction(ISD::SCALAR_TO_VECTOR,   MVT::v2f32, Custom);
+    if (IsV2F32Legal)
+      setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
     setOperationAction(ISD::SCALAR_TO_VECTOR,   MVT::v8i8,  Custom);
     setOperationAction(ISD::SCALAR_TO_VECTOR,   MVT::v4i16, Custom);
     setOperationAction(ISD::SCALAR_TO_VECTOR,   MVT::v1i64, Custom);
@@ -697,7 +706,8 @@
       setOperationAction(ISD::BIT_CONVERT,        MVT::v8i8,  Custom);
       setOperationAction(ISD::BIT_CONVERT,        MVT::v4i16, Custom);
       setOperationAction(ISD::BIT_CONVERT,        MVT::v2i32, Custom);
-      setOperationAction(ISD::BIT_CONVERT,        MVT::v2f32, Custom);
+      if (IsV2F32Legal)
+        setOperationAction(ISD::BIT_CONVERT,      MVT::v2f32, Custom);
       setOperationAction(ISD::BIT_CONVERT,        MVT::v1i64, Custom);
     }
   }

Added: llvm/trunk/test/CodeGen/X86/v2f32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/v2f32.ll?rev=107600&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/v2f32.ll (added)
+++ llvm/trunk/test/CodeGen/X86/v2f32.ll Sun Jul  4 17:57:10 2010
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=x86-64 -asm-verbose=0 -o - | FileCheck %s
+
+; PR7518
+define void @test1(<2 x float> %Q, float *%P2) nounwind {
+  %a = extractelement <2 x float> %Q, i32 0
+  %b = extractelement <2 x float> %Q, i32 1
+  %c = fadd float %a, %b
+
+  store float %c, float* %P2
+  ret void
+; CHECK: test1:
+; CHECK-NEXT: addss	%xmm1, %xmm0
+; CHECK-NEXT: movss	%xmm0, (%rdi)
+; CHECK-NEXT: ret
+}
+




From sabre at nondot.org  Sun Jul  4 18:07:25 2010
From: sabre at nondot.org (Chris Lattner)
Date: Sun, 04 Jul 2010 23:07:25 -0000
Subject: [llvm-commits] [llvm] r107601 - in /llvm/trunk:
 lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/v2f32.ll
Message-ID: <20100704230725.BF4682A6C12C@llvm.org>

Author: lattner
Date: Sun Jul  4 18:07:25 2010
New Revision: 107601

URL: http://llvm.org/viewvc/llvm-project?rev=107601&view=rev
Log:
Just rip v2f32 support completely out of the X86 backend.  In
the example in the testcase, we now generate:

_test1:                                 ## @test1
	movss	4(%esp), %xmm0
	addss	8(%esp), %xmm0
	movl	12(%esp), %eax
	movss	%xmm0, (%eax)
	ret

instead of:

_test1:                                                     ## @test1
	subl	$20, %esp
	movl	24(%esp), %eax
	movq	%mm0, (%esp)
	movq	%mm0, 8(%esp)
	movss	(%esp), %xmm0
	addss	12(%esp), %xmm0
	movss	%xmm0, (%eax)
	addl	$20, %esp
	ret

v2f32 support did not work reliably because most of the X86
backend didn't know it was legal.  It was apparently only added
to support returning source-level v2f32 values in MMX registers
in x86-32 mode.  If ABI compatibility is important on this
GCC-extended-vector type for some reason, then the frontend
should generate IR that returns v2i32 instead of v2f32.  However,
we generally don't try very hard to be abi compatible on gcc
extended vectors. 


Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/test/CodeGen/X86/v2f32.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=107601&r1=107600&r2=107601&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sun Jul  4 18:07:25 2010
@@ -618,11 +618,6 @@
     addRegisterClass(MVT::v4i16, X86::VR64RegisterClass, false);
     addRegisterClass(MVT::v2i32, X86::VR64RegisterClass, false);
     
-    // FIXME: v2f32 isn't an MMX type.  We currently claim that it is legal
-    // because of some ABI issue, but this isn't the right fix.
-    bool IsV2F32Legal = !Subtarget->is64Bit();
-    if (IsV2F32Legal)
-      addRegisterClass(MVT::v2f32, X86::VR64RegisterClass, false);
     addRegisterClass(MVT::v1i64, X86::VR64RegisterClass, false);
 
     setOperationAction(ISD::ADD,                MVT::v8i8,  Legal);
@@ -668,17 +663,11 @@
     AddPromotedToType (ISD::LOAD,               MVT::v4i16, MVT::v1i64);
     setOperationAction(ISD::LOAD,               MVT::v2i32, Promote);
     AddPromotedToType (ISD::LOAD,               MVT::v2i32, MVT::v1i64);
-    if (IsV2F32Legal) {
-      setOperationAction(ISD::LOAD,             MVT::v2f32, Promote);
-      AddPromotedToType (ISD::LOAD,             MVT::v2f32, MVT::v1i64);
-    }
     setOperationAction(ISD::LOAD,               MVT::v1i64, Legal);
 
     setOperationAction(ISD::BUILD_VECTOR,       MVT::v8i8,  Custom);
     setOperationAction(ISD::BUILD_VECTOR,       MVT::v4i16, Custom);
     setOperationAction(ISD::BUILD_VECTOR,       MVT::v2i32, Custom);
-    if (IsV2F32Legal)
-      setOperationAction(ISD::BUILD_VECTOR,     MVT::v2f32, Custom);
     setOperationAction(ISD::BUILD_VECTOR,       MVT::v1i64, Custom);
 
     setOperationAction(ISD::VECTOR_SHUFFLE,     MVT::v8i8,  Custom);
@@ -686,8 +675,6 @@
     setOperationAction(ISD::VECTOR_SHUFFLE,     MVT::v2i32, Custom);
     setOperationAction(ISD::VECTOR_SHUFFLE,     MVT::v1i64, Custom);
 
-    if (IsV2F32Legal)
-      setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
     setOperationAction(ISD::SCALAR_TO_VECTOR,   MVT::v8i8,  Custom);
     setOperationAction(ISD::SCALAR_TO_VECTOR,   MVT::v4i16, Custom);
     setOperationAction(ISD::SCALAR_TO_VECTOR,   MVT::v1i64, Custom);
@@ -706,8 +693,6 @@
       setOperationAction(ISD::BIT_CONVERT,        MVT::v8i8,  Custom);
       setOperationAction(ISD::BIT_CONVERT,        MVT::v4i16, Custom);
       setOperationAction(ISD::BIT_CONVERT,        MVT::v2i32, Custom);
-      if (IsV2F32Legal)
-        setOperationAction(ISD::BIT_CONVERT,      MVT::v2f32, Custom);
       setOperationAction(ISD::BIT_CONVERT,        MVT::v1i64, Custom);
     }
   }
@@ -4453,7 +4438,7 @@
 }
 
 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
-/// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
+/// ones, or rewriting v4i32 / v2i32 as 2 wide ones if possible. This can be
 /// done when every pair / quad of shuffle mask elements point to elements in
 /// the right sequence. e.g.
 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
@@ -5078,13 +5063,9 @@
 SDValue
 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
   DebugLoc dl = Op.getDebugLoc();
-  if (Op.getValueType() == MVT::v2f32)
-    return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32,
-                       DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32,
-                                   DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
-                                               Op.getOperand(0))));
-
-  if (Op.getValueType() == MVT::v1i64 && Op.getOperand(0).getValueType() == MVT::i64)
+  
+  if (Op.getValueType() == MVT::v1i64 &&
+      Op.getOperand(0).getValueType() == MVT::i64)
     return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
 
   SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));

Modified: llvm/trunk/test/CodeGen/X86/v2f32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/v2f32.ll?rev=107601&r1=107600&r2=107601&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/v2f32.ll (original)
+++ llvm/trunk/test/CodeGen/X86/v2f32.ll Sun Jul  4 18:07:25 2010
@@ -1,4 +1,5 @@
-; RUN: llc < %s -march=x86-64 -asm-verbose=0 -o - | FileCheck %s
+; RUN: llc < %s -march=x86-64 -asm-verbose=0 -o - | FileCheck %s -check-prefix=X64
+; RUN: llc < %s -march=x86 -asm-verbose=0 -o - | FileCheck %s -check-prefix=X32
 
 ; PR7518
 define void @test1(<2 x float> %Q, float *%P2) nounwind {
@@ -8,9 +9,16 @@
 
   store float %c, float* %P2
   ret void
-; CHECK: test1:
-; CHECK-NEXT: addss	%xmm1, %xmm0
-; CHECK-NEXT: movss	%xmm0, (%rdi)
-; CHECK-NEXT: ret
+; X64: test1:
+; X64-NEXT: addss	%xmm1, %xmm0
+; X64-NEXT: movss	%xmm0, (%rdi)
+; X64-NEXT: ret
+
+; X32: test1:
+; X32-NEXT: movss	4(%esp), %xmm0
+; X32-NEXT: addss	8(%esp), %xmm0
+; X32-NEXT: movl	12(%esp), %eax
+; X32-NEXT: movss	%xmm0, (%eax)
+; X32-NEXT: ret
 }
 




From stoklund at 2pi.dk  Sun Jul  4 18:24:23 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Sun, 04 Jul 2010 23:24:23 -0000
Subject: [llvm-commits] [llvm] r107602 -
	/llvm/trunk/lib/CodeGen/MachineInstr.cpp
Message-ID: <20100704232423.36B342A6C12C@llvm.org>

Author: stoklund
Date: Sun Jul  4 18:24:23 2010
New Revision: 107602

URL: http://llvm.org/viewvc/llvm-project?rev=107602&view=rev
Log:
Print symbolic subreg indices on REG_SEQUENCE and INSERT_SUBREG.

Modified:
    llvm/trunk/lib/CodeGen/MachineInstr.cpp

Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=107602&r1=107601&r2=107602&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Sun Jul  4 18:24:23 2010
@@ -1305,6 +1305,8 @@
         OS << "!\"" << MDS->getString() << '\"';
       else
         MO.print(OS, TM);
+    } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
+      OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm());
     } else
       MO.print(OS, TM);
   }




From sabre at nondot.org  Sun Jul  4 22:56:55 2010
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 05 Jul 2010 03:56:55 -0000
Subject: [llvm-commits] [llvm] r107608 -
	/llvm/trunk/test/CodeGen/X86/v2f32.ll
Message-ID: <20100705035655.4C4DC2A6C12C@llvm.org>

Author: lattner
Date: Sun Jul  4 22:56:55 2010
New Revision: 107608

URL: http://llvm.org/viewvc/llvm-project?rev=107608&view=rev
Log:
fix test on non-x86 hosts.

Modified:
    llvm/trunk/test/CodeGen/X86/v2f32.ll

Modified: llvm/trunk/test/CodeGen/X86/v2f32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/v2f32.ll?rev=107608&r1=107607&r2=107608&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/v2f32.ll (original)
+++ llvm/trunk/test/CodeGen/X86/v2f32.ll Sun Jul  4 22:56:55 2010
@@ -1,5 +1,5 @@
 ; RUN: llc < %s -march=x86-64 -asm-verbose=0 -o - | FileCheck %s -check-prefix=X64
-; RUN: llc < %s -march=x86 -asm-verbose=0 -o - | FileCheck %s -check-prefix=X32
+; RUN: llc < %s -mcpu=yonah -march=x86 -asm-verbose=0 -o - | FileCheck %s -check-prefix=X32
 
 ; PR7518
 define void @test1(<2 x float> %Q, float *%P2) nounwind {




From clattner at apple.com  Sun Jul  4 23:29:15 2010
From: clattner at apple.com (Chris Lattner)
Date: Sun, 4 Jul 2010 21:29:15 -0700
Subject: [llvm-commits] [llvm] r107529 - in /llvm/trunk:
	include/llvm/CodeGen/MachineInstr.h include/llvm/Target/Target.td
	include/llvm/Target/TargetOpcodes.h
	lib/CodeGen/LowerSubregs.cpp utils/TableGen/CodeGenTarget.cpp
In-Reply-To: <A7427FA6-FF34-4D30-BEE8-C61440C99E9E@2pi.dk>
References: <20100702222950.DC0692A6C12C@llvm.org>
	<762A630F-61FD-4DE1-993F-13A0AE1BFC4E@apple.com>
	<954B917F-C386-42B9-8561-A38B8608E429@2pi.dk>
	<7EEA3D26-DB63-4A35-B5FB-704B18C8CDCD@apple.com>
	<A7427FA6-FF34-4D30-BEE8-C61440C99E9E@2pi.dk>
Message-ID: <B5DB70ED-E2F8-4DDE-9D6C-97E75631C6E8@apple.com>

On Jul 4, 2010, at 3:20 PM, Jakob Stoklund Olesen wrote:
> On Jul 4, 2010, at 3:06 PM, Chris Lattner wrote:
> 
>>> I also intend to change the copyRegToReg hook to only allow physical register arguments, and eliminate the register class arguments.
>> 
>> Ok.  By virtue of taking vregs, the new COPY instruction will have regclass info.  I assume that COPY will also allow physregs, how will it (or will it?) represent regclass info for physregs?
> 
> COPY allows physregs, and it holds no register class information in that case.

Ok, if it ends up really being important, we can probably figure out some way to extend it :)

> Knowing the actual physreg should be enough to choose the proper copy instruction. Only extremely exotic architectures like x86 will have trouble.

Meh, who uses X86 anymore?

> When copying an xmm register, x86 will be forced to use a movaps instruction instead of movss/movsd because register class information is not available. I don't think that is going to cause performance problems, but it might depending on the specific microarchitecture.

Yeah, I don't know enough about the domain crossing penalties.  They may not affect movs?

> If a microarchitecture turns up where movaps is not the right choice, I would argue we need to model the xmm scalar sub-registers explicitly.

Right.  It seems fairly straight-forward to give COPY a third argument, which would indicate the register class #?

-Chris


From sabre at nondot.org  Sun Jul  4 23:36:27 2010
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 05 Jul 2010 04:36:27 -0000
Subject: [llvm-commits] [llvm] r107609 -
	/llvm/trunk/lib/Target/X86/X86CallingConv.td
Message-ID: <20100705043627.CE6082A6C12C@llvm.org>

Author: lattner
Date: Sun Jul  4 23:36:27 2010
New Revision: 107609

URL: http://llvm.org/viewvc/llvm-project?rev=107609&view=rev
Log:
rip out the various v2f32 "mmx" handling logic, now that 
v2f32 is illegal on x86.

Modified:
    llvm/trunk/lib/Target/X86/X86CallingConv.td

Modified: llvm/trunk/lib/Target/X86/X86CallingConv.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CallingConv.td?rev=107609&r1=107608&r2=107609&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86CallingConv.td (original)
+++ llvm/trunk/lib/Target/X86/X86CallingConv.td Sun Jul  4 23:36:27 2010
@@ -42,7 +42,7 @@
 
   // MMX vector types are always returned in MM0. If the target doesn't have
   // MM0, it doesn't support these vector types.
-  CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32], CCAssignToReg<[MM0]>>,
+  CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToReg<[MM0]>>,
 
   // Long double types are always returned in ST0 (even with SSE).
   CCIfType<[f80], CCAssignToReg<[ST0, ST1]>>
@@ -89,7 +89,7 @@
   // returned in RAX. This disagrees with ABI documentation but is bug
   // compatible with gcc.
   CCIfType<[v1i64], CCAssignToReg<[RAX]>>,
-  CCIfType<[v8i8, v4i16, v2i32, v2f32], CCAssignToReg<[XMM0, XMM1]>>,
+  CCIfType<[v8i8, v4i16, v2i32], CCAssignToReg<[XMM0, XMM1]>>,
   CCDelegateTo<RetCC_X86Common>
 ]>;
 
@@ -155,7 +155,7 @@
 
   // The first 8 MMX (except for v1i64) vector arguments are passed in XMM
   // registers on Darwin.
-  CCIfType<[v8i8, v4i16, v2i32, v2f32],
+  CCIfType<[v8i8, v4i16, v2i32],
             CCIfSubtarget<"isTargetDarwin()",
             CCIfSubtarget<"hasSSE2()",
             CCPromoteToType<v2i64>>>>,
@@ -177,7 +177,7 @@
   CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
 
   // __m64 vectors get 8-byte stack slots that are 8-byte aligned.
-  CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32], CCAssignToStack<8, 8>>
+  CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 8>>
 ]>;
 
 // Calling convention used on Win64
@@ -195,7 +195,7 @@
   CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCPassIndirect<i64>>,
 
   // The first 4 MMX vector arguments are passed in GPRs.
-  CCIfType<[v8i8, v4i16, v2i32, v1i64, v2f32],
+  CCIfType<[v8i8, v4i16, v2i32, v1i64],
            CCBitConvertToType<i64>>,
 
   // The first 4 integer arguments are passed in integer registers.
@@ -254,7 +254,7 @@
 
   // The first 3 __m64 (except for v1i64) vector arguments are passed in mmx
   // registers if the call is not a vararg call.
-  CCIfNotVarArg<CCIfType<[v8i8, v4i16, v2i32, v2f32],
+  CCIfNotVarArg<CCIfType<[v8i8, v4i16, v2i32],
                 CCAssignToReg<[MM0, MM1, MM2]>>>,
 
   // Integer/Float values get stored in stack slots that are 4 bytes in




From sabre at nondot.org  Sun Jul  4 23:38:33 2010
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 05 Jul 2010 04:38:33 -0000
Subject: [llvm-commits] [llvm] r107610 - in /llvm/trunk/lib/Target/X86:
 X86InstrMMX.td X86InstrSSE.td X86RegisterInfo.td
Message-ID: <20100705043833.DCF432A6C12C@llvm.org>

Author: lattner
Date: Sun Jul  4 23:38:33 2010
New Revision: 107610

URL: http://llvm.org/viewvc/llvm-project?rev=107610&view=rev
Log:
rip out even more sporadic v2f32 support.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrMMX.td
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/lib/Target/X86/X86RegisterInfo.td

Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrMMX.td?rev=107610&r1=107609&r2=107610&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrMMX.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrMMX.td Sun Jul  4 23:38:33 2010
@@ -513,30 +513,20 @@
           (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
 def : Pat<(store (v2i32 VR64:$src), addr:$dst),
           (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
-def : Pat<(store (v2f32 VR64:$src), addr:$dst),
-          (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
 def : Pat<(store (v1i64 VR64:$src), addr:$dst),
           (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
 
 // Bit convert.
 def : Pat<(v8i8  (bitconvert (v1i64 VR64:$src))), (v8i8  VR64:$src)>;
 def : Pat<(v8i8  (bitconvert (v2i32 VR64:$src))), (v8i8  VR64:$src)>;
-def : Pat<(v8i8  (bitconvert (v2f32 VR64:$src))), (v8i8  VR64:$src)>;
 def : Pat<(v8i8  (bitconvert (v4i16 VR64:$src))), (v8i8  VR64:$src)>;
 def : Pat<(v4i16 (bitconvert (v1i64 VR64:$src))), (v4i16 VR64:$src)>;
 def : Pat<(v4i16 (bitconvert (v2i32 VR64:$src))), (v4i16 VR64:$src)>;
-def : Pat<(v4i16 (bitconvert (v2f32 VR64:$src))), (v4i16 VR64:$src)>;
 def : Pat<(v4i16 (bitconvert (v8i8  VR64:$src))), (v4i16 VR64:$src)>;
 def : Pat<(v2i32 (bitconvert (v1i64 VR64:$src))), (v2i32 VR64:$src)>;
-def : Pat<(v2i32 (bitconvert (v2f32 VR64:$src))), (v2i32 VR64:$src)>;
 def : Pat<(v2i32 (bitconvert (v4i16 VR64:$src))), (v2i32 VR64:$src)>;
 def : Pat<(v2i32 (bitconvert (v8i8  VR64:$src))), (v2i32 VR64:$src)>;
-def : Pat<(v2f32 (bitconvert (v1i64 VR64:$src))), (v2f32 VR64:$src)>;
-def : Pat<(v2f32 (bitconvert (v2i32 VR64:$src))), (v2f32 VR64:$src)>;
-def : Pat<(v2f32 (bitconvert (v4i16 VR64:$src))), (v2f32 VR64:$src)>;
-def : Pat<(v2f32 (bitconvert (v8i8  VR64:$src))), (v2f32 VR64:$src)>;
 def : Pat<(v1i64 (bitconvert (v2i32 VR64:$src))), (v1i64 VR64:$src)>;
-def : Pat<(v1i64 (bitconvert (v2f32 VR64:$src))), (v1i64 VR64:$src)>;
 def : Pat<(v1i64 (bitconvert (v4i16 VR64:$src))), (v1i64 VR64:$src)>;
 def : Pat<(v1i64 (bitconvert (v8i8  VR64:$src))), (v1i64 VR64:$src)>;
 
@@ -545,8 +535,6 @@
           (MMX_MOVD64to64rr GR64:$src)>;
 def : Pat<(v2i32 (bitconvert (i64 GR64:$src))),
           (MMX_MOVD64to64rr GR64:$src)>;
-def : Pat<(v2f32 (bitconvert (i64 GR64:$src))),
-          (MMX_MOVD64to64rr GR64:$src)>;
 def : Pat<(v4i16 (bitconvert (i64 GR64:$src))),
           (MMX_MOVD64to64rr GR64:$src)>;
 def : Pat<(v8i8  (bitconvert (i64 GR64:$src))),
@@ -555,8 +543,6 @@
           (MMX_MOVD64from64rr VR64:$src)>;
 def : Pat<(i64 (bitconvert (v2i32 VR64:$src))),
           (MMX_MOVD64from64rr VR64:$src)>;
-def : Pat<(i64 (bitconvert (v2f32 VR64:$src))),
-          (MMX_MOVD64from64rr VR64:$src)>;
 def : Pat<(i64 (bitconvert (v4i16 VR64:$src))),
           (MMX_MOVD64from64rr VR64:$src)>;
 def : Pat<(i64  (bitconvert (v8i8 VR64:$src))),

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=107610&r1=107609&r2=107610&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Sun Jul  4 23:38:33 2010
@@ -3584,10 +3584,6 @@
           (PALIGNR64rr VR64:$src2, VR64:$src1,
                        (SHUFFLE_get_palign_imm VR64:$src3))>,
           Requires<[HasSSSE3]>;
-def : Pat<(v2f32 (palign:$src3 VR64:$src1, VR64:$src2)),
-          (PALIGNR64rr VR64:$src2, VR64:$src1,
-                       (SHUFFLE_get_palign_imm VR64:$src3))>,
-          Requires<[HasSSSE3]>;
 def : Pat<(v4i16 (palign:$src3 VR64:$src1, VR64:$src2)),
           (PALIGNR64rr VR64:$src2, VR64:$src1,
                        (SHUFFLE_get_palign_imm VR64:$src3))>,

Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=107610&r1=107609&r2=107610&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Sun Jul  4 23:38:33 2010
@@ -780,7 +780,7 @@
 }
 
 // Generic vector registers: VR64 and VR128.
-def VR64  : RegisterClass<"X86", [v8i8, v4i16, v2i32, v1i64, v2f32], 64,
+def VR64  : RegisterClass<"X86", [v8i8, v4i16, v2i32, v1i64], 64,
                           [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>;
 def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],128,
                           [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,