This document seeks to dispel the mystery and confusion surrounding LLVM's - GetElementPtr (GEP) instruction. Questions about the wily GEP instruction are + GetElementPtr (GEP) instruction. + Questions about the wily GEP instruction are probably the most frequently occurring questions once a developer gets down to coding with LLVM. Here we lay out the sources of confusion and show that the GEP instruction is really quite simple. @@ -653,7 +654,8 @@

Support C, C-like languages, and languages which can be conceptually lowered into C (this covers a lot).

Support optimizations such as those that are common in - C compilers.

+ C compilers. In particular, GEP is a cornerstone of LLVM's + pointer aliasing model.

Provide a consistent method for computing addresses so that address computations don't need to be a part of load and store instructions in the IR.

Modified: llvm/trunk/docs/LangRef.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=107659&r1=107658&r2=107659&view=diff ============================================================================== --- llvm/trunk/docs/LangRef.html (original) +++ llvm/trunk/docs/LangRef.html Tue Jul 6 10:26:33 2010 @@ -1062,7 +1062,15 @@ The caller shares the responsibility with the callee for ensuring that these requirements are met. For further details, please see the discussion of the NoAlias response in - alias analysis. + alias analysis.
+
+ Note that this definition of noalias is intentionally + similar to the definition of restrict in C99 for function + arguments, thought it is slightly weaker. + + For function return values, C99's restrict is not meaningful, + while LLVM's noalias is. + nocapture This indicates that the callee does not make any copies of the pointer @@ -2397,7 +2405,8 @@ An instruction with externally visible side effects depends on the most recent preceding instruction with externally visible side effects, following - the order in the IR. (This includes volatile loads and stores.) + the order in the IR. (This includes + volatile operations.) An instruction control-depends on a terminator instruction From gohman at apple.com Tue Jul 6 10:31:55 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 06 Jul 2010 15:31:55 -0000 Subject: [llvm-commits] [llvm] r107660 - in /llvm/trunk: include/llvm/Target/TargetRegisterInfo.h lib/Target/TargetRegisterInfo.cpp Message-ID: <20100706153155.8A9C22A6C12C@llvm.org> Author: djg Date: Tue Jul 6 10:31:55 2010 New Revision: 107660 URL: http://llvm.org/viewvc/llvm-project?rev=107660&view=rev Log: Make getMinimalPhysRegClass' comment mention what makes it different from getPhysicalRegisterRegClass. Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h llvm/trunk/lib/Target/TargetRegisterInfo.cpp Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=107660&r1=107659&r2=107660&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Tue Jul 6 10:31:55 2010 @@ -320,7 +320,8 @@ getPhysicalRegisterRegClass(unsigned Reg, EVT VT = MVT::Other) const; /// getMinimalPhysRegClass - Returns the Register Class of a physical - /// register of the given type. + /// register of the given type, picking the most sub register class of + /// the right type that contains this physreg. const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const; Modified: llvm/trunk/lib/Target/TargetRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetRegisterInfo.cpp?rev=107660&r1=107659&r2=107660&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/TargetRegisterInfo.cpp Tue Jul 6 10:31:55 2010 @@ -61,7 +61,8 @@ } /// getMinimalPhysRegClass - Returns the Register Class of a physical -/// register of the given type. +/// register of the given type, picking the most sub register class of +/// the right type that contains this physreg. const TargetRegisterClass * TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, EVT VT) const { assert(isPhysicalRegister(reg) && "reg must be a physical register"); From gohman at apple.com Tue Jul 6 10:35:07 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 06 Jul 2010 15:35:07 -0000 Subject: [llvm-commits] [llvm] r107661 - /llvm/trunk/include/llvm/CodeGen/CallingConvLower.h Message-ID: <20100706153507.210D92A6C12C@llvm.org> Author: djg Date: Tue Jul 6 10:35:06 2010 New Revision: 107661 URL: http://llvm.org/viewvc/llvm-project?rev=107661&view=rev Log: Add a new CCValAssign LocInfo value, and a comment explaining what it should be used for. Modified: llvm/trunk/include/llvm/CodeGen/CallingConvLower.h Modified: llvm/trunk/include/llvm/CodeGen/CallingConvLower.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/CallingConvLower.h?rev=107661&r1=107660&r2=107661&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/CallingConvLower.h (original) +++ llvm/trunk/include/llvm/CodeGen/CallingConvLower.h Tue Jul 6 10:35:06 2010 @@ -35,6 +35,9 @@ ZExt, // The value is zero extended in the location. AExt, // The value is extended with undefined upper bits. BCvt, // The value is bit-converted in the location. + VExt, // The value is vector-widened in the location. + // FIXME: Not implemented yet. Code that uses AExt to mean + // vector-widen should be fixed to use VExt instead. Indirect // The location contains pointer to the value. // TODO: a subset of the value is in the location. }; From gohman at apple.com Tue Jul 6 10:39:54 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 06 Jul 2010 15:39:54 -0000 Subject: [llvm-commits] [llvm] r107666 - in /llvm/trunk: include/llvm/CodeGen/CallingConvLower.h include/llvm/CodeGen/SelectionDAGNodes.h lib/CodeGen/SelectionDAG/CallingConvLower.cpp Message-ID: <20100706153954.E33152A6C12C@llvm.org> Author: djg Date: Tue Jul 6 10:39:54 2010 New Revision: 107666 URL: http://llvm.org/viewvc/llvm-project?rev=107666&view=rev Log: Add versions of OutputArgReg, AnalyzeReturn, and AnalyzeCallOperands which do not depend on SelectionDAG. Modified: llvm/trunk/include/llvm/CodeGen/CallingConvLower.h llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h llvm/trunk/lib/CodeGen/SelectionDAG/CallingConvLower.cpp Modified: llvm/trunk/include/llvm/CodeGen/CallingConvLower.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/CallingConvLower.h?rev=107666&r1=107665&r2=107666&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/CallingConvLower.h (original) +++ llvm/trunk/include/llvm/CodeGen/CallingConvLower.h Tue Jul 6 10:39:54 2010 @@ -185,6 +185,8 @@ /// incorporating info about the result values into this state. void AnalyzeReturn(const SmallVectorImpl &Outs, CCAssignFn Fn); + void AnalyzeReturn(const SmallVectorImpl &Outs, + CCAssignFn Fn); /// CheckReturn - Analyze the return values of a function, returning /// true if the return can be performed without sret-demotion, and @@ -197,6 +199,8 @@ /// incorporating info about the passed values into this state. void AnalyzeCallOperands(const SmallVectorImpl &Outs, CCAssignFn Fn); + void AnalyzeCallOperands(const SmallVectorImpl &Outs, + CCAssignFn Fn); /// AnalyzeCallOperands - Same as above except it takes vectors of types /// and argument flags. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h?rev=107666&r1=107665&r2=107666&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGNodes.h Tue Jul 6 10:39:54 2010 @@ -1583,6 +1583,23 @@ "OutputArg value type must be Simple!"); } }; + + /// OutputArgReg - This struct carries flags and a register value for a + /// single outgoing (actual) argument or outgoing (from the perspective + /// of the caller) return value virtual register. + /// + struct OutputArgReg { + ArgFlagsTy Flags; + EVT VT; + unsigned Reg; + + /// IsFixed - Is this a "fixed" value, ie not passed through a vararg "...". + bool IsFixed; + + OutputArgReg() : IsFixed(false) {} + OutputArgReg(ISD::ArgFlagsTy flags, EVT vt, unsigned reg, bool isfixed) + : Flags(flags), VT(vt), Reg(reg), IsFixed(isfixed) {} + }; } /// VTSDNode - This class is used to represent EVT's, which are used Modified: llvm/trunk/lib/CodeGen/SelectionDAG/CallingConvLower.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/CallingConvLower.cpp?rev=107666&r1=107665&r2=107666&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/CallingConvLower.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/CallingConvLower.cpp Tue Jul 6 10:39:54 2010 @@ -111,6 +111,22 @@ } } +void CCState::AnalyzeReturn(const SmallVectorImpl &Outs, + CCAssignFn Fn) { + // Determine which register each value should be copied into. + for (unsigned i = 0, e = Outs.size(); i != e; ++i) { + EVT VT = Outs[i].VT; + ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; + if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) { +#ifndef NDEBUG + dbgs() << "Return operand #" << i << " has unhandled type " + << VT.getEVTString(); +#endif + llvm_unreachable(0); + } + } +} + /// AnalyzeCallOperands - Analyze the outgoing arguments to a call, /// incorporating info about the passed values into this state. @@ -130,6 +146,25 @@ } } +/// AnalyzeCallOperands - Analyze the outgoing arguments to a call, +/// incorporating info about the passed values into this state. +void +CCState::AnalyzeCallOperands(const SmallVectorImpl &Outs, + CCAssignFn Fn) { + unsigned NumOps = Outs.size(); + for (unsigned i = 0; i != NumOps; ++i) { + EVT ArgVT = Outs[i].VT; + ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; + if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) { +#ifndef NDEBUG + dbgs() << "Call operand #" << i << " has unhandled type " + << ArgVT.getEVTString(); +#endif + llvm_unreachable(0); + } + } +} + /// AnalyzeCallOperands - Same as above except it takes vectors of types /// and argument flags. void CCState::AnalyzeCallOperands(SmallVectorImpl &ArgVTs, From ggreif at gmail.com Tue Jul 6 10:44:11 2010 From: ggreif at gmail.com (Gabor Greif) Date: Tue, 06 Jul 2010 15:44:11 -0000 Subject: [llvm-commits] [llvm] r107667 - /llvm/trunk/include/llvm/Instructions.h Message-ID: <20100706154411.CC51C2A6C12C@llvm.org> Author: ggreif Date: Tue Jul 6 10:44:11 2010 New Revision: 107667 URL: http://llvm.org/viewvc/llvm-project?rev=107667&view=rev Log: second round of low-level interface squeeze-out: making all of CallInst's low-level operand accessors private If you get compile errors I strongly urge you to update your code. I tried to write the necessary clues into the header where the compiler may point to, but no guarantees. It works for my GCC. You have several options to update your code: - you can use the v2.8 ArgOperand accessors - you can go via a temporary CallSite - you can upcast to, say, User and call its low-level accessors if your code is definitely operand-order agnostic. If you run into serious problems, please comment in below thread (and back out this revision only if absolutely necessary): Modified: llvm/trunk/include/llvm/Instructions.h Modified: llvm/trunk/include/llvm/Instructions.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=107667&r1=107666&r2=107667&view=diff ============================================================================== --- llvm/trunk/include/llvm/Instructions.h (original) +++ llvm/trunk/include/llvm/Instructions.h Tue Jul 6 10:44:11 2010 @@ -940,8 +940,25 @@ unsigned(isTC)); } + /// @deprecated these "define hacks" will go away soon + /// @brief coerce out-of-tree code to abandon the low-level interfaces + /// @detail see below comments and update your code to high-level interfaces + /// in LLVM v2.8-only code + /// - getOperand(N+1) ---> getArgOperand(N) + /// - setOperand(N+1, V) ---> setArgOperand(N, V) + /// - getNumOperands() ---> getNumArgOperands()+1 // note the "+1"! + /// + /// in backward compatible code please consult llvm/Support/CallSite.h, + /// you should create a callsite using the CallInst pointer and call its + /// methods + /// +# define public private +# define protected private /// Provide fast operand accessors DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value); +# undef public +# undef protected +public: enum { ArgOffset = 1 }; ///< temporary, do not use for new code! unsigned getNumArgOperands() const { return getNumOperands() - 1; } @@ -951,11 +968,12 @@ /// Provide compile-time errors for accessing operand 0 /// @deprecated these will go away soon /// @detail see below comments and update your code to high-level interfaces - /// - getOperand(0) ---> getCalledValue() + /// - getOperand(0) ---> getCalledValue(), or possibly getCalledFunction /// - setOperand(0, V) ---> setCalledFunction(V) /// private: - void getOperand(void*); // NO IMPL ---> use getCalledValue (or possibly getCalledFunction) instead + void getOperand(void*); // NO IMPL ---> use getCalledValue (or possibly + // getCalledFunction) instead void setOperand(void*, Value*); // NO IMPL ---> use setCalledFunction instead public: @@ -1103,6 +1121,10 @@ typename std::iterator_traits::iterator_category()); } + +// Note: if you get compile errors about private methods then +// please update your code to use the high-level operand +// interfaces. See line 943 above. DEFINE_TRANSPARENT_OPERAND_ACCESSORS(CallInst, Value) //===----------------------------------------------------------------------===// From gohman at apple.com Tue Jul 6 10:49:49 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 06 Jul 2010 15:49:49 -0000 Subject: [llvm-commits] [llvm] r107668 - in /llvm/trunk: include/llvm/CodeGen/ lib/CodeGen/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/MBlaze/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PIC16/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/SystemZ/ lib/Target/X86/ lib/Target/XCore/ Message-ID: <20100706154949.877042A6C12C@llvm.org> Author: djg Date: Tue Jul 6 10:49:48 2010 New Revision: 107668 URL: http://llvm.org/viewvc/llvm-project?rev=107668&view=rev Log: Revert r107655. Modified: llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86TargetMachine.cpp llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Modified: llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h?rev=107668&r1=107667&r2=107668&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h Tue Jul 6 10:49:48 2010 @@ -259,11 +259,6 @@ /// machine basic block (i.e., copies all the successors fromMBB and /// remove all the successors from fromMBB). void transferSuccessors(MachineBasicBlock *fromMBB); - - /// transferSuccessorsAndUpdatePHIs - Transfers all the successors, as - /// in transferSuccessors, and update PHI operands in the successor blocks - /// which refer to fromMBB to refer to this. - void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB); /// isSuccessor - Return true if the specified MBB is a successor of this /// block. Modified: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp?rev=107668&r1=107667&r2=107668&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp Tue Jul 6 10:49:48 2010 @@ -335,32 +335,12 @@ if (this == fromMBB) return; - while (!fromMBB->succ_empty()) { - MachineBasicBlock *Succ = *fromMBB->succ_begin(); - addSuccessor(Succ); - fromMBB->removeSuccessor(Succ); - } -} - -void -MachineBasicBlock::transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB) { - if (this == fromMBB) - return; + for (MachineBasicBlock::succ_iterator I = fromMBB->succ_begin(), + E = fromMBB->succ_end(); I != E; ++I) + addSuccessor(*I); - while (!fromMBB->succ_empty()) { - MachineBasicBlock *Succ = *fromMBB->succ_begin(); - addSuccessor(Succ); - fromMBB->removeSuccessor(Succ); - - // Fix up any PHI nodes in the successor. - for (MachineBasicBlock::iterator MI = Succ->begin(), ME = Succ->end(); - MI != ME && MI->isPHI(); ++MI) - for (unsigned i = 2, e = MI->getNumOperands()+1; i != e; i += 2) { - MachineOperand &MO = MI->getOperand(i); - if (MO.getMBB() == fromMBB) - MO.setMBB(this); - } - } + while (!fromMBB->succ_empty()) + fromMBB->removeSuccessor(fromMBB->succ_begin()); } bool MachineBasicBlock::isSuccessor(const MachineBasicBlock *MBB) const { Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=107668&r1=107667&r2=107668&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Jul 6 10:49:48 2010 @@ -3637,12 +3637,7 @@ MF->insert(It, loop1MBB); MF->insert(It, loop2MBB); MF->insert(It, exitMBB); - - // Transfer the remainder of BB and its successor edges to exitMBB. - exitMBB->splice(exitMBB->begin(), BB, - llvm::next(MachineBasicBlock::iterator(MI)), - BB->end()); - exitMBB->transferSuccessorsAndUpdatePHIs(BB); + exitMBB->transferSuccessors(BB); // thisMBB: // ... @@ -3680,7 +3675,7 @@ // ... BB = exitMBB; - MI->eraseFromParent(); // The instruction is gone now. + MF->DeleteMachineInstr(MI); // The instruction is gone now. return BB; } @@ -3723,12 +3718,7 @@ MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); MF->insert(It, loopMBB); MF->insert(It, exitMBB); - - // Transfer the remainder of BB and its successor edges to exitMBB. - exitMBB->splice(exitMBB->begin(), BB, - llvm::next(MachineBasicBlock::iterator(MI)), - BB->end()); - exitMBB->transferSuccessorsAndUpdatePHIs(BB); + exitMBB->transferSuccessors(BB); MachineRegisterInfo &RegInfo = MF->getRegInfo(); unsigned scratch = RegInfo.createVirtualRegister(ARM::GPRRegisterClass); @@ -3773,7 +3763,7 @@ // ... BB = exitMBB; - MI->eraseFromParent(); // The instruction is gone now. + MF->DeleteMachineInstr(MI); // The instruction is gone now. return BB; } @@ -3858,21 +3848,22 @@ MachineFunction *F = BB->getParent(); MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); + BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB) + .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg()); F->insert(It, copy0MBB); F->insert(It, sinkMBB); - - // Transfer the remainder of BB and its successor edges to sinkMBB. - sinkMBB->splice(sinkMBB->begin(), BB, - llvm::next(MachineBasicBlock::iterator(MI)), - BB->end()); - sinkMBB->transferSuccessorsAndUpdatePHIs(BB); - + // Update machine-CFG edges by first adding all successors of the current + // block to the new block which will contain the Phi node for the select. + for (MachineBasicBlock::succ_iterator I = BB->succ_begin(), + E = BB->succ_end(); I != E; ++I) + sinkMBB->addSuccessor(*I); + // Next, remove all successors of the current block, and add the true + // and fallthrough blocks as its successors. + while (!BB->succ_empty()) + BB->removeSuccessor(BB->succ_begin()); BB->addSuccessor(copy0MBB); BB->addSuccessor(sinkMBB); - BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB) - .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg()); - // copy0MBB: // %FalseValue = ... // # fallthrough to sinkMBB @@ -3885,12 +3876,11 @@ // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] // ... BB = sinkMBB; - BuildMI(*BB, BB->begin(), dl, - TII->get(ARM::PHI), MI->getOperand(0).getReg()) + BuildMI(BB, dl, TII->get(ARM::PHI), MI->getOperand(0).getReg()) .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); - MI->eraseFromParent(); // The pseudo instruction is gone now. + F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. return BB; } @@ -3911,7 +3901,7 @@ const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(SrcReg); unsigned CopyOpc = (RC == ARM::tGPRRegisterClass) ? ARM::tMOVtgpr2gpr : ARM::tMOVgpr2gpr; - BuildMI(*BB, MI, dl, TII->get(CopyOpc), ARM::SP) + BuildMI(BB, dl, TII->get(CopyOpc), ARM::SP) .addReg(SrcReg, getKillRegState(SrcIsKill)); } @@ -3943,7 +3933,7 @@ NeedPred = true; NeedCC = true; NeedOp3 = true; break; } - MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(OpOpc), ARM::SP); + MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(OpOpc), ARM::SP); if (OpOpc == ARM::tAND) AddDefaultT1CC(MIB); MIB.addReg(ARM::SP); @@ -3959,10 +3949,10 @@ const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(DstReg); unsigned CopyOpc = (RC == ARM::tGPRRegisterClass) ? ARM::tMOVgpr2tgpr : ARM::tMOVgpr2gpr; - BuildMI(*BB, MI, dl, TII->get(CopyOpc)) + BuildMI(BB, dl, TII->get(CopyOpc)) .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead)) .addReg(ARM::SP); - MI->eraseFromParent(); // The pseudo instruction is gone now. + MF->DeleteMachineInstr(MI); // The pseudo instruction is gone now. return BB; } } Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp?rev=107668&r1=107667&r2=107668&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Tue Jul 6 10:49:48 2010 @@ -863,10 +863,7 @@ MachineBasicBlock *llscMBB = F->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); - sinkMBB->splice(sinkMBB->begin(), thisMBB, - llvm::next(MachineBasicBlock::iterator(MI)), - thisMBB->end()); - sinkMBB->transferSuccessorsAndUpdatePHIs(thisMBB); + sinkMBB->transferSuccessors(thisMBB); F->insert(It, llscMBB); F->insert(It, sinkMBB); @@ -915,7 +912,7 @@ thisMBB->addSuccessor(llscMBB); llscMBB->addSuccessor(llscMBB); llscMBB->addSuccessor(sinkMBB); - MI->eraseFromParent(); // The pseudo instruction is gone now. + F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. return sinkMBB; } Modified: llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp?rev=107668&r1=107667&r2=107668&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp Tue Jul 6 10:49:48 2010 @@ -234,24 +234,6 @@ MachineRegisterInfo &R = F->getRegInfo(); MachineBasicBlock *loop = F->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *finish = F->CreateMachineBasicBlock(LLVM_BB); - F->insert(It, loop); - F->insert(It, finish); - - // Update machine-CFG edges by transfering adding all successors and - // remaining instructions from the current block to the new block which - // will contain the Phi node for the select. - finish->splice(finish->begin(), BB, - llvm::next(MachineBasicBlock::iterator(MI)), - BB->end()); - finish->transferSuccessorsAndUpdatePHIs(BB); - - // Add the true and fallthrough blocks as its successors. - BB->addSuccessor(loop); - BB->addSuccessor(finish); - - // Next, add the finish block as a successor of the loop block - loop->addSuccessor(finish); - loop->addSuccessor(loop); unsigned IAMT = R.createVirtualRegister(MBlaze::CPURegsRegisterClass); BuildMI(BB, dl, TII->get(MBlaze::ANDI), IAMT) @@ -267,6 +249,26 @@ .addReg(IAMT) .addMBB(finish); + F->insert(It, loop); + F->insert(It, finish); + + // Update machine-CFG edges by first adding all successors of the current + // block to the new block which will contain the Phi node for the select. + for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), + e = BB->succ_end(); i != e; ++i) + finish->addSuccessor(*i); + + // Next, remove all successors of the current block, and add the true + // and fallthrough blocks as its successors. + while(!BB->succ_empty()) + BB->removeSuccessor(BB->succ_begin()); + BB->addSuccessor(loop); + BB->addSuccessor(finish); + + // Next, add the finish block as a successor of the loop block + loop->addSuccessor(finish); + loop->addSuccessor(loop); + unsigned DST = R.createVirtualRegister(MBlaze::CPURegsRegisterClass); unsigned NDST = R.createVirtualRegister(MBlaze::CPURegsRegisterClass); BuildMI(loop, dl, TII->get(MBlaze::PHI), DST) @@ -296,13 +298,12 @@ .addReg(NAMT) .addMBB(loop); - BuildMI(*finish, finish->begin(), dl, - TII->get(MBlaze::PHI), MI->getOperand(0).getReg()) + BuildMI(finish, dl, TII->get(MBlaze::PHI), MI->getOperand(0).getReg()) .addReg(IVAL).addMBB(BB) .addReg(NDST).addMBB(loop); // The pseudo instruction is no longer needed so remove it - MI->eraseFromParent(); + F->DeleteMachineInstr(MI); return finish; } @@ -337,23 +338,27 @@ case MBlazeCC::LE: Opc = MBlaze::BGTID; break; } + BuildMI(BB, dl, TII->get(Opc)) + .addReg(MI->getOperand(3).getReg()) + .addMBB(dneBB); + F->insert(It, flsBB); F->insert(It, dneBB); - // Transfer the remainder of BB and its successor edges to dneBB. - dneBB->splice(dneBB->begin(), BB, - llvm::next(MachineBasicBlock::iterator(MI)), - BB->end()); - dneBB->transferSuccessorsAndUpdatePHIs(BB); - + // Update machine-CFG edges by first adding all successors of the current + // block to the new block which will contain the Phi node for the select. + for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), + e = BB->succ_end(); i != e; ++i) + dneBB->addSuccessor(*i); + + // Next, remove all successors of the current block, and add the true + // and fallthrough blocks as its successors. + while(!BB->succ_empty()) + BB->removeSuccessor(BB->succ_begin()); BB->addSuccessor(flsBB); BB->addSuccessor(dneBB); flsBB->addSuccessor(dneBB); - BuildMI(BB, dl, TII->get(Opc)) - .addReg(MI->getOperand(3).getReg()) - .addMBB(dneBB); - // sinkMBB: // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] // ... @@ -361,12 +366,11 @@ // .addReg(MI->getOperand(1).getReg()).addMBB(flsBB) // .addReg(MI->getOperand(2).getReg()).addMBB(BB); - BuildMI(*dneBB, dneBB->begin(), dl, - TII->get(MBlaze::PHI), MI->getOperand(0).getReg()) + BuildMI(dneBB, dl, TII->get(MBlaze::PHI), MI->getOperand(0).getReg()) .addReg(MI->getOperand(2).getReg()).addMBB(flsBB) .addReg(MI->getOperand(1).getReg()).addMBB(BB); - MI->eraseFromParent(); // The pseudo instruction is gone now. + F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. return dneBB; } } Modified: llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp?rev=107668&r1=107667&r2=107668&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp Tue Jul 6 10:49:48 2010 @@ -1070,10 +1070,7 @@ // Update machine-CFG edges by transferring all successors of the current // block to the block containing instructions after shift. - RemBB->splice(RemBB->begin(), BB, - llvm::next(MachineBasicBlock::iterator(MI)), - BB->end()); - RemBB->transferSuccessorsAndUpdatePHIs(BB); + RemBB->transferSuccessors(BB); // Add adges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB BB->addSuccessor(LoopBB); @@ -1119,11 +1116,11 @@ // RemBB: // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB] - BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg) + BuildMI(RemBB, dl, TII.get(MSP430::PHI), DstReg) .addReg(SrcReg).addMBB(BB) .addReg(ShiftReg2).addMBB(LoopBB); - MI->eraseFromParent(); // The pseudo instruction is gone now. + F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. return RemBB; } @@ -1161,22 +1158,18 @@ MachineFunction *F = BB->getParent(); MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB); + BuildMI(BB, dl, TII.get(MSP430::JCC)) + .addMBB(copy1MBB) + .addImm(MI->getOperand(3).getImm()); F->insert(I, copy0MBB); F->insert(I, copy1MBB); // Update machine-CFG edges by transferring all successors of the current // block to the new block which will contain the Phi node for the select. - copy1MBB->splice(copy1MBB->begin(), BB, - llvm::next(MachineBasicBlock::iterator(MI)), - BB->end()); - copy1MBB->transferSuccessorsAndUpdatePHIs(BB); + copy1MBB->transferSuccessors(BB); // Next, add the true and fallthrough blocks as its successors. BB->addSuccessor(copy0MBB); BB->addSuccessor(copy1MBB); - BuildMI(BB, dl, TII.get(MSP430::JCC)) - .addMBB(copy1MBB) - .addImm(MI->getOperand(3).getImm()); - // copy0MBB: // %FalseValue = ... // # fallthrough to copy1MBB @@ -1189,11 +1182,11 @@ // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] // ... BB = copy1MBB; - BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI), + BuildMI(BB, dl, TII.get(MSP430::PHI), MI->getOperand(0).getReg()) .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); - MI->eraseFromParent(); // The pseudo instruction is gone now. + F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. return BB; } Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=107668&r1=107667&r2=107668&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue Jul 6 10:49:48 2010 @@ -284,18 +284,6 @@ MachineFunction *F = BB->getParent(); MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); - F->insert(It, copy0MBB); - F->insert(It, sinkMBB); - - // Transfer the remainder of BB and its successor edges to sinkMBB. - sinkMBB->splice(sinkMBB->begin(), BB, - llvm::next(MachineBasicBlock::iterator(MI)), - BB->end()); - sinkMBB->transferSuccessorsAndUpdatePHIs(BB); - - // Next, add the true and fallthrough blocks as its successors. - BB->addSuccessor(copy0MBB); - BB->addSuccessor(sinkMBB); // Emit the right instruction according to the type of the operands compared if (isFPCmp) { @@ -308,6 +296,20 @@ BuildMI(BB, dl, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg()) .addReg(Mips::ZERO).addMBB(sinkMBB); + F->insert(It, copy0MBB); + F->insert(It, sinkMBB); + // Update machine-CFG edges by first adding all successors of the current + // block to the new block which will contain the Phi node for the select. + for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), + e = BB->succ_end(); i != e; ++i) + sinkMBB->addSuccessor(*i); + // Next, remove all successors of the current block, and add the true + // and fallthrough blocks as its successors. + while(!BB->succ_empty()) + BB->removeSuccessor(BB->succ_begin()); + BB->addSuccessor(copy0MBB); + BB->addSuccessor(sinkMBB); + // copy0MBB: // %FalseValue = ... // # fallthrough to sinkMBB @@ -320,12 +322,11 @@ // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] // ... BB = sinkMBB; - BuildMI(*BB, BB->begin(), dl, - TII->get(Mips::PHI), MI->getOperand(0).getReg()) + BuildMI(BB, dl, TII->get(Mips::PHI), MI->getOperand(0).getReg()) .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB); - MI->eraseFromParent(); // The pseudo instruction is gone now. + F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. return BB; } } Modified: llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp?rev=107668&r1=107667&r2=107668&view=diff ============================================================================== --- llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PIC16/PIC16ISelLowering.cpp Tue Jul 6 10:49:48 2010 @@ -1928,12 +1928,15 @@ F->insert(It, copy0MBB); F->insert(It, sinkMBB); - // Transfer the remainder of BB and its successor edges to sinkMBB. - sinkMBB->splice(sinkMBB->begin(), BB, - llvm::next(MachineBasicBlock::iterator(MI)), - BB->end()); - sinkMBB->transferSuccessorsAndUpdatePHIs(BB); - + // Update machine-CFG edges by first adding all successors of the current + // block to the new block which will contain the Phi node for the select. + for (MachineBasicBlock::succ_iterator I = BB->succ_begin(), + E = BB->succ_end(); I != E; ++I) + sinkMBB->addSuccessor(*I); + // Next, remove all successors of the current block, and add the true + // and fallthrough blocks as its successors. + while (!BB->succ_empty()) + BB->removeSuccessor(BB->succ_begin()); // Next, add the true and fallthrough blocks as its successors. BB->addSuccessor(copy0MBB); BB->addSuccessor(sinkMBB); @@ -1950,12 +1953,11 @@ // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] // ... BB = sinkMBB; - BuildMI(*BB, BB->begin(), dl, - TII.get(PIC16::PHI), MI->getOperand(0).getReg()) + BuildMI(BB, dl, TII.get(PIC16::PHI), MI->getOperand(0).getReg()) .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); - MI->eraseFromParent(); // The pseudo instruction is gone now. + F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. return BB; } Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=107668&r1=107667&r2=107668&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Tue Jul 6 10:49:48 2010 @@ -4513,10 +4513,7 @@ MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); F->insert(It, loopMBB); F->insert(It, exitMBB); - exitMBB->splice(exitMBB->begin(), BB, - llvm::next(MachineBasicBlock::iterator(MI)), - BB->end()); - exitMBB->transferSuccessorsAndUpdatePHIs(BB); + exitMBB->transferSuccessors(BB); MachineRegisterInfo &RegInfo = F->getRegInfo(); unsigned TmpReg = (!BinOpcode) ? incr : @@ -4581,10 +4578,7 @@ MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); F->insert(It, loopMBB); F->insert(It, exitMBB); - exitMBB->splice(exitMBB->begin(), BB, - llvm::next(MachineBasicBlock::iterator(MI)), - BB->end()); - exitMBB->transferSuccessorsAndUpdatePHIs(BB); + exitMBB->transferSuccessors(BB); MachineRegisterInfo &RegInfo = F->getRegInfo(); const TargetRegisterClass *RC = @@ -4717,22 +4711,23 @@ MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); unsigned SelectPred = MI->getOperand(4).getImm(); DebugLoc dl = MI->getDebugLoc(); + BuildMI(BB, dl, TII->get(PPC::BCC)) + .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); F->insert(It, copy0MBB); F->insert(It, sinkMBB); - - // Transfer the remainder of BB and its successor edges to sinkMBB. - sinkMBB->splice(sinkMBB->begin(), BB, - llvm::next(MachineBasicBlock::iterator(MI)), - BB->end()); - sinkMBB->transferSuccessorsAndUpdatePHIs(BB); - + // Update machine-CFG edges by first adding all successors of the current + // block to the new block which will contain the Phi node for the select. + for (MachineBasicBlock::succ_iterator I = BB->succ_begin(), + E = BB->succ_end(); I != E; ++I) + sinkMBB->addSuccessor(*I); + // Next, remove all successors of the current block, and add the true + // and fallthrough blocks as its successors. + while (!BB->succ_empty()) + BB->removeSuccessor(BB->succ_begin()); // Next, add the true and fallthrough blocks as its successors. BB->addSuccessor(copy0MBB); BB->addSuccessor(sinkMBB); - BuildMI(BB, dl, TII->get(PPC::BCC)) - .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); - // copy0MBB: // %FalseValue = ... // # fallthrough to sinkMBB @@ -4745,8 +4740,7 @@ // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] // ... BB = sinkMBB; - BuildMI(*BB, BB->begin(), dl, - TII->get(PPC::PHI), MI->getOperand(0).getReg()) + BuildMI(BB, dl, TII->get(PPC::PHI), MI->getOperand(0).getReg()) .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); } @@ -4832,10 +4826,7 @@ F->insert(It, loop2MBB); F->insert(It, midMBB); F->insert(It, exitMBB); - exitMBB->splice(exitMBB->begin(), BB, - llvm::next(MachineBasicBlock::iterator(MI)), - BB->end()); - exitMBB->transferSuccessorsAndUpdatePHIs(BB); + exitMBB->transferSuccessors(BB); // thisMBB: // ... @@ -4903,10 +4894,7 @@ F->insert(It, loop2MBB); F->insert(It, midMBB); F->insert(It, exitMBB); - exitMBB->splice(exitMBB->begin(), BB, - llvm::next(MachineBasicBlock::iterator(MI)), - BB->end()); - exitMBB->transferSuccessorsAndUpdatePHIs(BB); + exitMBB->transferSuccessors(BB); MachineRegisterInfo &RegInfo = F->getRegInfo(); const TargetRegisterClass *RC = @@ -5032,7 +5020,7 @@ llvm_unreachable("Unexpected instr type to insert"); } - MI->eraseFromParent(); // The pseudo instruction is gone now. + F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. return BB; } Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=107668&r1=107667&r2=107668&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Tue Jul 6 10:49:48 2010 @@ -1007,20 +1007,21 @@ MachineFunction *F = BB->getParent(); MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); - - // Transfer the remainder of BB and its successor edges to sinkMBB. - sinkMBB->splice(sinkMBB->begin(), BB, - llvm::next(MachineBasicBlock::iterator(MI)), - BB->end()); - sinkMBB->transferSuccessorsAndUpdatePHIs(BB); - - // Add the true and fallthrough blocks as its successors. - BB->addSuccessor(copy0MBB); - BB->addSuccessor(sinkMBB); - BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC); F->insert(It, copy0MBB); F->insert(It, sinkMBB); + // Update machine-CFG edges by first adding all successors of the current + // block to the new block which will contain the Phi node for the select. + for (MachineBasicBlock::succ_iterator I = BB->succ_begin(), + E = BB->succ_end(); I != E; ++I) + sinkMBB->addSuccessor(*I); + // Next, remove all successors of the current block, and add the true + // and fallthrough blocks as its successors. + while (!BB->succ_empty()) + BB->removeSuccessor(BB->succ_begin()); + // Next, add the true and fallthrough blocks as its successors. + BB->addSuccessor(copy0MBB); + BB->addSuccessor(sinkMBB); // copy0MBB: // %FalseValue = ... @@ -1034,11 +1035,11 @@ // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] // ... BB = sinkMBB; - BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI->getOperand(0).getReg()) + BuildMI(BB, dl, TII.get(SP::PHI), MI->getOperand(0).getReg()) .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); - MI->eraseFromParent(); // The pseudo instruction is gone now. + F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. return BB; } Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp?rev=107668&r1=107667&r2=107668&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp Tue Jul 6 10:49:48 2010 @@ -827,20 +827,16 @@ MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB); SystemZCC::CondCodes CC = (SystemZCC::CondCodes)MI->getOperand(3).getImm(); + BuildMI(BB, dl, TII.getBrCond(CC)).addMBB(copy1MBB); F->insert(I, copy0MBB); F->insert(I, copy1MBB); // Update machine-CFG edges by transferring all successors of the current // block to the new block which will contain the Phi node for the select. - copy1MBB->splice(copy1MBB->begin(), BB, - llvm::next(MachineBasicBlock::iterator(MI)), - BB->end()); - copy1MBB->transferSuccessorsAndUpdatePHIs(BB); + copy1MBB->transferSuccessors(BB); // Next, add the true and fallthrough blocks as its successors. BB->addSuccessor(copy0MBB); BB->addSuccessor(copy1MBB); - BuildMI(BB, dl, TII.getBrCond(CC)).addMBB(copy1MBB); - // copy0MBB: // %FalseValue = ... // # fallthrough to copy1MBB @@ -853,11 +849,11 @@ // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] // ... BB = copy1MBB; - BuildMI(*BB, BB->begin(), dl, TII.get(SystemZ::PHI), + BuildMI(BB, dl, TII.get(SystemZ::PHI), MI->getOperand(0).getReg()) .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); - MI->eraseFromParent(); // The pseudo instruction is gone now. + F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. return BB; } Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=107668&r1=107667&r2=107668&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Jul 6 10:49:48 2010 @@ -8023,11 +8023,8 @@ F->insert(MBBIter, newMBB); F->insert(MBBIter, nextMBB); - // Transfer the remainder of thisMBB and its successor edges to nextMBB. - nextMBB->splice(nextMBB->begin(), thisMBB, - llvm::next(MachineBasicBlock::iterator(bInstr)), - thisMBB->end()); - nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); + // Move all successors to thisMBB to nextMBB + nextMBB->transferSuccessors(thisMBB); // Update thisMBB to fall through to newMBB thisMBB->addSuccessor(newMBB); @@ -8090,7 +8087,7 @@ // insert branch BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); - bInstr->eraseFromParent(); // The pseudo instruction is gone now. + F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now. return nextMBB; } @@ -8135,11 +8132,8 @@ F->insert(MBBIter, newMBB); F->insert(MBBIter, nextMBB); - // Transfer the remainder of thisMBB and its successor edges to nextMBB. - nextMBB->splice(nextMBB->begin(), thisMBB, - llvm::next(MachineBasicBlock::iterator(bInstr)), - thisMBB->end()); - nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); + // Move all successors to thisMBB to nextMBB + nextMBB->transferSuccessors(thisMBB); // Update thisMBB to fall through to newMBB thisMBB->addSuccessor(newMBB); @@ -8256,7 +8250,7 @@ // insert branch BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); - bInstr->eraseFromParent(); // The pseudo instruction is gone now. + F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now. return nextMBB; } @@ -8290,11 +8284,8 @@ F->insert(MBBIter, newMBB); F->insert(MBBIter, nextMBB); - // Transfer the remainder of thisMBB and its successor edges to nextMBB. - nextMBB->splice(nextMBB->begin(), thisMBB, - llvm::next(MachineBasicBlock::iterator(mInstr)), - thisMBB->end()); - nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); + // Move all successors of thisMBB to nextMBB + nextMBB->transferSuccessors(thisMBB); // Update thisMBB to fall through to newMBB thisMBB->addSuccessor(newMBB); @@ -8362,7 +8353,7 @@ // insert branch BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); - mInstr->eraseFromParent(); // The pseudo instruction is gone now. + F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now. return nextMBB; } @@ -8372,6 +8363,7 @@ X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB, unsigned numArgs, bool memArg) const { + MachineFunction *F = BB->getParent(); DebugLoc dl = MI->getDebugLoc(); const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); @@ -8393,7 +8385,7 @@ BuildMI(BB, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg()) .addReg(X86::XMM0); - MI->eraseFromParent(); + F->DeleteMachineInstr(MI); return BB; } @@ -8422,12 +8414,9 @@ F->insert(MBBIter, XMMSaveMBB); F->insert(MBBIter, EndMBB); - // Transfer the remainder of MBB and its successor edges to EndMBB. - EndMBB->splice(EndMBB->begin(), MBB, - llvm::next(MachineBasicBlock::iterator(MI)), - MBB->end()); - EndMBB->transferSuccessorsAndUpdatePHIs(MBB); - + // Set up the CFG. + // Move any original successors of MBB to the end block. + EndMBB->transferSuccessors(MBB); // The original block will now fall through to the XMM save block. MBB->addSuccessor(XMMSaveMBB); // The XMMSaveMBB will fall through to the end block. @@ -8466,7 +8455,7 @@ .addMemOperand(MMO); } - MI->eraseFromParent(); // The pseudo instruction is gone now. + F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. return EndMBB; } @@ -8495,17 +8484,37 @@ MachineFunction *F = BB->getParent(); MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); + unsigned Opc = + X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); + + BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB); F->insert(It, copy0MBB); F->insert(It, sinkMBB); + // Update machine-CFG edges by first adding all successors of the current + // block to the new block which will contain the Phi node for the select. + for (MachineBasicBlock::succ_iterator I = BB->succ_begin(), + E = BB->succ_end(); I != E; ++I) + sinkMBB->addSuccessor(*I); + + // Next, remove all successors of the current block, and add the true + // and fallthrough blocks as its successors. + while (!BB->succ_empty()) + BB->removeSuccessor(BB->succ_begin()); + + // Add the true and fallthrough blocks as its successors. + BB->addSuccessor(copy0MBB); + BB->addSuccessor(sinkMBB); + // If the EFLAGS register isn't dead in the terminator, then claim that it's // live into the sink and copy blocks. const MachineFunction *MF = BB->getParent(); const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); BitVector ReservedRegs = TRI->getReservedRegs(*MF); + const MachineInstr *Term = BB->getFirstTerminator(); - for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) { - const MachineOperand &MO = MI->getOperand(I); + for (unsigned I = 0, E = Term->getNumOperands(); I != E; ++I) { + const MachineOperand &MO = Term->getOperand(I); if (!MO.isReg() || MO.isKill() || MO.isDead()) continue; unsigned Reg = MO.getReg(); if (Reg != X86::EFLAGS) continue; @@ -8513,21 +8522,6 @@ sinkMBB->addLiveIn(Reg); } - // Transfer the remainder of BB and its successor edges to sinkMBB. - sinkMBB->splice(sinkMBB->begin(), BB, - llvm::next(MachineBasicBlock::iterator(MI)), - BB->end()); - sinkMBB->transferSuccessorsAndUpdatePHIs(BB); - - // Add the true and fallthrough blocks as its successors. - BB->addSuccessor(copy0MBB); - BB->addSuccessor(sinkMBB); - - // Create the conditional branch instruction. - unsigned Opc = - X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); - BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB); - // copy0MBB: // %FalseValue = ... // # fallthrough to sinkMBB @@ -8536,12 +8530,11 @@ // sinkMBB: // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] // ... - BuildMI(*sinkMBB, sinkMBB->begin(), DL, - TII->get(X86::PHI), MI->getOperand(0).getReg()) + BuildMI(sinkMBB, DL, TII->get(X86::PHI), MI->getOperand(0).getReg()) .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); - MI->eraseFromParent(); // The pseudo instruction is gone now. + F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. return sinkMBB; } @@ -8550,20 +8543,21 @@ MachineBasicBlock *BB) const { const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); DebugLoc DL = MI->getDebugLoc(); + MachineFunction *F = BB->getParent(); // The lowering is pretty easy: we're just emitting the call to _alloca. The // non-trivial part is impdef of ESP. // FIXME: The code should be tweaked as soon as we'll try to do codegen for // mingw-w64. - BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32)) + BuildMI(BB, DL, TII->get(X86::CALLpcrel32)) .addExternalSymbol("_alloca") .addReg(X86::EAX, RegState::Implicit) .addReg(X86::ESP, RegState::Implicit) .addReg(X86::EAX, RegState::Define | RegState::Implicit) .addReg(X86::ESP, RegState::Define | RegState::Implicit); - MI->eraseFromParent(); // The pseudo instruction is gone now. + F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. return BB; } @@ -8582,38 +8576,35 @@ assert(MI->getOperand(3).isGlobal() && "This should be a global"); if (Subtarget->is64Bit()) { - MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, - TII->get(X86::MOV64rm), X86::RDI) + MachineInstrBuilder MIB = BuildMI(BB, DL, TII->get(X86::MOV64rm), X86::RDI) .addReg(X86::RIP) .addImm(0).addReg(0) .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, MI->getOperand(3).getTargetFlags()) .addReg(0); - MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m)); + MIB = BuildMI(BB, DL, TII->get(X86::CALL64m)); addDirectMem(MIB, X86::RDI).addReg(0); } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { - MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, - TII->get(X86::MOV32rm), X86::EAX) + MachineInstrBuilder MIB = BuildMI(BB, DL, TII->get(X86::MOV32rm), X86::EAX) .addReg(0) .addImm(0).addReg(0) .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, MI->getOperand(3).getTargetFlags()) .addReg(0); - MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); + MIB = BuildMI(BB, DL, TII->get(X86::CALL32m)); addDirectMem(MIB, X86::EAX).addReg(0); } else { - MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, - TII->get(X86::MOV32rm), X86::EAX) + MachineInstrBuilder MIB = BuildMI(BB, DL, TII->get(X86::MOV32rm), X86::EAX) .addReg(TII->getGlobalBaseReg(F)) .addImm(0).addReg(0) .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, MI->getOperand(3).getTargetFlags()) .addReg(0); - MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); + MIB = BuildMI(BB, DL, TII->get(X86::CALL32m)); addDirectMem(MIB, X86::EAX).addReg(0); } - MI->eraseFromParent(); // The pseudo instruction is gone now. + F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. return BB; } @@ -8657,25 +8648,23 @@ // mode when truncating to an integer value. MachineFunction *F = BB->getParent(); int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false); - addFrameReference(BuildMI(*BB, MI, DL, - TII->get(X86::FNSTCW16m)), CWFrameIdx); + addFrameReference(BuildMI(BB, DL, TII->get(X86::FNSTCW16m)), CWFrameIdx); // Load the old value of the high byte of the control word... unsigned OldCW = F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass); - addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW), + addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16rm), OldCW), CWFrameIdx); // Set the high part to be round to zero... - addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx) + addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mi)), CWFrameIdx) .addImm(0xC7F); // Reload the modified control word now... - addFrameReference(BuildMI(*BB, MI, DL, - TII->get(X86::FLDCW16m)), CWFrameIdx); + addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx); // Restore the memory image of control word to original value - addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx) + addFrameReference(BuildMI(BB, DL, TII->get(X86::MOV16mr)), CWFrameIdx) .addReg(OldCW); // Get the X86 opcode to use. @@ -8714,14 +8703,13 @@ } else { AM.Disp = Op.getImm(); } - addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM) + addFullAddress(BuildMI(BB, DL, TII->get(Opc)), AM) .addReg(MI->getOperand(X86AddrNumOperands).getReg()); // Reload the original control word now. - addFrameReference(BuildMI(*BB, MI, DL, - TII->get(X86::FLDCW16m)), CWFrameIdx); + addFrameReference(BuildMI(BB, DL, TII->get(X86::FLDCW16m)), CWFrameIdx); - MI->eraseFromParent(); // The pseudo instruction is gone now. + F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. return BB; } // String/text processing lowering. Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=107668&r1=107667&r2=107668&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original) +++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Tue Jul 6 10:49:48 2010 @@ -173,14 +173,14 @@ // Install an instruction selector. PM.add(createX86ISelDag(*this, OptLevel)); + // Install a pass to insert x87 FP_REG_KILL instructions, as needed. + PM.add(createX87FPRegKillInserterPass()); + return false; } bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel) { - // Install a pass to insert x87 FP_REG_KILL instructions, as needed. - PM.add(createX87FPRegKillInserterPass()); - PM.add(createX86MaxStackAlignmentHeuristicPass()); return false; // -print-machineinstr shouldn't print after this. } Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp?rev=107668&r1=107667&r2=107668&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Tue Jul 6 10:49:48 2010 @@ -1221,22 +1221,23 @@ MachineFunction *F = BB->getParent(); MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); + BuildMI(BB, dl, TII.get(XCore::BRFT_lru6)) + .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); F->insert(It, copy0MBB); F->insert(It, sinkMBB); - - // Transfer the remainder of BB and its successor edges to sinkMBB. - sinkMBB->splice(sinkMBB->begin(), BB, - llvm::next(MachineBasicBlock::iterator(MI)), - BB->end()); - sinkMBB->transferSuccessorsAndUpdatePHIs(BB); - + // Update machine-CFG edges by first adding all successors of the current + // block to the new block which will contain the Phi node for the select. + for (MachineBasicBlock::succ_iterator I = BB->succ_begin(), + E = BB->succ_end(); I != E; ++I) + sinkMBB->addSuccessor(*I); + // Next, remove all successors of the current block, and add the true + // and fallthrough blocks as its successors. + while (!BB->succ_empty()) + BB->removeSuccessor(BB->succ_begin()); // Next, add the true and fallthrough blocks as its successors. BB->addSuccessor(copy0MBB); BB->addSuccessor(sinkMBB); - BuildMI(BB, dl, TII.get(XCore::BRFT_lru6)) - .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); - // copy0MBB: // %FalseValue = ... // # fallthrough to sinkMBB @@ -1249,12 +1250,11 @@ // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] // ... BB = sinkMBB; - BuildMI(*BB, BB->begin(), dl, - TII.get(XCore::PHI), MI->getOperand(0).getReg()) + BuildMI(BB, dl, TII.get(XCore::PHI), MI->getOperand(0).getReg()) .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); - MI->eraseFromParent(); // The pseudo instruction is gone now. + F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. return BB; } From baldrick at free.fr Tue Jul 6 10:52:15 2010 From: baldrick at free.fr (Duncan Sands) Date: Tue, 06 Jul 2010 15:52:15 -0000 Subject: [llvm-commits] [llvm] r107669 - /llvm/trunk/docs/Passes.html Message-ID: <20100706155216.202C42A6C12C@llvm.org> Author: baldrick Date: Tue Jul 6 10:52:15 2010 New Revision: 107669 URL: http://llvm.org/viewvc/llvm-project?rev=107669&view=rev Log: Bring the list of passes and their descriptions up to date. Patch by Kenneth Hoste. Modified: llvm/trunk/docs/Passes.html Modified: llvm/trunk/docs/Passes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/Passes.html?rev=107669&r1=107668&r2=107669&view=diff ============================================================================== --- llvm/trunk/docs/Passes.html (original) +++ llvm/trunk/docs/Passes.html Tue Jul 6 10:52:15 2010 @@ -27,7 +27,7 @@ my $o = $order{$1}; $o = "000" unless defined $o; push @x, "$o-$1$2\n"; - push @y, "$o $2\n"; + push @y, "$o -$1: $2\n"; } @x = map { s/^\d\d\d//; $_ } sort @x; @y = map { s/^\d\d\d//; $_ } sort @y; @@ -91,29 +91,46 @@ -dot-postdom-onlyPrint post dominator tree of function to 'dot' file (with no function bodies) -globalsmodref-aaSimple mod/ref analysis for globals -instcountCounts the various types of Instructions +-interprocedural-aa-evalExhaustive Interprocedural Alias Analysis Precision Evaluator +-interprocedural-basic-aaInterprocedural Basic Alias Analysis -intervalsInterval Partition Construction --loopsNatural Loop Construction +-iv-usersInduction Variable Users +-lazy-value-infoLazy Value Information Analysis +-ldaLoop Dependence Analysis +-libcall-aaLibCall Alias Analysis +-lintCheck for common errors in LLVM IR +-live-valuesValue Liveness Analysis +-loopsNatural Loop Information -memdepMemory Dependence Analysis +-module-debuginfoPrints module debug info metadata -no-aaNo Alias Analysis (always returns 'may' alias) -no-profileNo Profile Information +-pointertrackingTrack pointer bounds -postdomfrontierPost-Dominance Frontier Construction -postdomtreePost-Dominator Tree Construction -print-alias-setsAlias Set Printer -print-callgraphPrint a call graph -print-callgraph-sccsPrint SCCs of the Call Graph -print-cfg-sccsPrint SCCs of each function CFG +-print-dbginfoPrint debug info in human readable form +-print-dom-infoDominator Info Printer -print-externalfnconstantsPrint external fn callsites passed constants -print-functionPrint function to stderr -print-modulePrint module to stderr -print-used-typesFind Used Types +-profile-estimatorEstimate profiling information -profile-loaderLoad profile information from llvmprof.out +-profile-verifierVerify profiling information -scalar-evolutionScalar Evolution Analysis +-scev-aaScalarEvolution-based Alias Analysis -targetdataTarget Data Layout TRANSFORM PASSES OptionName +-abcdRemove redundant conditional branches -adceAggressive Dead Code Elimination +-always-inlineInliner for always_inline functions -argpromotionPromote 'by reference' arguments to scalars -block-placementProfile Guided Basic Block Placement -break-crit-edgesBreak critical edges in CFG @@ -125,16 +142,14 @@ -deadtypeelimDead Type Elimination -dieDead Instruction Elimination -dseDead Store Elimination +-functionattrsDeduce function attributes -globaldceDead Global Elimination -globaloptGlobal Variable Optimizer -gvnGlobal Value Numbering -indvarsCanonicalize Induction Variables -inlineFunction Integration/Inlining --insert-block-profilingInsert instrumentation for block profiling -insert-edge-profilingInsert instrumentation for edge profiling --insert-function-profilingInsert instrumentation for function profiling --insert-null-profiling-rsMeasure profiling framework overhead --insert-rs-profiling-frameworkInsert random sampling instrumentation framework +-insert-optimal-edge-profilingInsert optimal instrumentation for edge profiling -instcombineCombine redundant instructions -internalizeInternalize Global Symbols -ipconstpropInterprocedural constant propagation @@ -156,16 +171,27 @@ -lowerswitchLower SwitchInst's to branches -mem2regPromote Memory to Register -memcpyoptOptimize use of memcpy and friends +-mergefuncMerge Functions -mergereturnUnify function exit nodes +-partial-inlinerPartial Inliner +-partialspecializationPartial Specialization -prune-ehRemove unused exception handling info -reassociateReassociate expressions -reg2memDemote all values to stack slots -scalarreplScalar Replacement of Aggregates -sccpSparse Conditional Constant Propagation +-sinkCode Sinking -simplify-libcallsSimplify well-known library calls +-simplify-libcalls-halfpowrSimplify half_powr library calls -simplifycfgSimplify the CFG +-split-gepsSplit complex GEPs into simple GEPs +-ssiStatic Single Information Construction +-ssi-everythingStatic Single Information Construction (everything, intended for debugging) -stripStrip all symbols from a module +-strip-dead-debug-infoStrip debug info for unused symbols -strip-dead-prototypesRemove unused function declarations +-strip-debug-declareStrip all llvm.dbg.declare intrinsics +-strip-nondebugStrip all symbols, except dbg symbols, from a module -sretpromotionPromote sret arguments -tailcallelimTail Call Elimination -tailduplicateTail Duplication @@ -175,6 +201,7 @@ OptionName -deadarghaX0rDead Argument Hacking (BUGPOINT USE ONLY; DO NOT USE) -extract-blocksExtract Basic Blocks From Module (for bugpoint use) +-instnamerAssign names to anonymous instructions -preverifyPreliminary module verification -verifyModule Verifier -view-cfgView CFG of function @@ -194,7 +221,7 @@ - Exhaustive Alias Analysis Precision Evaluator + -aa-eval: Exhaustive Alias Analysis Precision Evaluator This is a simple N^2 alias analysis accuracy evaluator. @@ -208,7 +235,7 @@ - Basic Alias Analysis (default AA impl) + -basicaa: Basic Alias Analysis (default AA impl) @@ -220,7 +247,7 @@ - Basic CallGraph Construction + -basiccg: Basic CallGraph Construction Yet to be written. @@ -228,7 +255,7 @@ - Optimize for code generation + -codegenprepare: Optimize for code generation @@ -240,7 +267,7 @@ - Count Alias Analysis Query Responses + -count-aa: Count Alias Analysis Query Responses @@ -251,7 +278,7 @@ - AA use debugger + -debug-aa: AA use debugger @@ -268,7 +295,7 @@ - Dominance Frontier Construction + -domfrontier: Dominance Frontier Construction @@ -279,7 +306,7 @@ - Dominator Tree Construction + -domtree: Dominator Tree Construction @@ -290,7 +317,7 @@ - Print Call Graph to 'dot' file + -dot-callgraph: Print Call Graph to 'dot' file @@ -302,7 +329,7 @@ - Print CFG of function to 'dot' file + -dot-cfg: Print CFG of function to 'dot' file @@ -314,7 +341,7 @@ - Print CFG of function to 'dot' file (with no function bodies) + -dot-cfg-only: Print CFG of function to 'dot' file (with no function bodies) @@ -327,7 +354,7 @@ - Print dominator tree of function to 'dot' file + -dot-dom: Print dominator tree of function to 'dot' file @@ -339,7 +366,7 @@ - Print dominator tree of function to 'dot' file (with no + -dot-dom-only: Print dominator tree of function to 'dot' file (with no function bodies) @@ -353,7 +380,7 @@ - Print post dominator tree of function to 'dot' file + dot-postdom: Print post dominator tree of function to 'dot' file @@ -365,7 +392,7 @@ - Print post dominator tree of function to 'dot' file + dot-postdom-only: Print post dominator tree of function to 'dot' file (with no function bodies) @@ -379,7 +406,7 @@ - Simple mod/ref analysis for globals + -globalsmodref-aa: Simple mod/ref analysis for globals @@ -392,7 +419,7 @@ - Counts the various types of Instructions + -instcount: Counts the various types of Instructions @@ -402,7 +429,30 @@ - Interval Partition Construction + -interprocedural-aa-eval: Exhaustive Interprocedural Alias Analysis Precision Evaluator + + + This pass implements a simple N^2 alias analysis accuracy evaluator. + Basically, for each function in the program, it simply queries to see how the + alias analysis implementation answers alias queries between each pair of + pointers in the function. + + + + + + -interprocedural-basic-aa: Interprocedural Basic Alias Analysis + + + This pass defines the default implementation of the Alias Analysis interface + that simply implements a few identities (two different globals cannot alias, + etc), but otherwise does no analysis. + + + + + + -intervals: Interval Partition Construction @@ -418,7 +468,80 @@ - Natural Loop Construction + -iv-users: Induction Variable Users + + + Bookkeeping for "interesting" users of expressions computed from + induction variables. + + + + + -lazy-value-info: Lazy Value Information Analysis + + + Interface for lazy computation of value constraint information. + + + + + -lda: Loop Dependence Analysis + + + Loop dependence analysis framework, which is used to detect dependences in + memory accesses in loops. + + + + + -libcall-aa: LibCall Alias Analysis + + + LibCall Alias Analysis. + + + + + -lint: Check for common errors in LLVM IR + + + This pass statically checks for common and easily-identified constructs + which produce undefined or likely unintended behavior in LLVM IR. + + It is not a guarantee of correctness, in two ways. First, it isn't + comprehensive. There are checks which could be done statically which are + not yet implemented. Some of these are indicated by TODO comments, but + those aren't comprehensive either. Second, many conditions cannot be + checked statically. This pass does no dynamic instrumentation, so it + can't check for all possible problems. + + Another limitation is that it assumes all code will be executed. A store + through a null pointer in a basic block which is never reached is harmless, + but this pass will warn about it anyway. + + Optimization passes may make conditions that this pass checks for more or + less obvious. If an optimization pass appears to be introducing a warning, + it may be that the optimization pass is merely exposing an existing + condition in the code. + + This code may be run before instcombine. In many cases, instcombine checks + for the same kinds of things and turns instructions with undefined behavior + into unreachable (or equivalent). Because of this, this pass makes some + effort to look through bitcasts and so on. + + + + + + -live-values: Values Liveness Analysis + + + LLVM IR Value liveness analysis pass. + + + + + -loops: Natural Loop Construction @@ -431,7 +554,7 @@ - Memory Dependence Analysis + -memdep: Memory Dependence Analysis @@ -444,7 +567,20 @@ - No Alias Analysis (always returns 'may' alias) + -module-debuginfo: Prints module debug info metadata + + + This pass decodes the debug info metadata in a module and prints in a + (sufficiently-prepared-) human-readable form. + + For example, run this pass from opt along with the -analyze option, and + it'll print to standard output. + + + + + + -no-aa: No Alias Analysis (always returns 'may' alias) @@ -456,7 +592,7 @@ - No Profile Information + -no-profile: No Profile Information @@ -467,7 +603,16 @@ - Post-Dominance Frontier Construction + -pointertracking: Track pointer bounds. + + + Tracking of pointer bounds. + + + + + + -postdomfrontier: Post-Dominance Frontier Construction @@ -478,7 +623,7 @@ - Post-Dominator Tree Construction + -postdomtree: Post-Dominator Tree Construction @@ -489,7 +634,7 @@ - Alias Set Printer + -print-alias-sets: Alias Set Printer Yet to be written. @@ -497,7 +642,7 @@ - Print a call graph + -print-callgraph: Print a call graph @@ -508,7 +653,7 @@ - Print SCCs of the Call Graph + -print-callgraph-sccs: Print SCCs of the Call Graph @@ -519,7 +664,7 @@ - Print SCCs of each function CFG + -print-cfg-sccs: Print SCCs of each function CFG @@ -530,7 +675,31 @@ - Print external fn callsites passed constants + -print-dbginfo: Print debug info in human readable form + + + Pass that prints instructions, and associated debug info: + + + source/line/col information + original variable name + original type name + + + + + + + + -print-dom-info: Dominator Info Printer + + + Dominator Info Printer. + + + + + -print-externalfnconstants: Print external fn callsites passed constants @@ -543,7 +712,7 @@ - Print function to stderr + -print-function: Print function to stderr @@ -555,7 +724,7 @@ - Print module to stderr + -print-module: Print module to stderr @@ -565,7 +734,7 @@ - Find Used Types + -print-used-types: Find Used Types @@ -576,7 +745,17 @@ - Load profile information from llvmprof.out + -profile-estimator: Estimate profiling information + + + Profiling information that estimates the profiling information + in a very crude and unimaginative way. + + + + + + -profile-loader: Load profile information from llvmprof.out @@ -587,7 +766,15 @@ - Scalar Evolution Analysis + -profile-verifier: Verify profiling information + + + Pass that checks profiling information for plausibility. + + + + + -scalar-evolution: Scalar Evolution Analysis @@ -606,7 +793,45 @@ - Target Data Layout + -scev-aa: + + + Simple alias analysis implemented in terms of ScalarEvolution queries. + + This differs from traditional loop dependence analysis in that it tests + for dependencies within a single iteration of a loop, rather than + dependencies between different iterations. + + ScalarEvolution has a more complete understanding of pointer arithmetic + than BasicAliasAnalysis' collection of ad-hoc analyses. + + + + + + -strip-dead-debug-info: Strip debug info for unused symbols + + + + performs code stripping. this transformation can delete: + + + + names for virtual registers + symbols for internal globals and functions + debug information + + + + note that this transformation makes code much less readable, so it should + only be used in situations where the strip utility would be used, + such as reducing code size or making it harder to reverse engineer code. + + + + + + -targetdata: Target Data Layout Provides other passes access to information on how the size and alignment @@ -621,7 +846,22 @@ - Aggressive Dead Code Elimination + -abcd: Remove redundant conditional branches + + + ABCD removes conditional branch instructions that can be proved redundant. + With the SSI representation, each variable has a constraint. By analyzing these + constraints we can prove that a branch is redundant. When a branch is proved + redundant it means that one direction will always be taken; thus, we can change + this branch into an unconditional jump. + It is advisable to run SimplifyCFG and + Aggressive Dead Code Elimination after ABCD + to clean up the code. + + + + + -adce: Aggressive Dead Code Elimination ADCE aggressively tries to eliminate code. This pass is similar to @@ -632,7 +872,16 @@ - Promote 'by reference' arguments to scalars + -always-inline: Inliner for always_inline functions + + + A custom inliner that handles only functions that are marked as + "always inline". + + + + + -argpromotion: Promote 'by reference' arguments to scalars @@ -663,7 +912,7 @@ - Profile Guided Basic Block Placement + -block-placement: Profile Guided Basic Block Placement This pass is a very simple profile guided basic block placement algorithm. @@ -675,7 +924,7 @@ - Break critical edges in CFG + -break-crit-edges: Break critical edges in CFG @@ -688,7 +937,7 @@ - Prepare a function for code generation + -codegenprepare: Prepare a function for code generation This pass munges the code in the input function to better prepare it for @@ -698,7 +947,7 @@ - Merge Duplicate Global Constants + -constmerge: Merge Duplicate Global Constants @@ -711,7 +960,7 @@ - Simple constant propagation + -constprop: Simple constant propagation This file implements constant propagation and merging. It looks for @@ -727,7 +976,7 @@ - Dead Code Elimination + -dce: Dead Code Elimination @@ -739,7 +988,7 @@ - Dead Argument Elimination + -deadargelim: Dead Argument Elimination @@ -757,7 +1006,7 @@ - Dead Type Elimination + -deadtypeelim: Dead Type Elimination @@ -769,7 +1018,7 @@ - Dead Instruction Elimination + -die: Dead Instruction Elimination @@ -780,7 +1029,7 @@ - Dead Store Elimination + -dse: Dead Store Elimination @@ -791,7 +1040,22 @@ - Dead Global Elimination + -functionattrs: Deduce function attributes + + + A simple interprocedural pass which walks the call-graph, looking for + functions which do not access or only read non-local memory, and marking them + readnone/readonly. In addition, it marks function arguments (of pointer type) + 'nocapture' if a call to the function does not create any copies of the pointer + value that outlive the call. This more or less means that the pointer is only + dereferenced, and not returned from the function or stored in a global. + This pass is implemented as a bottom-up traversal of the call-graph. + + + + + + -globaldce: Dead Global Elimination @@ -805,7 +1069,7 @@ - Global Variable Optimizer + -globalopt: Global Variable Optimizer @@ -817,7 +1081,7 @@ - Global Value Numbering + -gvn: Global Value Numbering @@ -826,10 +1090,9 @@ - - Canonicalize Induction Variables + -indvars: Canonicalize Induction Variables @@ -880,7 +1143,7 @@ - Function Integration/Inlining + -inline: Function Integration/Inlining @@ -890,26 +1153,7 @@ - Insert instrumentation for block profiling - - - - This pass instruments the specified program with counters for basic block - profiling, which counts the number of times each basic block executes. This - is the most basic form of profiling, which can tell which blocks are hot, but - cannot reliably detect hot paths through the CFG. - - - - Note that this implementation is very na??ve. Control equivalent regions of - the CFG should not require duplicate counters, but it does put duplicate - counters in. - - - - - - Insert instrumentation for edge profiling + -insert-edge-profiling: Insert instrumentation for edge profiling @@ -927,51 +1171,18 @@ - Insert instrumentation for function profiling + -insert-optimal-edge-profiling: Insert optimal instrumentation for edge profiling - - This pass instruments the specified program with counters for function - profiling, which counts the number of times each function is called. - - - - - - Measure profiling framework overhead - - - - The basic profiler that does nothing. It is the default profiler and thus - terminates RSProfiler chains. It is useful for measuring - framework overhead. - - - - - - Insert random sampling instrumentation framework - - - - The second stage of the random-sampling instrumentation framework, duplicates - all instructions in a function, ignoring the profiling code, then connects the - two versions together at the entry and at backedges. At each connection point - a choice is made as to whether to jump to the profiled code (take a sample) or - execute the unprofiled code. - - - - After this pass, it is highly recommended to runmem2reg - and adce. instcombine, - load-vn, gdce, and - dse also are good to run afterwards. + This pass instruments the specified program with counters for edge profiling. + Edge profiling can give a reasonable approximation of the hot paths through a + program, and is used for a wide variety of program transformations. - Combine redundant instructions + -instcombine: Combine redundant instructions @@ -1025,7 +1236,7 @@ - Internalize Global Symbols + -internalize: Internalize Global Symbols @@ -1037,7 +1248,7 @@ - Interprocedural constant propagation + -ipconstprop: Interprocedural constant propagation @@ -1051,7 +1262,7 @@ - Interprocedural Sparse Conditional Constant Propagation + -ipsccp: Interprocedural Sparse Conditional Constant Propagation @@ -1062,7 +1273,7 @@ - Thread control through conditional blocks + -jump-threading: Thread control through conditional blocks @@ -1091,7 +1302,7 @@ - Loop-Closed SSA Form Pass + -lcssa: Loop-Closed SSA Form Pass @@ -1120,7 +1331,7 @@ - Loop Invariant Code Motion + -licm: Loop Invariant Code Motion @@ -1156,7 +1367,7 @@ - Dead Loop Deletion Pass + -loop-deletion: Dead Loop Deletion Pass @@ -1169,7 +1380,7 @@ - Extract loops into new functions + -loop-extract: Extract loops into new functions @@ -1182,7 +1393,7 @@ - Extract at most one loop into a new function + -loop-extract-single: Extract at most one loop into a new function @@ -1194,7 +1405,7 @@ - Index Split Loops + -loop-index-split: Index Split Loops @@ -1205,7 +1416,7 @@ - Loop Strength Reduction + -loop-reduce: Loop Strength Reduction @@ -1219,7 +1430,7 @@ - Rotate Loops + -loop-rotate: Rotate Loops A simple loop rotation transformation. @@ -1227,7 +1438,7 @@ - Unroll loops + -loop-unroll: Unroll loops @@ -1239,7 +1450,7 @@ - Unswitch loops + -loop-unswitch: Unswitch loops @@ -1269,7 +1480,7 @@ - Canonicalize natural loops + -loopsimplify: Canonicalize natural loops @@ -1310,7 +1521,23 @@ - Lower invoke and unwind, for unwindless code generators + -lowerallocs: Lower allocations from instructions to calls + + + + Turn malloc and free instructions into @malloc and + @free calls. + + + + This is a target-dependent tranformation because it depends on the size of + data types and alignment constraints. + + + + + + -lowerinvoke: Lower invoke and unwind, for unwindless code generators @@ -1351,7 +1578,7 @@ - Lower Set Jump + -lowersetjmp: Lower Set Jump @@ -1380,7 +1607,7 @@ - Lower SwitchInst's to branches + -lowerswitch: Lower SwitchInst's to branches @@ -1392,7 +1619,7 @@ - Promote Memory to Register + -mem2reg: Promote Memory to Register @@ -1408,7 +1635,7 @@ - Optimize use of memcpy and friend + -memcpyopt: Optimize use of memcpy and friend @@ -1419,7 +1646,28 @@ - Unify function exit nodes + -mergefunc: Merge Functions + + + This pass looks for equivalent functions that are mergable and folds them. + + A hash is computed from the function, based on its type and number of + basic blocks. + + Once all hashes are computed, we perform an expensive equality comparison + on each function pair. This takes n^2/2 comparisons per bucket, so it's + important that the hash function be high quality. The equality comparison + iterates through each instruction in each basic block. + + When a match is found the functions are folded. If both functions are + overridable, we move the functionality into a new internal function and + leave two overridable thunks to it. + + + + + + -mergereturn: Unify function exit nodes @@ -1430,7 +1678,33 @@ - Remove unused exception handling info + -partial-inliner: Partial Inliner + + + This pass performs partial inlining, typically by inlining an if + statement that surrounds the body of the function. + + + + + + -partialspecialization: Partial Specialization + + + This pass finds function arguments that are often a common constant and + specializes a version of the called function for that constant. + + This pass simply does the cloning for functions it specializes. It depends + on IPSCCP and DAE to clean up the results. + + The initial heuristic favors constant arguments that are used in control + flow. + + + + + + -prune-eh: Remove unused exception handling info @@ -1443,7 +1717,7 @@ - Reassociate expressions + -reassociate: Reassociate expressions @@ -1466,7 +1740,7 @@ - Demote all values to stack slots + -reg2mem: Demote all values to stack slots @@ -1483,7 +1757,7 @@ - Scalar Replacement of Aggregates + -scalarrepl: Scalar Replacement of Aggregates @@ -1505,7 +1779,7 @@ - Sparse Conditional Constant Propagation + -sccp: Sparse Conditional Constant Propagation @@ -1528,7 +1802,17 @@ - Simplify well-known library calls + -sink: Code Sinking + + + This pass moves instructions into successor blocks, when possible, so that + they aren't executed on paths where their results aren't needed. + + + + + + -simplify-libcalls: Simplify well-known library calls @@ -1541,7 +1825,17 @@ - Simplify the CFG + -simplify-libcalls-halfpowr: Simplify half_powr library calls + + + Simple pass that applies an experimental transformation on calls + to specific functions. + + + + + + -simplifycfg: Simplify the CFG @@ -1560,11 +1854,48 @@ - Strip all symbols from a module + -split-geps: Split complex GEPs into simple GEPs + + + This function breaks GEPs with more than 2 non-zero operands into smaller + GEPs each with no more than 2 non-zero operands. This exposes redundancy + between GEPs with common initial operand sequences. + + + + + + -ssi: Static Single Information Construction + + + This pass converts a list of variables to the Static Single Information + form. + + We are building an on-demand representation, that is, we do not convert + every single variable in the target function to SSI form. Rather, we receive + a list of target variables that must be converted. We also do not + completely convert a target variable to the SSI format. Instead, we only + change the variable in the points where new information can be attached + to its live range, that is, at branch points. + + + + + + -ssi-everything: Static Single Information Construction (everything, intended for debugging) + + + A pass that runs SSI on every non-void variable, intended for debugging. + + + + + + -strip: Strip all symbols from a module - Performs code stripping. This transformation can delete: + performs code stripping. this transformation can delete: @@ -1574,7 +1905,7 @@ - Note that this transformation makes code much less readable, so it should + note that this transformation makes code much less readable, so it should only be used in situations where the strip utility would be used, such as reducing code size or making it harder to reverse engineer code. @@ -1582,7 +1913,7 @@ - Remove unused function declarations + -strip-dead-prototypes: Remove unused function declarations @@ -1595,7 +1926,41 @@ - Promote sret arguments + -strip-debug-declare: Strip all llvm.dbg.declare intrinsics + + + This pass implements code stripping. Specifically, it can delete: + + names for virtual registers + symbols for internal globals and functions + debug information + + Note that this transformation makes code much less readable, so it should + only be used in situations where the 'strip' utility would be used, such as + reducing code size or making it harder to reverse engineer code. + + + + + + -strip-nondebug: Strip all symbols, except dbg symbols, from a module + + + This pass implements code stripping. Specifically, it can delete: + + names for virtual registers + symbols for internal globals and functions + debug information + + Note that this transformation makes code much less readable, so it should + only be used in situations where the 'strip' utility would be used, such as + reducing code size or making it harder to reverse engineer code. + + + + + + -sretpromotion: Promote sret arguments @@ -1618,7 +1983,7 @@ - Tail Call Elimination + -tailcallelim: Tail Call Elimination @@ -1650,7 +2015,7 @@ - Tail Duplication + -tailduplicate: Tail Duplication @@ -1670,7 +2035,7 @@ - Dead Argument Hacking (BUGPOINT USE ONLY; DO NOT USE) + -deadarghaX0r: Dead Argument Hacking (BUGPOINT USE ONLY; DO NOT USE) @@ -1681,7 +2046,7 @@ - Extract Basic Blocks From Module (for bugpoint use) + -extract-blocks: Extract Basic Blocks From Module (for bugpoint use) @@ -1691,7 +2056,19 @@ - Preliminary module verification + -instnamer: Assign names to anonymous instructions + + + This is a little utility pass that gives instructions names, this is mostly + useful when diffing the effect of an optimization because deleting an + unnamed instruction can change all other instruction numbering, making the + diff very noisy. + + + + + + -preverify: Preliminary module verification @@ -1707,7 +2084,7 @@ - Module Verifier + -verify: Module Verifier @@ -1758,7 +2135,7 @@ - View CFG of function + -view-cfg: View CFG of function @@ -1768,7 +2145,7 @@ - View CFG of function (with no function bodies) + -view-cfg-only: View CFG of function (with no function bodies) @@ -1779,7 +2156,7 @@ - View dominator tree of function + -view-dom: View dominator tree of function @@ -1789,7 +2166,7 @@ - View dominator tree of function (with no function + -view-dom-only: View dominator tree of function (with no function bodies) @@ -1802,7 +2179,7 @@ - View post dominator tree of function + -view-postdom: View post dominator tree of function @@ -1812,7 +2189,7 @@ - View post dominator tree of function (with no + -view-postdom-only: View post dominator tree of function (with no function bodies) From clattner at apple.com Tue Jul 6 10:56:34 2010 From: clattner at apple.com (Chris Lattner) Date: Tue, 6 Jul 2010 08:56:34 -0700 Subject: [llvm-commits] [llvm] r107667 - /llvm/trunk/include/llvm/Instructions.h In-Reply-To: <20100706154411.CC51C2A6C12C@llvm.org> References: <20100706154411.CC51C2A6C12C@llvm.org> Message-ID: On Jul 6, 2010, at 8:44 AM, Gabor Greif wrote: > Author: ggreif > Date: Tue Jul 6 10:44:11 2010 > New Revision: 107667 > > URL: http://llvm.org/viewvc/llvm-project?rev=107667&view=rev > Log: > second round of low-level interface squeeze-out: > making all of CallInst's low-level operand accessors > private > > If you get compile errors I strongly urge you to > update your code. Hi Gabor, I'm all for the spirit of this patch, however, this is really really gross: > > +# define public private > +# define protected private > /// Provide fast operand accessors > DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value); > +# undef public > +# undef protected How about declaring a different macro, named DECLARE_PRIVATE_TRANSPARENT_OPERAND_ACCESSORS or something? -Chris From sabre at nondot.org Tue Jul 6 10:59:27 2010 From: sabre at nondot.org (Chris Lattner) Date: Tue, 06 Jul 2010 15:59:27 -0000 Subject: [llvm-commits] [llvm] r107670 - /llvm/trunk/lib/CodeGen/StackProtector.cpp Message-ID: <20100706155927.4EFE62A6C12C@llvm.org> Author: lattner Date: Tue Jul 6 10:59:27 2010 New Revision: 107670 URL: http://llvm.org/viewvc/llvm-project?rev=107670&view=rev Log: tighten up this code. Modified: llvm/trunk/lib/CodeGen/StackProtector.cpp Modified: llvm/trunk/lib/CodeGen/StackProtector.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/StackProtector.cpp?rev=107670&r1=107669&r2=107670&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/StackProtector.cpp (original) +++ llvm/trunk/lib/CodeGen/StackProtector.cpp Tue Jul 6 10:59:27 2010 @@ -153,21 +153,16 @@ // StackGuard = load __stack_chk_guard // call void @llvm.stackprotect.create(StackGuard, StackGuardSlot) // - PointerType *PtrTy = PointerType::getUnqual( - Type::getInt8Ty(RI->getContext())); - + const PointerType *PtrTy = Type::getInt8PtrTy(RI->getContext()); unsigned AddressSpace, Offset; if (TLI->getStackCookieLocation(AddressSpace, Offset)) { - Constant *ASPtr = Constant::getNullValue( - PointerType::get(Type::getInt8Ty(RI->getContext()), AddressSpace)); - APInt OffsetInt(32, Offset); - Constant *OffsetVal = Constant::getIntegerValue( - Type::getInt32Ty(RI->getContext()), OffsetInt); - StackGuardVar = ConstantExpr::getPointerCast( - ConstantExpr::getGetElementPtr(ASPtr, &OffsetVal, 1), - PointerType::get(PtrTy, AddressSpace)); + Constant *OffsetVal = + ConstantInt::get(Type::getInt32Ty(RI->getContext()), Offset); + + StackGuardVar = ConstantExpr::getIntToPtr(OffsetVal, + PointerType::get(PtrTy, AddressSpace)); } else { - StackGuardVar = M->getOrInsertGlobal("__stack_chk_guard", PtrTy); + StackGuardVar = M->getOrInsertGlobal("__stack_chk_guard", PtrTy); } BasicBlock &Entry = F->getEntryBlock(); From stoklund at 2pi.dk Tue Jul 6 11:16:12 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 6 Jul 2010 09:16:12 -0700 Subject: [llvm-commits] [patch] Don't create neon moves in CopyRegToReg, instead trust NEONMoveFixPass to do the conversion In-Reply-To: References: Message-ID: <4097B32E-6F0D-45A3-8C8A-40EBCA3F03F6@2pi.dk> On Jul 5, 2010, at 8:21 AM, Rafael Espindola wrote: > A recent patch caused a regression on ARM: we would create NEON copy > instructions when a VFP one would be more profitable. Two options were > discussed: > > *) Represent the NEON registers as distinct from the VFP registers and > have explicit copies from one to the other. > *) Figure out why NEONMoveFixPass was not fixing this. > > Currently NEONMoveFixPass only converts VFP moves to NEON moves. This > looks reasonable, we just have to avoid creating NEON moves early. > This is what the attached patch does. It fixes the previous > regression. That sounds like the right approach to me. > Is there a case I am missing? That is, a case where CopyRegToReg was > correctly creating a NEON move but NEONMoveFixPass fails to convert? > The tests found nothing. Go ahead and commit. If there are any cases like that, we'll fix NEONMoveFixPass. /jakob From rafael.espindola at gmail.com Tue Jul 6 11:24:34 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Tue, 06 Jul 2010 16:24:34 -0000 Subject: [llvm-commits] [llvm] r107673 - in /llvm/trunk: lib/Target/ARM/ARMBaseInstrInfo.cpp test/CodeGen/ARM/vget_lane.ll Message-ID: <20100706162434.D46BE2A6C12C@llvm.org> Author: rafael Date: Tue Jul 6 11:24:34 2010 New Revision: 107673 URL: http://llvm.org/viewvc/llvm-project?rev=107673&view=rev Log: Don't create neon moves in CopyRegToReg. NEONMoveFixPass will do the conversion if profitable. Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm/trunk/test/CodeGen/ARM/vget_lane.ll Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=107673&r1=107672&r2=107673&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Jul 6 11:24:34 2010 @@ -718,6 +718,12 @@ if (SrcRC == ARM::DPR_8RegisterClass) SrcRC = ARM::DPR_VFP2RegisterClass; + // NEONMoveFixPass will convert VFP moves to NEON moves when profitable. + if (DestRC == ARM::DPR_VFP2RegisterClass) + DestRC = ARM::DPRRegisterClass; + if (SrcRC == ARM::DPR_VFP2RegisterClass) + SrcRC = ARM::DPRRegisterClass; + // Allow QPR / QPR_VFP2 / QPR_8 cross-class copies. if (DestRC == ARM::QPR_VFP2RegisterClass || DestRC == ARM::QPR_8RegisterClass) @@ -750,10 +756,6 @@ Opc = (SrcRC == ARM::GPRRegisterClass ? ARM::VMOVSR : ARM::VMOVS); else if (DestRC == ARM::DPRRegisterClass) Opc = ARM::VMOVD; - else if (DestRC == ARM::DPR_VFP2RegisterClass || - SrcRC == ARM::DPR_VFP2RegisterClass) - // Always use neon reg-reg move if source or dest is NEON-only regclass. - Opc = ARM::VMOVDneon; else if (DestRC == ARM::QPRRegisterClass) Opc = ARM::VMOVQ; else if (DestRC == ARM::QQPRRegisterClass) Modified: llvm/trunk/test/CodeGen/ARM/vget_lane.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vget_lane.ll?rev=107673&r1=107672&r2=107673&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vget_lane.ll (original) +++ llvm/trunk/test/CodeGen/ARM/vget_lane.ll Tue Jul 6 11:24:34 2010 @@ -205,7 +205,7 @@ define arm_aapcs_vfpcc <2 x float> @test_vset_lanef32(float %arg0_float32_t, <2 x float> %arg1_float32x2_t) nounwind { ;CHECK: test_vset_lanef32: ;CHECK: vmov.f32 s3, s0 -;CHECK: vmov d0, d1 +;CHECK: vmov.f64 d0, d1 entry: %0 = insertelement <2 x float> %arg1_float32x2_t, float %arg0_float32_t, i32 1 ; <<2 x float>> [#uses=1] ret <2 x float> %0 From wdietz2 at illinois.edu Tue Jul 6 12:10:37 2010 From: wdietz2 at illinois.edu (Will Dietz) Date: Tue, 06 Jul 2010 17:10:37 -0000 Subject: [llvm-commits] [poolalloc] r107674 - /poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp Message-ID: <20100706171037.864502A6C12C@llvm.org> Author: wdietz2 Date: Tue Jul 6 12:10:37 2010 New Revision: 107674 URL: http://llvm.org/viewvc/llvm-project?rev=107674&view=rev Log: Added comments on what to fix from today's code review. Removed unnecessary whitespace. No functionality changes. Modified: poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp Modified: poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp?rev=107674&r1=107673&r2=107674&view=diff ============================================================================== --- poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp (original) +++ poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp Tue Jul 6 12:10:37 2010 @@ -54,7 +54,7 @@ // alloca instruction because it is allocated within the current function. std::multimap &PoolUses; - // PoolDestroys - For each pool, keep track of the actual poolfree calls + // PoolFrees - For each pool, keep track of the actual poolfree calls // inserted into the code. This is seperated out from PoolUses. std::multimap &PoolFrees; @@ -67,10 +67,12 @@ template void AddPoolUse(InstType &I, Value *PoolHandle, SetType &Set) { + // FIXME: Strip away pointer casts if (AllocaInst *AI = dyn_cast(PoolHandle)) Set.insert(std::make_pair(AI, &I)); } + // FIXME: Factor out assumptions about c stdlib function names void visitInstruction(Instruction &I); //void visitMallocInst(MallocInst &MI); void visitAllocaInst(AllocaInst &MI); @@ -129,6 +131,7 @@ return G->getScalarMap()[getOldValueIfAvailable(V)]; } + // FIXME: Does this get global (or just local) pools? Value *getPoolHandle(Value *V) { DSNode *Node = getDSNodeHFor(V).getNode(); // Get the pool handle for this DSNode... @@ -136,7 +139,7 @@ FI.PoolDescriptors.find(Node); return I != FI.PoolDescriptors.end() ? I->second : 0; } - + Function* retCloneIfFunc(Value *V); }; } @@ -152,6 +155,9 @@ // Returns the clone if V is a static function (not a pointer) and belongs // to an equivalence class i.e. is pool allocated +// FIXME: Rename this to 'getCloneIfFunc' (or similar)? +// FIXME: Strip pointer casts +// FIXME: Comment this? Function* FuncTransform::retCloneIfFunc(Value *V) { if (Function *F = dyn_cast(V)) if (FuncInfo *FI = PAInfo.getFuncInfo(*F)) @@ -174,28 +180,32 @@ Instruction *FuncTransform::TransformAllocationInstr(Instruction *I, Value *Size) { + // Ensure that the new instruction has the same name as the old one + // and the that the old one has no name. std::string Name = I->getName(); I->setName(""); + // FIXME: Don't assume allocation sizes are 32bit--this differs per architecture! if (!Size->getType()->isIntegerTy(32)) Size = CastInst::CreateIntegerCast(Size, Type::getInt32Ty(Size->getType()->getContext()), false, Size->getName(), I); - // Insert a call to poolalloc - Value *PH = getPoolHandle(I); + // Get the pool handle-- // Do not change the instruction into a poolalloc() call unless we have a // real pool descriptor + Value *PH = getPoolHandle(I); if (PH == 0 || isa(PH)) return I; - + + // Create call to poolalloc, and record the use of the pool Value* Opts[2] = {PH, Size}; Instruction *V = CallInst::Create(PAInfo.PoolAlloc, Opts, Opts + 2, Name, I); - AddPoolUse(*V, PH, PoolUses); // Cast to the appropriate type if necessary + // FIXME: Make use of "castTo" utility function Instruction *Casted = V; if (V->getType() != I->getType()) Casted = CastInst::CreatePointerCast(V, I->getType(), V->getName(), I); - + // Update def-use info I->replaceAllUsesWith(Casted); @@ -211,6 +221,7 @@ // If this was an invoke, fix up the CFG. if (InvokeInst *II = dyn_cast(I)) { + // FIXME: Assert out since we potentially don't handle "invoke" correctly BranchInst::Create (II->getNormalDest(), I); II->getUnwindDest()->removePredecessor(II->getParent(), true); } @@ -278,7 +289,7 @@ #endif void FuncTransform::visitAllocaInst(AllocaInst &MI) { - // + // FIXME: We should remove SAFECode-specific functionality (and comments) // SAFECode will register alloca instructions with the run-time, so do not // do that here. // @@ -303,6 +314,7 @@ // // Return value: // NULL - No call to poolfree() was inserted. +// This may be possible if PoolAlloc has decided not to pool-allocate this. // Otherwise, a pointer to the call instruction that calls poolfree() will be // returned. // @@ -318,6 +330,7 @@ // // Cast the pointer to be freed to a void pointer type if necessary. // + // FIXME: Change this to make use of "castTo" utility. Value *Casted = Arg; if (Arg->getType() != PointerType::getUnqual(Type::getInt8Ty(Arg->getContext()))) { Casted = CastInst::CreatePointerCast(Arg, PointerType::getUnqual(Type::getInt8Ty(Arg->getContext())), @@ -326,7 +339,7 @@ } // - // Insert a call to poolfree() + // Insert a call to poolfree(), and mark that memory was deallocated from the pool. // Value* Opts[2] = {PH, Casted}; CallInst *FreeI = CallInst::Create(PAInfo.PoolFree, Opts, Opts + 2, "", Where); @@ -339,7 +352,7 @@ if (Instruction *I = InsertPoolFreeInstr(FrI.getOperand(0), &FrI)) { // Delete the now obsolete free instruction... FrI.getParent()->getInstList().erase(&FrI); - + // Update the NewToOldValueMap if this is a clone if (!FI.NewToOldValueMap.empty()) { std::map::iterator II = @@ -361,9 +374,11 @@ Instruction * InsertPt = CS.getInstruction(); if (Instruction *I = InsertPoolFreeInstr (CS.getArgument(0), InsertPt)) { // Delete the now obsolete free instruction... + // FIXME: use "eraseFromParent"? (Note this might require a refactoring) InsertPt->getParent()->getInstList().erase(InsertPt); // Update the NewToOldValueMap if this is a clone + // FIXME: Use of utility function UpdateNewToOldValueMap if (!FI.NewToOldValueMap.empty()) { std::map::iterator II = FI.NewToOldValueMap.find(InsertPt); @@ -385,6 +400,7 @@ // // Get the pool handle for the node that this contributes to... // + // FIXME: This check may be redundant Value *PH = getPoolHandle(MI); if (PH == 0 || isa(PH)) return; @@ -396,7 +412,7 @@ // // Transform the allocation site to use poolalloc(). // - TransformAllocationInstr(MI, AllocSize); + TransformAllocationInstr(MI, AllocSize); } @@ -406,8 +422,13 @@ const Type* Int32Type = Type::getInt32Ty(CS.getInstruction()->getContext()); const Type* Int64Type = Type::getInt64Ty(CS.getInstruction()->getContext()); + // FIXME: Ensure that we use 32/64-bit object length sizes consistently + // FIXME: Rename 'useLong' to something more descriptive? + // FIXME: Introduce 'ObjectAllocationSize' variable + // or similar instead of repeatedly using same expression + // XXX: Start new review session here *** bool useLong = TD.getTypeAllocSize(PointerType::getUnqual(Int8Type)) != 4; - + Module *M = CS.getInstruction()->getParent()->getParent()->getParent(); assert(CS.arg_end()-CS.arg_begin() == 2 && "calloc takes two arguments!"); Value *V1 = CS.getArgument(0); @@ -955,6 +976,8 @@ // transformed calls. Many instructions can "take the address of" a function, // and we must make sure to catch each of these uses, and transform it into a // reference to the new, transformed, function. +// FIXME: Don't rename uses of function names that escape +// FIXME: Special-case when external user is pthread_create (or similar)? void FuncTransform::visitInstruction(Instruction &I) { for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) if (Function *clonedFunc = retCloneIfFunc(I.getOperand(i))) { From rjmccall at apple.com Tue Jul 6 13:07:52 2010 From: rjmccall at apple.com (John McCall) Date: Tue, 06 Jul 2010 18:07:52 -0000 Subject: [llvm-commits] [llvm] r107677 - /llvm/trunk/include/llvm/Support/IRBuilder.h Message-ID: <20100706180752.B856D2A6C12C@llvm.org> Author: rjmccall Date: Tue Jul 6 13:07:52 2010 New Revision: 107677 URL: http://llvm.org/viewvc/llvm-project?rev=107677&view=rev Log: Provide an abstraction to save and restore the current insertion point of an IRBuilder. Modified: llvm/trunk/include/llvm/Support/IRBuilder.h Modified: llvm/trunk/include/llvm/Support/IRBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/IRBuilder.h?rev=107677&r1=107676&r2=107677&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/IRBuilder.h (original) +++ llvm/trunk/include/llvm/Support/IRBuilder.h Tue Jul 6 13:07:52 2010 @@ -97,6 +97,48 @@ I->setDebugLoc(CurDbgLocation); } + /// InsertPoint - A saved insertion point. + class InsertPoint { + BasicBlock *Block; + BasicBlock::iterator Point; + + public: + /// Creates a new insertion point which doesn't point to anything. + InsertPoint() : Block(0) {} + + /// Creates a new insertion point at the given location. + InsertPoint(BasicBlock *InsertBlock, BasicBlock::iterator InsertPoint) + : Block(InsertBlock), Point(InsertPoint) {} + + /// isSet - Returns true if this insert point is set. + bool isSet() const { return (Block != 0); } + + llvm::BasicBlock *getBlock() const { return Block; } + llvm::BasicBlock::iterator getPoint() const { return Point; } + }; + + /// saveIP - Returns the current insert point. + InsertPoint saveIP() const { + return InsertPoint(GetInsertBlock(), GetInsertPoint()); + } + + /// saveAndClearIP - Returns the current insert point, clearing it + /// in the process. + InsertPoint saveAndClearIP() { + InsertPoint IP(GetInsertBlock(), GetInsertPoint()); + ClearInsertionPoint(); + return IP; + } + + /// restoreIP - Sets the current insert point to a previously-saved + /// location. + void restoreIP(InsertPoint IP) { + if (IP.isSet()) + SetInsertPoint(IP.getBlock(), IP.getPoint()); + else + ClearInsertionPoint(); + } + //===--------------------------------------------------------------------===// // Miscellaneous creation methods. //===--------------------------------------------------------------------===// From dpatel at apple.com Tue Jul 6 13:18:32 2010 From: dpatel at apple.com (Devang Patel) Date: Tue, 06 Jul 2010 18:18:32 -0000 Subject: [llvm-commits] [llvm] r107678 - in /llvm/trunk: lib/Target/X86/AsmPrinter/X86MCInstLower.cpp test/CodeGen/X86/2010-07-06-DbgCrash.ll Message-ID: <20100706181832.4A4402A6C12C@llvm.org> Author: dpatel Date: Tue Jul 6 13:18:32 2010 New Revision: 107678 URL: http://llvm.org/viewvc/llvm-project?rev=107678&view=rev Log: Fix PR7545 crash. Added: llvm/trunk/test/CodeGen/X86/2010-07-06-DbgCrash.ll Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp?rev=107678&r1=107677&r2=107678&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp Tue Jul 6 13:18:32 2010 @@ -505,7 +505,6 @@ O << V.getName(); O << " <- "; // Frame address. Currently handles register +- offset only. - assert(MI->getOperand(0).isReg() && MI->getOperand(3).isImm()); O << '['; printOperand(MI, 0, O); O << '+'; printOperand(MI, 3, O); O << ']'; O << "+"; @@ -517,8 +516,9 @@ MachineLocation Location; assert (MI->getNumOperands() == 7 && "Invalid no. of machine operands!"); // Frame address. Currently handles register +- offset only. - assert(MI->getOperand(0).isReg() && MI->getOperand(3).isImm()); - Location.set(MI->getOperand(0).getReg(), MI->getOperand(3).getImm()); + + if (MI->getOperand(0).isReg() && MI->getOperand(3).isImm()) + Location.set(MI->getOperand(0).getReg(), MI->getOperand(3).getImm()); return Location; } Added: llvm/trunk/test/CodeGen/X86/2010-07-06-DbgCrash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-07-06-DbgCrash.ll?rev=107678&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2010-07-06-DbgCrash.ll (added) +++ llvm/trunk/test/CodeGen/X86/2010-07-06-DbgCrash.ll Tue Jul 6 13:18:32 2010 @@ -0,0 +1,29 @@ +; RUN: llc -O0 -relocation-model pic -o /dev/null +; PR7545 + at .str = private constant [4 x i8] c"one\00", align 1 ; <[4 x i8]*> [#uses=1] + at .str1 = private constant [4 x i8] c"two\00", align 1 ; <[5 x i8]*> [#uses=1] + at C.9.2167 = internal constant [2 x i8*] [i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), i8* getelementptr inbounds ([4 x i8]* @.str1, i64 0, i64 0)] +!38 = metadata !{i32 524329, metadata !"pbmsrch.c", metadata !"/Users/grawp/LLVM/test-suite/MultiSource/Benchmarks/MiBench/office-stringsearch", metadata !39} ; [ DW_TAG_file_type ] +!39 = metadata !{i32 524305, i32 0, i32 1, metadata !"pbmsrch.c", metadata !"/Users/grawp/LLVM/test-suite/MultiSource/Benchmarks/MiBench/office-stringsearch", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build 9999)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!46 = metadata !{i32 524303, metadata !38, metadata !"", metadata !38, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !47} ; [ DW_TAG_pointer_type ]!97 = metadata !{i32 524334, i32 0, metadata !38, metadata !"main", metadata !"main", metadata !"main", metadata !38, i32 73, metadata !98, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]!101 = metadata !{[2 x i8*]* @C.9.2167} +!47 = metadata !{i32 524324, metadata !38, metadata !"char", metadata !38, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] +!97 = metadata !{i32 524334, i32 0, metadata !38, metadata !"main", metadata !"main", metadata !"main", metadata !38, i32 73, metadata !98, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ] +!98 = metadata !{i32 524309, metadata !38, metadata !"", metadata !38, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !99, i32 0, null} ; [ DW_TAG_subroutine_type ] +!99 = metadata !{metadata !100} +!100 = metadata !{i32 524324, metadata !38, metadata !"int", metadata !38, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!101 = metadata !{[2 x i8*]* @C.9.2167} +!102 = metadata !{i32 524544, metadata !103, metadata !"find_strings", metadata !38, i32 75, metadata !104} ; [ DW_TAG_auto_variable ] +!103 = metadata !{i32 524299, metadata !97, i32 73, i32 0} ; [ DW_TAG_lexical_block ] +!104 = metadata !{i32 524289, metadata !38, metadata !"", metadata !38, i32 0, i64 85312, i64 64, i64 0, i32 0, metadata !46, metadata !105, i32 0, null} ; [ DW_TAG_array_type ] +!105 = metadata !{metadata !106} +!106 = metadata !{i32 524321, i64 0, i64 1332} ; [ DW_TAG_subrange_type ] +!107 = metadata !{i32 73, i32 0, metadata !103, null} + +define i32 @main() nounwind ssp { +bb.nph: + tail call void @llvm.dbg.declare(metadata !101, metadata !102), !dbg !107 + ret i32 0, !dbg !107 +} + +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + From nicholas at mxc.ca Tue Jul 6 13:24:09 2010 From: nicholas at mxc.ca (Nick Lewycky) Date: Tue, 06 Jul 2010 18:24:09 -0000 Subject: [llvm-commits] [llvm] r107680 - /llvm/trunk/docs/LangRef.html Message-ID: <20100706182410.2CBF42A6C12C@llvm.org> Author: nicholas Date: Tue Jul 6 13:24:09 2010 New Revision: 107680 URL: http://llvm.org/viewvc/llvm-project?rev=107680&view=rev Log: Alphabetize the list of function parameters. Modified: llvm/trunk/docs/LangRef.html Modified: llvm/trunk/docs/LangRef.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=107680&r1=107679&r2=107680&view=diff ============================================================================== --- llvm/trunk/docs/LangRef.html (original) +++ llvm/trunk/docs/LangRef.html Tue Jul 6 13:24:09 2010 @@ -1147,15 +1147,21 @@ this function is desirable (such as the "inline" keyword in C/C++). It is just a hint; it imposes no requirements on the inliner. + naked + This attribute disables prologue / epilogue emission for the function. + This can have very system-specific consequences. + + noimplicitfloat + This attributes disables implicit floating point instructions. + noinline This attribute indicates that the inliner should never inline this function in any situation. This attribute may not be used together with the alwaysinline attribute. - optsize - This attribute suggests that optimization passes and code generator passes - make choices that keep the code size of this function low, and otherwise - do optimizations specifically to reduce code size. + noredzone + This attribute indicates that the code generator should not use a red + zone, even if the target-specific ABI normally permits it. noreturn This function attribute indicates that the function never returns @@ -1167,6 +1173,11 @@ unwind or exceptional control flow. If the function does unwind, its runtime behavior is undefined. + optsize + This attribute suggests that optimization passes and code generator passes + make choices that keep the code size of this function low, and otherwise + do optimizations specifically to reduce code size. + readnone This attribute indicates that the function computes its result (or decides to unwind an exception) based strictly on its arguments, without @@ -1209,17 +1220,6 @@ function that doesn't have an sspreq attribute or which has an ssp attribute, then the resulting function will have an sspreq attribute. - - noredzone - This attribute indicates that the code generator should not use a red - zone, even if the target-specific ABI normally permits it. - - noimplicitfloat - This attributes disables implicit floating point instructions. - - naked - This attribute disables prologue / epilogue emission for the function. - This can have very system-specific consequences.

-$ cvs -z 3 -d :pserver:anoncvs at sourceware.org:/cvs/src co gdb -$ mv src gdb # You probably don't want this checkout called "src". -$ cd gdb -$ ./configure --prefix="$GDB_INSTALL" -$ make -$ make install -

@@ -119,7 +56,9 @@

 # Compile foo.c to bitcode.  You can use either clang or llvm-gcc with this
 # command line.  Both require -fexceptions, or the calls are all marked
-# 'nounwind' which disables DWARF CFA info.
+# 'nounwind' which disables DWARF exception handling info.  Custom frontends
+# should avoid adding this attribute to JITed code, since it interferes with
+# DWARF CFA generation at the moment.
 $ clang foo.c -fexceptions -emit-llvm -c -o foo.bc
 
 # Run foo.bc under lli with -jit-emit-debug.  If you built lli in debug mode,
@@ -143,18 +82,60 @@
 #3  0x00007ffff7f5502a in main ()
 #4  0x00000000007c0225 in llvm::JIT::runFunction(llvm::Function*,
     std::vector<llvm::GenericValue,
-    std::allocator<llvm::GenericValue> > const&) ()
+    std::allocator<llvm::GenericValue> > const&) ()
 #5  0x00000000007d6d98 in
     llvm::ExecutionEngine::runFunctionAsMain(llvm::Function*,
     std::vector<std::string,
-    std::allocator<std::string> > const&, char const* const*) ()
+    std::allocator<std::string> > const&, char const* const*) ()
 #6  0x00000000004dab76 in main ()

This makefile specifies that all of the .cpp files in the current directory are to be compiled and linked together into a -Debug/lib/Hello.so shared object that can be dynamically loaded by +Debug+Asserts/lib/Hello.so shared object that can be dynamically loaded by the opt or bugpoint tools via their -load options. If your operating system uses a suffix other than .so (such as windows or Mac OS/X), the appropriate extension will be used.

Now that it's all together, compile the file with a simple "gmake" command in the local directory and you should get a new -"Debug/lib/Hello.so file. Note that everything in this file is +"Debug+Asserts/lib/Hello.so file. Note that everything in this file is contained in an anonymous namespace: this reflects the fact that passes are self contained units that do not need external interfaces (although they can have them) to be useful.

-$ opt -load ../../../Debug/lib/Hello.so -hello < hello.bc > /dev/null
+$ opt -load ../../../Debug+Asserts/lib/Hello.so -hello < hello.bc > /dev/null
 Hello: __main
 Hello: puts
 Hello: main
@@ -375,7 +375,7 @@
 opt with the -help option:
 
 -$ opt -load ../../../Debug/lib/Hello.so -help
+$ opt -load ../../../Debug+Asserts/lib/Hello.so -help
 OVERVIEW: llvm .bc -> .bc modular optimizer
 
 USAGE: opt [options] <input bitcode>
@@ -403,7 +403,7 @@
 example:
 
 -$ opt -load ../../../Debug/lib/Hello.so -hello -time-passes < hello.bc > /dev/null
+$ opt -load ../../../Debug+Asserts/lib/Hello.so -hello -time-passes < hello.bc > /dev/null
 Hello: __main
 Hello: puts
 Hello: main
@@ -1418,7 +1418,7 @@
 Lets try it out with the gcse and licm passes:
 
 -$ opt -load ../../../Debug/lib/Hello.so -gcse -licm --debug-pass=Structure < hello.bc > /dev/null
+$ opt -load ../../../Debug+Asserts/lib/Hello.so -gcse -licm --debug-pass=Structure < hello.bc > /dev/null
 Module Pass Manager
   Function Pass Manager
     Dominator Set Construction
@@ -1455,7 +1455,7 @@
 World pass in between the two passes:
 
 -$ opt -load ../../../Debug/lib/Hello.so -gcse -hello -licm --debug-pass=Structure < hello.bc > /dev/null
+$ opt -load ../../../Debug+Asserts/lib/Hello.so -gcse -hello -licm --debug-pass=Structure < hello.bc > /dev/null
 Module Pass Manager
   Function Pass Manager
     Dominator Set Construction
@@ -1496,7 +1496,7 @@
 Now when we run our pass, we get this output:
 
 -$ opt -load ../../../Debug/lib/Hello.so -gcse -hello -licm --debug-pass=Structure < hello.bc > /dev/null
+$ opt -load ../../../Debug+Asserts/lib/Hello.so -gcse -hello -licm --debug-pass=Structure < hello.bc > /dev/null
 Pass Arguments:  -gcse -hello -licm
 Module Pass Manager
   Function Pass Manager
@@ -1737,8 +1737,8 @@
  (gdb) break llvm::PassManager::run
 Breakpoint 1 at 0x2413bc: file Pass.cpp, line 70.
-(gdb) run test.bc -load $(LLVMTOP)/llvm/Debug/lib/[libname].so -[passoption]
-Starting program: opt test.bc -load $(LLVMTOP)/llvm/Debug/lib/[libname].so -[passoption]
+(gdb) run test.bc -load $(LLVMTOP)/llvm/Debug+Asserts/lib/[libname].so -[passoption]
+Starting program: opt test.bc -load $(LLVMTOP)/llvm/Debug+Asserts/lib/[libname].so -[passoption]
 Breakpoint 1, PassManager::run (this=0xffbef174, M=@0x70b298) at Pass.cpp:70
 70      bool PassManager::run(Module &M) { return PM->run(M); }
 (gdb)




From benny.kra at googlemail.com  Thu Jul  8 06:29:03 2010
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Thu, 8 Jul 2010 13:29:03 +0200
Subject: [llvm-commits] [PATCH] Add a instcombine optimization.
In-Reply-To: <4C357A78.2090005@free.fr>
References: <5728FE48-1EF0-4A7B-A11D-AE2E95B40227@gmail.com>
	<4C357A78.2090005@free.fr>
Message-ID: <4A50AB2D-4D4B-4EC0-A6A3-2F9457C6FD9C@gmail.com>


On 08.07.2010, at 09:12, Duncan Sands wrote:

> Hi Benjamin,
> 
>> The attached patch adds a new transformation to instcombine:
>> (X>s -1) ? C1 : C2 -->  ((X>>s 31)&  (C2 - C1)) + C1
> 
> how about (X >s -1) ? C1 : C2 -->  ((X >>s 31) & (C2 xor C1)) xor C1
> instead?  It might interact better with other bit fiddling optimizations.
> Otherwise the patch looks good.

Hmm, but we wont get a lea on x86 with xor. I don't think xor is profitable
unless we extend the optimization to transform non-const C1 and C2 too.


From benny.kra at googlemail.com  Thu Jul  8 06:39:10 2010
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Thu, 08 Jul 2010 11:39:10 -0000
Subject: [llvm-commits] [llvm] r107866 - in /llvm/trunk:
 lib/Target/README.txt lib/Transforms/InstCombine/InstCombineSelect.cpp
 test/Transforms/InstCombine/select.ll
Message-ID: <20100708113911.0859E2A6C12C@llvm.org>

Author: d0k
Date: Thu Jul  8 06:39:10 2010
New Revision: 107866

URL: http://llvm.org/viewvc/llvm-project?rev=107866&view=rev
Log:
Teach instcombine to transform
(X >s -1) ? C1 : C2 and (X >s 31) & (C2 - C1)) + C1, avoiding the conditional.

This optimization could be extended to take non-const C1 and C2 but we better
stay conservative to avoid code size bloat for now.

for
int sel(int n) {
     return n >= 0 ? 60 : 100;
}

we now generate
  sarl  $31, %edi
  andl  $40, %edi
  leal  60(%rdi), %eax

instead of
  testl %edi, %edi
  movl  $60, %ecx
  movl  $100, %eax
  cmovnsl %ecx, %eax

Modified:
    llvm/trunk/lib/Target/README.txt
    llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp
    llvm/trunk/test/Transforms/InstCombine/select.ll

Modified: llvm/trunk/lib/Target/README.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/README.txt?rev=107866&r1=107865&r2=107866&view=diff
==============================================================================
--- llvm/trunk/lib/Target/README.txt (original)
+++ llvm/trunk/lib/Target/README.txt Thu Jul  8 06:39:10 2010
@@ -906,17 +906,6 @@
 
 //===---------------------------------------------------------------------===//
 
-From GCC Bug 3756:
-int
-pn (int n)
-{
- return (n >= 0 ? 1 : -1);
-}
-Should combine to (n >> 31) | 1.  Currently not optimized with "clang
--emit-llvm-bc | opt -std-compile-opts | llc".
-
-//===---------------------------------------------------------------------===//
-
 void a(int variable)
 {
  if (variable == 4 || variable == 6)

Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp?rev=107866&r1=107865&r2=107866&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp Thu Jul  8 06:39:10 2010
@@ -329,6 +329,37 @@
       }
     }
 
+  // Transform (X >s -1) ? C1 : C2 --> ((X >>s 31) & (C2 - C1)) + C1
+  // and       (X  ((X >>s 31) & (C2 - C1)) + C1
+  // FIXME: Type and constness constraints could be lifted, but we have to
+  //        watch code size carefully. We should consider xor instead of
+  //        sub/add when we decide to do that.
+  if (const IntegerType *Ty = dyn_cast(CmpLHS->getType())) {
+    if (TrueVal->getType() == Ty) {
+      if (ConstantInt *Cmp = dyn_cast(CmpRHS)) {
+        ConstantInt *C1 = NULL, *C2 = NULL;
+        if (Pred == ICmpInst::ICMP_SGT && Cmp->isAllOnesValue()) {
+          C1 = dyn_cast(TrueVal);
+          C2 = dyn_cast(FalseVal);
+        } else if (Pred == ICmpInst::ICMP_SLT && Cmp->isNullValue()) {
+          C1 = dyn_cast(FalseVal);
+          C2 = dyn_cast(TrueVal);
+        }
+        if (C1 && C2) {
+          // This shift results in either -1 or 0.
+          Value *AShr = Builder->CreateAShr(CmpLHS, Ty->getBitWidth()-1);
+
+          // Check if we can express the operation with a single or.
+          if (C2->isAllOnesValue())
+            return ReplaceInstUsesWith(SI, Builder->CreateOr(AShr, C1));
+
+          Value *And = Builder->CreateAnd(AShr, C2->getValue()-C1->getValue());
+          return ReplaceInstUsesWith(SI, Builder->CreateAdd(And, C1));
+        }
+      }
+    }
+  }
+
   if (CmpLHS == TrueVal && CmpRHS == FalseVal) {
     // Transform (X == Y) ? X : Y  -> Y
     if (Pred == ICmpInst::ICMP_EQ)

Modified: llvm/trunk/test/Transforms/InstCombine/select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/select.ll?rev=107866&r1=107865&r2=107866&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/select.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/select.ll Thu Jul  8 06:39:10 2010
@@ -438,3 +438,35 @@
 ; CHECK: @test34
 ; CHECK: ret i32 %x
 }
+
+define i32 @test35(i32 %x) {
+  %cmp = icmp sge i32 %x, 0
+  %cond = select i1 %cmp, i32 60, i32 100
+  ret i32 %cond
+; CHECK: @test35
+; CHECK: ashr i32 %x, 31
+; CHECK: and i32 {{.*}}, 40
+; CHECK: add i32 {{.*}}, 60
+; CHECK: ret
+}
+
+define i32 @test36(i32 %x) {
+  %cmp = icmp slt i32 %x, 0
+  %cond = select i1 %cmp, i32 60, i32 100
+  ret i32 %cond
+; CHECK: @test36
+; CHECK: ashr i32 %x, 31
+; CHECK: and i32 {{.*}}, -40
+; CHECK: add i32 {{.*}}, 100
+; CHECK: ret
+}
+
+define i32 @test37(i32 %x) {
+  %cmp = icmp sgt i32 %x, -1
+  %cond = select i1 %cmp, i32 1, i32 -1
+  ret i32 %cond
+; CHECK: @test37
+; CHECK: ashr i32 %x, 31
+; CHECK: or i32 {{.*}}, 1
+; CHECK: ret
+}




From benny.kra at googlemail.com  Thu Jul  8 06:40:32 2010
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Thu, 8 Jul 2010 13:40:32 +0200
Subject: [llvm-commits] [PATCH] Add a instcombine optimization.
In-Reply-To: <4A50AB2D-4D4B-4EC0-A6A3-2F9457C6FD9C@gmail.com>
References: <5728FE48-1EF0-4A7B-A11D-AE2E95B40227@gmail.com>
	<4C357A78.2090005@free.fr>
	<4A50AB2D-4D4B-4EC0-A6A3-2F9457C6FD9C@gmail.com>
Message-ID: 


On 08.07.2010, at 13:29, Benjamin Kramer wrote:

> 
> On 08.07.2010, at 09:12, Duncan Sands wrote:
> 
>> Hi Benjamin,
>> 
>>> The attached patch adds a new transformation to instcombine:
>>> (X>s -1) ? C1 : C2 -->  ((X>>s 31)&  (C2 - C1)) + C1
>> 
>> how about (X >s -1) ? C1 : C2 -->  ((X >>s 31) & (C2 xor C1)) xor C1
>> instead?  It might interact better with other bit fiddling optimizations.
>> Otherwise the patch looks good.
> 
> Hmm, but we wont get a lea on x86 with xor. I don't think xor is profitable
> unless we extend the optimization to transform non-const C1 and C2 too.

I committed the patch along with a FIXME about xor in r107866.


From baldrick at free.fr  Thu Jul  8 06:54:27 2010
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 08 Jul 2010 11:54:27 -0000
Subject: [llvm-commits] [llvm] r107867 - in /llvm/trunk/include/llvm:
 ADT/PostOrderIterator.h Analysis/IntervalIterator.h
Message-ID: <20100708115427.D67BD2A6C12C@llvm.org>

Author: baldrick
Date: Thu Jul  8 06:54:27 2010
New Revision: 107867

URL: http://llvm.org/viewvc/llvm-project?rev=107867&view=rev
Log:
Do not use std::stack because it causes obscure failures when
compiled with MSVC 2010 (PR7367).  Instead use a SmallVector.

Modified:
    llvm/trunk/include/llvm/ADT/PostOrderIterator.h
    llvm/trunk/include/llvm/Analysis/IntervalIterator.h

Modified: llvm/trunk/include/llvm/ADT/PostOrderIterator.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/PostOrderIterator.h?rev=107867&r1=107866&r2=107867&view=diff
==============================================================================
--- llvm/trunk/include/llvm/ADT/PostOrderIterator.h (original)
+++ llvm/trunk/include/llvm/ADT/PostOrderIterator.h Thu Jul  8 06:54:27 2010
@@ -18,8 +18,8 @@
 
 #include "llvm/ADT/GraphTraits.h"
 #include "llvm/ADT/SmallPtrSet.h"
+#include "llvm/ADT/SmallVector.h"
 #include 
-#include 
 #include 
 
 namespace llvm {
@@ -52,21 +52,21 @@
 
   // VisitStack - Used to maintain the ordering.  Top = current block
   // First element is basic block pointer, second is the 'next child' to visit
-  std::stack > VisitStack;
+  SmallVector, 16> VisitStack;
 
   void traverseChild() {
-    while (VisitStack.top().second != GT::child_end(VisitStack.top().first)) {
-      NodeType *BB = *VisitStack.top().second++;
+    while (VisitStack.back().second != GT::child_end(VisitStack.back().first)) {
+      NodeType *BB = *VisitStack.back().second++;
       if (!this->Visited.count(BB)) {  // If the block is not visited...
         this->Visited.insert(BB);
-        VisitStack.push(std::make_pair(BB, GT::child_begin(BB)));
+        VisitStack.push_back(std::make_pair(BB, GT::child_begin(BB)));
       }
     }
   }
 
   inline po_iterator(NodeType *BB) {
     this->Visited.insert(BB);
-    VisitStack.push(std::make_pair(BB, GT::child_begin(BB)));
+    VisitStack.push_back(std::make_pair(BB, GT::child_begin(BB)));
     traverseChild();
   }
   inline po_iterator() {} // End is when stack is empty.
@@ -75,7 +75,7 @@
     po_iterator_storage(S) {
     if(!S.count(BB)) {
       this->Visited.insert(BB);
-      VisitStack.push(std::make_pair(BB, GT::child_begin(BB)));
+      VisitStack.push_back(std::make_pair(BB, GT::child_begin(BB)));
       traverseChild();
     }
   }
@@ -102,7 +102,7 @@
   inline bool operator!=(const _Self& x) const { return !operator==(x); }
 
   inline pointer operator*() const {
-    return VisitStack.top().first;
+    return VisitStack.back().first;
   }
 
   // This is a nonstandard operator-> that dereferences the pointer an extra
@@ -112,7 +112,7 @@
   inline NodeType *operator->() const { return operator*(); }
 
   inline _Self& operator++() {   // Preincrement
-    VisitStack.pop();
+    VisitStack.pop_back();
     if (!VisitStack.empty())
       traverseChild();
     return *this;

Modified: llvm/trunk/include/llvm/Analysis/IntervalIterator.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/IntervalIterator.h?rev=107867&r1=107866&r2=107867&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/IntervalIterator.h (original)
+++ llvm/trunk/include/llvm/Analysis/IntervalIterator.h Thu Jul  8 06:54:27 2010
@@ -33,10 +33,10 @@
 #ifndef LLVM_INTERVAL_ITERATOR_H
 #define LLVM_INTERVAL_ITERATOR_H
 
+#include "llvm/ADT/SmallVector.h"
 #include "llvm/Analysis/IntervalPartition.h"
 #include "llvm/Function.h"
 #include "llvm/Support/CFG.h"
-#include 
 #include 
 #include 
 
@@ -88,7 +88,7 @@
 template,
          class IGT = GraphTraits > >
 class IntervalIterator {
-  std::stack > IntStack;
+  SmallVector, 16> IntStack;
   std::set Visited;
   OrigContainer_t *OrigContainer;
   bool IOwnMem;     // If True, delete intervals when done with them
@@ -116,15 +116,15 @@
     if (IOwnMem)
       while (!IntStack.empty()) {
         delete operator*();
-        IntStack.pop();
+        IntStack.pop_back();
       }
   }
 
   inline bool operator==(const _Self& x) const { return IntStack == x.IntStack;}
   inline bool operator!=(const _Self& x) const { return !operator==(x); }
 
-  inline const Interval *operator*() const { return IntStack.top().first; }
-  inline       Interval *operator*()       { return IntStack.top().first; }
+  inline const Interval *operator*() const { return IntStack.back().first; }
+  inline       Interval *operator*()       { return IntStack.back().first; }
   inline const Interval *operator->() const { return operator*(); }
   inline       Interval *operator->()       { return operator*(); }
 
@@ -133,8 +133,8 @@
     do {
       // All of the intervals on the stack have been visited.  Try visiting
       // their successors now.
-      Interval::succ_iterator &SuccIt = IntStack.top().second,
-                                EndIt = succ_end(IntStack.top().first);
+      Interval::succ_iterator &SuccIt = IntStack.back().second,
+                                EndIt = succ_end(IntStack.back().first);
       while (SuccIt != EndIt) {                 // Loop over all interval succs
         bool Done = ProcessInterval(getSourceGraphNode(OrigContainer, *SuccIt));
         ++SuccIt;                               // Increment iterator
@@ -142,10 +142,10 @@
       }
 
       // Free interval memory... if necessary
-      if (IOwnMem) delete IntStack.top().first;
+      if (IOwnMem) delete IntStack.back().first;
 
       // We ran out of successors for this interval... pop off the stack
-      IntStack.pop();
+      IntStack.pop_back();
     } while (!IntStack.empty());
 
     return *this;
@@ -175,7 +175,7 @@
            E = GT::child_end(Node); I != E; ++I)
       ProcessNode(Int, getSourceGraphNode(OrigContainer, *I));
 
-    IntStack.push(std::make_pair(Int, succ_begin(Int)));
+    IntStack.push_back(std::make_pair(Int, succ_begin(Int)));
     return true;
   }
 




From benny.kra at googlemail.com  Thu Jul  8 07:09:56 2010
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Thu, 08 Jul 2010 12:09:56 -0000
Subject: [llvm-commits] [llvm] r107868 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Message-ID: <20100708120956.7F4412A6C12C@llvm.org>

Author: d0k
Date: Thu Jul  8 07:09:56 2010
New Revision: 107868

URL: http://llvm.org/viewvc/llvm-project?rev=107868&view=rev
Log:
Merge the duplicated iabs optimization in DAGCombiner and let it detected a few more idioms.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=107868&r1=107867&r2=107868&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Jul  8 07:09:56 2010
@@ -6892,38 +6892,34 @@
     }
   }
 
-  // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
+  // Check to see if this is an integer abs.
+  // select_cc setg[te] X,  0,  X, -X ->
+  // select_cc setgt    X, -1,  X, -X ->
+  // select_cc setl[te] X,  0, -X,  X ->
+  // select_cc setlt    X,  1, -X,  X ->
   // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
-  if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
-      N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) &&
-      N2.getOperand(0) == N1 && N0.getValueType().isInteger()) {
+  if (N1C) {
+    ConstantSDNode *SubC = NULL;
+    if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
+         (N1C->isAllOnesValue() && CC == ISD::SETGT)) &&
+        N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1))
+      SubC = dyn_cast(N3.getOperand(0));
+    else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) ||
+              (N1C->isOne() && CC == ISD::SETLT)) &&
+             N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1))
+      SubC = dyn_cast(N2.getOperand(0));
+
     EVT XType = N0.getValueType();
-    SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0,
-                                DAG.getConstant(XType.getSizeInBits()-1,
-                                                getShiftAmountTy()));
-    SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), XType,
-                              N0, Shift);
-    AddToWorkList(Shift.getNode());
-    AddToWorkList(Add.getNode());
-    return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
-  }
-  // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X ->
-  // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
-  if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT &&
-      N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) {
-    if (ConstantSDNode *SubC = dyn_cast(N3.getOperand(0))) {
-      EVT XType = N0.getValueType();
-      if (SubC->isNullValue() && XType.isInteger()) {
-        SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType,
-                                    N0,
-                                    DAG.getConstant(XType.getSizeInBits()-1,
-                                                    getShiftAmountTy()));
-        SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(),
-                                  XType, N0, Shift);
-        AddToWorkList(Shift.getNode());
-        AddToWorkList(Add.getNode());
-        return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
-      }
+    if (SubC && SubC->isNullValue() && XType.isInteger()) {
+      SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType,
+                                  N0,
+                                  DAG.getConstant(XType.getSizeInBits()-1,
+                                                  getShiftAmountTy()));
+      SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(),
+                                XType, N0, Shift);
+      AddToWorkList(Shift.getNode());
+      AddToWorkList(Add.getNode());
+      return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
     }
   }
 




From baldrick at free.fr  Thu Jul  8 08:06:08 2010
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 08 Jul 2010 13:06:08 -0000
Subject: [llvm-commits] [llvm] r107869 - in /llvm/trunk/include/llvm:
 ADT/PostOrderIterator.h Analysis/IntervalIterator.h
Message-ID: <20100708130608.96C702A6C12C@llvm.org>

Author: baldrick
Date: Thu Jul  8 08:06:08 2010
New Revision: 107869

URL: http://llvm.org/viewvc/llvm-project?rev=107869&view=rev
Log:
Use std::vector rather than SmallVector here because SmallVector
causes some versions of gcc to crash when building LLVM.

Modified:
    llvm/trunk/include/llvm/ADT/PostOrderIterator.h
    llvm/trunk/include/llvm/Analysis/IntervalIterator.h

Modified: llvm/trunk/include/llvm/ADT/PostOrderIterator.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/PostOrderIterator.h?rev=107869&r1=107868&r2=107869&view=diff
==============================================================================
--- llvm/trunk/include/llvm/ADT/PostOrderIterator.h (original)
+++ llvm/trunk/include/llvm/ADT/PostOrderIterator.h Thu Jul  8 08:06:08 2010
@@ -18,7 +18,6 @@
 
 #include "llvm/ADT/GraphTraits.h"
 #include "llvm/ADT/SmallPtrSet.h"
-#include "llvm/ADT/SmallVector.h"
 #include 
 #include 
 
@@ -52,7 +51,7 @@
 
   // VisitStack - Used to maintain the ordering.  Top = current block
   // First element is basic block pointer, second is the 'next child' to visit
-  SmallVector, 16> VisitStack;
+  std::vector > VisitStack;
 
   void traverseChild() {
     while (VisitStack.back().second != GT::child_end(VisitStack.back().first)) {

Modified: llvm/trunk/include/llvm/Analysis/IntervalIterator.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/IntervalIterator.h?rev=107869&r1=107868&r2=107869&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/IntervalIterator.h (original)
+++ llvm/trunk/include/llvm/Analysis/IntervalIterator.h Thu Jul  8 08:06:08 2010
@@ -33,12 +33,12 @@
 #ifndef LLVM_INTERVAL_ITERATOR_H
 #define LLVM_INTERVAL_ITERATOR_H
 
-#include "llvm/ADT/SmallVector.h"
 #include "llvm/Analysis/IntervalPartition.h"
 #include "llvm/Function.h"
 #include "llvm/Support/CFG.h"
-#include 
 #include 
+#include 
+#include 
 
 namespace llvm {
 
@@ -88,7 +88,7 @@
 template,
          class IGT = GraphTraits > >
 class IntervalIterator {
-  SmallVector, 16> IntStack;
+  std::vector > IntStack;
   std::set Visited;
   OrigContainer_t *OrigContainer;
   bool IOwnMem;     // If True, delete intervals when done with them




From espindola at google.com  Thu Jul  8 09:19:07 2010
From: espindola at google.com (Rafael Espindola)
Date: Thu, 8 Jul 2010 10:19:07 -0400
Subject: [llvm-commits] [patch] Fix va_arg for double and some cleanups
In-Reply-To: 
References: 
	<8F256730-8DB3-4855-86E0-38F60D7D148E@apple.com>
	
Message-ID: 

I think I found the correct method: getTransientStackAlignment.

The attached patch uses it. Is it OK?

Cheers,
-- 
Rafael ?vila de Esp?ndola
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From espindola at google.com  Thu Jul  8 09:34:29 2010
From: espindola at google.com (Rafael Espindola)
Date: Thu, 8 Jul 2010 10:34:29 -0400
Subject: [llvm-commits] [patch] Fix va_arg for double and some cleanups
In-Reply-To: 
References: 
	<8F256730-8DB3-4855-86E0-38F60D7D148E@apple.com>
	
	
Message-ID: 

Now with the comment fixed too.

Cheers,
-- 
Rafael ?vila de Esp?ndola
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From baldrick at free.fr  Thu Jul  8 10:10:11 2010
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 08 Jul 2010 17:10:11 +0200
Subject: [llvm-commits] [PATCH] Add a instcombine optimization.
In-Reply-To: <4A50AB2D-4D4B-4EC0-A6A3-2F9457C6FD9C@gmail.com>
References: <5728FE48-1EF0-4A7B-A11D-AE2E95B40227@gmail.com>
	<4C357A78.2090005@free.fr>
	<4A50AB2D-4D4B-4EC0-A6A3-2F9457C6FD9C@gmail.com>
Message-ID: <4C35EA53.7000607@free.fr>

Hi Benjamin,

>>> The attached patch adds a new transformation to instcombine:
>>> (X>s -1) ? C1 : C2 -->   ((X>>s 31)&   (C2 - C1)) + C1
>>
>> how about (X>s -1) ? C1 : C2 -->   ((X>>s 31)&  (C2 xor C1)) xor C1
>> instead?  It might interact better with other bit fiddling optimizations.
>> Otherwise the patch looks good.
>
> Hmm, but we wont get a lea on x86 with xor.

maybe this is a sign that it should be a DAGCombiner optimization rather
than an instcombine one?

Ciao,

Duncan.

I don't think xor is profitable
> unless we extend the optimization to transform non-const C1 and C2 too.




From grosbach at apple.com  Thu Jul  8 10:47:49 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 8 Jul 2010 08:47:49 -0700
Subject: [llvm-commits] [llvm] r107847 - in /llvm/trunk:
	include/llvm/CodeGen/RegisterScavenging.h	lib/CodeGen/PrologEpilogInserter.cpp
	lib/CodeGen/RegisterScavenging.cpp
In-Reply-To: <3DB6043D-A396-487E-AFA2-41EADC74803B@apple.com>
References: <20100708003854.AB2F12A6C12C@llvm.org>
	<70A40112-C2B9-4FA8-9765-4C158C40463F@2pi.dk>
	
	<3DB6043D-A396-487E-AFA2-41EADC74803B@apple.com>
Message-ID: <3D73D5BA-7463-471C-A76C-328421CCB6C4@apple.com>


On Jul 7, 2010, at 9:59 PM, Evan Cheng wrote:

> 
> 
> On Jul 7, 2010, at 7:48 PM, Jim Grosbach  wrote:
> 
>> 
>> On Jul 7, 2010, at 6:23 PM, Jakob Stoklund Olesen wrote:
>> 
>>> 
>>> On Jul 7, 2010, at 5:38 PM, Jim Grosbach wrote:
>>>> Modified: llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp
>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp?rev=107847&r1=107846&r2=107847&view=diff
>>>> ==============================================================================
>>>> --- llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp (original)
>>>> +++ llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp Wed Jul  7 19:38:54 2010
>>>> @@ -885,10 +885,20 @@
>>>>          // Scavenge a new scratch register
>>>>          CurrentVirtReg = Reg;
>>>>          const TargetRegisterClass *RC = Fn.getRegInfo().getRegClass(Reg);
>>>> -            CurrentScratchReg = RS->FindUnusedReg(RC);
>>>> -            if (CurrentScratchReg == 0)
>>>> +            const TargetRegisterInfo *TRI = Fn.getTarget().getRegisterInfo();
>>>> +            BitVector Candidates(TRI->getNumRegs());
>>>> +            RS->getRegsAvailable(RC, Candidates);
>>>> +
>>>> +            // If there are any registers available, use the one that's
>>>> +            // unused for the longest after this instruction. That increases
>>>> +            // the ability to reuse the value.
>>>> +            if (Candidates.any()) {
>>>> +              MachineBasicBlock::iterator UMI;
>>>> +              CurrentScratchReg = RS->findSurvivorReg(I, Candidates, 25, UMI);
>>>> +            } else {
>>>>            // No register is "free". Scavenge a register.
>>>>            CurrentScratchReg = RS->scavengeRegister(RC, I, SPAdj);
>>>> +            }
>>>> 
>>>>          PrevValue = Value;
>>>>        }
>>> 
>>> This looks like a method that escaped from RegScavenger. Isn't RegScavenger::scavengeRegister already doing this?
>>> 
>>> I think
>>> 
>>>             CurrentScratchReg = RS->scavengeRegister(RC, I, SPAdj);
>>> 
>>> is all you need.
>>> 
>>> 
>> 
>> It's close, but not quite. scavengeRegister() will find the register of the indicated register class that's used furthest away. It considers all registers of the register class as candidates, however, not just the available ones. Essentially, it's almost assuming that a spill will be required, but does have an early exit if for some reason it's called and finds a register that is available. That could just as easily be an assert, really.
>> 
>> Previously, we looked for an available register, taking the first one we noticed if one or more exists; otherwise, we called scavengeRegister() to find a reasonable choice to spill and free up a register to use. Now, we apply the same heuristic for "reasonable to use" to selecting amongst the available registers, not just when spilling.
> 
> Does it make sense to move the code into RS?

I think so, yes. I've been pondering whether it makes more sense to add a new method or to modify scavengeRegister() such that it'll incorporate this use-case directly. I'm leaning towards the latter, since as Jakob correctly points out, they're so similar already.


> Also, what's the magic number 25?
> 

Upper limit on how far ahead to scan for uses of the registers. That's the magic number the RS uses, so I mirrored that here. It would be better, I think, to change the operand order and give it a default value. I figured one change at a time, though, so didn't do that as part of the initial checkin.


> Evan
> 
>> 
>> -Jim
>> 
>> 
>> 
>> 
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits




From stoklund at 2pi.dk  Thu Jul  8 11:03:19 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Thu, 8 Jul 2010 09:03:19 -0700
Subject: [llvm-commits] [llvm] r107847 - in /llvm/trunk:
	include/llvm/CodeGen/RegisterScavenging.h	lib/CodeGen/PrologEpilogInserter.cpp
	lib/CodeGen/RegisterScavenging.cpp
In-Reply-To: <3D73D5BA-7463-471C-A76C-328421CCB6C4@apple.com>
References: <20100708003854.AB2F12A6C12C@llvm.org>
	<70A40112-C2B9-4FA8-9765-4C158C40463F@2pi.dk>
	
	<3DB6043D-A396-487E-AFA2-41EADC74803B@apple.com>
	<3D73D5BA-7463-471C-A76C-328421CCB6C4@apple.com>
Message-ID: 


On Jul 8, 2010, at 8:47 AM, Jim Grosbach wrote:
>>> It's close, but not quite. scavengeRegister() will find the register of the indicated register class that's used furthest away. It considers all registers of the register class as candidates, however, not just the available ones. Essentially, it's almost assuming that a spill will be required, but does have an early exit if for some reason it's called and finds a register that is available. That could just as easily be an assert, really.
>>> 
>>> Previously, we looked for an available register, taking the first one we noticed if one or more exists; otherwise, we called scavengeRegister() to find a reasonable choice to spill and free up a register to use. Now, we apply the same heuristic for "reasonable to use" to selecting amongst the available registers, not just when spilling.
>> 
>> Does it make sense to move the code into RS?
> 
> I think so, yes. I've been pondering whether it makes more sense to add a new method or to modify scavengeRegister() such that it'll incorporate this use-case directly. I'm leaning towards the latter, since as Jakob correctly points out, they're so similar already.

It should be as simple as:

if ((Candidates & RegsAvailable).any())
  Candidates &= RegsAvailable:

in the right place.





From bob.wilson at apple.com  Thu Jul  8 11:03:09 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Thu, 08 Jul 2010 16:03:09 -0000
Subject: [llvm-commits] [zorg] r107876 - /zorg/trunk/lnt/lnt/tests/nt.py
Message-ID: <20100708160309.282E82A6C12C@llvm.org>

Author: bwilson
Date: Thu Jul  8 11:03:08 2010
New Revision: 107876

URL: http://llvm.org/viewvc/llvm-project?rev=107876&view=rev
Log:
Fix setting of DISABLE_ASSERTIONS.  For some reason, our makefiles are
inconsistent and use DISABLE_ASSERTIONS instead of ENABLE_ASSERTIONS.

Modified:
    zorg/trunk/lnt/lnt/tests/nt.py

Modified: zorg/trunk/lnt/lnt/tests/nt.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/tests/nt.py?rev=107876&r1=107875&r2=107876&view=diff
==============================================================================
--- zorg/trunk/lnt/lnt/tests/nt.py (original)
+++ zorg/trunk/lnt/lnt/tests/nt.py Thu Jul  8 11:03:08 2010
@@ -66,7 +66,6 @@
     else:
         fatal('invalid build mode: %r' % opts.build_mode)
 
-    make_variables['DISABLE_ASSERTIONS'] = '1'
     while build_mode:
         for (name,key) in (('+Asserts', 'ENABLE_ASSERTIONS'),
                            ('+Checks', 'ENABLE_EXPENSIVE_CHECKS'),
@@ -80,6 +79,12 @@
         else:
             fatal('invalid build mode: %r' % opts.build_mode)
 
+    # Assertions are disabled by default.
+    if 'ENABLE_ASSERTIONS' in make_variables:
+        del make_variables['ENABLE_ASSERTIONS']
+    else:
+        make_variables['DISABLE_ASSERTIONS'] = '1'
+
     # Set the optimization level options.
     make_variables['OPTFLAGS'] = opts.optimize_option
     if opts.optimize_option == '-Os':




From bob.wilson at apple.com  Thu Jul  8 11:03:57 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Thu, 08 Jul 2010 16:03:57 -0000
Subject: [llvm-commits] [test-suite] r107877 -
	/test-suite/trunk/Makefile.rules
Message-ID: <20100708160357.3F5A32A6C12C@llvm.org>

Author: bwilson
Date: Thu Jul  8 11:03:57 2010
New Revision: 107877

URL: http://llvm.org/viewvc/llvm-project?rev=107877&view=rev
Log:
Fix comment to match use of DISABLE_ASSERTIONS.

Modified:
    test-suite/trunk/Makefile.rules

Modified: test-suite/trunk/Makefile.rules
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/Makefile.rules?rev=107877&r1=107876&r2=107877&view=diff
==============================================================================
--- test-suite/trunk/Makefile.rules (original)
+++ test-suite/trunk/Makefile.rules Thu Jul  8 11:03:57 2010
@@ -152,8 +152,8 @@
   CONFIGURATION := $(CONFIGURATION)+Profile
 endif
 
-# If ENABLE_ASSERTIONS=1 is specified (make command line or configured),
-# then adjust the CONFIGURATION name appropriately (to match LLVM makefiles)
+# Unless DISABLE_ASSERTIONS=1 is specified (make command line or configured),
+# adjust the CONFIGURATION name appropriately (to match LLVM makefiles)
 ifneq ($(DISABLE_ASSERTIONS),1)
   CONFIGURATION := $(CONFIGURATION)+Asserts
 endif




From grosbach at apple.com  Thu Jul  8 11:10:53 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 8 Jul 2010 09:10:53 -0700
Subject: [llvm-commits] [llvm] r107847 - in /llvm/trunk:
	include/llvm/CodeGen/RegisterScavenging.h	lib/CodeGen/PrologEpilogInserter.cpp
	lib/CodeGen/RegisterScavenging.cpp
In-Reply-To: 
References: <20100708003854.AB2F12A6C12C@llvm.org>
	<70A40112-C2B9-4FA8-9765-4C158C40463F@2pi.dk>
	
	<3DB6043D-A396-487E-AFA2-41EADC74803B@apple.com>
	<3D73D5BA-7463-471C-A76C-328421CCB6C4@apple.com>
	
Message-ID: <2221F725-21B6-4085-82F8-4897D5AE4E77@apple.com>


On Jul 8, 2010, at 9:03 AM, Jakob Stoklund Olesen wrote:

> 
> On Jul 8, 2010, at 8:47 AM, Jim Grosbach wrote:
>>>> It's close, but not quite. scavengeRegister() will find the register of the indicated register class that's used furthest away. It considers all registers of the register class as candidates, however, not just the available ones. Essentially, it's almost assuming that a spill will be required, but does have an early exit if for some reason it's called and finds a register that is available. That could just as easily be an assert, really.
>>>> 
>>>> Previously, we looked for an available register, taking the first one we noticed if one or more exists; otherwise, we called scavengeRegister() to find a reasonable choice to spill and free up a register to use. Now, we apply the same heuristic for "reasonable to use" to selecting amongst the available registers, not just when spilling.
>>> 
>>> Does it make sense to move the code into RS?
>> 
>> I think so, yes. I've been pondering whether it makes more sense to add a new method or to modify scavengeRegister() such that it'll incorporate this use-case directly. I'm leaning towards the latter, since as Jakob correctly points out, they're so similar already.
> 
> It should be as simple as:
> 
> if ((Candidates & RegsAvailable).any())
>  Candidates &= RegsAvailable:
> 
> in the right place.
> 
> 

Well, almost. scavengeRegister() still needs to handle the fall-back of considering all registers, not just the available ones. In any case, I do think that's the way to go, so I'll take care of it in a few.
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From grosbach at apple.com  Thu Jul  8 11:35:40 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 8 Jul 2010 09:35:40 -0700
Subject: [llvm-commits] [llvm] r107847 - in /llvm/trunk:
	include/llvm/CodeGen/RegisterScavenging.h	lib/CodeGen/PrologEpilogInserter.cpp
	lib/CodeGen/RegisterScavenging.cpp
In-Reply-To: <2221F725-21B6-4085-82F8-4897D5AE4E77@apple.com>
References: <20100708003854.AB2F12A6C12C@llvm.org>
	<70A40112-C2B9-4FA8-9765-4C158C40463F@2pi.dk>
	
	<3DB6043D-A396-487E-AFA2-41EADC74803B@apple.com>
	<3D73D5BA-7463-471C-A76C-328421CCB6C4@apple.com>
	
	<2221F725-21B6-4085-82F8-4897D5AE4E77@apple.com>
Message-ID: 


On Jul 8, 2010, at 9:10 AM, Jim Grosbach wrote:

> 
> On Jul 8, 2010, at 9:03 AM, Jakob Stoklund Olesen wrote:
> 
>> 
>> On Jul 8, 2010, at 8:47 AM, Jim Grosbach wrote:
>>>>> It's close, but not quite. scavengeRegister() will find the register of the indicated register class that's used furthest away. It considers all registers of the register class as candidates, however, not just the available ones. Essentially, it's almost assuming that a spill will be required, but does have an early exit if for some reason it's called and finds a register that is available. That could just as easily be an assert, really.
>>>>> 
>>>>> Previously, we looked for an available register, taking the first one we noticed if one or more exists; otherwise, we called scavengeRegister() to find a reasonable choice to spill and free up a register to use. Now, we apply the same heuristic for "reasonable to use" to selecting amongst the available registers, not just when spilling.
>>>> 
>>>> Does it make sense to move the code into RS?
>>> 
>>> I think so, yes. I've been pondering whether it makes more sense to add a new method or to modify scavengeRegister() such that it'll incorporate this use-case directly. I'm leaning towards the latter, since as Jakob correctly points out, they're so similar already.
>> 
>> It should be as simple as:
>> 
>> if ((Candidates & RegsAvailable).any())
>>  Candidates &= RegsAvailable:
>> 
>> in the right place.
>> 
>> 
> 
> Well, almost. scavengeRegister() still needs to handle the fall-back of considering all registers, not just the available ones.

Woops. I read too quickly. Saw what I expected, not what you actually wrote. Yes, that's what's needed.
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From stoklund at 2pi.dk  Thu Jul  8 11:40:15 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Thu, 08 Jul 2010 16:40:15 -0000
Subject: [llvm-commits] [llvm] r107878 - in /llvm/trunk/lib:
 CodeGen/LiveIntervalAnalysis.cpp CodeGen/LowerSubregs.cpp
 CodeGen/ProcessImplicitDefs.cpp CodeGen/RegisterCoalescer.cpp
 CodeGen/SimpleRegisterCoalescing.cpp CodeGen/StackSlotColoring.cpp
 CodeGen/TwoAddressInstructionPass.cpp Target/X86/X86InstrInfo.cpp
Message-ID: <20100708164015.9F82F2A6C12C@llvm.org>

Author: stoklund
Date: Thu Jul  8 11:40:15 2010
New Revision: 107878

URL: http://llvm.org/viewvc/llvm-project?rev=107878&view=rev
Log:
Remove references to INSERT_SUBREG after de-SSA.

Fix X86InstrInfo::convertToThreeAddressWithLEA to generate COPY instead of
INSERT_SUBREG.

Modified:
    llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
    llvm/trunk/lib/CodeGen/LowerSubregs.cpp
    llvm/trunk/lib/CodeGen/ProcessImplicitDefs.cpp
    llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
    llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
    llvm/trunk/lib/CodeGen/StackSlotColoring.cpp
    llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp

Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=107878&r1=107877&r2=107878&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Thu Jul  8 11:40:15 2010
@@ -324,12 +324,6 @@
     if (mi->isCopyLike() ||
         tii_->isMoveInstr(*mi, SrcReg, DstReg, SrcSubReg, DstSubReg)) {
       CopyMI = mi;
-
-      // Some of the REG_SEQUENCE lowering in TwoAddressInstrPass creates
-      // implicit defs without really knowing. It shows up as INSERT_SUBREG
-      // using an undefined register.
-      if (mi->isInsertSubreg())
-        mi->getOperand(1).setIsUndef();
     }
 
     VNInfo *ValNo = interval.getNextValue(defIndex, CopyMI, true,

Modified: llvm/trunk/lib/CodeGen/LowerSubregs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LowerSubregs.cpp?rev=107878&r1=107877&r2=107878&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LowerSubregs.cpp (original)
+++ llvm/trunk/lib/CodeGen/LowerSubregs.cpp Thu Jul  8 11:40:15 2010
@@ -54,7 +54,6 @@
 
   private:
     bool LowerExtract(MachineInstr *MI);
-    bool LowerInsert(MachineInstr *MI);
     bool LowerSubregToReg(MachineInstr *MI);
     bool LowerCopy(MachineInstr *MI);
 
@@ -225,85 +224,6 @@
   return true;
 }
 
-bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
-  MachineBasicBlock *MBB = MI->getParent();
-  assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
-         (MI->getOperand(1).isReg() && MI->getOperand(1).isUse()) &&
-         (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
-          MI->getOperand(3).isImm() && "Invalid insert_subreg");
-          
-  unsigned DstReg = MI->getOperand(0).getReg();
-#ifndef NDEBUG
-  unsigned SrcReg = MI->getOperand(1).getReg();
-#endif
-  unsigned InsReg = MI->getOperand(2).getReg();
-  unsigned SubIdx = MI->getOperand(3).getImm();     
-
-  assert(DstReg == SrcReg && "insert_subreg not a two-address instruction?");
-  assert(SubIdx != 0 && "Invalid index for insert_subreg");
-  unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
-  assert(DstSubReg && "invalid subregister index for register");
-  assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
-         "Insert superreg source must be in a physical register");
-  assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
-         "Inserted value must be in a physical register");
-
-  DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
-
-  if (DstSubReg == InsReg) {
-    // No need to insert an identity copy instruction. If the SrcReg was
-    // , we need to make sure it is alive by inserting a KILL
-    if (MI->getOperand(1).isUndef() && !MI->getOperand(0).isDead()) {
-      MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(),
-                                TII->get(TargetOpcode::KILL), DstReg);
-      if (MI->getOperand(2).isUndef())
-        MIB.addReg(InsReg, RegState::Undef);
-      else
-        MIB.addReg(InsReg, RegState::Kill);
-    } else {
-      DEBUG(dbgs() << "subreg: eliminated!\n");
-      MBB->erase(MI);
-      return true;
-    }
-  } else {
-    // Insert sub-register copy
-    if (MI->getOperand(2).isUndef())
-      // If the source register being inserted is undef, then this becomes a
-      // KILL.
-      BuildMI(*MBB, MI, MI->getDebugLoc(),
-              TII->get(TargetOpcode::KILL), DstSubReg);
-    else {
-      TII->copyPhysReg(*MBB, MI, MI->getDebugLoc(), DstSubReg, InsReg, false);
-    }
-    MachineBasicBlock::iterator CopyMI = MI;
-    --CopyMI;
-
-    // INSERT_SUBREG is a two-address instruction so it implicitly kills SrcReg.
-    if (!MI->getOperand(1).isUndef())
-      CopyMI->addOperand(MachineOperand::CreateReg(DstReg, false, true, true));
-
-    // Transfer the kill/dead flags, if needed.
-    if (MI->getOperand(0).isDead()) {
-      TransferDeadFlag(MI, DstSubReg, TRI);
-    } else {
-      // Make sure the full DstReg is live after this replacement.
-      CopyMI->addOperand(MachineOperand::CreateReg(DstReg, true, true));
-    }
-
-    // Make sure the inserted register gets killed
-    if (MI->getOperand(2).isKill() && !MI->getOperand(2).isUndef())
-      TransferKillFlag(MI, InsReg, TRI);
-  }
-
-  DEBUG({
-      MachineBasicBlock::iterator dMI = MI;
-      dbgs() << "subreg: " << *(--dMI) << "\n";
-    });
-
-  MBB->erase(MI);
-  return true;
-}
-
 bool LowerSubregsInstructionPass::LowerCopy(MachineInstr *MI) {
   MachineOperand &DstMO = MI->getOperand(0);
   MachineOperand &SrcMO = MI->getOperand(1);
@@ -359,10 +279,9 @@
          mi != me;) {
       MachineBasicBlock::iterator nmi = llvm::next(mi);
       MachineInstr *MI = mi;
+      assert(!MI->isInsertSubreg() && "INSERT_SUBREG should no longer appear");
       if (MI->isExtractSubreg()) {
         MadeChange |= LowerExtract(MI);
-      } else if (MI->isInsertSubreg()) {
-        MadeChange |= LowerInsert(MI);
       } else if (MI->isSubregToReg()) {
         MadeChange |= LowerSubregToReg(MI);
       } else if (MI->isCopy()) {

Modified: llvm/trunk/lib/CodeGen/ProcessImplicitDefs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ProcessImplicitDefs.cpp?rev=107878&r1=107877&r2=107878&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ProcessImplicitDefs.cpp (original)
+++ llvm/trunk/lib/CodeGen/ProcessImplicitDefs.cpp Thu Jul  8 11:40:15 2010
@@ -102,21 +102,6 @@
         continue;
       }
 
-      if (MI->isInsertSubreg()) {
-        MachineOperand &MO = MI->getOperand(2);
-        if (ImpDefRegs.count(MO.getReg())) {
-          // %reg1032 = INSERT_SUBREG %reg1032, undef, 2
-          // This is an identity copy, eliminate it now.
-          if (MO.isKill()) {
-            LiveVariables::VarInfo& vi = lv_->getVarInfo(MO.getReg());
-            vi.removeKill(MI);
-          }
-          MI->eraseFromParent();
-          Changed = true;
-          continue;
-        }
-      }
-
       // Eliminate %reg1032:sub = COPY undef.
       if (MI->isCopy() && MI->getOperand(0).getSubReg()) {
         MachineOperand &MO = MI->getOperand(1);

Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp?rev=107878&r1=107877&r2=107878&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp Thu Jul  8 11:40:15 2010
@@ -54,7 +54,7 @@
     DstSub = MI->getOperand(0).getSubReg();
     Src = MI->getOperand(1).getReg();
     SrcSub = compose(MI->getOperand(1).getSubReg(), MI->getOperand(2).getImm());
-  } else if (MI->isInsertSubreg() || MI->isSubregToReg()) {
+  } else if (MI->isSubregToReg()) {
     Dst = MI->getOperand(0).getReg();
     DstSub = compose(MI->getOperand(0).getSubReg(), MI->getOperand(3).getImm());
     Src = MI->getOperand(2).getReg();

Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=107878&r1=107877&r2=107878&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
+++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Thu Jul  8 11:40:15 2010
@@ -1528,12 +1528,7 @@
     if (Inst->isCopy() || Inst->isExtractSubreg()) {
       DstReg = Inst->getOperand(0).getReg();
       SrcReg = Inst->getOperand(1).getReg();
-    } else if (Inst->isInsertSubreg()) {
-      DstReg = Inst->getOperand(0).getReg();
-      SrcReg = Inst->getOperand(2).getReg();
-      if (Inst->getOperand(1).isUndef())
-        isInsUndef = true;
-    } else if (Inst->isInsertSubreg() || Inst->isSubregToReg()) {
+    } else if (Inst->isSubregToReg()) {
       DstReg = Inst->getOperand(0).getReg();
       SrcReg = Inst->getOperand(2).getReg();
     } else if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg, SrcSubIdx, DstSubIdx))

Modified: llvm/trunk/lib/CodeGen/StackSlotColoring.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/StackSlotColoring.cpp?rev=107878&r1=107877&r2=107878&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/StackSlotColoring.cpp (original)
+++ llvm/trunk/lib/CodeGen/StackSlotColoring.cpp Thu Jul  8 11:40:15 2010
@@ -508,8 +508,7 @@
 
         // Abort the use is actually a sub-register def. We don't have enough
         // information to figure out if it is really legal.
-        if (MO.getSubReg() || MII->isExtractSubreg() ||
-            MII->isInsertSubreg() || MII->isSubregToReg())
+        if (MO.getSubReg() || MII->isExtractSubreg() || MII->isSubregToReg())
           return false;
 
         const TargetRegisterClass *RC = TID.OpInfo[i].getRegClass(TRI);

Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=107878&r1=107877&r2=107878&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original)
+++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Thu Jul  8 11:40:15 2010
@@ -1359,25 +1359,11 @@
 
     // Insert a copy or an extract to replace the original extracts.
     MachineBasicBlock::iterator InsertLoc = SomeMI;
-    if (NewSrcSubIdx) {
-      // Insert an extract subreg.
-      BuildMI(*SomeMI->getParent(), InsertLoc, SomeMI->getDebugLoc(),
-              TII->get(TargetOpcode::EXTRACT_SUBREG), DstReg)
-        .addReg(SrcReg).addImm(NewSrcSubIdx);
-    } else if (NewDstSubIdx) {
-      // Do a subreg insertion.
-      BuildMI(*SomeMI->getParent(), InsertLoc, SomeMI->getDebugLoc(),
-              TII->get(TargetOpcode::INSERT_SUBREG), DstReg)
-        .addReg(DstReg).addReg(SrcReg).addImm(NewDstSubIdx);
-    } else {
-      // Insert a copy.
-      bool Emitted =
-        TII->copyRegToReg(*SomeMI->getParent(), InsertLoc, DstReg, SrcReg,
-                          MRI->getRegClass(DstReg), MRI->getRegClass(SrcReg),
-                          SomeMI->getDebugLoc());
-      (void)Emitted;
-    }
-    MachineBasicBlock::iterator CopyMI = prior(InsertLoc);
+    MachineInstr *CopyMI = BuildMI(*SomeMI->getParent(), SomeMI,
+                                   SomeMI->getDebugLoc(),
+                                   TII->get(TargetOpcode::COPY))
+      .addReg(DstReg, RegState::Define, NewDstSubIdx)
+      .addReg(SrcReg, 0, NewSrcSubIdx);
 
     // Remove all the old extract instructions.
     for (MachineRegisterInfo::use_nodbg_iterator

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=107878&r1=107877&r2=107878&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Thu Jul  8 11:40:15 2010
@@ -1145,10 +1145,9 @@
   // least on modern x86 machines).
   BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
   MachineInstr *InsMI =
-    BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::INSERT_SUBREG),leaInReg)
-    .addReg(leaInReg)
-    .addReg(Src, getKillRegState(isKill))
-    .addImm(X86::sub_16bit);
+    BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
+    .addReg(leaInReg, RegState::Define, X86::sub_16bit)
+    .addReg(Src, getKillRegState(isKill));
 
   MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
                                     get(Opc), leaOutReg);
@@ -1189,10 +1188,9 @@
       // well be shifting and then extracting the lower 16-bits. 
       BuildMI(*MFI, MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2);
       InsMI2 =
-        BuildMI(*MFI, MIB, MI->getDebugLoc(), get(X86::INSERT_SUBREG),leaInReg2)
-        .addReg(leaInReg2)
-        .addReg(Src2, getKillRegState(isKill2))
-        .addImm(X86::sub_16bit);
+        BuildMI(*MFI, MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
+        .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
+        .addReg(Src2, getKillRegState(isKill2));
       addRegReg(MIB, leaInReg, true, leaInReg2, true);
     }
     if (LV && isKill2 && InsMI2)




From stoklund at 2pi.dk  Thu Jul  8 11:40:23 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Thu, 08 Jul 2010 16:40:23 -0000
Subject: [llvm-commits] [llvm] r107879 - in /llvm/trunk:
 include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/
 lib/CodeGen/SelectionDAG/ lib/Target/ARM/ lib/Target/X86/
Message-ID: <20100708164023.4CA252A6C12D@llvm.org>

Author: stoklund
Date: Thu Jul  8 11:40:22 2010
New Revision: 107879

URL: http://llvm.org/viewvc/llvm-project?rev=107879&view=rev
Log:
Convert EXTRACT_SUBREG to COPY when emitting machine instrs.

EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead.

Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg().
The isMoveInstr hook will be removed later.

Modified:
    llvm/trunk/include/llvm/CodeGen/MachineInstr.h
    llvm/trunk/include/llvm/Target/TargetInstrInfo.h
    llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
    llvm/trunk/lib/CodeGen/LowerSubregs.cpp
    llvm/trunk/lib/CodeGen/MachineCSE.cpp
    llvm/trunk/lib/CodeGen/OptimizeExts.cpp
    llvm/trunk/lib/CodeGen/ProcessImplicitDefs.cpp
    llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp
    llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
    llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
    llvm/trunk/lib/CodeGen/StackSlotColoring.cpp
    llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
    llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp
    llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp
    llvm/trunk/lib/Target/X86/X86FastISel.cpp
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp

Modified: llvm/trunk/include/llvm/CodeGen/MachineInstr.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstr.h?rev=107879&r1=107878&r2=107879&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineInstr.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineInstr.h Thu Jul  8 11:40:22 2010
@@ -215,9 +215,6 @@
   bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
   bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
   bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
-  bool isExtractSubreg() const {
-    return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
-  }
   bool isInsertSubreg() const {
     return getOpcode() == TargetOpcode::INSERT_SUBREG;
   }
@@ -234,7 +231,13 @@
   /// isCopyLike - Return true if the instruction behaves like a copy.
   /// This does not include native copy instructions.
   bool isCopyLike() const {
-    return isCopy() || isSubregToReg() || isExtractSubreg() || isInsertSubreg();
+    return isCopy() || isSubregToReg();
+  }
+
+  /// isIdentityCopy - Return true is the instruction is an identity copy.
+  bool isIdentityCopy() const {
+    return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
+      getOperand(0).getSubReg() == getOperand(1).getSubReg();
   }
 
   /// readsRegister - Return true if the MachineInstr reads the specified

Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=107879&r1=107878&r2=107879&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Thu Jul  8 11:40:22 2010
@@ -122,10 +122,6 @@
         SrcReg == DstReg)
       return true;
 
-    if (MI.getOpcode() == TargetOpcode::EXTRACT_SUBREG &&
-        MI.getOperand(0).getReg() == MI.getOperand(1).getReg())
-    return true;
-
     if ((MI.getOpcode() == TargetOpcode::INSERT_SUBREG ||
          MI.getOpcode() == TargetOpcode::SUBREG_TO_REG) &&
         MI.getOperand(0).getReg() == MI.getOperand(2).getReg())

Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=107879&r1=107878&r2=107879&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Thu Jul  8 11:40:22 2010
@@ -192,6 +192,9 @@
     if (tii_->isMoveInstr(MI, SrcReg, DstReg, SrcSubReg, DstSubReg))
       if (SrcReg == li.reg || DstReg == li.reg)
         continue;
+    if (MI.isCopy() && MI.getOperand(0).getReg() == li.reg &&
+        MI.getOperand(1).getReg() == li.reg)
+      continue;
 
     // Check for operands using reg
     for (unsigned i = 0, e = MI.getNumOperands(); i != e;  ++i) {

Modified: llvm/trunk/lib/CodeGen/LowerSubregs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LowerSubregs.cpp?rev=107879&r1=107878&r2=107879&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LowerSubregs.cpp (original)
+++ llvm/trunk/lib/CodeGen/LowerSubregs.cpp Thu Jul  8 11:40:22 2010
@@ -53,7 +53,6 @@
     bool runOnMachineFunction(MachineFunction&);
 
   private:
-    bool LowerExtract(MachineInstr *MI);
     bool LowerSubregToReg(MachineInstr *MI);
     bool LowerCopy(MachineInstr *MI);
 
@@ -121,57 +120,6 @@
   }
 }
 
-bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
-  MachineBasicBlock *MBB = MI->getParent();
-
-  assert(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
-         MI->getOperand(1).isReg() && MI->getOperand(1).isUse() &&
-         MI->getOperand(2).isImm() && "Malformed extract_subreg");
-
-  unsigned DstReg   = MI->getOperand(0).getReg();
-  unsigned SuperReg = MI->getOperand(1).getReg();
-  unsigned SubIdx   = MI->getOperand(2).getImm();
-  unsigned SrcReg   = TRI->getSubReg(SuperReg, SubIdx);
-
-  assert(TargetRegisterInfo::isPhysicalRegister(SuperReg) &&
-         "Extract supperg source must be a physical register");
-  assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
-         "Extract destination must be in a physical register");
-  assert(SrcReg && "invalid subregister index for register");
-
-  DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
-
-  if (SrcReg == DstReg) {
-    // No need to insert an identity copy instruction.
-    if (MI->getOperand(1).isKill()) {
-      // We must make sure the super-register gets killed. Replace the
-      // instruction with KILL.
-      MI->setDesc(TII->get(TargetOpcode::KILL));
-      MI->RemoveOperand(2);     // SubIdx
-      DEBUG(dbgs() << "subreg: replace by: " << *MI);
-      return true;
-    }
-
-    DEBUG(dbgs() << "subreg: eliminated!");
-  } else {
-    TII->copyPhysReg(*MBB, MI, MI->getDebugLoc(), DstReg, SrcReg, false);
-    // Transfer the kill/dead flags, if needed.
-    if (MI->getOperand(0).isDead())
-      TransferDeadFlag(MI, DstReg, TRI);
-    if (MI->getOperand(1).isKill())
-      TransferKillFlag(MI, SuperReg, TRI, true);
-    TransferImplicitDefs(MI);
-    DEBUG({
-        MachineBasicBlock::iterator dMI = MI;
-        dbgs() << "subreg: " << *(--dMI);
-      });
-  }
-
-  DEBUG(dbgs() << '\n');
-  MBB->erase(MI);
-  return true;
-}
-
 bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
   MachineBasicBlock *MBB = MI->getParent();
   assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
@@ -280,9 +228,9 @@
       MachineBasicBlock::iterator nmi = llvm::next(mi);
       MachineInstr *MI = mi;
       assert(!MI->isInsertSubreg() && "INSERT_SUBREG should no longer appear");
-      if (MI->isExtractSubreg()) {
-        MadeChange |= LowerExtract(MI);
-      } else if (MI->isSubregToReg()) {
+      assert(MI->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
+             "EXTRACT_SUBREG should no longer appear");
+      if (MI->isSubregToReg()) {
         MadeChange |= LowerSubregToReg(MI);
       } else if (MI->isCopy()) {
         MadeChange |= LowerCopy(MI);

Modified: llvm/trunk/lib/CodeGen/MachineCSE.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineCSE.cpp?rev=107879&r1=107878&r2=107879&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineCSE.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineCSE.cpp Thu Jul  8 11:40:22 2010
@@ -126,6 +126,28 @@
       ++NumCoalesces;
       Changed = true;
     }
+
+    if (!DefMI->isCopy())
+      continue;
+    SrcReg = DefMI->getOperand(1).getReg();
+    if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
+      continue;
+    if (DefMI->getOperand(0).getSubReg() || DefMI->getOperand(1).getSubReg())
+      continue;
+    const TargetRegisterClass *SRC   = MRI->getRegClass(SrcReg);
+    const TargetRegisterClass *RC    = MRI->getRegClass(Reg);
+    const TargetRegisterClass *NewRC = getCommonSubClass(RC, SRC);
+    if (!NewRC)
+      continue;
+    DEBUG(dbgs() << "Coalescing: " << *DefMI);
+    DEBUG(dbgs() << "*** to: " << *MI);
+    MO.setReg(SrcReg);
+    MRI->clearKillFlags(SrcReg);
+    if (NewRC != SRC)
+      MRI->setRegClass(SrcReg, NewRC);
+    DefMI->eraseFromParent();
+    ++NumCoalesces;
+    Changed = true;
   }
 
   return Changed;

Modified: llvm/trunk/lib/CodeGen/OptimizeExts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/OptimizeExts.cpp?rev=107879&r1=107878&r2=107879&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/OptimizeExts.cpp (original)
+++ llvm/trunk/lib/CodeGen/OptimizeExts.cpp Thu Jul  8 11:40:22 2010
@@ -128,12 +128,12 @@
       //
       //    %reg1025 =  %reg1024
       //     ...
-      //    %reg1027 = EXTRACT_SUBREG %reg1025, 4
+      //    %reg1027 = COPY %reg1025:4
       //    %reg1026 = SUBREG_TO_REG 0, %reg1027, 4
       //
       // The problem here is that SUBREG_TO_REG is there to assert that an
       // implicit zext occurs. It doesn't insert a zext instruction. If we allow
-      // the EXTRACT_SUBREG here, it will give us the value after the ,
+      // the COPY here, it will give us the value after the ,
       // not the original value of %reg1024 before .
       if (UseMI->getOpcode() == TargetOpcode::SUBREG_TO_REG)
         continue;
@@ -185,8 +185,8 @@
           continue;
         unsigned NewVR = MRI->createVirtualRegister(RC);
         BuildMI(*UseMBB, UseMI, UseMI->getDebugLoc(),
-                TII->get(TargetOpcode::EXTRACT_SUBREG), NewVR)
-          .addReg(DstReg).addImm(SubIdx);
+                TII->get(TargetOpcode::COPY), NewVR)
+          .addReg(DstReg, 0, SubIdx);
         UseMO->setReg(NewVR);
         ++NumReuse;
         Changed = true;

Modified: llvm/trunk/lib/CodeGen/ProcessImplicitDefs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ProcessImplicitDefs.cpp?rev=107879&r1=107878&r2=107879&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ProcessImplicitDefs.cpp (original)
+++ llvm/trunk/lib/CodeGen/ProcessImplicitDefs.cpp Thu Jul  8 11:40:22 2010
@@ -50,8 +50,7 @@
     return true;
 
   switch(OpIdx) {
-    case 1: return (MI->isExtractSubreg() || MI->isCopy()) &&
-                   MI->getOperand(0).getSubReg() == 0;
+    case 1: return MI->isCopy() && MI->getOperand(0).getSubReg() == 0;
     case 2: return MI->isSubregToReg() && MI->getOperand(0).getSubReg() == 0;
     default: return false;
   }

Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp?rev=107879&r1=107878&r2=107879&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Thu Jul  8 11:40:22 2010
@@ -422,9 +422,10 @@
     unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
     if (vni->def != SlotIndex() && vni->isDefAccurate() &&
         (CopyMI = li_->getInstructionFromIndex(vni->def)) &&
-        tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg))
+        (CopyMI->isCopy() ||
+         tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg)))
       // Defined by a copy, try to extend SrcReg forward
-      CandReg = SrcReg;
+      CandReg = CopyMI->isCopy() ? CopyMI->getOperand(1).getReg() : SrcReg;
     else if (TrivCoalesceEnds &&
              (CopyMI =
               li_->getInstructionFromIndex(range.end.getBaseIndex())) &&
@@ -993,6 +994,24 @@
           if (Reg && allocatableRegs_[Reg] && RC->contains(Reg))
             mri_->setRegAllocationHint(cur->reg, 0, Reg);
         }
+      } else if (CopyMI && CopyMI->isCopy()) {
+        DstReg = CopyMI->getOperand(0).getReg();
+        DstSubReg = CopyMI->getOperand(0).getSubReg();
+        SrcReg = CopyMI->getOperand(1).getReg();
+        SrcSubReg = CopyMI->getOperand(1).getSubReg();
+        unsigned Reg = 0;
+        if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
+          Reg = SrcReg;
+        else if (vrm_->isAssignedReg(SrcReg))
+          Reg = vrm_->getPhys(SrcReg);
+        if (Reg) {
+          if (SrcSubReg)
+            Reg = tri_->getSubReg(Reg, SrcSubReg);
+          if (DstSubReg)
+            Reg = tri_->getMatchingSuperReg(Reg, DstSubReg, RC);
+          if (Reg && allocatableRegs_[Reg] && RC->contains(Reg))
+            mri_->setRegAllocationHint(cur->reg, 0, Reg);
+        }
       }
     }
   }

Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp?rev=107879&r1=107878&r2=107879&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp Thu Jul  8 11:40:22 2010
@@ -49,11 +49,6 @@
     DstSub = MI->getOperand(0).getSubReg();
     Src = MI->getOperand(1).getReg();
     SrcSub = MI->getOperand(1).getSubReg();
-  } else if (MI->isExtractSubreg()) {
-    Dst = MI->getOperand(0).getReg();
-    DstSub = MI->getOperand(0).getSubReg();
-    Src = MI->getOperand(1).getReg();
-    SrcSub = compose(MI->getOperand(1).getSubReg(), MI->getOperand(2).getImm());
   } else if (MI->isSubregToReg()) {
     Dst = MI->getOperand(0).getReg();
     DstSub = compose(MI->getOperand(0).getSubReg(), MI->getOperand(3).getImm());

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=107879&r1=107878&r2=107879&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Thu Jul  8 11:40:22 2010
@@ -1132,24 +1132,11 @@
 unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT,
                                               unsigned Op0, bool Op0IsKill,
                                               uint32_t Idx) {
-  const TargetRegisterClass* RC = MRI.getRegClass(Op0);
-  
   unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
-  const TargetInstrDesc &II = TII.get(TargetOpcode::EXTRACT_SUBREG);
-  
-  if (II.getNumDefs() >= 1)
-    BuildMI(MBB, DL, II, ResultReg)
-      .addReg(Op0, Op0IsKill * RegState::Kill)
-      .addImm(Idx);
-  else {
-    BuildMI(MBB, DL, II)
-      .addReg(Op0, Op0IsKill * RegState::Kill)
-      .addImm(Idx);
-    bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
-                                         II.ImplicitDefs[0], RC, RC, DL);
-    if (!InsertedCopy)
-      ResultReg = 0;
-  }
+  assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
+         "Cannot yet extract from physregs");
+  BuildMI(MBB, DL, TII.get(TargetOpcode::COPY), ResultReg)
+    .addReg(Op0, getKillRegState(Op0IsKill), Idx);
   return ResultReg;
 }
 

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp?rev=107879&r1=107878&r2=107879&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp Thu Jul  8 11:40:22 2010
@@ -428,12 +428,9 @@
   }
   
   if (Opc == TargetOpcode::EXTRACT_SUBREG) {
+    // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub
     unsigned SubIdx = cast(Node->getOperand(1))->getZExtValue();
 
-    // Create the extract_subreg machine instruction.
-    MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(),
-                               TII->get(TargetOpcode::EXTRACT_SUBREG));
-
     // Figure out the register class to create for the destreg.
     unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
     const TargetRegisterClass *TRC = MRI->getRegClass(VReg);
@@ -450,11 +447,16 @@
       VRBase = MRI->createVirtualRegister(SRC);
     }
 
-    // Add def, source, and subreg index
-    MI->addOperand(MachineOperand::CreateReg(VRBase, true));
+    // Create the extract_subreg machine instruction.
+    MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(),
+                               TII->get(TargetOpcode::COPY), VRBase);
+
+    // Add source, and subreg index
     AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap, /*IsDebug=*/false,
                IsClone, IsCloned);
-    MI->addOperand(MachineOperand::CreateImm(SubIdx));
+    assert(TargetRegisterInfo::isVirtualRegister(MI->getOperand(1).getReg()) &&
+           "Cannot yet extract from physregs");
+    MI->getOperand(1).setSubReg(SubIdx);
     MBB->insert(InsertPos, MI);
   } else if (Opc == TargetOpcode::INSERT_SUBREG ||
              Opc == TargetOpcode::SUBREG_TO_REG) {

Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=107879&r1=107878&r2=107879&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
+++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Thu Jul  8 11:40:22 2010
@@ -1525,7 +1525,7 @@
     // If this isn't a copy nor a extract_subreg, we can't join intervals.
     unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
     bool isInsUndef = false;
-    if (Inst->isCopy() || Inst->isExtractSubreg()) {
+    if (Inst->isCopy()) {
       DstReg = Inst->getOperand(0).getReg();
       SrcReg = Inst->getOperand(1).getReg();
     } else if (Inst->isSubregToReg()) {
@@ -1657,6 +1657,8 @@
            E = mri_->use_nodbg_end(); I != E; ++I) {
       MachineOperand &Use = I.getOperand();
       MachineInstr *UseMI = Use.getParent();
+      if (UseMI->isIdentityCopy())
+        continue;
       unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
       if (tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
           SrcReg == DstReg && SrcSubIdx == DstSubIdx)
@@ -1687,7 +1689,8 @@
 
     // Ignore identity copies.
     unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
-    if (!(tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
+    if (!MI->isIdentityCopy() &&
+        !(tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
           SrcReg == DstReg && SrcSubIdx == DstSubIdx))
       for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
         MachineOperand &Use = MI->getOperand(i);
@@ -1818,7 +1821,8 @@
 
       // If the move will be an identity move delete it
       bool isMove= tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx);
-      if (isMove && SrcReg == DstReg && SrcSubIdx == DstSubIdx) {
+      if (MI->isIdentityCopy() ||
+          (isMove && SrcReg == DstReg && SrcSubIdx == DstSubIdx)) {
         if (li_->hasInterval(SrcReg)) {
           LiveInterval &RegInt = li_->getInterval(SrcReg);
           // If def of this move instruction is dead, remove its live range

Modified: llvm/trunk/lib/CodeGen/StackSlotColoring.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/StackSlotColoring.cpp?rev=107879&r1=107878&r2=107879&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/StackSlotColoring.cpp (original)
+++ llvm/trunk/lib/CodeGen/StackSlotColoring.cpp Thu Jul  8 11:40:22 2010
@@ -508,7 +508,7 @@
 
         // Abort the use is actually a sub-register def. We don't have enough
         // information to figure out if it is really legal.
-        if (MO.getSubReg() || MII->isExtractSubreg() || MII->isSubregToReg())
+        if (MO.getSubReg() || MII->isSubregToReg())
           return false;
 
         const TargetRegisterClass *RC = TID.OpInfo[i].getRegClass(TRI);
@@ -570,7 +570,7 @@
 
         // Abort the use is actually a sub-register use. We don't have enough
         // information to figure out if it is really legal.
-        if (MO.getSubReg() || MII->isExtractSubreg())
+        if (MO.getSubReg())
           return false;
 
         const TargetRegisterClass *RC = TID.OpInfo[i].getRegClass(TRI);

Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=107879&r1=107878&r2=107879&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original)
+++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Thu Jul  8 11:40:22 2010
@@ -382,7 +382,7 @@
   DstReg = 0;
   unsigned SrcSubIdx, DstSubIdx;
   if (!TII->isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
-    if (MI.isCopy() || MI.isExtractSubreg()) {
+    if (MI.isCopy()) {
       DstReg = MI.getOperand(0).getReg();
       SrcReg = MI.getOperand(1).getReg();
     } else if (MI.isInsertSubreg()) {
@@ -1291,7 +1291,7 @@
     if (SrcDefMI->getParent() != DstDefMI->getParent())
       continue;
 
-    // If there are no other uses than extract_subreg which feed into
+    // If there are no other uses than copies which feed into
     // the reg_sequence, then we might be able to coalesce them.
     bool CanCoalesce = true;
     SmallVector SrcSubIndices, DstSubIndices;
@@ -1299,13 +1299,11 @@
            UI = MRI->use_nodbg_begin(SrcReg),
            UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
       MachineInstr *UseMI = &*UI;
-      if (!UseMI->isExtractSubreg() ||
-          UseMI->getOperand(0).getReg() != DstReg ||
-          UseMI->getOperand(1).getSubReg() != 0) {
+      if (!UseMI->isCopy() || UseMI->getOperand(0).getReg() != DstReg) {
         CanCoalesce = false;
         break;
       }
-      SrcSubIndices.push_back(UseMI->getOperand(2).getImm());
+      SrcSubIndices.push_back(UseMI->getOperand(1).getSubReg());
       DstSubIndices.push_back(UseMI->getOperand(0).getSubReg());
     }
 
@@ -1340,9 +1338,9 @@
            UI = MRI->use_nodbg_begin(SrcReg),
            UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
       MachineInstr *UseMI = &*UI;
-      assert(UseMI->isExtractSubreg());
+      assert(UseMI->isCopy());
       unsigned DstSubIdx = UseMI->getOperand(0).getSubReg();
-      unsigned SrcSubIdx = UseMI->getOperand(2).getImm();
+      unsigned SrcSubIdx = UseMI->getOperand(1).getSubReg();
       assert(DstSubIdx != 0 && "missing subreg from RegSequence elimination");
       if ((NewDstSubIdx == 0 &&
            TRI->composeSubRegIndices(NewSrcSubIdx, DstSubIdx) != SrcSubIdx) ||
@@ -1357,7 +1355,7 @@
     if (!CanCoalesce)
       continue;
 
-    // Insert a copy or an extract to replace the original extracts.
+    // Insert a copy to replace the original.
     MachineBasicBlock::iterator InsertLoc = SomeMI;
     MachineInstr *CopyMI = BuildMI(*SomeMI->getParent(), SomeMI,
                                    SomeMI->getDebugLoc(),
@@ -1373,11 +1371,10 @@
       ++UI;
       if (UseMI == CopyMI)
         continue;
-      assert(UseMI->isExtractSubreg());
+      assert(UseMI->isCopy());
       // Move any kills to the new copy or extract instruction.
       if (UseMI->getOperand(1).isKill()) {
-        MachineOperand *KillMO = CopyMI->findRegisterUseOperand(SrcReg);
-        KillMO->setIsKill();
+        CopyMI->getOperand(1).setIsKill();
         if (LV)
           // Update live variables
           LV->replaceKillInstruction(SrcReg, UseMI, &*CopyMI);
@@ -1438,9 +1435,8 @@
       }
       IsImpDef = false;
 
-      // Remember EXTRACT_SUBREG sources. These might be candidate for
-      // coalescing.
-      if (DefMI->isExtractSubreg())
+      // Remember COPY sources. These might be candidate for coalescing.
+      if (DefMI->isCopy())
         RealSrcs.push_back(DefMI->getOperand(1).getReg());
 
       if (!Seen.insert(SrcReg) ||

Modified: llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp?rev=107879&r1=107878&r2=107879&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp (original)
+++ llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp Thu Jul  8 11:40:22 2010
@@ -2012,7 +2012,7 @@
       //       = EXTRACT_SUBREG fi#1
       // fi#1 is available in EDI, but it cannot be reused because it's not in
       // the right register file.
-      if (PhysReg && !AvoidReload && (SubIdx || MI.isExtractSubreg())) {
+      if (PhysReg && !AvoidReload && SubIdx) {
         const TargetRegisterClass* RC = MRI->getRegClass(VirtReg);
         if (!RC->contains(PhysReg))
           PhysReg = 0;

Modified: llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp?rev=107879&r1=107878&r2=107879&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp (original)
+++ llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp Thu Jul  8 11:40:22 2010
@@ -407,7 +407,7 @@
            "expected a virtual register");
     // Extracting from a Q or QQ register.
     MachineInstr *DefMI = MRI->getVRegDef(VirtReg);
-    if (!DefMI || !DefMI->isExtractSubreg())
+    if (!DefMI || !DefMI->isCopy() || !DefMI->getOperand(1).getSubReg())
       return false;
     VirtReg = DefMI->getOperand(1).getReg();
     if (LastSrcReg && LastSrcReg != VirtReg)
@@ -418,7 +418,7 @@
         RC != ARM::QQPRRegisterClass &&
         RC != ARM::QQQQPRRegisterClass)
       return false;
-    unsigned SubIdx = DefMI->getOperand(2).getImm();
+    unsigned SubIdx = DefMI->getOperand(1).getSubReg();
     if (LastSubIdx) {
       if (LastSubIdx != SubIdx-Stride)
         return false;
@@ -445,7 +445,7 @@
     MachineOperand &MO = MI->getOperand(FirstOpnd + R);
     unsigned OldReg = MO.getReg();
     MachineInstr *DefMI = MRI->getVRegDef(OldReg);
-    assert(DefMI->isExtractSubreg());
+    assert(DefMI->isCopy());
     MO.setReg(LastSrcReg);
     MO.setSubReg(SubIds[R]);
     MO.setIsKill(false);

Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=107879&r1=107878&r2=107879&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Thu Jul  8 11:40:22 2010
@@ -1039,11 +1039,10 @@
   TII.copyRegToReg(*MBB, MBB->end(), CReg, Op1Reg, RC, RC, DL);
 
   // The shift instruction uses X86::CL. If we defined a super-register
-  // of X86::CL, emit an EXTRACT_SUBREG to precisely describe what
-  // we're doing here.
+  // of X86::CL, emit a subreg KILL to precisely describe what we're doing here.
   if (CReg != X86::CL)
-    BuildMI(MBB, DL, TII.get(TargetOpcode::EXTRACT_SUBREG), X86::CL)
-      .addReg(CReg).addImm(X86::sub_8bit);
+    BuildMI(MBB, DL, TII.get(TargetOpcode::KILL), X86::CL)
+      .addReg(CReg, RegState::Kill);
 
   unsigned ResultReg = createResultReg(RC);
   BuildMI(MBB, DL, TII.get(OpReg), ResultReg).addReg(Op0Reg);

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=107879&r1=107878&r2=107879&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Thu Jul  8 11:40:22 2010
@@ -1201,10 +1201,9 @@
 
   MachineInstr *NewMI = MIB;
   MachineInstr *ExtMI =
-    BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::EXTRACT_SUBREG))
+    BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
     .addReg(Dest, RegState::Define | getDeadRegState(isDead))
-    .addReg(leaOutReg, RegState::Kill)
-    .addImm(X86::sub_16bit);
+    .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
 
   if (LV) {
     // Update live variables




From grosbach at apple.com  Thu Jul  8 11:49:27 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 08 Jul 2010 16:49:27 -0000
Subject: [llvm-commits] [llvm] r107880 - in /llvm/trunk/lib/CodeGen:
 PrologEpilogInserter.cpp RegisterScavenging.cpp
Message-ID: <20100708164927.23F512A6C12C@llvm.org>

Author: grosbach
Date: Thu Jul  8 11:49:26 2010
New Revision: 107880

URL: http://llvm.org/viewvc/llvm-project?rev=107880&view=rev
Log:
Clean up scavengeRegister() a bit to prefer available regs, which allows
the simplification of frame index register scavenging to not have to check
for available registers directly and instead just let scavengeRegister()
handle it.

Modified:
    llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp
    llvm/trunk/lib/CodeGen/RegisterScavenging.cpp

Modified: llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp?rev=107880&r1=107879&r2=107880&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp (original)
+++ llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp Thu Jul  8 11:49:26 2010
@@ -885,21 +885,7 @@
             // Scavenge a new scratch register
             CurrentVirtReg = Reg;
             const TargetRegisterClass *RC = Fn.getRegInfo().getRegClass(Reg);
-            const TargetRegisterInfo *TRI = Fn.getTarget().getRegisterInfo();
-            BitVector Candidates(TRI->getNumRegs());
-            RS->getRegsAvailable(RC, Candidates);
-
-            // If there are any registers available, use the one that's
-            // unused for the longest after this instruction. That increases
-            // the ability to reuse the value.
-            if (Candidates.any()) {
-              MachineBasicBlock::iterator UMI;
-              CurrentScratchReg = RS->findSurvivorReg(I, Candidates, 25, UMI);
-            } else {
-              // No register is "free". Scavenge a register.
-              CurrentScratchReg = RS->scavengeRegister(RC, I, SPAdj);
-            }
-
+            CurrentScratchReg = RS->scavengeRegister(RC, I, SPAdj);
             PrevValue = Value;
           }
           // replace this reference to the virtual register with the

Modified: llvm/trunk/lib/CodeGen/RegisterScavenging.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterScavenging.cpp?rev=107880&r1=107879&r2=107880&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterScavenging.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterScavenging.cpp Thu Jul  8 11:49:26 2010
@@ -339,13 +339,16 @@
       Candidates.reset(MO.getReg());
   }
 
+  // Try to find a register that's unused if there is one, as then we won't
+  // have to spill.
+  if ((Candidates & RegsAvailable).any())
+     Candidates &= RegsAvailable;
+
   // Find the register whose use is furthest away.
   MachineBasicBlock::iterator UseMI;
   unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI);
 
-  // If we found an unused register there is no reason to spill it. We have
-  // probably found a callee-saved register that has been saved in the
-  // prologue, but happens to be unused at this point.
+  // If we found an unused register there is no reason to spill it.
   if (!isAliasUsed(SReg))
     return SReg;
 




From ggreif at gmail.com  Thu Jul  8 11:52:57 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Thu, 08 Jul 2010 16:52:57 -0000
Subject: [llvm-commits] [llvm] r107881 -
	/llvm/trunk/include/llvm/Support/CFG.h
Message-ID: <20100708165257.A8A1E2A6C12C@llvm.org>

Author: ggreif
Date: Thu Jul  8 11:52:57 2010
New Revision: 107881

URL: http://llvm.org/viewvc/llvm-project?rev=107881&view=rev
Log:
remove unneeded parens

Modified:
    llvm/trunk/include/llvm/Support/CFG.h

Modified: llvm/trunk/include/llvm/Support/CFG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/CFG.h?rev=107881&r1=107880&r2=107881&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/CFG.h (original)
+++ llvm/trunk/include/llvm/Support/CFG.h Thu Jul  8 11:52:57 2010
@@ -53,7 +53,7 @@
     assert(!It.atEnd() && "pred_iterator out of range!");
     return cast(*It)->getParent();
   }
-  inline pointer *operator->() const { return &(operator*()); }
+  inline pointer *operator->() const { return &operator*(); }
 
   inline Self& operator++() {   // Preincrement
     assert(!It.atEnd() && "pred_iterator out of range!");




From bob.wilson at apple.com  Thu Jul  8 11:54:46 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Thu, 08 Jul 2010 16:54:46 -0000
Subject: [llvm-commits] [llvm] r107882 -
	/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td
Message-ID: <20100708165446.2A6392A6C12C@llvm.org>

Author: bwilson
Date: Thu Jul  8 11:54:45 2010
New Revision: 107882

URL: http://llvm.org/viewvc/llvm-project?rev=107882&view=rev
Log:
Clean up a comment.

Modified:
    llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td?rev=107882&r1=107881&r2=107882&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td Thu Jul  8 11:54:45 2010
@@ -153,11 +153,11 @@
 
 // Pseudo 256-bit registers to represent pairs of Q registers. These should
 // never be present in the emitted code.
-// These are used for NEON load / store instructions, e.g. vld4, vst3.
-// NOTE: It's possible to define more QQ registers since technical the
-// starting D register number doesn't have to be multiple of 4. e.g. 
-// D1, D2, D3, D4 would be a legal quad. But that would make the sub-register
-// stuffs very messy.
+// These are used for NEON load / store instructions, e.g., vld4, vst3.
+// NOTE: It's possible to define more QQ registers since technically the
+// starting D register number doesn't have to be multiple of 4, e.g.,
+// D1, D2, D3, D4 would be a legal quad, but that would make the subregister
+// stuff very messy.
 let SubRegIndices = [qsub_0, qsub_1] in {
 let CompositeIndices = [(dsub_2 qsub_1, dsub_0), (dsub_3 qsub_1, dsub_1),
                         (ssub_4 qsub_1, ssub_0), (ssub_5 qsub_1, ssub_1),




From ggreif at gmail.com  Thu Jul  8 11:56:18 2010
From: ggreif at gmail.com (Gabor Greif)
Date: Thu, 08 Jul 2010 16:56:18 -0000
Subject: [llvm-commits] [llvm] r107883 -
	/llvm/trunk/include/llvm/Analysis/DominatorInternals.h
Message-ID: <20100708165618.F1C292A6C12C@llvm.org>

Author: ggreif
Date: Thu Jul  8 11:56:18 2010
New Revision: 107883

URL: http://llvm.org/viewvc/llvm-project?rev=107883&view=rev
Log:
only dereference iterator once in the loop
(by caching the result we save a potentially expensive dereference)

also use typedefs to shorten type declarations

Modified:
    llvm/trunk/include/llvm/Analysis/DominatorInternals.h

Modified: llvm/trunk/include/llvm/Analysis/DominatorInternals.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DominatorInternals.h?rev=107883&r1=107882&r2=107883&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/DominatorInternals.h (original)
+++ llvm/trunk/include/llvm/Analysis/DominatorInternals.h Thu Jul  8 11:56:18 2010
@@ -265,14 +265,17 @@
 
     // initialize the semi dominator to point to the parent node
     WInfo.Semi = WInfo.Parent;
-    for (typename GraphTraits >::ChildIteratorType CI =
-         GraphTraits >::child_begin(W),
-         E = GraphTraits >::child_end(W); CI != E; ++CI)
-      if (DT.Info.count(*CI)) {  // Only if this predecessor is reachable!
-        unsigned SemiU = DT.Info[Eval(DT, *CI)].Semi;
+    typedef GraphTraits > InvTraits;
+    for (typename InvTraits::ChildIteratorType CI =
+         InvTraits::child_begin(W),
+         E = InvTraits::child_end(W); CI != E; ++CI) {
+      typename InvTraits::NodeType *N = *CI;
+      if (DT.Info.count(N)) {  // Only if this predecessor is reachable!
+        unsigned SemiU = DT.Info[Eval(DT, N)].Semi;
         if (SemiU < WInfo.Semi)
           WInfo.Semi = SemiU;
       }
+    }
 
     DT.Info[DT.Vertex[WInfo.Semi]].Bucket.push_back(W);
 




From gohman at apple.com  Thu Jul  8 12:20:28 2010
From: gohman at apple.com (Dan Gohman)
Date: Thu, 08 Jul 2010 10:20:28 -0700
Subject: [llvm-commits] [patch] Fix va_arg for double and some cleanups
In-Reply-To: 
References: 
	<8F256730-8DB3-4855-86E0-38F60D7D148E@apple.com>
	
	
Message-ID: <9A8F1803-7291-4665-95C5-BB0B5B7822A7@apple.com>

getTransientStackAlignment does not seem the right tool here.  You  
want to know how arguments in memory for varargs are aligned, not how  
the stack pointer itself is aligned.

Dan

On Jul 8, 2010, at 7:19 AM, Rafael Espindola   
wrote:

> I think I found the correct method: getTransientStackAlignment.
>
> The attached patch uses it. Is it OK?
>
> Cheers,
> -- 
> Rafael ?vila de Esp?ndola
> 



From enderby at apple.com  Thu Jul  8 12:22:42 2010
From: enderby at apple.com (Kevin Enderby)
Date: Thu, 08 Jul 2010 17:22:42 -0000
Subject: [llvm-commits] [llvm] r107886 - in /llvm/trunk:
 include/llvm/MC/MCAsmInfo.h include/llvm/MC/MCDirectives.h
 lib/MC/MCAsmInfo.cpp lib/MC/MCAsmInfoDarwin.cpp lib/MC/MCAsmStreamer.cpp
 lib/MC/MCMachOStreamer.cpp lib/MC/MCParser/AsmParser.cpp
Message-ID: <20100708172242.7F83B2A6C12C@llvm.org>

Author: enderby
Date: Thu Jul  8 12:22:42 2010
New Revision: 107886

URL: http://llvm.org/viewvc/llvm-project?rev=107886&view=rev
Log:
Added the darwin .weak_def_can_be_hidden directive.

Modified:
    llvm/trunk/include/llvm/MC/MCAsmInfo.h
    llvm/trunk/include/llvm/MC/MCDirectives.h
    llvm/trunk/lib/MC/MCAsmInfo.cpp
    llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp
    llvm/trunk/lib/MC/MCAsmStreamer.cpp
    llvm/trunk/lib/MC/MCMachOStreamer.cpp
    llvm/trunk/lib/MC/MCParser/AsmParser.cpp

Modified: llvm/trunk/include/llvm/MC/MCAsmInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAsmInfo.h?rev=107886&r1=107885&r2=107886&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCAsmInfo.h (original)
+++ llvm/trunk/include/llvm/MC/MCAsmInfo.h Thu Jul  8 12:22:42 2010
@@ -217,6 +217,11 @@
     /// global as being a weak defined symbol.
     const char *WeakDefDirective;            // Defaults to NULL.
 
+    /// WeakDefAutoPrivateDirective - This directive, if non-null, is used to
+    /// declare a global as being a weak defined symbol that is automatically
+    /// made private by the static linker.
+    const char *WeakDefAutoPrivateDirective; // Defaults to NULL.
+
     /// LinkOnceDirective - This directive, if non-null is used to declare a
     /// global as being a weak defined symbol.  This is used on cygwin/mingw.
     const char *LinkOnceDirective;           // Defaults to NULL.
@@ -387,6 +392,9 @@
     bool hasNoDeadStrip() const { return HasNoDeadStrip; }
     const char *getWeakRefDirective() const { return WeakRefDirective; }
     const char *getWeakDefDirective() const { return WeakDefDirective; }
+    const char *getWeakDefAutoPrivateDirective() const {
+      return WeakDefAutoPrivateDirective;
+    }
     const char *getLinkOnceDirective() const { return LinkOnceDirective; }
     
     MCSymbolAttr getHiddenVisibilityAttr() const { return HiddenVisibilityAttr;}

Modified: llvm/trunk/include/llvm/MC/MCDirectives.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCDirectives.h?rev=107886&r1=107885&r2=107886&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCDirectives.h (original)
+++ llvm/trunk/include/llvm/MC/MCDirectives.h Thu Jul  8 12:22:42 2010
@@ -38,7 +38,8 @@
   MCSA_Reference,           ///< .reference (MachO)
   MCSA_Weak,                ///< .weak
   MCSA_WeakDefinition,      ///< .weak_definition (MachO)
-  MCSA_WeakReference        ///< .weak_reference (MachO)
+  MCSA_WeakReference,       ///< .weak_reference (MachO)
+  MCSA_WeakDefAutoPrivate   ///< .weak_def_can_be_hidden (MachO)
 };
 
 enum MCAssemblerFlag {

Modified: llvm/trunk/lib/MC/MCAsmInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmInfo.cpp?rev=107886&r1=107885&r2=107886&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAsmInfo.cpp (original)
+++ llvm/trunk/lib/MC/MCAsmInfo.cpp Thu Jul  8 12:22:42 2010
@@ -59,6 +59,7 @@
   HasNoDeadStrip = false;
   WeakRefDirective = 0;
   WeakDefDirective = 0;
+  WeakDefAutoPrivateDirective = 0;
   LinkOnceDirective = 0;
   HiddenVisibilityAttr = MCSA_Hidden;
   ProtectedVisibilityAttr = MCSA_Protected;

Modified: llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp?rev=107886&r1=107885&r2=107886&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp (original)
+++ llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp Thu Jul  8 12:22:42 2010
@@ -33,6 +33,7 @@
   // Directives:
   WeakDefDirective = "\t.weak_definition ";
   WeakRefDirective = "\t.weak_reference ";
+  WeakDefAutoPrivateDirective = "\t.weak_def_can_be_hidden ";
   ZeroDirective = "\t.space\t";  // ".space N" emits N zeros.
   HasMachoZeroFillDirective = true;  // Uses .zerofill
   HasMachoTBSSDirective = true; // Uses .tbss

Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=107886&r1=107885&r2=107886&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original)
+++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Thu Jul  8 12:22:42 2010
@@ -288,6 +288,7 @@
   case MCSA_WeakDefinition: OS << "\t.weak_definition\t"; break;
       // .weak_reference
   case MCSA_WeakReference:  OS << MAI.getWeakRefDirective(); break;
+  case MCSA_WeakDefAutoPrivate: OS << "\t.weak_def_can_be_hidden\t"; break;
   }
 
   OS << *Symbol;

Modified: llvm/trunk/lib/MC/MCMachOStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCMachOStreamer.cpp?rev=107886&r1=107885&r2=107886&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCMachOStreamer.cpp (original)
+++ llvm/trunk/lib/MC/MCMachOStreamer.cpp Thu Jul  8 12:22:42 2010
@@ -273,6 +273,10 @@
     // it has to be in a coalesced section, but this isn't enforced.
     SD.setFlags(SD.getFlags() | SF_WeakDefinition);
     break;
+
+  case MCSA_WeakDefAutoPrivate:
+    SD.setFlags(SD.getFlags() | SF_WeakDefinition | SF_WeakReference);
+    break;
   }
 }
 

Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=107886&r1=107885&r2=107886&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original)
+++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Thu Jul  8 12:22:42 2010
@@ -755,6 +755,8 @@
       return ParseDirectiveSymbolAttribute(MCSA_WeakDefinition);
     if (IDVal == ".weak_reference")
       return ParseDirectiveSymbolAttribute(MCSA_WeakReference);
+    if (IDVal == ".weak_def_can_be_hidden")
+      return ParseDirectiveSymbolAttribute(MCSA_WeakDefAutoPrivate);
 
     if (IDVal == ".comm")
       return ParseDirectiveComm(/*IsLocal=*/false);




From grosbach at apple.com  Thu Jul  8 12:27:23 2010
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 08 Jul 2010 17:27:23 -0000
Subject: [llvm-commits] [llvm] r107887 -
	/llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h
Message-ID: <20100708172723.38E3E2A6C12C@llvm.org>

Author: grosbach
Date: Thu Jul  8 12:27:23 2010
New Revision: 107887

URL: http://llvm.org/viewvc/llvm-project?rev=107887&view=rev
Log:
After r107880, findSurvivorReg() no longer needs to be public.

Modified:
    llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h

Modified: llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h?rev=107887&r1=107886&r2=107887&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h (original)
+++ llvm/trunk/include/llvm/CodeGen/RegisterScavenging.h Thu Jul  8 12:27:23 2010
@@ -106,16 +106,6 @@
   /// Return 0 if none is found.
   unsigned FindUnusedReg(const TargetRegisterClass *RegClass) const;
 
-  /// findSurvivorReg - Return the candidate register that is unused for the
-  /// longest after StartMI. UseMI is set to the instruction where the search
-  /// stopped.
-  ///
-  /// No more than InstrLimit instructions are inspected.
-  unsigned findSurvivorReg(MachineBasicBlock::iterator StartMI,
-                           BitVector &Candidates,
-                           unsigned InstrLimit,
-                           MachineBasicBlock::iterator &UseMI);
-
   /// setScavengingFrameIndex / getScavengingFrameIndex - accessor and setter of
   /// ScavengingFrameIndex.
   void setScavengingFrameIndex(int FI) { ScavengingFrameIndex = FI; }
@@ -161,6 +151,16 @@
   /// Add Reg and its aliases to BV.
   void addRegWithAliases(BitVector &BV, unsigned Reg);
 
+  /// findSurvivorReg - Return the candidate register that is unused for the
+  /// longest after StartMI. UseMI is set to the instruction where the search
+  /// stopped.
+  ///
+  /// No more than InstrLimit instructions are inspected.
+  unsigned findSurvivorReg(MachineBasicBlock::iterator StartMI,
+                           BitVector &Candidates,
+                           unsigned InstrLimit,
+                           MachineBasicBlock::iterator &UseMI);
+
 };
 
 } // End llvm namespace




From criswell at uiuc.edu  Thu Jul  8 12:33:59 2010
From: criswell at uiuc.edu (John Criswell)
Date: Thu, 08 Jul 2010 17:33:59 -0000
Subject: [llvm-commits] [poolalloc] r107888 -
 /poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp
Message-ID: <20100708173359.631F42A6C12C@llvm.org>

Author: criswell
Date: Thu Jul  8 12:33:59 2010
New Revision: 107888

URL: http://llvm.org/viewvc/llvm-project?rev=107888&view=rev
Log:
Removed code that inserted poolinit()/pooldestroy() around function calls which
had parameters that had no pool handle.  I believe adding this code is
incorrect when the heuristic allows certain values to be allocated using the
original allocator (i.e., some values are not pool-allocated).

Modified:
    poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp

Modified: poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp?rev=107888&r1=107887&r2=107888&view=diff
==============================================================================
--- poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp (original)
+++ poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp Thu Jul  8 12:33:59 2010
@@ -167,8 +167,21 @@
 }
 
 void FuncTransform::visitLoadInst(LoadInst &LI) {
+  //
+  // Record the use of the pool handle for the pointer being dereferenced.
+  //
   if (Value *PH = getPoolHandle(LI.getOperand(0)))
     AddPoolUse(LI, PH, PoolUses);
+
+  //
+  // If this is a volatile load, then record a use of the pool handle for the
+  // loaded value, even if it is never used.
+  //
+  if (LI.isVolatile()) {
+    if (Value *PH = getPoolHandle(&LI))
+      AddPoolUse (LI, PH, PoolUses);
+  }
+
   visitInstruction(LI);
 }
 
@@ -650,14 +663,21 @@
   I->eraseFromParent();
 }
 
-
+//
+// Method: visitCallSite()
+//
+// Description:
+//  This method transforms a call site.  A call site may either be a call
+//  instruction or an invoke instruction.
+//
+// Inputs:
+//  CS - The call site representing the instruction that should be transformed.
+//
 void FuncTransform::visitCallSite(CallSite& CS) {
   const Function *CF = CS.getCalledFunction();
   Instruction *TheCall = CS.getInstruction();
   bool thread_creation_point = false;
 
-  const Type* Int32Type = Type::getInt32Ty(CS.getInstruction()->getContext());
-
   //
   // Get the value that is called at this call site.  Strip away any pointer
   // casts that do not change the representation of the data (i.e., are
@@ -877,36 +897,30 @@
 //                                    getDSNodeHFor(*GI),
 //                                    NodeMapping, false);
 
+  //
   // Okay, now that we have established our mapping, we can figure out which
   // pool descriptors to pass in...
+  //
+  // Note:
+  // There used to be code here that would create a new pool before the
+  // function call and destroy it after the function call.  This could would
+  // get triggered if bounds checking was disbled or the DSNode for the
+  // argument was an array value.
+  //
+  // I believe that code was incorrect; an argument may have a NULL pool handle
+  // (i.e., no pool handle) because the pool allocation heuristic used simply
+  // decided not to assign that value a pool.  The argument may alias data
+  // that should not be freed after the function call is complete, so calling
+  // pooldestroy() after the call would free data, causing dangling pointer
+  // dereference errors.
+  //
   std::vector Args;
   for (unsigned i = 0, e = ArgNodes.size(); i != e; ++i) {
     Value *ArgVal = Constant::getNullValue(PoolAllocate::PoolDescPtrTy);
-    if (NodeMapping.count(ArgNodes[i]))
+    if (NodeMapping.count(ArgNodes[i])) {
       if (DSNode *LocalNode = NodeMapping[ArgNodes[i]].getNode())
         if (FI.PoolDescriptors.count(LocalNode))
           ArgVal = FI.PoolDescriptors.find(LocalNode)->second;
-    if (isa(ArgVal) && cast(ArgVal)->isNullValue()) {
-      if ((!(PAInfo.BoundsChecksEnabled)) || (ArgNodes[i]->isArrayNode())) {
-        if (!isa(TheCall)) {
-          // Dinakar: We need pooldescriptors for allocas in the callee if it
-          //          escapes
-          BasicBlock::iterator InsertPt = TheCall->getParent()->getParent()->front().begin();
-          ArgVal =  new AllocaInst(PAInfo.getPoolType(&TheCall->getContext()),
-                                   0,
-                                   "PD",
-                                   InsertPt);
-          Value *ElSize = ConstantInt::get(Int32Type,0);
-          Value *Align  = ConstantInt::get(Int32Type,0);
-          Value* Opts[3] = {ArgVal, ElSize, Align};
-          CallInst::Create(PAInfo.PoolInit, Opts, Opts + 3,"", TheCall);
-          BasicBlock::iterator BBI = TheCall;
-          CallInst::Create(PAInfo.PoolDestroy, ArgVal, "", ++BBI);
-        }
-
-        //probably need to update DSG
-        //      errs() << "WARNING: NULL POOL ARGUMENTS ARE PASSED IN!\n";
-      }
     }
     Args.push_back(ArgVal);
   }




From espindola at google.com  Thu Jul  8 12:35:24 2010
From: espindola at google.com (Rafael Espindola)
Date: Thu, 8 Jul 2010 13:35:24 -0400
Subject: [llvm-commits] [patch] Fix va_arg for double and some cleanups
In-Reply-To: <9A8F1803-7291-4665-95C5-BB0B5B7822A7@apple.com>
References: 
	<8F256730-8DB3-4855-86E0-38F60D7D148E@apple.com>
	
	
	<9A8F1803-7291-4665-95C5-BB0B5B7822A7@apple.com>
Message-ID: 

On 8 July 2010 13:20, Dan Gohman  wrote:
> getTransientStackAlignment does not seem the right tool here. ?You want to
> know how arguments in memory for varargs are aligned, not how the stack
> pointer itself is aligned.

No, I what to know the stack alignment. The VAARG node already contain
by how much the argument is aligned. The question we are trying to
answer is "Is this argument more alignment that what we know the stack
already is?". Knowing that we can insert alignment instructions only
when necessary.

> Dan

Cheers,
-- 
Rafael ?vila de Esp?ndola



From bob.wilson at apple.com  Thu Jul  8 12:44:00 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Thu, 08 Jul 2010 17:44:00 -0000
Subject: [llvm-commits] [llvm] r107890 -
	/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
Message-ID: <20100708174400.4476C2A6C12D@llvm.org>

Author: bwilson
Date: Thu Jul  8 12:44:00 2010
New Revision: 107890

URL: http://llvm.org/viewvc/llvm-project?rev=107890&view=rev
Log:
For big-endian systems, VLD2/VST2 with 32-bit vector elements will swap the
words within the 64-bit D registers.  Use VLD1/VST1 with 64-bit elements
instead.

Modified:
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=107890&r1=107889&r2=107890&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Thu Jul  8 12:44:00 2010
@@ -848,7 +848,7 @@
     if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
       // FIXME: It's possible to only store part of the QQ register if the
       // spilled def has a sub-register index.
-      MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VST2q32))
+      MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VST1d64Q))
         .addFrameIndex(FI).addImm(16);
       MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
       MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
@@ -941,7 +941,7 @@
   case ARM::QQPRRegClassID:
   case ARM::QQPR_VFP2RegClassID:
     if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
-      MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLD2q32));
+      MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLD1d64Q));
       MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
       MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
       MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);




From scanon at apple.com  Thu Jul  8 12:45:05 2010
From: scanon at apple.com (Stephen Canon)
Date: Thu, 08 Jul 2010 17:45:05 -0000
Subject: [llvm-commits] [compiler-rt] r107891 -
	/compiler-rt/trunk/lib/arm/comparesf2.S
Message-ID: <20100708174505.B673D2A6C12C@llvm.org>

Author: scanon
Date: Thu Jul  8 12:45:05 2010
New Revision: 107891

URL: http://llvm.org/viewvc/llvm-project?rev=107891&view=rev
Log:
Hand-tuning of single-precision soft-float comparison routines for ARM

Added:
    compiler-rt/trunk/lib/arm/comparesf2.S

Added: compiler-rt/trunk/lib/arm/comparesf2.S
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/lib/arm/comparesf2.S?rev=107891&view=auto
==============================================================================
--- compiler-rt/trunk/lib/arm/comparesf2.S (added)
+++ compiler-rt/trunk/lib/arm/comparesf2.S Thu Jul  8 12:45:05 2010
@@ -0,0 +1,130 @@
+//===-- comparesf2.S - Implement single-precision soft-float comparisons --===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the following soft-fp_t comparison routines:
+//
+//   __eqsf2   __gesf2   __unordsf2
+//   __lesf2   __gtsf2
+//   __ltsf2
+//   __nesf2
+//
+// The semantics of the routines grouped in each column are identical, so there
+// is a single implementation for each, with multiple names.
+//
+// The routines behave as follows:
+//
+//   __lesf2(a,b) returns -1 if a < b
+//                         0 if a == b
+//                         1 if a > b
+//                         1 if either a or b is NaN
+//
+//   __gesf2(a,b) returns -1 if a < b
+//                         0 if a == b
+//                         1 if a > b
+//                        -1 if either a or b is NaN
+//
+//   __unordsf2(a,b) returns 0 if both a and b are numbers
+//                           1 if either a or b is NaN
+//
+// Note that __lesf2( ) and __gesf2( ) are identical except in their handling of
+// NaN values.
+//
+//===----------------------------------------------------------------------===//
+
+#include "../assembly.h"
+.syntax unified
+
+.align 2
+DEFINE_COMPILERRT_FUNCTION(__eqsf2)
+DEFINE_COMPILERRT_FUNCTION(__lesf2)
+DEFINE_COMPILERRT_FUNCTION(__ltsf2)
+DEFINE_COMPILERRT_FUNCTION(__nesf2)
+    // Make copies of a and b with the sign bit shifted off the top.  These will
+    // be used to detect zeros and NaNs.
+    mov     r2,         r0, lsl #1
+    mov     r3,         r1, lsl #1
+    
+    // We do the comparison in three stages (ignoring NaN values for the time
+    // being).  First, we orr the absolute values of a and b; this sets the Z
+    // flag if both a and b are zero (of either sign).  The shift of r3 doesn't
+    // effect this at all, but it *does* make sure that the C flag is clear for
+    // the subsequent operations.
+    orrs    r12,    r2, r3, lsr #1
+    
+    // Next, we check if a and b have the same or different signs.  If they have
+    // opposite signs, this eor will set the N flag.
+    eorsne  r12,    r0, r1
+    
+    // If a and b are equal (either both zeros or bit identical; again, we're
+    // ignoring NaNs for now), this subtract will zero out r0.  If they have the
+    // same sign, the flags are updated as they would be for a comparison of the
+    // absolute values of a and b.
+    subspl  r0,     r2, r3
+    
+    // If a is smaller in magnitude than b and both have the same sign, place
+    // the negation of the sign of b in r0.  Thus, if both are negative and
+    // a > b, this sets r0 to 0; if both are positive and a < b, this sets
+    // r0 to -1.
+    //
+    // This is also done if a and b have opposite signs and are not both zero,
+    // because in that case the subtract was not performed and the C flag is
+    // still clear from the shift argument in orrs; if a is positive and b
+    // negative, this places 0 in r0; if a is negative and b positive, -1 is
+    // placed in r0.
+    mvnlo   r0,         r1, asr #31
+
+    // If a is greater in magnitude than b and both have the same sign, place
+    // the sign of b in r0.  Thus, if both are negative and a < b, -1 is placed
+    // in r0, which is the desired result.  Conversely, if both are positive
+    // and a > b, zero is placed in r0.
+    movhi   r0,         r1, asr #31
+    
+    // If you've been keeping track, at this point r0 contains -1 if a < b and
+    // 0 if a >= b.  All that remains to be done is to set it to 1 if a > b.
+    // If a == b, then the Z flag is set, so we can get the correct final value
+    // into r0 by simply or'ing with 1 if Z is clear.
+	orrne	r0,     r0, #1
+    
+    // Finally, we need to deal with NaNs.  If either argument is NaN, replace
+    // the value in r0 with 1.
+    cmp     r2,         #0xff000000
+    cmpls   r3,         #0xff000000
+    movhi   r0,         #1
+    bx      lr
+    
+.align 2
+DEFINE_COMPILERRT_FUNCTION(__gesf2)
+DEFINE_COMPILERRT_FUNCTION(__gtsf2)
+    // Identical to the preceeding except in that we return -1 for NaN values.
+    // Given that the two paths share so much code, one might be tempted to 
+    // unify them; however, the extra code needed to do so makes the code size
+    // to performance tradeoff very hard to justify for such small functions.
+    mov     r2,         r0, lsl #1
+    mov     r3,         r1, lsl #1
+    orrs    r12,    r2, r3, lsr #1
+    eorsne  r12,    r0, r1
+    subspl  r0,     r2, r3
+    mvnlo   r0,         r1, asr #31
+    movhi   r0,         r1, asr #31
+	orrne	r0,     r0, #1
+    cmp     r2,         #0xff000000
+    cmpls   r3,         #0xff000000
+    movhi   r0,         #-1
+    bx      lr
+    
+.align 2
+DEFINE_COMPILERRT_FUNCTION(__unordsf2)
+    // Return 1 for NaN values, 0 otherwise.
+    mov     r2,         r0, lsl #1
+    mov     r3,         r1, lsl #1
+    mov     r0,         #0
+    cmp     r2,         #0xff000000
+    cmpls   r3,         #0xff000000
+    movhi   r0,         #1
+    bx      lr




From bob.wilson at apple.com  Thu Jul  8 12:45:26 2010
From: bob.wilson at apple.com (Bob Wilson)
Date: Thu, 08 Jul 2010 17:45:26 -0000
Subject: [llvm-commits] [llvm] r107892 -
	/llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp
Message-ID: <20100708174526.35BDC2A6C12C@llvm.org>

Author: bwilson
Date: Thu Jul  8 12:45:26 2010
New Revision: 107892

URL: http://llvm.org/viewvc/llvm-project?rev=107892&view=rev
Log:
The NEONPreAllocPass should never have to assign fixed registers anymore.
This pass can go away entirely soon.

Modified:
    llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp

Modified: llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp?rev=107892&r1=107891&r2=107892&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp (original)
+++ llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp Thu Jul  8 12:45:26 2010
@@ -468,40 +468,7 @@
       continue;
     if (FormsRegSequence(MI, FirstOpnd, NumRegs, Offset, Stride))
       continue;
-
-    MachineBasicBlock::iterator NextI = llvm::next(MBBI);
-    for (unsigned R = 0; R < NumRegs; ++R) {
-      MachineOperand &MO = MI->getOperand(FirstOpnd + R);
-      assert(MO.isReg() && MO.getSubReg() == 0 && "unexpected operand");
-      unsigned VirtReg = MO.getReg();
-      assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
-             "expected a virtual register");
-
-      // For now, just assign a fixed set of adjacent registers.
-      // This leaves plenty of room for future improvements.
-      static const unsigned NEONDRegs[] = {
-        ARM::D0, ARM::D1, ARM::D2, ARM::D3,
-        ARM::D4, ARM::D5, ARM::D6, ARM::D7
-      };
-      MO.setReg(NEONDRegs[Offset + R * Stride]);
-
-      if (MO.isUse()) {
-        // Insert a copy from VirtReg.
-        TII->copyRegToReg(MBB, MBBI, MO.getReg(), VirtReg,
-                          ARM::DPRRegisterClass, ARM::DPRRegisterClass,
-                          DebugLoc());
-        if (MO.isKill()) {
-          MachineInstr *CopyMI = prior(MBBI);
-          CopyMI->findRegisterUseOperand(VirtReg)->setIsKill();
-        }
-        MO.setIsKill();
-      } else if (MO.isDef() && !MO.isDead()) {
-        // Add a copy to VirtReg.
-        TII->copyRegToReg(MBB, NextI, VirtReg, MO.getReg(),
-                          ARM::DPRRegisterClass, ARM::DPRRegisterClass,
-                          DebugLoc());
-      }
-    }
+    llvm_unreachable("expected a REG_SEQUENCE");
   }
 
   return Modified;




From wdietz2 at illinois.edu  Thu Jul  8 13:51:55 2010
From: wdietz2 at illinois.edu (Will Dietz)
Date: Thu, 08 Jul 2010 18:51:55 -0000
Subject: [llvm-commits] [poolalloc] r107896 -
 /poolalloc/trunk/test/dsa/regression/2010-07-07.UndefArg.ll
Message-ID: <20100708185155.0C79D2A6C12C@llvm.org>

Author: wdietz2
Date: Thu Jul  8 13:51:54 2010
New Revision: 107896

URL: http://llvm.org/viewvc/llvm-project?rev=107896&view=rev
Log:
Don't output the bitcode to stdout, even if the user never sees it.

Modified:
    poolalloc/trunk/test/dsa/regression/2010-07-07.UndefArg.ll

Modified: poolalloc/trunk/test/dsa/regression/2010-07-07.UndefArg.ll
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/regression/2010-07-07.UndefArg.ll?rev=107896&r1=107895&r2=107896&view=diff
==============================================================================
--- poolalloc/trunk/test/dsa/regression/2010-07-07.UndefArg.ll (original)
+++ poolalloc/trunk/test/dsa/regression/2010-07-07.UndefArg.ll Thu Jul  8 13:51:54 2010
@@ -1,4 +1,4 @@
-;RUN: dsaopt %s -ds-aa -gvn
+;RUN: dsaopt %s -ds-aa -gvn -disable-output
 ; FIXME: Make this test more directly test the underlying issue.
 ; (the -ds-aa and -gvn are just ways of forcing the right query to be made)
 




From stoklund at 2pi.dk  Thu Jul  8 14:46:25 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Thu, 08 Jul 2010 19:46:25 -0000
Subject: [llvm-commits] [llvm] r107898 - in /llvm/trunk:
 include/llvm/Target/TargetRegisterInfo.h lib/Target/X86/X86InstrInfo.cpp
 lib/Target/X86/X86InstrInfo.h
Message-ID: <20100708194625.759222A6C12C@llvm.org>

Author: stoklund
Date: Thu Jul  8 14:46:25 2010
New Revision: 107898

URL: http://llvm.org/viewvc/llvm-project?rev=107898&view=rev
Log:
Implement X86InstrInfo::copyPhysReg

Modified:
    llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
    llvm/trunk/lib/Target/X86/X86InstrInfo.h

Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=107898&r1=107897&r2=107898&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Thu Jul  8 14:46:25 2010
@@ -115,6 +115,11 @@
     return RegSet.count(Reg);
   }
 
+  /// contains - Return true if both registers are in this class.
+  bool contains(unsigned Reg1, unsigned Reg2) const {
+    return contains(Reg1) && contains(Reg2);
+  }
+
   /// hasType - return true if this TargetRegisterClass has the ValueType vt.
   ///
   bool hasType(EVT vt) const {

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=107898&r1=107897&r2=107898&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Thu Jul  8 14:46:25 2010
@@ -2058,6 +2058,66 @@
   return false;
 }
 
+void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
+                               MachineBasicBlock::iterator MI, DebugLoc DL,
+                               unsigned DestReg, unsigned SrcReg,
+                               bool KillSrc) const {
+  // First deal with the normal symmetric copies.
+  unsigned Opc = 0;
+  if (X86::GR64RegClass.contains(DestReg, SrcReg))
+    Opc = X86::MOV64rr;
+  else if (X86::GR32RegClass.contains(DestReg, SrcReg))
+    Opc = X86::MOV32rr;
+  else if (X86::GR16RegClass.contains(DestReg, SrcReg))
+    Opc = X86::MOV16rr;
+  else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
+    // Copying to or from a physical H register on x86-64 requires a NOREX
+    // move.  Otherwise use a normal move.
+    if ((isHReg(DestReg) || isHReg(SrcReg)) &&
+        TM.getSubtarget().is64Bit())
+      Opc = X86::MOV8rr_NOREX;
+    else
+      Opc = X86::MOV8rr;
+  } else if (X86::VR128RegClass.contains(DestReg, SrcReg))
+    Opc = X86::MOVAPSrr;
+
+  if (Opc) {
+    BuildMI(MBB, MI, DL, get(Opc), DestReg)
+      .addReg(SrcReg, getKillRegState(KillSrc));
+    return;
+  }
+
+  // Moving EFLAGS to / from another register requires a push and a pop.
+  if (SrcReg == X86::EFLAGS) {
+    if (X86::GR64RegClass.contains(DestReg)) {
+      BuildMI(MBB, MI, DL, get(X86::PUSHF64));
+      BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
+      return;
+    } else if (X86::GR32RegClass.contains(DestReg)) {
+      BuildMI(MBB, MI, DL, get(X86::PUSHF32));
+      BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
+      return;
+    }
+  }
+  if (DestReg == X86::EFLAGS) {
+    if (X86::GR64RegClass.contains(SrcReg)) {
+      BuildMI(MBB, MI, DL, get(X86::PUSH64r))
+        .addReg(SrcReg, getKillRegState(KillSrc));
+      BuildMI(MBB, MI, DL, get(X86::POPF64));
+      return;
+    } else if (X86::GR32RegClass.contains(SrcReg)) {
+      BuildMI(MBB, MI, DL, get(X86::PUSH32r))
+        .addReg(SrcReg, getKillRegState(KillSrc));
+      BuildMI(MBB, MI, DL, get(X86::POPF32));
+      return;
+    }
+  }
+
+  DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
+               << " to " << RI.getName(DestReg) << '\n');
+  llvm_unreachable("Cannot emit physreg copy instruction");
+}
+
 static unsigned getLoadStoreRegOpcode(unsigned Reg,
                                       const TargetRegisterClass *RC,
                                       bool isStackAligned,

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=107898&r1=107897&r2=107898&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Thu Jul  8 14:46:25 2010
@@ -632,6 +632,10 @@
                             const TargetRegisterClass *DestRC,
                             const TargetRegisterClass *SrcRC,
                             DebugLoc DL) const;
+  virtual void copyPhysReg(MachineBasicBlock &MBB,
+                           MachineBasicBlock::iterator MI, DebugLoc DL,
+                           unsigned DestReg, unsigned SrcReg,
+                           bool KillSrc) const;
   virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
                                    MachineBasicBlock::iterator MI,
                                    unsigned SrcReg, bool isKill, int FrameIndex,




From stoklund at 2pi.dk  Thu Jul  8 14:46:30 2010
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Thu, 08 Jul 2010 19:46:30 -0000
Subject: [llvm-commits] [llvm] r107899 -
	/llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp
Message-ID: <20100708194630.8A7602A6C12D@llvm.org>

Author: stoklund
Date: Thu Jul  8 14:46:30 2010
New Revision: 107899

URL: http://llvm.org/viewvc/llvm-project?rev=107899&view=rev
Log:
Teach the x86 floating point stackifier to handle COPY instructions.

This pass runs before COPY instructions are passed to copyPhysReg, so we simply
translate COPY to the proper pseudo instruction. Note that copyPhysReg does not
handle floating point stack copies.

Once COPY is used everywhere, this can be cleaned up a bit, and most of the
pseudo instructions can be removed.

Modified:
    llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp

Modified: llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp?rev=107899&r1=107898&r2=107899&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp Thu Jul  8 14:46:30 2010
@@ -164,6 +164,8 @@
     void handleCompareFP(MachineBasicBlock::iterator &I);
     void handleCondMovFP(MachineBasicBlock::iterator &I);
     void handleSpecialFP(MachineBasicBlock::iterator &I);
+
+    bool translateCopy(MachineInstr*);
   };
   char FPS::ID = 0;
 }
@@ -237,7 +239,10 @@
     unsigned FPInstClass = Flags & X86II::FPTypeMask;
     if (MI->isInlineAsm())
       FPInstClass = X86II::SpecialFP;
-    
+
+    if (MI->isCopy() && translateCopy(MI))
+      FPInstClass = X86II::SpecialFP;
+
     if (FPInstClass == X86II::NotFP)
       continue;  // Efficiently ignore non-fp insts!
 
@@ -1206,3 +1211,33 @@
   I = MBB->erase(I);  // Remove the pseudo instruction
   --I;
 }
+
+// Translate a COPY instruction to a pseudo-op that handleSpecialFP understands.
+bool FPS::translateCopy(MachineInstr *MI) {
+  unsigned DstReg = MI->getOperand(0).getReg();
+  unsigned SrcReg = MI->getOperand(1).getReg();
+
+  if (DstReg == X86::ST0) {
+    MI->setDesc(TII->get(X86::FpSET_ST0_80));
+    MI->RemoveOperand(0);
+    return true;
+  }
+  if (DstReg == X86::ST1) {
+    MI->setDesc(TII->get(X86::FpSET_ST1_80));
+    MI->RemoveOperand(0);
+    return true;
+  }
+  if (SrcReg == X86::ST0) {
+    MI->setDesc(TII->get(X86::FpGET_ST0_80));
+    return true;
+  }
+  if (SrcReg == X86::ST1) {
+    MI->setDesc(TII->get(X86::FpGET_ST1_80));
+    return true;
+  }
+  if (X86::RFP80RegClass.contains(DstReg, SrcReg)) {
+    MI->setDesc(TII->get(X86::MOV_Fp8080));
+    return true;
+  }
+  return false;
+}




From clattner at apple.com  Thu Jul  8 15:04:44 2010
From: clattner at apple.com (Chris Lattner)
Date: Thu, 8 Jul 2010 13:04:44 -0700
Subject: [llvm-commits] [llvm] r107886 - in /llvm/trunk:
	include/llvm/MC/MCAsmInfo.h include/llvm/MC/MCDirectives.h
	lib/MC/MCAsmInfo.cpp lib/MC/MCAsmInfoDarwin.cpp
	lib/MC/MCAsmStreamer.cpp lib/MC/MCMachOStreamer.cpp
	lib/MC/MCParser/AsmParser.cpp
In-Reply-To: <20100708172242.7F83B2A6C12C@llvm.org>
References: <20100708172242.7F83B2A6C12C@llvm.org>
Message-ID: <4DD03A78-26B8-4A48-B18D-C69D30603F8C@apple.com>


On Jul 8, 2010, at 10:22 AM, Kevin Enderby wrote:

> Author: enderby
> Date: Thu Jul  8 12:22:42 2010
> New Revision: 107886
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=107886&view=rev
> Log:
> Added the darwin .weak_def_can_be_hidden directive.

Thanks Kevin,

I think that the MCAsmInfo.h/.cpp chunks aren't needed for this until the compiler starts generating these.  When that happens it will be more convenient for it to be a bool than a const char*.  For now it's probably best to revert those two hunks.  Thanks!

-Chris

> 
> Modified:
>    llvm/trunk/include/llvm/MC/MCAsmInfo.h
>    llvm/trunk/include/llvm/MC/MCDirectives.h
>    llvm/trunk/lib/MC/MCAsmInfo.cpp
>    llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp
>    llvm/trunk/lib/MC/MCAsmStreamer.cpp
>    llvm/trunk/lib/MC/MCMachOStreamer.cpp
>    llvm/trunk/lib/MC/MCParser/AsmParser.cpp
> 
> Modified: llvm/trunk/include/llvm/MC/MCAsmInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAsmInfo.h?rev=107886&r1=107885&r2=107886&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/MC/MCAsmInfo.h (original)
> +++ llvm/trunk/include/llvm/MC/MCAsmInfo.h Thu Jul  8 12:22:42 2010
> @@ -217,6 +217,11 @@
>     /// global as being a weak defined symbol.
>     const char *WeakDefDirective;            // Defaults to NULL.
> 
> +    /// WeakDefAutoPrivateDirective - This directive, if non-null, is used to
> +    /// declare a global as being a weak defined symbol that is automatically
> +    /// made private by the static linker.
> +    const char *WeakDefAutoPrivateDirective; // Defaults to NULL.
> +
>     /// LinkOnceDirective - This directive, if non-null is used to declare a
>     /// global as being a weak defined symbol.  This is used on cygwin/mingw.
>     const char *LinkOnceDirective;           // Defaults to NULL.
> @@ -387,6 +392,9 @@
>     bool hasNoDeadStrip() const { return HasNoDeadStrip; }
>     const char *getWeakRefDirective() const { return WeakRefDirective; }
>     const char *getWeakDefDirective() const { return WeakDefDirective; }
> +    const char *getWeakDefAutoPrivateDirective() const {
> +      return WeakDefAutoPrivateDirective;
> +    }
>     const char *getLinkOnceDirective() const { return LinkOnceDirective; }
> 
>     MCSymbolAttr getHiddenVisibilityAttr() const { return HiddenVisibilityAttr;}
> 
> Modified: llvm/trunk/include/llvm/MC/MCDirectives.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCDirectives.h?rev=107886&r1=107885&r2=107886&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/MC/MCDirectives.h (original)
> +++ llvm/trunk/include/llvm/MC/MCDirectives.h Thu Jul  8 12:22:42 2010
> @@ -38,7 +38,8 @@
>   MCSA_Reference,           ///< .reference (MachO)
>   MCSA_Weak,                ///< .weak
>   MCSA_WeakDefinition,      ///< .weak_definition (MachO)
> -  MCSA_WeakReference        ///< .weak_reference (MachO)
> +  MCSA_WeakReference,       ///< .weak_reference (MachO)
> +  MCSA_WeakDefAutoPrivate   ///< .weak_def_can_be_hidden (MachO)
> };
> 
> enum MCAssemblerFlag {
> 
> Modified: llvm/trunk/lib/MC/MCAsmInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmInfo.cpp?rev=107886&r1=107885&r2=107886&view=diff
> ==============================================================================
> --- llvm/trunk/lib/MC/MCAsmInfo.cpp (original)
> +++ llvm/trunk/lib/MC/MCAsmInfo.cpp Thu Jul  8 12:22:42 2010
> @@ -59,6 +59,7 @@
>   HasNoDeadStrip = false;
>   WeakRefDirective = 0;
>   WeakDefDirective = 0;
> +  WeakDefAutoPrivateDirective = 0;
>   LinkOnceDirective = 0;
>   HiddenVisibilityAttr = MCSA_Hidden;
>   ProtectedVisibilityAttr = MCSA_Protected;
> 
> Modified: llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp?rev=107886&r1=107885&r2=107886&view=diff
> ==============================================================================
> --- llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp (original)
> +++ llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp Thu Jul  8 12:22:42 2010
> @@ -33,6 +33,7 @@
>   // Directives:
>   WeakDefDirective = "\t.weak_definition ";
>   WeakRefDirective = "\t.weak_reference ";
> +  WeakDefAutoPrivateDirective = "\t.weak_def_can_be_hidden ";
>   ZeroDirective = "\t.space\t";  // ".space N" emits N zeros.
>   HasMachoZeroFillDirective = true;  // Uses .zerofill
>   HasMachoTBSSDirective = true; // Uses .tbss
> 
> Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=107886&r1=107885&r2=107886&view=diff
> ==============================================================================
> --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original)
> +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Thu Jul  8 12:22:42 2010
> @@ -288,6 +288,7 @@
>   case MCSA_WeakDefinition: OS << "\t.weak_definition\t"; break;
>       // .weak_reference
>   case MCSA_WeakReference:  OS << MAI.getWeakRefDirective(); break;
> +  case MCSA_WeakDefAutoPrivate: OS << "\t.weak_def_can_be_hidden\t"; break;
>   }
> 
>   OS << *Symbol;
> 
> Modified: llvm/trunk/lib/MC/MCMachOStreamer.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCMachOStreamer.cpp?rev=107886&r1=107885&r2=107886&view=diff
> ==============================================================================
> --- llvm/trunk/lib/MC/MCMachOStreamer.cpp (original)
> +++ llvm/trunk/lib/MC/MCMachOStreamer.cpp Thu Jul  8 12:22:42 2010
> @@ -273,6 +273,10 @@
>     // it has to be in a coalesced section, but this isn't enforced.
>     SD.setFlags(SD.getFlags() | SF_WeakDefinition);
>     break;
> +
> +  case MCSA_WeakDefAutoPrivate:
> +    SD.setFlags(SD.getFlags() | SF_WeakDefinition | SF_WeakReference);
> +    break;
>   }
> }
> 
> 
> Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=107886&r1=107885&r2=107886&view=diff
> ==============================================================================
> --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original)
> +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Thu Jul  8 12:22:42 2010
> @@ -755,6 +755,8 @@
>       return ParseDirectiveSymbolAttribute(MCSA_WeakDefinition);
>     if (IDVal == ".weak_reference")
>       return ParseDirectiveSymbolAttribute(MCSA_WeakReference);
> +    if (IDVal == ".weak_def_can_be_hidden")
> +      return ParseDirectiveSymbolAttribute(MCSA_WeakDefAutoPrivate);
> 
>     if (IDVal == ".comm")
>       return ParseDirectiveComm(/*IsLocal=*/false);
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits




From wdietz2 at illinois.edu  Thu Jul  8 15:08:05 2010
From: wdietz2 at illinois.edu (Will Dietz)
Date: Thu, 08 Jul 2010 20:08:05 -0000
Subject: [llvm-commits] [poolalloc] r107901 -
 /poolalloc/trunk/test/dsa/regression/2010-07-08.FPDeclaration.c
Message-ID: <20100708200805.B81EF2A6C12C@llvm.org>

Author: wdietz2
Date: Thu Jul  8 15:08:05 2010
New Revision: 107901

URL: http://llvm.org/viewvc/llvm-project?rev=107901&view=rev
Log:
Added test case where DSA crashes when processing an indirect call to an external function.

Added:
    poolalloc/trunk/test/dsa/regression/2010-07-08.FPDeclaration.c

Added: poolalloc/trunk/test/dsa/regression/2010-07-08.FPDeclaration.c
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/regression/2010-07-08.FPDeclaration.c?rev=107901&view=auto
==============================================================================
--- poolalloc/trunk/test/dsa/regression/2010-07-08.FPDeclaration.c (added)
+++ poolalloc/trunk/test/dsa/regression/2010-07-08.FPDeclaration.c Thu Jul  8 15:08:05 2010
@@ -0,0 +1,12 @@
+//Test that DSA doesn't crash when processing an indirect call to an external function.
+//RUN: llvm-gcc -S --emit-llvm -c %s -o %t.bc
+//RUN: dsaopt %t.bc -dsa-td -disable-output
+
+extern void func(void);
+
+int main() {
+  void (*fp)(void) = func;
+  fp();
+  return 0;
+}
+




From dpatel at apple.com  Thu Jul  8 15:10:35 2010
From: dpatel at apple.com (Devang Patel)
Date: Thu, 08 Jul 2010 20:10:35 -0000
Subject: [llvm-commits] [llvm] r107903 - in
 /llvm/trunk/lib/CodeGen/AsmPrinter: DwarfDebug.cpp DwarfDebug.h
Message-ID: <20100708201035.CD0872A6C12C@llvm.org>

Author: dpatel
Date: Thu Jul  8 15:10:35 2010
New Revision: 107903

URL: http://llvm.org/viewvc/llvm-project?rev=107903&view=rev
Log:
Reuse DIEInteger for 1. This is frequently used while emitting an attribute using dwarf::DW_FORM_flag form.

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=107903&r1=107902&r2=107903&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Thu Jul  8 15:10:35 2010
@@ -322,6 +322,7 @@
   DwarfDebugRangeSectionSym = DwarfDebugLocSectionSym = 0; 
   DwarfDebugLineSectionSym = CurrentLineSectionSym = 0;
   FunctionBeginSym = FunctionEndSym = 0;
+  DIEIntegerOne = new (DIEValueAllocator) DIEInteger(1);
   {
     NamedRegionTimer T(DbgTimerName, DWARFGroupName, TimePassesIsEnabled);
     beginModule(M);
@@ -376,7 +377,8 @@
 void DwarfDebug::addUInt(DIE *Die, unsigned Attribute,
                          unsigned Form, uint64_t Integer) {
   if (!Form) Form = DIEInteger::BestForm(false, Integer);
-  DIEValue *Value = new (DIEValueAllocator) DIEInteger(Integer);
+  DIEValue *Value = Integer == 1 ? 
+    DIEIntegerOne : new (DIEValueAllocator) DIEInteger(Integer);
   Die->addValue(Attribute, Form, Value);
 }
 

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h?rev=107903&r1=107902&r2=107903&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Thu Jul  8 15:10:35 2010
@@ -263,6 +263,8 @@
   MCSymbol *DwarfDebugLocSectionSym;
   MCSymbol *DwarfDebugLineSectionSym, *CurrentLineSectionSym;
   MCSymbol *FunctionBeginSym, *FunctionEndSym;
+
+  DIEInteger *DIEIntegerOne;
 private:
   
   /// getSourceDirectoryAndFileIds - Return the directory and file ids that




From evan.cheng at apple.com  Thu Jul  8 15:12:24 2010
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 08 Jul 2010 20:12:24 -0000
Subject: [llvm-commits] [llvm] r107904 - in /llvm/trunk:
 lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/ARM/fpcmp-opt.ll
Message-ID: <20100708201224.B8FBB2A6C12C@llvm.org>

Author: evancheng
Date: Thu Jul  8 15:12:24 2010
New Revision: 107904

URL: http://llvm.org/viewvc/llvm-project?rev=107904&view=rev
Log:
Check for FiniteOnlyFPMath as well.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/test/CodeGen/ARM/fpcmp-opt.ll

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=107904&r1=107903&r2=107904&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Jul  8 15:12:24 2010
@@ -2295,7 +2295,7 @@
 ARMTargetLowering::getVFPCmp(SDValue &LHS, SDValue &RHS, ISD::CondCode CC,
                              SDValue &ARMCC, SelectionDAG &DAG,
                              DebugLoc dl) const {
-  if (UnsafeFPMath &&
+  if (UnsafeFPMath && FiniteOnlyFPMath() &&
       (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
        CC == ISD::SETNE || CC == ISD::SETUNE) &&
       canBitcastToInt(LHS.getNode()) && canBitcastToInt(RHS.getNode())) {

Modified: llvm/trunk/test/CodeGen/ARM/fpcmp-opt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fpcmp-opt.ll?rev=107904&r1=107903&r2=107904&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fpcmp-opt.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fpcmp-opt.ll Thu Jul  8 15:12:24 2010
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm -mattr=+vfp2 -enable-unsafe-fp-math | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+vfp2 -enable-unsafe-fp-math -enable-finite-only-fp-math | FileCheck %s
 ; rdar://7461510
 
 define arm_apcscc i32 @t1(float* %a, float* %b) nounwind {




From clattner at apple.com  Thu Jul  8 15:15:36 2010
From: clattner at apple.com (Chris Lattner)
Date: Thu, 8 Jul 2010 13:15:36 -0700
Subject: [llvm-commits] [llvm] r107904 - in /llvm/trunk:
	lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/ARM/fpcmp-opt.ll
In-Reply-To: <20100708201224.B8FBB2A6C12C@llvm.org>
References: <20100708201224.B8FBB2A6C12C@llvm.org>
Message-ID: 


On Jul 8, 2010, at 1:12 PM, Evan Cheng wrote:

> Author: evancheng
> Date: Thu Jul  8 15:12:24 2010
> New Revision: 107904
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=107904&view=rev
> Log:
> Check for FiniteOnlyFPMath as well.

Evan, this xform is not target specific.  Is there any reason not to implement it in dag combine?

It also seems really dangerous to me, even for -ffast-math.

-Chris

> 
> Modified:
>    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
>    llvm/trunk/test/CodeGen/ARM/fpcmp-opt.ll
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=107904&r1=107903&r2=107904&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Jul  8 15:12:24 2010
> @@ -2295,7 +2295,7 @@
> ARMTargetLowering::getVFPCmp(SDValue &LHS, SDValue &RHS, ISD::CondCode CC,
>                              SDValue &ARMCC, SelectionDAG &DAG,
>                              DebugLoc dl) const {
> -  if (UnsafeFPMath &&
> +  if (UnsafeFPMath && FiniteOnlyFPMath() &&
>       (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
>        CC == ISD::SETNE || CC == ISD::SETUNE) &&
>       canBitcastToInt(LHS.getNode()) && canBitcastToInt(RHS.getNode())) {
> 
> Modified: llvm/trunk/test/CodeGen/ARM/fpcmp-opt.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fpcmp-opt.ll?rev=107904&r1=107903&r2=107904&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/fpcmp-opt.ll (original)
> +++ llvm/trunk/test/CodeGen/ARM/fpcmp-opt.ll Thu Jul  8 15:12:24 2010
> @@ -1,4 +1,4 @@
> -; RUN: llc < %s -march=arm -mattr=+vfp2 -enable-unsafe-fp-math | FileCheck %s
> +; RUN: llc < %s -march=arm -mattr=+vfp2 -enable-unsafe-fp-math -enable-finite-only-fp-math | FileCheck %s
> ; rdar://7461510
> 
> define arm_apcscc i32 @t1(float* %a, float* %b) nounwind {
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits




From enderby at apple.com  Thu Jul  8 15:30:44 2010
From: enderby at apple.com (Kevin Enderby)
Date: Thu, 08 Jul 2010 20:30:44 -0000
Subject: [llvm-commits] [llvm] r107906 - in /llvm/trunk:
 include/llvm/MC/MCAsmInfo.h lib/MC/MCAsmInfo.cpp lib/MC/MCAsmInfoDarwin.cpp
Message-ID: <20100708203044.F3CA92A6C12C@llvm.org>

Author: enderby
Date: Thu Jul  8 15:30:44 2010
New Revision: 107906

URL: http://llvm.org/viewvc/llvm-project?rev=107906&view=rev
Log:
Revert some unneeded parts of the change in r107886 for the
.weak_def_can_be_hidden directive.  Chris pointed out that the MCAsmInfo.h/.cpp
chunks aren't needed for this until the compiler starts generating these.  And
when that happens it will be more convenient for it to be a bool than a const
char*.

Modified:
    llvm/trunk/include/llvm/MC/MCAsmInfo.h
    llvm/trunk/lib/MC/MCAsmInfo.cpp
    llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp

Modified: llvm/trunk/include/llvm/MC/MCAsmInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAsmInfo.h?rev=107906&r1=107905&r2=107906&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCAsmInfo.h (original)
+++ llvm/trunk/include/llvm/MC/MCAsmInfo.h Thu Jul  8 15:30:44 2010
@@ -217,11 +217,6 @@
     /// global as being a weak defined symbol.
     const char *WeakDefDirective;            // Defaults to NULL.
 
-    /// WeakDefAutoPrivateDirective - This directive, if non-null, is used to
-    /// declare a global as being a weak defined symbol that is automatically
-    /// made private by the static linker.
-    const char *WeakDefAutoPrivateDirective; // Defaults to NULL.
-
     /// LinkOnceDirective - This directive, if non-null is used to declare a
     /// global as being a weak defined symbol.  This is used on cygwin/mingw.
     const char *LinkOnceDirective;           // Defaults to NULL.
@@ -392,9 +387,6 @@
     bool hasNoDeadStrip() const { return HasNoDeadStrip; }
     const char *getWeakRefDirective() const { return WeakRefDirective; }
     const char *getWeakDefDirective() const { return WeakDefDirective; }
-    const char *getWeakDefAutoPrivateDirective() const {
-      return WeakDefAutoPrivateDirective;
-    }
     const char *getLinkOnceDirective() const { return LinkOnceDirective; }
     
     MCSymbolAttr getHiddenVisibilityAttr() const { return HiddenVisibilityAttr;}

Modified: llvm/trunk/lib/MC/MCAsmInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmInfo.cpp?rev=107906&r1=107905&r2=107906&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAsmInfo.cpp (original)
+++ llvm/trunk/lib/MC/MCAsmInfo.cpp Thu Jul  8 15:30:44 2010
@@ -59,7 +59,6 @@
   HasNoDeadStrip = false;
   WeakRefDirective = 0;
   WeakDefDirective = 0;
-  WeakDefAutoPrivateDirective = 0;
   LinkOnceDirective = 0;
   HiddenVisibilityAttr = MCSA_Hidden;
   ProtectedVisibilityAttr = MCSA_Protected;

Modified: llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp?rev=107906&r1=107905&r2=107906&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp (original)
+++ llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp Thu Jul  8 15:30:44 2010
@@ -33,7 +33,6 @@
   // Directives:
   WeakDefDirective = "\t.weak_definition ";
   WeakRefDirective = "\t.weak_reference ";
-  WeakDefAutoPrivateDirective = "\t.weak_def_can_be_hidden ";
   ZeroDirective = "\t.space\t";  // ".space N" emits N zeros.
   HasMachoZeroFillDirective = true;  // Uses .zerofill
   HasMachoTBSSDirective = true; // Uses .tbss




From stuart at apple.com  Thu Jul  8 15:31:05 2010
From: stuart at apple.com (Stuart Hastings)
Date: Thu, 08 Jul 2010 20:31:05 -0000
Subject: [llvm-commits] [llvm] r107907 -
	/llvm/trunk/test/FrontendC/2010-07-08-DeclDebugLineNo.c
Message-ID: <20100708203105.D51052A6C12C@llvm.org>

Author: stuart
Date: Thu Jul  8 15:31:05 2010
New Revision: 107907

URL: http://llvm.org/viewvc/llvm-project?rev=107907&view=rev
Log:
Test case for r107843.  Radar 8152866.

Added:
    llvm/trunk/test/FrontendC/2010-07-08-DeclDebugLineNo.c

Added: llvm/trunk/test/FrontendC/2010-07-08-DeclDebugLineNo.c
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/2010-07-08-DeclDebugLineNo.c?rev=107907&view=auto
==============================================================================
--- llvm/trunk/test/FrontendC/2010-07-08-DeclDebugLineNo.c (added)
+++ llvm/trunk/test/FrontendC/2010-07-08-DeclDebugLineNo.c Thu Jul  8 15:31:05 2010
@@ -0,0 +1,10 @@
+// RUN: %llvmgcc -S -O0 -g %s -o - | FileCheck %s
+// Insure that dbg.declare lines for locals refer to correct line number records.
+// Radar 8152866.
+void foo() {
+  int l = 0;    // line #4: CHECK: {{call.*llvm.dbg.declare.*%l.*\!dbg }}[[variable_l:![0-9]+]]
+  int p = 0;    // line #5: CHECK: {{call.*llvm.dbg.declare.*%p.*\!dbg }}[[variable_p:![0-9]+]]
+}
+// Now match the line number records:
+// CHECK: {{^}}[[variable_l]]{{ = metadata ![{]i32 5,}}
+// CHECK: {{^}}[[variable_p]]{{ = metadata ![{]i32 6,}}




From kalle.raiskila at nokia.com  Thu Jul  8 16:15:22 2010
From: kalle.raiskila at nokia.com (Kalle Raiskila)
Date: Thu, 08 Jul 2010 21:15:22 -0000
Subject: [llvm-commits] [llvm] r107913 - in /llvm/trunk/lib/Target/CellSPU:
 SPUCallingConv.td SPUISelLowering.cpp SPURegisterInfo.cpp SPURegisterInfo.h
Message-ID: <20100708211522.D721C2A6C12C@llvm.org>

Author: kraiskil
Date: Thu Jul  8 16:15:22 2010
New Revision: 107913

URL: http://llvm.org/viewvc/llvm-project?rev=107913&view=rev
Log:
Switch SPU calling convention (function arguments) 
to a Tablegen implementation.

Modified:
    llvm/trunk/lib/Target/CellSPU/SPUCallingConv.td
    llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
    llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp
    llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h

Modified: llvm/trunk/lib/Target/CellSPU/SPUCallingConv.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUCallingConv.td?rev=107913&r1=107912&r2=107913&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUCallingConv.td (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUCallingConv.td Thu Jul  8 16:15:22 2010
@@ -34,76 +34,19 @@
 
 //===----------------------------------------------------------------------===//
 // CellSPU Argument Calling Conventions
-// (note: this isn't used, but presumably should be at some point when other
-//  targets do.)
 //===----------------------------------------------------------------------===//
-/*
-def CC_SPU : CallingConv<[
-  CCIfType<[i8],  CCAssignToReg<[R3,   R4,  R5,  R6,  R7,  R8,  R9, R10, R11,
-                                 R12, R13, R14, R15, R16, R17, R18, R19, R20,
-                                 R21, R22, R23, R24, R25, R26, R27, R28, R29,
-                                 R30, R31, R32, R33, R34, R35, R36, R37, R38,
-                                 R39, R40, R41, R42, R43, R44, R45, R46, R47,
-                                 R48, R49, R50, R51, R52, R53, R54, R55, R56,
-                                 R57, R58, R59, R60, R61, R62, R63, R64, R65,
-                                 R66, R67, R68, R69, R70, R71, R72, R73, R74,
-                                 R75, R76, R77, R78, R79]>>,
-  CCIfType<[i16], CCAssignToReg<[R3,   R4,  R5,  R6,  R7,  R8,  R9, R10, R11,
-                                 R12, R13, R14, R15, R16, R17, R18, R19, R20,
-                                 R21, R22, R23, R24, R25, R26, R27, R28, R29,
-                                 R30, R31, R32, R33, R34, R35, R36, R37, R38,
-                                 R39, R40, R41, R42, R43, R44, R45, R46, R47,
-                                 R48, R49, R50, R51, R52, R53, R54, R55, R56,
-                                 R57, R58, R59, R60, R61, R62, R63, R64, R65,
-                                 R66, R67, R68, R69, R70, R71, R72, R73, R74,
-                                 R75, R76, R77, R78, R79]>>,
-  CCIfType<[i32], CCAssignToReg<[R3,   R4,  R5,  R6,  R7,  R8,  R9, R10, R11,
-                                 R12, R13, R14, R15, R16, R17, R18, R19, R20,
-                                 R21, R22, R23, R24, R25, R26, R27, R28, R29,
-                                 R30, R31, R32, R33, R34, R35, R36, R37, R38,
-                                 R39, R40, R41, R42, R43, R44, R45, R46, R47,
-                                 R48, R49, R50, R51, R52, R53, R54, R55, R56,
-                                 R57, R58, R59, R60, R61, R62, R63, R64, R65,
-                                 R66, R67, R68, R69, R70, R71, R72, R73, R74,
-                                 R75, R76, R77, R78, R79]>>,
-  CCIfType<[f32], CCAssignToReg<[R3,   R4,  R5,  R6,  R7,  R8,  R9, R10, R11,
-                                 R12, R13, R14, R15, R16, R17, R18, R19, R20,
-                                 R21, R22, R23, R24, R25, R26, R27, R28, R29,
-                                 R30, R31, R32, R33, R34, R35, R36, R37, R38,
-                                 R39, R40, R41, R42, R43, R44, R45, R46, R47,
-                                 R48, R49, R50, R51, R52, R53, R54, R55, R56,
-                                 R57, R58, R59, R60, R61, R62, R63, R64, R65,
-                                 R66, R67, R68, R69, R70, R71, R72, R73, R74,
-                                 R75, R76, R77, R78, R79]>>,
-  CCIfType<[i64], CCAssignToReg<[R3,   R4,  R5,  R6,  R7,  R8,  R9, R10, R11,
-                                 R12, R13, R14, R15, R16, R17, R18, R19, R20,
-                                 R21, R22, R23, R24, R25, R26, R27, R28, R29,
-                                 R30, R31, R32, R33, R34, R35, R36, R37, R38,
-                                 R39, R40, R41, R42, R43, R44, R45, R46, R47,
-                                 R48, R49, R50, R51, R52, R53, R54, R55, R56,
-                                 R57, R58, R59, R60, R61, R62, R63, R64, R65,
-                                 R66, R67, R68, R69, R70, R71, R72, R73, R74,
-                                 R75, R76, R77, R78, R79]>>,
-  CCIfType<[f64], CCAssignToReg<[R3,   R4,  R5,  R6,  R7,  R8,  R9, R10, R11,
-                                 R12, R13, R14, R15, R16, R17, R18, R19, R20,
-                                 R21, R22, R23, R24, R25, R26, R27, R28, R29,
-                                 R30, R31, R32, R33, R34, R35, R36, R37, R38,
-                                 R39, R40, R41, R42, R43, R44, R45, R46, R47,
-                                 R48, R49, R50, R51, R52, R53, R54, R55, R56,
-                                 R57, R58, R59, R60, R61, R62, R63, R64, R65,
-                                 R66, R67, R68, R69, R70, R71, R72, R73, R74,
-                                 R75, R76, R77, R78, R79]>>,
-  CCIfType<[v16i8, v8i16, v4i32, v4f32, v2i64, v2f64],
-                  CCAssignToReg<[R3,   R4,  R5,  R6,  R7,  R8,  R9, R10, R11,
-                                 R12, R13, R14, R15, R16, R17, R18, R19, R20,
-                                 R21, R22, R23, R24, R25, R26, R27, R28, R29,
-                                 R30, R31, R32, R33, R34, R35, R36, R37, R38,
-                                 R39, R40, R41, R42, R43, R44, R45, R46, R47,
-                                 R48, R49, R50, R51, R52, R53, R54, R55, R56,
-                                 R57, R58, R59, R60, R61, R62, R63, R64, R65,
-                                 R66, R67, R68, R69, R70, R71, R72, R73, R74,
-                                 R75, R76, R77, R78, R79]>>,
-  
+def CCC_SPU : CallingConv<[
+  CCIfType<[i8, i16, i32, i64, i128, f32, f64, 
+            v16i8, v8i16, v4i32, v4f32, v2i64, v2f64],
+            CCAssignToReg<[R3,   R4,  R5,  R6,  R7,  R8,  R9, R10, R11,
+                           R12, R13, R14, R15, R16, R17, R18, R19, R20,
+                           R21, R22, R23, R24, R25, R26, R27, R28, R29,
+                           R30, R31, R32, R33, R34, R35, R36, R37, R38,
+                           R39, R40, R41, R42, R43, R44, R45, R46, R47,
+                           R48, R49, R50, R51, R52, R53, R54, R55, R56,
+                           R57, R58, R59, R60, R61, R62, R63, R64, R65,
+                           R66, R67, R68, R69, R70, R71, R72, R73, R74,
+                           R75, R76, R77, R78, R79]>>,
   // Integer/FP values get stored in stack slots that are 8 bytes in size and
   // 8-byte aligned if there are no more registers to hold them.
   CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
@@ -112,4 +55,3 @@
   CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
               CCAssignToStack<16, 16>>
 ]>;
-*/

Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=107913&r1=107912&r2=107913&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Thu Jul  8 16:15:22 2010
@@ -1014,22 +1014,26 @@
   MachineRegisterInfo &RegInfo = MF.getRegInfo();
   SPUFunctionInfo *FuncInfo = MF.getInfo();
 
-  const unsigned *ArgRegs = SPURegisterInfo::getArgRegs();
-  const unsigned NumArgRegs = SPURegisterInfo::getNumArgRegs();
-
   unsigned ArgOffset = SPUFrameInfo::minStackSize();
   unsigned ArgRegIdx = 0;
   unsigned StackSlotSize = SPUFrameInfo::stackSlotSize();
 
   EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
 
+  SmallVector ArgLocs;
+  CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
+                 *DAG.getContext());
+  // FIXME: allow for other calling conventions
+  CCInfo.AnalyzeFormalArguments(Ins, CCC_SPU);
+
   // Add DAG nodes to load the arguments or copy them out of registers.
   for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
     EVT ObjectVT = Ins[ArgNo].VT;
     unsigned ObjSize = ObjectVT.getSizeInBits()/8;
     SDValue ArgVal;
+    CCValAssign &VA = ArgLocs[ArgNo];
 
-    if (ArgRegIdx < NumArgRegs) {
+    if (VA.isRegLoc()) {
       const TargetRegisterClass *ArgRegClass;
 
       switch (ObjectVT.getSimpleVT().SimpleTy) {
@@ -1068,7 +1072,7 @@
       }
 
       unsigned VReg = RegInfo.createVirtualRegister(ArgRegClass);
-      RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg);
+      RegInfo.addLiveIn(VA.getLocReg(), VReg);
       ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
       ++ArgRegIdx;
     } else {
@@ -1088,12 +1092,28 @@
 
   // vararg handling:
   if (isVarArg) {
-    // unsigned int ptr_size = PtrVT.getSizeInBits() / 8;
+    // FIXME: we should be able to query the argument registers from 
+    //        tablegen generated code. 
+    static const unsigned ArgRegs[] = {
+      SPU::R3,  SPU::R4,  SPU::R5,  SPU::R6,  SPU::R7,  SPU::R8,  SPU::R9,
+      SPU::R10, SPU::R11, SPU::R12, SPU::R13, SPU::R14, SPU::R15, SPU::R16,
+      SPU::R17, SPU::R18, SPU::R19, SPU::R20, SPU::R21, SPU::R22, SPU::R23,
+      SPU::R24, SPU::R25, SPU::R26, SPU::R27, SPU::R28, SPU::R29, SPU::R30,
+      SPU::R31, SPU::R32, SPU::R33, SPU::R34, SPU::R35, SPU::R36, SPU::R37,
+      SPU::R38, SPU::R39, SPU::R40, SPU::R41, SPU::R42, SPU::R43, SPU::R44,
+      SPU::R45, SPU::R46, SPU::R47, SPU::R48, SPU::R49, SPU::R50, SPU::R51,
+      SPU::R52, SPU::R53, SPU::R54, SPU::R55, SPU::R56, SPU::R57, SPU::R58,
+      SPU::R59, SPU::R60, SPU::R61, SPU::R62, SPU::R63, SPU::R64, SPU::R65,
+      SPU::R66, SPU::R67, SPU::R68, SPU::R69, SPU::R70, SPU::R71, SPU::R72,
+      SPU::R73, SPU::R74, SPU::R75, SPU::R76, SPU::R77, SPU::R78, SPU::R79
+    };
+    // size of ArgRegs array
+    unsigned NumArgRegs = 77;
+
     // We will spill (79-3)+1 registers to the stack
     SmallVector MemOps;
 
     // Create the frame slot
-
     for (; ArgRegIdx != NumArgRegs; ++ArgRegIdx) {
       FuncInfo->setVarArgsFrameIndex(
         MFI->CreateFixedObject(StackSlotSize, ArgOffset, true));
@@ -1145,8 +1165,15 @@
   const SPUSubtarget *ST = SPUTM.getSubtargetImpl();
   unsigned NumOps     = Outs.size();
   unsigned StackSlotSize = SPUFrameInfo::stackSlotSize();
-  const unsigned *ArgRegs = SPURegisterInfo::getArgRegs();
-  const unsigned NumArgRegs = SPURegisterInfo::getNumArgRegs();
+
+  SmallVector ArgLocs;
+  CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
+                 *DAG.getContext()); 
+  // FIXME: allow for other calling conventions
+  CCInfo.AnalyzeCallOperands(Outs, CCC_SPU);
+  
+  const unsigned NumArgRegs = ArgLocs.size();
+
 
   // Handy pointer type
   EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
@@ -1166,8 +1193,9 @@
   // And the arguments passed on the stack
   SmallVector MemOpChains;
 
-  for (unsigned i = 0; i != NumOps; ++i) {
-    SDValue Arg = OutVals[i];
+  for (; ArgRegIdx != NumOps; ++ArgRegIdx) {
+    SDValue Arg = OutVals[ArgRegIdx];
+    CCValAssign &VA = ArgLocs[ArgRegIdx];
 
     // PtrOff will be used to store the current argument to the stack if a
     // register cannot be found for it.
@@ -1190,7 +1218,7 @@
     case MVT::v8i16:
     case MVT::v16i8:
       if (ArgRegIdx != NumArgRegs) {
-        RegsToPass.push_back(std::make_pair(ArgRegs[ArgRegIdx++], Arg));
+        RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
       } else {
         MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0,
                                            false, false, 0));

Modified: llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp?rev=107913&r1=107912&r2=107913&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp Thu Jul  8 16:15:22 2010
@@ -191,33 +191,6 @@
 {
 }
 
-// SPU's 128-bit registers used for argument passing:
-static const unsigned SPU_ArgRegs[] = {
-  SPU::R3,  SPU::R4,  SPU::R5,  SPU::R6,  SPU::R7,  SPU::R8,  SPU::R9,
-  SPU::R10, SPU::R11, SPU::R12, SPU::R13, SPU::R14, SPU::R15, SPU::R16,
-  SPU::R17, SPU::R18, SPU::R19, SPU::R20, SPU::R21, SPU::R22, SPU::R23,
-  SPU::R24, SPU::R25, SPU::R26, SPU::R27, SPU::R28, SPU::R29, SPU::R30,
-  SPU::R31, SPU::R32, SPU::R33, SPU::R34, SPU::R35, SPU::R36, SPU::R37,
-  SPU::R38, SPU::R39, SPU::R40, SPU::R41, SPU::R42, SPU::R43, SPU::R44,
-  SPU::R45, SPU::R46, SPU::R47, SPU::R48, SPU::R49, SPU::R50, SPU::R51,
-  SPU::R52, SPU::R53, SPU::R54, SPU::R55, SPU::R56, SPU::R57, SPU::R58,
-  SPU::R59, SPU::R60, SPU::R61, SPU::R62, SPU::R63, SPU::R64, SPU::R65,
-  SPU::R66, SPU::R67, SPU::R68, SPU::R69, SPU::R70, SPU::R71, SPU::R72,
-  SPU::R73, SPU::R74, SPU::R75, SPU::R76, SPU::R77, SPU::R78, SPU::R79
-};
-
-const unsigned *
-SPURegisterInfo::getArgRegs()
-{
-  return SPU_ArgRegs;
-}
-
-unsigned
-SPURegisterInfo::getNumArgRegs()
-{
-  return sizeof(SPU_ArgRegs) / sizeof(SPU_ArgRegs[0]);
-}
-
 /// getPointerRegClass - Return the register class to use to hold pointers.
 /// This is used for addressing modes.
 const TargetRegisterClass *

Modified: llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h?rev=107913&r1=107912&r2=107913&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h (original)
+++ llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h Thu Jul  8 16:15:22 2010
@@ -86,15 +86,6 @@
     // New methods added:
     //------------------------------------------------------------------------
 
-    //! Return the array of argument passing registers
-    /*!
-      \note The size of this array is returned by getArgRegsSize().
-     */
-    static const unsigned *getArgRegs();
-
-    //! Return the size of the argument passing register array
-    static unsigned getNumArgRegs();
-
     //! Get DWARF debugging register number
     int getDwarfRegNum(unsigned RegNum, bool isEH) const;
 




From sabre at nondot.org  Thu Jul  8 17:27:06 2010
From: sabre at nondot.org (Chris Lattner)
Date: Thu, 08 Jul 2010 22:27:06 -0000
Subject: [llvm-commits] [llvm] r107916 -
	/llvm/trunk/lib/Target/X86/X86InstrInfo.h
Message-ID: <20100708222706.EF9182A6C12C@llvm.org>

Author: lattner
Date: Thu Jul  8 17:27:06 2010
New Revision: 107916

URL: http://llvm.org/viewvc/llvm-project?rev=107916&view=rev
Log:
introduce a new X86II::getMemoryOperandNo method, which
returns the start of the memory operand for an instruction.

Introduce a new "X86AddrSegment" enum to reduce # magic numbers
referring to X86 memory operand layout.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrInfo.h

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=107916&r1=107915&r2=107916&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Thu Jul  8 17:27:06 2010
@@ -473,21 +473,80 @@
   /// TSFlags indicates that it is pc relative.
   static inline unsigned isImmPCRel(uint64_t TSFlags) {
     switch (TSFlags & X86II::ImmMask) {
-      default: assert(0 && "Unknown immediate size");
-      case X86II::Imm8PCRel:
-      case X86II::Imm16PCRel:
-      case X86II::Imm32PCRel:
-        return true;
-      case X86II::Imm8:
-      case X86II::Imm16:
-      case X86II::Imm32:
-      case X86II::Imm64:
-        return false;
+    default: assert(0 && "Unknown immediate size");
+    case X86II::Imm8PCRel:
+    case X86II::Imm16PCRel:
+    case X86II::Imm32PCRel:
+      return true;
+    case X86II::Imm8:
+    case X86II::Imm16:
+    case X86II::Imm32:
+    case X86II::Imm64:
+      return false;
     }
-  }    
+  }
+  
+  /// getMemoryOperandNo - The function returns the MCInst operand # for the
+  /// first field of the memory operand.  If the instruction doesn't have a
+  /// memory operand, this returns -1.
+  ///
+  /// Note that this ignores tied operands.  If there is a tied register which
+  /// is duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only
+  /// counted as one operand.
+  ///
+  static inline int getMemoryOperandNo(uint64_t TSFlags) {
+    switch (TSFlags & X86II::FormMask) {
+    case X86II::MRMInitReg:  assert(0 && "FIXME: Remove this form");
+    default: assert(0 && "Unknown FormMask value in getMemoryOperandNo!");
+    case X86II::Pseudo:
+    case X86II::RawFrm:
+    case X86II::AddRegFrm:
+    case X86II::MRMDestReg:
+    case X86II::MRMSrcReg:
+       return -1;
+    case X86II::MRMDestMem:
+      return 0;
+    case X86II::MRMSrcMem: {
+      bool HasVEX_4V = (TSFlags >> 32) & X86II::VEX_4V;
+      unsigned FirstMemOp = 1;
+      if (HasVEX_4V)
+        ++FirstMemOp;// Skip the register source (which is encoded in VEX_VVVV).
+      
+      // FIXME: Maybe lea should have its own form?  This is a horrible hack.
+      //if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
+      //    Opcode == X86::LEA16r || Opcode == X86::LEA32r)
+      return FirstMemOp;
+    }
+    case X86II::MRM0r: case X86II::MRM1r:
+    case X86II::MRM2r: case X86II::MRM3r:
+    case X86II::MRM4r: case X86II::MRM5r:
+    case X86II::MRM6r: case X86II::MRM7r:
+      return -1;
+    case X86II::MRM0m: case X86II::MRM1m:
+    case X86II::MRM2m: case X86II::MRM3m:
+    case X86II::MRM4m: case X86II::MRM5m:
+    case X86II::MRM6m: case X86II::MRM7m:
+      return 0;
+    case X86II::MRM_C1:
+    case X86II::MRM_C2:
+    case X86II::MRM_C3:
+    case X86II::MRM_C4:
+    case X86II::MRM_C8:
+    case X86II::MRM_C9:
+    case X86II::MRM_E8:
+    case X86II::MRM_F0:
+    case X86II::MRM_F8:
+    case X86II::MRM_F9:
+      return -1;
+    }
+  }
 }
 
-const int X86AddrNumOperands = 5;
+// FIXME: Move into X86II namespace.
+enum {
+  X86AddrSegment = 4,
+  X86AddrNumOperands = 5
+};
 
 inline static bool isScale(const MachineOperand &MO) {
   return MO.isImm() &&




From sabre at nondot.org  Thu Jul  8 17:28:12 2010
From: sabre at nondot.org (Chris Lattner)
Date: Thu, 08 Jul 2010 22:28:12 -0000
Subject: [llvm-commits] [llvm] r107917 - in /llvm/trunk:
 lib/Target/X86/X86MCCodeEmitter.cpp test/MC/AsmParser/X86/x86_64-encoding.s
Message-ID: <20100708222812.848692A6C12C@llvm.org>

Author: lattner
Date: Thu Jul  8 17:28:12 2010
New Revision: 107917

URL: http://llvm.org/viewvc/llvm-project?rev=107917&view=rev
Log:
Rework segment prefix emission code to handle segments
in memory operands at the same type as hard coded segments.
This fixes problems where we'd emit the segment override after
the REX prefix on instructions like:
mov %gs:(%rdi), %rax

This fixes rdar://8127102.  I have several cleanup patches coming
next.

Modified:
    llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp
    llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s

Modified: llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp?rev=107917&r1=107916&r2=107917&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp Thu Jul  8 17:28:12 2010
@@ -121,9 +121,6 @@
   }
   
   
-  void EmitSegmentOverridePrefix(const MCOperand &Op, unsigned TSFlags,
-                                 unsigned &CurByte, raw_ostream &OS) const;
-
   void EmitMemModRMByte(const MCInst &MI, unsigned Op,
                         unsigned RegOpcodeField, 
                         uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS,
@@ -136,7 +133,7 @@
                            const MCInst &MI, const TargetInstrDesc &Desc,
                            raw_ostream &OS) const;
 
-  void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
+  void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
                         const MCInst &MI, const TargetInstrDesc &Desc,
                         raw_ostream &OS) const;
 };
@@ -214,27 +211,6 @@
   EmitConstant(0, Size, CurByte, OS);
 }
 
-void X86MCCodeEmitter::EmitSegmentOverridePrefix(const MCOperand &Op,
-                                                 unsigned TSFlags,
-                                                 unsigned &CurByte,
-                                                 raw_ostream &OS) const {
-  // If no segment register is present, we don't need anything.
-  if (Op.getReg() == 0)
-    return;
-
-  // Check if we need an override.
-  switch (Op.getReg()) {
-  case X86::CS: EmitByte(0x2E, CurByte, OS); return;
-  case X86::SS: EmitByte(0x36, CurByte, OS); return;
-  case X86::DS: EmitByte(0x3E, CurByte, OS); return;
-  case X86::ES: EmitByte(0x26, CurByte, OS); return;
-  case X86::FS: EmitByte(0x64, CurByte, OS); return;
-  case X86::GS: EmitByte(0x65, CurByte, OS); return;
-  }
-
-  assert(0 && "Invalid segment register!");
-}
-
 void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
                                         unsigned RegOpcodeField,
                                         uint64_t TSFlags, unsigned &CurByte,
@@ -662,8 +638,11 @@
 }
 
 /// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode.
+///
+/// MemOperand is the operand # of the start of a memory operand if present.  If
+/// Not present, it is -1.
 void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
-                                        const MCInst &MI, 
+                                        int MemOperand, const MCInst &MI, 
                                         const TargetInstrDesc &Desc,
                                         raw_ostream &OS) const {
 
@@ -674,7 +653,24 @@
   // Emit segment override opcode prefix as needed.
   switch (TSFlags & X86II::SegOvrMask) {
   default: assert(0 && "Invalid segment!");
-  case 0: break;  // No segment override!
+  case 0:
+    // No segment override, check for explicit one on memory operand.
+    if (MemOperand != -1 &&   // If the instruction has a memory operand.
+        // FIXME: This is disgusting.
+        MI.getOpcode() != X86::LEA64r && MI.getOpcode() != X86::LEA64_32r &&
+        MI.getOpcode() != X86::LEA16r && MI.getOpcode() != X86::LEA32r) {
+      switch (MI.getOperand(MemOperand+X86AddrSegment).getReg()) {
+      default: assert(0 && "Unknown segment register!");
+      case 0: break;
+      case X86::CS: EmitByte(0x2E, CurByte, OS); break;
+      case X86::SS: EmitByte(0x36, CurByte, OS); break;
+      case X86::DS: EmitByte(0x3E, CurByte, OS); break;
+      case X86::ES: EmitByte(0x26, CurByte, OS); break;
+      case X86::FS: EmitByte(0x64, CurByte, OS); break;
+      case X86::GS: EmitByte(0x65, CurByte, OS); break;
+      }
+    }
+    break;
   case X86II::FS:
     EmitByte(0x64, CurByte, OS);
     break;
@@ -757,6 +753,17 @@
   const TargetInstrDesc &Desc = TII.get(Opcode);
   uint64_t TSFlags = Desc.TSFlags;
 
+  
+  // If this is a two-address instruction, skip one of the register operands.
+  // FIXME: This should be handled during MCInst lowering.
+  unsigned NumOps = Desc.getNumOperands();
+  unsigned CurOp = 0;
+  if (NumOps > 1 && Desc.getOperandConstraint(1, TOI::TIED_TO) != -1)
+    ++CurOp;
+  else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
+    // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
+    --NumOps;
+  
   // Keep track of the current byte being emitted.
   unsigned CurByte = 0;
   
@@ -770,24 +777,17 @@
     HasVEXPrefix = true;
   if ((TSFlags >> 32) & X86II::VEX_4V)
     HasVEX_4V = true;
-
-  // FIXME: We should emit the prefixes in exactly the same order as GAS does,
-  // in order to provide diffability.
-
+  
+  // Determine where the memory operand starts, if present.
+  int MemoryOperand = X86II::getMemoryOperandNo(TSFlags);
+  if (MemoryOperand != -1) MemoryOperand += CurOp;
+  
   if (!HasVEXPrefix)
-    EmitOpcodePrefix(TSFlags, CurByte, MI, Desc, OS);
+    EmitOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
   else
+    // FIXME: Segment overrides??
     EmitVEXOpcodePrefix(TSFlags, CurByte, MI, Desc, OS);
   
-  // If this is a two-address instruction, skip one of the register operands.
-  unsigned NumOps = Desc.getNumOperands();
-  unsigned CurOp = 0;
-  if (NumOps > 1 && Desc.getOperandConstraint(1, TOI::TIED_TO) != -1)
-    ++CurOp;
-  else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
-    // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
-    --NumOps;
-  
   unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
   unsigned SrcRegNum = 0;
   switch (TSFlags & X86II::FormMask) {
@@ -812,7 +812,6 @@
     break;
   
   case