From echristo at apple.com Mon Jul 12 00:13:36 2010 From: echristo at apple.com (Eric Christopher) Date: Mon, 12 Jul 2010 05:13:36 -0000 Subject: [llvm-commits] [llvm] r108126 - in /llvm/trunk/include/llvm-c: Target.h lto.h Message-ID: <20100712051336.121762A6C12C@llvm.org> Author: echristo Date: Mon Jul 12 00:13:35 2010 New Revision: 108126 URL: http://llvm.org/viewvc/llvm-project?rev=108126&view=rev Log: 80 columns. Modified: llvm/trunk/include/llvm-c/Target.h llvm/trunk/include/llvm-c/lto.h Modified: llvm/trunk/include/llvm-c/Target.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm-c/Target.h?rev=108126&r1=108125&r2=108126&view=diff ============================================================================== --- llvm/trunk/include/llvm-c/Target.h (original) +++ llvm/trunk/include/llvm-c/Target.h Mon Jul 12 00:13:35 2010 @@ -32,7 +32,8 @@ typedef struct LLVMStructLayout *LLVMStructLayoutRef; /* Declare all of the target-initialization functions that are available. */ -#define LLVM_TARGET(TargetName) void LLVMInitialize##TargetName##TargetInfo(void); +#define LLVM_TARGET(TargetName) \ + void LLVMInitialize##TargetName##TargetInfo(void); #include "llvm/Config/Targets.def" #undef LLVM_TARGET /* Explicit undef to make SWIG happier */ Modified: llvm/trunk/include/llvm-c/lto.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm-c/lto.h?rev=108126&r1=108125&r2=108126&view=diff ============================================================================== --- llvm/trunk/include/llvm-c/lto.h (original) +++ llvm/trunk/include/llvm-c/lto.h Mon Jul 12 00:13:35 2010 @@ -102,7 +102,7 @@ */ extern bool lto_module_is_object_file_in_memory_for_target(const void* mem, size_t length, - const char* target_triple_prefix); + const char* target_triple_prefix); /** From echristo at apple.com Mon Jul 12 00:26:37 2010 From: echristo at apple.com (Eric Christopher) Date: Mon, 12 Jul 2010 05:26:37 -0000 Subject: [llvm-commits] [llvm] r108127 - in /llvm/trunk/include/llvm: Analysis/CFGPrinter.h Support/raw_ostream.h Message-ID: <20100712052637.A3F602A6C12C@llvm.org> Author: echristo Date: Mon Jul 12 00:26:37 2010 New Revision: 108127 URL: http://llvm.org/viewvc/llvm-project?rev=108127&view=rev Log: Remove tab characters and 80-col. Modified: llvm/trunk/include/llvm/Analysis/CFGPrinter.h llvm/trunk/include/llvm/Support/raw_ostream.h Modified: llvm/trunk/include/llvm/Analysis/CFGPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/CFGPrinter.h?rev=108127&r1=108126&r2=108127&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/CFGPrinter.h (original) +++ llvm/trunk/include/llvm/Analysis/CFGPrinter.h Mon Jul 12 00:26:37 2010 @@ -1,4 +1,4 @@ -//===-- CFGPrinter.h - CFG printer external interface ------------*- C++ -*-===// +//===-- CFGPrinter.h - CFG printer external interface -----------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -43,8 +43,8 @@ return OS.str(); } - static std::string getCompleteNodeLabel(const BasicBlock *Node, - const Function *Graph) { + static std::string getCompleteNodeLabel(const BasicBlock *Node, + const Function *Graph) { std::string Str; raw_string_ostream OS(Str); Modified: llvm/trunk/include/llvm/Support/raw_ostream.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/raw_ostream.h?rev=108127&r1=108126&r2=108127&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/raw_ostream.h (original) +++ llvm/trunk/include/llvm/Support/raw_ostream.h Mon Jul 12 00:26:37 2010 @@ -234,8 +234,8 @@ /// @param bold bold/brighter text, default false /// @param bg if true change the background, default: change foreground /// @returns itself so it can be used within << invocations - virtual raw_ostream &changeColor(enum Colors, bool = false, - bool = false) { return *this; } + virtual raw_ostream &changeColor(enum Colors, bool = false, bool = false) { + return *this; } /// Resets the colors to terminal defaults. Call this when you are done /// outputting colored text, or before program exit. From chandlerc at google.com Mon Jul 12 01:31:04 2010 From: chandlerc at google.com (Chandler Carruth) Date: Sun, 11 Jul 2010 23:31:04 -0700 Subject: [llvm-commits] [llvm] r108113 - in /llvm/trunk: lib/Analysis/ConstantFolding.cpp test/Transforms/InstCombine/load3.ll In-Reply-To: <20100712002251.D3AE92A6C12C@llvm.org> References: <20100712002251.D3AE92A6C12C@llvm.org> Message-ID: On Sun, Jul 11, 2010 at 5:22 PM, Chris Lattner wrote: > Author: lattner > Date: Sun Jul 11 19:22:51 2010 > New Revision: 108113 > > URL: http://llvm.org/viewvc/llvm-project?rev=108113&view=rev > Log: > fix PR7429, a crash turning a load from a string into a float. > > Modified: > ? ?llvm/trunk/lib/Analysis/ConstantFolding.cpp > ? ?llvm/trunk/test/Transforms/InstCombine/load3.ll > > Modified: llvm/trunk/lib/Analysis/ConstantFolding.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ConstantFolding.cpp?rev=108113&r1=108112&r2=108113&view=diff > ============================================================================== > --- llvm/trunk/lib/Analysis/ConstantFolding.cpp (original) > +++ llvm/trunk/lib/Analysis/ConstantFolding.cpp Sun Jul 11 19:22:51 2010 > @@ -436,8 +436,10 @@ > ? ? unsigned StrLen = Str.length(); > ? ? const Type *Ty = cast(CE->getType())->getElementType(); > ? ? unsigned NumBits = Ty->getPrimitiveSizeInBits(); > - ? ?// Replace LI with immediate integer store. > - ? ?if ((NumBits >> 3) == StrLen + 1) { > + ? ?// Replace load with immediate integer if the result is an integer or fp > + ? ?// value. > + ? ?if ((NumBits >> 3) == StrLen + 1 && (NumBits & 7) == 0 && > + ? ? ? ?isa(Ty) || Ty->isFloatingPointTy()) { GCC warns about the && and || operators being used w/o parentheses. Sometimes, this is just pedantic, but did you mean to have ()s around the 'isa(Ty) || Ty->isFloatingPointTy()' here? As it stands, won't an fp value bypass the checks on NumBits? > ? ? ? APInt StrVal(NumBits, 0); > ? ? ? APInt SingleChar(NumBits, 0); > ? ? ? if (TD->isLittleEndian()) { > @@ -454,7 +456,11 @@ > ? ? ? ? SingleChar = 0; > ? ? ? ? StrVal = (StrVal << 8) | SingleChar; > ? ? ? } > - ? ? ?return ConstantInt::get(CE->getContext(), StrVal); > + > + ? ? ?Constant *Res = ConstantInt::get(CE->getContext(), StrVal); > + ? ? ?if (Ty->isFloatingPointTy()) > + ? ? ? ?Res = ConstantExpr::getBitCast(Res, Ty); > + ? ? ?return Res; > ? ? } > ? } > > > Modified: llvm/trunk/test/Transforms/InstCombine/load3.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/load3.ll?rev=108113&r1=108112&r2=108113&view=diff > ============================================================================== > --- llvm/trunk/test/Transforms/InstCombine/load3.ll (original) > +++ llvm/trunk/test/Transforms/InstCombine/load3.ll Sun Jul 11 19:22:51 2010 > @@ -1,4 +1,6 @@ > ?; RUN: opt < %s -instcombine -S | FileCheck %s > +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" > +target triple = "x86_64-apple-darwin10.0.0" > > ?; Instcombine should be able to do trivial CSE of loads. > > @@ -12,3 +14,14 @@ > ?; CHECK: @test1 > ?; CHECK: ret i32 0 > ?} > + > + > +; PR7429 > + at .str = private constant [4 x i8] c"XYZ\00" > +define float @test2() { > + ?%tmp = load float* bitcast ([4 x i8]* @.str to float*), align 1 > + ?ret float %tmp > + > +; CHECK: @test2 > +; CHECK: ret float 0x3806965600000000 > +} > \ No newline at end of file > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From chandlerc at gmail.com Mon Jul 12 01:47:05 2010 From: chandlerc at gmail.com (Chandler Carruth) Date: Mon, 12 Jul 2010 06:47:05 -0000 Subject: [llvm-commits] [llvm] r108129 - /llvm/trunk/lib/Analysis/ConstantFolding.cpp Message-ID: <20100712064705.47BF52A6C12C@llvm.org> Author: chandlerc Date: Mon Jul 12 01:47:05 2010 New Revision: 108129 URL: http://llvm.org/viewvc/llvm-project?rev=108129&view=rev Log: Add parentheses around an || to correct the logic. Also silences a GCC warning that was actually useful here. Chris, please double check that this is the correct interpretation. I was pretty sure, and ran it by Nick as well. Modified: llvm/trunk/lib/Analysis/ConstantFolding.cpp Modified: llvm/trunk/lib/Analysis/ConstantFolding.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ConstantFolding.cpp?rev=108129&r1=108128&r2=108129&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ConstantFolding.cpp (original) +++ llvm/trunk/lib/Analysis/ConstantFolding.cpp Mon Jul 12 01:47:05 2010 @@ -439,7 +439,7 @@ // Replace load with immediate integer if the result is an integer or fp // value. if ((NumBits >> 3) == StrLen + 1 && (NumBits & 7) == 0 && - isa(Ty) || Ty->isFloatingPointTy()) { + (isa(Ty) || Ty->isFloatingPointTy())) { APInt StrVal(NumBits, 0); APInt SingleChar(NumBits, 0); if (TD->isLittleEndian()) { From chandlerc at google.com Mon Jul 12 01:49:11 2010 From: chandlerc at google.com (Chandler Carruth) Date: Sun, 11 Jul 2010 23:49:11 -0700 Subject: [llvm-commits] [llvm] r108113 - in /llvm/trunk: lib/Analysis/ConstantFolding.cpp test/Transforms/InstCombine/load3.ll In-Reply-To: References: <20100712002251.D3AE92A6C12C@llvm.org> Message-ID: On Sun, Jul 11, 2010 at 11:31 PM, Chandler Carruth wrote: > On Sun, Jul 11, 2010 at 5:22 PM, Chris Lattner wrote: >> Author: lattner >> Date: Sun Jul 11 19:22:51 2010 >> New Revision: 108113 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=108113&view=rev >> Log: >> fix PR7429, a crash turning a load from a string into a float. >> >> Modified: >> ? ?llvm/trunk/lib/Analysis/ConstantFolding.cpp >> ? ?llvm/trunk/test/Transforms/InstCombine/load3.ll >> >> Modified: llvm/trunk/lib/Analysis/ConstantFolding.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ConstantFolding.cpp?rev=108113&r1=108112&r2=108113&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Analysis/ConstantFolding.cpp (original) >> +++ llvm/trunk/lib/Analysis/ConstantFolding.cpp Sun Jul 11 19:22:51 2010 >> @@ -436,8 +436,10 @@ >> ? ? unsigned StrLen = Str.length(); >> ? ? const Type *Ty = cast(CE->getType())->getElementType(); >> ? ? unsigned NumBits = Ty->getPrimitiveSizeInBits(); >> - ? ?// Replace LI with immediate integer store. >> - ? ?if ((NumBits >> 3) == StrLen + 1) { >> + ? ?// Replace load with immediate integer if the result is an integer or fp >> + ? ?// value. >> + ? ?if ((NumBits >> 3) == StrLen + 1 && (NumBits & 7) == 0 && >> + ? ? ? ?isa(Ty) || Ty->isFloatingPointTy()) { > > GCC warns about the && and || operators being used w/o parentheses. > Sometimes, this is just pedantic, but did you mean to have ()s around > the 'isa(Ty) || Ty->isFloatingPointTy()' here? As it > stands, won't an fp value bypass the checks on NumBits? After sanity checking with Nick on IRC, I submitted a patch adding these parens in r 108129. Reading the code made me much more confident that this was just an oversight. Let me know if I broke anything! From evan.cheng at apple.com Mon Jul 12 02:55:26 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 12 Jul 2010 00:55:26 -0700 Subject: [llvm-commits] [patch] Convert uses of getPhysicalRegisterRegClass in VirtRegRewriter.cpp In-Reply-To: References: <5B907AF6-0AA0-4CB2-80C8-0854CE96E8B7@2pi.dk> Message-ID: I don't think it's quite done. I plan to evaluate it in the near future. Using getMinimalPhysRegClass for now is fine. Evan On Jul 11, 2010, at 7:29 PM, Rafael Espindola wrote: >> Using getMinimalPhysRegClass should be correct, but very conservative. >> It is possible that the current register is used only in instructions >> that would accept registers from a larger classes. Unfortunately "make >> check-lit" found no such cases :-( > > Just noticed that this is because there is no test that uses > -break-anti-dependencies=all :-(. Is this being file being used at > all? > > Cheers, > -- > Rafael ?vila de Esp?ndola > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Mon Jul 12 02:57:47 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 12 Jul 2010 00:57:47 -0700 Subject: [llvm-commits] [llvm] r108109 - /llvm/trunk/lib/CodeGen/MachineLICM.cpp In-Reply-To: <20100712000035.393982A6C12C@llvm.org> References: <20100712000035.393982A6C12C@llvm.org> Message-ID: <5470C984-D21B-4C3F-860C-D7506AFBFAAB@apple.com> On Jul 11, 2010, at 5:00 PM, Chris Lattner wrote: > Author: lattner > Date: Sun Jul 11 19:00:35 2010 > New Revision: 108109 > > URL: http://llvm.org/viewvc/llvm-project?rev=108109&view=rev > Log: > change machinelicm to use MachineInstr::isSafeToMove. No > intended functionality change. > > The avoidance of hoistiing implicitdef seems wrong though. It's not. We want to avoid creating implicitdef with no trivial live intervals. The trivial ones will be converted to undef machine operands which do not take up registers. Evan > > Modified: > llvm/trunk/lib/CodeGen/MachineLICM.cpp > > Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineLICM.cpp?rev=108109&r1=108108&r2=108109&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/MachineLICM.cpp (original) > +++ llvm/trunk/lib/CodeGen/MachineLICM.cpp Sun Jul 11 19:00:35 2010 > @@ -127,8 +127,8 @@ > void AddToLiveIns(unsigned Reg); > > /// IsLICMCandidate - Returns true if the instruction may be a suitable > - /// candidate for LICM. e.g. If the instruction is a call, then it's obviously > - /// not safe to hoist it. > + /// candidate for LICM. e.g. If the instruction is a call, then it's > + /// obviously not safe to hoist it. > bool IsLICMCandidate(MachineInstr &I); > > /// IsLoopInvariantInst - Returns true if the instruction is loop > @@ -497,26 +497,16 @@ > /// candidate for LICM. e.g. If the instruction is a call, then it's obviously > /// not safe to hoist it. > bool MachineLICM::IsLICMCandidate(MachineInstr &I) { > + // It is not profitable to hoist implicitdefs. FIXME: Why not? what if they > + // are an argument to some other otherwise-hoistable instruction? > if (I.isImplicitDef()) > return false; > - > - const TargetInstrDesc &TID = I.getDesc(); > > - // Ignore stuff that we obviously can't hoist. > - if (TID.mayStore() || TID.isCall() || TID.isTerminator() || > - TID.hasUnmodeledSideEffects()) > + // Check if it's safe to move the instruction. > + bool DontMoveAcrossStore = true; > + if (!I.isSafeToMove(TII, AA, DontMoveAcrossStore)) > return false; > - > - if (TID.mayLoad()) { > - // Okay, this instruction does a load. As a refinement, we allow the target > - // to decide whether the loaded value is actually a constant. If so, we can > - // actually use it as a load. > - if (!I.isInvariantLoad(AA)) > - // FIXME: we should be able to hoist loads with no other side effects if > - // there are no other instructions which can change memory in this loop. > - // This is a trivial form of alias analysis. > - return false; > - } > + > return true; > } > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Mon Jul 12 03:04:38 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 12 Jul 2010 01:04:38 -0700 Subject: [llvm-commits] [llvm] r108109 - /llvm/trunk/lib/CodeGen/MachineLICM.cpp In-Reply-To: <20100712000035.393982A6C12C@llvm.org> References: <20100712000035.393982A6C12C@llvm.org> Message-ID: On Jul 11, 2010, at 5:00 PM, Chris Lattner wrote: > Author: lattner > Date: Sun Jul 11 19:00:35 2010 > New Revision: 108109 > > URL: http://llvm.org/viewvc/llvm-project?rev=108109&view=rev > Log: > change machinelicm to use MachineInstr::isSafeToMove. No > intended functionality change. > > The avoidance of hoistiing implicitdef seems wrong though. > > Modified: > llvm/trunk/lib/CodeGen/MachineLICM.cpp > > Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineLICM.cpp?rev=108109&r1=108108&r2=108109&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/MachineLICM.cpp (original) > +++ llvm/trunk/lib/CodeGen/MachineLICM.cpp Sun Jul 11 19:00:35 2010 > @@ -127,8 +127,8 @@ > void AddToLiveIns(unsigned Reg); > > /// IsLICMCandidate - Returns true if the instruction may be a suitable > - /// candidate for LICM. e.g. If the instruction is a call, then it's obviously > - /// not safe to hoist it. > + /// candidate for LICM. e.g. If the instruction is a call, then it's > + /// obviously not safe to hoist it. > bool IsLICMCandidate(MachineInstr &I); > > /// IsLoopInvariantInst - Returns true if the instruction is loop > @@ -497,26 +497,16 @@ > /// candidate for LICM. e.g. If the instruction is a call, then it's obviously > /// not safe to hoist it. > bool MachineLICM::IsLICMCandidate(MachineInstr &I) { > + // It is not profitable to hoist implicitdefs. FIXME: Why not? what if they > + // are an argument to some other otherwise-hoistable instruction? I think this can to be handled specifically during check for loop invariant. If an operand is non-invariant implicitdef, this pass can create an invariant implicitdef operand to allow the instruction to be hoisted. Evan > if (I.isImplicitDef()) > return false; > - > - const TargetInstrDesc &TID = I.getDesc(); > > - // Ignore stuff that we obviously can't hoist. > - if (TID.mayStore() || TID.isCall() || TID.isTerminator() || > - TID.hasUnmodeledSideEffects()) > + // Check if it's safe to move the instruction. > + bool DontMoveAcrossStore = true; > + if (!I.isSafeToMove(TII, AA, DontMoveAcrossStore)) > return false; > - > - if (TID.mayLoad()) { > - // Okay, this instruction does a load. As a refinement, we allow the target > - // to decide whether the loaded value is actually a constant. If so, we can > - // actually use it as a load. > - if (!I.isInvariantLoad(AA)) > - // FIXME: we should be able to hoist loads with no other side effects if > - // there are no other instructions which can change memory in this loop. > - // This is a trivial form of alias analysis. > - return false; > - } > + > return true; > } > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From baldrick at free.fr Mon Jul 12 03:16:59 2010 From: baldrick at free.fr (Duncan Sands) Date: Mon, 12 Jul 2010 08:16:59 -0000 Subject: [llvm-commits] [llvm] r108130 - in /llvm/trunk: examples/Kaleidoscope/Chapter3/ examples/Kaleidoscope/Chapter4/ examples/Kaleidoscope/Chapter5/ examples/Kaleidoscope/Chapter6/ include/llvm/ExecutionEngine/ lib/Analysis/ lib/CodeGen/PBQP/ lib/CodeGen/SelectionDAG/ lib/ExecutionEngine/Interpreter/ lib/ExecutionEngine/JIT/ lib/MC/ lib/MC/MCParser/ lib/System/Win32/ lib/Target/ARM/AsmParser/ lib/Target/ARM/AsmPrinter/ lib/Target/ARM/Disassembler/ lib/Target/PIC16/ lib/Transforms/InstCombine/ lib/Transforms/Scalar/ lib/VMCo... Message-ID: <20100712081659.A50112A6C12D@llvm.org> Author: baldrick Date: Mon Jul 12 03:16:59 2010 New Revision: 108130 URL: http://llvm.org/viewvc/llvm-project?rev=108130&view=rev Log: Convert some tab stops into spaces. Modified: llvm/trunk/examples/Kaleidoscope/Chapter3/toy.cpp llvm/trunk/examples/Kaleidoscope/Chapter4/toy.cpp llvm/trunk/examples/Kaleidoscope/Chapter5/toy.cpp llvm/trunk/examples/Kaleidoscope/Chapter6/toy.cpp llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h llvm/trunk/lib/Analysis/DomPrinter.cpp llvm/trunk/lib/CodeGen/PBQP/HeuristicSolver.h llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp llvm/trunk/lib/ExecutionEngine/JIT/JIT.h llvm/trunk/lib/MC/MCContext.cpp llvm/trunk/lib/MC/MCExpr.cpp llvm/trunk/lib/MC/MCParser/AsmLexer.cpp llvm/trunk/lib/MC/MCParser/AsmParser.cpp llvm/trunk/lib/System/Win32/Signals.inc llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp llvm/trunk/lib/Target/PIC16/PIC16MemSelOpt.cpp llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp llvm/trunk/lib/Transforms/Scalar/ABCD.cpp llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp llvm/trunk/lib/VMCore/AsmWriter.cpp llvm/trunk/lib/VMCore/Instructions.cpp llvm/trunk/tools/bugpoint/BugDriver.h llvm/trunk/tools/bugpoint/ListReducer.h llvm/trunk/tools/bugpoint/ToolRunner.h llvm/trunk/tools/opt/opt.cpp llvm/trunk/utils/TableGen/ARMDecoderEmitter.h llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp Modified: llvm/trunk/examples/Kaleidoscope/Chapter3/toy.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/Kaleidoscope/Chapter3/toy.cpp?rev=108130&r1=108129&r2=108130&view=diff ============================================================================== --- llvm/trunk/examples/Kaleidoscope/Chapter3/toy.cpp (original) +++ llvm/trunk/examples/Kaleidoscope/Chapter3/toy.cpp Mon Jul 12 03:16:59 2010 @@ -400,7 +400,7 @@ Function *PrototypeAST::Codegen() { // Make the function type: double(double,double) etc. - std::vector Doubles(Args.size(), + std::vector Doubles(Args.size(), Type::getDoubleTy(getGlobalContext())); FunctionType *FT = FunctionType::get(Type::getDoubleTy(getGlobalContext()), Doubles, false); Modified: llvm/trunk/examples/Kaleidoscope/Chapter4/toy.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/Kaleidoscope/Chapter4/toy.cpp?rev=108130&r1=108129&r2=108130&view=diff ============================================================================== --- llvm/trunk/examples/Kaleidoscope/Chapter4/toy.cpp (original) +++ llvm/trunk/examples/Kaleidoscope/Chapter4/toy.cpp Mon Jul 12 03:16:59 2010 @@ -407,7 +407,7 @@ Function *PrototypeAST::Codegen() { // Make the function type: double(double,double) etc. - std::vector Doubles(Args.size(), + std::vector Doubles(Args.size(), Type::getDoubleTy(getGlobalContext())); FunctionType *FT = FunctionType::get(Type::getDoubleTy(getGlobalContext()), Doubles, false); Modified: llvm/trunk/examples/Kaleidoscope/Chapter5/toy.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/Kaleidoscope/Chapter5/toy.cpp?rev=108130&r1=108129&r2=108130&view=diff ============================================================================== --- llvm/trunk/examples/Kaleidoscope/Chapter5/toy.cpp (original) +++ llvm/trunk/examples/Kaleidoscope/Chapter5/toy.cpp Mon Jul 12 03:16:59 2010 @@ -652,7 +652,7 @@ Function *PrototypeAST::Codegen() { // Make the function type: double(double,double) etc. - std::vector Doubles(Args.size(), + std::vector Doubles(Args.size(), Type::getDoubleTy(getGlobalContext())); FunctionType *FT = FunctionType::get(Type::getDoubleTy(getGlobalContext()), Doubles, false); Modified: llvm/trunk/examples/Kaleidoscope/Chapter6/toy.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/Kaleidoscope/Chapter6/toy.cpp?rev=108130&r1=108129&r2=108130&view=diff ============================================================================== --- llvm/trunk/examples/Kaleidoscope/Chapter6/toy.cpp (original) +++ llvm/trunk/examples/Kaleidoscope/Chapter6/toy.cpp Mon Jul 12 03:16:59 2010 @@ -756,7 +756,7 @@ Function *PrototypeAST::Codegen() { // Make the function type: double(double,double) etc. - std::vector Doubles(Args.size(), + std::vector Doubles(Args.size(), Type::getDoubleTy(getGlobalContext())); FunctionType *FT = FunctionType::get(Type::getDoubleTy(getGlobalContext()), Doubles, false); Modified: llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h?rev=108130&r1=108129&r2=108130&view=diff ============================================================================== --- llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h (original) +++ llvm/trunk/include/llvm/ExecutionEngine/ExecutionEngine.h Mon Jul 12 03:16:59 2010 @@ -174,8 +174,8 @@ CodeGenOpt::Level OptLevel = CodeGenOpt::Default, bool GVsWithCode = true, - CodeModel::Model CMM = - CodeModel::Default); + CodeModel::Model CMM = + CodeModel::Default); /// addModule - Add a Module to the list of modules that we can JIT from. /// Note that this takes ownership of the Module: when the ExecutionEngine is Modified: llvm/trunk/lib/Analysis/DomPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DomPrinter.cpp?rev=108130&r1=108129&r2=108130&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/DomPrinter.cpp (original) +++ llvm/trunk/lib/Analysis/DomPrinter.cpp Mon Jul 12 03:16:59 2010 @@ -43,10 +43,10 @@ if (isSimple()) return DOTGraphTraits - ::getSimpleNodeLabel(BB, BB->getParent()); + ::getSimpleNodeLabel(BB, BB->getParent()); else return DOTGraphTraits - ::getCompleteNodeLabel(BB, BB->getParent()); + ::getCompleteNodeLabel(BB, BB->getParent()); } }; Modified: llvm/trunk/lib/CodeGen/PBQP/HeuristicSolver.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PBQP/HeuristicSolver.h?rev=108130&r1=108129&r2=108130&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PBQP/HeuristicSolver.h (original) +++ llvm/trunk/lib/CodeGen/PBQP/HeuristicSolver.h Mon Jul 12 03:16:59 2010 @@ -406,7 +406,7 @@ // Create node data objects. for (Graph::NodeItr nItr = g.nodesBegin(), nEnd = g.nodesEnd(); - nItr != nEnd; ++nItr) { + nItr != nEnd; ++nItr) { nodeDataList.push_back(NodeData()); g.setNodeData(nItr, &nodeDataList.back()); } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=108130&r1=108129&r2=108130&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Jul 12 03:16:59 2010 @@ -3573,24 +3573,24 @@ // we know that the element size of the sext'd result matches the // element size of the compare operands. if (VT.getSizeInBits() == N0VT.getSizeInBits()) - return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), - N0.getOperand(1), - cast(N0.getOperand(2))->get()); + return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), + N0.getOperand(1), + cast(N0.getOperand(2))->get()); // If the desired elements are smaller or larger than the source // elements we can use a matching integer vector type and then // truncate/sign extend else { - EVT MatchingElementType = - EVT::getIntegerVT(*DAG.getContext(), - N0VT.getScalarType().getSizeInBits()); - EVT MatchingVectorType = - EVT::getVectorVT(*DAG.getContext(), MatchingElementType, - N0VT.getVectorNumElements()); - SDValue VsetCC = - DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), - N0.getOperand(1), - cast(N0.getOperand(2))->get()); - return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); + EVT MatchingElementType = + EVT::getIntegerVT(*DAG.getContext(), + N0VT.getScalarType().getSizeInBits()); + EVT MatchingVectorType = + EVT::getVectorVT(*DAG.getContext(), MatchingElementType, + N0VT.getVectorNumElements()); + SDValue VsetCC = + DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), + N0.getOperand(1), + cast(N0.getOperand(2))->get()); + return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); } } @@ -3964,24 +3964,24 @@ // we know that the element size of the sext'd result matches the // element size of the compare operands. if (VT.getSizeInBits() == N0VT.getSizeInBits()) - return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), - N0.getOperand(1), - cast(N0.getOperand(2))->get()); + return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), + N0.getOperand(1), + cast(N0.getOperand(2))->get()); // If the desired elements are smaller or larger than the source // elements we can use a matching integer vector type and then // truncate/sign extend else { - EVT MatchingElementType = - EVT::getIntegerVT(*DAG.getContext(), - N0VT.getScalarType().getSizeInBits()); - EVT MatchingVectorType = - EVT::getVectorVT(*DAG.getContext(), MatchingElementType, - N0VT.getVectorNumElements()); - SDValue VsetCC = - DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), - N0.getOperand(1), - cast(N0.getOperand(2))->get()); - return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); + EVT MatchingElementType = + EVT::getIntegerVT(*DAG.getContext(), + N0VT.getScalarType().getSizeInBits()); + EVT MatchingVectorType = + EVT::getVectorVT(*DAG.getContext(), MatchingElementType, + N0VT.getVectorNumElements()); + SDValue VsetCC = + DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), + N0.getOperand(1), + cast(N0.getOperand(2))->get()); + return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); } } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp?rev=108130&r1=108129&r2=108130&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp Mon Jul 12 03:16:59 2010 @@ -505,7 +505,7 @@ SDValue NewVAARG; NewVAARG = DAG.getVAArg(NVT, dl, Chain, Ptr, N->getOperand(2), - N->getConstantOperandVal(3)); + N->getConstantOperandVal(3)); // Legalized the chain result - switch anything that used the old chain to // use the new one. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp?rev=108130&r1=108129&r2=108130&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp Mon Jul 12 03:16:59 2010 @@ -278,7 +278,7 @@ FlaggedNodes.push_back(N); while (!FlaggedNodes.empty()) { O << DOTGraphTraits - ::getSimpleNodeLabel(FlaggedNodes.back(), DAG); + ::getSimpleNodeLabel(FlaggedNodes.back(), DAG); FlaggedNodes.pop_back(); if (!FlaggedNodes.empty()) O << "\n "; Modified: llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp?rev=108130&r1=108129&r2=108130&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp (original) +++ llvm/trunk/lib/ExecutionEngine/Interpreter/ExternalFunctions.cpp Mon Jul 12 03:16:59 2010 @@ -266,7 +266,7 @@ RawFn = (RawFunc)(intptr_t) sys::DynamicLibrary::SearchForAddressOfSymbol(F->getName()); if (!RawFn) - RawFn = (RawFunc)(intptr_t)getPointerToGlobalIfAvailable(F); + RawFn = (RawFunc)(intptr_t)getPointerToGlobalIfAvailable(F); if (RawFn != 0) RawFunctions->insert(std::make_pair(F, RawFn)); // Cache for later } else { Modified: llvm/trunk/lib/ExecutionEngine/JIT/JIT.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/JIT.h?rev=108130&r1=108129&r2=108130&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/JIT/JIT.h (original) +++ llvm/trunk/lib/ExecutionEngine/JIT/JIT.h Mon Jul 12 03:16:59 2010 @@ -100,9 +100,9 @@ CodeGenOpt::Level OptLevel = CodeGenOpt::Default, bool GVsWithCode = true, - CodeModel::Model CMM = CodeModel::Default) { + CodeModel::Model CMM = CodeModel::Default) { return ExecutionEngine::createJIT(M, Err, JMM, OptLevel, GVsWithCode, - CMM); + CMM); } virtual void addModule(Module *M); Modified: llvm/trunk/lib/MC/MCContext.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCContext.cpp?rev=108130&r1=108129&r2=108130&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCContext.cpp (original) +++ llvm/trunk/lib/MC/MCContext.cpp Mon Jul 12 03:16:59 2010 @@ -97,14 +97,14 @@ return GetOrCreateSymbol(Twine(MAI.getPrivateGlobalPrefix()) + Twine(LocalLabelVal) + "\2" + - Twine(NextInstance(LocalLabelVal))); + Twine(NextInstance(LocalLabelVal))); } MCSymbol *MCContext::GetDirectionalLocalSymbol(int64_t LocalLabelVal, int bORf) { return GetOrCreateSymbol(Twine(MAI.getPrivateGlobalPrefix()) + Twine(LocalLabelVal) + "\2" + - Twine(GetInstance(LocalLabelVal) + bORf)); + Twine(GetInstance(LocalLabelVal) + bORf)); } MCSymbol *MCContext::LookupSymbol(StringRef Name) const { Modified: llvm/trunk/lib/MC/MCExpr.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCExpr.cpp?rev=108130&r1=108129&r2=108130&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCExpr.cpp (original) +++ llvm/trunk/lib/MC/MCExpr.cpp Mon Jul 12 03:16:59 2010 @@ -40,7 +40,7 @@ const MCSymbol &Sym = SRE.getSymbol(); if (SRE.getKind() == MCSymbolRefExpr::VK_ARM_HI16 || - SRE.getKind() == MCSymbolRefExpr::VK_ARM_LO16) + SRE.getKind() == MCSymbolRefExpr::VK_ARM_LO16) OS << MCSymbolRefExpr::getVariantKindName(SRE.getKind()); // Parenthesize names that start with $ so that they don't look like @@ -51,8 +51,8 @@ OS << Sym; if (SRE.getKind() != MCSymbolRefExpr::VK_None && - SRE.getKind() != MCSymbolRefExpr::VK_ARM_HI16 && - SRE.getKind() != MCSymbolRefExpr::VK_ARM_LO16) + SRE.getKind() != MCSymbolRefExpr::VK_ARM_HI16 && + SRE.getKind() != MCSymbolRefExpr::VK_ARM_LO16) OS << '@' << MCSymbolRefExpr::getVariantKindName(SRE.getKind()); return; Modified: llvm/trunk/lib/MC/MCParser/AsmLexer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmLexer.cpp?rev=108130&r1=108129&r2=108130&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmLexer.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmLexer.cpp Mon Jul 12 03:16:59 2010 @@ -229,7 +229,7 @@ TokStart = CurPtr; while (!isAtStartOfComment(*CurPtr) && // Start of line comment. - *CurPtr != ';' && // End of statement marker. + *CurPtr != ';' && // End of statement marker. *CurPtr != '\n' && *CurPtr != '\r' && (*CurPtr != 0 || CurPtr != CurBuf->getBufferEnd())) { Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=108130&r1=108129&r2=108130&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Mon Jul 12 03:16:59 2010 @@ -453,8 +453,8 @@ IDVal = getTok().getString(); Lex(); // Consume the integer token to be used as an identifier token. if (Lexer.getKind() != AsmToken::Colon) { - if (!TheCondState.Ignore) - return TokError("unexpected token at start of statement"); + if (!TheCondState.Ignore) + return TokError("unexpected token at start of statement"); } } } Modified: llvm/trunk/lib/System/Win32/Signals.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Win32/Signals.inc?rev=108130&r1=108129&r2=108130&view=diff ============================================================================== --- llvm/trunk/lib/System/Win32/Signals.inc (original) +++ llvm/trunk/lib/System/Win32/Signals.inc Mon Jul 12 03:16:59 2010 @@ -283,7 +283,7 @@ #ifdef _MSC_VER if (ExitOnUnhandledExceptions) - _exit(-3); + _exit(-3); #endif // Allow dialog box to pop up allowing choice to start debugger. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=108130&r1=108129&r2=108130&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Jul 12 03:16:59 2010 @@ -425,7 +425,7 @@ const AsmToken &NextTok = Parser.getTok(); if (NextTok.isNot(AsmToken::EndOfStatement)) { if (NextTok.isNot(AsmToken::Comma)) - return Error(NextTok.getLoc(), "',' expected"); + return Error(NextTok.getLoc(), "',' expected"); Parser.Lex(); // Eat comma token. if(ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount, Offset, OffsetIsReg, OffsetRegNum, @@ -488,7 +488,7 @@ const AsmToken &Tok = Parser.getTok(); if (ParseShift(ShiftType, ShiftAmount, E)) - return Error(Tok.getLoc(), "shift expected"); + return Error(Tok.getLoc(), "shift expected"); OffsetRegShifted = true; } } Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=108130&r1=108129&r2=108130&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Mon Jul 12 03:16:59 2010 @@ -1397,11 +1397,11 @@ } else if (MO.isGlobal()) { MCSymbol *Symbol = MCInstLowering.GetGlobalAddressSymbol(MO); const MCSymbolRefExpr *SymRef1 = - MCSymbolRefExpr::Create(Symbol, - MCSymbolRefExpr::VK_ARM_LO16, OutContext); + MCSymbolRefExpr::Create(Symbol, + MCSymbolRefExpr::VK_ARM_LO16, OutContext); const MCSymbolRefExpr *SymRef2 = - MCSymbolRefExpr::Create(Symbol, - MCSymbolRefExpr::VK_ARM_HI16, OutContext); + MCSymbolRefExpr::Create(Symbol, + MCSymbolRefExpr::VK_ARM_HI16, OutContext); V1 = MCOperand::CreateExpr(SymRef1); V2 = MCOperand::CreateExpr(SymRef2); } else { Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=108130&r1=108129&r2=108130&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Mon Jul 12 03:16:59 2010 @@ -34,7 +34,7 @@ /// Uses and Defs by this instr. For the Uses part, the pred:$p operand is /// defined with two components: /// -/// def pred { // Operand PredicateOperand +/// def pred { // Operand PredicateOperand /// ValueType Type = OtherVT; /// string PrintMethod = "printPredicateOperand"; /// string AsmOperandLowerMethod = ?; @@ -54,7 +54,7 @@ /// /// For the Defs part, in the simple case of only cc_out:$s, we have: /// -/// def cc_out { // Operand OptionalDefOperand +/// def cc_out { // Operand OptionalDefOperand /// ValueType Type = OtherVT; /// string PrintMethod = "printSBitModifierOperand"; /// string AsmOperandLowerMethod = ?; Modified: llvm/trunk/lib/Target/PIC16/PIC16MemSelOpt.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16MemSelOpt.cpp?rev=108130&r1=108129&r2=108130&view=diff ============================================================================== --- llvm/trunk/lib/Target/PIC16/PIC16MemSelOpt.cpp (original) +++ llvm/trunk/lib/Target/PIC16/PIC16MemSelOpt.cpp Mon Jul 12 03:16:59 2010 @@ -117,7 +117,7 @@ DebugLoc dl = I->getDebugLoc(); BuildMI(*MBB, I, dl, TII->get(PIC16::pagesel)).addExternalSymbol("$"); Changed = true; - PageChanged = 0; + PageChanged = 0; } } } Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp?rev=108130&r1=108129&r2=108130&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp Mon Jul 12 03:16:59 2010 @@ -1446,7 +1446,7 @@ } break; default: - break; + break; } } } Modified: llvm/trunk/lib/Transforms/Scalar/ABCD.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ABCD.cpp?rev=108130&r1=108129&r2=108130&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ABCD.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ABCD.cpp Mon Jul 12 03:16:59 2010 @@ -230,7 +230,7 @@ DenseMapIterator begin = map.begin(); DenseMapIterator end = map.end(); for (; begin != end; ++begin) { - begin->second.clear(); + begin->second.clear(); } map.clear(); } @@ -396,8 +396,8 @@ /// this case the method returns true, otherwise false. It also obtains the /// Instruction and ConstantInt from the BinaryOperator and returns it. bool createBinaryOperatorInfo(BinaryOperator *BO, Instruction **I1, - Instruction **I2, ConstantInt **C1, - ConstantInt **C2); + Instruction **I2, ConstantInt **C1, + ConstantInt **C2); /// This method creates a constraint between a Sigma and an Instruction. /// These constraints are created as soon as we find a comparator that uses a Modified: llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp?rev=108130&r1=108129&r2=108130&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp Mon Jul 12 03:16:59 2010 @@ -958,11 +958,11 @@ continue; for (BasicBlock::iterator BI = BB->begin(), BE = BB->end(); - BI != BE; ++BI) { + BI != BE; ++BI) { Instruction *Inst = BI; if (!Inst->isSafeToSpeculativelyExecute() && !isa(Inst) - && !isa(Inst) && !isa(Inst)) + && !isa(Inst) && !isa(Inst)) return false; } } Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=108130&r1=108129&r2=108130&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/AsmWriter.cpp (original) +++ llvm/trunk/lib/VMCore/AsmWriter.cpp Mon Jul 12 03:16:59 2010 @@ -2036,7 +2036,7 @@ } static void WriteMDNodeComment(const MDNode *Node, - formatted_raw_ostream &Out) { + formatted_raw_ostream &Out) { if (Node->getNumOperands() < 1) return; ConstantInt *CI = dyn_cast_or_null(Node->getOperand(0)); Modified: llvm/trunk/lib/VMCore/Instructions.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=108130&r1=108129&r2=108130&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Instructions.cpp (original) +++ llvm/trunk/lib/VMCore/Instructions.cpp Mon Jul 12 03:16:59 2010 @@ -471,7 +471,7 @@ Instruction *CallInst::CreateMalloc(Instruction *InsertBefore, const Type *IntPtrTy, const Type *AllocTy, Value *AllocSize, Value *ArraySize, - Function * MallocF, + Function * MallocF, const Twine &Name) { return createMalloc(InsertBefore, NULL, IntPtrTy, AllocTy, AllocSize, ArraySize, MallocF, Name); Modified: llvm/trunk/tools/bugpoint/BugDriver.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/bugpoint/BugDriver.h?rev=108130&r1=108129&r2=108130&view=diff ============================================================================== --- llvm/trunk/tools/bugpoint/BugDriver.h (original) +++ llvm/trunk/tools/bugpoint/BugDriver.h Mon Jul 12 03:16:59 2010 @@ -269,7 +269,7 @@ /// recreate the failure. This returns true if a compiler error is found. /// bool runManyPasses(const std::vector &AllPasses, - std::string &ErrMsg); + std::string &ErrMsg); /// writeProgramToFile - This writes the current "Program" to the named /// bitcode file. If an error occurs, true is returned. Modified: llvm/trunk/tools/bugpoint/ListReducer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/bugpoint/ListReducer.h?rev=108130&r1=108129&r2=108130&view=diff ============================================================================== --- llvm/trunk/tools/bugpoint/ListReducer.h (original) +++ llvm/trunk/tools/bugpoint/ListReducer.h Mon Jul 12 03:16:59 2010 @@ -183,8 +183,8 @@ --i; // Don't skip an element of the list Changed = true; } - if (!Error.empty()) - return true; + if (!Error.empty()) + return true; } // This can take a long time if left uncontrolled. For now, don't // iterate. Modified: llvm/trunk/tools/bugpoint/ToolRunner.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/bugpoint/ToolRunner.h?rev=108130&r1=108129&r2=108130&view=diff ============================================================================== --- llvm/trunk/tools/bugpoint/ToolRunner.h (original) +++ llvm/trunk/tools/bugpoint/ToolRunner.h Mon Jul 12 03:16:59 2010 @@ -64,7 +64,7 @@ FileType fileType, const std::string &InputFile, const std::string &OutputFile, - std::string *Error = 0, + std::string *Error = 0, const std::vector &GCCArgs = std::vector(), unsigned Timeout = 0, Modified: llvm/trunk/tools/opt/opt.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/opt/opt.cpp?rev=108130&r1=108129&r2=108130&view=diff ============================================================================== --- llvm/trunk/tools/opt/opt.cpp (original) +++ llvm/trunk/tools/opt/opt.cpp Mon Jul 12 03:16:59 2010 @@ -112,7 +112,7 @@ static cl::opt UnitAtATime("funit-at-a-time", cl::desc("Enable IPO. This is same as llvm-gcc's -funit-at-a-time"), - cl::init(true)); + cl::init(true)); static cl::opt DisableSimplifyLibCalls("disable-simplify-libcalls", Modified: llvm/trunk/utils/TableGen/ARMDecoderEmitter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/ARMDecoderEmitter.h?rev=108130&r1=108129&r2=108130&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/ARMDecoderEmitter.h (original) +++ llvm/trunk/utils/TableGen/ARMDecoderEmitter.h Mon Jul 12 03:16:59 2010 @@ -31,7 +31,7 @@ ~ARMDecoderEmitter() { shutdownBackend(); } - + // run - Output the code emitter void run(raw_ostream &o); Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=108130&r1=108129&r2=108130&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Mon Jul 12 03:16:59 2010 @@ -407,9 +407,9 @@ default: // This class preceeds the RHS if it is a proper subset of the RHS. if (isSubsetOf(RHS)) - return true; + return true; if (RHS.isSubsetOf(*this)) - return false; + return false; // Otherwise, order by name to ensure we have a total ordering. return ValueName < RHS.ValueName; Modified: llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp?rev=108130&r1=108129&r2=108130&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp (original) +++ llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp Mon Jul 12 03:16:59 2010 @@ -33,7 +33,7 @@ MAP(C9, 38) \ MAP(E8, 39) \ MAP(F0, 40) \ - MAP(F8, 41) \ + MAP(F8, 41) \ MAP(F9, 42) // A clone of X86 since we can't depend on something that is generated. From ggreif at gmail.com Mon Jul 12 05:36:48 2010 From: ggreif at gmail.com (Gabor Greif) Date: Mon, 12 Jul 2010 10:36:48 -0000 Subject: [llvm-commits] [llvm] r108131 - in /llvm/trunk/lib: Transforms/Scalar/TailDuplication.cpp Transforms/Scalar/TailRecursionElimination.cpp VMCore/Instruction.cpp Message-ID: <20100712103648.6E8782A6C12C@llvm.org> Author: ggreif Date: Mon Jul 12 05:36:48 2010 New Revision: 108131 URL: http://llvm.org/viewvc/llvm-project?rev=108131&view=rev Log: cache dereferenced iterators Modified: llvm/trunk/lib/Transforms/Scalar/TailDuplication.cpp llvm/trunk/lib/Transforms/Scalar/TailRecursionElimination.cpp llvm/trunk/lib/VMCore/Instruction.cpp Modified: llvm/trunk/lib/Transforms/Scalar/TailDuplication.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/TailDuplication.cpp?rev=108131&r1=108130&r2=108131&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/TailDuplication.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/TailDuplication.cpp Mon Jul 12 05:36:48 2010 @@ -206,13 +206,14 @@ // there is only one other pred, get it, otherwise we can't handle it. PI = pred_begin(DstBlock); PE = pred_end(DstBlock); BasicBlock *DstOtherPred = 0; - if (*PI == SrcBlock) { + BasicBlock *P = *PI; + if (P == SrcBlock) { if (++PI == PE) return 0; - DstOtherPred = *PI; + DstOtherPred = P; if (++PI != PE) return 0; } else { - DstOtherPred = *PI; - if (++PI == PE || *PI != SrcBlock || ++PI != PE) return 0; + DstOtherPred = P; + if (++PI == PE || P != SrcBlock || ++PI != PE) return 0; } // We can handle two situations here: "if then" and "if then else" blocks. An Modified: llvm/trunk/lib/Transforms/Scalar/TailRecursionElimination.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/TailRecursionElimination.cpp?rev=108131&r1=108130&r2=108131&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/TailRecursionElimination.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/TailRecursionElimination.cpp Mon Jul 12 05:36:48 2010 @@ -476,10 +476,11 @@ // it will not show up as a predecessor. for (pred_iterator PI = pred_begin(OldEntry), PE = pred_end(OldEntry); PI != PE; ++PI) { - if (*PI == &F->getEntryBlock()) - AccPN->addIncoming(AccumulatorRecursionEliminationInitVal, *PI); + BasicBlock *P = *PI; + if (P == &F->getEntryBlock()) + AccPN->addIncoming(AccumulatorRecursionEliminationInitVal, P); else - AccPN->addIncoming(AccPN, *PI); + AccPN->addIncoming(AccPN, P); } // Add an incoming argument for the current block, which is computed by our Modified: llvm/trunk/lib/VMCore/Instruction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instruction.cpp?rev=108131&r1=108130&r2=108131&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Instruction.cpp (original) +++ llvm/trunk/lib/VMCore/Instruction.cpp Mon Jul 12 05:36:48 2010 @@ -286,9 +286,10 @@ for (const_use_iterator UI = use_begin(), E = use_end(); UI != E; ++UI) { // PHI nodes uses values in the corresponding predecessor block. For other // instructions, just check to see whether the parent of the use matches up. - const PHINode *PN = dyn_cast(*UI); + const User *U = *UI; + const PHINode *PN = dyn_cast(U); if (PN == 0) { - if (cast(*UI)->getParent() != BB) + if (cast(U)->getParent() != BB) return true; continue; } From ggreif at gmail.com Mon Jul 12 05:49:54 2010 From: ggreif at gmail.com (Gabor Greif) Date: Mon, 12 Jul 2010 10:49:54 -0000 Subject: [llvm-commits] [llvm] r108132 - /llvm/trunk/lib/Transforms/Utils/Local.cpp Message-ID: <20100712104954.5DC212A6C12C@llvm.org> Author: ggreif Date: Mon Jul 12 05:49:54 2010 New Revision: 108132 URL: http://llvm.org/viewvc/llvm-project?rev=108132&view=rev Log: cache dereferenced iterators Modified: llvm/trunk/lib/Transforms/Utils/Local.cpp Modified: llvm/trunk/lib/Transforms/Utils/Local.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/Local.cpp?rev=108132&r1=108131&r2=108132&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/Local.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/Local.cpp Mon Jul 12 05:49:54 2010 @@ -432,9 +432,11 @@ // Use that list to make another list of common predecessors of BB and Succ BlockSet CommonPreds; for (pred_iterator PI = pred_begin(Succ), PE = pred_end(Succ); - PI != PE; ++PI) - if (BBPreds.count(*PI)) - CommonPreds.insert(*PI); + PI != PE; ++PI) { + BasicBlock *P = *PI; + if (BBPreds.count(P)) + CommonPreds.insert(P); + } // Shortcut, if there are no common predecessors, merging is always safe if (CommonPreds.empty()) From ggreif at gmail.com Mon Jul 12 05:59:23 2010 From: ggreif at gmail.com (Gabor Greif) Date: Mon, 12 Jul 2010 10:59:23 -0000 Subject: [llvm-commits] [llvm] r108133 - /llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Message-ID: <20100712105923.615CD2A6C12C@llvm.org> Author: ggreif Date: Mon Jul 12 05:59:23 2010 New Revision: 108133 URL: http://llvm.org/viewvc/llvm-project?rev=108133&view=rev Log: cache dereferenced iterators Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=108133&r1=108132&r2=108133&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Mon Jul 12 05:59:23 2010 @@ -1513,17 +1513,19 @@ // Okay, we're going to insert the PHI node. Since PBI is not the only // predecessor, compute the PHI'd conditional value for all of the preds. // Any predecessor where the condition is not computable we keep symbolic. - for (pred_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI) - if ((PBI = dyn_cast((*PI)->getTerminator())) && + for (pred_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI) { + BasicBlock *P = *PI; + if ((PBI = dyn_cast(P->getTerminator())) && PBI != BI && PBI->isConditional() && PBI->getCondition() == BI->getCondition() && PBI->getSuccessor(0) != PBI->getSuccessor(1)) { bool CondIsTrue = PBI->getSuccessor(0) == BB; NewPN->addIncoming(ConstantInt::get(Type::getInt1Ty(BB->getContext()), - CondIsTrue), *PI); + CondIsTrue), P); } else { - NewPN->addIncoming(BI->getCondition(), *PI); + NewPN->addIncoming(BI->getCondition(), P); } + } BI->setCondition(NewPN); return true; From ggreif at gmail.com Mon Jul 12 06:19:24 2010 From: ggreif at gmail.com (Gabor Greif) Date: Mon, 12 Jul 2010 11:19:24 -0000 Subject: [llvm-commits] [llvm] r108134 - /llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp Message-ID: <20100712111924.627412A6C12C@llvm.org> Author: ggreif Date: Mon Jul 12 06:19:24 2010 New Revision: 108134 URL: http://llvm.org/viewvc/llvm-project?rev=108134&view=rev Log: cache dereferenced iterators Modified: llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp Modified: llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp?rev=108134&r1=108133&r2=108134&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/StructRetPromotion.cpp Mon Jul 12 06:19:24 2010 @@ -171,16 +171,16 @@ // Check FirstArg's users. for (Value::use_iterator ArgI = FirstArg->use_begin(), ArgE = FirstArg->use_end(); ArgI != ArgE; ++ArgI) { - + User *U = *ArgI; // If FirstArg user is a CallInst that does not correspond to current // call site then this function F is not suitable for sret promotion. - if (CallInst *CI = dyn_cast(ArgI)) { + if (CallInst *CI = dyn_cast(U)) { if (CI != Call) return false; } // If FirstArg user is a GEP whose all users are not LoadInst then // this function F is not suitable for sret promotion. - else if (GetElementPtrInst *GEP = dyn_cast(ArgI)) { + else if (GetElementPtrInst *GEP = dyn_cast(U)) { // TODO : Use dom info and insert PHINodes to collect get results // from multiple call sites for this GEP. if (GEP->getParent() != Call->getParent()) From ggreif at gmail.com Mon Jul 12 06:32:39 2010 From: ggreif at gmail.com (Gabor Greif) Date: Mon, 12 Jul 2010 11:32:39 -0000 Subject: [llvm-commits] [llvm] r108135 - /llvm/trunk/lib/Transforms/Scalar/TailDuplication.cpp Message-ID: <20100712113239.EA62A2A6C12C@llvm.org> Author: ggreif Date: Mon Jul 12 06:32:39 2010 New Revision: 108135 URL: http://llvm.org/viewvc/llvm-project?rev=108135&view=rev Log: back out r108131 (of TailDuplication.cpp) for now, it causes a buildbot failure Modified: llvm/trunk/lib/Transforms/Scalar/TailDuplication.cpp Modified: llvm/trunk/lib/Transforms/Scalar/TailDuplication.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/TailDuplication.cpp?rev=108135&r1=108134&r2=108135&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/TailDuplication.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/TailDuplication.cpp Mon Jul 12 06:32:39 2010 @@ -206,14 +206,13 @@ // there is only one other pred, get it, otherwise we can't handle it. PI = pred_begin(DstBlock); PE = pred_end(DstBlock); BasicBlock *DstOtherPred = 0; - BasicBlock *P = *PI; - if (P == SrcBlock) { + if (*PI == SrcBlock) { if (++PI == PE) return 0; - DstOtherPred = P; + DstOtherPred = *PI; if (++PI != PE) return 0; } else { - DstOtherPred = P; - if (++PI == PE || P != SrcBlock || ++PI != PE) return 0; + DstOtherPred = *PI; + if (++PI == PE || *PI != SrcBlock || ++PI != PE) return 0; } // We can handle two situations here: "if then" and "if then else" blocks. An From benny.kra at googlemail.com Mon Jul 12 06:54:45 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Mon, 12 Jul 2010 11:54:45 -0000 Subject: [llvm-commits] [llvm] r108136 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineAndOrXor.cpp test/Transforms/InstCombine/or.ll test/Transforms/InstCombine/xor2.ll Message-ID: <20100712115445.45EB72A6C12C@llvm.org> Author: d0k Date: Mon Jul 12 06:54:45 2010 New Revision: 108136 URL: http://llvm.org/viewvc/llvm-project?rev=108136&view=rev Log: instcombine: fold (x & y) | (~x & z) and (x & y) ^ (~x & z) into ((y ^ z) & x) ^ z which is one instruction shorter. (PR6773) before: %and = and i32 %y, %x %neg = xor i32 %x, -1 %and4 = and i32 %z, %neg %xor = xor i32 %and4, %and after: %xor1 = xor i32 %z, %y %and2 = and i32 %xor1, %x %xor = xor i32 %and2, %z Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp llvm/trunk/test/Transforms/InstCombine/or.ll llvm/trunk/test/Transforms/InstCombine/xor2.ll Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp?rev=108136&r1=108135&r2=108136&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp Mon Jul 12 06:54:45 2010 @@ -1584,6 +1584,14 @@ if ((match(A, m_Not(m_Specific(B))) && match(D, m_Not(m_Specific(C))))) return BinaryOperator::CreateXor(C, B); + + // (A & ~C) | (B & C) -> ((B ^ A) & C) ^ A + if (Op0->hasOneUse() && Op1->hasOneUse() && + match(C, m_Not(m_Specific(D)))) { + Value *Xor = Builder->CreateXor(B, A, "xor"); + Value *And = Builder->CreateAnd(Xor, D, "and"); + return BinaryOperator::CreateXor(And, A); + } } // (X >> Z) | (Y >> Z) -> (X|Y) >> Z for all shifts. @@ -1920,6 +1928,15 @@ return BinaryOperator::CreateAnd(NewOp, X); } } + + // (A & ~C) ^ (B & C) -> ((B ^ A) & C) ^ A + if (Op0->hasOneUse() && Op1->hasOneUse() && + match(Op0I, m_And(m_Value(A), m_Not(m_Value(D)))) && + match(Op1I, m_And(m_Value(B), m_Value(D)))) { + Value *Xor = Builder->CreateXor(B, A, "xor"); + Value *And = Builder->CreateAnd(Xor, D, "and"); + return BinaryOperator::CreateXor(And, A); + } } // (icmp1 A, B) ^ (icmp2 A, B) --> (icmp3 A, B) Modified: llvm/trunk/test/Transforms/InstCombine/or.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/or.ll?rev=108136&r1=108135&r2=108136&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/or.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/or.ll Mon Jul 12 06:54:45 2010 @@ -350,3 +350,17 @@ ; CHECK: or <4 x i32> %and.i, %and.i129 } +; PR6773 +define i32 @test33(i32 %x, i32 %y, i32 %z) nounwind readnone { + %and = and i32 %y, %x + %not = xor i32 %x, -1 + %and2 = and i32 %z, %not + %xor = xor i32 %and2, %and + ret i32 %xor +; CHECK: @test33 +; CHECK: xor i32 +; CHECK: and i32 +; CHECK: xor i32 +; CHECK: ret i32 +} + Modified: llvm/trunk/test/Transforms/InstCombine/xor2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/xor2.ll?rev=108136&r1=108135&r2=108136&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/xor2.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/xor2.ll Mon Jul 12 06:54:45 2010 @@ -51,3 +51,17 @@ ; CHECK: %1 = ashr i32 %A, %B ; CHECK: ret i32 %1 } + +; PR6773 +define i32 @test5(i32 %x, i32 %y, i32 %z) nounwind readnone { + %and = and i32 %y, %x + %not = xor i32 %x, -1 + %and2 = and i32 %z, %not + %or = or i32 %and2, %and + ret i32 %or +; CHECK: @test5 +; CHECK: xor i32 +; CHECK: and i32 +; CHECK: xor i32 +; CHECK: ret i32 +} From ggreif at gmail.com Mon Jul 12 07:02:10 2010 From: ggreif at gmail.com (Gabor Greif) Date: Mon, 12 Jul 2010 12:02:10 -0000 Subject: [llvm-commits] [llvm] r108137 - /llvm/trunk/lib/Transforms/Scalar/TailDuplication.cpp Message-ID: <20100712120210.E5DE42A6C12C@llvm.org> Author: ggreif Date: Mon Jul 12 07:02:10 2010 New Revision: 108137 URL: http://llvm.org/viewvc/llvm-project?rev=108137&view=rev Log: recommit r108131 (hich has been backed out in r108135) with a fix Modified: llvm/trunk/lib/Transforms/Scalar/TailDuplication.cpp Modified: llvm/trunk/lib/Transforms/Scalar/TailDuplication.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/TailDuplication.cpp?rev=108137&r1=108136&r2=108137&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/TailDuplication.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/TailDuplication.cpp Mon Jul 12 07:02:10 2010 @@ -206,12 +206,13 @@ // there is only one other pred, get it, otherwise we can't handle it. PI = pred_begin(DstBlock); PE = pred_end(DstBlock); BasicBlock *DstOtherPred = 0; - if (*PI == SrcBlock) { + BasicBlock *P = *PI; + if (P == SrcBlock) { if (++PI == PE) return 0; DstOtherPred = *PI; if (++PI != PE) return 0; } else { - DstOtherPred = *PI; + DstOtherPred = P; if (++PI == PE || *PI != SrcBlock || ++PI != PE) return 0; } From ggreif at gmail.com Mon Jul 12 07:03:02 2010 From: ggreif at gmail.com (Gabor Greif) Date: Mon, 12 Jul 2010 12:03:02 -0000 Subject: [llvm-commits] [llvm] r108138 - /llvm/trunk/lib/Transforms/Scalar/Reassociate.cpp Message-ID: <20100712120302.3182F2A6C12C@llvm.org> Author: ggreif Date: Mon Jul 12 07:03:02 2010 New Revision: 108138 URL: http://llvm.org/viewvc/llvm-project?rev=108138&view=rev Log: cache dereferenced iterators Modified: llvm/trunk/lib/Transforms/Scalar/Reassociate.cpp Modified: llvm/trunk/lib/Transforms/Scalar/Reassociate.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/Reassociate.cpp?rev=108138&r1=108137&r2=108138&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/Reassociate.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/Reassociate.cpp Mon Jul 12 07:03:02 2010 @@ -407,13 +407,14 @@ // Okay, we need to materialize a negated version of V with an instruction. // Scan the use lists of V to see if we have one already. for (Value::use_iterator UI = V->use_begin(), E = V->use_end(); UI != E;++UI){ - if (!BinaryOperator::isNeg(*UI)) continue; + User *U = *UI; + if (!BinaryOperator::isNeg(U)) continue; // We found one! Now we have to make sure that the definition dominates // this use. We do this by moving it to the entry block (if it is a // non-instruction value) or right after the definition. These negates will // be zapped by reassociate later, so we don't need much finesse here. - BinaryOperator *TheNeg = cast(*UI); + BinaryOperator *TheNeg = cast(U); // Verify that the negate is in this function, V might be a constant expr. if (TheNeg->getParent()->getParent() != BI->getParent()->getParent()) From benny.kra at googlemail.com Mon Jul 12 07:35:49 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Mon, 12 Jul 2010 12:35:49 -0000 Subject: [llvm-commits] [llvm] r108139 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineAndOrXor.cpp test/Transforms/InstCombine/or.ll test/Transforms/InstCombine/xor2.ll Message-ID: <20100712123549.39BF22A6C12C@llvm.org> Author: d0k Date: Mon Jul 12 07:35:49 2010 New Revision: 108139 URL: http://llvm.org/viewvc/llvm-project?rev=108139&view=rev Log: Revert r108136 until I figure out why it broke selfhost. Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp llvm/trunk/test/Transforms/InstCombine/or.ll llvm/trunk/test/Transforms/InstCombine/xor2.ll Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp?rev=108139&r1=108138&r2=108139&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp Mon Jul 12 07:35:49 2010 @@ -1584,14 +1584,6 @@ if ((match(A, m_Not(m_Specific(B))) && match(D, m_Not(m_Specific(C))))) return BinaryOperator::CreateXor(C, B); - - // (A & ~C) | (B & C) -> ((B ^ A) & C) ^ A - if (Op0->hasOneUse() && Op1->hasOneUse() && - match(C, m_Not(m_Specific(D)))) { - Value *Xor = Builder->CreateXor(B, A, "xor"); - Value *And = Builder->CreateAnd(Xor, D, "and"); - return BinaryOperator::CreateXor(And, A); - } } // (X >> Z) | (Y >> Z) -> (X|Y) >> Z for all shifts. @@ -1928,15 +1920,6 @@ return BinaryOperator::CreateAnd(NewOp, X); } } - - // (A & ~C) ^ (B & C) -> ((B ^ A) & C) ^ A - if (Op0->hasOneUse() && Op1->hasOneUse() && - match(Op0I, m_And(m_Value(A), m_Not(m_Value(D)))) && - match(Op1I, m_And(m_Value(B), m_Value(D)))) { - Value *Xor = Builder->CreateXor(B, A, "xor"); - Value *And = Builder->CreateAnd(Xor, D, "and"); - return BinaryOperator::CreateXor(And, A); - } } // (icmp1 A, B) ^ (icmp2 A, B) --> (icmp3 A, B) Modified: llvm/trunk/test/Transforms/InstCombine/or.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/or.ll?rev=108139&r1=108138&r2=108139&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/or.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/or.ll Mon Jul 12 07:35:49 2010 @@ -350,17 +350,3 @@ ; CHECK: or <4 x i32> %and.i, %and.i129 } -; PR6773 -define i32 @test33(i32 %x, i32 %y, i32 %z) nounwind readnone { - %and = and i32 %y, %x - %not = xor i32 %x, -1 - %and2 = and i32 %z, %not - %xor = xor i32 %and2, %and - ret i32 %xor -; CHECK: @test33 -; CHECK: xor i32 -; CHECK: and i32 -; CHECK: xor i32 -; CHECK: ret i32 -} - Modified: llvm/trunk/test/Transforms/InstCombine/xor2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/xor2.ll?rev=108139&r1=108138&r2=108139&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/xor2.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/xor2.ll Mon Jul 12 07:35:49 2010 @@ -51,17 +51,3 @@ ; CHECK: %1 = ashr i32 %A, %B ; CHECK: ret i32 %1 } - -; PR6773 -define i32 @test5(i32 %x, i32 %y, i32 %z) nounwind readnone { - %and = and i32 %y, %x - %not = xor i32 %x, -1 - %and2 = and i32 %z, %not - %or = or i32 %and2, %and - ret i32 %or -; CHECK: @test5 -; CHECK: xor i32 -; CHECK: and i32 -; CHECK: xor i32 -; CHECK: ret i32 -} From benny.kra at googlemail.com Mon Jul 12 08:34:22 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Mon, 12 Jul 2010 13:34:22 -0000 Subject: [llvm-commits] [llvm] r108140 - /llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp Message-ID: <20100712133422.D7ED62A6C12C@llvm.org> Author: d0k Date: Mon Jul 12 08:34:22 2010 New Revision: 108140 URL: http://llvm.org/viewvc/llvm-project?rev=108140&view=rev Log: Move optimization to avoid redundant matching. Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp?rev=108140&r1=108139&r2=108140&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp Mon Jul 12 08:34:22 2010 @@ -1584,6 +1584,19 @@ if ((match(A, m_Not(m_Specific(B))) && match(D, m_Not(m_Specific(C))))) return BinaryOperator::CreateXor(C, B); + + // ((A|B)&1)|(B&-2) -> (A&1) | B + if (match(A, m_Or(m_Value(V1), m_Specific(B))) || + match(A, m_Or(m_Specific(B), m_Value(V1)))) { + Instruction *Ret = FoldOrWithConstants(I, Op1, V1, B, C); + if (Ret) return Ret; + } + // (B&-2)|((A|B)&1) -> (A&1) | B + if (match(B, m_Or(m_Specific(A), m_Value(V1))) || + match(B, m_Or(m_Value(V1), m_Specific(A)))) { + Instruction *Ret = FoldOrWithConstants(I, Op0, A, V1, D); + if (Ret) return Ret; + } } // (X >> Z) | (Y >> Z) -> (X|Y) >> Z for all shifts. @@ -1599,19 +1612,6 @@ } } - // ((A|B)&1)|(B&-2) -> (A&1) | B - if (match(Op0, m_And(m_Or(m_Value(A), m_Value(B)), m_Value(C))) || - match(Op0, m_And(m_Value(C), m_Or(m_Value(A), m_Value(B))))) { - Instruction *Ret = FoldOrWithConstants(I, Op1, A, B, C); - if (Ret) return Ret; - } - // (B&-2)|((A|B)&1) -> (A&1) | B - if (match(Op1, m_And(m_Or(m_Value(A), m_Value(B)), m_Value(C))) || - match(Op1, m_And(m_Value(C), m_Or(m_Value(A), m_Value(B))))) { - Instruction *Ret = FoldOrWithConstants(I, Op0, A, B, C); - if (Ret) return Ret; - } - // (~A | ~B) == (~(A & B)) - De Morgan's Law if (Value *Op0NotVal = dyn_castNotVal(Op0)) if (Value *Op1NotVal = dyn_castNotVal(Op1)) From wilsons at start.ca Mon Jul 12 08:35:55 2010 From: wilsons at start.ca (Stephen Wilson) Date: Mon, 12 Jul 2010 09:35:55 -0400 Subject: [llvm-commits] [PATCH] Support/ELF.h extensions In-Reply-To: (Stephen Wilson's message of "Sat, 10 Jul 2010 18:02:45 -0400") References: Message-ID: An embedded and charset-unspecified text was scrubbed... Name: elf.patch Url: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100712/8174ecec/attachment.pl From benny.kra at googlemail.com Mon Jul 12 08:44:00 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Mon, 12 Jul 2010 13:44:00 -0000 Subject: [llvm-commits] [llvm] r108141 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineAndOrXor.cpp test/Transforms/InstCombine/or.ll test/Transforms/InstCombine/xor2.ll Message-ID: <20100712134400.A751A2A6C12C@llvm.org> Author: d0k Date: Mon Jul 12 08:44:00 2010 New Revision: 108141 URL: http://llvm.org/viewvc/llvm-project?rev=108141&view=rev Log: Reapply 108136 with an ugly pasto fixed. Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp llvm/trunk/test/Transforms/InstCombine/or.ll llvm/trunk/test/Transforms/InstCombine/xor2.ll Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp?rev=108141&r1=108140&r2=108141&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp Mon Jul 12 08:44:00 2010 @@ -1597,6 +1597,14 @@ Instruction *Ret = FoldOrWithConstants(I, Op0, A, V1, D); if (Ret) return Ret; } + + // (A & ~C) | (B & C) -> ((B ^ A) & C) ^ A + if (Op0->hasOneUse() && Op1->hasOneUse() && + match(C, m_Not(m_Specific(D)))) { + Value *Xor = Builder->CreateXor(B, A, "xor"); + Value *And = Builder->CreateAnd(Xor, D, "and"); + return BinaryOperator::CreateXor(And, A); + } } // (X >> Z) | (Y >> Z) -> (X|Y) >> Z for all shifts. @@ -1920,6 +1928,15 @@ return BinaryOperator::CreateAnd(NewOp, X); } } + + // (A & ~C) ^ (B & C) -> ((B ^ A) & C) ^ A + if (Op0->hasOneUse() && Op1->hasOneUse() && + match(Op0I, m_And(m_Value(A), m_Not(m_Value(D)))) && + match(Op1I, m_And(m_Value(B), m_Specific(D)))) { + Value *Xor = Builder->CreateXor(B, A, "xor"); + Value *And = Builder->CreateAnd(Xor, D, "and"); + return BinaryOperator::CreateXor(And, A); + } } // (icmp1 A, B) ^ (icmp2 A, B) --> (icmp3 A, B) Modified: llvm/trunk/test/Transforms/InstCombine/or.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/or.ll?rev=108141&r1=108140&r2=108141&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/or.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/or.ll Mon Jul 12 08:44:00 2010 @@ -350,3 +350,16 @@ ; CHECK: or <4 x i32> %and.i, %and.i129 } +; PR6773 +define i32 @test33(i32 %x, i32 %y, i32 %z) nounwind readnone { + %and = and i32 %y, %x + %not = xor i32 %x, -1 + %and2 = and i32 %z, %not + %or = or i32 %and2, %and + ret i32 %or +; CHECK: @test33 +; CHECK-NEXT: xor i32 +; CHECK-NEXT: and i32 +; CHECK-NEXT: xor i32 +; CHECK-NEXT: ret i32 +} Modified: llvm/trunk/test/Transforms/InstCombine/xor2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/xor2.ll?rev=108141&r1=108140&r2=108141&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/xor2.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/xor2.ll Mon Jul 12 08:44:00 2010 @@ -51,3 +51,17 @@ ; CHECK: %1 = ashr i32 %A, %B ; CHECK: ret i32 %1 } + +; PR6773 +define i32 @test5(i32 %x, i32 %y, i32 %z) nounwind readnone { + %and = and i32 %y, %x + %not = xor i32 %x, -1 + %and2 = and i32 %z, %not + %xor = xor i32 %and2, %and + ret i32 %xor +; CHECK: @test5 +; CHECK-NEXT: xor i32 +; CHECK-NEXT: and i32 +; CHECK-NEXT: xor i32 +; CHECK-NEXT: ret i32 +} From ggreif at gmail.com Mon Jul 12 09:10:24 2010 From: ggreif at gmail.com (Gabor Greif) Date: Mon, 12 Jul 2010 14:10:24 -0000 Subject: [llvm-commits] [llvm] r108142 - /llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Message-ID: <20100712141024.71EF62A6C12C@llvm.org> Author: ggreif Date: Mon Jul 12 09:10:24 2010 New Revision: 108142 URL: http://llvm.org/viewvc/llvm-project?rev=108142&view=rev Log: cache results of operator* Modified: llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Modified: llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp?rev=108142&r1=108141&r2=108142&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Mon Jul 12 09:10:24 2010 @@ -289,14 +289,15 @@ // Perhaps getConstantOnEdge should be smart enough to do this? for (pred_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI) { + BasicBlock *P = *PI; // If the value is known by LazyValueInfo to be a constant in a // predecessor, use that information to try to thread this block. - Constant *PredCst = LVI->getConstantOnEdge(V, *PI, BB); + Constant *PredCst = LVI->getConstantOnEdge(V, P, BB); if (PredCst == 0 || (!isa(PredCst) && !isa(PredCst))) continue; - Result.push_back(std::make_pair(dyn_cast(PredCst), *PI)); + Result.push_back(std::make_pair(dyn_cast(PredCst), P)); } return !Result.empty(); @@ -421,20 +422,21 @@ (!isa(Cmp->getOperand(0)) || cast(Cmp->getOperand(0))->getParent() != BB)) { Constant *RHSCst = cast(Cmp->getOperand(1)); - + for (pred_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI) { + BasicBlock *P = *PI; // If the value is known by LazyValueInfo to be a constant in a // predecessor, use that information to try to thread this block. LazyValueInfo::Tristate Res = LVI->getPredicateOnEdge(Cmp->getPredicate(), Cmp->getOperand(0), - RHSCst, *PI, BB); + RHSCst, P, BB); if (Res == LazyValueInfo::Unknown) continue; Constant *ResC = ConstantInt::get(Cmp->getType(), Res); - Result.push_back(std::make_pair(cast(ResC), *PI)); + Result.push_back(std::make_pair(cast(ResC), P)); } - + return !Result.empty(); } } @@ -550,18 +552,22 @@ (CondInst == 0 || CondInst->getParent() != BB)) { // Non-local definition. pred_iterator PI = pred_begin(BB), E = pred_end(BB); if (isa(BB->getTerminator())) { - for (; PI != E; ++PI) - if (BranchInst *PBI = dyn_cast((*PI)->getTerminator())) + for (; PI != E; ++PI) { + BasicBlock *P = *PI; + if (BranchInst *PBI = dyn_cast(P->getTerminator())) if (PBI->isConditional() && PBI->getCondition() == Condition && - ProcessBranchOnDuplicateCond(*PI, BB)) + ProcessBranchOnDuplicateCond(P, BB)) return true; + } } else { assert(isa(BB->getTerminator()) && "Unknown jump terminator"); - for (; PI != E; ++PI) - if (SwitchInst *PSI = dyn_cast((*PI)->getTerminator())) + for (; PI != E; ++PI) { + BasicBlock *P = *PI; + if (SwitchInst *PSI = dyn_cast(P->getTerminator())) if (PSI->getCondition() == Condition && - ProcessSwitchOnDuplicateCond(*PI, BB)) + ProcessSwitchOnDuplicateCond(P, BB)) return true; + } } } @@ -581,19 +587,21 @@ // If we have a comparison, loop over the predecessors to see if there is // a condition with a lexically identical value. pred_iterator PI = pred_begin(BB), E = pred_end(BB); - for (; PI != E; ++PI) - if (BranchInst *PBI = dyn_cast((*PI)->getTerminator())) - if (PBI->isConditional() && *PI != BB) { + for (; PI != E; ++PI) { + BasicBlock *P = *PI; + if (BranchInst *PBI = dyn_cast(P->getTerminator())) + if (PBI->isConditional() && P != BB) { if (CmpInst *CI = dyn_cast(PBI->getCondition())) { if (CI->getOperand(0) == CondCmp->getOperand(0) && CI->getOperand(1) == CondCmp->getOperand(1) && CI->getPredicate() == CondCmp->getPredicate()) { // TODO: Could handle things like (x != 4) --> (x == 17) - if (ProcessBranchOnDuplicateCond(*PI, BB)) + if (ProcessBranchOnDuplicateCond(P, BB)) return true; } } } + } } } @@ -882,12 +890,13 @@ // Add all the unavailable predecessors to the PredsToSplit list. for (pred_iterator PI = pred_begin(LoadBB), PE = pred_end(LoadBB); PI != PE; ++PI) { + BasicBlock *P = *PI; // If the predecessor is an indirect goto, we can't split the edge. - if (isa((*PI)->getTerminator())) + if (isa(P->getTerminator())) return false; - if (!AvailablePredSet.count(*PI)) - PredsToSplit.push_back(*PI); + if (!AvailablePredSet.count(P)) + PredsToSplit.push_back(P); } // Split them out to their own block. @@ -920,11 +929,12 @@ // have multiple entries here. for (pred_iterator PI = pred_begin(LoadBB), E = pred_end(LoadBB); PI != E; ++PI) { + BasicBlock *P = *PI; AvailablePredsTy::iterator I = std::lower_bound(AvailablePreds.begin(), AvailablePreds.end(), - std::make_pair(*PI, (Value*)0)); + std::make_pair(P, (Value*)0)); - assert(I != AvailablePreds.end() && I->first == *PI && + assert(I != AvailablePreds.end() && I->first == P && "Didn't find entry for predecessor!"); PN->addIncoming(I->second, I->first); From ggreif at gmail.com Mon Jul 12 09:12:11 2010 From: ggreif at gmail.com (Gabor Greif) Date: Mon, 12 Jul 2010 14:12:11 -0000 Subject: [llvm-commits] [llvm] r108143 - /llvm/trunk/lib/Transforms/IPO/LowerSetJmp.cpp Message-ID: <20100712141211.A33B42A6C12C@llvm.org> Author: ggreif Date: Mon Jul 12 09:12:11 2010 New Revision: 108143 URL: http://llvm.org/viewvc/llvm-project?rev=108143&view=rev Log: cache results of operator* Modified: llvm/trunk/lib/Transforms/IPO/LowerSetJmp.cpp Modified: llvm/trunk/lib/Transforms/IPO/LowerSetJmp.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/LowerSetJmp.cpp?rev=108143&r1=108142&r2=108143&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/LowerSetJmp.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/LowerSetJmp.cpp Mon Jul 12 09:12:11 2010 @@ -406,12 +406,14 @@ // Loop over all of the uses of instruction. If any of them are after the // call, "spill" the value to the stack. for (Value::use_iterator UI = II->use_begin(), E = II->use_end(); - UI != E; ++UI) - if (cast(*UI)->getParent() != ABlock || - InstrsAfterCall.count(cast(*UI))) { + UI != E; ++UI) { + User *U = *UI; + if (cast(U)->getParent() != ABlock || + InstrsAfterCall.count(cast(U))) { DemoteRegToStack(*II); break; } + } InstrsAfterCall.clear(); // Change the setjmp call into a branch statement. We'll remove the From ggreif at gmail.com Mon Jul 12 09:13:15 2010 From: ggreif at gmail.com (Gabor Greif) Date: Mon, 12 Jul 2010 14:13:15 -0000 Subject: [llvm-commits] [llvm] r108144 - /llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp Message-ID: <20100712141315.733C12A6C12C@llvm.org> Author: ggreif Date: Mon Jul 12 09:13:15 2010 New Revision: 108144 URL: http://llvm.org/viewvc/llvm-project?rev=108144&view=rev Log: cache result of operator* Modified: llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp Modified: llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp?rev=108144&r1=108143&r2=108144&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp Mon Jul 12 09:13:15 2010 @@ -1600,13 +1600,15 @@ GVElType->isFloatingPointTy() || GVElType->isPointerTy() || GVElType->isVectorTy()) return false; - + // Walk the use list of the global seeing if all the uses are load or store. // If there is anything else, bail out. - for (Value::use_iterator I = GV->use_begin(), E = GV->use_end(); I != E; ++I) - if (!isa(I) && !isa(I)) + for (Value::use_iterator I = GV->use_begin(), E = GV->use_end(); I != E; ++I){ + User *U = *I; + if (!isa(U) && !isa(U)) return false; - + } + DEBUG(dbgs() << " *** SHRINKING TO BOOL: " << *GV); // Create the new global, initializing it to false. From ggreif at gmail.com Mon Jul 12 09:14:03 2010 From: ggreif at gmail.com (Gabor Greif) Date: Mon, 12 Jul 2010 14:14:03 -0000 Subject: [llvm-commits] [llvm] r108145 - /llvm/trunk/lib/Transforms/IPO/IPConstantPropagation.cpp Message-ID: <20100712141403.455302A6C12C@llvm.org> Author: ggreif Date: Mon Jul 12 09:14:03 2010 New Revision: 108145 URL: http://llvm.org/viewvc/llvm-project?rev=108145&view=rev Log: cache result of operator* Modified: llvm/trunk/lib/Transforms/IPO/IPConstantPropagation.cpp Modified: llvm/trunk/lib/Transforms/IPO/IPConstantPropagation.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/IPConstantPropagation.cpp?rev=108145&r1=108144&r2=108145&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/IPConstantPropagation.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/IPConstantPropagation.cpp Mon Jul 12 09:14:03 2010 @@ -85,15 +85,16 @@ unsigned NumNonconstant = 0; for (Value::use_iterator UI = F.use_begin(), E = F.use_end(); UI != E; ++UI) { + User *U = *UI; // Ignore blockaddress uses. - if (isa(*UI)) continue; + if (isa(U)) continue; // Used by a non-instruction, or not the callee of a function, do not // transform. - if (!isa(*UI) && !isa(*UI)) + if (!isa(U) && !isa(U)) return false; - CallSite CS = CallSite::get(cast(*UI)); + CallSite CS = CallSite::get(cast(U)); if (!CS.isCallee(UI)) return false; From ggreif at gmail.com Mon Jul 12 09:15:10 2010 From: ggreif at gmail.com (Gabor Greif) Date: Mon, 12 Jul 2010 14:15:10 -0000 Subject: [llvm-commits] [llvm] r108146 - /llvm/trunk/lib/Transforms/IPO/ArgumentPromotion.cpp Message-ID: <20100712141510.E38082A6C12C@llvm.org> Author: ggreif Date: Mon Jul 12 09:15:10 2010 New Revision: 108146 URL: http://llvm.org/viewvc/llvm-project?rev=108146&view=rev Log: cache result of operator* Modified: llvm/trunk/lib/Transforms/IPO/ArgumentPromotion.cpp Modified: llvm/trunk/lib/Transforms/IPO/ArgumentPromotion.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/ArgumentPromotion.cpp?rev=108146&r1=108145&r2=108146&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/ArgumentPromotion.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/ArgumentPromotion.cpp Mon Jul 12 09:15:10 2010 @@ -360,19 +360,20 @@ IndicesVector Operands; for (Value::use_iterator UI = Arg->use_begin(), E = Arg->use_end(); UI != E; ++UI) { + User *U = *UI; Operands.clear(); - if (LoadInst *LI = dyn_cast(*UI)) { + if (LoadInst *LI = dyn_cast(U)) { if (LI->isVolatile()) return false; // Don't hack volatile loads Loads.push_back(LI); // Direct loads are equivalent to a GEP with a zero index and then a load. Operands.push_back(0); - } else if (GetElementPtrInst *GEP = dyn_cast(*UI)) { + } else if (GetElementPtrInst *GEP = dyn_cast(U)) { if (GEP->use_empty()) { // Dead GEP's cause trouble later. Just remove them if we run into // them. getAnalysis().deleteValue(GEP); GEP->eraseFromParent(); - // TODO: This runs the above loop over and over again for dead GEPS + // TODO: This runs the above loop over and over again for dead GEPs // Couldn't we just do increment the UI iterator earlier and erase the // use? return isSafeToPromoteArgument(Arg, isByVal); @@ -452,12 +453,14 @@ // Now check every path from the entry block to the load for transparency. // To do this, we perform a depth first search on the inverse CFG from the // loading block. - for (pred_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI) + for (pred_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI) { + BasicBlock *P = *PI; for (idf_ext_iterator > - I = idf_ext_begin(*PI, TranspBlocks), - E = idf_ext_end(*PI, TranspBlocks); I != E; ++I) + I = idf_ext_begin(P, TranspBlocks), + E = idf_ext_end(P, TranspBlocks); I != E; ++I) if (AA.canBasicBlockModify(**I, Arg, LoadSize)) return false; + } } // If the path from the entry of the function to each load is free of From ggreif at gmail.com Mon Jul 12 09:15:58 2010 From: ggreif at gmail.com (Gabor Greif) Date: Mon, 12 Jul 2010 14:15:58 -0000 Subject: [llvm-commits] [llvm] r108147 - /llvm/trunk/lib/Transforms/InstCombine/InstCombinePHI.cpp Message-ID: <20100712141558.575882A6C12C@llvm.org> Author: ggreif Date: Mon Jul 12 09:15:58 2010 New Revision: 108147 URL: http://llvm.org/viewvc/llvm-project?rev=108147&view=rev Log: cache result of operator* Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombinePHI.cpp Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombinePHI.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombinePHI.cpp?rev=108147&r1=108146&r2=108147&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombinePHI.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombinePHI.cpp Mon Jul 12 09:15:58 2010 @@ -230,8 +230,9 @@ bool isAddressTaken = false; for (Value::use_iterator UI = AI->use_begin(), E = AI->use_end(); UI != E; ++UI) { - if (isa(UI)) continue; - if (StoreInst *SI = dyn_cast(*UI)) { + User *U = *UI; + if (isa(U)) continue; + if (StoreInst *SI = dyn_cast(U)) { // If storing TO the alloca, then the address isn't taken. if (SI->getOperand(1) == AI) continue; } From espindola at google.com Mon Jul 12 09:27:36 2010 From: espindola at google.com (Rafael Espindola) Date: Mon, 12 Jul 2010 10:27:36 -0400 Subject: [llvm-commits] [PATCH] Support/ELF.h extensions In-Reply-To: References: Message-ID: On 10 July 2010 18:02, Stephen Wilson wrote: > Greetings! > > The following patch adds a few magic constants and structures to > Support/ELF.h. ?In particular, it extends support for the ELF 64 bit > format. > > Note this file is not heavily used in LLVM or Clang AFAICT. ?These are > minimal extensions needed for LLDB elf parsing. ?With this change both > projects can rely on the same file, eliminating a local version within > LLDB. > On linux I also have EI_OSABI 7 EI_ABIVERSION 8 EI_PAD 9 Not sure if those are important for us now. > Could someone look this over and, if OK, commit on my behalf? I think the patch is OK, but not sure I can approve it. > > Many thanks! > Steve > Cheers, -- Rafael ?vila de Esp?ndola From benny.kra at googlemail.com Mon Jul 12 09:42:04 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Mon, 12 Jul 2010 14:42:04 -0000 Subject: [llvm-commits] [llvm] r108148 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineAndOrXor.cpp test/Transforms/InstCombine/or.ll test/Transforms/InstCombine/xor2.ll Message-ID: <20100712144204.564692A6C12C@llvm.org> Author: d0k Date: Mon Jul 12 09:42:04 2010 New Revision: 108148 URL: http://llvm.org/viewvc/llvm-project?rev=108148&view=rev Log: Revert r108141 again, sigh. Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp llvm/trunk/test/Transforms/InstCombine/or.ll llvm/trunk/test/Transforms/InstCombine/xor2.ll Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp?rev=108148&r1=108147&r2=108148&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp Mon Jul 12 09:42:04 2010 @@ -1597,14 +1597,6 @@ Instruction *Ret = FoldOrWithConstants(I, Op0, A, V1, D); if (Ret) return Ret; } - - // (A & ~C) | (B & C) -> ((B ^ A) & C) ^ A - if (Op0->hasOneUse() && Op1->hasOneUse() && - match(C, m_Not(m_Specific(D)))) { - Value *Xor = Builder->CreateXor(B, A, "xor"); - Value *And = Builder->CreateAnd(Xor, D, "and"); - return BinaryOperator::CreateXor(And, A); - } } // (X >> Z) | (Y >> Z) -> (X|Y) >> Z for all shifts. @@ -1928,15 +1920,6 @@ return BinaryOperator::CreateAnd(NewOp, X); } } - - // (A & ~C) ^ (B & C) -> ((B ^ A) & C) ^ A - if (Op0->hasOneUse() && Op1->hasOneUse() && - match(Op0I, m_And(m_Value(A), m_Not(m_Value(D)))) && - match(Op1I, m_And(m_Value(B), m_Specific(D)))) { - Value *Xor = Builder->CreateXor(B, A, "xor"); - Value *And = Builder->CreateAnd(Xor, D, "and"); - return BinaryOperator::CreateXor(And, A); - } } // (icmp1 A, B) ^ (icmp2 A, B) --> (icmp3 A, B) Modified: llvm/trunk/test/Transforms/InstCombine/or.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/or.ll?rev=108148&r1=108147&r2=108148&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/or.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/or.ll Mon Jul 12 09:42:04 2010 @@ -350,16 +350,3 @@ ; CHECK: or <4 x i32> %and.i, %and.i129 } -; PR6773 -define i32 @test33(i32 %x, i32 %y, i32 %z) nounwind readnone { - %and = and i32 %y, %x - %not = xor i32 %x, -1 - %and2 = and i32 %z, %not - %or = or i32 %and2, %and - ret i32 %or -; CHECK: @test33 -; CHECK-NEXT: xor i32 -; CHECK-NEXT: and i32 -; CHECK-NEXT: xor i32 -; CHECK-NEXT: ret i32 -} Modified: llvm/trunk/test/Transforms/InstCombine/xor2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/xor2.ll?rev=108148&r1=108147&r2=108148&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/xor2.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/xor2.ll Mon Jul 12 09:42:04 2010 @@ -51,17 +51,3 @@ ; CHECK: %1 = ashr i32 %A, %B ; CHECK: ret i32 %1 } - -; PR6773 -define i32 @test5(i32 %x, i32 %y, i32 %z) nounwind readnone { - %and = and i32 %y, %x - %not = xor i32 %x, -1 - %and2 = and i32 %z, %not - %xor = xor i32 %and2, %and - ret i32 %xor -; CHECK: @test5 -; CHECK-NEXT: xor i32 -; CHECK-NEXT: and i32 -; CHECK-NEXT: xor i32 -; CHECK-NEXT: ret i32 -} From wilsons at start.ca Mon Jul 12 09:56:10 2010 From: wilsons at start.ca (Stephen Wilson) Date: Mon, 12 Jul 2010 10:56:10 -0400 Subject: [llvm-commits] [PATCH] Support/ELF.h extensions In-Reply-To: (Rafael Espindola's message of "Mon, 12 Jul 2010 10:27:36 -0400") References: Message-ID: An embedded and charset-unspecified text was scrubbed... Name: elf2.patch Url: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100712/3ae37775/attachment.pl From sabre at nondot.org Mon Jul 12 10:28:33 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 12 Jul 2010 08:28:33 -0700 Subject: [llvm-commits] [llvm] r108113 - in /llvm/trunk: lib/Analysis/ConstantFolding.cpp test/Transforms/InstCombine/load3.ll In-Reply-To: References: <20100712002251.D3AE92A6C12C@llvm.org> Message-ID: On Jul 11, 2010, at 11:49 PM, Chandler Carruth wrote: >>> +++ llvm/trunk/lib/Analysis/ConstantFolding.cpp Sun Jul 11 19:22:51 2010 >>> @@ -436,8 +436,10 @@ >>> unsigned StrLen = Str.length(); >>> const Type *Ty = cast(CE->getType())->getElementType(); >>> unsigned NumBits = Ty->getPrimitiveSizeInBits(); >>> - // Replace LI with immediate integer store. >>> - if ((NumBits >> 3) == StrLen + 1) { >>> + // Replace load with immediate integer if the result is an integer or fp >>> + // value. >>> + if ((NumBits >> 3) == StrLen + 1 && (NumBits & 7) == 0 && >>> + isa(Ty) || Ty->isFloatingPointTy()) { >> >> GCC warns about the && and || operators being used w/o parentheses. >> Sometimes, this is just pedantic, but did you mean to have ()s around >> the 'isa(Ty) || Ty->isFloatingPointTy()' here? As it >> stands, won't an fp value bypass the checks on NumBits? > > After sanity checking with Nick on IRC, I submitted a patch adding > these parens in r 108129. Reading the code made me much more confident > that this was just an oversight. Let me know if I broke anything! Yep, that was the right fix, thanks! From sabre at nondot.org Mon Jul 12 10:29:30 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 12 Jul 2010 08:29:30 -0700 Subject: [llvm-commits] [llvm] r108109 - /llvm/trunk/lib/CodeGen/MachineLICM.cpp In-Reply-To: <5470C984-D21B-4C3F-860C-D7506AFBFAAB@apple.com> References: <20100712000035.393982A6C12C@llvm.org> <5470C984-D21B-4C3F-860C-D7506AFBFAAB@apple.com> Message-ID: On Jul 12, 2010, at 12:57 AM, Evan Cheng wrote: >> change machinelicm to use MachineInstr::isSafeToMove. No >> intended functionality change. >> >> The avoidance of hoistiing implicitdef seems wrong though. > > It's not. We want to avoid creating implicitdef with no trivial live intervals. The trivial ones will be converted to undef machine operands which do not take up registers. Why? The register allocator treats them specially just so they don't use a register (according to Jakob). -Chris From gohman at apple.com Mon Jul 12 10:46:30 2010 From: gohman at apple.com (Dan Gohman) Date: Mon, 12 Jul 2010 15:46:30 -0000 Subject: [llvm-commits] [llvm] r108149 - /llvm/trunk/lib/Target/X86/X86FastISel.cpp Message-ID: <20100712154630.94EA82A6C12C@llvm.org> Author: djg Date: Mon Jul 12 10:46:30 2010 New Revision: 108149 URL: http://llvm.org/viewvc/llvm-project?rev=108149&view=rev Log: Don't fast-isel an x87 comparison opcode, as fast-isel doesn't support branching on x87 comparisons yet. This fixes PR7624. Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=108149&r1=108148&r2=108149&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Mon Jul 12 10:46:30 2010 @@ -798,8 +798,8 @@ case MVT::i16: return X86::CMP16rr; case MVT::i32: return X86::CMP32rr; case MVT::i64: return X86::CMP64rr; - case MVT::f32: return Subtarget->hasSSE1() ? X86::UCOMISSrr : X86::UCOM_Fpr32; - case MVT::f64: return Subtarget->hasSSE2() ? X86::UCOMISDrr : X86::UCOM_Fpr64; + case MVT::f32: return Subtarget->hasSSE1() ? X86::UCOMISSrr : 0; + case MVT::f64: return Subtarget->hasSSE2() ? X86::UCOMISDrr : 0; } } From ggreif at gmail.com Mon Jul 12 10:48:26 2010 From: ggreif at gmail.com (Gabor Greif) Date: Mon, 12 Jul 2010 15:48:26 -0000 Subject: [llvm-commits] [llvm] r108150 - /llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp Message-ID: <20100712154826.9CE642A6C12C@llvm.org> Author: ggreif Date: Mon Jul 12 10:48:26 2010 New Revision: 108150 URL: http://llvm.org/viewvc/llvm-project?rev=108150&view=rev Log: cache result of operator* Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp?rev=108150&r1=108149&r2=108150&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp Mon Jul 12 10:48:26 2010 @@ -525,17 +525,20 @@ // Determine whether Dest has exactly two predecessors and, if so, compute // the other predecessor. pred_iterator PI = pred_begin(DestBB); + BasicBlock *P = *PI; BasicBlock *OtherBB = 0; - if (*PI != StoreBB) - OtherBB = *PI; - ++PI; - if (PI == pred_end(DestBB)) + + if (P != StoreBB) + OtherBB = P; + + if (++PI == pred_end(DestBB)) return false; - if (*PI != StoreBB) { + P = *PI; + if (P != StoreBB) { if (OtherBB) return false; - OtherBB = *PI; + OtherBB = P; } if (++PI != pred_end(DestBB)) return false; From clattner at apple.com Mon Jul 12 10:49:20 2010 From: clattner at apple.com (Chris Lattner) Date: Mon, 12 Jul 2010 08:49:20 -0700 Subject: [llvm-commits] [PATCH] Support/ELF.h extensions In-Reply-To: References: Message-ID: On Jul 12, 2010, at 7:27 AM, Rafael Espindola wrote: > On 10 July 2010 18:02, Stephen Wilson wrote: >> Greetings! >> >> The following patch adds a few magic constants and structures to >> Support/ELF.h. In particular, it extends support for the ELF 64 bit >> format. >> >> Note this file is not heavily used in LLVM or Clang AFAICT. These are >> minimal extensions needed for LLDB elf parsing. With this change both >> projects can rely on the same file, eliminating a local version within >> LLDB. >> > > On linux I also have > > EI_OSABI 7 > EI_ABIVERSION 8 > EI_PAD 9 > > Not sure if those are important for us now. > >> Could someone look this over and, if OK, commit on my behalf? > > I think the patch is OK, but not sure I can approve it. Anyone with commit access can approve it :) -Chris From clattner at apple.com Mon Jul 12 10:52:31 2010 From: clattner at apple.com (Chris Lattner) Date: Mon, 12 Jul 2010 08:52:31 -0700 Subject: [llvm-commits] [PATCH] Support/ELF.h extensions In-Reply-To: References: Message-ID: <3008EE29-F5B7-4499-831F-B4DE8E61573C@apple.com> On Jul 12, 2010, at 7:56 AM, Stephen Wilson wrote: > Hi Rafael, > > Rafael Espindola writes: > >> On 10 July 2010 18:02, Stephen Wilson wrote: >> On linux I also have >> >> EI_OSABI 7 >> EI_ABIVERSION 8 >> EI_PAD 9 >> >> Not sure if those are important for us now. > > Should probably be included for the sake of completeness. Updated patch > attached. A few stylistic updates: - unsigned char getFileClass () const { return e_ident[4]; } - unsigned char getDataEncoding () { return e_ident[5]; } + unsigned char getFileClass () const { return e_ident[EI_CLASS]; } + unsigned char getDataEncoding () { return e_ident[EI_DATA]; } Not your doing, but please don't put a space before argument lists: use getFileClass() instead of getFileClass () Likewise here: Elf64_Quarter e_shstrndx; + bool checkMagic () const { + return (memcmp (e_ident, ElfMagic, strlen (ElfMagic))) == 0; + } + unsigned char getFileClass () const { return e_ident[EI_CLASS]; } + unsigned char getDataEncoding () { return e_ident[EI_DATA]; } and in Elf64_Sym. Do you have commit access? If so, please commit with these tweaks. If not, please read the DeveloperPolicy.html document and send me the requested info (offline). Thanks Stephen! -Chris From dag at cray.com Mon Jul 12 10:54:34 2010 From: dag at cray.com (David A. Greene) Date: Mon, 12 Jul 2010 10:54:34 -0500 Subject: [llvm-commits] [llvm] r107996 - in /llvm/trunk: lib/Target/X86/AsmPrinter/X86ATTInstPrinter.h lib/Target/X86/AsmPrinter/X86IntelInstPrinter.h lib/Target/X86/X86InstrInfo.cpp lib/Target/X86/X86InstrInfo.td lib/Target/X86/X86InstrSSE.td lib/Target/X8... In-Reply-To: (Chris Lattner's message of "Sat, 10 Jul 2010 12:25:25 -0500") References: <20100709182743.E1E922A6C12C@llvm.org> Message-ID: Chris Lattner writes: > On Jul 9, 2010, at 2:36 PM, David A. Greene wrote: >> Chris, what's the best way to move forward? I've even got some block >> posts ready to explain all of these changes. > > Hi David, > > I don't have any strong opinions about this. Do your patches apply > cleanly to mainline? Since Bruno has been doing all his work in a > nice incremental style, I'd suggest working with him on any specific > patches you want to pull in. Bruno has mentioned that he thinks he > can implement AVX without reimplementing a lisp interpreter in tblgen, > which I was pleased to hear ;-) ;-) There's no reimplementation of lisp. Yes, one can implement AVX in the same way SSE1-4.2 were implemented but long term, it doesn't scale because patterns have to be repeated over and over for various element sizes and vector lengths. Every generation of SSE/AVX improvement basically doubles the pattern space. When Larrabee-type instructions begin appearing (and they will in some form, I believe), we're going to see yet another doubling. Actually two doublings if masks are included. The idea of my patches is to specify generic patterns and let TableGen handle generating all of the various combinations. I anticipate a quite long discussion about them and I believe there will be quite a few changes to the patches before they go in, but long term I believe it is the most maintainable approach. -Dave From benny.kra at googlemail.com Mon Jul 12 11:15:48 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Mon, 12 Jul 2010 16:15:48 -0000 Subject: [llvm-commits] [llvm] r108152 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineAndOrXor.cpp test/Transforms/InstCombine/or.ll Message-ID: <20100712161548.EB2A32A6C12C@llvm.org> Author: d0k Date: Mon Jul 12 11:15:48 2010 New Revision: 108152 URL: http://llvm.org/viewvc/llvm-project?rev=108152&view=rev Log: Reapply the "or" half of r108136, which seems to be less problematic. Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp llvm/trunk/test/Transforms/InstCombine/or.ll Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp?rev=108152&r1=108151&r2=108152&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp Mon Jul 12 11:15:48 2010 @@ -1597,6 +1597,14 @@ Instruction *Ret = FoldOrWithConstants(I, Op0, A, V1, D); if (Ret) return Ret; } + + // (A & ~D) | (B & D) -> ((B ^ A) & D) ^ A + if (Op0->hasOneUse() && Op1->hasOneUse() && + match(C, m_Not(m_Specific(D)))) { + Value *Xor = Builder->CreateXor(B, A, "xor"); + Value *And = Builder->CreateAnd(Xor, D, "and"); + return BinaryOperator::CreateXor(And, A); + } } // (X >> Z) | (Y >> Z) -> (X|Y) >> Z for all shifts. Modified: llvm/trunk/test/Transforms/InstCombine/or.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/or.ll?rev=108152&r1=108151&r2=108152&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/or.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/or.ll Mon Jul 12 11:15:48 2010 @@ -350,3 +350,16 @@ ; CHECK: or <4 x i32> %and.i, %and.i129 } +; PR6773 +define i32 @test33(i32 %x, i32 %y, i32 %z) nounwind readnone { + %and = and i32 %y, %x + %not = xor i32 %x, -1 + %and2 = and i32 %z, %not + %or = or i32 %and2, %and + ret i32 %or +; CHECK: @test33 +; CHECK-NEXT: xor i32 +; CHECK-NEXT: and i32 +; CHECK-NEXT: xor i32 +; CHECK-NEXT: ret i32 +} From benny.kra at googlemail.com Mon Jul 12 11:38:48 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Mon, 12 Jul 2010 16:38:48 -0000 Subject: [llvm-commits] [llvm] r108153 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineAndOrXor.cpp test/Transforms/InstCombine/or.ll Message-ID: <20100712163848.6EDA12A6C12C@llvm.org> Author: d0k Date: Mon Jul 12 11:38:48 2010 New Revision: 108153 URL: http://llvm.org/viewvc/llvm-project?rev=108153&view=rev Log: Nope, still breaks the release selfhost bots :( Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp llvm/trunk/test/Transforms/InstCombine/or.ll Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp?rev=108153&r1=108152&r2=108153&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp Mon Jul 12 11:38:48 2010 @@ -1597,14 +1597,6 @@ Instruction *Ret = FoldOrWithConstants(I, Op0, A, V1, D); if (Ret) return Ret; } - - // (A & ~D) | (B & D) -> ((B ^ A) & D) ^ A - if (Op0->hasOneUse() && Op1->hasOneUse() && - match(C, m_Not(m_Specific(D)))) { - Value *Xor = Builder->CreateXor(B, A, "xor"); - Value *And = Builder->CreateAnd(Xor, D, "and"); - return BinaryOperator::CreateXor(And, A); - } } // (X >> Z) | (Y >> Z) -> (X|Y) >> Z for all shifts. Modified: llvm/trunk/test/Transforms/InstCombine/or.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/or.ll?rev=108153&r1=108152&r2=108153&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/or.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/or.ll Mon Jul 12 11:38:48 2010 @@ -350,16 +350,3 @@ ; CHECK: or <4 x i32> %and.i, %and.i129 } -; PR6773 -define i32 @test33(i32 %x, i32 %y, i32 %z) nounwind readnone { - %and = and i32 %y, %x - %not = xor i32 %x, -1 - %and2 = and i32 %z, %not - %or = or i32 %and2, %and - ret i32 %or -; CHECK: @test33 -; CHECK-NEXT: xor i32 -; CHECK-NEXT: and i32 -; CHECK-NEXT: xor i32 -; CHECK-NEXT: ret i32 -} From wilsons at start.ca Mon Jul 12 11:46:21 2010 From: wilsons at start.ca (Stephen Wilson) Date: Mon, 12 Jul 2010 12:46:21 -0400 Subject: [llvm-commits] [PATCH] Support/ELF.h extensions In-Reply-To: <3008EE29-F5B7-4499-831F-B4DE8E61573C@apple.com> (Chris Lattner's message of "Mon, 12 Jul 2010 08:52:31 -0700") References: <3008EE29-F5B7-4499-831F-B4DE8E61573C@apple.com> Message-ID: Hi Chris, Chris Lattner writes: > A few stylistic updates: > > - unsigned char getFileClass () const { return e_ident[4]; } > - unsigned char getDataEncoding () { return e_ident[5]; } > + unsigned char getFileClass () const { return e_ident[EI_CLASS]; } > + unsigned char getDataEncoding () { return e_ident[EI_DATA]; } > > Not your doing, but please don't put a space before argument lists: use getFileClass() instead of getFileClass () > > Likewise here: > > Elf64_Quarter e_shstrndx; > + bool checkMagic () const { > + return (memcmp (e_ident, ElfMagic, strlen (ElfMagic))) == 0; > + } > + unsigned char getFileClass () const { return e_ident[EI_CLASS]; } > + unsigned char getDataEncoding () { return e_ident[EI_DATA]; } > OK. There are a few additional places in the file that require this format fix as well. Will apply. > and in Elf64_Sym. Do you have commit access? If so, please commit > with these tweaks. If not, please read the DeveloperPolicy.html > document and send me the requested info (offline). No, I do not have commit access. Details sent. > > Thanks Stephen! > > -Chris Thank you! Steve From daniel at zuster.org Mon Jul 12 12:10:01 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 12 Jul 2010 17:10:01 -0000 Subject: [llvm-commits] [llvm] r108154 - in /llvm/trunk: include/llvm/MC/MCParser/AsmLexer.h include/llvm/MC/MCParser/MCAsmLexer.h lib/MC/MCParser/AsmLexer.cpp lib/MC/MCParser/MCAsmLexer.cpp Message-ID: <20100712171001.1702A2A6C12C@llvm.org> Author: ddunbar Date: Mon Jul 12 12:10:00 2010 New Revision: 108154 URL: http://llvm.org/viewvc/llvm-project?rev=108154&view=rev Log: MC: Move getLoc() to MCAsmLexer(). Modified: llvm/trunk/include/llvm/MC/MCParser/AsmLexer.h llvm/trunk/include/llvm/MC/MCParser/MCAsmLexer.h llvm/trunk/lib/MC/MCParser/AsmLexer.cpp llvm/trunk/lib/MC/MCParser/MCAsmLexer.cpp Modified: llvm/trunk/include/llvm/MC/MCParser/AsmLexer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/AsmLexer.h?rev=108154&r1=108153&r2=108154&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCParser/AsmLexer.h (original) +++ llvm/trunk/include/llvm/MC/MCParser/AsmLexer.h Mon Jul 12 12:10:00 2010 @@ -33,8 +33,6 @@ const char *CurPtr; const MemoryBuffer *CurBuf; - const char *TokStart; - void operator=(const AsmLexer&); // DO NOT IMPLEMENT AsmLexer(const AsmLexer&); // DO NOT IMPLEMENT @@ -48,8 +46,6 @@ void setBuffer(const MemoryBuffer *buf, const char *ptr = NULL); - SMLoc getLoc() const; - StringRef LexUntilEndOfStatement(); bool isAtStartOfComment(char Char); Modified: llvm/trunk/include/llvm/MC/MCParser/MCAsmLexer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/MCAsmLexer.h?rev=108154&r1=108153&r2=108154&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCParser/MCAsmLexer.h (original) +++ llvm/trunk/include/llvm/MC/MCParser/MCAsmLexer.h Mon Jul 12 12:10:00 2010 @@ -121,6 +121,8 @@ MCAsmLexer(const MCAsmLexer &); // DO NOT IMPLEMENT void operator=(const MCAsmLexer &); // DO NOT IMPLEMENT protected: // Can only create subclasses. + const char *TokStart; + MCAsmLexer(); virtual AsmToken LexToken() = 0; @@ -141,6 +143,9 @@ return CurTok = LexToken(); } + /// getLoc - Get the current source location. + SMLoc getLoc() const; + /// getTok - Get the current (last) lexed token. const AsmToken &getTok() { return CurTok; Modified: llvm/trunk/lib/MC/MCParser/AsmLexer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmLexer.cpp?rev=108154&r1=108153&r2=108154&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmLexer.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmLexer.cpp Mon Jul 12 12:10:00 2010 @@ -23,7 +23,6 @@ AsmLexer::AsmLexer(const MCAsmInfo &_MAI) : MAI(_MAI) { CurBuf = NULL; CurPtr = NULL; - TokStart = 0; } AsmLexer::~AsmLexer() { @@ -40,10 +39,6 @@ TokStart = 0; } -SMLoc AsmLexer::getLoc() const { - return SMLoc::getFromPointer(TokStart); -} - /// ReturnError - Set the error to the specified string at the specified /// location. This is defined to always return AsmToken::Error. AsmToken AsmLexer::ReturnError(const char *Loc, const std::string &Msg) { Modified: llvm/trunk/lib/MC/MCParser/MCAsmLexer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/MCAsmLexer.cpp?rev=108154&r1=108153&r2=108154&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/MCAsmLexer.cpp (original) +++ llvm/trunk/lib/MC/MCParser/MCAsmLexer.cpp Mon Jul 12 12:10:00 2010 @@ -12,12 +12,16 @@ using namespace llvm; -MCAsmLexer::MCAsmLexer() : CurTok(AsmToken::Error, StringRef()) { +MCAsmLexer::MCAsmLexer() : CurTok(AsmToken::Error, StringRef()), TokStart(0) { } MCAsmLexer::~MCAsmLexer() { } +SMLoc MCAsmLexer::getLoc() const { + return SMLoc::getFromPointer(TokStart); +} + SMLoc AsmToken::getLoc() const { return SMLoc::getFromPointer(Str.data()); } From daniel at zuster.org Mon Jul 12 12:18:45 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 12 Jul 2010 17:18:45 -0000 Subject: [llvm-commits] [llvm] r108155 - in /llvm/trunk: include/llvm/MC/MCParser/AsmParser.h include/llvm/MC/MCParser/MCAsmParser.h lib/MC/MCParser/AsmParser.cpp lib/MC/MCParser/MCAsmParser.cpp Message-ID: <20100712171845.D5A3D2A6C12C@llvm.org> Author: ddunbar Date: Mon Jul 12 12:18:45 2010 New Revision: 108155 URL: http://llvm.org/viewvc/llvm-project?rev=108155&view=rev Log: MC: Move AsmParser::TokError to MCAsmParser(). Modified: llvm/trunk/include/llvm/MC/MCParser/AsmParser.h llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h llvm/trunk/lib/MC/MCParser/AsmParser.cpp llvm/trunk/lib/MC/MCParser/MCAsmParser.cpp Modified: llvm/trunk/include/llvm/MC/MCParser/AsmParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/AsmParser.h?rev=108155&r1=108154&r2=108155&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCParser/AsmParser.h (original) +++ llvm/trunk/include/llvm/MC/MCParser/AsmParser.h Mon Jul 12 12:18:45 2010 @@ -96,8 +96,6 @@ MCSymbol *CreateSymbol(StringRef Name); bool ParseStatement(); - - bool TokError(const char *Msg); void PrintMessage(SMLoc Loc, const std::string &Msg, const char *Type) const; Modified: llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h?rev=108155&r1=108154&r2=108155&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h (original) +++ llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h Mon Jul 12 12:18:45 2010 @@ -28,7 +28,7 @@ void operator=(const MCAsmParser &); // DO NOT IMPLEMENT protected: // Can only create subclasses. MCAsmParser(); - + public: virtual ~MCAsmParser(); @@ -43,7 +43,7 @@ /// Msg. virtual void Warning(SMLoc L, const Twine &Msg) = 0; - /// Warning - Emit an error at the location \arg L, with the message \arg + /// Error - Emit an error at the location \arg L, with the message \arg /// Msg. /// /// \return The return value is always true, as an idiomatic convenience to @@ -53,10 +53,13 @@ /// Lex - Get the next AsmToken in the stream, possibly handling file /// inclusion first. virtual const AsmToken &Lex() = 0; - + /// getTok - Get the current AsmToken from the stream. const AsmToken &getTok(); - + + /// \brief Report an error at the current lexer location. + bool TokError(const char *Msg); + /// ParseExpression - Parse an arbitrary expression. /// /// @param Res - The value of the expression. The result is undefined @@ -64,7 +67,7 @@ /// @result - False on success. virtual bool ParseExpression(const MCExpr *&Res, SMLoc &EndLoc) = 0; bool ParseExpression(const MCExpr *&Res); - + /// ParseParenExpression - Parse an arbitrary expression, assuming that an /// initial '(' has already been consumed. /// Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=108155&r1=108154&r2=108155&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Mon Jul 12 12:18:45 2010 @@ -56,11 +56,6 @@ return true; } -bool AsmParser::TokError(const char *Msg) { - PrintMessage(Lexer.getLoc(), Msg, "error"); - return true; -} - void AsmParser::PrintMessage(SMLoc Loc, const std::string &Msg, const char *Type) const { SrcMgr.PrintMessage(Loc, Msg, Type); Modified: llvm/trunk/lib/MC/MCParser/MCAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/MCAsmParser.cpp?rev=108155&r1=108154&r2=108155&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/MCAsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/MCAsmParser.cpp Mon Jul 12 12:18:45 2010 @@ -8,6 +8,7 @@ //===----------------------------------------------------------------------===// #include "llvm/MC/MCParser/MCAsmParser.h" +#include "llvm/ADT/Twine.h" #include "llvm/MC/MCParser/MCAsmLexer.h" #include "llvm/MC/MCParser/MCParsedAsmOperand.h" #include "llvm/Support/SourceMgr.h" @@ -23,6 +24,11 @@ return getLexer().getTok(); } +bool MCAsmParser::TokError(const char *Msg) { + Error(getLexer().getLoc(), Msg); + return true; +} + bool MCAsmParser::ParseExpression(const MCExpr *&Res) { SMLoc L; return ParseExpression(Res, L); From bob.wilson at apple.com Mon Jul 12 12:26:26 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Mon, 12 Jul 2010 10:26:26 -0700 Subject: [llvm-commits] [patch] Fix va_arg for double and some cleanups In-Reply-To: References: <8F256730-8DB3-4855-86E0-38F60D7D148E@apple.com> <9A8F1803-7291-4665-95C5-BB0B5B7822A7@apple.com> <59A16583-103F-4DF9-A8A6-F512B76A44DF@apple.com> Message-ID: On Jul 9, 2010, at 3:25 PM, Rafael Espindola wrote: >> But it's not the stack pointer itself that you care about here, it's the >> alignment of whatever the prior argument was. So you really want to know >> "What's the least alignment of any argument?" That's why I thought >> getCallFrameTypeAlignment would work. If it's not returning the right >> value, that may be a bug. > > On IRC we agreed that we need yet another alignment type :-( > > The attached patch adds MinStackArgumentAlignment to > TargetLoweringInfo and uses that. I also extended the test a bit to > check that only the necessary alignment is added. Two minor comments: > @@ -1515,6 +1527,11 @@ private: > /// buffers > unsigned JumpBufAlignment; > > + /// MinStackArgumentAlignment - The minimum alginment that any argument typo: "alginment" > + /// on the stack needs to have. > + /// > + unsigned MinStackArgumentAlignment; > + > /// PrefLoopAlignment - The perferred loop alignment. > /// > unsigned PrefLoopAlignment; > @@ -5736,7 +5736,8 @@ void SelectionDAGBuilder::visitVAStart(const CallInst &I) { > void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { > SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(), > getRoot(), getValue(I.getOperand(0)), > - DAG.getSrcValue(I.getOperand(0))); > + DAG.getSrcValue(I.getOperand(0)), > + TLI.getTargetData()->getABITypeAlignment(I.getType())); width exceeds 80 columns > setValue(&I, V); > DAG.setRoot(V.getValue(1)); > } -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100712/05ff0761/attachment.html From daniel at zuster.org Mon Jul 12 12:27:45 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 12 Jul 2010 17:27:45 -0000 Subject: [llvm-commits] [llvm] r108158 - in /llvm/trunk: include/llvm/MC/MCParser/AsmParser.h include/llvm/MC/MCParser/MCAsmParserExtension.h include/llvm/Target/TargetAsmParser.h lib/MC/MCParser/AsmParser.cpp lib/MC/MCParser/CMakeLists.txt lib/MC/MCParser/MCAsmParserExtension.cpp Message-ID: <20100712172745.ECE172A6C12C@llvm.org> Author: ddunbar Date: Mon Jul 12 12:27:45 2010 New Revision: 108158 URL: http://llvm.org/viewvc/llvm-project?rev=108158&view=rev Log: MC: Add MCAsmParserExtension, a base class for all the target/object specific classes which want to extend the basic asm parser. Added: llvm/trunk/include/llvm/MC/MCParser/MCAsmParserExtension.h llvm/trunk/lib/MC/MCParser/MCAsmParserExtension.cpp Modified: llvm/trunk/include/llvm/MC/MCParser/AsmParser.h llvm/trunk/include/llvm/Target/TargetAsmParser.h llvm/trunk/lib/MC/MCParser/AsmParser.cpp llvm/trunk/lib/MC/MCParser/CMakeLists.txt Modified: llvm/trunk/include/llvm/MC/MCParser/AsmParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/AsmParser.h?rev=108158&r1=108157&r2=108158&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCParser/AsmParser.h (original) +++ llvm/trunk/include/llvm/MC/MCParser/AsmParser.h Mon Jul 12 12:27:45 2010 @@ -63,7 +63,6 @@ ~AsmParser(); bool Run(bool NoInitialTextSection, bool NoFinalize = false); - void AddDirectiveHandler(StringRef Directive, bool (AsmParser::*Handler)(StringRef, SMLoc)) { @@ -71,7 +70,7 @@ } public: TargetAsmParser &getTargetParser() const { return *TargetParser; } - void setTargetParser(TargetAsmParser &P) { TargetParser = &P; } + void setTargetParser(TargetAsmParser &P); /// @name MCAsmParser Interface /// { Added: llvm/trunk/include/llvm/MC/MCParser/MCAsmParserExtension.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/MCAsmParserExtension.h?rev=108158&view=auto ============================================================================== --- llvm/trunk/include/llvm/MC/MCParser/MCAsmParserExtension.h (added) +++ llvm/trunk/include/llvm/MC/MCParser/MCAsmParserExtension.h Mon Jul 12 12:27:45 2010 @@ -0,0 +1,65 @@ +//===-- llvm/MC/MCAsmParserExtension.h - Asm Parser Hooks -------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_MC_MCASMPARSEREXTENSION_H +#define LLVM_MC_MCASMPARSEREXTENSION_H + +#include "llvm/MC/MCParser/MCAsmParser.h" +#include "llvm/Support/SMLoc.h" + +namespace llvm { + +/// \brief Generic interface for extending the MCAsmParser, +/// which is implemented by target and object file assembly parser +/// implementations. +class MCAsmParserExtension { + MCAsmParserExtension(const MCAsmParserExtension &); // DO NOT IMPLEMENT + void operator=(const MCAsmParserExtension &); // DO NOT IMPLEMENT + + MCAsmParser *Parser; + +protected: + MCAsmParserExtension(); + +public: + virtual ~MCAsmParserExtension(); + + /// \brief Initialize the extension for parsing using the given \arg + /// Parser. The extension should use the AsmParser interfaces to register its + /// parsing routines. + virtual void Initialize(MCAsmParser &Parser); + + /// @name MCAsmParser Proxy Interfaces + /// @{ + + MCContext &getContext() { return getParser().getContext(); } + MCAsmLexer &getLexer() { return getParser().getLexer(); } + MCAsmParser &getParser() { return *Parser; } + MCStreamer &getStreamer() { return getParser().getStreamer(); } + void Warning(SMLoc L, const Twine &Msg) { + return getParser().Warning(L, Msg); + } + bool Error(SMLoc L, const Twine &Msg) { + return getParser().Error(L, Msg); + } + + const AsmToken &Lex() { return getParser().Lex(); } + + const AsmToken &getTok() { return getParser().getTok(); } + + bool TokError(const char *Msg) { + return getParser().TokError(Msg); + } + + /// @} +}; + +} // End llvm namespace + +#endif Modified: llvm/trunk/include/llvm/Target/TargetAsmParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetAsmParser.h?rev=108158&r1=108157&r2=108158&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetAsmParser.h (original) +++ llvm/trunk/include/llvm/Target/TargetAsmParser.h Mon Jul 12 12:27:45 2010 @@ -10,6 +10,8 @@ #ifndef LLVM_TARGET_TARGETPARSER_H #define LLVM_TARGET_TARGETPARSER_H +#include "llvm/MC/MCParser/MCAsmParserExtension.h" + namespace llvm { class MCInst; class StringRef; @@ -20,7 +22,7 @@ template class SmallVectorImpl; /// TargetAsmParser - Generic interface to target specific assembly parsers. -class TargetAsmParser { +class TargetAsmParser : public MCAsmParserExtension { TargetAsmParser(const TargetAsmParser &); // DO NOT IMPLEMENT void operator=(const TargetAsmParser &); // DO NOT IMPLEMENT protected: // Can only create subclasses. Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=108158&r1=108157&r2=108158&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Mon Jul 12 12:27:45 2010 @@ -47,6 +47,12 @@ AsmParser::~AsmParser() { } +void AsmParser::setTargetParser(TargetAsmParser &P) { + assert(!TargetParser && "Target parser is already initialized!"); + TargetParser = &P; + TargetParser->Initialize(*this); +} + void AsmParser::Warning(SMLoc L, const Twine &Msg) { PrintMessage(L, Msg.str(), "warning"); } Modified: llvm/trunk/lib/MC/MCParser/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/CMakeLists.txt?rev=108158&r1=108157&r2=108158&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/CMakeLists.txt (original) +++ llvm/trunk/lib/MC/MCParser/CMakeLists.txt Mon Jul 12 12:27:45 2010 @@ -3,5 +3,6 @@ AsmParser.cpp MCAsmLexer.cpp MCAsmParser.cpp + MCAsmParserExtension.cpp TargetAsmParser.cpp ) Added: llvm/trunk/lib/MC/MCParser/MCAsmParserExtension.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/MCAsmParserExtension.cpp?rev=108158&view=auto ============================================================================== --- llvm/trunk/lib/MC/MCParser/MCAsmParserExtension.cpp (added) +++ llvm/trunk/lib/MC/MCParser/MCAsmParserExtension.cpp Mon Jul 12 12:27:45 2010 @@ -0,0 +1,21 @@ +//===-- MCAsmParserExtension.cpp - Asm Parser Hooks -----------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "llvm/MC/MCParser/MCAsmParserExtension.h" +using namespace llvm; + +MCAsmParserExtension::MCAsmParserExtension() { +} + +MCAsmParserExtension::~MCAsmParserExtension() { +} + +void MCAsmParserExtension::Initialize(MCAsmParser &Parser) { + this->Parser = &Parser; +} From daniel at zuster.org Mon Jul 12 12:45:27 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 12 Jul 2010 17:45:27 -0000 Subject: [llvm-commits] [llvm] r108160 - /llvm/trunk/lib/MC/MCParser/AsmParser.cpp Message-ID: <20100712174527.7FD432A6C12C@llvm.org> Author: ddunbar Date: Mon Jul 12 12:45:27 2010 New Revision: 108160 URL: http://llvm.org/viewvc/llvm-project?rev=108160&view=rev Log: MC/AsmParser: Switch some directive parsing to use accessor methods. Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=108160&r1=108159&r2=108160&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Mon Jul 12 12:45:27 2010 @@ -1898,37 +1898,37 @@ bool AsmParser::ParseDirectiveFile(StringRef, SMLoc DirectiveLoc) { // FIXME: I'm not sure what this is. int64_t FileNumber = -1; - if (Lexer.is(AsmToken::Integer)) { + if (getLexer().is(AsmToken::Integer)) { FileNumber = getTok().getIntVal(); Lex(); - + if (FileNumber < 1) return TokError("file number less than one"); } - if (Lexer.isNot(AsmToken::String)) + if (getLexer().isNot(AsmToken::String)) return TokError("unexpected token in '.file' directive"); - + StringRef Filename = getTok().getString(); Filename = Filename.substr(1, Filename.size()-2); Lex(); - if (Lexer.isNot(AsmToken::EndOfStatement)) + if (getLexer().isNot(AsmToken::EndOfStatement)) return TokError("unexpected token in '.file' directive"); if (FileNumber == -1) - Out.EmitFileDirective(Filename); + getStreamer().EmitFileDirective(Filename); else - Out.EmitDwarfFileDirective(FileNumber, Filename); - + getStreamer().EmitDwarfFileDirective(FileNumber, Filename); + return false; } /// ParseDirectiveLine /// ::= .line [number] bool AsmParser::ParseDirectiveLine(StringRef, SMLoc DirectiveLoc) { - if (Lexer.isNot(AsmToken::EndOfStatement)) { - if (Lexer.isNot(AsmToken::Integer)) + if (getLexer().isNot(AsmToken::EndOfStatement)) { + if (getLexer().isNot(AsmToken::Integer)) return TokError("unexpected token in '.line' directive"); int64_t LineNumber = getTok().getIntVal(); @@ -1938,7 +1938,7 @@ // FIXME: Do something with the .line. } - if (Lexer.isNot(AsmToken::EndOfStatement)) + if (getLexer().isNot(AsmToken::EndOfStatement)) return TokError("unexpected token in '.line' directive"); return false; @@ -1948,7 +1948,7 @@ /// ParseDirectiveLoc /// ::= .loc number [number [number]] bool AsmParser::ParseDirectiveLoc(StringRef, SMLoc DirectiveLoc) { - if (Lexer.isNot(AsmToken::Integer)) + if (getLexer().isNot(AsmToken::Integer)) return TokError("unexpected token in '.loc' directive"); // FIXME: What are these fields? @@ -1957,16 +1957,16 @@ // FIXME: Validate file. Lex(); - if (Lexer.isNot(AsmToken::EndOfStatement)) { - if (Lexer.isNot(AsmToken::Integer)) + if (getLexer().isNot(AsmToken::EndOfStatement)) { + if (getLexer().isNot(AsmToken::Integer)) return TokError("unexpected token in '.loc' directive"); int64_t Param2 = getTok().getIntVal(); (void) Param2; Lex(); - if (Lexer.isNot(AsmToken::EndOfStatement)) { - if (Lexer.isNot(AsmToken::Integer)) + if (getLexer().isNot(AsmToken::EndOfStatement)) { + if (getLexer().isNot(AsmToken::Integer)) return TokError("unexpected token in '.loc' directive"); int64_t Param3 = getTok().getIntVal(); @@ -1977,7 +1977,7 @@ } } - if (Lexer.isNot(AsmToken::EndOfStatement)) + if (getLexer().isNot(AsmToken::EndOfStatement)) return TokError("unexpected token in '.file' directive"); return false; From daniel at zuster.org Mon Jul 12 12:54:38 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 12 Jul 2010 17:54:38 -0000 Subject: [llvm-commits] [llvm] r108161 - in /llvm/trunk: include/llvm/MC/MCParser/AsmParser.h include/llvm/MC/MCParser/MCAsmParser.h lib/MC/MCParser/AsmParser.cpp Message-ID: <20100712175438.628E62A6C12C@llvm.org> Author: ddunbar Date: Mon Jul 12 12:54:38 2010 New Revision: 108161 URL: http://llvm.org/viewvc/llvm-project?rev=108161&view=rev Log: MCAsmParser: Pull some directive handling out into a helper class, and change DirectiveMap to be based on MCAsmParserExtension. Modified: llvm/trunk/include/llvm/MC/MCParser/AsmParser.h llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h llvm/trunk/lib/MC/MCParser/AsmParser.cpp Modified: llvm/trunk/include/llvm/MC/MCParser/AsmParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/AsmParser.h?rev=108161&r1=108160&r2=108161&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCParser/AsmParser.h (original) +++ llvm/trunk/include/llvm/MC/MCParser/AsmParser.h Mon Jul 12 12:54:38 2010 @@ -26,6 +26,7 @@ namespace llvm { class AsmCond; class AsmToken; +class MCAsmParserExtension; class MCContext; class MCExpr; class MCInst; @@ -43,6 +44,7 @@ MCContext &Ctx; MCStreamer &Out; SourceMgr &SrcMgr; + MCAsmParserExtension *GenericParser; TargetAsmParser *TargetParser; /// This is the current buffer index we're lexing from as managed by the @@ -56,18 +58,20 @@ /// invoked after the directive identifier is read and is responsible for /// parsing and validating the rest of the directive. The handler is passed /// in the directive name and the location of the directive keyword. - StringMap DirectiveMap; + StringMap > DirectiveMap; public: AsmParser(const Target &T, SourceMgr &SM, MCContext &Ctx, MCStreamer &Out, const MCAsmInfo &MAI); ~AsmParser(); bool Run(bool NoInitialTextSection, bool NoFinalize = false); - - void AddDirectiveHandler(StringRef Directive, - bool (AsmParser::*Handler)(StringRef, SMLoc)) { - DirectiveMap[Directive] = Handler; + + void AddDirectiveHandler(MCAsmParserExtension *Object, + StringRef Directive, + DirectiveHandler Handler) { + DirectiveMap[Directive] = std::make_pair(Object, Handler); } + public: TargetAsmParser &getTargetParser() const { return *TargetParser; } void setTargetParser(TargetAsmParser &P); @@ -155,10 +159,6 @@ bool ParseDirectiveElse(SMLoc DirectiveLoc); // ".else" bool ParseDirectiveEndIf(SMLoc DirectiveLoc); // .endif - bool ParseDirectiveFile(StringRef, SMLoc DirectiveLoc); // ".file" - bool ParseDirectiveLine(StringRef, SMLoc DirectiveLoc); // ".line" - bool ParseDirectiveLoc(StringRef, SMLoc DirectiveLoc); // ".loc" - /// ParseEscapedString - Parse the current token as a string which may include /// escaped characters and return the string contents. bool ParseEscapedString(std::string &Data); Modified: llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h?rev=108161&r1=108160&r2=108161&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h (original) +++ llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h Mon Jul 12 12:54:38 2010 @@ -15,15 +15,21 @@ namespace llvm { class AsmToken; class MCAsmLexer; +class MCAsmParserExtension; class MCContext; class MCExpr; class MCStreamer; class SMLoc; +class StringRef; class Twine; /// MCAsmParser - Generic assembler parser interface, for use by target specific /// assembly parsers. class MCAsmParser { +public: + typedef bool (MCAsmParserExtension::*DirectiveHandler)(StringRef, SMLoc); + +private: MCAsmParser(const MCAsmParser &); // DO NOT IMPLEMENT void operator=(const MCAsmParser &); // DO NOT IMPLEMENT protected: // Can only create subclasses. @@ -32,11 +38,15 @@ public: virtual ~MCAsmParser(); + virtual void AddDirectiveHandler(MCAsmParserExtension *Object, + StringRef Directive, + DirectiveHandler Handler) = 0; + virtual MCAsmLexer &getLexer() = 0; virtual MCContext &getContext() = 0; - /// getSteamer - Return the output streamer for the assembler. + /// getStreamer - Return the output streamer for the assembler. virtual MCStreamer &getStreamer() = 0; /// Warning - Emit a warning at the location \arg L, with the message \arg Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=108161&r1=108160&r2=108161&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Mon Jul 12 12:54:38 2010 @@ -30,21 +30,48 @@ using namespace llvm; +namespace { + +/// \brief Generic implementations of directive handling, etc. which is shared +/// (or the default, at least) for all assembler parser. +class GenericAsmParser : public MCAsmParserExtension { +public: + GenericAsmParser() {} + + virtual void Initialize(MCAsmParser &Parser) { + // Call the base implementation. + this->MCAsmParserExtension::Initialize(Parser); + + // Debugging directives. + Parser.AddDirectiveHandler(this, ".file", MCAsmParser::DirectiveHandler( + &GenericAsmParser::ParseDirectiveFile)); + Parser.AddDirectiveHandler(this, ".line", MCAsmParser::DirectiveHandler( + &GenericAsmParser::ParseDirectiveLine)); + Parser.AddDirectiveHandler(this, ".loc", MCAsmParser::DirectiveHandler( + &GenericAsmParser::ParseDirectiveLoc)); + } + + bool ParseDirectiveFile(StringRef, SMLoc DirectiveLoc); // ".file" + bool ParseDirectiveLine(StringRef, SMLoc DirectiveLoc); // ".line" + bool ParseDirectiveLoc(StringRef, SMLoc DirectiveLoc); // ".loc" +}; + +} + enum { DEFAULT_ADDRSPACE = 0 }; AsmParser::AsmParser(const Target &T, SourceMgr &_SM, MCContext &_Ctx, MCStreamer &_Out, const MCAsmInfo &_MAI) - : Lexer(_MAI), Ctx(_Ctx), Out(_Out), SrcMgr(_SM), TargetParser(0), - CurBuffer(0) { + : Lexer(_MAI), Ctx(_Ctx), Out(_Out), SrcMgr(_SM), + GenericParser(new GenericAsmParser), TargetParser(0), CurBuffer(0) { Lexer.setBuffer(SrcMgr.getMemoryBuffer(CurBuffer)); - - // Debugging directives. - AddDirectiveHandler(".file", &AsmParser::ParseDirectiveFile); - AddDirectiveHandler(".line", &AsmParser::ParseDirectiveLine); - AddDirectiveHandler(".loc", &AsmParser::ParseDirectiveLoc); + + // Initialize the generic parser. + GenericParser->Initialize(*this); } AsmParser::~AsmParser() { + delete GenericParser; } void AsmParser::setTargetParser(TargetAsmParser &P) { @@ -787,11 +814,12 @@ if (IDVal == ".secure_log_reset") return ParseDirectiveDarwinSecureLogReset(IDLoc); - // Look up the handler in the handler table, - bool(AsmParser::*Handler)(StringRef, SMLoc) = DirectiveMap[IDVal]; - if (Handler) - return (this->*Handler)(IDVal, IDLoc); - + // Look up the handler in the handler table. + std::pair Handler = + DirectiveMap.lookup(IDVal); + if (Handler.first) + return (Handler.first->*Handler.second)(IDVal, IDLoc); + // Target hook for parsing target specific directives. if (!getTargetParser().ParseDirective(ID)) return false; @@ -1895,7 +1923,7 @@ /// ParseDirectiveFile /// ::= .file [number] string -bool AsmParser::ParseDirectiveFile(StringRef, SMLoc DirectiveLoc) { +bool GenericAsmParser::ParseDirectiveFile(StringRef, SMLoc DirectiveLoc) { // FIXME: I'm not sure what this is. int64_t FileNumber = -1; if (getLexer().is(AsmToken::Integer)) { @@ -1926,7 +1954,7 @@ /// ParseDirectiveLine /// ::= .line [number] -bool AsmParser::ParseDirectiveLine(StringRef, SMLoc DirectiveLoc) { +bool GenericAsmParser::ParseDirectiveLine(StringRef, SMLoc DirectiveLoc) { if (getLexer().isNot(AsmToken::EndOfStatement)) { if (getLexer().isNot(AsmToken::Integer)) return TokError("unexpected token in '.line' directive"); @@ -1947,7 +1975,7 @@ /// ParseDirectiveLoc /// ::= .loc number [number [number]] -bool AsmParser::ParseDirectiveLoc(StringRef, SMLoc DirectiveLoc) { +bool GenericAsmParser::ParseDirectiveLoc(StringRef, SMLoc DirectiveLoc) { if (getLexer().isNot(AsmToken::Integer)) return TokError("unexpected token in '.loc' directive"); From gohman at apple.com Mon Jul 12 13:02:04 2010 From: gohman at apple.com (Dan Gohman) Date: Mon, 12 Jul 2010 18:02:04 -0000 Subject: [llvm-commits] [llvm] r108162 - in /llvm/trunk: lib/Analysis/Lint.cpp test/Other/lint.ll Message-ID: <20100712180204.8C3BD2A6C12C@llvm.org> Author: djg Date: Mon Jul 12 13:02:04 2010 New Revision: 108162 URL: http://llvm.org/viewvc/llvm-project?rev=108162&view=rev Log: Add a lint check for mismatched return types, inspired by PR6944. Modified: llvm/trunk/lib/Analysis/Lint.cpp llvm/trunk/test/Other/lint.ll Modified: llvm/trunk/lib/Analysis/Lint.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/Lint.cpp?rev=108162&r1=108161&r2=108162&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/Lint.cpp (original) +++ llvm/trunk/lib/Analysis/Lint.cpp Mon Jul 12 13:02:04 2010 @@ -225,6 +225,10 @@ "Undefined behavior: Call argument count mismatches callee " "argument count", &I); + Assert1(FT->getReturnType() == I.getType(), + "Undefined behavior: Call return type mismatches " + "callee return type", &I); + // Check argument types (in case the callee was casted) and attributes. // TODO: Verify that caller and callee attributes are compatible. Function::arg_iterator PI = F->arg_begin(), PE = F->arg_end(); Modified: llvm/trunk/test/Other/lint.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Other/lint.ll?rev=108162&r1=108161&r2=108162&view=diff ============================================================================== --- llvm/trunk/test/Other/lint.ll (original) +++ llvm/trunk/test/Other/lint.ll Mon Jul 12 13:02:04 2010 @@ -154,3 +154,12 @@ %x = volatile load i32* %t3 br label %exit } + +; CHECK: Call return type mismatches callee return type +%struct = type { double, double } +declare i32 @nonstruct_callee() nounwind +define void @struct_caller() nounwind { +entry: + call %struct bitcast (i32 ()* @foo to %struct ()*)() + ret void +} From daniel at zuster.org Mon Jul 12 13:03:11 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 12 Jul 2010 18:03:11 -0000 Subject: [llvm-commits] [llvm] r108163 - /llvm/trunk/lib/MC/MCParser/AsmParser.cpp Message-ID: <20100712180311.8DFCF2A6C12C@llvm.org> Author: ddunbar Date: Mon Jul 12 13:03:11 2010 New Revision: 108163 URL: http://llvm.org/viewvc/llvm-project?rev=108163&view=rev Log: MC/AsmParser: Switch a bunch of directive parsing to use accessors. Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=108163&r1=108162&r2=108163&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Mon Jul 12 13:03:11 2010 @@ -935,7 +935,7 @@ if (ParseIdentifier(Name)) return TokError("expected identifier after '.set' directive"); - if (Lexer.isNot(AsmToken::Comma)) + if (getLexer().isNot(AsmToken::Comma)) return TokError("unexpected token in '.set'"); Lex(); @@ -947,14 +947,14 @@ /// FIXME: This should actually parse out the segment, section, attributes and /// sizeof_stub fields. bool AsmParser::ParseDirectiveDarwinSection() { - SMLoc Loc = Lexer.getLoc(); + SMLoc Loc = getLexer().getLoc(); StringRef SectionName; if (ParseIdentifier(SectionName)) return Error(Loc, "expected identifier after '.section' directive"); // Verify there is a following comma. - if (!Lexer.is(AsmToken::Comma)) + if (!getLexer().is(AsmToken::Comma)) return TokError("unexpected token in '.section' directive"); std::string SectionSpec = SectionName; @@ -966,7 +966,7 @@ SectionSpec.append(EOL.begin(), EOL.end()); Lex(); - if (Lexer.isNot(AsmToken::EndOfStatement)) + if (getLexer().isNot(AsmToken::EndOfStatement)) return TokError("unexpected token in '.section' directive"); Lex(); @@ -982,9 +982,10 @@ // FIXME: Arch specific. bool isText = Segment == "__TEXT"; // FIXME: Hack. - Out.SwitchSection(Ctx.getMachOSection(Segment, Section, TAA, StubSize, - isText ? SectionKind::getText() - : SectionKind::getDataRel())); + getStreamer().SwitchSection(Ctx.getMachOSection( + Segment, Section, TAA, StubSize, + isText ? SectionKind::getText() + : SectionKind::getDataRel())); return false; } @@ -993,13 +994,13 @@ const char *Section, unsigned TAA, unsigned Align, unsigned StubSize) { - if (Lexer.isNot(AsmToken::EndOfStatement)) + if (getLexer().isNot(AsmToken::EndOfStatement)) return TokError("unexpected token in section switching directive"); Lex(); // FIXME: Arch specific. bool isText = StringRef(Segment) == "__TEXT"; // FIXME: Hack. - Out.SwitchSection(Ctx.getMachOSection(Segment, Section, TAA, StubSize, + getStreamer().SwitchSection(Ctx.getMachOSection(Segment, Section, TAA, StubSize, isText ? SectionKind::getText() : SectionKind::getDataRel())); @@ -1012,13 +1013,13 @@ // is no good reason for someone to intentionally emit incorrectly sized // values into the implicitly aligned sections. if (Align) - Out.EmitValueToAlignment(Align, 0, 1, 0); + getStreamer().EmitValueToAlignment(Align, 0, 1, 0); return false; } bool AsmParser::ParseEscapedString(std::string &Data) { - assert(Lexer.is(AsmToken::String) && "Unexpected current token!"); + assert(getLexer().is(AsmToken::String) && "Unexpected current token!"); Data = ""; StringRef Str = getTok().getStringContents(); @@ -1078,25 +1079,25 @@ /// ParseDirectiveAscii: /// ::= ( .ascii | .asciz ) [ "string" ( , "string" )* ] bool AsmParser::ParseDirectiveAscii(bool ZeroTerminated) { - if (Lexer.isNot(AsmToken::EndOfStatement)) { + if (getLexer().isNot(AsmToken::EndOfStatement)) { for (;;) { - if (Lexer.isNot(AsmToken::String)) + if (getLexer().isNot(AsmToken::String)) return TokError("expected string in '.ascii' or '.asciz' directive"); - + std::string Data; if (ParseEscapedString(Data)) return true; - - Out.EmitBytes(Data, DEFAULT_ADDRSPACE); + + getStreamer().EmitBytes(Data, DEFAULT_ADDRSPACE); if (ZeroTerminated) - Out.EmitBytes(StringRef("\0", 1), DEFAULT_ADDRSPACE); - + getStreamer().EmitBytes(StringRef("\0", 1), DEFAULT_ADDRSPACE); + Lex(); - - if (Lexer.is(AsmToken::EndOfStatement)) + + if (getLexer().is(AsmToken::EndOfStatement)) break; - if (Lexer.isNot(AsmToken::Comma)) + if (getLexer().isNot(AsmToken::Comma)) return TokError("unexpected token in '.ascii' or '.asciz' directive"); Lex(); } @@ -1109,24 +1110,24 @@ /// ParseDirectiveValue /// ::= (.byte | .short | ... ) [ expression (, expression)* ] bool AsmParser::ParseDirectiveValue(unsigned Size) { - if (Lexer.isNot(AsmToken::EndOfStatement)) { + if (getLexer().isNot(AsmToken::EndOfStatement)) { for (;;) { const MCExpr *Value; - SMLoc ATTRIBUTE_UNUSED StartLoc = Lexer.getLoc(); + SMLoc ATTRIBUTE_UNUSED StartLoc = getLexer().getLoc(); if (ParseExpression(Value)) return true; // Special case constant expressions to match code generator. if (const MCConstantExpr *MCE = dyn_cast(Value)) - Out.EmitIntValue(MCE->getValue(), Size, DEFAULT_ADDRSPACE); + getStreamer().EmitIntValue(MCE->getValue(), Size, DEFAULT_ADDRSPACE); else - Out.EmitValue(Value, Size, DEFAULT_ADDRSPACE); + getStreamer().EmitValue(Value, Size, DEFAULT_ADDRSPACE); - if (Lexer.is(AsmToken::EndOfStatement)) + if (getLexer().is(AsmToken::EndOfStatement)) break; // FIXME: Improve diagnostic. - if (Lexer.isNot(AsmToken::Comma)) + if (getLexer().isNot(AsmToken::Comma)) return TokError("unexpected token in directive"); Lex(); } @@ -1144,15 +1145,15 @@ return true; int64_t FillExpr = 0; - if (Lexer.isNot(AsmToken::EndOfStatement)) { - if (Lexer.isNot(AsmToken::Comma)) + if (getLexer().isNot(AsmToken::EndOfStatement)) { + if (getLexer().isNot(AsmToken::Comma)) return TokError("unexpected token in '.space' directive"); Lex(); if (ParseAbsoluteExpression(FillExpr)) return true; - if (Lexer.isNot(AsmToken::EndOfStatement)) + if (getLexer().isNot(AsmToken::EndOfStatement)) return TokError("unexpected token in '.space' directive"); } @@ -1162,7 +1163,7 @@ return TokError("invalid number of bytes in '.space' directive"); // FIXME: Sometimes the fill expr is 'nop' if it isn't supplied, instead of 0. - Out.EmitFill(NumBytes, FillExpr, DEFAULT_ADDRSPACE); + getStreamer().EmitFill(NumBytes, FillExpr, DEFAULT_ADDRSPACE); return false; } @@ -1174,7 +1175,7 @@ if (ParseAbsoluteExpression(NumValues)) return true; - if (Lexer.isNot(AsmToken::Comma)) + if (getLexer().isNot(AsmToken::Comma)) return TokError("unexpected token in '.fill' directive"); Lex(); @@ -1182,7 +1183,7 @@ if (ParseAbsoluteExpression(FillSize)) return true; - if (Lexer.isNot(AsmToken::Comma)) + if (getLexer().isNot(AsmToken::Comma)) return TokError("unexpected token in '.fill' directive"); Lex(); @@ -1190,7 +1191,7 @@ if (ParseAbsoluteExpression(FillExpr)) return true; - if (Lexer.isNot(AsmToken::EndOfStatement)) + if (getLexer().isNot(AsmToken::EndOfStatement)) return TokError("unexpected token in '.fill' directive"); Lex(); @@ -1199,7 +1200,7 @@ return TokError("invalid '.fill' size, expected 1, 2, 4, or 8"); for (uint64_t i = 0, e = NumValues; i != e; ++i) - Out.EmitIntValue(FillExpr, FillSize, DEFAULT_ADDRSPACE); + getStreamer().EmitIntValue(FillExpr, FillSize, DEFAULT_ADDRSPACE); return false; } @@ -1213,15 +1214,15 @@ // Parse optional fill expression. int64_t FillExpr = 0; - if (Lexer.isNot(AsmToken::EndOfStatement)) { - if (Lexer.isNot(AsmToken::Comma)) + if (getLexer().isNot(AsmToken::EndOfStatement)) { + if (getLexer().isNot(AsmToken::Comma)) return TokError("unexpected token in '.org' directive"); Lex(); if (ParseAbsoluteExpression(FillExpr)) return true; - if (Lexer.isNot(AsmToken::EndOfStatement)) + if (getLexer().isNot(AsmToken::EndOfStatement)) return TokError("unexpected token in '.org' directive"); } @@ -1229,7 +1230,7 @@ // FIXME: Only limited forms of relocatable expressions are accepted here, it // has to be relative to the current section. - Out.EmitValueToOffset(Offset, FillExpr); + getStreamer().EmitValueToOffset(Offset, FillExpr); return false; } @@ -1237,7 +1238,7 @@ /// ParseDirectiveAlign /// ::= {.align, ...} expression [ , expression [ , expression ]] bool AsmParser::ParseDirectiveAlign(bool IsPow2, unsigned ValueSize) { - SMLoc AlignmentLoc = Lexer.getLoc(); + SMLoc AlignmentLoc = getLexer().getLoc(); int64_t Alignment; if (ParseAbsoluteExpression(Alignment)) return true; @@ -1246,30 +1247,30 @@ bool HasFillExpr = false; int64_t FillExpr = 0; int64_t MaxBytesToFill = 0; - if (Lexer.isNot(AsmToken::EndOfStatement)) { - if (Lexer.isNot(AsmToken::Comma)) + if (getLexer().isNot(AsmToken::EndOfStatement)) { + if (getLexer().isNot(AsmToken::Comma)) return TokError("unexpected token in directive"); Lex(); // The fill expression can be omitted while specifying a maximum number of // alignment bytes, e.g: // .align 3,,4 - if (Lexer.isNot(AsmToken::Comma)) { + if (getLexer().isNot(AsmToken::Comma)) { HasFillExpr = true; if (ParseAbsoluteExpression(FillExpr)) return true; } - if (Lexer.isNot(AsmToken::EndOfStatement)) { - if (Lexer.isNot(AsmToken::Comma)) + if (getLexer().isNot(AsmToken::EndOfStatement)) { + if (getLexer().isNot(AsmToken::Comma)) return TokError("unexpected token in directive"); Lex(); - MaxBytesLoc = Lexer.getLoc(); + MaxBytesLoc = getLexer().getLoc(); if (ParseAbsoluteExpression(MaxBytesToFill)) return true; - if (Lexer.isNot(AsmToken::EndOfStatement)) + if (getLexer().isNot(AsmToken::EndOfStatement)) return TokError("unexpected token in directive"); } } @@ -1311,14 +1312,14 @@ // FIXME: This should be using a target hook. bool UseCodeAlign = false; if (const MCSectionMachO *S = dyn_cast( - Out.getCurrentSection())) + getStreamer().getCurrentSection())) UseCodeAlign = S->hasAttribute(MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS); if ((!HasFillExpr || Lexer.getMAI().getTextAlignFillValue() == FillExpr) && ValueSize == 1 && UseCodeAlign) { - Out.EmitCodeAlignment(Alignment, MaxBytesToFill); + getStreamer().EmitCodeAlignment(Alignment, MaxBytesToFill); } else { // FIXME: Target specific behavior about how the "extra" bytes are filled. - Out.EmitValueToAlignment(Alignment, FillExpr, ValueSize, MaxBytesToFill); + getStreamer().EmitValueToAlignment(Alignment, FillExpr, ValueSize, MaxBytesToFill); } return false; @@ -1327,7 +1328,7 @@ /// ParseDirectiveSymbolAttribute /// ::= { ".globl", ".weak", ... } [ identifier ( , identifier )* ] bool AsmParser::ParseDirectiveSymbolAttribute(MCSymbolAttr Attr) { - if (Lexer.isNot(AsmToken::EndOfStatement)) { + if (getLexer().isNot(AsmToken::EndOfStatement)) { for (;;) { StringRef Name; @@ -1336,12 +1337,12 @@ MCSymbol *Sym = CreateSymbol(Name); - Out.EmitSymbolAttribute(Sym, Attr); + getStreamer().EmitSymbolAttribute(Sym, Attr); - if (Lexer.is(AsmToken::EndOfStatement)) + if (getLexer().is(AsmToken::EndOfStatement)) break; - if (Lexer.isNot(AsmToken::Comma)) + if (getLexer().isNot(AsmToken::Comma)) return TokError("unexpected token in directive"); Lex(); } @@ -1361,18 +1362,18 @@ // Handle the identifier as the key symbol. MCSymbol *Sym = CreateSymbol(Name); - if (Lexer.isNot(AsmToken::Comma)) + if (getLexer().isNot(AsmToken::Comma)) return TokError("unexpected token in '.type' directive"); Lex(); - if (Lexer.isNot(AsmToken::At)) + if (getLexer().isNot(AsmToken::At)) return TokError("expected '@' before type"); Lex(); StringRef Type; SMLoc TypeLoc; - TypeLoc = Lexer.getLoc(); + TypeLoc = getLexer().getLoc(); if (ParseIdentifier(Type)) return TokError("expected symbol type in directive"); @@ -1387,12 +1388,12 @@ if (Attr == MCSA_Invalid) return Error(TypeLoc, "unsupported attribute in '.type' directive"); - if (Lexer.isNot(AsmToken::EndOfStatement)) + if (getLexer().isNot(AsmToken::EndOfStatement)) return TokError("unexpected token in '.type' directive"); Lex(); - Out.EmitSymbolAttribute(Sym, Attr); + getStreamer().EmitSymbolAttribute(Sym, Attr); return false; } @@ -1407,7 +1408,7 @@ // Handle the identifier as the key symbol. MCSymbol *Sym = CreateSymbol(Name); - if (Lexer.isNot(AsmToken::Comma)) + if (getLexer().isNot(AsmToken::Comma)) return TokError("unexpected token in '.desc' directive"); Lex(); @@ -1415,13 +1416,13 @@ if (ParseAbsoluteExpression(DescValue)) return true; - if (Lexer.isNot(AsmToken::EndOfStatement)) + if (getLexer().isNot(AsmToken::EndOfStatement)) return TokError("unexpected token in '.desc' directive"); Lex(); // Set the n_desc field of this Symbol to this DescValue - Out.EmitSymbolDesc(Sym, DescValue); + getStreamer().EmitSymbolDesc(Sym, DescValue); return false; } @@ -1429,7 +1430,7 @@ /// ParseDirectiveComm /// ::= ( .comm | .lcomm ) identifier , size_expression [ , align_expression ] bool AsmParser::ParseDirectiveComm(bool IsLocal) { - SMLoc IDLoc = Lexer.getLoc(); + SMLoc IDLoc = getLexer().getLoc(); StringRef Name; if (ParseIdentifier(Name)) return TokError("expected identifier in directive"); @@ -1437,20 +1438,20 @@ // Handle the identifier as the key symbol. MCSymbol *Sym = CreateSymbol(Name); - if (Lexer.isNot(AsmToken::Comma)) + if (getLexer().isNot(AsmToken::Comma)) return TokError("unexpected token in directive"); Lex(); int64_t Size; - SMLoc SizeLoc = Lexer.getLoc(); + SMLoc SizeLoc = getLexer().getLoc(); if (ParseAbsoluteExpression(Size)) return true; int64_t Pow2Alignment = 0; SMLoc Pow2AlignmentLoc; - if (Lexer.is(AsmToken::Comma)) { + if (getLexer().is(AsmToken::Comma)) { Lex(); - Pow2AlignmentLoc = Lexer.getLoc(); + Pow2AlignmentLoc = getLexer().getLoc(); if (ParseAbsoluteExpression(Pow2Alignment)) return true; @@ -1462,7 +1463,7 @@ } } - if (Lexer.isNot(AsmToken::EndOfStatement)) + if (getLexer().isNot(AsmToken::EndOfStatement)) return TokError("unexpected token in '.comm' or '.lcomm' directive"); Lex(); @@ -1486,14 +1487,14 @@ // '.lcomm' is equivalent to '.zerofill'. // Create the Symbol as a common or local common with Size and Pow2Alignment if (IsLocal) { - Out.EmitZerofill(Ctx.getMachOSection("__DATA", "__bss", - MCSectionMachO::S_ZEROFILL, 0, - SectionKind::getBSS()), - Sym, Size, 1 << Pow2Alignment); + getStreamer().EmitZerofill(Ctx.getMachOSection( + "__DATA", "__bss", MCSectionMachO::S_ZEROFILL, + 0, SectionKind::getBSS()), + Sym, Size, 1 << Pow2Alignment); return false; } - Out.EmitCommonSymbol(Sym, Size, 1 << Pow2Alignment); + getStreamer().EmitCommonSymbol(Sym, Size, 1 << Pow2Alignment); return false; } @@ -1505,7 +1506,7 @@ if (ParseIdentifier(Segment)) return TokError("expected segment name after '.zerofill' directive"); - if (Lexer.isNot(AsmToken::Comma)) + if (getLexer().isNot(AsmToken::Comma)) return TokError("unexpected token in directive"); Lex(); @@ -1516,19 +1517,19 @@ // If this is the end of the line all that was wanted was to create the // the section but with no symbol. - if (Lexer.is(AsmToken::EndOfStatement)) { + if (getLexer().is(AsmToken::EndOfStatement)) { // Create the zerofill section but no symbol - Out.EmitZerofill(Ctx.getMachOSection(Segment, Section, + getStreamer().EmitZerofill(Ctx.getMachOSection(Segment, Section, MCSectionMachO::S_ZEROFILL, 0, SectionKind::getBSS())); return false; } - if (Lexer.isNot(AsmToken::Comma)) + if (getLexer().isNot(AsmToken::Comma)) return TokError("unexpected token in directive"); Lex(); - SMLoc IDLoc = Lexer.getLoc(); + SMLoc IDLoc = getLexer().getLoc(); StringRef IDStr; if (ParseIdentifier(IDStr)) return TokError("expected identifier in directive"); @@ -1536,25 +1537,25 @@ // handle the identifier as the key symbol. MCSymbol *Sym = CreateSymbol(IDStr); - if (Lexer.isNot(AsmToken::Comma)) + if (getLexer().isNot(AsmToken::Comma)) return TokError("unexpected token in directive"); Lex(); int64_t Size; - SMLoc SizeLoc = Lexer.getLoc(); + SMLoc SizeLoc = getLexer().getLoc(); if (ParseAbsoluteExpression(Size)) return true; int64_t Pow2Alignment = 0; SMLoc Pow2AlignmentLoc; - if (Lexer.is(AsmToken::Comma)) { + if (getLexer().is(AsmToken::Comma)) { Lex(); - Pow2AlignmentLoc = Lexer.getLoc(); + Pow2AlignmentLoc = getLexer().getLoc(); if (ParseAbsoluteExpression(Pow2Alignment)) return true; } - if (Lexer.isNot(AsmToken::EndOfStatement)) + if (getLexer().isNot(AsmToken::EndOfStatement)) return TokError("unexpected token in '.zerofill' directive"); Lex(); @@ -1576,7 +1577,7 @@ // Create the zerofill Symbol with Size and Pow2Alignment // // FIXME: Arch specific. - Out.EmitZerofill(Ctx.getMachOSection(Segment, Section, + getStreamer().EmitZerofill(Ctx.getMachOSection(Segment, Section, MCSectionMachO::S_ZEROFILL, 0, SectionKind::getBSS()), Sym, Size, 1 << Pow2Alignment); @@ -1587,7 +1588,7 @@ /// ParseDirectiveDarwinTBSS /// ::= .tbss identifier, size, align bool AsmParser::ParseDirectiveDarwinTBSS() { - SMLoc IDLoc = Lexer.getLoc(); + SMLoc IDLoc = getLexer().getLoc(); StringRef Name; if (ParseIdentifier(Name)) return TokError("expected identifier in directive"); @@ -1595,25 +1596,25 @@ // Handle the identifier as the key symbol. MCSymbol *Sym = CreateSymbol(Name); - if (Lexer.isNot(AsmToken::Comma)) + if (getLexer().isNot(AsmToken::Comma)) return TokError("unexpected token in directive"); Lex(); int64_t Size; - SMLoc SizeLoc = Lexer.getLoc(); + SMLoc SizeLoc = getLexer().getLoc(); if (ParseAbsoluteExpression(Size)) return true; int64_t Pow2Alignment = 0; SMLoc Pow2AlignmentLoc; - if (Lexer.is(AsmToken::Comma)) { + if (getLexer().is(AsmToken::Comma)) { Lex(); - Pow2AlignmentLoc = Lexer.getLoc(); + Pow2AlignmentLoc = getLexer().getLoc(); if (ParseAbsoluteExpression(Pow2Alignment)) return true; } - if (Lexer.isNot(AsmToken::EndOfStatement)) + if (getLexer().isNot(AsmToken::EndOfStatement)) return TokError("unexpected token in '.tbss' directive"); Lex(); @@ -1630,10 +1631,11 @@ if (!Sym->isUndefined()) return Error(IDLoc, "invalid symbol redefinition"); - Out.EmitTBSSSymbol(Ctx.getMachOSection("__DATA", "__thread_bss", - MCSectionMachO::S_THREAD_LOCAL_ZEROFILL, - 0, SectionKind::getThreadBSS()), - Sym, Size, 1 << Pow2Alignment); + getStreamer().EmitTBSSSymbol(Ctx.getMachOSection( + "__DATA", "__thread_bss", + MCSectionMachO::S_THREAD_LOCAL_ZEROFILL, + 0, SectionKind::getThreadBSS()), + Sym, Size, 1 << Pow2Alignment); return false; } @@ -1641,12 +1643,12 @@ /// ParseDirectiveDarwinSubsectionsViaSymbols /// ::= .subsections_via_symbols bool AsmParser::ParseDirectiveDarwinSubsectionsViaSymbols() { - if (Lexer.isNot(AsmToken::EndOfStatement)) + if (getLexer().isNot(AsmToken::EndOfStatement)) return TokError("unexpected token in '.subsections_via_symbols' directive"); Lex(); - Out.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols); + getStreamer().EmitAssemblerFlag(MCAF_SubsectionsViaSymbols); return false; } @@ -1655,11 +1657,11 @@ /// ::= .abort [ "abort_string" ] bool AsmParser::ParseDirectiveAbort() { // FIXME: Use loc from directive. - SMLoc Loc = Lexer.getLoc(); + SMLoc Loc = getLexer().getLoc(); StringRef Str = ""; - if (Lexer.isNot(AsmToken::EndOfStatement)) { - if (Lexer.isNot(AsmToken::String)) + if (getLexer().isNot(AsmToken::EndOfStatement)) { + if (getLexer().isNot(AsmToken::String)) return TokError("expected string in '.abort' directive"); Str = getTok().getString(); @@ -1667,7 +1669,7 @@ Lex(); } - if (Lexer.isNot(AsmToken::EndOfStatement)) + if (getLexer().isNot(AsmToken::EndOfStatement)) return TokError("unexpected token in '.abort' directive"); Lex(); @@ -1691,7 +1693,7 @@ // Handle the identifier as the key symbol. MCSymbol *Sym = CreateSymbol(Name); - if (Lexer.isNot(AsmToken::Comma)) + if (getLexer().isNot(AsmToken::Comma)) return TokError("unexpected token in '.lsym' directive"); Lex(); @@ -1699,7 +1701,7 @@ if (ParseExpression(Value)) return true; - if (Lexer.isNot(AsmToken::EndOfStatement)) + if (getLexer().isNot(AsmToken::EndOfStatement)) return TokError("unexpected token in '.lsym' directive"); Lex(); @@ -1714,14 +1716,14 @@ /// ParseDirectiveInclude /// ::= .include "filename" bool AsmParser::ParseDirectiveInclude() { - if (Lexer.isNot(AsmToken::String)) + if (getLexer().isNot(AsmToken::String)) return TokError("expected string in '.include' directive"); std::string Filename = getTok().getString(); - SMLoc IncludeLoc = Lexer.getLoc(); + SMLoc IncludeLoc = getLexer().getLoc(); Lex(); - if (Lexer.isNot(AsmToken::EndOfStatement)) + if (getLexer().isNot(AsmToken::EndOfStatement)) return TokError("unexpected token in '.include' directive"); // Strip the quotes. @@ -1742,12 +1744,12 @@ /// ParseDirectiveDarwinDumpOrLoad /// ::= ( .dump | .load ) "filename" bool AsmParser::ParseDirectiveDarwinDumpOrLoad(SMLoc IDLoc, bool IsDump) { - if (Lexer.isNot(AsmToken::String)) + if (getLexer().isNot(AsmToken::String)) return TokError("expected string in '.dump' or '.load' directive"); Lex(); - if (Lexer.isNot(AsmToken::EndOfStatement)) + if (getLexer().isNot(AsmToken::EndOfStatement)) return TokError("unexpected token in '.dump' or '.load' directive"); Lex(); @@ -1810,7 +1812,7 @@ /// ParseDirectiveDarwinSecureLogReset /// ::= .secure_log_reset bool AsmParser::ParseDirectiveDarwinSecureLogReset(SMLoc IDLoc) { - if (Lexer.isNot(AsmToken::EndOfStatement)) + if (getLexer().isNot(AsmToken::EndOfStatement)) return TokError("unexpected token in '.secure_log_reset' directive"); Lex(); @@ -1833,7 +1835,7 @@ if (ParseAbsoluteExpression(ExprValue)) return true; - if (Lexer.isNot(AsmToken::EndOfStatement)) + if (getLexer().isNot(AsmToken::EndOfStatement)) return TokError("unexpected token in '.if' directive"); Lex(); @@ -1866,7 +1868,7 @@ if (ParseAbsoluteExpression(ExprValue)) return true; - if (Lexer.isNot(AsmToken::EndOfStatement)) + if (getLexer().isNot(AsmToken::EndOfStatement)) return TokError("unexpected token in '.elseif' directive"); Lex(); @@ -1880,7 +1882,7 @@ /// ParseDirectiveElse /// ::= .else bool AsmParser::ParseDirectiveElse(SMLoc DirectiveLoc) { - if (Lexer.isNot(AsmToken::EndOfStatement)) + if (getLexer().isNot(AsmToken::EndOfStatement)) return TokError("unexpected token in '.else' directive"); Lex(); @@ -1904,7 +1906,7 @@ /// ParseDirectiveEndIf /// ::= .endif bool AsmParser::ParseDirectiveEndIf(SMLoc DirectiveLoc) { - if (Lexer.isNot(AsmToken::EndOfStatement)) + if (getLexer().isNot(AsmToken::EndOfStatement)) return TokError("unexpected token in '.endif' directive"); Lex(); From rafael.espindola at gmail.com Mon Jul 12 13:11:17 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Mon, 12 Jul 2010 18:11:17 -0000 Subject: [llvm-commits] [llvm] r108164 - in /llvm/trunk: include/llvm/Target/TargetLowering.h lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Message-ID: <20100712181117.785B02A6C12C@llvm.org> Author: rafael Date: Mon Jul 12 13:11:17 2010 New Revision: 108164 URL: http://llvm.org/viewvc/llvm-project?rev=108164&view=rev Log: Fix a typo and fit in 80 columns. Found by Bob Wilson. Modified: llvm/trunk/include/llvm/Target/TargetLowering.h llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Modified: llvm/trunk/include/llvm/Target/TargetLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=108164&r1=108163&r2=108164&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetLowering.h (original) +++ llvm/trunk/include/llvm/Target/TargetLowering.h Mon Jul 12 13:11:17 2010 @@ -1527,7 +1527,7 @@ /// buffers unsigned JumpBufAlignment; - /// MinStackArgumentAlignment - The minimum alginment that any argument + /// MinStackArgumentAlignment - The minimum alignment that any argument /// on the stack needs to have. /// unsigned MinStackArgumentAlignment; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=108164&r1=108163&r2=108164&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Mon Jul 12 13:11:17 2010 @@ -5670,10 +5670,11 @@ } void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { + const TargetData &TD = *TLI.getTargetData(); SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(), getRoot(), getValue(I.getOperand(0)), DAG.getSrcValue(I.getOperand(0)), - TLI.getTargetData()->getABITypeAlignment(I.getType())); + TD.getABITypeAlignment(I.getType())); setValue(&I, V); DAG.setRoot(V.getValue(1)); } From daniel at zuster.org Mon Jul 12 13:12:02 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 12 Jul 2010 18:12:02 -0000 Subject: [llvm-commits] [llvm] r108165 - in /llvm/trunk: include/llvm/MC/MCParser/AsmParser.h lib/MC/MCParser/AsmParser.cpp Message-ID: <20100712181202.7D2052A6C12C@llvm.org> Author: ddunbar Date: Mon Jul 12 13:12:02 2010 New Revision: 108165 URL: http://llvm.org/viewvc/llvm-project?rev=108165&view=rev Log: MC/AsmParser: Add a DarwinAsmParser extension. - Currently initialization is a bit of a hack, but harmless. We need to rework various parts of target initialization to clean this up. Modified: llvm/trunk/include/llvm/MC/MCParser/AsmParser.h llvm/trunk/lib/MC/MCParser/AsmParser.cpp Modified: llvm/trunk/include/llvm/MC/MCParser/AsmParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/AsmParser.h?rev=108165&r1=108164&r2=108165&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCParser/AsmParser.h (original) +++ llvm/trunk/include/llvm/MC/MCParser/AsmParser.h Mon Jul 12 13:12:02 2010 @@ -45,6 +45,7 @@ MCStreamer &Out; SourceMgr &SrcMgr; MCAsmParserExtension *GenericParser; + MCAsmParserExtension *PlatformParser; TargetAsmParser *TargetParser; /// This is the current buffer index we're lexing from as managed by the Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=108165&r1=108164&r2=108165&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Mon Jul 12 13:12:02 2010 @@ -56,6 +56,18 @@ bool ParseDirectiveLoc(StringRef, SMLoc DirectiveLoc); // ".loc" }; +/// \brief Implementation of directive handling which is shared across all +/// Darwin targets. +class DarwinAsmParser : public MCAsmParserExtension { +public: + DarwinAsmParser() {} + + virtual void Initialize(MCAsmParser &Parser) { + // Call the base implementation. + this->MCAsmParserExtension::Initialize(Parser); + } +}; + } enum { DEFAULT_ADDRSPACE = 0 }; @@ -63,14 +75,25 @@ AsmParser::AsmParser(const Target &T, SourceMgr &_SM, MCContext &_Ctx, MCStreamer &_Out, const MCAsmInfo &_MAI) : Lexer(_MAI), Ctx(_Ctx), Out(_Out), SrcMgr(_SM), - GenericParser(new GenericAsmParser), TargetParser(0), CurBuffer(0) { + GenericParser(new GenericAsmParser), PlatformParser(0), + TargetParser(0), CurBuffer(0) { Lexer.setBuffer(SrcMgr.getMemoryBuffer(CurBuffer)); // Initialize the generic parser. GenericParser->Initialize(*this); + + // Initialize the platform / file format parser. + // + // FIXME: This is a hack, we need to (majorly) cleanup how these objects are + // created. + if (_MAI.hasSubsectionsViaSymbols()) { + PlatformParser = new DarwinAsmParser; + PlatformParser->Initialize(*this); + } } AsmParser::~AsmParser() { + delete PlatformParser; delete GenericParser; } From gohman at apple.com Mon Jul 12 13:12:35 2010 From: gohman at apple.com (Dan Gohman) Date: Mon, 12 Jul 2010 18:12:35 -0000 Subject: [llvm-commits] [llvm] r108167 - /llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Message-ID: <20100712181235.5F2AC2A6C12C@llvm.org> Author: djg Date: Mon Jul 12 13:12:35 2010 New Revision: 108167 URL: http://llvm.org/viewvc/llvm-project?rev=108167&view=rev Log: Check begin!=end, rather than !begin. Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=108167&r1=108166&r2=108167&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Mon Jul 12 13:12:35 2010 @@ -2060,7 +2060,7 @@ MachineInstr::mmo_iterator MMOBegin, MachineInstr::mmo_iterator MMOEnd, SmallVectorImpl &NewMIs) const { - bool isAligned = *MMOBegin && (*MMOBegin)->getAlignment() >= 16; + bool isAligned = MMOBegin != MMOEnd && (*MMOBegin)->getAlignment() >= 16; unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM); DebugLoc DL; MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)); @@ -2090,7 +2090,7 @@ MachineInstr::mmo_iterator MMOBegin, MachineInstr::mmo_iterator MMOEnd, SmallVectorImpl &NewMIs) const { - bool isAligned = *MMOBegin && (*MMOBegin)->getAlignment() >= 16; + bool isAligned = MMOBegin != MMOEnd && (*MMOBegin)->getAlignment() >= 16; unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM); DebugLoc DL; MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); From stoklund at 2pi.dk Mon Jul 12 13:17:48 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 12 Jul 2010 18:17:48 -0000 Subject: [llvm-commits] [llvm] r108169 - /llvm/trunk/utils/unittest/googletest/gtest.cc Message-ID: <20100712181748.1D3E02A6C12C@llvm.org> Author: stoklund Date: Mon Jul 12 13:17:47 2010 New Revision: 108169 URL: http://llvm.org/viewvc/llvm-project?rev=108169&view=rev Log: Silence a warning. Modified: llvm/trunk/utils/unittest/googletest/gtest.cc Modified: llvm/trunk/utils/unittest/googletest/gtest.cc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/googletest/gtest.cc?rev=108169&r1=108168&r2=108169&view=diff ============================================================================== --- llvm/trunk/utils/unittest/googletest/gtest.cc (original) +++ llvm/trunk/utils/unittest/googletest/gtest.cc Mon Jul 12 13:17:47 2010 @@ -3602,7 +3602,7 @@ // the --gtest_catch_exceptions flags are specified. DebugBreak(); #else - *static_cast(NULL) = 1; + abort(); #endif // GTEST_OS_WINDOWS } else if (GTEST_FLAG(throw_on_failure)) { #if GTEST_HAS_EXCEPTIONS From criswell at uiuc.edu Mon Jul 12 13:18:35 2010 From: criswell at uiuc.edu (John Criswell) Date: Mon, 12 Jul 2010 18:18:35 -0000 Subject: [llvm-commits] [poolalloc] r108170 - /poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp Message-ID: <20100712181835.0E9702A6C12C@llvm.org> Author: criswell Date: Mon Jul 12 13:18:34 2010 New Revision: 108170 URL: http://llvm.org/viewvc/llvm-project?rev=108170&view=rev Log: If the target of an indirect function call has no body, don't transform the call. This fixes PR#7628. Modified: poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp Modified: poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp?rev=108170&r1=108169&r2=108170&view=diff ============================================================================== --- poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp (original) +++ poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp Mon Jul 12 13:18:34 2010 @@ -30,15 +30,6 @@ using namespace llvm; using namespace PA; -// -// Flag: UsingBugpoint -// -// Description: -// There are certain assertions that interfere with bugpoint's ability to -// reduce test cases. When using bugpoint, set this variable to true. -// -static bool UsingBugpoint = false; - namespace { /// FuncTransform - This class implements transformation required of pool /// allocated functions. @@ -828,11 +819,18 @@ // if (!CF) return; + // + // It's possible that this program has indirect call targets that are + // not defined in this module. Do not transformation for such functions. + // + if (!(Graphs.hasDSGraph(*CF))) return; + + // // Get the common graph for the set of functions this call may invoke. - if (UsingBugpoint && (!(Graphs.hasDSGraph(*CF)))) return; + // assert ((Graphs.hasDSGraph(*CF)) && "Function has no DSGraph!\n"); CalleeGraph = Graphs.getDSGraph(*CF); - + #ifndef NDEBUG // Verify that all potential callees at call site have the same DS graph. DSCallGraph::callee_iterator E = Graphs.getCallGraph().callee_end(OrigInst); From evan.cheng at apple.com Mon Jul 12 13:22:30 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 12 Jul 2010 11:22:30 -0700 Subject: [llvm-commits] [llvm] r108109 - /llvm/trunk/lib/CodeGen/MachineLICM.cpp In-Reply-To: References: <20100712000035.393982A6C12C@llvm.org> <5470C984-D21B-4C3F-860C-D7506AFBFAAB@apple.com> Message-ID: On Jul 12, 2010, at 8:29 AM, Chris Lattner wrote: > > On Jul 12, 2010, at 12:57 AM, Evan Cheng wrote: > >>> change machinelicm to use MachineInstr::isSafeToMove. No >>> intended functionality change. >>> >>> The avoidance of hoistiing implicitdef seems wrong though. >> >> It's not. We want to avoid creating implicitdef with no trivial live intervals. The trivial ones will be converted to undef machine operands which do not take up registers. > > Why? The register allocator treats them specially just so they don't use a register (according to Jakob). No, that's not correct. The ones with trivial live intervals, i.e. defined and used in the same BB, are converted to undef operands. These do not take up registers. The ones that have uses outside of the definition block *may* not be eliminated. Those will take up registers. Evan > > -Chris From daniel at zuster.org Mon Jul 12 13:35:04 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 12 Jul 2010 18:35:04 -0000 Subject: [llvm-commits] [llvm] r108171 - in /llvm/trunk/include/llvm/MC/MCParser: AsmParser.h MCAsmParser.h MCAsmParserExtension.h Message-ID: <20100712183504.5E9E72A6C12C@llvm.org> Author: ddunbar Date: Mon Jul 12 13:35:04 2010 New Revision: 108171 URL: http://llvm.org/viewvc/llvm-project?rev=108171&view=rev Log: MCAsmParser: Add getSourceManager(). Modified: llvm/trunk/include/llvm/MC/MCParser/AsmParser.h llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h llvm/trunk/include/llvm/MC/MCParser/MCAsmParserExtension.h Modified: llvm/trunk/include/llvm/MC/MCParser/AsmParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/AsmParser.h?rev=108171&r1=108170&r2=108171&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCParser/AsmParser.h (original) +++ llvm/trunk/include/llvm/MC/MCParser/AsmParser.h Mon Jul 12 13:35:04 2010 @@ -80,6 +80,7 @@ /// @name MCAsmParser Interface /// { + virtual SourceMgr &getSourceManager() { return SrcMgr; } virtual MCAsmLexer &getLexer() { return Lexer; } virtual MCContext &getContext() { return Ctx; } virtual MCStreamer &getStreamer() { return Out; } Modified: llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h?rev=108171&r1=108170&r2=108171&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h (original) +++ llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h Mon Jul 12 13:35:04 2010 @@ -20,6 +20,7 @@ class MCExpr; class MCStreamer; class SMLoc; +class SourceMgr; class StringRef; class Twine; @@ -42,6 +43,8 @@ StringRef Directive, DirectiveHandler Handler) = 0; + virtual SourceMgr &getSourceManager() = 0; + virtual MCAsmLexer &getLexer() = 0; virtual MCContext &getContext() = 0; Modified: llvm/trunk/include/llvm/MC/MCParser/MCAsmParserExtension.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/MCAsmParserExtension.h?rev=108171&r1=108170&r2=108171&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCParser/MCAsmParserExtension.h (original) +++ llvm/trunk/include/llvm/MC/MCParser/MCAsmParserExtension.h Mon Jul 12 13:35:04 2010 @@ -41,6 +41,7 @@ MCContext &getContext() { return getParser().getContext(); } MCAsmLexer &getLexer() { return getParser().getLexer(); } MCAsmParser &getParser() { return *Parser; } + SourceMgr &getSourceManager() { return getParser().getSourceManager(); } MCStreamer &getStreamer() { return getParser().getStreamer(); } void Warning(SMLoc L, const Twine &Msg) { return getParser().Warning(L, Msg); From criswell at uiuc.edu Mon Jul 12 13:38:54 2010 From: criswell at uiuc.edu (John Criswell) Date: Mon, 12 Jul 2010 18:38:54 -0000 Subject: [llvm-commits] [poolalloc] r108173 - /poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp Message-ID: <20100712183854.EACC52A6C12C@llvm.org> Author: criswell Date: Mon Jul 12 13:38:54 2010 New Revision: 108173 URL: http://llvm.org/viewvc/llvm-project?rev=108173&view=rev Log: Modified code so that we do not risk invalidating DenseMap iterators. Modified code so that DSNodes which are external, incomplete, or unknown are also moved into global pools, even if they are not explicitly reachable from a global. Modified: poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp Modified: poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp?rev=108173&r1=108172&r2=108173&view=diff ============================================================================== --- poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp (original) +++ poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp Mon Jul 12 13:38:54 2010 @@ -693,7 +693,7 @@ // allocated from the heap, this pool gets a global lifetime. This is // implemented by making the pool descriptor be a global variable of its own, // and initializing the pool on entrance to main. Note that we never destroy -// the pool, because it has global lifetime. +// the pool because it has global lifetime. // // This method returns true if correct pool allocation of the module cannot be // performed because there is no main function for the module and there are @@ -707,14 +707,20 @@ DenseSet GlobalHeapNodes; GetNodesReachableFromGlobals(GG, GlobalHeapNodes); - // Filter out all nodes which have no heap allocations merged into them. + // + // We do not want to create pools for all memory objects reachable from + // globals. We only want those that are heap objects, could be heap objects, + // or are array objects. + // + std::vector toRemove; for (DenseSet::iterator I = GlobalHeapNodes.begin(), E = GlobalHeapNodes.end(); I != E; ) { DenseSet::iterator Last = I; ++I; // - // FIXME: If the PoolAllocateAllGlobalNodes option is selected for the heuristic, - // then we should make global pools for heap and non-heap DSNodes. + // FIXME: If the PoolAllocateAllGlobalNodes option is selected for the + // heuristic, then we should make global pools for heap and + // non-heap DSNodes. // #if 0 // @@ -728,13 +734,47 @@ } #endif - //FIXME: erase on a densemap invalidates all iterators + // + // Nodes that escape to external code could be reachable from globals. + // Nodes that are incomplete could be heap nodes. + // Unknown nodes could be anything. + // const DSNode *tmp = *Last; - // errs() << "test \n"; - if (!(tmp->isHeapNode() || tmp->isArrayNode())) - GlobalHeapNodes.erase(tmp); + if (!(tmp->isHeapNode() || tmp->isArrayNode() || + tmp->isExternalNode() || tmp->isIncompleteNode() || + tmp->isUnknownNode())) + toRemove.push_back (tmp); } + // + // Remove all the DSNodes for which we do not want to create a global pool. + // + while (toRemove.size()) { + const DSNode * Node = toRemove.back(); + toRemove.pop_back(); + GlobalHeapNodes.erase(Node); + } + + // + // Scan through all the local graphs looking for DSNodes which may be + // reachable by a global. These nodes may not end up in the globals graph + // because of the fact that DSA doesn't actually know what is happening to + // them. + // + for (Module::iterator F = M.begin(); F != M.end(); ++F) { + if (F->isDeclaration()) continue; + DSGraph* G = Graphs->getDSGraph(*F); + for (DSGraph::node_iterator I = G->node_begin(), E = G->node_end(); + I != E; + ++I){ + DSNode * Node = I; + if (Node->isExternalNode() || Node->isIncompleteNode() || + Node->isUnknownNode()) { + GlobalHeapNodes.insert (Node); + } + } + } + // Otherwise get the main function to insert the poolinit calls. Function *MainFunc = M.getFunction("main"); if (MainFunc == 0 || MainFunc->isDeclaration()) { From daniel at zuster.org Mon Jul 12 13:49:22 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 12 Jul 2010 18:49:22 -0000 Subject: [llvm-commits] [llvm] r108174 - in /llvm/trunk: include/llvm/MC/MCParser/AsmParser.h lib/MC/MCParser/AsmParser.cpp test/MC/AsmParser/directive_subsections_via_symbols.s test/MC/AsmParser/hello.s Message-ID: <20100712184923.062202A6C12C@llvm.org> Author: ddunbar Date: Mon Jul 12 13:49:22 2010 New Revision: 108174 URL: http://llvm.org/viewvc/llvm-project?rev=108174&view=rev Log: MC/AsmParser: Move some misc. Darwin directive handling to DarwinAsmParser. Modified: llvm/trunk/include/llvm/MC/MCParser/AsmParser.h llvm/trunk/lib/MC/MCParser/AsmParser.cpp llvm/trunk/test/MC/AsmParser/directive_subsections_via_symbols.s llvm/trunk/test/MC/AsmParser/hello.s Modified: llvm/trunk/include/llvm/MC/MCParser/AsmParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/AsmParser.h?rev=108174&r1=108173&r2=108174&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCParser/AsmParser.h (original) +++ llvm/trunk/include/llvm/MC/MCParser/AsmParser.h Mon Jul 12 13:49:22 2010 @@ -144,15 +144,6 @@ bool ParseDirectiveDarwinZerofill(); // Darwin specific ".zerofill" bool ParseDirectiveDarwinTBSS(); // Darwin specific ".tbss" - // Darwin specific ".subsections_via_symbols" - bool ParseDirectiveDarwinSubsectionsViaSymbols(); - // Darwin specific .dump and .load - bool ParseDirectiveDarwinDumpOrLoad(SMLoc IDLoc, bool IsDump); - // Darwin specific .secure_log_unique - bool ParseDirectiveDarwinSecureLogUnique(SMLoc IDLoc); - // Darwin specific .secure_log_reset - bool ParseDirectiveDarwinSecureLogReset(SMLoc IDLoc); - bool ParseDirectiveAbort(); // ".abort" bool ParseDirectiveInclude(); // ".include" Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=108174&r1=108173&r2=108174&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Mon Jul 12 13:49:22 2010 @@ -65,7 +65,26 @@ virtual void Initialize(MCAsmParser &Parser) { // Call the base implementation. this->MCAsmParserExtension::Initialize(Parser); - } + + Parser.AddDirectiveHandler(this, ".subsections_via_symbols", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseDirectiveSubsectionsViaSymbols)); + Parser.AddDirectiveHandler(this, ".dump", MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseDirectiveDumpOrLoad)); + Parser.AddDirectiveHandler(this, ".load", MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseDirectiveDumpOrLoad)); + Parser.AddDirectiveHandler(this, ".secure_log_unique", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseDirectiveSecureLogUnique)); + Parser.AddDirectiveHandler(this, ".secure_log_reset", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseDirectiveSecureLogReset)); + } + + bool ParseDirectiveSubsectionsViaSymbols(StringRef, SMLoc); + bool ParseDirectiveDumpOrLoad(StringRef, SMLoc); + bool ParseDirectiveSecureLogUnique(StringRef, SMLoc); + bool ParseDirectiveSecureLogReset(StringRef, SMLoc); }; } @@ -822,20 +841,10 @@ if (IDVal == ".tbss") return ParseDirectiveDarwinTBSS(); - if (IDVal == ".subsections_via_symbols") - return ParseDirectiveDarwinSubsectionsViaSymbols(); if (IDVal == ".abort") return ParseDirectiveAbort(); if (IDVal == ".include") return ParseDirectiveInclude(); - if (IDVal == ".dump") - return ParseDirectiveDarwinDumpOrLoad(IDLoc, /*IsDump=*/true); - if (IDVal == ".load") - return ParseDirectiveDarwinDumpOrLoad(IDLoc, /*IsLoad=*/false); - if (IDVal == ".secure_log_unique") - return ParseDirectiveDarwinSecureLogUnique(IDLoc); - if (IDVal == ".secure_log_reset") - return ParseDirectiveDarwinSecureLogReset(IDLoc); // Look up the handler in the handler table. std::pair Handler = @@ -1663,9 +1672,9 @@ return false; } -/// ParseDirectiveDarwinSubsectionsViaSymbols +/// ParseDirectiveSubsectionsViaSymbols /// ::= .subsections_via_symbols -bool AsmParser::ParseDirectiveDarwinSubsectionsViaSymbols() { +bool DarwinAsmParser::ParseDirectiveSubsectionsViaSymbols(StringRef, SMLoc) { if (getLexer().isNot(AsmToken::EndOfStatement)) return TokError("unexpected token in '.subsections_via_symbols' directive"); @@ -1764,9 +1773,11 @@ return false; } -/// ParseDirectiveDarwinDumpOrLoad +/// ParseDirectiveDumpOrLoad /// ::= ( .dump | .load ) "filename" -bool AsmParser::ParseDirectiveDarwinDumpOrLoad(SMLoc IDLoc, bool IsDump) { +bool DarwinAsmParser::ParseDirectiveDumpOrLoad(StringRef Directive, + SMLoc IDLoc) { + bool IsDump = Directive == ".dump"; if (getLexer().isNot(AsmToken::String)) return TokError("expected string in '.dump' or '.load' directive"); @@ -1787,19 +1798,19 @@ return false; } -/// ParseDirectiveDarwinSecureLogUnique +/// ParseDirectiveSecureLogUnique /// ::= .secure_log_unique "log message" -bool AsmParser::ParseDirectiveDarwinSecureLogUnique(SMLoc IDLoc) { +bool DarwinAsmParser::ParseDirectiveSecureLogUnique(StringRef, SMLoc IDLoc) { std::string LogMessage; - if (Lexer.isNot(AsmToken::String)) + if (getLexer().isNot(AsmToken::String)) LogMessage = ""; else{ LogMessage = getTok().getString(); Lex(); } - if (Lexer.isNot(AsmToken::EndOfStatement)) + if (getLexer().isNot(AsmToken::EndOfStatement)) return TokError("unexpected token in '.secure_log_unique' directive"); if (getContext().getSecureLogUsed() != false) @@ -1822,9 +1833,9 @@ getContext().setSecureLog(OS); } - int CurBuf = SrcMgr.FindBufferContainingLoc(IDLoc); - *OS << SrcMgr.getBufferInfo(CurBuf).Buffer->getBufferIdentifier() << ":" - << SrcMgr.FindLineNumber(IDLoc, CurBuf) << ":" + int CurBuf = getSourceManager().FindBufferContainingLoc(IDLoc); + *OS << getSourceManager().getBufferInfo(CurBuf).Buffer->getBufferIdentifier() + << ":" << getSourceManager().FindLineNumber(IDLoc, CurBuf) << ":" << LogMessage + "\n"; getContext().setSecureLogUsed(true); @@ -1832,9 +1843,9 @@ return false; } -/// ParseDirectiveDarwinSecureLogReset +/// ParseDirectiveSecureLogReset /// ::= .secure_log_reset -bool AsmParser::ParseDirectiveDarwinSecureLogReset(SMLoc IDLoc) { +bool DarwinAsmParser::ParseDirectiveSecureLogReset(StringRef, SMLoc IDLoc) { if (getLexer().isNot(AsmToken::EndOfStatement)) return TokError("unexpected token in '.secure_log_reset' directive"); Modified: llvm/trunk/test/MC/AsmParser/directive_subsections_via_symbols.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/directive_subsections_via_symbols.s?rev=108174&r1=108173&r2=108174&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/directive_subsections_via_symbols.s (original) +++ llvm/trunk/test/MC/AsmParser/directive_subsections_via_symbols.s Mon Jul 12 13:49:22 2010 @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple i386-unknown-unknown %s | FileCheck %s +# RUN: llvm-mc -triple i386-apple-darwin9 %s | FileCheck %s # CHECK: TEST0: # CHECK: .subsections_via_symbols Modified: llvm/trunk/test/MC/AsmParser/hello.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/hello.s?rev=108174&r1=108173&r2=108174&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/hello.s (original) +++ llvm/trunk/test/MC/AsmParser/hello.s Mon Jul 12 13:49:22 2010 @@ -1,6 +1,6 @@ -// RUN: llvm-mc -triple i386-unknown-unknown %s -o - -// RUN: llvm-mc -triple i386-unknown-unknown %s -o - -output-asm-variant=1 - +// RUN: llvm-mc -triple i386-apple-darwin9 %s -o - +// RUN: llvm-mc -triple i386-apple-darwin9 %s -o - -output-asm-variant=1 + .text .align 4,0x90 .globl _main From daniel at zuster.org Mon Jul 12 14:08:25 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 12 Jul 2010 19:08:25 -0000 Subject: [llvm-commits] [llvm] r108176 - in /llvm/trunk: include/llvm/MC/MCParser/AsmParser.h include/llvm/MC/MCParser/MCAsmParser.h lib/MC/MCParser/AsmParser.cpp Message-ID: <20100712190825.42A0D2A6C12C@llvm.org> Author: ddunbar Date: Mon Jul 12 14:08:25 2010 New Revision: 108176 URL: http://llvm.org/viewvc/llvm-project?rev=108176&view=rev Log: MC/AsmParser: Move .lsym parsing to Darwin specific parser. Modified: llvm/trunk/include/llvm/MC/MCParser/AsmParser.h llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h llvm/trunk/lib/MC/MCParser/AsmParser.cpp Modified: llvm/trunk/include/llvm/MC/MCParser/AsmParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/AsmParser.h?rev=108176&r1=108175&r2=108176&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCParser/AsmParser.h (original) +++ llvm/trunk/include/llvm/MC/MCParser/AsmParser.h Mon Jul 12 14:08:25 2010 @@ -138,7 +138,6 @@ bool ParseDirectiveSymbolAttribute(MCSymbolAttr Attr); bool ParseDirectiveELFType(); // ELF specific ".type" bool ParseDirectiveDarwinSymbolDesc(); // Darwin specific ".desc" - bool ParseDirectiveDarwinLsym(); // Darwin specific ".lsym" bool ParseDirectiveComm(bool IsLocal); // ".comm" and ".lcomm" bool ParseDirectiveDarwinZerofill(); // Darwin specific ".zerofill" Modified: llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h?rev=108176&r1=108175&r2=108176&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h (original) +++ llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h Mon Jul 12 14:08:25 2010 @@ -73,6 +73,10 @@ /// \brief Report an error at the current lexer location. bool TokError(const char *Msg); + /// ParseIdentifier - Parse an identifier or string (as a quoted identifier) + /// and set \arg Res to the identifier contents. + virtual bool ParseIdentifier(StringRef &Res) = 0; + /// ParseExpression - Parse an arbitrary expression. /// /// @param Res - The value of the expression. The result is undefined Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=108176&r1=108175&r2=108176&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Mon Jul 12 14:08:25 2010 @@ -66,6 +66,8 @@ // Call the base implementation. this->MCAsmParserExtension::Initialize(Parser); + Parser.AddDirectiveHandler(this, ".lsym", MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseDirectiveLsym)); Parser.AddDirectiveHandler(this, ".subsections_via_symbols", MCAsmParser::DirectiveHandler( &DarwinAsmParser::ParseDirectiveSubsectionsViaSymbols)); @@ -81,10 +83,11 @@ &DarwinAsmParser::ParseDirectiveSecureLogReset)); } - bool ParseDirectiveSubsectionsViaSymbols(StringRef, SMLoc); bool ParseDirectiveDumpOrLoad(StringRef, SMLoc); - bool ParseDirectiveSecureLogUnique(StringRef, SMLoc); + bool ParseDirectiveLsym(StringRef, SMLoc); bool ParseDirectiveSecureLogReset(StringRef, SMLoc); + bool ParseDirectiveSecureLogUnique(StringRef, SMLoc); + bool ParseDirectiveSubsectionsViaSymbols(StringRef, SMLoc); }; } @@ -836,8 +839,6 @@ return ParseDirectiveDarwinZerofill(); if (IDVal == ".desc") return ParseDirectiveDarwinSymbolDesc(); - if (IDVal == ".lsym") - return ParseDirectiveDarwinLsym(); if (IDVal == ".tbss") return ParseDirectiveDarwinTBSS(); @@ -1717,20 +1718,20 @@ /// ParseDirectiveLsym /// ::= .lsym identifier , expression -bool AsmParser::ParseDirectiveDarwinLsym() { +bool DarwinAsmParser::ParseDirectiveLsym(StringRef, SMLoc) { StringRef Name; - if (ParseIdentifier(Name)) + if (getParser().ParseIdentifier(Name)) return TokError("expected identifier in directive"); // Handle the identifier as the key symbol. - MCSymbol *Sym = CreateSymbol(Name); + MCSymbol *Sym = getContext().GetOrCreateSymbol(Name); if (getLexer().isNot(AsmToken::Comma)) return TokError("unexpected token in '.lsym' directive"); Lex(); const MCExpr *Value; - if (ParseExpression(Value)) + if (getParser().ParseExpression(Value)) return true; if (getLexer().isNot(AsmToken::EndOfStatement)) From criswell at uiuc.edu Mon Jul 12 14:11:19 2010 From: criswell at uiuc.edu (John Criswell) Date: Mon, 12 Jul 2010 19:11:19 -0000 Subject: [llvm-commits] [poolalloc] r108177 - /poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp Message-ID: <20100712191119.6095C2A6C12C@llvm.org> Author: criswell Date: Mon Jul 12 14:11:19 2010 New Revision: 108177 URL: http://llvm.org/viewvc/llvm-project?rev=108177&view=rev Log: Refactored code to avoid iterator invalidation error. This fixes PR#7629. Modified: poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp Modified: poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp?rev=108177&r1=108176&r2=108177&view=diff ============================================================================== --- poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp (original) +++ poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp Mon Jul 12 14:11:19 2010 @@ -213,6 +213,7 @@ // have been transformed already), and // o) the called function is the function that we're replacing // + std::vector toReplace; for (Function::use_iterator User = F->use_begin(); User != F->use_end(); ++User) { @@ -228,17 +229,30 @@ continue; } + // + // We want to replace this use. Add it to the worklist. + // + toReplace.push_back (*User); + } + + // + // Now do replacement on all items within the worklist. + // + while (toReplace.size()) { + llvm::User * user = toReplace.back(); + toReplace.pop_back(); + Constant* CEnew = ConstantExpr::getPointerCast(I->second, F->getType()); // Must handle Constants specially, we cannot call replaceUsesOfWith on a // constant because they are uniqued. - if (Constant *C = dyn_cast(User)) { + if (Constant *C = dyn_cast(user)) { if (!isa(C)) { - C->replaceUsesOfWithOnConstant(F, CEnew, User->op_begin()); + C->replaceUsesOfWithOnConstant(F, CEnew, user->op_begin()); continue; } } - User->replaceUsesOfWith (F, CEnew); + user->replaceUsesOfWith (F, CEnew); } } From daniel at zuster.org Mon Jul 12 14:22:53 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 12 Jul 2010 19:22:53 -0000 Subject: [llvm-commits] [llvm] r108179 - in /llvm/trunk: include/llvm/MC/MCParser/AsmParser.h lib/MC/MCParser/AsmParser.cpp test/MC/AsmParser/directive_desc.s Message-ID: <20100712192253.A96522A6C12C@llvm.org> Author: ddunbar Date: Mon Jul 12 14:22:53 2010 New Revision: 108179 URL: http://llvm.org/viewvc/llvm-project?rev=108179&view=rev Log: MC/AsmParser: Move .desc parsing to Darwin specific parser. Modified: llvm/trunk/include/llvm/MC/MCParser/AsmParser.h llvm/trunk/lib/MC/MCParser/AsmParser.cpp llvm/trunk/test/MC/AsmParser/directive_desc.s Modified: llvm/trunk/include/llvm/MC/MCParser/AsmParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/AsmParser.h?rev=108179&r1=108178&r2=108179&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCParser/AsmParser.h (original) +++ llvm/trunk/include/llvm/MC/MCParser/AsmParser.h Mon Jul 12 14:22:53 2010 @@ -137,7 +137,6 @@ /// accepts a single symbol (which should be a label or an external). bool ParseDirectiveSymbolAttribute(MCSymbolAttr Attr); bool ParseDirectiveELFType(); // ELF specific ".type" - bool ParseDirectiveDarwinSymbolDesc(); // Darwin specific ".desc" bool ParseDirectiveComm(bool IsLocal); // ".comm" and ".lcomm" bool ParseDirectiveDarwinZerofill(); // Darwin specific ".zerofill" Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=108179&r1=108178&r2=108179&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Mon Jul 12 14:22:53 2010 @@ -66,6 +66,8 @@ // Call the base implementation. this->MCAsmParserExtension::Initialize(Parser); + Parser.AddDirectiveHandler(this, ".desc", MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseDirectiveDesc)); Parser.AddDirectiveHandler(this, ".lsym", MCAsmParser::DirectiveHandler( &DarwinAsmParser::ParseDirectiveLsym)); Parser.AddDirectiveHandler(this, ".subsections_via_symbols", @@ -83,6 +85,7 @@ &DarwinAsmParser::ParseDirectiveSecureLogReset)); } + bool ParseDirectiveDesc(StringRef, SMLoc); bool ParseDirectiveDumpOrLoad(StringRef, SMLoc); bool ParseDirectiveLsym(StringRef, SMLoc); bool ParseDirectiveSecureLogReset(StringRef, SMLoc); @@ -837,8 +840,6 @@ return ParseDirectiveComm(/*IsLocal=*/true); if (IDVal == ".zerofill") return ParseDirectiveDarwinZerofill(); - if (IDVal == ".desc") - return ParseDirectiveDarwinSymbolDesc(); if (IDVal == ".tbss") return ParseDirectiveDarwinTBSS(); @@ -1431,22 +1432,22 @@ return false; } -/// ParseDirectiveDarwinSymbolDesc +/// ParseDirectiveDesc /// ::= .desc identifier , expression -bool AsmParser::ParseDirectiveDarwinSymbolDesc() { +bool DarwinAsmParser::ParseDirectiveDesc(StringRef, SMLoc) { StringRef Name; - if (ParseIdentifier(Name)) + if (getParser().ParseIdentifier(Name)) return TokError("expected identifier in directive"); // Handle the identifier as the key symbol. - MCSymbol *Sym = CreateSymbol(Name); + MCSymbol *Sym = getContext().GetOrCreateSymbol(Name); if (getLexer().isNot(AsmToken::Comma)) return TokError("unexpected token in '.desc' directive"); Lex(); int64_t DescValue; - if (ParseAbsoluteExpression(DescValue)) + if (getParser().ParseAbsoluteExpression(DescValue)) return true; if (getLexer().isNot(AsmToken::EndOfStatement)) Modified: llvm/trunk/test/MC/AsmParser/directive_desc.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/directive_desc.s?rev=108179&r1=108178&r2=108179&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/directive_desc.s (original) +++ llvm/trunk/test/MC/AsmParser/directive_desc.s Mon Jul 12 14:22:53 2010 @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple i386-unknown-unknown %s | FileCheck %s +# RUN: llvm-mc -triple i386-apple-darwin9 %s | FileCheck %s # CHECK: TEST0: # CHECK: .desc foo,16 From daniel at zuster.org Mon Jul 12 14:37:35 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 12 Jul 2010 19:37:35 -0000 Subject: [llvm-commits] [llvm] r108180 - in /llvm/trunk: include/llvm/MC/MCParser/AsmParser.h lib/MC/MCParser/AsmParser.cpp test/MC/AsmParser/directive_zerofill.s test/MC/AsmParser/exprs.s Message-ID: <20100712193735.7244F2A6C12C@llvm.org> Author: ddunbar Date: Mon Jul 12 14:37:35 2010 New Revision: 108180 URL: http://llvm.org/viewvc/llvm-project?rev=108180&view=rev Log: MC/AsmParser: Move .tbss and .zerofill parsing to Darwin specific parser. Modified: llvm/trunk/include/llvm/MC/MCParser/AsmParser.h llvm/trunk/lib/MC/MCParser/AsmParser.cpp llvm/trunk/test/MC/AsmParser/directive_zerofill.s llvm/trunk/test/MC/AsmParser/exprs.s Modified: llvm/trunk/include/llvm/MC/MCParser/AsmParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/AsmParser.h?rev=108180&r1=108179&r2=108180&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCParser/AsmParser.h (original) +++ llvm/trunk/include/llvm/MC/MCParser/AsmParser.h Mon Jul 12 14:37:35 2010 @@ -139,8 +139,6 @@ bool ParseDirectiveELFType(); // ELF specific ".type" bool ParseDirectiveComm(bool IsLocal); // ".comm" and ".lcomm" - bool ParseDirectiveDarwinZerofill(); // Darwin specific ".zerofill" - bool ParseDirectiveDarwinTBSS(); // Darwin specific ".tbss" bool ParseDirectiveAbort(); // ".abort" bool ParseDirectiveInclude(); // ".include" Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=108180&r1=108179&r2=108180&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Mon Jul 12 14:37:35 2010 @@ -83,6 +83,12 @@ Parser.AddDirectiveHandler(this, ".secure_log_reset", MCAsmParser::DirectiveHandler( &DarwinAsmParser::ParseDirectiveSecureLogReset)); + Parser.AddDirectiveHandler(this, ".tbss", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseDirectiveTBSS)); + Parser.AddDirectiveHandler(this, ".zerofill", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseDirectiveZerofill)); } bool ParseDirectiveDesc(StringRef, SMLoc); @@ -91,6 +97,8 @@ bool ParseDirectiveSecureLogReset(StringRef, SMLoc); bool ParseDirectiveSecureLogUnique(StringRef, SMLoc); bool ParseDirectiveSubsectionsViaSymbols(StringRef, SMLoc); + bool ParseDirectiveTBSS(StringRef, SMLoc); + bool ParseDirectiveZerofill(StringRef, SMLoc); }; } @@ -838,10 +846,6 @@ return ParseDirectiveComm(/*IsLocal=*/false); if (IDVal == ".lcomm") return ParseDirectiveComm(/*IsLocal=*/true); - if (IDVal == ".zerofill") - return ParseDirectiveDarwinZerofill(); - if (IDVal == ".tbss") - return ParseDirectiveDarwinTBSS(); if (IDVal == ".abort") return ParseDirectiveAbort(); @@ -1532,12 +1536,12 @@ return false; } -/// ParseDirectiveDarwinZerofill +/// ParseDirectiveZerofill /// ::= .zerofill segname , sectname [, identifier , size_expression [ /// , align_expression ]] -bool AsmParser::ParseDirectiveDarwinZerofill() { +bool DarwinAsmParser::ParseDirectiveZerofill(StringRef, SMLoc) { StringRef Segment; - if (ParseIdentifier(Segment)) + if (getParser().ParseIdentifier(Segment)) return TokError("expected segment name after '.zerofill' directive"); if (getLexer().isNot(AsmToken::Comma)) @@ -1545,7 +1549,7 @@ Lex(); StringRef Section; - if (ParseIdentifier(Section)) + if (getParser().ParseIdentifier(Section)) return TokError("expected section name after comma in '.zerofill' " "directive"); @@ -1553,9 +1557,9 @@ // the section but with no symbol. if (getLexer().is(AsmToken::EndOfStatement)) { // Create the zerofill section but no symbol - getStreamer().EmitZerofill(Ctx.getMachOSection(Segment, Section, - MCSectionMachO::S_ZEROFILL, 0, - SectionKind::getBSS())); + getStreamer().EmitZerofill(getContext().getMachOSection( + Segment, Section, MCSectionMachO::S_ZEROFILL, + 0, SectionKind::getBSS())); return false; } @@ -1565,11 +1569,11 @@ SMLoc IDLoc = getLexer().getLoc(); StringRef IDStr; - if (ParseIdentifier(IDStr)) + if (getParser().ParseIdentifier(IDStr)) return TokError("expected identifier in directive"); // handle the identifier as the key symbol. - MCSymbol *Sym = CreateSymbol(IDStr); + MCSymbol *Sym = getContext().GetOrCreateSymbol(IDStr); if (getLexer().isNot(AsmToken::Comma)) return TokError("unexpected token in directive"); @@ -1577,7 +1581,7 @@ int64_t Size; SMLoc SizeLoc = getLexer().getLoc(); - if (ParseAbsoluteExpression(Size)) + if (getParser().ParseAbsoluteExpression(Size)) return true; int64_t Pow2Alignment = 0; @@ -1585,7 +1589,7 @@ if (getLexer().is(AsmToken::Comma)) { Lex(); Pow2AlignmentLoc = getLexer().getLoc(); - if (ParseAbsoluteExpression(Pow2Alignment)) + if (getParser().ParseAbsoluteExpression(Pow2Alignment)) return true; } @@ -1611,24 +1615,24 @@ // Create the zerofill Symbol with Size and Pow2Alignment // // FIXME: Arch specific. - getStreamer().EmitZerofill(Ctx.getMachOSection(Segment, Section, - MCSectionMachO::S_ZEROFILL, 0, - SectionKind::getBSS()), - Sym, Size, 1 << Pow2Alignment); + getStreamer().EmitZerofill(getContext().getMachOSection( + Segment, Section, MCSectionMachO::S_ZEROFILL, + 0, SectionKind::getBSS()), + Sym, Size, 1 << Pow2Alignment); return false; } -/// ParseDirectiveDarwinTBSS +/// ParseDirectiveTBSS /// ::= .tbss identifier, size, align -bool AsmParser::ParseDirectiveDarwinTBSS() { +bool DarwinAsmParser::ParseDirectiveTBSS(StringRef, SMLoc) { SMLoc IDLoc = getLexer().getLoc(); StringRef Name; - if (ParseIdentifier(Name)) + if (getParser().ParseIdentifier(Name)) return TokError("expected identifier in directive"); // Handle the identifier as the key symbol. - MCSymbol *Sym = CreateSymbol(Name); + MCSymbol *Sym = getContext().GetOrCreateSymbol(Name); if (getLexer().isNot(AsmToken::Comma)) return TokError("unexpected token in directive"); @@ -1636,7 +1640,7 @@ int64_t Size; SMLoc SizeLoc = getLexer().getLoc(); - if (ParseAbsoluteExpression(Size)) + if (getParser().ParseAbsoluteExpression(Size)) return true; int64_t Pow2Alignment = 0; @@ -1644,7 +1648,7 @@ if (getLexer().is(AsmToken::Comma)) { Lex(); Pow2AlignmentLoc = getLexer().getLoc(); - if (ParseAbsoluteExpression(Pow2Alignment)) + if (getParser().ParseAbsoluteExpression(Pow2Alignment)) return true; } @@ -1665,7 +1669,7 @@ if (!Sym->isUndefined()) return Error(IDLoc, "invalid symbol redefinition"); - getStreamer().EmitTBSSSymbol(Ctx.getMachOSection( + getStreamer().EmitTBSSSymbol(getContext().getMachOSection( "__DATA", "__thread_bss", MCSectionMachO::S_THREAD_LOCAL_ZEROFILL, 0, SectionKind::getThreadBSS()), Modified: llvm/trunk/test/MC/AsmParser/directive_zerofill.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/directive_zerofill.s?rev=108180&r1=108179&r2=108180&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/directive_zerofill.s (original) +++ llvm/trunk/test/MC/AsmParser/directive_zerofill.s Mon Jul 12 14:37:35 2010 @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple i386-unknown-unknown %s | FileCheck %s +# RUN: llvm-mc -triple i386-apple-darwin9 %s | FileCheck %s # CHECK: TEST0: # CHECK: .zerofill __FOO,__bar,x,1 Modified: llvm/trunk/test/MC/AsmParser/exprs.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/exprs.s?rev=108180&r1=108179&r2=108180&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/exprs.s (original) +++ llvm/trunk/test/MC/AsmParser/exprs.s Mon Jul 12 14:37:35 2010 @@ -70,5 +70,3 @@ L1: jmp A .long . - L1 - - .zerofill __DATA,_bss,A,0 From daniel at zuster.org Mon Jul 12 14:52:11 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 12 Jul 2010 19:52:11 -0000 Subject: [llvm-commits] [llvm] r108183 - in /llvm/trunk: include/llvm/MC/MCParser/AsmParser.h lib/MC/MCParser/AsmParser.cpp Message-ID: <20100712195211.1B7472A6C12C@llvm.org> Author: ddunbar Date: Mon Jul 12 14:52:10 2010 New Revision: 108183 URL: http://llvm.org/viewvc/llvm-project?rev=108183&view=rev Log: MC/AsmParser: Inline AsmParser::CreateSymbol into callers. Modified: llvm/trunk/include/llvm/MC/MCParser/AsmParser.h llvm/trunk/lib/MC/MCParser/AsmParser.cpp Modified: llvm/trunk/include/llvm/MC/MCParser/AsmParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/AsmParser.h?rev=108183&r1=108182&r2=108183&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCParser/AsmParser.h (original) +++ llvm/trunk/include/llvm/MC/MCParser/AsmParser.h Mon Jul 12 14:52:10 2010 @@ -98,10 +98,8 @@ /// } private: - MCSymbol *CreateSymbol(StringRef Name); - bool ParseStatement(); - + void PrintMessage(SMLoc Loc, const std::string &Msg, const char *Type) const; /// EnterIncludeFile - Enter the specified file. This returns true on failure. Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=108183&r1=108182&r2=108183&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Mon Jul 12 14:52:10 2010 @@ -246,11 +246,6 @@ return false; } -MCSymbol *AsmParser::CreateSymbol(StringRef Name) { - // FIXME: Inline into callers. - return Ctx.GetOrCreateSymbol(Name); -} - /// ParsePrimaryExpr - Parse a primary expression and return it. /// primaryexpr ::= (parenexpr /// primaryexpr ::= symbol @@ -271,7 +266,7 @@ case AsmToken::Identifier: { // This is a symbol reference. std::pair Split = getTok().getIdentifier().split('@'); - MCSymbol *Sym = CreateSymbol(Split.first); + MCSymbol *Sym = getContext().GetOrCreateSymbol(Split.first); // Mark the symbol as used in an expression. Sym->setUsedInExpr(true); @@ -581,7 +576,7 @@ // implicitly marked as external. MCSymbol *Sym; if (LocalLabelVal == -1) - Sym = CreateSymbol(IDVal); + Sym = getContext().GetOrCreateSymbol(IDVal); else Sym = Ctx.CreateDirectionalLocalSymbol(LocalLabelVal); if (!Sym->isUndefined() || Sym->isVariable()) @@ -938,7 +933,7 @@ return Error(EqualLoc, "invalid reassignment of non-absolute variable '" + Name + "'"); } else - Sym = CreateSymbol(Name); + Sym = getContext().GetOrCreateSymbol(Name); // FIXME: Handle '.'. @@ -1373,7 +1368,7 @@ if (ParseIdentifier(Name)) return TokError("expected identifier in directive"); - MCSymbol *Sym = CreateSymbol(Name); + MCSymbol *Sym = getContext().GetOrCreateSymbol(Name); getStreamer().EmitSymbolAttribute(Sym, Attr); @@ -1398,7 +1393,7 @@ return TokError("expected identifier in directive"); // Handle the identifier as the key symbol. - MCSymbol *Sym = CreateSymbol(Name); + MCSymbol *Sym = getContext().GetOrCreateSymbol(Name); if (getLexer().isNot(AsmToken::Comma)) return TokError("unexpected token in '.type' directive"); @@ -1474,7 +1469,7 @@ return TokError("expected identifier in directive"); // Handle the identifier as the key symbol. - MCSymbol *Sym = CreateSymbol(Name); + MCSymbol *Sym = getContext().GetOrCreateSymbol(Name); if (getLexer().isNot(AsmToken::Comma)) return TokError("unexpected token in directive"); From bob.wilson at apple.com Mon Jul 12 14:54:15 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Mon, 12 Jul 2010 12:54:15 -0700 Subject: [llvm-commits] (patch) PR7608 ARMv4 JIT forgets to set the lr register when making a indirect function call In-Reply-To: <4C3A4388.1040703@zafena.se> References: <4C3A4388.1040703@zafena.se> Message-ID: I don't think this is good enough. The "mov lr, pc" instruction must be emitted immediately before the call. I don't know how to do that without making all the "call_nolink" instructions into pseudo-instructions. That is kind of ugly because there are a fair number of those "call_nolink" instructions, but I can't think of anything better. (And, if it weren't for that blocking issue, I'd recommend changing the MOVLRPC instruction to explicitly define LR, and changing all the "call_nolink" instructions to use LR. That would prevent LR from being clobbered between the MOVLRPC and the call. But, it's not good enough to prevent some other instruction being scheduled between them.....) On Jul 11, 2010, at 3:19 PM, Xerxes Ranby wrote: > http://llvm.org/bugs/show_bug.cgi?id=7608 > Attached patch fixes the PR7608 bug by defining a new ARM selection dag node > ARMmovlrpc and makes sure both jit and non-jit got a ARMmovlrpc chained and > flagged before any ARMcall_nolink non-tailcall selection dag node. > * llvm/lib/Target/ARM/ARMISelLowering.cpp > (ARMTargetLowering::getTargetNodeName): Update to handle ARMISD::MOVLRPC. > (ARMTargetLowering::LowerCall): Add chain and flag a ARMmovlrpc before any > ARMcall_nolink non-tailcall selection dag node. > * llvm/lib/Target/ARM/ARMISelLowering.h > (ARMISD::MOVLRPC): New enum. > * llvm/lib/Target/ARM/ARMInstrInfo.td > (ARMmovlrpc): New defined selection dag node. > (MOVLRPC): New defined instruction. > (BX): Emit only one instruction for non-jit. > (BMOVPCRX): Likewise. > (BXr9): Likewise. > (BMOVPCRXr9): Likewise. > > Ok to push? > > Cheers > Xerxes > > Index: llvm/lib/Target/ARM/ARMISelLowering.cpp > =================================================================== > --- llvm.orig/lib/Target/ARM/ARMISelLowering.cpp 2010-07-11 12:57:59.000000000 +0200 > +++ llvm/lib/Target/ARM/ARMISelLowering.cpp 2010-07-11 22:07:28.000000000 +0200 > @@ -560,6 +560,7 @@ > case ARMISD::BR_JT: return "ARMISD::BR_JT"; > case ARMISD::BR2_JT: return "ARMISD::BR2_JT"; > case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG"; > + case ARMISD::MOVLRPC: return "ARMISD::MOVLRPC"; > case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD"; > case ARMISD::CMP: return "ARMISD::CMP"; > case ARMISD::CMPZ: return "ARMISD::CMPZ"; > @@ -1288,6 +1289,14 @@ > // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK > Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(MVT::i32),InFlag); > InFlag = Chain.getValue(1); > + > + if(!isTailCall){ > + // explicit copy PC to LR and chain flag it to the call. > + Chain = DAG.getNode(ARMISD::MOVLRPC, dl, > + DAG.getVTList(MVT::Other, MVT::Flag), > + Chain, InFlag); > + InFlag = Chain.getValue(1); > + } > } > > std::vector Ops; > Index: llvm/lib/Target/ARM/ARMISelLowering.h > =================================================================== > --- llvm.orig/lib/Target/ARM/ARMISelLowering.h 2010-07-11 12:57:59.000000000 +0200 > +++ llvm/lib/Target/ARM/ARMISelLowering.h 2010-07-11 12:59:02.000000000 +0200 > @@ -42,6 +42,7 @@ > BR_JT, // Jumptable branch. > BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump). > RET_FLAG, // Return with a flag operand. > + MOVLRPC, // Store return address PC in LR before call - flag before CALL_NOLINK > > PIC_ADD, // Add with a PC operand and a PIC label. > > Index: llvm/lib/Target/ARM/ARMInstrInfo.td > =================================================================== > --- llvm.orig/lib/Target/ARM/ARMInstrInfo.td 2010-07-11 12:57:59.000000000 +0200 > +++ llvm/lib/Target/ARM/ARMInstrInfo.td 2010-07-11 12:59:02.000000000 +0200 > @@ -74,6 +74,9 @@ > [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag, > SDNPVariadic]>; > > +def ARMmovlrpc : SDNode<"ARMISD::MOVLRPC", SDTNone, > + [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; > + > def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone, > [SDNPHasChain, SDNPOptInFlag]>; > > @@ -674,6 +677,16 @@ > [(ARMcallseq_start timm:$amt)]>; > } > > +let Defs = [LR], hasSideEffects = 1 in > +def MOVLRPC : AI<(outs), (ins), BrMiscFrm, IIC_Br, > + "mov", "\tlr, pc", [(ARMmovlrpc)]>, > + Requires<[IsARM]> { > + let Inst{11-0} = 0b000000001111; > + let Inst{15-12} = 0b1110; > + let Inst{19-16} = 0b0000; > + let Inst{27-20} = 0b00011010; > +} > + > def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "", > [/* For disassembly only; pattern left blank */]>, > Requires<[IsARM, HasV6T2]> { > @@ -962,7 +975,7 @@ > // ARMv4T > // Note: Restrict $func to the tGPR regclass to prevent it being in LR. > def BX : ABXIx2<(outs), (ins tGPR:$func, variable_ops), > - IIC_Br, "mov\tlr, pc\n\tbx\t$func", > + IIC_Br, "bx\t$func", > [(ARMcall_nolink tGPR:$func)]>, > Requires<[IsARM, HasV4T, IsNotDarwin]> { > let Inst{7-4} = 0b0001; > @@ -972,7 +985,7 @@ > > // ARMv4 > def BMOVPCRX : ABXIx2<(outs), (ins tGPR:$func, variable_ops), > - IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func", > + IIC_Br, "mov\tpc, $func", > [(ARMcall_nolink tGPR:$func)]>, > Requires<[IsARM, NoV4T, IsNotDarwin]> { > let Inst{11-4} = 0b00000000; > @@ -1011,7 +1024,7 @@ > // ARMv4T > // Note: Restrict $func to the tGPR regclass to prevent it being in LR. > def BXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops), > - IIC_Br, "mov\tlr, pc\n\tbx\t$func", > + IIC_Br, "bx\t$func", > [(ARMcall_nolink tGPR:$func)]>, > Requires<[IsARM, HasV4T, IsDarwin]> { > let Inst{7-4} = 0b0001; > @@ -1021,7 +1034,7 @@ > > // ARMv4 > def BMOVPCRXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops), > - IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func", > + IIC_Br, "mov\tpc, $func", > [(ARMcall_nolink tGPR:$func)]>, > Requires<[IsARM, NoV4T, IsDarwin]> { > let Inst{11-4} = 0b00000000; > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From bruno.cardoso at gmail.com Mon Jul 12 15:06:32 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Mon, 12 Jul 2010 20:06:32 -0000 Subject: [llvm-commits] [llvm] r108184 - in /llvm/trunk: lib/Target/X86/X86InstrSSE.td test/MC/AsmParser/X86/x86_32-encoding.s test/MC/AsmParser/X86/x86_64-encoding.s Message-ID: <20100712200633.1B8222A6C12C@llvm.org> Author: bruno Date: Mon Jul 12 15:06:32 2010 New Revision: 108184 URL: http://llvm.org/viewvc/llvm-project?rev=108184&view=rev Log: Add AVX 256-bit MOVMSK forms Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=108184&r1=108183&r2=108184&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Jul 12 15:06:32 2010 @@ -1598,6 +1598,12 @@ defm VMOVMSKPD : sse12_extr_sign_mask, OpSize, VEX; + // FIXME: merge with multiclass above when the intrinsics come. + def VMOVMSKPSYrr : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src), + "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX; + def VMOVMSKPDYrr : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src), + "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize, + VEX; } //===----------------------------------------------------------------------===// Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s?rev=108184&r1=108183&r2=108184&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s Mon Jul 12 15:06:32 2010 @@ -12398,4 +12398,11 @@ // CHECK: encoding: [0xc5,0xfc,0x2b,0x08] vmovntps %ymm1, (%eax) +// CHECK: vmovmskps %xmm2, %eax +// CHECK: encoding: [0xc5,0xf8,0x50,0xc2] + vmovmskps %xmm2, %eax + +// CHECK: vmovmskpd %xmm2, %eax +// CHECK: encoding: [0xc5,0xf9,0x50,0xc2] + vmovmskpd %xmm2, %eax Modified: llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s?rev=108184&r1=108183&r2=108184&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s Mon Jul 12 15:06:32 2010 @@ -2472,3 +2472,11 @@ // CHECK: encoding: [0xc5,0x7c,0x2b,0x18] vmovntps %ymm11, (%rax) +// CHECK: vmovmskps %xmm12, %eax +// CHECK: encoding: [0xc4,0xc1,0x78,0x50,0xc4] + vmovmskps %xmm12, %eax + +// CHECK: vmovmskpd %xmm12, %eax +// CHECK: encoding: [0xc4,0xc1,0x79,0x50,0xc4] + vmovmskpd %xmm12, %eax + From daniel at zuster.org Mon Jul 12 15:08:04 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 12 Jul 2010 20:08:04 -0000 Subject: [llvm-commits] [llvm] r108185 - /llvm/trunk/lib/MC/MCParser/AsmParser.cpp Message-ID: <20100712200804.A0BD42A6C12C@llvm.org> Author: ddunbar Date: Mon Jul 12 15:08:04 2010 New Revision: 108185 URL: http://llvm.org/viewvc/llvm-project?rev=108185&view=rev Log: MC/AsmParser: Add a basic ELFAsmParser extension. Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=108185&r1=108184&r2=108185&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Mon Jul 12 15:08:04 2010 @@ -18,6 +18,7 @@ #include "llvm/MC/MCContext.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" +#include "llvm/MC/MCSectionELF.h" #include "llvm/MC/MCSectionMachO.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSymbol.h" @@ -101,6 +102,35 @@ bool ParseDirectiveZerofill(StringRef, SMLoc); }; +class ELFAsmParser : public MCAsmParserExtension { + bool ParseSectionSwitch(StringRef Section, unsigned Type, + unsigned Flags, SectionKind Kind); + +public: + ELFAsmParser() {} + + virtual void Initialize(MCAsmParser &Parser) { + // Call the base implementation. + this->MCAsmParserExtension::Initialize(Parser); + + Parser.AddDirectiveHandler(this, ".data", MCAsmParser::DirectiveHandler( + &ELFAsmParser::ParseSectionDirectiveData)); + Parser.AddDirectiveHandler(this, ".text", MCAsmParser::DirectiveHandler( + &ELFAsmParser::ParseSectionDirectiveText)); + } + + bool ParseSectionDirectiveData(StringRef, SMLoc) { + return ParseSectionSwitch(".data", MCSectionELF::SHT_PROGBITS, + MCSectionELF::SHF_WRITE |MCSectionELF::SHF_ALLOC, + SectionKind::getDataRel()); + } + bool ParseSectionDirectiveText(StringRef, SMLoc) { + return ParseSectionSwitch(".text", MCSectionELF::SHT_PROGBITS, + MCSectionELF::SHF_EXECINSTR | + MCSectionELF::SHF_ALLOC, SectionKind::getText()); + } +}; + } enum { DEFAULT_ADDRSPACE = 0 }; @@ -122,6 +152,9 @@ if (_MAI.hasSubsectionsViaSymbols()) { PlatformParser = new DarwinAsmParser; PlatformParser->Initialize(*this); + } else { + PlatformParser = new ELFAsmParser; + PlatformParser->Initialize(*this); } } @@ -1051,6 +1084,18 @@ return false; } +bool ELFAsmParser::ParseSectionSwitch(StringRef Section, unsigned Type, + unsigned Flags, SectionKind Kind) { + if (getLexer().isNot(AsmToken::EndOfStatement)) + return TokError("unexpected token in section switching directive"); + Lex(); + + getStreamer().SwitchSection(getContext().getELFSection( + Section, Type, Flags, Kind)); + + return false; +} + bool AsmParser::ParseEscapedString(std::string &Data) { assert(getLexer().is(AsmToken::String) && "Unexpected current token!"); From bob.wilson at apple.com Mon Jul 12 15:22:45 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Mon, 12 Jul 2010 20:22:45 -0000 Subject: [llvm-commits] [llvm] r108186 - /llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Message-ID: <20100712202245.DCB6B2A6C12C@llvm.org> Author: bwilson Date: Mon Jul 12 15:22:45 2010 New Revision: 108186 URL: http://llvm.org/viewvc/llvm-project?rev=108186&view=rev Log: Remove some code that doesn't appear to do anything. All the ARM call instructions already have implicit defs of LR. The comment suggests that this is intended to fix something like pr6111, but it doesn't really do that either. Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=108186&r1=108185&r2=108186&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Mon Jul 12 15:22:45 2010 @@ -1284,11 +1284,6 @@ ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL) : ARMISD::CALL_NOLINK; } - if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb1Only()) { - // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK - Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(MVT::i32),InFlag); - InFlag = Chain.getValue(1); - } std::vector Ops; Ops.push_back(Chain); From xerxes at zafena.se Mon Jul 12 15:23:27 2010 From: xerxes at zafena.se (Xerxes Ranby) Date: Mon, 12 Jul 2010 22:23:27 +0200 Subject: [llvm-commits] (patch) PR7608 ARMv4 JIT forgets to set the lr register when making a indirect function call In-Reply-To: References: <4C3A4388.1040703@zafena.se> Message-ID: <4C3B79BF.3080303@zafena.se> Bob Wilson wrote: > I don't think this is good enough. The "mov lr, pc" instruction must be emitted immediately before the call. I don't know how to do that without making all the "call_nolink" instructions into pseudo-instructions. When writing the patch i had these references in mind: http://wiki.llvm.org/Flags http://www.nabble.com/-RFC%2C-ARM--expanding-RET-to-CopyToReg-BRIND-to4625955.html#a4632200 "Flag in the SelectionDAG stuff is so named because it was originally used for condition codes. However, it has since grown to mean "keep these two nodes always together". In the case of return, you want the scheduler to produce code like this (on PPC): ... R3 = outval_virtreg blr not like this: ... R3 = outval_virtreg ... blr So the copy and blr are flagged together. " I have got the understanding that by flagging two instructions together are the mechanism to use in order to prevent something-else from getting scheduled in between. Have this changed? Where can I find documentation on what pseudo instructions are and how pseudo instructions can resolve this kind of situation? > That is kind of ugly because there are a fair number of those "call_nolink" instructions, but I can't think of anything better. > > (And, if it weren't for that blocking issue, I'd recommend changing the MOVLRPC instruction to explicitly define LR, What do I have to do more than let Defs = [LR] in order to make MOVLRPC explicitly define LR? +let Defs = [LR], hasSideEffects = 1 in +def MOVLRPC : AI<(outs), (ins), BrMiscFrm, IIC_Br, + "mov", "\tlr, pc", [(ARMmovlrpc)]>, Cheers and have a great day! Xerxes > and changing all the "call_nolink" instructions to use LR. That would prevent LR from being clobbered between the MOVLRPC and the call. But, it's not good enough to prevent some other instruction being scheduled between them.....) > > On Jul 11, 2010, at 3:19 PM, Xerxes Ranby wrote: > > >> http://llvm.org/bugs/show_bug.cgi?id=7608 >> Attached patch fixes the PR7608 bug by defining a new ARM selection dag node >> ARMmovlrpc and makes sure both jit and non-jit got a ARMmovlrpc chained and >> flagged before any ARMcall_nolink non-tailcall selection dag node. >> * llvm/lib/Target/ARM/ARMISelLowering.cpp >> (ARMTargetLowering::getTargetNodeName): Update to handle ARMISD::MOVLRPC. >> (ARMTargetLowering::LowerCall): Add chain and flag a ARMmovlrpc before any >> ARMcall_nolink non-tailcall selection dag node. >> * llvm/lib/Target/ARM/ARMISelLowering.h >> (ARMISD::MOVLRPC): New enum. >> * llvm/lib/Target/ARM/ARMInstrInfo.td >> (ARMmovlrpc): New defined selection dag node. >> (MOVLRPC): New defined instruction. >> (BX): Emit only one instruction for non-jit. >> (BMOVPCRX): Likewise. >> (BXr9): Likewise. >> (BMOVPCRXr9): Likewise. >> >> Ok to push? >> >> Cheers >> Xerxes >> >> Index: llvm/lib/Target/ARM/ARMISelLowering.cpp >> =================================================================== >> --- llvm.orig/lib/Target/ARM/ARMISelLowering.cpp 2010-07-11 12:57:59.000000000 +0200 >> +++ llvm/lib/Target/ARM/ARMISelLowering.cpp 2010-07-11 22:07:28.000000000 +0200 >> @@ -560,6 +560,7 @@ >> case ARMISD::BR_JT: return "ARMISD::BR_JT"; >> case ARMISD::BR2_JT: return "ARMISD::BR2_JT"; >> case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG"; >> + case ARMISD::MOVLRPC: return "ARMISD::MOVLRPC"; >> case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD"; >> case ARMISD::CMP: return "ARMISD::CMP"; >> case ARMISD::CMPZ: return "ARMISD::CMPZ"; >> @@ -1288,6 +1289,14 @@ >> // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK >> Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(MVT::i32),InFlag); >> InFlag = Chain.getValue(1); >> + >> + if(!isTailCall){ >> + // explicit copy PC to LR and chain flag it to the call. >> + Chain = DAG.getNode(ARMISD::MOVLRPC, dl, >> + DAG.getVTList(MVT::Other, MVT::Flag), >> + Chain, InFlag); >> + InFlag = Chain.getValue(1); >> + } >> } >> >> std::vector Ops; >> Index: llvm/lib/Target/ARM/ARMISelLowering.h >> =================================================================== >> --- llvm.orig/lib/Target/ARM/ARMISelLowering.h 2010-07-11 12:57:59.000000000 +0200 >> +++ llvm/lib/Target/ARM/ARMISelLowering.h 2010-07-11 12:59:02.000000000 +0200 >> @@ -42,6 +42,7 @@ >> BR_JT, // Jumptable branch. >> BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump). >> RET_FLAG, // Return with a flag operand. >> + MOVLRPC, // Store return address PC in LR before call - flag before CALL_NOLINK >> >> PIC_ADD, // Add with a PC operand and a PIC label. >> >> Index: llvm/lib/Target/ARM/ARMInstrInfo.td >> =================================================================== >> --- llvm.orig/lib/Target/ARM/ARMInstrInfo.td 2010-07-11 12:57:59.000000000 +0200 >> +++ llvm/lib/Target/ARM/ARMInstrInfo.td 2010-07-11 12:59:02.000000000 +0200 >> @@ -74,6 +74,9 @@ >> [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag, >> SDNPVariadic]>; >> >> +def ARMmovlrpc : SDNode<"ARMISD::MOVLRPC", SDTNone, >> + [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; >> + >> def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone, >> [SDNPHasChain, SDNPOptInFlag]>; >> >> @@ -674,6 +677,16 @@ >> [(ARMcallseq_start timm:$amt)]>; >> } >> >> +let Defs = [LR], hasSideEffects = 1 in >> +def MOVLRPC : AI<(outs), (ins), BrMiscFrm, IIC_Br, >> + "mov", "\tlr, pc", [(ARMmovlrpc)]>, >> + Requires<[IsARM]> { >> + let Inst{11-0} = 0b000000001111; >> + let Inst{15-12} = 0b1110; >> + let Inst{19-16} = 0b0000; >> + let Inst{27-20} = 0b00011010; >> +} >> + >> def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "", >> [/* For disassembly only; pattern left blank */]>, >> Requires<[IsARM, HasV6T2]> { >> @@ -962,7 +975,7 @@ >> // ARMv4T >> // Note: Restrict $func to the tGPR regclass to prevent it being in LR. >> def BX : ABXIx2<(outs), (ins tGPR:$func, variable_ops), >> - IIC_Br, "mov\tlr, pc\n\tbx\t$func", >> + IIC_Br, "bx\t$func", >> [(ARMcall_nolink tGPR:$func)]>, >> Requires<[IsARM, HasV4T, IsNotDarwin]> { >> let Inst{7-4} = 0b0001; >> @@ -972,7 +985,7 @@ >> >> // ARMv4 >> def BMOVPCRX : ABXIx2<(outs), (ins tGPR:$func, variable_ops), >> - IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func", >> + IIC_Br, "mov\tpc, $func", >> [(ARMcall_nolink tGPR:$func)]>, >> Requires<[IsARM, NoV4T, IsNotDarwin]> { >> let Inst{11-4} = 0b00000000; >> @@ -1011,7 +1024,7 @@ >> // ARMv4T >> // Note: Restrict $func to the tGPR regclass to prevent it being in LR. >> def BXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops), >> - IIC_Br, "mov\tlr, pc\n\tbx\t$func", >> + IIC_Br, "bx\t$func", >> [(ARMcall_nolink tGPR:$func)]>, >> Requires<[IsARM, HasV4T, IsDarwin]> { >> let Inst{7-4} = 0b0001; >> @@ -1021,7 +1034,7 @@ >> >> // ARMv4 >> def BMOVPCRXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops), >> - IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func", >> + IIC_Br, "mov\tpc, $func", >> [(ARMcall_nolink tGPR:$func)]>, >> Requires<[IsARM, NoV4T, IsDarwin]> { >> let Inst{11-4} = 0b00000000; >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> > > From daniel at zuster.org Mon Jul 12 15:23:36 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 12 Jul 2010 20:23:36 -0000 Subject: [llvm-commits] [llvm] r108187 - in /llvm/trunk: include/llvm/MC/MCParser/AsmParser.h lib/MC/MCParser/AsmParser.cpp Message-ID: <20100712202336.41AAE2A6C12C@llvm.org> Author: ddunbar Date: Mon Jul 12 15:23:36 2010 New Revision: 108187 URL: http://llvm.org/viewvc/llvm-project?rev=108187&view=rev Log: MC/AsmParser: Move special section directive parsing to Darwin specific parser. Modified: llvm/trunk/include/llvm/MC/MCParser/AsmParser.h llvm/trunk/lib/MC/MCParser/AsmParser.cpp Modified: llvm/trunk/include/llvm/MC/MCParser/AsmParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/AsmParser.h?rev=108187&r1=108186&r2=108187&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCParser/AsmParser.h (original) +++ llvm/trunk/include/llvm/MC/MCParser/AsmParser.h Mon Jul 12 15:23:36 2010 @@ -119,9 +119,6 @@ // Directive Parsing. bool ParseDirectiveDarwinSection(); // Darwin specific ".section". - bool ParseDirectiveSectionSwitch(const char *Segment, const char *Section, - unsigned TAA = 0, unsigned ImplicitAlign = 0, - unsigned StubSize = 0); bool ParseDirectiveAscii(bool ZeroTerminated); // ".ascii", ".asciiz" bool ParseDirectiveValue(unsigned Size); // ".byte", ".long", ... bool ParseDirectiveFill(); // ".fill" Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=108187&r1=108186&r2=108187&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Mon Jul 12 15:23:36 2010 @@ -60,6 +60,10 @@ /// \brief Implementation of directive handling which is shared across all /// Darwin targets. class DarwinAsmParser : public MCAsmParserExtension { + bool ParseSectionSwitch(const char *Segment, const char *Section, + unsigned TAA = 0, unsigned ImplicitAlign = 0, + unsigned StubSize = 0); + public: DarwinAsmParser() {} @@ -90,6 +94,137 @@ Parser.AddDirectiveHandler(this, ".zerofill", MCAsmParser::DirectiveHandler( &DarwinAsmParser::ParseDirectiveZerofill)); + + // Special section directives. + Parser.AddDirectiveHandler(this, ".const", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveConst)); + Parser.AddDirectiveHandler(this, ".const_data", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveConstData)); + Parser.AddDirectiveHandler(this, ".constructor", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveConstructor)); + Parser.AddDirectiveHandler(this, ".cstring", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveCString)); + Parser.AddDirectiveHandler(this, ".data", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveData)); + Parser.AddDirectiveHandler(this, ".destructor", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveDestructor)); + Parser.AddDirectiveHandler(this, ".dyld", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveDyld)); + Parser.AddDirectiveHandler(this, ".fvmlib_init0", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveFVMLibInit0)); + Parser.AddDirectiveHandler(this, ".fvmlib_init1", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveFVMLibInit1)); + Parser.AddDirectiveHandler(this, ".lazy_symbol_pointer", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveLazySymbolPointers)); + Parser.AddDirectiveHandler(this, ".literal16", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveLiteral16)); + Parser.AddDirectiveHandler(this, ".literal4", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveLiteral4)); + Parser.AddDirectiveHandler(this, ".literal8", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveLiteral8)); + Parser.AddDirectiveHandler(this, ".mod_init_func", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveModInitFunc)); + Parser.AddDirectiveHandler(this, ".mod_term_func", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveModTermFunc)); + Parser.AddDirectiveHandler(this, ".non_lazy_symbol_pointer", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveNonLazySymbolPointers)); + Parser.AddDirectiveHandler(this, ".objc_cat_cls_meth", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveObjCCatClsMeth)); + Parser.AddDirectiveHandler(this, ".objc_cat_inst_meth", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveObjCCatInstMeth)); + Parser.AddDirectiveHandler(this, ".objc_category", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveObjCCategory)); + Parser.AddDirectiveHandler(this, ".objc_class", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveObjCClass)); + Parser.AddDirectiveHandler(this, ".objc_class_names", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveObjCClassNames)); + Parser.AddDirectiveHandler(this, ".objc_class_vars", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveObjCClassVars)); + Parser.AddDirectiveHandler(this, ".objc_cls_meth", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveObjCClsMeth)); + Parser.AddDirectiveHandler(this, ".objc_cls_refs", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveObjCClsRefs)); + Parser.AddDirectiveHandler(this, ".objc_inst_meth", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveObjCInstMeth)); + Parser.AddDirectiveHandler(this, ".objc_instance_vars", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveObjCInstanceVars)); + Parser.AddDirectiveHandler(this, ".objc_message_refs", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveObjCMessageRefs)); + Parser.AddDirectiveHandler(this, ".objc_meta_class", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveObjCMetaClass)); + Parser.AddDirectiveHandler(this, ".objc_meth_var_names", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveObjCMethVarNames)); + Parser.AddDirectiveHandler(this, ".objc_meth_var_types", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveObjCMethVarTypes)); + Parser.AddDirectiveHandler(this, ".objc_module_info", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveObjCModuleInfo)); + Parser.AddDirectiveHandler(this, ".objc_protocol", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveObjCProtocol)); + Parser.AddDirectiveHandler(this, ".objc_selector_strs", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveObjCSelectorStrs)); + Parser.AddDirectiveHandler(this, ".objc_string_object", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveObjCStringObject)); + Parser.AddDirectiveHandler(this, ".objc_symbols", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveObjCSymbols)); + Parser.AddDirectiveHandler(this, ".picsymbol_stub", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectivePICSymbolStub)); + Parser.AddDirectiveHandler(this, ".static_const", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveStaticConst)); + Parser.AddDirectiveHandler(this, ".static_data", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveStaticData)); + Parser.AddDirectiveHandler(this, ".symbol_stub", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveSymbolStub)); + Parser.AddDirectiveHandler(this, ".tdata", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveTData)); + Parser.AddDirectiveHandler(this, ".text", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveText)); + Parser.AddDirectiveHandler(this, ".thread_init_func", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveThreadInitFunc)); + Parser.AddDirectiveHandler(this, ".tlv", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveTLV)); } bool ParseDirectiveDesc(StringRef, SMLoc); @@ -100,6 +235,177 @@ bool ParseDirectiveSubsectionsViaSymbols(StringRef, SMLoc); bool ParseDirectiveTBSS(StringRef, SMLoc); bool ParseDirectiveZerofill(StringRef, SMLoc); + + // Named Section Directive + bool ParseSectionDirectiveConst(StringRef, SMLoc) { + return ParseSectionSwitch("__TEXT", "__const"); + } + bool ParseSectionDirectiveStaticConst(StringRef, SMLoc) { + return ParseSectionSwitch("__TEXT", "__static_const"); + } + bool ParseSectionDirectiveCString(StringRef, SMLoc) { + return ParseSectionSwitch("__TEXT","__cstring", + MCSectionMachO::S_CSTRING_LITERALS); + } + bool ParseSectionDirectiveLiteral4(StringRef, SMLoc) { + return ParseSectionSwitch("__TEXT", "__literal4", + MCSectionMachO::S_4BYTE_LITERALS, 4); + } + bool ParseSectionDirectiveLiteral8(StringRef, SMLoc) { + return ParseSectionSwitch("__TEXT", "__literal8", + MCSectionMachO::S_8BYTE_LITERALS, 8); + } + bool ParseSectionDirectiveLiteral16(StringRef, SMLoc) { + return ParseSectionSwitch("__TEXT","__literal16", + MCSectionMachO::S_16BYTE_LITERALS, 16); + } + bool ParseSectionDirectiveConstructor(StringRef, SMLoc) { + return ParseSectionSwitch("__TEXT","__constructor"); + } + bool ParseSectionDirectiveDestructor(StringRef, SMLoc) { + return ParseSectionSwitch("__TEXT","__destructor"); + } + bool ParseSectionDirectiveFVMLibInit0(StringRef, SMLoc) { + return ParseSectionSwitch("__TEXT","__fvmlib_init0"); + } + bool ParseSectionDirectiveFVMLibInit1(StringRef, SMLoc) { + return ParseSectionSwitch("__TEXT","__fvmlib_init1"); + } + bool ParseSectionDirectiveSymbolStub(StringRef, SMLoc) { + return ParseSectionSwitch("__TEXT","__symbol_stub", + MCSectionMachO::S_SYMBOL_STUBS | + MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS, + // FIXME: Different on PPC and ARM. + 0, 16); + } + bool ParseSectionDirectivePICSymbolStub(StringRef, SMLoc) { + return ParseSectionSwitch("__TEXT","__picsymbol_stub", + MCSectionMachO::S_SYMBOL_STUBS | + MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS, 0, 26); + } + bool ParseSectionDirectiveData(StringRef, SMLoc) { + return ParseSectionSwitch("__DATA", "__data"); + } + bool ParseSectionDirectiveStaticData(StringRef, SMLoc) { + return ParseSectionSwitch("__DATA", "__static_data"); + } + bool ParseSectionDirectiveNonLazySymbolPointers(StringRef, SMLoc) { + return ParseSectionSwitch("__DATA", "__nl_symbol_ptr", + MCSectionMachO::S_NON_LAZY_SYMBOL_POINTERS, 4); + } + bool ParseSectionDirectiveLazySymbolPointers(StringRef, SMLoc) { + return ParseSectionSwitch("__DATA", "__la_symbol_ptr", + MCSectionMachO::S_LAZY_SYMBOL_POINTERS, 4); + } + bool ParseSectionDirectiveDyld(StringRef, SMLoc) { + return ParseSectionSwitch("__DATA", "__dyld"); + } + bool ParseSectionDirectiveModInitFunc(StringRef, SMLoc) { + return ParseSectionSwitch("__DATA", "__mod_init_func", + MCSectionMachO::S_MOD_INIT_FUNC_POINTERS, 4); + } + bool ParseSectionDirectiveModTermFunc(StringRef, SMLoc) { + return ParseSectionSwitch("__DATA", "__mod_term_func", + MCSectionMachO::S_MOD_TERM_FUNC_POINTERS, 4); + } + bool ParseSectionDirectiveConstData(StringRef, SMLoc) { + return ParseSectionSwitch("__DATA", "__const"); + } + bool ParseSectionDirectiveObjCClass(StringRef, SMLoc) { + return ParseSectionSwitch("__OBJC", "__class", + MCSectionMachO::S_ATTR_NO_DEAD_STRIP); + } + bool ParseSectionDirectiveObjCMetaClass(StringRef, SMLoc) { + return ParseSectionSwitch("__OBJC", "__meta_class", + MCSectionMachO::S_ATTR_NO_DEAD_STRIP); + } + bool ParseSectionDirectiveObjCCatClsMeth(StringRef, SMLoc) { + return ParseSectionSwitch("__OBJC", "__cat_cls_meth", + MCSectionMachO::S_ATTR_NO_DEAD_STRIP); + } + bool ParseSectionDirectiveObjCCatInstMeth(StringRef, SMLoc) { + return ParseSectionSwitch("__OBJC", "__cat_inst_meth", + MCSectionMachO::S_ATTR_NO_DEAD_STRIP); + } + bool ParseSectionDirectiveObjCProtocol(StringRef, SMLoc) { + return ParseSectionSwitch("__OBJC", "__protocol", + MCSectionMachO::S_ATTR_NO_DEAD_STRIP); + } + bool ParseSectionDirectiveObjCStringObject(StringRef, SMLoc) { + return ParseSectionSwitch("__OBJC", "__string_object", + MCSectionMachO::S_ATTR_NO_DEAD_STRIP); + } + bool ParseSectionDirectiveObjCClsMeth(StringRef, SMLoc) { + return ParseSectionSwitch("__OBJC", "__cls_meth", + MCSectionMachO::S_ATTR_NO_DEAD_STRIP); + } + bool ParseSectionDirectiveObjCInstMeth(StringRef, SMLoc) { + return ParseSectionSwitch("__OBJC", "__inst_meth", + MCSectionMachO::S_ATTR_NO_DEAD_STRIP); + } + bool ParseSectionDirectiveObjCClsRefs(StringRef, SMLoc) { + return ParseSectionSwitch("__OBJC", "__cls_refs", + MCSectionMachO::S_ATTR_NO_DEAD_STRIP | + MCSectionMachO::S_LITERAL_POINTERS, 4); + } + bool ParseSectionDirectiveObjCMessageRefs(StringRef, SMLoc) { + return ParseSectionSwitch("__OBJC", "__message_refs", + MCSectionMachO::S_ATTR_NO_DEAD_STRIP | + MCSectionMachO::S_LITERAL_POINTERS, 4); + } + bool ParseSectionDirectiveObjCSymbols(StringRef, SMLoc) { + return ParseSectionSwitch("__OBJC", "__symbols", + MCSectionMachO::S_ATTR_NO_DEAD_STRIP); + } + bool ParseSectionDirectiveObjCCategory(StringRef, SMLoc) { + return ParseSectionSwitch("__OBJC", "__category", + MCSectionMachO::S_ATTR_NO_DEAD_STRIP); + } + bool ParseSectionDirectiveObjCClassVars(StringRef, SMLoc) { + return ParseSectionSwitch("__OBJC", "__class_vars", + MCSectionMachO::S_ATTR_NO_DEAD_STRIP); + } + bool ParseSectionDirectiveObjCInstanceVars(StringRef, SMLoc) { + return ParseSectionSwitch("__OBJC", "__instance_vars", + MCSectionMachO::S_ATTR_NO_DEAD_STRIP); + } + bool ParseSectionDirectiveObjCModuleInfo(StringRef, SMLoc) { + return ParseSectionSwitch("__OBJC", "__module_info", + MCSectionMachO::S_ATTR_NO_DEAD_STRIP); + } + bool ParseSectionDirectiveObjCClassNames(StringRef, SMLoc) { + return ParseSectionSwitch("__TEXT", "__cstring", + MCSectionMachO::S_CSTRING_LITERALS); + } + bool ParseSectionDirectiveObjCMethVarTypes(StringRef, SMLoc) { + return ParseSectionSwitch("__TEXT", "__cstring", + MCSectionMachO::S_CSTRING_LITERALS); + } + bool ParseSectionDirectiveObjCMethVarNames(StringRef, SMLoc) { + return ParseSectionSwitch("__TEXT", "__cstring", + MCSectionMachO::S_CSTRING_LITERALS); + } + bool ParseSectionDirectiveObjCSelectorStrs(StringRef, SMLoc) { + return ParseSectionSwitch("__OBJC", "__selector_strs", + MCSectionMachO::S_CSTRING_LITERALS); + } + bool ParseSectionDirectiveTData(StringRef, SMLoc) { + return ParseSectionSwitch("__DATA", "__thread_data", + MCSectionMachO::S_THREAD_LOCAL_REGULAR); + } + bool ParseSectionDirectiveText(StringRef, SMLoc) { + return ParseSectionSwitch("__TEXT", "__text", + MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS); + } + bool ParseSectionDirectiveTLV(StringRef, SMLoc) { + return ParseSectionSwitch("__DATA", "__thread_vars", + MCSectionMachO::S_THREAD_LOCAL_VARIABLES); + } + bool ParseSectionDirectiveThreadInitFunc(StringRef, SMLoc) { + return ParseSectionSwitch("__DATA", "__thread_init", + MCSectionMachO::S_THREAD_LOCAL_INIT_FUNCTION_POINTERS); + } + }; class ELFAsmParser : public MCAsmParserExtension { @@ -644,155 +950,7 @@ // FIXME: This should be driven based on a hash lookup and callback. if (IDVal == ".section") return ParseDirectiveDarwinSection(); - if (IDVal == ".text") - // FIXME: This changes behavior based on the -static flag to the - // assembler. - return ParseDirectiveSectionSwitch("__TEXT", "__text", - MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS); - if (IDVal == ".const") - return ParseDirectiveSectionSwitch("__TEXT", "__const"); - if (IDVal == ".static_const") - return ParseDirectiveSectionSwitch("__TEXT", "__static_const"); - if (IDVal == ".cstring") - return ParseDirectiveSectionSwitch("__TEXT","__cstring", - MCSectionMachO::S_CSTRING_LITERALS); - if (IDVal == ".literal4") - return ParseDirectiveSectionSwitch("__TEXT", "__literal4", - MCSectionMachO::S_4BYTE_LITERALS, - 4); - if (IDVal == ".literal8") - return ParseDirectiveSectionSwitch("__TEXT", "__literal8", - MCSectionMachO::S_8BYTE_LITERALS, - 8); - if (IDVal == ".literal16") - return ParseDirectiveSectionSwitch("__TEXT","__literal16", - MCSectionMachO::S_16BYTE_LITERALS, - 16); - if (IDVal == ".constructor") - return ParseDirectiveSectionSwitch("__TEXT","__constructor"); - if (IDVal == ".destructor") - return ParseDirectiveSectionSwitch("__TEXT","__destructor"); - if (IDVal == ".fvmlib_init0") - return ParseDirectiveSectionSwitch("__TEXT","__fvmlib_init0"); - if (IDVal == ".fvmlib_init1") - return ParseDirectiveSectionSwitch("__TEXT","__fvmlib_init1"); - - // FIXME: The assembler manual claims that this has the self modify code - // flag, at least on x86-32, but that does not appear to be correct. - if (IDVal == ".symbol_stub") - return ParseDirectiveSectionSwitch("__TEXT","__symbol_stub", - MCSectionMachO::S_SYMBOL_STUBS | - MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS, - // FIXME: Different on PPC and ARM. - 0, 16); - // FIXME: PowerPC only? - if (IDVal == ".picsymbol_stub") - return ParseDirectiveSectionSwitch("__TEXT","__picsymbol_stub", - MCSectionMachO::S_SYMBOL_STUBS | - MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS, - 0, 26); - if (IDVal == ".data") - return ParseDirectiveSectionSwitch("__DATA", "__data"); - if (IDVal == ".static_data") - return ParseDirectiveSectionSwitch("__DATA", "__static_data"); - - // FIXME: The section names of these two are misspelled in the assembler - // manual. - if (IDVal == ".non_lazy_symbol_pointer") - return ParseDirectiveSectionSwitch("__DATA", "__nl_symbol_ptr", - MCSectionMachO::S_NON_LAZY_SYMBOL_POINTERS, - 4); - if (IDVal == ".lazy_symbol_pointer") - return ParseDirectiveSectionSwitch("__DATA", "__la_symbol_ptr", - MCSectionMachO::S_LAZY_SYMBOL_POINTERS, - 4); - - if (IDVal == ".dyld") - return ParseDirectiveSectionSwitch("__DATA", "__dyld"); - if (IDVal == ".mod_init_func") - return ParseDirectiveSectionSwitch("__DATA", "__mod_init_func", - MCSectionMachO::S_MOD_INIT_FUNC_POINTERS, - 4); - if (IDVal == ".mod_term_func") - return ParseDirectiveSectionSwitch("__DATA", "__mod_term_func", - MCSectionMachO::S_MOD_TERM_FUNC_POINTERS, - 4); - if (IDVal == ".const_data") - return ParseDirectiveSectionSwitch("__DATA", "__const"); - - - if (IDVal == ".objc_class") - return ParseDirectiveSectionSwitch("__OBJC", "__class", - MCSectionMachO::S_ATTR_NO_DEAD_STRIP); - if (IDVal == ".objc_meta_class") - return ParseDirectiveSectionSwitch("__OBJC", "__meta_class", - MCSectionMachO::S_ATTR_NO_DEAD_STRIP); - if (IDVal == ".objc_cat_cls_meth") - return ParseDirectiveSectionSwitch("__OBJC", "__cat_cls_meth", - MCSectionMachO::S_ATTR_NO_DEAD_STRIP); - if (IDVal == ".objc_cat_inst_meth") - return ParseDirectiveSectionSwitch("__OBJC", "__cat_inst_meth", - MCSectionMachO::S_ATTR_NO_DEAD_STRIP); - if (IDVal == ".objc_protocol") - return ParseDirectiveSectionSwitch("__OBJC", "__protocol", - MCSectionMachO::S_ATTR_NO_DEAD_STRIP); - if (IDVal == ".objc_string_object") - return ParseDirectiveSectionSwitch("__OBJC", "__string_object", - MCSectionMachO::S_ATTR_NO_DEAD_STRIP); - if (IDVal == ".objc_cls_meth") - return ParseDirectiveSectionSwitch("__OBJC", "__cls_meth", - MCSectionMachO::S_ATTR_NO_DEAD_STRIP); - if (IDVal == ".objc_inst_meth") - return ParseDirectiveSectionSwitch("__OBJC", "__inst_meth", - MCSectionMachO::S_ATTR_NO_DEAD_STRIP); - if (IDVal == ".objc_cls_refs") - return ParseDirectiveSectionSwitch("__OBJC", "__cls_refs", - MCSectionMachO::S_ATTR_NO_DEAD_STRIP | - MCSectionMachO::S_LITERAL_POINTERS, - 4); - if (IDVal == ".objc_message_refs") - return ParseDirectiveSectionSwitch("__OBJC", "__message_refs", - MCSectionMachO::S_ATTR_NO_DEAD_STRIP | - MCSectionMachO::S_LITERAL_POINTERS, - 4); - if (IDVal == ".objc_symbols") - return ParseDirectiveSectionSwitch("__OBJC", "__symbols", - MCSectionMachO::S_ATTR_NO_DEAD_STRIP); - if (IDVal == ".objc_category") - return ParseDirectiveSectionSwitch("__OBJC", "__category", - MCSectionMachO::S_ATTR_NO_DEAD_STRIP); - if (IDVal == ".objc_class_vars") - return ParseDirectiveSectionSwitch("__OBJC", "__class_vars", - MCSectionMachO::S_ATTR_NO_DEAD_STRIP); - if (IDVal == ".objc_instance_vars") - return ParseDirectiveSectionSwitch("__OBJC", "__instance_vars", - MCSectionMachO::S_ATTR_NO_DEAD_STRIP); - if (IDVal == ".objc_module_info") - return ParseDirectiveSectionSwitch("__OBJC", "__module_info", - MCSectionMachO::S_ATTR_NO_DEAD_STRIP); - if (IDVal == ".objc_class_names") - return ParseDirectiveSectionSwitch("__TEXT", "__cstring", - MCSectionMachO::S_CSTRING_LITERALS); - if (IDVal == ".objc_meth_var_types") - return ParseDirectiveSectionSwitch("__TEXT", "__cstring", - MCSectionMachO::S_CSTRING_LITERALS); - if (IDVal == ".objc_meth_var_names") - return ParseDirectiveSectionSwitch("__TEXT", "__cstring", - MCSectionMachO::S_CSTRING_LITERALS); - if (IDVal == ".objc_selector_strs") - return ParseDirectiveSectionSwitch("__OBJC", "__selector_strs", - MCSectionMachO::S_CSTRING_LITERALS); - - if (IDVal == ".tdata") - return ParseDirectiveSectionSwitch("__DATA", "__thread_data", - MCSectionMachO::S_THREAD_LOCAL_REGULAR); - if (IDVal == ".tlv") - return ParseDirectiveSectionSwitch("__DATA", "__thread_vars", - MCSectionMachO::S_THREAD_LOCAL_VARIABLES); - if (IDVal == ".thread_init_func") - return ParseDirectiveSectionSwitch("__DATA", "__thread_init", - MCSectionMachO::S_THREAD_LOCAL_INIT_FUNCTION_POINTERS); - + // Assembler features if (IDVal == ".set") return ParseDirectiveSet(); @@ -1055,20 +1213,20 @@ return false; } -/// ParseDirectiveSectionSwitch - -bool AsmParser::ParseDirectiveSectionSwitch(const char *Segment, - const char *Section, - unsigned TAA, unsigned Align, - unsigned StubSize) { +bool DarwinAsmParser::ParseSectionSwitch(const char *Segment, + const char *Section, + unsigned TAA, unsigned Align, + unsigned StubSize) { if (getLexer().isNot(AsmToken::EndOfStatement)) return TokError("unexpected token in section switching directive"); Lex(); - + // FIXME: Arch specific. bool isText = StringRef(Segment) == "__TEXT"; // FIXME: Hack. - getStreamer().SwitchSection(Ctx.getMachOSection(Segment, Section, TAA, StubSize, - isText ? SectionKind::getText() - : SectionKind::getDataRel())); + getStreamer().SwitchSection(getContext().getMachOSection( + Segment, Section, TAA, StubSize, + isText ? SectionKind::getText() + : SectionKind::getDataRel())); // Set the implicit alignment, if any. // From isanbard at gmail.com Mon Jul 12 15:27:03 2010 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 12 Jul 2010 20:27:03 -0000 Subject: [llvm-commits] [llvm] r108188 - /llvm/trunk/include/llvm/ADT/EquivalenceClasses.h Message-ID: <20100712202703.234DE2A6C12C@llvm.org> Author: void Date: Mon Jul 12 15:27:02 2010 New Revision: 108188 URL: http://llvm.org/viewvc/llvm-project?rev=108188&view=rev Log: getOrInsertLeaderValue cannot be const because it calls insert. Patch by Xi Wang! Modified: llvm/trunk/include/llvm/ADT/EquivalenceClasses.h Modified: llvm/trunk/include/llvm/ADT/EquivalenceClasses.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/EquivalenceClasses.h?rev=108188&r1=108187&r2=108188&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/EquivalenceClasses.h (original) +++ llvm/trunk/include/llvm/ADT/EquivalenceClasses.h Mon Jul 12 15:27:02 2010 @@ -169,7 +169,7 @@ /// getOrInsertLeaderValue - Return the leader for the specified value that is /// in the set. If the member is not in the set, it is inserted, then /// returned. - const ElemTy &getOrInsertLeaderValue(const ElemTy &V) const { + const ElemTy &getOrInsertLeaderValue(const ElemTy &V) { member_iterator MI = findLeader(insert(V)); assert(MI != member_end() && "Value is not in the set!"); return *MI; From daniel at zuster.org Mon Jul 12 15:32:33 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 12 Jul 2010 20:32:33 -0000 Subject: [llvm-commits] [llvm] r108189 - in /llvm/trunk/include/llvm/MC/MCParser: AsmLexer.h MCAsmLexer.h Message-ID: <20100712203233.770472A6C12C@llvm.org> Author: ddunbar Date: Mon Jul 12 15:32:33 2010 New Revision: 108189 URL: http://llvm.org/viewvc/llvm-project?rev=108189&view=rev Log: MC/AsmLexer: Raise LexUntilEndOfStatement to MCAsmLexer. Modified: llvm/trunk/include/llvm/MC/MCParser/AsmLexer.h llvm/trunk/include/llvm/MC/MCParser/MCAsmLexer.h Modified: llvm/trunk/include/llvm/MC/MCParser/AsmLexer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/AsmLexer.h?rev=108189&r1=108188&r2=108189&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCParser/AsmLexer.h (original) +++ llvm/trunk/include/llvm/MC/MCParser/AsmLexer.h Mon Jul 12 15:32:33 2010 @@ -46,7 +46,7 @@ void setBuffer(const MemoryBuffer *buf, const char *ptr = NULL); - StringRef LexUntilEndOfStatement(); + virtual StringRef LexUntilEndOfStatement(); bool isAtStartOfComment(char Char); Modified: llvm/trunk/include/llvm/MC/MCParser/MCAsmLexer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/MCAsmLexer.h?rev=108189&r1=108188&r2=108189&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCParser/MCAsmLexer.h (original) +++ llvm/trunk/include/llvm/MC/MCParser/MCAsmLexer.h Mon Jul 12 15:32:33 2010 @@ -143,6 +143,8 @@ return CurTok = LexToken(); } + virtual StringRef LexUntilEndOfStatement() = 0; + /// getLoc - Get the current source location. SMLoc getLoc() const; From bob.wilson at apple.com Mon Jul 12 15:35:05 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Mon, 12 Jul 2010 13:35:05 -0700 Subject: [llvm-commits] (patch) PR7608 ARMv4 JIT forgets to set the lr register when making a indirect function call In-Reply-To: <4C3B79BF.3080303@zafena.se> References: <4C3A4388.1040703@zafena.se> <4C3B79BF.3080303@zafena.se> Message-ID: On Jul 12, 2010, at 1:23 PM, Xerxes Ranby wrote: > Bob Wilson wrote: >> I don't think this is good enough. The "mov lr, pc" instruction must be emitted immediately before the call. I don't know how to do that without making all the "call_nolink" instructions into pseudo-instructions. > When writing the patch i had these references in mind: > http://wiki.llvm.org/Flags http://www.nabble.com/-RFC%2C-ARM--expanding-RET-to-CopyToReg-BRIND-to4625955.html#a4632200 > "Flag in the SelectionDAG stuff is so named because it was originally used > for condition codes. However, it has since grown to mean "keep these two > nodes always together". In the case of return, you want the scheduler to > produce code like this (on PPC): > > ... > R3 = outval_virtreg > blr > > not like this: > > ... > R3 = outval_virtreg > ... > blr > > So the copy and blr are flagged together. > " > > I have got the understanding that by flagging two instructions together are the mechanism to use in order to prevent something-else from getting scheduled in between. > Have this changed? No, I'm not aware that it has changed recently, but flagging and chaining only work at the SelectionDAG level. Once the code gets selected to MachineInstrs, there's nothing to keep things from moving around. > > Where can I find documentation on what pseudo instructions are and how pseudo instructions can resolve this kind of situation? Look at ARMCodeEmitter::emitPseudoInstruction for some examples. Basically you would just change the "call_nolink" instructions to be marked as pseudo instructions and then add code to ARMCodeEmitter to generate both the "mov lr, pc" and "bx" instructions together. >> That is kind of ugly because there are a fair number of those "call_nolink" instructions, but I can't think of anything better. >> >> (And, if it weren't for that blocking issue, I'd recommend changing the MOVLRPC instruction to explicitly define LR, > What do I have to do more than let Defs = [LR] in order to make MOVLRPC explicitly define LR? > > +let Defs = [LR], hasSideEffects = 1 in > +def MOVLRPC : AI<(outs), (ins), BrMiscFrm, IIC_Br, > + "mov", "\tlr, pc", [(ARMmovlrpc)]>, Oh, I guess I missed that. You would still need to make the "call_nolink" instruction use LR, but it's not really relevant because it won't solve the problem of keeping the mov/bx together. > > > Cheers and have a great day! > Xerxes > >> and changing all the "call_nolink" instructions to use LR. That would prevent LR from being clobbered between the MOVLRPC and the call. But, it's not good enough to prevent some other instruction being scheduled between them.....) >> >> On Jul 11, 2010, at 3:19 PM, Xerxes Ranby wrote: >> >> >>> http://llvm.org/bugs/show_bug.cgi?id=7608 >>> Attached patch fixes the PR7608 bug by defining a new ARM selection dag node >>> ARMmovlrpc and makes sure both jit and non-jit got a ARMmovlrpc chained and >>> flagged before any ARMcall_nolink non-tailcall selection dag node. * llvm/lib/Target/ARM/ARMISelLowering.cpp >>> (ARMTargetLowering::getTargetNodeName): Update to handle ARMISD::MOVLRPC. >>> (ARMTargetLowering::LowerCall): Add chain and flag a ARMmovlrpc before any >>> ARMcall_nolink non-tailcall selection dag node. >>> * llvm/lib/Target/ARM/ARMISelLowering.h >>> (ARMISD::MOVLRPC): New enum. >>> * llvm/lib/Target/ARM/ARMInstrInfo.td >>> (ARMmovlrpc): New defined selection dag node. >>> (MOVLRPC): New defined instruction. >>> (BX): Emit only one instruction for non-jit. >>> (BMOVPCRX): Likewise. >>> (BXr9): Likewise. >>> (BMOVPCRXr9): Likewise. >>> >>> Ok to push? >>> >>> Cheers >>> Xerxes >>> >>> Index: llvm/lib/Target/ARM/ARMISelLowering.cpp >>> =================================================================== >>> --- llvm.orig/lib/Target/ARM/ARMISelLowering.cpp 2010-07-11 12:57:59.000000000 +0200 >>> +++ llvm/lib/Target/ARM/ARMISelLowering.cpp 2010-07-11 22:07:28.000000000 +0200 >>> @@ -560,6 +560,7 @@ >>> case ARMISD::BR_JT: return "ARMISD::BR_JT"; >>> case ARMISD::BR2_JT: return "ARMISD::BR2_JT"; >>> case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG"; >>> + case ARMISD::MOVLRPC: return "ARMISD::MOVLRPC"; >>> case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD"; >>> case ARMISD::CMP: return "ARMISD::CMP"; >>> case ARMISD::CMPZ: return "ARMISD::CMPZ"; >>> @@ -1288,6 +1289,14 @@ >>> // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK >>> Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(MVT::i32),InFlag); >>> InFlag = Chain.getValue(1); >>> + >>> + if(!isTailCall){ >>> + // explicit copy PC to LR and chain flag it to the call. >>> + Chain = DAG.getNode(ARMISD::MOVLRPC, dl, >>> + DAG.getVTList(MVT::Other, MVT::Flag), >>> + Chain, InFlag); >>> + InFlag = Chain.getValue(1); >>> + } >>> } >>> >>> std::vector Ops; >>> Index: llvm/lib/Target/ARM/ARMISelLowering.h >>> =================================================================== >>> --- llvm.orig/lib/Target/ARM/ARMISelLowering.h 2010-07-11 12:57:59.000000000 +0200 >>> +++ llvm/lib/Target/ARM/ARMISelLowering.h 2010-07-11 12:59:02.000000000 +0200 >>> @@ -42,6 +42,7 @@ >>> BR_JT, // Jumptable branch. >>> BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump). >>> RET_FLAG, // Return with a flag operand. >>> + MOVLRPC, // Store return address PC in LR before call - flag before CALL_NOLINK >>> >>> PIC_ADD, // Add with a PC operand and a PIC label. >>> >>> Index: llvm/lib/Target/ARM/ARMInstrInfo.td >>> =================================================================== >>> --- llvm.orig/lib/Target/ARM/ARMInstrInfo.td 2010-07-11 12:57:59.000000000 +0200 >>> +++ llvm/lib/Target/ARM/ARMInstrInfo.td 2010-07-11 12:59:02.000000000 +0200 >>> @@ -74,6 +74,9 @@ >>> [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag, >>> SDNPVariadic]>; >>> >>> +def ARMmovlrpc : SDNode<"ARMISD::MOVLRPC", SDTNone, >>> + [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; >>> + >>> def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone, >>> [SDNPHasChain, SDNPOptInFlag]>; >>> >>> @@ -674,6 +677,16 @@ >>> [(ARMcallseq_start timm:$amt)]>; >>> } >>> >>> +let Defs = [LR], hasSideEffects = 1 in >>> +def MOVLRPC : AI<(outs), (ins), BrMiscFrm, IIC_Br, >>> + "mov", "\tlr, pc", [(ARMmovlrpc)]>, >>> + Requires<[IsARM]> { >>> + let Inst{11-0} = 0b000000001111; >>> + let Inst{15-12} = 0b1110; >>> + let Inst{19-16} = 0b0000; >>> + let Inst{27-20} = 0b00011010; >>> +} >>> + >>> def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "", >>> [/* For disassembly only; pattern left blank */]>, >>> Requires<[IsARM, HasV6T2]> { >>> @@ -962,7 +975,7 @@ >>> // ARMv4T >>> // Note: Restrict $func to the tGPR regclass to prevent it being in LR. >>> def BX : ABXIx2<(outs), (ins tGPR:$func, variable_ops), >>> - IIC_Br, "mov\tlr, pc\n\tbx\t$func", >>> + IIC_Br, "bx\t$func", >>> [(ARMcall_nolink tGPR:$func)]>, >>> Requires<[IsARM, HasV4T, IsNotDarwin]> { >>> let Inst{7-4} = 0b0001; >>> @@ -972,7 +985,7 @@ >>> >>> // ARMv4 >>> def BMOVPCRX : ABXIx2<(outs), (ins tGPR:$func, variable_ops), >>> - IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func", >>> + IIC_Br, "mov\tpc, $func", >>> [(ARMcall_nolink tGPR:$func)]>, >>> Requires<[IsARM, NoV4T, IsNotDarwin]> { >>> let Inst{11-4} = 0b00000000; >>> @@ -1011,7 +1024,7 @@ >>> // ARMv4T >>> // Note: Restrict $func to the tGPR regclass to prevent it being in LR. >>> def BXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops), >>> - IIC_Br, "mov\tlr, pc\n\tbx\t$func", >>> + IIC_Br, "bx\t$func", >>> [(ARMcall_nolink tGPR:$func)]>, >>> Requires<[IsARM, HasV4T, IsDarwin]> { >>> let Inst{7-4} = 0b0001; >>> @@ -1021,7 +1034,7 @@ >>> >>> // ARMv4 >>> def BMOVPCRXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops), >>> - IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func", >>> + IIC_Br, "mov\tpc, $func", >>> [(ARMcall_nolink tGPR:$func)]>, >>> Requires<[IsARM, NoV4T, IsDarwin]> { >>> let Inst{11-4} = 0b00000000; >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>> >> >> > From stoklund at 2pi.dk Mon Jul 12 15:38:43 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 12 Jul 2010 13:38:43 -0700 Subject: [llvm-commits] (patch) PR7608 ARMv4 JIT forgets to set the lr register when making a indirect function call In-Reply-To: <4C3B79BF.3080303@zafena.se> References: <4C3A4388.1040703@zafena.se> <4C3B79BF.3080303@zafena.se> Message-ID: On Jul 12, 2010, at 1:23 PM, Xerxes Ranby wrote: > I have got the understanding that by flagging two instructions together > are the mechanism to use in order to prevent something-else from getting > scheduled in between. > Have this changed? No, this is still true. The instructions will be /scheduled/ together. There is a lot of stuff going on after scheduling, though. There is no guarantee that instructions won't be inserted by a later pass. For instance: mov lr, pc bx %reg1234 If %reg1234 is spilled, a reload will be inserted immediately before the call: mov lr, pc ldr r4, [sp..] bx r4 We don't currently have a way of gluing instructions together except using pseudo-instructions. From daniel at zuster.org Mon Jul 12 15:42:34 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 12 Jul 2010 20:42:34 -0000 Subject: [llvm-commits] [llvm] r108190 - in /llvm/trunk: include/llvm/MC/MCParser/AsmParser.h lib/MC/MCParser/AsmParser.cpp Message-ID: <20100712204234.B2A222A6C12C@llvm.org> Author: ddunbar Date: Mon Jul 12 15:42:34 2010 New Revision: 108190 URL: http://llvm.org/viewvc/llvm-project?rev=108190&view=rev Log: MC/AsmParser: Move .section parsing to Darwin specific parser. Modified: llvm/trunk/include/llvm/MC/MCParser/AsmParser.h llvm/trunk/lib/MC/MCParser/AsmParser.cpp Modified: llvm/trunk/include/llvm/MC/MCParser/AsmParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/AsmParser.h?rev=108190&r1=108189&r2=108190&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCParser/AsmParser.h (original) +++ llvm/trunk/include/llvm/MC/MCParser/AsmParser.h Mon Jul 12 15:42:34 2010 @@ -118,7 +118,6 @@ bool ParseIdentifier(StringRef &Res); // Directive Parsing. - bool ParseDirectiveDarwinSection(); // Darwin specific ".section". bool ParseDirectiveAscii(bool ZeroTerminated); // ".ascii", ".asciiz" bool ParseDirectiveValue(unsigned Size); // ".byte", ".long", ... bool ParseDirectiveFill(); // ".fill" Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=108190&r1=108189&r2=108190&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Mon Jul 12 15:42:34 2010 @@ -82,6 +82,8 @@ &DarwinAsmParser::ParseDirectiveDumpOrLoad)); Parser.AddDirectiveHandler(this, ".load", MCAsmParser::DirectiveHandler( &DarwinAsmParser::ParseDirectiveDumpOrLoad)); + Parser.AddDirectiveHandler(this, ".section", MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseDirectiveSection)); Parser.AddDirectiveHandler(this, ".secure_log_unique", MCAsmParser::DirectiveHandler( &DarwinAsmParser::ParseDirectiveSecureLogUnique)); @@ -230,6 +232,7 @@ bool ParseDirectiveDesc(StringRef, SMLoc); bool ParseDirectiveDumpOrLoad(StringRef, SMLoc); bool ParseDirectiveLsym(StringRef, SMLoc); + bool ParseDirectiveSection(); bool ParseDirectiveSecureLogReset(StringRef, SMLoc); bool ParseDirectiveSecureLogUnique(StringRef, SMLoc); bool ParseDirectiveSubsectionsViaSymbols(StringRef, SMLoc); @@ -947,10 +950,6 @@ // Otherwise, we have a normal instruction or directive. if (IDVal[0] == '.') { - // FIXME: This should be driven based on a hash lookup and callback. - if (IDVal == ".section") - return ParseDirectiveDarwinSection(); - // Assembler features if (IDVal == ".set") return ParseDirectiveSet(); @@ -1168,13 +1167,11 @@ /// ParseDirectiveSection: /// ::= .section identifier (',' identifier)* -/// FIXME: This should actually parse out the segment, section, attributes and -/// sizeof_stub fields. -bool AsmParser::ParseDirectiveDarwinSection() { +bool DarwinAsmParser::ParseDirectiveSection() { SMLoc Loc = getLexer().getLoc(); StringRef SectionName; - if (ParseIdentifier(SectionName)) + if (getParser().ParseIdentifier(SectionName)) return Error(Loc, "expected identifier after '.section' directive"); // Verify there is a following comma. @@ -1186,7 +1183,7 @@ // Add all the tokens until the end of the line, ParseSectionSpecifier will // handle this. - StringRef EOL = Lexer.LexUntilEndOfStatement(); + StringRef EOL = getLexer().LexUntilEndOfStatement(); SectionSpec.append(EOL.begin(), EOL.end()); Lex(); @@ -1197,16 +1194,16 @@ StringRef Segment, Section; unsigned TAA, StubSize; - std::string ErrorStr = + std::string ErrorStr = MCSectionMachO::ParseSectionSpecifier(SectionSpec, Segment, Section, TAA, StubSize); - + if (!ErrorStr.empty()) return Error(Loc, ErrorStr.c_str()); - + // FIXME: Arch specific. bool isText = Segment == "__TEXT"; // FIXME: Hack. - getStreamer().SwitchSection(Ctx.getMachOSection( + getStreamer().SwitchSection(getContext().getMachOSection( Segment, Section, TAA, StubSize, isText ? SectionKind::getText() : SectionKind::getDataRel())); From gohman at apple.com Mon Jul 12 15:46:04 2010 From: gohman at apple.com (Dan Gohman) Date: Mon, 12 Jul 2010 20:46:04 -0000 Subject: [llvm-commits] [llvm] r108191 - in /llvm/trunk: lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/break-sse-dep.ll Message-ID: <20100712204604.E8C612A6C12C@llvm.org> Author: djg Date: Mon Jul 12 15:46:04 2010 New Revision: 108191 URL: http://llvm.org/viewvc/llvm-project?rev=108191&view=rev Log: Apply the SSE dependence idiom for SSE unary operations to SD instructions too, in addition to SS instructions. And add a comment about it. Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/test/CodeGen/X86/break-sse-dep.ll Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=108191&r1=108190&r2=108191&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Jul 12 15:46:04 2010 @@ -1937,6 +1937,10 @@ def SSr : SSI; + // For scalar unary operations, fold a load into the operation + // only in OptForSize mode. It eliminates an instruction, but it also + // eliminates a whole-register clobber (the load), so it introduces a + // partial register update condition. def SSm : I, XS, @@ -1992,9 +1996,11 @@ def SDr : SDI; - def SDm : SDI; + [(set FR64:$dst, (OpNode (load addr:$src)))]>, XD, + Requires<[HasSSE2, OptForSize]>; def SDr_Int : SDI; Modified: llvm/trunk/test/CodeGen/X86/break-sse-dep.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/break-sse-dep.ll?rev=108191&r1=108190&r2=108191&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/break-sse-dep.ll (original) +++ llvm/trunk/test/CodeGen/X86/break-sse-dep.ll Mon Jul 12 15:46:04 2010 @@ -19,3 +19,44 @@ %1 = fptrunc double %0 to float ret float %1 } + +define float @squirtf(float* %x) nounwind { +entry: +; CHECK: squirtf: +; CHECK: movss (%rdi), %xmm0 +; CHECK: sqrtss %xmm0, %xmm0 + %z = load float* %x + %t = call float @llvm.sqrt.f32(float %z) + ret float %t +} + +define double @squirt(double* %x) nounwind { +entry: +; CHECK: squirt: +; CHECK: movsd (%rdi), %xmm0 +; CHECK: sqrtsd %xmm0, %xmm0 + %z = load double* %x + %t = call double @llvm.sqrt.f64(double %z) + ret double %t +} + +define float @squirtf_size(float* %x) nounwind optsize { +entry: +; CHECK: squirtf_size: +; CHECK: sqrtss (%rdi), %xmm0 + %z = load float* %x + %t = call float @llvm.sqrt.f32(float %z) + ret float %t +} + +define double @squirt_size(double* %x) nounwind optsize { +entry: +; CHECK: squirt_size: +; CHECK: sqrtsd (%rdi), %xmm0 + %z = load double* %x + %t = call double @llvm.sqrt.f64(double %z) + ret double %t +} + +declare float @llvm.sqrt.f32(float) +declare double @llvm.sqrt.f64(double) From daniel at zuster.org Mon Jul 12 15:51:51 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 12 Jul 2010 20:51:51 -0000 Subject: [llvm-commits] [llvm] r108193 - in /llvm/trunk/lib/MC/MCParser: AsmParser.cpp CMakeLists.txt DarwinAsmParser.cpp Message-ID: <20100712205151.C92B22A6C12C@llvm.org> Author: ddunbar Date: Mon Jul 12 15:51:51 2010 New Revision: 108193 URL: http://llvm.org/viewvc/llvm-project?rev=108193&view=rev Log: MC/AsmParser: Move Darwin specific parse to DarwinAsmParser.cpp. Added: llvm/trunk/lib/MC/MCParser/DarwinAsmParser.cpp Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp llvm/trunk/lib/MC/MCParser/CMakeLists.txt Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=108193&r1=108192&r2=108193&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Mon Jul 12 15:51:51 2010 @@ -19,7 +19,6 @@ #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCSectionELF.h" -#include "llvm/MC/MCSectionMachO.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSymbol.h" #include "llvm/MC/MCParser/MCParsedAsmOperand.h" @@ -30,7 +29,6 @@ #include "llvm/Target/TargetAsmParser.h" using namespace llvm; - namespace { /// \brief Generic implementations of directive handling, etc. which is shared @@ -57,360 +55,6 @@ bool ParseDirectiveLoc(StringRef, SMLoc DirectiveLoc); // ".loc" }; -/// \brief Implementation of directive handling which is shared across all -/// Darwin targets. -class DarwinAsmParser : public MCAsmParserExtension { - bool ParseSectionSwitch(const char *Segment, const char *Section, - unsigned TAA = 0, unsigned ImplicitAlign = 0, - unsigned StubSize = 0); - -public: - DarwinAsmParser() {} - - virtual void Initialize(MCAsmParser &Parser) { - // Call the base implementation. - this->MCAsmParserExtension::Initialize(Parser); - - Parser.AddDirectiveHandler(this, ".desc", MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseDirectiveDesc)); - Parser.AddDirectiveHandler(this, ".lsym", MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseDirectiveLsym)); - Parser.AddDirectiveHandler(this, ".subsections_via_symbols", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseDirectiveSubsectionsViaSymbols)); - Parser.AddDirectiveHandler(this, ".dump", MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseDirectiveDumpOrLoad)); - Parser.AddDirectiveHandler(this, ".load", MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseDirectiveDumpOrLoad)); - Parser.AddDirectiveHandler(this, ".section", MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseDirectiveSection)); - Parser.AddDirectiveHandler(this, ".secure_log_unique", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseDirectiveSecureLogUnique)); - Parser.AddDirectiveHandler(this, ".secure_log_reset", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseDirectiveSecureLogReset)); - Parser.AddDirectiveHandler(this, ".tbss", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseDirectiveTBSS)); - Parser.AddDirectiveHandler(this, ".zerofill", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseDirectiveZerofill)); - - // Special section directives. - Parser.AddDirectiveHandler(this, ".const", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveConst)); - Parser.AddDirectiveHandler(this, ".const_data", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveConstData)); - Parser.AddDirectiveHandler(this, ".constructor", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveConstructor)); - Parser.AddDirectiveHandler(this, ".cstring", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveCString)); - Parser.AddDirectiveHandler(this, ".data", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveData)); - Parser.AddDirectiveHandler(this, ".destructor", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveDestructor)); - Parser.AddDirectiveHandler(this, ".dyld", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveDyld)); - Parser.AddDirectiveHandler(this, ".fvmlib_init0", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveFVMLibInit0)); - Parser.AddDirectiveHandler(this, ".fvmlib_init1", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveFVMLibInit1)); - Parser.AddDirectiveHandler(this, ".lazy_symbol_pointer", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveLazySymbolPointers)); - Parser.AddDirectiveHandler(this, ".literal16", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveLiteral16)); - Parser.AddDirectiveHandler(this, ".literal4", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveLiteral4)); - Parser.AddDirectiveHandler(this, ".literal8", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveLiteral8)); - Parser.AddDirectiveHandler(this, ".mod_init_func", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveModInitFunc)); - Parser.AddDirectiveHandler(this, ".mod_term_func", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveModTermFunc)); - Parser.AddDirectiveHandler(this, ".non_lazy_symbol_pointer", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveNonLazySymbolPointers)); - Parser.AddDirectiveHandler(this, ".objc_cat_cls_meth", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveObjCCatClsMeth)); - Parser.AddDirectiveHandler(this, ".objc_cat_inst_meth", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveObjCCatInstMeth)); - Parser.AddDirectiveHandler(this, ".objc_category", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveObjCCategory)); - Parser.AddDirectiveHandler(this, ".objc_class", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveObjCClass)); - Parser.AddDirectiveHandler(this, ".objc_class_names", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveObjCClassNames)); - Parser.AddDirectiveHandler(this, ".objc_class_vars", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveObjCClassVars)); - Parser.AddDirectiveHandler(this, ".objc_cls_meth", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveObjCClsMeth)); - Parser.AddDirectiveHandler(this, ".objc_cls_refs", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveObjCClsRefs)); - Parser.AddDirectiveHandler(this, ".objc_inst_meth", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveObjCInstMeth)); - Parser.AddDirectiveHandler(this, ".objc_instance_vars", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveObjCInstanceVars)); - Parser.AddDirectiveHandler(this, ".objc_message_refs", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveObjCMessageRefs)); - Parser.AddDirectiveHandler(this, ".objc_meta_class", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveObjCMetaClass)); - Parser.AddDirectiveHandler(this, ".objc_meth_var_names", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveObjCMethVarNames)); - Parser.AddDirectiveHandler(this, ".objc_meth_var_types", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveObjCMethVarTypes)); - Parser.AddDirectiveHandler(this, ".objc_module_info", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveObjCModuleInfo)); - Parser.AddDirectiveHandler(this, ".objc_protocol", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveObjCProtocol)); - Parser.AddDirectiveHandler(this, ".objc_selector_strs", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveObjCSelectorStrs)); - Parser.AddDirectiveHandler(this, ".objc_string_object", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveObjCStringObject)); - Parser.AddDirectiveHandler(this, ".objc_symbols", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveObjCSymbols)); - Parser.AddDirectiveHandler(this, ".picsymbol_stub", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectivePICSymbolStub)); - Parser.AddDirectiveHandler(this, ".static_const", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveStaticConst)); - Parser.AddDirectiveHandler(this, ".static_data", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveStaticData)); - Parser.AddDirectiveHandler(this, ".symbol_stub", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveSymbolStub)); - Parser.AddDirectiveHandler(this, ".tdata", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveTData)); - Parser.AddDirectiveHandler(this, ".text", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveText)); - Parser.AddDirectiveHandler(this, ".thread_init_func", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveThreadInitFunc)); - Parser.AddDirectiveHandler(this, ".tlv", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveTLV)); - } - - bool ParseDirectiveDesc(StringRef, SMLoc); - bool ParseDirectiveDumpOrLoad(StringRef, SMLoc); - bool ParseDirectiveLsym(StringRef, SMLoc); - bool ParseDirectiveSection(); - bool ParseDirectiveSecureLogReset(StringRef, SMLoc); - bool ParseDirectiveSecureLogUnique(StringRef, SMLoc); - bool ParseDirectiveSubsectionsViaSymbols(StringRef, SMLoc); - bool ParseDirectiveTBSS(StringRef, SMLoc); - bool ParseDirectiveZerofill(StringRef, SMLoc); - - // Named Section Directive - bool ParseSectionDirectiveConst(StringRef, SMLoc) { - return ParseSectionSwitch("__TEXT", "__const"); - } - bool ParseSectionDirectiveStaticConst(StringRef, SMLoc) { - return ParseSectionSwitch("__TEXT", "__static_const"); - } - bool ParseSectionDirectiveCString(StringRef, SMLoc) { - return ParseSectionSwitch("__TEXT","__cstring", - MCSectionMachO::S_CSTRING_LITERALS); - } - bool ParseSectionDirectiveLiteral4(StringRef, SMLoc) { - return ParseSectionSwitch("__TEXT", "__literal4", - MCSectionMachO::S_4BYTE_LITERALS, 4); - } - bool ParseSectionDirectiveLiteral8(StringRef, SMLoc) { - return ParseSectionSwitch("__TEXT", "__literal8", - MCSectionMachO::S_8BYTE_LITERALS, 8); - } - bool ParseSectionDirectiveLiteral16(StringRef, SMLoc) { - return ParseSectionSwitch("__TEXT","__literal16", - MCSectionMachO::S_16BYTE_LITERALS, 16); - } - bool ParseSectionDirectiveConstructor(StringRef, SMLoc) { - return ParseSectionSwitch("__TEXT","__constructor"); - } - bool ParseSectionDirectiveDestructor(StringRef, SMLoc) { - return ParseSectionSwitch("__TEXT","__destructor"); - } - bool ParseSectionDirectiveFVMLibInit0(StringRef, SMLoc) { - return ParseSectionSwitch("__TEXT","__fvmlib_init0"); - } - bool ParseSectionDirectiveFVMLibInit1(StringRef, SMLoc) { - return ParseSectionSwitch("__TEXT","__fvmlib_init1"); - } - bool ParseSectionDirectiveSymbolStub(StringRef, SMLoc) { - return ParseSectionSwitch("__TEXT","__symbol_stub", - MCSectionMachO::S_SYMBOL_STUBS | - MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS, - // FIXME: Different on PPC and ARM. - 0, 16); - } - bool ParseSectionDirectivePICSymbolStub(StringRef, SMLoc) { - return ParseSectionSwitch("__TEXT","__picsymbol_stub", - MCSectionMachO::S_SYMBOL_STUBS | - MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS, 0, 26); - } - bool ParseSectionDirectiveData(StringRef, SMLoc) { - return ParseSectionSwitch("__DATA", "__data"); - } - bool ParseSectionDirectiveStaticData(StringRef, SMLoc) { - return ParseSectionSwitch("__DATA", "__static_data"); - } - bool ParseSectionDirectiveNonLazySymbolPointers(StringRef, SMLoc) { - return ParseSectionSwitch("__DATA", "__nl_symbol_ptr", - MCSectionMachO::S_NON_LAZY_SYMBOL_POINTERS, 4); - } - bool ParseSectionDirectiveLazySymbolPointers(StringRef, SMLoc) { - return ParseSectionSwitch("__DATA", "__la_symbol_ptr", - MCSectionMachO::S_LAZY_SYMBOL_POINTERS, 4); - } - bool ParseSectionDirectiveDyld(StringRef, SMLoc) { - return ParseSectionSwitch("__DATA", "__dyld"); - } - bool ParseSectionDirectiveModInitFunc(StringRef, SMLoc) { - return ParseSectionSwitch("__DATA", "__mod_init_func", - MCSectionMachO::S_MOD_INIT_FUNC_POINTERS, 4); - } - bool ParseSectionDirectiveModTermFunc(StringRef, SMLoc) { - return ParseSectionSwitch("__DATA", "__mod_term_func", - MCSectionMachO::S_MOD_TERM_FUNC_POINTERS, 4); - } - bool ParseSectionDirectiveConstData(StringRef, SMLoc) { - return ParseSectionSwitch("__DATA", "__const"); - } - bool ParseSectionDirectiveObjCClass(StringRef, SMLoc) { - return ParseSectionSwitch("__OBJC", "__class", - MCSectionMachO::S_ATTR_NO_DEAD_STRIP); - } - bool ParseSectionDirectiveObjCMetaClass(StringRef, SMLoc) { - return ParseSectionSwitch("__OBJC", "__meta_class", - MCSectionMachO::S_ATTR_NO_DEAD_STRIP); - } - bool ParseSectionDirectiveObjCCatClsMeth(StringRef, SMLoc) { - return ParseSectionSwitch("__OBJC", "__cat_cls_meth", - MCSectionMachO::S_ATTR_NO_DEAD_STRIP); - } - bool ParseSectionDirectiveObjCCatInstMeth(StringRef, SMLoc) { - return ParseSectionSwitch("__OBJC", "__cat_inst_meth", - MCSectionMachO::S_ATTR_NO_DEAD_STRIP); - } - bool ParseSectionDirectiveObjCProtocol(StringRef, SMLoc) { - return ParseSectionSwitch("__OBJC", "__protocol", - MCSectionMachO::S_ATTR_NO_DEAD_STRIP); - } - bool ParseSectionDirectiveObjCStringObject(StringRef, SMLoc) { - return ParseSectionSwitch("__OBJC", "__string_object", - MCSectionMachO::S_ATTR_NO_DEAD_STRIP); - } - bool ParseSectionDirectiveObjCClsMeth(StringRef, SMLoc) { - return ParseSectionSwitch("__OBJC", "__cls_meth", - MCSectionMachO::S_ATTR_NO_DEAD_STRIP); - } - bool ParseSectionDirectiveObjCInstMeth(StringRef, SMLoc) { - return ParseSectionSwitch("__OBJC", "__inst_meth", - MCSectionMachO::S_ATTR_NO_DEAD_STRIP); - } - bool ParseSectionDirectiveObjCClsRefs(StringRef, SMLoc) { - return ParseSectionSwitch("__OBJC", "__cls_refs", - MCSectionMachO::S_ATTR_NO_DEAD_STRIP | - MCSectionMachO::S_LITERAL_POINTERS, 4); - } - bool ParseSectionDirectiveObjCMessageRefs(StringRef, SMLoc) { - return ParseSectionSwitch("__OBJC", "__message_refs", - MCSectionMachO::S_ATTR_NO_DEAD_STRIP | - MCSectionMachO::S_LITERAL_POINTERS, 4); - } - bool ParseSectionDirectiveObjCSymbols(StringRef, SMLoc) { - return ParseSectionSwitch("__OBJC", "__symbols", - MCSectionMachO::S_ATTR_NO_DEAD_STRIP); - } - bool ParseSectionDirectiveObjCCategory(StringRef, SMLoc) { - return ParseSectionSwitch("__OBJC", "__category", - MCSectionMachO::S_ATTR_NO_DEAD_STRIP); - } - bool ParseSectionDirectiveObjCClassVars(StringRef, SMLoc) { - return ParseSectionSwitch("__OBJC", "__class_vars", - MCSectionMachO::S_ATTR_NO_DEAD_STRIP); - } - bool ParseSectionDirectiveObjCInstanceVars(StringRef, SMLoc) { - return ParseSectionSwitch("__OBJC", "__instance_vars", - MCSectionMachO::S_ATTR_NO_DEAD_STRIP); - } - bool ParseSectionDirectiveObjCModuleInfo(StringRef, SMLoc) { - return ParseSectionSwitch("__OBJC", "__module_info", - MCSectionMachO::S_ATTR_NO_DEAD_STRIP); - } - bool ParseSectionDirectiveObjCClassNames(StringRef, SMLoc) { - return ParseSectionSwitch("__TEXT", "__cstring", - MCSectionMachO::S_CSTRING_LITERALS); - } - bool ParseSectionDirectiveObjCMethVarTypes(StringRef, SMLoc) { - return ParseSectionSwitch("__TEXT", "__cstring", - MCSectionMachO::S_CSTRING_LITERALS); - } - bool ParseSectionDirectiveObjCMethVarNames(StringRef, SMLoc) { - return ParseSectionSwitch("__TEXT", "__cstring", - MCSectionMachO::S_CSTRING_LITERALS); - } - bool ParseSectionDirectiveObjCSelectorStrs(StringRef, SMLoc) { - return ParseSectionSwitch("__OBJC", "__selector_strs", - MCSectionMachO::S_CSTRING_LITERALS); - } - bool ParseSectionDirectiveTData(StringRef, SMLoc) { - return ParseSectionSwitch("__DATA", "__thread_data", - MCSectionMachO::S_THREAD_LOCAL_REGULAR); - } - bool ParseSectionDirectiveText(StringRef, SMLoc) { - return ParseSectionSwitch("__TEXT", "__text", - MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS); - } - bool ParseSectionDirectiveTLV(StringRef, SMLoc) { - return ParseSectionSwitch("__DATA", "__thread_vars", - MCSectionMachO::S_THREAD_LOCAL_VARIABLES); - } - bool ParseSectionDirectiveThreadInitFunc(StringRef, SMLoc) { - return ParseSectionSwitch("__DATA", "__thread_init", - MCSectionMachO::S_THREAD_LOCAL_INIT_FUNCTION_POINTERS); - } - -}; - class ELFAsmParser : public MCAsmParserExtension { bool ParseSectionSwitch(StringRef Section, unsigned Type, unsigned Flags, SectionKind Kind); @@ -442,6 +86,12 @@ } +namespace llvm { + +extern MCAsmParserExtension *createDarwinAsmParser(); + +} + enum { DEFAULT_ADDRSPACE = 0 }; AsmParser::AsmParser(const Target &T, SourceMgr &_SM, MCContext &_Ctx, @@ -459,7 +109,7 @@ // FIXME: This is a hack, we need to (majorly) cleanup how these objects are // created. if (_MAI.hasSubsectionsViaSymbols()) { - PlatformParser = new DarwinAsmParser; + PlatformParser = createDarwinAsmParser(); PlatformParser->Initialize(*this); } else { PlatformParser = new ELFAsmParser; @@ -1165,80 +815,6 @@ return ParseAssignment(Name); } -/// ParseDirectiveSection: -/// ::= .section identifier (',' identifier)* -bool DarwinAsmParser::ParseDirectiveSection() { - SMLoc Loc = getLexer().getLoc(); - - StringRef SectionName; - if (getParser().ParseIdentifier(SectionName)) - return Error(Loc, "expected identifier after '.section' directive"); - - // Verify there is a following comma. - if (!getLexer().is(AsmToken::Comma)) - return TokError("unexpected token in '.section' directive"); - - std::string SectionSpec = SectionName; - SectionSpec += ","; - - // Add all the tokens until the end of the line, ParseSectionSpecifier will - // handle this. - StringRef EOL = getLexer().LexUntilEndOfStatement(); - SectionSpec.append(EOL.begin(), EOL.end()); - - Lex(); - if (getLexer().isNot(AsmToken::EndOfStatement)) - return TokError("unexpected token in '.section' directive"); - Lex(); - - - StringRef Segment, Section; - unsigned TAA, StubSize; - std::string ErrorStr = - MCSectionMachO::ParseSectionSpecifier(SectionSpec, Segment, Section, - TAA, StubSize); - - if (!ErrorStr.empty()) - return Error(Loc, ErrorStr.c_str()); - - // FIXME: Arch specific. - bool isText = Segment == "__TEXT"; // FIXME: Hack. - getStreamer().SwitchSection(getContext().getMachOSection( - Segment, Section, TAA, StubSize, - isText ? SectionKind::getText() - : SectionKind::getDataRel())); - return false; -} - -bool DarwinAsmParser::ParseSectionSwitch(const char *Segment, - const char *Section, - unsigned TAA, unsigned Align, - unsigned StubSize) { - if (getLexer().isNot(AsmToken::EndOfStatement)) - return TokError("unexpected token in section switching directive"); - Lex(); - - // FIXME: Arch specific. - bool isText = StringRef(Segment) == "__TEXT"; // FIXME: Hack. - getStreamer().SwitchSection(getContext().getMachOSection( - Segment, Section, TAA, StubSize, - isText ? SectionKind::getText() - : SectionKind::getDataRel())); - - // Set the implicit alignment, if any. - // - // FIXME: This isn't really what 'as' does; I think it just uses the implicit - // alignment on the section (e.g., if one manually inserts bytes into the - // section, then just issueing the section switch directive will not realign - // the section. However, this is arguably more reasonable behavior, and there - // is no good reason for someone to intentionally emit incorrectly sized - // values into the implicitly aligned sections. - if (Align) - getStreamer().EmitValueToAlignment(Align, 0, 1, 0); - - return false; -} - bool ELFAsmParser::ParseSectionSwitch(StringRef Section, unsigned Type, unsigned Flags, SectionKind Kind) { if (getLexer().isNot(AsmToken::EndOfStatement)) @@ -1631,35 +1207,6 @@ return false; } -/// ParseDirectiveDesc -/// ::= .desc identifier , expression -bool DarwinAsmParser::ParseDirectiveDesc(StringRef, SMLoc) { - StringRef Name; - if (getParser().ParseIdentifier(Name)) - return TokError("expected identifier in directive"); - - // Handle the identifier as the key symbol. - MCSymbol *Sym = getContext().GetOrCreateSymbol(Name); - - if (getLexer().isNot(AsmToken::Comma)) - return TokError("unexpected token in '.desc' directive"); - Lex(); - - int64_t DescValue; - if (getParser().ParseAbsoluteExpression(DescValue)) - return true; - - if (getLexer().isNot(AsmToken::EndOfStatement)) - return TokError("unexpected token in '.desc' directive"); - - Lex(); - - // Set the n_desc field of this Symbol to this DescValue - getStreamer().EmitSymbolDesc(Sym, DescValue); - - return false; -} - /// ParseDirectiveComm /// ::= ( .comm | .lcomm ) identifier , size_expression [ , align_expression ] bool AsmParser::ParseDirectiveComm(bool IsLocal) { @@ -1731,161 +1278,6 @@ return false; } -/// ParseDirectiveZerofill -/// ::= .zerofill segname , sectname [, identifier , size_expression [ -/// , align_expression ]] -bool DarwinAsmParser::ParseDirectiveZerofill(StringRef, SMLoc) { - StringRef Segment; - if (getParser().ParseIdentifier(Segment)) - return TokError("expected segment name after '.zerofill' directive"); - - if (getLexer().isNot(AsmToken::Comma)) - return TokError("unexpected token in directive"); - Lex(); - - StringRef Section; - if (getParser().ParseIdentifier(Section)) - return TokError("expected section name after comma in '.zerofill' " - "directive"); - - // If this is the end of the line all that was wanted was to create the - // the section but with no symbol. - if (getLexer().is(AsmToken::EndOfStatement)) { - // Create the zerofill section but no symbol - getStreamer().EmitZerofill(getContext().getMachOSection( - Segment, Section, MCSectionMachO::S_ZEROFILL, - 0, SectionKind::getBSS())); - return false; - } - - if (getLexer().isNot(AsmToken::Comma)) - return TokError("unexpected token in directive"); - Lex(); - - SMLoc IDLoc = getLexer().getLoc(); - StringRef IDStr; - if (getParser().ParseIdentifier(IDStr)) - return TokError("expected identifier in directive"); - - // handle the identifier as the key symbol. - MCSymbol *Sym = getContext().GetOrCreateSymbol(IDStr); - - if (getLexer().isNot(AsmToken::Comma)) - return TokError("unexpected token in directive"); - Lex(); - - int64_t Size; - SMLoc SizeLoc = getLexer().getLoc(); - if (getParser().ParseAbsoluteExpression(Size)) - return true; - - int64_t Pow2Alignment = 0; - SMLoc Pow2AlignmentLoc; - if (getLexer().is(AsmToken::Comma)) { - Lex(); - Pow2AlignmentLoc = getLexer().getLoc(); - if (getParser().ParseAbsoluteExpression(Pow2Alignment)) - return true; - } - - if (getLexer().isNot(AsmToken::EndOfStatement)) - return TokError("unexpected token in '.zerofill' directive"); - - Lex(); - - if (Size < 0) - return Error(SizeLoc, "invalid '.zerofill' directive size, can't be less " - "than zero"); - - // NOTE: The alignment in the directive is a power of 2 value, the assembler - // may internally end up wanting an alignment in bytes. - // FIXME: Diagnose overflow. - if (Pow2Alignment < 0) - return Error(Pow2AlignmentLoc, "invalid '.zerofill' directive alignment, " - "can't be less than zero"); - - if (!Sym->isUndefined()) - return Error(IDLoc, "invalid symbol redefinition"); - - // Create the zerofill Symbol with Size and Pow2Alignment - // - // FIXME: Arch specific. - getStreamer().EmitZerofill(getContext().getMachOSection( - Segment, Section, MCSectionMachO::S_ZEROFILL, - 0, SectionKind::getBSS()), - Sym, Size, 1 << Pow2Alignment); - - return false; -} - -/// ParseDirectiveTBSS -/// ::= .tbss identifier, size, align -bool DarwinAsmParser::ParseDirectiveTBSS(StringRef, SMLoc) { - SMLoc IDLoc = getLexer().getLoc(); - StringRef Name; - if (getParser().ParseIdentifier(Name)) - return TokError("expected identifier in directive"); - - // Handle the identifier as the key symbol. - MCSymbol *Sym = getContext().GetOrCreateSymbol(Name); - - if (getLexer().isNot(AsmToken::Comma)) - return TokError("unexpected token in directive"); - Lex(); - - int64_t Size; - SMLoc SizeLoc = getLexer().getLoc(); - if (getParser().ParseAbsoluteExpression(Size)) - return true; - - int64_t Pow2Alignment = 0; - SMLoc Pow2AlignmentLoc; - if (getLexer().is(AsmToken::Comma)) { - Lex(); - Pow2AlignmentLoc = getLexer().getLoc(); - if (getParser().ParseAbsoluteExpression(Pow2Alignment)) - return true; - } - - if (getLexer().isNot(AsmToken::EndOfStatement)) - return TokError("unexpected token in '.tbss' directive"); - - Lex(); - - if (Size < 0) - return Error(SizeLoc, "invalid '.tbss' directive size, can't be less than" - "zero"); - - // FIXME: Diagnose overflow. - if (Pow2Alignment < 0) - return Error(Pow2AlignmentLoc, "invalid '.tbss' alignment, can't be less" - "than zero"); - - if (!Sym->isUndefined()) - return Error(IDLoc, "invalid symbol redefinition"); - - getStreamer().EmitTBSSSymbol(getContext().getMachOSection( - "__DATA", "__thread_bss", - MCSectionMachO::S_THREAD_LOCAL_ZEROFILL, - 0, SectionKind::getThreadBSS()), - Sym, Size, 1 << Pow2Alignment); - - return false; -} - -/// ParseDirectiveSubsectionsViaSymbols -/// ::= .subsections_via_symbols -bool DarwinAsmParser::ParseDirectiveSubsectionsViaSymbols(StringRef, SMLoc) { - if (getLexer().isNot(AsmToken::EndOfStatement)) - return TokError("unexpected token in '.subsections_via_symbols' directive"); - - Lex(); - - getStreamer().EmitAssemblerFlag(MCAF_SubsectionsViaSymbols); - - return false; -} - /// ParseDirectiveAbort /// ::= .abort [ "abort_string" ] bool AsmParser::ParseDirectiveAbort() { @@ -1916,36 +1308,6 @@ return false; } -/// ParseDirectiveLsym -/// ::= .lsym identifier , expression -bool DarwinAsmParser::ParseDirectiveLsym(StringRef, SMLoc) { - StringRef Name; - if (getParser().ParseIdentifier(Name)) - return TokError("expected identifier in directive"); - - // Handle the identifier as the key symbol. - MCSymbol *Sym = getContext().GetOrCreateSymbol(Name); - - if (getLexer().isNot(AsmToken::Comma)) - return TokError("unexpected token in '.lsym' directive"); - Lex(); - - const MCExpr *Value; - if (getParser().ParseExpression(Value)) - return true; - - if (getLexer().isNot(AsmToken::EndOfStatement)) - return TokError("unexpected token in '.lsym' directive"); - - Lex(); - - // We don't currently support this directive. - // - // FIXME: Diagnostic location! - (void) Sym; - return TokError("directive '.lsym' is unsupported"); -} - /// ParseDirectiveInclude /// ::= .include "filename" bool AsmParser::ParseDirectiveInclude() { @@ -1974,89 +1336,6 @@ return false; } -/// ParseDirectiveDumpOrLoad -/// ::= ( .dump | .load ) "filename" -bool DarwinAsmParser::ParseDirectiveDumpOrLoad(StringRef Directive, - SMLoc IDLoc) { - bool IsDump = Directive == ".dump"; - if (getLexer().isNot(AsmToken::String)) - return TokError("expected string in '.dump' or '.load' directive"); - - Lex(); - - if (getLexer().isNot(AsmToken::EndOfStatement)) - return TokError("unexpected token in '.dump' or '.load' directive"); - - Lex(); - - // FIXME: If/when .dump and .load are implemented they will be done in the - // the assembly parser and not have any need for an MCStreamer API. - if (IsDump) - Warning(IDLoc, "ignoring directive .dump for now"); - else - Warning(IDLoc, "ignoring directive .load for now"); - - return false; -} - -/// ParseDirectiveSecureLogUnique -/// ::= .secure_log_unique "log message" -bool DarwinAsmParser::ParseDirectiveSecureLogUnique(StringRef, SMLoc IDLoc) { - std::string LogMessage; - - if (getLexer().isNot(AsmToken::String)) - LogMessage = ""; - else{ - LogMessage = getTok().getString(); - Lex(); - } - - if (getLexer().isNot(AsmToken::EndOfStatement)) - return TokError("unexpected token in '.secure_log_unique' directive"); - - if (getContext().getSecureLogUsed() != false) - return Error(IDLoc, ".secure_log_unique specified multiple times"); - - char *SecureLogFile = getContext().getSecureLogFile(); - if (SecureLogFile == NULL) - return Error(IDLoc, ".secure_log_unique used but AS_SECURE_LOG_FILE " - "environment variable unset."); - - raw_ostream *OS = getContext().getSecureLog(); - if (OS == NULL) { - std::string Err; - OS = new raw_fd_ostream(SecureLogFile, Err, raw_fd_ostream::F_Append); - if (!Err.empty()) { - delete OS; - return Error(IDLoc, Twine("can't open secure log file: ") + - SecureLogFile + " (" + Err + ")"); - } - getContext().setSecureLog(OS); - } - - int CurBuf = getSourceManager().FindBufferContainingLoc(IDLoc); - *OS << getSourceManager().getBufferInfo(CurBuf).Buffer->getBufferIdentifier() - << ":" << getSourceManager().FindLineNumber(IDLoc, CurBuf) << ":" - << LogMessage + "\n"; - - getContext().setSecureLogUsed(true); - - return false; -} - -/// ParseDirectiveSecureLogReset -/// ::= .secure_log_reset -bool DarwinAsmParser::ParseDirectiveSecureLogReset(StringRef, SMLoc IDLoc) { - if (getLexer().isNot(AsmToken::EndOfStatement)) - return TokError("unexpected token in '.secure_log_reset' directive"); - - Lex(); - - getContext().setSecureLogUsed(false); - - return false; -} - /// ParseDirectiveIf /// ::= .if expression bool AsmParser::ParseDirectiveIf(SMLoc DirectiveLoc) { Modified: llvm/trunk/lib/MC/MCParser/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/CMakeLists.txt?rev=108193&r1=108192&r2=108193&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/CMakeLists.txt (original) +++ llvm/trunk/lib/MC/MCParser/CMakeLists.txt Mon Jul 12 15:51:51 2010 @@ -1,6 +1,7 @@ add_llvm_library(LLVMMCParser AsmLexer.cpp AsmParser.cpp + DarwinAsmParser.cpp MCAsmLexer.cpp MCAsmParser.cpp MCAsmParserExtension.cpp Added: llvm/trunk/lib/MC/MCParser/DarwinAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/DarwinAsmParser.cpp?rev=108193&view=auto ============================================================================== --- llvm/trunk/lib/MC/MCParser/DarwinAsmParser.cpp (added) +++ llvm/trunk/lib/MC/MCParser/DarwinAsmParser.cpp Mon Jul 12 15:51:51 2010 @@ -0,0 +1,758 @@ +//===- DarwinAsmParser.cpp - Darwin (Mach-O) Assembly Parser --------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "llvm/MC/MCParser/MCAsmParserExtension.h" +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCSectionMachO.h" +#include "llvm/MC/MCStreamer.h" +#include "llvm/MC/MCSymbol.h" +#include "llvm/MC/MCParser/MCAsmLexer.h" +#include "llvm/MC/MCParser/MCAsmParser.h" +#include "llvm/ADT/StringRef.h" +#include "llvm/ADT/Twine.h" +#include "llvm/Support/MemoryBuffer.h" +#include "llvm/Support/SourceMgr.h" +using namespace llvm; + +namespace { + +/// \brief Implementation of directive handling which is shared across all +/// Darwin targets. +class DarwinAsmParser : public MCAsmParserExtension { + bool ParseSectionSwitch(const char *Segment, const char *Section, + unsigned TAA = 0, unsigned ImplicitAlign = 0, + unsigned StubSize = 0); + +public: + DarwinAsmParser() {} + + virtual void Initialize(MCAsmParser &Parser) { + // Call the base implementation. + this->MCAsmParserExtension::Initialize(Parser); + + Parser.AddDirectiveHandler(this, ".desc", MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseDirectiveDesc)); + Parser.AddDirectiveHandler(this, ".lsym", MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseDirectiveLsym)); + Parser.AddDirectiveHandler(this, ".subsections_via_symbols", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseDirectiveSubsectionsViaSymbols)); + Parser.AddDirectiveHandler(this, ".dump", MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseDirectiveDumpOrLoad)); + Parser.AddDirectiveHandler(this, ".load", MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseDirectiveDumpOrLoad)); + Parser.AddDirectiveHandler(this, ".section", MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseDirectiveSection)); + Parser.AddDirectiveHandler(this, ".secure_log_unique", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseDirectiveSecureLogUnique)); + Parser.AddDirectiveHandler(this, ".secure_log_reset", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseDirectiveSecureLogReset)); + Parser.AddDirectiveHandler(this, ".tbss", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseDirectiveTBSS)); + Parser.AddDirectiveHandler(this, ".zerofill", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseDirectiveZerofill)); + + // Special section directives. + Parser.AddDirectiveHandler(this, ".const", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveConst)); + Parser.AddDirectiveHandler(this, ".const_data", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveConstData)); + Parser.AddDirectiveHandler(this, ".constructor", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveConstructor)); + Parser.AddDirectiveHandler(this, ".cstring", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveCString)); + Parser.AddDirectiveHandler(this, ".data", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveData)); + Parser.AddDirectiveHandler(this, ".destructor", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveDestructor)); + Parser.AddDirectiveHandler(this, ".dyld", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveDyld)); + Parser.AddDirectiveHandler(this, ".fvmlib_init0", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveFVMLibInit0)); + Parser.AddDirectiveHandler(this, ".fvmlib_init1", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveFVMLibInit1)); + Parser.AddDirectiveHandler(this, ".lazy_symbol_pointer", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveLazySymbolPointers)); + Parser.AddDirectiveHandler(this, ".literal16", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveLiteral16)); + Parser.AddDirectiveHandler(this, ".literal4", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveLiteral4)); + Parser.AddDirectiveHandler(this, ".literal8", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveLiteral8)); + Parser.AddDirectiveHandler(this, ".mod_init_func", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveModInitFunc)); + Parser.AddDirectiveHandler(this, ".mod_term_func", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveModTermFunc)); + Parser.AddDirectiveHandler(this, ".non_lazy_symbol_pointer", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveNonLazySymbolPointers)); + Parser.AddDirectiveHandler(this, ".objc_cat_cls_meth", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveObjCCatClsMeth)); + Parser.AddDirectiveHandler(this, ".objc_cat_inst_meth", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveObjCCatInstMeth)); + Parser.AddDirectiveHandler(this, ".objc_category", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveObjCCategory)); + Parser.AddDirectiveHandler(this, ".objc_class", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveObjCClass)); + Parser.AddDirectiveHandler(this, ".objc_class_names", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveObjCClassNames)); + Parser.AddDirectiveHandler(this, ".objc_class_vars", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveObjCClassVars)); + Parser.AddDirectiveHandler(this, ".objc_cls_meth", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveObjCClsMeth)); + Parser.AddDirectiveHandler(this, ".objc_cls_refs", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveObjCClsRefs)); + Parser.AddDirectiveHandler(this, ".objc_inst_meth", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveObjCInstMeth)); + Parser.AddDirectiveHandler(this, ".objc_instance_vars", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveObjCInstanceVars)); + Parser.AddDirectiveHandler(this, ".objc_message_refs", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveObjCMessageRefs)); + Parser.AddDirectiveHandler(this, ".objc_meta_class", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveObjCMetaClass)); + Parser.AddDirectiveHandler(this, ".objc_meth_var_names", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveObjCMethVarNames)); + Parser.AddDirectiveHandler(this, ".objc_meth_var_types", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveObjCMethVarTypes)); + Parser.AddDirectiveHandler(this, ".objc_module_info", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveObjCModuleInfo)); + Parser.AddDirectiveHandler(this, ".objc_protocol", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveObjCProtocol)); + Parser.AddDirectiveHandler(this, ".objc_selector_strs", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveObjCSelectorStrs)); + Parser.AddDirectiveHandler(this, ".objc_string_object", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveObjCStringObject)); + Parser.AddDirectiveHandler(this, ".objc_symbols", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveObjCSymbols)); + Parser.AddDirectiveHandler(this, ".picsymbol_stub", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectivePICSymbolStub)); + Parser.AddDirectiveHandler(this, ".static_const", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveStaticConst)); + Parser.AddDirectiveHandler(this, ".static_data", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveStaticData)); + Parser.AddDirectiveHandler(this, ".symbol_stub", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveSymbolStub)); + Parser.AddDirectiveHandler(this, ".tdata", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveTData)); + Parser.AddDirectiveHandler(this, ".text", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveText)); + Parser.AddDirectiveHandler(this, ".thread_init_func", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveThreadInitFunc)); + Parser.AddDirectiveHandler(this, ".tlv", + MCAsmParser::DirectiveHandler( + &DarwinAsmParser::ParseSectionDirectiveTLV)); + } + + bool ParseDirectiveDesc(StringRef, SMLoc); + bool ParseDirectiveDumpOrLoad(StringRef, SMLoc); + bool ParseDirectiveLsym(StringRef, SMLoc); + bool ParseDirectiveSection(); + bool ParseDirectiveSecureLogReset(StringRef, SMLoc); + bool ParseDirectiveSecureLogUnique(StringRef, SMLoc); + bool ParseDirectiveSubsectionsViaSymbols(StringRef, SMLoc); + bool ParseDirectiveTBSS(StringRef, SMLoc); + bool ParseDirectiveZerofill(StringRef, SMLoc); + + // Named Section Directive + bool ParseSectionDirectiveConst(StringRef, SMLoc) { + return ParseSectionSwitch("__TEXT", "__const"); + } + bool ParseSectionDirectiveStaticConst(StringRef, SMLoc) { + return ParseSectionSwitch("__TEXT", "__static_const"); + } + bool ParseSectionDirectiveCString(StringRef, SMLoc) { + return ParseSectionSwitch("__TEXT","__cstring", + MCSectionMachO::S_CSTRING_LITERALS); + } + bool ParseSectionDirectiveLiteral4(StringRef, SMLoc) { + return ParseSectionSwitch("__TEXT", "__literal4", + MCSectionMachO::S_4BYTE_LITERALS, 4); + } + bool ParseSectionDirectiveLiteral8(StringRef, SMLoc) { + return ParseSectionSwitch("__TEXT", "__literal8", + MCSectionMachO::S_8BYTE_LITERALS, 8); + } + bool ParseSectionDirectiveLiteral16(StringRef, SMLoc) { + return ParseSectionSwitch("__TEXT","__literal16", + MCSectionMachO::S_16BYTE_LITERALS, 16); + } + bool ParseSectionDirectiveConstructor(StringRef, SMLoc) { + return ParseSectionSwitch("__TEXT","__constructor"); + } + bool ParseSectionDirectiveDestructor(StringRef, SMLoc) { + return ParseSectionSwitch("__TEXT","__destructor"); + } + bool ParseSectionDirectiveFVMLibInit0(StringRef, SMLoc) { + return ParseSectionSwitch("__TEXT","__fvmlib_init0"); + } + bool ParseSectionDirectiveFVMLibInit1(StringRef, SMLoc) { + return ParseSectionSwitch("__TEXT","__fvmlib_init1"); + } + bool ParseSectionDirectiveSymbolStub(StringRef, SMLoc) { + return ParseSectionSwitch("__TEXT","__symbol_stub", + MCSectionMachO::S_SYMBOL_STUBS | + MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS, + // FIXME: Different on PPC and ARM. + 0, 16); + } + bool ParseSectionDirectivePICSymbolStub(StringRef, SMLoc) { + return ParseSectionSwitch("__TEXT","__picsymbol_stub", + MCSectionMachO::S_SYMBOL_STUBS | + MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS, 0, 26); + } + bool ParseSectionDirectiveData(StringRef, SMLoc) { + return ParseSectionSwitch("__DATA", "__data"); + } + bool ParseSectionDirectiveStaticData(StringRef, SMLoc) { + return ParseSectionSwitch("__DATA", "__static_data"); + } + bool ParseSectionDirectiveNonLazySymbolPointers(StringRef, SMLoc) { + return ParseSectionSwitch("__DATA", "__nl_symbol_ptr", + MCSectionMachO::S_NON_LAZY_SYMBOL_POINTERS, 4); + } + bool ParseSectionDirectiveLazySymbolPointers(StringRef, SMLoc) { + return ParseSectionSwitch("__DATA", "__la_symbol_ptr", + MCSectionMachO::S_LAZY_SYMBOL_POINTERS, 4); + } + bool ParseSectionDirectiveDyld(StringRef, SMLoc) { + return ParseSectionSwitch("__DATA", "__dyld"); + } + bool ParseSectionDirectiveModInitFunc(StringRef, SMLoc) { + return ParseSectionSwitch("__DATA", "__mod_init_func", + MCSectionMachO::S_MOD_INIT_FUNC_POINTERS, 4); + } + bool ParseSectionDirectiveModTermFunc(StringRef, SMLoc) { + return ParseSectionSwitch("__DATA", "__mod_term_func", + MCSectionMachO::S_MOD_TERM_FUNC_POINTERS, 4); + } + bool ParseSectionDirectiveConstData(StringRef, SMLoc) { + return ParseSectionSwitch("__DATA", "__const"); + } + bool ParseSectionDirectiveObjCClass(StringRef, SMLoc) { + return ParseSectionSwitch("__OBJC", "__class", + MCSectionMachO::S_ATTR_NO_DEAD_STRIP); + } + bool ParseSectionDirectiveObjCMetaClass(StringRef, SMLoc) { + return ParseSectionSwitch("__OBJC", "__meta_class", + MCSectionMachO::S_ATTR_NO_DEAD_STRIP); + } + bool ParseSectionDirectiveObjCCatClsMeth(StringRef, SMLoc) { + return ParseSectionSwitch("__OBJC", "__cat_cls_meth", + MCSectionMachO::S_ATTR_NO_DEAD_STRIP); + } + bool ParseSectionDirectiveObjCCatInstMeth(StringRef, SMLoc) { + return ParseSectionSwitch("__OBJC", "__cat_inst_meth", + MCSectionMachO::S_ATTR_NO_DEAD_STRIP); + } + bool ParseSectionDirectiveObjCProtocol(StringRef, SMLoc) { + return ParseSectionSwitch("__OBJC", "__protocol", + MCSectionMachO::S_ATTR_NO_DEAD_STRIP); + } + bool ParseSectionDirectiveObjCStringObject(StringRef, SMLoc) { + return ParseSectionSwitch("__OBJC", "__string_object", + MCSectionMachO::S_ATTR_NO_DEAD_STRIP); + } + bool ParseSectionDirectiveObjCClsMeth(StringRef, SMLoc) { + return ParseSectionSwitch("__OBJC", "__cls_meth", + MCSectionMachO::S_ATTR_NO_DEAD_STRIP); + } + bool ParseSectionDirectiveObjCInstMeth(StringRef, SMLoc) { + return ParseSectionSwitch("__OBJC", "__inst_meth", + MCSectionMachO::S_ATTR_NO_DEAD_STRIP); + } + bool ParseSectionDirectiveObjCClsRefs(StringRef, SMLoc) { + return ParseSectionSwitch("__OBJC", "__cls_refs", + MCSectionMachO::S_ATTR_NO_DEAD_STRIP | + MCSectionMachO::S_LITERAL_POINTERS, 4); + } + bool ParseSectionDirectiveObjCMessageRefs(StringRef, SMLoc) { + return ParseSectionSwitch("__OBJC", "__message_refs", + MCSectionMachO::S_ATTR_NO_DEAD_STRIP | + MCSectionMachO::S_LITERAL_POINTERS, 4); + } + bool ParseSectionDirectiveObjCSymbols(StringRef, SMLoc) { + return ParseSectionSwitch("__OBJC", "__symbols", + MCSectionMachO::S_ATTR_NO_DEAD_STRIP); + } + bool ParseSectionDirectiveObjCCategory(StringRef, SMLoc) { + return ParseSectionSwitch("__OBJC", "__category", + MCSectionMachO::S_ATTR_NO_DEAD_STRIP); + } + bool ParseSectionDirectiveObjCClassVars(StringRef, SMLoc) { + return ParseSectionSwitch("__OBJC", "__class_vars", + MCSectionMachO::S_ATTR_NO_DEAD_STRIP); + } + bool ParseSectionDirectiveObjCInstanceVars(StringRef, SMLoc) { + return ParseSectionSwitch("__OBJC", "__instance_vars", + MCSectionMachO::S_ATTR_NO_DEAD_STRIP); + } + bool ParseSectionDirectiveObjCModuleInfo(StringRef, SMLoc) { + return ParseSectionSwitch("__OBJC", "__module_info", + MCSectionMachO::S_ATTR_NO_DEAD_STRIP); + } + bool ParseSectionDirectiveObjCClassNames(StringRef, SMLoc) { + return ParseSectionSwitch("__TEXT", "__cstring", + MCSectionMachO::S_CSTRING_LITERALS); + } + bool ParseSectionDirectiveObjCMethVarTypes(StringRef, SMLoc) { + return ParseSectionSwitch("__TEXT", "__cstring", + MCSectionMachO::S_CSTRING_LITERALS); + } + bool ParseSectionDirectiveObjCMethVarNames(StringRef, SMLoc) { + return ParseSectionSwitch("__TEXT", "__cstring", + MCSectionMachO::S_CSTRING_LITERALS); + } + bool ParseSectionDirectiveObjCSelectorStrs(StringRef, SMLoc) { + return ParseSectionSwitch("__OBJC", "__selector_strs", + MCSectionMachO::S_CSTRING_LITERALS); + } + bool ParseSectionDirectiveTData(StringRef, SMLoc) { + return ParseSectionSwitch("__DATA", "__thread_data", + MCSectionMachO::S_THREAD_LOCAL_REGULAR); + } + bool ParseSectionDirectiveText(StringRef, SMLoc) { + return ParseSectionSwitch("__TEXT", "__text", + MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS); + } + bool ParseSectionDirectiveTLV(StringRef, SMLoc) { + return ParseSectionSwitch("__DATA", "__thread_vars", + MCSectionMachO::S_THREAD_LOCAL_VARIABLES); + } + bool ParseSectionDirectiveThreadInitFunc(StringRef, SMLoc) { + return ParseSectionSwitch("__DATA", "__thread_init", + MCSectionMachO::S_THREAD_LOCAL_INIT_FUNCTION_POINTERS); + } + +}; + +} + +bool DarwinAsmParser::ParseSectionSwitch(const char *Segment, + const char *Section, + unsigned TAA, unsigned Align, + unsigned StubSize) { + if (getLexer().isNot(AsmToken::EndOfStatement)) + return TokError("unexpected token in section switching directive"); + Lex(); + + // FIXME: Arch specific. + bool isText = StringRef(Segment) == "__TEXT"; // FIXME: Hack. + getStreamer().SwitchSection(getContext().getMachOSection( + Segment, Section, TAA, StubSize, + isText ? SectionKind::getText() + : SectionKind::getDataRel())); + + // Set the implicit alignment, if any. + // + // FIXME: This isn't really what 'as' does; I think it just uses the implicit + // alignment on the section (e.g., if one manually inserts bytes into the + // section, then just issueing the section switch directive will not realign + // the section. However, this is arguably more reasonable behavior, and there + // is no good reason for someone to intentionally emit incorrectly sized + // values into the implicitly aligned sections. + if (Align) + getStreamer().EmitValueToAlignment(Align, 0, 1, 0); + + return false; +} + +/// ParseDirectiveDesc +/// ::= .desc identifier , expression +bool DarwinAsmParser::ParseDirectiveDesc(StringRef, SMLoc) { + StringRef Name; + if (getParser().ParseIdentifier(Name)) + return TokError("expected identifier in directive"); + + // Handle the identifier as the key symbol. + MCSymbol *Sym = getContext().GetOrCreateSymbol(Name); + + if (getLexer().isNot(AsmToken::Comma)) + return TokError("unexpected token in '.desc' directive"); + Lex(); + + int64_t DescValue; + if (getParser().ParseAbsoluteExpression(DescValue)) + return true; + + if (getLexer().isNot(AsmToken::EndOfStatement)) + return TokError("unexpected token in '.desc' directive"); + + Lex(); + + // Set the n_desc field of this Symbol to this DescValue + getStreamer().EmitSymbolDesc(Sym, DescValue); + + return false; +} + +/// ParseDirectiveDumpOrLoad +/// ::= ( .dump | .load ) "filename" +bool DarwinAsmParser::ParseDirectiveDumpOrLoad(StringRef Directive, + SMLoc IDLoc) { + bool IsDump = Directive == ".dump"; + if (getLexer().isNot(AsmToken::String)) + return TokError("expected string in '.dump' or '.load' directive"); + + Lex(); + + if (getLexer().isNot(AsmToken::EndOfStatement)) + return TokError("unexpected token in '.dump' or '.load' directive"); + + Lex(); + + // FIXME: If/when .dump and .load are implemented they will be done in the + // the assembly parser and not have any need for an MCStreamer API. + if (IsDump) + Warning(IDLoc, "ignoring directive .dump for now"); + else + Warning(IDLoc, "ignoring directive .load for now"); + + return false; +} + +/// ParseDirectiveLsym +/// ::= .lsym identifier , expression +bool DarwinAsmParser::ParseDirectiveLsym(StringRef, SMLoc) { + StringRef Name; + if (getParser().ParseIdentifier(Name)) + return TokError("expected identifier in directive"); + + // Handle the identifier as the key symbol. + MCSymbol *Sym = getContext().GetOrCreateSymbol(Name); + + if (getLexer().isNot(AsmToken::Comma)) + return TokError("unexpected token in '.lsym' directive"); + Lex(); + + const MCExpr *Value; + if (getParser().ParseExpression(Value)) + return true; + + if (getLexer().isNot(AsmToken::EndOfStatement)) + return TokError("unexpected token in '.lsym' directive"); + + Lex(); + + // We don't currently support this directive. + // + // FIXME: Diagnostic location! + (void) Sym; + return TokError("directive '.lsym' is unsupported"); +} + +/// ParseDirectiveSection: +/// ::= .section identifier (',' identifier)* +bool DarwinAsmParser::ParseDirectiveSection() { + SMLoc Loc = getLexer().getLoc(); + + StringRef SectionName; + if (getParser().ParseIdentifier(SectionName)) + return Error(Loc, "expected identifier after '.section' directive"); + + // Verify there is a following comma. + if (!getLexer().is(AsmToken::Comma)) + return TokError("unexpected token in '.section' directive"); + + std::string SectionSpec = SectionName; + SectionSpec += ","; + + // Add all the tokens until the end of the line, ParseSectionSpecifier will + // handle this. + StringRef EOL = getLexer().LexUntilEndOfStatement(); + SectionSpec.append(EOL.begin(), EOL.end()); + + Lex(); + if (getLexer().isNot(AsmToken::EndOfStatement)) + return TokError("unexpected token in '.section' directive"); + Lex(); + + + StringRef Segment, Section; + unsigned TAA, StubSize; + std::string ErrorStr = + MCSectionMachO::ParseSectionSpecifier(SectionSpec, Segment, Section, + TAA, StubSize); + + if (!ErrorStr.empty()) + return Error(Loc, ErrorStr.c_str()); + + // FIXME: Arch specific. + bool isText = Segment == "__TEXT"; // FIXME: Hack. + getStreamer().SwitchSection(getContext().getMachOSection( + Segment, Section, TAA, StubSize, + isText ? SectionKind::getText() + : SectionKind::getDataRel())); + return false; +} + +/// ParseDirectiveSecureLogUnique +/// ::= .secure_log_unique "log message" +bool DarwinAsmParser::ParseDirectiveSecureLogUnique(StringRef, SMLoc IDLoc) { + std::string LogMessage; + + if (getLexer().isNot(AsmToken::String)) + LogMessage = ""; + else{ + LogMessage = getTok().getString(); + Lex(); + } + + if (getLexer().isNot(AsmToken::EndOfStatement)) + return TokError("unexpected token in '.secure_log_unique' directive"); + + if (getContext().getSecureLogUsed() != false) + return Error(IDLoc, ".secure_log_unique specified multiple times"); + + char *SecureLogFile = getContext().getSecureLogFile(); + if (SecureLogFile == NULL) + return Error(IDLoc, ".secure_log_unique used but AS_SECURE_LOG_FILE " + "environment variable unset."); + + raw_ostream *OS = getContext().getSecureLog(); + if (OS == NULL) { + std::string Err; + OS = new raw_fd_ostream(SecureLogFile, Err, raw_fd_ostream::F_Append); + if (!Err.empty()) { + delete OS; + return Error(IDLoc, Twine("can't open secure log file: ") + + SecureLogFile + " (" + Err + ")"); + } + getContext().setSecureLog(OS); + } + + int CurBuf = getSourceManager().FindBufferContainingLoc(IDLoc); + *OS << getSourceManager().getBufferInfo(CurBuf).Buffer->getBufferIdentifier() + << ":" << getSourceManager().FindLineNumber(IDLoc, CurBuf) << ":" + << LogMessage + "\n"; + + getContext().setSecureLogUsed(true); + + return false; +} + +/// ParseDirectiveSecureLogReset +/// ::= .secure_log_reset +bool DarwinAsmParser::ParseDirectiveSecureLogReset(StringRef, SMLoc IDLoc) { + if (getLexer().isNot(AsmToken::EndOfStatement)) + return TokError("unexpected token in '.secure_log_reset' directive"); + + Lex(); + + getContext().setSecureLogUsed(false); + + return false; +} + +/// ParseDirectiveSubsectionsViaSymbols +/// ::= .subsections_via_symbols +bool DarwinAsmParser::ParseDirectiveSubsectionsViaSymbols(StringRef, SMLoc) { + if (getLexer().isNot(AsmToken::EndOfStatement)) + return TokError("unexpected token in '.subsections_via_symbols' directive"); + + Lex(); + + getStreamer().EmitAssemblerFlag(MCAF_SubsectionsViaSymbols); + + return false; +} + +/// ParseDirectiveTBSS +/// ::= .tbss identifier, size, align +bool DarwinAsmParser::ParseDirectiveTBSS(StringRef, SMLoc) { + SMLoc IDLoc = getLexer().getLoc(); + StringRef Name; + if (getParser().ParseIdentifier(Name)) + return TokError("expected identifier in directive"); + + // Handle the identifier as the key symbol. + MCSymbol *Sym = getContext().GetOrCreateSymbol(Name); + + if (getLexer().isNot(AsmToken::Comma)) + return TokError("unexpected token in directive"); + Lex(); + + int64_t Size; + SMLoc SizeLoc = getLexer().getLoc(); + if (getParser().ParseAbsoluteExpression(Size)) + return true; + + int64_t Pow2Alignment = 0; + SMLoc Pow2AlignmentLoc; + if (getLexer().is(AsmToken::Comma)) { + Lex(); + Pow2AlignmentLoc = getLexer().getLoc(); + if (getParser().ParseAbsoluteExpression(Pow2Alignment)) + return true; + } + + if (getLexer().isNot(AsmToken::EndOfStatement)) + return TokError("unexpected token in '.tbss' directive"); + + Lex(); + + if (Size < 0) + return Error(SizeLoc, "invalid '.tbss' directive size, can't be less than" + "zero"); + + // FIXME: Diagnose overflow. + if (Pow2Alignment < 0) + return Error(Pow2AlignmentLoc, "invalid '.tbss' alignment, can't be less" + "than zero"); + + if (!Sym->isUndefined()) + return Error(IDLoc, "invalid symbol redefinition"); + + getStreamer().EmitTBSSSymbol(getContext().getMachOSection( + "__DATA", "__thread_bss", + MCSectionMachO::S_THREAD_LOCAL_ZEROFILL, + 0, SectionKind::getThreadBSS()), + Sym, Size, 1 << Pow2Alignment); + + return false; +} + +/// ParseDirectiveZerofill +/// ::= .zerofill segname , sectname [, identifier , size_expression [ +/// , align_expression ]] +bool DarwinAsmParser::ParseDirectiveZerofill(StringRef, SMLoc) { + StringRef Segment; + if (getParser().ParseIdentifier(Segment)) + return TokError("expected segment name after '.zerofill' directive"); + + if (getLexer().isNot(AsmToken::Comma)) + return TokError("unexpected token in directive"); + Lex(); + + StringRef Section; + if (getParser().ParseIdentifier(Section)) + return TokError("expected section name after comma in '.zerofill' " + "directive"); + + // If this is the end of the line all that was wanted was to create the + // the section but with no symbol. + if (getLexer().is(AsmToken::EndOfStatement)) { + // Create the zerofill section but no symbol + getStreamer().EmitZerofill(getContext().getMachOSection( + Segment, Section, MCSectionMachO::S_ZEROFILL, + 0, SectionKind::getBSS())); + return false; + } + + if (getLexer().isNot(AsmToken::Comma)) + return TokError("unexpected token in directive"); + Lex(); + + SMLoc IDLoc = getLexer().getLoc(); + StringRef IDStr; + if (getParser().ParseIdentifier(IDStr)) + return TokError("expected identifier in directive"); + + // handle the identifier as the key symbol. + MCSymbol *Sym = getContext().GetOrCreateSymbol(IDStr); + + if (getLexer().isNot(AsmToken::Comma)) + return TokError("unexpected token in directive"); + Lex(); + + int64_t Size; + SMLoc SizeLoc = getLexer().getLoc(); + if (getParser().ParseAbsoluteExpression(Size)) + return true; + + int64_t Pow2Alignment = 0; + SMLoc Pow2AlignmentLoc; + if (getLexer().is(AsmToken::Comma)) { + Lex(); + Pow2AlignmentLoc = getLexer().getLoc(); + if (getParser().ParseAbsoluteExpression(Pow2Alignment)) + return true; + } + + if (getLexer().isNot(AsmToken::EndOfStatement)) + return TokError("unexpected token in '.zerofill' directive"); + + Lex(); + + if (Size < 0) + return Error(SizeLoc, "invalid '.zerofill' directive size, can't be less " + "than zero"); + + // NOTE: The alignment in the directive is a power of 2 value, the assembler + // may internally end up wanting an alignment in bytes. + // FIXME: Diagnose overflow. + if (Pow2Alignment < 0) + return Error(Pow2AlignmentLoc, "invalid '.zerofill' directive alignment, " + "can't be less than zero"); + + if (!Sym->isUndefined()) + return Error(IDLoc, "invalid symbol redefinition"); + + // Create the zerofill Symbol with Size and Pow2Alignment + // + // FIXME: Arch specific. + getStreamer().EmitZerofill(getContext().getMachOSection( + Segment, Section, MCSectionMachO::S_ZEROFILL, + 0, SectionKind::getBSS()), + Sym, Size, 1 << Pow2Alignment); + + return false; +} + +namespace llvm { + +MCAsmParserExtension *createDarwinAsmParser() { + return new DarwinAsmParser; +} + +} From akyrtzi at gmail.com Mon Jul 12 15:47:08 2010 From: akyrtzi at gmail.com (Argyrios Kyrtzidis) Date: Mon, 12 Jul 2010 20:47:08 -0000 Subject: [llvm-commits] [llvm] r108192 - /llvm/trunk/include/llvm/ADT/FoldingSet.h Message-ID: <20100712204708.6A1B72A6C12C@llvm.org> Author: akirtzidis Date: Mon Jul 12 15:47:08 2010 New Revision: 108192 URL: http://llvm.org/viewvc/llvm-project?rev=108192&view=rev Log: Add convenience method FoldingSetImpl::InsertNode(Node *N) that asserts if the node is already inserted. Modified: llvm/trunk/include/llvm/ADT/FoldingSet.h Modified: llvm/trunk/include/llvm/ADT/FoldingSet.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/FoldingSet.h?rev=108192&r1=108191&r2=108192&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/FoldingSet.h (original) +++ llvm/trunk/include/llvm/ADT/FoldingSet.h Mon Jul 12 15:47:08 2010 @@ -166,6 +166,14 @@ /// FindNodeOrInsertPos. void InsertNode(Node *N, void *InsertPos); + /// InsertNode - Insert the specified node into the folding set, knowing that + /// it is not already in the folding set. + void InsertNode(Node *N) { + Node *Inserted = GetOrInsertNode(N); + (void)Inserted; + assert(Inserted == N && "Node already inserted!"); + } + /// size - Returns the number of nodes in the folding set. unsigned size() const { return NumNodes; } From clattner at apple.com Mon Jul 12 16:22:46 2010 From: clattner at apple.com (Chris Lattner) Date: Mon, 12 Jul 2010 14:22:46 -0700 Subject: [llvm-commits] [PATCH] Support/ELF.h extensions In-Reply-To: References: <3008EE29-F5B7-4499-831F-B4DE8E61573C@apple.com> Message-ID: <1CE631DC-C0B0-4AE5-BECD-8430B6DBE08A@apple.com> On Jul 12, 2010, at 9:46 AM, Stephen Wilson wrote: > Hi Chris, > > Chris Lattner writes: >> A few stylistic updates: >> >> - unsigned char getFileClass () const { return e_ident[4]; } >> - unsigned char getDataEncoding () { return e_ident[5]; } >> + unsigned char getFileClass () const { return e_ident[EI_CLASS]; } >> + unsigned char getDataEncoding () { return e_ident[EI_DATA]; } >> >> Not your doing, but please don't put a space before argument lists: use getFileClass() instead of getFileClass () >> >> Likewise here: >> >> Elf64_Quarter e_shstrndx; >> + bool checkMagic () const { >> + return (memcmp (e_ident, ElfMagic, strlen (ElfMagic))) == 0; >> + } >> + unsigned char getFileClass () const { return e_ident[EI_CLASS]; } >> + unsigned char getDataEncoding () { return e_ident[EI_DATA]; } >> > > OK. There are a few additional places in the file that require this > format fix as well. Will apply. Sounds good, thanks! -Chris From daniel at zuster.org Mon Jul 12 16:23:33 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 12 Jul 2010 21:23:33 -0000 Subject: [llvm-commits] [llvm] r108196 - in /llvm/trunk/lib/MC/MCParser: AsmParser.cpp CMakeLists.txt ELFAsmParser.cpp Message-ID: <20100712212333.23EA82A6C12C@llvm.org> Author: ddunbar Date: Mon Jul 12 16:23:32 2010 New Revision: 108196 URL: http://llvm.org/viewvc/llvm-project?rev=108196&view=rev Log: MC/AsmParser: Move ELF specific parser to ELFAsmParser.cpp. Added: llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp llvm/trunk/lib/MC/MCParser/CMakeLists.txt Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=108196&r1=108195&r2=108196&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Mon Jul 12 16:23:32 2010 @@ -18,7 +18,6 @@ #include "llvm/MC/MCContext.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" -#include "llvm/MC/MCSectionELF.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSymbol.h" #include "llvm/MC/MCParser/MCParsedAsmOperand.h" @@ -55,40 +54,12 @@ bool ParseDirectiveLoc(StringRef, SMLoc DirectiveLoc); // ".loc" }; -class ELFAsmParser : public MCAsmParserExtension { - bool ParseSectionSwitch(StringRef Section, unsigned Type, - unsigned Flags, SectionKind Kind); - -public: - ELFAsmParser() {} - - virtual void Initialize(MCAsmParser &Parser) { - // Call the base implementation. - this->MCAsmParserExtension::Initialize(Parser); - - Parser.AddDirectiveHandler(this, ".data", MCAsmParser::DirectiveHandler( - &ELFAsmParser::ParseSectionDirectiveData)); - Parser.AddDirectiveHandler(this, ".text", MCAsmParser::DirectiveHandler( - &ELFAsmParser::ParseSectionDirectiveText)); - } - - bool ParseSectionDirectiveData(StringRef, SMLoc) { - return ParseSectionSwitch(".data", MCSectionELF::SHT_PROGBITS, - MCSectionELF::SHF_WRITE |MCSectionELF::SHF_ALLOC, - SectionKind::getDataRel()); - } - bool ParseSectionDirectiveText(StringRef, SMLoc) { - return ParseSectionSwitch(".text", MCSectionELF::SHT_PROGBITS, - MCSectionELF::SHF_EXECINSTR | - MCSectionELF::SHF_ALLOC, SectionKind::getText()); - } -}; - } namespace llvm { extern MCAsmParserExtension *createDarwinAsmParser(); +extern MCAsmParserExtension *createELFAsmParser(); } @@ -112,7 +83,7 @@ PlatformParser = createDarwinAsmParser(); PlatformParser->Initialize(*this); } else { - PlatformParser = new ELFAsmParser; + PlatformParser = createELFAsmParser(); PlatformParser->Initialize(*this); } } @@ -815,18 +786,6 @@ return ParseAssignment(Name); } -bool ELFAsmParser::ParseSectionSwitch(StringRef Section, unsigned Type, - unsigned Flags, SectionKind Kind) { - if (getLexer().isNot(AsmToken::EndOfStatement)) - return TokError("unexpected token in section switching directive"); - Lex(); - - getStreamer().SwitchSection(getContext().getELFSection( - Section, Type, Flags, Kind)); - - return false; -} - bool AsmParser::ParseEscapedString(std::string &Data) { assert(getLexer().is(AsmToken::String) && "Unexpected current token!"); Modified: llvm/trunk/lib/MC/MCParser/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/CMakeLists.txt?rev=108196&r1=108195&r2=108196&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/CMakeLists.txt (original) +++ llvm/trunk/lib/MC/MCParser/CMakeLists.txt Mon Jul 12 16:23:32 2010 @@ -2,6 +2,7 @@ AsmLexer.cpp AsmParser.cpp DarwinAsmParser.cpp + ELFAsmParser.cpp MCAsmLexer.cpp MCAsmParser.cpp MCAsmParserExtension.cpp Added: llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp?rev=108196&view=auto ============================================================================== --- llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp (added) +++ llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp Mon Jul 12 16:23:32 2010 @@ -0,0 +1,68 @@ +//===- ELFAsmParser.cpp - ELF Assembly Parser -----------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "llvm/MC/MCParser/MCAsmParserExtension.h" +#include "llvm/MC/MCSectionELF.h" +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCStreamer.h" +#include "llvm/MC/MCParser/MCAsmLexer.h" +using namespace llvm; + +namespace { + +class ELFAsmParser : public MCAsmParserExtension { + bool ParseSectionSwitch(StringRef Section, unsigned Type, + unsigned Flags, SectionKind Kind); + +public: + ELFAsmParser() {} + + virtual void Initialize(MCAsmParser &Parser) { + // Call the base implementation. + this->MCAsmParserExtension::Initialize(Parser); + + Parser.AddDirectiveHandler(this, ".data", MCAsmParser::DirectiveHandler( + &ELFAsmParser::ParseSectionDirectiveData)); + Parser.AddDirectiveHandler(this, ".text", MCAsmParser::DirectiveHandler( + &ELFAsmParser::ParseSectionDirectiveText)); + } + + bool ParseSectionDirectiveData(StringRef, SMLoc) { + return ParseSectionSwitch(".data", MCSectionELF::SHT_PROGBITS, + MCSectionELF::SHF_WRITE |MCSectionELF::SHF_ALLOC, + SectionKind::getDataRel()); + } + bool ParseSectionDirectiveText(StringRef, SMLoc) { + return ParseSectionSwitch(".text", MCSectionELF::SHT_PROGBITS, + MCSectionELF::SHF_EXECINSTR | + MCSectionELF::SHF_ALLOC, SectionKind::getText()); + } +}; + +} + +bool ELFAsmParser::ParseSectionSwitch(StringRef Section, unsigned Type, + unsigned Flags, SectionKind Kind) { + if (getLexer().isNot(AsmToken::EndOfStatement)) + return TokError("unexpected token in section switching directive"); + Lex(); + + getStreamer().SwitchSection(getContext().getELFSection( + Section, Type, Flags, Kind)); + + return false; +} + +namespace llvm { + +MCAsmParserExtension *createELFAsmParser() { + return new ELFAsmParser; +} + +} From wilsons at start.ca Mon Jul 12 16:34:37 2010 From: wilsons at start.ca (Stephen Wilson) Date: Mon, 12 Jul 2010 21:34:37 -0000 Subject: [llvm-commits] [llvm] r108197 - /llvm/trunk/include/llvm/Support/ELF.h Message-ID: <20100712213437.3C55A2A6C12C@llvm.org> Author: wilsons Date: Mon Jul 12 16:34:37 2010 New Revision: 108197 URL: http://llvm.org/viewvc/llvm-project?rev=108197&view=rev Log: Test commit. Modified: llvm/trunk/include/llvm/Support/ELF.h Modified: llvm/trunk/include/llvm/Support/ELF.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ELF.h?rev=108197&r1=108196&r2=108197&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/ELF.h (original) +++ llvm/trunk/include/llvm/Support/ELF.h Mon Jul 12 16:34:37 2010 @@ -62,7 +62,7 @@ Elf32_Half e_shentsize; // Size of an entry in the section header table Elf32_Half e_shnum; // Number of entries in the section header table Elf32_Half e_shstrndx; // Sect hdr table index of sect name string table - bool checkMagic () const { + bool checkMagic() const { return (memcmp (e_ident, ElfMagic, strlen (ElfMagic))) == 0; } unsigned char getFileClass () const { return e_ident[4]; } From sabre at nondot.org Mon Jul 12 16:44:00 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 12 Jul 2010 14:44:00 -0700 Subject: [llvm-commits] [llvm] r108109 - /llvm/trunk/lib/CodeGen/MachineLICM.cpp In-Reply-To: References: <20100712000035.393982A6C12C@llvm.org> <5470C984-D21B-4C3F-860C-D7506AFBFAAB@apple.com> Message-ID: <3434519D-9F54-4516-A09A-FAE224A0E8C5@nondot.org> On Jul 12, 2010, at 11:22 AM, Evan Cheng wrote: > > On Jul 12, 2010, at 8:29 AM, Chris Lattner wrote: > >> >> On Jul 12, 2010, at 12:57 AM, Evan Cheng wrote: >> >>>> change machinelicm to use MachineInstr::isSafeToMove. No >>>> intended functionality change. >>>> >>>> The avoidance of hoistiing implicitdef seems wrong though. >>> >>> It's not. We want to avoid creating implicitdef with no trivial live intervals. The trivial ones will be converted to undef machine operands which do not take up registers. >> >> Why? The register allocator treats them specially just so they don't use a register (according to Jakob). > > No, that's not correct. The ones with trivial live intervals, i.e. defined and used in the same BB, are converted to undef operands. These do not take up registers. The ones that have uses outside of the definition block *may* not be eliminated. Those will take up registers. Jakob, didn't you just tell me that the RA turned them into trivial short live ranges? If not, isn't that the right thing to do? -Chris From echristo at apple.com Mon Jul 12 17:06:53 2010 From: echristo at apple.com (Eric Christopher) Date: Mon, 12 Jul 2010 22:06:53 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r108201 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Message-ID: <20100712220653.1B9F32A6C12C@llvm.org> Author: echristo Date: Mon Jul 12 17:06:52 2010 New Revision: 108201 URL: http://llvm.org/viewvc/llvm-project?rev=108201&view=rev Log: 80-col fixups. Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=108201&r1=108200&r2=108201&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Mon Jul 12 17:06:52 2010 @@ -546,7 +546,8 @@ } else if (DECL_WEAK(FnDecl)) { // The user may have explicitly asked for weak linkage - ignore flag_odr. Fn->setLinkage(Function::WeakAnyLinkage); - } else if (DECL_ONE_ONLY(FnDecl) || lang_hooks.function_is_thunk_p (FnDecl)) { + } else if (DECL_ONE_ONLY(FnDecl) || + lang_hooks.function_is_thunk_p (FnDecl)) { Fn->setLinkage(Function::getWeakLinkage(flag_odr)); } else if (IS_EXTERN_INLINE(FnDecl)) { // gcc "extern inline", C99 "inline" @@ -770,7 +771,7 @@ RetVal = BitCastToType(RetVal, Type::getInt8PtrTy(Context)); RetVal = Builder.CreateGEP(RetVal, - ConstantInt::get(TD.getIntPtrType(Context), ReturnOffset)); + ConstantInt::get(TD.getIntPtrType(Context), ReturnOffset)); } RetVal = BitCastToType(RetVal, Fn->getReturnType()->getPointerTo()); RetVal = Builder.CreateLoad(RetVal, "retval"); @@ -842,7 +843,8 @@ // basic block. But an empty block must have one outgoing edge, // and there might be some location info there; grab it. if (!stmt && EmitDebugInfo()) { - assert(EDGE_COUNT(bb->succs) == 1 && "empty basic block with multiple successors?") ; + assert(EDGE_COUNT(bb->succs) == 1 && + "empty basic block with multiple successors?"); e = EDGE_I(bb->succs, 0); source_locus locus = e->goto_locus; if (locus) { @@ -908,14 +910,16 @@ // equal, but the climbers differ, they are siblings: both // climbers rise to the next level. while (new_climber != current_climber) { - current_climber_depth = DECL_P(current_climber) ? 0 : BLOCK_NUMBER(current_climber); + current_climber_depth = DECL_P(current_climber) ? + 0 : BLOCK_NUMBER(current_climber); new_climber_depth = DECL_P(new_climber) ? 0 : BLOCK_NUMBER(new_climber); if (new_climber_depth <= current_climber_depth) current_climber = BLOCK_SUPERCONTEXT(current_climber); if (new_climber_depth >= current_climber_depth) new_climber = BLOCK_SUPERCONTEXT(new_climber); } - assert(new_climber == current_climber && "missed common TREE_BLOCK parent"); + assert(new_climber == current_climber && + "missed common TREE_BLOCK parent"); // Pop and push lexical blocks to arrive at the new context. TheDebugInfo->change_regions(new_block, new_climber); } @@ -1958,7 +1962,8 @@ if (!Cond->getType()->isIntegerTy(1)) Cond = Builder.CreateIsNotNull(Cond, "toBool"); } else { - Cond = EmitCompare(exp_cond, UIPred, SIPred, FPPred, Type::getInt1Ty(Context)); + Cond = EmitCompare(exp_cond, UIPred, SIPred, FPPred, + Type::getInt1Ty(Context)); assert(Cond->getType() == Type::getInt1Ty(Context)); } @@ -3143,7 +3148,8 @@ } if (!InsertPtFinal) { - // If the instruction is an invoke, the init is inserted on the normal edge. + // If the instruction is an invoke, the init is inserted on the normal + // edge. if (InvokeInst *II = dyn_cast(InsertPt)) { InsertPt = II->getNormalDest()->begin(); while (isa(InsertPt)) @@ -3294,7 +3300,8 @@ ThisLastBitPlusOne = LV.BitStart+LV.BitSize; Value *Ptr = Index ? - Builder.CreateGEP(LV.Ptr, ConstantInt::get(Type::getInt32Ty(Context), Index)) : + Builder.CreateGEP(LV.Ptr, + ConstantInt::get(Type::getInt32Ty(Context), Index)) : LV.Ptr; LoadInst *LI = Builder.CreateLoad(Ptr, isVolatile); LI->setAlignment(Alignment); @@ -3693,15 +3700,16 @@ // Handle floating point comparisons, if we get here. Result = Builder.CreateFCmp(FCmpInst::Predicate(FPPred), LHS, RHS); } else { - // Handle the integer/pointer cases. Determine which predicate to use based - // on signedness. - ICmpInst::Predicate pred = ICmpInst::Predicate(LHSIsSigned ? SIOpc: UIOpc); + // Handle the integer/pointer cases. Determine which predicate to use + // based on signedness. + ICmpInst::Predicate pred = ICmpInst::Predicate(LHSIsSigned ? SIOpc:UIOpc); // Get the compare instructions Result = Builder.CreateICmp(pred, LHS, RHS); } } - assert(Result->getType() == Type::getInt1Ty(Context) && "Expected i1 result for compare"); + assert(Result->getType() == Type::getInt1Ty(Context) && + "Expected i1 result for compare"); if (DestTy == 0) DestTy = ConvertType(TREE_TYPE(exp)); @@ -4886,17 +4894,17 @@ unsigned OTyBits = TD.getTypeSizeInBits(OTy); unsigned OpTyBits = TD.getTypeSizeInBits(OpTy); if (OTyBits == 0 || OpTyBits == 0 || OTyBits < OpTyBits) { - // It's tempting to implement the OTyBits < OpTyBits case by truncating - // Op down to OTy, however that breaks in the case of an inline asm - // constraint that corresponds to a single register, because the - // user can write code that assumes the whole register is defined, - // despite the output operand being only a subset of the register. For - // example: + // It's tempting to implement the OTyBits < OpTyBits case by + // truncating Op down to OTy, however that breaks in the case of an + // inline asm constraint that corresponds to a single register, + // because the user can write code that assumes the whole register + // is defined, despite the output operand being only a subset of the + // register. For example: // // asm ("sarl $10, %%eax" : "=a"(c) : "0"(1000000)); // - // The expected behavior is for %eax to be fully defined with the value - // 1000000 immediately before the asm. + // The expected behavior is for %eax to be fully defined with the + // value 1000000 immediately before the asm. error("%Hunsupported inline asm: input constraint with a matching " "output constraint of incompatible type!", &EXPR_LOCATION(exp)); @@ -5064,7 +5072,7 @@ for (unsigned i = 0, e = Ops.size(); i != e; ++i) Result = Builder.CreateInsertElement(Result, Ops[i], - ConstantInt::get(Type::getInt32Ty(Context), i)); + ConstantInt::get(Type::getInt32Ty(Context), i)); return Result; } @@ -5419,7 +5427,8 @@ Value *Amt = Emit(TREE_VALUE(TREE_OPERAND(exp, 1)), 0); EmitBuiltinUnaryOp(Amt, Result, Intrinsic::ctlz); const Type *DestTy = ConvertType(TREE_TYPE(exp)); - Result = Builder.CreateIntCast(Result, DestTy, !TYPE_UNSIGNED(TREE_TYPE(exp)), + Result = Builder.CreateIntCast(Result, DestTy, + !TYPE_UNSIGNED(TREE_TYPE(exp)), "cast"); return true; } @@ -5429,7 +5438,8 @@ Value *Amt = Emit(TREE_VALUE(TREE_OPERAND(exp, 1)), 0); EmitBuiltinUnaryOp(Amt, Result, Intrinsic::cttz); const Type *DestTy = ConvertType(TREE_TYPE(exp)); - Result = Builder.CreateIntCast(Result, DestTy, !TYPE_UNSIGNED(TREE_TYPE(exp)), + Result = Builder.CreateIntCast(Result, DestTy, + !TYPE_UNSIGNED(TREE_TYPE(exp)), "cast"); return true; } @@ -5448,7 +5458,8 @@ Value *Amt = Emit(TREE_VALUE(TREE_OPERAND(exp, 1)), 0); EmitBuiltinUnaryOp(Amt, Result, Intrinsic::ctpop); const Type *DestTy = ConvertType(TREE_TYPE(exp)); - Result = Builder.CreateIntCast(Result, DestTy, !TYPE_UNSIGNED(TREE_TYPE(exp)), + Result = Builder.CreateIntCast(Result, DestTy, + !TYPE_UNSIGNED(TREE_TYPE(exp)), "cast"); return true; } @@ -5457,7 +5468,8 @@ Value *Amt = Emit(TREE_VALUE(TREE_OPERAND(exp, 1)), 0); EmitBuiltinUnaryOp(Amt, Result, Intrinsic::bswap); const Type *DestTy = ConvertType(TREE_TYPE(exp)); - Result = Builder.CreateIntCast(Result, DestTy, !TYPE_UNSIGNED(TREE_TYPE(exp)), + Result = Builder.CreateIntCast(Result, DestTy, + !TYPE_UNSIGNED(TREE_TYPE(exp)), "cast"); return true; } @@ -6302,7 +6314,8 @@ ReadWrite = 0; } else { ReadWrite = Builder.getFolder().CreateIntCast(cast(ReadWrite), - Type::getInt32Ty(Context), false); + Type::getInt32Ty(Context), + false); } if (TREE_CHAIN(TREE_CHAIN(arglist))) { @@ -6315,7 +6328,8 @@ Locality = 0; } else { Locality = Builder.getFolder().CreateIntCast(cast(Locality), - Type::getInt32Ty(Context), false); + Type::getInt32Ty(Context), + false); } } } @@ -6436,7 +6450,8 @@ // FIXME: is i32 always enough here? Result = Builder.CreateCall(Intrinsic::getDeclaration(TheModule, Intrinsic::eh_dwarf_cfa), - ConstantInt::get(Type::getInt32Ty(Context), cfa_offset)); + ConstantInt::get(Type::getInt32Ty(Context), + cfa_offset)); return true; } @@ -6552,13 +6567,15 @@ if (!wrote_return_column) { Size = ConstantInt::get(Type::getInt8Ty(Context), GET_MODE_SIZE (Pmode)); - Idx = ConstantInt::get(Type::getInt32Ty(Context), DWARF_FRAME_RETURN_COLUMN); + Idx = ConstantInt::get(Type::getInt32Ty(Context), + DWARF_FRAME_RETURN_COLUMN); Builder.CreateStore(Size, Builder.CreateGEP(Addr, Idx), false); } #ifdef DWARF_ALT_FRAME_RETURN_COLUMN Size = ConstantInt::get(Type::getInt8Ty(Context), GET_MODE_SIZE (Pmode)); - Idx = ConstantInt::get(Type::getInt32Ty(Context), DWARF_ALT_FRAME_RETURN_COLUMN); + Idx = ConstantInt::get(Type::getInt32Ty(Context), + DWARF_ALT_FRAME_RETURN_COLUMN); Builder.CreateStore(Size, Builder.CreateGEP(Addr, Idx), false); #endif @@ -7053,7 +7070,8 @@ // than this. e.g. check out when compiling unwind-dw2-fde-darwin.c. Ptr.Ptr = BitCastToType(Ptr.Ptr, ValTy->getPointerTo()); Ptr.Ptr = Builder.CreateGEP(Ptr.Ptr, - ConstantInt::get(Type::getInt32Ty(Context), UnitOffset)); + ConstantInt::get(Type::getInt32Ty(Context), + UnitOffset)); BitStart -= UnitOffset*ValueSizeInBits; } @@ -7696,7 +7714,8 @@ if (llvm::sys::isBigEndianHost() == BYTES_BIG_ENDIAN) Elts.push_back(ConstantInt::get(Type::getInt16Ty(Context), InStr[i])); else - Elts.push_back(ConstantInt::get(Type::getInt16Ty(Context), ByteSwap_16(InStr[i]))); + Elts.push_back(ConstantInt::get(Type::getInt16Ty(Context), + ByteSwap_16(InStr[i]))); } } else if (ElTy->isIntegerTy(32)) { assert((Len&3) == 0 && @@ -7709,7 +7728,8 @@ if (llvm::sys::isBigEndianHost() == BYTES_BIG_ENDIAN) Elts.push_back(ConstantInt::get(Type::getInt32Ty(Context), InStr[i])); else - Elts.push_back(ConstantInt::get(Type::getInt32Ty(Context), ByteSwap_32(InStr[i]))); + Elts.push_back(ConstantInt::get(Type::getInt32Ty(Context), + ByteSwap_32(InStr[i]))); } } else { assert(0 && "Unknown character type!"); @@ -8334,7 +8354,7 @@ ValC = dyn_cast(Val); if (ValC && ValC->isZero()) { // G++ has various bugs handling {} initializers where it doesn't - // synthesize a zero node of the right type. Instead of figuring out G++, + // synthesize a zero node of the right type. Instead of figuring out G++, // just hack around it by special casing zero and allowing it to be the // wrong size. if (ValueSizeInBits != FieldSizeInBits) { From daniel at zuster.org Mon Jul 12 17:30:06 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 12 Jul 2010 22:30:06 -0000 Subject: [llvm-commits] [test-suite] r108202 - in /test-suite/trunk/MultiSource: Applications/sgefa/blas.c Applications/sgefa/sgesl.c Benchmarks/MallocBench/espresso/cvrm.c Benchmarks/MallocBench/espresso/cvrout.c Benchmarks/MallocBench/espresso/hack.c Benchmarks/MallocBench/espresso/pair.c Benchmarks/McCat/09-vor/splay.c Benchmarks/McCat/09-vor/splay2.c Message-ID: <20100712223006.715062A6C12C@llvm.org> Author: ddunbar Date: Mon Jul 12 17:30:06 2010 New Revision: 108202 URL: http://llvm.org/viewvc/llvm-project?rev=108202&view=rev Log: Fix some -Wreturn-value problems, which Clang now errors on. Modified: test-suite/trunk/MultiSource/Applications/sgefa/blas.c test-suite/trunk/MultiSource/Applications/sgefa/sgesl.c test-suite/trunk/MultiSource/Benchmarks/MallocBench/espresso/cvrm.c test-suite/trunk/MultiSource/Benchmarks/MallocBench/espresso/cvrout.c test-suite/trunk/MultiSource/Benchmarks/MallocBench/espresso/hack.c test-suite/trunk/MultiSource/Benchmarks/MallocBench/espresso/pair.c test-suite/trunk/MultiSource/Benchmarks/McCat/09-vor/splay.c test-suite/trunk/MultiSource/Benchmarks/McCat/09-vor/splay2.c Modified: test-suite/trunk/MultiSource/Applications/sgefa/blas.c URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/MultiSource/Applications/sgefa/blas.c?rev=108202&r1=108201&r2=108202&view=diff ============================================================================== --- test-suite/trunk/MultiSource/Applications/sgefa/blas.c (original) +++ test-suite/trunk/MultiSource/Applications/sgefa/blas.c Mon Jul 12 17:30:06 2010 @@ -431,12 +431,12 @@ if( incx < 0 ) sx += (-n+1)*incx; for( i=0; ipd[k]; ilabel == NIL(char *) || PLA->label[0] == NIL(char)) - return; + return 0; /* try to find a binary variable named "DONT_CARE" */ var = -1; @@ -23,7 +23,7 @@ } } if (var == -1) { - return; + return 0; } /* form the cofactor cubes for the don't-care variable */ @@ -408,7 +408,7 @@ /* hack with the labels */ if ((oldlabel = PLA->label) == NIL(char *)) - return; + return 0; PLA->label = ALLOC(char *, new_size); for(i = 0; i < new_size; i++) { PLA->label[i] = NIL(char); Modified: test-suite/trunk/MultiSource/Benchmarks/MallocBench/espresso/pair.c URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/MultiSource/Benchmarks/MallocBench/espresso/pair.c?rev=108202&r1=108201&r2=108202&view=diff ============================================================================== --- test-suite/trunk/MultiSource/Benchmarks/MallocBench/espresso/pair.c (original) +++ test-suite/trunk/MultiSource/Benchmarks/MallocBench/espresso/pair.c Mon Jul 12 17:30:06 2010 @@ -585,7 +585,7 @@ if (set_ord(candidate) < 2) { (*action)(pair); - return; + return 0; } recur_pair = pair_save(pair, n); Modified: test-suite/trunk/MultiSource/Benchmarks/McCat/09-vor/splay.c URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/MultiSource/Benchmarks/McCat/09-vor/splay.c?rev=108202&r1=108201&r2=108202&view=diff ============================================================================== --- test-suite/trunk/MultiSource/Benchmarks/McCat/09-vor/splay.c (original) +++ test-suite/trunk/MultiSource/Benchmarks/McCat/09-vor/splay.c Mon Jul 12 17:30:06 2010 @@ -129,7 +129,7 @@ { splay(root,temp->element.key); if (temp->element.key == (*root)->element.key) - return; + return 0; else if ((*root)->element.key > temp->element.key) { temp->left = (*root)->left; if (temp->left != NULL) temp->left->father = temp; @@ -165,7 +165,7 @@ else { printf("No elements in tree! [delete_min]\n"); - return; + return min_elm.p; } return min_elm.p; } Modified: test-suite/trunk/MultiSource/Benchmarks/McCat/09-vor/splay2.c URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/MultiSource/Benchmarks/McCat/09-vor/splay2.c?rev=108202&r1=108201&r2=108202&view=diff ============================================================================== --- test-suite/trunk/MultiSource/Benchmarks/McCat/09-vor/splay2.c (original) +++ test-suite/trunk/MultiSource/Benchmarks/McCat/09-vor/splay2.c Mon Jul 12 17:30:06 2010 @@ -204,7 +204,7 @@ free(max_node); } else { printf("No elements in tree! [CHdelete_max]\n"); - return; } + return 0; } return max_elm.point; } From wilsons at start.ca Mon Jul 12 17:36:08 2010 From: wilsons at start.ca (Stephen Wilson) Date: Mon, 12 Jul 2010 22:36:08 -0000 Subject: [llvm-commits] [llvm] r108203 - /llvm/trunk/include/llvm/Support/ELF.h Message-ID: <20100712223608.AC7142A6C12C@llvm.org> Author: wilsons Date: Mon Jul 12 17:36:08 2010 New Revision: 108203 URL: http://llvm.org/viewvc/llvm-project?rev=108203&view=rev Log: Simple format/style fixes. Modified: llvm/trunk/include/llvm/Support/ELF.h Modified: llvm/trunk/include/llvm/Support/ELF.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ELF.h?rev=108203&r1=108202&r2=108203&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/ELF.h (original) +++ llvm/trunk/include/llvm/Support/ELF.h Mon Jul 12 17:36:08 2010 @@ -63,10 +63,10 @@ Elf32_Half e_shnum; // Number of entries in the section header table Elf32_Half e_shstrndx; // Sect hdr table index of sect name string table bool checkMagic() const { - return (memcmp (e_ident, ElfMagic, strlen (ElfMagic))) == 0; + return (memcmp(e_ident, ElfMagic, strlen(ElfMagic))) == 0; } - unsigned char getFileClass () const { return e_ident[4]; } - unsigned char getDataEncoding () { return e_ident[5]; } + unsigned char getFileClass() const { return e_ident[4]; } + unsigned char getDataEncoding() { return e_ident[5]; } }; // 64-bit ELF header. Fields are the same as for ELF32, but with different @@ -273,11 +273,11 @@ // These accessors and mutators correspond to the ELF32_ST_BIND, // ELF32_ST_TYPE, and ELF32_ST_INFO macros defined in the ELF specification: - unsigned char getBinding () const { return st_info >> 4; } - unsigned char getType () const { return st_info & 0x0f; } - void setBinding (unsigned char b) { setBindingAndType (b, getType ()); } - void setType (unsigned char t) { setBindingAndType (getBinding (), t); } - void setBindingAndType (unsigned char b, unsigned char t) { + unsigned char getBinding() const { return st_info >> 4; } + unsigned char getType() const { return st_info & 0x0f; } + void setBinding(unsigned char b) { setBindingAndType(b, getType()); } + void setType(unsigned char t) { setBindingAndType(getBinding(), t); } + void setBindingAndType(unsigned char b, unsigned char t) { st_info = (b << 4) + (t & 0x0f); } }; @@ -309,11 +309,11 @@ // These accessors and mutators correspond to the ELF32_R_SYM, ELF32_R_TYPE, // and ELF32_R_INFO macros defined in the ELF specification: - Elf32_Word getSymbol () const { return (r_info >> 8); } - unsigned char getType () const { return (unsigned char) (r_info & 0x0ff); } - void setSymbol (Elf32_Word s) { setSymbolAndType (s, getType ()); } - void setType (unsigned char t) { setSymbolAndType (getSymbol(), t); } - void setSymbolAndType (Elf32_Word s, unsigned char t) { + Elf32_Word getSymbol() const { return (r_info >> 8); } + unsigned char getType() const { return (unsigned char) (r_info & 0x0ff); } + void setSymbol(Elf32_Word s) { setSymbolAndType(s, getType()); } + void setType(unsigned char t) { setSymbolAndType(getSymbol(), t); } + void setSymbolAndType(Elf32_Word s, unsigned char t) { r_info = (s << 8) + t; }; }; @@ -326,11 +326,11 @@ // These accessors and mutators correspond to the ELF32_R_SYM, ELF32_R_TYPE, // and ELF32_R_INFO macros defined in the ELF specification: - Elf32_Word getSymbol () const { return (r_info >> 8); } - unsigned char getType () const { return (unsigned char) (r_info & 0x0ff); } - void setSymbol (Elf32_Word s) { setSymbolAndType (s, getType ()); } - void setType (unsigned char t) { setSymbolAndType (getSymbol(), t); } - void setSymbolAndType (Elf32_Word s, unsigned char t) { + Elf32_Word getSymbol() const { return (r_info >> 8); } + unsigned char getType() const { return (unsigned char) (r_info & 0x0ff); } + void setSymbol(Elf32_Word s) { setSymbolAndType(s, getType()); } + void setType(unsigned char t) { setSymbolAndType(getSymbol(), t); } + void setSymbolAndType(Elf32_Word s, unsigned char t) { r_info = (s << 8) + t; }; }; @@ -342,13 +342,13 @@ // These accessors and mutators correspond to the ELF64_R_SYM, ELF64_R_TYPE, // and ELF64_R_INFO macros defined in the ELF specification: - Elf64_Xword getSymbol () const { return (r_info >> 32); } - unsigned char getType () const { + Elf64_Xword getSymbol() const { return (r_info >> 32); } + unsigned char getType() const { return (unsigned char) (r_info & 0xffffffffL); } - void setSymbol (Elf32_Word s) { setSymbolAndType (s, getType ()); } - void setType (unsigned char t) { setSymbolAndType (getSymbol(), t); } - void setSymbolAndType (Elf64_Xword s, unsigned char t) { + void setSymbol(Elf32_Word s) { setSymbolAndType(s, getType()); } + void setType(unsigned char t) { setSymbolAndType(getSymbol(), t); } + void setSymbolAndType(Elf64_Xword s, unsigned char t) { r_info = (s << 32) + (t&0xffffffffL); }; }; @@ -361,13 +361,13 @@ // These accessors and mutators correspond to the ELF64_R_SYM, ELF64_R_TYPE, // and ELF64_R_INFO macros defined in the ELF specification: - Elf64_Xword getSymbol () const { return (r_info >> 32); } - unsigned char getType () const { + Elf64_Xword getSymbol() const { return (r_info >> 32); } + unsigned char getType() const { return (unsigned char) (r_info & 0xffffffffL); } - void setSymbol (Elf64_Xword s) { setSymbolAndType (s, getType ()); } - void setType (unsigned char t) { setSymbolAndType (getSymbol(), t); } - void setSymbolAndType (Elf64_Xword s, unsigned char t) { + void setSymbol(Elf64_Xword s) { setSymbolAndType(s, getType()); } + void setType(unsigned char t) { setSymbolAndType(getSymbol(), t); } + void setSymbolAndType(Elf64_Xword s, unsigned char t) { r_info = (s << 32) + (t&0xffffffffL); }; }; From stoklund at 2pi.dk Mon Jul 12 17:37:24 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 12 Jul 2010 15:37:24 -0700 Subject: [llvm-commits] [llvm] r108109 - /llvm/trunk/lib/CodeGen/MachineLICM.cpp In-Reply-To: <3434519D-9F54-4516-A09A-FAE224A0E8C5@nondot.org> References: <20100712000035.393982A6C12C@llvm.org> <5470C984-D21B-4C3F-860C-D7506AFBFAAB@apple.com> <3434519D-9F54-4516-A09A-FAE224A0E8C5@nondot.org> Message-ID: <01AEDF63-186E-4CA3-BCA9-0686BFC66E3A@2pi.dk> On Jul 12, 2010, at 2:44 PM, Chris Lattner wrote: > > On Jul 12, 2010, at 11:22 AM, Evan Cheng wrote: > >> >> On Jul 12, 2010, at 8:29 AM, Chris Lattner wrote: >> >>> >>> On Jul 12, 2010, at 12:57 AM, Evan Cheng wrote: >>> >>>>> change machinelicm to use MachineInstr::isSafeToMove. No >>>>> intended functionality change. >>>>> >>>>> The avoidance of hoistiing implicitdef seems wrong though. >>>> >>>> It's not. We want to avoid creating implicitdef with no trivial live intervals. The trivial ones will be converted to undef machine operands which do not take up registers. >>> >>> Why? The register allocator treats them specially just so they don't use a register (according to Jakob). >> >> No, that's not correct. The ones with trivial live intervals, i.e. defined and used in the same BB, are converted to undef operands. These do not take up registers. The ones that have uses outside of the definition block *may* not be eliminated. Those will take up registers. > > Jakob, didn't you just tell me that the RA turned them into trivial short live ranges? I thought they were. > If not, isn't that the right thing to do? I can't imagine why we would want to keep IMPLICIT_DEFs around, but I can imagine ProcessImplicitDefs getting confused because the code is not SSA. From bruno.cardoso at gmail.com Mon Jul 12 17:41:32 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Mon, 12 Jul 2010 22:41:32 -0000 Subject: [llvm-commits] [llvm] r108204 - /llvm/trunk/lib/Target/X86/X86InstrSSE.td Message-ID: <20100712224132.F37792A6C12C@llvm.org> Author: bruno Date: Mon Jul 12 17:41:32 2010 New Revision: 108204 URL: http://llvm.org/viewvc/llvm-project?rev=108204&view=rev Log: More refactoring of basic SSE arith instructions. Open room for 256-bit instructions Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=108204&r1=108203&r2=108204&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Jul 12 17:41:32 2010 @@ -393,75 +393,103 @@ /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class multiclass sse12_fp_scalar opc, string OpcodeStr, SDNode OpNode, - RegisterClass RC, X86MemOperand x86memop> { + RegisterClass RC, X86MemOperand x86memop, + bit Is2Addr = 1> { let isCommutable = 1 in { def rr : SI; + !if(Is2Addr, + !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), + !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")), + [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>; } def rm : SI; + !if(Is2Addr, + !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), + !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")), + [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>; } /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class multiclass sse12_fp_scalar_int opc, string OpcodeStr, RegisterClass RC, - string asm, string SSEVer, string FPSizeStr, - Operand memopr, ComplexPattern mem_cpat> { + string asm, string SSEVer, string FPSizeStr, + Operand memopr, ComplexPattern mem_cpat, + bit Is2Addr = 1> { def rr_Int : SI("int_x86_sse", - !strconcat(SSEVer, !strconcat("_", - !strconcat(OpcodeStr, FPSizeStr)))) - RC:$src1, RC:$src2))]>; + !if(Is2Addr, + !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"), + !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")), + [(set RC:$dst, (!nameconcat("int_x86_sse", + !strconcat(SSEVer, !strconcat("_", + !strconcat(OpcodeStr, FPSizeStr)))) + RC:$src1, RC:$src2))]>; def rm_Int : SI("int_x86_sse", - !strconcat(SSEVer, !strconcat("_", - !strconcat(OpcodeStr, FPSizeStr)))) - RC:$src1, mem_cpat:$src2))]>; + !if(Is2Addr, + !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"), + !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")), + [(set RC:$dst, (!nameconcat("int_x86_sse", + !strconcat(SSEVer, !strconcat("_", + !strconcat(OpcodeStr, FPSizeStr)))) + RC:$src1, mem_cpat:$src2))]>; } /// sse12_fp_packed - SSE 1 & 2 packed instructions class multiclass sse12_fp_packed opc, string OpcodeStr, SDNode OpNode, RegisterClass RC, ValueType vt, X86MemOperand x86memop, PatFrag mem_frag, - Domain d, bit MayLoad = 0> { + Domain d, bit Is2Addr = 1> { let isCommutable = 1 in def rr : PI; - let mayLoad = MayLoad in + !if(Is2Addr, + !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), + !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")), + [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], d>; + let mayLoad = 1 in def rm : PI; + !if(Is2Addr, + !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), + !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")), + [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))], d>; } /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class multiclass sse12_fp_packed_logical_rm opc, RegisterClass RC, Domain d, string OpcodeStr, X86MemOperand x86memop, - list pat_rr, list pat_rm> { + list pat_rr, list pat_rm, + bit Is2Addr = 1> { let isCommutable = 1 in - def rr : PI; - def rm : PI; + def rr : PI; + def rm : PI; } /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class multiclass sse12_fp_packed_int opc, string OpcodeStr, RegisterClass RC, - string asm, string SSEVer, string FPSizeStr, - X86MemOperand x86memop, PatFrag mem_frag, - Domain d> { + string asm, string SSEVer, string FPSizeStr, + X86MemOperand x86memop, PatFrag mem_frag, + Domain d, bit Is2Addr = 1> { def rr_Int : PI("int_x86_sse", - !strconcat(SSEVer, !strconcat("_", - !strconcat(OpcodeStr, FPSizeStr)))) - RC:$src1, RC:$src2))], d>; - def rm_Int : PI("int_x86_sse", - !strconcat(SSEVer, !strconcat("_", - !strconcat(OpcodeStr, FPSizeStr)))) - RC:$src1, (mem_frag addr:$src2)))], d>; + !if(Is2Addr, + !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"), + !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")), + [(set RC:$dst, (!nameconcat("int_x86_sse", + !strconcat(SSEVer, !strconcat("_", + !strconcat(OpcodeStr, FPSizeStr)))) + RC:$src1, RC:$src2))], d>; + def rm_Int : PI("int_x86_sse", + !strconcat(SSEVer, !strconcat("_", + !strconcat(OpcodeStr, FPSizeStr)))) + RC:$src1, (mem_frag addr:$src2)))], d>; } //===----------------------------------------------------------------------===// @@ -1652,36 +1680,33 @@ /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops /// multiclass sse12_fp_alias_pack_logical opc, string OpcodeStr, - SDNode OpNode, bit MayLoad = 0> { + SDNode OpNode> { let isAsmParserOnly = 1 in { - defm V#NAME#PS : sse12_fp_packed, VEX_4V; - - defm V#NAME#PD : sse12_fp_packed, OpSize, - VEX_4V; + defm V#NAME#PS : sse12_fp_packed, VEX_4V; + + defm V#NAME#PD : sse12_fp_packed, OpSize, VEX_4V; } let Constraints = "$src1 = $dst" in { - defm PS : sse12_fp_packed, TB; - - defm PD : sse12_fp_packed, TB, OpSize; + defm PS : sse12_fp_packed, TB; + + defm PD : sse12_fp_packed, TB, OpSize; } } // Alias bitwise logical operations using SSE logical ops on packed FP values. -defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>; -defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>; -defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>; +let mayLoad = 0 in { + defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>; + defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>; + defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>; +} let neverHasSideEffects = 1, Pattern = [], isCommutable = 0 in - defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef, 1>; + defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef>; /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops /// @@ -1690,31 +1715,29 @@ list> Pattern = []> { let isAsmParserOnly = 1 in { defm V#NAME#PS : sse12_fp_packed_logical_rm, + (memopv2i64 addr:$src2)))]), 0>, VEX_4V; defm V#NAME#PD : sse12_fp_packed_logical_rm, + (memopv2i64 addr:$src2)))]), 0>, OpSize, VEX_4V; } let Constraints = "$src1 = $dst" in { defm PS : sse12_fp_packed_logical_rm, TB; defm PD : sse12_fp_packed_logical_rm opc, string OpcodeStr, - SDNode OpNode> { - - let isAsmParserOnly = 1 in { - defm V#NAME#SS : sse12_fp_scalar, XS, VEX_4V; - - defm V#NAME#SD : sse12_fp_scalar, XD, VEX_4V; - - defm V#NAME#PS : sse12_fp_packed, - VEX_4V; +multiclass basic_sse12_fp_binop_s opc, string OpcodeStr, SDNode OpNode, + bit Is2Addr = 1> { + defm SS : sse12_fp_scalar, XS; + defm SD : sse12_fp_scalar, XD; +} - defm V#NAME#PD : sse12_fp_packed, - OpSize, VEX_4V; - - defm V#NAME#SS : sse12_fp_scalar_int, XS, VEX_4V; - - defm V#NAME#SD : sse12_fp_scalar_int, XD, VEX_4V; +multiclass basic_sse12_fp_binop_p opc, string OpcodeStr, SDNode OpNode, + bit Is2Addr = 1> { + let mayLoad = 0 in { + defm PS : sse12_fp_packed, TB; + defm PD : sse12_fp_packed, TB, OpSize; } +} - let Constraints = "$src1 = $dst" in { - defm SS : sse12_fp_scalar, XS; - - defm SD : sse12_fp_scalar, XD; - - defm PS : sse12_fp_packed, TB; - - defm PD : sse12_fp_packed, TB, OpSize; - - defm SS : sse12_fp_scalar_int, XS; - - defm SD : sse12_fp_scalar_int, XD; - } +multiclass basic_sse12_fp_binop_s_int opc, string OpcodeStr, + bit Is2Addr = 1> { + defm SS : sse12_fp_scalar_int, XS; + defm SD : sse12_fp_scalar_int, XD; +} + +multiclass basic_sse12_fp_binop_p_int opc, string OpcodeStr, + bit Is2Addr = 1> { + defm PS : sse12_fp_packed_int, TB; + + defm PD : sse12_fp_packed_int, TB, OpSize; } // Arithmetic instructions -defm ADD : basic_sse12_fp_binop_rm<0x58, "add", fadd>; -defm MUL : basic_sse12_fp_binop_rm<0x59, "mul", fmul>; +let isAsmParserOnly = 1, Predicates = [HasAVX] in { + defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, 0>, + basic_sse12_fp_binop_p<0x58, "add", fadd, 0>, VEX_4V; + defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, 0>, + basic_sse12_fp_binop_p<0x59, "mul", fmul, 0>, VEX_4V; -let isCommutable = 0 in { - defm SUB : basic_sse12_fp_binop_rm<0x5C, "sub", fsub>; - defm DIV : basic_sse12_fp_binop_rm<0x5E, "div", fdiv>; + let isCommutable = 0 in { + defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, 0>, + basic_sse12_fp_binop_p<0x5C, "sub", fsub, 0>, VEX_4V; + defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, 0>, + basic_sse12_fp_binop_p<0x5E, "div", fdiv, 0>, VEX_4V; + defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, 0>, + basic_sse12_fp_binop_p<0x5F, "max", X86fmax, 0>, VEX_4V; + defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, 0>, + basic_sse12_fp_binop_p<0x5D, "min", X86fmin, 0>, VEX_4V; + } } -/// sse12_fp_binop_rm - Other SSE 1 & 2 binops -/// -/// This multiclass is like basic_sse12_fp_binop_rm, with the addition of -/// instructions for a full-vector intrinsic form. Operations that map -/// onto C operators don't use this form since they just use the plain -/// vector form instead of having a separate vector intrinsic form. -/// -multiclass sse12_fp_binop_rm opc, string OpcodeStr, - SDNode OpNode> { - - let isAsmParserOnly = 1 in { - // Scalar operation, reg+reg. - defm V#NAME#SS : sse12_fp_scalar, XS, VEX_4V; - - defm V#NAME#SD : sse12_fp_scalar, XD, VEX_4V; - - defm V#NAME#PS : sse12_fp_packed, - VEX_4V; - - defm V#NAME#PD : sse12_fp_packed, - OpSize, VEX_4V; - - defm V#NAME#SS : sse12_fp_scalar_int, XS, VEX_4V; - - defm V#NAME#SD : sse12_fp_scalar_int, XD, VEX_4V; - - defm V#NAME#PS : sse12_fp_packed_int, VEX_4V; - - defm V#NAME#PD : sse12_fp_packed_int, OpSize, - VEX_4V; - } +let Constraints = "$src1 = $dst" in { + defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd>, + basic_sse12_fp_binop_p<0x58, "add", fadd>, + basic_sse12_fp_binop_s_int<0x58, "add">; + defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul>, + basic_sse12_fp_binop_p<0x59, "mul", fmul>, + basic_sse12_fp_binop_s_int<0x59, "mul">; - let Constraints = "$src1 = $dst" in { - // Scalar operation, reg+reg. - defm SS : sse12_fp_scalar, XS; - defm SD : sse12_fp_scalar, XD; - defm PS : sse12_fp_packed, TB; - - defm PD : sse12_fp_packed, TB, OpSize; - - defm SS : sse12_fp_scalar_int, XS; - - defm SD : sse12_fp_scalar_int, XD; - - defm PS : sse12_fp_packed_int, TB; - - defm PD : sse12_fp_packed_int, TB, OpSize; + let isCommutable = 0 in { + defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub>, + basic_sse12_fp_binop_p<0x5C, "sub", fsub>, + basic_sse12_fp_binop_s_int<0x5C, "sub">; + defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv>, + basic_sse12_fp_binop_p<0x5E, "div", fdiv>, + basic_sse12_fp_binop_s_int<0x5E, "div">; + defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax>, + basic_sse12_fp_binop_p<0x5F, "max", X86fmax>, + basic_sse12_fp_binop_s_int<0x5F, "max">, + basic_sse12_fp_binop_p_int<0x5F, "max">; + defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin>, + basic_sse12_fp_binop_p<0x5D, "min", X86fmin>, + basic_sse12_fp_binop_s_int<0x5D, "min">, + basic_sse12_fp_binop_p_int<0x5D, "min">; } } -let isCommutable = 0 in { - defm MAX : sse12_fp_binop_rm<0x5F, "max", X86fmax>; - defm MIN : sse12_fp_binop_rm<0x5D, "min", X86fmin>; -} - /// Unop Arithmetic /// In addition, we also have a special variant of the scalar form here to /// represent the associated intrinsic operation. This form is unlike the From echristo at apple.com Mon Jul 12 18:02:56 2010 From: echristo at apple.com (Eric Christopher) Date: Mon, 12 Jul 2010 23:02:56 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r108206 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Message-ID: <20100712230256.C6C322A6C12C@llvm.org> Author: echristo Date: Mon Jul 12 18:02:56 2010 New Revision: 108206 URL: http://llvm.org/viewvc/llvm-project?rev=108206&view=rev Log: Make sure that the requested alignment isn't greater than the stack alignment for a vla - we won't adhere to it anyways so make it an error. Fixes rdar://7506902 Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=108206&r1=108205&r2=108206&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Mon Jul 12 18:02:56 2010 @@ -39,6 +39,7 @@ #include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetFrameInfo.h" #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/DenseMap.h" @@ -1755,6 +1756,15 @@ if (isGimpleTemporary(decl)) return; + /* If this is a vla type and we requested an alignment greater than the stack + alignment, error out since we're not going to dynamically realign + variable length array allocations. We're placing this here instead of + later in case it's a relatively unused variable. */ + if (TREE_CODE (type) == ARRAY_TYPE && C_TYPE_VARIABLE_SIZE (type) && + DECL_ALIGN(decl)/8u > TheTarget->getFrameInfo()->getStackAlignment()) + error ("alignment for %q+D is greater than the stack alignment, " + "we cannot guarantee the alignment.", decl); + // If this is just the rotten husk of a variable that the gimplifier // eliminated all uses of, but is preserving for debug info, ignore it. if (TREE_CODE(decl) == VAR_DECL && DECL_VALUE_EXPR(decl)) From bruno.cardoso at gmail.com Mon Jul 12 18:04:15 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Mon, 12 Jul 2010 23:04:15 -0000 Subject: [llvm-commits] [llvm] r108207 - in /llvm/trunk: lib/Target/X86/X86InstrSSE.td test/MC/AsmParser/X86/x86_32-encoding.s test/MC/AsmParser/X86/x86_64-encoding.s Message-ID: <20100712230415.AAAFF2A6C12C@llvm.org> Author: bruno Date: Mon Jul 12 18:04:15 2010 New Revision: 108207 URL: http://llvm.org/viewvc/llvm-project?rev=108207&view=rev Log: Add AVX 256 binary arithmetic instructions Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=108207&r1=108206&r2=108207&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Jul 12 18:04:15 2010 @@ -1810,6 +1810,16 @@ } } +multiclass basic_sse12_fp_binop_p_y opc, string OpcodeStr, + SDNode OpNode> { + let mayLoad = 0 in { + defm PSY : sse12_fp_packed, TB; + defm PDY : sse12_fp_packed, TB, OpSize; + } +} + multiclass basic_sse12_fp_binop_s_int opc, string OpcodeStr, bit Is2Addr = 1> { defm SS : sse12_fp_scalar_int, TB, OpSize; } -// Arithmetic instructions +// Binary Arithmetic instructions let isAsmParserOnly = 1, Predicates = [HasAVX] in { defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, 0>, - basic_sse12_fp_binop_p<0x58, "add", fadd, 0>, VEX_4V; + basic_sse12_fp_binop_p<0x58, "add", fadd, 0>, + basic_sse12_fp_binop_p_y<0x58, "add", fadd>, VEX_4V; defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, 0>, - basic_sse12_fp_binop_p<0x59, "mul", fmul, 0>, VEX_4V; + basic_sse12_fp_binop_p<0x59, "mul", fmul, 0>, + basic_sse12_fp_binop_p_y<0x59, "mul", fmul>, VEX_4V; let isCommutable = 0 in { defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, 0>, - basic_sse12_fp_binop_p<0x5C, "sub", fsub, 0>, VEX_4V; + basic_sse12_fp_binop_p<0x5C, "sub", fsub, 0>, + basic_sse12_fp_binop_p_y<0x5C, "sub", fsub>, VEX_4V; defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, 0>, - basic_sse12_fp_binop_p<0x5E, "div", fdiv, 0>, VEX_4V; + basic_sse12_fp_binop_p<0x5E, "div", fdiv, 0>, + basic_sse12_fp_binop_p_y<0x5E, "div", fdiv>, VEX_4V; defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, 0>, - basic_sse12_fp_binop_p<0x5F, "max", X86fmax, 0>, VEX_4V; + basic_sse12_fp_binop_p<0x5F, "max", X86fmax, 0>, + basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax>, VEX_4V; defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, 0>, - basic_sse12_fp_binop_p<0x5D, "min", X86fmin, 0>, VEX_4V; + basic_sse12_fp_binop_p<0x5D, "min", X86fmin, 0>, + basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin>, VEX_4V; } } Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s?rev=108207&r1=108206&r2=108207&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s Mon Jul 12 18:04:15 2010 @@ -12406,3 +12406,99 @@ // CHECK: encoding: [0xc5,0xf9,0x50,0xc2] vmovmskpd %xmm2, %eax +// CHECK: vmaxps %ymm2, %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x5f,0xf2] + vmaxps %ymm2, %ymm4, %ymm6 + +// CHECK: vmaxpd %ymm2, %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x5f,0xf2] + vmaxpd %ymm2, %ymm4, %ymm6 + +// CHECK: vminps %ymm2, %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x5d,0xf2] + vminps %ymm2, %ymm4, %ymm6 + +// CHECK: vminpd %ymm2, %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x5d,0xf2] + vminpd %ymm2, %ymm4, %ymm6 + +// CHECK: vsubps %ymm2, %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x5c,0xf2] + vsubps %ymm2, %ymm4, %ymm6 + +// CHECK: vsubpd %ymm2, %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x5c,0xf2] + vsubpd %ymm2, %ymm4, %ymm6 + +// CHECK: vdivps %ymm2, %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x5e,0xf2] + vdivps %ymm2, %ymm4, %ymm6 + +// CHECK: vdivpd %ymm2, %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x5e,0xf2] + vdivpd %ymm2, %ymm4, %ymm6 + +// CHECK: vaddps %ymm2, %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x58,0xf2] + vaddps %ymm2, %ymm4, %ymm6 + +// CHECK: vaddpd %ymm2, %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x58,0xf2] + vaddpd %ymm2, %ymm4, %ymm6 + +// CHECK: vmulps %ymm2, %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x59,0xf2] + vmulps %ymm2, %ymm4, %ymm6 + +// CHECK: vmulpd %ymm2, %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x59,0xf2] + vmulpd %ymm2, %ymm4, %ymm6 + +// CHECK: vmaxps (%eax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x5f,0x30] + vmaxps (%eax), %ymm4, %ymm6 + +// CHECK: vmaxpd (%eax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x5f,0x30] + vmaxpd (%eax), %ymm4, %ymm6 + +// CHECK: vminps (%eax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x5d,0x30] + vminps (%eax), %ymm4, %ymm6 + +// CHECK: vminpd (%eax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x5d,0x30] + vminpd (%eax), %ymm4, %ymm6 + +// CHECK: vsubps (%eax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x5c,0x30] + vsubps (%eax), %ymm4, %ymm6 + +// CHECK: vsubpd (%eax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x5c,0x30] + vsubpd (%eax), %ymm4, %ymm6 + +// CHECK: vdivps (%eax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x5e,0x30] + vdivps (%eax), %ymm4, %ymm6 + +// CHECK: vdivpd (%eax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x5e,0x30] + vdivpd (%eax), %ymm4, %ymm6 + +// CHECK: vaddps (%eax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x58,0x30] + vaddps (%eax), %ymm4, %ymm6 + +// CHECK: vaddpd (%eax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x58,0x30] + vaddpd (%eax), %ymm4, %ymm6 + +// CHECK: vmulps (%eax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x59,0x30] + vmulps (%eax), %ymm4, %ymm6 + +// CHECK: vmulpd (%eax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x59,0x30] + vmulpd (%eax), %ymm4, %ymm6 + Modified: llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s?rev=108207&r1=108206&r2=108207&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s Mon Jul 12 18:04:15 2010 @@ -2480,3 +2480,99 @@ // CHECK: encoding: [0xc4,0xc1,0x79,0x50,0xc4] vmovmskpd %xmm12, %eax +// CHECK: vmaxps %ymm12, %ymm4, %ymm6 +// CHECK: encoding: [0xc4,0xc1,0x5c,0x5f,0xf4] + vmaxps %ymm12, %ymm4, %ymm6 + +// CHECK: vmaxpd %ymm12, %ymm4, %ymm6 +// CHECK: encoding: [0xc4,0xc1,0x5d,0x5f,0xf4] + vmaxpd %ymm12, %ymm4, %ymm6 + +// CHECK: vminps %ymm12, %ymm4, %ymm6 +// CHECK: encoding: [0xc4,0xc1,0x5c,0x5d,0xf4] + vminps %ymm12, %ymm4, %ymm6 + +// CHECK: vminpd %ymm12, %ymm4, %ymm6 +// CHECK: encoding: [0xc4,0xc1,0x5d,0x5d,0xf4] + vminpd %ymm12, %ymm4, %ymm6 + +// CHECK: vsubps %ymm12, %ymm4, %ymm6 +// CHECK: encoding: [0xc4,0xc1,0x5c,0x5c,0xf4] + vsubps %ymm12, %ymm4, %ymm6 + +// CHECK: vsubpd %ymm12, %ymm4, %ymm6 +// CHECK: encoding: [0xc4,0xc1,0x5d,0x5c,0xf4] + vsubpd %ymm12, %ymm4, %ymm6 + +// CHECK: vdivps %ymm12, %ymm4, %ymm6 +// CHECK: encoding: [0xc4,0xc1,0x5c,0x5e,0xf4] + vdivps %ymm12, %ymm4, %ymm6 + +// CHECK: vdivpd %ymm12, %ymm4, %ymm6 +// CHECK: encoding: [0xc4,0xc1,0x5d,0x5e,0xf4] + vdivpd %ymm12, %ymm4, %ymm6 + +// CHECK: vaddps %ymm12, %ymm4, %ymm6 +// CHECK: encoding: [0xc4,0xc1,0x5c,0x58,0xf4] + vaddps %ymm12, %ymm4, %ymm6 + +// CHECK: vaddpd %ymm12, %ymm4, %ymm6 +// CHECK: encoding: [0xc4,0xc1,0x5d,0x58,0xf4] + vaddpd %ymm12, %ymm4, %ymm6 + +// CHECK: vmulps %ymm12, %ymm4, %ymm6 +// CHECK: encoding: [0xc4,0xc1,0x5c,0x59,0xf4] + vmulps %ymm12, %ymm4, %ymm6 + +// CHECK: vmulpd %ymm12, %ymm4, %ymm6 +// CHECK: encoding: [0xc4,0xc1,0x5d,0x59,0xf4] + vmulpd %ymm12, %ymm4, %ymm6 + +// CHECK: vmaxps (%rax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x5f,0x30] + vmaxps (%rax), %ymm4, %ymm6 + +// CHECK: vmaxpd (%rax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x5f,0x30] + vmaxpd (%rax), %ymm4, %ymm6 + +// CHECK: vminps (%rax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x5d,0x30] + vminps (%rax), %ymm4, %ymm6 + +// CHECK: vminpd (%rax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x5d,0x30] + vminpd (%rax), %ymm4, %ymm6 + +// CHECK: vsubps (%rax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x5c,0x30] + vsubps (%rax), %ymm4, %ymm6 + +// CHECK: vsubpd (%rax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x5c,0x30] + vsubpd (%rax), %ymm4, %ymm6 + +// CHECK: vdivps (%rax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x5e,0x30] + vdivps (%rax), %ymm4, %ymm6 + +// CHECK: vdivpd (%rax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x5e,0x30] + vdivpd (%rax), %ymm4, %ymm6 + +// CHECK: vaddps (%rax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x58,0x30] + vaddps (%rax), %ymm4, %ymm6 + +// CHECK: vaddpd (%rax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x58,0x30] + vaddpd (%rax), %ymm4, %ymm6 + +// CHECK: vmulps (%rax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x59,0x30] + vmulps (%rax), %ymm4, %ymm6 + +// CHECK: vmulpd (%rax), %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x59,0x30] + vmulpd (%rax), %ymm4, %ymm6 + From wdietz2 at illinois.edu Mon Jul 12 18:22:37 2010 From: wdietz2 at illinois.edu (Will Dietz) Date: Mon, 12 Jul 2010 23:22:37 -0000 Subject: [llvm-commits] [poolalloc] r108211 - /poolalloc/trunk/test/pa/regression/2010-07-09-ArgAttrMismatch.ll Message-ID: <20100712232237.6A30B2A6C12C@llvm.org> Author: wdietz2 Date: Mon Jul 12 18:22:37 2010 New Revision: 108211 URL: http://llvm.org/viewvc/llvm-project?rev=108211&view=rev Log: In PoolAlloc tests, until we remove always-on debug prints to stderr, tests should allow/expect "Pool Allocating.*nodes!" message. Modified: poolalloc/trunk/test/pa/regression/2010-07-09-ArgAttrMismatch.ll Modified: poolalloc/trunk/test/pa/regression/2010-07-09-ArgAttrMismatch.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/pa/regression/2010-07-09-ArgAttrMismatch.ll?rev=108211&r1=108210&r2=108211&view=diff ============================================================================== --- poolalloc/trunk/test/pa/regression/2010-07-09-ArgAttrMismatch.ll (original) +++ poolalloc/trunk/test/pa/regression/2010-07-09-ArgAttrMismatch.ll Mon Jul 12 18:22:37 2010 @@ -1,4 +1,4 @@ -;RUN: paopt %s -poolalloc -disable-output +;RUN: paopt %s -poolalloc -disable-output |& grep "Pool allocating.*nodes!" target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" From greened at obbligato.org Mon Jul 12 18:41:28 2010 From: greened at obbligato.org (David Greene) Date: Mon, 12 Jul 2010 23:41:28 -0000 Subject: [llvm-commits] [llvm] r108213 - in /llvm/trunk/lib/Target/X86: X86InstrFragmentsSIMD.td X86InstrSSE.td Message-ID: <20100712234128.BA9692A6C12C@llvm.org> Author: greened Date: Mon Jul 12 18:41:28 2010 New Revision: 108213 URL: http://llvm.org/viewvc/llvm-project?rev=108213&view=rev Log: Move some SIMD fragment code into X86InstrFragmentsSIMD so that the utility classes can be used from multiple files. This will aid transitioning to a new refactored x86 SIMD specification. Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=108213&r1=108212&r2=108213&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Mon Jul 12 18:41:28 2010 @@ -60,3 +60,339 @@ (vector_shuffle node:$lhs, node:$rhs), [{ return X86::isPSHUFDMask(cast(N)); }], MMX_SHUFFLE_get_shuf_imm>; + +//===----------------------------------------------------------------------===// +// SSE specific DAG Nodes. +//===----------------------------------------------------------------------===// + +def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>, + SDTCisFP<0>, SDTCisInt<2> ]>; +def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, + SDTCisFP<1>, SDTCisVT<3, i8>]>; + +def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>; +def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>; +def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp, + [SDNPCommutative, SDNPAssociative]>; +def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp, + [SDNPCommutative, SDNPAssociative]>; +def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp, + [SDNPCommutative, SDNPAssociative]>; +def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>; +def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>; +def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>; +def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>; +def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>; +def X86pshufb : SDNode<"X86ISD::PSHUFB", + SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>, + SDTCisSameAs<0,2>]>>; +def X86pextrb : SDNode<"X86ISD::PEXTRB", + SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>; +def X86pextrw : SDNode<"X86ISD::PEXTRW", + SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>; +def X86pinsrb : SDNode<"X86ISD::PINSRB", + SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>, + SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>; +def X86pinsrw : SDNode<"X86ISD::PINSRW", + SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>, + SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>; +def X86insrtps : SDNode<"X86ISD::INSERTPS", + SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>, + SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>; +def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL", + SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>; +def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad, + [SDNPHasChain, SDNPMayLoad]>; +def X86vshl : SDNode<"X86ISD::VSHL", SDTIntShiftOp>; +def X86vshr : SDNode<"X86ISD::VSRL", SDTIntShiftOp>; +def X86cmpps : SDNode<"X86ISD::CMPPS", SDTX86VFCMP>; +def X86cmppd : SDNode<"X86ISD::CMPPD", SDTX86VFCMP>; +def X86pcmpeqb : SDNode<"X86ISD::PCMPEQB", SDTIntBinOp, [SDNPCommutative]>; +def X86pcmpeqw : SDNode<"X86ISD::PCMPEQW", SDTIntBinOp, [SDNPCommutative]>; +def X86pcmpeqd : SDNode<"X86ISD::PCMPEQD", SDTIntBinOp, [SDNPCommutative]>; +def X86pcmpeqq : SDNode<"X86ISD::PCMPEQQ", SDTIntBinOp, [SDNPCommutative]>; +def X86pcmpgtb : SDNode<"X86ISD::PCMPGTB", SDTIntBinOp>; +def X86pcmpgtw : SDNode<"X86ISD::PCMPGTW", SDTIntBinOp>; +def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>; +def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>; + +def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, + SDTCisVT<1, v4f32>, + SDTCisVT<2, v4f32>]>; +def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>; + +//===----------------------------------------------------------------------===// +// SSE Complex Patterns +//===----------------------------------------------------------------------===// + +// These are 'extloads' from a scalar to the low element of a vector, zeroing +// the top elements. These are used for the SSE 'ss' and 'sd' instruction +// forms. +def sse_load_f32 : ComplexPattern; +def sse_load_f64 : ComplexPattern; + +def ssmem : Operand { + let PrintMethod = "printf32mem"; + let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm); + let ParserMatchClass = X86MemAsmOperand; +} +def sdmem : Operand { + let PrintMethod = "printf64mem"; + let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm); + let ParserMatchClass = X86MemAsmOperand; +} + +//===----------------------------------------------------------------------===// +// SSE pattern fragments +//===----------------------------------------------------------------------===// + +def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>; +def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>; +def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>; +def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>; + +// FIXME: move this to a more appropriate place after all AVX is done. +def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>; +def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>; +def loadv8i32 : PatFrag<(ops node:$ptr), (v8i32 (load node:$ptr))>; +def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>; + +// Like 'store', but always requires vector alignment. +def alignedstore : PatFrag<(ops node:$val, node:$ptr), + (store node:$val, node:$ptr), [{ + return cast(N)->getAlignment() >= 16; +}]>; + +// Like 'load', but always requires vector alignment. +def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{ + return cast(N)->getAlignment() >= 16; +}]>; + +def alignedloadfsf32 : PatFrag<(ops node:$ptr), + (f32 (alignedload node:$ptr))>; +def alignedloadfsf64 : PatFrag<(ops node:$ptr), + (f64 (alignedload node:$ptr))>; +def alignedloadv4f32 : PatFrag<(ops node:$ptr), + (v4f32 (alignedload node:$ptr))>; +def alignedloadv2f64 : PatFrag<(ops node:$ptr), + (v2f64 (alignedload node:$ptr))>; +def alignedloadv4i32 : PatFrag<(ops node:$ptr), + (v4i32 (alignedload node:$ptr))>; +def alignedloadv2i64 : PatFrag<(ops node:$ptr), + (v2i64 (alignedload node:$ptr))>; + +// FIXME: move this to a more appropriate place after all AVX is done. +def alignedloadv8f32 : PatFrag<(ops node:$ptr), + (v8f32 (alignedload node:$ptr))>; +def alignedloadv4f64 : PatFrag<(ops node:$ptr), + (v4f64 (alignedload node:$ptr))>; +def alignedloadv8i32 : PatFrag<(ops node:$ptr), + (v8i32 (alignedload node:$ptr))>; +def alignedloadv4i64 : PatFrag<(ops node:$ptr), + (v4i64 (alignedload node:$ptr))>; + +// Like 'load', but uses special alignment checks suitable for use in +// memory operands in most SSE instructions, which are required to +// be naturally aligned on some targets but not on others. If the subtarget +// allows unaligned accesses, match any load, though this may require +// setting a feature bit in the processor (on startup, for example). +// Opteron 10h and later implement such a feature. +def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{ + return Subtarget->hasVectorUAMem() + || cast(N)->getAlignment() >= 16; +}]>; + +def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>; +def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>; +def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>; +def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>; +def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>; +def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>; +def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>; + +// FIXME: move this to a more appropriate place after all AVX is done. +def memopv8f32 : PatFrag<(ops node:$ptr), (v8f32 (memop node:$ptr))>; +def memopv4f64 : PatFrag<(ops node:$ptr), (v4f64 (memop node:$ptr))>; + +// SSSE3 uses MMX registers for some instructions. They aren't aligned on a +// 16-byte boundary. +// FIXME: 8 byte alignment for mmx reads is not required +def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{ + return cast(N)->getAlignment() >= 8; +}]>; + +def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>; +def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>; +def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>; +def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>; + +// MOVNT Support +// Like 'store', but requires the non-temporal bit to be set +def nontemporalstore : PatFrag<(ops node:$val, node:$ptr), + (st node:$val, node:$ptr), [{ + if (StoreSDNode *ST = dyn_cast(N)) + return ST->isNonTemporal(); + return false; +}]>; + +def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr), + (st node:$val, node:$ptr), [{ + if (StoreSDNode *ST = dyn_cast(N)) + return ST->isNonTemporal() && !ST->isTruncatingStore() && + ST->getAddressingMode() == ISD::UNINDEXED && + ST->getAlignment() >= 16; + return false; +}]>; + +def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr), + (st node:$val, node:$ptr), [{ + if (StoreSDNode *ST = dyn_cast(N)) + return ST->isNonTemporal() && + ST->getAlignment() < 16; + return false; +}]>; + +def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>; +def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>; +def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>; +def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>; +def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>; +def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>; + +def vzmovl_v2i64 : PatFrag<(ops node:$src), + (bitconvert (v2i64 (X86vzmovl + (v2i64 (scalar_to_vector (loadi64 node:$src))))))>; +def vzmovl_v4i32 : PatFrag<(ops node:$src), + (bitconvert (v4i32 (X86vzmovl + (v4i32 (scalar_to_vector (loadi32 node:$src))))))>; + +def vzload_v2i64 : PatFrag<(ops node:$src), + (bitconvert (v2i64 (X86vzload node:$src)))>; + + +def fp32imm0 : PatLeaf<(f32 fpimm), [{ + return N->isExactlyValue(+0.0); +}]>; + +// BYTE_imm - Transform bit immediates into byte immediates. +def BYTE_imm : SDNodeXForm> 3 + return getI32Imm(N->getZExtValue() >> 3); +}]>; + +// SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*, +// SHUFP* etc. imm. +def SHUFFLE_get_shuf_imm : SDNodeXForm; + +// SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to +// PSHUFHW imm. +def SHUFFLE_get_pshufhw_imm : SDNodeXForm; + +// SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to +// PSHUFLW imm. +def SHUFFLE_get_pshuflw_imm : SDNodeXForm; + +// SHUFFLE_get_palign_imm xform function: convert vector_shuffle mask to +// a PALIGNR imm. +def SHUFFLE_get_palign_imm : SDNodeXForm; + +def splat_lo : PatFrag<(ops node:$lhs, node:$rhs), + (vector_shuffle node:$lhs, node:$rhs), [{ + ShuffleVectorSDNode *SVOp = cast(N); + return SVOp->isSplat() && SVOp->getSplatIndex() == 0; +}]>; + +def movddup : PatFrag<(ops node:$lhs, node:$rhs), + (vector_shuffle node:$lhs, node:$rhs), [{ + return X86::isMOVDDUPMask(cast(N)); +}]>; + +def movhlps : PatFrag<(ops node:$lhs, node:$rhs), + (vector_shuffle node:$lhs, node:$rhs), [{ + return X86::isMOVHLPSMask(cast(N)); +}]>; + +def movhlps_undef : PatFrag<(ops node:$lhs, node:$rhs), + (vector_shuffle node:$lhs, node:$rhs), [{ + return X86::isMOVHLPS_v_undef_Mask(cast(N)); +}]>; + +def movlhps : PatFrag<(ops node:$lhs, node:$rhs), + (vector_shuffle node:$lhs, node:$rhs), [{ + return X86::isMOVLHPSMask(cast(N)); +}]>; + +def movlp : PatFrag<(ops node:$lhs, node:$rhs), + (vector_shuffle node:$lhs, node:$rhs), [{ + return X86::isMOVLPMask(cast(N)); +}]>; + +def movl : PatFrag<(ops node:$lhs, node:$rhs), + (vector_shuffle node:$lhs, node:$rhs), [{ + return X86::isMOVLMask(cast(N)); +}]>; + +def movshdup : PatFrag<(ops node:$lhs, node:$rhs), + (vector_shuffle node:$lhs, node:$rhs), [{ + return X86::isMOVSHDUPMask(cast(N)); +}]>; + +def movsldup : PatFrag<(ops node:$lhs, node:$rhs), + (vector_shuffle node:$lhs, node:$rhs), [{ + return X86::isMOVSLDUPMask(cast(N)); +}]>; + +def unpckl : PatFrag<(ops node:$lhs, node:$rhs), + (vector_shuffle node:$lhs, node:$rhs), [{ + return X86::isUNPCKLMask(cast(N)); +}]>; + +def unpckh : PatFrag<(ops node:$lhs, node:$rhs), + (vector_shuffle node:$lhs, node:$rhs), [{ + return X86::isUNPCKHMask(cast(N)); +}]>; + +def unpckl_undef : PatFrag<(ops node:$lhs, node:$rhs), + (vector_shuffle node:$lhs, node:$rhs), [{ + return X86::isUNPCKL_v_undef_Mask(cast(N)); +}]>; + +def unpckh_undef : PatFrag<(ops node:$lhs, node:$rhs), + (vector_shuffle node:$lhs, node:$rhs), [{ + return X86::isUNPCKH_v_undef_Mask(cast(N)); +}]>; + +def pshufd : PatFrag<(ops node:$lhs, node:$rhs), + (vector_shuffle node:$lhs, node:$rhs), [{ + return X86::isPSHUFDMask(cast(N)); +}], SHUFFLE_get_shuf_imm>; + +def shufp : PatFrag<(ops node:$lhs, node:$rhs), + (vector_shuffle node:$lhs, node:$rhs), [{ + return X86::isSHUFPMask(cast(N)); +}], SHUFFLE_get_shuf_imm>; + +def pshufhw : PatFrag<(ops node:$lhs, node:$rhs), + (vector_shuffle node:$lhs, node:$rhs), [{ + return X86::isPSHUFHWMask(cast(N)); +}], SHUFFLE_get_pshufhw_imm>; + +def pshuflw : PatFrag<(ops node:$lhs, node:$rhs), + (vector_shuffle node:$lhs, node:$rhs), [{ + return X86::isPSHUFLWMask(cast(N)); +}], SHUFFLE_get_pshuflw_imm>; + +def palign : PatFrag<(ops node:$lhs, node:$rhs), + (vector_shuffle node:$lhs, node:$rhs), [{ + return X86::isPALIGNRMask(cast(N)); +}], SHUFFLE_get_palign_imm>; Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=108213&r1=108212&r2=108213&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Jul 12 18:41:28 2010 @@ -15,342 +15,6 @@ //===----------------------------------------------------------------------===// -// SSE specific DAG Nodes. -//===----------------------------------------------------------------------===// - -def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>, - SDTCisFP<0>, SDTCisInt<2> ]>; -def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, - SDTCisFP<1>, SDTCisVT<3, i8>]>; - -def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>; -def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>; -def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp, - [SDNPCommutative, SDNPAssociative]>; -def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp, - [SDNPCommutative, SDNPAssociative]>; -def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp, - [SDNPCommutative, SDNPAssociative]>; -def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>; -def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>; -def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>; -def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>; -def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>; -def X86pshufb : SDNode<"X86ISD::PSHUFB", - SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>, - SDTCisSameAs<0,2>]>>; -def X86pextrb : SDNode<"X86ISD::PEXTRB", - SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>; -def X86pextrw : SDNode<"X86ISD::PEXTRW", - SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>; -def X86pinsrb : SDNode<"X86ISD::PINSRB", - SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>, - SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>; -def X86pinsrw : SDNode<"X86ISD::PINSRW", - SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>, - SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>; -def X86insrtps : SDNode<"X86ISD::INSERTPS", - SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>, - SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>; -def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL", - SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>; -def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad, - [SDNPHasChain, SDNPMayLoad]>; -def X86vshl : SDNode<"X86ISD::VSHL", SDTIntShiftOp>; -def X86vshr : SDNode<"X86ISD::VSRL", SDTIntShiftOp>; -def X86cmpps : SDNode<"X86ISD::CMPPS", SDTX86VFCMP>; -def X86cmppd : SDNode<"X86ISD::CMPPD", SDTX86VFCMP>; -def X86pcmpeqb : SDNode<"X86ISD::PCMPEQB", SDTIntBinOp, [SDNPCommutative]>; -def X86pcmpeqw : SDNode<"X86ISD::PCMPEQW", SDTIntBinOp, [SDNPCommutative]>; -def X86pcmpeqd : SDNode<"X86ISD::PCMPEQD", SDTIntBinOp, [SDNPCommutative]>; -def X86pcmpeqq : SDNode<"X86ISD::PCMPEQQ", SDTIntBinOp, [SDNPCommutative]>; -def X86pcmpgtb : SDNode<"X86ISD::PCMPGTB", SDTIntBinOp>; -def X86pcmpgtw : SDNode<"X86ISD::PCMPGTW", SDTIntBinOp>; -def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>; -def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>; - -def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, - SDTCisVT<1, v4f32>, - SDTCisVT<2, v4f32>]>; -def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>; - -//===----------------------------------------------------------------------===// -// SSE Complex Patterns -//===----------------------------------------------------------------------===// - -// These are 'extloads' from a scalar to the low element of a vector, zeroing -// the top elements. These are used for the SSE 'ss' and 'sd' instruction -// forms. -def sse_load_f32 : ComplexPattern; -def sse_load_f64 : ComplexPattern; - -def ssmem : Operand { - let PrintMethod = "printf32mem"; - let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm); - let ParserMatchClass = X86MemAsmOperand; -} -def sdmem : Operand { - let PrintMethod = "printf64mem"; - let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm); - let ParserMatchClass = X86MemAsmOperand; -} - -//===----------------------------------------------------------------------===// -// SSE pattern fragments -//===----------------------------------------------------------------------===// - -def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>; -def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>; -def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>; -def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>; - -// FIXME: move this to a more appropriate place after all AVX is done. -def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>; -def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>; -def loadv8i32 : PatFrag<(ops node:$ptr), (v8i32 (load node:$ptr))>; -def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>; - -// Like 'store', but always requires vector alignment. -def alignedstore : PatFrag<(ops node:$val, node:$ptr), - (store node:$val, node:$ptr), [{ - return cast(N)->getAlignment() >= 16; -}]>; - -// Like 'load', but always requires vector alignment. -def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{ - return cast(N)->getAlignment() >= 16; -}]>; - -def alignedloadfsf32 : PatFrag<(ops node:$ptr), - (f32 (alignedload node:$ptr))>; -def alignedloadfsf64 : PatFrag<(ops node:$ptr), - (f64 (alignedload node:$ptr))>; -def alignedloadv4f32 : PatFrag<(ops node:$ptr), - (v4f32 (alignedload node:$ptr))>; -def alignedloadv2f64 : PatFrag<(ops node:$ptr), - (v2f64 (alignedload node:$ptr))>; -def alignedloadv4i32 : PatFrag<(ops node:$ptr), - (v4i32 (alignedload node:$ptr))>; -def alignedloadv2i64 : PatFrag<(ops node:$ptr), - (v2i64 (alignedload node:$ptr))>; - -// FIXME: move this to a more appropriate place after all AVX is done. -def alignedloadv8f32 : PatFrag<(ops node:$ptr), - (v8f32 (alignedload node:$ptr))>; -def alignedloadv4f64 : PatFrag<(ops node:$ptr), - (v4f64 (alignedload node:$ptr))>; -def alignedloadv8i32 : PatFrag<(ops node:$ptr), - (v8i32 (alignedload node:$ptr))>; -def alignedloadv4i64 : PatFrag<(ops node:$ptr), - (v4i64 (alignedload node:$ptr))>; - -// Like 'load', but uses special alignment checks suitable for use in -// memory operands in most SSE instructions, which are required to -// be naturally aligned on some targets but not on others. If the subtarget -// allows unaligned accesses, match any load, though this may require -// setting a feature bit in the processor (on startup, for example). -// Opteron 10h and later implement such a feature. -def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{ - return Subtarget->hasVectorUAMem() - || cast(N)->getAlignment() >= 16; -}]>; - -def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>; -def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>; -def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>; -def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>; -def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>; -def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>; -def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>; - -// FIXME: move this to a more appropriate place after all AVX is done. -def memopv8f32 : PatFrag<(ops node:$ptr), (v8f32 (memop node:$ptr))>; -def memopv4f64 : PatFrag<(ops node:$ptr), (v4f64 (memop node:$ptr))>; - -// SSSE3 uses MMX registers for some instructions. They aren't aligned on a -// 16-byte boundary. -// FIXME: 8 byte alignment for mmx reads is not required -def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{ - return cast(N)->getAlignment() >= 8; -}]>; - -def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>; -def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>; -def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>; -def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>; - -// MOVNT Support -// Like 'store', but requires the non-temporal bit to be set -def nontemporalstore : PatFrag<(ops node:$val, node:$ptr), - (st node:$val, node:$ptr), [{ - if (StoreSDNode *ST = dyn_cast(N)) - return ST->isNonTemporal(); - return false; -}]>; - -def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr), - (st node:$val, node:$ptr), [{ - if (StoreSDNode *ST = dyn_cast(N)) - return ST->isNonTemporal() && !ST->isTruncatingStore() && - ST->getAddressingMode() == ISD::UNINDEXED && - ST->getAlignment() >= 16; - return false; -}]>; - -def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr), - (st node:$val, node:$ptr), [{ - if (StoreSDNode *ST = dyn_cast(N)) - return ST->isNonTemporal() && - ST->getAlignment() < 16; - return false; -}]>; - -def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>; -def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>; -def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>; -def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>; -def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>; -def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>; - -def vzmovl_v2i64 : PatFrag<(ops node:$src), - (bitconvert (v2i64 (X86vzmovl - (v2i64 (scalar_to_vector (loadi64 node:$src))))))>; -def vzmovl_v4i32 : PatFrag<(ops node:$src), - (bitconvert (v4i32 (X86vzmovl - (v4i32 (scalar_to_vector (loadi32 node:$src))))))>; - -def vzload_v2i64 : PatFrag<(ops node:$src), - (bitconvert (v2i64 (X86vzload node:$src)))>; - - -def fp32imm0 : PatLeaf<(f32 fpimm), [{ - return N->isExactlyValue(+0.0); -}]>; - -// BYTE_imm - Transform bit immediates into byte immediates. -def BYTE_imm : SDNodeXForm> 3 - return getI32Imm(N->getZExtValue() >> 3); -}]>; - -// SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*, -// SHUFP* etc. imm. -def SHUFFLE_get_shuf_imm : SDNodeXForm; - -// SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to -// PSHUFHW imm. -def SHUFFLE_get_pshufhw_imm : SDNodeXForm; - -// SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to -// PSHUFLW imm. -def SHUFFLE_get_pshuflw_imm : SDNodeXForm; - -// SHUFFLE_get_palign_imm xform function: convert vector_shuffle mask to -// a PALIGNR imm. -def SHUFFLE_get_palign_imm : SDNodeXForm; - -def splat_lo : PatFrag<(ops node:$lhs, node:$rhs), - (vector_shuffle node:$lhs, node:$rhs), [{ - ShuffleVectorSDNode *SVOp = cast(N); - return SVOp->isSplat() && SVOp->getSplatIndex() == 0; -}]>; - -def movddup : PatFrag<(ops node:$lhs, node:$rhs), - (vector_shuffle node:$lhs, node:$rhs), [{ - return X86::isMOVDDUPMask(cast(N)); -}]>; - -def movhlps : PatFrag<(ops node:$lhs, node:$rhs), - (vector_shuffle node:$lhs, node:$rhs), [{ - return X86::isMOVHLPSMask(cast(N)); -}]>; - -def movhlps_undef : PatFrag<(ops node:$lhs, node:$rhs), - (vector_shuffle node:$lhs, node:$rhs), [{ - return X86::isMOVHLPS_v_undef_Mask(cast(N)); -}]>; - -def movlhps : PatFrag<(ops node:$lhs, node:$rhs), - (vector_shuffle node:$lhs, node:$rhs), [{ - return X86::isMOVLHPSMask(cast(N)); -}]>; - -def movlp : PatFrag<(ops node:$lhs, node:$rhs), - (vector_shuffle node:$lhs, node:$rhs), [{ - return X86::isMOVLPMask(cast(N)); -}]>; - -def movl : PatFrag<(ops node:$lhs, node:$rhs), - (vector_shuffle node:$lhs, node:$rhs), [{ - return X86::isMOVLMask(cast(N)); -}]>; - -def movshdup : PatFrag<(ops node:$lhs, node:$rhs), - (vector_shuffle node:$lhs, node:$rhs), [{ - return X86::isMOVSHDUPMask(cast(N)); -}]>; - -def movsldup : PatFrag<(ops node:$lhs, node:$rhs), - (vector_shuffle node:$lhs, node:$rhs), [{ - return X86::isMOVSLDUPMask(cast(N)); -}]>; - -def unpckl : PatFrag<(ops node:$lhs, node:$rhs), - (vector_shuffle node:$lhs, node:$rhs), [{ - return X86::isUNPCKLMask(cast(N)); -}]>; - -def unpckh : PatFrag<(ops node:$lhs, node:$rhs), - (vector_shuffle node:$lhs, node:$rhs), [{ - return X86::isUNPCKHMask(cast(N)); -}]>; - -def unpckl_undef : PatFrag<(ops node:$lhs, node:$rhs), - (vector_shuffle node:$lhs, node:$rhs), [{ - return X86::isUNPCKL_v_undef_Mask(cast(N)); -}]>; - -def unpckh_undef : PatFrag<(ops node:$lhs, node:$rhs), - (vector_shuffle node:$lhs, node:$rhs), [{ - return X86::isUNPCKH_v_undef_Mask(cast(N)); -}]>; - -def pshufd : PatFrag<(ops node:$lhs, node:$rhs), - (vector_shuffle node:$lhs, node:$rhs), [{ - return X86::isPSHUFDMask(cast(N)); -}], SHUFFLE_get_shuf_imm>; - -def shufp : PatFrag<(ops node:$lhs, node:$rhs), - (vector_shuffle node:$lhs, node:$rhs), [{ - return X86::isSHUFPMask(cast(N)); -}], SHUFFLE_get_shuf_imm>; - -def pshufhw : PatFrag<(ops node:$lhs, node:$rhs), - (vector_shuffle node:$lhs, node:$rhs), [{ - return X86::isPSHUFHWMask(cast(N)); -}], SHUFFLE_get_pshufhw_imm>; - -def pshuflw : PatFrag<(ops node:$lhs, node:$rhs), - (vector_shuffle node:$lhs, node:$rhs), [{ - return X86::isPSHUFLWMask(cast(N)); -}], SHUFFLE_get_pshuflw_imm>; - -def palign : PatFrag<(ops node:$lhs, node:$rhs), - (vector_shuffle node:$lhs, node:$rhs), [{ - return X86::isPALIGNRMask(cast(N)); -}], SHUFFLE_get_palign_imm>; - -//===----------------------------------------------------------------------===// // SSE scalar FP Instructions //===----------------------------------------------------------------------===// From evan.cheng at apple.com Mon Jul 12 18:53:26 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 12 Jul 2010 16:53:26 -0700 Subject: [llvm-commits] [llvm] r108109 - /llvm/trunk/lib/CodeGen/MachineLICM.cpp In-Reply-To: <01AEDF63-186E-4CA3-BCA9-0686BFC66E3A@2pi.dk> References: <20100712000035.393982A6C12C@llvm.org> <5470C984-D21B-4C3F-860C-D7506AFBFAAB@apple.com> <3434519D-9F54-4516-A09A-FAE224A0E8C5@nondot.org> <01AEDF63-186E-4CA3-BCA9-0686BFC66E3A@2pi.dk> Message-ID: <271FD80E-5C28-4114-8430-8E7053E9DEFA@apple.com> On Jul 12, 2010, at 3:37 PM, Jakob Stoklund Olesen wrote: > > On Jul 12, 2010, at 2:44 PM, Chris Lattner wrote: > >> >> On Jul 12, 2010, at 11:22 AM, Evan Cheng wrote: >> >>> >>> On Jul 12, 2010, at 8:29 AM, Chris Lattner wrote: >>> >>>> >>>> On Jul 12, 2010, at 12:57 AM, Evan Cheng wrote: >>>> >>>>>> change machinelicm to use MachineInstr::isSafeToMove. No >>>>>> intended functionality change. >>>>>> >>>>>> The avoidance of hoistiing implicitdef seems wrong though. >>>>> >>>>> It's not. We want to avoid creating implicitdef with no trivial live intervals. The trivial ones will be converted to undef machine operands which do not take up registers. >>>> >>>> Why? The register allocator treats them specially just so they don't use a register (according to Jakob). >>> >>> No, that's not correct. The ones with trivial live intervals, i.e. defined and used in the same BB, are converted to undef operands. These do not take up registers. The ones that have uses outside of the definition block *may* not be eliminated. Those will take up registers. >> >> Jakob, didn't you just tell me that the RA turned them into trivial short live ranges? > > I thought they were. > >> If not, isn't that the right thing to do? > > I can't imagine why we would want to keep IMPLICIT_DEFs around, but I can imagine ProcessImplicitDefs getting confused because the code is not SSA. > > RA, or rather ProcessImplicitDef pass, turn them into trivial short live ranges when it's possible. But it does miss some cases. It's relatively rare but it does happen. Evan From wdietz2 at illinois.edu Mon Jul 12 19:00:42 2010 From: wdietz2 at illinois.edu (Will Dietz) Date: Tue, 13 Jul 2010 00:00:42 -0000 Subject: [llvm-commits] [poolalloc] r108215 - in /poolalloc/trunk/test/pa/clone: ./ AttrTest.ll dg.exp Message-ID: <20100713000042.CE2712A6C12C@llvm.org> Author: wdietz2 Date: Mon Jul 12 19:00:42 2010 New Revision: 108215 URL: http://llvm.org/viewvc/llvm-project?rev=108215&view=rev Log: Added "AttrTest" lit test to verify we do the right thing with attributes. Test is simple, but does the job. Added: poolalloc/trunk/test/pa/clone/ poolalloc/trunk/test/pa/clone/AttrTest.ll poolalloc/trunk/test/pa/clone/dg.exp Added: poolalloc/trunk/test/pa/clone/AttrTest.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/pa/clone/AttrTest.ll?rev=108215&view=auto ============================================================================== --- poolalloc/trunk/test/pa/clone/AttrTest.ll (added) +++ poolalloc/trunk/test/pa/clone/AttrTest.ll Mon Jul 12 19:00:42 2010 @@ -0,0 +1,20 @@ +;This test does some very basic checking on the attribute copying of arguments +;RUN: paopt %s -poolalloc -o %t.bc |& grep "Pool allocating.*nodes!" +;RUN: llvm-dis %t.bc -o %t.ll +;Make sure 'nocapture' attribute isn't copied to new PD argument +;RUN: cat %t.ll | grep -v ".*@.*(.*nocapture.*,.*,.*)" +;But ensure the other arguments have their original attributes +;RUN: cat %t.ll | grep ".*@.*(.*,.*zeroext.*,.*nocapture.*)" +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" + +define i32 @main(i32 %argc, i8** nocapture %argv) nounwind { +entry: + unreachable +} + +define void @attr(i16 zeroext %IntParam, i8** nocapture %NeedsPool) { +entry: + unreachable +} + Added: poolalloc/trunk/test/pa/clone/dg.exp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/pa/clone/dg.exp?rev=108215&view=auto ============================================================================== --- poolalloc/trunk/test/pa/clone/dg.exp (added) +++ poolalloc/trunk/test/pa/clone/dg.exp Mon Jul 12 19:00:42 2010 @@ -0,0 +1,3 @@ +load_lib llvm.exp + +RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]] From grosbach at apple.com Mon Jul 12 19:02:14 2010 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 12 Jul 2010 17:02:14 -0700 Subject: [llvm-commits] [llvm-gcc-4.2] r108206 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp In-Reply-To: <20100712230256.C6C322A6C12C@llvm.org> References: <20100712230256.C6C322A6C12C@llvm.org> Message-ID: <352523D6-C758-4C1F-B9F6-40AAD6F9B43B@apple.com> The diagnostic needs to be a bit broader than this, actually. It's not just the variable sized allocation that can't be dynamically aligned, but any declaration in the same function. That is, a function which has variable sized stack objects cannot also contain stack objects which require dynamic stack realignment. -Jim On Jul 12, 2010, at 4:02 PM, Eric Christopher wrote: > Author: echristo > Date: Mon Jul 12 18:02:56 2010 > New Revision: 108206 > > URL: http://llvm.org/viewvc/llvm-project?rev=108206&view=rev > Log: > Make sure that the requested alignment isn't greater than the stack alignment > for a vla - we won't adhere to it anyways so make it an error. > > Fixes rdar://7506902 > > Modified: > llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp > > Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=108206&r1=108205&r2=108206&view=diff > ============================================================================== > --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) > +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Mon Jul 12 18:02:56 2010 > @@ -39,6 +39,7 @@ > #include "llvm/Target/TargetLowering.h" > #include "llvm/Target/TargetData.h" > #include "llvm/Target/TargetMachine.h" > +#include "llvm/Target/TargetFrameInfo.h" > #include "llvm/ADT/StringExtras.h" > #include "llvm/ADT/DenseMap.h" > > @@ -1755,6 +1756,15 @@ > if (isGimpleTemporary(decl)) > return; > > + /* If this is a vla type and we requested an alignment greater than the stack > + alignment, error out since we're not going to dynamically realign > + variable length array allocations. We're placing this here instead of > + later in case it's a relatively unused variable. */ > + if (TREE_CODE (type) == ARRAY_TYPE && C_TYPE_VARIABLE_SIZE (type) && > + DECL_ALIGN(decl)/8u > TheTarget->getFrameInfo()->getStackAlignment()) > + error ("alignment for %q+D is greater than the stack alignment, " > + "we cannot guarantee the alignment.", decl); > + > // If this is just the rotten husk of a variable that the gimplifier > // eliminated all uses of, but is preserving for debug info, ignore it. > if (TREE_CODE(decl) == VAR_DECL && DECL_VALUE_EXPR(decl)) > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From wdietz2 at illinois.edu Mon Jul 12 19:04:39 2010 From: wdietz2 at illinois.edu (Will Dietz) Date: Tue, 13 Jul 2010 00:04:39 -0000 Subject: [llvm-commits] [poolalloc] r108216 - /poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp Message-ID: <20100713000439.ED4012A6C12C@llvm.org> Author: wdietz2 Date: Mon Jul 12 19:04:39 2010 New Revision: 108216 URL: http://llvm.org/viewvc/llvm-project?rev=108216&view=rev Log: Improve/fix attribute copying from old function to the new clone. Not listing the attributes also makes it more robust to changes in the types of attributes moving forward. Fixes PR#7631. Modified: poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp Modified: poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp?rev=108216&r1=108215&r2=108216&view=diff ============================================================================== --- poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp (original) +++ poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp Mon Jul 12 19:04:39 2010 @@ -645,10 +645,6 @@ NI->setName(I->getName()); } - // Perform the cloning. - SmallVector Returns; - CloneFunctionInto(New, &F, ValueMap, Returns); - // // Invert the ValueMap into the NewToOldValueMap. // @@ -657,6 +653,10 @@ E = ValueMap.end(); I != E; ++I) NewToOldValueMap.insert(std::make_pair(I->second, I->first)); + // Perform the cloning. + SmallVector Returns; + CloneFunctionInto(New, &F, ValueMap, Returns); + // // FIXME: File a bug report for CloneFunctionInto; it should take care of // this mess for us. Also check whether it does it correctly. @@ -673,8 +673,8 @@ Function::ArgumentListType & ArgList = New->getArgumentList (); Function::ArgumentListType::iterator arg = ArgList.begin(); for (; arg != ArgList.end(); ++arg) { - arg->removeAttr (Attribute::ParameterOnly); - arg->removeAttr (Attribute::NoAlias); + // Whatever attributes New has for this argument, remove them. + arg->removeAttr(New->getAttributes().getParamAttributes(arg->getArgNo()+1)); } // @@ -686,11 +686,7 @@ Argument * newArg = dyn_cast(ValueMap[arg]); assert (newArg && "Value Map for arguments incorrect!\n"); - if (arg->hasByValAttr ()) newArg->addAttr (Attribute::ByVal); - if (arg->hasNestAttr ()) newArg->addAttr (Attribute::Nest); - if (arg->hasNoAliasAttr ()) newArg->addAttr (Attribute::NoAlias); - if (arg->hasNoCaptureAttr ()) newArg->addAttr (Attribute::NoCapture); - if (arg->hasStructRetAttr ()) newArg->addAttr (Attribute::StructRet); + newArg->addAttr(F.getAttributes().getParamAttributes(arg->getArgNo()+1)); } return FI.Clone = New; From echristo at apple.com Mon Jul 12 19:17:53 2010 From: echristo at apple.com (Eric Christopher) Date: Mon, 12 Jul 2010 17:17:53 -0700 Subject: [llvm-commits] [llvm-gcc-4.2] r108206 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp In-Reply-To: <352523D6-C758-4C1F-B9F6-40AAD6F9B43B@apple.com> References: <20100712230256.C6C322A6C12C@llvm.org> <352523D6-C758-4C1F-B9F6-40AAD6F9B43B@apple.com> Message-ID: On Jul 12, 2010, at 5:02 PM, Jim Grosbach wrote: > The diagnostic needs to be a bit broader than this, actually. It's not just the variable sized allocation that can't be dynamically aligned, but any declaration in the same function. That is, a function which has variable sized stack objects cannot also contain stack objects which require dynamic stack realignment. I'm not entirely convinced. The original aim would have been to put the code in c-common.c so that when we handle user requested alignment we make the check on the stack size, but without including a lot of llvm bits into c-common.c it's not possible (unless we make the assumption that the gcc/config/arm backend has the right stack alignment :) That said I should definitely add a quick check for DECL_USER_ALIGN to make sure that the user set it and not something else somewhere. A quick change to say "requested alignment..." would probably help as well. Unless I'm missing what you're trying to say (which is altogether possible). -eric From grosbach at apple.com Mon Jul 12 19:21:33 2010 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 12 Jul 2010 17:21:33 -0700 Subject: [llvm-commits] [llvm-gcc-4.2] r108206 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp In-Reply-To: References: <20100712230256.C6C322A6C12C@llvm.org> <352523D6-C758-4C1F-B9F6-40AAD6F9B43B@apple.com> Message-ID: <824AB794-5BB3-4863-BE17-D1AAF551A403@apple.com> On Jul 12, 2010, at 5:17 PM, Eric Christopher wrote: > > On Jul 12, 2010, at 5:02 PM, Jim Grosbach wrote: > >> The diagnostic needs to be a bit broader than this, actually. It's not just the variable sized allocation that can't be dynamically aligned, but any declaration in the same function. That is, a function which has variable sized stack objects cannot also contain stack objects which require dynamic stack realignment. > > I'm not entirely convinced. The original aim would have been to put the code in c-common.c so that when we handle user requested alignment we make the check on the stack size, but without including a lot of llvm bits into c-common.c it's not possible (unless we make the assumption that the gcc/config/arm backend has the right stack alignment :) > > That said I should definitely add a quick check for DECL_USER_ALIGN to make sure that the user set it and not something else somewhere. > > A quick change to say "requested alignment..." would probably help as well. > > Unless I'm missing what you're trying to say (which is altogether possible). > A function can either: a) contain a variable sized stack-based object, or b) require dynamic stack realignment. If it tries to do both, an error diagnostic should be generated. This is target, specific, also. It's true, as far as I know, for all targets currently, but that's not guaranteed to always be the case. -Jim From stoklund at 2pi.dk Mon Jul 12 19:23:30 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 13 Jul 2010 00:23:30 -0000 Subject: [llvm-commits] [llvm] r108219 - /llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp Message-ID: <20100713002330.9D06F2A6C12C@llvm.org> Author: stoklund Date: Mon Jul 12 19:23:30 2010 New Revision: 108219 URL: http://llvm.org/viewvc/llvm-project?rev=108219&view=rev Log: Don't add memory operands to storeRegToStackSlot / loadRegFromStackSlot results, they already have one. This fixes the himenobmtxpa miscompilation on ARM. The PostRA scheduler got confused by the double memoperand and hoisted a stack slot load above a store to the same slot. Modified: llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp Modified: llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp?rev=108219&r1=108218&r2=108219&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp (original) +++ llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp Mon Jul 12 19:23:30 2010 @@ -24,6 +24,7 @@ #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/PostRAHazardRecognizer.h" #include "llvm/CodeGen/PseudoSourceValue.h" +#include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" using namespace llvm; @@ -253,51 +254,44 @@ MachineFunction &MF = *MBB->getParent(); // Ask the target to do the actual folding. - MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, FI); + if (MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, FI)) { + // Add a memory operand, foldMemoryOperandImpl doesn't do that. + assert((!(Flags & MachineMemOperand::MOStore) || + NewMI->getDesc().mayStore()) && + "Folded a def to a non-store!"); + assert((!(Flags & MachineMemOperand::MOLoad) || + NewMI->getDesc().mayLoad()) && + "Folded a use to a non-load!"); + const MachineFrameInfo &MFI = *MF.getFrameInfo(); + assert(MFI.getObjectOffset(FI) != -1); + MachineMemOperand *MMO = + MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI), + Flags, /*Offset=*/0, + MFI.getObjectSize(FI), + MFI.getObjectAlignment(FI)); + NewMI->addMemOperand(MF, MMO); - // Straight COPY may fold as load/store. - if (!NewMI) { - if (!MI->isCopy() || Ops.size() != 1) - return 0; - - const TargetRegisterClass *RC = canFoldCopy(MI, Ops[0]); - if (!RC) - return 0; - - const MachineOperand &MO = MI->getOperand(1-Ops[0]); - MachineBasicBlock::iterator Pos = MI; - const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); - - if (Flags == MachineMemOperand::MOStore) - storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI); - else - loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, TRI); - - NewMI = --Pos; - } else { // FIXME: change foldMemoryOperandImpl semantics to also insert NewMI. - NewMI = MBB->insert(MI, NewMI); + return MBB->insert(MI, NewMI); } - if (!NewMI) return 0; - + // Straight COPY may fold as load/store. + if (!MI->isCopy() || Ops.size() != 1) + return 0; - assert((!(Flags & MachineMemOperand::MOStore) || - NewMI->getDesc().mayStore()) && - "Folded a def to a non-store!"); - assert((!(Flags & MachineMemOperand::MOLoad) || - NewMI->getDesc().mayLoad()) && - "Folded a use to a non-load!"); - const MachineFrameInfo &MFI = *MF.getFrameInfo(); - assert(MFI.getObjectOffset(FI) != -1); - MachineMemOperand *MMO = - MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI), - Flags, /*Offset=*/0, - MFI.getObjectSize(FI), - MFI.getObjectAlignment(FI)); - NewMI->addMemOperand(MF, MMO); + const TargetRegisterClass *RC = canFoldCopy(MI, Ops[0]); + if (!RC) + return 0; - return NewMI; + const MachineOperand &MO = MI->getOperand(1-Ops[0]); + MachineBasicBlock::iterator Pos = MI; + const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); + + if (Flags == MachineMemOperand::MOStore) + storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI); + else + loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, TRI); + return --Pos; } /// foldMemoryOperand - Same as the previous version except it allows folding From wilsons at start.ca Mon Jul 12 19:25:00 2010 From: wilsons at start.ca (Stephen Wilson) Date: Tue, 13 Jul 2010 00:25:00 -0000 Subject: [llvm-commits] [llvm] r108221 - /llvm/trunk/include/llvm/Support/ELF.h Message-ID: <20100713002500.18E332A6C12C@llvm.org> Author: wilsons Date: Mon Jul 12 19:24:59 2010 New Revision: 108221 URL: http://llvm.org/viewvc/llvm-project?rev=108221&view=rev Log: Bring ELF64 on par with ELF32, add a few magic constants and support ".dynamic" section entries. Modified: llvm/trunk/include/llvm/Support/ELF.h Modified: llvm/trunk/include/llvm/Support/ELF.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ELF.h?rev=108221&r1=108220&r2=108221&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/ELF.h (original) +++ llvm/trunk/include/llvm/Support/ELF.h Mon Jul 12 19:24:59 2010 @@ -10,11 +10,10 @@ // This header contains common, non-processor-specific data structures and // constants for the ELF file format. // -// The details of the ELF32 bits in this file are largely based on -// the Tool Interface Standard (TIS) Executable and Linking Format -// (ELF) Specification Version 1.2, May 1995. The ELF64 stuff is not -// standardized, as far as I can tell. It was largely based on information -// I found in OpenBSD header files. +// The details of the ELF32 bits in this file are largely based on the Tool +// Interface Standard (TIS) Executable and Linking Format (ELF) Specification +// Version 1.2, May 1995. The ELF64 stuff is based on ELF-64 Object File Format +// Version 1.5, Draft 2, May 1998 as well as OpenBSD header files. // //===----------------------------------------------------------------------===// @@ -47,8 +46,23 @@ // Object file magic string. static const char ElfMagic[] = { 0x7f, 'E', 'L', 'F', '\0' }; +// e_ident size and indices. +enum { + EI_MAG0 = 0, // File identification index. + EI_MAG1 = 1, // File identification index. + EI_MAG2 = 2, // File identification index. + EI_MAG3 = 3, // File identification index. + EI_CLASS = 4, // File class. + EI_DATA = 5, // Data encoding. + EI_VERSION = 6, // File version. + EI_OSABI = 7, // OS/ABI identification. + EI_ABIVERSION = 8, // ABI version. + EI_PAD = 9, // Start of padding bytes. + EI_NIDENT = 16 // Number of bytes in e_ident. +}; + struct Elf32_Ehdr { - unsigned char e_ident[16]; // ELF Identification bytes + unsigned char e_ident[EI_NIDENT]; // ELF Identification bytes Elf32_Half e_type; // Type of file (see ET_* below) Elf32_Half e_machine; // Required architecture for this file (see EM_*) Elf32_Word e_version; // Must be equal to 1 @@ -65,14 +79,14 @@ bool checkMagic() const { return (memcmp(e_ident, ElfMagic, strlen(ElfMagic))) == 0; } - unsigned char getFileClass() const { return e_ident[4]; } - unsigned char getDataEncoding() { return e_ident[5]; } + unsigned char getFileClass() const { return e_ident[EI_CLASS]; } + unsigned char getDataEncoding() const { return e_ident[EI_DATA]; } }; // 64-bit ELF header. Fields are the same as for ELF32, but with different // types (see above). struct Elf64_Ehdr { - unsigned char e_ident[16]; + unsigned char e_ident[EI_NIDENT]; Elf64_Quarter e_type; Elf64_Quarter e_machine; Elf64_Half e_version; @@ -86,6 +100,11 @@ Elf64_Quarter e_shentsize; Elf64_Quarter e_shnum; Elf64_Quarter e_shstrndx; + bool checkMagic() const { + return (memcmp(e_ident, ElfMagic, strlen(ElfMagic))) == 0; + } + unsigned char getFileClass() const { return e_ident[EI_CLASS]; } + unsigned char getDataEncoding() const { return e_ident[EI_DATA]; } }; // File types @@ -117,6 +136,7 @@ EM_860 = 7, // Intel 80860 EM_MIPS = 8, // MIPS R3000 EM_PPC = 20, // PowerPC + EM_PPC64 = 21, // PowerPC64 EM_ARM = 40, // ARM EM_ALPHA = 41, // DEC Alpha EM_SPARCV9 = 43, // SPARC V9 @@ -131,6 +151,7 @@ // Object file byte orderings. enum { + ELFDATANONE = 0, // Invalid data encoding. ELFDATA2LSB = 1, // Little-endian object file ELFDATA2MSB = 2 // Big-endian object file }; @@ -262,7 +283,7 @@ SHF_MASKPROC = 0xf0000000 // Bits indicating processor-specific flags. }; -// Symbol table entries. +// Symbol table entries for ELF32. struct Elf32_Sym { Elf32_Word st_name; // Symbol name (index into string table) Elf32_Addr st_value; // Value or address associated with the symbol @@ -282,6 +303,26 @@ } }; +// Symbol table entries for ELF64. +struct Elf64_Sym { + Elf64_Word st_name; // Symbol name (index into string table) + unsigned char st_info; // Symbol's type and binding attributes + unsigned char st_other; // Must be zero; reserved + Elf64_Half st_shndx; // Which section (header table index) it's defined in + Elf64_Addr st_value; // Value or address associated with the symbol + Elf64_Xword st_size; // Size of the symbol + + // These accessors and mutators are identical to those defined for ELF32 + // symbol table entries. + unsigned char getBinding() const { return st_info >> 4; } + unsigned char getType() const { return st_info & 0x0f; } + void setBinding(unsigned char b) { setBindingAndType(b, getType()); } + void setType(unsigned char t) { setBindingAndType(getBinding(), t); } + void setBindingAndType(unsigned char b, unsigned char t) { + st_info = (b << 4) + (t & 0x0f); + } +}; + // Symbol bindings. enum { STB_LOCAL = 0, // Local symbol, not visible outside obj file containing def @@ -372,7 +413,7 @@ }; }; -// Program header. +// Program header for ELF32. struct Elf32_Phdr { Elf32_Word p_type; // Type of segment Elf32_Off p_offset; // File offset where segment is located, in bytes @@ -384,6 +425,18 @@ Elf32_Word p_align; // Segment alignment constraint }; +// Program header for ELF64. +struct Elf64_Phdr { + Elf64_Word p_type; // Type of segment + Elf64_Word p_flags; // Segment flags + Elf64_Off p_offset; // File offset where segment is located, in bytes + Elf64_Addr p_vaddr; // Virtual address of beginning of segment + Elf64_Addr p_paddr; // Physical address of beginning of segment (OS-specific) + Elf64_Xword p_filesz; // Num. of bytes in file image of segment (may be zero) + Elf64_Xword p_memsz; // Num. of bytes in mem image of segment (may be zero) + Elf64_Xword p_align; // Segment alignment constraint +}; + // Segment types. enum { PT_NULL = 0, // Unused segment. @@ -405,6 +458,65 @@ PF_MASKPROC = 0xf0000000 // Unspecified }; +// Dynamic table entry for ELF32. +struct Elf32_Dyn +{ + Elf32_Sword d_tag; // Type of dynamic table entry. + union + { + Elf32_Word d_val; // Integer value of entry. + Elf32_Addr d_ptr; // Pointer value of entry. + } d_un; +}; + +// Dynamic table entry for ELF64. +struct Elf64_Dyn +{ + Elf64_Sxword d_tag; // Type of dynamic table entry. + union + { + Elf64_Xword d_val; // Integer value of entry. + Elf64_Addr d_ptr; // Pointer value of entry. + } d_un; +}; + +// Dynamic table entry tags. +enum { + DT_NULL = 0, // Marks end of dynamic array. + DT_NEEDED = 1, // String table offset of needed library. + DT_PLTRELSZ = 2, // Size of relocation entries in PLT. + DT_PLTGOT = 3, // Address associated with linkage table. + DT_HASH = 4, // Address of symbolic hash table. + DT_STRTAB = 5, // Address of dynamic string table. + DT_SYMTAB = 6, // Address of dynamic symbol table. + DT_RELA = 7, // Address of relocation table (Rela entries). + DT_RELASZ = 8, // Size of Rela relocation table. + DT_RELAENT = 9, // Size of a Rela relocation entry. + DT_STRSZ = 10, // Total size of the string table. + DT_SYMENT = 11, // Size of a symbol table entry. + DT_INIT = 12, // Address of initialization function. + DT_FINI = 13, // Address of termination function. + DT_SONAME = 14, // String table offset of a shared objects name. + DT_RPATH = 15, // String table offset of library search path. + DT_SYMBOLIC = 16, // Changes symbol resolution algorithm. + DT_REL = 17, // Address of relocation table (Rel entries). + DT_RELSZ = 18, // Size of Rel relocation table. + DT_RELENT = 19, // Size of a Rel relocation entry. + DT_PLTREL = 20, // Type of relocation entry used for linking. + DT_DEBUG = 21, // Reserved for debugger. + DT_TEXTREL = 22, // Relocations exist for non-writable segements. + DT_JMPREL = 23, // Address of relocations associated with PLT. + DT_BIND_NOW = 24, // Process all relocations before execution. + DT_INIT_ARRAY = 25, // Pointer to array of initialization functions. + DT_FINI_ARRAY = 26, // Pointer to array of termination functions. + DT_INIT_ARRAYSZ = 27, // Size of DT_INIT_ARRAY. + DT_FINI_ARRAYSZ = 28, // Size of DT_FINI_ARRAY. + DT_LOOS = 0x60000000, // Start of environment specific tags. + DT_HIOS = 0x6FFFFFFF, // End of environment specific tags. + DT_LOPROC = 0x70000000, // Start of processor specific tags. + DT_HIPROC = 0x7FFFFFFF // End of processor specific tags. +}; + } // end namespace ELF } // end namespace llvm From bruno.cardoso at gmail.com Mon Jul 12 19:38:47 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 13 Jul 2010 00:38:47 -0000 Subject: [llvm-commits] [llvm] r108222 - in /llvm/trunk/lib/Target/X86: X86InstrFormats.td X86InstrSSE.td Message-ID: <20100713003847.6014C2A6C12C@llvm.org> Author: bruno Date: Mon Jul 12 19:38:47 2010 New Revision: 108222 URL: http://llvm.org/viewvc/llvm-project?rev=108222&view=rev Log: Since AVX is a superset of all SSE versions, only use HasAVX for AVX instructions Modified: llvm/trunk/lib/Target/X86/X86InstrFormats.td llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFormats.td?rev=108222&r1=108221&r2=108222&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrFormats.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrFormats.td Mon Jul 12 19:38:47 2010 @@ -235,8 +235,7 @@ // SI - SSE 1 & 2 scalar instructions class SI o, Format F, dag outs, dag ins, string asm, list pattern> : I { - let Predicates = !if(hasVEXPrefix /* VEX_4V */, - !if(!eq(Prefix, 11 /* XD */), [HasAVX, HasSSE2], [HasAVX, HasSSE1]), + let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX], !if(!eq(Prefix, 12 /* XS */), [HasSSE1], [HasSSE2])); // AVX instructions have a 'v' prefix in the mnemonic @@ -247,8 +246,7 @@ class SIi8 o, Format F, dag outs, dag ins, string asm, list pattern> : Ii8 { - let Predicates = !if(hasVEXPrefix /* VEX_4V */, - !if(!eq(Prefix, 11 /* XD */), [HasAVX, HasSSE2], [HasAVX, HasSSE1]), + let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX], !if(!eq(Prefix, 12 /* XS */), [HasSSE1], [HasSSE2])); // AVX instructions have a 'v' prefix in the mnemonic @@ -259,8 +257,7 @@ class PI o, Format F, dag outs, dag ins, string asm, list pattern, Domain d> : I { - let Predicates = !if(hasVEXPrefix /* VEX_4V */, - !if(hasOpSizePrefix /* OpSize */, [HasAVX, HasSSE2], [HasAVX, HasSSE1]), + let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX], !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1])); // AVX instructions have a 'v' prefix in the mnemonic @@ -271,8 +268,7 @@ class PIi8 o, Format F, dag outs, dag ins, string asm, list pattern, Domain d> : Ii8 { - let Predicates = !if(hasVEX_4VPrefix /* VEX_4V */, - !if(hasOpSizePrefix /* OpSize */, [HasAVX, HasSSE2], [HasAVX, HasSSE1]), + let Predicates = !if(hasVEX_4VPrefix /* VEX */, [HasAVX], !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1])); // AVX instructions have a 'v' prefix in the mnemonic @@ -302,11 +298,11 @@ class VSSI o, Format F, dag outs, dag ins, string asm, list pattern> : I, XS, - Requires<[HasAVX, HasSSE1]>; + Requires<[HasAVX]>; class VPSI o, Format F, dag outs, dag ins, string asm, list pattern> : I, - Requires<[HasAVX, HasSSE1]>; + Requires<[HasAVX]>; // SSE2 Instruction Templates: // @@ -336,11 +332,11 @@ class VSDI o, Format F, dag outs, dag ins, string asm, list pattern> : I, XD, - Requires<[HasAVX, HasSSE2]>; + Requires<[HasAVX]>; class VPDI o, Format F, dag outs, dag ins, string asm, list pattern> : I, - OpSize, Requires<[HasAVX, HasSSE2]>; + OpSize, Requires<[HasAVX]>; // SSE3 Instruction Templates: // Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=108222&r1=108221&r2=108222&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Jul 12 19:38:47 2010 @@ -686,7 +686,7 @@ def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins FR64:$src1, f64mem:$src2), "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", - []>, XD, Requires<[HasAVX, HasSSE2, OptForSize]>, VEX_4V; + []>, XD, Requires<[HasAVX, OptForSize]>, VEX_4V; } def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src), "cvtsd2ss\t{$src, $dst|$dst, $src}", @@ -711,11 +711,11 @@ def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src1, FR32:$src2), "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}", - []>, XS, Requires<[HasAVX, HasSSE2]>, VEX_4V; + []>, XS, Requires<[HasAVX]>, VEX_4V; def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins FR32:$src1, f32mem:$src2), "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}", - []>, XS, VEX_4V, Requires<[HasAVX, HasSSE2, OptForSize]>; + []>, XS, VEX_4V, Requires<[HasAVX, OptForSize]>; } def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src), "cvtss2sd\t{$src, $dst|$dst, $src}", @@ -732,13 +732,13 @@ "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))]>, XS, VEX_4V, - Requires<[HasAVX, HasSSE2]>; + Requires<[HasAVX]>; def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2), "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1, (load addr:$src2)))]>, XS, VEX_4V, - Requires<[HasAVX, HasSSE2]>; + Requires<[HasAVX]>; } let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg, @@ -764,12 +764,12 @@ def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "vcvtdq2ps\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>, - TB, VEX, Requires<[HasAVX, HasSSE2]>; + TB, VEX, Requires<[HasAVX]>; def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), "vcvtdq2ps\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cvtdq2ps (bitconvert (memopv2i64 addr:$src))))]>, - TB, VEX, Requires<[HasAVX, HasSSE2]>; + TB, VEX, Requires<[HasAVX]>; } def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "cvtdq2ps\t{$src, $dst|$dst, $src}", @@ -786,12 +786,12 @@ def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "vcvtdq2pd\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>, - XS, VEX, Requires<[HasAVX, HasSSE2]>; + XS, VEX, Requires<[HasAVX]>; def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src), "vcvtdq2pd\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cvtdq2pd (bitconvert (memopv2i64 addr:$src))))]>, - XS, VEX, Requires<[HasAVX, HasSSE2]>; + XS, VEX, Requires<[HasAVX]>; } def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "cvtdq2pd\t{$src, $dst|$dst, $src}", @@ -838,12 +838,12 @@ def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "vcvtpd2dq\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>, - XD, VEX, Requires<[HasAVX, HasSSE2]>; + XD, VEX, Requires<[HasAVX]>; def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), "vcvtpd2dq\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cvtpd2dq (memop addr:$src)))]>, - XD, VEX, Requires<[HasAVX, HasSSE2]>; + XD, VEX, Requires<[HasAVX]>; } def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "cvtpd2dq\t{$src, $dst|$dst, $src}", @@ -874,12 +874,12 @@ "vcvttps2dq\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))]>, - XS, VEX, Requires<[HasAVX, HasSSE2]>; + XS, VEX, Requires<[HasAVX]>; def Int_VCVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), "vcvttps2dq\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cvttps2dq (memop addr:$src)))]>, - XS, VEX, Requires<[HasAVX, HasSSE2]>; + XS, VEX, Requires<[HasAVX]>; } def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "cvttps2dq\t{$src, $dst|$dst, $src}", @@ -930,12 +930,12 @@ def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "cvtps2pd\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>, - VEX, Requires<[HasAVX, HasSSE2]>; + VEX, Requires<[HasAVX]>; def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src), "cvtps2pd\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_cvtps2pd (load addr:$src)))]>, - VEX, Requires<[HasAVX, HasSSE2]>; + VEX, Requires<[HasAVX]>; } def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "cvtps2pd\t{$src, $dst|$dst, $src}", @@ -1377,7 +1377,7 @@ multiclass sse12_fp_packed_logical opc, string OpcodeStr, SDNode OpNode, int HasPat = 0, list> Pattern = []> { - let isAsmParserOnly = 1 in { + let isAsmParserOnly = 1, Pattern = [] in { defm V#NAME#PS : sse12_fp_packed_logical_rm, basic_sse12_fp_binop_p<0x58, "add", fadd, 0>, basic_sse12_fp_binop_p_y<0x58, "add", fadd>, VEX_4V; @@ -1610,7 +1610,7 @@ def SSm : I, XS, Requires<[HasAVX, HasSSE1, OptForSize]>; + []>, XS, Requires<[HasAVX, OptForSize]>; def SSr_Int : SSI, VEX_4V; defm VSQRT : sse2_fp_unop_p<0x51, "vsqrt", fsqrt, int_x86_sse2_sqrt_pd>, VEX; } - let Predicates = [HasAVX, HasSSE1] in { + let Predicates = [HasAVX] in { defm VSQRT : sse1_fp_unop_s_avx<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>, VEX_4V; defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt, int_x86_sse_sqrt_ps>, VEX; @@ -1907,7 +1907,7 @@ def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), "vmovdqu\t{$src, $dst|$dst, $src}", [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>, - XS, VEX, Requires<[HasAVX, HasSSE2]>; + XS, VEX, Requires<[HasAVX]>; } let mayStore = 1 in { @@ -1918,7 +1918,7 @@ def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src), "vmovdqu\t{$src, $dst|$dst, $src}", [/*(store (v2i64 VR128:$src), addr:$dst)*/]>, - XS, VEX, Requires<[HasAVX, HasSSE2]>; + XS, VEX, Requires<[HasAVX]>; } } @@ -1952,11 +1952,11 @@ def VMOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), "vmovdqu\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>, - XS, VEX, Requires<[HasAVX, HasSSE2]>; + XS, VEX, Requires<[HasAVX]>; def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src), "vmovdqu\t{$src, $dst|$dst, $src}", [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>, - XS, VEX, Requires<[HasAVX, HasSSE2]>; + XS, VEX, Requires<[HasAVX]>; } let canFoldAsLoad = 1 in @@ -2064,7 +2064,7 @@ // 128-bit Integer Arithmetic -let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE2] in { +let isAsmParserOnly = 1, Predicates = [HasAVX] in { defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, 1, 0 /*3addr*/>, VEX_4V; defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, 1, 0>, VEX_4V; defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, 1, 0>, VEX_4V; @@ -2154,7 +2154,7 @@ // SSE2 - Packed Integer Logical Instructions //===---------------------------------------------------------------------===// -let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE2] in { +let isAsmParserOnly = 1, Predicates = [HasAVX] in { defm VPSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "vpsllw", int_x86_sse2_psll_w, int_x86_sse2_pslli_w, 0>, VEX_4V; @@ -2286,7 +2286,7 @@ // SSE2 - Packed Integer Comparison Instructions //===---------------------------------------------------------------------===// -let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE2] in { +let isAsmParserOnly = 1, Predicates = [HasAVX] in { defm VPCMPEQB : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_sse2_pcmpeq_b, 1, 0>, VEX_4V; defm VPCMPEQW : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_sse2_pcmpeq_w, 1, @@ -2340,7 +2340,7 @@ // SSE2 - Packed Integer Pack Instructions //===---------------------------------------------------------------------===// -let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE2] in { +let isAsmParserOnly = 1, Predicates = [HasAVX] in { defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128, 0, 0>, VEX_4V; defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128, @@ -2378,7 +2378,7 @@ } } // ExeDomain = SSEPackedInt -let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE2] in { +let isAsmParserOnly = 1, Predicates = [HasAVX] in { let AddedComplexity = 5 in defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, OpSize, VEX; @@ -2426,7 +2426,7 @@ addr:$src2))))]>; } -let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE2] in { +let isAsmParserOnly = 1, Predicates = [HasAVX] in { defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, unpckl, bc_v16i8, 0>, VEX_4V; defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, unpckl, bc_v8i16, @@ -2536,7 +2536,7 @@ } // Extract -let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE2] in +let isAsmParserOnly = 1, Predicates = [HasAVX] in def VPEXTRWri : Ii8<0xC5, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2), "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}", @@ -2549,7 +2549,7 @@ imm:$src2))]>; // Insert -let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE2] in +let isAsmParserOnly = 1, Predicates = [HasAVX] in defm PINSRW : sse2_pinsrw<0>, OpSize, VEX_4V; let Constraints = "$src1 = $dst" in @@ -2741,7 +2741,7 @@ "vmovq\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS, - VEX, Requires<[HasAVX, HasSSE2]>; + VEX, Requires<[HasAVX]>; def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src), "movq\t{$src, $dst|$dst, $src}", [(set VR128:$dst, @@ -2777,7 +2777,7 @@ [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>, - XS, VEX, Requires<[HasAVX, HasSSE2]>; + XS, VEX, Requires<[HasAVX]>; let AddedComplexity = 20 in { def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src), @@ -2800,7 +2800,7 @@ def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "vmovq\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>, - XS, VEX, Requires<[HasAVX, HasSSE2]>; + XS, VEX, Requires<[HasAVX]>; let AddedComplexity = 15 in def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "movq\t{$src, $dst|$dst, $src}", @@ -2812,7 +2812,7 @@ "vmovq\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (v2i64 (X86vzmovl (loadv2i64 addr:$src))))]>, - XS, VEX, Requires<[HasAVX, HasSSE2]>; + XS, VEX, Requires<[HasAVX]>; let AddedComplexity = 20 in { def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), "movq\t{$src, $dst|$dst, $src}", @@ -2883,7 +2883,7 @@ // SSE3 - Conversion Instructions //===---------------------------------------------------------------------===// -let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE3] in { +let isAsmParserOnly = 1, Predicates = [HasAVX] in { def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX; def VCVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), @@ -2917,7 +2917,7 @@ (memopv4f32 addr:$src), (undef)))]>; } -let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE3] in { +let isAsmParserOnly = 1, Predicates = [HasAVX] in { defm VMOVSHDUP : sse3_replicate_sfp<0x16, movshdup, "vmovshdup">, VEX; defm VMOVSLDUP : sse3_replicate_sfp<0x12, movsldup, "vmovsldup">, VEX; } @@ -2936,7 +2936,7 @@ (undef))))]>; } -let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE3] in +let isAsmParserOnly = 1, Predicates = [HasAVX] in defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX; defm MOVDDUP : sse3_replicate_dfp<"movddup">; @@ -3003,7 +3003,7 @@ } -let isAsmParserOnly = 1, Predicates = [HasSSE3, HasAVX], +let isAsmParserOnly = 1, Predicates = [HasAVX], ExeDomain = SSEPackedDouble in { defm VADDSUBPS : sse3_addsub, XD, VEX_4V; @@ -3046,7 +3046,7 @@ !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")), [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (memopv2f64 addr:$src2))))]>; -let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE3] in { +let isAsmParserOnly = 1, Predicates = [HasAVX] in { def VHADDPSrr : S3D_Intrr<0x7C, "vhaddps", int_x86_sse3_hadd_ps, 0>, VEX_4V; def VHADDPSrm : S3D_Intrm<0x7C, "vhaddps", int_x86_sse3_hadd_ps, 0>, VEX_4V; def VHADDPDrr : S3_Intrr <0x7C, "vhaddpd", int_x86_sse3_hadd_pd, 0>, VEX_4V; @@ -3099,7 +3099,7 @@ (bitconvert (mem_frag128 addr:$src))))]>, OpSize; } -let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE3] in { +let isAsmParserOnly = 1, Predicates = [HasAVX] in { defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", memopv8i8, memopv16i8, int_x86_ssse3_pabs_b, int_x86_ssse3_pabs_b_128>, VEX; @@ -3164,7 +3164,7 @@ (bitconvert (memopv16i8 addr:$src2))))]>, OpSize; } -let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE3] in { +let isAsmParserOnly = 1, Predicates = [HasAVX] in { let isCommutable = 0 in { defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw", memopv4i16, memopv8i16, int_x86_ssse3_phadd_w, @@ -3288,7 +3288,7 @@ []>, OpSize; } -let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE3] in +let isAsmParserOnly = 1, Predicates = [HasAVX] in defm VPALIGN : sse3_palign<"vpalignr", 0>, VEX_4V; let Constraints = "$src1 = $dst" in defm PALIGN : sse3_palign<"palignr">; @@ -3634,7 +3634,7 @@ OpSize; } -let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in { +let isAsmParserOnly = 1, Predicates = [HasAVX] in { defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>, VEX; defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>, @@ -3700,7 +3700,7 @@ OpSize; } -let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in { +let isAsmParserOnly = 1, Predicates = [HasAVX] in { defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>, VEX; defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>, @@ -3741,7 +3741,7 @@ OpSize; } -let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in { +let isAsmParserOnly = 1, Predicates = [HasAVX] in { defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>, VEX; defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>, @@ -3783,7 +3783,7 @@ // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst) } -let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in +let isAsmParserOnly = 1, Predicates = [HasAVX] in defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX; defm PEXTRB : SS41I_extract8<0x14, "pextrb">; @@ -3801,7 +3801,7 @@ // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst) } -let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in +let isAsmParserOnly = 1, Predicates = [HasAVX] in defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX; defm PEXTRW : SS41I_extract16<0x15, "pextrw">; @@ -3823,7 +3823,7 @@ addr:$dst)]>, OpSize; } -let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in +let isAsmParserOnly = 1, Predicates = [HasAVX] in defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX; defm PEXTRD : SS41I_extract32<0x16, "pextrd">; @@ -3844,7 +3844,7 @@ addr:$dst)]>, OpSize, REX_W; } -let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in +let isAsmParserOnly = 1, Predicates = [HasAVX] in defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W; defm PEXTRQ : SS41I_extract64<0x16, "pextrq">; @@ -3867,7 +3867,7 @@ addr:$dst)]>, OpSize; } -let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in +let isAsmParserOnly = 1, Predicates = [HasAVX] in defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX; defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">; @@ -3902,7 +3902,7 @@ imm:$src3))]>, OpSize; } -let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in +let isAsmParserOnly = 1, Predicates = [HasAVX] in defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V; let Constraints = "$src1 = $dst" in defm PINSRB : SS41I_insert8<0x20, "pinsrb">; @@ -3928,7 +3928,7 @@ imm:$src3)))]>, OpSize; } -let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in +let isAsmParserOnly = 1, Predicates = [HasAVX] in defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V; let Constraints = "$src1 = $dst" in defm PINSRD : SS41I_insert32<0x22, "pinsrd">; @@ -3954,7 +3954,7 @@ imm:$src3)))]>, OpSize; } -let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in +let isAsmParserOnly = 1, Predicates = [HasAVX] in defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W; let Constraints = "$src1 = $dst" in defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W; @@ -3987,7 +3987,7 @@ let Constraints = "$src1 = $dst" in defm INSERTPS : SS41I_insertf32<0x21, "insertps">; -let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in +let isAsmParserOnly = 1, Predicates = [HasAVX] in defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V; def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3), @@ -4153,7 +4153,7 @@ } // FP round - roundss, roundps, roundsd, roundpd -let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in { +let isAsmParserOnly = 1, Predicates = [HasAVX] in { // Intrinsic form defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", int_x86_sse41_round_ps, int_x86_sse41_round_pd>, @@ -4191,7 +4191,7 @@ (bitconvert (memopv8i16 addr:$src))))]>, OpSize; } -let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in +let isAsmParserOnly = 1, Predicates = [HasAVX] in defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw", int_x86_sse41_phminposuw>, VEX; defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw", @@ -4217,7 +4217,7 @@ (bitconvert (memopv16i8 addr:$src2))))]>, OpSize; } -let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in { +let isAsmParserOnly = 1, Predicates = [HasAVX] in { let isCommutable = 0 in defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw, 0>, VEX_4V; @@ -4284,7 +4284,7 @@ OpSize; } -let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in +let isAsmParserOnly = 1, Predicates = [HasAVX] in defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, 0>, VEX_4V; let Constraints = "$src1 = $dst" in defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32>; @@ -4316,7 +4316,7 @@ OpSize; } -let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in { +let isAsmParserOnly = 1, Predicates = [HasAVX] in { let isCommutable = 0 in { defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps, 0>, VEX_4V; @@ -4345,7 +4345,7 @@ } /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators -let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in { +let isAsmParserOnly = 1, Predicates = [HasAVX] in { multiclass SS41I_quaternary_int_avx opc, string OpcodeStr> { def rr : I, @@ -4413,7 +4413,7 @@ OpSize; } -let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in +let isAsmParserOnly = 1, Predicates = [HasAVX] in def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>, @@ -4447,7 +4447,7 @@ (bitconvert (memopv16i8 addr:$src2))))]>, OpSize; } -let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE42] in +let isAsmParserOnly = 1, Predicates = [HasAVX] in defm VPCMPGTQ : SS42I_binop_rm_int<0x37, "vpcmpgtq", int_x86_sse42_pcmpgtq, 0>, VEX_4V; let Constraints = "$src1 = $dst" in @@ -4477,7 +4477,7 @@ } let Defs = [XMM0, EFLAGS], isAsmParserOnly = 1, - Predicates = [HasAVX, HasSSE42] in { + Predicates = [HasAVX] in { def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2, i8imm:$src3), "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX; @@ -4512,7 +4512,7 @@ OpSize; } -let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE42], +let isAsmParserOnly = 1, Predicates = [HasAVX], Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in { def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src3, i8imm:$src5), @@ -4547,7 +4547,7 @@ } } -let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE42] in { +let isAsmParserOnly = 1, Predicates = [HasAVX] in { defm VPCMPISTRI : SS42AI_pcmpistri, VEX; defm VPCMPISTRIA : SS42AI_pcmpistri, @@ -4586,7 +4586,7 @@ } } -let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE42] in { +let isAsmParserOnly = 1, Predicates = [HasAVX] in { defm VPCMPESTRI : SS42AI_pcmpestri, VEX; defm VPCMPESTRIA : SS42AI_pcmpestri, From echristo at apple.com Mon Jul 12 19:41:42 2010 From: echristo at apple.com (Eric Christopher) Date: Mon, 12 Jul 2010 17:41:42 -0700 Subject: [llvm-commits] [llvm-gcc-4.2] r108206 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp In-Reply-To: <824AB794-5BB3-4863-BE17-D1AAF551A403@apple.com> References: <20100712230256.C6C322A6C12C@llvm.org> <352523D6-C758-4C1F-B9F6-40AAD6F9B43B@apple.com> <824AB794-5BB3-4863-BE17-D1AAF551A403@apple.com> Message-ID: On Jul 12, 2010, at 5:21 PM, Jim Grosbach wrote: > > On Jul 12, 2010, at 5:17 PM, Eric Christopher wrote: > >> >> On Jul 12, 2010, at 5:02 PM, Jim Grosbach wrote: >> >>> The diagnostic needs to be a bit broader than this, actually. It's not just the variable sized allocation that can't be dynamically aligned, but any declaration in the same function. That is, a function which has variable sized stack objects cannot also contain stack objects which require dynamic stack realignment. >> >> I'm not entirely convinced. The original aim would have been to put the code in c-common.c so that when we handle user requested alignment we make the check on the stack size, but without including a lot of llvm bits into c-common.c it's not possible (unless we make the assumption that the gcc/config/arm backend has the right stack alignment :) >> >> That said I should definitely add a quick check for DECL_USER_ALIGN to make sure that the user set it and not something else somewhere. >> >> A quick change to say "requested alignment..." would probably help as well. >> >> Unless I'm missing what you're trying to say (which is altogether possible). >> > > A function can either: > a) contain a variable sized stack-based object, or > b) require dynamic stack realignment. > > If it tries to do both, an error diagnostic should be generated. > > This is target, specific, also. It's true, as far as I know, for all targets currently, but that's not guaranteed to always be the case. *listens to logic* *pounds head on desk* I see what you mean now. Ugh. -eric From bruno.cardoso at gmail.com Mon Jul 12 20:53:31 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 13 Jul 2010 01:53:31 -0000 Subject: [llvm-commits] [llvm] r108223 - in /llvm/trunk: lib/Target/X86/X86InstrSSE.td test/MC/AsmParser/X86/x86_32-encoding.s test/MC/AsmParser/X86/x86_64-encoding.s Message-ID: <20100713015331.7FBDF2A6C12C@llvm.org> Author: bruno Date: Mon Jul 12 20:53:31 2010 New Revision: 108223 URL: http://llvm.org/viewvc/llvm-project?rev=108223&view=rev Log: Add AVX 256-bit unop arithmetic instructions Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=108223&r1=108222&r2=108223&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Jul 12 20:53:31 2010 @@ -1584,23 +1584,6 @@ [(set VR128:$dst, (F32Int sse_load_f32:$src))]>; } -/// sse1_fp_unop_p - SSE1 unops in scalar form. -multiclass sse1_fp_unop_p opc, string OpcodeStr, - SDNode OpNode, Intrinsic V4F32Int> { - def PSr : PSI; - def PSm : PSI; - def PSr_Int : PSI; - def PSm_Int : PSI; -} - /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form. multiclass sse1_fp_unop_s_avx opc, string OpcodeStr, SDNode OpNode, Intrinsic F32Int> { @@ -1621,6 +1604,38 @@ "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>; } +/// sse1_fp_unop_p - SSE1 unops in packed form. +multiclass sse1_fp_unop_p opc, string OpcodeStr, SDNode OpNode> { + def PSr : PSI; + def PSm : PSI; +} + +/// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form. +multiclass sse1_fp_unop_p_y opc, string OpcodeStr, SDNode OpNode> { + def PSYr : PSI; + def PSYm : PSI; +} + +/// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms. +multiclass sse1_fp_unop_p_int opc, string OpcodeStr, + Intrinsic V4F32Int> { + def PSr_Int : PSI; + def PSm_Int : PSI; +} + + /// sse2_fp_unop_s - SSE2 unops in scalar form. multiclass sse2_fp_unop_s opc, string OpcodeStr, SDNode OpNode, Intrinsic F64Int> { @@ -1640,23 +1655,6 @@ [(set VR128:$dst, (F64Int sse_load_f64:$src))]>; } -/// sse2_fp_unop_p - SSE2 unops in vector forms. -multiclass sse2_fp_unop_p opc, string OpcodeStr, - SDNode OpNode, Intrinsic V2F64Int> { - def PDr : PDI; - def PDm : PDI; - def PDr_Int : PDI; - def PDm_Int : PDI; -} - /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form. multiclass sse2_fp_unop_s_avx opc, string OpcodeStr, SDNode OpNode, Intrinsic F64Int> { @@ -1677,44 +1675,79 @@ []>; } -let isAsmParserOnly = 1 in { - // Square root. - let Predicates = [HasAVX] in { - defm VSQRT : sse2_fp_unop_s_avx<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>, - VEX_4V; +/// sse2_fp_unop_p - SSE2 unops in vector forms. +multiclass sse2_fp_unop_p opc, string OpcodeStr, + SDNode OpNode> { + def PDr : PDI; + def PDm : PDI; +} - defm VSQRT : sse2_fp_unop_p<0x51, "vsqrt", fsqrt, int_x86_sse2_sqrt_pd>, VEX; - } +/// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms. +multiclass sse2_fp_unop_p_y opc, string OpcodeStr, SDNode OpNode> { + def PDYr : PDI; + def PDYm : PDI; +} + +/// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms. +multiclass sse2_fp_unop_p_int opc, string OpcodeStr, + Intrinsic V2F64Int> { + def PDr_Int : PDI; + def PDm_Int : PDI; +} - let Predicates = [HasAVX] in { +let isAsmParserOnly = 1, Predicates = [HasAVX] in { + // Square root. defm VSQRT : sse1_fp_unop_s_avx<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>, - VEX_4V; - defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt, int_x86_sse_sqrt_ps>, VEX; + sse2_fp_unop_s_avx<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>, + VEX_4V; + + defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt>, + sse2_fp_unop_p<0x51, "vsqrt", fsqrt>, + sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt>, + sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt>, + VEX; + // Reciprocal approximations. Note that these typically require refinement // in order to obtain suitable precision. defm VRSQRT : sse1_fp_unop_s_avx<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss>, VEX_4V; - defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt, int_x86_sse_rsqrt_ps>, - VEX; + defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt>, + sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt>, VEX; + defm VRCP : sse1_fp_unop_s_avx<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>, VEX_4V; - defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp, int_x86_sse_rcp_ps>, - VEX; - } + defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp>, + sse1_fp_unop_p_y<0x53, "vrcp", X86frcp>, VEX; } // Square root. defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>, - sse1_fp_unop_p<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ps>, + sse1_fp_unop_p<0x51, "sqrt", fsqrt>, + sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps>, sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>, - sse2_fp_unop_p<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_pd>; + sse2_fp_unop_p<0x51, "sqrt", fsqrt>, + sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd>; // Reciprocal approximations. Note that these typically require refinement // in order to obtain suitable precision. defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss>, - sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ps>; + sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt>, + sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps>; defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>, - sse1_fp_unop_p<0x53, "rcp", X86frcp, int_x86_sse_rcp_ps>; + sse1_fp_unop_p<0x53, "rcp", X86frcp>, + sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps>; // There is no f64 version of the reciprocal approximation instructions. Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s?rev=108223&r1=108222&r2=108223&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s Mon Jul 12 20:53:31 2010 @@ -12502,3 +12502,35 @@ // CHECK: encoding: [0xc5,0xdd,0x59,0x30] vmulpd (%eax), %ymm4, %ymm6 +// CHECK: vsqrtpd %ymm1, %ymm2 +// CHECK: encoding: [0xc5,0xfd,0x51,0xd1] + vsqrtpd %ymm1, %ymm2 + +// CHECK: vsqrtpd (%eax), %ymm2 +// CHECK: encoding: [0xc5,0xfd,0x51,0x10] + vsqrtpd (%eax), %ymm2 + +// CHECK: vsqrtps %ymm1, %ymm2 +// CHECK: encoding: [0xc5,0xfc,0x51,0xd1] + vsqrtps %ymm1, %ymm2 + +// CHECK: vsqrtps (%eax), %ymm2 +// CHECK: encoding: [0xc5,0xfc,0x51,0x10] + vsqrtps (%eax), %ymm2 + +// CHECK: vrsqrtps %ymm1, %ymm2 +// CHECK: encoding: [0xc5,0xfc,0x52,0xd1] + vrsqrtps %ymm1, %ymm2 + +// CHECK: vrsqrtps (%eax), %ymm2 +// CHECK: encoding: [0xc5,0xfc,0x52,0x10] + vrsqrtps (%eax), %ymm2 + +// CHECK: vrcpps %ymm1, %ymm2 +// CHECK: encoding: [0xc5,0xfc,0x53,0xd1] + vrcpps %ymm1, %ymm2 + +// CHECK: vrcpps (%eax), %ymm2 +// CHECK: encoding: [0xc5,0xfc,0x53,0x10] + vrcpps (%eax), %ymm2 + Modified: llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s?rev=108223&r1=108222&r2=108223&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s Mon Jul 12 20:53:31 2010 @@ -2576,3 +2576,35 @@ // CHECK: encoding: [0xc5,0xdd,0x59,0x30] vmulpd (%rax), %ymm4, %ymm6 +// CHECK: vsqrtpd %ymm11, %ymm12 +// CHECK: encoding: [0xc4,0x41,0x7d,0x51,0xe3] + vsqrtpd %ymm11, %ymm12 + +// CHECK: vsqrtpd (%rax), %ymm12 +// CHECK: encoding: [0xc5,0x7d,0x51,0x20] + vsqrtpd (%rax), %ymm12 + +// CHECK: vsqrtps %ymm11, %ymm12 +// CHECK: encoding: [0xc4,0x41,0x7c,0x51,0xe3] + vsqrtps %ymm11, %ymm12 + +// CHECK: vsqrtps (%rax), %ymm12 +// CHECK: encoding: [0xc5,0x7c,0x51,0x20] + vsqrtps (%rax), %ymm12 + +// CHECK: vrsqrtps %ymm11, %ymm12 +// CHECK: encoding: [0xc4,0x41,0x7c,0x52,0xe3] + vrsqrtps %ymm11, %ymm12 + +// CHECK: vrsqrtps (%rax), %ymm12 +// CHECK: encoding: [0xc5,0x7c,0x52,0x20] + vrsqrtps (%rax), %ymm12 + +// CHECK: vrcpps %ymm11, %ymm12 +// CHECK: encoding: [0xc4,0x41,0x7c,0x53,0xe3] + vrcpps %ymm11, %ymm12 + +// CHECK: vrcpps (%rax), %ymm12 +// CHECK: encoding: [0xc5,0x7c,0x53,0x20] + vrcpps (%rax), %ymm12 + From bruno.cardoso at gmail.com Mon Jul 12 21:38:35 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 13 Jul 2010 02:38:35 -0000 Subject: [llvm-commits] [llvm] r108224 - in /llvm/trunk: lib/Target/X86/X86InstrSSE.td test/MC/AsmParser/X86/x86_32-encoding.s test/MC/AsmParser/X86/x86_64-encoding.s Message-ID: <20100713023835.593402A6C12C@llvm.org> Author: bruno Date: Mon Jul 12 21:38:35 2010 New Revision: 108224 URL: http://llvm.org/viewvc/llvm-project?rev=108224&view=rev Log: Add AVX 256-bit packed logical forms Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=108224&r1=108223&r2=108224&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Jul 12 21:38:35 2010 @@ -1422,6 +1422,25 @@ } } +/// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms +/// +let isAsmParserOnly = 1 in { +multiclass sse12_fp_packed_logical_y opc, string OpcodeStr> { + defm PSY : sse12_fp_packed_logical_rm, VEX_4V; + + defm PDY : sse12_fp_packed_logical_rm, OpSize, VEX_4V; +} +} + +// AVX 256-bit packed logical ops forms +defm VAND : sse12_fp_packed_logical_y<0x54, "and">; +defm VOR : sse12_fp_packed_logical_y<0x56, "or">; +defm VXOR : sse12_fp_packed_logical_y<0x57, "xor">; +let isCommutable = 0 in + defm VANDN : sse12_fp_packed_logical_y<0x55, "andn">; + defm AND : sse12_fp_packed_logical<0x54, "and", and>; defm OR : sse12_fp_packed_logical<0x56, "or", or>; defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>; Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s?rev=108224&r1=108223&r2=108224&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s Mon Jul 12 21:38:35 2010 @@ -12534,3 +12534,67 @@ // CHECK: encoding: [0xc5,0xfc,0x53,0x10] vrcpps (%eax), %ymm2 +// CHECK: vandps %ymm2, %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x54,0xf2] + vandps %ymm2, %ymm4, %ymm6 + +// CHECK: vandpd %ymm2, %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x54,0xf2] + vandpd %ymm2, %ymm4, %ymm6 + +// CHECK: vandps -4(%ebx,%ecx,8), %ymm2, %ymm5 +// CHECK: encoding: [0xc5,0xec,0x54,0x6c,0xcb,0xfc] + vandps -4(%ebx,%ecx,8), %ymm2, %ymm5 + +// CHECK: vandpd -4(%ebx,%ecx,8), %ymm2, %ymm5 +// CHECK: encoding: [0xc5,0xed,0x54,0x6c,0xcb,0xfc] + vandpd -4(%ebx,%ecx,8), %ymm2, %ymm5 + +// CHECK: vorps %ymm2, %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x56,0xf2] + vorps %ymm2, %ymm4, %ymm6 + +// CHECK: vorpd %ymm2, %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x56,0xf2] + vorpd %ymm2, %ymm4, %ymm6 + +// CHECK: vorps -4(%ebx,%ecx,8), %ymm2, %ymm5 +// CHECK: encoding: [0xc5,0xec,0x56,0x6c,0xcb,0xfc] + vorps -4(%ebx,%ecx,8), %ymm2, %ymm5 + +// CHECK: vorpd -4(%ebx,%ecx,8), %ymm2, %ymm5 +// CHECK: encoding: [0xc5,0xed,0x56,0x6c,0xcb,0xfc] + vorpd -4(%ebx,%ecx,8), %ymm2, %ymm5 + +// CHECK: vxorps %ymm2, %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x57,0xf2] + vxorps %ymm2, %ymm4, %ymm6 + +// CHECK: vxorpd %ymm2, %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x57,0xf2] + vxorpd %ymm2, %ymm4, %ymm6 + +// CHECK: vxorps -4(%ebx,%ecx,8), %ymm2, %ymm5 +// CHECK: encoding: [0xc5,0xec,0x57,0x6c,0xcb,0xfc] + vxorps -4(%ebx,%ecx,8), %ymm2, %ymm5 + +// CHECK: vxorpd -4(%ebx,%ecx,8), %ymm2, %ymm5 +// CHECK: encoding: [0xc5,0xed,0x57,0x6c,0xcb,0xfc] + vxorpd -4(%ebx,%ecx,8), %ymm2, %ymm5 + +// CHECK: vandnps %ymm2, %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdc,0x55,0xf2] + vandnps %ymm2, %ymm4, %ymm6 + +// CHECK: vandnpd %ymm2, %ymm4, %ymm6 +// CHECK: encoding: [0xc5,0xdd,0x55,0xf2] + vandnpd %ymm2, %ymm4, %ymm6 + +// CHECK: vandnps -4(%ebx,%ecx,8), %ymm2, %ymm5 +// CHECK: encoding: [0xc5,0xec,0x55,0x6c,0xcb,0xfc] + vandnps -4(%ebx,%ecx,8), %ymm2, %ymm5 + +// CHECK: vandnpd -4(%ebx,%ecx,8), %ymm2, %ymm5 +// CHECK: encoding: [0xc5,0xed,0x55,0x6c,0xcb,0xfc] + vandnpd -4(%ebx,%ecx,8), %ymm2, %ymm5 + Modified: llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s?rev=108224&r1=108223&r2=108224&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s Mon Jul 12 21:38:35 2010 @@ -2608,3 +2608,67 @@ // CHECK: encoding: [0xc5,0x7c,0x53,0x20] vrcpps (%rax), %ymm12 +// CHECK: vandps %ymm12, %ymm14, %ymm11 +// CHECK: encoding: [0xc4,0x41,0x0c,0x54,0xdc] + vandps %ymm12, %ymm14, %ymm11 + +// CHECK: vandpd %ymm12, %ymm14, %ymm11 +// CHECK: encoding: [0xc4,0x41,0x0d,0x54,0xdc] + vandpd %ymm12, %ymm14, %ymm11 + +// CHECK: vandps -4(%rbx,%rcx,8), %ymm12, %ymm10 +// CHECK: encoding: [0xc5,0x1c,0x54,0x54,0xcb,0xfc] + vandps -4(%rbx,%rcx,8), %ymm12, %ymm10 + +// CHECK: vandpd -4(%rbx,%rcx,8), %ymm12, %ymm10 +// CHECK: encoding: [0xc5,0x1d,0x54,0x54,0xcb,0xfc] + vandpd -4(%rbx,%rcx,8), %ymm12, %ymm10 + +// CHECK: vorps %ymm12, %ymm14, %ymm11 +// CHECK: encoding: [0xc4,0x41,0x0c,0x56,0xdc] + vorps %ymm12, %ymm14, %ymm11 + +// CHECK: vorpd %ymm12, %ymm14, %ymm11 +// CHECK: encoding: [0xc4,0x41,0x0d,0x56,0xdc] + vorpd %ymm12, %ymm14, %ymm11 + +// CHECK: vorps -4(%rbx,%rcx,8), %ymm12, %ymm10 +// CHECK: encoding: [0xc5,0x1c,0x56,0x54,0xcb,0xfc] + vorps -4(%rbx,%rcx,8), %ymm12, %ymm10 + +// CHECK: vorpd -4(%rbx,%rcx,8), %ymm12, %ymm10 +// CHECK: encoding: [0xc5,0x1d,0x56,0x54,0xcb,0xfc] + vorpd -4(%rbx,%rcx,8), %ymm12, %ymm10 + +// CHECK: vxorps %ymm12, %ymm14, %ymm11 +// CHECK: encoding: [0xc4,0x41,0x0c,0x57,0xdc] + vxorps %ymm12, %ymm14, %ymm11 + +// CHECK: vxorpd %ymm12, %ymm14, %ymm11 +// CHECK: encoding: [0xc4,0x41,0x0d,0x57,0xdc] + vxorpd %ymm12, %ymm14, %ymm11 + +// CHECK: vxorps -4(%rbx,%rcx,8), %ymm12, %ymm10 +// CHECK: encoding: [0xc5,0x1c,0x57,0x54,0xcb,0xfc] + vxorps -4(%rbx,%rcx,8), %ymm12, %ymm10 + +// CHECK: vxorpd -4(%rbx,%rcx,8), %ymm12, %ymm10 +// CHECK: encoding: [0xc5,0x1d,0x57,0x54,0xcb,0xfc] + vxorpd -4(%rbx,%rcx,8), %ymm12, %ymm10 + +// CHECK: vandnps %ymm12, %ymm14, %ymm11 +// CHECK: encoding: [0xc4,0x41,0x0c,0x55,0xdc] + vandnps %ymm12, %ymm14, %ymm11 + +// CHECK: vandnpd %ymm12, %ymm14, %ymm11 +// CHECK: encoding: [0xc4,0x41,0x0d,0x55,0xdc] + vandnpd %ymm12, %ymm14, %ymm11 + +// CHECK: vandnps -4(%rbx,%rcx,8), %ymm12, %ymm10 +// CHECK: encoding: [0xc5,0x1c,0x55,0x54,0xcb,0xfc] + vandnps -4(%rbx,%rcx,8), %ymm12, %ymm10 + +// CHECK: vandnpd -4(%rbx,%rcx,8), %ymm12, %ymm10 +// CHECK: encoding: [0xc5,0x1d,0x55,0x54,0xcb,0xfc] + vandnpd -4(%rbx,%rcx,8), %ymm12, %ymm10 + From echristo at apple.com Mon Jul 12 22:02:18 2010 From: echristo at apple.com (Eric Christopher) Date: Tue, 13 Jul 2010 03:02:18 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r108225 - in /llvm-gcc-4.2/trunk/gcc: llvm-convert.cpp llvm-internal.h Message-ID: <20100713030218.4EFCB2A6C12C@llvm.org> Author: echristo Date: Mon Jul 12 22:02:18 2010 New Revision: 108225 URL: http://llvm.org/viewvc/llvm-project?rev=108225&view=rev Log: Rework previous patch for vlas and stack alignment. Now checks if we may dynamically realign the stack and works for c++ which is lowered separately. Removed the dead variable elimination since vlas are not lowered through some of this mechanism and we'd miss them otherwise. Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp llvm-gcc-4.2/trunk/gcc/llvm-internal.h Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=108225&r1=108224&r2=108225&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Mon Jul 12 22:02:18 2010 @@ -185,6 +185,8 @@ } AllocaInsertionPoint = 0; + GreatestAlignment = TheTarget->getFrameInfo()->getStackAlignment(); + SeenVLA = NULL; ExceptionValue = 0; ExceptionSelectorValue = 0; @@ -812,6 +814,15 @@ } UniquedValues.clear(); + // If we've seen a vla in this function and we'll possibly need to + // either dynamically realign or this is greater than the maximum stack + // alignment, error out now. This is here so we don't output an error + // every time we see a variable. + if (SeenVLA && + GreatestAlignment > TheTarget->getFrameInfo()->getStackAlignment()) + error ("alignment for %q+D conflicts with either a dynamically " + "realigned stack or the maximum stack alignment", SeenVLA); + return Fn; } @@ -1751,25 +1762,20 @@ TREE_STATIC(decl) || DECL_EXTERNAL(decl) || type == error_mark_node) return; + // If we've seen a VLA remember it in case we try to dynamically realign + // the stack or request an alignment greater than the default stack + // alignment. + // We're basing the VLA on an expression that is an array that doesn't have + // a constant decl size as below. + if (TREE_CODE(type) == ARRAY_TYPE && + DECL_SIZE(decl) != 0 && TREE_CODE(DECL_SIZE_UNIT(decl)) != INTEGER_CST) + SeenVLA = decl; + // Gimple temporaries are handled specially: their DECL_LLVM is set when the // definition is encountered. if (isGimpleTemporary(decl)) return; - /* If this is a vla type and we requested an alignment greater than the stack - alignment, error out since we're not going to dynamically realign - variable length array allocations. We're placing this here instead of - later in case it's a relatively unused variable. */ - if (TREE_CODE (type) == ARRAY_TYPE && C_TYPE_VARIABLE_SIZE (type) && - DECL_ALIGN(decl)/8u > TheTarget->getFrameInfo()->getStackAlignment()) - error ("alignment for %q+D is greater than the stack alignment, " - "we cannot guarantee the alignment.", decl); - - // If this is just the rotten husk of a variable that the gimplifier - // eliminated all uses of, but is preserving for debug info, ignore it. - if (TREE_CODE(decl) == VAR_DECL && DECL_VALUE_EXPR(decl)) - return; - const Type *Ty; // Type to allocate Value *Size = 0; // Amount to alloca (null for 1) @@ -1832,6 +1838,10 @@ } AI->setAlignment(Alignment); + + // Record the alignment if it's the largest we've seen. + if (Alignment > GreatestAlignment) + GreatestAlignment = Alignment; SET_DECL_LLVM(decl, AI); Modified: llvm-gcc-4.2/trunk/gcc/llvm-internal.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-internal.h?rev=108225&r1=108224&r2=108225&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-internal.h (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-internal.h Mon Jul 12 22:02:18 2010 @@ -299,6 +299,15 @@ /// unique. These can be simplified once the function has been emitted. std::vector UniquedValues; + /// GreatestAlignment - The largest alignment seen on a variable declaration. + /// With stack realignment the TargetMachine's frame info won't be sufficient + /// to determine the greatest stack alignment. + unsigned GreatestAlignment; + + /// SeenVLA - Whether or not we have a VLA in the current function. This + /// and dynamic stack realignment currently conflict so we'll use this to + /// warn later. + tree_node *SeenVLA; //===---------------------- Exception Handling --------------------------===// /// LandingPads - The landing pad for a given EH region. From sabre at nondot.org Mon Jul 12 22:46:58 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 12 Jul 2010 20:46:58 -0700 Subject: [llvm-commits] [llvm] r108109 - /llvm/trunk/lib/CodeGen/MachineLICM.cpp In-Reply-To: <271FD80E-5C28-4114-8430-8E7053E9DEFA@apple.com> References: <20100712000035.393982A6C12C@llvm.org> <5470C984-D21B-4C3F-860C-D7506AFBFAAB@apple.com> <3434519D-9F54-4516-A09A-FAE224A0E8C5@nondot.org> <01AEDF63-186E-4CA3-BCA9-0686BFC66E3A@2pi.dk> <271FD80E-5C28-4114-8430-8E7053E9DEFA@apple.com> Message-ID: On Jul 12, 2010, at 4:53 PM, Evan Cheng wrote: >> I can't imagine why we would want to keep IMPLICIT_DEFs around, but I can imagine ProcessImplicitDefs getting confused because the code is not SSA. >> >> > > > RA, or rather ProcessImplicitDef pass, turn them into trivial short live ranges when it's possible. But it does miss some cases. It's relatively rare but it does happen. I don't think that LICM should be complicated by a deficiency handling implicit defs. -Chris From evan.cheng at apple.com Mon Jul 12 22:55:37 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 12 Jul 2010 20:55:37 -0700 Subject: [llvm-commits] [llvm] r108109 - /llvm/trunk/lib/CodeGen/MachineLICM.cpp In-Reply-To: References: <20100712000035.393982A6C12C@llvm.org> <5470C984-D21B-4C3F-860C-D7506AFBFAAB@apple.com> <3434519D-9F54-4516-A09A-FAE224A0E8C5@nondot.org> <01AEDF63-186E-4CA3-BCA9-0686BFC66E3A@2pi.dk> <271FD80E-5C28-4114-8430-8E7053E9DEFA@apple.com> Message-ID: <7087D555-AF3C-47AA-981D-02FC19B18B96@apple.com> On Jul 12, 2010, at 8:46 PM, Chris Lattner wrote: > > On Jul 12, 2010, at 4:53 PM, Evan Cheng wrote: > >>> I can't imagine why we would want to keep IMPLICIT_DEFs around, but I can imagine ProcessImplicitDefs getting confused because the code is not SSA. >>> >>> >> >> >> RA, or rather ProcessImplicitDef pass, turn them into trivial short live ranges when it's possible. But it does miss some cases. It's relatively rare but it does happen. > > I don't think that LICM should be complicated by a deficiency handling implicit defs. I agree. But it's already neutered by register allocator deficiency. We are only hoisting some of the loop invariants for fear of increasing register pressure. We should remove all such restrictions only after live range splitting work lands. Evan > > -Chris From sabre at nondot.org Mon Jul 12 22:58:49 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 12 Jul 2010 20:58:49 -0700 Subject: [llvm-commits] [llvm] r108109 - /llvm/trunk/lib/CodeGen/MachineLICM.cpp In-Reply-To: <7087D555-AF3C-47AA-981D-02FC19B18B96@apple.com> References: <20100712000035.393982A6C12C@llvm.org> <5470C984-D21B-4C3F-860C-D7506AFBFAAB@apple.com> <3434519D-9F54-4516-A09A-FAE224A0E8C5@nondot.org> <01AEDF63-186E-4CA3-BCA9-0686BFC66E3A@2pi.dk> <271FD80E-5C28-4114-8430-8E7053E9DEFA@apple.com> <7087D555-AF3C-47AA-981D-02FC19B18B96@apple.com> Message-ID: On Jul 12, 2010, at 8:55 PM, Evan Cheng wrote: >>> RA, or rather ProcessImplicitDef pass, turn them into trivial short live ranges when it's possible. But it does miss some cases. It's relatively rare but it does happen. >> >> I don't think that LICM should be complicated by a deficiency handling implicit defs. > > I agree. But it's already neutered by register allocator deficiency. We are only hoisting some of the loop invariants for fear of increasing register pressure. We should remove all such restrictions only after live range splitting work lands. I don't see what that has to do with hoisting implicit defs. -Chris From evan.cheng at apple.com Mon Jul 12 23:10:48 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 12 Jul 2010 21:10:48 -0700 Subject: [llvm-commits] [llvm] r108109 - /llvm/trunk/lib/CodeGen/MachineLICM.cpp In-Reply-To: References: <20100712000035.393982A6C12C@llvm.org> <5470C984-D21B-4C3F-860C-D7506AFBFAAB@apple.com> <3434519D-9F54-4516-A09A-FAE224A0E8C5@nondot.org> <01AEDF63-186E-4CA3-BCA9-0686BFC66E3A@2pi.dk> <271FD80E-5C28-4114-8430-8E7053E9DEFA@apple.com> <7087D555-AF3C-47AA-981D-02FC19B18B96@apple.com> Message-ID: On Jul 12, 2010, at 8:58 PM, Chris Lattner wrote: > > On Jul 12, 2010, at 8:55 PM, Evan Cheng wrote: > >>>> RA, or rather ProcessImplicitDef pass, turn them into trivial short live ranges when it's possible. But it does miss some cases. It's relatively rare but it does happen. >>> >>> I don't think that LICM should be complicated by a deficiency handling implicit defs. >> >> I agree. But it's already neutered by register allocator deficiency. We are only hoisting some of the loop invariants for fear of increasing register pressure. We should remove all such restrictions only after live range splitting work lands. > > I don't see what that has to do with hoisting implicit defs. It's the same issue. It can lead to increased register pressure. You guys should look at how implicit defs are being handled before jumping to conclusions. There are legitimate cases where implicit defs are not easily removed. Evan > > -Chris From sabre at nondot.org Mon Jul 12 23:14:59 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 12 Jul 2010 21:14:59 -0700 Subject: [llvm-commits] [llvm] r108109 - /llvm/trunk/lib/CodeGen/MachineLICM.cpp In-Reply-To: References: <20100712000035.393982A6C12C@llvm.org> <5470C984-D21B-4C3F-860C-D7506AFBFAAB@apple.com> <3434519D-9F54-4516-A09A-FAE224A0E8C5@nondot.org> <01AEDF63-186E-4CA3-BCA9-0686BFC66E3A@2pi.dk> <271FD80E-5C28-4114-8430-8E7053E9DEFA@apple.com> <7087D555-AF3C-47AA-981D-02FC19B18B96@apple.com> Message-ID: <9EE0AD47-2443-4D1D-9564-721369F5FC78@nondot.org> On Jul 12, 2010, at 9:10 PM, Evan Cheng wrote: > > On Jul 12, 2010, at 8:58 PM, Chris Lattner wrote: > >> >> On Jul 12, 2010, at 8:55 PM, Evan Cheng wrote: >> >>>>> RA, or rather ProcessImplicitDef pass, turn them into trivial short live ranges when it's possible. But it does miss some cases. It's relatively rare but it does happen. >>>> >>>> I don't think that LICM should be complicated by a deficiency handling implicit defs. >>> >>> I agree. But it's already neutered by register allocator deficiency. We are only hoisting some of the loop invariants for fear of increasing register pressure. We should remove all such restrictions only after live range splitting work lands. >> >> I don't see what that has to do with hoisting implicit defs. > > It's the same issue. It can lead to increased register pressure. You guys should look at how implicit defs are being handled before jumping to conclusions. There are legitimate cases where implicit defs are not easily removed. You just said that this is "relatively rare". -Chris From sabre at nondot.org Mon Jul 12 23:23:55 2010 From: sabre at nondot.org (Chris Lattner) Date: Tue, 13 Jul 2010 04:23:55 -0000 Subject: [llvm-commits] [llvm] r108226 - in /llvm/trunk: lib/Target/X86/Disassembler/X86Disassembler.cpp test/MC/Disassembler/simple-tests.txt Message-ID: <20100713042355.477542A6C12C@llvm.org> Author: lattner Date: Mon Jul 12 23:23:55 2010 New Revision: 108226 URL: http://llvm.org/viewvc/llvm-project?rev=108226&view=rev Log: my work on adding segment registers to LEA missed the disassembler. Remove some code from the disassembler to compensate, unbreaking disassembly of lea's. Modified: llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp llvm/trunk/test/MC/Disassembler/simple-tests.txt Modified: llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp?rev=108226&r1=108225&r2=108226&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp (original) +++ llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp Mon Jul 12 23:23:55 2010 @@ -252,13 +252,8 @@ /// @param mcInst - The MCInst to append to. /// @param insn - The instruction to extract Mod, R/M, and SIB fields /// from. -/// @param sr - Whether or not to emit the segment register. The -/// LEA instruction does not expect a segment-register -/// operand. /// @return - 0 on success; nonzero otherwise -static bool translateRMMemory(MCInst &mcInst, - InternalInstruction &insn, - bool sr) { +static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn) { // Addresses in an MCInst are represented as five operands: // 1. basereg (register) The R/M base, or (if there is a SIB) the // SIB base @@ -385,10 +380,7 @@ mcInst.addOperand(scaleAmount); mcInst.addOperand(indexReg); mcInst.addOperand(displacement); - - if (sr) - mcInst.addOperand(segmentReg); - + mcInst.addOperand(segmentReg); return false; } @@ -439,9 +431,8 @@ case TYPE_M1616: case TYPE_M1632: case TYPE_M1664: - return translateRMMemory(mcInst, insn, true); case TYPE_LEA: - return translateRMMemory(mcInst, insn, false); + return translateRMMemory(mcInst, insn); } } Modified: llvm/trunk/test/MC/Disassembler/simple-tests.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/simple-tests.txt?rev=108226&r1=108225&r2=108226&view=diff ============================================================================== --- llvm/trunk/test/MC/Disassembler/simple-tests.txt (original) +++ llvm/trunk/test/MC/Disassembler/simple-tests.txt Mon Jul 12 23:23:55 2010 @@ -57,3 +57,6 @@ # CHECK: movq %cr0, %rcx 0x0f 0x20 0xc1 + +# CHECK: leal 4(%rsp), %ecx +0x8d 0x4c 0x24 0x04 \ No newline at end of file From bob.wilson at apple.com Mon Jul 12 23:44:35 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 13 Jul 2010 04:44:35 -0000 Subject: [llvm-commits] [llvm] r108227 - in /llvm/trunk/lib/Target/ARM: ARMAddressingModes.h ARMISelLowering.cpp AsmPrinter/ARMAsmPrinter.cpp AsmPrinter/ARMInstPrinter.cpp Message-ID: <20100713044435.2CFB92A6C12C@llvm.org> Author: bwilson Date: Mon Jul 12 23:44:34 2010 New Revision: 108227 URL: http://llvm.org/viewvc/llvm-project?rev=108227&view=rev Log: Move NEON "modified immediate" encode/decode into ARMAddressingModes.h to avoid replicated code. Modified: llvm/trunk/lib/Target/ARM/ARMAddressingModes.h llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMAddressingModes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAddressingModes.h?rev=108227&r1=108226&r2=108227&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAddressingModes.h (original) +++ llvm/trunk/lib/Target/ARM/ARMAddressingModes.h Mon Jul 12 23:44:34 2010 @@ -523,6 +523,68 @@ // Valid alignments are: 0, 8, 16, and 32 bytes, depending on the specific // instruction. + //===--------------------------------------------------------------------===// + // NEON Modified Immediates + //===--------------------------------------------------------------------===// + // + // Several NEON instructions (e.g., VMOV) take a "modified immediate" + // vector operand, where a small immediate encoded in the instruction + // specifies a full NEON vector value. These modified immediates are + // represented here as encoded integers. The low 8 bits hold the immediate + // value; bit 12 holds the "Op" field of the instruction, and bits 11-8 hold + // the "Cmode" field of the instruction. The interfaces below treat the + // Op and Cmode values as a single 5-bit value. + + static inline unsigned createNEONModImm(unsigned OpCmode, unsigned Val) { + return (OpCmode << 8) | Val; + } + static inline unsigned getNEONModImmOpCmode(unsigned ModImm) { + return (ModImm >> 8) & 0x1f; + } + static inline unsigned getNEONModImmVal(unsigned ModImm) { + return ModImm & 0xff; + } + + /// decodeNEONModImm - Decode a NEON modified immediate value into the + /// element value and the element size in bits. (If the element size is + /// smaller than the vector, it is splatted into all the elements.) + static inline uint64_t decodeNEONModImm(unsigned ModImm, unsigned &EltBits) { + unsigned OpCmode = getNEONModImmOpCmode(ModImm); + unsigned Imm8 = getNEONModImmVal(ModImm); + uint64_t Val = 0; + + if (OpCmode == 0xe) { + // 8-bit vector elements + Val = Imm8; + EltBits = 8; + } else if ((OpCmode & 0xc) == 0x8) { + // 16-bit vector elements + unsigned ByteNum = (OpCmode & 0x6) >> 1; + Val = Imm8 << (8 * ByteNum); + EltBits = 16; + } else if ((OpCmode & 0x8) == 0) { + // 32-bit vector elements, zero with one byte set + unsigned ByteNum = (OpCmode & 0x6) >> 1; + Val = Imm8 << (8 * ByteNum); + EltBits = 32; + } else if ((OpCmode & 0xe) == 0xc) { + // 32-bit vector elements, one byte with low bits set + unsigned ByteNum = 1 + (OpCmode & 0x1); + Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum))); + EltBits = 32; + } else if (OpCmode == 0x1e) { + // 64-bit vector elements + for (unsigned ByteNum = 0; ByteNum < 8; ++ByteNum) { + if ((ModImm >> ByteNum) & 1) + Val |= (uint64_t)0xff << (8 * ByteNum); + } + EltBits = 64; + } else { + assert(false && "Unsupported NEON immediate"); + } + return Val; + } + } // end namespace ARM_AM } // end namespace llvm Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=108227&r1=108226&r2=108227&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Mon Jul 12 23:44:34 2010 @@ -2851,13 +2851,11 @@ /// isNEONModifiedImm - Check if the specified splat value corresponds to a /// valid vector constant for a NEON instruction with a "modified immediate" /// operand (e.g., VMOV). If so, return either the constant being -/// splatted or the encoded value, depending on the DoEncode parameter. The -/// format of the encoded value is: bit12=Op, bits11-8=Cmode, -/// bits7-0=Immediate. +/// splatted or the encoded value, depending on the DoEncode parameter. static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef, unsigned SplatBitSize, SelectionDAG &DAG, bool isVMOV, bool DoEncode) { - unsigned Op, Cmode, Imm; + unsigned OpCmode, Imm; EVT VT; // SplatBitSize is set to the smallest size that splats the vector, so a @@ -2868,12 +2866,11 @@ if (SplatBits == 0) SplatBitSize = 32; - Op = 0; switch (SplatBitSize) { case 8: // Any 1-byte value is OK. Op=0, Cmode=1110. assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big"); - Cmode = 0xe; + OpCmode = 0xe; Imm = SplatBits; VT = MVT::i8; break; @@ -2883,13 +2880,13 @@ VT = MVT::i16; if ((SplatBits & ~0xff) == 0) { // Value = 0x00nn: Op=x, Cmode=100x. - Cmode = 0x8; + OpCmode = 0x8; Imm = SplatBits; break; } if ((SplatBits & ~0xff00) == 0) { // Value = 0xnn00: Op=x, Cmode=101x. - Cmode = 0xa; + OpCmode = 0xa; Imm = SplatBits >> 8; break; } @@ -2903,25 +2900,25 @@ VT = MVT::i32; if ((SplatBits & ~0xff) == 0) { // Value = 0x000000nn: Op=x, Cmode=000x. - Cmode = 0; + OpCmode = 0; Imm = SplatBits; break; } if ((SplatBits & ~0xff00) == 0) { // Value = 0x0000nn00: Op=x, Cmode=001x. - Cmode = 0x2; + OpCmode = 0x2; Imm = SplatBits >> 8; break; } if ((SplatBits & ~0xff0000) == 0) { // Value = 0x00nn0000: Op=x, Cmode=010x. - Cmode = 0x4; + OpCmode = 0x4; Imm = SplatBits >> 16; break; } if ((SplatBits & ~0xff000000) == 0) { // Value = 0xnn000000: Op=x, Cmode=011x. - Cmode = 0x6; + OpCmode = 0x6; Imm = SplatBits >> 24; break; } @@ -2929,7 +2926,7 @@ if ((SplatBits & ~0xffff) == 0 && ((SplatBits | SplatUndef) & 0xff) == 0xff) { // Value = 0x0000nnff: Op=x, Cmode=1100. - Cmode = 0xc; + OpCmode = 0xc; Imm = SplatBits >> 8; SplatBits |= 0xff; break; @@ -2938,7 +2935,7 @@ if ((SplatBits & ~0xffffff) == 0 && ((SplatBits | SplatUndef) & 0xffff) == 0xffff) { // Value = 0x00nnffff: Op=x, Cmode=1101. - Cmode = 0xd; + OpCmode = 0xd; Imm = SplatBits >> 16; SplatBits |= 0xffff; break; @@ -2970,8 +2967,7 @@ ImmMask <<= 1; } // Op=1, Cmode=1110. - Op = 1; - Cmode = 0xe; + OpCmode = 0x1e; SplatBits = Val; VT = MVT::i64; break; @@ -2982,12 +2978,13 @@ return SDValue(); } - if (DoEncode) - return DAG.getTargetConstant((Op << 12) | (Cmode << 8) | Imm, MVT::i32); + if (DoEncode) { + unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm); + return DAG.getTargetConstant(EncodedVal, MVT::i32); + } return DAG.getTargetConstant(SplatBits, VT); } - /// getNEONModImm - If this is a valid vector constant for a NEON instruction /// with a "modified immediate" operand (e.g., VMOV) of the specified element /// size, return the encoded value for that immediate. The ByteSize field Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=108227&r1=108226&r2=108227&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Mon Jul 12 23:44:34 2010 @@ -1030,35 +1030,9 @@ void ARMAsmPrinter::printNEONModImmOperand(const MachineInstr *MI, int OpNum, raw_ostream &O) { - unsigned Imm = MI->getOperand(OpNum).getImm(); - unsigned OpCmode = (Imm >> 8) & 0x1f; - unsigned Imm8 = Imm & 0xff; - uint64_t Val = 0; - - if (OpCmode == 0xe) { - // 8-bit vector elements - Val = Imm8; - } else if ((OpCmode & 0xc) == 0x8) { - // 16-bit vector elements - unsigned ByteNum = (OpCmode & 0x6) >> 1; - Val = Imm8 << (8 * ByteNum); - } else if ((OpCmode & 0x8) == 0) { - // 32-bit vector elements, zero with one byte set - unsigned ByteNum = (OpCmode & 0x6) >> 1; - Val = Imm8 << (8 * ByteNum); - } else if ((OpCmode & 0xe) == 0xc) { - // 32-bit vector elements, one byte with low bits set - unsigned ByteNum = 1 + (OpCmode & 0x1); - Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum))); - } else if (OpCmode == 0x1e) { - // 64-bit vector elements - for (unsigned ByteNum = 0; ByteNum < 8; ++ByteNum) { - if ((Imm >> ByteNum) & 1) - Val |= (uint64_t)0xff << (8 * ByteNum); - } - } else { - assert(false && "Unsupported NEON immediate"); - } + unsigned EncodedImm = MI->getOperand(OpNum).getImm(); + unsigned EltBits; + uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits); O << "#0x" << utohexstr(Val); } Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp?rev=108227&r1=108226&r2=108227&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Mon Jul 12 23:44:34 2010 @@ -781,34 +781,8 @@ void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) { - unsigned Imm = MI->getOperand(OpNum).getImm(); - unsigned OpCmode = (Imm >> 8) & 0x1f; - unsigned Imm8 = Imm & 0xff; - uint64_t Val = 0; - - if (OpCmode == 0xe) { - // 8-bit vector elements - Val = Imm8; - } else if ((OpCmode & 0xc) == 0x8) { - // 16-bit vector elements - unsigned ByteNum = (OpCmode & 0x6) >> 1; - Val = Imm8 << (8 * ByteNum); - } else if ((OpCmode & 0x8) == 0) { - // 32-bit vector elements, zero with one byte set - unsigned ByteNum = (OpCmode & 0x6) >> 1; - Val = Imm8 << (8 * ByteNum); - } else if ((OpCmode & 0xe) == 0xc) { - // 32-bit vector elements, one byte with low bits set - unsigned ByteNum = 1 + (OpCmode & 0x1); - Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum))); - } else if (OpCmode == 0x1e) { - // 64-bit vector elements - for (unsigned ByteNum = 0; ByteNum < 8; ++ByteNum) { - if ((Imm >> ByteNum) & 1) - Val |= (uint64_t)0xff << (8 * ByteNum); - } - } else { - assert(false && "Unsupported NEON immediate"); - } + unsigned EncodedImm = MI->getOperand(OpNum).getImm(); + unsigned EltBits; + uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits); O << "#0x" << utohexstr(Val); } From evan.cheng at apple.com Mon Jul 12 23:52:31 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 12 Jul 2010 21:52:31 -0700 Subject: [llvm-commits] [llvm] r108109 - /llvm/trunk/lib/CodeGen/MachineLICM.cpp In-Reply-To: <9EE0AD47-2443-4D1D-9564-721369F5FC78@nondot.org> References: <20100712000035.393982A6C12C@llvm.org> <5470C984-D21B-4C3F-860C-D7506AFBFAAB@apple.com> <3434519D-9F54-4516-A09A-FAE224A0E8C5@nondot.org> <01AEDF63-186E-4CA3-BCA9-0686BFC66E3A@2pi.dk> <271FD80E-5C28-4114-8430-8E7053E9DEFA@apple.com> <7087D555-AF3C-47AA-981D-02FC19B18B96@apple.com> <9EE0AD47-2443-4D1D-9564-721369F5FC78@nondot.org> Message-ID: On Jul 12, 2010, at 9:14 PM, Chris Lattner wrote: > > On Jul 12, 2010, at 9:10 PM, Evan Cheng wrote: > >> >> On Jul 12, 2010, at 8:58 PM, Chris Lattner wrote: >> >>> >>> On Jul 12, 2010, at 8:55 PM, Evan Cheng wrote: >>> >>>>>> RA, or rather ProcessImplicitDef pass, turn them into trivial short live ranges when it's possible. But it does miss some cases. It's relatively rare but it does happen. >>>>> >>>>> I don't think that LICM should be complicated by a deficiency handling implicit defs. >>>> >>>> I agree. But it's already neutered by register allocator deficiency. We are only hoisting some of the loop invariants for fear of increasing register pressure. We should remove all such restrictions only after live range splitting work lands. >>> >>> I don't see what that has to do with hoisting implicit defs. >> >> It's the same issue. It can lead to increased register pressure. You guys should look at how implicit defs are being handled before jumping to conclusions. There are legitimate cases where implicit defs are not easily removed. > > You just said that this is "relatively rare". Rare implies it does happen. It happens when one or more of the PHI inputs are undef. There might be other cases. This is worth filing a bug and actually run through a bunch of code. It's not worth arguing over here. Evan > > -Chris > From bigcheesegs at gmail.com Tue Jul 13 00:27:27 2010 From: bigcheesegs at gmail.com (Michael Spencer) Date: Tue, 13 Jul 2010 01:27:27 -0400 Subject: [llvm-commits] [MC][patch] Use typedef instead of redundent decl spec in MCAssembler. Message-ID: Very minor patch, but it was bugging me. - Michael Spencer -------------- next part -------------- A non-text attachment was scrubbed... Name: use-td-instead-of-redundent-ds.patch Type: application/octet-stream Size: 442 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100713/1e84d9c4/attachment.obj From echristo at apple.com Tue Jul 13 00:50:09 2010 From: echristo at apple.com (Eric Christopher) Date: Tue, 13 Jul 2010 05:50:09 -0000 Subject: [llvm-commits] [llvm] r108228 - in /llvm/trunk/include/llvm: ADT/ImmutableIntervalMap.h ADT/Triple.h Analysis/CaptureTracking.h Analysis/DebugInfo.h Analysis/DominatorInternals.h Message-ID: <20100713055009.2FE382A6C12C@llvm.org> Author: echristo Date: Tue Jul 13 00:50:08 2010 New Revision: 108228 URL: http://llvm.org/viewvc/llvm-project?rev=108228&view=rev Log: 80-columns Modified: llvm/trunk/include/llvm/ADT/ImmutableIntervalMap.h llvm/trunk/include/llvm/ADT/Triple.h llvm/trunk/include/llvm/Analysis/CaptureTracking.h llvm/trunk/include/llvm/Analysis/DebugInfo.h llvm/trunk/include/llvm/Analysis/DominatorInternals.h Modified: llvm/trunk/include/llvm/ADT/ImmutableIntervalMap.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/ImmutableIntervalMap.h?rev=108228&r1=108227&r2=108228&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/ImmutableIntervalMap.h (original) +++ llvm/trunk/include/llvm/ADT/ImmutableIntervalMap.h Tue Jul 13 00:50:08 2010 @@ -125,9 +125,11 @@ key_type_ref KCurrent = ImutInfo::KeyOfValue(this->Value(T)); if (ImutInfo::isLess(K, KCurrent)) - return this->Balance(Add_internal(V, this->Left(T)), this->Value(T), this->Right(T)); + return this->Balance(Add_internal(V, this->Left(T)), this->Value(T), + this->Right(T)); else - return this->Balance(this->Left(T), this->Value(T), Add_internal(V, this->Right(T))); + return this->Balance(this->Left(T), this->Value(T), + Add_internal(V, this->Right(T))); } // Remove all overlaps from T. @@ -150,9 +152,11 @@ // If current key does not overlap the inserted key. if (CurrentK.getStart() > K.getEnd()) - return this->Balance(RemoveOverlap(this->Left(T), K, Changed), this->Value(T), this->Right(T)); + return this->Balance(RemoveOverlap(this->Left(T), K, Changed), + this->Value(T), this->Right(T)); else if (CurrentK.getEnd() < K.getStart()) - return this->Balance(this->Left(T), this->Value(T), RemoveOverlap(this->Right(T), K, Changed)); + return this->Balance(this->Left(T), this->Value(T), + RemoveOverlap(this->Right(T), K, Changed)); // Current key overlaps with the inserted key. // Remove the current key. Modified: llvm/trunk/include/llvm/ADT/Triple.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/Triple.h?rev=108228&r1=108227&r2=108228&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/Triple.h (original) +++ llvm/trunk/include/llvm/ADT/Triple.h Tue Jul 13 00:50:08 2010 @@ -243,8 +243,8 @@ /// environment components with a single string. void setOSAndEnvironmentName(StringRef Str); - /// getArchNameForAssembler - Get an architecture name that is understood by the - /// target assembler. + /// getArchNameForAssembler - Get an architecture name that is understood by + /// the target assembler. const char *getArchNameForAssembler(); /// @} Modified: llvm/trunk/include/llvm/Analysis/CaptureTracking.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/CaptureTracking.h?rev=108228&r1=108227&r2=108228&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/CaptureTracking.h (original) +++ llvm/trunk/include/llvm/Analysis/CaptureTracking.h Tue Jul 13 00:50:08 2010 @@ -21,9 +21,9 @@ /// by the enclosing function (which is required to exist). This routine can /// be expensive, so consider caching the results. The boolean ReturnCaptures /// specifies whether returning the value (or part of it) from the function - /// counts as capturing it or not. The boolean StoreCaptures specified whether - /// storing the value (or part of it) into memory anywhere automatically - /// counts as capturing it or not. + /// counts as capturing it or not. The boolean StoreCaptures specified + /// whether storing the value (or part of it) into memory anywhere + /// automatically counts as capturing it or not. bool PointerMayBeCaptured(const Value *V, bool ReturnCaptures, bool StoreCaptures); Modified: llvm/trunk/include/llvm/Analysis/DebugInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DebugInfo.h?rev=108228&r1=108227&r2=108228&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/DebugInfo.h (original) +++ llvm/trunk/include/llvm/Analysis/DebugInfo.h Tue Jul 13 00:50:08 2010 @@ -580,7 +580,8 @@ unsigned RunTimeVer = 0); /// CreateFile - Create a new descriptor for the specified file. - DIFile CreateFile(StringRef Filename, StringRef Directory, DICompileUnit CU); + DIFile CreateFile(StringRef Filename, StringRef Directory, + DICompileUnit CU); /// CreateEnumerator - Create a single enumerator value. DIEnumerator CreateEnumerator(StringRef Name, uint64_t Val); Modified: llvm/trunk/include/llvm/Analysis/DominatorInternals.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DominatorInternals.h?rev=108228&r1=108227&r2=108228&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/DominatorInternals.h (original) +++ llvm/trunk/include/llvm/Analysis/DominatorInternals.h Tue Jul 13 00:50:08 2010 @@ -152,8 +152,9 @@ } template -typename GraphT::NodeType* Eval(DominatorTreeBase& DT, - typename GraphT::NodeType *V) { +typename GraphT::NodeType* +Eval(DominatorTreeBase& DT, + typename GraphT::NodeType *V) { typename DominatorTreeBase::InfoRec &VInfo = DT.Info[V]; #if !BALANCE_IDOM_TREE From sabre at nondot.org Tue Jul 13 00:52:36 2010 From: sabre at nondot.org (Chris Lattner) Date: Tue, 13 Jul 2010 05:52:36 -0000 Subject: [llvm-commits] [llvm] r108229 - /llvm/trunk/include/llvm/MC/MCAssembler.h Message-ID: <20100713055236.93C232A6C12C@llvm.org> Author: lattner Date: Tue Jul 13 00:52:36 2010 New Revision: 108229 URL: http://llvm.org/viewvc/llvm-project?rev=108229&view=rev Log: use a typedef instead of its expansion, patch by Michael Spencer Modified: llvm/trunk/include/llvm/MC/MCAssembler.h Modified: llvm/trunk/include/llvm/MC/MCAssembler.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAssembler.h?rev=108229&r1=108228&r2=108229&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCAssembler.h (original) +++ llvm/trunk/include/llvm/MC/MCAssembler.h Tue Jul 13 00:52:36 2010 @@ -354,7 +354,7 @@ typedef FragmentListType::reverse_iterator reverse_iterator; private: - iplist Fragments; + FragmentListType Fragments; const MCSection *Section; /// Ordinal - The section index in the assemblers section list. From clattner at apple.com Tue Jul 13 00:53:18 2010 From: clattner at apple.com (Chris Lattner) Date: Mon, 12 Jul 2010 22:53:18 -0700 Subject: [llvm-commits] [MC][patch] Use typedef instead of redundent decl spec in MCAssembler. In-Reply-To: References: Message-ID: <47CAE62D-2B45-48E8-BF36-BA5D27C8B130@apple.com> Committed in r108229, thanks! On Jul 12, 2010, at 10:27 PM, Michael Spencer wrote: > Very minor patch, but it was bugging me. From baldrick at free.fr Tue Jul 13 01:42:46 2010 From: baldrick at free.fr (Duncan Sands) Date: Tue, 13 Jul 2010 08:42:46 +0200 Subject: [llvm-commits] [llvm-gcc-4.2] r108206 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp In-Reply-To: <20100712230256.C6C322A6C12C@llvm.org> References: <20100712230256.C6C322A6C12C@llvm.org> Message-ID: <4C3C0AE6.2090305@free.fr> Hi Eric, > + /* If this is a vla type and we requested an alignment greater than the stack > + alignment, error out since we're not going to dynamically realign > + variable length array allocations. We're placing this here instead of > + later in case it's a relatively unused variable. */ does gcc support dynamic stack realignment with vla? > + if (TREE_CODE (type) == ARRAY_TYPE&& C_TYPE_VARIABLE_SIZE (type)&& > + DECL_ALIGN(decl)/8u> TheTarget->getFrameInfo()->getStackAlignment()) What is C_TYPE_VARIABLE_SIZE? It sounds like you are calling a C language specific function from language independent code. Ciao, Duncan. From baldrick at free.fr Tue Jul 13 07:06:15 2010 From: baldrick at free.fr (Duncan Sands) Date: Tue, 13 Jul 2010 12:06:15 -0000 Subject: [llvm-commits] [llvm] r108238 - /llvm/trunk/docs/LangRef.html Message-ID: <20100713120615.7EAA72A6C12C@llvm.org> Author: baldrick Date: Tue Jul 13 07:06:14 2010 New Revision: 108238 URL: http://llvm.org/viewvc/llvm-project?rev=108238&view=rev Log: When doing sext/zext of constants, the target type must be strictly wider than the source type. Correct LangRef. Modified: llvm/trunk/docs/LangRef.html Modified: llvm/trunk/docs/LangRef.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=108238&r1=108237&r2=108238&view=diff ============================================================================== --- llvm/trunk/docs/LangRef.html (original) +++ llvm/trunk/docs/LangRef.html Tue Jul 13 07:06:14 2010 @@ -2513,13 +2513,11 @@
zext (CST to TYPE)
Zero extend a constant to another type. The bit size of CST must be - smaller or equal to the bit size of TYPE. Both types must be - integers.
+ smaller than the bit size of TYPE. Both types must be integers.
sext (CST to TYPE)
Sign extend a constant to another type. The bit size of CST must be - smaller or equal to the bit size of TYPE. Both types must be - integers.
+ smaller than the bit size of TYPE. Both types must be integers.
fptrunc (CST to TYPE)
Truncate a floating point constant to another floating point type. The From benny.kra at googlemail.com Tue Jul 13 07:26:09 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Tue, 13 Jul 2010 12:26:09 -0000 Subject: [llvm-commits] [llvm] r108239 - /llvm/trunk/docs/LangRef.html Message-ID: <20100713122609.EFD892A6C12C@llvm.org> Author: d0k Date: Tue Jul 13 07:26:09 2010 New Revision: 108239 URL: http://llvm.org/viewvc/llvm-project?rev=108239&view=rev Log: HTML cleanup and validation. Modified: llvm/trunk/docs/LangRef.html Modified: llvm/trunk/docs/LangRef.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=108239&r1=108238&r2=108239&view=diff ============================================================================== --- llvm/trunk/docs/LangRef.html (original) +++ llvm/trunk/docs/LangRef.html Tue Jul 13 07:26:09 2010 @@ -370,11 +370,9 @@ what is considered 'well formed'. For example, the following instruction is syntactically okay, but not well formed:

-
-
+
 %x = add i32 1, %x
 

-

because the definition of %x does not dominate all of its uses. The LLVM infrastructure provides a verification pass that may be used to verify @@ -437,29 +435,23 @@

The easy way:

-
-
+
 %result = mul i32 %X, 8
 

-

After strength reduction:

-
-
+
 %result = shl i32 %X, i8 3
 

-

And the hard way:

-
-
+
 %0 = add i32 %X, %X           ; yields {i32}:%0
 %1 = add i32 %0, %0           ; yields {i32}:%1
 %result = add i32 %1, %1
 

-

This last way of multiplying %X by 8 illustrates several important lexical features of LLVM:

@@ -498,8 +490,7 @@ forward declarations, and merges symbol table entries. Here is an example of the "hello world" module:

-
-
+
 ; Declare the string constant as a global constant.
 @.LC0 = internal constant [13 x i8] c"hello world\0A\00"    ; [13 x i8]*
 
@@ -519,7 +510,6 @@
 !1 = metadata !{i32 41}
 !foo = !{!1, null}
 

-

This example is made up of a global variable named ".LC0", an external declaration of the "puts" function, @@ -793,11 +783,9 @@ it easier to read the IR and make the IR more condensed (particularly when recursive types are involved). An example of a name specification is:

-
-
+
 %mytype = type { %mytype*, i32 }
 

-

You may give a name to any type except "void". Type name aliases may be used anywhere a type @@ -869,11 +857,9 @@

For example, the following defines a global in a numbered address space with an initializer, section, and alignment:

-
-
+
 @G = addrspace(5) constant float 1.0, section "foo", align 4
 

-
@@ -926,15 +912,13 @@ alignments must be a power of 2.

Syntax:
-
-
+
 define [linkage] [visibility]
        [cconv] [ret attrs]
        <ResultType> @<FunctionName> ([argument list])
        [fn Attrs] [section "name"] [align N]
        [gc] { ... }
 

-
@@ -951,11 +935,9 @@ optional visibility style.

Syntax:
-
-
+
 @<Name> = alias [Linkage] [Visibility] <AliaseeTy> @<Aliasee>
 

-
@@ -971,12 +953,10 @@ a named metadata.

Syntax:
-
-
+
 !1 = metadata !{metadata !"one"}
 !name = !{null, !1}
 

-
@@ -996,13 +976,11 @@ multiple parameter attributes are needed, they are space separated. For example:

-
-
+
 declare i32 @printf(i8* noalias nocapture, ...)
 declare i32 @atoi(i8 zeroext)
 declare signext i8 @returns_signed_char()
 

-

Note that any attributes for the function result (nounwind, readonly) come immediately after the argument list.

@@ -1095,11 +1073,9 @@

Each function may specify a garbage collector name, which is simply a string:

-
-
+
 define void @f() gc "name" { ... }
 

-

The compiler declares the supported values of name. Specifying a collector which will cause the compiler to alter its output in order to @@ -1122,14 +1098,12 @@

Function attributes are simple keywords that follow the type specified. If multiple attributes are needed, they are space separated. For example:

-
-
+
 define void @f() noinline { ... }
 define void @f() alwaysinline { ... }
 define void @f() alwaysinline optsize { ... }
 define void @f() optsize { ... }
 

-
alignstack(<n>)
@@ -1236,12 +1210,10 @@ concatenated by LLVM and treated as a single unit, but may be separated in the .ll file if desired. The syntax is very simple:

-
-
+
 module asm "inline asm code goes here"
 module asm "more can go here"
 

-

The strings can contain any character by escaping non-printable characters. The escape sequence used is simply "\xx" where "xx" is the two digit hex code @@ -1263,11 +1235,9 @@ data is to be laid out in memory. The syntax for the data layout is simply:

-
-
+
 target datalayout = "layout specification"
 

-

The layout specification consists of a list of specifications separated by the minus sign character ('-'). Each specification starts with @@ -1663,8 +1633,6 @@ - -

Array Type
@@ -2198,13 +2166,11 @@ have pointer type. For example, the following is a legal LLVM file:

-
-
+
 @X = global i32 17
 @Y = global i32 42
 @Z = global [2 x i32*] [ i32* @X, i32* @Y ]
 

-
@@ -2223,8 +2189,7 @@ surprising) transformations that are valid (in pseudo IR):

-
-
+
   %A = add %X, undef
   %B = sub %X, undef
   %C = xor %X, undef
@@ -2233,13 +2198,11 @@
   %B = undef
   %C = undef
 

-

This is safe because all of the output bits are affected by the undef bits. Any output bit can have a zero or one depending on the input bits.

-
-
+
   %A = or %X, undef
   %B = and %X, undef
 Safe:
@@ -2249,7 +2212,6 @@
   %A = undef
   %B = undef
 

-

These logical operations have bits that are not always affected by the input. For example, if "%X" has a zero bit, then the output of the 'and' operation will @@ -2260,8 +2222,7 @@ the undef operand to the or could be set, allowing the or to be folded to -1.

-
-
+
   %A = select undef, %X, %Y
   %B = select undef, 42, %Y
   %C = select %X, %Y, undef
@@ -2274,7 +2235,6 @@
   %B = undef
   %C = undef
 

-

This set of examples show that undefined select (and conditional branch) conditions can go "either way" but they have to come from one of the two @@ -2284,8 +2244,7 @@ %Y, allowing the whole select to be eliminated.

-
-
+
   %A = xor undef, undef
 
   %B = undef
@@ -2303,7 +2262,6 @@
   %E = undef
   %F = undef
 

-

This example points out that two undef operands are not necessarily the same. This can be surprising to people (and also matches C semantics) where they @@ -2316,15 +2274,13 @@ to have the same semantics or the core LLVM "replace all uses with" concept would not hold.

-
-
+
   %A = fdiv undef, %X
   %B = fdiv %X, undef
 Safe:
   %A = undef
 b: unreachable
 

-

These examples show the crucial difference between an undefined value and undefined behavior. An undefined value (like undef) is @@ -2339,15 +2295,13 @@ it occurs in dead code.

-
-
+
 a:  store undef -> %X
 b:  store %X -> undef
 Safe:
 a: <deleted>
 b: unreachable
 

-

These examples reiterate the fdiv example: a store "of" an undefined value can be assumed to not have any effect: we can assume that the value is @@ -2373,7 +2327,6 @@

Trap value behavior is defined in terms of value dependence:

-

  • Values other than phi nodes depend on their operands.
    • @@ -2417,7 +2370,6 @@
  • Dependence is transitive.
-

Whenever a trap value is generated, all values which depend on it evaluate to trap. If they have side effects, the evoke their side effects as if each @@ -2426,8 +2378,7 @@

Here are some examples:

-
-
+
 entry:
   %trap = sub nuw i32 0, 1           ; Results in a trap value.
   %still_trap = and i32 %trap, 0     ; Whereas (and i32 undef, 0) would return 0.
@@ -2462,7 +2413,6 @@
                                      ; so this is defined (ignoring earlier
                                      ; undefined behavior in this example).
 

-
@@ -2644,31 +2594,25 @@ containing the asm needs to align its stack conservatively. An example inline assembler expression is:

-
-
+
 i32 (i32) asm "bswap $0", "=r,r"
 

-

Inline assembler expressions may only be used as the callee operand of a call instruction. Thus, typically we have:

-
-
+
 %X = call i32 asm "bswap $0", "=r,r"(i32 %Y)
 

-

Inline asms with side effects not visible in the constraint list must be marked as having side effects. This is done through the use of the 'sideeffect' keyword, like so:

-
-
+
 call void asm sideeffect "eieio", ""()
 

-

In some cases inline asms will contain code that will not work unless the stack is aligned in some way, such as calls or SSE instructions on x86, @@ -2677,11 +2621,9 @@ contain and should generate its usual stack alignment code in the prologue if the 'alignstack' keyword is present:

-
-
+
 call void asm alignstack "eieio", ""()
 

-

If both keywords appear the 'sideeffect' keyword must come first.

@@ -2705,13 +2647,11 @@ front-end to correlate backend errors that occur with inline asm back to the source code that produced it. For example:

-
-
+
 call void asm sideeffect "something bad", ""(), !srcloc !42
 ...
 !42 = !{ i32 1234567 }
 

-

It is up to the front-end to make sense of the magic numbers it places in the IR.

@@ -2746,22 +2686,18 @@ example: "!foo = metadata !{!4, !3}".

Metadata can be used as function arguments. Here llvm.dbg.value - function is using two metadata arguments. + function is using two metadata arguments.

-
- 
+     
        call void @llvm.dbg.value(metadata !24, i64 0, metadata !25)
      

-

Metadata can be attached with an instruction. Here metadata !21 is - attached with add instruction using !dbg identifier. + attached with add instruction using !dbg identifier.

-
- 
+    
       %indvar.next = add i64 %indvar, 1, !dbg !21
     

-

@@ -4389,8 +4325,8 @@
Syntax:
-  store <ty> <value>, <ty>* <pointer>[, align <alignment>][, !nontemporal !]                   ; yields {void}
-  volatile store <ty> <value>, <ty>* <pointer>[, align <alignment>][, !nontemporal !]          ; yields {void}
+  store <ty> <value>, <ty>* <pointer>[, align <alignment>][, !nontemporal !<index>]                   ; yields {void}
+  volatile store <ty> <value>, <ty>* <pointer>[, align <alignment>][, !nontemporal !<index>]          ; yields {void}
Overview:
@@ -4415,7 +4351,7 @@ produce less efficient code. An alignment of 1 is always safe.

The optional !nontemporal metadata must reference a single metatadata - name corresponding to a metadata node with one i32 entry of + name <index> corresponding to a metadata node with one i32 entry of value 1. The existence of the !nontemporal metatadata on the instruction tells the optimizer and code generator that this load is not expected to be reused in the cache. The code generator may @@ -4482,8 +4418,7 @@

For example, let's consider a C code fragment and how it gets compiled to LLVM:

-
-
+
 struct RT {
   char A;
   int B[10][20];
@@ -4499,12 +4434,10 @@
   return &s[1].Z.B[5][13];
 }
 

-

The LLVM code generated by the GCC frontend is:

-
-
+
 %RT = type { i8 , [10 x [20 x i32]], i8  }
 %ST = type { i32, double, %RT }
 
@@ -4514,7 +4447,6 @@
   ret i32* %reg
 }
 

-
Semantics:

In the example above, the first index is indexing into the '%ST*' @@ -5585,8 +5517,7 @@ instruction and the variable argument handling intrinsic functions are used.

-
-
+
 define i32 @test(i32 %X, ...) {
   ; Initialize variable argument processing
   %ap = alloca i8*
@@ -5611,7 +5542,6 @@
 declare void @llvm.va_copy(i8*, i8*)
 declare void @llvm.va_end(i8*)
 

-
@@ -6977,14 +6907,12 @@ pointer has signature i32 (i32, i32)*. It can be created as follows:

-
-
+
   %tramp = alloca [10 x i8], align 4 ; size and alignment only correct for X86
   %tramp1 = getelementptr [10 x i8]* %tramp, i32 0, i32 0
   %p = call i8* @llvm.init.trampoline(i8* %tramp1, i8* bitcast (i32 (i8* nest , i32, i32)* @f to i8*), i8* %nval)
   %fp = bitcast i8* %p to i32 (i32, i32)*
 

-

The call %val = call i32 %fp(i32 %x, i32 %y) is then equivalent to %val = call i32 %f(i8* %nval, i32 %x, i32 %y).

From ggreif at gmail.com Tue Jul 13 10:31:37 2010 From: ggreif at gmail.com (Gabor Greif) Date: Tue, 13 Jul 2010 15:31:37 -0000 Subject: [llvm-commits] [llvm] r108240 - in /llvm/trunk: include/llvm/Instructions.h lib/Target/CppBackend/CPPBackend.cpp lib/VMCore/Verifier.cpp Message-ID: <20100713153137.20B702A6C12C@llvm.org> Author: ggreif Date: Tue Jul 13 10:31:36 2010 New Revision: 108240 URL: http://llvm.org/viewvc/llvm-project?rev=108240&view=rev Log: rotate CallInst operands with this commit the callee moves to the end of the operand array (from the start) and the call arguments now start at index 0 (formerly 1) this ordering is now consistent with InvokeInst this commit only flips the switch, functionally it is equivalent to r101465 I intend to commit several cleanups after a few days of soak period Modified: llvm/trunk/include/llvm/Instructions.h llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp llvm/trunk/lib/VMCore/Verifier.cpp Modified: llvm/trunk/include/llvm/Instructions.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=108240&r1=108239&r2=108240&view=diff ============================================================================== --- llvm/trunk/include/llvm/Instructions.h (original) +++ llvm/trunk/include/llvm/Instructions.h Tue Jul 13 10:31:36 2010 @@ -944,6 +944,9 @@ /// @deprecated these "define hacks" will go away soon /// @brief coerce out-of-tree code to abandon the low-level interfaces /// @detail see below comments and update your code to high-level interfaces + /// - getOperand(0) ---> getCalledValue(), or possibly getCalledFunction + /// - setOperand(0, V) ---> setCalledFunction(V) + /// /// in LLVM v2.8-only code /// - getOperand(N+1) ---> getArgOperand(N) /// - setOperand(N+1, V) ---> setArgOperand(N, V) @@ -961,23 +964,11 @@ # undef protected public: - enum { ArgOffset = 1 }; ///< temporary, do not use for new code! + enum { ArgOffset = 0 }; ///< temporary, do not use for new code! unsigned getNumArgOperands() const { return getNumOperands() - 1; } Value *getArgOperand(unsigned i) const { return getOperand(i + ArgOffset); } void setArgOperand(unsigned i, Value *v) { setOperand(i + ArgOffset, v); } - /// Provide compile-time errors for accessing operand 0 - /// @deprecated these will go away soon - /// @detail see below comments and update your code to high-level interfaces - /// - getOperand(0) ---> getCalledValue(), or possibly getCalledFunction - /// - setOperand(0, V) ---> setCalledFunction(V) - /// -private: - void getOperand(void*); // NO IMPL ---> use getCalledValue (or possibly - // getCalledFunction) instead - void setOperand(void*, Value*); // NO IMPL ---> use setCalledFunction instead -public: - /// getCallingConv/setCallingConv - Get or set the calling convention of this /// function call. CallingConv::ID getCallingConv() const { Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp?rev=108240&r1=108239&r2=108240&view=diff ============================================================================== --- llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp (original) +++ llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Tue Jul 13 10:31:36 2010 @@ -1400,18 +1400,18 @@ Out << "std::vector " << iName << "_params;"; nl(Out); for (unsigned i = 0; i < call->getNumArgOperands(); ++i) { - Out << iName << "_params.push_back(" << opNames[i+1] << ");"; + Out << iName << "_params.push_back(" << opNames[i] << ");"; nl(Out); } Out << "CallInst* " << iName << " = CallInst::Create(" - << opNames[0] << ", " << iName << "_params.begin(), " + << opNames[call->getNumArgOperands()] << ", " << iName << "_params.begin(), " << iName << "_params.end(), \""; } else if (call->getNumArgOperands() == 1) { Out << "CallInst* " << iName << " = CallInst::Create(" - << opNames[0] << ", " << opNames[1] << ", \""; + << opNames[call->getNumArgOperands()] << ", " << opNames[0] << ", \""; } else { - Out << "CallInst* " << iName << " = CallInst::Create(" << opNames[0] - << ", \""; + Out << "CallInst* " << iName << " = CallInst::Create(" + << opNames[call->getNumArgOperands()] << ", \""; } printEscapedString(call->getName()); Out << "\", " << bbname << ");"; Modified: llvm/trunk/lib/VMCore/Verifier.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=108240&r1=108239&r2=108240&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Verifier.cpp (original) +++ llvm/trunk/lib/VMCore/Verifier.cpp Tue Jul 13 10:31:36 2010 @@ -1454,7 +1454,7 @@ if (Function *F = dyn_cast(I.getOperand(i))) { // Check to make sure that the "address of" an intrinsic function is never // taken. - Assert1(!F->isIntrinsic() || (i == 0 && isa(I)), + Assert1(!F->isIntrinsic() || (i + 1 == e && isa(I)), "Cannot take the address of an intrinsic!", &I); Assert1(F->getParent() == Mod, "Referencing function in another module!", &I); @@ -1537,7 +1537,8 @@ "Instruction does not dominate all uses!", Op, &I); } } else if (isa(I.getOperand(i))) { - Assert1((i == 0 && isa(I)) || (i + 3 == e && isa(I)), + Assert1((i + 1 == e && isa(I)) || + (i + 3 == e && isa(I)), "Cannot take the address of an inline asm!", &I); } } From baldrick at free.fr Tue Jul 13 10:41:41 2010 From: baldrick at free.fr (Duncan Sands) Date: Tue, 13 Jul 2010 15:41:41 -0000 Subject: [llvm-commits] [llvm] r108241 - in /llvm/trunk: lib/Transforms/Scalar/TailRecursionElimination.cpp test/Transforms/TailCallElim/2010-06-26-MultipleReturnValues.ll Message-ID: <20100713154141.C689A2A6C12C@llvm.org> Author: baldrick Date: Tue Jul 13 10:41:41 2010 New Revision: 108241 URL: http://llvm.org/viewvc/llvm-project?rev=108241&view=rev Log: Handle the case of a tail recursion in which the tail call is followed by a return that returns a constant, while elsewhere in the function another return instruction returns a different constant. This is a special case of accumulator recursion, so just generalize the existing logic a bit. Modified: llvm/trunk/lib/Transforms/Scalar/TailRecursionElimination.cpp llvm/trunk/test/Transforms/TailCallElim/2010-06-26-MultipleReturnValues.ll Modified: llvm/trunk/lib/Transforms/Scalar/TailRecursionElimination.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/TailRecursionElimination.cpp?rev=108241&r1=108240&r2=108241&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/TailRecursionElimination.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/TailRecursionElimination.cpp Tue Jul 13 10:41:41 2010 @@ -373,7 +373,12 @@ // the call instruction that are both associative and commutative, the initial // value for the accumulator is placed in this variable. If this value is set // then we actually perform accumulator recursion elimination instead of - // simple tail recursion elimination. + // simple tail recursion elimination. If the operation is an LLVM instruction + // (eg: "add") then it is recorded in AccumulatorRecursionInstr. If not, then + // we are handling the case when the return instruction returns a constant C + // which is different to the constant returned by other return instructions + // (which is recorded in AccumulatorRecursionEliminationInitVal). This is a + // special case of accumulator recursion, the operation being "return C". Value *AccumulatorRecursionEliminationInitVal = 0; Instruction *AccumulatorRecursionInstr = 0; @@ -404,8 +409,18 @@ if (Ret->getNumOperands() == 1 && Ret->getReturnValue() != CI && !isa(Ret->getReturnValue()) && AccumulatorRecursionEliminationInitVal == 0 && - !getCommonReturnValue(0, CI)) - return false; + !getCommonReturnValue(0, CI)) { + // One case remains that we are able to handle: the current return + // instruction returns a constant, and all other return instructions + // return a different constant. + if (!isDynamicConstant(Ret->getReturnValue(), CI, Ret)) + return false; // Current return instruction does not return a constant. + // Check that all other return instructions return a common constant. If + // so, record it in AccumulatorRecursionEliminationInitVal. + AccumulatorRecursionEliminationInitVal = getCommonReturnValue(Ret, CI); + if (!AccumulatorRecursionEliminationInitVal) + return false; + } // OK! We can transform this tail call. If this is the first one found, // create the new entry block, allowing us to branch back to the old entry. @@ -465,8 +480,9 @@ if (AccumulatorRecursionEliminationInitVal) { Instruction *AccRecInstr = AccumulatorRecursionInstr; // Start by inserting a new PHI node for the accumulator. - PHINode *AccPN = PHINode::Create(AccRecInstr->getType(), "accumulator.tr", - OldEntry->begin()); + PHINode *AccPN = + PHINode::Create(AccumulatorRecursionEliminationInitVal->getType(), + "accumulator.tr", OldEntry->begin()); // Loop over all of the predecessors of the tail recursion block. For the // real entry into the function we seed the PHI with the initial value, @@ -483,14 +499,20 @@ AccPN->addIncoming(AccPN, P); } - // Add an incoming argument for the current block, which is computed by our - // associative and commutative accumulator instruction. - AccPN->addIncoming(AccRecInstr, BB); - - // Next, rewrite the accumulator recursion instruction so that it does not - // use the result of the call anymore, instead, use the PHI node we just - // inserted. - AccRecInstr->setOperand(AccRecInstr->getOperand(0) != CI, AccPN); + if (AccRecInstr) { + // Add an incoming argument for the current block, which is computed by + // our associative and commutative accumulator instruction. + AccPN->addIncoming(AccRecInstr, BB); + + // Next, rewrite the accumulator recursion instruction so that it does not + // use the result of the call anymore, instead, use the PHI node we just + // inserted. + AccRecInstr->setOperand(AccRecInstr->getOperand(0) != CI, AccPN); + } else { + // Add an incoming argument for the current block, which is just the + // constant returned by the current return instruction. + AccPN->addIncoming(Ret->getReturnValue(), BB); + } // Finally, rewrite any return instructions in the program to return the PHI // node instead of the "initval" that they do currently. This loop will Modified: llvm/trunk/test/Transforms/TailCallElim/2010-06-26-MultipleReturnValues.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/TailCallElim/2010-06-26-MultipleReturnValues.ll?rev=108241&r1=108240&r2=108241&view=diff ============================================================================== --- llvm/trunk/test/Transforms/TailCallElim/2010-06-26-MultipleReturnValues.ll (original) +++ llvm/trunk/test/Transforms/TailCallElim/2010-06-26-MultipleReturnValues.ll Tue Jul 13 10:41:41 2010 @@ -1,7 +1,9 @@ ; RUN: opt < %s -tailcallelim -S | FileCheck %s ; PR7328 +; PR7506 define i32 @foo(i32 %x) { ; CHECK: define i32 @foo +; CHECK: %accumulator.tr = phi i32 [ 1, %entry ], [ 0, %body ] entry: %cond = icmp ugt i32 %x, 0 ; [#uses=1] br i1 %cond, label %return, label %body @@ -9,8 +11,9 @@ body: ; preds = %entry %y = add i32 %x, 1 ; [#uses=1] %tmp = call i32 @foo(i32 %y) ; [#uses=0] +; CHECK-NOT: call ret i32 0 -; CHECK: ret i32 0 +; CHECK: ret i32 %accumulator.tr return: ; preds = %entry ret i32 1 From kennethuil at gmail.com Tue Jul 13 10:49:02 2010 From: kennethuil at gmail.com (Kenneth Uildriks) Date: Tue, 13 Jul 2010 10:49:02 -0500 Subject: [llvm-commits] Unit test for partial spec Message-ID: This is my second attempt to set up a unit test to catch a recurrence of the Partial Specialization bug where callsites were using the wrong specialization. Thus, the test needs to check that (a) a specialization is done and (b) callsites are adjusted properly so the wrong code isn't being called. Also, I don't want the test to depend in any way on the names of the specializations, since I want to create a naming scheme based on the value(s) being specialized on; this will allow redundant equivalent specializations to be removed at link time. So the approach I'm using is to have two test runs in the file differentiated by FileCheck prefix. One simply makes sure that PartialSpecialization transformed the code when I expected it to. The other applies inlining to the result of the partial specialization and checks the inline result to make sure that the callsites in the partial specialized version were calling the right specialization. If the callsites are wrong, the inlining step will bring the wrong function bodies into the main function and trigger the test failure. Does this make sense? Is there a better way to go about it? Does anyone see portability problems (the last attempt failed on one particular buildbot running on a platform I don't have access to). -------------- next part -------------- A non-text attachment was scrubbed... Name: PartialSpecTest.patch Type: application/octet-stream Size: 1662 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100713/7e788120/attachment.obj From daniel at zuster.org Tue Jul 13 11:11:26 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Tue, 13 Jul 2010 16:11:26 -0000 Subject: [llvm-commits] [test-suite] r108244 - /test-suite/trunk/External/SPEC/CINT2000/300.twolf/Makefile Message-ID: <20100713161126.BA5C02A6C12C@llvm.org> Author: ddunbar Date: Tue Jul 13 11:11:26 2010 New Revision: 108244 URL: http://llvm.org/viewvc/llvm-project?rev=108244&view=rev Log: Disable -Wreturn-type for 300.twolf, which Clang now errors on. Modified: test-suite/trunk/External/SPEC/CINT2000/300.twolf/Makefile Modified: test-suite/trunk/External/SPEC/CINT2000/300.twolf/Makefile URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/External/SPEC/CINT2000/300.twolf/Makefile?rev=108244&r1=108243&r2=108244&view=diff ============================================================================== --- test-suite/trunk/External/SPEC/CINT2000/300.twolf/Makefile (original) +++ test-suite/trunk/External/SPEC/CINT2000/300.twolf/Makefile Tue Jul 13 11:11:26 2010 @@ -3,5 +3,6 @@ RUN_OPTIONS = $(RUN_TYPE) STDOUT_FILENAME = $(RUN_TYPE).stdout HASH_PROGRAM_OUTPUT = 1 +CFLAGS += -Wno-return-type include ../../Makefile.spec2000 From dpatel at apple.com Tue Jul 13 11:53:20 2010 From: dpatel at apple.com (Devang Patel) Date: Tue, 13 Jul 2010 16:53:20 -0000 Subject: [llvm-commits] [llvm] r108246 - /llvm/trunk/docs/SourceLevelDebugging.html Message-ID: <20100713165321.10E962A6C12C@llvm.org> Author: dpatel Date: Tue Jul 13 11:53:20 2010 New Revision: 108246 URL: http://llvm.org/viewvc/llvm-project?rev=108246&view=rev Log: Fix compile unit in example. Thanks Renato Golin! Modified: llvm/trunk/docs/SourceLevelDebugging.html Modified: llvm/trunk/docs/SourceLevelDebugging.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/SourceLevelDebugging.html?rev=108246&r1=108245&r2=108246&view=diff ============================================================================== --- llvm/trunk/docs/SourceLevelDebugging.html (original) +++ llvm/trunk/docs/SourceLevelDebugging.html Tue Jul 13 11:53:20 2010 @@ -1058,7 +1058,7 @@ i32 524329, ;; Tag metadata !"MySource.cpp", metadata !"/Users/mine/sources", - metadata !3 ;; Compile unit + metadata !2 ;; Compile unit } ;; @@ -1068,7 +1068,7 @@ i32 524329, ;; Tag metadata !"Myheader.h" metadata !"/Users/mine/sources", - metadata !3 ;; Compile unit + metadata !2 ;; Compile unit } ... From echristo at apple.com Tue Jul 13 12:22:01 2010 From: echristo at apple.com (Eric Christopher) Date: Tue, 13 Jul 2010 10:22:01 -0700 Subject: [llvm-commits] [llvm-gcc-4.2] r108206 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp In-Reply-To: <4C3C0AE6.2090305@free.fr> References: <20100712230256.C6C322A6C12C@llvm.org> <4C3C0AE6.2090305@free.fr> Message-ID: <807E94C5-4FEF-461A-983B-636B901B6855@apple.com> On Jul 12, 2010, at 11:42 PM, Duncan Sands wrote: > Hi Eric, > >> + /* If this is a vla type and we requested an alignment greater than the stack >> + alignment, error out since we're not going to dynamically realign >> + variable length array allocations. We're placing this here instead of >> + later in case it's a relatively unused variable. */ > > does gcc support dynamic stack realignment with vla? > Nope. >> + if (TREE_CODE (type) == ARRAY_TYPE&& C_TYPE_VARIABLE_SIZE (type)&& >> + DECL_ALIGN(decl)/8u> TheTarget->getFrameInfo()->getStackAlignment()) > > What is C_TYPE_VARIABLE_SIZE? It sounds like you are calling a C language > specific function from language independent code. Somewhat, I changed it later :) Especially since C++ lowers VLAs by hand. -eric From chandlerc at gmail.com Tue Jul 13 12:28:06 2010 From: chandlerc at gmail.com (Chandler Carruth) Date: Tue, 13 Jul 2010 17:28:06 -0000 Subject: [llvm-commits] [llvm] r108248 - in /llvm/trunk/unittests: ADT/APIntTest.cpp VMCore/PassManagerTest.cpp Message-ID: <20100713172806.1B7D82A6C12C@llvm.org> Author: chandlerc Date: Tue Jul 13 12:28:05 2010 New Revision: 108248 URL: http://llvm.org/viewvc/llvm-project?rev=108248&view=rev Log: Switch from EXPECT_EQ({true,false, ...) to the more canonical EXPECT_{TRUE,FALSE}(...) macros. This also prevents suprious warnings about bool-to-pointer conversion that occurs withit EXPECT_EQ. Modified: llvm/trunk/unittests/ADT/APIntTest.cpp llvm/trunk/unittests/VMCore/PassManagerTest.cpp Modified: llvm/trunk/unittests/ADT/APIntTest.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/ADT/APIntTest.cpp?rev=108248&r1=108247&r2=108248&view=diff ============================================================================== --- llvm/trunk/unittests/ADT/APIntTest.cpp (original) +++ llvm/trunk/unittests/ADT/APIntTest.cpp Tue Jul 13 12:28:05 2010 @@ -20,8 +20,8 @@ TEST(APIntTest, ShiftLeftByZero) { APInt One = APInt::getNullValue(65) + 1; APInt Shl = One.shl(0); - EXPECT_EQ(true, Shl[0]); - EXPECT_EQ(false, Shl[1]); + EXPECT_TRUE(Shl[0]); + EXPECT_FALSE(Shl[1]); } TEST(APIntTest, i128_NegativeCount) { Modified: llvm/trunk/unittests/VMCore/PassManagerTest.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/VMCore/PassManagerTest.cpp?rev=108248&r1=108247&r2=108248&view=diff ============================================================================== --- llvm/trunk/unittests/VMCore/PassManagerTest.cpp (original) +++ llvm/trunk/unittests/VMCore/PassManagerTest.cpp Tue Jul 13 12:28:05 2010 @@ -105,8 +105,8 @@ static bool finalized; int allocated; void run() { - EXPECT_EQ(true, initialized); - EXPECT_EQ(false, finalized); + EXPECT_TRUE(initialized); + EXPECT_FALSE(finalized); EXPECT_EQ(0, allocated); allocated++; runc++; @@ -115,8 +115,8 @@ static char ID; static void finishedOK(int run) { EXPECT_GT(runc, 0); - EXPECT_EQ(true, initialized); - EXPECT_EQ(true, finalized); + EXPECT_TRUE(initialized); + EXPECT_TRUE(finalized); EXPECT_EQ(run, runc); } PassTestBase() : P(&ID), allocated(0) { @@ -140,12 +140,12 @@ struct PassTest : public PassTestBase

{ public: virtual bool doInitialization(T &t) { - EXPECT_EQ(false, PassTestBase

::initialized); + EXPECT_FALSE(PassTestBase

::initialized); PassTestBase

::initialized = true; return false; } virtual bool doFinalization(T &t) { - EXPECT_EQ(false, PassTestBase

::finalized); + EXPECT_FALSE(PassTestBase

::finalized); PassTestBase

::finalized = true; EXPECT_EQ(0, PassTestBase

::allocated); return false; @@ -180,7 +180,7 @@ public: LPass() { initcount = 0; fincount=0; - EXPECT_EQ(false, initialized); + EXPECT_FALSE(initialized); } static void finishedOK(int run, int finalized) { PassTestBase::finishedOK(run); @@ -222,7 +222,7 @@ fin = 0; } virtual bool doInitialization(Module &M) { - EXPECT_EQ(false, initialized); + EXPECT_FALSE(initialized); initialized = true; return false; } @@ -240,7 +240,7 @@ return false; } virtual bool doFinalization(Module &M) { - EXPECT_EQ(false, finalized); + EXPECT_FALSE(finalized); finalized = true; EXPECT_EQ(0, allocated); return false; From wdietz2 at illinois.edu Tue Jul 13 12:56:51 2010 From: wdietz2 at illinois.edu (Will Dietz) Date: Tue, 13 Jul 2010 17:56:51 -0000 Subject: [llvm-commits] [poolalloc] r108249 - /poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp Message-ID: <20100713175651.2CF032A6C12C@llvm.org> Author: wdietz2 Date: Tue Jul 13 12:56:51 2010 New Revision: 108249 URL: http://llvm.org/viewvc/llvm-project?rev=108249&view=rev Log: Update NewToOldValueMap after cloning. Modified: poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp Modified: poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp?rev=108249&r1=108248&r2=108249&view=diff ============================================================================== --- poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp (original) +++ poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp Tue Jul 13 12:56:51 2010 @@ -645,6 +645,10 @@ NI->setName(I->getName()); } + // Perform the cloning. + SmallVector Returns; + CloneFunctionInto(New, &F, ValueMap, Returns); + // // Invert the ValueMap into the NewToOldValueMap. // @@ -653,10 +657,6 @@ E = ValueMap.end(); I != E; ++I) NewToOldValueMap.insert(std::make_pair(I->second, I->first)); - // Perform the cloning. - SmallVector Returns; - CloneFunctionInto(New, &F, ValueMap, Returns); - // // FIXME: File a bug report for CloneFunctionInto; it should take care of // this mess for us. Also check whether it does it correctly. From bob.wilson at apple.com Tue Jul 13 13:12:05 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 13 Jul 2010 18:12:05 -0000 Subject: [llvm-commits] [zorg] r108250 - /zorg/trunk/lnt/lnt/tests/nt.py Message-ID: <20100713181205.BF5002A6C12C@llvm.org> Author: bwilson Date: Tue Jul 13 13:12:05 2010 New Revision: 108250 URL: http://llvm.org/viewvc/llvm-project?rev=108250&view=rev Log: Fix logic for checking if the compiler has a tagged version number. Also ignore '00' since some builds of llvm-gcc report that as the build number. Modified: zorg/trunk/lnt/lnt/tests/nt.py Modified: zorg/trunk/lnt/lnt/tests/nt.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/tests/nt.py?rev=108250&r1=108249&r2=108250&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/tests/nt.py (original) +++ zorg/trunk/lnt/lnt/tests/nt.py Tue Jul 13 13:12:05 2010 @@ -428,8 +428,9 @@ # don't accept 0 or 9999 as valid source tag, since that is what # llvm-gcc builds use when no build number is given. elif (run_info.get('cc_build') == 'PROD' and - (run_info.get('cc_src_tag') != '0' or - run_info.get('cc_src_tag') != '9999') and + run_info.get('cc_src_tag') != '0' and + run_info.get('cc_src_tag') != '00' and + run_info.get('cc_src_tag') != '9999' and run_info.get('cc_src_tag','').isdigit()): run_info['run_order'] = run_info['cc_src_tag'] From dalej at apple.com Tue Jul 13 13:14:47 2010 From: dalej at apple.com (Dale Johannesen) Date: Tue, 13 Jul 2010 18:14:47 -0000 Subject: [llvm-commits] [llvm] r108251 - /llvm/trunk/test/CodeGen/X86/2010-07-06-asm-RIP.ll Message-ID: <20100713181447.825E02A6C12C@llvm.org> Author: johannes Date: Tue Jul 13 13:14:47 2010 New Revision: 108251 URL: http://llvm.org/viewvc/llvm-project?rev=108251&view=rev Log: Fix PR number. Modified: llvm/trunk/test/CodeGen/X86/2010-07-06-asm-RIP.ll Modified: llvm/trunk/test/CodeGen/X86/2010-07-06-asm-RIP.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-07-06-asm-RIP.ll?rev=108251&r1=108250&r2=108251&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2010-07-06-asm-RIP.ll (original) +++ llvm/trunk/test/CodeGen/X86/2010-07-06-asm-RIP.ll Tue Jul 13 13:14:47 2010 @@ -1,5 +1,5 @@ ; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s -; PR 7528 +; PR 4752 @n = global i32 0 ; [#uses=2] From echristo at apple.com Tue Jul 13 13:27:14 2010 From: echristo at apple.com (Eric Christopher) Date: Tue, 13 Jul 2010 18:27:14 -0000 Subject: [llvm-commits] [llvm] r108252 - /llvm/trunk/lib/Transforms/IPO/Inliner.cpp Message-ID: <20100713182714.1D5BD2A6C12C@llvm.org> Author: echristo Date: Tue Jul 13 13:27:13 2010 New Revision: 108252 URL: http://llvm.org/viewvc/llvm-project?rev=108252&view=rev Log: Grammar. Modified: llvm/trunk/lib/Transforms/IPO/Inliner.cpp Modified: llvm/trunk/lib/Transforms/IPO/Inliner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/Inliner.cpp?rev=108252&r1=108251&r2=108252&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/Inliner.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/Inliner.cpp Tue Jul 13 13:27:13 2010 @@ -399,7 +399,7 @@ // We can only inline direct calls to non-declarations. if (Callee == 0 || Callee->isDeclaration()) continue; - // If this call sites was obtained by inlining another function, verify + // If this call site was obtained by inlining another function, verify // that the include path for the function did not include the callee // itself. If so, we'd be recursively inlinling the same function, // which would provide the same callsites, which would cause us to From evan.cheng at apple.com Tue Jul 13 13:46:14 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 13 Jul 2010 18:46:14 -0000 Subject: [llvm-commits] [llvm] r108254 - in /llvm/trunk: lib/Target/TargetMachine.cpp test/CodeGen/X86/2006-05-22-FPSetEQ.ll test/CodeGen/X86/fabs.ll test/CodeGen/X86/sse-minmax.ll Message-ID: <20100713184614.70C5F2A6C12C@llvm.org> Author: evancheng Date: Tue Jul 13 13:46:14 2010 New Revision: 108254 URL: http://llvm.org/viewvc/llvm-project?rev=108254&view=rev Log: -enable-unsafe-fp-math should not imply -enable-finite-only-fp-math. Modified: llvm/trunk/lib/Target/TargetMachine.cpp llvm/trunk/test/CodeGen/X86/2006-05-22-FPSetEQ.ll llvm/trunk/test/CodeGen/X86/fabs.ll llvm/trunk/test/CodeGen/X86/sse-minmax.ll Modified: llvm/trunk/lib/Target/TargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetMachine.cpp?rev=108254&r1=108253&r2=108254&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetMachine.cpp (original) +++ llvm/trunk/lib/Target/TargetMachine.cpp Tue Jul 13 13:46:14 2010 @@ -294,7 +294,7 @@ /// option is specified on the command line. If this returns false (default), /// the code generator is not allowed to assume that FP arithmetic arguments /// and results are never NaNs or +-Infs. - bool FiniteOnlyFPMath() { return UnsafeFPMath || FiniteOnlyFPMathOption; } + bool FiniteOnlyFPMath() { return FiniteOnlyFPMathOption; } /// HonorSignDependentRoundingFPMath - Return true if the codegen must assume /// that the rounding mode of the FPU can change from its default. Modified: llvm/trunk/test/CodeGen/X86/2006-05-22-FPSetEQ.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2006-05-22-FPSetEQ.ll?rev=108254&r1=108253&r2=108254&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2006-05-22-FPSetEQ.ll (original) +++ llvm/trunk/test/CodeGen/X86/2006-05-22-FPSetEQ.ll Tue Jul 13 13:46:14 2010 @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=x86 | grep setnp -; RUN: llc < %s -march=x86 -enable-unsafe-fp-math | \ +; RUN: llc < %s -march=x86 -enable-unsafe-fp-math -enable-finite-only-fp-math | \ ; RUN: not grep setnp define i32 @test(float %f) { Modified: llvm/trunk/test/CodeGen/X86/fabs.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fabs.ll?rev=108254&r1=108253&r2=108254&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/fabs.ll (original) +++ llvm/trunk/test/CodeGen/X86/fabs.ll Tue Jul 13 13:46:14 2010 @@ -1,7 +1,7 @@ ; Make sure this testcase codegens to the fabs instruction, not a call to fabsf ; RUN: llc < %s -march=x86 -mattr=-sse2,-sse3,-sse | grep fabs\$ | \ ; RUN: count 2 -; RUN: llc < %s -march=x86 -mattr=-sse,-sse2,-sse3 -enable-unsafe-fp-math | \ +; RUN: llc < %s -march=x86 -mattr=-sse,-sse2,-sse3 -enable-unsafe-fp-math -enable-finite-only-fp-math | \ ; RUN: grep fabs\$ | count 3 declare float @fabsf(float) Modified: llvm/trunk/test/CodeGen/X86/sse-minmax.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-minmax.ll?rev=108254&r1=108253&r2=108254&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/sse-minmax.ll (original) +++ llvm/trunk/test/CodeGen/X86/sse-minmax.ll Tue Jul 13 13:46:14 2010 @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=x86-64 -asm-verbose=false | FileCheck %s -; RUN: llc < %s -march=x86-64 -asm-verbose=false -enable-unsafe-fp-math | FileCheck -check-prefix=UNSAFE %s +; RUN: llc < %s -march=x86-64 -asm-verbose=false -enable-unsafe-fp-math -enable-finite-only-fp-math | FileCheck -check-prefix=UNSAFE %s ; RUN: llc < %s -march=x86-64 -asm-verbose=false -enable-finite-only-fp-math | FileCheck -check-prefix=FINITE %s ; Some of these patterns can be matched as SSE min or max. Some of From gclayton at apple.com Tue Jul 13 13:47:09 2010 From: gclayton at apple.com (Greg Clayton) Date: Tue, 13 Jul 2010 18:47:09 -0000 Subject: [llvm-commits] [llvm] r108255 - /llvm/trunk/Makefile.rules Message-ID: <20100713184709.94FAD2A6C12C@llvm.org> Author: gclayton Date: Tue Jul 13 13:47:09 2010 New Revision: 108255 URL: http://llvm.org/viewvc/llvm-project?rev=108255&view=rev Log: Patched Makefile.rules to allow objective C and objective C++ compilation. This allows LLDB (llvm/tools/lldb) to build on Mac OS X. Modified: llvm/trunk/Makefile.rules Modified: llvm/trunk/Makefile.rules URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=108255&r1=108254&r2=108255&view=diff ============================================================================== --- llvm/trunk/Makefile.rules (original) +++ llvm/trunk/Makefile.rules Tue Jul 13 13:47:09 2010 @@ -42,7 +42,7 @@ # Reset the list of suffixes we know how to build. #-------------------------------------------------------------------- .SUFFIXES: -.SUFFIXES: .c .cpp .cc .h .hpp .o .a .bc .td .ps .dot .ll +.SUFFIXES: .c .cpp .cc .h .hpp .o .a .bc .td .ps .dot .ll .m .mm .SUFFIXES: $(SHLIBEXT) $(SUFFIXES) #-------------------------------------------------------------------- @@ -1442,6 +1442,11 @@ $(Verb) if $(Compile.CXX) $(DEPEND_OPTIONS) $< -o $(ObjDir)/$*.o ; \ $(DEPEND_MOVEFILE) +$(ObjDir)/%.o: %.mm $(ObjDir)/.dir $(BUILT_SOURCES) $(PROJ_SRC_DIR)/Makefile + $(Echo) "Compiling $*.mm for $(BuildMode) build" $(PIC_FLAG) + $(Verb) if $(Compile.CXX) $(DEPEND_OPTIONS) $< -o $(ObjDir)/$*.o ; \ + $(DEPEND_MOVEFILE) + $(ObjDir)/%.o: %.cc $(ObjDir)/.dir $(BUILT_SOURCES) $(PROJ_SRC_DIR)/Makefile $(Echo) "Compiling $*.cc for $(BuildMode) build" $(PIC_FLAG) $(Verb) if $(Compile.CXX) $(DEPEND_OPTIONS) $< -o $(ObjDir)/$*.o ; \ @@ -1452,6 +1457,11 @@ $(Verb) if $(Compile.C) $(DEPEND_OPTIONS) $< -o $(ObjDir)/$*.o ; \ $(DEPEND_MOVEFILE) +$(ObjDir)/%.o: %.m $(ObjDir)/.dir $(BUILT_SOURCES) $(PROJ_SRC_DIR)/Makefile + $(Echo) "Compiling $*.m for $(BuildMode) build" $(PIC_FLAG) + $(Verb) if $(Compile.C) $(DEPEND_OPTIONS) $< -o $(ObjDir)/$*.o ; \ + $(DEPEND_MOVEFILE) + #--------------------------------------------------------- # Create .bc files in the ObjDir directory from .cpp .cc and .c files... #--------------------------------------------------------- @@ -1470,6 +1480,12 @@ $< -o $(ObjDir)/$*.ll -S -emit-llvm ; \ $(BC_DEPEND_MOVEFILE) +$(ObjDir)/%.ll: %.mm $(ObjDir)/.dir $(BUILT_SOURCES) $(LLVMCXX) + $(Echo) "Compiling $*.mm for $(BuildMode) build (bytecode)" + $(Verb) if $(BCCompile.CXX) $(BC_DEPEND_OPTIONS) \ + $< -o $(ObjDir)/$*.ll -S -emit-llvm ; \ + $(BC_DEPEND_MOVEFILE) + $(ObjDir)/%.ll: %.cc $(ObjDir)/.dir $(BUILT_SOURCES) $(LLVMCXX) $(Echo) "Compiling $*.cc for $(BuildMode) build (bytecode)" $(Verb) if $(BCCompile.CXX) $(BC_DEPEND_OPTIONS) \ @@ -1482,6 +1498,12 @@ $< -o $(ObjDir)/$*.ll -S -emit-llvm ; \ $(BC_DEPEND_MOVEFILE) +$(ObjDir)/%.ll: %.m $(ObjDir)/.dir $(BUILT_SOURCES) $(LLVMCC) + $(Echo) "Compiling $*.m for $(BuildMode) build (bytecode)" + $(Verb) if $(BCCompile.C) $(BC_DEPEND_OPTIONS) \ + $< -o $(ObjDir)/$*.ll -S -emit-llvm ; \ + $(BC_DEPEND_MOVEFILE) + # Provide alternate rule sets if dependencies are disabled else @@ -1489,6 +1511,10 @@ $(Echo) "Compiling $*.cpp for $(BuildMode) build" $(PIC_FLAG) $(Compile.CXX) $< -o $@ +$(ObjDir)/%.o: %.mm $(ObjDir)/.dir $(BUILT_SOURCES) + $(Echo) "Compiling $*.mm for $(BuildMode) build" $(PIC_FLAG) + $(Compile.CXX) $< -o $@ + $(ObjDir)/%.o: %.cc $(ObjDir)/.dir $(BUILT_SOURCES) $(Echo) "Compiling $*.cc for $(BuildMode) build" $(PIC_FLAG) $(Compile.CXX) $< -o $@ @@ -1497,10 +1523,18 @@ $(Echo) "Compiling $*.c for $(BuildMode) build" $(PIC_FLAG) $(Compile.C) $< -o $@ +$(ObjDir)/%.o: %.m $(ObjDir)/.dir $(BUILT_SOURCES) + $(Echo) "Compiling $*.m for $(BuildMode) build" $(PIC_FLAG) + $(Compile.C) $< -o $@ + $(ObjDir)/%.ll: %.cpp $(ObjDir)/.dir $(BUILT_SOURCES) $(LLVMCXX) $(Echo) "Compiling $*.cpp for $(BuildMode) build (bytecode)" $(BCCompile.CXX) $< -o $@ -S -emit-llvm +$(ObjDir)/%.ll: %.mm $(ObjDir)/.dir $(BUILT_SOURCES) $(LLVMCXX) + $(Echo) "Compiling $*.mm for $(BuildMode) build (bytecode)" + $(BCCompile.CXX) $< -o $@ -S -emit-llvm + $(ObjDir)/%.ll: %.cc $(ObjDir)/.dir $(BUILT_SOURCES) $(LLVMCXX) $(Echo) "Compiling $*.cc for $(BuildMode) build (bytecode)" $(BCCompile.CXX) $< -o $@ -S -emit-llvm @@ -1509,6 +1543,10 @@ $(Echo) "Compiling $*.c for $(BuildMode) build (bytecode)" $(BCCompile.C) $< -o $@ -S -emit-llvm +$(ObjDir)/%.ll: %.m $(ObjDir)/.dir $(BUILT_SOURCES) $(LLVMCC) + $(Echo) "Compiling $*.m for $(BuildMode) build (bytecode)" + $(BCCompile.C) $< -o $@ -S -emit-llvm + endif @@ -1517,6 +1555,10 @@ $(Echo) "Compiling $*.cpp for $(BuildMode) build to .ii file" $(Verb) $(Preprocess.CXX) $< -o $@ +$(BuildMode)/%.ii: %.mm $(ObjDir)/.dir $(BUILT_SOURCES) + $(Echo) "Compiling $*.mm for $(BuildMode) build to .ii file" + $(Verb) $(Preprocess.CXX) $< -o $@ + $(BuildMode)/%.ii: %.cc $(ObjDir)/.dir $(BUILT_SOURCES) $(Echo) "Compiling $*.cc for $(BuildMode) build to .ii file" $(Verb) $(Preprocess.CXX) $< -o $@ @@ -1525,11 +1567,19 @@ $(Echo) "Compiling $*.c for $(BuildMode) build to .i file" $(Verb) $(Preprocess.C) $< -o $@ +$(BuildMode)/%.i: %.m $(ObjDir)/.dir $(BUILT_SOURCES) + $(Echo) "Compiling $*.m for $(BuildMode) build to .i file" + $(Verb) $(Preprocess.C) $< -o $@ + $(ObjDir)/%.s: %.cpp $(ObjDir)/.dir $(BUILT_SOURCES) $(Echo) "Compiling $*.cpp to asm for $(BuildMode) build" $(PIC_FLAG) $(Compile.CXX) $< -o $@ -S +$(ObjDir)/%.s: %.mm $(ObjDir)/.dir $(BUILT_SOURCES) + $(Echo) "Compiling $*.mm to asm for $(BuildMode) build" $(PIC_FLAG) + $(Compile.CXX) $< -o $@ -S + $(ObjDir)/%.s: %.cc $(ObjDir)/.dir $(BUILT_SOURCES) $(Echo) "Compiling $*.cc to asm for $(BuildMode) build" $(PIC_FLAG) $(Compile.CXX) $< -o $@ -S @@ -1538,6 +1588,10 @@ $(Echo) "Compiling $*.c to asm for $(BuildMode) build" $(PIC_FLAG) $(Compile.C) $< -o $@ -S +$(ObjDir)/%.s: %.m $(ObjDir)/.dir $(BUILT_SOURCES) + $(Echo) "Compiling $*.m to asm for $(BuildMode) build" $(PIC_FLAG) + $(Compile.C) $< -o $@ -S + # make the C and C++ compilers strip debug info out of bytecode libraries. ifdef DEBUG_RUNTIME @@ -1750,7 +1804,7 @@ ifndef IS_CLEANING_TARGET # Get the list of dependency files -DependSourceFiles := $(basename $(filter %.cpp %.c %.cc, $(Sources))) +DependSourceFiles := $(basename $(filter %.cpp %.c %.cc %.m %.mm, $(Sources))) DependFiles := $(DependSourceFiles:%=$(PROJ_OBJ_DIR)/$(BuildMode)/%.d) # Include bitcode dependency files if using bitcode libraries From evan.cheng at apple.com Tue Jul 13 14:21:50 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 13 Jul 2010 19:21:50 -0000 Subject: [llvm-commits] [llvm] r108256 - in /llvm/trunk/lib/Target/ARM: ARM.td ARMSubtarget.h Message-ID: <20100713192150.BF97C2A6C12C@llvm.org> Author: evancheng Date: Tue Jul 13 14:21:50 2010 New Revision: 108256 URL: http://llvm.org/viewvc/llvm-project?rev=108256&view=rev Log: Add an ARM "feature". Cortex-a8 fp comparison is very slow (> 20 cycles). Modified: llvm/trunk/lib/Target/ARM/ARM.td llvm/trunk/lib/Target/ARM/ARMSubtarget.h Modified: llvm/trunk/lib/Target/ARM/ARM.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=108256&r1=108255&r2=108256&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARM.td (original) +++ llvm/trunk/lib/Target/ARM/ARM.td Tue Jul 13 14:21:50 2010 @@ -48,6 +48,8 @@ "Enable divide instructions">; def FeatureT2ExtractPack: SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true", "Enable Thumb2 extract and pack instructions">; +def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true", + "FP compare + branch is slow">; // Some processors have multiply-accumulate instructions that don't // play nicely with other VFP instructions, and it's generally better @@ -129,7 +131,7 @@ // V7 Processors. def : Processor<"cortex-a8", CortexA8Itineraries, [ArchV7A, FeatureThumb2, FeatureNEON, FeatureHasSlowVMLx, - FeatureNEONForFP, FeatureT2ExtractPack]>; + FeatureSlowFPBrcc, FeatureNEONForFP, FeatureT2ExtractPack]>; def : Processor<"cortex-a9", CortexA9Itineraries, [ArchV7A, FeatureThumb2, FeatureNEON, FeatureT2ExtractPack]>; def : ProcNoItin<"cortex-m3", [ArchV7M, FeatureThumb2, FeatureHWDiv]>; Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=108256&r1=108255&r2=108256&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original) +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Tue Jul 13 14:21:50 2010 @@ -54,6 +54,9 @@ /// the VML[AS] instructions are slow (if so, don't use them). bool SlowVMLx; + /// SlowFPBrcc - True if floating point compare + branch is slow. + bool SlowFPBrcc; + /// IsThumb - True if we are in thumb mode, false if in ARM mode. bool IsThumb; @@ -133,6 +136,7 @@ bool hasDivide() const { return HasHardwareDivide; } bool hasT2ExtractPack() const { return HasT2ExtractPack; } bool useVMLx() const {return hasVFP2() && !SlowVMLx; } + bool isFPBrccSlow() const { return SlowFPBrcc; } bool hasFP16() const { return HasFP16; } From evan.cheng at apple.com Tue Jul 13 14:27:43 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 13 Jul 2010 19:27:43 -0000 Subject: [llvm-commits] [llvm] r108258 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMISelLowering.h lib/Target/ARM/ARMInstrInfo.td test/CodeGen/ARM/fpcmp-opt.ll Message-ID: <20100713192743.33FCC2A6C12C@llvm.org> Author: evancheng Date: Tue Jul 13 14:27:42 2010 New Revision: 108258 URL: http://llvm.org/viewvc/llvm-project?rev=108258&view=rev Log: Extend the r107852 optimization which turns some fp compare to code sequence using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0. Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.h llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/test/CodeGen/ARM/fpcmp-opt.ll Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=108258&r1=108257&r2=108258&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Jul 13 14:27:42 2010 @@ -565,6 +565,7 @@ case ARMISD::CMPZ: return "ARMISD::CMPZ"; case ARMISD::CMPFP: return "ARMISD::CMPFP"; case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0"; + case ARMISD::BCC_i64: return "ARMISD::BCC_i64"; case ARMISD::FMSTAT: return "ARMISD::FMSTAT"; case ARMISD::CMOV: return "ARMISD::CMOV"; case ARMISD::CNEG: return "ARMISD::CNEG"; @@ -2216,7 +2217,7 @@ /// the given operands. SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, - SDValue &ARMCC, SelectionDAG &DAG, + SDValue &ARMcc, SelectionDAG &DAG, DebugLoc dl) const { if (ConstantSDNode *RHSC = dyn_cast(RHS.getNode())) { unsigned C = RHSC->getZExtValue(); @@ -2268,48 +2269,14 @@ CompareType = ARMISD::CMPZ; break; } - ARMCC = DAG.getConstant(CondCode, MVT::i32); + ARMcc = DAG.getConstant(CondCode, MVT::i32); return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS); } -static bool canBitcastToInt(SDNode *Op) { - return Op->hasOneUse() && - ISD::isNormalLoad(Op) && - Op->getValueType(0) == MVT::f32; -} - -static SDValue bitcastToInt(SDValue Op, SelectionDAG &DAG) { - if (LoadSDNode *Ld = dyn_cast(Op)) - return DAG.getLoad(MVT::i32, Op.getDebugLoc(), - Ld->getChain(), Ld->getBasePtr(), - Ld->getSrcValue(), Ld->getSrcValueOffset(), - Ld->isVolatile(), Ld->isNonTemporal(), - Ld->getAlignment()); - - llvm_unreachable("Unknown VFP cmp argument!"); -} - /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands. SDValue -ARMTargetLowering::getVFPCmp(SDValue &LHS, SDValue &RHS, ISD::CondCode CC, - SDValue &ARMCC, SelectionDAG &DAG, +ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG, DebugLoc dl) const { - if (UnsafeFPMath && FiniteOnlyFPMath() && - (CC == ISD::SETEQ || CC == ISD::SETOEQ || - CC == ISD::SETNE || CC == ISD::SETUNE) && - canBitcastToInt(LHS.getNode()) && canBitcastToInt(RHS.getNode())) { - // If unsafe fp math optimization is enabled and there are no othter uses of - // the CMP operands, and the condition code is EQ oe NE, we can optimize it - // to an integer comparison. - if (CC == ISD::SETOEQ) - CC = ISD::SETEQ; - else if (CC == ISD::SETUNE) - CC = ISD::SETNE; - LHS = bitcastToInt(LHS, DAG); - RHS = bitcastToInt(RHS, DAG); - return getARMCmp(LHS, RHS, CC, ARMCC, DAG, dl); - } - SDValue Cmp; if (!isFloatingPointZero(RHS)) Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS); @@ -2328,59 +2295,184 @@ DebugLoc dl = Op.getDebugLoc(); if (LHS.getValueType() == MVT::i32) { - SDValue ARMCC; + SDValue ARMcc; SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); - SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, dl); - return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, CCR,Cmp); + SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl); + return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp); } ARMCC::CondCodes CondCode, CondCode2; FPCCToARMCC(CC, CondCode, CondCode2); - SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32); + SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32); + SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl); SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); - SDValue Cmp = getVFPCmp(LHS, RHS, CC, ARMCC, DAG, dl); SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, - ARMCC, CCR, Cmp); + ARMcc, CCR, Cmp); if (CondCode2 != ARMCC::AL) { - SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32); + SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32); // FIXME: Needs another CMP because flag can have but one use. - SDValue Cmp2 = getVFPCmp(LHS, RHS, CC, ARMCC2, DAG, dl); + SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl); Result = DAG.getNode(ARMISD::CMOV, dl, VT, - Result, TrueVal, ARMCC2, CCR, Cmp2); + Result, TrueVal, ARMcc2, CCR, Cmp2); } return Result; } +/// canChangeToInt - Given the fp compare operand, return true if it is suitable +/// to morph to an integer compare sequence. +static bool canChangeToInt(SDValue Op, bool &SeenZero, + const ARMSubtarget *Subtarget) { + SDNode *N = Op.getNode(); + if (!N->hasOneUse()) + // Otherwise it requires moving the value from fp to integer registers. + return false; + if (!N->getNumValues()) + return false; + EVT VT = Op.getValueType(); + if (VT != MVT::f32 && !Subtarget->isFPBrccSlow()) + // f32 case is generally profitable. f64 case only makes sense when vcmpe + + // vmrs are very slow, e.g. cortex-a8. + return false; + + if (isFloatingPointZero(Op)) { + SeenZero = true; + return true; + } + return ISD::isNormalLoad(N); +} + +static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) { + if (isFloatingPointZero(Op)) + return DAG.getConstant(0, MVT::i32); + + if (LoadSDNode *Ld = dyn_cast(Op)) + return DAG.getLoad(MVT::i32, Op.getDebugLoc(), + Ld->getChain(), Ld->getBasePtr(), + Ld->getSrcValue(), Ld->getSrcValueOffset(), + Ld->isVolatile(), Ld->isNonTemporal(), + Ld->getAlignment()); + + llvm_unreachable("Unknown VFP cmp argument!"); +} + +static void expandf64Toi32(SDValue Op, SelectionDAG &DAG, + SDValue &RetVal1, SDValue &RetVal2) { + if (isFloatingPointZero(Op)) { + RetVal1 = DAG.getConstant(0, MVT::i32); + RetVal2 = DAG.getConstant(0, MVT::i32); + return; + } + + if (LoadSDNode *Ld = dyn_cast(Op)) { + SDValue Ptr = Ld->getBasePtr(); + RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(), + Ld->getChain(), Ptr, + Ld->getSrcValue(), Ld->getSrcValueOffset(), + Ld->isVolatile(), Ld->isNonTemporal(), + Ld->getAlignment()); + + EVT PtrType = Ptr.getValueType(); + unsigned NewAlign = MinAlign(Ld->getAlignment(), 4); + SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(), + PtrType, Ptr, DAG.getConstant(4, PtrType)); + RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(), + Ld->getChain(), NewPtr, + Ld->getSrcValue(), Ld->getSrcValueOffset() + 4, + Ld->isVolatile(), Ld->isNonTemporal(), + NewAlign); + return; + } + + llvm_unreachable("Unknown VFP cmp argument!"); +} + +/// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some +/// f32 and even f64 comparisons to integer ones. +SDValue +ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const { + SDValue Chain = Op.getOperand(0); + ISD::CondCode CC = cast(Op.getOperand(1))->get(); + SDValue LHS = Op.getOperand(2); + SDValue RHS = Op.getOperand(3); + SDValue Dest = Op.getOperand(4); + DebugLoc dl = Op.getDebugLoc(); + + bool SeenZero = false; + if (canChangeToInt(LHS, SeenZero, Subtarget) && + canChangeToInt(RHS, SeenZero, Subtarget) && + // If one of the operand is zero, it's safe to ignore the NaN case. + (FiniteOnlyFPMath() || SeenZero)) { + // If unsafe fp math optimization is enabled and there are no othter uses of + // the CMP operands, and the condition code is EQ oe NE, we can optimize it + // to an integer comparison. + if (CC == ISD::SETOEQ) + CC = ISD::SETEQ; + else if (CC == ISD::SETUNE) + CC = ISD::SETNE; + + SDValue ARMcc; + if (LHS.getValueType() == MVT::f32) { + LHS = bitcastf32Toi32(LHS, DAG); + RHS = bitcastf32Toi32(RHS, DAG); + SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl); + SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); + return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, + Chain, Dest, ARMcc, CCR, Cmp); + } + + SDValue LHS1, LHS2; + SDValue RHS1, RHS2; + expandf64Toi32(LHS, DAG, LHS1, LHS2); + expandf64Toi32(RHS, DAG, RHS1, RHS2); + ARMCC::CondCodes CondCode = IntCCToARMCC(CC); + ARMcc = DAG.getConstant(CondCode, MVT::i32); + SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag); + SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest }; + return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7); + } + + return SDValue(); +} + SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { - SDValue Chain = Op.getOperand(0); + SDValue Chain = Op.getOperand(0); ISD::CondCode CC = cast(Op.getOperand(1))->get(); - SDValue LHS = Op.getOperand(2); - SDValue RHS = Op.getOperand(3); - SDValue Dest = Op.getOperand(4); + SDValue LHS = Op.getOperand(2); + SDValue RHS = Op.getOperand(3); + SDValue Dest = Op.getOperand(4); DebugLoc dl = Op.getDebugLoc(); if (LHS.getValueType() == MVT::i32) { - SDValue ARMCC; + SDValue ARMcc; + SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl); SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); - SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, dl); return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, - Chain, Dest, ARMCC, CCR,Cmp); + Chain, Dest, ARMcc, CCR, Cmp); } assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64); + + if (UnsafeFPMath && + (CC == ISD::SETEQ || CC == ISD::SETOEQ || + CC == ISD::SETNE || CC == ISD::SETUNE)) { + SDValue Result = OptimizeVFPBrcond(Op, DAG); + if (Result.getNode()) + return Result; + } + ARMCC::CondCodes CondCode, CondCode2; FPCCToARMCC(CC, CondCode, CondCode2); - SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32); - SDValue Cmp = getVFPCmp(LHS, RHS, CC, ARMCC, DAG, dl); + SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32); + SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl); SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag); - SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp }; + SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp }; SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5); if (CondCode2 != ARMCC::AL) { - ARMCC = DAG.getConstant(CondCode2, MVT::i32); - SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) }; + ARMcc = DAG.getConstant(CondCode2, MVT::i32); + SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) }; Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5); } return Res; @@ -2469,12 +2561,11 @@ EVT VT = Op.getValueType(); EVT SrcVT = Tmp1.getValueType(); SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0); - SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32); + SDValue ARMcc = DAG.getConstant(ARMCC::LT, MVT::i32); SDValue FP0 = DAG.getConstantFP(0.0, SrcVT); - SDValue Cmp = getVFPCmp(Tmp1, FP0, - ISD::SETLT, ARMCC, DAG, dl); + SDValue Cmp = getVFPCmp(Tmp1, FP0, DAG, dl); SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); - return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp); + return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMcc, CCR, Cmp); } SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{ @@ -2611,7 +2702,7 @@ SDValue ShOpLo = Op.getOperand(0); SDValue ShOpHi = Op.getOperand(1); SDValue ShAmt = Op.getOperand(2); - SDValue ARMCC; + SDValue ARMcc; unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL; assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS); @@ -2627,9 +2718,9 @@ SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE, - ARMCC, DAG, dl); + ARMcc, DAG, dl); SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt); - SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, + SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp); SDValue Ops[2] = { Lo, Hi }; @@ -2647,7 +2738,7 @@ SDValue ShOpLo = Op.getOperand(0); SDValue ShOpHi = Op.getOperand(1); SDValue ShAmt = Op.getOperand(2); - SDValue ARMCC; + SDValue ARMcc; assert(Op.getOpcode() == ISD::SHL_PARTS); SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, @@ -2661,9 +2752,9 @@ SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE, - ARMCC, DAG, dl); + ARMcc, DAG, dl); SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); - SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMCC, + SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc, CCR, Cmp); SDValue Ops[2] = { Lo, Hi }; @@ -3825,6 +3916,15 @@ return BB; } +static +MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) { + for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(), + E = MBB->succ_end(); I != E; ++I) + if (*I != Succ) + return *I; + llvm_unreachable("Expecting a BB with two successors!"); +} + MachineBasicBlock * ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *BB) const { @@ -3941,6 +4041,46 @@ return BB; } + case ARM::BCCi64: + case ARM::BCCZi64: { + // Compare both parts that make up the double comparison separately for + // equality. + bool RHSisZero = MI->getOpcode() == ARM::BCCZi64; + + unsigned LHS1 = MI->getOperand(1).getReg(); + unsigned LHS2 = MI->getOperand(2).getReg(); + if (RHSisZero) { + AddDefaultPred(BuildMI(BB, dl, + TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) + .addReg(LHS1).addImm(0)); + BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) + .addReg(LHS2).addImm(0) + .addImm(ARMCC::EQ).addReg(ARM::CPSR); + } else { + unsigned RHS1 = MI->getOperand(3).getReg(); + unsigned RHS2 = MI->getOperand(4).getReg(); + AddDefaultPred(BuildMI(BB, dl, + TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr)) + .addReg(LHS1).addReg(RHS1)); + BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr)) + .addReg(LHS2).addReg(RHS2) + .addImm(ARMCC::EQ).addReg(ARM::CPSR); + } + + MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB(); + MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB); + if (MI->getOperand(0).getImm() == ARMCC::NE) + std::swap(destMBB, exitMBB); + + BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) + .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR); + BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2B : ARM::B)) + .addMBB(exitMBB); + + MI->eraseFromParent(); // The pseudo instruction is gone now. + return BB; + } + case ARM::tANDsp: case ARM::tADDspr_: case ARM::tSUBspi_: Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=108258&r1=108257&r2=108258&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Tue Jul 13 14:27:42 2010 @@ -53,6 +53,8 @@ CMOV, // ARM conditional move instructions. CNEG, // ARM conditional negate instructions. + BCC_i64, + RBIT, // ARM bitreverse instruction FTOSI, // FP to sint within a FP register. @@ -363,9 +365,11 @@ DebugLoc dl, SelectionDAG &DAG) const; SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, - SDValue &ARMCC, SelectionDAG &DAG, DebugLoc dl) const; - SDValue getVFPCmp(SDValue &LHS, SDValue &RHS, ISD::CondCode CC, - SDValue &ARMCC, SelectionDAG &DAG, DebugLoc dl) const; + SDValue &ARMcc, SelectionDAG &DAG, DebugLoc dl) const; + SDValue getVFPCmp(SDValue LHS, SDValue RHS, + SelectionDAG &DAG, DebugLoc dl) const; + + SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const; MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI, MachineBasicBlock *BB, Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=108258&r1=108257&r2=108258&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Jul 13 14:27:42 2010 @@ -38,6 +38,12 @@ [SDTCisPtrTy<0>, SDTCisVT<1, i32>, SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; +def SDT_ARMBCC_i64 : SDTypeProfile<0, 6, + [SDTCisVT<0, i32>, + SDTCisVT<1, i32>, SDTCisVT<2, i32>, + SDTCisVT<3, i32>, SDTCisVT<4, i32>, + SDTCisVT<5, OtherVT>]>; + def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, @@ -90,6 +96,9 @@ def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT, [SDNPHasChain]>; +def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64, + [SDNPHasChain]>; + def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp, [SDNPOutFlag]>; @@ -2279,6 +2288,22 @@ def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm), (CMNzri GPR:$src, so_imm_neg:$imm)>; +// Pseudo i64 compares for some floating point compares. +let usesCustomInserter = 1, isBranch = 1, isTerminator = 1, + Defs = [CPSR] in { +def BCCi64 : PseudoInst<(outs), + (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst), + IIC_Br, + "${:comment} B\t$dst GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, imm:$cc", + [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>; + +def BCCZi64 : PseudoInst<(outs), + (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), + IIC_Br, + "${:comment} B\t$dst GPR:$lhs1, GPR:$lhs2, 0, 0, imm:$cc", + [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>; +} // usesCustomInserter + // Conditional moves // FIXME: should be able to write a pattern for ARMcmov, but can't use Modified: llvm/trunk/test/CodeGen/ARM/fpcmp-opt.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fpcmp-opt.ll?rev=108258&r1=108257&r2=108258&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fpcmp-opt.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fpcmp-opt.ll Tue Jul 13 14:27:42 2010 @@ -1,16 +1,24 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 -enable-unsafe-fp-math -enable-finite-only-fp-math | FileCheck %s +; RUN: llc < %s -march=arm -mcpu=cortex-a8 -mattr=+vfp2 -enable-unsafe-fp-math -enable-finite-only-fp-math | FileCheck -check-prefix=FINITE %s +; RUN: llc < %s -march=arm -mcpu=cortex-a8 -mattr=+vfp2 -enable-unsafe-fp-math | FileCheck -check-prefix=NAN %s ; rdar://7461510 define arm_apcscc i32 @t1(float* %a, float* %b) nounwind { entry: -; CHECK: t1: -; CHECK-NOT: vldr -; CHECK: ldr -; CHECK: ldr -; CHECK: cmp r0, r1 -; CHECK-NOT: vcmpe.f32 -; CHECK-NOT: vmrs -; CHECK: beq +; FINITE: t1: +; FINITE-NOT: vldr +; FINITE: ldr +; FINITE: ldr +; FINITE: cmp r0, r1 +; FINITE-NOT: vcmpe.f32 +; FINITE-NOT: vmrs +; FINITE: beq + +; NAN: t1: +; NAN: vldr.32 s0, +; NAN: vldr.32 s1, +; NAN: vcmpe.f32 s1, s0 +; NAN: vmrs apsr_nzcv, fpscr +; NAN: beq %0 = load float* %a %1 = load float* %b %2 = fcmp une float %0, %1 @@ -25,5 +33,50 @@ ret i32 %4 } +define arm_apcscc i32 @t2(double* %a, double* %b) nounwind { +entry: +; FINITE: t2: +; FINITE-NOT: vldr +; FINITE: ldrd r0, [r0] +; FINITE: cmp r0, #0 +; FINITE: cmpeq r1, #0 +; FINITE-NOT: vcmpe.f32 +; FINITE-NOT: vmrs +; FINITE: bne + %0 = load double* %a + %1 = fcmp oeq double %0, 0.000000e+00 + br i1 %1, label %bb1, label %bb2 + +bb1: + %2 = call i32 @bar() + ret i32 %2 + +bb2: + %3 = call i32 @foo() + ret i32 %3 +} + +define arm_apcscc i32 @t3(float* %a, float* %b) nounwind { +entry: +; FINITE: t3: +; FINITE-NOT: vldr +; FINITE: ldr r0, [r0] +; FINITE: cmp r0, #0 +; FINITE-NOT: vcmpe.f32 +; FINITE-NOT: vmrs +; FINITE: bne + %0 = load float* %a + %1 = fcmp oeq float %0, 0.000000e+00 + br i1 %1, label %bb1, label %bb2 + +bb1: + %2 = call i32 @bar() + ret i32 %2 + +bb2: + %3 = call i32 @foo() + ret i32 %3 +} + declare i32 @bar() declare i32 @foo() From gohman at apple.com Tue Jul 13 14:33:27 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 13 Jul 2010 19:33:27 -0000 Subject: [llvm-commits] [llvm] r108259 - in /llvm/trunk: lib/AsmParser/LLParser.cpp lib/Bitcode/Reader/BitcodeReader.cpp lib/VMCore/Metadata.cpp test/Feature/metadata.ll Message-ID: <20100713193327.7633A2A6C12C@llvm.org> Author: djg Date: Tue Jul 13 14:33:27 2010 New Revision: 108259 URL: http://llvm.org/viewvc/llvm-project?rev=108259&view=rev Log: Add support for empty metadata nodes: !{}. Modified: llvm/trunk/lib/AsmParser/LLParser.cpp llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp llvm/trunk/lib/VMCore/Metadata.cpp llvm/trunk/test/Feature/metadata.ll Modified: llvm/trunk/lib/AsmParser/LLParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=108259&r1=108258&r2=108259&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLParser.cpp (original) +++ llvm/trunk/lib/AsmParser/LLParser.cpp Tue Jul 13 14:33:27 2010 @@ -3983,6 +3983,10 @@ /// ::= 'null' | TypeAndValue bool LLParser::ParseMDNodeVector(SmallVectorImpl &Elts, PerFunctionState *PFS) { + // Check for an empty list. + if (Lex.getKind() == lltok::rbrace) + return false; + do { // Null is a special case since it is typeless. if (EatIfPresent(lltok::kw_null)) { Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp?rev=108259&r1=108258&r2=108259&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp (original) +++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp Tue Jul 13 14:33:27 2010 @@ -820,7 +820,7 @@ IsFunctionLocal = true; // fall-through case bitc::METADATA_NODE: { - if (Record.empty() || Record.size() % 2 == 1) + if (Record.size() % 2 == 1) return Error("Invalid METADATA_NODE record"); unsigned Size = Record.size(); @@ -834,7 +834,8 @@ else Elts.push_back(NULL); } - Value *V = MDNode::getWhenValsUnresolved(Context, &Elts[0], Elts.size(), + Value *V = MDNode::getWhenValsUnresolved(Context, + Elts.data(), Elts.size(), IsFunctionLocal); IsFunctionLocal = false; MDValueList.AssignValue(V, NextMDValueNo++); Modified: llvm/trunk/lib/VMCore/Metadata.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Metadata.cpp?rev=108259&r1=108258&r2=108259&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Metadata.cpp (original) +++ llvm/trunk/lib/VMCore/Metadata.cpp Tue Jul 13 14:33:27 2010 @@ -78,7 +78,8 @@ /// getOperandPtr - Helper function to get the MDNodeOperand's coallocated on /// the end of the MDNode. static MDNodeOperand *getOperandPtr(MDNode *N, unsigned Op) { - assert(Op < N->getNumOperands() && "Invalid operand number"); + // Use <= instead of < to permit a one-past-the-end address. + assert(Op <= N->getNumOperands() && "Invalid operand number"); return reinterpret_cast(N+1)+Op; } Modified: llvm/trunk/test/Feature/metadata.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Feature/metadata.ll?rev=108259&r1=108258&r2=108259&view=diff ============================================================================== --- llvm/trunk/test/Feature/metadata.ll (original) +++ llvm/trunk/test/Feature/metadata.ll Tue Jul 13 14:33:27 2010 @@ -10,4 +10,5 @@ !named = !{!0} !0 = metadata !{i8** null} -!1 = metadata !{i8* null} +!1 = metadata !{i8* null, metadata !2} +!2 = metadata !{} From stoklund at 2pi.dk Tue Jul 13 14:42:20 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 13 Jul 2010 19:42:20 -0000 Subject: [llvm-commits] [llvm] r108261 - /llvm/trunk/lib/CodeGen/LiveInterval.cpp Message-ID: <20100713194220.61CC92A6C12C@llvm.org> Author: stoklund Date: Tue Jul 13 14:42:20 2010 New Revision: 108261 URL: http://llvm.org/viewvc/llvm-project?rev=108261&view=rev Log: Fix LiveInterval::overlaps so it doesn't claim touching intervals overlap. Also, one binary search is enough. Modified: llvm/trunk/lib/CodeGen/LiveInterval.cpp Modified: llvm/trunk/lib/CodeGen/LiveInterval.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveInterval.cpp?rev=108261&r1=108260&r2=108261&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveInterval.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveInterval.cpp Tue Jul 13 14:42:20 2010 @@ -161,16 +161,8 @@ /// by [Start, End). bool LiveInterval::overlaps(SlotIndex Start, SlotIndex End) const { assert(Start < End && "Invalid range"); - const_iterator I = begin(); - const_iterator E = end(); - const_iterator si = std::upper_bound(I, E, Start); - const_iterator ei = std::upper_bound(I, E, End); - if (si != ei) - return true; - if (si == I) - return false; - --si; - return si->contains(Start); + const_iterator I = std::lower_bound(begin(), end(), End); + return I != begin() && (--I)->end > Start; } /// extendIntervalEndTo - This method is used when we want to extend the range From gohman at apple.com Tue Jul 13 14:42:44 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 13 Jul 2010 19:42:44 -0000 Subject: [llvm-commits] [llvm] r108262 - in /llvm/trunk: lib/AsmParser/LLParser.cpp test/Feature/metadata.ll Message-ID: <20100713194244.A12512A6C12C@llvm.org> Author: djg Date: Tue Jul 13 14:42:44 2010 New Revision: 108262 URL: http://llvm.org/viewvc/llvm-project?rev=108262&view=rev Log: Add support for empty named metadata too. This isn't particularly useful, but it is nice for consistency. Modified: llvm/trunk/lib/AsmParser/LLParser.cpp llvm/trunk/test/Feature/metadata.ll Modified: llvm/trunk/lib/AsmParser/LLParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=108262&r1=108261&r2=108262&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLParser.cpp (original) +++ llvm/trunk/lib/AsmParser/LLParser.cpp Tue Jul 13 14:42:44 2010 @@ -544,20 +544,21 @@ return true; SmallVector Elts; - do { - // Null is a special case since it is typeless. - if (EatIfPresent(lltok::kw_null)) { - Elts.push_back(0); - continue; - } + if (Lex.getKind() != lltok::rbrace) + do { + // Null is a special case since it is typeless. + if (EatIfPresent(lltok::kw_null)) { + Elts.push_back(0); + continue; + } - if (ParseToken(lltok::exclaim, "Expected '!' here")) - return true; + if (ParseToken(lltok::exclaim, "Expected '!' here")) + return true; - MDNode *N = 0; - if (ParseMDNodeID(N)) return true; - Elts.push_back(N); - } while (EatIfPresent(lltok::comma)); + MDNode *N = 0; + if (ParseMDNodeID(N)) return true; + Elts.push_back(N); + } while (EatIfPresent(lltok::comma)); if (ParseToken(lltok::rbrace, "expected end of metadata node")) return true; Modified: llvm/trunk/test/Feature/metadata.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Feature/metadata.ll?rev=108262&r1=108261&r2=108262&view=diff ============================================================================== --- llvm/trunk/test/Feature/metadata.ll (original) +++ llvm/trunk/test/Feature/metadata.ll Tue Jul 13 14:42:44 2010 @@ -9,6 +9,7 @@ declare void @llvm.zonk(metadata, i64, metadata) nounwind readnone !named = !{!0} +!another_named = !{} !0 = metadata !{i8** null} !1 = metadata !{i8* null, metadata !2} !2 = metadata !{} From gohman at apple.com Tue Jul 13 14:48:13 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 13 Jul 2010 19:48:13 -0000 Subject: [llvm-commits] [llvm] r108263 - /llvm/trunk/docs/LangRef.html Message-ID: <20100713194813.9A3622A6C12C@llvm.org> Author: djg Date: Tue Jul 13 14:48:13 2010 New Revision: 108263 URL: http://llvm.org/viewvc/llvm-project?rev=108263&view=rev Log: Fix the Named Metadata example to make it clear which specific construct is the named metadata. Modified: llvm/trunk/docs/LangRef.html Modified: llvm/trunk/docs/LangRef.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=108263&r1=108262&r2=108263&view=diff ============================================================================== --- llvm/trunk/docs/LangRef.html (original) +++ llvm/trunk/docs/LangRef.html Tue Jul 13 14:48:13 2010 @@ -954,7 +954,9 @@

Syntax:
+; An unnamed metadata node, which is referenced by the named metadata.
 !1 = metadata !{metadata !"one"}
+; A named metadata.
 !name = !{null, !1}
From stoklund at 2pi.dk Tue Jul 13 14:56:28 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 13 Jul 2010 19:56:28 -0000 Subject: [llvm-commits] [llvm] r108264 - /llvm/trunk/lib/CodeGen/LiveInterval.cpp Message-ID: <20100713195628.2FB7F2A6C12D@llvm.org> Author: stoklund Date: Tue Jul 13 14:56:28 2010 New Revision: 108264 URL: http://llvm.org/viewvc/llvm-project?rev=108264&view=rev Log: Add an assertion to make PR7542 fail consistently. LiveInterval::overlapsFrom dereferences end() if it is called on an empty interval. It would be reasonable to just return false - an empty interval doesn't overlap anything, but I want to know who is doing it first. Modified: llvm/trunk/lib/CodeGen/LiveInterval.cpp Modified: llvm/trunk/lib/CodeGen/LiveInterval.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveInterval.cpp?rev=108264&r1=108263&r2=108264&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveInterval.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveInterval.cpp Tue Jul 13 14:56:28 2010 @@ -119,6 +119,7 @@ // bool LiveInterval::overlapsFrom(const LiveInterval& other, const_iterator StartPos) const { + assert(!empty() && "empty interval"); const_iterator i = begin(); const_iterator ie = end(); const_iterator j = StartPos; From enderby at apple.com Tue Jul 13 15:05:41 2010 From: enderby at apple.com (Kevin Enderby) Date: Tue, 13 Jul 2010 20:05:41 -0000 Subject: [llvm-commits] [llvm] r108265 - /llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Message-ID: <20100713200541.5A9C52A6C12C@llvm.org> Author: enderby Date: Tue Jul 13 15:05:41 2010 New Revision: 108265 URL: http://llvm.org/viewvc/llvm-project?rev=108265&view=rev Log: Added a check that pusha cannot be encoded in 64-bit mode. Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=108265&r1=108264&r2=108265&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Tue Jul 13 15:05:41 2010 @@ -612,6 +612,8 @@ return Error(NameLoc, "popfl cannot be encoded in 64-bit mode"); else if (Name == "pushfl") return Error(NameLoc, "pushfl cannot be encoded in 64-bit mode"); + else if (Name == "pusha") + return Error(NameLoc, "pusha cannot be encoded in 64-bit mode"); } else { if (Name == "popfq") return Error(NameLoc, "popfq cannot be encoded in 32-bit mode"); From dalej at apple.com Tue Jul 13 15:17:05 2010 From: dalej at apple.com (Dale Johannesen) Date: Tue, 13 Jul 2010 20:17:05 -0000 Subject: [llvm-commits] [llvm] r108268 - in /llvm/trunk: lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp test/CodeGen/X86/2010-07-13-indirectXconstraint.ll Message-ID: <20100713201705.899D92A6C12C@llvm.org> Author: johannes Date: Tue Jul 13 15:17:05 2010 New Revision: 108268 URL: http://llvm.org/viewvc/llvm-project?rev=108268&view=rev Log: In inline asm treat indirect 'X' constraint as 'm'. This may not be right in all cases, but it's better than asserting which it was doing before. PR 7528. Added: llvm/trunk/test/CodeGen/X86/2010-07-13-indirectXconstraint.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=108268&r1=108267&r2=108268&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Tue Jul 13 15:17:05 2010 @@ -5522,10 +5522,12 @@ break; } - if (OpInfo.ConstraintType == TargetLowering::C_Other) { - assert(!OpInfo.isIndirect && - "Don't know how to handle indirect other inputs yet!"); + // Treat indirect 'X' constraint as memory. + if (OpInfo.ConstraintType == TargetLowering::C_Other && + OpInfo.isIndirect) + OpInfo.ConstraintType = TargetLowering::C_Memory; + if (OpInfo.ConstraintType == TargetLowering::C_Other) { std::vector Ops; TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0], Ops, DAG); Added: llvm/trunk/test/CodeGen/X86/2010-07-13-indirectXconstraint.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-07-13-indirectXconstraint.ll?rev=108268&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2010-07-13-indirectXconstraint.ll (added) +++ llvm/trunk/test/CodeGen/X86/2010-07-13-indirectXconstraint.ll Tue Jul 13 15:17:05 2010 @@ -0,0 +1,18 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s +; PR 7528 +; formerly crashed + +%0 = type { [12 x i16] } +%union..0anon = type { [3 x <1 x i64>] } + + at gsm_H.1466 = internal constant %0 { [12 x i16] [i16 -134, i16 -374, i16 0, i16 2054, i16 5741, i16 8192, i16 5741, i16 2054, i16 0, i16 -374, i16 -134, i16 0] }, align 8 ; <%0*> [#uses=1] + +define void @weighting_filter() nounwind ssp { +entry: +; CHECK: leaq _gsm_H.1466(%rip),%rax; + call void asm sideeffect "leaq $0,%rax;\0A", "*X,~{dirflag},~{fpsr},~{flags},~{memory},~{rax}"(%union..0anon* bitcast (%0* @gsm_H.1466 to %union..0anon*)) nounwind + br label %return + +return: ; preds = %entry + ret void +} From wdietz2 at illinois.edu Tue Jul 13 15:20:17 2010 From: wdietz2 at illinois.edu (Will Dietz) Date: Tue, 13 Jul 2010 20:20:17 -0000 Subject: [llvm-commits] [poolalloc] r108269 - /poolalloc/trunk/lib/DSA/CompleteBottomUp.cpp Message-ID: <20100713202017.1FC772A6C12E@llvm.org> Author: wdietz2 Date: Tue Jul 13 15:20:16 2010 New Revision: 108269 URL: http://llvm.org/viewvc/llvm-project?rev=108269&view=rev Log: Make CBU fail gracefully (assert) if there is no entry for a given function. Modified: poolalloc/trunk/lib/DSA/CompleteBottomUp.cpp Modified: poolalloc/trunk/lib/DSA/CompleteBottomUp.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/CompleteBottomUp.cpp?rev=108269&r1=108268&r2=108269&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/CompleteBottomUp.cpp (original) +++ poolalloc/trunk/lib/DSA/CompleteBottomUp.cpp Tue Jul 13 15:20:16 2010 @@ -54,10 +54,13 @@ DSCallGraph::callee_iterator csi = callgraph.callee_begin(*ii), cse = callgraph.callee_end(*ii); if (csi != cse && SM.find(*csi) != SM.end()) { + assert((SM.find(*csi) != SM.end()) && "Function not in Global graph?"); DSNodeHandle& SrcNH = SM.find(*csi)->second; ++csi; - for (; csi != cse; ++csi) + for (; csi != cse; ++csi) { + assert((SM.find(*csi) != SM.end()) && "Function not in Global graph?"); SrcNH.mergeWith(SM.find(*csi)->second); + } } } } From gohman at apple.com Tue Jul 13 15:22:18 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 13 Jul 2010 13:22:18 -0700 Subject: [llvm-commits] [llvm] r107943 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/Support/ include/llvm/Target/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/X86/ lib/Target/XCore/ test/CodeGen/X86/ In-Reply-To: <4C36D60B.9050807@free.fr> References: <20100709003923.A1CA72A6C12C@llvm.org> <4C36D60B.9050807@free.fr> Message-ID: On Jul 9, 2010, at 12:55 AM, Duncan Sands wrote: >> --- llvm/trunk/include/llvm/Support/PassNameParser.h (original) >> +++ llvm/trunk/include/llvm/Support/PassNameParser.h Thu Jul 8 19:39:23 2010 >> @@ -69,6 +69,7 @@ >> virtual void passRegistered(const PassInfo *P) { >> if (ignorablePass(P) || !Opt) return; >> if (findOption(P->getPassArgument()) != getNumOptions()) { >> + return; >> errs()<< "Two passes with the same argument (-" >> << P->getPassArgument()<< ") attempted to be registered!\n"; >> llvm_unreachable(0); > > Did you mean to apply this bit? Nope, it was a mistake. Dan From evan.cheng at apple.com Tue Jul 13 16:03:14 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 13 Jul 2010 21:03:14 -0000 Subject: [llvm-commits] [llvm] r108272 - /llvm/trunk/include/llvm/Target/TargetOptions.h Message-ID: <20100713210314.4C78F2A6C12C@llvm.org> Author: evancheng Date: Tue Jul 13 16:03:14 2010 New Revision: 108272 URL: http://llvm.org/viewvc/llvm-project?rev=108272&view=rev Log: Update comment. Modified: llvm/trunk/include/llvm/Target/TargetOptions.h Modified: llvm/trunk/include/llvm/Target/TargetOptions.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetOptions.h?rev=108272&r1=108271&r2=108272&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetOptions.h (original) +++ llvm/trunk/include/llvm/Target/TargetOptions.h Tue Jul 13 16:03:14 2010 @@ -68,7 +68,7 @@ /// this flag is off (the default), the code generator is not allowed to /// produce results that are "less precise" than IEEE allows. This includes /// use of X86 instructions like FSIN and FCOS instead of libcalls. - /// UnsafeFPMath implies FiniteOnlyFPMath and LessPreciseFPMAD. + /// UnsafeFPMath implies LessPreciseFPMAD. extern bool UnsafeFPMath; /// FiniteOnlyFPMath - This returns true when the -enable-finite-only-fp-math From bruno.cardoso at gmail.com Tue Jul 13 16:07:28 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 13 Jul 2010 21:07:28 -0000 Subject: [llvm-commits] [llvm] r108274 - in /llvm/trunk: lib/Target/X86/X86InstrFormats.td lib/Target/X86/X86InstrInfo.h lib/Target/X86/X86InstrSSE.td lib/Target/X86/X86MCCodeEmitter.cpp test/MC/AsmParser/X86/x86_32-encoding.s test/MC/AsmParser/X86/x86_64-encoding.s Message-ID: <20100713210729.1A0472A6C12C@llvm.org> Author: bruno Date: Tue Jul 13 16:07:28 2010 New Revision: 108274 URL: http://llvm.org/viewvc/llvm-project?rev=108274&view=rev Log: AVX 256-bit conversion instructions Add the x86 VEX_L form to handle special cases where VEX_L must be set. Modified: llvm/trunk/lib/Target/X86/X86InstrFormats.td llvm/trunk/lib/Target/X86/X86InstrInfo.h llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s Modified: llvm/trunk/lib/Target/X86/X86InstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFormats.td?rev=108274&r1=108273&r2=108274&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrFormats.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrFormats.td Tue Jul 13 16:07:28 2010 @@ -106,6 +106,7 @@ class VEX_W { bit hasVEX_WPrefix = 1; } class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; } class VEX_I8IMM { bit hasVEX_i8ImmReg = 1; } +class VEX_L { bit hasVEX_L = 1; } class X86Inst opcod, Format f, ImmType i, dag outs, dag ins, string AsmStr, Domain d = GenericDomain> @@ -138,6 +139,7 @@ bit hasVEX_4VPrefix = 0; // Does this inst requires the VEX.VVVV field? bit hasVEX_i8ImmReg = 0; // Does this inst requires the last source register // to be encoded in a immediate field? + bit hasVEX_L = 0; // Does this inst uses large (256-bit) registers? // TSFlags layout should be kept in sync with X86InstrInfo.h. let TSFlags{5-0} = FormBits; @@ -155,6 +157,7 @@ let TSFlags{33} = hasVEX_WPrefix; let TSFlags{34} = hasVEX_4VPrefix; let TSFlags{35} = hasVEX_i8ImmReg; + let TSFlags{36} = hasVEX_L; } class I o, Format f, dag outs, dag ins, string asm, Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=108274&r1=108273&r2=108274&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Tue Jul 13 16:07:28 2010 @@ -453,7 +453,13 @@ // VEX_I8IMM - Specifies that the last register used in a AVX instruction, // must be encoded in the i8 immediate field. This usually happens in // instructions with 4 operands. - VEX_I8IMM = 1ULL << 35 + VEX_I8IMM = 1ULL << 35, + + // VEX_L - Stands for a bit in the VEX opcode prefix meaning the current + // instruction uses 256-bit wide registers. This is usually auto detected if + // a VR256 register is used, but some AVX instructions also have this field + // marked when using a f256 memory references. + VEX_L = 1ULL << 36 }; // getBaseOpcodeFor - This function returns the "base" X86 opcode for the Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=108274&r1=108273&r2=108274&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Jul 13 16:07:28 2010 @@ -666,6 +666,9 @@ defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, f128mem, load, "cvtdq2ps\t{$src, $dst|$dst, $src}", SSEPackedSingle>, TB, VEX; +defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, f256mem, load, + "cvtdq2ps\t{$src, $dst|$dst, $src}", + SSEPackedSingle>, TB, VEX; } let Pattern = [] in { defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/, @@ -806,9 +809,13 @@ // Convert packed single/double fp to doubleword let isAsmParserOnly = 1 in { def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), - "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX; + "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX; def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), - "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX; + "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX; +def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src), + "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX; +def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src), + "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX; } def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "cvtps2dq\t{$src, $dst|$dst, $src}", []>; @@ -862,6 +869,10 @@ "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX; def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX; +def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src), + "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX; +def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src), + "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX; } def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "cvttps2dq\t{$src, $dst|$dst, $src}", []>; @@ -912,14 +923,39 @@ [(set VR128:$dst, (int_x86_sse2_cvttpd2dq (memop addr:$src)))]>; +let isAsmParserOnly = 1 in { +// The assembler can recognize rr 256-bit instructions by seeing a ymm +// register, but the same isn't true when using memory operands instead. +// Provide other assembly rr and rm forms to address this explicitly. +def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX; +def VCVTTPD2DQXrYr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src), + "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX; + +// XMM only +def VCVTTPD2DQXrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX; +def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), + "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX; + +// YMM only +def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src), + "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX; +def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src), + "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L; +} + // Convert packed single to packed double -let isAsmParserOnly = 1 in { // SSE2 instructions without OpSize prefix +let isAsmParserOnly = 1, Predicates = [HasAVX] in { + // SSE2 instructions without OpSize prefix def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), - "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX, - Requires<[HasAVX]>; + "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX; def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src), - "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX, - Requires<[HasAVX]>; + "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX; +def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src), + "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX; +def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src), + "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX; } def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB; @@ -949,10 +985,25 @@ // Convert packed double to packed single let isAsmParserOnly = 1 in { +// The assembler can recognize rr 256-bit instructions by seeing a ymm +// register, but the same isn't true when using memory operands instead. +// Provide other assembly rr and rm forms to address this explicitly. def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), - "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX; -// FIXME: the memory form of this instruction should described using -// use extra asm syntax + "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX; +def VCVTPD2PSXrYr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src), + "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX; + +// XMM only +def VCVTPD2PSXrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX; +def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), + "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX; + +// YMM only +def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src), + "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX; +def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src), + "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L; } def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "cvtpd2ps\t{$src, $dst|$dst, $src}", []>; @@ -2935,19 +2986,46 @@ // SSE3 - Conversion Instructions //===---------------------------------------------------------------------===// +// Convert Packed Double FP to Packed DW Integers let isAsmParserOnly = 1, Predicates = [HasAVX] in { +// The assembler can recognize rr 256-bit instructions by seeing a ymm +// register, but the same isn't true when using memory operands instead. +// Provide other assembly rr and rm forms to address this explicitly. def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX; -def VCVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), - "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX; -def VCVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), - "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX; +def VCVTPD2DQXrYr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src), + "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX; + +// XMM only +def VCVTPD2DQXrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX; +def VCVTPD2DQXrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), + "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX; + +// YMM only +def VCVTPD2DQYrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src), + "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX; +def VCVTPD2DQYrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src), + "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L; } def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), "cvtpd2dq\t{$src, $dst|$dst, $src}", []>; def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "cvtpd2dq\t{$src, $dst|$dst, $src}", []>; + +// Convert Packed DW Integers to Packed Double FP +let isAsmParserOnly = 1, Predicates = [HasAVX] in { +def VCVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), + "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX; +def VCVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX; +def VCVTDQ2PDYrm : S3SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src), + "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX; +def VCVTDQ2PDYrr : S3SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src), + "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX; +} + def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), "cvtdq2pd\t{$src, $dst|$dst, $src}", []>; def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), Modified: llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp?rev=108274&r1=108273&r2=108274&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp Tue Jul 13 16:07:28 2010 @@ -432,6 +432,9 @@ if (TSFlags & X86II::VEX_W) VEX_W = 1; + if (TSFlags & X86II::VEX_L) + VEX_L = 1; + switch (TSFlags & X86II::Op0Mask) { default: assert(0 && "Invalid prefix!"); case X86II::T8: // 0F 38 Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s?rev=108274&r1=108273&r2=108274&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s Tue Jul 13 16:07:28 2010 @@ -12598,3 +12598,107 @@ // CHECK: encoding: [0xc5,0xed,0x55,0x6c,0xcb,0xfc] vandnpd -4(%ebx,%ecx,8), %ymm2, %ymm5 +// CHECK: vcvtps2pd %xmm3, %ymm2 +// CHECK: encoding: [0xc5,0xfc,0x5a,0xd3] + vcvtps2pd %xmm3, %ymm2 + +// CHECK: vcvtps2pd (%eax), %ymm2 +// CHECK: encoding: [0xc5,0xfc,0x5a,0x10] + vcvtps2pd (%eax), %ymm2 + +// CHECK: vcvtdq2pd %xmm3, %ymm2 +// CHECK: encoding: [0xc5,0xfe,0xe6,0xd3] + vcvtdq2pd %xmm3, %ymm2 + +// CHECK: vcvtdq2pd (%eax), %ymm2 +// CHECK: encoding: [0xc5,0xfe,0xe6,0x10] + vcvtdq2pd (%eax), %ymm2 + +// CHECK: vcvtdq2ps %ymm2, %ymm5 +// CHECK: encoding: [0xc5,0xfc,0x5b,0xea] + vcvtdq2ps %ymm2, %ymm5 + +// CHECK: vcvtdq2ps (%eax), %ymm2 +// CHECK: encoding: [0xc5,0xfc,0x5b,0x10] + vcvtdq2ps (%eax), %ymm2 + +// CHECK: vcvtps2dq %ymm2, %ymm5 +// CHECK: encoding: [0xc5,0xfd,0x5b,0xea] + vcvtps2dq %ymm2, %ymm5 + +// CHECK: vcvtps2dq (%eax), %ymm5 +// CHECK: encoding: [0xc5,0xfd,0x5b,0x28] + vcvtps2dq (%eax), %ymm5 + +// CHECK: vcvttps2dq %ymm2, %ymm5 +// CHECK: encoding: [0xc5,0xfe,0x5b,0xea] + vcvttps2dq %ymm2, %ymm5 + +// CHECK: vcvttps2dq (%eax), %ymm5 +// CHECK: encoding: [0xc5,0xfe,0x5b,0x28] + vcvttps2dq (%eax), %ymm5 + +// CHECK: vcvttpd2dq %xmm1, %xmm5 +// CHECK: encoding: [0xc5,0xf9,0xe6,0xe9] + vcvttpd2dq %xmm1, %xmm5 + +// CHECK: vcvttpd2dq %ymm2, %xmm5 +// CHECK: encoding: [0xc5,0xfd,0xe6,0xea] + vcvttpd2dq %ymm2, %xmm5 + +// CHECK: vcvttpd2dqx %xmm1, %xmm5 +// CHECK: encoding: [0xc5,0xf9,0xe6,0xe9] + vcvttpd2dqx %xmm1, %xmm5 + +// CHECK: vcvttpd2dqx (%eax), %xmm1 +// CHECK: encoding: [0xc5,0xf9,0xe6,0x08] + vcvttpd2dqx (%eax), %xmm1 + +// CHECK: vcvttpd2dqy %ymm2, %xmm1 +// CHECK: encoding: [0xc5,0xfd,0xe6,0xca] + vcvttpd2dqy %ymm2, %xmm1 + +// CHECK: vcvttpd2dqy (%eax), %xmm1 +// CHECK: encoding: [0xc5,0xfd,0xe6,0x08] + vcvttpd2dqy (%eax), %xmm1 + +// CHECK: vcvtpd2ps %ymm2, %xmm5 +// CHECK: encoding: [0xc5,0xfd,0x5a,0xea] + vcvtpd2ps %ymm2, %xmm5 + +// CHECK: vcvtpd2psx %xmm1, %xmm5 +// CHECK: encoding: [0xc5,0xf9,0x5a,0xe9] + vcvtpd2psx %xmm1, %xmm5 + +// CHECK: vcvtpd2psx (%eax), %xmm1 +// CHECK: encoding: [0xc5,0xf9,0x5a,0x08] + vcvtpd2psx (%eax), %xmm1 + +// CHECK: vcvtpd2psy %ymm2, %xmm1 +// CHECK: encoding: [0xc5,0xfd,0x5a,0xca] + vcvtpd2psy %ymm2, %xmm1 + +// CHECK: vcvtpd2psy (%eax), %xmm1 +// CHECK: encoding: [0xc5,0xfd,0x5a,0x08] + vcvtpd2psy (%eax), %xmm1 + +// CHECK: vcvtpd2dq %ymm2, %xmm5 +// CHECK: encoding: [0xc5,0xff,0xe6,0xea] + vcvtpd2dq %ymm2, %xmm5 + +// CHECK: vcvtpd2dqy %ymm2, %xmm1 +// CHECK: encoding: [0xc5,0xff,0xe6,0xca] + vcvtpd2dqy %ymm2, %xmm1 + +// CHECK: vcvtpd2dqy (%eax), %xmm1 +// CHECK: encoding: [0xc5,0xff,0xe6,0x08] + vcvtpd2dqy (%eax), %xmm1 + +// CHECK: vcvtpd2dqx %xmm1, %xmm5 +// CHECK: encoding: [0xc5,0xfb,0xe6,0xe9] + vcvtpd2dqx %xmm1, %xmm5 + +// CHECK: vcvtpd2dqx (%eax), %xmm1 +// CHECK: encoding: [0xc5,0xfb,0xe6,0x08] + vcvtpd2dqx (%eax), %xmm1 + Modified: llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s?rev=108274&r1=108273&r2=108274&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s Tue Jul 13 16:07:28 2010 @@ -2672,3 +2672,107 @@ // CHECK: encoding: [0xc5,0x1d,0x55,0x54,0xcb,0xfc] vandnpd -4(%rbx,%rcx,8), %ymm12, %ymm10 +// CHECK: vcvtps2pd %xmm13, %ymm12 +// CHECK: encoding: [0xc4,0x41,0x7c,0x5a,0xe5] + vcvtps2pd %xmm13, %ymm12 + +// CHECK: vcvtps2pd (%rax), %ymm12 +// CHECK: encoding: [0xc5,0x7c,0x5a,0x20] + vcvtps2pd (%rax), %ymm12 + +// CHECK: vcvtdq2pd %xmm13, %ymm12 +// CHECK: encoding: [0xc4,0x41,0x7e,0xe6,0xe5] + vcvtdq2pd %xmm13, %ymm12 + +// CHECK: vcvtdq2pd (%rax), %ymm12 +// CHECK: encoding: [0xc5,0x7e,0xe6,0x20] + vcvtdq2pd (%rax), %ymm12 + +// CHECK: vcvtdq2ps %ymm12, %ymm10 +// CHECK: encoding: [0xc4,0x41,0x7c,0x5b,0xd4] + vcvtdq2ps %ymm12, %ymm10 + +// CHECK: vcvtdq2ps (%rax), %ymm12 +// CHECK: encoding: [0xc5,0x7c,0x5b,0x20] + vcvtdq2ps (%rax), %ymm12 + +// CHECK: vcvtps2dq %ymm12, %ymm10 +// CHECK: encoding: [0xc4,0x41,0x7d,0x5b,0xd4] + vcvtps2dq %ymm12, %ymm10 + +// CHECK: vcvtps2dq (%rax), %ymm10 +// CHECK: encoding: [0xc5,0x7d,0x5b,0x10] + vcvtps2dq (%rax), %ymm10 + +// CHECK: vcvttps2dq %ymm12, %ymm10 +// CHECK: encoding: [0xc4,0x41,0x7e,0x5b,0xd4] + vcvttps2dq %ymm12, %ymm10 + +// CHECK: vcvttps2dq (%rax), %ymm10 +// CHECK: encoding: [0xc5,0x7e,0x5b,0x10] + vcvttps2dq (%rax), %ymm10 + +// CHECK: vcvttpd2dq %xmm11, %xmm10 +// CHECK: encoding: [0xc4,0x41,0x79,0xe6,0xd3] + vcvttpd2dq %xmm11, %xmm10 + +// CHECK: vcvttpd2dq %ymm12, %xmm10 +// CHECK: encoding: [0xc4,0x41,0x7d,0xe6,0xd4] + vcvttpd2dq %ymm12, %xmm10 + +// CHECK: vcvttpd2dqx %xmm11, %xmm10 +// CHECK: encoding: [0xc4,0x41,0x79,0xe6,0xd3] + vcvttpd2dqx %xmm11, %xmm10 + +// CHECK: vcvttpd2dqx (%rax), %xmm11 +// CHECK: encoding: [0xc5,0x79,0xe6,0x18] + vcvttpd2dqx (%rax), %xmm11 + +// CHECK: vcvttpd2dqy %ymm12, %xmm11 +// CHECK: encoding: [0xc4,0x41,0x7d,0xe6,0xdc] + vcvttpd2dqy %ymm12, %xmm11 + +// CHECK: vcvttpd2dqy (%rax), %xmm11 +// CHECK: encoding: [0xc5,0x7d,0xe6,0x18] + vcvttpd2dqy (%rax), %xmm11 + +// CHECK: vcvtpd2ps %ymm12, %xmm10 +// CHECK: encoding: [0xc4,0x41,0x7d,0x5a,0xd4] + vcvtpd2ps %ymm12, %xmm10 + +// CHECK: vcvtpd2psx %xmm11, %xmm10 +// CHECK: encoding: [0xc4,0x41,0x79,0x5a,0xd3] + vcvtpd2psx %xmm11, %xmm10 + +// CHECK: vcvtpd2psx (%rax), %xmm11 +// CHECK: encoding: [0xc5,0x79,0x5a,0x18] + vcvtpd2psx (%rax), %xmm11 + +// CHECK: vcvtpd2psy %ymm12, %xmm11 +// CHECK: encoding: [0xc4,0x41,0x7d,0x5a,0xdc] + vcvtpd2psy %ymm12, %xmm11 + +// CHECK: vcvtpd2psy (%rax), %xmm11 +// CHECK: encoding: [0xc5,0x7d,0x5a,0x18] + vcvtpd2psy (%rax), %xmm11 + +// CHECK: vcvtpd2dq %ymm12, %xmm10 +// CHECK: encoding: [0xc4,0x41,0x7f,0xe6,0xd4] + vcvtpd2dq %ymm12, %xmm10 + +// CHECK: vcvtpd2dqy %ymm12, %xmm11 +// CHECK: encoding: [0xc4,0x41,0x7f,0xe6,0xdc] + vcvtpd2dqy %ymm12, %xmm11 + +// CHECK: vcvtpd2dqy (%rax), %xmm11 +// CHECK: encoding: [0xc5,0x7f,0xe6,0x18] + vcvtpd2dqy (%rax), %xmm11 + +// CHECK: vcvtpd2dqx %xmm11, %xmm10 +// CHECK: encoding: [0xc4,0x41,0x7b,0xe6,0xd3] + vcvtpd2dqx %xmm11, %xmm10 + +// CHECK: vcvtpd2dqx (%rax), %xmm11 +// CHECK: encoding: [0xc5,0x7b,0xe6,0x18] + vcvtpd2dqx (%rax), %xmm11 + From gkistanova at gmail.com Tue Jul 13 13:29:25 2010 From: gkistanova at gmail.com (Galina Kistanova) Date: Tue, 13 Jul 2010 11:29:25 -0700 Subject: [llvm-commits] [zorg] r106933 - /zorg/trunk/buildbot/osuosl/master/config/status.py In-Reply-To: <4C35ED3C.8070703@free.fr> References: <20100626003739.319A82A6C12C@llvm.org> <4C35ED3C.8070703@free.fr> Message-ID: Hi Duncan, Seems the notifier does not work as I expected unfortunatly. The same change works fine at my local master. May be Daniel could find what is wrong with it? Thanks Galina On Thu, Jul 8, 2010 at 8:22 AM, Duncan Sands wrote: > Hi Galina, > >> Added e-mail notifier for dragonegg builders which sends the last 15 lines >> of stdio > > unfortunately it doesn't seem to do so... ?For example, see > http://lists.cs.uiuc.edu/pipermail/llvm-testresults/2010-July/027328.html > Any idea what's up? > > Ciao, > > Duncan. > From bob.wilson at apple.com Tue Jul 13 16:16:48 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 13 Jul 2010 21:16:48 -0000 Subject: [llvm-commits] [llvm] r108275 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMISelLowering.h lib/Target/ARM/ARMInstrNEON.td test/CodeGen/ARM/reg_sequence.ll Message-ID: <20100713211649.196412A6C12C@llvm.org> Author: bwilson Date: Tue Jul 13 16:16:48 2010 New Revision: 108275 URL: http://llvm.org/viewvc/llvm-project?rev=108275&view=rev Log: Use a target-specific VMOVIMM DAG node instead of BUILD_VECTOR to represent NEON VMOV-immediate instructions. This simplifies some things. Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.h llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/test/CodeGen/ARM/reg_sequence.ll Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=108275&r1=108274&r2=108275&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Jul 13 16:16:48 2010 @@ -624,6 +624,7 @@ case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu"; case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu"; case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs"; + case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM"; case ARMISD::VDUP: return "ARMISD::VDUP"; case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE"; case ARMISD::VEXT: return "ARMISD::VEXT"; @@ -2644,51 +2645,18 @@ } /// getZeroVector - Returns a vector of specified type with all zero elements. -/// +/// Zero vectors are used to represent vector negation and in those cases +/// will be implemented with the NEON VNEG instruction. However, VNEG does +/// not support i64 elements, so sometimes the zero vectors will need to be +/// explicitly constructed. Regardless, use a canonical VMOV to create the +/// zero vector. static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) { assert(VT.isVector() && "Expected a vector type"); - - // Zero vectors are used to represent vector negation and in those cases - // will be implemented with the NEON VNEG instruction. However, VNEG does - // not support i64 elements, so sometimes the zero vectors will need to be - // explicitly constructed. For those cases, and potentially other uses in - // the future, always build zero vectors as <16 x i8> or <8 x i8> bitcasted - // to their dest type. This ensures they get CSE'd. - SDValue Vec; - SDValue Cst = DAG.getTargetConstant(0, MVT::i8); - SmallVector Ops; - MVT TVT; - - if (VT.getSizeInBits() == 64) { - Ops.assign(8, Cst); TVT = MVT::v8i8; - } else { - Ops.assign(16, Cst); TVT = MVT::v16i8; - } - Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, TVT, &Ops[0], Ops.size()); - - return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec); -} - -/// getOnesVector - Returns a vector of specified type with all bits set. -/// -static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) { - assert(VT.isVector() && "Expected a vector type"); - - // Always build ones vectors as <16 x i8> or <8 x i8> bitcasted to their - // dest type. This ensures they get CSE'd. - SDValue Vec; - SDValue Cst = DAG.getTargetConstant(0xFF, MVT::i8); - SmallVector Ops; - MVT TVT; - - if (VT.getSizeInBits() == 64) { - Ops.assign(8, Cst); TVT = MVT::v8i8; - } else { - Ops.assign(16, Cst); TVT = MVT::v16i8; - } - Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, TVT, &Ops[0], Ops.size()); - - return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec); + // The canonical modified immediate encoding of a zero vector is....0! + SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32); + EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32; + SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal); + return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov); } /// LowerShiftRightParts - Lower SRA_PARTS, which returns two @@ -2941,13 +2909,11 @@ /// isNEONModifiedImm - Check if the specified splat value corresponds to a /// valid vector constant for a NEON instruction with a "modified immediate" -/// operand (e.g., VMOV). If so, return either the constant being -/// splatted or the encoded value, depending on the DoEncode parameter. +/// operand (e.g., VMOV). If so, return the encoded value. static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef, unsigned SplatBitSize, SelectionDAG &DAG, - bool isVMOV, bool DoEncode) { + EVT &VT, bool is128Bits, bool isVMOV) { unsigned OpCmode, Imm; - EVT VT; // SplatBitSize is set to the smallest size that splats the vector, so a // zero vector will always have SplatBitSize == 8. However, NEON modified @@ -2963,12 +2929,12 @@ assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big"); OpCmode = 0xe; Imm = SplatBits; - VT = MVT::i8; + VT = is128Bits ? MVT::v16i8 : MVT::v8i8; break; case 16: // NEON's 16-bit VMOV supports splat values where only one byte is nonzero. - VT = MVT::i16; + VT = is128Bits ? MVT::v8i16 : MVT::v4i16; if ((SplatBits & ~0xff) == 0) { // Value = 0x00nn: Op=x, Cmode=100x. OpCmode = 0x8; @@ -2988,7 +2954,7 @@ // * only one byte is nonzero, or // * the least significant byte is 0xff and the second byte is nonzero, or // * the least significant 2 bytes are 0xff and the third is nonzero. - VT = MVT::i32; + VT = is128Bits ? MVT::v4i32 : MVT::v2i32; if ((SplatBits & ~0xff) == 0) { // Value = 0x000000nn: Op=x, Cmode=000x. OpCmode = 0; @@ -3060,7 +3026,7 @@ // Op=1, Cmode=1110. OpCmode = 0x1e; SplatBits = Val; - VT = MVT::i64; + VT = is128Bits ? MVT::v2i64 : MVT::v1i64; break; } @@ -3069,32 +3035,8 @@ return SDValue(); } - if (DoEncode) { - unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm); - return DAG.getTargetConstant(EncodedVal, MVT::i32); - } - return DAG.getTargetConstant(SplatBits, VT); -} - -/// getNEONModImm - If this is a valid vector constant for a NEON instruction -/// with a "modified immediate" operand (e.g., VMOV) of the specified element -/// size, return the encoded value for that immediate. The ByteSize field -/// indicates the number of bytes of each element [1248]. -SDValue ARM::getNEONModImm(SDNode *N, unsigned ByteSize, bool isVMOV, - SelectionDAG &DAG) { - BuildVectorSDNode *BVN = dyn_cast(N); - APInt SplatBits, SplatUndef; - unsigned SplatBitSize; - bool HasAnyUndefs; - if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, - HasAnyUndefs, ByteSize * 8)) - return SDValue(); - - if (SplatBitSize > ByteSize * 8) - return SDValue(); - - return isNEONModifiedImm(SplatBits.getZExtValue(), SplatUndef.getZExtValue(), - SplatBitSize, DAG, isVMOV, true); + unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm); + return DAG.getTargetConstant(EncodedVal, MVT::i32); } static bool isVEXTMask(const SmallVectorImpl &M, EVT VT, @@ -3285,43 +3227,6 @@ return true; } - -static SDValue BuildSplat(SDValue Val, EVT VT, SelectionDAG &DAG, DebugLoc dl) { - // Canonicalize all-zeros and all-ones vectors. - ConstantSDNode *ConstVal = cast(Val.getNode()); - if (ConstVal->isNullValue()) - return getZeroVector(VT, DAG, dl); - if (ConstVal->isAllOnesValue()) - return getOnesVector(VT, DAG, dl); - - EVT CanonicalVT; - if (VT.is64BitVector()) { - switch (Val.getValueType().getSizeInBits()) { - case 8: CanonicalVT = MVT::v8i8; break; - case 16: CanonicalVT = MVT::v4i16; break; - case 32: CanonicalVT = MVT::v2i32; break; - case 64: CanonicalVT = MVT::v1i64; break; - default: llvm_unreachable("unexpected splat element type"); break; - } - } else { - assert(VT.is128BitVector() && "unknown splat vector size"); - switch (Val.getValueType().getSizeInBits()) { - case 8: CanonicalVT = MVT::v16i8; break; - case 16: CanonicalVT = MVT::v8i16; break; - case 32: CanonicalVT = MVT::v4i32; break; - case 64: CanonicalVT = MVT::v2i64; break; - default: llvm_unreachable("unexpected splat element type"); break; - } - } - - // Build a canonical splat for this value. - SmallVector Ops; - Ops.assign(CanonicalVT.getVectorNumElements(), Val); - SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, &Ops[0], - Ops.size()); - return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Res); -} - // If this is a case we can't handle, return null and let the default // expansion code take care of it. static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { @@ -3335,11 +3240,14 @@ if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { if (SplatBitSize <= 64) { // Check if an immediate VMOV works. + EVT VmovVT; SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(), - SplatUndef.getZExtValue(), - SplatBitSize, DAG, true, false); - if (Val.getNode()) - return BuildSplat(Val, VT, DAG, dl); + SplatUndef.getZExtValue(), SplatBitSize, + DAG, VmovVT, VT.is128BitVector(), true); + if (Val.getNode()) { + SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val); + return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov); + } } } Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=108275&r1=108274&r2=108275&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Tue Jul 13 16:16:48 2010 @@ -125,6 +125,7 @@ VGETLANEs, // sign-extend vector extract element // Vector duplicate: + VMOVIMM, VDUP, VDUPLANE, @@ -152,13 +153,6 @@ /// Define some predicates that are used for node matching. namespace ARM { - /// getNEONModImm - If this is a valid vector constant for a NEON - /// instruction with a "modified immediate" operand (e.g., VMOV) of the - /// specified element size, return the encoded value for that immediate. - /// The ByteSize field indicates the number of bytes of each element [1248]. - SDValue getNEONModImm(SDNode *N, unsigned ByteSize, bool isVMOV, - SelectionDAG &DAG); - /// getVFPf32Imm / getVFPf64Imm - If the given fp immediate can be /// materialized with a VMOV.f32 / VMOV.f64 (i.e. fconsts / fconstd) /// instruction, returns its 8-bit integer representation. Otherwise, Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=108275&r1=108274&r2=108275&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Jul 13 16:16:48 2010 @@ -65,6 +65,9 @@ def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>; def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>; +def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", + SDTypeProfile<1, 1, [SDTCisVec<0>, + SDTCisVT<1, i32>]>>; def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>; // VDUPLANE can produce a quad-register result from a double-register source, @@ -94,6 +97,20 @@ def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>; def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>; +def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{ + ConstantSDNode *ConstVal = cast(N->getOperand(0)); + unsigned EltBits; + uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits); + return (EltBits == 32 && EltVal == 0); +}]>; + +def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{ + ConstantSDNode *ConstVal = cast(N->getOperand(0)); + unsigned EltBits; + uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits); + return (EltBits == 8 && EltVal == 0xff); +}]>; + //===----------------------------------------------------------------------===// // NEON operand definitions //===----------------------------------------------------------------------===// @@ -2318,10 +2335,10 @@ // Vector Bitwise Operations. -def vnot8 : PatFrag<(ops node:$in), - (xor node:$in, (bitconvert (v8i8 immAllOnesV)))>; -def vnot16 : PatFrag<(ops node:$in), - (xor node:$in, (bitconvert (v16i8 immAllOnesV)))>; +def vnotd : PatFrag<(ops node:$in), + (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>; +def vnotq : PatFrag<(ops node:$in), + (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>; // VAND : Vector Bitwise AND @@ -2347,36 +2364,36 @@ (ins DPR:$src1, DPR:$src2), N3RegFrm, IIC_VBINiD, "vbic", "$dst, $src1, $src2", "", [(set DPR:$dst, (v2i32 (and DPR:$src1, - (vnot8 DPR:$src2))))]>; + (vnotd DPR:$src2))))]>; def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), N3RegFrm, IIC_VBINiQ, "vbic", "$dst, $src1, $src2", "", [(set QPR:$dst, (v4i32 (and QPR:$src1, - (vnot16 QPR:$src2))))]>; + (vnotq QPR:$src2))))]>; // VORN : Vector Bitwise OR NOT def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, IIC_VBINiD, "vorn", "$dst, $src1, $src2", "", [(set DPR:$dst, (v2i32 (or DPR:$src1, - (vnot8 DPR:$src2))))]>; + (vnotd DPR:$src2))))]>; def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), N3RegFrm, IIC_VBINiQ, "vorn", "$dst, $src1, $src2", "", [(set QPR:$dst, (v4i32 (or QPR:$src1, - (vnot16 QPR:$src2))))]>; + (vnotq QPR:$src2))))]>; // VMVN : Vector Bitwise NOT def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0, (outs DPR:$dst), (ins DPR:$src), IIC_VSUBiD, "vmvn", "$dst, $src", "", - [(set DPR:$dst, (v2i32 (vnot8 DPR:$src)))]>; + [(set DPR:$dst, (v2i32 (vnotd DPR:$src)))]>; def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0, (outs QPR:$dst), (ins QPR:$src), IIC_VSUBiD, "vmvn", "$dst, $src", "", - [(set QPR:$dst, (v4i32 (vnot16 QPR:$src)))]>; -def : Pat<(v2i32 (vnot8 DPR:$src)), (VMVNd DPR:$src)>; -def : Pat<(v4i32 (vnot16 QPR:$src)), (VMVNq QPR:$src)>; + [(set QPR:$dst, (v4i32 (vnotq QPR:$src)))]>; +def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>; +def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>; // VBSL : Vector Bitwise Select def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst), @@ -2385,14 +2402,14 @@ "vbsl", "$dst, $src2, $src3", "$src1 = $dst", [(set DPR:$dst, (v2i32 (or (and DPR:$src2, DPR:$src1), - (and DPR:$src3, (vnot8 DPR:$src1)))))]>; + (and DPR:$src3, (vnotd DPR:$src1)))))]>; def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), N3RegFrm, IIC_VCNTiQ, "vbsl", "$dst, $src2, $src3", "$src1 = $dst", [(set QPR:$dst, (v4i32 (or (and QPR:$src2, QPR:$src1), - (and QPR:$src3, (vnot16 QPR:$src1)))))]>; + (and QPR:$src3, (vnotq QPR:$src1)))))]>; // VBIF : Vector Bitwise Insert if False // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst", @@ -2726,20 +2743,19 @@ // Vector Negate. -def vneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>; -def vneg8 : PatFrag<(ops node:$in), - (sub (bitconvert (v8i8 immAllZerosV)), node:$in)>; -def vneg16 : PatFrag<(ops node:$in), - (sub (bitconvert (v16i8 immAllZerosV)), node:$in)>; +def vnegd : PatFrag<(ops node:$in), + (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>; +def vnegq : PatFrag<(ops node:$in), + (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>; class VNEGD size, string OpcodeStr, string Dt, ValueType Ty> : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src), IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "", - [(set DPR:$dst, (Ty (vneg8 DPR:$src)))]>; + [(set DPR:$dst, (Ty (vnegd DPR:$src)))]>; class VNEGQ size, string OpcodeStr, string Dt, ValueType Ty> : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src), IIC_VSHLiD, OpcodeStr, Dt, "$dst, $src", "", - [(set QPR:$dst, (Ty (vneg16 QPR:$src)))]>; + [(set QPR:$dst, (Ty (vnegq QPR:$src)))]>; // VNEG : Vector Negate (integer) def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>; @@ -2759,12 +2775,12 @@ "vneg", "f32", "$dst, $src", "", [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>; -def : Pat<(v8i8 (vneg8 DPR:$src)), (VNEGs8d DPR:$src)>; -def : Pat<(v4i16 (vneg8 DPR:$src)), (VNEGs16d DPR:$src)>; -def : Pat<(v2i32 (vneg8 DPR:$src)), (VNEGs32d DPR:$src)>; -def : Pat<(v16i8 (vneg16 QPR:$src)), (VNEGs8q QPR:$src)>; -def : Pat<(v8i16 (vneg16 QPR:$src)), (VNEGs16q QPR:$src)>; -def : Pat<(v4i32 (vneg16 QPR:$src)), (VNEGs32q QPR:$src)>; +def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>; +def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>; +def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>; +def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>; +def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>; +def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>; // VQNEG : Vector Saturating Negate defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0, @@ -2818,74 +2834,42 @@ // VMOV : Vector Move (Immediate) -// VMOV_get_imm8 xform function: convert build_vector to VMOV.i8 imm. -def VMOV_get_imm8 : SDNodeXForm; -def vmovImm8 : PatLeaf<(build_vector), [{ - return ARM::getNEONModImm(N, 1, true, *CurDAG).getNode() != 0; -}], VMOV_get_imm8>; - -// VMOV_get_imm16 xform function: convert build_vector to VMOV.i16 imm. -def VMOV_get_imm16 : SDNodeXForm; -def vmovImm16 : PatLeaf<(build_vector), [{ - return ARM::getNEONModImm(N, 2, true, *CurDAG).getNode() != 0; -}], VMOV_get_imm16>; - -// VMOV_get_imm32 xform function: convert build_vector to VMOV.i32 imm. -def VMOV_get_imm32 : SDNodeXForm; -def vmovImm32 : PatLeaf<(build_vector), [{ - return ARM::getNEONModImm(N, 4, true, *CurDAG).getNode() != 0; -}], VMOV_get_imm32>; - -// VMOV_get_imm64 xform function: convert build_vector to VMOV.i64 imm. -def VMOV_get_imm64 : SDNodeXForm; -def vmovImm64 : PatLeaf<(build_vector), [{ - return ARM::getNEONModImm(N, 8, true, *CurDAG).getNode() != 0; -}], VMOV_get_imm64>; - let isReMaterializable = 1 in { def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst), (ins nModImm:$SIMM), IIC_VMOVImm, "vmov", "i8", "$dst, $SIMM", "", - [(set DPR:$dst, (v8i8 vmovImm8:$SIMM))]>; + [(set DPR:$dst, (v8i8 (NEONvmovImm timm:$SIMM)))]>; def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst), (ins nModImm:$SIMM), IIC_VMOVImm, "vmov", "i8", "$dst, $SIMM", "", - [(set QPR:$dst, (v16i8 vmovImm8:$SIMM))]>; + [(set QPR:$dst, (v16i8 (NEONvmovImm timm:$SIMM)))]>; def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$dst), (ins nModImm:$SIMM), IIC_VMOVImm, "vmov", "i16", "$dst, $SIMM", "", - [(set DPR:$dst, (v4i16 vmovImm16:$SIMM))]>; + [(set DPR:$dst, (v4i16 (NEONvmovImm timm:$SIMM)))]>; def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$dst), (ins nModImm:$SIMM), IIC_VMOVImm, "vmov", "i16", "$dst, $SIMM", "", - [(set QPR:$dst, (v8i16 vmovImm16:$SIMM))]>; + [(set QPR:$dst, (v8i16 (NEONvmovImm timm:$SIMM)))]>; def VMOVv2i32 : N1ModImm<1, 0b000, {0,?,?,0}, 0, 0, 0, 1, (outs DPR:$dst), (ins nModImm:$SIMM), IIC_VMOVImm, "vmov", "i32", "$dst, $SIMM", "", - [(set DPR:$dst, (v2i32 vmovImm32:$SIMM))]>; + [(set DPR:$dst, (v2i32 (NEONvmovImm timm:$SIMM)))]>; def VMOVv4i32 : N1ModImm<1, 0b000, {0,?,?,0}, 0, 1, 0, 1, (outs QPR:$dst), (ins nModImm:$SIMM), IIC_VMOVImm, "vmov", "i32", "$dst, $SIMM", "", - [(set QPR:$dst, (v4i32 vmovImm32:$SIMM))]>; + [(set QPR:$dst, (v4i32 (NEONvmovImm timm:$SIMM)))]>; def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst), (ins nModImm:$SIMM), IIC_VMOVImm, "vmov", "i64", "$dst, $SIMM", "", - [(set DPR:$dst, (v1i64 vmovImm64:$SIMM))]>; + [(set DPR:$dst, (v1i64 (NEONvmovImm timm:$SIMM)))]>; def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst), (ins nModImm:$SIMM), IIC_VMOVImm, "vmov", "i64", "$dst, $SIMM", "", - [(set QPR:$dst, (v2i64 vmovImm64:$SIMM))]>; + [(set QPR:$dst, (v2i64 (NEONvmovImm timm:$SIMM)))]>; } // isReMaterializable // VMOV : Vector Get Lane (move scalar to ARM core register) Modified: llvm/trunk/test/CodeGen/ARM/reg_sequence.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/reg_sequence.ll?rev=108275&r1=108274&r2=108275&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/reg_sequence.ll (original) +++ llvm/trunk/test/CodeGen/ARM/reg_sequence.ll Tue Jul 13 16:16:48 2010 @@ -239,7 +239,7 @@ ; CHECK: t9: ; CHECK: vldr.64 ; CHECK-NOT: vmov d{{.*}}, d0 -; CHECK: vmov.i8 d1 +; CHECK: vmov.i32 d1 ; CHECK-NEXT: vstmia r0, {d0, d1} ; CHECK-NEXT: vstmia r0, {d0, d1} %3 = bitcast double 0.000000e+00 to <2 x float> ; <<2 x float>> [#uses=2] From stoklund at 2pi.dk Tue Jul 13 16:19:05 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 13 Jul 2010 21:19:05 -0000 Subject: [llvm-commits] [llvm] r108277 - /llvm/trunk/lib/CodeGen/LiveInterval.cpp Message-ID: <20100713211905.944862A6C12C@llvm.org> Author: stoklund Date: Tue Jul 13 16:19:05 2010 New Revision: 108277 URL: http://llvm.org/viewvc/llvm-project?rev=108277&view=rev Log: Print VNInfo flags. Modified: llvm/trunk/lib/CodeGen/LiveInterval.cpp Modified: llvm/trunk/lib/CodeGen/LiveInterval.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveInterval.cpp?rev=108277&r1=108276&r2=108277&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveInterval.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveInterval.cpp Tue Jul 13 16:19:05 2010 @@ -861,6 +861,10 @@ OS << "?"; else OS << vni->def; + if (vni->hasPHIKill()) + OS << "-phikill"; + if (vni->hasRedefByEC()) + OS << "-ec"; } } } From stoklund at 2pi.dk Tue Jul 13 16:19:08 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 13 Jul 2010 21:19:08 -0000 Subject: [llvm-commits] [llvm] r108278 - /llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h Message-ID: <20100713211908.E23FE2A6C12E@llvm.org> Author: stoklund Date: Tue Jul 13 16:19:08 2010 New Revision: 108278 URL: http://llvm.org/viewvc/llvm-project?rev=108278&view=rev Log: Remove vestigial decl. Modified: llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h Modified: llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h?rev=108278&r1=108277&r2=108278&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h (original) +++ llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h Tue Jul 13 16:19:08 2010 @@ -272,10 +272,6 @@ unsigned getNumConflictsWithPhysReg(const LiveInterval &li, unsigned PhysReg) const; - /// processImplicitDefs - Process IMPLICIT_DEF instructions. Add isUndef - /// marker to implicit_def defs and their uses. - void processImplicitDefs(); - /// intervalIsInOneMBB - Returns true if the specified interval is entirely /// within a single basic block. bool intervalIsInOneMBB(const LiveInterval &li) const; From bigcheesegs at gmail.com Tue Jul 13 16:47:54 2010 From: bigcheesegs at gmail.com (Michael Spencer) Date: Tue, 13 Jul 2010 17:47:54 -0400 Subject: [llvm-commits] [patch] Merged lib/Target/X86/X86COFF.h into include/llvm/Support/COFF.h Message-ID: Merged lib/Target/X86/X86COFF.h into include/llvm/Support/COFF.h - Michael Spencer -------------- next part -------------- A non-text attachment was scrubbed... Name: merge-x86coff-coff.patch Type: application/octet-stream Size: 11896 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100713/a130c9ae/attachment.obj From bruno.cardoso at gmail.com Tue Jul 13 17:06:38 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 13 Jul 2010 22:06:38 -0000 Subject: [llvm-commits] [llvm] r108286 - in /llvm/trunk: lib/Target/X86/X86InstrSSE.td test/MC/AsmParser/X86/x86_32-encoding.s test/MC/AsmParser/X86/x86_64-encoding.s Message-ID: <20100713220638.8C19A2A6C12C@llvm.org> Author: bruno Date: Tue Jul 13 17:06:38 2010 New Revision: 108286 URL: http://llvm.org/viewvc/llvm-project?rev=108286&view=rev Log: Add AVX 256-bit compare instructions and a bunch of testcases Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/test/MC/AsmParser/X86/x86_32-encoding.s llvm/trunk/test/MC/AsmParser/X86/x86_64-encoding.s Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=108286&r1=108285&r2=108286&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Jul 13 17:06:38 2010 @@ -1193,6 +1193,16 @@ "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}", "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}", SSEPackedDouble>, OpSize, VEX_4V; + let Pattern = [] in { + defm VCMPPSY : sse12_cmp_packed, VEX_4V; + defm VCMPPDY : sse12_cmp_packed, OpSize, VEX_4V; + } } let Constraints = "$src1 = $dst" in { defm CMPPS : sse12_cmp_packed Author: wdietz2 Date: Tue Jul 13 17:45:25 2010 New Revision: 108291 URL: http://llvm.org/viewvc/llvm-project?rev=108291&view=rev Log: While skipping calls within the SCC, assume functions that are declarations aren't part of this SCC. Allows DSA to execute on programs with function pointers to decls. Fixes FPDeclaration regression test. Modified: poolalloc/trunk/lib/DSA/TopDownClosure.cpp Modified: poolalloc/trunk/lib/DSA/TopDownClosure.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/TopDownClosure.cpp?rev=108291&r1=108290&r2=108291&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/TopDownClosure.cpp (original) +++ poolalloc/trunk/lib/DSA/TopDownClosure.cpp Tue Jul 13 17:45:25 2010 @@ -304,7 +304,8 @@ IPE = callgraph.callee_end(CI->getCallSite()); // Skip over all calls to this graph (SCC calls). - while (IPI != IPE && getDSGraph(**IPI) == DSG) + // Note that Functions that are just declarations are their own SCC + while (IPI != IPE && !(*IPI)->isDeclaration() && getDSGraph(**IPI) == DSG) ++IPI; // All SCC calls? @@ -314,7 +315,7 @@ ++IPI; // Skip over more SCC calls. - while (IPI != IPE && getDSGraph(**IPI) == DSG) + while (IPI != IPE && !(*IPI)->isDeclaration() && getDSGraph(**IPI) == DSG) ++IPI; // If there is exactly one callee from this call site, remember the edge in From gohman at apple.com Tue Jul 13 20:07:45 2010 From: gohman at apple.com (Dan Gohman) Date: Wed, 14 Jul 2010 01:07:45 -0000 Subject: [llvm-commits] [llvm] r108302 - in /llvm/trunk: include/llvm/CodeGen/FastISel.h lib/CodeGen/SelectionDAG/FastISel.cpp lib/Target/X86/X86FastISel.cpp Message-ID: <20100714010745.25B322A6C12C@llvm.org> Author: djg Date: Tue Jul 13 20:07:44 2010 New Revision: 108302 URL: http://llvm.org/viewvc/llvm-project?rev=108302&view=rev Log: Don't propagate debug locations to instructions for materializing constants, since they may not be emited near the other instructions which get the same line, and this confuses debug info. Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp llvm/trunk/lib/Target/X86/X86FastISel.cpp Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FastISel.h?rev=108302&r1=108301&r2=108302&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/FastISel.h (original) +++ llvm/trunk/include/llvm/CodeGen/FastISel.h Tue Jul 13 20:07:44 2010 @@ -106,12 +106,17 @@ /// into the current block. void recomputeInsertPt(); + struct SavePoint { + MachineBasicBlock::iterator InsertPt; + DebugLoc DL; + }; + /// enterLocalValueArea - Prepare InsertPt to begin inserting instructions /// into the local value area and return the old insert position. - MachineBasicBlock::iterator enterLocalValueArea(); + SavePoint enterLocalValueArea(); - /// leaveLocalValueArea - Reset InsertPt to the given old insert position - void leaveLocalValueArea(MachineBasicBlock::iterator OldInsertPt); + /// leaveLocalValueArea - Reset InsertPt to the given old insert position. + void leaveLocalValueArea(SavePoint Old); virtual ~FastISel(); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=108302&r1=108301&r2=108302&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Tue Jul 13 20:07:44 2010 @@ -135,7 +135,7 @@ !FuncInfo.StaticAllocaMap.count(cast(V)))) return FuncInfo.InitializeRegForValue(V); - MachineBasicBlock::iterator SaveInsertPt = enterLocalValueArea(); + SavePoint SaveInsertPt = enterLocalValueArea(); // Materialize the value in a register. Emit any instructions in the // local value area. @@ -286,18 +286,21 @@ ++FuncInfo.InsertPt; } -MachineBasicBlock::iterator FastISel::enterLocalValueArea() { +FastISel::SavePoint FastISel::enterLocalValueArea() { MachineBasicBlock::iterator OldInsertPt = FuncInfo.InsertPt; recomputeInsertPt(); - return OldInsertPt; + DL = DebugLoc(); + SavePoint SP = { OldInsertPt, DL }; + return SP; } -void FastISel::leaveLocalValueArea(MachineBasicBlock::iterator OldInsertPt) { +void FastISel::leaveLocalValueArea(SavePoint OldInsertPt) { if (FuncInfo.InsertPt != FuncInfo.MBB->begin()) LastLocalValue = llvm::prior(FuncInfo.InsertPt); // Restore the previous insert position. - FuncInfo.InsertPt = OldInsertPt; + FuncInfo.InsertPt = OldInsertPt.InsertPt; + DL = OldInsertPt.DL; } /// SelectBinaryOp - Select and emit code for a binary operator instruction, Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=108302&r1=108301&r2=108302&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Tue Jul 13 20:07:44 2010 @@ -540,7 +540,7 @@ StubAM.GVOpFlags = GVFlags; // Prepare for inserting code in the local-value area. - MachineBasicBlock::iterator SaveInsertPt = enterLocalValueArea(); + SavePoint SaveInsertPt = enterLocalValueArea(); if (TLI.getPointerTy() == MVT::i64) { Opc = X86::MOV64rm; From bob.wilson at apple.com Tue Jul 13 20:22:12 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Wed, 14 Jul 2010 01:22:12 -0000 Subject: [llvm-commits] [llvm] r108303 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/ARM/vdup.ll Message-ID: <20100714012212.392DD2A6C12C@llvm.org> Author: bwilson Date: Tue Jul 13 20:22:12 2010 New Revision: 108303 URL: http://llvm.org/viewvc/llvm-project?rev=108303&view=rev Log: Add an ARM-specific DAG combining to avoid redundant VDUPLANE nodes. Radar 7373643. Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/test/CodeGen/ARM/vdup.ll Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=108303&r1=108302&r2=108303&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Jul 13 20:22:12 2010 @@ -4228,6 +4228,34 @@ return SDValue(); } +/// PerformVDUPLANECombine - Target-specific dag combine xforms for +/// ARMISD::VDUPLANE. +static SDValue PerformVDUPLANECombine(SDNode *N, + TargetLowering::DAGCombinerInfo &DCI) { + // If the source is already a VMOVIMM splat, the VDUPLANE is redundant. + SDValue Op = N->getOperand(0); + EVT VT = N->getValueType(0); + + // Ignore bit_converts. + while (Op.getOpcode() == ISD::BIT_CONVERT) + Op = Op.getOperand(0); + if (Op.getOpcode() != ARMISD::VMOVIMM) + return SDValue(); + + // Make sure the VMOV element size is not bigger than the VDUPLANE elements. + unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits(); + // The canonical VMOV for a zero vector uses a 32-bit element size. + unsigned Imm = cast(Op.getOperand(0))->getZExtValue(); + unsigned EltBits; + if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0) + EltSize = 8; + if (EltSize > VT.getVectorElementType().getSizeInBits()) + return SDValue(); + + SDValue Res = DCI.DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op); + return DCI.CombineTo(N, Res, false); +} + /// getVShiftImm - Check if this is a valid build_vector for the immediate /// operand of a vector shift operation, where all the elements of the /// build_vector must have the same constant integer value. @@ -4606,6 +4634,7 @@ case ISD::SUB: return PerformSUBCombine(N, DCI); case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget); case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI); + case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI); case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG); case ISD::SHL: case ISD::SRA: Modified: llvm/trunk/test/CodeGen/ARM/vdup.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vdup.ll?rev=108303&r1=108302&r2=108303&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vdup.ll (original) +++ llvm/trunk/test/CodeGen/ARM/vdup.ll Tue Jul 13 20:22:12 2010 @@ -267,3 +267,15 @@ %0 = shufflevector <2 x double> %arg0_int64x1_t, <2 x double> undef, <2 x i32> ret <2 x double> %0 } + +; Radar 7373643 +;CHECK: redundantVdup: +;CHECK: vmov.i8 +;CHECK-NOT: vdup.8 +;CHECK: vstr.64 +define void @redundantVdup(<8 x i8>* %ptr) nounwind { + %1 = insertelement <8 x i8> undef, i8 -128, i32 0 + %2 = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> zeroinitializer + store <8 x i8> %2, <8 x i8>* %ptr, align 8 + ret void +} From evan.cheng at apple.com Tue Jul 13 20:22:19 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 14 Jul 2010 01:22:19 -0000 Subject: [llvm-commits] [llvm] r108304 - in /llvm/trunk: include/llvm/CodeGen/ProcessImplicitDefs.h lib/CodeGen/MachineLICM.cpp lib/CodeGen/ProcessImplicitDefs.cpp test/CodeGen/X86/2009-02-26-MachineLICMBug.ll Message-ID: <20100714012219.E0A902A6C12C@llvm.org> Author: evancheng Date: Tue Jul 13 20:22:19 2010 New Revision: 108304 URL: http://llvm.org/viewvc/llvm-project?rev=108304&view=rev Log: Teach ProcessImplicitDefs to transform more COPY instructions into IMPLICIT_DEF (and subsequently eliminate them). This allows machine LICM to hoist IMPLICIT_DEF's. PR7620. Modified: llvm/trunk/include/llvm/CodeGen/ProcessImplicitDefs.h llvm/trunk/lib/CodeGen/MachineLICM.cpp llvm/trunk/lib/CodeGen/ProcessImplicitDefs.cpp llvm/trunk/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll Modified: llvm/trunk/include/llvm/CodeGen/ProcessImplicitDefs.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ProcessImplicitDefs.h?rev=108304&r1=108303&r2=108304&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/ProcessImplicitDefs.h (original) +++ llvm/trunk/include/llvm/CodeGen/ProcessImplicitDefs.h Tue Jul 13 20:22:19 2010 @@ -12,6 +12,7 @@ #define LLVM_CODEGEN_PROCESSIMPLICITDEFS_H #include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/ADT/SmallSet.h" namespace llvm { @@ -24,7 +25,8 @@ private: bool CanTurnIntoImplicitDef(MachineInstr *MI, unsigned Reg, - unsigned OpIdx, const TargetInstrInfo *tii_); + unsigned OpIdx, const TargetInstrInfo *tii_, + SmallSet &ImpDefRegs); public: static char ID; Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineLICM.cpp?rev=108304&r1=108303&r2=108304&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineLICM.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineLICM.cpp Tue Jul 13 20:22:19 2010 @@ -497,11 +497,6 @@ /// candidate for LICM. e.g. If the instruction is a call, then it's obviously /// not safe to hoist it. bool MachineLICM::IsLICMCandidate(MachineInstr &I) { - // It is not profitable to hoist implicitdefs. FIXME: Why not? what if they - // are an argument to some other otherwise-hoistable instruction? - if (I.isImplicitDef()) - return false; - // Check if it's safe to move the instruction. bool DontMoveAcrossStore = true; if (!I.isSafeToMove(TII, AA, DontMoveAcrossStore)) @@ -717,7 +712,9 @@ bool MachineLICM::EliminateCSE(MachineInstr *MI, DenseMap >::iterator &CI) { - if (CI == CSEMap.end()) + // Do not CSE implicit_def so ProcessImplicitDefs can properly propagate + // the undef property onto uses. + if (CI == CSEMap.end() || MI->isImplicitDef()) return false; if (const MachineInstr *Dup = LookForDuplicate(MI, CI->second)) { Modified: llvm/trunk/lib/CodeGen/ProcessImplicitDefs.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ProcessImplicitDefs.cpp?rev=108304&r1=108303&r2=108304&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ProcessImplicitDefs.cpp (original) +++ llvm/trunk/lib/CodeGen/ProcessImplicitDefs.cpp Tue Jul 13 20:22:19 2010 @@ -41,21 +41,51 @@ MachineFunctionPass::getAnalysisUsage(AU); } -bool ProcessImplicitDefs::CanTurnIntoImplicitDef(MachineInstr *MI, - unsigned Reg, unsigned OpIdx, - const TargetInstrInfo *tii_) { +bool +ProcessImplicitDefs::CanTurnIntoImplicitDef(MachineInstr *MI, + unsigned Reg, unsigned OpIdx, + const TargetInstrInfo *tii_, + SmallSet &ImpDefRegs) { unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; if (tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg) && - Reg == SrcReg && DstSubReg == 0) + Reg == SrcReg && + (DstSubReg == 0 || ImpDefRegs.count(DstReg))) return true; switch(OpIdx) { - case 1: return MI->isCopy() && MI->getOperand(0).getSubReg() == 0; - case 2: return MI->isSubregToReg() && MI->getOperand(0).getSubReg() == 0; - default: return false; + case 1: + return MI->isCopy() && (MI->getOperand(0).getSubReg() == 0 || + ImpDefRegs.count(MI->getOperand(0).getReg())); + case 2: + return MI->isSubregToReg() && (MI->getOperand(0).getSubReg() == 0 || + ImpDefRegs.count(MI->getOperand(0).getReg())); + default: return false; } } +static bool isUndefCopy(MachineInstr *MI, unsigned Reg, + const TargetInstrInfo *tii_, + SmallSet &ImpDefRegs) { + if (MI->isCopy()) { + MachineOperand &MO0 = MI->getOperand(0); + MachineOperand &MO1 = MI->getOperand(1); + if (MO1.getReg() != Reg) + return false; + if (!MO0.getSubReg() || ImpDefRegs.count(MO0.getReg())) + return true; + return false; + } + + unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; + if (tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg)) { + if (Reg != SrcReg) + return false; + if (DstSubReg == 0 || ImpDefRegs.count(DstReg)) + return true; + } + return false; +} + /// processImplicitDefs - Process IMPLICIT_DEF instructions and make sure /// there is one implicit_def for each use. Add isUndef marker to /// implicit_def defs and their uses. @@ -104,7 +134,7 @@ // Eliminate %reg1032:sub = COPY undef. if (MI->isCopy() && MI->getOperand(0).getSubReg()) { MachineOperand &MO = MI->getOperand(1); - if (ImpDefRegs.count(MO.getReg())) { + if (MO.isUndef() || ImpDefRegs.count(MO.getReg())) { if (MO.isKill()) { LiveVariables::VarInfo& vi = lv_->getVarInfo(MO.getReg()); vi.removeKill(MI); @@ -126,7 +156,7 @@ if (!ImpDefRegs.count(Reg)) continue; // Use is a copy, just turn it into an implicit_def. - if (CanTurnIntoImplicitDef(MI, Reg, i, tii_)) { + if (CanTurnIntoImplicitDef(MI, Reg, i, tii_, ImpDefRegs)) { bool isKill = MO.isKill(); MI->setDesc(tii_->get(TargetOpcode::IMPLICIT_DEF)); for (int j = MI->getNumOperands() - 1, ee = 0; j > ee; --j) @@ -223,11 +253,7 @@ MachineInstr *RMI = RUses[i]; // Turn a copy use into an implicit_def. - unsigned SrcReg, DstReg, SrcSubReg, DstSubReg; - if ((RMI->isCopy() && RMI->getOperand(1).getReg() == Reg && - RMI->getOperand(0).getSubReg() == 0) || - (tii_->isMoveInstr(*RMI, SrcReg, DstReg, SrcSubReg, DstSubReg) && - Reg == SrcReg && DstSubReg == 0)) { + if (isUndefCopy(RMI, Reg, tii_, ImpDefRegs)) { RMI->setDesc(tii_->get(TargetOpcode::IMPLICIT_DEF)); bool isKill = false; Modified: llvm/trunk/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll?rev=108304&r1=108303&r2=108304&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll (original) +++ llvm/trunk/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll Tue Jul 13 20:22:19 2010 @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 -mattr=+sse3 -stats |& grep {2 machine-licm} +; RUN: llc < %s -march=x86-64 -mattr=+sse3 -stats |& grep {7 machine-licm} ; RUN: llc < %s -march=x86-64 -mattr=+sse3 | FileCheck %s ; rdar://6627786 ; rdar://7792037 From daniel at zuster.org Tue Jul 13 20:39:46 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 14 Jul 2010 01:39:46 -0000 Subject: [llvm-commits] [zorg] r108305 - in /zorg/trunk/lnt/lnt: db/perfdbsummary.py viewer/PerfDB.py Message-ID: <20100714013946.71C482A6C12C@llvm.org> Author: ddunbar Date: Tue Jul 13 20:39:46 2010 New Revision: 108305 URL: http://llvm.org/viewvc/llvm-project?rev=108305&view=rev Log: LNT: Add Test.get_parameter_set helper method. Modified: zorg/trunk/lnt/lnt/db/perfdbsummary.py zorg/trunk/lnt/lnt/viewer/PerfDB.py Modified: zorg/trunk/lnt/lnt/db/perfdbsummary.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/db/perfdbsummary.py?rev=108305&r1=108304&r2=108305&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/db/perfdbsummary.py (original) +++ zorg/trunk/lnt/lnt/db/perfdbsummary.py Tue Jul 13 20:39:46 2010 @@ -55,9 +55,7 @@ for t in tests: name = t.name.split('.', 1)[1] - items = [(k,v.value) for k,v in t.info.items()] - items.sort() - key = tuple(items) + key = t.get_parameter_set() parameter_sets.add(key) test_id_map[(name, key)] = t.id Modified: zorg/trunk/lnt/lnt/viewer/PerfDB.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/viewer/PerfDB.py?rev=108305&r1=108304&r2=108305&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/viewer/PerfDB.py (original) +++ zorg/trunk/lnt/lnt/viewer/PerfDB.py Tue Jul 13 20:39:46 2010 @@ -118,6 +118,11 @@ return '%s%r' % (self.__class__.__name__, (self.name,)) + def get_parameter_set(self): + items = [(k,v.value) for k,v in self.info.items()] + items.sort() + return tuple(items) + class TestInfo(Base): __tablename__ = 'TestInfo' From daniel at zuster.org Tue Jul 13 20:39:52 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 14 Jul 2010 01:39:52 -0000 Subject: [llvm-commits] [zorg] r108306 - in /zorg/trunk/lnt/lnt/viewer: GraphUtil.py simple.ptl Message-ID: <20100714013953.0789B2A6C12D@llvm.org> Author: ddunbar Date: Tue Jul 13 20:39:52 2010 New Revision: 108306 URL: http://llvm.org/viewvc/llvm-project?rev=108306&view=rev Log: LNT/simple: Pull some graphing code out into a helper module. Added: zorg/trunk/lnt/lnt/viewer/GraphUtil.py Modified: zorg/trunk/lnt/lnt/viewer/simple.ptl Added: zorg/trunk/lnt/lnt/viewer/GraphUtil.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/viewer/GraphUtil.py?rev=108306&view=auto ============================================================================== --- zorg/trunk/lnt/lnt/viewer/GraphUtil.py (added) +++ zorg/trunk/lnt/lnt/viewer/GraphUtil.py Tue Jul 13 20:39:52 2010 @@ -0,0 +1,92 @@ +""" +Helper functions for graphing test results. +""" + +import Util + +from lnt.util import stats + +from PerfDB import Machine, Run, RunInfo, Sample, Test + +def get_test_plots(db, machine, test_ids, run_summary, ts_summary, + show_mad_error = False, show_points = False, + show_all_points = False): + # Load all the samples for these tests and this machine. + q = db.session.query(Sample.run_id,Sample.test_id, + Sample.value).join(Run) + q = q.filter(Run.machine_id == machine.id) + q = q.filter(Sample.test_id.in_(test_ids)) + samples = list(q) + + # Aggregate by test id and then run key. + # + # FIXME: Pretty expensive. + samples_by_test_id = {} + for run_id,test_id,value in samples: + d = samples_by_test_id.get(test_id) + if d is None: + d = samples_by_test_id[test_id] = Util.multidict() + run_key = run_summary.get_run_order(run_id) + if run_key is None: + continue + + # FIXME: What to do on failure? + run_key = int(run_key) + d[run_key] = value + + # Build the graph data + pset_id_map = dict([(pset,i) + for i,pset in enumerate(ts_summary.parameter_sets)]) + num_plots = len(test_ids) + for index,test_id in enumerate(test_ids): + test = db.getTest(test_id) + pset = test.get_parameter_set() + name = test.name + + # Get the plot for this test. + # + # FIXME: Support order by something other than time. + errorbar_data = [] + points_data = [] + data = [] + points = [] + for x,values in samples_by_test_id.get(test_id,{}).items(): + min_value = min(values) + data.append((x, min_value)) + if show_points: + if show_all_points: + for v in values: + points_data.append((x, v)) + else: + points_data.append((x, min_value)) + if show_mad_error: + med = stats.median(values) + mad = stats.median_absolute_deviation(values, med) + errorbar_data.append((x, med - mad, med + mad)) + points.append((x, min_value, mad, med)) + data.sort() + points.sort() + + plot_js = "" + + col = list(Util.makeDarkColor(float(index) / num_plots)) + pts = ','.join(['[%.4f,%.4f]' % (t,v) + for t,v in data]) + style = "new Graph2D_LinePlotStyle(1, %r)" % col + plot_js += " graph.addPlot([%s], %s);\n" % (pts,style) + + if points_data: + pts_col = (0,0,0) + pts = ','.join(['[%.4f,%.4f]' % (t,v) + for t,v in points_data]) + style = "new Graph2D_PointPlotStyle(1, %r)" % (pts_col,) + plot_js += " graph.addPlot([%s], %s);\n" % (pts,style) + + if errorbar_data: + bar_col = [c*.7 for c in col] + pts = ','.join(['[%.4f,%.4f,%.4f]' % (x,y_min,y_max) + for x,y_min,y_max in errorbar_data]) + style = "new Graph2D_ErrorBarPlotStyle(1, %r)" % (bar_col,) + plot_js += " graph.addPlot([%s], %s);\n" % (pts,style) + + yield (test_id, plot_js, col, data, points) Modified: zorg/trunk/lnt/lnt/viewer/simple.ptl URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/viewer/simple.ptl?rev=108306&r1=108305&r2=108306&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/viewer/simple.ptl (original) +++ zorg/trunk/lnt/lnt/viewer/simple.ptl Tue Jul 13 20:39:52 2010 @@ -14,6 +14,7 @@ from lnt.db import runinfo from lnt.db import perfdbsummary from lnt.util import stats +from lnt.viewer import GraphUtil import Util from Util import safediv @@ -233,93 +234,26 @@ for name in graph_tests for pset in graph_psets] - # Load all the samples for those tests and this machine. - q = db.session.query(Sample.run_id,Sample.test_id, - Sample.value).join(Run) - q = q.filter(Run.machine_id == machine.id) - q = q.filter(Sample.test_id.in_(test_ids)) - samples = list(q) - - # Aggregate by test id and then run key. - # - # FIXME: Pretty expensive. - samples_by_test_id = {} - for run_id,test_id,value in samples: - d = samples_by_test_id.get(test_id) - if d is None: - d = samples_by_test_id[test_id] = Util.multidict() - run_key = run_summary.get_run_order(run_id) - if run_key is None: - continue - - # FIXME: What to do on failure? - run_key = int(run_key) - d[run_key] = value - # Build the graph data pset_id_map = dict([(pset,i) for i,pset in enumerate(ts_summary.parameter_sets)]) legend = [] + num_points = 0 plot_points = [] plots = "" - num_plots = len(graph_tests) * len(graph_psets) - num_points = 0 - index = 0 - show_mad_error = True - show_points = True - show_all_points = False - for name in graph_tests: - for pset in graph_psets: - test_id = ts_summary.test_id_map[(name,pset)] - - # Get the plot for this test. - # - # FIXME: Support order by something other than time. - errorbar_data = [] - points_data = [] - data = [] - points = [] - for x,values in samples_by_test_id.get(test_id,{}).items(): - min_value = min(values) - data.append((x, min_value)) - if show_points: - if show_all_points: - for v in values: - points_data.append((x, v)) - else: - points_data.append((x, min_value)) - if show_mad_error: - med = stats.median(values) - mad = stats.median_absolute_deviation(values, med) - errorbar_data.append((x, med - mad, med + mad)) - points.append((x, min_value, mad, med)) - data.sort() - num_points += len(data) - - col = list(Util.makeDarkColor(float(index) / num_plots)) - pts = ','.join(['[%.4f,%.4f]' % (t,v) - for t,v in data]) - style = "new Graph2D_LinePlotStyle(1, %r)" % col - plots += " graph.addPlot([%s], %s);\n" % (pts,style) - - if points_data: - pts_col = (0,0,0) - pts = ','.join(['[%.4f,%.4f]' % (t,v) - for t,v in points_data]) - style = "new Graph2D_PointPlotStyle(1, %r)" % (pts_col,) - plots += " graph.addPlot([%s], %s);\n" % (pts,style) - - if errorbar_data: - bar_col = [c*.7 for c in col] - pts = ','.join(['[%.4f,%.4f,%.4f]' % (x,y_min,y_max) - for x,y_min,y_max in errorbar_data]) - style = "new Graph2D_ErrorBarPlotStyle(1, %r)" % (bar_col,) - plots += " graph.addPlot([%s], %s);\n" % (pts,style) - - legend.append(("%s : P%d" % (name, pset_id_map[pset]), col)) - points.sort() - plot_points.append(points) - index += 1 + plots_iter = GraphUtil.get_test_plots(db, machine, test_ids, + run_summary, ts_summary, + show_mad_error = True, + show_points = True) + for test_id, plot_js, col, points, ext_points in plots_iter: + test = db.getTest(test_id) + name = test.name + pset = test.get_parameter_set() + + num_points += len(points) + legend.append(("%s : P%d" % (name, pset_id_map[pset]), col)) + plots += plot_js + plot_points.append(ext_points) def graph_body [html] (): """ @@ -351,7 +285,7 @@

Plots: %d
Num Points: %d
- """ % (num_plots, num_points) + """ % (len(test_ids), num_points) """

Deltas

""" From daniel at zuster.org Tue Jul 13 20:39:55 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 14 Jul 2010 01:39:55 -0000 Subject: [llvm-commits] [zorg] r108307 - /zorg/trunk/lnt/lnt/util/NTEmailReport.py Message-ID: <20100714013955.BE9DB2A6C12C@llvm.org> Author: ddunbar Date: Tue Jul 13 20:39:55 2010 New Revision: 108307 URL: http://llvm.org/viewvc/llvm-project?rev=108307&view=rev Log: LNT: Add support for multipart email reports (not yet used). Modified: zorg/trunk/lnt/lnt/util/NTEmailReport.py Modified: zorg/trunk/lnt/lnt/util/NTEmailReport.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/util/NTEmailReport.py?rev=108307&r1=108306&r2=108307&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/util/NTEmailReport.py (original) +++ zorg/trunk/lnt/lnt/util/NTEmailReport.py Tue Jul 13 20:39:55 2010 @@ -36,14 +36,29 @@ def emailReport(db, run, baseurl, host, from_, to, was_added=True, will_commit=True): + import email.mime.multipart import email.mime.text - subject, report = getReport(db, run, baseurl, was_added, will_commit) + subject, report, html_report = getReport(db, run, baseurl, was_added, + will_commit) - msg = email.mime.text.MIMEText(report) - msg['Subject'] = subject - msg['From'] = from_ - msg['To'] = to + # Generate a plain text message if we have no html report. + if not html_report: + msg = email.mime.text.MIMEText(report) + msg['Subject'] = subject + msg['From'] = from_ + msg['To'] = to + else: + msg = email.mime.multipart.MIMEMultipart('alternative') + msg['Subject'] = subject + msg['From'] = from_ + msg['To'] = to + + # Attach parts into message container, according to RFC 2046, the last + # part of a multipart message, in this case the HTML message, is best + # and preferred. + msg.attach(email.mime.text.MIMEText(report, 'plain')) + msg.attach(email.mime.text.MIMEText(html_report, 'html')) s = smtplib.SMTP(host) s.sendmail(from_, [to], msg.as_string()) @@ -221,7 +236,7 @@ if len(tests) > 10: print >>report, ' ... and %d more ...' % (len(tests) - 10,) - return subject, report.getvalue() + return subject, report.getvalue(), None def getReport(db, run, baseurl, was_added, will_commit): report = StringIO.StringIO() @@ -397,7 +412,7 @@ # FIXME: Where is the old mailer getting the arch from? subject = """%s nightly tester results""" % machine.name - return subject,report.getvalue() + return subject, report.getvalue(), None if __name__ == '__main__': main() From daniel at zuster.org Tue Jul 13 20:39:58 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 14 Jul 2010 01:39:58 -0000 Subject: [llvm-commits] [zorg] r108308 - in /zorg/trunk/lnt/lnt: util/NTEmailReport.py viewer/simple.ptl Message-ID: <20100714013958.A8F052A6C12E@llvm.org> Author: ddunbar Date: Tue Jul 13 20:39:58 2010 New Revision: 108308 URL: http://llvm.org/viewvc/llvm-project?rev=108308&view=rev Log: LNT/simple: Add HTML email reports for simple style tests. Also, add support to web view to see text/HTML reports directly. Modified: zorg/trunk/lnt/lnt/util/NTEmailReport.py zorg/trunk/lnt/lnt/viewer/simple.ptl Modified: zorg/trunk/lnt/lnt/util/NTEmailReport.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/util/NTEmailReport.py?rev=108308&r1=108307&r2=108308&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/util/NTEmailReport.py (original) +++ zorg/trunk/lnt/lnt/util/NTEmailReport.py Tue Jul 13 20:39:58 2010 @@ -14,10 +14,13 @@ from lnt import viewer from lnt.db import runinfo from lnt.db import perfdbsummary +from lnt.viewer import GraphUtil from lnt.viewer import Util from lnt.viewer import PerfDB from lnt.viewer.NTUtil import * +from lnt.viewer.PerfDB import Run, Sample + def main(): global opts from optparse import OptionParser @@ -79,7 +82,9 @@ best = r return best -def getSimpleReport(db, run, baseurl, was_added, will_commit): +def getSimpleReport(db, run, baseurl, was_added, will_commit, + only_html_body = False, show_graphs = False): + machine = run.machine tag = run.info['tag'].value # Get the run summary. @@ -140,14 +145,18 @@ # Generate the report. report = StringIO.StringIO() + html_report = StringIO.StringIO() machine = run.machine subject = """%s nightly tester results""" % machine.name + # Generate the report header. if baseurl[-1] == '/': baseurl = baseurl[:-1] - print >>report, """%s/simple/%s/%d/""" % (baseurl, tag, run.id) + + report_url = """%s/simple/%s/%d/""" % (baseurl, tag, run.id) + print >>report, report_url print >>report, """Nickname: %s:%d""" % (machine.name, machine.number) if 'name' in machine.info: print >>report, """Name: %s""" % (machine.info['name'].value,) @@ -168,11 +177,53 @@ print >>report, """ To: (none)""" print >>report + # Generate the HTML report header. + print >>html_report, """\ +

%s

+""" % subject + print >>html_report, """\ +""" % (report_url, report_url) + print >>html_report, "" % ( + machine.name, machine.number) + if 'name' in machine.info: + print >>html_report, """""" % ( + machine.info['name'].value,) + print >>html_report, """
URL%s
Nickname%s:%d
Name%s
""" + print >>html_report, """\ +

+ + + + + + + + """ + print >>html_report, """\ +""" % ( + run.id, run.info['run_order'].value, run.start_time, run.end_time) + if compare_to: + print >>html_report, """\ +""" % ( + compare_to.id, compare_to.info['run_order'].value, + compare_to.start_time, compare_to.end_time) + else: + print >>html_report, """""" + print >>html_report, """
RunIDOrderStart TimeEnd Time
Current%d%s%s%s
Previous%d%s%s%s
No Previous Run
""" + if compare_to and run.machine != compare_to.machine: + print >>html_report, """

*** WARNING ***:""", + print >>html_report, """comparison is against a different machine""", + print >>html_report, """(%s:%d)

""" % (compare_to.machine.name, + compare_to.machine.number) + if existing_failures: - print >>report, 'Total Existing Failures:', sum( - map(len, existing_failures.values())) + num_existing_failures = sum(map(len, existing_failures.values())) + print >>report, 'Total Existing Failures:', num_existing_failures print >>report + print >>html_report, """\ +

Total Existing Failures: %d

""" % num_existing_failures + # Generate the summary of the changes. items_info = (('New Failures', new_failures, False), ('New Passes', new_passes, False), @@ -182,23 +233,39 @@ ('Added Tests', added_tests, False)) total_changes = sum([sum(map(len, items.values())) for _,items,_ in items_info]) + graphs = [] if total_changes: print >>report, """===============""" print >>report, """Changes Summary""" print >>report, """===============""" print >>report + print >>html_report, """ +
+

Changes Summary

+ +""" for name,items,_ in items_info: if items: - print >>report, '%s: %d' % (name, sum(map(len, items.values()))) + num_items = sum(map(len, items.values())) + print >>report, '%s: %d' % (name, num_items) + print >>html_report, """ +""" % (name, num_items) print >>report + print >>html_report, """ +
Change Kind#
%s%d
+""" print >>report, """==============""" print >>report, """Changes Detail""" print >>report, """==============""" + print >>html_report, """ +

+

Changes Detail

""" for name,items,show_perf in items_info: if not items: continue + show_pset = items.items()[0][0] or len(items) > 1 print >>report print >>report, name print >>report, '-' * len(name) @@ -206,36 +273,130 @@ if show_perf: tests.sort(key = lambda (_,cr): -abs(cr.pct_delta)) - if pset or len(items) > 1: + if show_pset: print >>report print >>report, "Parameter Set:", pset - for name,cr in tests: + table_name = "%s - %s" % (name, pset) + else: + table_name = name + print >>html_report, """ +

+ +""" % table_name + if show_perf: + print >>html_report, """ +""" + print >>html_report, """""" + + for i,(name,cr) in enumerate(tests): if show_perf: print >>report, (' %s: %.2f%%' '(%.4f => %.4f, std. dev.: %.4f)') % ( name, 100. * cr.pct_delta, cr.previous, cr.current, cr.stddev) + + # Show inline charts for top 10 changes. + if show_graphs and i < 10: + graph_name = "graph.%d" % len(graphs) + graphs.append( (graph_name,name,pset) ) + extra_cell_value = """ +
+""" % (graph_name) + else: + extra_cell_value = "" + pct_value = Util.PctCell(cr.pct_delta).render() + print >>html_report, """ +%s""" %( + name, extra_cell_value, pct_value, + cr.previous, cr.current, cr.stddev) else: print >>report, ' %s' % (name,) + print >>html_report, """ +""" % (name,) + print >>html_report, """ +
%sΔPreviousCurrent σ
%s%s%.4f%.4f%.4f
%s
""" # Generate a list of the existing failures. if existing_failures: + show_pset = existing_failures.items()[0][0] or len(items) > 1 + print >>report print >>report, """=================""" print >>report, """Existing Failures""" print >>report, """=================""" + print >>html_report, """ +

+

Existing Failures

""" for pset,tests in existing_failures.items(): - if pset or len(existing_failures) > 1: + if show_pset: print >>report print >>report, "Parameter Set:", pset + table_name = "Existing Failures - %s" % (name, pset) + else: + table_name = "Existing Failures" # Print at most 10 failures in an email report. + print >>html_report, """ +

+ +""" % table_name N = 10 for name,cr in tests[:N]: print >>report, ' %s' % (name,) + print >>html_report, """""" % (name,) if len(tests) > 10: print >>report, ' ... and %d more ...' % (len(tests) - 10,) + print >>html_report, """ +""" % ( + len(tests) - 10,) + print >>html_report, """ +
%s
%s
... and %d more ...
""" + + # Finish up the HTML report. + if graphs: + # Get the test ids we want data for. + test_ids = [ts_summary.test_id_map[(name,pset)] + for _,name,pset in graphs] + + plots_iter = GraphUtil.get_test_plots(db, machine, test_ids, + run_summary, ts_summary, + show_mad_error = True, + show_points = True) + + print >>html_report, """ +""" + + html_report = html_report.getvalue() + if not only_html_body: + html_report = """ + + + + + + + %(subject)s + + +%(html_report)s + +""" % locals() + return subject, report.getvalue(), html_report return subject, report.getvalue(), None def getReport(db, run, baseurl, was_added, will_commit): Modified: zorg/trunk/lnt/lnt/viewer/simple.ptl URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/viewer/simple.ptl?rev=108308&r1=108307&r2=108308&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/viewer/simple.ptl (original) +++ zorg/trunk/lnt/lnt/viewer/simple.ptl Tue Jul 13 20:39:58 2010 @@ -10,10 +10,12 @@ import quixote from quixote.directory import Directory from quixote.errors import TraversalError +from quixote.html import htmltext from lnt.db import runinfo from lnt.db import perfdbsummary from lnt.util import stats +from lnt.util import NTEmailReport from lnt.viewer import GraphUtil import Util @@ -23,7 +25,7 @@ from PerfDB import Machine, Run, RunInfo, Test class SimpleRunUI(Directory): - _q_exports = ["", "graph"] + _q_exports = ["", "graph", "report", "text_report"] def __init__(self, root, tag, idstr): self.root = root @@ -196,13 +198,23 @@ run,run_summary,compare_to = self.getInfo(db) machine = run.machine + # Add JS to run the init_report function, if embedded. + init = """\ + function init() { + if (init_report) { + init_report(); + } + } + """ self.root.getHeader('Run Results', "../../..", components=((self.tag, '%s/%s' % ('simple',self.tag)), ('machine', 'simple/%s/machines/%d'%(self.tag, machine.id))), - addPopupJS=True, addFormCSS=True) + addPopupJS=True, addFormCSS=True, addGraphJS=True, + addJSScript=init, + onload="init()") self.show_run_page(db, run, run_summary, compare_to, lambda: self._q_index_body(db, run, run_summary, @@ -393,6 +405,35 @@ self.show_run_page(db, run, run_summary, compare_to, graph_body) + def report(self): + db = self.root.getDB() + + request = quixote.get_request() + show_graphs = bool(request.form.get('show_graphs')) + run,run_summary,compare_to = self.getInfo(db) + + _, _, html_report = NTEmailReport.getSimpleReport( + db, run, str("%s/db_%s/") % (self.root.config.zorgURL, + self.root.dbName), + True, True, show_graphs = show_graphs) + + return htmltext(html_report) + + def text_report(self): + db = self.root.getDB() + + run,run_summary,compare_to = self.getInfo(db) + + _, text_report, _ = NTEmailReport.getSimpleReport( + db, run, str("%s/db_%s/") % (self.root.config.zorgURL, + self.root.dbName), + True, True) + + response = quixote.get_response() + response.set_content_type('text/plain') + + return text_report + def _q_index_body [html] (self, db, run, run_summary, compare_to): # Load the test suite summary. ts_summary = perfdbsummary.get_simple_suite_summary(db, self.tag) @@ -410,13 +451,17 @@ title="Show All Values") form.add(quixote.form.IntWidget, "num_comparison_runs", title="Number of Comparison Runs") + form.add(quixote.form.CheckboxWidget, "show_graphs", + title="Show Report Graphs") form.add_submit("submit", "Update") request = quixote.get_request() + show_graphs = bool(form['show_graphs']) show_delta = bool(form['show_delta']) show_stddev = bool(form['show_stddev']) show_mad = bool(form['show_mad']) show_all = bool(form['show_all']) + show_graphs = bool(form['show_graphs']) try: num_comparison_runs = int(form['num_comparison_runs']) except: @@ -426,6 +471,19 @@ form.render() self.renderPopupEnd() + _, text_report, html_report = NTEmailReport.getSimpleReport( + db, run, str("%s/db_%s/") % (self.root.config.zorgURL, + self.root.dbName), + True, True, only_html_body = True, show_graphs = show_graphs) + self.renderPopupBegin('text_report', 'Report (Text)', True) + """ + 

%s
""" % (text_report,) + self.renderPopupEnd() + + self.renderPopupBegin('html_report', 'Report (HTML)', False) + htmltext(html_report) + self.renderPopupEnd() + # Gather the runs to use for statistical data. cur_id = run.id comparison_window = [] From sabre at nondot.org Tue Jul 13 20:57:17 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 14 Jul 2010 01:57:17 -0000 Subject: [llvm-commits] [llvm] r108309 - /llvm/trunk/lib/Target/PIC16/PIC16DebugInfo.cpp Message-ID: <20100714015717.9EBF32A6C12C@llvm.org> Author: lattner Date: Tue Jul 13 20:57:17 2010 New Revision: 108309 URL: http://llvm.org/viewvc/llvm-project?rev=108309&view=rev Log: fix a bug found by a warning I added to clang this morning. Modified: llvm/trunk/lib/Target/PIC16/PIC16DebugInfo.cpp Modified: llvm/trunk/lib/Target/PIC16/PIC16DebugInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16DebugInfo.cpp?rev=108309&r1=108308&r2=108309&view=diff ============================================================================== --- llvm/trunk/lib/Target/PIC16/PIC16DebugInfo.cpp (original) +++ llvm/trunk/lib/Target/PIC16/PIC16DebugInfo.cpp Tue Jul 13 20:57:17 2010 @@ -416,7 +416,7 @@ if (!TagName.empty()) Tmp += ", " + TagName; for (int i = 0; i Author: lattner Date: Tue Jul 13 21:21:59 2010 New Revision: 108310 URL: http://llvm.org/viewvc/llvm-project?rev=108310&view=rev Log: temporarily disable to test to fix buildbots. Modified: llvm/trunk/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll Modified: llvm/trunk/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll?rev=108310&r1=108309&r2=108310&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll (original) +++ llvm/trunk/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll Tue Jul 13 21:21:59 2010 @@ -1,5 +1,6 @@ -; RUN: llc < %s -march=x86-64 -mattr=+sse3 -stats |& grep {7 machine-licm} -; RUN: llc < %s -march=x86-64 -mattr=+sse3 | FileCheck %s +; RUN: true +; llc < %s -march=x86-64 -mattr=+sse3 -stats |& grep {7 machine-licm} +; llc < %s -march=x86-64 -mattr=+sse3 | FileCheck %s ; rdar://6627786 ; rdar://7792037 From evan.cheng at apple.com Wed Jul 14 00:49:23 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 14 Jul 2010 05:49:23 -0000 Subject: [llvm-commits] [llvm] r108319 - /llvm/trunk/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll Message-ID: <20100714054923.32C882A6C12C@llvm.org> Author: evancheng Date: Wed Jul 14 00:49:23 2010 New Revision: 108319 URL: http://llvm.org/viewvc/llvm-project?rev=108319&view=rev Log: Re-enable the test with fix. Modified: llvm/trunk/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll Modified: llvm/trunk/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll?rev=108319&r1=108318&r2=108319&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll (original) +++ llvm/trunk/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll Wed Jul 14 00:49:23 2010 @@ -1,6 +1,5 @@ -; RUN: true -; llc < %s -march=x86-64 -mattr=+sse3 -stats |& grep {7 machine-licm} -; llc < %s -march=x86-64 -mattr=+sse3 | FileCheck %s +; RUN: llc < %s -march=x86-64 -mattr=+sse3,+sse41 -stats |& grep {7 machine-licm} +; RUN: llc < %s -march=x86-64 -mattr=+sse3,+sse41 | FileCheck %s ; rdar://6627786 ; rdar://7792037 From sabre at nondot.org Wed Jul 14 00:59:14 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 14 Jul 2010 05:59:14 -0000 Subject: [llvm-commits] [llvm] r108320 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineAndOrXor.cpp test/Transforms/InstCombine/or.ll Message-ID: <20100714055914.286BD2A6C12C@llvm.org> Author: lattner Date: Wed Jul 14 00:59:13 2010 New Revision: 108320 URL: http://llvm.org/viewvc/llvm-project?rev=108320&view=rev Log: reapply benjamin's instcombine patch, I don't see anything wrong with it and can't repro any problems with a manual self-host. Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp llvm/trunk/test/Transforms/InstCombine/or.ll Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp?rev=108320&r1=108319&r2=108320&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp Wed Jul 14 00:59:13 2010 @@ -1597,6 +1597,14 @@ Instruction *Ret = FoldOrWithConstants(I, Op0, A, V1, D); if (Ret) return Ret; } + + // (A & ~D) | (B & D) -> ((B ^ A) & D) ^ A + if (Op0->hasOneUse() && Op1->hasOneUse() && + match(C, m_Not(m_Specific(D)))) { + Value *Xor = Builder->CreateXor(B, A, "xor"); + Value *And = Builder->CreateAnd(Xor, D, "and"); + return BinaryOperator::CreateXor(And, A); + } } // (X >> Z) | (Y >> Z) -> (X|Y) >> Z for all shifts. Modified: llvm/trunk/test/Transforms/InstCombine/or.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/or.ll?rev=108320&r1=108319&r2=108320&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/or.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/or.ll Wed Jul 14 00:59:13 2010 @@ -350,3 +350,16 @@ ; CHECK: or <4 x i32> %and.i, %and.i129 } +; PR6773 +define i32 @test33(i32 %x, i32 %y, i32 %z) nounwind readnone { + %and = and i32 %y, %x + %not = xor i32 %x, -1 + %and2 = and i32 %z, %not + %or = or i32 %and2, %and + ret i32 %or +; CHECK: @test33 +; CHECK-NEXT: xor i32 +; CHECK-NEXT: and i32 +; CHECK-NEXT: xor i32 +; CHECK-NEXT: ret i32 +} From sabre at nondot.org Wed Jul 14 01:16:36 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 14 Jul 2010 06:16:36 -0000 Subject: [llvm-commits] [llvm] r108322 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineAndOrXor.cpp test/Transforms/InstCombine/or.ll Message-ID: <20100714061636.1D0812A6C12C@llvm.org> Author: lattner Date: Wed Jul 14 01:16:35 2010 New Revision: 108322 URL: http://llvm.org/viewvc/llvm-project?rev=108322&view=rev Log: revert r108320, I see the failures now... Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp llvm/trunk/test/Transforms/InstCombine/or.ll Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp?rev=108322&r1=108321&r2=108322&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp Wed Jul 14 01:16:35 2010 @@ -1597,14 +1597,6 @@ Instruction *Ret = FoldOrWithConstants(I, Op0, A, V1, D); if (Ret) return Ret; } - - // (A & ~D) | (B & D) -> ((B ^ A) & D) ^ A - if (Op0->hasOneUse() && Op1->hasOneUse() && - match(C, m_Not(m_Specific(D)))) { - Value *Xor = Builder->CreateXor(B, A, "xor"); - Value *And = Builder->CreateAnd(Xor, D, "and"); - return BinaryOperator::CreateXor(And, A); - } } // (X >> Z) | (Y >> Z) -> (X|Y) >> Z for all shifts. Modified: llvm/trunk/test/Transforms/InstCombine/or.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/or.ll?rev=108322&r1=108321&r2=108322&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/or.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/or.ll Wed Jul 14 01:16:35 2010 @@ -350,16 +350,3 @@ ; CHECK: or <4 x i32> %and.i, %and.i129 } -; PR6773 -define i32 @test33(i32 %x, i32 %y, i32 %z) nounwind readnone { - %and = and i32 %y, %x - %not = xor i32 %x, -1 - %and2 = and i32 %z, %not - %or = or i32 %and2, %and - ret i32 %or -; CHECK: @test33 -; CHECK-NEXT: xor i32 -; CHECK-NEXT: and i32 -; CHECK-NEXT: xor i32 -; CHECK-NEXT: ret i32 -} From bob.wilson at apple.com Wed Jul 14 01:30:44 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Wed, 14 Jul 2010 06:30:44 -0000 Subject: [llvm-commits] [llvm] r108323 - /llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Message-ID: <20100714063044.F3E4F2A6C12C@llvm.org> Author: bwilson Date: Wed Jul 14 01:30:44 2010 New Revision: 108323 URL: http://llvm.org/viewvc/llvm-project?rev=108323&view=rev Log: The bits in the cmode field of 32-bit VMOV immediate instructions all depend of the value of the immediate. Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=108323&r1=108322&r2=108323&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Wed Jul 14 01:30:44 2010 @@ -2853,11 +2853,11 @@ "vmov", "i16", "$dst, $SIMM", "", [(set QPR:$dst, (v8i16 (NEONvmovImm timm:$SIMM)))]>; -def VMOVv2i32 : N1ModImm<1, 0b000, {0,?,?,0}, 0, 0, 0, 1, (outs DPR:$dst), +def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$dst), (ins nModImm:$SIMM), IIC_VMOVImm, "vmov", "i32", "$dst, $SIMM", "", [(set DPR:$dst, (v2i32 (NEONvmovImm timm:$SIMM)))]>; -def VMOVv4i32 : N1ModImm<1, 0b000, {0,?,?,0}, 0, 1, 0, 1, (outs QPR:$dst), +def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$dst), (ins nModImm:$SIMM), IIC_VMOVImm, "vmov", "i32", "$dst, $SIMM", "", [(set QPR:$dst, (v4i32 (NEONvmovImm timm:$SIMM)))]>; From bob.wilson at apple.com Wed Jul 14 01:31:50 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Wed, 14 Jul 2010 06:31:50 -0000 Subject: [llvm-commits] [llvm] r108324 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMISelLowering.h lib/Target/ARM/ARMInstrNEON.td test/CodeGen/ARM/vmov.ll Message-ID: <20100714063150.9C7592A6C12C@llvm.org> Author: bwilson Date: Wed Jul 14 01:31:50 2010 New Revision: 108324 URL: http://llvm.org/viewvc/llvm-project?rev=108324&view=rev Log: Add support for NEON VMVN immediate instructions. Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.h llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/test/CodeGen/ARM/vmov.ll Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=108324&r1=108323&r2=108324&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Jul 14 01:31:50 2010 @@ -625,6 +625,7 @@ case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu"; case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs"; case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM"; + case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM"; case ARMISD::VDUP: return "ARMISD::VDUP"; case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE"; case ARMISD::VEXT: return "ARMISD::VEXT"; @@ -2925,6 +2926,8 @@ switch (SplatBitSize) { case 8: + if (!isVMOV) + return SDValue(); // Any 1-byte value is OK. Op=0, Cmode=1110. assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big"); OpCmode = 0xe; @@ -3006,9 +3009,9 @@ return SDValue(); case 64: { - // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff. if (!isVMOV) return SDValue(); + // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff. uint64_t BitMask = 0xff; uint64_t Val = 0; unsigned ImmMask = 1; @@ -3248,6 +3251,17 @@ SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val); return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov); } + + // Try an immediate VMVN. + uint64_t NegatedImm = (SplatBits.getZExtValue() ^ + ((1LL << SplatBitSize) - 1)); + Val = isNEONModifiedImm(NegatedImm, + SplatUndef.getZExtValue(), SplatBitSize, + DAG, VmovVT, VT.is128BitVector(), false); + if (Val.getNode()) { + SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val); + return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov); + } } } @@ -4232,14 +4246,15 @@ /// ARMISD::VDUPLANE. static SDValue PerformVDUPLANECombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) { - // If the source is already a VMOVIMM splat, the VDUPLANE is redundant. + // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is + // redundant. SDValue Op = N->getOperand(0); EVT VT = N->getValueType(0); // Ignore bit_converts. while (Op.getOpcode() == ISD::BIT_CONVERT) Op = Op.getOperand(0); - if (Op.getOpcode() != ARMISD::VMOVIMM) + if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM) return SDValue(); // Make sure the VMOV element size is not bigger than the VDUPLANE elements. Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=108324&r1=108323&r2=108324&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Wed Jul 14 01:31:50 2010 @@ -124,8 +124,11 @@ VGETLANEu, // zero-extend vector extract element VGETLANEs, // sign-extend vector extract element - // Vector duplicate: + // Vector move immediate and move negated immediate: VMOVIMM, + VMVNIMM, + + // Vector duplicate: VDUP, VDUPLANE, Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=108324&r1=108323&r2=108324&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Wed Jul 14 01:31:50 2010 @@ -65,9 +65,10 @@ def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>; def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>; -def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", - SDTypeProfile<1, 1, [SDTCisVec<0>, - SDTCisVT<1, i32>]>>; +def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>; +def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>; +def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>; + def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>; // VDUPLANE can produce a quad-register result from a double-register source, @@ -2383,6 +2384,28 @@ [(set QPR:$dst, (v4i32 (or QPR:$src1, (vnotq QPR:$src2))))]>; +// VMVN : Vector Bitwise NOT (Immediate) + +let isReMaterializable = 1 in { +def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$dst), + (ins nModImm:$SIMM), IIC_VMOVImm, + "vmvn", "i16", "$dst, $SIMM", "", + [(set DPR:$dst, (v4i16 (NEONvmvnImm timm:$SIMM)))]>; +def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$dst), + (ins nModImm:$SIMM), IIC_VMOVImm, + "vmvn", "i16", "$dst, $SIMM", "", + [(set QPR:$dst, (v8i16 (NEONvmvnImm timm:$SIMM)))]>; + +def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$dst), + (ins nModImm:$SIMM), IIC_VMOVImm, + "vmvn", "i32", "$dst, $SIMM", "", + [(set DPR:$dst, (v2i32 (NEONvmvnImm timm:$SIMM)))]>; +def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$dst), + (ins nModImm:$SIMM), IIC_VMOVImm, + "vmvn", "i32", "$dst, $SIMM", "", + [(set QPR:$dst, (v4i32 (NEONvmvnImm timm:$SIMM)))]>; +} + // VMVN : Vector Bitwise NOT def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0, (outs DPR:$dst), (ins DPR:$src), IIC_VSUBiD, Modified: llvm/trunk/test/CodeGen/ARM/vmov.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vmov.ll?rev=108324&r1=108323&r2=108324&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vmov.ll (original) +++ llvm/trunk/test/CodeGen/ARM/vmov.ll Wed Jul 14 01:31:50 2010 @@ -18,6 +18,18 @@ ret <4 x i16> < i16 4096, i16 4096, i16 4096, i16 4096 > } +define <4 x i16> @v_mvni16a() nounwind { +;CHECK: v_mvni16a: +;CHECK: vmvn.i16 d0, #0x10 + ret <4 x i16> < i16 65519, i16 65519, i16 65519, i16 65519 > +} + +define <4 x i16> @v_mvni16b() nounwind { +;CHECK: v_mvni16b: +;CHECK: vmvn.i16 d0, #0x1000 + ret <4 x i16> < i16 61439, i16 61439, i16 61439, i16 61439 > +} + define <2 x i32> @v_movi32a() nounwind { ;CHECK: v_movi32a: ;CHECK: vmov.i32 d0, #0x20 @@ -54,6 +66,42 @@ ret <2 x i32> < i32 2162687, i32 2162687 > } +define <2 x i32> @v_mvni32a() nounwind { +;CHECK: v_mvni32a: +;CHECK: vmvn.i32 d0, #0x20 + ret <2 x i32> < i32 4294967263, i32 4294967263 > +} + +define <2 x i32> @v_mvni32b() nounwind { +;CHECK: v_mvni32b: +;CHECK: vmvn.i32 d0, #0x2000 + ret <2 x i32> < i32 4294959103, i32 4294959103 > +} + +define <2 x i32> @v_mvni32c() nounwind { +;CHECK: v_mvni32c: +;CHECK: vmvn.i32 d0, #0x200000 + ret <2 x i32> < i32 4292870143, i32 4292870143 > +} + +define <2 x i32> @v_mvni32d() nounwind { +;CHECK: v_mvni32d: +;CHECK: vmvn.i32 d0, #0x20000000 + ret <2 x i32> < i32 3758096383, i32 3758096383 > +} + +define <2 x i32> @v_mvni32e() nounwind { +;CHECK: v_mvni32e: +;CHECK: vmvn.i32 d0, #0x20FF + ret <2 x i32> < i32 4294958848, i32 4294958848 > +} + +define <2 x i32> @v_mvni32f() nounwind { +;CHECK: v_mvni32f: +;CHECK: vmvn.i32 d0, #0x20FFFF + ret <2 x i32> < i32 4292804608, i32 4292804608 > +} + define <1 x i64> @v_movi64() nounwind { ;CHECK: v_movi64: ;CHECK: vmov.i64 d0, #0xFF0000FF0000FFFF From evan.cheng at apple.com Wed Jul 14 01:44:01 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 14 Jul 2010 06:44:01 -0000 Subject: [llvm-commits] [llvm] r108327 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/sibcall-4.ll Message-ID: <20100714064401.693402A6C12C@llvm.org> Author: evancheng Date: Wed Jul 14 01:44:01 2010 New Revision: 108327 URL: http://llvm.org/viewvc/llvm-project?rev=108327&view=rev Log: Fix for PR7193 was overly conservative. The only case where sibcall callee address cannot be allocated a register is in 32-bit mode where the first three arguments are marked inreg. In that case EAX, EDX, and ECX will be used for argument passing. This fixes PR7610. Added: llvm/trunk/test/CodeGen/X86/sibcall-4.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=108327&r1=108326&r2=108327&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Jul 14 01:44:01 2010 @@ -2458,17 +2458,23 @@ // If the tailcall address may be in a register, then make sure it's // possible to register allocate for it. In 32-bit, the call address can // only target EAX, EDX, or ECX since the tail call must be scheduled after - // callee-saved registers are restored. In 64-bit, it's RAX, RCX, RDX, RSI, - // RDI, R8, R9, R11. - if (!isa(Callee) && + // callee-saved registers are restored. These happen to be the same + // registers used to pass 'inreg' arguments so watch out for those. + if (!Subtarget->is64Bit() && + !isa(Callee) && !isa(Callee)) { - unsigned Limit = Subtarget->is64Bit() ? 8 : 3; unsigned NumInRegs = 0; for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { CCValAssign &VA = ArgLocs[i]; - if (VA.isRegLoc()) { - if (++NumInRegs == Limit) + if (!VA.isRegLoc()) + continue; + unsigned Reg = VA.getLocReg(); + switch (Reg) { + default: break; + case X86::EAX: case X86::EDX: case X86::ECX: + if (++NumInRegs == 3) return false; + break; } } } Added: llvm/trunk/test/CodeGen/X86/sibcall-4.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sibcall-4.ll?rev=108327&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/sibcall-4.ll (added) +++ llvm/trunk/test/CodeGen/X86/sibcall-4.ll Wed Jul 14 01:44:01 2010 @@ -0,0 +1,13 @@ +; RUN: llc < %s -mtriple=i386-pc-linux-gnu | FileCheck %s +; pr7610 + +define cc10 void @t(i32* %Base_Arg, i32* %Sp_Arg, i32* %Hp_Arg, i32 %R1_Arg) nounwind { +cm1: +; CHECK: t: +; CHECK: jmpl *%eax + %nm3 = getelementptr i32* %Sp_Arg, i32 1 + %nm9 = load i32* %Sp_Arg + %nma = inttoptr i32 %nm9 to void (i32*, i32*, i32*, i32)* + tail call cc10 void %nma(i32* %Base_Arg, i32* %nm3, i32* %Hp_Arg, i32 %R1_Arg) nounwind + ret void +} From eli.friedman at gmail.com Wed Jul 14 01:58:26 2010 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 14 Jul 2010 06:58:26 -0000 Subject: [llvm-commits] [llvm] r108328 - /llvm/trunk/lib/Target/ARM/README.txt Message-ID: <20100714065826.DE7A02A6C12C@llvm.org> Author: efriedma Date: Wed Jul 14 01:58:26 2010 New Revision: 108328 URL: http://llvm.org/viewvc/llvm-project?rev=108328&view=rev Log: A couple potential optimizations inspired by comment 4 in PR6773. Modified: llvm/trunk/lib/Target/ARM/README.txt Modified: llvm/trunk/lib/Target/ARM/README.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/README.txt?rev=108328&r1=108327&r2=108328&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/README.txt (original) +++ llvm/trunk/lib/Target/ARM/README.txt Wed Jul 14 01:58:26 2010 @@ -590,3 +590,44 @@ associated with the comparison. Perhaps a pseudo-instruction for the comparison, with a post-codegen pass to clean up and handle the condition codes? See PR5694 for testcase. + +//===---------------------------------------------------------------------===// + +Given the following on armv5: +int test1(int A, int B) { + return (A&-8388481)|(B&8388480); +} + +We currently generate: + ldr r2, .LCPI0_0 + and r0, r0, r2 + ldr r2, .LCPI0_1 + and r1, r1, r2 + orr r0, r1, r0 + bx lr + +We should be able to replace the second ldr+and with a bic (i.e. reuse the +constant which was already loaded). Not sure what's necessary to do that. + +//===---------------------------------------------------------------------===// + +Given the following on ARMv7: +int test1(int A, int B) { + return (A&-8388481)|(B&8388480); +} + +We currently generate: + bfc r0, #7, #16 + movw r2, #:lower16:8388480 + movt r2, #:upper16:8388480 + and r1, r1, r2 + orr r0, r1, r0 + bx lr + +The following is much shorter: + lsr r1, r1, #7 + bfi r0, r1, #7, #16 + bx lr + + +//===---------------------------------------------------------------------===// From grosser at fim.uni-passau.de Wed Jul 14 06:59:27 2010 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Wed, 14 Jul 2010 13:59:27 +0200 Subject: [llvm-commits] Contributing RegionInfo analysis pass Message-ID: <4C3DA69F.6060402@fim.uni-passau.de> Hi, I would like to propose a new analysis pass for LLVM. It was developed by ether and me. What is it? ======================================================================= It is called RegionInfo and calculates the (refined) single entry single exit regions of a function. A simple region is a subgraph of the CFG, that is connected to the remaining CFG by only two edges, an incoming (entry) and an outgoing (exit) edge. Such regions can be analyzed/optimized independently of the remaining CFG. Algorithms can therefore filter out regions they cannot handle or they can only optimize regions that match a certain criteria (well structured, side effect free, ...). Furthermore it might be possible to use regions to improve performance by running algorithms in a divide and conquer style on the region tree. The original idea was taken from "The Program Structure Tree - Richard Johnson, David Pearson, Keshav Pingali - 1994", however enriched with ideas from "The Refined Process Structure Tree - Jussi Vanhatalo, Hagen Voelyer, Jana Koehler - 2009". There are two main differences to the classical Program Structure Tree. First of all the algorithm takes advantage of the dominance information. I believe it is easier to understand. Furthermore so called refined regions are detected. These are subgraphs that do not have a single entry or exit edge, but can easily be transformed to have one. Refined regions allow a more fine grained analysis. ======================================================================== How was it tested? ======================================================================== There is a small test suite included in the patchset. Furthermore, it was run on the llvm/test-suite as well as the whole SPEC 2006 benchmark suite as well as the polyhedron.com fortran benchmarks. The pass was tested on an cmake and autoconf build using gcc. As well as using clang on a cmake build. (all amd64-linux) Furthermore, an analysis was done that showed the runtime is on all test cases in the order of magnitude of dominance calculation (on a Release-Asserts build on linux amd64). Furthermore, it was shown that the refined region support enables the analysis to detect over three times more regions in average. ======================================================================= Is it already used? ======================================================================= ether and me use the analysis pass in polly[2] to detect the static control parts, the regions that can be analyzed and optimized with polyhedral optimizations. As the RegionInfo pass is used almost unchanged (except small bug fixes) since April, it got some regular testing during the development of polly. ======================================================================= Where to get more information? ======================================================================= * Wiki page http://wiki.llvm.org/RegionInfo It that contains some further explanations and some nice graphs. * Doxygen of the patch http://tobias.osaft.eu/regioninfo/doxygen/annotated.html * Coverage http://tobias.osaft.eu/regioninfo/coverage/RegionInfo.cpp.html * Runtime / Number of regions found http://wiki.llvm.org/RegionInfo#Analysis ======================================================================= I want to try it? ======================================================================= Just run it on a test case or any other llvm-ir file. #> opt -regions analyze test/Analyze/RegionInfo/mix_1.ll [0] 0 => [1] 8 => 10 [2] 11 => 14 [1] 0 => 15 [2] 1 => 7 To get a graphical graphviz/dot output use: #> opt -view-regions-only test/Analyze/RegionInfo/mix_1.ll ======================================================================= The patch? ======================================================================= Attached. Any comments are highly appreciated. The patch only contains the RegionInfo pass itself, the test cases as well as the graphviz RegionViewer/RegionPrinter. The RegionPass framework, that was also developed, is not contained. We may contribute this later. ======================================================================= Thanks for reviewing the patch Cheers Tobi [1] http://wiki.llvm.org/Polyhedral_optimization_framework -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: regioninfo.patch Url: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100714/a09ce04d/attachment.pl From baldrick at free.fr Wed Jul 14 07:52:22 2010 From: baldrick at free.fr (Duncan Sands) Date: Wed, 14 Jul 2010 12:52:22 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r108329 - in /llvm-gcc-4.2/trunk/gcc: configure configure.ac Message-ID: <20100714125222.985FB2A6C12C@llvm.org> Author: baldrick Date: Wed Jul 14 07:52:22 2010 New Revision: 108329 URL: http://llvm.org/viewvc/llvm-project?rev=108329&view=rev Log: The Release-Asserts and Debug-Asserts build modes no longer exist. Remove support for them. Modified: llvm-gcc-4.2/trunk/gcc/configure llvm-gcc-4.2/trunk/gcc/configure.ac Modified: llvm-gcc-4.2/trunk/gcc/configure URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/configure?rev=108329&r1=108328&r2=108329&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/configure (original) +++ llvm-gcc-4.2/trunk/gcc/configure Wed Jul 14 07:52:22 2010 @@ -8925,12 +8925,6 @@ LLVMBUILDMODE="Release" elif test -x "$LLVMBASEPATH/Debug/bin/llc$EXEEXT"; then LLVMBUILDMODE="Debug" - elif test -x "$LLVMBASEPATH/Release-Asserts/bin/llc$EXEEXT"; then - echo Found Release-Asserts LLVM Tree in $LLVMBASEPATH - LLVMBUILDMODE="Release-Asserts" - elif test -x "$LLVMBASEPATH/Debug-Asserts/bin/llc$EXEEXT"; then - echo Found Debug-Asserts LLVM Tree in $LLVMBASEPATH - LLVMBUILDMODE="Debug-Asserts" elif test -x "$LLVMBASEPATH/Release+Asserts/bin/llc$EXEEXT"; then echo Found Release+Asserts LLVM Tree in $LLVMBASEPATH LLVMBUILDMODE="Release+Asserts" @@ -8943,12 +8937,6 @@ elif test -x "$LLVMBASEPATH/Debug+Checks/bin/llc$EXEEXT"; then echo Found Debug+Checks LLVM Tree in $LLVMBASEPATH LLVMBUILDMODE="Debug+Checks" - elif test -x "$LLVMBASEPATH/Release-Asserts+Checks/bin/llc$EXEEXT"; then - echo Found Release-Asserts+Checks LLVM Tree in $LLVMBASEPATH - LLVMBUILDMODE="Release-Asserts+Checks" - elif test -x "$LLVMBASEPATH/Debug-Asserts+Checks/bin/llc$EXEEXT"; then - echo Found Debug-Asserts+Checks LLVM Tree in $LLVMBASEPATH - LLVMBUILDMODE="Debug-Asserts+Checks" elif test -x "$LLVMBASEPATH/Release+Asserts+Checks/bin/llc$EXEEXT"; then echo Found Release+Asserts+Checks LLVM Tree in $LLVMBASEPATH LLVMBUILDMODE="Release+Asserts+Checks" Modified: llvm-gcc-4.2/trunk/gcc/configure.ac URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/configure.ac?rev=108329&r1=108328&r2=108329&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/configure.ac (original) +++ llvm-gcc-4.2/trunk/gcc/configure.ac Wed Jul 14 07:52:22 2010 @@ -858,12 +858,6 @@ LLVMBUILDMODE="Release" elif test -x "$LLVMBASEPATH/Debug/bin/llc$EXEEXT"; then LLVMBUILDMODE="Debug" - elif test -x "$LLVMBASEPATH/Release-Asserts/bin/llc$EXEEXT"; then - echo Found Release-Asserts LLVM Tree in $LLVMBASEPATH - LLVMBUILDMODE="Release-Asserts" - elif test -x "$LLVMBASEPATH/Debug-Asserts/bin/llc$EXEEXT"; then - echo Found Debug-Asserts LLVM Tree in $LLVMBASEPATH - LLVMBUILDMODE="Debug-Asserts" elif test -x "$LLVMBASEPATH/Release+Asserts/bin/llc$EXEEXT"; then echo Found Release+Asserts LLVM Tree in $LLVMBASEPATH LLVMBUILDMODE="Release+Asserts" @@ -876,12 +870,6 @@ elif test -x "$LLVMBASEPATH/Debug+Checks/bin/llc$EXEEXT"; then echo Found Debug+Checks LLVM Tree in $LLVMBASEPATH LLVMBUILDMODE="Debug+Checks" - elif test -x "$LLVMBASEPATH/Release-Asserts+Checks/bin/llc$EXEEXT"; then - echo Found Release-Asserts+Checks LLVM Tree in $LLVMBASEPATH - LLVMBUILDMODE="Release-Asserts+Checks" - elif test -x "$LLVMBASEPATH/Debug-Asserts+Checks/bin/llc$EXEEXT"; then - echo Found Debug-Asserts+Checks LLVM Tree in $LLVMBASEPATH - LLVMBUILDMODE="Debug-Asserts+Checks" elif test -x "$LLVMBASEPATH/Release+Asserts+Checks/bin/llc$EXEEXT"; then echo Found Release+Asserts+Checks LLVM Tree in $LLVMBASEPATH LLVMBUILDMODE="Release+Asserts+Checks" From baldrick at free.fr Wed Jul 14 09:32:34 2010 From: baldrick at free.fr (Duncan Sands) Date: Wed, 14 Jul 2010 14:32:34 -0000 Subject: [llvm-commits] [llvm] r108330 - /llvm/trunk/lib/System/Unix/Program.inc Message-ID: <20100714143234.18D012A6C12C@llvm.org> Author: baldrick Date: Wed Jul 14 09:32:33 2010 New Revision: 108330 URL: http://llvm.org/viewvc/llvm-project?rev=108330&view=rev Log: Rather than using an ifdef on the target to zero out fields, just use memset to zero the entire struct. Modified: llvm/trunk/lib/System/Unix/Program.inc Modified: llvm/trunk/lib/System/Unix/Program.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Unix/Program.inc?rev=108330&r1=108329&r2=108330&view=diff ============================================================================== --- llvm/trunk/lib/System/Unix/Program.inc (original) +++ llvm/trunk/lib/System/Unix/Program.inc Wed Jul 14 09:32:33 2010 @@ -310,12 +310,9 @@ // fact of having a handler at all causes the wait below to return with EINTR, // unlike if we used SIG_IGN. if (secondsToWait) { -#if !defined(__HAIKU__) && !defined(__minix) - Act.sa_sigaction = 0; -#endif + memset(&Act, 0, sizeof(Act)); Act.sa_handler = TimeOutHandler; sigemptyset(&Act.sa_mask); - Act.sa_flags = 0; sigaction(SIGALRM, &Act, &Old); alarm(secondsToWait); } From bob.wilson at apple.com Wed Jul 14 11:02:13 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Wed, 14 Jul 2010 16:02:13 -0000 Subject: [llvm-commits] [llvm] r108332 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Message-ID: <20100714160213.4D9C62A6C12C@llvm.org> Author: bwilson Date: Wed Jul 14 11:02:13 2010 New Revision: 108332 URL: http://llvm.org/viewvc/llvm-project?rev=108332&view=rev Log: Add missing address register update to t2LDM_RET instruction. Patch by Brian Lucas. PR7636. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=108332&r1=108331&r2=108332&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Jul 14 11:02:13 2010 @@ -2435,7 +2435,7 @@ hasExtraDefRegAllocReq = 1 in def t2LDM_RET : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, reglist:$dsts, variable_ops), IIC_Br, - "ldm${addr:submode}${p}${addr:wide}\t$addr, $dsts", + "ldm${addr:submode}${p}${addr:wide}\t$addr!, $dsts", "$addr.addr = $wb", []> { let Inst{31-27} = 0b11101; let Inst{26-25} = 0b00; From evan.cheng at apple.com Wed Jul 14 11:06:14 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 14 Jul 2010 09:06:14 -0700 Subject: [llvm-commits] [llvm] r108332 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td In-Reply-To: <20100714160213.4D9C62A6C12C@llvm.org> References: <20100714160213.4D9C62A6C12C@llvm.org> Message-ID: Wow. How would code work without this? Evan On Jul 14, 2010, at 9:02 AM, Bob Wilson wrote: > Author: bwilson > Date: Wed Jul 14 11:02:13 2010 > New Revision: 108332 > > URL: http://llvm.org/viewvc/llvm-project?rev=108332&view=rev > Log: > Add missing address register update to t2LDM_RET instruction. > Patch by Brian Lucas. PR7636. > > Modified: > llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td > > Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=108332&r1=108331&r2=108332&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) > +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Jul 14 11:02:13 2010 > @@ -2435,7 +2435,7 @@ > hasExtraDefRegAllocReq = 1 in > def t2LDM_RET : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, > reglist:$dsts, variable_ops), IIC_Br, > - "ldm${addr:submode}${p}${addr:wide}\t$addr, $dsts", > + "ldm${addr:submode}${p}${addr:wide}\t$addr!, $dsts", > "$addr.addr = $wb", []> { > let Inst{31-27} = 0b11101; > let Inst{26-25} = 0b00; > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From bob.wilson at apple.com Wed Jul 14 11:08:12 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Wed, 14 Jul 2010 09:08:12 -0700 Subject: [llvm-commits] [llvm] r108332 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td In-Reply-To: References: <20100714160213.4D9C62A6C12C@llvm.org> Message-ID: Thumb2SizeReduction replaces it with tPOP_RET most of the time? On Jul 14, 2010, at 9:06 AM, Evan Cheng wrote: > Wow. How would code work without this? > > Evan > > On Jul 14, 2010, at 9:02 AM, Bob Wilson wrote: > >> Author: bwilson >> Date: Wed Jul 14 11:02:13 2010 >> New Revision: 108332 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=108332&view=rev >> Log: >> Add missing address register update to t2LDM_RET instruction. >> Patch by Brian Lucas. PR7636. >> >> Modified: >> llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td >> >> Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=108332&r1=108331&r2=108332&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) >> +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Jul 14 11:02:13 2010 >> @@ -2435,7 +2435,7 @@ >> hasExtraDefRegAllocReq = 1 in >> def t2LDM_RET : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, >> reglist:$dsts, variable_ops), IIC_Br, >> - "ldm${addr:submode}${p}${addr:wide}\t$addr, $dsts", >> + "ldm${addr:submode}${p}${addr:wide}\t$addr!, $dsts", >> "$addr.addr = $wb", []> { >> let Inst{31-27} = 0b11101; >> let Inst{26-25} = 0b00; >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From bob.wilson at apple.com Wed Jul 14 11:43:47 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Wed, 14 Jul 2010 16:43:47 -0000 Subject: [llvm-commits] [llvm] r108334 - /llvm/trunk/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll Message-ID: <20100714164347.81F012A6C12C@llvm.org> Author: bwilson Date: Wed Jul 14 11:43:47 2010 New Revision: 108334 URL: http://llvm.org/viewvc/llvm-project?rev=108334&view=rev Log: Fix test to appease the buildbots. Modified: llvm/trunk/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll Modified: llvm/trunk/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll?rev=108334&r1=108333&r2=108334&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll Wed Jul 14 11:43:47 2010 @@ -12,7 +12,7 @@ ; CHECK: _ZNKSs7compareERKSs: ; CHECK: it eq ; CHECK-NEXT: subeq.w r0, r6, r8 -; CHECK-NEXT: ldmia.w sp, {r4, r5, r6, r8, r9, pc} +; CHECK-NEXT: ldmia.w sp!, {r4, r5, r6, r8, r9, pc} entry: %0 = tail call arm_aapcs_vfpcc i32 @_ZNKSs4sizeEv(%"struct.std::basic_string,std::allocator >"* %this) ; [#uses=3] %1 = tail call arm_aapcs_vfpcc i32 @_ZNKSs4sizeEv(%"struct.std::basic_string,std::allocator >"* %__str) ; [#uses=3] From bagel99 at gmail.com Wed Jul 14 11:48:44 2010 From: bagel99 at gmail.com (bagel) Date: Wed, 14 Jul 2010 11:48:44 -0500 Subject: [llvm-commits] [llvm] r108332 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td References: 20100714160213.4D9C62A6C12C@llvm.org Message-ID: <4C3DEA6C.50302@gmail.com> > Wow. How would code work without this? > > Evan It didn't. Took me a long time to track it down. Am I the only person using LLVM to generate code for a Cortex-M3 target? bagel From clattner at apple.com Wed Jul 14 11:52:32 2010 From: clattner at apple.com (Chris Lattner) Date: Wed, 14 Jul 2010 09:52:32 -0700 Subject: [llvm-commits] [llvm] r108328 - /llvm/trunk/lib/Target/ARM/README.txt In-Reply-To: <20100714065826.DE7A02A6C12C@llvm.org> References: <20100714065826.DE7A02A6C12C@llvm.org> Message-ID: <795E37E6-65DE-45CE-9FC2-4E6F9EC5E286@apple.com> Wow, nice catch. The thumb2 code in particular is really terrible, and this pattern occurs all the time for bitfield insertion. -Chris On Jul 13, 2010, at 11:58 PM, Eli Friedman wrote: > Author: efriedma > Date: Wed Jul 14 01:58:26 2010 > New Revision: 108328 > > URL: http://llvm.org/viewvc/llvm-project?rev=108328&view=rev > Log: > A couple potential optimizations inspired by comment 4 in PR6773. > > > Modified: > llvm/trunk/lib/Target/ARM/README.txt > > Modified: llvm/trunk/lib/Target/ARM/README.txt > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/README.txt?rev=108328&r1=108327&r2=108328&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/README.txt (original) > +++ llvm/trunk/lib/Target/ARM/README.txt Wed Jul 14 01:58:26 2010 > @@ -590,3 +590,44 @@ > associated with the comparison. Perhaps a pseudo-instruction for the comparison, > with a post-codegen pass to clean up and handle the condition codes? > See PR5694 for testcase. > + > +//===---------------------------------------------------------------------===// > + > +Given the following on armv5: > +int test1(int A, int B) { > + return (A&-8388481)|(B&8388480); > +} > + > +We currently generate: > + ldr r2, .LCPI0_0 > + and r0, r0, r2 > + ldr r2, .LCPI0_1 > + and r1, r1, r2 > + orr r0, r1, r0 > + bx lr > + > +We should be able to replace the second ldr+and with a bic (i.e. reuse the > +constant which was already loaded). Not sure what's necessary to do that. > + > +//===---------------------------------------------------------------------===// > + > +Given the following on ARMv7: > +int test1(int A, int B) { > + return (A&-8388481)|(B&8388480); > +} > + > +We currently generate: > + bfc r0, #7, #16 > + movw r2, #:lower16:8388480 > + movt r2, #:upper16:8388480 > + and r1, r1, r2 > + orr r0, r1, r0 > + bx lr > + > +The following is much shorter: > + lsr r1, r1, #7 > + bfi r0, r1, #7, #16 > + bx lr > + > + > +//===---------------------------------------------------------------------===// > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From gabor at mac.com Wed Jul 14 12:00:19 2010 From: gabor at mac.com (Gabor Greif) Date: Wed, 14 Jul 2010 19:00:19 +0200 Subject: [llvm-commits] [STATS] Compile time measurements r107882 vs. r108240 Message-ID: <4C3DED23.3090109@mac.com> Hi all, I was curious what effect in compile performance my commits throughout the last few days did cause. So I ran a loop three times (after a warmup round) on several revisions of the "opt" tool on a raw 403.gcc bitcode file ("-std-compile-opts"). Here are the results: gabor at google7:~/llvm-build$ grep "Total Execution" */1.info r107882/1.info: Total Execution Time: 32.1460 seconds (32.1268 wall clock) r107990/1.info: Total Execution Time: 32.0500 seconds (32.0840 wall clock) r108150/1.info: Total Execution Time: 32.0700 seconds (32.1464 wall clock) r108239/1.info: Total Execution Time: 32.0780 seconds (31.9802 wall clock) r108240/1.info: Total Execution Time: 31.8140 seconds (31.7415 wall clock) gabor at google7:~/llvm-build$ grep "Total Execution" */2.info r107882/2.info: Total Execution Time: 32.4140 seconds (32.1649 wall clock) r107990/2.info: Total Execution Time: 32.0940 seconds (31.9776 wall clock) r108150/2.info: Total Execution Time: 32.0220 seconds (32.0771 wall clock) r108239/2.info: Total Execution Time: 32.1420 seconds (32.0734 wall clock) r108240/2.info: Total Execution Time: 31.7900 seconds (31.7341 wall clock) gabor at google7:~/llvm-build$ grep "Total Execution" */3.info r107882/3.info: Total Execution Time: 32.2140 seconds (32.1837 wall clock) r107990/3.info: Total Execution Time: 32.0900 seconds (32.1469 wall clock) r108150/3.info: Total Execution Time: 32.0980 seconds (32.0384 wall clock) r108239/3.info: Total Execution Time: 32.0540 seconds (32.0528 wall clock) r108240/3.info: Total Execution Time: 31.8500 seconds (31.7337 wall clock) Dividing the fastest "after" by the fastest "before" gives: gabor at google7:~/llvm-build$ expr 317900000 / 32146 9889 This is more than 1% speedup. Just looking at the "CallInst operand rotation" (r108240) gives: gabor at google7:~/llvm-build$ expr 317900000 / 32054 9917 About 0.83%. Not too bad. Hope you enjoyed these numbers, Gabor PS: any ideas what options for heavy-duty passes in "opt" could I test? From gohman at apple.com Wed Jul 14 12:25:37 2010 From: gohman at apple.com (Dan Gohman) Date: Wed, 14 Jul 2010 17:25:37 -0000 Subject: [llvm-commits] [llvm] r108336 - in /llvm/trunk: include/llvm/CodeGen/FastISel.h lib/CodeGen/SelectionDAG/FastISel.cpp test/CodeGen/X86/fast-isel-loads.ll Message-ID: <20100714172537.38EC82A6C12C@llvm.org> Author: djg Date: Wed Jul 14 12:25:37 2010 New Revision: 108336 URL: http://llvm.org/viewvc/llvm-project?rev=108336&view=rev Log: Delete fast-isel's trivial load optimization; it breaks debugging because it can look past points where a debugger might modify user variables. Removed: llvm/trunk/test/CodeGen/X86/fast-isel-loads.ll Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FastISel.h?rev=108336&r1=108335&r2=108336&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/FastISel.h (original) +++ llvm/trunk/include/llvm/CodeGen/FastISel.h Wed Jul 14 12:25:37 2010 @@ -307,8 +307,6 @@ } private: - bool SelectLoad(const User *I); - bool SelectBinaryOp(const User *I, unsigned ISDOpcode); bool SelectFNeg(const User *I); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=108336&r1=108335&r2=108336&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Wed Jul 14 12:25:37 2010 @@ -782,39 +782,8 @@ } bool -FastISel::SelectLoad(const User *I) { - LoadInst *LI = const_cast(cast(I)); - - // For a load from an alloca, make a limited effort to find the value - // already available in a register, avoiding redundant loads. - if (!LI->isVolatile() && isa(LI->getPointerOperand())) { - BasicBlock::iterator ScanFrom = LI; - if (const Value *V = FindAvailableLoadedValue(LI->getPointerOperand(), - LI->getParent(), ScanFrom)) { - if (!V->use_empty() && - (!isa(V) || - cast(V)->getParent() == LI->getParent() || - (isa(V) && - FuncInfo.StaticAllocaMap.count(cast(V)))) && - (!isa(V) || - LI->getParent() == &LI->getParent()->getParent()->getEntryBlock())) { - unsigned ResultReg = getRegForValue(V); - if (ResultReg != 0) { - UpdateValueMap(I, ResultReg); - return true; - } - } - } - } - - return false; -} - -bool FastISel::SelectOperator(const User *I, unsigned Opcode) { switch (Opcode) { - case Instruction::Load: - return SelectLoad(I); case Instruction::Add: return SelectBinaryOp(I, ISD::ADD); case Instruction::FAdd: Removed: llvm/trunk/test/CodeGen/X86/fast-isel-loads.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-loads.ll?rev=108335&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/fast-isel-loads.ll (original) +++ llvm/trunk/test/CodeGen/X86/fast-isel-loads.ll (removed) @@ -1,23 +0,0 @@ -; RUN: llc -march=x86-64 -O0 -asm-verbose=false < %s | FileCheck %s - -; Fast-isel shouldn't reload the argument values from the stack. - -; CHECK: foo: -; CHECK-NEXT: movq %rdi, -8(%rsp) -; CHECK-NEXT: movq %rsi, -16(%rsp) -; CHECK-NEXT: movsd 128(%rsi,%rdi,8), %xmm0 -; CHECK-NEXT: ret - -define double @foo(i64 %x, double* %p) nounwind { -entry: - %x.addr = alloca i64, align 8 ; [#uses=2] - %p.addr = alloca double*, align 8 ; [#uses=2] - store i64 %x, i64* %x.addr - store double* %p, double** %p.addr - %tmp = load i64* %x.addr ; [#uses=1] - %tmp1 = load double** %p.addr ; [#uses=1] - %add = add nsw i64 %tmp, 16 ; [#uses=1] - %arrayidx = getelementptr inbounds double* %tmp1, i64 %add ; [#uses=1] - %tmp2 = load double* %arrayidx ; [#uses=1] - ret double %tmp2 -} From criswell at uiuc.edu Wed Jul 14 12:36:13 2010 From: criswell at uiuc.edu (John Criswell) Date: Wed, 14 Jul 2010 17:36:13 -0000 Subject: [llvm-commits] [poolalloc] r108337 - /poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp Message-ID: <20100714173613.1B8DD2A6C12C@llvm.org> Author: criswell Date: Wed Jul 14 12:36:12 2010 New Revision: 108337 URL: http://llvm.org/viewvc/llvm-project?rev=108337&view=rev Log: The CloneFunctionInto() function now copies over function attributes more or less correctly. Removed old code that tries to copy over the attributes. Added new code to remove the sret parameter since it is (most likely) not on the first parameter anymore. Added code to set the calling convention on a cloned function to match the original function. This ensures that old call sites to the old function use the correct calling convention when they are changed to call the clone. All of this hopefully fixes PR#7626. Modified: poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp Modified: poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp?rev=108337&r1=108336&r2=108337&view=diff ============================================================================== --- poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp (original) +++ poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp Wed Jul 14 12:36:12 2010 @@ -612,7 +612,6 @@ // Create the new function... // Function *New = Function::Create(FuncTy, Function::InternalLinkage, F.getName()); - New->copyAttributesFrom(&F); F.getParent()->getFunctionList().insert(&F, New); CloneToOrigMap[New] = &F; // Remember original function. @@ -658,36 +657,27 @@ NewToOldValueMap.insert(std::make_pair(I->second, I->first)); // - // FIXME: File a bug report for CloneFunctionInto; it should take care of - // this mess for us. Also check whether it does it correctly. - // - // The cloned function will have its function attributes set more or less - // correctly at this point. However, it will not have its parameter - // attributes set correctly. We need to go through each argument in the - // old function and copy the parameter attributes over correctly. - // - - // - // Begin by clearing out all function parameter attributes. + // The CloneFunctionInto() copies over all the parameter attributes from the + // old function to the new function. However, it may place the sret + // attribute on a parameter that is no longer the first parameter. Since + // sret is required to be on the first parameter, go find any use of it and + // strip it off. This is safe since it is only used for calling conventions + // and optimization hints. // Function::ArgumentListType & ArgList = New->getArgumentList (); Function::ArgumentListType::iterator arg = ArgList.begin(); for (; arg != ArgList.end(); ++arg) { - // Whatever attributes New has for this argument, remove them. - arg->removeAttr(New->getAttributes().getParamAttributes(arg->getArgNo()+1)); + arg->removeAttr (Attribute::StructRet); } // - // Copy over the attributes from the old parameters to the new parameters. + // The CloneFunctionInto() function does not ensure that the clone has the + // same calling convention as the original function. Since pool allocation + // merely replaces uses of the old function with the clone, both must have + // the same calling convention. Make sure the new function has the same + // calling convention as the original function. // - Function::ArgumentListType & OldArgList = F.getArgumentList (); - arg = OldArgList.begin(); - for (; arg != OldArgList.end(); ++arg) { - Argument * newArg = dyn_cast(ValueMap[arg]); - assert (newArg && "Value Map for arguments incorrect!\n"); - - newArg->addAttr(F.getAttributes().getParamAttributes(arg->getArgNo()+1)); - } + New->setCallingConv (F.getCallingConv()); return FI.Clone = New; } From grosbach at apple.com Wed Jul 14 12:45:16 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 14 Jul 2010 17:45:16 -0000 Subject: [llvm-commits] [llvm] r108339 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td test/CodeGen/ARM/sub.ll test/CodeGen/Thumb2/thumb2-sbc.ll test/CodeGen/Thumb2/thumb2-sub3.ll Message-ID: <20100714174516.C92932A6C12C@llvm.org> Author: grosbach Date: Wed Jul 14 12:45:16 2010 New Revision: 108339 URL: http://llvm.org/viewvc/llvm-project?rev=108339&view=rev Log: Improve 64-subtraction of immediates when parts of the immediate can fit in the literal field of an instruction. E.g., long long foo(long long a) { return a - 734439407618LL; } rdar://7038284 Added: llvm/trunk/test/CodeGen/ARM/sub.ll llvm/trunk/test/CodeGen/Thumb2/thumb2-sub3.ll Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/test/CodeGen/Thumb2/thumb2-sbc.ll Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=108339&r1=108338&r2=108339&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Jul 14 12:45:16 2010 @@ -1694,13 +1694,19 @@ } // (sub X, imm) gets canonicalized to (add X, -imm). Match this form. +// The assume-no-carry-in form uses the negation of the input since add/sub +// assume opposite meanings of the carry flag (i.e., carry == !borrow). +// See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory +// details. def : ARMPat<(add GPR:$src, so_imm_neg:$imm), (SUBri GPR:$src, so_imm_neg:$imm)>; - -//def : ARMPat<(addc GPR:$src, so_imm_neg:$imm), -// (SUBSri GPR:$src, so_imm_neg:$imm)>; -//def : ARMPat<(adde GPR:$src, so_imm_neg:$imm), -// (SBCri GPR:$src, so_imm_neg:$imm)>; +def : ARMPat<(addc GPR:$src, so_imm_neg:$imm), + (SUBSri GPR:$src, so_imm_neg:$imm)>; +// The with-carry-in form matches bitwise not instead of the negation. +// Effectively, the inverse interpretation of the carry flag already accounts +// for part of the negation. +def : ARMPat<(adde GPR:$src, so_imm_not:$imm), + (SBCri GPR:$src, so_imm_not:$imm)>; // Note: These are implemented in C++ code, because they have to generate // ADD/SUBrs instructions, which use a complex pattern that a xform function Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=108339&r1=108338&r2=108339&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Jul 14 12:45:16 2010 @@ -122,6 +122,10 @@ return (uint32_t)(-N->getZExtValue()) < 255; }], imm_neg_XFORM>; +def imm0_255_not : PatLeaf<(i32 imm), [{ + return (uint32_t)(~N->getZExtValue()) < 255; +}], imm_comp_XFORM>; + // Define Thumb2 specific addressing modes. // t2addrmode_imm12 := reg + imm12 @@ -1391,13 +1395,32 @@ BinOpFrag<(subc node:$LHS, node:$RHS)>>; // (sub X, imm) gets canonicalized to (add X, -imm). Match this form. +// The assume-no-carry-in form uses the negation of the input since add/sub +// assume opposite meanings of the carry flag (i.e., carry == !borrow). +// See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory +// details. +// The AddedComplexity preferences the first variant over the others since +// it can be shrunk to a 16-bit wide encoding, while the others cannot. +let AddedComplexity = 1 in +def : T2Pat<(add GPR:$src, imm0_255_neg:$imm), + (t2SUBri GPR:$src, imm0_255_neg:$imm)>; +def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm), + (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>; +def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm), + (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>; +let AddedComplexity = 1 in +def : T2Pat<(addc GPR:$src, imm0_255_neg:$imm), + (t2SUBSri GPR:$src, imm0_255_neg:$imm)>; +def : T2Pat<(addc GPR:$src, t2_so_imm_neg:$imm), + (t2SUBSri GPR:$src, t2_so_imm_neg:$imm)>; +// The with-carry-in form matches bitwise not instead of the negation. +// Effectively, the inverse interpretation of the carry flag already accounts +// for part of the negation. let AddedComplexity = 1 in -def : T2Pat<(add GPR:$src, imm0_255_neg:$imm), - (t2SUBri GPR:$src, imm0_255_neg:$imm)>; -def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm), - (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>; -def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm), - (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>; +def : T2Pat<(adde GPR:$src, imm0_255_not:$imm), + (t2SBCSri GPR:$src, imm0_255_not:$imm)>; +def : T2Pat<(adde GPR:$src, t2_so_imm_not:$imm), + (t2SBCSri GPR:$src, t2_so_imm_not:$imm)>; // Select Bytes -- for disassembly only Added: llvm/trunk/test/CodeGen/ARM/sub.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/sub.ll?rev=108339&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/sub.ll (added) +++ llvm/trunk/test/CodeGen/ARM/sub.ll Wed Jul 14 12:45:16 2010 @@ -0,0 +1,29 @@ +; RUN: llc -march=arm < %s | FileCheck %s + +; 171 = 0x000000ab +define i64 @f1(i64 %a) { +; CHECK: f1 +; CHECK: subs r0, r0, #171 +; CHECK: sbc r1, r1, #0 + %tmp = sub i64 %a, 171 + ret i64 %tmp +} + +; 66846720 = 0x03fc0000 +define i64 @f2(i64 %a) { +; CHECK: f2 +; CHECK: subs r0, r0, #255, 14 +; CHECK: sbc r1, r1, #0 + %tmp = sub i64 %a, 66846720 + ret i64 %tmp +} + +; 734439407618 = 0x000000ab00000002 +define i64 @f3(i64 %a) { +; CHECK: f3 +; CHECK: subs r0, r0, #2 +; CHECK: sbc r1, r1, #171 + %tmp = sub i64 %a, 734439407618 + ret i64 %tmp +} + Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-sbc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-sbc.ll?rev=108339&r1=108338&r2=108339&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-sbc.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-sbc.ll Wed Jul 14 12:45:16 2010 @@ -1,8 +1,54 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s +; RUN: llc -march=thumb -mattr=+thumb2 < %s | FileCheck %s define i64 @f1(i64 %a, i64 %b) { -; CHECK: f1: +; CHECK: f1 ; CHECK: subs r0, r0, r2 %tmp = sub i64 %a, %b ret i64 %tmp } + +; 734439407618 = 0x000000ab00000002 +define i64 @f2(i64 %a) { +; CHECK: f2 +; CHECK: subs r0, #2 +; CHECK: sbc r1, r1, #171 + %tmp = sub i64 %a, 734439407618 + ret i64 %tmp +} + +; 5066626890203138 = 0x0012001200000002 +define i64 @f3(i64 %a) { +; CHECK: f3 +; CHECK: subs r0, #2 +; CHECK: sbc r1, r1, #1179666 + %tmp = sub i64 %a, 5066626890203138 + ret i64 %tmp +} + +; 3747052064576897026 = 0x3400340000000002 +define i64 @f4(i64 %a) { +; CHECK: f4 +; CHECK: subs r0, #2 +; CHECK: sbc r1, r1, #872428544 + %tmp = sub i64 %a, 3747052064576897026 + ret i64 %tmp +} + +; 6221254862626095106 = 0x5656565600000002 +define i64 @f5(i64 %a) { +; CHECK: f5 +; CHECK: subs r0, #2 +; CHECK: adc r1, r1, #-1448498775 + %tmp = sub i64 %a, 6221254862626095106 + ret i64 %tmp +} + +; 287104476244869122 = 0x03fc000000000002 +define i64 @f6(i64 %a) { +; CHECK: f6 +; CHECK: subs r0, #2 +; CHECK: sbc r1, r1, #66846720 + %tmp = sub i64 %a, 287104476244869122 + ret i64 %tmp +} + Added: llvm/trunk/test/CodeGen/Thumb2/thumb2-sub3.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-sub3.ll?rev=108339&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-sub3.ll (added) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-sub3.ll Wed Jul 14 12:45:16 2010 @@ -0,0 +1,55 @@ +; RUN: llc -march=thumb -mattr=+thumb2 < %s | FileCheck %s + +; 171 = 0x000000ab +define i64 @f1(i64 %a) { +; CHECK: f1 +; CHECK: subs r0, #171 +; CHECK: adc r1, r1, #-1 + %tmp = sub i64 %a, 171 + ret i64 %tmp +} + +; 1179666 = 0x00120012 +define i64 @f2(i64 %a) { +; CHECK: f2 +; CHECK: subs.w r0, r0, #1179666 +; CHECK: adc r1, r1, #-1 + %tmp = sub i64 %a, 1179666 + ret i64 %tmp +} + +; 872428544 = 0x34003400 +define i64 @f3(i64 %a) { +; CHECK: f3 +; CHECK: subs.w r0, r0, #872428544 +; CHECK: adc r1, r1, #-1 + %tmp = sub i64 %a, 872428544 + ret i64 %tmp +} + +; 1448498774 = 0x56565656 +define i64 @f4(i64 %a) { +; CHECK: f4 +; CHECK: subs.w r0, r0, #1448498774 +; CHECK: adc r1, r1, #-1 + %tmp = sub i64 %a, 1448498774 + ret i64 %tmp +} + +; 66846720 = 0x03fc0000 +define i64 @f5(i64 %a) { +; CHECK: f5 +; CHECK: subs.w r0, r0, #66846720 +; CHECK: adc r1, r1, #-1 + %tmp = sub i64 %a, 66846720 + ret i64 %tmp +} + +; 734439407618 = 0x000000ab00000002 +define i64 @f6(i64 %a) { +; CHECK: f6 +; CHECK: subs r0, #2 +; CHECK: sbc r1, r1, #171 + %tmp = sub i64 %a, 734439407618 + ret i64 %tmp +} From sabre at nondot.org Wed Jul 14 13:14:33 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 14 Jul 2010 18:14:33 -0000 Subject: [llvm-commits] [llvm] r108342 - in /llvm/trunk: include/llvm/Support/COFF.h lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp lib/Target/X86/X86COFF.h Message-ID: <20100714181433.D53372A6C12C@llvm.org> Author: lattner Date: Wed Jul 14 13:14:33 2010 New Revision: 108342 URL: http://llvm.org/viewvc/llvm-project?rev=108342&view=rev Log: Merge lib/Target/X86/X86COFF.h into include/llvm/Support/COFF.h, patch by Michael Spencer! Removed: llvm/trunk/lib/Target/X86/X86COFF.h Modified: llvm/trunk/include/llvm/Support/COFF.h llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp Modified: llvm/trunk/include/llvm/Support/COFF.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/COFF.h?rev=108342&r1=108341&r2=108342&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/COFF.h (original) +++ llvm/trunk/include/llvm/Support/COFF.h Wed Jul 14 13:14:33 2010 @@ -10,12 +10,12 @@ // This file contains an definitions used in Windows COFF Files. // // Structures and enums defined within this file where created using -// information from Microsofts publicly available PE/COFF format document: +// information from Microsoft's publicly available PE/COFF format document: // // Microsoft Portable Executable and Common Object File Format Specification // Revision 8.1 - February 15, 2008 // -// As of 5/2/2010, hosted by microsoft at: +// As of 5/2/2010, hosted by Microsoft at: // http://www.microsoft.com/whdc/system/platform/firmware/pecoff.mspx // //===----------------------------------------------------------------------===// @@ -57,7 +57,7 @@ uint8_t NumberOfAuxSymbols; }; - enum symbol_flags { + enum SymbolFlags { SF_TypeMask = 0x0000FFFF, SF_TypeShift = 0, @@ -67,36 +67,70 @@ SF_WeakReference = 0x01000000 }; - enum symbol_storage_class { - IMAGE_SYM_CLASS_END_OF_FUNCTION = -1, - IMAGE_SYM_CLASS_NULL = 0, - IMAGE_SYM_CLASS_AUTOMATIC = 1, - IMAGE_SYM_CLASS_EXTERNAL = 2, - IMAGE_SYM_CLASS_STATIC = 3, - IMAGE_SYM_CLASS_REGISTER = 4, - IMAGE_SYM_CLASS_EXTERNAL_DEF = 5, - IMAGE_SYM_CLASS_LABEL = 6, - IMAGE_SYM_CLASS_UNDEFINED_LABEL = 7, - IMAGE_SYM_CLASS_MEMBER_OF_STRUCT = 8, - IMAGE_SYM_CLASS_ARGUMENT = 9, - IMAGE_SYM_CLASS_STRUCT_TAG = 10, - IMAGE_SYM_CLASS_MEMBER_OF_UNION = 11, - IMAGE_SYM_CLASS_UNION_TAG = 12, - IMAGE_SYM_CLASS_TYPE_DEFINITION = 13, - IMAGE_SYM_CLASS_UNDEFINED_STATIC = 14, - IMAGE_SYM_CLASS_ENUM_TAG = 15, - IMAGE_SYM_CLASS_MEMBER_OF_ENUM = 16, - IMAGE_SYM_CLASS_REGISTER_PARAM = 17, - IMAGE_SYM_CLASS_BIT_FIELD = 18, + /// Storage class tells where and what the symbol represents + enum SymbolStorageClass { + IMAGE_SYM_CLASS_END_OF_FUNCTION = -1, ///< Physical end of function + IMAGE_SYM_CLASS_NULL = 0, ///< No symbol + IMAGE_SYM_CLASS_AUTOMATIC = 1, ///< Stack variable + IMAGE_SYM_CLASS_EXTERNAL = 2, ///< External symbol + IMAGE_SYM_CLASS_STATIC = 3, ///< Static + IMAGE_SYM_CLASS_REGISTER = 4, ///< Register variable + IMAGE_SYM_CLASS_EXTERNAL_DEF = 5, ///< External definition + IMAGE_SYM_CLASS_LABEL = 6, ///< Label + IMAGE_SYM_CLASS_UNDEFINED_LABEL = 7, ///< Undefined label + IMAGE_SYM_CLASS_MEMBER_OF_STRUCT = 8, ///< Member of structure + IMAGE_SYM_CLASS_ARGUMENT = 9, ///< Function argument + IMAGE_SYM_CLASS_STRUCT_TAG = 10, ///< Structure tag + IMAGE_SYM_CLASS_MEMBER_OF_UNION = 11, ///< Member of union + IMAGE_SYM_CLASS_UNION_TAG = 12, ///< Union tag + IMAGE_SYM_CLASS_TYPE_DEFINITION = 13, ///< Type definition + IMAGE_SYM_CLASS_UNDEFINED_STATIC = 14, ///< Undefined static + IMAGE_SYM_CLASS_ENUM_TAG = 15, ///< Enumeration tag + IMAGE_SYM_CLASS_MEMBER_OF_ENUM = 16, ///< Member of enumeration + IMAGE_SYM_CLASS_REGISTER_PARAM = 17, ///< Register parameter + IMAGE_SYM_CLASS_BIT_FIELD = 18, ///< Bit field + /// ".bb" or ".eb" - beginning or end of block IMAGE_SYM_CLASS_BLOCK = 100, + /// ".bf" or ".ef" - beginning or end of function IMAGE_SYM_CLASS_FUNCTION = 101, - IMAGE_SYM_CLASS_END_OF_STRUCT = 102, - IMAGE_SYM_CLASS_FILE = 103, + IMAGE_SYM_CLASS_END_OF_STRUCT = 102, ///< End of structure + IMAGE_SYM_CLASS_FILE = 103, ///< File name + /// Line number, reformatted as symbol IMAGE_SYM_CLASS_SECTION = 104, - IMAGE_SYM_CLASS_WEAK_EXTERNAL = 105, + IMAGE_SYM_CLASS_WEAK_EXTERNAL = 105, ///< Duplicate tag + /// External symbol in dmert public lib IMAGE_SYM_CLASS_CLR_TOKEN = 107 }; + enum SymbolBaseType { + IMAGE_SYM_TYPE_NULL = 0, ///< No type information or unknown base type. + IMAGE_SYM_TYPE_VOID = 1, ///< Used with void pointers and functions. + IMAGE_SYM_TYPE_CHAR = 2, ///< A character (signed byte). + IMAGE_SYM_TYPE_SHORT = 3, ///< A 2-byte signed integer. + IMAGE_SYM_TYPE_INT = 4, ///< A natural integer type on the target. + IMAGE_SYM_TYPE_LONG = 5, ///< A 4-byte signed integer. + IMAGE_SYM_TYPE_FLOAT = 6, ///< A 4-byte floating-point number. + IMAGE_SYM_TYPE_DOUBLE = 7, ///< An 8-byte floating-point number. + IMAGE_SYM_TYPE_STRUCT = 8, ///< A structure. + IMAGE_SYM_TYPE_UNION = 9, ///< An union. + IMAGE_SYM_TYPE_ENUM = 10, ///< An enumerated type. + IMAGE_SYM_TYPE_MOE = 11, ///< A member of enumeration (a specific value). + IMAGE_SYM_TYPE_BYTE = 12, ///< A byte; unsigned 1-byte integer. + IMAGE_SYM_TYPE_WORD = 13, ///< A word; unsigned 2-byte integer. + IMAGE_SYM_TYPE_UINT = 14, ///< An unsigned integer of natural size. + IMAGE_SYM_TYPE_DWORD = 15 ///< An unsigned 4-byte integer. + }; + + enum SymbolComplexType { + IMAGE_SYM_DTYPE_NULL = 0, ///< No complex type; simple scalar variable. + IMAGE_SYM_DTYPE_POINTER = 1, ///< A pointer to base type. + IMAGE_SYM_DTYPE_FUNCTION = 2, ///< A function that returns a base type. + IMAGE_SYM_DTYPE_ARRAY = 3, ///< An array of base type. + + /// Type is formed as (base + (derived << SCT_COMPLEX_TYPE_SHIFT)) + SCT_COMPLEX_TYPE_SHIFT = 4 + }; + struct section { char Name[NameSize]; uint32_t VirtualSize; @@ -110,7 +144,7 @@ uint32_t Characteristics; }; - enum section_characteristics { + enum SectionCharacteristics { IMAGE_SCN_TYPE_NO_PAD = 0x00000008, IMAGE_SCN_CNT_CODE = 0x00000020, IMAGE_SCN_CNT_INITIALIZED_DATA = 0x00000040, @@ -154,7 +188,7 @@ uint16_t Type; }; - enum relocation_type_x86 { + enum RelocationTypeX86 { IMAGE_REL_I386_ABSOLUTE = 0x0000, IMAGE_REL_I386_DIR16 = 0x0001, IMAGE_REL_I386_REL16 = 0x0002, Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp?rev=108342&r1=108341&r2=108342&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp Wed Jul 14 13:14:33 2010 @@ -17,7 +17,6 @@ #include "X86IntelInstPrinter.h" #include "X86MCInstLower.h" #include "X86.h" -#include "X86COFF.h" #include "X86COFFMachineModuleInfo.h" #include "X86MachineFunctionInfo.h" #include "X86TargetMachine.h" @@ -35,6 +34,7 @@ #include "llvm/CodeGen/MachineJumpTableInfo.h" #include "llvm/CodeGen/MachineModuleInfoImpls.h" #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" +#include "llvm/Support/COFF.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Target/Mangler.h" #include "llvm/Target/TargetOptions.h" @@ -60,8 +60,10 @@ if (Subtarget->isTargetCOFF()) { bool Intrn = MF.getFunction()->hasInternalLinkage(); OutStreamer.BeginCOFFSymbolDef(CurrentFnSym); - OutStreamer.EmitCOFFSymbolStorageClass(Intrn ? COFF::C_STAT : COFF::C_EXT); - OutStreamer.EmitCOFFSymbolType(COFF::DT_FCN << COFF::N_BTSHFT); + OutStreamer.EmitCOFFSymbolStorageClass(Intrn ? COFF::IMAGE_SYM_CLASS_STATIC + : COFF::IMAGE_SYM_CLASS_EXTERNAL); + OutStreamer.EmitCOFFSymbolType(COFF::IMAGE_SYM_DTYPE_FUNCTION + << COFF::SCT_COMPLEX_TYPE_SHIFT); OutStreamer.EndCOFFSymbolDef(); } @@ -582,8 +584,9 @@ E = COFFMMI.externals_end(); I != E; ++I) { OutStreamer.BeginCOFFSymbolDef(CurrentFnSym); - OutStreamer.EmitCOFFSymbolStorageClass(COFF::C_EXT); - OutStreamer.EmitCOFFSymbolType(COFF::DT_FCN << COFF::N_BTSHFT); + OutStreamer.EmitCOFFSymbolStorageClass(COFF::IMAGE_SYM_CLASS_EXTERNAL); + OutStreamer.EmitCOFFSymbolType(COFF::IMAGE_SYM_DTYPE_FUNCTION + << COFF::SCT_COMPLEX_TYPE_SHIFT); OutStreamer.EndCOFFSymbolDef(); } Removed: llvm/trunk/lib/Target/X86/X86COFF.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86COFF.h?rev=108341&view=auto ============================================================================== --- llvm/trunk/lib/Target/X86/X86COFF.h (original) +++ llvm/trunk/lib/Target/X86/X86COFF.h (removed) @@ -1,95 +0,0 @@ -//===--- X86COFF.h - Some definitions from COFF documentations ------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file just defines some symbols found in COFF documentation. They are -// used to emit function type information for COFF targets (Cygwin/Mingw32). -// -//===----------------------------------------------------------------------===// - -#ifndef X86COFF_H -#define X86COFF_H - -namespace COFF -{ -/// Storage class tells where and what the symbol represents -enum StorageClass { - C_EFCN = -1, ///< Physical end of function - C_NULL = 0, ///< No symbol - C_AUTO = 1, ///< External definition - C_EXT = 2, ///< External symbol - C_STAT = 3, ///< Static - C_REG = 4, ///< Register variable - C_EXTDEF = 5, ///< External definition - C_LABEL = 6, ///< Label - C_ULABEL = 7, ///< Undefined label - C_MOS = 8, ///< Member of structure - C_ARG = 9, ///< Function argument - C_STRTAG = 10, ///< Structure tag - C_MOU = 11, ///< Member of union - C_UNTAG = 12, ///< Union tag - C_TPDEF = 13, ///< Type definition - C_USTATIC = 14, ///< Undefined static - C_ENTAG = 15, ///< Enumeration tag - C_MOE = 16, ///< Member of enumeration - C_REGPARM = 17, ///< Register parameter - C_FIELD = 18, ///< Bit field - - C_BLOCK = 100, ///< ".bb" or ".eb" - beginning or end of block - C_FCN = 101, ///< ".bf" or ".ef" - beginning or end of function - C_EOS = 102, ///< End of structure - C_FILE = 103, ///< File name - C_LINE = 104, ///< Line number, reformatted as symbol - C_ALIAS = 105, ///< Duplicate tag - C_HIDDEN = 106 ///< External symbol in dmert public lib -}; - -/// The type of the symbol. This is made up of a base type and a derived type. -/// For example, pointer to int is "pointer to T" and "int" -enum SymbolType { - T_NULL = 0, ///< No type info - T_ARG = 1, ///< Void function argument (only used by compiler) - T_VOID = 1, ///< The same as above. Just named differently in some specs. - T_CHAR = 2, ///< Character - T_SHORT = 3, ///< Short integer - T_INT = 4, ///< Integer - T_LONG = 5, ///< Long integer - T_FLOAT = 6, ///< Floating point - T_DOUBLE = 7, ///< Double word - T_STRUCT = 8, ///< Structure - T_UNION = 9, ///< Union - T_ENUM = 10, ///< Enumeration - T_MOE = 11, ///< Member of enumeration - T_UCHAR = 12, ///< Unsigned character - T_USHORT = 13, ///< Unsigned short - T_UINT = 14, ///< Unsigned integer - T_ULONG = 15 ///< Unsigned long -}; - -/// Derived type of symbol -enum SymbolDerivedType { - DT_NON = 0, ///< No derived type - DT_PTR = 1, ///< Pointer to T - DT_FCN = 2, ///< Function returning T - DT_ARY = 3 ///< Array of T -}; - -/// Masks for extracting parts of type -enum SymbolTypeMasks { - N_BTMASK = 017, ///< Mask for base type - N_TMASK = 060 ///< Mask for derived type -}; - -/// Offsets of parts of type -enum Shifts { - N_BTSHFT = 4 ///< Type is formed as (base + derived << N_BTSHIFT) -}; - -} - -#endif // X86COFF_H From clattner at apple.com Wed Jul 14 13:14:55 2010 From: clattner at apple.com (Chris Lattner) Date: Wed, 14 Jul 2010 11:14:55 -0700 Subject: [llvm-commits] [patch] Merged lib/Target/X86/X86COFF.h into include/llvm/Support/COFF.h In-Reply-To: References: Message-ID: <910E22A0-7BAE-4657-9F4B-BFF9F2603731@apple.com> Applied in r108342, thanks! On Jul 13, 2010, at 2:47 PM, Michael Spencer wrote: > Merged lib/Target/X86/X86COFF.h into include/llvm/Support/COFF.h > > - Michael Spencer > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From gohman at apple.com Wed Jul 14 13:26:50 2010 From: gohman at apple.com (Dan Gohman) Date: Wed, 14 Jul 2010 18:26:50 -0000 Subject: [llvm-commits] [llvm] r108343 - in /llvm/trunk/lib/AsmParser: LLParser.cpp LLParser.h Message-ID: <20100714182650.5968D2A6C12C@llvm.org> Author: djg Date: Wed Jul 14 13:26:50 2010 New Revision: 108343 URL: http://llvm.org/viewvc/llvm-project?rev=108343&view=rev Log: Factor out metadata parsing into a separate function. Modified: llvm/trunk/lib/AsmParser/LLParser.cpp llvm/trunk/lib/AsmParser/LLParser.h Modified: llvm/trunk/lib/AsmParser/LLParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=108343&r1=108342&r2=108343&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLParser.cpp (original) +++ llvm/trunk/lib/AsmParser/LLParser.cpp Wed Jul 14 13:26:50 2010 @@ -2022,33 +2022,8 @@ ID.StrVal = Lex.getStrVal(); ID.Kind = ValID::t_LocalName; break; - case lltok::exclaim: // !{...} MDNode, !"foo" MDString - Lex.Lex(); - - if (EatIfPresent(lltok::lbrace)) { - SmallVector Elts; - if (ParseMDNodeVector(Elts, PFS) || - ParseToken(lltok::rbrace, "expected end of metadata node")) - return true; - - ID.MDNodeVal = MDNode::get(Context, Elts.data(), Elts.size()); - ID.Kind = ValID::t_MDNode; - return false; - } - - // Standalone metadata reference - // !{ ..., !42, ... } - if (Lex.getKind() == lltok::APSInt) { - if (ParseMDNodeID(ID.MDNodeVal)) return true; - ID.Kind = ValID::t_MDNode; - return false; - } - - // MDString: - // ::= '!' STRINGCONSTANT - if (ParseMDString(ID.MDStringVal)) return true; - ID.Kind = ValID::t_MDString; - return false; + case lltok::exclaim: // !42, !{...}, or !"foo" + return ParseMetadataValue(ID, PFS); case lltok::APSInt: ID.APSIntVal = Lex.getAPSIntVal(); ID.Kind = ValID::t_APSInt; @@ -2529,6 +2504,42 @@ return false; } +/// ParseMetadataValue +/// ::= !42 +/// ::= !{...} +/// ::= !"string" +bool LLParser::ParseMetadataValue(ValID &ID, PerFunctionState *PFS) { + assert(Lex.getKind() == lltok::exclaim); + Lex.Lex(); + + // MDNode: + // !{ ... } + if (EatIfPresent(lltok::lbrace)) { + SmallVector Elts; + if (ParseMDNodeVector(Elts, PFS) || + ParseToken(lltok::rbrace, "expected end of metadata node")) + return true; + + ID.MDNodeVal = MDNode::get(Context, Elts.data(), Elts.size()); + ID.Kind = ValID::t_MDNode; + return false; + } + + // Standalone metadata reference + // !42 + if (Lex.getKind() == lltok::APSInt) { + if (ParseMDNodeID(ID.MDNodeVal)) return true; + ID.Kind = ValID::t_MDNode; + return false; + } + + // MDString: + // ::= '!' STRINGCONSTANT + if (ParseMDString(ID.MDStringVal)) return true; + ID.Kind = ValID::t_MDString; + return false; +} + //===----------------------------------------------------------------------===// // Function Parsing. Modified: llvm/trunk/lib/AsmParser/LLParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.h?rev=108343&r1=108342&r2=108343&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLParser.h (original) +++ llvm/trunk/lib/AsmParser/LLParser.h Wed Jul 14 13:26:50 2010 @@ -308,6 +308,7 @@ bool ParseGlobalValue(const Type *Ty, Constant *&V); bool ParseGlobalTypeAndValue(Constant *&V); bool ParseGlobalValueVector(SmallVectorImpl &Elts); + bool ParseMetadataValue(ValID &ID, PerFunctionState *PFS); bool ParseMDNodeVector(SmallVectorImpl &, PerFunctionState *PFS); // Function Parsing. From wdietz2 at illinois.edu Wed Jul 14 14:13:26 2010 From: wdietz2 at illinois.edu (Will Dietz) Date: Wed, 14 Jul 2010 19:13:26 -0000 Subject: [llvm-commits] [poolalloc] r108348 - in /poolalloc/trunk: include/dsa/DataStructure.h lib/DSA/DSTest.cpp lib/DSA/Printer.cpp Message-ID: <20100714191326.C03ED2A6C12C@llvm.org> Author: wdietz2 Date: Wed Jul 14 14:13:26 2010 New Revision: 108348 URL: http://llvm.org/viewvc/llvm-project?rev=108348&view=rev Log: Clean up and improve DSTest. Added -verify-flags option to DSTest, since this is a common testing requirement. Remove worthless '-dstest' option, instead just check if user specified tests. Modified: poolalloc/trunk/include/dsa/DataStructure.h poolalloc/trunk/lib/DSA/DSTest.cpp poolalloc/trunk/lib/DSA/Printer.cpp Modified: poolalloc/trunk/include/dsa/DataStructure.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/dsa/DataStructure.h?rev=108348&r1=108347&r2=108348&view=diff ============================================================================== --- poolalloc/trunk/include/dsa/DataStructure.h (original) +++ poolalloc/trunk/include/dsa/DataStructure.h Wed Jul 14 14:13:26 2010 @@ -98,9 +98,10 @@ void print(llvm::raw_ostream &O, const Module *M) const; void dumpCallGraph() const; - /// printTestInfo - Print answers to queries made by tests + /// handleTest - Handles various user-specified testing options. + /// Returns true iff the user specified for us to test something. /// - void printTestInfo(llvm::raw_ostream &O, const Module *M) const; + bool handleTest(llvm::raw_ostream &O, const Module *M) const; virtual void releaseMemory(); Modified: poolalloc/trunk/lib/DSA/DSTest.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DSTest.cpp?rev=108348&r1=108347&r2=108348&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/DSTest.cpp (original) +++ poolalloc/trunk/lib/DSA/DSTest.cpp Wed Jul 14 14:13:26 2010 @@ -1,4 +1,4 @@ -//===- DSTest.cpp - Code for quering DSA results for testing --------------===// +//===- DSTest.cpp - Queries DSA results for testing -----------------------===// // // The LLVM Compiler Infrastructure // @@ -7,10 +7,27 @@ // //===----------------------------------------------------------------------===// // -// This file implements a few basic operations that allow tests to query -// properties of the DSGraph, with an emphasis on making results something -// that is can be easily verified by 'grep' or similar basic commands. +// This defines various commandline options to DSA to help in regression tests. +// These options are: +// -print-node-for-value= Print the DSNodes for the given values +// -print-only-flags Only print Flags for the given values +// -print-only-values Only print the values pointed to by the given values +// -print-only-types Only print the types for the given values +// -check-same-node= Verify the given values' nodes were merged. +// -verify-flags= Verify the given values match the flag specifications. // +// In general a 'value' query on the DSA results looks like this: +// graph:value[:offset]* +// Examples: +// "value" specifies 'value' in the globals graph +// "func:value" specifies 'value' in graph for function 'func' +// "func:value:0" the node pointed to at offset 0 from the above +// "func:value:0:1" the node pointed to at offset 1 from the above +// ..etc +// We are also robust to "@value" and "@func" notation for convenience +// The -verify-flags option takes values in this format, but also followed +// by any number of 'flag specifiers' of the form '+flags' and '-flags', +// which indicate flags that the node should and shouldn't have. //===----------------------------------------------------------------------===// #define DEBUG_TYPE "dsgraph-test" @@ -32,9 +49,12 @@ cl::opt OnlyPrintFlags("print-only-flags", cl::ReallyHidden); cl::opt OnlyPrintValues("print-only-values", cl::ReallyHidden); cl::opt OnlyPrintTypes("print-only-types", cl::ReallyHidden); - //Test if all mentioned values are in the same node + // Test if all mentioned values are in the same node (merged) cl::list CheckNodesSame("check-same-node", cl::CommaSeparated, cl::ReallyHidden); + // For each value, verify they have (or don't have) the specified flags + cl::list VerifyFlags("verify-flags", + cl::CommaSeparated, cl::ReallyHidden); } /// NodeValue -- represents a particular node in a DSGraph @@ -43,15 +63,6 @@ /// FIXME: Make this integrated into cl parsing, as mentioned: /// http://llvm.org/docs/CommandLine.html#customparser /// -/// Supported formats (so far) -/// graph:value[:offset]* -/// Examples: -/// "value" specifies 'value' in the globals graph -/// "func:value" specifies 'value' in graph for function 'func' -/// "func:value:0" the node pointed to at offset 0 from the above -/// "func:value:0:1" the node pointed to at offset 1 from the above -/// ..etc -/// We are also robust to "@value" and "@func" notation for convenience /// FIXME: Support querying special nodes like return nodes, VANodes, etc class NodeValue { // Containing Function, if applicable. @@ -179,7 +190,7 @@ Value * getValue() { return V; } Function * getFunction() { return F; } - //Helper to fetch the node from the nodehandle + /// Helper to fetch the node from the nodehandle DSNode * getNode() { assert(NH.getNode() && "NULL node?"); return NH.getNode(); @@ -254,23 +265,31 @@ O << " array"; } -static void printFlags(llvm::raw_ostream &O, DSNode *N) { +static std::string getFlags(DSNode *N) { + std::string flags(""); + // FIXME: This code is lifted directly from Printer.cpp // Probably would be good to make this code shared... // Leaving it separate for now to minimize invasiveness if (unsigned NodeType = N->getNodeFlags()) { - if (NodeType & DSNode::AllocaNode ) O << "S"; - if (NodeType & DSNode::HeapNode ) O << "H"; - if (NodeType & DSNode::GlobalNode ) O << "G"; - if (NodeType & DSNode::UnknownNode ) O << "U"; - if (NodeType & DSNode::IncompleteNode ) O << "I"; - if (NodeType & DSNode::ModifiedNode ) O << "M"; - if (NodeType & DSNode::ReadNode ) O << "R"; - if (NodeType & DSNode::ExternalNode ) O << "E"; - if (NodeType & DSNode::IntToPtrNode ) O << "P"; - if (NodeType & DSNode::PtrToIntNode ) O << "2"; - if (NodeType & DSNode::VAStartNode ) O << "V"; + if (NodeType & DSNode::AllocaNode ) flags += "S"; + if (NodeType & DSNode::HeapNode ) flags += "H"; + if (NodeType & DSNode::GlobalNode ) flags += "G"; + if (NodeType & DSNode::UnknownNode ) flags += "U"; + if (NodeType & DSNode::IncompleteNode ) flags += "I"; + if (NodeType & DSNode::ModifiedNode ) flags += "M"; + if (NodeType & DSNode::ReadNode ) flags += "R"; + if (NodeType & DSNode::ExternalNode ) flags += "E"; + if (NodeType & DSNode::IntToPtrNode ) flags += "P"; + if (NodeType & DSNode::PtrToIntNode ) flags += "2"; + if (NodeType & DSNode::VAStartNode ) flags += "V"; } + + return flags; +} + +static void printFlags(llvm::raw_ostream &O, DSNode *N) { + O << getFlags(N); } /// printNodes -- print the node specified by NV @@ -291,47 +310,139 @@ } else if (OnlyPrintValues) { printAllValuesForNode(O, NV); } else if (OnlyPrintTypes) { - printTypesForNode(O,NV); + printTypesForNode(O, NV); } else { //Print all of them printFlags(O,NV.getNode()); O << ":{"; printAllValuesForNode(O, NV); O << "}:{"; - printTypesForNode(O,NV); + printTypesForNode(O, NV); O << "}"; } O << "\n"; } -/// printTestInfo -- runs through the user-specified testing arguments (if any) -/// and prints the requested information. -void DataStructures::printTestInfo(llvm::raw_ostream &O, const Module *M) const { - - // For each node the user indicated, print the node. - // See 'printNode' for more details. - for (cl::list::iterator I = PrintNodesForValues.begin(), - E = PrintNodesForValues.end(); I != E; ++I ) { - // Make sense of what the user gave us - NodeValue NV(*I, M, this); - // Print corresponding node - printNode(O, NV); + +/// printNodes -- For each node the user indicated, print the node. +/// See 'printNode' for more details. +/// Returns true iff the user specified nodes to print. +/// +static bool printNodes(llvm::raw_ostream &O, const Module *M, const DataStructures *DS) { + cl::list::iterator I = PrintNodesForValues.begin(), + E = PrintNodesForValues.end(); + if (I != E) { + for ( ; I != E; ++I ) { + // Make sense of what the user gave us + NodeValue NV(*I, M, DS); + // Print corresponding node + printNode(O, NV); + } + return true; } + return false; +} + +/// checkIfNodesAreSame -- Verify each node that the user indicated +/// should be merged, is in fact merged. +/// Returns true iff the user specified any nodes for this option. +/// +static bool checkIfNodesAreSame(llvm::raw_ostream &O, const Module *M, const DataStructures *DS) { // Verify all nodes listed in "CheckNodesSame" belong to the same node. - cl::list::iterator CI = CheckNodesSame.begin(), - CE = CheckNodesSame.end(); + cl::list::iterator I = CheckNodesSame.begin(), + E = CheckNodesSame.end(); // If the user specified that a set of values should be in the same node... - if (CI != CE) { + if (I != E) { // Take the first such value as the reference to compare to the others - NodeValue NVReference(*CI++,M,this); + NodeValue NVReference(*I++, M, DS); // Iterate through the remaining to verify they're the same node. - for(; CI != CE; ++CI) { - NodeValue NV(*CI, M, this); + for(; I != E; ++I) { + NodeValue NV(*I, M, DS); assert(NVReference.getNodeH()==NV.getNodeH() && "Nodes don't match!"); } + return true; + } + + return false; +} + +/// VerifyFlags -- Verify flag properties for the given nodes. +/// This is a common enough testing process that this was added to make it simpler. +/// Returns true iff the user specified anything for this option. +/// +/// This builds upon the node notation used elsewhere, and tacks on +/// node+flags, node-flags, node+flags-flags +/// Where +flags means 'this node should have these flags' +/// And -flags means 'this node should NOT have these flags' +/// +static bool verifyFlags(llvm::raw_ostream &O, const Module *M, const DataStructures *DS) { + cl::list::iterator I = VerifyFlags.begin(), + E = VerifyFlags.end(); + if (I != E) { + for(; I != E; ++I) { + std::string NodeFlagOption = *I; + std::string::size_type FlagPos = NodeFlagOption.find_first_of("+-"); + if (FlagPos == std::string::npos) { + errs() << "No flags given for option \"" << NodeFlagOption << "\"!\n"; + assert(0 && "Invalid input!"); + } + + // Grab the part before the flag specifiers and parse that as a node + std::string NodeString = std::string(I->begin(),I->begin()+FlagPos); + NodeValue NV(NodeString, M, DS); + + // Process each of the flag specifiers (+flag, or -flag) + do { + bool shouldHaveFlag = (NodeFlagOption[FlagPos] == '+'); + + // Find the next specifier... + std::string::size_type NextPos = NodeFlagOption.find_first_of("+-",FlagPos+1); + + // Parse out the flags for this option + std::string FlagsListed; + if (NextPos != std::string::npos) + FlagsListed = std::string(I->begin()+FlagPos+1,I->begin()+NextPos); + else + FlagsListed = std::string(I->begin()+FlagPos+1,I->end()); + + // Do the checking! + std::string ActualFlags = getFlags(NV.getNode()); + for (std::string::iterator I = FlagsListed.begin(), E = FlagsListed.end(); + I != E; ++I ) { + if (shouldHaveFlag) + assert((ActualFlags.find(*I) != std::string::npos) + && "Node doesn't have flag it should!"); + else + assert((ActualFlags.find(*I) == std::string::npos) + && "Node has flag it shouldn't!"); + } + + + // Update FlagPos + FlagPos = NextPos; + } while(FlagPos != std::string::npos); + } + return true; } + + return false; + +} + +/// handleTest -- handles any user-specified testing options. +/// returns true iff the user specified something to test. +/// +bool DataStructures::handleTest(llvm::raw_ostream &O, const Module *M) const { + + bool tested = false; + + tested |= printNodes(O,M,this); + tested |= checkIfNodesAreSame(O,M,this); + tested |= verifyFlags(O,M,this); + + return tested; } Modified: poolalloc/trunk/lib/DSA/Printer.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/Printer.cpp?rev=108348&r1=108347&r2=108348&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/Printer.cpp (original) +++ poolalloc/trunk/lib/DSA/Printer.cpp Wed Jul 14 14:13:26 2010 @@ -34,7 +34,6 @@ cl::list OnlyPrint("dsa-only-print", cl::ReallyHidden); cl::opt DontPrintAnything("dont-print-ds", cl::ReallyHidden); cl::opt LimitPrint("dsa-limit-print", cl::Hidden); - cl::opt PrintDSATest("dstest", cl::ReallyHidden); STATISTIC (MaxGraphSize , "Maximum graph size"); STATISTIC (NumFoldedNodes , "Number of folded nodes (in final graph)"); } @@ -402,10 +401,7 @@ // print - Print out the analysis results... void DataStructures::print(llvm::raw_ostream &O, const Module *M) const { if (DontPrintAnything) return; - if (PrintDSATest) { - printTestInfo(O, M); - return; - } + if (handleTest(O, M)) return; printCollection(*this, O, M, printname); //dumpCallGraph(); } From wdietz2 at illinois.edu Wed Jul 14 14:14:02 2010 From: wdietz2 at illinois.edu (Will Dietz) Date: Wed, 14 Jul 2010 19:14:02 -0000 Subject: [llvm-commits] [poolalloc] r108349 - /poolalloc/trunk/test/dsa/local/flags.ll Message-ID: <20100714191403.094EC2A6C12C@llvm.org> Author: wdietz2 Date: Wed Jul 14 14:14:02 2010 New Revision: 108349 URL: http://llvm.org/viewvc/llvm-project?rev=108349&view=rev Log: Move 'flags.ll' test to new, better, cleaner -verify-flags option. Modified: poolalloc/trunk/test/dsa/local/flags.ll Modified: poolalloc/trunk/test/dsa/local/flags.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/local/flags.ll?rev=108349&r1=108348&r2=108349&view=diff ============================================================================== --- poolalloc/trunk/test/dsa/local/flags.ll (original) +++ poolalloc/trunk/test/dsa/local/flags.ll Wed Jul 14 14:14:02 2010 @@ -6,34 +6,22 @@ ;a's are none, b's are mod, c'd as ref, d's are mod/ref. ;--Stack: -;RUN: dsaopt %s -dsa-local -analyze -dstest -print-only-flags -print-node-for-value \ -;RUN: "func:stack_a" | grep "S" | grep -v "M" | grep -v "R" -;RUN: dsaopt %s -dsa-local -analyze -dstest -print-only-flags -print-node-for-value \ -;RUN: "func:stack_b" | grep "S" | grep "M" | grep -v "R" -;RUN: dsaopt %s -dsa-local -analyze -dstest -print-only-flags -print-node-for-value \ -;RUN: "func:stack_c" | grep "S" | grep -v "M" | grep -v "M" -;RUN: dsaopt %s -dsa-local -analyze -dstest -print-only-flags -print-node-for-value \ -;RUN: "func:stack_d" | grep "S" | grep "M" | grep "R" +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "func:stack_a+S-MR" +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "func:stack_b+SM-R" +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "func:stack_c+S-M+R" +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "func:stack_d+SMR" ;--Heap: -;RUN: dsaopt %s -dsa-local -analyze -dstest -print-only-flags -print-node-for-value \ -;RUN: "func:heap_a:0" | grep "H" | grep -v "M" | grep -v "R" -;RUN: dsaopt %s -dsa-local -analyze -dstest -print-only-flags -print-node-for-value \ -;RUN: "func:heap_b:0" | grep "H" | grep "M" | grep -v "R" -;RUN: dsaopt %s -dsa-local -analyze -dstest -print-only-flags -print-node-for-value \ -;RUN: "func:heap_c:0" | grep "H" | grep -v "M" | grep "R" -;RUN: dsaopt %s -dsa-local -analyze -dstest -print-only-flags -print-node-for-value \ -;RUN: "func:heap_d:0" | grep "H" | grep "M" | grep "R" +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "func:heap_a:0+H-MR" +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "func:heap_b:0+HM-R" +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "func:heap_c:0+H-M+R" +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "func:heap_d:0+HMR" ;--Globals: -;RUN: dsaopt %s -dsa-local -analyze -dstest -print-only-flags -print-node-for-value \ -;RUN: "global_a" | grep "G" | grep -v "M" | grep -v "R" -;RUN: dsaopt %s -dsa-local -analyze -dstest -print-only-flags -print-node-for-value \ -;RUN: "global_b" | grep "G" | grep "M" | grep -v "R" -;RUN: dsaopt %s -dsa-local -analyze -dstest -print-only-flags -print-node-for-value \ -;RUN: "global_c" | grep "G" | grep -v "M" | grep "R" -;RUN: dsaopt %s -dsa-local -analyze -dstest -print-only-flags -print-node-for-value \ -;RUN: "global_d" | grep "G" | grep "M" | grep "R" +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "global_a+G-MR" +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "global_b+GM-R" +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "global_c+G-M+R" +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "global_d+GMR" @global_c = common global i32 0 ; [#uses=1] From wdietz2 at illinois.edu Wed Jul 14 14:33:50 2010 From: wdietz2 at illinois.edu (Will Dietz) Date: Wed, 14 Jul 2010 19:33:50 -0000 Subject: [llvm-commits] [poolalloc] r108350 - /poolalloc/trunk/test/dsa/local/malloc.ll Message-ID: <20100714193350.260112A6C12C@llvm.org> Author: wdietz2 Date: Wed Jul 14 14:33:49 2010 New Revision: 108350 URL: http://llvm.org/viewvc/llvm-project?rev=108350&view=rev Log: Update malloc test to use -verify-flags. Modified: poolalloc/trunk/test/dsa/local/malloc.ll Modified: poolalloc/trunk/test/dsa/local/malloc.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/local/malloc.ll?rev=108350&r1=108349&r2=108350&view=diff ============================================================================== --- poolalloc/trunk/test/dsa/local/malloc.ll (original) +++ poolalloc/trunk/test/dsa/local/malloc.ll Wed Jul 14 14:33:49 2010 @@ -1,10 +1,10 @@ ;--check that local detects call to malloc properly (marks them heap) -;RUN: dsaopt %s -dsa-local -analyze -dstest -print-node-for-value "main:b:0" -print-only-flags | grep "H" +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "main:b:0+H" ;--check that local has b pointing to node containing c and d -;RUN: dsaopt %s -dsa-local -analyze -dstest -check-same-node=main:b:0,main:c,main:d +;RUN: dsaopt %s -dsa-local -analyze -check-same-node=main:b:0,main:c,main:d ;--check that td/bu don't mark such nodes as incomplete -;RUN: dsaopt %s -dsa-td -analyze -dstest -print-node-for-value "main:c" -print-only-flags | not grep "I" -;RUN: dsaopt %s -dsa-bu -analyze -dstest -print-node-for-value "main:c" -print-only-flags | not grep "I" +;RUN: dsaopt %s -dsa-td -analyze -verify-flags "main:c-I" +;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "main:c-I" ; ModuleID = 'malloc_free.ll' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" From resistor at mac.com Wed Jul 14 14:52:16 2010 From: resistor at mac.com (Owen Anderson) Date: Wed, 14 Jul 2010 19:52:16 -0000 Subject: [llvm-commits] [llvm] r108351 - /llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Message-ID: <20100714195216.C609C2A6C12C@llvm.org> Author: resistor Date: Wed Jul 14 14:52:16 2010 New Revision: 108351 URL: http://llvm.org/viewvc/llvm-project?rev=108351&view=rev Log: Extend SimplifyCFG's common-destination folding heuristic to allow a single "bonus" instruction to be speculatively executed. Add a heuristic to ensure we're not tripping up out-of-order execution by checking that this bonus instruction only uses values that were already guaranteed to be available. This allows us to eliminate the short circuit in (x&1)&&(x&2). Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=108351&r1=108350&r2=108351&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Wed Jul 14 14:52:16 2010 @@ -1377,8 +1377,9 @@ bool llvm::FoldBranchToCommonDest(BranchInst *BI) { BasicBlock *BB = BI->getParent(); Instruction *Cond = dyn_cast(BI->getCondition()); - if (Cond == 0) return false; - + if (Cond == 0 || (!isa(Cond) && !isa(Cond)) || + Cond->getParent() != BB || !Cond->hasOneUse()) + return false; // Only allow this if the condition is a simple instruction that can be // executed unconditionally. It must be in the same block as the branch, and @@ -1387,11 +1388,24 @@ // Ignore dbg intrinsics. while(isa(FrontIt)) ++FrontIt; - if ((!isa(Cond) && !isa(Cond)) || - Cond->getParent() != BB || &*FrontIt != Cond || !Cond->hasOneUse()) { - return false; + + // Allow a single instruction to be hoisted in addition to the compare + // that feeds the branch. We later ensure that any values that _it_ uses + // were also live in the predecessor, so that we don't unnecessarily create + // register pressure or inhibit out-of-order execution. + Instruction *BonusInst = 0; + if (&*FrontIt != Cond && + (*FrontIt).hasOneUse() && *(*FrontIt).use_begin() == Cond && + (*FrontIt).isSafeToSpeculativelyExecute() && + !(*FrontIt).mayReadFromMemory()) { + BonusInst = &*FrontIt; + ++FrontIt; } + // Only a single bonus inst is allowed. + if (&*FrontIt != Cond) + return false; + // Make sure the instruction after the condition is the cond branch. BasicBlock::iterator CondIt = Cond; ++CondIt; // Ingore dbg intrinsics. @@ -1429,6 +1443,44 @@ !SafeToMergeTerminators(BI, PBI)) continue; + // Ensure that any values used in the bonus instruction are also used + // by the terminator of the predecessor. This means that those values + // must already have been resolved, so we won't be inhibiting the + // out-of-order core by speculating them earlier. + if (BonusInst) { + // Collect the values used by the bonus inst + SmallPtrSet UsedValues; + for (Instruction::op_iterator OI = BonusInst->op_begin(), + OE = BonusInst->op_end(); OI != OE; ++OI) { + Value* V = *OI; + if (!isa(V)) + UsedValues.insert(V); + } + + SmallVector, 4> Worklist; + Worklist.push_back(std::make_pair(PBI->getOperand(0), 0)); + + // Walk up to four levels back up the use-def chain of the predecessor's + // terminator to see if all those values were used. The choice of four + // levels is arbitrary, to provide a compile-time-cost bound. + while (!Worklist.empty()) { + std::pair Pair = Worklist.back(); + Worklist.pop_back(); + + if (Pair.second >= 4) continue; + UsedValues.erase(Pair.first); + if (UsedValues.empty()) break; + + if (Instruction* I = dyn_cast(Pair.first)) { + for (Instruction::op_iterator OI = I->op_begin(), OE = I->op_end(); + OI != OE; ++OI) + Worklist.push_back(std::make_pair(OI->get(), Pair.second+1)); + } + } + + if (!UsedValues.empty()) return false; + } + Instruction::BinaryOps Opc; bool InvertPredCond = false; @@ -1457,9 +1509,19 @@ PBI->setSuccessor(1, OldTrue); } + // If we have a bonus inst, clone it into the predecessor block. + Instruction *NewBonus = 0; + if (BonusInst) { + NewBonus = BonusInst->clone(); + PredBlock->getInstList().insert(PBI, NewBonus); + NewBonus->takeName(BonusInst); + BonusInst->setName(BonusInst->getName()+".old"); + } + // Clone Cond into the predecessor basic block, and or/and the // two conditions together. Instruction *New = Cond->clone(); + if (BonusInst) New->replaceUsesOfWith(BonusInst, NewBonus); PredBlock->getInstList().insert(PBI, New); New->takeName(Cond); Cond->setName(New->getName()+".old"); From daniel at zuster.org Wed Jul 14 15:34:16 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 14 Jul 2010 20:34:16 -0000 Subject: [llvm-commits] [zorg] r108355 - in /zorg/trunk/zorg/buildbot/builders: ClangBuilder.py DragonEggBuilder.py Util.py Message-ID: <20100714203416.90D1A2A6C12C@llvm.org> Author: ddunbar Date: Wed Jul 14 15:34:16 2010 New Revision: 108355 URL: http://llvm.org/viewvc/llvm-project?rev=108355&view=rev Log: Tweak buildbot config a bit for +Asserts change. Modified: zorg/trunk/zorg/buildbot/builders/ClangBuilder.py zorg/trunk/zorg/buildbot/builders/DragonEggBuilder.py zorg/trunk/zorg/buildbot/builders/Util.py Modified: zorg/trunk/zorg/buildbot/builders/ClangBuilder.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/zorg/buildbot/builders/ClangBuilder.py?rev=108355&r1=108354&r2=108355&view=diff ============================================================================== --- zorg/trunk/zorg/buildbot/builders/ClangBuilder.py (original) +++ zorg/trunk/zorg/buildbot/builders/ClangBuilder.py Wed Jul 14 15:34:16 2010 @@ -18,7 +18,8 @@ valgrindLeakCheck=False, outOfDir=False, useTwoStage=False, completely_clean=False, always_install=False, make='make', jobs="%(jobs)s", - stage1_config='Debug+Asserts', stage2_config='Release+Asserts', + stage1_config='Debug+Asserts', + stage2_config='Release+Asserts', extra_configure_args=[], use_pty_in_tests=False): # Don't use in-dir builds with a two stage build process. inDir = not outOfDir and not useTwoStage Modified: zorg/trunk/zorg/buildbot/builders/DragonEggBuilder.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/zorg/buildbot/builders/DragonEggBuilder.py?rev=108355&r1=108354&r2=108355&view=diff ============================================================================== --- zorg/trunk/zorg/buildbot/builders/DragonEggBuilder.py (original) +++ zorg/trunk/zorg/buildbot/builders/DragonEggBuilder.py Wed Jul 14 15:34:16 2010 @@ -180,7 +180,7 @@ WithProperties("CC=%(builddir)s/gcc.1.install/bin/gcc"), WithProperties("CXX=%(builddir)s/gcc.1.install/bin/g++"), WithProperties("GCC=%(builddir)s/gcc.1.install/bin/gcc"), - WithProperties("LLVM_CONFIG=%(builddir)s/llvm.1.obj/Debug/bin/llvm-config"), + WithProperties("LLVM_CONFIG=%(builddir)s/llvm.1.obj/Debug+Asserts/bin/llvm-config"), ], haltOnFailure = True, description=["compile", "dragonegg", "(stage 1)"], Modified: zorg/trunk/zorg/buildbot/builders/Util.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/zorg/buildbot/builders/Util.py?rev=108355&r1=108354&r2=108355&view=diff ============================================================================== --- zorg/trunk/zorg/buildbot/builders/Util.py (original) +++ zorg/trunk/zorg/buildbot/builders/Util.py Wed Jul 14 15:34:16 2010 @@ -9,10 +9,14 @@ else: raise ValueError,'Unknown config name: %r' % origname - args.append('--disable-assertions') if name.startswith('+Asserts'): name = name[len('+Asserts'):] args.append('--enable-assertions') + elif name.startswith('-Asserts'): + name = name[len('-Asserts'):] + args.append('--disable-assertions') + else: + args.append('--disable-assertions') if name.startswith('+Checks'): name = name[len('+Checks'):] From echristo at apple.com Wed Jul 14 15:50:46 2010 From: echristo at apple.com (Eric Christopher) Date: Wed, 14 Jul 2010 20:50:46 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r108356 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Message-ID: <20100714205047.0AA592A6C12C@llvm.org> Author: echristo Date: Wed Jul 14 15:50:46 2010 New Revision: 108356 URL: http://llvm.org/viewvc/llvm-project?rev=108356&view=rev Log: Revert part of the previous patch here. This is causing some miscompiles later on via SelectionDAG, likely when debug info is present. Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=108356&r1=108355&r2=108356&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Wed Jul 14 15:50:46 2010 @@ -1771,6 +1771,13 @@ DECL_SIZE(decl) != 0 && TREE_CODE(DECL_SIZE_UNIT(decl)) != INTEGER_CST) SeenVLA = decl; + // If this is just the rotten husk of a variable that the gimplifier + // eliminated all uses of, but is preserving for debug info, ignore it. + // TODO: This affects the correctness of the warning we're attempting to + // watch above. + if (TREE_CODE(decl) == VAR_DECL && DECL_VALUE_EXPR(decl)) + return; + // Gimple temporaries are handled specially: their DECL_LLVM is set when the // definition is encountered. if (isGimpleTemporary(decl)) From gohman at apple.com Wed Jul 14 15:57:55 2010 From: gohman at apple.com (Dan Gohman) Date: Wed, 14 Jul 2010 20:57:55 -0000 Subject: [llvm-commits] [llvm] r108357 - /llvm/trunk/lib/VMCore/AsmWriter.cpp Message-ID: <20100714205755.8A8502A6C12C@llvm.org> Author: djg Date: Wed Jul 14 15:57:55 2010 New Revision: 108357 URL: http://llvm.org/viewvc/llvm-project?rev=108357&view=rev Log: Rename WriteConstantInt to WriteConstantInternal, to avoid confusion. Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=108357&r1=108356&r2=108357&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/AsmWriter.cpp (original) +++ llvm/trunk/lib/VMCore/AsmWriter.cpp Wed Jul 14 15:57:55 2010 @@ -855,8 +855,9 @@ } } -static void WriteConstantInt(raw_ostream &Out, const Constant *CV, - TypePrinting &TypePrinter, SlotTracker *Machine) { +static void WriteConstantInternal(raw_ostream &Out, const Constant *CV, + TypePrinting &TypePrinter, + SlotTracker *Machine) { if (const ConstantInt *CI = dyn_cast(CV)) { if (CI->getType()->isIntegerTy(1)) { Out << (CI->getZExtValue() ? "true" : "false"); @@ -1147,7 +1148,7 @@ const Constant *CV = dyn_cast(V); if (CV && !isa(CV)) { assert(TypePrinter && "Constants require TypePrinting!"); - WriteConstantInt(Out, CV, *TypePrinter, Machine); + WriteConstantInternal(Out, CV, *TypePrinter, Machine); return; } @@ -2138,7 +2139,7 @@ TypePrinting TypePrinter; TypePrinter.print(C->getType(), OS); OS << ' '; - WriteConstantInt(OS, C, TypePrinter, 0); + WriteConstantInternal(OS, C, TypePrinter, 0); } else if (isa(this) || isa(this) || isa(this)) { WriteAsOperand(OS, this, true, 0); From gohman at apple.com Wed Jul 14 16:12:44 2010 From: gohman at apple.com (Dan Gohman) Date: Wed, 14 Jul 2010 21:12:44 -0000 Subject: [llvm-commits] [llvm] r108358 - /llvm/trunk/lib/VMCore/AsmWriter.cpp Message-ID: <20100714211244.899732A6C12C@llvm.org> Author: djg Date: Wed Jul 14 16:12:44 2010 New Revision: 108358 URL: http://llvm.org/viewvc/llvm-project?rev=108358&view=rev Log: Just use getParent() instead of getModuleFromVal when the value is a Function. Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=108358&r1=108357&r2=108358&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/AsmWriter.cpp (original) +++ llvm/trunk/lib/VMCore/AsmWriter.cpp Wed Jul 14 16:12:44 2010 @@ -2129,7 +2129,7 @@ } else if (const MDNode *N = dyn_cast(this)) { const Function *F = N->getFunction(); SlotTracker SlotTable(F); - AssemblyWriter W(OS, SlotTable, F ? getModuleFromVal(F) : 0, AAW); + AssemblyWriter W(OS, SlotTable, F ? F->getParent() : 0, AAW); W.printMDNodeBody(N); } else if (const NamedMDNode *N = dyn_cast(this)) { SlotTracker SlotTable(N->getParent()); From dalej at apple.com Wed Jul 14 16:21:39 2010 From: dalej at apple.com (Dale Johannesen) Date: Wed, 14 Jul 2010 21:21:39 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r108360 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Message-ID: <20100714212139.1965A2A6C12C@llvm.org> Author: johannes Date: Wed Jul 14 16:21:38 2010 New Revision: 108360 URL: http://llvm.org/viewvc/llvm-project?rev=108360&view=rev Log: Revert 46726. The problem it was solving has since been fixed a better way, and it had bad performance side effects. PR 5995. Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=108360&r1=108359&r2=108360&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Wed Jul 14 16:21:38 2010 @@ -2445,13 +2445,6 @@ bool isVolatile = TREE_THIS_VOLATILE(exp); const Type *Ty = ConvertType(TREE_TYPE(exp)); unsigned Alignment = LV.getAlignment(); - if (TREE_CODE(exp) == COMPONENT_REF) - if (const StructType *STy = - dyn_cast(ConvertType(TREE_TYPE(TREE_OPERAND(exp, 0))))) - if (STy->isPacked()) - // Packed struct members use 1 byte alignment - Alignment = 1; - if (!LV.isBitfield()) { if (!DestLoc) { @@ -3259,12 +3252,6 @@ LValue LV = EmitLV(lhs); bool isVolatile = TREE_THIS_VOLATILE(lhs); unsigned Alignment = LV.getAlignment(); - if (TREE_CODE(lhs) == COMPONENT_REF) - if (const StructType *STy = - dyn_cast(ConvertType(TREE_TYPE(TREE_OPERAND(lhs, 0))))) - if (STy->isPacked()) - // Packed struct members use 1 byte alignment - Alignment = 1; if (!LV.isBitfield()) { const Type *ValTy = ConvertType(TREE_TYPE(rhs)); From criswell at uiuc.edu Wed Jul 14 16:22:27 2010 From: criswell at uiuc.edu (John Criswell) Date: Wed, 14 Jul 2010 21:22:27 -0000 Subject: [llvm-commits] [poolalloc] r108361 - /poolalloc/trunk/lib/DSA/StdLibPass.cpp Message-ID: <20100714212227.C2DB32A6C12C@llvm.org> Author: criswell Date: Wed Jul 14 16:22:27 2010 New Revision: 108361 URL: http://llvm.org/viewvc/llvm-project?rev=108361&view=rev Log: Added comments. No functionality changes. Modified: poolalloc/trunk/lib/DSA/StdLibPass.cpp Modified: poolalloc/trunk/lib/DSA/StdLibPass.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/StdLibPass.cpp?rev=108361&r1=108360&r2=108361&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/StdLibPass.cpp (original) +++ poolalloc/trunk/lib/DSA/StdLibPass.cpp Wed Jul 14 16:22:27 2010 @@ -34,12 +34,32 @@ #define numOps 10 +// +// Structure: libAction +// +// Description: +// Describe how the DSGraph of a function should be built. Note that for the +// boolean arrays of arity numOps, the first element is a flag describing the +// return value, and the remaining elements are flags describing the +// function's arguments. +// struct libAction { + // The return value/arguments that should be marked read. bool read[numOps]; + + // The return value/arguments that should be marked modified. bool write[numOps]; + + // The return value/arguments that should be marked as heap. bool heap[numOps]; + + // Flags whether all arguments should be merged together. bool mergeAllArgs; + + // Flags whether the return value should be merged with all arguments. bool mergeWithRet; + + // Flags whether the return value and arguments should be folded. bool collapse; }; From dalej at apple.com Wed Jul 14 16:22:35 2010 From: dalej at apple.com (Dale Johannesen) Date: Wed, 14 Jul 2010 21:22:35 -0000 Subject: [llvm-commits] [llvm] r108362 - in /llvm/trunk/test/FrontendC: 2010-07-14-overconservative-align.c 2010-07-14-ref-off-end.c Message-ID: <20100714212235.CFB212A6C12C@llvm.org> Author: johannes Date: Wed Jul 14 16:22:35 2010 New Revision: 108362 URL: http://llvm.org/viewvc/llvm-project?rev=108362&view=rev Log: Tests for llvm-gcc commit 108360. Added: llvm/trunk/test/FrontendC/2010-07-14-overconservative-align.c llvm/trunk/test/FrontendC/2010-07-14-ref-off-end.c Added: llvm/trunk/test/FrontendC/2010-07-14-overconservative-align.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/2010-07-14-overconservative-align.c?rev=108362&view=auto ============================================================================== --- llvm/trunk/test/FrontendC/2010-07-14-overconservative-align.c (added) +++ llvm/trunk/test/FrontendC/2010-07-14-overconservative-align.c Wed Jul 14 16:22:35 2010 @@ -0,0 +1,14 @@ +// RUN: %llvmgcc %s -emit-llvm -m64 -S -o - | FileCheck %s +// PR 5995 +struct s { + int word; + struct { + int filler __attribute__ ((aligned (8))); + }; +}; + +void func (struct s *s) +{ +// CHECK: load %struct.s** %s_addr, align 8 + s->word = 0; +} Added: llvm/trunk/test/FrontendC/2010-07-14-ref-off-end.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/2010-07-14-ref-off-end.c?rev=108362&view=auto ============================================================================== --- llvm/trunk/test/FrontendC/2010-07-14-ref-off-end.c (added) +++ llvm/trunk/test/FrontendC/2010-07-14-ref-off-end.c Wed Jul 14 16:22:35 2010 @@ -0,0 +1,27 @@ +// RUN: %llvmgcc %s -S -m32 -o - | FileCheck %s +// Formerly this generated code that did a load past the end of the structure. +// That was fixed by 46726, but that patch had bad side effects and was +// reverted. This has been fixed another way in the meantime. +extern void abort(); +extern void exit(int); +struct T +{ +unsigned i:8; +unsigned c:24; +}; +f(struct T t) +{ +struct T s[1]; +s[0]=t; +return(char)s->c; +} +main() +{ +// CHECK: getelementptr inbounds %struct.T* %t, i32 0, i32 0 ; [#uses=2] +// CHECK: getelementptr inbounds %struct.T* %t, i32 0, i32 0 ; [#uses=2] +struct T t; +t.i=0xff; +t.c=0xffff11; +if(f(t)!=0x11)abort(); +exit(0); +} From gohman at apple.com Wed Jul 14 17:01:31 2010 From: gohman at apple.com (Dan Gohman) Date: Wed, 14 Jul 2010 22:01:31 -0000 Subject: [llvm-commits] [llvm] r108364 - /llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Message-ID: <20100714220131.550C62A6C12C@llvm.org> Author: djg Date: Wed Jul 14 17:01:31 2010 New Revision: 108364 URL: http://llvm.org/viewvc/llvm-project?rev=108364&view=rev Log: Properly restore DebugLoc after leaving the local constant area. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=108364&r1=108363&r2=108364&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Wed Jul 14 17:01:31 2010 @@ -288,9 +288,10 @@ FastISel::SavePoint FastISel::enterLocalValueArea() { MachineBasicBlock::iterator OldInsertPt = FuncInfo.InsertPt; + DebugLoc OldDL = DL; recomputeInsertPt(); DL = DebugLoc(); - SavePoint SP = { OldInsertPt, DL }; + SavePoint SP = { OldInsertPt, OldDL }; return SP; } From echristo at apple.com Wed Jul 14 17:26:35 2010 From: echristo at apple.com (Eric Christopher) Date: Wed, 14 Jul 2010 22:26:35 -0000 Subject: [llvm-commits] [llvm] r108365 - /llvm/trunk/test/FrontendC/vla-1.c Message-ID: <20100714222635.C11EC2A6C12C@llvm.org> Author: echristo Date: Wed Jul 14 17:26:35 2010 New Revision: 108365 URL: http://llvm.org/viewvc/llvm-project?rev=108365&view=rev Log: Add a testcase for the vla and stack realignment warning. Added: llvm/trunk/test/FrontendC/vla-1.c Added: llvm/trunk/test/FrontendC/vla-1.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/vla-1.c?rev=108365&view=auto ============================================================================== --- llvm/trunk/test/FrontendC/vla-1.c (added) +++ llvm/trunk/test/FrontendC/vla-1.c Wed Jul 14 17:26:35 2010 @@ -0,0 +1,7 @@ +// RUN: %llvmgcc -std=gnu99 %s -S |& grep {error: "is greater than the stack alignment" } + +int foo(int a) +{ + int var[a] __attribute__((__aligned__(32))); + return 4; +} From benny.kra at googlemail.com Wed Jul 14 17:38:02 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Wed, 14 Jul 2010 22:38:02 -0000 Subject: [llvm-commits] [llvm] r108366 - in /llvm/trunk: docs/ include/llvm/ADT/ include/llvm/MC/MCParser/ include/llvm/Support/ include/llvm/Target/ lib/MC/MCParser/ lib/Support/ lib/Target/ARM/AsmParser/ lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CellSPU/ lib/Target/MBlaze/ lib/Target/MSIL/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PIC16/ lib/Target/Sparc/ lib/Target/SystemZ/ lib/Target/X86/AsmParser/ lib/Target/XCore/ lib/VMCore/ Message-ID: <20100714223803.2B1982A6C12C@llvm.org> Author: d0k Date: Wed Jul 14 17:38:02 2010 New Revision: 108366 URL: http://llvm.org/viewvc/llvm-project?rev=108366&view=rev Log: Don't pass StringRef by reference. Modified: llvm/trunk/docs/ProgrammersManual.html llvm/trunk/include/llvm/ADT/APFloat.h llvm/trunk/include/llvm/ADT/APInt.h llvm/trunk/include/llvm/MC/MCParser/AsmParser.h llvm/trunk/include/llvm/Support/Regex.h llvm/trunk/include/llvm/Support/StringPool.h llvm/trunk/include/llvm/Target/TargetAsmParser.h llvm/trunk/lib/MC/MCParser/AsmParser.cpp llvm/trunk/lib/Support/APFloat.cpp llvm/trunk/lib/Support/APInt.cpp llvm/trunk/lib/Support/Regex.cpp llvm/trunk/lib/Support/StringPool.cpp llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/lib/Target/Alpha/AlphaMCAsmInfo.cpp llvm/trunk/lib/Target/Alpha/AlphaMCAsmInfo.h llvm/trunk/lib/Target/Blackfin/BlackfinMCAsmInfo.cpp llvm/trunk/lib/Target/Blackfin/BlackfinMCAsmInfo.h llvm/trunk/lib/Target/CellSPU/SPUMCAsmInfo.cpp llvm/trunk/lib/Target/CellSPU/SPUMCAsmInfo.h llvm/trunk/lib/Target/MBlaze/MBlazeMCAsmInfo.cpp llvm/trunk/lib/Target/MBlaze/MBlazeMCAsmInfo.h llvm/trunk/lib/Target/MSIL/MSILWriter.cpp llvm/trunk/lib/Target/MSIL/MSILWriter.h llvm/trunk/lib/Target/MSP430/MSP430MCAsmInfo.cpp llvm/trunk/lib/Target/MSP430/MSP430MCAsmInfo.h llvm/trunk/lib/Target/Mips/MipsMCAsmInfo.cpp llvm/trunk/lib/Target/Mips/MipsMCAsmInfo.h llvm/trunk/lib/Target/PIC16/PIC16MCAsmInfo.cpp llvm/trunk/lib/Target/PIC16/PIC16MCAsmInfo.h llvm/trunk/lib/Target/Sparc/SparcMCAsmInfo.cpp llvm/trunk/lib/Target/Sparc/SparcMCAsmInfo.h llvm/trunk/lib/Target/SystemZ/SystemZMCAsmInfo.cpp llvm/trunk/lib/Target/SystemZ/SystemZMCAsmInfo.h llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/lib/Target/XCore/XCoreMCAsmInfo.cpp llvm/trunk/lib/Target/XCore/XCoreMCAsmInfo.h llvm/trunk/lib/VMCore/AsmWriter.cpp Modified: llvm/trunk/docs/ProgrammersManual.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ProgrammersManual.html?rev=108366&r1=108365&r2=108366&view=diff ============================================================================== --- llvm/trunk/docs/ProgrammersManual.html (original) +++ llvm/trunk/docs/ProgrammersManual.html Wed Jul 14 17:38:02 2010 @@ -457,8 +457,8 @@ may have embedded null characters. Therefore, they cannot simply take a const char *, and taking a const std::string& requires clients to perform a heap allocation which is usually unnecessary. Instead, -many LLVM APIs use a const StringRef& or a const -Twine& for passing strings efficiently.

+many LLVM APIs use a StringRef or a const Twine& for +passing strings efficiently.

@@ -477,19 +477,17 @@ an std::string, or explicitly with a character pointer and length. For example, the StringRef find function is declared as:

-
- iterator find(const StringRef &Key); -
+
+  iterator find(StringRef Key);
+

and clients can call it using any one of:

-
-
+
   Map.find("foo");                 // Lookup "foo"
   Map.find(std::string("bar"));    // Lookup "bar"
   Map.find(StringRef("\0baz", 4)); // Lookup "\0baz"
 

-

Similarly, APIs which need to return a string may return a StringRef instance, which can be used directly or converted to an std::string @@ -499,7 +497,8 @@

You should rarely use the StringRef class directly, because it contains pointers to external memory it is not generally safe to store an instance of the -class (unless you know that the external storage will not be freed).

+class (unless you know that the external storage will not be freed). StringRef is +small and pervasive enough in LLVM that it should always be passed by value.

Modified: llvm/trunk/include/llvm/ADT/APFloat.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/APFloat.h?rev=108366&r1=108365&r2=108366&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/APFloat.h (original) +++ llvm/trunk/include/llvm/ADT/APFloat.h Wed Jul 14 17:38:02 2010 @@ -179,7 +179,7 @@ // Constructors. APFloat(const fltSemantics &); // Default construct to 0.0 - APFloat(const fltSemantics &, const StringRef &); + APFloat(const fltSemantics &, StringRef); APFloat(const fltSemantics &, integerPart); APFloat(const fltSemantics &, fltCategory, bool negative); APFloat(const fltSemantics &, uninitializedTag); @@ -282,7 +282,7 @@ bool, roundingMode); opStatus convertFromZeroExtendedInteger(const integerPart *, unsigned int, bool, roundingMode); - opStatus convertFromString(const StringRef&, roundingMode); + opStatus convertFromString(StringRef, roundingMode); APInt bitcastToAPInt() const; double convertToDouble() const; float convertToFloat() const; @@ -386,8 +386,8 @@ roundingMode, bool *) const; opStatus convertFromUnsignedParts(const integerPart *, unsigned int, roundingMode); - opStatus convertFromHexadecimalString(const StringRef&, roundingMode); - opStatus convertFromDecimalString (const StringRef&, roundingMode); + opStatus convertFromHexadecimalString(StringRef, roundingMode); + opStatus convertFromDecimalString(StringRef, roundingMode); char *convertNormalToHexString(char *, unsigned int, bool, roundingMode) const; opStatus roundSignificandWithExponent(const integerPart *, unsigned int, Modified: llvm/trunk/include/llvm/ADT/APInt.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/APInt.h?rev=108366&r1=108365&r2=108366&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/APInt.h (original) +++ llvm/trunk/include/llvm/ADT/APInt.h Wed Jul 14 17:38:02 2010 @@ -162,7 +162,7 @@ /// /// @param radix 2, 8, 10, or 16 /// @brief Convert a char array into an APInt - void fromString(unsigned numBits, const StringRef &str, uint8_t radix); + void fromString(unsigned numBits, StringRef str, uint8_t radix); /// This is used by the toString method to divide by the radix. It simply /// provides a more convenient form of divide for internal use since KnuthDiv @@ -248,7 +248,7 @@ /// @param str the string to be interpreted /// @param radix the radix to use for the conversion /// @brief Construct an APInt from a string representation. - APInt(unsigned numBits, const StringRef &str, uint8_t radix); + APInt(unsigned numBits, StringRef str, uint8_t radix); /// Simply makes *this a copy of that. /// @brief Copy Constructor. @@ -1153,7 +1153,7 @@ /// This method determines how many bits are required to hold the APInt /// equivalent of the string given by \arg str. /// @brief Get bits required for string value. - static unsigned getBitsNeeded(const StringRef& str, uint8_t radix); + static unsigned getBitsNeeded(StringRef str, uint8_t radix); /// countLeadingZeros - This function is an APInt version of the /// countLeadingZeros_{32,64} functions in MathExtras.h. It counts the number Modified: llvm/trunk/include/llvm/MC/MCParser/AsmParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/AsmParser.h?rev=108366&r1=108365&r2=108366&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCParser/AsmParser.h (original) +++ llvm/trunk/include/llvm/MC/MCParser/AsmParser.h Wed Jul 14 17:38:02 2010 @@ -107,7 +107,7 @@ void EatToEndOfStatement(); - bool ParseAssignment(const StringRef &Name); + bool ParseAssignment(StringRef Name); bool ParsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc); bool ParseBinOpRHS(unsigned Precedence, const MCExpr *&Res, SMLoc &EndLoc); Modified: llvm/trunk/include/llvm/Support/Regex.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/Regex.h?rev=108366&r1=108365&r2=108366&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/Regex.h (original) +++ llvm/trunk/include/llvm/Support/Regex.h Wed Jul 14 17:38:02 2010 @@ -36,7 +36,7 @@ /// Compiles the given POSIX Extended Regular Expression \arg Regex. /// This implementation supports regexes and matching strings with embedded /// NUL characters. - Regex(const StringRef &Regex, unsigned Flags = NoFlags); + Regex(StringRef Regex, unsigned Flags = NoFlags); ~Regex(); /// isValid - returns the error encountered during regex compilation, or @@ -55,7 +55,7 @@ /// the first group is always the entire pattern. /// /// This returns true on a successful match. - bool match(const StringRef &String, SmallVectorImpl *Matches=0); + bool match(StringRef String, SmallVectorImpl *Matches = 0); /// sub - Return the result of replacing the first match of the regex in /// \arg String with the \arg Repl string. Backreferences like "\0" in the Modified: llvm/trunk/include/llvm/Support/StringPool.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/StringPool.h?rev=108366&r1=108365&r2=108366&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/StringPool.h (original) +++ llvm/trunk/include/llvm/Support/StringPool.h Wed Jul 14 17:38:02 2010 @@ -64,7 +64,7 @@ /// intern - Adds a string to the pool and returns a reference-counted /// pointer to it. No additional memory is allocated if the string already /// exists in the pool. - PooledStringPtr intern(const StringRef &Str); + PooledStringPtr intern(StringRef Str); /// empty - Checks whether the pool is empty. Returns true if so. /// Modified: llvm/trunk/include/llvm/Target/TargetAsmParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetAsmParser.h?rev=108366&r1=108365&r2=108366&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetAsmParser.h (original) +++ llvm/trunk/include/llvm/Target/TargetAsmParser.h Wed Jul 14 17:38:02 2010 @@ -49,7 +49,7 @@ /// \param Operands [out] - The list of parsed operands, this returns /// ownership of them to the caller. /// \return True on failure. - virtual bool ParseInstruction(const StringRef &Name, SMLoc NameLoc, + virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc, SmallVectorImpl &Operands) = 0; /// ParseDirective - Parse a target specific assembler directive Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=108366&r1=108365&r2=108366&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Wed Jul 14 17:38:02 2010 @@ -712,7 +712,7 @@ return HadError; } -bool AsmParser::ParseAssignment(const StringRef &Name) { +bool AsmParser::ParseAssignment(StringRef Name) { // FIXME: Use better location, we should use proper tokens. SMLoc EqualLoc = Lexer.getLoc(); Modified: llvm/trunk/lib/Support/APFloat.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/APFloat.cpp?rev=108366&r1=108365&r2=108366&view=diff ============================================================================== --- llvm/trunk/lib/Support/APFloat.cpp (original) +++ llvm/trunk/lib/Support/APFloat.cpp Wed Jul 14 17:38:02 2010 @@ -761,7 +761,7 @@ makeNaN(); } -APFloat::APFloat(const fltSemantics &ourSemantics, const StringRef& text) +APFloat::APFloat(const fltSemantics &ourSemantics, StringRef text) { assertArithmeticOK(ourSemantics); initialize(&ourSemantics); @@ -2185,8 +2185,7 @@ } APFloat::opStatus -APFloat::convertFromHexadecimalString(const StringRef &s, - roundingMode rounding_mode) +APFloat::convertFromHexadecimalString(StringRef s, roundingMode rounding_mode) { lostFraction lost_fraction = lfExactlyZero; integerPart *significand; @@ -2361,7 +2360,7 @@ } APFloat::opStatus -APFloat::convertFromDecimalString(const StringRef &str, roundingMode rounding_mode) +APFloat::convertFromDecimalString(StringRef str, roundingMode rounding_mode) { decimalInfo D; opStatus fs; @@ -2471,7 +2470,7 @@ } APFloat::opStatus -APFloat::convertFromString(const StringRef &str, roundingMode rounding_mode) +APFloat::convertFromString(StringRef str, roundingMode rounding_mode) { assertArithmeticOK(*semantics); assert(!str.empty() && "Invalid string length"); Modified: llvm/trunk/lib/Support/APInt.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/APInt.cpp?rev=108366&r1=108365&r2=108366&view=diff ============================================================================== --- llvm/trunk/lib/Support/APInt.cpp (original) +++ llvm/trunk/lib/Support/APInt.cpp Wed Jul 14 17:38:02 2010 @@ -102,7 +102,7 @@ clearUnusedBits(); } -APInt::APInt(unsigned numbits, const StringRef& Str, uint8_t radix) +APInt::APInt(unsigned numbits, StringRef Str, uint8_t radix) : BitWidth(numbits), VAL(0) { assert(BitWidth && "Bitwidth too small"); fromString(numbits, Str, radix); @@ -613,7 +613,7 @@ return *this; } -unsigned APInt::getBitsNeeded(const StringRef& str, uint8_t radix) { +unsigned APInt::getBitsNeeded(StringRef str, uint8_t radix) { assert(!str.empty() && "Invalid string length"); assert((radix == 10 || radix == 8 || radix == 16 || radix == 2) && "Radix should be 2, 8, 10, or 16!"); @@ -2046,7 +2046,7 @@ divide(LHS, lhsWords, RHS, rhsWords, &Quotient, &Remainder); } -void APInt::fromString(unsigned numbits, const StringRef& str, uint8_t radix) { +void APInt::fromString(unsigned numbits, StringRef str, uint8_t radix) { // Check our assumptions here assert(!str.empty() && "Invalid string length"); assert((radix == 10 || radix == 8 || radix == 16 || radix == 2) && Modified: llvm/trunk/lib/Support/Regex.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Regex.cpp?rev=108366&r1=108365&r2=108366&view=diff ============================================================================== --- llvm/trunk/lib/Support/Regex.cpp (original) +++ llvm/trunk/lib/Support/Regex.cpp Wed Jul 14 17:38:02 2010 @@ -19,7 +19,7 @@ #include using namespace llvm; -Regex::Regex(const StringRef ®ex, unsigned Flags) { +Regex::Regex(StringRef regex, unsigned Flags) { unsigned flags = 0; preg = new llvm_regex(); preg->re_endp = regex.end(); @@ -52,7 +52,7 @@ return preg->re_nsub; } -bool Regex::match(const StringRef &String, SmallVectorImpl *Matches){ +bool Regex::match(StringRef String, SmallVectorImpl *Matches){ unsigned nmatch = Matches ? preg->re_nsub+1 : 0; // pmatch needs to have at least one element. Modified: llvm/trunk/lib/Support/StringPool.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/StringPool.cpp?rev=108366&r1=108365&r2=108366&view=diff ============================================================================== --- llvm/trunk/lib/Support/StringPool.cpp (original) +++ llvm/trunk/lib/Support/StringPool.cpp Wed Jul 14 17:38:02 2010 @@ -22,7 +22,7 @@ assert(InternTable.empty() && "PooledStringPtr leaked!"); } -PooledStringPtr StringPool::intern(const StringRef &Key) { +PooledStringPtr StringPool::intern(StringRef Key) { table_t::iterator I = InternTable.find(Key); if (I != InternTable.end()) return PooledStringPtr(&*I); Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=108366&r1=108365&r2=108366&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Jul 14 17:38:02 2010 @@ -88,7 +88,7 @@ /// its register number, or -1 if there is no match. To allow return values /// to be used directly in register lists, arm registers have values between /// 0 and 15. - int MatchRegisterName(const StringRef &Name); + int MatchRegisterName(StringRef Name); /// } @@ -97,7 +97,7 @@ ARMAsmParser(const Target &T, MCAsmParser &_Parser) : TargetAsmParser(T), Parser(_Parser) {} - virtual bool ParseInstruction(const StringRef &Name, SMLoc NameLoc, + virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc, SmallVectorImpl &Operands); virtual bool ParseDirective(AsmToken DirectiveID); @@ -517,7 +517,7 @@ const AsmToken &Tok = Parser.getTok(); if (Tok.isNot(AsmToken::Identifier)) return true; - const StringRef &ShiftName = Tok.getString(); + StringRef ShiftName = Tok.getString(); if (ShiftName == "lsl" || ShiftName == "LSL") St = Lsl; else if (ShiftName == "lsr" || ShiftName == "LSR") @@ -549,7 +549,7 @@ } /// A hack to allow some testing, to be replaced by a real table gen version. -int ARMAsmParser::MatchRegisterName(const StringRef &Name) { +int ARMAsmParser::MatchRegisterName(StringRef Name) { if (Name == "r0" || Name == "R0") return 0; else if (Name == "r1" || Name == "R1") @@ -593,7 +593,7 @@ MCInst &Inst) { ARMOperand &Op0 = *(ARMOperand*)Operands[0]; assert(Op0.Kind == ARMOperand::Token && "First operand not a Token"); - const StringRef &Mnemonic = Op0.getToken(); + StringRef Mnemonic = Op0.getToken(); if (Mnemonic == "add" || Mnemonic == "stmfd" || Mnemonic == "str" || @@ -658,7 +658,7 @@ } /// Parse an arm instruction mnemonic followed by its operands. -bool ARMAsmParser::ParseInstruction(const StringRef &Name, SMLoc NameLoc, +bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc, SmallVectorImpl &Operands) { OwningPtr Op; ARMOperand::CreateToken(Op, Name, NameLoc); @@ -761,7 +761,7 @@ const AsmToken &Tok = Parser.getTok(); if (Tok.isNot(AsmToken::Identifier)) return Error(L, "unexpected token in .syntax directive"); - const StringRef &Mode = Tok.getString(); + StringRef Mode = Tok.getString(); if (Mode == "unified" || Mode == "UNIFIED") Parser.Lex(); else if (Mode == "divided" || Mode == "DIVIDED") Modified: llvm/trunk/lib/Target/Alpha/AlphaMCAsmInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaMCAsmInfo.cpp?rev=108366&r1=108365&r2=108366&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaMCAsmInfo.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaMCAsmInfo.cpp Wed Jul 14 17:38:02 2010 @@ -14,7 +14,7 @@ #include "AlphaMCAsmInfo.h" using namespace llvm; -AlphaMCAsmInfo::AlphaMCAsmInfo(const Target &T, const StringRef &TT) { +AlphaMCAsmInfo::AlphaMCAsmInfo(const Target &T, StringRef TT) { AlignmentIsInBytes = false; PrivateGlobalPrefix = "$"; GPRel32Directive = ".gprel32"; Modified: llvm/trunk/lib/Target/Alpha/AlphaMCAsmInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaMCAsmInfo.h?rev=108366&r1=108365&r2=108366&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaMCAsmInfo.h (original) +++ llvm/trunk/lib/Target/Alpha/AlphaMCAsmInfo.h Wed Jul 14 17:38:02 2010 @@ -14,14 +14,14 @@ #ifndef ALPHATARGETASMINFO_H #define ALPHATARGETASMINFO_H +#include "llvm/ADT/StringRef.h" #include "llvm/MC/MCAsmInfo.h" namespace llvm { class Target; - class StringRef; struct AlphaMCAsmInfo : public MCAsmInfo { - explicit AlphaMCAsmInfo(const Target &T, const StringRef &TT); + explicit AlphaMCAsmInfo(const Target &T, StringRef TT); }; } // namespace llvm Modified: llvm/trunk/lib/Target/Blackfin/BlackfinMCAsmInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinMCAsmInfo.cpp?rev=108366&r1=108365&r2=108366&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinMCAsmInfo.cpp (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinMCAsmInfo.cpp Wed Jul 14 17:38:02 2010 @@ -15,7 +15,7 @@ using namespace llvm; -BlackfinMCAsmInfo::BlackfinMCAsmInfo(const Target &T, const StringRef &TT) { +BlackfinMCAsmInfo::BlackfinMCAsmInfo(const Target &T, StringRef TT) { GlobalPrefix = "_"; CommentString = "//"; HasSetDirective = false; Modified: llvm/trunk/lib/Target/Blackfin/BlackfinMCAsmInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinMCAsmInfo.h?rev=108366&r1=108365&r2=108366&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinMCAsmInfo.h (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinMCAsmInfo.h Wed Jul 14 17:38:02 2010 @@ -14,14 +14,14 @@ #ifndef BLACKFINTARGETASMINFO_H #define BLACKFINTARGETASMINFO_H +#include "llvm/ADT/StringRef.h" #include "llvm/MC/MCAsmInfo.h" namespace llvm { class Target; - class StringRef; struct BlackfinMCAsmInfo : public MCAsmInfo { - explicit BlackfinMCAsmInfo(const Target &T, const StringRef &TT); + explicit BlackfinMCAsmInfo(const Target &T, StringRef TT); }; } // namespace llvm Modified: llvm/trunk/lib/Target/CellSPU/SPUMCAsmInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUMCAsmInfo.cpp?rev=108366&r1=108365&r2=108366&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUMCAsmInfo.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUMCAsmInfo.cpp Wed Jul 14 17:38:02 2010 @@ -14,7 +14,7 @@ #include "SPUMCAsmInfo.h" using namespace llvm; -SPULinuxMCAsmInfo::SPULinuxMCAsmInfo(const Target &T, const StringRef &TT) { +SPULinuxMCAsmInfo::SPULinuxMCAsmInfo(const Target &T, StringRef TT) { ZeroDirective = "\t.space\t"; Data64bitsDirective = "\t.quad\t"; AlignmentIsInBytes = false; Modified: llvm/trunk/lib/Target/CellSPU/SPUMCAsmInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUMCAsmInfo.h?rev=108366&r1=108365&r2=108366&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUMCAsmInfo.h (original) +++ llvm/trunk/lib/Target/CellSPU/SPUMCAsmInfo.h Wed Jul 14 17:38:02 2010 @@ -14,14 +14,14 @@ #ifndef SPUTARGETASMINFO_H #define SPUTARGETASMINFO_H +#include "llvm/ADT/StringRef.h" #include "llvm/MC/MCAsmInfo.h" namespace llvm { class Target; - class StringRef; struct SPULinuxMCAsmInfo : public MCAsmInfo { - explicit SPULinuxMCAsmInfo(const Target &T, const StringRef &TT); + explicit SPULinuxMCAsmInfo(const Target &T, StringRef TT); }; } // namespace llvm Modified: llvm/trunk/lib/Target/MBlaze/MBlazeMCAsmInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeMCAsmInfo.cpp?rev=108366&r1=108365&r2=108366&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeMCAsmInfo.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeMCAsmInfo.cpp Wed Jul 14 17:38:02 2010 @@ -14,7 +14,7 @@ #include "MBlazeMCAsmInfo.h" using namespace llvm; -MBlazeMCAsmInfo::MBlazeMCAsmInfo(const Target &T, const StringRef &TT) { +MBlazeMCAsmInfo::MBlazeMCAsmInfo(const Target &T, StringRef TT) { AlignmentIsInBytes = false; Data16bitsDirective = "\t.half\t"; Data32bitsDirective = "\t.word\t"; Modified: llvm/trunk/lib/Target/MBlaze/MBlazeMCAsmInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeMCAsmInfo.h?rev=108366&r1=108365&r2=108366&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeMCAsmInfo.h (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeMCAsmInfo.h Wed Jul 14 17:38:02 2010 @@ -14,15 +14,15 @@ #ifndef MBLAZETARGETASMINFO_H #define MBLAZETARGETASMINFO_H +#include "llvm/ADT/StringRef.h" #include "llvm/MC/MCAsmInfo.h" namespace llvm { class Target; - class StringRef; class MBlazeMCAsmInfo : public MCAsmInfo { public: - explicit MBlazeMCAsmInfo(const Target &T, const StringRef &TT); + explicit MBlazeMCAsmInfo(const Target &T, StringRef TT); }; } // namespace llvm Modified: llvm/trunk/lib/Target/MSIL/MSILWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSIL/MSILWriter.cpp?rev=108366&r1=108365&r2=108366&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSIL/MSILWriter.cpp (original) +++ llvm/trunk/lib/Target/MSIL/MSILWriter.cpp Wed Jul 14 17:38:02 2010 @@ -1621,8 +1621,7 @@ } -const char* MSILWriter::getLibraryForSymbol(const StringRef &Name, - bool isFunction, +const char* MSILWriter::getLibraryForSymbol(StringRef Name, bool isFunction, CallingConv::ID CallingConv) { // TODO: Read *.def file with function and libraries definitions. return "MSVCRT.DLL"; Modified: llvm/trunk/lib/Target/MSIL/MSILWriter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSIL/MSILWriter.h?rev=108366&r1=108365&r2=108366&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSIL/MSILWriter.h (original) +++ llvm/trunk/lib/Target/MSIL/MSILWriter.h Wed Jul 14 17:38:02 2010 @@ -246,7 +246,7 @@ const char* getLibraryName(const GlobalVariable* GV); - const char* getLibraryForSymbol(const StringRef &Name, bool isFunction, + const char* getLibraryForSymbol(StringRef Name, bool isFunction, CallingConv::ID CallingConv); void printExternals(); Modified: llvm/trunk/lib/Target/MSP430/MSP430MCAsmInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430MCAsmInfo.cpp?rev=108366&r1=108365&r2=108366&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430MCAsmInfo.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MSP430MCAsmInfo.cpp Wed Jul 14 17:38:02 2010 @@ -14,7 +14,7 @@ #include "MSP430MCAsmInfo.h" using namespace llvm; -MSP430MCAsmInfo::MSP430MCAsmInfo(const Target &T, const StringRef &TT) { +MSP430MCAsmInfo::MSP430MCAsmInfo(const Target &T, StringRef TT) { PrivateGlobalPrefix = ".L"; WeakRefDirective ="\t.weak\t"; PCSymbol="."; Modified: llvm/trunk/lib/Target/MSP430/MSP430MCAsmInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430MCAsmInfo.h?rev=108366&r1=108365&r2=108366&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430MCAsmInfo.h (original) +++ llvm/trunk/lib/Target/MSP430/MSP430MCAsmInfo.h Wed Jul 14 17:38:02 2010 @@ -14,13 +14,14 @@ #ifndef MSP430TARGETASMINFO_H #define MSP430TARGETASMINFO_H +#include "llvm/ADT/StringRef.h" #include "llvm/MC/MCAsmInfo.h" namespace llvm { class Target; - class StringRef; + struct MSP430MCAsmInfo : public MCAsmInfo { - explicit MSP430MCAsmInfo(const Target &T, const StringRef &TT); + explicit MSP430MCAsmInfo(const Target &T, StringRef TT); }; } // namespace llvm Modified: llvm/trunk/lib/Target/Mips/MipsMCAsmInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMCAsmInfo.cpp?rev=108366&r1=108365&r2=108366&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsMCAsmInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsMCAsmInfo.cpp Wed Jul 14 17:38:02 2010 @@ -14,7 +14,7 @@ #include "MipsMCAsmInfo.h" using namespace llvm; -MipsMCAsmInfo::MipsMCAsmInfo(const Target &T, const StringRef &TT) { +MipsMCAsmInfo::MipsMCAsmInfo(const Target &T, StringRef TT) { AlignmentIsInBytes = false; Data16bitsDirective = "\t.half\t"; Data32bitsDirective = "\t.word\t"; Modified: llvm/trunk/lib/Target/Mips/MipsMCAsmInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMCAsmInfo.h?rev=108366&r1=108365&r2=108366&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsMCAsmInfo.h (original) +++ llvm/trunk/lib/Target/Mips/MipsMCAsmInfo.h Wed Jul 14 17:38:02 2010 @@ -14,15 +14,15 @@ #ifndef MIPSTARGETASMINFO_H #define MIPSTARGETASMINFO_H +#include "llvm/ADT/StringRef.h" #include "llvm/MC/MCAsmInfo.h" namespace llvm { class Target; - class StringRef; class MipsMCAsmInfo : public MCAsmInfo { public: - explicit MipsMCAsmInfo(const Target &T, const StringRef &TT); + explicit MipsMCAsmInfo(const Target &T, StringRef TT); }; } // namespace llvm Modified: llvm/trunk/lib/Target/PIC16/PIC16MCAsmInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16MCAsmInfo.cpp?rev=108366&r1=108365&r2=108366&view=diff ============================================================================== --- llvm/trunk/lib/Target/PIC16/PIC16MCAsmInfo.cpp (original) +++ llvm/trunk/lib/Target/PIC16/PIC16MCAsmInfo.cpp Wed Jul 14 17:38:02 2010 @@ -20,7 +20,7 @@ #include "PIC16ISelLowering.h" using namespace llvm; -PIC16MCAsmInfo::PIC16MCAsmInfo(const Target &T, const StringRef &TT) { +PIC16MCAsmInfo::PIC16MCAsmInfo(const Target &T, StringRef TT) { CommentString = ";"; GlobalPrefix = PAN::getTagName(PAN::PREFIX_SYMBOL); GlobalDirective = "\tglobal\t"; Modified: llvm/trunk/lib/Target/PIC16/PIC16MCAsmInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16MCAsmInfo.h?rev=108366&r1=108365&r2=108366&view=diff ============================================================================== --- llvm/trunk/lib/Target/PIC16/PIC16MCAsmInfo.h (original) +++ llvm/trunk/lib/Target/PIC16/PIC16MCAsmInfo.h Wed Jul 14 17:38:02 2010 @@ -25,7 +25,7 @@ const char *RomData16bitsDirective; const char *RomData32bitsDirective; public: - PIC16MCAsmInfo(const Target &T, const StringRef &TT); + PIC16MCAsmInfo(const Target &T, StringRef TT); virtual const char *getDataASDirective(unsigned size, unsigned AS) const; }; Modified: llvm/trunk/lib/Target/Sparc/SparcMCAsmInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcMCAsmInfo.cpp?rev=108366&r1=108365&r2=108366&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcMCAsmInfo.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcMCAsmInfo.cpp Wed Jul 14 17:38:02 2010 @@ -12,10 +12,9 @@ //===----------------------------------------------------------------------===// #include "SparcMCAsmInfo.h" -#include "llvm/ADT/SmallVector.h" using namespace llvm; -SparcELFMCAsmInfo::SparcELFMCAsmInfo(const Target &T, const StringRef &TT) { +SparcELFMCAsmInfo::SparcELFMCAsmInfo(const Target &T, StringRef TT) { Data16bitsDirective = "\t.half\t"; Data32bitsDirective = "\t.word\t"; Data64bitsDirective = 0; // .xword is only supported by V9. Modified: llvm/trunk/lib/Target/Sparc/SparcMCAsmInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcMCAsmInfo.h?rev=108366&r1=108365&r2=108366&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcMCAsmInfo.h (original) +++ llvm/trunk/lib/Target/Sparc/SparcMCAsmInfo.h Wed Jul 14 17:38:02 2010 @@ -14,13 +14,14 @@ #ifndef SPARCTARGETASMINFO_H #define SPARCTARGETASMINFO_H +#include "llvm/ADT/StringRef.h" #include "llvm/MC/MCAsmInfo.h" namespace llvm { class Target; - class StringRef; + struct SparcELFMCAsmInfo : public MCAsmInfo { - explicit SparcELFMCAsmInfo(const Target &T, const StringRef &TT); + explicit SparcELFMCAsmInfo(const Target &T, StringRef TT); }; } // namespace llvm Modified: llvm/trunk/lib/Target/SystemZ/SystemZMCAsmInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZMCAsmInfo.cpp?rev=108366&r1=108365&r2=108366&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZMCAsmInfo.cpp (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZMCAsmInfo.cpp Wed Jul 14 17:38:02 2010 @@ -16,7 +16,7 @@ #include "llvm/MC/MCSectionELF.h" using namespace llvm; -SystemZMCAsmInfo::SystemZMCAsmInfo(const Target &T, const StringRef &TT) { +SystemZMCAsmInfo::SystemZMCAsmInfo(const Target &T, StringRef TT) { PrivateGlobalPrefix = ".L"; WeakRefDirective = "\t.weak\t"; PCSymbol = "."; Modified: llvm/trunk/lib/Target/SystemZ/SystemZMCAsmInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZMCAsmInfo.h?rev=108366&r1=108365&r2=108366&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZMCAsmInfo.h (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZMCAsmInfo.h Wed Jul 14 17:38:02 2010 @@ -21,7 +21,7 @@ class StringRef; struct SystemZMCAsmInfo : public MCAsmInfo { - explicit SystemZMCAsmInfo(const Target &T, const StringRef &TT); + explicit SystemZMCAsmInfo(const Target &T, StringRef TT); virtual const MCSection *getNonexecutableStackSection(MCContext &Ctx) const; }; Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=108366&r1=108365&r2=108366&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Wed Jul 14 17:38:02 2010 @@ -65,7 +65,7 @@ X86ATTAsmParser(const Target &T, MCAsmParser &_Parser) : TargetAsmParser(T), Parser(_Parser) {} - virtual bool ParseInstruction(const StringRef &Name, SMLoc NameLoc, + virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc, SmallVectorImpl &Operands); virtual bool ParseDirective(AsmToken DirectiveID); @@ -602,7 +602,7 @@ } bool X86ATTAsmParser:: -ParseInstruction(const StringRef &Name, SMLoc NameLoc, +ParseInstruction(StringRef Name, SMLoc NameLoc, SmallVectorImpl &Operands) { // The various flavors of pushf and popf use Requires and // Requires, but the assembler doesn't yet implement that. Modified: llvm/trunk/lib/Target/XCore/XCoreMCAsmInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreMCAsmInfo.cpp?rev=108366&r1=108365&r2=108366&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreMCAsmInfo.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreMCAsmInfo.cpp Wed Jul 14 17:38:02 2010 @@ -10,7 +10,7 @@ #include "XCoreMCAsmInfo.h" using namespace llvm; -XCoreMCAsmInfo::XCoreMCAsmInfo(const Target &T, const StringRef &TT) { +XCoreMCAsmInfo::XCoreMCAsmInfo(const Target &T, StringRef TT) { SupportsDebugInformation = true; Data16bitsDirective = "\t.short\t"; Data32bitsDirective = "\t.long\t"; Modified: llvm/trunk/lib/Target/XCore/XCoreMCAsmInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreMCAsmInfo.h?rev=108366&r1=108365&r2=108366&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreMCAsmInfo.h (original) +++ llvm/trunk/lib/Target/XCore/XCoreMCAsmInfo.h Wed Jul 14 17:38:02 2010 @@ -14,14 +14,15 @@ #ifndef XCORETARGETASMINFO_H #define XCORETARGETASMINFO_H +#include "llvm/ADT/StringRef.h" #include "llvm/MC/MCAsmInfo.h" namespace llvm { class Target; - class StringRef; + class XCoreMCAsmInfo : public MCAsmInfo { public: - explicit XCoreMCAsmInfo(const Target &T, const StringRef &TT); + explicit XCoreMCAsmInfo(const Target &T, StringRef TT); }; } // namespace llvm Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=108366&r1=108365&r2=108366&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/AsmWriter.cpp (original) +++ llvm/trunk/lib/VMCore/AsmWriter.cpp Wed Jul 14 17:38:02 2010 @@ -90,8 +90,7 @@ /// PrintLLVMName - Turn the specified name into an 'LLVM name', which is either /// prefixed with % (if the string only contains simple characters) or is /// surrounded with ""'s (if it has special chars in it). Print it out. -static void PrintLLVMName(raw_ostream &OS, const StringRef &Name, - PrefixType Prefix) { +static void PrintLLVMName(raw_ostream &OS, StringRef Name, PrefixType Prefix) { assert(Name.data() && "Cannot get empty name!"); switch (Prefix) { default: llvm_unreachable("Bad prefix!"); From bob.wilson at apple.com Wed Jul 14 17:41:51 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Wed, 14 Jul 2010 22:41:51 -0000 Subject: [llvm-commits] [llvm] r108367 - in /llvm/trunk/tools: Makefile edis/Makefile Message-ID: <20100714224151.38A132A6C12C@llvm.org> Author: bwilson Date: Wed Jul 14 17:41:51 2010 New Revision: 108367 URL: http://llvm.org/viewvc/llvm-project?rev=108367&view=rev Log: Remove some broken code to check the DISABLE_EDIS flag (edis is now in the DIRS list, so it does no good to filter it from PARALLEL_DIRS), and replace it with a check to disable building the shared library version of edis when the flag is set. Disabling it entirely does not work because MC uses it now. Modified: llvm/trunk/tools/Makefile llvm/trunk/tools/edis/Makefile Modified: llvm/trunk/tools/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/Makefile?rev=108367&r1=108366&r2=108367&view=diff ============================================================================== --- llvm/trunk/tools/Makefile (original) +++ llvm/trunk/tools/Makefile Wed Jul 14 17:41:51 2010 @@ -49,9 +49,4 @@ endif endif -# Don't build edis if we explicitly disabled it. -ifeq ($(DISABLE_EDIS),1) - PARALLEL_DIRS := $(filter-out edis, $(PARALLEL_DIRS)) -endif - include $(LEVEL)/Makefile.common Modified: llvm/trunk/tools/edis/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/edis/Makefile?rev=108367&r1=108366&r2=108367&view=diff ============================================================================== --- llvm/trunk/tools/edis/Makefile (original) +++ llvm/trunk/tools/edis/Makefile Wed Jul 14 17:41:51 2010 @@ -20,10 +20,12 @@ include $(LEVEL)/Makefile.config ifeq ($(ENABLE_PIC),1) + ifneq ($(DISABLE_EDIS),1) ifneq ($(TARGET_OS), $(filter $(TARGET_OS), Cygwin MingW)) LINK_LIBS_IN_SHARED = 1 SHARED_LIBRARY = 1 endif + endif endif LINK_COMPONENTS := $(TARGETS_TO_BUILD) x86asmprinter x86disassembler From sabre at nondot.org Wed Jul 14 18:04:59 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 14 Jul 2010 23:04:59 -0000 Subject: [llvm-commits] [llvm] r108368 - /llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp Message-ID: <20100714230459.8A3A12A6C12C@llvm.org> Author: lattner Date: Wed Jul 14 18:04:59 2010 New Revision: 108368 URL: http://llvm.org/viewvc/llvm-project?rev=108368&view=rev Log: fix indentation Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp?rev=108368&r1=108367&r2=108368&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp Wed Jul 14 18:04:59 2010 @@ -154,15 +154,13 @@ case X86II::MO_TLVP: RefKind = MCSymbolRefExpr::VK_TLVP; break; case X86II::MO_TLVP_PIC_BASE: - Expr = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx); - // Subtract the pic base. - Expr - = MCBinaryExpr::CreateSub(Expr, - MCSymbolRefExpr::Create(GetPICBaseSymbol(), - Ctx), - Ctx); - - break; + Expr = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx); + // Subtract the pic base. + Expr = MCBinaryExpr::CreateSub(Expr, + MCSymbolRefExpr::Create(GetPICBaseSymbol(), + Ctx), + Ctx); + break; case X86II::MO_TLSGD: RefKind = MCSymbolRefExpr::VK_TLSGD; break; case X86II::MO_GOTTPOFF: RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break; case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break; From gohman at apple.com Wed Jul 14 18:08:16 2010 From: gohman at apple.com (Dan Gohman) Date: Wed, 14 Jul 2010 23:08:16 -0000 Subject: [llvm-commits] [llvm] r108369 - in /llvm/trunk: include/llvm/CodeGen/MachineModuleInfo.h lib/CodeGen/MachineModuleInfo.cpp Message-ID: <20100714230816.C305B2A6C12C@llvm.org> Author: djg Date: Wed Jul 14 18:08:16 2010 New Revision: 108369 URL: http://llvm.org/viewvc/llvm-project?rev=108369&view=rev Log: Make the order in which variables are described in debug information independent of the order that isel happens to visit the dbg_declare intrinsics. This fixes a bug in which the formal arguments were being printed in reverse order, now that fast isel is going bottom up. Modified: llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp Modified: llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h?rev=108369&r1=108368&r2=108369&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h Wed Jul 14 18:08:16 2010 @@ -344,7 +344,7 @@ VariableDbgInfo.push_back(std::make_pair(N, std::make_pair(Slot, Loc))); } - VariableDbgInfoMapTy &getVariableDbgInfo() { return VariableDbgInfo; } + VariableDbgInfoMapTy &getVariableDbgInfo(); }; // End class MachineModuleInfo Modified: llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp?rev=108369&r1=108368&r2=108369&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp Wed Jul 14 18:08:16 2010 @@ -563,3 +563,26 @@ return 0; } +namespace { + /// VariableDebugSorter - Comparison to sort the VariableDbgInfo map + /// by source location, to avoid depending on the arbitrary order that + /// instruction selection visits variables in. + struct VariableDebugSorter { + bool operator()(const MachineModuleInfo::VariableDbgInfoMapTy::value_type &A, + const MachineModuleInfo::VariableDbgInfoMapTy::value_type &B) + const { + if (A.second.second.getLine() != B.second.second.getLine()) + return A.second.second.getLine() < B.second.second.getLine(); + if (A.second.second.getCol() != B.second.second.getCol()) + return A.second.second.getCol() < B.second.second.getCol(); + return false; + } + }; +} + +MachineModuleInfo::VariableDbgInfoMapTy & +MachineModuleInfo::getVariableDbgInfo() { + std::stable_sort(VariableDbgInfo.begin(), VariableDbgInfo.end(), + VariableDebugSorter()); + return VariableDbgInfo; +} From dpatel at apple.com Wed Jul 14 18:12:52 2010 From: dpatel at apple.com (Devang Patel) Date: Wed, 14 Jul 2010 23:12:52 -0000 Subject: [llvm-commits] [llvm] r108370 - in /llvm/trunk/test: CodeGen/X86/2010-06-28-DbgEntryPC.ll FrontendC/2010-06-28-DbgEntryPC.c Message-ID: <20100714231252.A51582A6C12C@llvm.org> Author: dpatel Date: Wed Jul 14 18:12:52 2010 New Revision: 108370 URL: http://llvm.org/viewvc/llvm-project?rev=108370&view=rev Log: Make it a .ll test case. Added: llvm/trunk/test/CodeGen/X86/2010-06-28-DbgEntryPC.ll Removed: llvm/trunk/test/FrontendC/2010-06-28-DbgEntryPC.c Added: llvm/trunk/test/CodeGen/X86/2010-06-28-DbgEntryPC.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-06-28-DbgEntryPC.ll?rev=108370&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2010-06-28-DbgEntryPC.ll (added) +++ llvm/trunk/test/CodeGen/X86/2010-06-28-DbgEntryPC.ll Wed Jul 14 18:12:52 2010 @@ -0,0 +1,108 @@ +; RUN: llc -O2 -mtriple=i386-apple-darwin <%s | FileCheck %s +; Use DW_FORM_addr for DW_AT_entry_pc. +; Radar 8094785 + +; CHECK: .byte 17 ## DW_TAG_compile_unit +; CHECK-NEXT: .byte 1 ## DW_CHILDREN_yes +; CHECK-NEXT: .byte 37 ## DW_AT_producer +; CHECK-NEXT: .byte 8 ## DW_FORM_string +; CHECK-NEXT: .byte 19 ## DW_AT_language +; CHECK-NEXT: .byte 11 ## DW_FORM_data1 +; CHECK-NEXT: .byte 3 ## DW_AT_name +; CHECK-NEXT: .byte 8 ## DW_FORM_string +; CHECK-NEXT: .byte 82 ## DW_AT_entry_pc +; CHECK-NEXT: .byte 1 ## DW_FORM_addr +; CHECK-NEXT: .byte 16 ## DW_AT_stmt_list +; CHECK-NEXT: .byte 6 ## DW_FORM_data4 +; CHECK-NEXT: .byte 27 ## DW_AT_comp_dir +; CHECK-NEXT: .byte 8 ## DW_FORM_string +; CHECK-NEXT: .byte 225 ## DW_AT_APPLE_optimized + +%struct.a = type { i32, %struct.a* } + + at ret = common global i32 0 ; [#uses=2] + +define void @foo(i32 %x) nounwind noinline ssp { +entry: + tail call void @llvm.dbg.value(metadata !{i32 %x}, i64 0, metadata !21), !dbg !28 + store i32 %x, i32* @ret, align 4, !dbg !29 + ret void, !dbg !31 +} + +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone + +define i8* @bar(%struct.a* %b) nounwind noinline ssp { +entry: + tail call void @llvm.dbg.value(metadata !{%struct.a* %b}, i64 0, metadata !22), !dbg !32 + %0 = getelementptr inbounds %struct.a* %b, i64 0, i32 0, !dbg !33 ; [#uses=1] + %1 = load i32* %0, align 8, !dbg !33 ; [#uses=1] + tail call void @foo(i32 %1) nounwind noinline ssp, !dbg !33 + %2 = bitcast %struct.a* %b to i8*, !dbg !35 ; [#uses=1] + ret i8* %2, !dbg !35 +} + +define i32 @main(i32 %argc, i8** nocapture %argv) nounwind ssp { +entry: + %e = alloca %struct.a, align 8 ; <%struct.a*> [#uses=4] + call void @llvm.dbg.value(metadata !{i32 %argc}, i64 0, metadata !23), !dbg !36 + call void @llvm.dbg.value(metadata !{i8** %argv}, i64 0, metadata !24), !dbg !36 + call void @llvm.dbg.declare(metadata !{%struct.a* %e}, metadata !25), !dbg !37 + %0 = getelementptr inbounds %struct.a* %e, i64 0, i32 0, !dbg !38 ; [#uses=1] + store i32 4, i32* %0, align 8, !dbg !38 + %1 = getelementptr inbounds %struct.a* %e, i64 0, i32 1, !dbg !39 ; <%struct.a**> [#uses=1] + store %struct.a* %e, %struct.a** %1, align 8, !dbg !39 + %2 = call i8* @bar(%struct.a* %e) nounwind noinline ssp, !dbg !40 ; [#uses=0] + %3 = load i32* @ret, align 4, !dbg !41 ; [#uses=1] + ret i32 %3, !dbg !41 +} + +!llvm.dbg.sp = !{!0, !6, !15} +!llvm.dbg.lv.foo = !{!21} +!llvm.dbg.lv.bar = !{!22} +!llvm.dbg.lv.main = !{!23, !24, !25} +!llvm.dbg.gv = !{!27} + +!0 = metadata !{i32 524334, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"foo", metadata !1, i32 34, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, void (i32)* @foo} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 524329, metadata !"2010-06-28-DbgEntryPC.c", metadata !"/Users/yash/clean/llvm/test/FrontendC", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 524305, i32 0, i32 1, metadata !"2010-06-28-DbgEntryPC.c", metadata !"/Users/yash/clean/llvm/test/FrontendC", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{null, metadata !5} +!5 = metadata !{i32 524324, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 524334, i32 0, metadata !1, metadata !"bar", metadata !"bar", metadata !"bar", metadata !1, i32 38, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, i8* (%struct.a*)* @bar} ; [ DW_TAG_subprogram ] +!7 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, null} ; [ DW_TAG_subroutine_type ] +!8 = metadata !{metadata !9, metadata !10} +!9 = metadata !{i32 524303, metadata !1, metadata !"", metadata !1, i32 0, i64 64, i64 64, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ] +!10 = metadata !{i32 524303, metadata !1, metadata !"", metadata !1, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !11} ; [ DW_TAG_pointer_type ] +!11 = metadata !{i32 524307, metadata !1, metadata !"a", metadata !1, i32 23, i64 128, i64 64, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_structure_type ] +!12 = metadata !{metadata !13, metadata !14} +!13 = metadata !{i32 524301, metadata !11, metadata !"c", metadata !1, i32 24, i64 32, i64 32, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] +!14 = metadata !{i32 524301, metadata !11, metadata !"d", metadata !1, i32 25, i64 64, i64 64, i64 64, i32 0, metadata !10} ; [ DW_TAG_member ] +!15 = metadata !{i32 524334, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"main", metadata !1, i32 43, metadata !16, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, i32 (i32, i8**)* @main} ; [ DW_TAG_subprogram ] +!16 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !17, i32 0, null} ; [ DW_TAG_subroutine_type ] +!17 = metadata !{metadata !5, metadata !5, metadata !18} +!18 = metadata !{i32 524303, metadata !1, metadata !"", metadata !1, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !19} ; [ DW_TAG_pointer_type ] +!19 = metadata !{i32 524303, metadata !1, metadata !"", metadata !1, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !20} ; [ DW_TAG_pointer_type ] +!20 = metadata !{i32 524324, metadata !1, metadata !"char", metadata !1, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] +!21 = metadata !{i32 524545, metadata !0, metadata !"x", metadata !1, i32 33, metadata !5} ; [ DW_TAG_arg_variable ] +!22 = metadata !{i32 524545, metadata !6, metadata !"b", metadata !1, i32 38, metadata !10} ; [ DW_TAG_arg_variable ] +!23 = metadata !{i32 524545, metadata !15, metadata !"argc", metadata !1, i32 43, metadata !5} ; [ DW_TAG_arg_variable ] +!24 = metadata !{i32 524545, metadata !15, metadata !"argv", metadata !1, i32 43, metadata !18} ; [ DW_TAG_arg_variable ] +!25 = metadata !{i32 524544, metadata !26, metadata !"e", metadata !1, i32 44, metadata !11} ; [ DW_TAG_auto_variable ] +!26 = metadata !{i32 524299, metadata !15, i32 43, i32 0} ; [ DW_TAG_lexical_block ] +!27 = metadata !{i32 524340, i32 0, metadata !1, metadata !"ret", metadata !"ret", metadata !"", metadata !1, i32 28, metadata !5, i1 false, i1 true, i32* @ret} ; [ DW_TAG_variable ] +!28 = metadata !{i32 33, i32 0, metadata !0, null} +!29 = metadata !{i32 35, i32 0, metadata !30, null} +!30 = metadata !{i32 524299, metadata !0, i32 34, i32 0} ; [ DW_TAG_lexical_block ] +!31 = metadata !{i32 36, i32 0, metadata !30, null} +!32 = metadata !{i32 38, i32 0, metadata !6, null} +!33 = metadata !{i32 39, i32 0, metadata !34, null} +!34 = metadata !{i32 524299, metadata !6, i32 38, i32 0} ; [ DW_TAG_lexical_block ] +!35 = metadata !{i32 40, i32 0, metadata !34, null} +!36 = metadata !{i32 43, i32 0, metadata !15, null} +!37 = metadata !{i32 44, i32 0, metadata !26, null} +!38 = metadata !{i32 45, i32 0, metadata !26, null} +!39 = metadata !{i32 46, i32 0, metadata !26, null} +!40 = metadata !{i32 48, i32 0, metadata !26, null} +!41 = metadata !{i32 49, i32 0, metadata !26, null} Removed: llvm/trunk/test/FrontendC/2010-06-28-DbgEntryPC.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/2010-06-28-DbgEntryPC.c?rev=108369&view=auto ============================================================================== --- llvm/trunk/test/FrontendC/2010-06-28-DbgEntryPC.c (original) +++ llvm/trunk/test/FrontendC/2010-06-28-DbgEntryPC.c (removed) @@ -1,50 +0,0 @@ -// RUN: %llvmgcc -S -O2 -g %s -o - | llc -O2 -mtriple=i386-apple-darwin | FileCheck %s -// Use DW_FORM_addr for DW_AT_entry_pc. -// Radar 8094785 - -// XFAIL: * -// XTARGET: x86,i386,i686 -// CHECK: .byte 17 ## DW_TAG_compile_unit -// CHECK-NEXT: .byte 1 ## DW_CHILDREN_yes -// CHECK-NEXT: .byte 37 ## DW_AT_producer -// CHECK-NEXT: .byte 8 ## DW_FORM_string -// CHECK-NEXT: .byte 19 ## DW_AT_language -// CHECK-NEXT: .byte 11 ## DW_FORM_data1 -// CHECK-NEXT: .byte 3 ## DW_AT_name -// CHECK-NEXT: .byte 8 ## DW_FORM_string -// CHECK-NEXT: .byte 82 ## DW_AT_entry_pc -// CHECK-NEXT: .byte 1 ## DW_FORM_addr -// CHECK-NEXT: .byte 16 ## DW_AT_stmt_list -// CHECK-NEXT: .byte 6 ## DW_FORM_data4 -// CHECK-NEXT: .byte 27 ## DW_AT_comp_dir -// CHECK-NEXT: .byte 8 ## DW_FORM_string -// CHECK-NEXT: .byte 225 ## DW_AT_APPLE_optimized - -struct a { - int c; - struct a *d; -}; - -int ret; - -void foo(int x) __attribute__((noinline)); -void *bar(struct a *b) __attribute__((noinline)); - -void foo(int x) -{ - ret = x; -} - -void *bar(struct a *b) { - foo(b->c); - return b; -} - -int main(int argc, char *argv[]) { - struct a e; - e.c = 4; - e.d = &e; - - (void)bar(&e); - return ret; -} From echristo at apple.com Wed Jul 14 18:12:58 2010 From: echristo at apple.com (Eric Christopher) Date: Wed, 14 Jul 2010 23:12:58 -0000 Subject: [llvm-commits] [llvm] r108371 - /llvm/trunk/test/FrontendC/vla-1.c Message-ID: <20100714231258.9923E2A6C12D@llvm.org> Author: echristo Date: Wed Jul 14 18:12:58 2010 New Revision: 108371 URL: http://llvm.org/viewvc/llvm-project?rev=108371&view=rev Log: Temporarily disable this test. Modified: llvm/trunk/test/FrontendC/vla-1.c Modified: llvm/trunk/test/FrontendC/vla-1.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/vla-1.c?rev=108371&r1=108370&r2=108371&view=diff ============================================================================== --- llvm/trunk/test/FrontendC/vla-1.c (original) +++ llvm/trunk/test/FrontendC/vla-1.c Wed Jul 14 18:12:58 2010 @@ -1,4 +1,5 @@ -// RUN: %llvmgcc -std=gnu99 %s -S |& grep {error: "is greater than the stack alignment" } +// RUN: true +// %llvmgcc -std=gnu99 %s -S |& grep {error: "is greater than the stack alignment" } int foo(int a) { From wdietz2 at illinois.edu Wed Jul 14 18:15:19 2010 From: wdietz2 at illinois.edu (Will Dietz) Date: Wed, 14 Jul 2010 23:15:19 -0000 Subject: [llvm-commits] [poolalloc] r108373 - /poolalloc/trunk/lib/DSA/DSTest.cpp Message-ID: <20100714231519.758E32A6C12C@llvm.org> Author: wdietz2 Date: Wed Jul 14 18:15:19 2010 New Revision: 108373 URL: http://llvm.org/viewvc/llvm-project?rev=108373&view=rev Log: Refactor the stripping of offsets in DSTest. Support offsets off of globals. Modified: poolalloc/trunk/lib/DSA/DSTest.cpp Modified: poolalloc/trunk/lib/DSA/DSTest.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DSTest.cpp?rev=108373&r1=108372&r2=108373&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/DSTest.cpp (original) +++ poolalloc/trunk/lib/DSA/DSTest.cpp Wed Jul 14 18:15:19 2010 @@ -75,7 +75,7 @@ DSNodeHandle NH; // String version (that we were given) - StringRef serialized; + std::string serialized; // Parsed list of offsets typedef SmallVector OffsetVectorTy; @@ -109,45 +109,70 @@ } } + /// stripOffsets -- strips the offsets + /// Walks backwards, stripping offsets. + /// Returns serialized without the offsets + /// + std::string stripOffsets() { + std::vector offsets_reversed; + SmallVector colonSeparated; + StringRef serializedRef = serialized; + serializedRef.split(colonSeparated,":"); + SmallVector::reverse_iterator I = colonSeparated.rbegin(), + E = colonSeparated.rend(); + for(; I != E; ++I ) { + unsigned offset; + // If this isn't an integer (offset), then bail + if (I->getAsInteger(0,offset)) + break; + offsets_reversed.push_back(offset); + } + // Okay so we built reversed list of offsets, now put things back together + + // If we have more than 2 values left, then we have something like: + // name1:name2:name3[:offset]*, which is no good. + // Also, if we have *nothing* left, something is similarly wrong. + int stringsLeft = E - I; + assert((stringsLeft > 0) && "Node was entirely made of offsets?"); + assert((stringsLeft <= 2) && "Too many colons! (Invalid node/offset given)"); + + // Now rebuild the string, without the offsets. + std::string rebuilt = I++->str(); + for(; I != E; ++I) { + rebuilt = I->str() + ":" + rebuilt; + } + + // Reverse the offsets (since we parsed backwards) and put the result + // into the 'offsets' vector for use elsewhere. + offsets.insert(offsets.begin(), + offsets_reversed.rbegin(),offsets_reversed.rend()); + + return rebuilt; + } + + /// parseValue -- sets value for the string we were constructed on, /// using the provided module as the context to find the value void parseValue(const Module *M) { - unsigned count = serialized.count(':'); + // Parse the offsets, and remove from the string + StringRef stripped = stripOffsets(); + + unsigned count = stripped.count(':'); if (count == 0) { // Global case // format: "[@]value" - StringRef globalName = stripAtIfRequired(serialized); + StringRef globalName = stripAtIfRequired(stripped); V = M->getNamedValue(globalName); assert(V && "Unable to find specified global!"); - } else { // count >= 1 + } else if (count == 1) { // Function-specific case // format: "[@]func:value" - // format: "[@]func:value:offset0:offset1:offset2" - std::pair split = serialized.split(':'); + std::pair split = stripped.split(':'); StringRef func = stripAtIfRequired(split.first); StringRef value = split.second; - if (count > 1) { - //If we have more semicolons, split them off to get the value and offsets - std::pair tmp = value.split(':'); - value = tmp.first; - StringRef offStrings = tmp.second; - - //Small detour--parse offsets into vector - unsigned offset; - while(offStrings.count(':') > 0) { - tmp = offStrings.split(':'); - assert(!tmp.first.getAsInteger(0,offset) && "failed to parse offset!"); - offsets.push_back(offset); - offStrings = tmp.second; - } - assert(!offStrings.getAsInteger(0,offset) && "failed to parse offset!"); - offsets.push_back(offset); - } - // Now back to your regularly scheduled programming... - // First, find the function F = M->getFunction(func); assert(F && "Unable to find function specified!"); @@ -159,6 +184,8 @@ assert(V && "Unable to find value in specified function!"); + } else { + assert(0 && "Too many colons, offsets not stripped?"); } assert(V && "Parsing value failed!"); @@ -241,9 +268,12 @@ // Go through all the types, and just dump them. // FIXME: Lifted from Printer.cpp, probably should be shared + bool firstType = true; if (N->type_begin() != N->type_end()) for (DSNode::TyMapTy::const_iterator ii = N->type_begin(), ee = N->type_end(); ii != ee; ++ii) { + if (!firstType) O << " "; + firstType = false; O << ii->first << ": "; if (ii->second) { bool first = true; @@ -256,7 +286,6 @@ } else O << "VOID"; - O << " "; } else O << "VOID"; From wdietz2 at illinois.edu Wed Jul 14 18:16:35 2010 From: wdietz2 at illinois.edu (Will Dietz) Date: Wed, 14 Jul 2010 23:16:35 -0000 Subject: [llvm-commits] [poolalloc] r108374 - in /poolalloc/trunk/test/dsa/var_arg: basic_32.ll basic_64.ll va_copy_32.ll va_copy_64.ll Message-ID: <20100714231635.AB79C2A6C12C@llvm.org> Author: wdietz2 Date: Wed Jul 14 18:16:35 2010 New Revision: 108374 URL: http://llvm.org/viewvc/llvm-project?rev=108374&view=rev Log: Added 32/64-bit var_arg ll tests to more cleanly verify var-args behavior. Added: poolalloc/trunk/test/dsa/var_arg/basic_32.ll poolalloc/trunk/test/dsa/var_arg/basic_64.ll poolalloc/trunk/test/dsa/var_arg/va_copy_32.ll poolalloc/trunk/test/dsa/var_arg/va_copy_64.ll Added: poolalloc/trunk/test/dsa/var_arg/basic_32.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/var_arg/basic_32.ll?rev=108374&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/var_arg/basic_32.ll (added) +++ poolalloc/trunk/test/dsa/var_arg/basic_32.ll Wed Jul 14 18:16:35 2010 @@ -0,0 +1,82 @@ +; ModuleID = 'basic.c' +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32" +target triple = "i386-unknown-linux-gnu" +; Verify all the passes run on this +;RUN: dsaopt %s -dsa-local -disable-output +;RUN: dsaopt %s -dsa-bu -disable-output +;RUN: dsaopt %s -dsa-td -disable-output +;RUN: dsaopt %s -dsa-eq -disable-output +;=== Local Tests === +; Verify VAStart flag +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "get:ap+V" +; Don't propagate the VAStart flag to children... +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "get:ap:0-V" +; On 32-bit, VAStart node should point to an array of the arguments +;RUN: dsaopt %s -dsa-local -analyze -print-only-types \ +;RUN: -print-node-for-value "get:ap:0" | grep -i array | grep -i folded | grep -i void +; And the argument node should be of the proper type (in this case an i32) +;RUN: dsaopt %s -dsa-local -analyze -print-only-types \ +;RUN: -print-node-for-value "get:ap:0:0" | grep {^0: i32$} +; The argument should be ref'd, but not mod'd +;RUN: dsaopt %s -dsa-local -analyze --verify-flags "get:ap:0:0+R-M" + +define internal i32 @get(i32 %unused, ...) nounwind { +entry: + %unused_addr = alloca i32 ; [#uses=1] + %retval = alloca i32 ; [#uses=2] + %0 = alloca i32 ; [#uses=2] + %ap.0 = alloca i8* ; [#uses=3] + %ap = alloca i8* ; [#uses=4] + %val = alloca i32* ; [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store i32 %unused, i32* %unused_addr + %ap1 = bitcast i8** %ap to i8* ; [#uses=1] + call void @llvm.va_start(i8* %ap1) + %1 = load i8** %ap, align 4 ; [#uses=1] + store i8* %1, i8** %ap.0, align 4 + %2 = load i8** %ap.0, align 4 ; [#uses=1] + %3 = getelementptr inbounds i8* %2, i64 4 ; [#uses=1] + store i8* %3, i8** %ap, align 4 + %4 = load i8** %ap.0, align 4 ; [#uses=1] + %5 = bitcast i8* %4 to i32** ; [#uses=1] + %6 = load i32** %5, align 4 ; [#uses=1] + store i32* %6, i32** %val, align 4 + %ap2 = bitcast i8** %ap to i8* ; [#uses=1] + call void @llvm.va_end(i8* %ap2) + %7 = load i32** %val, align 4 ; [#uses=1] + %8 = load i32* %7, align 4 ; [#uses=1] + store i32 %8, i32* %0, align 4 + %9 = load i32* %0, align 4 ; [#uses=1] + store i32 %9, i32* %retval, align 4 + br label %return + +return: ; preds = %entry + %retval3 = load i32* %retval ; [#uses=1] + ret i32 %retval3 +} + +declare void @llvm.va_start(i8*) nounwind + +declare void @llvm.va_end(i8*) nounwind + +define i32 @main() nounwind { +entry: + %retval = alloca i32 ; [#uses=2] + %0 = alloca i32 ; [#uses=2] + %stack_val = alloca i32 ; [#uses=2] + %ret = alloca i32 ; [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store i32 5, i32* %stack_val, align 4 + %1 = call i32 (i32, ...)* @get(i32 0, i32* %stack_val) nounwind ; [#uses=1] + store i32 %1, i32* %ret, align 4 + %2 = load i32* %ret, align 4 ; [#uses=1] + %3 = sub nsw i32 %2, 5 ; [#uses=1] + store i32 %3, i32* %0, align 4 + %4 = load i32* %0, align 4 ; [#uses=1] + store i32 %4, i32* %retval, align 4 + br label %return + +return: ; preds = %entry + %retval1 = load i32* %retval ; [#uses=1] + ret i32 %retval1 +} Added: poolalloc/trunk/test/dsa/var_arg/basic_64.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/var_arg/basic_64.ll?rev=108374&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/var_arg/basic_64.ll (added) +++ poolalloc/trunk/test/dsa/var_arg/basic_64.ll Wed Jul 14 18:16:35 2010 @@ -0,0 +1,126 @@ +; ModuleID = 'basic.c' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" +; Verify all the passes run on this +;RUN: dsaopt %s -dsa-local -disable-output +;RUN: dsaopt %s -dsa-bu -disable-output +;RUN: dsaopt %s -dsa-td -disable-output +;RUN: dsaopt %s -dsa-eq -disable-output +;=== Local Tests === +; Verify VAStart flag +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "get:ap+V" +; Don't propagate the VAStart flag to children... +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "get:ap:8-V" +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "get:ap:16-V" +; On 64-bit, VAStart node should be a struct pointing to an array of the arguments +;RUN: dsaopt %s -dsa-local -analyze -print-only-types \ +;RUN: -print-node-for-value "get:ap:8" | grep -i array | grep -i folded | grep -i void +; Both offsets 8 and 16 point to the array as a simplification. +; Verify that these are indeed the same node. +;RUN: dsaopt %s -dsa-local -analyze -check-same-node \ +;RUN: "get:ap:8,get:ap:16" +; And the argument node should be of the proper type (in this case an i32) +;RUN: dsaopt %s -dsa-local -analyze -print-only-types \ +;RUN: -print-node-for-value "get:ap:8:0" | grep {^0: i32$} +; The argument should be ref'd, but not mod'd +;RUN: dsaopt %s -dsa-local -analyze --verify-flags "get:ap:8:0+R-M" + +%struct.__va_list_tag = type { i32, i32, i8*, i8* } + +define internal i32 @get(i32 %unused, ...) nounwind { +entry: + %unused_addr = alloca i32 ; [#uses=1] + %retval = alloca i32 ; [#uses=2] + %0 = alloca i32 ; [#uses=2] + %addr.0 = alloca i8* ; [#uses=3] + %ap = alloca [1 x %struct.__va_list_tag] ; <[1 x %struct.__va_list_tag]*> [#uses=9] + %val = alloca i32* ; [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store i32 %unused, i32* %unused_addr + %ap1 = bitcast [1 x %struct.__va_list_tag]* %ap to %struct.__va_list_tag* ; <%struct.__va_list_tag*> [#uses=1] + %ap12 = bitcast %struct.__va_list_tag* %ap1 to i8* ; [#uses=1] + call void @llvm.va_start(i8* %ap12) + %1 = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0 ; <%struct.__va_list_tag*> [#uses=1] + %2 = getelementptr inbounds %struct.__va_list_tag* %1, i32 0, i32 0 ; [#uses=1] + %3 = load i32* %2, align 8 ; [#uses=1] + %4 = icmp uge i32 %3, 48 ; [#uses=1] + br i1 %4, label %bb3, label %bb + +bb: ; preds = %entry + %5 = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0 ; <%struct.__va_list_tag*> [#uses=1] + %6 = getelementptr inbounds %struct.__va_list_tag* %5, i32 0, i32 3 ; [#uses=1] + %7 = load i8** %6, align 8 ; [#uses=1] + %8 = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0 ; <%struct.__va_list_tag*> [#uses=1] + %9 = getelementptr inbounds %struct.__va_list_tag* %8, i32 0, i32 0 ; [#uses=1] + %10 = load i32* %9, align 8 ; [#uses=1] + %11 = inttoptr i32 %10 to i8* ; [#uses=1] + %12 = ptrtoint i8* %7 to i64 ; [#uses=1] + %13 = ptrtoint i8* %11 to i64 ; [#uses=1] + %14 = add i64 %12, %13 ; [#uses=1] + %15 = inttoptr i64 %14 to i8* ; [#uses=1] + store i8* %15, i8** %addr.0, align 8 + %16 = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0 ; <%struct.__va_list_tag*> [#uses=1] + %17 = getelementptr inbounds %struct.__va_list_tag* %16, i32 0, i32 0 ; [#uses=1] + %18 = load i32* %17, align 8 ; [#uses=1] + %19 = add i32 %18, 8 ; [#uses=1] + %20 = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0 ; <%struct.__va_list_tag*> [#uses=1] + %21 = getelementptr inbounds %struct.__va_list_tag* %20, i32 0, i32 0 ; [#uses=1] + store i32 %19, i32* %21, align 8 + br label %bb4 + +bb3: ; preds = %entry + %22 = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0 ; <%struct.__va_list_tag*> [#uses=1] + %23 = getelementptr inbounds %struct.__va_list_tag* %22, i32 0, i32 2 ; [#uses=1] + %24 = load i8** %23, align 8 ; [#uses=2] + store i8* %24, i8** %addr.0, align 8 + %25 = getelementptr inbounds i8* %24, i64 8 ; [#uses=1] + %26 = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0 ; <%struct.__va_list_tag*> [#uses=1] + %27 = getelementptr inbounds %struct.__va_list_tag* %26, i32 0, i32 2 ; [#uses=1] + store i8* %25, i8** %27, align 8 + br label %bb4 + +bb4: ; preds = %bb3, %bb + %28 = load i8** %addr.0, align 8 ; [#uses=1] + %29 = bitcast i8* %28 to i32** ; [#uses=1] + %30 = load i32** %29, align 8 ; [#uses=1] + store i32* %30, i32** %val, align 8 + %ap5 = bitcast [1 x %struct.__va_list_tag]* %ap to %struct.__va_list_tag* ; <%struct.__va_list_tag*> [#uses=1] + %ap56 = bitcast %struct.__va_list_tag* %ap5 to i8* ; [#uses=1] + call void @llvm.va_end(i8* %ap56) + %31 = load i32** %val, align 8 ; [#uses=1] + %32 = load i32* %31, align 4 ; [#uses=1] + store i32 %32, i32* %0, align 4 + %33 = load i32* %0, align 4 ; [#uses=1] + store i32 %33, i32* %retval, align 4 + br label %return + +return: ; preds = %bb4 + %retval7 = load i32* %retval ; [#uses=1] + ret i32 %retval7 +} + +declare void @llvm.va_start(i8*) nounwind + +declare void @llvm.va_end(i8*) nounwind + +define i32 @main() nounwind { +entry: + %retval = alloca i32 ; [#uses=2] + %0 = alloca i32 ; [#uses=2] + %stack_val = alloca i32 ; [#uses=2] + %ret = alloca i32 ; [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store i32 5, i32* %stack_val, align 4 + %1 = call i32 (i32, ...)* @get(i32 0, i32* %stack_val) nounwind ; [#uses=1] + store i32 %1, i32* %ret, align 4 + %2 = load i32* %ret, align 4 ; [#uses=1] + %3 = sub nsw i32 %2, 5 ; [#uses=1] + store i32 %3, i32* %0, align 4 + %4 = load i32* %0, align 4 ; [#uses=1] + store i32 %4, i32* %retval, align 4 + br label %return + +return: ; preds = %entry + %retval1 = load i32* %retval ; [#uses=1] + ret i32 %retval1 +} Added: poolalloc/trunk/test/dsa/var_arg/va_copy_32.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/var_arg/va_copy_32.ll?rev=108374&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/var_arg/va_copy_32.ll (added) +++ poolalloc/trunk/test/dsa/var_arg/va_copy_32.ll Wed Jul 14 18:16:35 2010 @@ -0,0 +1,97 @@ +; ModuleID = 'va_copy.c' +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32" +target triple = "i386-unknown-linux-gnu" +; Verify all the passes run on this +;RUN: dsaopt %s -dsa-local -disable-output +;RUN: dsaopt %s -dsa-bu -disable-output +;RUN: dsaopt %s -dsa-td -disable-output +;RUN: dsaopt %s -dsa-eq -disable-output +; Verify that val1 and val2 are merged +;RUN: dsaopt %s -dsa-local -analyze -check-same-node "val1:0,val2:0" + + + at val1 = common global i32* null ; [#uses=2] + at val2 = common global i32* null ; [#uses=2] + +define internal i32 @get(i32 %unused, ...) nounwind { +entry: + %unused_addr = alloca i32 ; [#uses=1] + %retval = alloca i32 ; [#uses=2] + %0 = alloca i32 ; [#uses=2] + %ap_copy.3 = alloca i8* ; [#uses=3] + %ap.1 = alloca i8* ; [#uses=3] + %ap = alloca i8* ; [#uses=5] + %ap_copy = alloca i8* ; [#uses=4] + %memtmp = alloca i8* ; [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store i32 %unused, i32* %unused_addr + %ap1 = bitcast i8** %ap to i8* ; [#uses=1] + call void @llvm.va_start(i8* %ap1) + %1 = load i8** %ap, align 4 ; [#uses=1] + store i8* %1, i8** %memtmp + %ap_copy2 = bitcast i8** %ap_copy to i8* ; [#uses=1] + %memtmp3 = bitcast i8** %memtmp to i8* ; [#uses=1] + call void @llvm.va_copy(i8* %ap_copy2, i8* %memtmp3) + %2 = load i8** %ap, align 4 ; [#uses=1] + store i8* %2, i8** %ap.1, align 4 + %3 = load i8** %ap.1, align 4 ; [#uses=1] + %4 = getelementptr inbounds i8* %3, i64 4 ; [#uses=1] + store i8* %4, i8** %ap, align 4 + %5 = load i8** %ap.1, align 4 ; [#uses=1] + %6 = bitcast i8* %5 to i32** ; [#uses=1] + %7 = load i32** %6, align 4 ; [#uses=1] + store i32* %7, i32** @val1, align 4 + %ap4 = bitcast i8** %ap to i8* ; [#uses=1] + call void @llvm.va_end(i8* %ap4) + %8 = load i8** %ap_copy, align 4 ; [#uses=1] + store i8* %8, i8** %ap_copy.3, align 4 + %9 = load i8** %ap_copy.3, align 4 ; [#uses=1] + %10 = getelementptr inbounds i8* %9, i64 4 ; [#uses=1] + store i8* %10, i8** %ap_copy, align 4 + %11 = load i8** %ap_copy.3, align 4 ; [#uses=1] + %12 = bitcast i8* %11 to i32** ; [#uses=1] + %13 = load i32** %12, align 4 ; [#uses=1] + store i32* %13, i32** @val2, align 4 + %ap_copy5 = bitcast i8** %ap_copy to i8* ; [#uses=1] + call void @llvm.va_end(i8* %ap_copy5) + %14 = load i32** @val1, align 4 ; [#uses=1] + %15 = load i32* %14, align 4 ; [#uses=1] + %16 = load i32** @val2, align 4 ; [#uses=1] + %17 = load i32* %16, align 4 ; [#uses=1] + %18 = sub nsw i32 %15, %17 ; [#uses=1] + store i32 %18, i32* %0, align 4 + %19 = load i32* %0, align 4 ; [#uses=1] + store i32 %19, i32* %retval, align 4 + br label %return + +return: ; preds = %entry + %retval6 = load i32* %retval ; [#uses=1] + ret i32 %retval6 +} + +declare void @llvm.va_start(i8*) nounwind + +declare void @llvm.va_copy(i8*, i8*) nounwind + +declare void @llvm.va_end(i8*) nounwind + +define i32 @main() nounwind { +entry: + %retval = alloca i32 ; [#uses=2] + %0 = alloca i32 ; [#uses=2] + %stack_val = alloca i32 ; [#uses=2] + %ret = alloca i32 ; [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store i32 5, i32* %stack_val, align 4 + %1 = call i32 (i32, ...)* @get(i32 0, i32* %stack_val) nounwind ; [#uses=1] + store i32 %1, i32* %ret, align 4 + %2 = load i32* %ret, align 4 ; [#uses=1] + store i32 %2, i32* %0, align 4 + %3 = load i32* %0, align 4 ; [#uses=1] + store i32 %3, i32* %retval, align 4 + br label %return + +return: ; preds = %entry + %retval1 = load i32* %retval ; [#uses=1] + ret i32 %retval1 +} Added: poolalloc/trunk/test/dsa/var_arg/va_copy_64.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/var_arg/va_copy_64.ll?rev=108374&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/var_arg/va_copy_64.ll (added) +++ poolalloc/trunk/test/dsa/var_arg/va_copy_64.ll Wed Jul 14 18:16:35 2010 @@ -0,0 +1,170 @@ +; ModuleID = 'va_copy.c' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" +; Verify all the passes run on this +;RUN: dsaopt %s -dsa-local -disable-output +;RUN: dsaopt %s -dsa-bu -disable-output +;RUN: dsaopt %s -dsa-td -disable-output +;RUN: dsaopt %s -dsa-eq -disable-output +; Verify that val1 and val2 are merged +;RUN: dsaopt %s -dsa-local -analyze -check-same-node "val1:0,val2:0" + +%struct.__va_list_tag = type { i32, i32, i8*, i8* } + + at val1 = common global i32* null ; [#uses=2] + at val2 = common global i32* null ; [#uses=2] + +define internal i32 @get(i32 %unused, ...) nounwind { +entry: + %unused_addr = alloca i32 ; [#uses=1] + %retval = alloca i32 ; [#uses=2] + %0 = alloca i32 ; [#uses=2] + %addr.2 = alloca i8* ; [#uses=3] + %addr.0 = alloca i8* ; [#uses=3] + %ap = alloca [1 x %struct.__va_list_tag] ; <[1 x %struct.__va_list_tag]*> [#uses=10] + %ap_copy = alloca [1 x %struct.__va_list_tag] ; <[1 x %struct.__va_list_tag]*> [#uses=9] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store i32 %unused, i32* %unused_addr + %ap1 = bitcast [1 x %struct.__va_list_tag]* %ap to %struct.__va_list_tag* ; <%struct.__va_list_tag*> [#uses=1] + %ap12 = bitcast %struct.__va_list_tag* %ap1 to i8* ; [#uses=1] + call void @llvm.va_start(i8* %ap12) + %ap_copy3 = bitcast [1 x %struct.__va_list_tag]* %ap_copy to %struct.__va_list_tag* ; <%struct.__va_list_tag*> [#uses=1] + %ap4 = bitcast [1 x %struct.__va_list_tag]* %ap to %struct.__va_list_tag* ; <%struct.__va_list_tag*> [#uses=1] + %ap_copy35 = bitcast %struct.__va_list_tag* %ap_copy3 to i8* ; [#uses=1] + %ap46 = bitcast %struct.__va_list_tag* %ap4 to i8* ; [#uses=1] + call void @llvm.va_copy(i8* %ap_copy35, i8* %ap46) + %1 = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0 ; <%struct.__va_list_tag*> [#uses=1] + %2 = getelementptr inbounds %struct.__va_list_tag* %1, i32 0, i32 0 ; [#uses=1] + %3 = load i32* %2, align 8 ; [#uses=1] + %4 = icmp uge i32 %3, 48 ; [#uses=1] + br i1 %4, label %bb7, label %bb + +bb: ; preds = %entry + %5 = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0 ; <%struct.__va_list_tag*> [#uses=1] + %6 = getelementptr inbounds %struct.__va_list_tag* %5, i32 0, i32 3 ; [#uses=1] + %7 = load i8** %6, align 8 ; [#uses=1] + %8 = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0 ; <%struct.__va_list_tag*> [#uses=1] + %9 = getelementptr inbounds %struct.__va_list_tag* %8, i32 0, i32 0 ; [#uses=1] + %10 = load i32* %9, align 8 ; [#uses=1] + %11 = inttoptr i32 %10 to i8* ; [#uses=1] + %12 = ptrtoint i8* %7 to i64 ; [#uses=1] + %13 = ptrtoint i8* %11 to i64 ; [#uses=1] + %14 = add i64 %12, %13 ; [#uses=1] + %15 = inttoptr i64 %14 to i8* ; [#uses=1] + store i8* %15, i8** %addr.0, align 8 + %16 = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0 ; <%struct.__va_list_tag*> [#uses=1] + %17 = getelementptr inbounds %struct.__va_list_tag* %16, i32 0, i32 0 ; [#uses=1] + %18 = load i32* %17, align 8 ; [#uses=1] + %19 = add i32 %18, 8 ; [#uses=1] + %20 = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0 ; <%struct.__va_list_tag*> [#uses=1] + %21 = getelementptr inbounds %struct.__va_list_tag* %20, i32 0, i32 0 ; [#uses=1] + store i32 %19, i32* %21, align 8 + br label %bb8 + +bb7: ; preds = %entry + %22 = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0 ; <%struct.__va_list_tag*> [#uses=1] + %23 = getelementptr inbounds %struct.__va_list_tag* %22, i32 0, i32 2 ; [#uses=1] + %24 = load i8** %23, align 8 ; [#uses=2] + store i8* %24, i8** %addr.0, align 8 + %25 = getelementptr inbounds i8* %24, i64 8 ; [#uses=1] + %26 = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap, i64 0, i64 0 ; <%struct.__va_list_tag*> [#uses=1] + %27 = getelementptr inbounds %struct.__va_list_tag* %26, i32 0, i32 2 ; [#uses=1] + store i8* %25, i8** %27, align 8 + br label %bb8 + +bb8: ; preds = %bb7, %bb + %28 = load i8** %addr.0, align 8 ; [#uses=1] + %29 = bitcast i8* %28 to i32** ; [#uses=1] + %30 = load i32** %29, align 8 ; [#uses=1] + store i32* %30, i32** @val1, align 8 + %ap9 = bitcast [1 x %struct.__va_list_tag]* %ap to %struct.__va_list_tag* ; <%struct.__va_list_tag*> [#uses=1] + %ap910 = bitcast %struct.__va_list_tag* %ap9 to i8* ; [#uses=1] + call void @llvm.va_end(i8* %ap910) + %31 = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap_copy, i64 0, i64 0 ; <%struct.__va_list_tag*> [#uses=1] + %32 = getelementptr inbounds %struct.__va_list_tag* %31, i32 0, i32 0 ; [#uses=1] + %33 = load i32* %32, align 8 ; [#uses=1] + %34 = icmp uge i32 %33, 48 ; [#uses=1] + br i1 %34, label %bb12, label %bb11 + +bb11: ; preds = %bb8 + %35 = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap_copy, i64 0, i64 0 ; <%struct.__va_list_tag*> [#uses=1] + %36 = getelementptr inbounds %struct.__va_list_tag* %35, i32 0, i32 3 ; [#uses=1] + %37 = load i8** %36, align 8 ; [#uses=1] + %38 = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap_copy, i64 0, i64 0 ; <%struct.__va_list_tag*> [#uses=1] + %39 = getelementptr inbounds %struct.__va_list_tag* %38, i32 0, i32 0 ; [#uses=1] + %40 = load i32* %39, align 8 ; [#uses=1] + %41 = inttoptr i32 %40 to i8* ; [#uses=1] + %42 = ptrtoint i8* %37 to i64 ; [#uses=1] + %43 = ptrtoint i8* %41 to i64 ; [#uses=1] + %44 = add i64 %42, %43 ; [#uses=1] + %45 = inttoptr i64 %44 to i8* ; [#uses=1] + store i8* %45, i8** %addr.2, align 8 + %46 = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap_copy, i64 0, i64 0 ; <%struct.__va_list_tag*> [#uses=1] + %47 = getelementptr inbounds %struct.__va_list_tag* %46, i32 0, i32 0 ; [#uses=1] + %48 = load i32* %47, align 8 ; [#uses=1] + %49 = add i32 %48, 8 ; [#uses=1] + %50 = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap_copy, i64 0, i64 0 ; <%struct.__va_list_tag*> [#uses=1] + %51 = getelementptr inbounds %struct.__va_list_tag* %50, i32 0, i32 0 ; [#uses=1] + store i32 %49, i32* %51, align 8 + br label %bb13 + +bb12: ; preds = %bb8 + %52 = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap_copy, i64 0, i64 0 ; <%struct.__va_list_tag*> [#uses=1] + %53 = getelementptr inbounds %struct.__va_list_tag* %52, i32 0, i32 2 ; [#uses=1] + %54 = load i8** %53, align 8 ; [#uses=2] + store i8* %54, i8** %addr.2, align 8 + %55 = getelementptr inbounds i8* %54, i64 8 ; [#uses=1] + %56 = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap_copy, i64 0, i64 0 ; <%struct.__va_list_tag*> [#uses=1] + %57 = getelementptr inbounds %struct.__va_list_tag* %56, i32 0, i32 2 ; [#uses=1] + store i8* %55, i8** %57, align 8 + br label %bb13 + +bb13: ; preds = %bb12, %bb11 + %58 = load i8** %addr.2, align 8 ; [#uses=1] + %59 = bitcast i8* %58 to i32** ; [#uses=1] + %60 = load i32** %59, align 8 ; [#uses=1] + store i32* %60, i32** @val2, align 8 + %ap_copy14 = bitcast [1 x %struct.__va_list_tag]* %ap_copy to %struct.__va_list_tag* ; <%struct.__va_list_tag*> [#uses=1] + %ap_copy1415 = bitcast %struct.__va_list_tag* %ap_copy14 to i8* ; [#uses=1] + call void @llvm.va_end(i8* %ap_copy1415) + %61 = load i32** @val1, align 8 ; [#uses=1] + %62 = load i32* %61, align 4 ; [#uses=1] + %63 = load i32** @val2, align 8 ; [#uses=1] + %64 = load i32* %63, align 4 ; [#uses=1] + %65 = sub nsw i32 %62, %64 ; [#uses=1] + store i32 %65, i32* %0, align 4 + %66 = load i32* %0, align 4 ; [#uses=1] + store i32 %66, i32* %retval, align 4 + br label %return + +return: ; preds = %bb13 + %retval16 = load i32* %retval ; [#uses=1] + ret i32 %retval16 +} + +declare void @llvm.va_start(i8*) nounwind + +declare void @llvm.va_copy(i8*, i8*) nounwind + +declare void @llvm.va_end(i8*) nounwind + +define i32 @main() nounwind { +entry: + %retval = alloca i32 ; [#uses=2] + %0 = alloca i32 ; [#uses=2] + %stack_val = alloca i32 ; [#uses=2] + %ret = alloca i32 ; [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store i32 5, i32* %stack_val, align 4 + %1 = call i32 (i32, ...)* @get(i32 0, i32* %stack_val) nounwind ; [#uses=1] + store i32 %1, i32* %ret, align 4 + %2 = load i32* %ret, align 4 ; [#uses=1] + store i32 %2, i32* %0, align 4 + %3 = load i32* %0, align 4 ; [#uses=1] + store i32 %3, i32* %retval, align 4 + br label %return + +return: ; preds = %entry + %retval1 = load i32* %retval ; [#uses=1] + ret i32 %retval1 +} From resistor at mac.com Wed Jul 14 18:33:51 2010 From: resistor at mac.com (Owen Anderson) Date: Wed, 14 Jul 2010 23:33:51 -0000 Subject: [llvm-commits] [llvm] r108378 - in /llvm/trunk/lib/Transforms/InstCombine: InstCombineAndOrXor.cpp InstCombineSelect.cpp Message-ID: <20100714233351.814D82A6C12C@llvm.org> Author: resistor Date: Wed Jul 14 18:33:51 2010 New Revision: 108378 URL: http://llvm.org/viewvc/llvm-project?rev=108378&view=rev Log: Add instcombine transforms to optimize tests of multiple bits of the same value into a single larger comparison. Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp?rev=108378&r1=108377&r2=108378&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp Wed Jul 14 18:33:51 2010 @@ -472,6 +472,24 @@ Value *NewOr = Builder->CreateOr(Val, Val2); return Builder->CreateICmp(LHSCC, NewOr, LHSCst); } + + // (icmp ne (A & C1) 0) & (icmp ne (A & C2), 0) --> + // (icmp eq (A & (C1|C2)), (C1|C2)) + if (LHSCC == ICmpInst::ICMP_NE && LHSCst->isZero()) { + Instruction *I1 = dyn_cast(Val); + Instruction *I2 = dyn_cast(Val2); + if (I1 && I1->getOpcode() == Instruction::And && + I2 && I2->getOpcode() == Instruction::And && + I1->getOperand(0) == I1->getOperand(0)) { + ConstantInt *CI1 = dyn_cast(I1->getOperand(1)); + ConstantInt *CI2 = dyn_cast(I2->getOperand(1)); + if (CI1 && CI2) { + Constant *ConstOr = ConstantExpr::getOr(CI1, CI2); + Value *NewAnd = Builder->CreateAnd(I1->getOperand(0), ConstOr); + return Builder->CreateICmp(ICmpInst::ICMP_EQ, NewAnd, ConstOr); + } + } + } } // From here on, we only handle: Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp?rev=108378&r1=108377&r2=108378&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp Wed Jul 14 18:33:51 2010 @@ -699,6 +699,31 @@ SI.setOperand(2, TrueVal); return &SI; } + + // select (or (A == 0) (B == 0)) T, F--> select (and (A != 0) (B != 0)) F, T + // Note: This is a canonicalization rather than an optimization, and is used + // to expose opportunities to other instcombine transforms. + Instruction* CondInst = dyn_cast(CondVal); + if (CondInst && CondInst->getOpcode() == Instruction::Or) { + ICmpInst *LHSCmp = dyn_cast(CondInst->getOperand(0)); + ICmpInst *RHSCmp = dyn_cast(CondInst->getOperand(1)); + if (LHSCmp && LHSCmp->getPredicate() == ICmpInst::ICMP_EQ && + RHSCmp && RHSCmp->getPredicate() == ICmpInst::ICMP_EQ) { + ConstantInt* C1 = dyn_cast(LHSCmp->getOperand(1)); + ConstantInt* C2 = dyn_cast(RHSCmp->getOperand(1)); + if (C1 && C1->isZero() && C2 && C2->isZero()) { + LHSCmp->setPredicate(ICmpInst::ICMP_NE); + RHSCmp->setPredicate(ICmpInst::ICMP_NE); + Value *And = + InsertNewInstBefore(BinaryOperator::CreateAnd(LHSCmp, RHSCmp, + "and."+CondVal->getName()), SI); + SI.setOperand(0, And); + SI.setOperand(1, FalseVal); + SI.setOperand(2, TrueVal); + return &SI; + } + } + } return 0; } From echristo at apple.com Wed Jul 14 18:41:32 2010 From: echristo at apple.com (Eric Christopher) Date: Wed, 14 Jul 2010 23:41:32 -0000 Subject: [llvm-commits] [llvm] r108381 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Message-ID: <20100714234132.358A32A6C12C@llvm.org> Author: echristo Date: Wed Jul 14 18:41:32 2010 New Revision: 108381 URL: http://llvm.org/viewvc/llvm-project?rev=108381&view=rev Log: 80-col. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=108381&r1=108380&r2=108381&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Wed Jul 14 18:41:32 2010 @@ -820,7 +820,7 @@ unsigned InReg = It->second; RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType()); SDValue Chain = DAG.getEntryNode(); - return N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL); + return N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain,NULL); } // Otherwise create a new SDValue and remember it. @@ -3955,7 +3955,8 @@ if (AA->alias(I.getArgOperand(0), Size, I.getArgOperand(1), Size) == AliasAnalysis::NoAlias) { DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, - false, I.getArgOperand(0), 0, I.getArgOperand(1), 0)); + false, I.getArgOperand(0), 0, + I.getArgOperand(1), 0)); return 0; } From bob.wilson at apple.com Wed Jul 14 18:41:59 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Wed, 14 Jul 2010 23:41:59 -0000 Subject: [llvm-commits] [llvm] r108382 - in /llvm/trunk/utils/buildit: GNUmakefile build_llvm Message-ID: <20100714234159.112EC2A6C12C@llvm.org> Author: bwilson Date: Wed Jul 14 18:41:58 2010 New Revision: 108382 URL: http://llvm.org/viewvc/llvm-project?rev=108382&view=rev Log: Try to get embedded build of llvmCore to pass verification. Simplify some things in the process. Modified: llvm/trunk/utils/buildit/GNUmakefile llvm/trunk/utils/buildit/build_llvm Modified: llvm/trunk/utils/buildit/GNUmakefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/buildit/GNUmakefile?rev=108382&r1=108381&r2=108382&view=diff ============================================================================== --- llvm/trunk/utils/buildit/GNUmakefile (original) +++ llvm/trunk/utils/buildit/GNUmakefile Wed Jul 14 18:41:58 2010 @@ -32,7 +32,7 @@ ####################################################################### -PREFIX = /usr/local +PREFIX = /Developer/usr/local # Unless assertions are forced on in the GMAKE command line, disable them. ifndef ENABLE_ASSERTIONS @@ -70,7 +70,7 @@ $(RC_ProjectSourceVersion) $(RC_ProjectSourceSubversion) EmbeddedHosted: - $(MAKE) ARM_HOSTED_BUILD=yes install + $(MAKE) ARM_HOSTED_BUILD=yes PREFIX=/usr install # installhdrs does nothing, because the headers aren't useful until # the compiler is installed. Modified: llvm/trunk/utils/buildit/build_llvm URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/buildit/build_llvm?rev=108382&r1=108381&r2=108382&view=diff ============================================================================== --- llvm/trunk/utils/buildit/build_llvm (original) +++ llvm/trunk/utils/buildit/build_llvm Wed Jul 14 18:41:58 2010 @@ -63,15 +63,6 @@ DARWIN_VERS=`uname -r | sed 's/\..*//'` echo DARWIN_VERS = $DARWIN_VERS -DEVELOPER_DIR="${DEVELOPER_DIR-Developer}" -if [ "$ARM_HOSTED_BUILD" = yes ]; then - DT_HOME="$DEST_DIR/usr" -else - DT_HOME="$DEST_DIR/$DEVELOPER_DIR/usr" -fi - -DEST_ROOT="/$DEVELOPER_DIR$DEST_ROOT" - ################################################################################ # Run the build. @@ -131,16 +122,14 @@ fi if [ "$ARM_HOSTED_BUILD" = yes ]; then - configure_prefix=$DT_HOME configure_opts="--enable-targets=arm --host=arm-apple-darwin10 \ --target=arm-apple-darwin10 --build=i686-apple-darwin10" else - configure_prefix=$DT_HOME/local configure_opts="--enable-targets=arm,x86,powerpc,cbe" fi if [ \! -f Makefile.config ]; then - $SRC_DIR/configure --prefix=$configure_prefix $configure_opts \ + $SRC_DIR/configure --prefix=$DEST_DIR$DEST_ROOT $configure_opts \ --enable-assertions=$LLVM_ASSERTIONS \ --enable-optimized=$LLVM_OPTIMIZED \ --disable-bindings \ @@ -254,7 +243,7 @@ fi # Copy over the tblgen utility. -cp `find $DIR -name tblgen` $DT_HOME/local/bin +cp `find $DIR -name tblgen` $DEST_DIR$DEST_ROOT/bin # Remove .dir files cd $DEST_DIR$DEST_ROOT @@ -274,7 +263,7 @@ fi # The Hello dylib is an example of how to build a pass. No need to install it. -rm $DEST_DIR$DEST_ROOT/lib/libLLVMHello.dylib +rm $DEST_DIR$DEST_ROOT/lib/LLVMHello.dylib # Compress manpages MDIR=$DEST_DIR$DEST_ROOT/share/man/man1 @@ -324,12 +313,15 @@ cd $DEST_DIR$DEST_ROOT if [ "$INSTALL_LIBLTO" = "yes" ]; then + DT_HOME="$DEST_DIR/Developer/usr" mkdir -p $DT_HOME/lib mv lib/libLTO.dylib $DT_HOME/lib/libLTO.dylib # Use '-l' to strip i386 modules. N.B. that flag doesn't work with kext or # PPC objects! strip -arch all -Sl $DT_HOME/lib/libLTO.dylib +else + rm -f lib/libLTO.dylib fi rm -f lib/libLTO.a lib/libLTO.la @@ -363,7 +355,7 @@ if [ "$INSTALL_LIBLTO" = "yes" ]; then mkdir -p $DEST_DIR/usr/lib/ cd $DEST_DIR/usr/lib && \ - ln -s ../../$DEVELOPER_DIR/usr/lib/libLTO.dylib ./libLTO.dylib + ln -s ../../Developer/usr/lib/libLTO.dylib ./libLTO.dylib fi ################################################################################ From eli.friedman at gmail.com Wed Jul 14 18:47:26 2010 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 14 Jul 2010 16:47:26 -0700 Subject: [llvm-commits] [llvm] r108378 - in /llvm/trunk/lib/Transforms/InstCombine: InstCombineAndOrXor.cpp InstCombineSelect.cpp In-Reply-To: <20100714233351.814D82A6C12C@llvm.org> References: <20100714233351.814D82A6C12C@llvm.org> Message-ID: On Wed, Jul 14, 2010 at 4:33 PM, Owen Anderson wrote: > Author: resistor > Date: Wed Jul 14 18:33:51 2010 > New Revision: 108378 > > URL: http://llvm.org/viewvc/llvm-project?rev=108378&view=rev > Log: > Add instcombine transforms to optimize tests of multiple bits of the same value into a single larger comparison. > > Modified: > ? ?llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp > ? ?llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp Tests? > Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp?rev=108378&r1=108377&r2=108378&view=diff > ============================================================================== > --- llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp (original) > +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp Wed Jul 14 18:33:51 2010 > @@ -699,6 +699,31 @@ > ? ? SI.setOperand(2, TrueVal); > ? ? return &SI; > ? } > + > + ?// select (or (A == 0) (B == 0)) T, F--> select (and (A != 0) (B != 0)) F, T > + ?// Note: This is a canonicalization rather than an optimization, and is used > + ?// to expose opportunities to other instcombine transforms. > + ?Instruction* CondInst = dyn_cast(CondVal); > + ?if (CondInst && CondInst->getOpcode() == Instruction::Or) { > + ? ?ICmpInst *LHSCmp = dyn_cast(CondInst->getOperand(0)); > + ? ?ICmpInst *RHSCmp = dyn_cast(CondInst->getOperand(1)); > + ? ?if (LHSCmp && LHSCmp->getPredicate() == ICmpInst::ICMP_EQ && > + ? ? ? ?RHSCmp && RHSCmp->getPredicate() == ICmpInst::ICMP_EQ) { > + ? ? ?ConstantInt* C1 = dyn_cast(LHSCmp->getOperand(1)); > + ? ? ?ConstantInt* C2 = dyn_cast(RHSCmp->getOperand(1)); > + ? ? ?if (C1 && C1->isZero() && C2 && C2->isZero()) { > + ? ? ? ?LHSCmp->setPredicate(ICmpInst::ICMP_NE); > + ? ? ? ?RHSCmp->setPredicate(ICmpInst::ICMP_NE); > + ? ? ? ?Value *And = > + ? ? ? ? ?InsertNewInstBefore(BinaryOperator::CreateAnd(LHSCmp, RHSCmp, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? "and."+CondVal->getName()), SI); > + ? ? ? ?SI.setOperand(0, And); > + ? ? ? ?SI.setOperand(1, FalseVal); > + ? ? ? ?SI.setOperand(2, TrueVal); > + ? ? ? ?return &SI; > + ? ? ?} > + ? ?} > + ?} Is this missing checks that the or and cmp instructions only have one use? -Eli From bob.wilson at apple.com Wed Jul 14 18:49:19 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Wed, 14 Jul 2010 23:49:19 -0000 Subject: [llvm-commits] [llvm] r108384 - /llvm/trunk/utils/buildit/build_llvm Message-ID: <20100714234919.0D14E2A6C12C@llvm.org> Author: bwilson Date: Wed Jul 14 18:49:18 2010 New Revision: 108384 URL: http://llvm.org/viewvc/llvm-project?rev=108384&view=rev Log: Remove the entire docs directory from Apple-style builds. This fixes a "usr_junk" verification failure when installing into /usr. Modified: llvm/trunk/utils/buildit/build_llvm Modified: llvm/trunk/utils/buildit/build_llvm URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/buildit/build_llvm?rev=108384&r1=108383&r2=108384&view=diff ============================================================================== --- llvm/trunk/utils/buildit/build_llvm (original) +++ llvm/trunk/utils/buildit/build_llvm Wed Jul 14 18:49:18 2010 @@ -345,9 +345,9 @@ chgrp -R wheel $DEST_DIR ################################################################################ -# Remove tar ball from docs directory +# Remove the docs directory -find $DEST_DIR -name html.tar.gz -exec rm {} \; +rm -rf $DEST_DIR$DEST_ROOT/docs ################################################################################ # symlinks so that B&I can find things From stoklund at 2pi.dk Wed Jul 14 18:50:27 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 14 Jul 2010 23:50:27 -0000 Subject: [llvm-commits] [llvm] r108385 - in /llvm/trunk/lib/Target/X86: X86ISelLowering.cpp X86ISelLowering.h Message-ID: <20100714235027.83E292A6C12C@llvm.org> Author: stoklund Date: Wed Jul 14 18:50:27 2010 New Revision: 108385 URL: http://llvm.org/viewvc/llvm-project?rev=108385&view=rev Log: Use TargetOpcode::COPY instead of X86-native register copy instructions when lowering atomics. This will allow those copies to still be coalesced after TII::isMoveInstr is removed. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.h Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=108385&r1=108384&r2=108385&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Jul 14 18:50:27 2010 @@ -7999,7 +7999,6 @@ unsigned immOpc, unsigned LoadOpc, unsigned CXchgOpc, - unsigned copyOpc, unsigned notOpc, unsigned EAXreg, TargetRegisterClass *RC, @@ -8076,7 +8075,7 @@ MIB.addReg(tt); (*MIB).addOperand(*argOpers[valArgIndx]); - MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg); + MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg); MIB.addReg(t1); MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc)); @@ -8087,7 +8086,7 @@ (*MIB).setMemRefs(bInstr->memoperands_begin(), bInstr->memoperands_end()); - MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg()); + MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); MIB.addReg(EAXreg); // insert branch @@ -8123,7 +8122,6 @@ const TargetRegisterClass *RC = X86::GR32RegisterClass; const unsigned LoadOpc = X86::MOV32rm; - const unsigned copyOpc = X86::MOV32rr; const unsigned NotOpc = X86::NOT32r; const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); const BasicBlock *LLVM_BB = MBB->getBasicBlock(); @@ -8233,14 +8231,14 @@ MIB.addReg(t2); (*MIB).addOperand(*argOpers[valArgIndx + 1]); - MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX); + MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); MIB.addReg(t1); - MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX); + MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX); MIB.addReg(t2); - MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX); + MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX); MIB.addReg(t5); - MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX); + MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX); MIB.addReg(t6); MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B)); @@ -8251,9 +8249,9 @@ (*MIB).setMemRefs(bInstr->memoperands_begin(), bInstr->memoperands_end()); - MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3); + MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3); MIB.addReg(X86::EAX); - MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4); + MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4); MIB.addReg(X86::EDX); // insert branch @@ -8332,12 +8330,12 @@ unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); if (argOpers[valArgIndx]->isReg()) - MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); + MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2); else MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); (*MIB).addOperand(*argOpers[valArgIndx]); - MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX); + MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); MIB.addReg(t1); MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr)); @@ -8359,7 +8357,7 @@ (*MIB).setMemRefs(mInstr->memoperands_begin(), mInstr->memoperands_end()); - MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg()); + MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); MIB.addReg(X86::EAX); // insert branch @@ -8741,25 +8739,25 @@ case X86::ATOMAND32: return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, X86::AND32ri, X86::MOV32rm, - X86::LCMPXCHG32, X86::MOV32rr, + X86::LCMPXCHG32, X86::NOT32r, X86::EAX, X86::GR32RegisterClass); case X86::ATOMOR32: return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr, X86::OR32ri, X86::MOV32rm, - X86::LCMPXCHG32, X86::MOV32rr, + X86::LCMPXCHG32, X86::NOT32r, X86::EAX, X86::GR32RegisterClass); case X86::ATOMXOR32: return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr, X86::XOR32ri, X86::MOV32rm, - X86::LCMPXCHG32, X86::MOV32rr, + X86::LCMPXCHG32, X86::NOT32r, X86::EAX, X86::GR32RegisterClass); case X86::ATOMNAND32: return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, X86::AND32ri, X86::MOV32rm, - X86::LCMPXCHG32, X86::MOV32rr, + X86::LCMPXCHG32, X86::NOT32r, X86::EAX, X86::GR32RegisterClass, true); case X86::ATOMMIN32: @@ -8774,25 +8772,25 @@ case X86::ATOMAND16: return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, X86::AND16ri, X86::MOV16rm, - X86::LCMPXCHG16, X86::MOV16rr, + X86::LCMPXCHG16, X86::NOT16r, X86::AX, X86::GR16RegisterClass); case X86::ATOMOR16: return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr, X86::OR16ri, X86::MOV16rm, - X86::LCMPXCHG16, X86::MOV16rr, + X86::LCMPXCHG16, X86::NOT16r, X86::AX, X86::GR16RegisterClass); case X86::ATOMXOR16: return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr, X86::XOR16ri, X86::MOV16rm, - X86::LCMPXCHG16, X86::MOV16rr, + X86::LCMPXCHG16, X86::NOT16r, X86::AX, X86::GR16RegisterClass); case X86::ATOMNAND16: return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, X86::AND16ri, X86::MOV16rm, - X86::LCMPXCHG16, X86::MOV16rr, + X86::LCMPXCHG16, X86::NOT16r, X86::AX, X86::GR16RegisterClass, true); case X86::ATOMMIN16: @@ -8807,25 +8805,25 @@ case X86::ATOMAND8: return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, X86::AND8ri, X86::MOV8rm, - X86::LCMPXCHG8, X86::MOV8rr, + X86::LCMPXCHG8, X86::NOT8r, X86::AL, X86::GR8RegisterClass); case X86::ATOMOR8: return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr, X86::OR8ri, X86::MOV8rm, - X86::LCMPXCHG8, X86::MOV8rr, + X86::LCMPXCHG8, X86::NOT8r, X86::AL, X86::GR8RegisterClass); case X86::ATOMXOR8: return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr, X86::XOR8ri, X86::MOV8rm, - X86::LCMPXCHG8, X86::MOV8rr, + X86::LCMPXCHG8, X86::NOT8r, X86::AL, X86::GR8RegisterClass); case X86::ATOMNAND8: return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, X86::AND8ri, X86::MOV8rm, - X86::LCMPXCHG8, X86::MOV8rr, + X86::LCMPXCHG8, X86::NOT8r, X86::AL, X86::GR8RegisterClass, true); // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way. @@ -8833,25 +8831,25 @@ case X86::ATOMAND64: return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, X86::AND64ri32, X86::MOV64rm, - X86::LCMPXCHG64, X86::MOV64rr, + X86::LCMPXCHG64, X86::NOT64r, X86::RAX, X86::GR64RegisterClass); case X86::ATOMOR64: return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr, X86::OR64ri32, X86::MOV64rm, - X86::LCMPXCHG64, X86::MOV64rr, + X86::LCMPXCHG64, X86::NOT64r, X86::RAX, X86::GR64RegisterClass); case X86::ATOMXOR64: return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr, X86::XOR64ri32, X86::MOV64rm, - X86::LCMPXCHG64, X86::MOV64rr, + X86::LCMPXCHG64, X86::NOT64r, X86::RAX, X86::GR64RegisterClass); case X86::ATOMNAND64: return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, X86::AND64ri32, X86::MOV64rm, - X86::LCMPXCHG64, X86::MOV64rr, + X86::LCMPXCHG64, X86::NOT64r, X86::RAX, X86::GR64RegisterClass, true); case X86::ATOMMIN64: Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=108385&r1=108384&r2=108385&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Wed Jul 14 18:50:27 2010 @@ -764,7 +764,6 @@ unsigned immOpc, unsigned loadOpc, unsigned cxchgOpc, - unsigned copyOpc, unsigned notOpc, unsigned EAXreg, TargetRegisterClass *RC, From bob.wilson at apple.com Wed Jul 14 18:54:44 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Wed, 14 Jul 2010 23:54:44 -0000 Subject: [llvm-commits] [llvm] r108386 - in /llvm/trunk/lib/Target/ARM: ARMAddressingModes.h AsmPrinter/ARMAsmPrinter.cpp AsmPrinter/ARMInstPrinter.cpp Message-ID: <20100714235444.258A42A6C12C@llvm.org> Author: bwilson Date: Wed Jul 14 18:54:43 2010 New Revision: 108386 URL: http://llvm.org/viewvc/llvm-project?rev=108386&view=rev Log: Remove restriction on NEON alignment values. Some of the NEON ld/st instructions use different values (e.g., 2-byte or 4-byte alignment). Also fix ARMInstPrinter to print these alignments as bits instead of bytes. Modified: llvm/trunk/lib/Target/ARM/ARMAddressingModes.h llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMAddressingModes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAddressingModes.h?rev=108386&r1=108385&r2=108386&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAddressingModes.h (original) +++ llvm/trunk/lib/Target/ARM/ARMAddressingModes.h Wed Jul 14 18:54:43 2010 @@ -519,9 +519,8 @@ // // This is stored in two operands [regaddr, align]. The first is the // address register. The second operand is the value of the alignment - // specifier to use or zero if no explicit alignment. - // Valid alignments are: 0, 8, 16, and 32 bytes, depending on the specific - // instruction. + // specifier in bytes or zero if no explicit alignment. + // Valid alignments depend on the specific instruction. //===--------------------------------------------------------------------===// // NEON Modified Immediates Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=108386&r1=108385&r2=108386&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Wed Jul 14 18:54:43 2010 @@ -602,12 +602,8 @@ O << "[" << getRegisterName(MO1.getReg()); if (MO2.getImm()) { - unsigned Align = MO2.getImm(); - assert((Align == 8 || Align == 16 || Align == 32) && - "unexpected NEON load/store alignment"); - Align <<= 3; // FIXME: Both darwin as and GNU as violate ARM docs here. - O << ", :" << Align; + O << ", :" << (MO2.getImm() << 3); } O << "]"; } Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp?rev=108386&r1=108385&r2=108386&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Wed Jul 14 18:54:43 2010 @@ -442,7 +442,7 @@ O << "[" << getRegisterName(MO1.getReg()); if (MO2.getImm()) { // FIXME: Both darwin as and GNU as violate ARM docs here. - O << ", :" << MO2.getImm(); + O << ", :" << (MO2.getImm() << 3); } O << "]"; } From stoklund at 2pi.dk Wed Jul 14 18:58:21 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 14 Jul 2010 23:58:21 -0000 Subject: [llvm-commits] [llvm] r108387 - /llvm/trunk/lib/Target/X86/X86FastISel.cpp Message-ID: <20100714235821.C1D902A6C12C@llvm.org> Author: stoklund Date: Wed Jul 14 18:58:21 2010 New Revision: 108387 URL: http://llvm.org/viewvc/llvm-project?rev=108387&view=rev Log: Last COPY conversion. Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=108387&r1=108386&r2=108387&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Wed Jul 14 18:58:21 2010 @@ -1279,12 +1279,11 @@ return false; // First issue a copy to GR16_ABCD or GR32_ABCD. - unsigned CopyOpc = (SrcVT == MVT::i16) ? X86::MOV16rr : X86::MOV32rr; const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16) ? X86::GR16_ABCDRegisterClass : X86::GR32_ABCDRegisterClass; unsigned CopyReg = createResultReg(CopyRC); - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CopyOpc), CopyReg) - .addReg(InputReg); + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), + CopyReg).addReg(InputReg); // Then issue an extract_subreg. unsigned ResultReg = FastEmitInst_extractsubreg(MVT::i8, From eli.friedman at gmail.com Wed Jul 14 19:33:00 2010 From: eli.friedman at gmail.com (Eli Friedman) Date: Thu, 15 Jul 2010 00:33:00 -0000 Subject: [llvm-commits] [llvm] r108389 - in /llvm/trunk/lib/Transforms/InstCombine: InstCombineAndOrXor.cpp InstCombineSelect.cpp Message-ID: <20100715003300.EC62D2A6C12C@llvm.org> Author: efriedma Date: Wed Jul 14 19:33:00 2010 New Revision: 108389 URL: http://llvm.org/viewvc/llvm-project?rev=108389&view=rev Log: Speculatively revert r108378; may be causing bootstrap failures. Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp?rev=108389&r1=108388&r2=108389&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp Wed Jul 14 19:33:00 2010 @@ -472,24 +472,6 @@ Value *NewOr = Builder->CreateOr(Val, Val2); return Builder->CreateICmp(LHSCC, NewOr, LHSCst); } - - // (icmp ne (A & C1) 0) & (icmp ne (A & C2), 0) --> - // (icmp eq (A & (C1|C2)), (C1|C2)) - if (LHSCC == ICmpInst::ICMP_NE && LHSCst->isZero()) { - Instruction *I1 = dyn_cast(Val); - Instruction *I2 = dyn_cast(Val2); - if (I1 && I1->getOpcode() == Instruction::And && - I2 && I2->getOpcode() == Instruction::And && - I1->getOperand(0) == I1->getOperand(0)) { - ConstantInt *CI1 = dyn_cast(I1->getOperand(1)); - ConstantInt *CI2 = dyn_cast(I2->getOperand(1)); - if (CI1 && CI2) { - Constant *ConstOr = ConstantExpr::getOr(CI1, CI2); - Value *NewAnd = Builder->CreateAnd(I1->getOperand(0), ConstOr); - return Builder->CreateICmp(ICmpInst::ICMP_EQ, NewAnd, ConstOr); - } - } - } } // From here on, we only handle: Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp?rev=108389&r1=108388&r2=108389&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp Wed Jul 14 19:33:00 2010 @@ -699,31 +699,6 @@ SI.setOperand(2, TrueVal); return &SI; } - - // select (or (A == 0) (B == 0)) T, F--> select (and (A != 0) (B != 0)) F, T - // Note: This is a canonicalization rather than an optimization, and is used - // to expose opportunities to other instcombine transforms. - Instruction* CondInst = dyn_cast(CondVal); - if (CondInst && CondInst->getOpcode() == Instruction::Or) { - ICmpInst *LHSCmp = dyn_cast(CondInst->getOperand(0)); - ICmpInst *RHSCmp = dyn_cast(CondInst->getOperand(1)); - if (LHSCmp && LHSCmp->getPredicate() == ICmpInst::ICMP_EQ && - RHSCmp && RHSCmp->getPredicate() == ICmpInst::ICMP_EQ) { - ConstantInt* C1 = dyn_cast(LHSCmp->getOperand(1)); - ConstantInt* C2 = dyn_cast(RHSCmp->getOperand(1)); - if (C1 && C1->isZero() && C2 && C2->isZero()) { - LHSCmp->setPredicate(ICmpInst::ICMP_NE); - RHSCmp->setPredicate(ICmpInst::ICMP_NE); - Value *And = - InsertNewInstBefore(BinaryOperator::CreateAnd(LHSCmp, RHSCmp, - "and."+CondVal->getName()), SI); - SI.setOperand(0, And); - SI.setOperand(1, FalseVal); - SI.setOperand(2, TrueVal); - return &SI; - } - } - } return 0; } From sabre at nondot.org Wed Jul 14 19:37:34 2010 From: sabre at nondot.org (Chris Lattner) Date: Thu, 15 Jul 2010 00:37:34 -0000 Subject: [llvm-commits] [llvm] r108390 - in /llvm/trunk/lib/CodeGen/AsmPrinter: AsmPrinter.cpp AsmPrinterInlineAsm.cpp Message-ID: <20100715003734.E42922A6C12C@llvm.org> Author: lattner Date: Wed Jul 14 19:37:34 2010 New Revision: 108390 URL: http://llvm.org/viewvc/llvm-project?rev=108390&view=rev Log: a more graceful fix for test/Other/inline-asm-newline-terminator.ll, follow on to r103765 Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=108390&r1=108389&r2=108390&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Wed Jul 14 19:37:34 2010 @@ -178,7 +178,7 @@ if (!M.getModuleInlineAsm().empty()) { OutStreamer.AddComment("Start of file scope inline assembly"); OutStreamer.AddBlankLine(); - EmitInlineAsm(M.getModuleInlineAsm(), 0/*no loc cookie*/); + EmitInlineAsm(M.getModuleInlineAsm()+"\n", 0/*no loc cookie*/); OutStreamer.AddComment("End of file scope inline assembly"); OutStreamer.AddBlankLine(); } Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp?rev=108390&r1=108389&r2=108390&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp Wed Jul 14 19:37:34 2010 @@ -53,17 +53,6 @@ } SourceMgr SrcMgr; - - // Ensure the buffer is newline terminated. - char *TmpString = 0; - if (Str.back() != '\n') { - TmpString = new char[Str.size() + 2]; - memcpy(TmpString, Str.data(), Str.size()); - TmpString[Str.size()] = '\n'; - TmpString[Str.size() + 1] = 0; - isNullTerminated = true; - Str = TmpString; - } // If the current LLVMContext has an inline asm handler, set it in SourceMgr. LLVMContext &LLVMCtx = MMI->getModule()->getContext(); @@ -95,9 +84,6 @@ /*NoFinalize*/ true); if (Res && !HasDiagHandler) report_fatal_error("Error parsing inline asm\n"); - - if (TmpString) - delete[] TmpString; } From clattner at apple.com Wed Jul 14 19:38:05 2010 From: clattner at apple.com (Chris Lattner) Date: Wed, 14 Jul 2010 17:38:05 -0700 Subject: [llvm-commits] [llvm] r103765 - in /llvm/trunk: lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp test/Other/inline-asm-newline-terminator.ll In-Reply-To: <20100514043150.C06E9312800A@llvm.org> References: <20100514043150.C06E9312800A@llvm.org> Message-ID: <370D013F-90A2-4581-9BDF-D16095FE8264@apple.com> On May 13, 2010, at 9:31 PM, Daniel Dunbar wrote: > Author: ddunbar > Date: Thu May 13 23:31:50 2010 > New Revision: 103765 > > URL: http://llvm.org/viewvc/llvm-project?rev=103765&view=rev > Log: > Inline Asm: Ensure buffer is newline terminated to match how the text is printed. > - This is a hack, but I can't decide the best place to handle this. Chris? I checked in a more elegant fix in r108390, thanks! -Chris From daniel at zuster.org Wed Jul 14 20:18:52 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 15 Jul 2010 01:18:52 -0000 Subject: [llvm-commits] [test-suite] r108392 - /test-suite/trunk/External/SPEC/CINT95/129.compress/Makefile Message-ID: <20100715011852.E71EF2A6C12C@llvm.org> Author: ddunbar Date: Wed Jul 14 20:18:52 2010 New Revision: 108392 URL: http://llvm.org/viewvc/llvm-project?rev=108392&view=rev Log: Set -Wno-return-type for 129.compress, clang errors on this one as well now. Modified: test-suite/trunk/External/SPEC/CINT95/129.compress/Makefile Modified: test-suite/trunk/External/SPEC/CINT95/129.compress/Makefile URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/External/SPEC/CINT95/129.compress/Makefile?rev=108392&r1=108391&r2=108392&view=diff ============================================================================== --- test-suite/trunk/External/SPEC/CINT95/129.compress/Makefile (original) +++ test-suite/trunk/External/SPEC/CINT95/129.compress/Makefile Wed Jul 14 20:18:52 2010 @@ -7,3 +7,5 @@ else STDIN_FILENAME = test.in endif + +CFLAGS += -Wno-return-type From daniel at zuster.org Wed Jul 14 20:18:55 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 15 Jul 2010 01:18:55 -0000 Subject: [llvm-commits] [test-suite] r108393 - /test-suite/trunk/MultiSource/Applications/ClamAV/clamscan_treewalk.c Message-ID: <20100715011855.A3E262A6C12D@llvm.org> Author: ddunbar Date: Wed Jul 14 20:18:55 2010 New Revision: 108393 URL: http://llvm.org/viewvc/llvm-project?rev=108393&view=rev Log: Don't print excluded .svn directories in the output (in another place), to match reference output. Modified: test-suite/trunk/MultiSource/Applications/ClamAV/clamscan_treewalk.c Modified: test-suite/trunk/MultiSource/Applications/ClamAV/clamscan_treewalk.c URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/MultiSource/Applications/ClamAV/clamscan_treewalk.c?rev=108393&r1=108392&r2=108393&view=diff ============================================================================== --- test-suite/trunk/MultiSource/Applications/ClamAV/clamscan_treewalk.c (original) +++ test-suite/trunk/MultiSource/Applications/ClamAV/clamscan_treewalk.c Wed Jul 14 20:18:55 2010 @@ -70,8 +70,10 @@ argument = opt_firstarg(opt, "exclude-dir", &optnode); while(argument) { if(match_regex(dirname, argument) == 1) { +#if 0 if(!printinfected) logg("%s: Excluded\n", dirname); +#endif return 0; } argument = opt_nextarg(&optnode, "exclude-dir"); From daniel at zuster.org Wed Jul 14 20:42:44 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 15 Jul 2010 01:42:44 -0000 Subject: [llvm-commits] [test-suite] r108394 - in /test-suite/trunk/External/SPEC: CINT2000/Makefile CINT95/Makefile Message-ID: <20100715014244.9B2E82A6C12C@llvm.org> Author: ddunbar Date: Wed Jul 14 20:42:44 2010 New Revision: 108394 URL: http://llvm.org/viewvc/llvm-project?rev=108394&view=rev Log: Add a CC_UNDER_TEST_IS_CLANG make variable (not set automatically), which disables certain non-standard tests (126.gcc and 176.gcc). Modified: test-suite/trunk/External/SPEC/CINT2000/Makefile test-suite/trunk/External/SPEC/CINT95/Makefile Modified: test-suite/trunk/External/SPEC/CINT2000/Makefile URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/External/SPEC/CINT2000/Makefile?rev=108394&r1=108393&r2=108394&view=diff ============================================================================== --- test-suite/trunk/External/SPEC/CINT2000/Makefile (original) +++ test-suite/trunk/External/SPEC/CINT2000/Makefile Wed Jul 14 20:42:44 2010 @@ -13,6 +13,11 @@ 256.bzip2 \ 300.twolf +# Disable 176.gcc when testing with Clang, which doesn't support lvalue casts. +ifdef CC_UNDER_TEST_IS_CLANG +PARALLEL_DIRS := $(filter-out 176.gcc, $(PARALLEL_DIRS)) +endif + # Get the $(ARCH) setting include $(LEVEL)/Makefile.config Modified: test-suite/trunk/External/SPEC/CINT95/Makefile URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/External/SPEC/CINT95/Makefile?rev=108394&r1=108393&r2=108394&view=diff ============================================================================== --- test-suite/trunk/External/SPEC/CINT95/Makefile (original) +++ test-suite/trunk/External/SPEC/CINT95/Makefile Wed Jul 14 20:42:44 2010 @@ -9,6 +9,11 @@ 134.perl \ 147.vortex +# Disable 126.gcc when testing with Clang, which doesn't support lvalue casts. +ifdef CC_UNDER_TEST_IS_CLANG +PARALLEL_DIRS := $(filter-out 126.gcc, $(PARALLEL_DIRS)) +endif + # Get the $(ARCH) setting include $(LEVEL)/Makefile.config From daniel at zuster.org Wed Jul 14 20:48:17 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 15 Jul 2010 01:48:17 -0000 Subject: [llvm-commits] [test-suite] r108395 - /test-suite/trunk/MultiSource/Benchmarks/Trimaran/netbench-crc/netbench-crc.reference_output.small Message-ID: <20100715014817.F19122A6C12C@llvm.org> Author: ddunbar Date: Wed Jul 14 20:48:17 2010 New Revision: 108395 URL: http://llvm.org/viewvc/llvm-project?rev=108395&view=rev Log: netbench-crc: Update small reference output. Modified: test-suite/trunk/MultiSource/Benchmarks/Trimaran/netbench-crc/netbench-crc.reference_output.small Modified: test-suite/trunk/MultiSource/Benchmarks/Trimaran/netbench-crc/netbench-crc.reference_output.small URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/MultiSource/Benchmarks/Trimaran/netbench-crc/netbench-crc.reference_output.small?rev=108395&r1=108394&r2=108395&view=diff ============================================================================== --- test-suite/trunk/MultiSource/Benchmarks/Trimaran/netbench-crc/netbench-crc.reference_output.small (original) +++ test-suite/trunk/MultiSource/Benchmarks/Trimaran/netbench-crc/netbench-crc.reference_output.small Wed Jul 14 20:48:17 2010 @@ -1,3 +1,3 @@ CRC completed for 1000 packets -crc_accum is 144398862177705626 +crc_accum is 101883546 exit 0 From eli.friedman at gmail.com Wed Jul 14 20:49:02 2010 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 14 Jul 2010 18:49:02 -0700 Subject: [llvm-commits] [llvm] r108389 - in /llvm/trunk/lib/Transforms/InstCombine: InstCombineAndOrXor.cpp InstCombineSelect.cpp In-Reply-To: <20100715003300.EC62D2A6C12C@llvm.org> References: <20100715003300.EC62D2A6C12C@llvm.org> Message-ID: On Wed, Jul 14, 2010 at 5:33 PM, Eli Friedman wrote: > Author: efriedma > Date: Wed Jul 14 19:33:00 2010 > New Revision: 108389 > > URL: http://llvm.org/viewvc/llvm-project?rev=108389&view=rev > Log: > Speculatively revert r108378; may be causing bootstrap failures. This did in fact fix the buildbot failures. -Eli From eli.friedman at gmail.com Wed Jul 14 21:20:38 2010 From: eli.friedman at gmail.com (Eli Friedman) Date: Thu, 15 Jul 2010 02:20:38 -0000 Subject: [llvm-commits] [llvm] r108396 - /llvm/trunk/lib/Target/ARM/README.txt Message-ID: <20100715022038.86F312A6C12C@llvm.org> Author: efriedma Date: Wed Jul 14 21:20:38 2010 New Revision: 108396 URL: http://llvm.org/viewvc/llvm-project?rev=108396&view=rev Log: Random note about bswap. Modified: llvm/trunk/lib/Target/ARM/README.txt Modified: llvm/trunk/lib/Target/ARM/README.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/README.txt?rev=108396&r1=108395&r2=108396&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/README.txt (original) +++ llvm/trunk/lib/Target/ARM/README.txt Wed Jul 14 21:20:38 2010 @@ -631,3 +631,29 @@ //===---------------------------------------------------------------------===// + +The code generated for bswap on armv4/5 (CPUs without rev) is less than ideal: + +int a(int x) { return __builtin_bswap32(x); } + +a: + mov r1, #255, 24 + mov r2, #255, 16 + and r1, r1, r0, lsr #8 + and r2, r2, r0, lsl #8 + orr r1, r1, r0, lsr #24 + orr r0, r2, r0, lsl #24 + orr r0, r0, r1 + bx lr + +Something like the following would be better (fewer instructions/registers): + eor r1, r0, r0, ror #16 + bic r1, r1, #0xff0000 + mov r1, r1, lsr #8 + eor r0, r1, r0, ror #8 + bx lr + +A custom Thumb version would also be a slight improvement over the generic +version. + +//===---------------------------------------------------------------------===// From daniel at zuster.org Wed Jul 14 22:03:19 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 15 Jul 2010 03:03:19 -0000 Subject: [llvm-commits] [zorg] r108398 - /zorg/trunk/lnt/lnt/tests/nt.py Message-ID: <20100715030319.A33C52A6C12C@llvm.org> Author: ddunbar Date: Wed Jul 14 22:03:19 2010 New Revision: 108398 URL: http://llvm.org/viewvc/llvm-project?rev=108398&view=rev Log: LNT/nt: Automatically set CC_UNDER_TEST_IS_CLANG in the make variables. Modified: zorg/trunk/lnt/lnt/tests/nt.py Modified: zorg/trunk/lnt/lnt/tests/nt.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/tests/nt.py?rev=108398&r1=108397&r2=108398&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/tests/nt.py (original) +++ zorg/trunk/lnt/lnt/tests/nt.py Wed Jul 14 22:03:19 2010 @@ -133,6 +133,10 @@ cc_info = lnt.testing.util.compilers.get_cc_info(opts.cc_under_test, target_flags) + # Set CC_UNDER_TEST_IS_CLANG when appropriate. + if cc_info.get('cc_name') == 'clang': + make_variables['CC_UNDER_TEST_IS_CLANG'] = '1' + # Set ARCH appropriately, based on the inferred target. # # FIXME: We should probably be more strict about this. From daniel at zuster.org Wed Jul 14 22:03:22 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 15 Jul 2010 03:03:22 -0000 Subject: [llvm-commits] [zorg] r108399 - /zorg/trunk/lnt/lnt/util/NTEmailReport.py Message-ID: <20100715030323.08F772A6C12D@llvm.org> Author: ddunbar Date: Wed Jul 14 22:03:22 2010 New Revision: 108399 URL: http://llvm.org/viewvc/llvm-project?rev=108399&view=rev Log: LNT/simple: Show entire list of existing failures in report, truncation doesn't seem to be very useful. Modified: zorg/trunk/lnt/lnt/util/NTEmailReport.py Modified: zorg/trunk/lnt/lnt/util/NTEmailReport.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/util/NTEmailReport.py?rev=108399&r1=108398&r2=108399&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/util/NTEmailReport.py (original) +++ zorg/trunk/lnt/lnt/util/NTEmailReport.py Wed Jul 14 22:03:22 2010 @@ -335,20 +335,13 @@ else: table_name = "Existing Failures" - # Print at most 10 failures in an email report. print >>html_report, """

""" % table_name - N = 10 - for name,cr in tests[:N]: + for name,cr in tests: print >>report, ' %s' % (name,) print >>html_report, """""" % (name,) - if len(tests) > 10: - print >>report, ' ... and %d more ...' % (len(tests) - 10,) - print >>html_report, """ -""" % ( - len(tests) - 10,) print >>html_report, """
%s
%s
... and %d more ...
""" From daniel at zuster.org Wed Jul 14 22:03:26 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 15 Jul 2010 03:03:26 -0000 Subject: [llvm-commits] [zorg] r108400 - in /zorg/trunk/lnt/lnt: db/perfdbsummary.py util/NTEmailReport.py viewer/simple.ptl Message-ID: <20100715030326.305CA2A6C12E@llvm.org> Author: ddunbar Date: Wed Jul 14 22:03:25 2010 New Revision: 108400 URL: http://llvm.org/viewvc/llvm-project?rev=108400&view=rev Log: LNT/simple: Only consider the tests present in the current (and previous) run when generating reports, instead of all tests submitted to the DB. Modified: zorg/trunk/lnt/lnt/db/perfdbsummary.py zorg/trunk/lnt/lnt/util/NTEmailReport.py zorg/trunk/lnt/lnt/viewer/simple.ptl Modified: zorg/trunk/lnt/lnt/db/perfdbsummary.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/db/perfdbsummary.py?rev=108400&r1=108399&r2=108400&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/db/perfdbsummary.py (original) +++ zorg/trunk/lnt/lnt/db/perfdbsummary.py Wed Jul 14 22:03:25 2010 @@ -2,7 +2,7 @@ Classes for caching metadata about a PerfDB instance. """ -from lnt.viewer.PerfDB import Run, RunInfo, Test +from lnt.viewer.PerfDB import Run, RunInfo, Sample, Test class SuiteSummary: def __init__(self, name, path): @@ -109,11 +109,27 @@ self.test_status_map = test_status_map self.parameter_keys = parameter_keys self.parameter_sets = parameter_sets + self.test_info_map = dict([(v,k) for k,v in test_id_map.items()]) def is_up_to_date(self, db): return (not db.modified_test and self.revision == db.get_revision_number("Test")) + def get_test_names_in_runs(self, db, runs): + # Load the distinct test ids for these runs. + test_ids = db.session.query(Sample.test_id)\ + .filter(Sample.run_id.in_(runs)).distinct() + + # Get the test names for the test ids. + test_names = [self.test_info_map[id][0] + for id, in test_ids] + + # Limit to the tests we actually report. + test_names = list(set(test_names) & set(self.test_names)) + test_names.sort() + + return test_names + _cache = {} def get_simple_suite_summary(db, tag): key = (db.path, tag) Modified: zorg/trunk/lnt/lnt/util/NTEmailReport.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/util/NTEmailReport.py?rev=108400&r1=108399&r2=108400&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/util/NTEmailReport.py (original) +++ zorg/trunk/lnt/lnt/util/NTEmailReport.py Wed Jul 14 22:03:25 2010 @@ -114,6 +114,12 @@ # FIXME: Look for run across machine. compare_to = None + # Get the list of tests we are interested in. + interesting_runs = [run.id] + if compare_to: + interesting_runs.append(compare_to.id) + test_names = ts_summary.get_test_names_in_runs(db, interesting_runs) + # Gather the changes to report, mapped by parameter set. new_failures = Util.multidict() new_passes = Util.multidict() @@ -122,7 +128,7 @@ added_tests = Util.multidict() removed_tests = Util.multidict() existing_failures = Util.multidict() - for name in ts_summary.test_names: + for name in test_names: for pset in ts_summary.parameter_sets: cr = sri.get_run_comparison_result(run, compare_to, name, pset, comparison_window) Modified: zorg/trunk/lnt/lnt/viewer/simple.ptl URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/viewer/simple.ptl?rev=108400&r1=108399&r2=108400&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/viewer/simple.ptl (original) +++ zorg/trunk/lnt/lnt/viewer/simple.ptl Wed Jul 14 22:03:25 2010 @@ -484,6 +484,12 @@ htmltext(html_report) self.renderPopupEnd() + # Get the list of tests we are interested in. + interesting_runs = [run.id] + if compare_to: + interesting_runs.append(compare_to.id) + test_names = ts_summary.get_test_names_in_runs(db, interesting_runs) + # Gather the runs to use for statistical data. cur_id = run.id comparison_window = [] @@ -599,7 +605,7 @@ """ """ - for name in ts_summary.test_names: + for name in test_names: """ From daniel at zuster.org Wed Jul 14 22:46:46 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 14 Jul 2010 20:46:46 -0700 Subject: [llvm-commits] [llvm] r108219 - /llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp In-Reply-To: <20100713002330.9D06F2A6C12C@llvm.org> References: <20100713002330.9D06F2A6C12C@llvm.org> Message-ID: Hi Jakob, memcpy-inline.ll is currently failing on llvm-gcc-powerpc-darwin9, like this: -- ******************** TEST 'LLVM :: CodeGen/ARM/memcpy-inline.ll' FAILED ********************Script: -- llc < /Users/buildslave/zorg/buildbot/smooshlab/slave/build.llvm-gcc-powerpc-darwin9/llvm.src/test/CodeGen/ARM/memcpy-inline.ll -mtriple=arm-apple-darwin | grep ldmia llc < /Users/buildslave/zorg/buildbot/smooshlab/slave/build.llvm-gcc-powerpc-darwin9/llvm.src/test/CodeGen/ARM/memcpy-inline.ll -mtriple=arm-apple-darwin | grep stmia llc < /Users/buildslave/zorg/buildbot/smooshlab/slave/build.llvm-gcc-powerpc-darwin9/llvm.src/test/CodeGen/ARM/memcpy-inline.ll -mtriple=arm-apple-darwin | grep ldrb llc < /Users/buildslave/zorg/buildbot/smooshlab/slave/build.llvm-gcc-powerpc-darwin9/llvm.src/test/CodeGen/ARM/memcpy-inline.ll -mtriple=arm-apple-darwin | grep ldrh -- Exit Code: 1 Command Output (stdout): -- Command has output on stderr! -- Command Output (stderr): -- 0 llc 0x00b890cc llvm::sys::RunInterruptHandlers() + 1196 1 llc 0x00b897d8 llvm::sys::PrintStackTraceOnErrorSignal() + 1128 2 libSystem.B.dylib 0x966089fc _sigtramp + 68 Stack dump: 0. Program arguments: llc -mtriple=arm-apple-darwin 1. Running pass 'Function Pass Manager' on module ''. 2. Running pass 'ARM Instruction Selection' on function '@t' -- ******************** -- It started in this build: http://smooshlab.apple.com:8010/builders/llvm-gcc-powerpc-darwin9/builds/3331 and I think this change is the most likely culprit. Can you take a look, or point the finger? - Daniel On Mon, Jul 12, 2010 at 5:23 PM, Jakob Stoklund Olesen wrote: > Author: stoklund > Date: Mon Jul 12 19:23:30 2010 > New Revision: 108219 > > URL: http://llvm.org/viewvc/llvm-project?rev=108219&view=rev > Log: > Don't add memory operands to storeRegToStackSlot / loadRegFromStackSlot results, > they already have one. > > This fixes the himenobmtxpa miscompilation on ARM. > > The PostRA scheduler got confused by the double memoperand and hoisted a stack > slot load above a store to the same slot. > > Modified: > ? ?llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp > > Modified: llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp?rev=108219&r1=108218&r2=108219&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp (original) > +++ llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp Mon Jul 12 19:23:30 2010 > @@ -24,6 +24,7 @@ > ?#include "llvm/CodeGen/MachineRegisterInfo.h" > ?#include "llvm/CodeGen/PostRAHazardRecognizer.h" > ?#include "llvm/CodeGen/PseudoSourceValue.h" > +#include "llvm/Support/Debug.h" > ?#include "llvm/Support/ErrorHandling.h" > ?#include "llvm/Support/raw_ostream.h" > ?using namespace llvm; > @@ -253,51 +254,44 @@ > ? MachineFunction &MF = *MBB->getParent(); > > ? // Ask the target to do the actual folding. > - ?MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, FI); > + ?if (MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, FI)) { > + ? ?// Add a memory operand, foldMemoryOperandImpl doesn't do that. > + ? ?assert((!(Flags & MachineMemOperand::MOStore) || > + ? ? ? ? ? ?NewMI->getDesc().mayStore()) && > + ? ? ? ? ? "Folded a def to a non-store!"); > + ? ?assert((!(Flags & MachineMemOperand::MOLoad) || > + ? ? ? ? ? ?NewMI->getDesc().mayLoad()) && > + ? ? ? ? ? "Folded a use to a non-load!"); > + ? ?const MachineFrameInfo &MFI = *MF.getFrameInfo(); > + ? ?assert(MFI.getObjectOffset(FI) != -1); > + ? ?MachineMemOperand *MMO = > + ? ? ?MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI), > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?Flags, /*Offset=*/0, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?MFI.getObjectSize(FI), > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?MFI.getObjectAlignment(FI)); > + ? ?NewMI->addMemOperand(MF, MMO); > > - ?// Straight COPY may fold as load/store. > - ?if (!NewMI) { > - ? ?if (!MI->isCopy() || Ops.size() != 1) > - ? ? ?return 0; > - > - ? ?const TargetRegisterClass *RC = canFoldCopy(MI, Ops[0]); > - ? ?if (!RC) > - ? ? ?return 0; > - > - ? ?const MachineOperand &MO = MI->getOperand(1-Ops[0]); > - ? ?MachineBasicBlock::iterator Pos = MI; > - ? ?const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); > - > - ? ?if (Flags == MachineMemOperand::MOStore) > - ? ? ?storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI); > - ? ?else > - ? ? ?loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, TRI); > - > - ? ?NewMI = --Pos; > - ?} else { > ? ? // FIXME: change foldMemoryOperandImpl semantics to also insert NewMI. > - ? ?NewMI = MBB->insert(MI, NewMI); > + ? ?return MBB->insert(MI, NewMI); > ? } > > - ?if (!NewMI) return 0; > - > + ?// Straight COPY may fold as load/store. > + ?if (!MI->isCopy() || Ops.size() != 1) > + ? ?return 0; > > - ?assert((!(Flags & MachineMemOperand::MOStore) || > - ? ? ? ? ?NewMI->getDesc().mayStore()) && > - ? ? ? ? "Folded a def to a non-store!"); > - ?assert((!(Flags & MachineMemOperand::MOLoad) || > - ? ? ? ? ?NewMI->getDesc().mayLoad()) && > - ? ? ? ? "Folded a use to a non-load!"); > - ?const MachineFrameInfo &MFI = *MF.getFrameInfo(); > - ?assert(MFI.getObjectOffset(FI) != -1); > - ?MachineMemOperand *MMO = > - ? ?MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI), > - ? ? ? ? ? ? ? ? ? ? ? ? ? ?Flags, /*Offset=*/0, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ?MFI.getObjectSize(FI), > - ? ? ? ? ? ? ? ? ? ? ? ? ? ?MFI.getObjectAlignment(FI)); > - ?NewMI->addMemOperand(MF, MMO); > + ?const TargetRegisterClass *RC = canFoldCopy(MI, Ops[0]); > + ?if (!RC) > + ? ?return 0; > > - ?return NewMI; > + ?const MachineOperand &MO = MI->getOperand(1-Ops[0]); > + ?MachineBasicBlock::iterator Pos = MI; > + ?const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); > + > + ?if (Flags == MachineMemOperand::MOStore) > + ? ?storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI); > + ?else > + ? ?loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, TRI); > + ?return --Pos; > ?} > > ?/// foldMemoryOperand - Same as the previous version except it allows folding > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From stoklund at 2pi.dk Wed Jul 14 23:10:28 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 14 Jul 2010 21:10:28 -0700 Subject: [llvm-commits] [llvm] r108219 - /llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp In-Reply-To: References: <20100713002330.9D06F2A6C12C@llvm.org> Message-ID: <59EC4350-1ADE-410C-B44B-1AA7AF4E8ABE@2pi.dk> On Jul 14, 2010, at 8:46 PM, Daniel Dunbar wrote: > Hi Jakob, > > memcpy-inline.ll is currently failing on llvm-gcc-powerpc-darwin9, like this: > > It started in this build: > http://smooshlab.apple.com:8010/builders/llvm-gcc-powerpc-darwin9/builds/3331 > and I think this change is the most likely culprit. Can you take a > look, or point the finger? Strange, it must be miscompiling llvm-gcc - it was supposed to be a bugfix. I'll take a look in the morning. Thanks, /Jakob -------------- next part -------------- A non-text attachment was scrubbed... Name: smime.p7s Type: application/pkcs7-signature Size: 1929 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100714/fdfcacd8/attachment.bin From eli.friedman at gmail.com Wed Jul 14 23:46:14 2010 From: eli.friedman at gmail.com (Eli Friedman) Date: Thu, 15 Jul 2010 04:46:14 -0000 Subject: [llvm-commits] [llvm] r108401 - /llvm/trunk/lib/Analysis/InstructionSimplify.cpp Message-ID: <20100715044615.03A982A6C12C@llvm.org> Author: efriedma Date: Wed Jul 14 23:46:14 2010 New Revision: 108401 URL: http://llvm.org/viewvc/llvm-project?rev=108401&view=rev Log: Add AssertingVH which makes PR7647 break consistently. Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InstructionSimplify.cpp?rev=108401&r1=108400&r2=108401&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/InstructionSimplify.cpp (original) +++ llvm/trunk/lib/Analysis/InstructionSimplify.cpp Wed Jul 14 23:46:14 2010 @@ -443,7 +443,9 @@ // FromHandle - This keeps a weakvh on the from value so that we can know if // it gets deleted out from under us in a recursive simplification. WeakVH FromHandle(From); - + // Double-check that To isn't deleted. + AssertingVH<> CheckedTo = To; + while (!From->use_empty()) { // Update the instruction to use the new value. Use &U = From->use_begin().getUse(); From eli.friedman at gmail.com Thu Jul 15 00:09:31 2010 From: eli.friedman at gmail.com (Eli Friedman) Date: Thu, 15 Jul 2010 05:09:31 -0000 Subject: [llvm-commits] [llvm] r108407 - /llvm/trunk/lib/Analysis/InstructionSimplify.cpp Message-ID: <20100715050931.EB2DA2A6C12C@llvm.org> Author: efriedma Date: Thu Jul 15 00:09:31 2010 New Revision: 108407 URL: http://llvm.org/viewvc/llvm-project?rev=108407&view=rev Log: Revert r108401; it breaks bootstrap :( Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InstructionSimplify.cpp?rev=108407&r1=108406&r2=108407&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/InstructionSimplify.cpp (original) +++ llvm/trunk/lib/Analysis/InstructionSimplify.cpp Thu Jul 15 00:09:31 2010 @@ -443,9 +443,7 @@ // FromHandle - This keeps a weakvh on the from value so that we can know if // it gets deleted out from under us in a recursive simplification. WeakVH FromHandle(From); - // Double-check that To isn't deleted. - AssertingVH<> CheckedTo = To; - + while (!From->use_empty()) { // Update the instruction to use the new value. Use &U = From->use_begin().getUse(); From sabre at nondot.org Thu Jul 15 00:14:01 2010 From: sabre at nondot.org (Chris Lattner) Date: Thu, 15 Jul 2010 05:14:01 -0000 Subject: [llvm-commits] [llvm] r108408 - /llvm/trunk/include/llvm/Value.h Message-ID: <20100715051401.2F7112A6C12C@llvm.org> Author: lattner Date: Thu Jul 15 00:14:01 2010 New Revision: 108408 URL: http://llvm.org/viewvc/llvm-project?rev=108408&view=rev Log: add an accessor. Modified: llvm/trunk/include/llvm/Value.h Modified: llvm/trunk/include/llvm/Value.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Value.h?rev=108408&r1=108407&r2=108408&view=diff ============================================================================== --- llvm/trunk/include/llvm/Value.h (original) +++ llvm/trunk/include/llvm/Value.h Thu Jul 15 00:14:01 2010 @@ -266,6 +266,10 @@ SubclassOptionalData &= V->SubclassOptionalData; } + /// hasValueHandle - Return true if there is a value handle associated with + /// this value. + bool hasValueHandle() const { return HasValueHandle; } + // Methods for support type inquiry through isa, cast, and dyn_cast: static inline bool classof(const Value *) { return true; // Values are always values. From sabre at nondot.org Thu Jul 15 00:17:36 2010 From: sabre at nondot.org (Chris Lattner) Date: Thu, 15 Jul 2010 05:17:36 -0000 Subject: [llvm-commits] [llvm] r108409 - /llvm/trunk/test/Makefile Message-ID: <20100715051736.563132A6C12C@llvm.org> Author: lattner Date: Thu Jul 15 00:17:36 2010 New Revision: 108409 URL: http://llvm.org/viewvc/llvm-project?rev=108409&view=rev Log: see comment. Modified: llvm/trunk/test/Makefile Modified: llvm/trunk/test/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Makefile?rev=108409&r1=108408&r2=108409&view=diff ============================================================================== --- llvm/trunk/test/Makefile (original) +++ llvm/trunk/test/Makefile Thu Jul 15 00:17:36 2010 @@ -202,3 +202,7 @@ -e "s#@ENABLE_SHARED@#$(ENABLE_SHARED)#g" \ -e "s#@SHLIBPATH_VAR@#$(SHLIBPATH_VAR)#g" \ $(PROJ_SRC_DIR)/Unit/lit.site.cfg.in > $@ + +# Daniel hates Chris. +chris-lit: + make check-lit LIT_ARGS='-j16 -s' From isanbard at gmail.com Thu Jul 15 00:56:32 2010 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 15 Jul 2010 05:56:32 -0000 Subject: [llvm-commits] [llvm] r108411 - in /llvm/trunk/lib/CodeGen: CriticalAntiDepBreaker.cpp CriticalAntiDepBreaker.h Message-ID: <20100715055632.76FE32A6C12C@llvm.org> Author: void Date: Thu Jul 15 00:56:32 2010 New Revision: 108411 URL: http://llvm.org/viewvc/llvm-project?rev=108411&view=rev Log: Use std::vector instead of a hard-coded array. The length of that array could get *very* large, but we only need it to be the size of thenumber of pregs. Modified: llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.h Modified: llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp?rev=108411&r1=108410&r2=108411&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp (original) +++ llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp Thu Jul 15 00:56:32 2010 @@ -34,6 +34,9 @@ TRI(MF.getTarget().getRegisterInfo()), AllocatableSet(TRI->getAllocatableSet(MF)) { + Classes.reserve(TRI->getNumRegs()); + KillIndices.reserve(TRI->getNumRegs()); + DefIndices.reserve(TRI->getNumRegs()); } CriticalAntiDepBreaker::~CriticalAntiDepBreaker() { @@ -41,8 +44,7 @@ void CriticalAntiDepBreaker::StartBlock(MachineBasicBlock *BB) { // Clear out the register class data. - std::fill(Classes, array_endof(Classes), - static_cast(0)); + Classes.clear(); // Initialize the indices to indicate that no registers are live. const unsigned BBSize = BB->size(); Modified: llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.h?rev=108411&r1=108410&r2=108411&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.h (original) +++ llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.h Thu Jul 15 00:56:32 2010 @@ -25,6 +25,7 @@ #include "llvm/ADT/BitVector.h" #include "llvm/ADT/SmallSet.h" #include +#include namespace llvm { class TargetInstrInfo; @@ -46,19 +47,18 @@ /// corresponding value is null. If the register is live but used in /// multiple register classes, the corresponding value is -1 casted to a /// pointer. - const TargetRegisterClass * - Classes[TargetRegisterInfo::FirstVirtualRegister]; + std::vector Classes; /// RegRegs - Map registers to all their references within a live range. std::multimap RegRefs; /// KillIndices - The index of the most recent kill (proceding bottom-up), /// or ~0u if the register is not live. - unsigned KillIndices[TargetRegisterInfo::FirstVirtualRegister]; + std::vector KillIndices; /// DefIndices - The index of the most recent complete def (proceding bottom /// up), or ~0u if the register is live. - unsigned DefIndices[TargetRegisterInfo::FirstVirtualRegister]; + std::vector DefIndices; /// KeepRegs - A set of registers which are live and cannot be changed to /// break anti-dependencies. From isanbard at gmail.com Thu Jul 15 01:04:38 2010 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 15 Jul 2010 06:04:38 -0000 Subject: [llvm-commits] [llvm] r108412 - in /llvm/trunk/lib/CodeGen: AggressiveAntiDepBreaker.cpp AggressiveAntiDepBreaker.h Message-ID: <20100715060438.746082A6C12C@llvm.org> Author: void Date: Thu Jul 15 01:04:38 2010 New Revision: 108412 URL: http://llvm.org/viewvc/llvm-project?rev=108412&view=rev Log: Use std::vector instead of a hard-coded array. The length of that array could get *very* large, but we only need it to be the size of the number of pregs. Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp?rev=108412&r1=108411&r2=108412&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp (original) +++ llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp Thu Jul 15 01:04:38 2010 @@ -22,7 +22,6 @@ #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" -#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" @@ -42,6 +41,8 @@ AggressiveAntiDepState::AggressiveAntiDepState(const unsigned TargetRegs, MachineBasicBlock *BB) : NumTargetRegs(TargetRegs), GroupNodes(TargetRegs, 0) { + KillIndices.reserve(TargetRegs); + DefIndices.reserve(TargetRegs); const unsigned BBSize = BB->size(); for (unsigned i = 0; i < NumTargetRegs; ++i) { @@ -145,8 +146,8 @@ State = new AggressiveAntiDepState(TRI->getNumRegs(), BB); bool IsReturnBlock = (!BB->empty() && BB->back().getDesc().isReturn()); - unsigned *KillIndices = State->GetKillIndices(); - unsigned *DefIndices = State->GetDefIndices(); + std::vector &KillIndices = State->GetKillIndices(); + std::vector &DefIndices = State->GetDefIndices(); // Determine the live-out physregs for this block. if (IsReturnBlock) { @@ -226,7 +227,7 @@ DEBUG(MI->dump()); DEBUG(dbgs() << "\tRegs:"); - unsigned *DefIndices = State->GetDefIndices(); + std::vector &DefIndices = State->GetDefIndices(); for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { // If Reg is current live, then mark that it can't be renamed as // we don't know the extent of its live-range anymore (now that it @@ -328,8 +329,8 @@ const char *tag, const char *header, const char *footer) { - unsigned *KillIndices = State->GetKillIndices(); - unsigned *DefIndices = State->GetDefIndices(); + std::vector &KillIndices = State->GetKillIndices(); + std::vector &DefIndices = State->GetDefIndices(); std::multimap& RegRefs = State->GetRegRefs(); @@ -364,7 +365,7 @@ void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI, unsigned Count, std::set& PassthruRegs) { - unsigned *DefIndices = State->GetDefIndices(); + std::vector &DefIndices = State->GetDefIndices(); std::multimap& RegRefs = State->GetRegRefs(); @@ -560,8 +561,8 @@ unsigned AntiDepGroupIndex, RenameOrderType& RenameOrder, std::map &RenameMap) { - unsigned *KillIndices = State->GetKillIndices(); - unsigned *DefIndices = State->GetDefIndices(); + std::vector &KillIndices = State->GetKillIndices(); + std::vector &DefIndices = State->GetDefIndices(); std::multimap& RegRefs = State->GetRegRefs(); @@ -733,8 +734,8 @@ MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, unsigned InsertPosIndex) { - unsigned *KillIndices = State->GetKillIndices(); - unsigned *DefIndices = State->GetDefIndices(); + std::vector &KillIndices = State->GetKillIndices(); + std::vector &DefIndices = State->GetDefIndices(); std::multimap& RegRefs = State->GetRegRefs(); Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h?rev=108412&r1=108411&r2=108412&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h (original) +++ llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h Thu Jul 15 01:04:38 2010 @@ -24,12 +24,14 @@ #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/ScheduleDAG.h" #include "llvm/Target/TargetSubtarget.h" -#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/SmallSet.h" #include +#include namespace llvm { + class TargetRegisterInfo; + /// Class AggressiveAntiDepState /// Contains all the state necessary for anti-dep breaking. class AggressiveAntiDepState { @@ -59,27 +61,27 @@ /// currently representing the group that the register belongs to. /// Register 0 is always represented by the 0 group, a group /// composed of registers that are not eligible for anti-aliasing. - unsigned GroupNodeIndices[TargetRegisterInfo::FirstVirtualRegister]; + std::vector GroupNodeIndices; /// RegRefs - Map registers to all their references within a live range. std::multimap RegRefs; /// KillIndices - The index of the most recent kill (proceding bottom-up), /// or ~0u if the register is not live. - unsigned KillIndices[TargetRegisterInfo::FirstVirtualRegister]; + std::vector KillIndices; /// DefIndices - The index of the most recent complete def (proceding bottom /// up), or ~0u if the register is live. - unsigned DefIndices[TargetRegisterInfo::FirstVirtualRegister]; + std::vector DefIndices; public: AggressiveAntiDepState(const unsigned TargetRegs, MachineBasicBlock *BB); /// GetKillIndices - Return the kill indices. - unsigned *GetKillIndices() { return KillIndices; } + std::vector &GetKillIndices() { return KillIndices; } /// GetDefIndices - Return the define indices. - unsigned *GetDefIndices() { return DefIndices; } + std::vector &GetDefIndices() { return DefIndices; } /// GetRegRefs - Return the RegRefs map. std::multimap& GetRegRefs() { return RegRefs; } From isanbard at gmail.com Thu Jul 15 01:05:18 2010 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 15 Jul 2010 06:05:18 -0000 Subject: [llvm-commits] [llvm] r108413 - in /llvm/trunk/lib/CodeGen: AggressiveAntiDepBreaker.cpp AggressiveAntiDepBreaker.h Message-ID: <20100715060518.3AD252A6C12C@llvm.org> Author: void Date: Thu Jul 15 01:05:18 2010 New Revision: 108413 URL: http://llvm.org/viewvc/llvm-project?rev=108413&view=rev Log: Fix headers. Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp?rev=108413&r1=108412&r2=108413&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp (original) +++ llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp Thu Jul 15 01:05:18 2010 @@ -22,6 +22,7 @@ #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h?rev=108413&r1=108412&r2=108413&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h (original) +++ llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h Thu Jul 15 01:05:18 2010 @@ -31,7 +31,6 @@ namespace llvm { class TargetRegisterInfo; - /// Class AggressiveAntiDepState /// Contains all the state necessary for anti-dep breaking. class AggressiveAntiDepState { From sabre at nondot.org Thu Jul 15 01:06:04 2010 From: sabre at nondot.org (Chris Lattner) Date: Thu, 15 Jul 2010 06:06:04 -0000 Subject: [llvm-commits] [llvm] r108414 - /llvm/trunk/lib/Transforms/Utils/Local.cpp Message-ID: <20100715060605.03E122A6C12C@llvm.org> Author: lattner Date: Thu Jul 15 01:06:04 2010 New Revision: 108414 URL: http://llvm.org/viewvc/llvm-project?rev=108414&view=rev Log: make various clients of ReplaceAndSimplifyAllUses tolerate it *changing* the things it replaces, not just causing them to drop to null. There is no functionality change yet, but this is required for a subsequent patch. Modified: llvm/trunk/lib/Transforms/Utils/Local.cpp Modified: llvm/trunk/lib/Transforms/Utils/Local.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/Local.cpp?rev=108414&r1=108413&r2=108414&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/Local.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/Local.cpp Thu Jul 15 01:06:04 2010 @@ -306,7 +306,7 @@ WeakVH BIHandle(BI); ReplaceAndSimplifyAllUses(Inst, V, TD); MadeChange = true; - if (BIHandle == 0) + if (BIHandle != BI) BI = BB->begin(); continue; } @@ -354,12 +354,13 @@ // value into all of its uses. assert(PNV != PN && "hasConstantValue broken"); + Value *OldPhiIt = PhiIt; ReplaceAndSimplifyAllUses(PN, PNV, TD); // If recursive simplification ended up deleting the next PHI node we would // iterate to, then our iterator is invalid, restart scanning from the top // of the block. - if (PhiIt == 0) PhiIt = &BB->front(); + if (PhiIt != OldPhiIt) PhiIt = &BB->front(); } } From sabre at nondot.org Thu Jul 15 01:36:08 2010 From: sabre at nondot.org (Chris Lattner) Date: Thu, 15 Jul 2010 06:36:08 -0000 Subject: [llvm-commits] [llvm] r108415 - in /llvm/trunk: lib/Analysis/InstructionSimplify.cpp test/Transforms/JumpThreading/crash.ll Message-ID: <20100715063609.0397E2A6C12C@llvm.org> Author: lattner Date: Thu Jul 15 01:36:08 2010 New Revision: 108415 URL: http://llvm.org/viewvc/llvm-project?rev=108415&view=rev Log: Fix PR7647, handling the case when 'To' ends up being mutated by recursive simplification. This also enhances ReplaceAndSimplifyAllUses to actually do a real RAUW at the end of it, which updates any value handles pointing to "From" to start pointing to "To". This seems useful for debug info and random other VH users. Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp llvm/trunk/test/Transforms/JumpThreading/crash.ll Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InstructionSimplify.cpp?rev=108415&r1=108414&r2=108415&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/InstructionSimplify.cpp (original) +++ llvm/trunk/lib/Analysis/InstructionSimplify.cpp Thu Jul 15 01:36:08 2010 @@ -440,27 +440,47 @@ const TargetData *TD) { assert(From != To && "ReplaceAndSimplifyAllUses(X,X) is not valid!"); - // FromHandle - This keeps a weakvh on the from value so that we can know if - // it gets deleted out from under us in a recursive simplification. + // FromHandle/ToHandle - This keeps a WeakVH on the from/to values so that + // we can know if it gets deleted out from under us or replaced in a + // recursive simplification. WeakVH FromHandle(From); + WeakVH ToHandle(To); while (!From->use_empty()) { // Update the instruction to use the new value. - Use &U = From->use_begin().getUse(); - Instruction *User = cast(U.getUser()); - U = To; + Use &TheUse = From->use_begin().getUse(); + Instruction *User = cast(TheUse.getUser()); + TheUse = To; + + // Check to see if the instruction can be folded due to the operand + // replacement. For example changing (or X, Y) into (or X, -1) can replace + // the 'or' with -1. + Value *SimplifiedVal; + { + // Sanity check to make sure 'User' doesn't dangle across + // SimplifyInstruction. + AssertingVH<> UserHandle(User); - // See if we can simplify it. - if (Value *V = SimplifyInstruction(User, TD)) { - // Recursively simplify this. - ReplaceAndSimplifyAllUses(User, V, TD); - - // If the recursive simplification ended up revisiting and deleting 'From' - // then we're done. - if (FromHandle == 0) - return; + SimplifiedVal = SimplifyInstruction(User, TD); + if (SimplifiedVal == 0) continue; } + + // Recursively simplify this user to the new value. + ReplaceAndSimplifyAllUses(User, SimplifiedVal, TD); + From = dyn_cast_or_null((Value*)FromHandle); + To = ToHandle; + + assert(ToHandle && "To value deleted by recursive simplification?"); + + // If the recursive simplification ended up revisiting and deleting + // 'From' then we're done. + if (From == 0) + return; } + + // If 'From' has value handles referring to it, do a real RAUW to update them. + From->replaceAllUsesWith(To); + From->eraseFromParent(); } Modified: llvm/trunk/test/Transforms/JumpThreading/crash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/JumpThreading/crash.ll?rev=108415&r1=108414&r2=108415&view=diff ============================================================================== --- llvm/trunk/test/Transforms/JumpThreading/crash.ll (original) +++ llvm/trunk/test/Transforms/JumpThreading/crash.ll Thu Jul 15 01:36:08 2010 @@ -387,3 +387,50 @@ ret void } +; PR7647 +define void @test15() nounwind { +entry: + ret void + +if.then237: + br label %lbl_664 + +lbl_596: ; preds = %lbl_664, %for.end37 + volatile store i64 undef, i64* undef, align 4 + br label %for.cond111 + +for.cond111: ; preds = %safe_sub_func_int64_t_s_s.exit, %lbl_596 + %storemerge = phi i8 [ undef, %cond.true.i100 ], [ 22, %lbl_596 ] ; [#uses=1] + %l_678.5 = phi i64 [ %l_678.3, %cond.true.i100 ], [ undef, %lbl_596 ] ; [#uses=2] + %cmp114 = icmp slt i8 %storemerge, -2 ; [#uses=1] + br i1 %cmp114, label %lbl_664, label %if.end949 + +lbl_664: ; preds = %for.end1058, %if.then237, %for.cond111 + %l_678.3 = phi i64 [ %l_678.5, %for.cond111 ], [ %l_678.2, %for.cond1035 ], [ 5, %if.then237 ] ; [#uses=1] + %tobool118 = icmp eq i32 undef, 0 ; [#uses=1] + br i1 %tobool118, label %cond.true.i100, label %lbl_596 + +cond.true.i100: ; preds = %for.inc120 + br label %for.cond111 + +lbl_709: + br label %if.end949 + +for.cond603: ; preds = %for.body607, %if.end336 + br i1 undef, label %for.cond603, label %if.end949 + +if.end949: ; preds = %for.cond603, %lbl_709, %for.cond111 + %l_678.2 = phi i64 [ %l_678.5, %for.cond111 ], [ undef, %lbl_709 ], [ 5, %for.cond603 ] ; [#uses=1] + br label %for.body1016 + +for.body1016: ; preds = %for.cond1012 + br label %for.body1016 + +for.cond1035: ; preds = %for.inc1055, %if.then1026 + br i1 undef, label %for.cond1040, label %lbl_664 + +for.cond1040: ; preds = %for.body1044, %for.cond1035 + ret void +} + + From kremenek at apple.com Thu Jul 15 01:36:57 2010 From: kremenek at apple.com (Ted Kremenek) Date: Thu, 15 Jul 2010 06:36:57 -0000 Subject: [llvm-commits] [llvm] r108416 - /llvm/trunk/Makefile.rules Message-ID: <20100715063657.3D8E02A6C12C@llvm.org> Author: kremenek Date: Thu Jul 15 01:36:57 2010 New Revision: 108416 URL: http://llvm.org/viewvc/llvm-project?rev=108416&view=rev Log: Correctly set rpath on Mac OS X for executable tools. Note that I am not certain this is the best fix; the code immediately above looks confused, as it first checks to see if we are NOT on Darwin and then checks the Darwin version number. This fix allows c-index-test (in Clang) to run outside of running the regression test suite. I would appreciate if someone reviewed this. Modified: llvm/trunk/Makefile.rules Modified: llvm/trunk/Makefile.rules URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=108416&r1=108415&r2=108416&view=diff ============================================================================== --- llvm/trunk/Makefile.rules (original) +++ llvm/trunk/Makefile.rules Thu Jul 15 01:36:57 2010 @@ -632,7 +632,12 @@ endif endif endif +else +ifneq ($(DARWIN_MAJVERS),4) + LD.Flags += $(RPATH) -Wl, at executable_path/../lib endif +endif + #---------------------------------------------------------- # Options To Invoke Tools From nicholas at mxc.ca Thu Jul 15 01:48:56 2010 From: nicholas at mxc.ca (Nick Lewycky) Date: Thu, 15 Jul 2010 06:48:56 -0000 Subject: [llvm-commits] [llvm] r108417 - /llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp Message-ID: <20100715064856.78FB02A6C12C@llvm.org> Author: nicholas Date: Thu Jul 15 01:48:56 2010 New Revision: 108417 URL: http://llvm.org/viewvc/llvm-project?rev=108417&view=rev Log: Disable aliases on all platforms. Modified: llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp Modified: llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp?rev=108417&r1=108416&r2=108417&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp Thu Jul 15 01:48:56 2010 @@ -603,6 +603,10 @@ } static void AliasGToF(Function *F, Function *G) { + // Darwin will trigger llvm_unreachable if asked to codegen an alias + return ThunkGToF(F, G); + +#if 0 if (!G->hasExternalLinkage() && !G->hasLocalLinkage() && !G->hasWeakLinkage()) return ThunkGToF(F, G); @@ -614,6 +618,7 @@ GA->setVisibility(G->getVisibility()); G->replaceAllUsesWith(GA); G->eraseFromParent(); +#endif } static bool fold(std::vector &FnVec, unsigned i, unsigned j) { From nicholas at mxc.ca Thu Jul 15 01:51:22 2010 From: nicholas at mxc.ca (Nick Lewycky) Date: Thu, 15 Jul 2010 06:51:22 -0000 Subject: [llvm-commits] [llvm] r108418 - /llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp Message-ID: <20100715065122.966F42A6C12C@llvm.org> Author: nicholas Date: Thu Jul 15 01:51:22 2010 New Revision: 108418 URL: http://llvm.org/viewvc/llvm-project?rev=108418&view=rev Log: This is a full sentence. Modified: llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp Modified: llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp?rev=108418&r1=108417&r2=108418&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp Thu Jul 15 01:51:22 2010 @@ -603,7 +603,7 @@ } static void AliasGToF(Function *F, Function *G) { - // Darwin will trigger llvm_unreachable if asked to codegen an alias + // Darwin will trigger llvm_unreachable if asked to codegen an alias. return ThunkGToF(F, G); #if 0 From sabre at nondot.org Thu Jul 15 01:51:46 2010 From: sabre at nondot.org (Chris Lattner) Date: Thu, 15 Jul 2010 06:51:46 -0000 Subject: [llvm-commits] [llvm] r108419 - in /llvm/trunk/lib/CodeGen: AggressiveAntiDepBreaker.cpp AggressiveAntiDepBreaker.h CriticalAntiDepBreaker.cpp CriticalAntiDepBreaker.h Message-ID: <20100715065146.37BC62A6C12C@llvm.org> Author: lattner Date: Thu Jul 15 01:51:46 2010 New Revision: 108419 URL: http://llvm.org/viewvc/llvm-project?rev=108419&view=rev Log: revert bill's patches in an attempt to fix the buildbot. Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.h Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp?rev=108419&r1=108418&r2=108419&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp (original) +++ llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp Thu Jul 15 01:51:46 2010 @@ -42,8 +42,6 @@ AggressiveAntiDepState::AggressiveAntiDepState(const unsigned TargetRegs, MachineBasicBlock *BB) : NumTargetRegs(TargetRegs), GroupNodes(TargetRegs, 0) { - KillIndices.reserve(TargetRegs); - DefIndices.reserve(TargetRegs); const unsigned BBSize = BB->size(); for (unsigned i = 0; i < NumTargetRegs; ++i) { @@ -147,8 +145,8 @@ State = new AggressiveAntiDepState(TRI->getNumRegs(), BB); bool IsReturnBlock = (!BB->empty() && BB->back().getDesc().isReturn()); - std::vector &KillIndices = State->GetKillIndices(); - std::vector &DefIndices = State->GetDefIndices(); + unsigned *KillIndices = State->GetKillIndices(); + unsigned *DefIndices = State->GetDefIndices(); // Determine the live-out physregs for this block. if (IsReturnBlock) { @@ -228,7 +226,7 @@ DEBUG(MI->dump()); DEBUG(dbgs() << "\tRegs:"); - std::vector &DefIndices = State->GetDefIndices(); + unsigned *DefIndices = State->GetDefIndices(); for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { // If Reg is current live, then mark that it can't be renamed as // we don't know the extent of its live-range anymore (now that it @@ -330,8 +328,8 @@ const char *tag, const char *header, const char *footer) { - std::vector &KillIndices = State->GetKillIndices(); - std::vector &DefIndices = State->GetDefIndices(); + unsigned *KillIndices = State->GetKillIndices(); + unsigned *DefIndices = State->GetDefIndices(); std::multimap& RegRefs = State->GetRegRefs(); @@ -366,7 +364,7 @@ void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI, unsigned Count, std::set& PassthruRegs) { - std::vector &DefIndices = State->GetDefIndices(); + unsigned *DefIndices = State->GetDefIndices(); std::multimap& RegRefs = State->GetRegRefs(); @@ -562,8 +560,8 @@ unsigned AntiDepGroupIndex, RenameOrderType& RenameOrder, std::map &RenameMap) { - std::vector &KillIndices = State->GetKillIndices(); - std::vector &DefIndices = State->GetDefIndices(); + unsigned *KillIndices = State->GetKillIndices(); + unsigned *DefIndices = State->GetDefIndices(); std::multimap& RegRefs = State->GetRegRefs(); @@ -735,8 +733,8 @@ MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, unsigned InsertPosIndex) { - std::vector &KillIndices = State->GetKillIndices(); - std::vector &DefIndices = State->GetDefIndices(); + unsigned *KillIndices = State->GetKillIndices(); + unsigned *DefIndices = State->GetDefIndices(); std::multimap& RegRefs = State->GetRegRefs(); Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h?rev=108419&r1=108418&r2=108419&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h (original) +++ llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h Thu Jul 15 01:51:46 2010 @@ -24,13 +24,12 @@ #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/ScheduleDAG.h" #include "llvm/Target/TargetSubtarget.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/SmallSet.h" #include -#include namespace llvm { - class TargetRegisterInfo; /// Class AggressiveAntiDepState /// Contains all the state necessary for anti-dep breaking. class AggressiveAntiDepState { @@ -60,27 +59,27 @@ /// currently representing the group that the register belongs to. /// Register 0 is always represented by the 0 group, a group /// composed of registers that are not eligible for anti-aliasing. - std::vector GroupNodeIndices; + unsigned GroupNodeIndices[TargetRegisterInfo::FirstVirtualRegister]; /// RegRefs - Map registers to all their references within a live range. std::multimap RegRefs; /// KillIndices - The index of the most recent kill (proceding bottom-up), /// or ~0u if the register is not live. - std::vector KillIndices; + unsigned KillIndices[TargetRegisterInfo::FirstVirtualRegister]; /// DefIndices - The index of the most recent complete def (proceding bottom /// up), or ~0u if the register is live. - std::vector DefIndices; + unsigned DefIndices[TargetRegisterInfo::FirstVirtualRegister]; public: AggressiveAntiDepState(const unsigned TargetRegs, MachineBasicBlock *BB); /// GetKillIndices - Return the kill indices. - std::vector &GetKillIndices() { return KillIndices; } + unsigned *GetKillIndices() { return KillIndices; } /// GetDefIndices - Return the define indices. - std::vector &GetDefIndices() { return DefIndices; } + unsigned *GetDefIndices() { return DefIndices; } /// GetRegRefs - Return the RegRefs map. std::multimap& GetRegRefs() { return RegRefs; } Modified: llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp?rev=108419&r1=108418&r2=108419&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp (original) +++ llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp Thu Jul 15 01:51:46 2010 @@ -34,9 +34,6 @@ TRI(MF.getTarget().getRegisterInfo()), AllocatableSet(TRI->getAllocatableSet(MF)) { - Classes.reserve(TRI->getNumRegs()); - KillIndices.reserve(TRI->getNumRegs()); - DefIndices.reserve(TRI->getNumRegs()); } CriticalAntiDepBreaker::~CriticalAntiDepBreaker() { @@ -44,7 +41,8 @@ void CriticalAntiDepBreaker::StartBlock(MachineBasicBlock *BB) { // Clear out the register class data. - Classes.clear(); + std::fill(Classes, array_endof(Classes), + static_cast(0)); // Initialize the indices to indicate that no registers are live. const unsigned BBSize = BB->size(); Modified: llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.h?rev=108419&r1=108418&r2=108419&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.h (original) +++ llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.h Thu Jul 15 01:51:46 2010 @@ -25,7 +25,6 @@ #include "llvm/ADT/BitVector.h" #include "llvm/ADT/SmallSet.h" #include -#include namespace llvm { class TargetInstrInfo; @@ -47,18 +46,19 @@ /// corresponding value is null. If the register is live but used in /// multiple register classes, the corresponding value is -1 casted to a /// pointer. - std::vector Classes; + const TargetRegisterClass * + Classes[TargetRegisterInfo::FirstVirtualRegister]; /// RegRegs - Map registers to all their references within a live range. std::multimap RegRefs; /// KillIndices - The index of the most recent kill (proceding bottom-up), /// or ~0u if the register is not live. - std::vector KillIndices; + unsigned KillIndices[TargetRegisterInfo::FirstVirtualRegister]; /// DefIndices - The index of the most recent complete def (proceding bottom /// up), or ~0u if the register is live. - std::vector DefIndices; + unsigned DefIndices[TargetRegisterInfo::FirstVirtualRegister]; /// KeepRegs - A set of registers which are live and cannot be changed to /// break anti-dependencies. From clattner at apple.com Thu Jul 15 02:06:34 2010 From: clattner at apple.com (Chris Lattner) Date: Thu, 15 Jul 2010 00:06:34 -0700 Subject: [llvm-commits] turn on function merging In-Reply-To: <4C396EC3.40709@mxc.ca> References: <4C396EC3.40709@mxc.ca> Message-ID: On Jul 11, 2010, at 12:12 AM, Nick Lewycky wrote: > I'd like to turn on the function merging pass by default (patch attached). Function merging is already in the tree and I've been testing it locally for a while. It works great and doesn't do undue harm to my build times. > > Functions are merged when they are identical under a comparison that treats all pointers as equivalent. So i8* and i32* are considered equivalent types, so long as you never load one which would produce an i8 as that's different from i32. Here is some general code review comments: Please comment the code, each method should get a function comment. The linkage code needs comments explaining what is going on. Please rename 'hash' and 'fold' to something less generic, and give AliasGToF a longer name that says what it does. The compare methods should be static or const. Stuff like this: SmallVector Indices1, Indices2; for (GetElementPtrInst::const_op_iterator I = GEP1->idx_begin(), E = GEP1->idx_end(); I != E; ++I) { Indices1.push_back(*I); } for (GetElementPtrInst::const_op_iterator I = GEP2->idx_begin(), E = GEP2->idx_end(); I != E; ++I) { Indices2.push_back(*I); } Should be able to be written as: SmallVector Indices1(GEP1->idx_begin(), GEP1->idx_end()); SmallVector Indices2(GEP2->idx_begin(), GEP2->idx_end()); I don't understand this logic: bool MergeFunctions::compare(const Value *V1, const Value *V2) { if (V1 == LHS || V1 == RHS) if (V2 == LHS || V2 == RHS) return true; Also, related to that, making LHS and RHS be members of the MergeFunctions pass is kinda gross. It would be better to split the comparison stuff out to its own trivial comparison class, using a pattern like this: class FunctionComparisonator { Function *LHS, *RHS; ... public: FunctionComparisonator(...); bool Compare(); private: ... }; if (FunctionComparisonator(LHSFunc, RHSFunc).Compare()) ... That will also partition the comparison logic cleanly from the pass and transformation mechanics. This is some seriously crazy indentation, it hurts: :) } } break; } break; It's unclear to me why you use "std::map > " as your hashing/uniquing data structure instead of a densemap. Wouldn't it substantially simplify the code to use DenseMap where YourType just contains a Function* and a cached hash? Then you just define your hash and equality predicates and the hash table does everything else? I'll take another look after this changes go in, thanks for working on this! -Chris From baldrick at free.fr Thu Jul 15 02:12:05 2010 From: baldrick at free.fr (Duncan Sands) Date: Thu, 15 Jul 2010 09:12:05 +0200 Subject: [llvm-commits] [llvm] r108351 - /llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp In-Reply-To: <20100714195216.C609C2A6C12C@llvm.org> References: <20100714195216.C609C2A6C12C@llvm.org> Message-ID: <4C3EB4C5.8030106@free.fr> Hi Owen, > This allows us to eliminate the short circuit in (x&1)&&(x&2). testcase? > + Instruction *BonusInst = 0; > + if (&*FrontIt != Cond&& > + (*FrontIt).hasOneUse()&& *(*FrontIt).use_begin() == Cond&& > + (*FrontIt).isSafeToSpeculativelyExecute()&& > + !(*FrontIt).mayReadFromMemory()) { Why the check on mayReadFromMemory? Ciao, Duncan. From baldrick at free.fr Thu Jul 15 02:49:29 2010 From: baldrick at free.fr (Duncan Sands) Date: Thu, 15 Jul 2010 09:49:29 +0200 Subject: [llvm-commits] [llvm] r108378 - in /llvm/trunk/lib/Transforms/InstCombine: InstCombineAndOrXor.cpp InstCombineSelect.cpp In-Reply-To: <20100714233351.814D82A6C12C@llvm.org> References: <20100714233351.814D82A6C12C@llvm.org> Message-ID: <4C3EBD89.3080704@free.fr> Hi Owen, > + // (icmp ne (A& C1) 0)& (icmp ne (A& C2), 0) --> missing comma before first 0. > + // select (or (A == 0) (B == 0)) T, F--> select (and (A != 0) (B != 0)) F, T Here you use a different style ("or" rather than | etc). Ciao, Duncan. From echristo at apple.com Thu Jul 15 02:49:30 2010 From: echristo at apple.com (Eric Christopher) Date: Thu, 15 Jul 2010 07:49:30 -0000 Subject: [llvm-commits] [llvm] r108420 - /llvm/trunk/include/llvm/Target/TargetInstrInfo.h Message-ID: <20100715074930.6A9082A6C12D@llvm.org> Author: echristo Date: Thu Jul 15 02:49:30 2010 New Revision: 108420 URL: http://llvm.org/viewvc/llvm-project?rev=108420&view=rev Log: 80-col. Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=108420&r1=108419&r2=108420&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Thu Jul 15 02:49:30 2010 @@ -371,7 +371,7 @@ unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { - assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!"); + assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!"); } /// loadRegFromStackSlot - Load the specified register of the given register @@ -383,7 +383,7 @@ unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { - assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!"); + assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!"); } /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee @@ -392,7 +392,7 @@ /// storeRegToStackSlot(). Returns false otherwise. virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, - const std::vector &CSI, + const std::vector &CSI, const TargetRegisterInfo *TRI) const { return false; } @@ -457,7 +457,7 @@ /// take care of adding a MachineMemOperand to the newly created instruction. virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, MachineInstr* MI, - const SmallVectorImpl &Ops, + const SmallVectorImpl &Ops, MachineInstr* LoadMI) const { return 0; } @@ -501,7 +501,7 @@ /// only differences between the two addresses are the offset. It also returns /// the offsets by reference. virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, - int64_t &Offset1, int64_t &Offset2) const { + int64_t &Offset1, int64_t &Offset2) const { return false; } From echristo at apple.com Thu Jul 15 03:21:42 2010 From: echristo at apple.com (Eric Christopher) Date: Thu, 15 Jul 2010 01:21:42 -0700 Subject: [llvm-commits] [llvm] r108416 - /llvm/trunk/Makefile.rules In-Reply-To: <20100715063657.3D8E02A6C12C@llvm.org> References: <20100715063657.3D8E02A6C12C@llvm.org> Message-ID: <68DEA7C2-5CB3-4D9E-869D-5803213E0279@apple.com> On Jul 14, 2010, at 11:36 PM, Ted Kremenek wrote: > Author: kremenek > Date: Thu Jul 15 01:36:57 2010 > New Revision: 108416 > > URL: http://llvm.org/viewvc/llvm-project?rev=108416&view=rev > Log: > Correctly set rpath on Mac OS X for executable tools. Note that I am not certain this is the best fix; the code immediately above looks confused, as it first checks to see if we are NOT on Darwin and then checks the Darwin version number. This fix allows c-index-test (in Clang) to run outside of running the regression test suite. I would appreciate if someone reviewed this. Yeah, line 625 can probably go away. I'll test that in the morning. -eric From ggreif at gmail.com Thu Jul 15 05:19:23 2010 From: ggreif at gmail.com (Gabor Greif) Date: Thu, 15 Jul 2010 10:19:23 -0000 Subject: [llvm-commits] [llvm] r108421 - /llvm/trunk/lib/Analysis/ProfileInfo.cpp Message-ID: <20100715101923.A7F482A6C12C@llvm.org> Author: ggreif Date: Thu Jul 15 05:19:23 2010 New Revision: 108421 URL: http://llvm.org/viewvc/llvm-project?rev=108421&view=rev Log: cache another dereferenced iterator Modified: llvm/trunk/lib/Analysis/ProfileInfo.cpp Modified: llvm/trunk/lib/Analysis/ProfileInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ProfileInfo.cpp?rev=108421&r1=108420&r2=108421&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ProfileInfo.cpp (original) +++ llvm/trunk/lib/Analysis/ProfileInfo.cpp Thu Jul 15 05:19:23 2010 @@ -71,22 +71,24 @@ // Are there zero predecessors of this block? if (PI == PE) { - Edge e = getEdge(0,BB); + Edge e = getEdge(0, BB); Count = getEdgeWeight(e); } else { // Otherwise, if there are predecessors, the execution count of this block is // the sum of the edge frequencies from the incoming edges. std::set ProcessedPreds; Count = 0; - for (; PI != PE; ++PI) - if (ProcessedPreds.insert(*PI).second) { - double w = getEdgeWeight(getEdge(*PI, BB)); + for (; PI != PE; ++PI) { + const BasicBlock *P = *PI; + if (ProcessedPreds.insert(P).second) { + double w = getEdgeWeight(getEdge(P, BB)); if (w == MissingValue) { Count = MissingValue; break; } Count += w; } + } } // If the predecessors did not suffice to get block weight, try successors. From baldrick at free.fr Thu Jul 15 09:53:47 2010 From: baldrick at free.fr (Duncan Sands) Date: Thu, 15 Jul 2010 16:53:47 +0200 Subject: [llvm-commits] turn on function merging In-Reply-To: <4C396EC3.40709@mxc.ca> References: <4C396EC3.40709@mxc.ca> Message-ID: <4C3F20FB.9040609@free.fr> Hi Nick, I found the following problem by running mergefunc on the dragonegg testsuite: $ opt -mergefunc merge.ll -disable-output opt: /home/duncan/LLVM/llvm.top/llvm/lib/VMCore/Instructions.cpp:2662: llvm::BitCastInst::BitCastInst(llvm::Value*, const llvm::Type*, const llvm::Twine&, llvm::BasicBlock*): Assertion `castIsValid(getOpcode(), S, Ty) && "Illegal BitCast"' failed. See attached file. Ciao, Duncan. -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: merge.ll Url: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100715/659c6862/attachment.pl From resistor at mac.com Thu Jul 15 09:59:37 2010 From: resistor at mac.com (Owen Anderson) Date: Thu, 15 Jul 2010 07:59:37 -0700 Subject: [llvm-commits] [llvm] r108351 - /llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp In-Reply-To: <4C3EB4C5.8030106@free.fr> References: <20100714195216.C609C2A6C12C@llvm.org> <4C3EB4C5.8030106@free.fr> Message-ID: <2B9ADA84-2EFD-4120-968A-3C6FA32DD259@mac.com> On Jul 15, 2010, at 12:12 AM, Duncan Sands wrote: > >> + Instruction *BonusInst = 0; >> + if (&*FrontIt != Cond&& >> + (*FrontIt).hasOneUse()&& *(*FrontIt).use_begin() == Cond&& >> + (*FrontIt).isSafeToSpeculativelyExecute()&& >> + !(*FrontIt).mayReadFromMemory()) { > > Why the check on mayReadFromMemory? We don't want to speculatively execute a load before a null check. --Owen -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100715/9a6b2913/attachment.html From resistor at mac.com Thu Jul 15 10:00:24 2010 From: resistor at mac.com (Owen Anderson) Date: Thu, 15 Jul 2010 15:00:24 -0000 Subject: [llvm-commits] [llvm] r108422 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineAndOrXor.cpp lib/Transforms/InstCombine/InstCombineSelect.cpp test/Transforms/InstCombine/bit-checks.ll Message-ID: <20100715150024.103622A6C12C@llvm.org> Author: resistor Date: Thu Jul 15 10:00:23 2010 New Revision: 108422 URL: http://llvm.org/viewvc/llvm-project?rev=108422&view=rev Log: Reapply r108378, with bugfixes, testcase, and improved comment formatting. This now passes LIT, nighty test, and llvm-gcc bootstrap on my machine. Added: llvm/trunk/test/Transforms/InstCombine/bit-checks.ll Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp?rev=108422&r1=108421&r2=108422&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp Thu Jul 15 10:00:23 2010 @@ -472,6 +472,25 @@ Value *NewOr = Builder->CreateOr(Val, Val2); return Builder->CreateICmp(LHSCC, NewOr, LHSCst); } + + // (icmp ne (A & C1), 0) & (icmp ne (A & C2), 0) --> + // (icmp eq (A & (C1|C2)), (C1|C2)) + if (LHSCC == ICmpInst::ICMP_NE && LHSCst->isZero()) { + Instruction *I1 = dyn_cast(Val); + Instruction *I2 = dyn_cast(Val2); + if (I1 && I1->getOpcode() == Instruction::And && + I2 && I2->getOpcode() == Instruction::And && + I1->getOperand(0) == I1->getOperand(0)) { + ConstantInt *CI1 = dyn_cast(I1->getOperand(1)); + ConstantInt *CI2 = dyn_cast(I2->getOperand(1)); + if (CI1 && !CI1->isZero() && CI2 && !CI2->isZero() && + CI1->getValue().operator&(CI2->getValue()) == 0) { + Constant *ConstOr = ConstantExpr::getOr(CI1, CI2); + Value *NewAnd = Builder->CreateAnd(I1->getOperand(0), ConstOr); + return Builder->CreateICmp(ICmpInst::ICMP_EQ, NewAnd, ConstOr); + } + } + } } // From here on, we only handle: Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp?rev=108422&r1=108421&r2=108422&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp Thu Jul 15 10:00:23 2010 @@ -699,6 +699,34 @@ SI.setOperand(2, TrueVal); return &SI; } + + // select (A == 0 | B == 0), T, F--> select (A != 0 & B != 0), F, T + // Note: This is a canonicalization rather than an optimization, and is used + // to expose opportunities to other instcombine transforms. + Instruction* CondInst = dyn_cast(CondVal); + if (CondInst && CondInst->hasOneUse() && + CondInst->getOpcode() == Instruction::Or) { + ICmpInst *LHSCmp = dyn_cast(CondInst->getOperand(0)); + ICmpInst *RHSCmp = dyn_cast(CondInst->getOperand(1)); + if (LHSCmp && LHSCmp->hasOneUse() && + LHSCmp->getPredicate() == ICmpInst::ICMP_EQ && + RHSCmp && RHSCmp->hasOneUse() && + RHSCmp->getPredicate() == ICmpInst::ICMP_EQ) { + ConstantInt* C1 = dyn_cast(LHSCmp->getOperand(1)); + ConstantInt* C2 = dyn_cast(RHSCmp->getOperand(1)); + if (C1 && C1->isZero() && C2 && C2->isZero()) { + LHSCmp->setPredicate(ICmpInst::ICMP_NE); + RHSCmp->setPredicate(ICmpInst::ICMP_NE); + Value *And = + InsertNewInstBefore(BinaryOperator::CreateAnd(LHSCmp, RHSCmp, + "and."+CondVal->getName()), SI); + SI.setOperand(0, And); + SI.setOperand(1, FalseVal); + SI.setOperand(2, TrueVal); + return &SI; + } + } + } return 0; } Added: llvm/trunk/test/Transforms/InstCombine/bit-checks.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/bit-checks.ll?rev=108422&view=auto ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/bit-checks.ll (added) +++ llvm/trunk/test/Transforms/InstCombine/bit-checks.ll Thu Jul 15 10:00:23 2010 @@ -0,0 +1,15 @@ +; This test makes sure that these instructions are properly eliminated. +; +; RUN: opt < %s -instcombine -S | \ +; RUN: not grep {tobool} +; END. +define i32 @main(i32 %argc, i8** %argv) nounwind ssp { +entry: + %and = and i32 %argc, 1 ; [#uses=1] + %tobool = icmp ne i32 %and, 0 ; [#uses=1] + %and2 = and i32 %argc, 2 ; [#uses=1] + %tobool3 = icmp ne i32 %and2, 0 ; [#uses=1] + %or.cond = and i1 %tobool, %tobool3 ; [#uses=1] + %retval.0 = select i1 %or.cond, i32 2, i32 1 ; [#uses=1] + ret i32 %retval.0 +} From gohman at apple.com Thu Jul 15 10:14:45 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 15 Jul 2010 15:14:45 -0000 Subject: [llvm-commits] [llvm] r108424 - in /llvm/trunk: lib/Transforms/Scalar/LoopStrengthReduce.cpp test/CodeGen/X86/lsr-i386.ll Message-ID: <20100715151445.A2AAF2A6C12C@llvm.org> Author: djg Date: Thu Jul 15 10:14:45 2010 New Revision: 108424 URL: http://llvm.org/viewvc/llvm-project?rev=108424&view=rev Log: Watch out for a constant offset cancelling out a base register, forming a zero. This situation arrises in Fortran code with induction variables that start at 1 instead of 0. This fixes PR7651. Added: llvm/trunk/test/CodeGen/X86/lsr-i386.ll Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=108424&r1=108423&r2=108424&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Thu Jul 15 10:14:45 2010 @@ -2362,7 +2362,7 @@ Formula Base) { // TODO: For now, just add the min and max offset, because it usually isn't // worthwhile looking at everything inbetween. - SmallVector Worklist; + SmallVector Worklist; Worklist.push_back(LU.MinOffset); if (LU.MaxOffset != LU.MinOffset) Worklist.push_back(LU.MaxOffset); @@ -2376,7 +2376,14 @@ F.AM.BaseOffs = (uint64_t)Base.AM.BaseOffs - *I; if (isLegalUse(F.AM, LU.MinOffset - *I, LU.MaxOffset - *I, LU.Kind, LU.AccessTy, TLI)) { - F.BaseRegs[i] = SE.getAddExpr(G, SE.getConstant(G->getType(), *I)); + // Add the offset to the base register. + const SCEV *NewG = SE.getAddExpr(G, SE.getConstant(G->getType(), *I)); + // If it cancelled out, drop the base register, otherwise update it. + if (NewG->isZero()) { + std::swap(F.BaseRegs[i], F.BaseRegs.back()); + F.BaseRegs.pop_back(); + } else + F.BaseRegs[i] = NewG; (void)InsertFormula(LU, LUIdx, F); } Added: llvm/trunk/test/CodeGen/X86/lsr-i386.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lsr-i386.ll?rev=108424&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/lsr-i386.ll (added) +++ llvm/trunk/test/CodeGen/X86/lsr-i386.ll Thu Jul 15 10:14:45 2010 @@ -0,0 +1,44 @@ +; RUN: llc -march=x86 < %s | FileCheck %s +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32" +target triple = "i386-pc-linux-gnu" +; PR7651 + +; CHECK: align +; CHECK: align +; CHECK: align +; CHECK: movl $0, (%e +; CHECK-NEXT: addl $4, %e +; CHECK-NEXT: decl %e +; CHECK-NEXT: jne + +%struct.anon = type { [72 x i32], i32 } + + at mp2grad_ = external global %struct.anon + +define void @chomp2g_setup_(i32 %n, i32 %m) nounwind { +entry: + br label %bb1 + +bb1: ; preds = %bb6, %bb + %indvar11 = phi i32 [ %indvar.next12, %bb6 ], [ 0, %entry ] ; [#uses=2] + %tmp21 = add i32 %indvar11, 1 ; [#uses=1] + %t = load i32* getelementptr inbounds (%struct.anon* @mp2grad_, i32 0, i32 1) + %tmp15 = mul i32 %n, %t ; [#uses=1] + %tmp16 = add i32 %tmp21, %tmp15 ; [#uses=1] + %tmp17 = shl i32 %tmp16, 3 ; [#uses=1] + %tmp18 = add i32 %tmp17, -8 ; [#uses=1] + br label %bb2 + +bb2: ; preds = %bb2, %bb2.preheader + %indvar = phi i32 [ 0, %bb1 ], [ %indvar.next, %bb2 ] ; [#uses=2] + %tmp19 = add i32 %tmp18, %indvar ; [#uses=1] + %scevgep = getelementptr %struct.anon* @mp2grad_, i32 0, i32 0, i32 %tmp19 ; [#uses=1] + store i32 0, i32* %scevgep + %indvar.next = add i32 %indvar, 1 ; [#uses=1] + %c = icmp ne i32 %indvar.next, %m + br i1 %c, label %bb2, label %bb6 + +bb6: ; preds = %bb2, %bb1 + %indvar.next12 = add i32 %indvar11, 1 ; [#uses=1] + br label %bb1 +} From eli.friedman at gmail.com Thu Jul 15 11:28:57 2010 From: eli.friedman at gmail.com (Eli Friedman) Date: Thu, 15 Jul 2010 09:28:57 -0700 Subject: [llvm-commits] [llvm] r108351 - /llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp In-Reply-To: <2B9ADA84-2EFD-4120-968A-3C6FA32DD259@mac.com> References: <20100714195216.C609C2A6C12C@llvm.org> <4C3EB4C5.8030106@free.fr> <2B9ADA84-2EFD-4120-968A-3C6FA32DD259@mac.com> Message-ID: On Thu, Jul 15, 2010 at 7:59 AM, Owen Anderson wrote: > > On Jul 15, 2010, at 12:12 AM, Duncan Sands wrote: > > + ?Instruction *BonusInst = 0; > > + ?if (&*FrontIt != Cond&& > > + ?????(*FrontIt).hasOneUse()&& ?*(*FrontIt).use_begin() == Cond&& > > + ?????(*FrontIt).isSafeToSpeculativelyExecute()&& > > + ?????!(*FrontIt).mayReadFromMemory()) { > > Why the check on mayReadFromMemory? > > We don't want to speculatively execute a load before a null check. isSafeToSpeculativelyExecute will handle this for you. -Eli From clattner at apple.com Thu Jul 15 11:35:15 2010 From: clattner at apple.com (Chris Lattner) Date: Thu, 15 Jul 2010 09:35:15 -0700 Subject: [llvm-commits] [llvm] r108351 - /llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp In-Reply-To: References: <20100714195216.C609C2A6C12C@llvm.org> <4C3EB4C5.8030106@free.fr> <2B9ADA84-2EFD-4120-968A-3C6FA32DD259@mac.com> Message-ID: On Jul 15, 2010, at 9:28 AM, Eli Friedman wrote: > On Thu, Jul 15, 2010 at 7:59 AM, Owen Anderson wrote: >> >> On Jul 15, 2010, at 12:12 AM, Duncan Sands wrote: >> >> + Instruction *BonusInst = 0; >> >> + if (&*FrontIt != Cond&& >> >> + (*FrontIt).hasOneUse()&& *(*FrontIt).use_begin() == Cond&& >> >> + (*FrontIt).isSafeToSpeculativelyExecute()&& >> >> + !(*FrontIt).mayReadFromMemory()) { >> >> Why the check on mayReadFromMemory? >> >> We don't want to speculatively execute a load before a null check. > > isSafeToSpeculativelyExecute will handle this for you. Also, please use X->y instead of (*X).y -Chris From resistor at mac.com Thu Jul 15 11:38:22 2010 From: resistor at mac.com (Owen Anderson) Date: Thu, 15 Jul 2010 16:38:22 -0000 Subject: [llvm-commits] [llvm] r108427 - /llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Message-ID: <20100715163822.C12032A6C12C@llvm.org> Author: resistor Date: Thu Jul 15 11:38:22 2010 New Revision: 108427 URL: http://llvm.org/viewvc/llvm-project?rev=108427&view=rev Log: Remove unneeded check, and correct style. Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=108427&r1=108426&r2=108427&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Thu Jul 15 11:38:22 2010 @@ -1395,9 +1395,8 @@ // register pressure or inhibit out-of-order execution. Instruction *BonusInst = 0; if (&*FrontIt != Cond && - (*FrontIt).hasOneUse() && *(*FrontIt).use_begin() == Cond && - (*FrontIt).isSafeToSpeculativelyExecute() && - !(*FrontIt).mayReadFromMemory()) { + FrontIt->hasOneUse() && *FrontIt->use_begin() == Cond && + FrontIt->isSafeToSpeculativelyExecute()) { BonusInst = &*FrontIt; ++FrontIt; } From clattner at apple.com Thu Jul 15 11:42:14 2010 From: clattner at apple.com (Chris Lattner) Date: Thu, 15 Jul 2010 09:42:14 -0700 Subject: [llvm-commits] [llvm] r108422 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineAndOrXor.cpp lib/Transforms/InstCombine/InstCombineSelect.cpp test/Transforms/InstCombine/bit-checks.ll In-Reply-To: <20100715150024.103622A6C12C@llvm.org> References: <20100715150024.103622A6C12C@llvm.org> Message-ID: <6C11873B-53BE-4747-A479-8851C84486A7@apple.com> On Jul 15, 2010, at 8:00 AM, Owen Anderson wrote: > Author: resistor > Date: Thu Jul 15 10:00:23 2010 > New Revision: 108422 > > URL: http://llvm.org/viewvc/llvm-project?rev=108422&view=rev > Log: > Reapply r108378, with bugfixes, testcase, and improved comment formatting. > This now passes LIT, nighty test, and llvm-gcc bootstrap on my machine. Hi Owen, Is there a reason not to make the corresponding "or" pattern? Handling the or pattern in instcombineselect seems more limited than handling the general (icmp ne (A & C1), 0) | (icmp ne (A & C2), 0) pattern. -Chris > > Added: > llvm/trunk/test/Transforms/InstCombine/bit-checks.ll > Modified: > llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp > llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp > > Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp?rev=108422&r1=108421&r2=108422&view=diff > ============================================================================== > --- llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp (original) > +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp Thu Jul 15 10:00:23 2010 > @@ -472,6 +472,25 @@ > Value *NewOr = Builder->CreateOr(Val, Val2); > return Builder->CreateICmp(LHSCC, NewOr, LHSCst); > } > + > + // (icmp ne (A & C1), 0) & (icmp ne (A & C2), 0) --> > + // (icmp eq (A & (C1|C2)), (C1|C2)) > + if (LHSCC == ICmpInst::ICMP_NE && LHSCst->isZero()) { > + Instruction *I1 = dyn_cast(Val); > + Instruction *I2 = dyn_cast(Val2); > + if (I1 && I1->getOpcode() == Instruction::And && > + I2 && I2->getOpcode() == Instruction::And && > + I1->getOperand(0) == I1->getOperand(0)) { > + ConstantInt *CI1 = dyn_cast(I1->getOperand(1)); > + ConstantInt *CI2 = dyn_cast(I2->getOperand(1)); > + if (CI1 && !CI1->isZero() && CI2 && !CI2->isZero() && > + CI1->getValue().operator&(CI2->getValue()) == 0) { > + Constant *ConstOr = ConstantExpr::getOr(CI1, CI2); > + Value *NewAnd = Builder->CreateAnd(I1->getOperand(0), ConstOr); > + return Builder->CreateICmp(ICmpInst::ICMP_EQ, NewAnd, ConstOr); > + } > + } > + } > } > > // From here on, we only handle: > > Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp?rev=108422&r1=108421&r2=108422&view=diff > ============================================================================== > --- llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp (original) > +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp Thu Jul 15 10:00:23 2010 > @@ -699,6 +699,34 @@ > SI.setOperand(2, TrueVal); > return &SI; > } > + > + // select (A == 0 | B == 0), T, F--> select (A != 0 & B != 0), F, T > + // Note: This is a canonicalization rather than an optimization, and is used > + // to expose opportunities to other instcombine transforms. > + Instruction* CondInst = dyn_cast(CondVal); > + if (CondInst && CondInst->hasOneUse() && > + CondInst->getOpcode() == Instruction::Or) { > + ICmpInst *LHSCmp = dyn_cast(CondInst->getOperand(0)); > + ICmpInst *RHSCmp = dyn_cast(CondInst->getOperand(1)); > + if (LHSCmp && LHSCmp->hasOneUse() && > + LHSCmp->getPredicate() == ICmpInst::ICMP_EQ && > + RHSCmp && RHSCmp->hasOneUse() && > + RHSCmp->getPredicate() == ICmpInst::ICMP_EQ) { > + ConstantInt* C1 = dyn_cast(LHSCmp->getOperand(1)); > + ConstantInt* C2 = dyn_cast(RHSCmp->getOperand(1)); > + if (C1 && C1->isZero() && C2 && C2->isZero()) { > + LHSCmp->setPredicate(ICmpInst::ICMP_NE); > + RHSCmp->setPredicate(ICmpInst::ICMP_NE); > + Value *And = > + InsertNewInstBefore(BinaryOperator::CreateAnd(LHSCmp, RHSCmp, > + "and."+CondVal->getName()), SI); > + SI.setOperand(0, And); > + SI.setOperand(1, FalseVal); > + SI.setOperand(2, TrueVal); > + return &SI; > + } > + } > + } > > return 0; > } > > Added: llvm/trunk/test/Transforms/InstCombine/bit-checks.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/bit-checks.ll?rev=108422&view=auto > ============================================================================== > --- llvm/trunk/test/Transforms/InstCombine/bit-checks.ll (added) > +++ llvm/trunk/test/Transforms/InstCombine/bit-checks.ll Thu Jul 15 10:00:23 2010 > @@ -0,0 +1,15 @@ > +; This test makes sure that these instructions are properly eliminated. > +; > +; RUN: opt < %s -instcombine -S | \ > +; RUN: not grep {tobool} > +; END. > +define i32 @main(i32 %argc, i8** %argv) nounwind ssp { > +entry: > + %and = and i32 %argc, 1 ; [#uses=1] > + %tobool = icmp ne i32 %and, 0 ; [#uses=1] > + %and2 = and i32 %argc, 2 ; [#uses=1] > + %tobool3 = icmp ne i32 %and2, 0 ; [#uses=1] > + %or.cond = and i1 %tobool, %tobool3 ; [#uses=1] > + %retval.0 = select i1 %or.cond, i32 2, i32 1 ; [#uses=1] > + ret i32 %retval.0 > +} > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dpatel at apple.com Thu Jul 15 11:46:45 2010 From: dpatel at apple.com (Devang Patel) Date: Thu, 15 Jul 2010 09:46:45 -0700 Subject: [llvm-commits] [llvm] r108369 - in /llvm/trunk: include/llvm/CodeGen/MachineModuleInfo.h lib/CodeGen/MachineModuleInfo.cpp In-Reply-To: <20100714230816.C305B2A6C12C@llvm.org> References: <20100714230816.C305B2A6C12C@llvm.org> Message-ID: Dan, On Jul 14, 2010, at 4:08 PM, Dan Gohman wrote: > Author: djg > Date: Wed Jul 14 18:08:16 2010 > New Revision: 108369 > > URL: http://llvm.org/viewvc/llvm-project?rev=108369&view=rev > Log: > Make the order in which variables are described in debug information > independent of the order that isel happens to visit the dbg_declare > intrinsics. This fixes a bug in which the formal arguments were > being printed in reverse order, now that fast isel is going bottom up. This won't help llvm-gcc because of lack of column no. info llvm-gcc generated debug info. - Devang > > Modified: > llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h > llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp > > Modified: llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h?rev=108369&r1=108368&r2=108369&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h (original) > +++ llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h Wed Jul 14 18:08:16 2010 > @@ -344,7 +344,7 @@ > VariableDbgInfo.push_back(std::make_pair(N, std::make_pair(Slot, Loc))); > } > > - VariableDbgInfoMapTy &getVariableDbgInfo() { return VariableDbgInfo; } > + VariableDbgInfoMapTy &getVariableDbgInfo(); > > }; // End class MachineModuleInfo > > > Modified: llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp?rev=108369&r1=108368&r2=108369&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp (original) > +++ llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp Wed Jul 14 18:08:16 2010 > @@ -563,3 +563,26 @@ > return 0; > } > > +namespace { > + /// VariableDebugSorter - Comparison to sort the VariableDbgInfo map > + /// by source location, to avoid depending on the arbitrary order that > + /// instruction selection visits variables in. > + struct VariableDebugSorter { > + bool operator()(const MachineModuleInfo::VariableDbgInfoMapTy::value_type &A, > + const MachineModuleInfo::VariableDbgInfoMapTy::value_type &B) > + const { > + if (A.second.second.getLine() != B.second.second.getLine()) > + return A.second.second.getLine() < B.second.second.getLine(); > + if (A.second.second.getCol() != B.second.second.getCol()) > + return A.second.second.getCol() < B.second.second.getCol(); > + return false; > + } > + }; > +} > + > +MachineModuleInfo::VariableDbgInfoMapTy & > +MachineModuleInfo::getVariableDbgInfo() { > + std::stable_sort(VariableDbgInfo.begin(), VariableDbgInfo.end(), > + VariableDebugSorter()); > + return VariableDbgInfo; > +} > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From resistor at mac.com Thu Jul 15 12:24:23 2010 From: resistor at mac.com (Owen Anderson) Date: Thu, 15 Jul 2010 17:24:23 -0000 Subject: [llvm-commits] [llvm] r108429 - in /llvm/trunk/lib/Transforms/InstCombine: InstCombineAndOrXor.cpp InstCombineSelect.cpp Message-ID: <20100715172423.564442A6C12C@llvm.org> Author: resistor Date: Thu Jul 15 12:24:23 2010 New Revision: 108429 URL: http://llvm.org/viewvc/llvm-project?rev=108429&view=rev Log: Per Chris' suggestion, get rid of the select canonicalization and just add the corresponding or-icmp-and pattern. This has the added benefit of doing the matching earlier, and thus being less susceptible to being confused by earlier transforms. Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp?rev=108429&r1=108428&r2=108429&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp Thu Jul 15 12:24:23 2010 @@ -1177,6 +1177,25 @@ return Builder->CreateICmp(LHSCC, NewOr, LHSCst); } + // (icmp eq (A & C1), 0) | (icmp eq (A & C2), 0) --> + // (icmp ne (A & (C1|C2)), (C1|C2)) + if (LHSCC == ICmpInst::ICMP_EQ && LHSCst->isZero()) { + Instruction *I1 = dyn_cast(Val); + Instruction *I2 = dyn_cast(Val2); + if (I1 && I1->getOpcode() == Instruction::And && + I2 && I2->getOpcode() == Instruction::And && + I1->getOperand(0) == I1->getOperand(0)) { + ConstantInt *CI1 = dyn_cast(I1->getOperand(1)); + ConstantInt *CI2 = dyn_cast(I2->getOperand(1)); + if (CI1 && !CI1->isZero() && CI2 && !CI2->isZero() && + CI1->getValue().operator&(CI2->getValue()) == 0) { + Constant *ConstOr = ConstantExpr::getOr(CI1, CI2); + Value *NewAnd = Builder->CreateAnd(I1->getOperand(0), ConstOr); + return Builder->CreateICmp(ICmpInst::ICMP_NE, NewAnd, ConstOr); + } + } + } + // From here on, we only handle: // (icmp1 A, C1) | (icmp2 A, C2) --> something simpler. if (Val != Val2) return 0; Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp?rev=108429&r1=108428&r2=108429&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp Thu Jul 15 12:24:23 2010 @@ -699,34 +699,6 @@ SI.setOperand(2, TrueVal); return &SI; } - - // select (A == 0 | B == 0), T, F--> select (A != 0 & B != 0), F, T - // Note: This is a canonicalization rather than an optimization, and is used - // to expose opportunities to other instcombine transforms. - Instruction* CondInst = dyn_cast(CondVal); - if (CondInst && CondInst->hasOneUse() && - CondInst->getOpcode() == Instruction::Or) { - ICmpInst *LHSCmp = dyn_cast(CondInst->getOperand(0)); - ICmpInst *RHSCmp = dyn_cast(CondInst->getOperand(1)); - if (LHSCmp && LHSCmp->hasOneUse() && - LHSCmp->getPredicate() == ICmpInst::ICMP_EQ && - RHSCmp && RHSCmp->hasOneUse() && - RHSCmp->getPredicate() == ICmpInst::ICMP_EQ) { - ConstantInt* C1 = dyn_cast(LHSCmp->getOperand(1)); - ConstantInt* C2 = dyn_cast(RHSCmp->getOperand(1)); - if (C1 && C1->isZero() && C2 && C2->isZero()) { - LHSCmp->setPredicate(ICmpInst::ICMP_NE); - RHSCmp->setPredicate(ICmpInst::ICMP_NE); - Value *And = - InsertNewInstBefore(BinaryOperator::CreateAnd(LHSCmp, RHSCmp, - "and."+CondVal->getName()), SI); - SI.setOperand(0, And); - SI.setOperand(1, FalseVal); - SI.setOperand(2, TrueVal); - return &SI; - } - } - } return 0; } From clattner at apple.com Thu Jul 15 12:47:52 2010 From: clattner at apple.com (Chris Lattner) Date: Thu, 15 Jul 2010 10:47:52 -0700 Subject: [llvm-commits] [llvm] r108429 - in /llvm/trunk/lib/Transforms/InstCombine: InstCombineAndOrXor.cpp InstCombineSelect.cpp In-Reply-To: <20100715172423.564442A6C12C@llvm.org> References: <20100715172423.564442A6C12C@llvm.org> Message-ID: <3EF1EB8B-A351-4262-A453-BF970BD62577@apple.com> On Jul 15, 2010, at 10:24 AM, Owen Anderson wrote: > Author: resistor > Date: Thu Jul 15 12:24:23 2010 > New Revision: 108429 > > URL: http://llvm.org/viewvc/llvm-project?rev=108429&view=rev > Log: > Per Chris' suggestion, get rid of the select canonicalization and just add > the corresponding or-icmp-and pattern. This has the added benefit of doing > the matching earlier, and thus being less susceptible to being confused by > earlier transforms. Thanks, btw, the pattern would be cleaner to match with some match(x, m_And(... 's -Chris > > Modified: > llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp > llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp > > Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp?rev=108429&r1=108428&r2=108429&view=diff > ============================================================================== > --- llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp (original) > +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp Thu Jul 15 12:24:23 2010 > @@ -1177,6 +1177,25 @@ > return Builder->CreateICmp(LHSCC, NewOr, LHSCst); > } > > + // (icmp eq (A & C1), 0) | (icmp eq (A & C2), 0) --> > + // (icmp ne (A & (C1|C2)), (C1|C2)) > + if (LHSCC == ICmpInst::ICMP_EQ && LHSCst->isZero()) { > + Instruction *I1 = dyn_cast(Val); > + Instruction *I2 = dyn_cast(Val2); > + if (I1 && I1->getOpcode() == Instruction::And && > + I2 && I2->getOpcode() == Instruction::And && > + I1->getOperand(0) == I1->getOperand(0)) { > + ConstantInt *CI1 = dyn_cast(I1->getOperand(1)); > + ConstantInt *CI2 = dyn_cast(I2->getOperand(1)); > + if (CI1 && !CI1->isZero() && CI2 && !CI2->isZero() && > + CI1->getValue().operator&(CI2->getValue()) == 0) { > + Constant *ConstOr = ConstantExpr::getOr(CI1, CI2); > + Value *NewAnd = Builder->CreateAnd(I1->getOperand(0), ConstOr); > + return Builder->CreateICmp(ICmpInst::ICMP_NE, NewAnd, ConstOr); > + } > + } > + } > + > // From here on, we only handle: > // (icmp1 A, C1) | (icmp2 A, C2) --> something simpler. > if (Val != Val2) return 0; > > Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp?rev=108429&r1=108428&r2=108429&view=diff > ============================================================================== > --- llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp (original) > +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp Thu Jul 15 12:24:23 2010 > @@ -699,34 +699,6 @@ > SI.setOperand(2, TrueVal); > return &SI; > } > - > - // select (A == 0 | B == 0), T, F--> select (A != 0 & B != 0), F, T > - // Note: This is a canonicalization rather than an optimization, and is used > - // to expose opportunities to other instcombine transforms. > - Instruction* CondInst = dyn_cast(CondVal); > - if (CondInst && CondInst->hasOneUse() && > - CondInst->getOpcode() == Instruction::Or) { > - ICmpInst *LHSCmp = dyn_cast(CondInst->getOperand(0)); > - ICmpInst *RHSCmp = dyn_cast(CondInst->getOperand(1)); > - if (LHSCmp && LHSCmp->hasOneUse() && > - LHSCmp->getPredicate() == ICmpInst::ICMP_EQ && > - RHSCmp && RHSCmp->hasOneUse() && > - RHSCmp->getPredicate() == ICmpInst::ICMP_EQ) { > - ConstantInt* C1 = dyn_cast(LHSCmp->getOperand(1)); > - ConstantInt* C2 = dyn_cast(RHSCmp->getOperand(1)); > - if (C1 && C1->isZero() && C2 && C2->isZero()) { > - LHSCmp->setPredicate(ICmpInst::ICMP_NE); > - RHSCmp->setPredicate(ICmpInst::ICMP_NE); > - Value *And = > - InsertNewInstBefore(BinaryOperator::CreateAnd(LHSCmp, RHSCmp, > - "and."+CondVal->getName()), SI); > - SI.setOperand(0, And); > - SI.setOperand(1, FalseVal); > - SI.setOperand(2, TrueVal); > - return &SI; > - } > - } > - } > > return 0; > } > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From resistor at mac.com Thu Jul 15 13:18:57 2010 From: resistor at mac.com (Owen Anderson) Date: Thu, 15 Jul 2010 18:18:57 -0000 Subject: [llvm-commits] [llvm] r108436 - in /llvm/trunk/lib/Transforms/InstCombine: InstCombineAndOrXor.cpp InstCombineSelect.cpp Message-ID: <20100715181857.6937B2A6C12C@llvm.org> Author: resistor Date: Thu Jul 15 13:18:57 2010 New Revision: 108436 URL: http://llvm.org/viewvc/llvm-project?rev=108436&view=rev Log: Speculatively revert r108429 to fix the clang self-host. Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp?rev=108436&r1=108435&r2=108436&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp Thu Jul 15 13:18:57 2010 @@ -1177,25 +1177,6 @@ return Builder->CreateICmp(LHSCC, NewOr, LHSCst); } - // (icmp eq (A & C1), 0) | (icmp eq (A & C2), 0) --> - // (icmp ne (A & (C1|C2)), (C1|C2)) - if (LHSCC == ICmpInst::ICMP_EQ && LHSCst->isZero()) { - Instruction *I1 = dyn_cast(Val); - Instruction *I2 = dyn_cast(Val2); - if (I1 && I1->getOpcode() == Instruction::And && - I2 && I2->getOpcode() == Instruction::And && - I1->getOperand(0) == I1->getOperand(0)) { - ConstantInt *CI1 = dyn_cast(I1->getOperand(1)); - ConstantInt *CI2 = dyn_cast(I2->getOperand(1)); - if (CI1 && !CI1->isZero() && CI2 && !CI2->isZero() && - CI1->getValue().operator&(CI2->getValue()) == 0) { - Constant *ConstOr = ConstantExpr::getOr(CI1, CI2); - Value *NewAnd = Builder->CreateAnd(I1->getOperand(0), ConstOr); - return Builder->CreateICmp(ICmpInst::ICMP_NE, NewAnd, ConstOr); - } - } - } - // From here on, we only handle: // (icmp1 A, C1) | (icmp2 A, C2) --> something simpler. if (Val != Val2) return 0; Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp?rev=108436&r1=108435&r2=108436&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp Thu Jul 15 13:18:57 2010 @@ -699,6 +699,34 @@ SI.setOperand(2, TrueVal); return &SI; } + + // select (A == 0 | B == 0), T, F--> select (A != 0 & B != 0), F, T + // Note: This is a canonicalization rather than an optimization, and is used + // to expose opportunities to other instcombine transforms. + Instruction* CondInst = dyn_cast(CondVal); + if (CondInst && CondInst->hasOneUse() && + CondInst->getOpcode() == Instruction::Or) { + ICmpInst *LHSCmp = dyn_cast(CondInst->getOperand(0)); + ICmpInst *RHSCmp = dyn_cast(CondInst->getOperand(1)); + if (LHSCmp && LHSCmp->hasOneUse() && + LHSCmp->getPredicate() == ICmpInst::ICMP_EQ && + RHSCmp && RHSCmp->hasOneUse() && + RHSCmp->getPredicate() == ICmpInst::ICMP_EQ) { + ConstantInt* C1 = dyn_cast(LHSCmp->getOperand(1)); + ConstantInt* C2 = dyn_cast(RHSCmp->getOperand(1)); + if (C1 && C1->isZero() && C2 && C2->isZero()) { + LHSCmp->setPredicate(ICmpInst::ICMP_NE); + RHSCmp->setPredicate(ICmpInst::ICMP_NE); + Value *And = + InsertNewInstBefore(BinaryOperator::CreateAnd(LHSCmp, RHSCmp, + "and."+CondVal->getName()), SI); + SI.setOperand(0, And); + SI.setOperand(1, FalseVal); + SI.setOperand(2, TrueVal); + return &SI; + } + } + } return 0; } From isanbard at gmail.com Thu Jul 15 13:40:50 2010 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 15 Jul 2010 18:40:50 -0000 Subject: [llvm-commits] [llvm] r108438 - /llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h Message-ID: <20100715184050.58C872A6C12C@llvm.org> Author: void Date: Thu Jul 15 13:40:50 2010 New Revision: 108438 URL: http://llvm.org/viewvc/llvm-project?rev=108438&view=rev Log: Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister. Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h?rev=108438&r1=108437&r2=108438&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h (original) +++ llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h Thu Jul 15 13:40:50 2010 @@ -59,7 +59,7 @@ /// currently representing the group that the register belongs to. /// Register 0 is always represented by the 0 group, a group /// composed of registers that are not eligible for anti-aliasing. - unsigned GroupNodeIndices[TargetRegisterInfo::FirstVirtualRegister]; + std::vector GroupNodeIndices; /// RegRefs - Map registers to all their references within a live range. std::multimap RegRefs; From isanbard at gmail.com Thu Jul 15 13:43:10 2010 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 15 Jul 2010 18:43:10 -0000 Subject: [llvm-commits] [llvm] r108440 - in /llvm/trunk/lib/CodeGen: AggressiveAntiDepBreaker.cpp AggressiveAntiDepBreaker.h Message-ID: <20100715184310.1D9332A6C12C@llvm.org> Author: void Date: Thu Jul 15 13:43:09 2010 New Revision: 108440 URL: http://llvm.org/viewvc/llvm-project?rev=108440&view=rev Log: Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister. Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp?rev=108440&r1=108439&r2=108440&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp (original) +++ llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp Thu Jul 15 13:43:09 2010 @@ -145,8 +145,8 @@ State = new AggressiveAntiDepState(TRI->getNumRegs(), BB); bool IsReturnBlock = (!BB->empty() && BB->back().getDesc().isReturn()); - unsigned *KillIndices = State->GetKillIndices(); - unsigned *DefIndices = State->GetDefIndices(); + std::vector &KillIndices = State->GetKillIndices(); + std::vector &DefIndices = State->GetDefIndices(); // Determine the live-out physregs for this block. if (IsReturnBlock) { @@ -226,7 +226,7 @@ DEBUG(MI->dump()); DEBUG(dbgs() << "\tRegs:"); - unsigned *DefIndices = State->GetDefIndices(); + std::vector &DefIndices = State->GetDefIndices(); for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { // If Reg is current live, then mark that it can't be renamed as // we don't know the extent of its live-range anymore (now that it @@ -328,8 +328,8 @@ const char *tag, const char *header, const char *footer) { - unsigned *KillIndices = State->GetKillIndices(); - unsigned *DefIndices = State->GetDefIndices(); + std::vector &KillIndices = State->GetKillIndices(); + std::vector &DefIndices = State->GetDefIndices(); std::multimap& RegRefs = State->GetRegRefs(); @@ -364,7 +364,7 @@ void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI, unsigned Count, std::set& PassthruRegs) { - unsigned *DefIndices = State->GetDefIndices(); + std::vector &DefIndices = State->GetDefIndices(); std::multimap& RegRefs = State->GetRegRefs(); @@ -560,8 +560,8 @@ unsigned AntiDepGroupIndex, RenameOrderType& RenameOrder, std::map &RenameMap) { - unsigned *KillIndices = State->GetKillIndices(); - unsigned *DefIndices = State->GetDefIndices(); + std::vector &KillIndices = State->GetKillIndices(); + std::vector &DefIndices = State->GetDefIndices(); std::multimap& RegRefs = State->GetRegRefs(); @@ -733,8 +733,8 @@ MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, unsigned InsertPosIndex) { - unsigned *KillIndices = State->GetKillIndices(); - unsigned *DefIndices = State->GetDefIndices(); + std::vector &KillIndices = State->GetKillIndices(); + std::vector &DefIndices = State->GetDefIndices(); std::multimap& RegRefs = State->GetRegRefs(); Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h?rev=108440&r1=108439&r2=108440&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h (original) +++ llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h Thu Jul 15 13:43:09 2010 @@ -66,20 +66,20 @@ /// KillIndices - The index of the most recent kill (proceding bottom-up), /// or ~0u if the register is not live. - unsigned KillIndices[TargetRegisterInfo::FirstVirtualRegister]; + std::vector KillIndices; /// DefIndices - The index of the most recent complete def (proceding bottom /// up), or ~0u if the register is live. - unsigned DefIndices[TargetRegisterInfo::FirstVirtualRegister]; + std::vector DefIndices; public: AggressiveAntiDepState(const unsigned TargetRegs, MachineBasicBlock *BB); /// GetKillIndices - Return the kill indices. - unsigned *GetKillIndices() { return KillIndices; } + std::vector &GetKillIndices() { return KillIndices; } /// GetDefIndices - Return the define indices. - unsigned *GetDefIndices() { return DefIndices; } + std::vector &GetDefIndices() { return DefIndices; } /// GetRegRefs - Return the RegRefs map. std::multimap& GetRegRefs() { return RegRefs; } From Micah.Villmow at amd.com Thu Jul 15 13:45:15 2010 From: Micah.Villmow at amd.com (Villmow, Micah) Date: Thu, 15 Jul 2010 13:45:15 -0500 Subject: [llvm-commits] Windows compilation warnings Message-ID: There are a bunch of windows warnings, here is a patch that fixes some of them. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100715/993e3b5f/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: windows_warnings.diff Type: application/octet-stream Size: 38183 bytes Desc: windows_warnings.diff Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100715/993e3b5f/attachment.obj From dpatel at apple.com Thu Jul 15 13:45:27 2010 From: dpatel at apple.com (Devang Patel) Date: Thu, 15 Jul 2010 18:45:27 -0000 Subject: [llvm-commits] [llvm] r108441 - in /llvm/trunk: lib/CodeGen/SelectionDAG/TargetLowering.cpp test/CodeGen/X86/2010-07-15-Crash.ll Message-ID: <20100715184528.0AD022A6C12C@llvm.org> Author: dpatel Date: Thu Jul 15 13:45:27 2010 New Revision: 108441 URL: http://llvm.org/viewvc/llvm-project?rev=108441&view=rev Log: Fix crash reported in PR7653. Added: llvm/trunk/test/CodeGen/X86/2010-07-15-Crash.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=108441&r1=108440&r2=108441&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Thu Jul 15 13:45:27 2010 @@ -2476,7 +2476,7 @@ int64_t Offs = GA->getOffset(); if (C) Offs += C->getZExtValue(); Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), - C->getDebugLoc(), + C ? C->getDebugLoc() : DebugLoc(), Op.getValueType(), Offs)); return; } Added: llvm/trunk/test/CodeGen/X86/2010-07-15-Crash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-07-15-Crash.ll?rev=108441&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2010-07-15-Crash.ll (added) +++ llvm/trunk/test/CodeGen/X86/2010-07-15-Crash.ll Thu Jul 15 13:45:27 2010 @@ -0,0 +1,12 @@ +; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s -o /dev/null +; PR7653 + + at __FUNCTION__.1623 = external constant [4 x i8] ; <[4 x i8]*> [#uses=1] + +define void @foo() nounwind { +entry: + tail call void asm sideeffect "", "s,i,~{fpsr},~{flags}"(i8* getelementptr +inbounds ([4 x i8]* @__FUNCTION__.1623, i64 0, i64 0), i8* getelementptr +inbounds ([4 x i8]* @__FUNCTION__.1623, i64 0, i64 0)) nounwind + ret void +} From daniel at zuster.org Thu Jul 15 14:33:39 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 15 Jul 2010 19:33:39 -0000 Subject: [llvm-commits] [llvm] r108444 - /llvm/trunk/Makefile.rules Message-ID: <20100715193339.1CE812A6C12C@llvm.org> Author: ddunbar Date: Thu Jul 15 14:33:38 2010 New Revision: 108444 URL: http://llvm.org/viewvc/llvm-project?rev=108444&view=rev Log: build/Darwin: Add support for embedding version information in tool executables. Modified: llvm/trunk/Makefile.rules Modified: llvm/trunk/Makefile.rules URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=108444&r1=108443&r2=108444&view=diff ============================================================================== --- llvm/trunk/Makefile.rules (original) +++ llvm/trunk/Makefile.rules Thu Jul 15 14:33:38 2010 @@ -1345,6 +1345,27 @@ endif endif +#--------------------------------------------------------- +# Tool Version Info Support +#--------------------------------------------------------- + +ifeq ($(HOST_OS),Darwin) +ifdef TOOL_INFO_PLIST + +LD.Flags += -Wl,-sectcreate,__TEXT,__info_plist,$(ObjDir)/$(TOOL_INFO_PLIST) + +$(ToolBuildPath): $(ObjDir)/$(TOOL_INFO_PLIST) + +$(ObjDir)/$(TOOL_INFO_PLIST): $(PROJ_SRC_DIR)/$(TOOL_INFO_PLIST).in + $(Echo) "Creating $(TOOLNAME) '$(TOOL_INFO_PLIST)' file..." + $(Verb)sed -e "s#@TOOL_INFO_UTI@#$(TOOL_INFO_UTI)#g" \ + -e "s#@TOOL_INFO_NAME@#$(TOOL_INFO_NAME)#g" \ + -e "s#@TOOL_INFO_VERSION@#$(TOOL_INFO_VERSION)#g" \ + -e "s#@TOOL_INFO_BUILD_VERSION@#$(TOOL_INFO_BUILD_VERSION)#g" \ + $< > $@ + +endif +endif #--------------------------------------------------------- # Provide targets for building the tools From isanbard at gmail.com Thu Jul 15 14:41:20 2010 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 15 Jul 2010 19:41:20 -0000 Subject: [llvm-commits] [llvm] r108448 - /llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp Message-ID: <20100715194120.CAE062A6C12C@llvm.org> Author: void Date: Thu Jul 15 14:41:20 2010 New Revision: 108448 URL: http://llvm.org/viewvc/llvm-project?rev=108448&view=rev Log: Reserve a goodly amount of room for the vectors. Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp?rev=108448&r1=108447&r2=108448&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp (original) +++ llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp Thu Jul 15 14:41:20 2010 @@ -42,6 +42,9 @@ AggressiveAntiDepState::AggressiveAntiDepState(const unsigned TargetRegs, MachineBasicBlock *BB) : NumTargetRegs(TargetRegs), GroupNodes(TargetRegs, 0) { + GroupNodeIndices.reserve(TargetRegs); + KillIndices.reserve(TargetRegs); + DefIndices.reserve(TargetRegs); const unsigned BBSize = BB->size(); for (unsigned i = 0; i < NumTargetRegs; ++i) { @@ -54,8 +57,7 @@ } } -unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) -{ +unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) { unsigned Node = GroupNodeIndices[Reg]; while (GroupNodes[Node] != Node) Node = GroupNodes[Node]; From clattner at apple.com Thu Jul 15 14:51:24 2010 From: clattner at apple.com (Chris Lattner) Date: Thu, 15 Jul 2010 12:51:24 -0700 Subject: [llvm-commits] [llvm] r108440 - in /llvm/trunk/lib/CodeGen: AggressiveAntiDepBreaker.cpp AggressiveAntiDepBreaker.h In-Reply-To: <20100715184310.1D9332A6C12C@llvm.org> References: <20100715184310.1D9332A6C12C@llvm.org> Message-ID: Doesn't something need to resize these? -Chris On Jul 15, 2010, at 11:43 AM, Bill Wendling wrote: > Author: void > Date: Thu Jul 15 13:43:09 2010 > New Revision: 108440 > > URL: http://llvm.org/viewvc/llvm-project?rev=108440&view=rev > Log: > Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister. > > Modified: > llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp > llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h > > Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp?rev=108440&r1=108439&r2=108440&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp (original) > +++ llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp Thu Jul 15 13:43:09 2010 > @@ -145,8 +145,8 @@ > State = new AggressiveAntiDepState(TRI->getNumRegs(), BB); > > bool IsReturnBlock = (!BB->empty() && BB->back().getDesc().isReturn()); > - unsigned *KillIndices = State->GetKillIndices(); > - unsigned *DefIndices = State->GetDefIndices(); > + std::vector &KillIndices = State->GetKillIndices(); > + std::vector &DefIndices = State->GetDefIndices(); > > // Determine the live-out physregs for this block. > if (IsReturnBlock) { > @@ -226,7 +226,7 @@ > DEBUG(MI->dump()); > DEBUG(dbgs() << "\tRegs:"); > > - unsigned *DefIndices = State->GetDefIndices(); > + std::vector &DefIndices = State->GetDefIndices(); > for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { > // If Reg is current live, then mark that it can't be renamed as > // we don't know the extent of its live-range anymore (now that it > @@ -328,8 +328,8 @@ > const char *tag, > const char *header, > const char *footer) { > - unsigned *KillIndices = State->GetKillIndices(); > - unsigned *DefIndices = State->GetDefIndices(); > + std::vector &KillIndices = State->GetKillIndices(); > + std::vector &DefIndices = State->GetDefIndices(); > std::multimap& > RegRefs = State->GetRegRefs(); > > @@ -364,7 +364,7 @@ > void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI, > unsigned Count, > std::set& PassthruRegs) { > - unsigned *DefIndices = State->GetDefIndices(); > + std::vector &DefIndices = State->GetDefIndices(); > std::multimap& > RegRefs = State->GetRegRefs(); > > @@ -560,8 +560,8 @@ > unsigned AntiDepGroupIndex, > RenameOrderType& RenameOrder, > std::map &RenameMap) { > - unsigned *KillIndices = State->GetKillIndices(); > - unsigned *DefIndices = State->GetDefIndices(); > + std::vector &KillIndices = State->GetKillIndices(); > + std::vector &DefIndices = State->GetDefIndices(); > std::multimap& > RegRefs = State->GetRegRefs(); > > @@ -733,8 +733,8 @@ > MachineBasicBlock::iterator Begin, > MachineBasicBlock::iterator End, > unsigned InsertPosIndex) { > - unsigned *KillIndices = State->GetKillIndices(); > - unsigned *DefIndices = State->GetDefIndices(); > + std::vector &KillIndices = State->GetKillIndices(); > + std::vector &DefIndices = State->GetDefIndices(); > std::multimap& > RegRefs = State->GetRegRefs(); > > > Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h?rev=108440&r1=108439&r2=108440&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h (original) > +++ llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h Thu Jul 15 13:43:09 2010 > @@ -66,20 +66,20 @@ > > /// KillIndices - The index of the most recent kill (proceding bottom-up), > /// or ~0u if the register is not live. > - unsigned KillIndices[TargetRegisterInfo::FirstVirtualRegister]; > + std::vector KillIndices; > > /// DefIndices - The index of the most recent complete def (proceding bottom > /// up), or ~0u if the register is live. > - unsigned DefIndices[TargetRegisterInfo::FirstVirtualRegister]; > + std::vector DefIndices; > > public: > AggressiveAntiDepState(const unsigned TargetRegs, MachineBasicBlock *BB); > > /// GetKillIndices - Return the kill indices. > - unsigned *GetKillIndices() { return KillIndices; } > + std::vector &GetKillIndices() { return KillIndices; } > > /// GetDefIndices - Return the define indices. > - unsigned *GetDefIndices() { return DefIndices; } > + std::vector &GetDefIndices() { return DefIndices; } > > /// GetRegRefs - Return the RegRefs map. > std::multimap& GetRegRefs() { return RegRefs; } > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From isanbard at gmail.com Thu Jul 15 14:58:14 2010 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 15 Jul 2010 19:58:14 -0000 Subject: [llvm-commits] [llvm] r108449 - in /llvm/trunk/lib/CodeGen: AggressiveAntiDepBreaker.cpp CriticalAntiDepBreaker.cpp CriticalAntiDepBreaker.h Message-ID: <20100715195814.3E2CE2A6C12C@llvm.org> Author: void Date: Thu Jul 15 14:58:14 2010 New Revision: 108449 URL: http://llvm.org/viewvc/llvm-project?rev=108449&view=rev Log: Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister. This time make sure to allocate enough space in the std::vector. Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.h Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp?rev=108449&r1=108448&r2=108449&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp (original) +++ llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp Thu Jul 15 14:58:14 2010 @@ -41,11 +41,11 @@ AggressiveAntiDepState::AggressiveAntiDepState(const unsigned TargetRegs, MachineBasicBlock *BB) : - NumTargetRegs(TargetRegs), GroupNodes(TargetRegs, 0) { - GroupNodeIndices.reserve(TargetRegs); - KillIndices.reserve(TargetRegs); - DefIndices.reserve(TargetRegs); - + NumTargetRegs(TargetRegs), GroupNodes(TargetRegs, 0), + GroupNodeIndices(TargetRegs, 0), + KillIndices(TargetRegs, 0), + DefIndices(TargetRegs, 0) +{ const unsigned BBSize = BB->size(); for (unsigned i = 0; i < NumTargetRegs; ++i) { // Initialize all registers to be in their own group. Initially we Modified: llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp?rev=108449&r1=108448&r2=108449&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp (original) +++ llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp Thu Jul 15 14:58:14 2010 @@ -32,21 +32,23 @@ MRI(MF.getRegInfo()), TII(MF.getTarget().getInstrInfo()), TRI(MF.getTarget().getRegisterInfo()), - AllocatableSet(TRI->getAllocatableSet(MF)) -{ -} + AllocatableSet(TRI->getAllocatableSet(MF)), + Classes(TRI->getNumRegs(), static_cast(0)), + KillIndices(TRI->getNumRegs(), 0), + DefIndices(TRI->getNumRegs(), 0) {} CriticalAntiDepBreaker::~CriticalAntiDepBreaker() { } void CriticalAntiDepBreaker::StartBlock(MachineBasicBlock *BB) { - // Clear out the register class data. - std::fill(Classes, array_endof(Classes), - static_cast(0)); + Classes.clear(); - // Initialize the indices to indicate that no registers are live. const unsigned BBSize = BB->size(); - for (unsigned i = 0; i < TRI->getNumRegs(); ++i) { + for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) { + // Clear out the register class data. + Classes[i] = static_cast(0); + + // Initialize the indices to indicate that no registers are live. KillIndices[i] = ~0u; DefIndices[i] = BBSize; } @@ -65,6 +67,7 @@ Classes[Reg] = reinterpret_cast(-1); KillIndices[Reg] = BB->size(); DefIndices[Reg] = ~0u; + // Repeat, for all aliases. for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { unsigned AliasReg = *Alias; @@ -86,6 +89,7 @@ Classes[Reg] = reinterpret_cast(-1); KillIndices[Reg] = BB->size(); DefIndices[Reg] = ~0u; + // Repeat, for all aliases. for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { unsigned AliasReg = *Alias; @@ -106,6 +110,7 @@ Classes[Reg] = reinterpret_cast(-1); KillIndices[Reg] = BB->size(); DefIndices[Reg] = ~0u; + // Repeat, for all aliases. for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { unsigned AliasReg = *Alias; @@ -134,8 +139,10 @@ for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) if (DefIndices[Reg] < InsertPosIndex && DefIndices[Reg] >= Count) { assert(KillIndices[Reg] == ~0u && "Clobbered register is live!"); + // Mark this register to be non-renamable. Classes[Reg] = reinterpret_cast(-1); + // Move the def index to the end of the previous region, to reflect // that the def could theoretically have been scheduled at the end. DefIndices[Reg] = InsertPosIndex; @@ -433,7 +440,7 @@ // fix that remaining critical edge too. This is a little more involved, // because unlike the most recent register, less recent registers should // still be considered, though only if no other registers are available. - unsigned LastNewReg[TargetRegisterInfo::FirstVirtualRegister] = {}; + std::vector LastNewReg(TRI->getNumRegs(), 0); // Attempt to break anti-dependence edges on the critical path. Walk the // instructions from the bottom up, tracking information about liveness Modified: llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.h?rev=108449&r1=108448&r2=108449&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.h (original) +++ llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.h Thu Jul 15 14:58:14 2010 @@ -46,19 +46,18 @@ /// corresponding value is null. If the register is live but used in /// multiple register classes, the corresponding value is -1 casted to a /// pointer. - const TargetRegisterClass * - Classes[TargetRegisterInfo::FirstVirtualRegister]; + std::vector Classes; /// RegRegs - Map registers to all their references within a live range. std::multimap RegRefs; /// KillIndices - The index of the most recent kill (proceding bottom-up), /// or ~0u if the register is not live. - unsigned KillIndices[TargetRegisterInfo::FirstVirtualRegister]; + std::vector KillIndices; /// DefIndices - The index of the most recent complete def (proceding bottom /// up), or ~0u if the register is live. - unsigned DefIndices[TargetRegisterInfo::FirstVirtualRegister]; + std::vector DefIndices; /// KeepRegs - A set of registers which are live and cannot be changed to /// break anti-dependencies. From dpatel at apple.com Thu Jul 15 14:59:00 2010 From: dpatel at apple.com (Devang Patel) Date: Thu, 15 Jul 2010 12:59:00 -0700 Subject: [llvm-commits] [llvm] r108444 - /llvm/trunk/Makefile.rules In-Reply-To: <20100715193339.1CE812A6C12C@llvm.org> References: <20100715193339.1CE812A6C12C@llvm.org> Message-ID: <631BA221-4800-49FD-A4F0-A79D9CD2D3C3@apple.com> After svn update, I am seeing make[4]: *** No rule to make target `/Volumes/Lalgate/clean/llvm/tools/clang/tools/driver/Info.plist.in', needed by `/Volumes/Lalgate/clean/D/tools/clang/tools/driver/Debug+Asserts/Info.plist'. Stop. Is this related to this check-in ? - Devang On Jul 15, 2010, at 12:33 PM, Daniel Dunbar wrote: > Author: ddunbar > Date: Thu Jul 15 14:33:38 2010 > New Revision: 108444 > > URL: http://llvm.org/viewvc/llvm-project?rev=108444&view=rev > Log: > build/Darwin: Add support for embedding version information in tool executables. > > Modified: > llvm/trunk/Makefile.rules > > Modified: llvm/trunk/Makefile.rules > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=108444&r1=108443&r2=108444&view=diff > ============================================================================== > --- llvm/trunk/Makefile.rules (original) > +++ llvm/trunk/Makefile.rules Thu Jul 15 14:33:38 2010 > @@ -1345,6 +1345,27 @@ > endif > endif > > +#--------------------------------------------------------- > +# Tool Version Info Support > +#--------------------------------------------------------- > + > +ifeq ($(HOST_OS),Darwin) > +ifdef TOOL_INFO_PLIST > + > +LD.Flags += -Wl,-sectcreate,__TEXT,__info_plist,$(ObjDir)/$(TOOL_INFO_PLIST) > + > +$(ToolBuildPath): $(ObjDir)/$(TOOL_INFO_PLIST) > + > +$(ObjDir)/$(TOOL_INFO_PLIST): $(PROJ_SRC_DIR)/$(TOOL_INFO_PLIST).in > + $(Echo) "Creating $(TOOLNAME) '$(TOOL_INFO_PLIST)' file..." > + $(Verb)sed -e "s#@TOOL_INFO_UTI@#$(TOOL_INFO_UTI)#g" \ > + -e "s#@TOOL_INFO_NAME@#$(TOOL_INFO_NAME)#g" \ > + -e "s#@TOOL_INFO_VERSION@#$(TOOL_INFO_VERSION)#g" \ > + -e "s#@TOOL_INFO_BUILD_VERSION@#$(TOOL_INFO_BUILD_VERSION)#g" \ > + $< > $@ > + > +endif > +endif > > #--------------------------------------------------------- > # Provide targets for building the tools > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From isanbard at gmail.com Thu Jul 15 15:01:02 2010 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 15 Jul 2010 20:01:02 -0000 Subject: [llvm-commits] [llvm] r108450 - /llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp Message-ID: <20100715200102.523B52A6C12C@llvm.org> Author: void Date: Thu Jul 15 15:01:02 2010 New Revision: 108450 URL: http://llvm.org/viewvc/llvm-project?rev=108450&view=rev Log: Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister. Modified: llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp Modified: llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp?rev=108450&r1=108449&r2=108450&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp (original) +++ llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp Thu Jul 15 15:01:02 2010 @@ -130,7 +130,7 @@ /// KillIndices - The index of the most recent kill (proceding bottom-up), /// or ~0u if the register is not live. - unsigned KillIndices[TargetRegisterInfo::FirstVirtualRegister]; + std::vector KillIndices; public: SchedulePostRATDList(MachineFunction &MF, @@ -140,7 +140,8 @@ AntiDepBreaker *ADB, AliasAnalysis *aa) : ScheduleDAGInstrs(MF, MLI, MDT), Topo(SUnits), - HazardRec(HR), AntiDepBreak(ADB), AA(aa) {} + HazardRec(HR), AntiDepBreak(ADB), AA(aa), + KillIndices(TRI->getNumRegs()) {} ~SchedulePostRATDList() { } From gohman at apple.com Thu Jul 15 15:02:11 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 15 Jul 2010 20:02:11 -0000 Subject: [llvm-commits] [llvm] r108451 - /llvm/trunk/lib/Analysis/ScalarEvolution.cpp Message-ID: <20100715200211.5FC2B2A6C12C@llvm.org> Author: djg Date: Thu Jul 15 15:02:11 2010 New Revision: 108451 URL: http://llvm.org/viewvc/llvm-project?rev=108451&view=rev Log: Teach ScalarEvolution how to fold trunc(undef) and anyext(undef) to undef. This helps LSR behave more consistently on bugpoint-reduced testcases. Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=108451&r1=108450&r2=108451&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Thu Jul 15 15:02:11 2010 @@ -845,6 +845,13 @@ return getAddRecExpr(Operands, AddRec->getLoop()); } + // As a special case, fold trunc(undef) to undef. We don't want to + // know too much about SCEVUnknowns, but this special case is handy + // and harmless. + if (const SCEVUnknown *U = dyn_cast(Op)) + if (isa(U->getValue())) + return getSCEV(UndefValue::get(Ty)); + // The cast wasn't folded; create an explicit cast node. We can reuse // the existing insert position since if we get here, we won't have // made any changes which would invalidate it. @@ -1163,6 +1170,13 @@ return getAddRecExpr(Ops, AR->getLoop()); } + // As a special case, fold anyext(undef) to undef. We don't want to + // know too much about SCEVUnknowns, but this special case is handy + // and harmless. + if (const SCEVUnknown *U = dyn_cast(Op)) + if (isa(U->getValue())) + return getSCEV(UndefValue::get(Ty)); + // If the expression is obviously signed, use the sext cast value. if (isa(Op)) return SExt; From isanbard at gmail.com Thu Jul 15 15:04:36 2010 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 15 Jul 2010 20:04:36 -0000 Subject: [llvm-commits] [llvm] r108452 - /llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Message-ID: <20100715200436.691182A6C12C@llvm.org> Author: void Date: Thu Jul 15 15:04:36 2010 New Revision: 108452 URL: http://llvm.org/viewvc/llvm-project?rev=108452&view=rev Log: Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister. Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=108452&r1=108451&r2=108452&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp (original) +++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Thu Jul 15 15:04:36 2010 @@ -159,8 +159,9 @@ std::map > AliasMemUses, NonAliasMemUses; // Keep track of dangling debug references to registers. - std::pair - DanglingDebugValue[TargetRegisterInfo::FirstVirtualRegister]; + std::vector > + DanglingDebugValue(TRI->getNumRegs(), + std::make_pair(static_cast(0), 0)); // Check to see if the scheduler cares about latencies. bool UnitLatencies = ForceUnitLatencies(); @@ -172,7 +173,6 @@ // Remove any stale debug info; sometimes BuildSchedGraph is called again // without emitting the info from the previous call. DbgValueVec.clear(); - std::memset(DanglingDebugValue, 0, sizeof(DanglingDebugValue)); // Walk the list of instructions, from bottom moving up. for (MachineBasicBlock::iterator MII = InsertPos, MIE = Begin; From isanbard at gmail.com Thu Jul 15 15:08:33 2010 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 15 Jul 2010 13:08:33 -0700 Subject: [llvm-commits] [llvm] r108440 - in /llvm/trunk/lib/CodeGen: AggressiveAntiDepBreaker.cpp AggressiveAntiDepBreaker.h In-Reply-To: References: <20100715184310.1D9332A6C12C@llvm.org> Message-ID: They need to be initialized. They shouldn't need resizing. :) -bw On Jul 15, 2010, at 12:51 PM, Chris Lattner wrote: > Doesn't something need to resize these? > > -Chris > > On Jul 15, 2010, at 11:43 AM, Bill Wendling wrote: > >> Author: void >> Date: Thu Jul 15 13:43:09 2010 >> New Revision: 108440 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=108440&view=rev >> Log: >> Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister. >> >> Modified: >> llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp >> llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h >> >> Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp?rev=108440&r1=108439&r2=108440&view=diff >> ============================================================================== >> --- llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp (original) >> +++ llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp Thu Jul 15 13:43:09 2010 >> @@ -145,8 +145,8 @@ >> State = new AggressiveAntiDepState(TRI->getNumRegs(), BB); >> >> bool IsReturnBlock = (!BB->empty() && BB->back().getDesc().isReturn()); >> - unsigned *KillIndices = State->GetKillIndices(); >> - unsigned *DefIndices = State->GetDefIndices(); >> + std::vector &KillIndices = State->GetKillIndices(); >> + std::vector &DefIndices = State->GetDefIndices(); >> >> // Determine the live-out physregs for this block. >> if (IsReturnBlock) { >> @@ -226,7 +226,7 @@ >> DEBUG(MI->dump()); >> DEBUG(dbgs() << "\tRegs:"); >> >> - unsigned *DefIndices = State->GetDefIndices(); >> + std::vector &DefIndices = State->GetDefIndices(); >> for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { >> // If Reg is current live, then mark that it can't be renamed as >> // we don't know the extent of its live-range anymore (now that it >> @@ -328,8 +328,8 @@ >> const char *tag, >> const char *header, >> const char *footer) { >> - unsigned *KillIndices = State->GetKillIndices(); >> - unsigned *DefIndices = State->GetDefIndices(); >> + std::vector &KillIndices = State->GetKillIndices(); >> + std::vector &DefIndices = State->GetDefIndices(); >> std::multimap& >> RegRefs = State->GetRegRefs(); >> >> @@ -364,7 +364,7 @@ >> void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI, >> unsigned Count, >> std::set& PassthruRegs) { >> - unsigned *DefIndices = State->GetDefIndices(); >> + std::vector &DefIndices = State->GetDefIndices(); >> std::multimap& >> RegRefs = State->GetRegRefs(); >> >> @@ -560,8 +560,8 @@ >> unsigned AntiDepGroupIndex, >> RenameOrderType& RenameOrder, >> std::map &RenameMap) { >> - unsigned *KillIndices = State->GetKillIndices(); >> - unsigned *DefIndices = State->GetDefIndices(); >> + std::vector &KillIndices = State->GetKillIndices(); >> + std::vector &DefIndices = State->GetDefIndices(); >> std::multimap& >> RegRefs = State->GetRegRefs(); >> >> @@ -733,8 +733,8 @@ >> MachineBasicBlock::iterator Begin, >> MachineBasicBlock::iterator End, >> unsigned InsertPosIndex) { >> - unsigned *KillIndices = State->GetKillIndices(); >> - unsigned *DefIndices = State->GetDefIndices(); >> + std::vector &KillIndices = State->GetKillIndices(); >> + std::vector &DefIndices = State->GetDefIndices(); >> std::multimap& >> RegRefs = State->GetRegRefs(); >> >> >> Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h?rev=108440&r1=108439&r2=108440&view=diff >> ============================================================================== >> --- llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h (original) >> +++ llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h Thu Jul 15 13:43:09 2010 >> @@ -66,20 +66,20 @@ >> >> /// KillIndices - The index of the most recent kill (proceding bottom-up), >> /// or ~0u if the register is not live. >> - unsigned KillIndices[TargetRegisterInfo::FirstVirtualRegister]; >> + std::vector KillIndices; >> >> /// DefIndices - The index of the most recent complete def (proceding bottom >> /// up), or ~0u if the register is live. >> - unsigned DefIndices[TargetRegisterInfo::FirstVirtualRegister]; >> + std::vector DefIndices; >> >> public: >> AggressiveAntiDepState(const unsigned TargetRegs, MachineBasicBlock *BB); >> >> /// GetKillIndices - Return the kill indices. >> - unsigned *GetKillIndices() { return KillIndices; } >> + std::vector &GetKillIndices() { return KillIndices; } >> >> /// GetDefIndices - Return the define indices. >> - unsigned *GetDefIndices() { return DefIndices; } >> + std::vector &GetDefIndices() { return DefIndices; } >> >> /// GetRegRefs - Return the RegRefs map. >> std::multimap& GetRegRefs() { return RegRefs; } >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From grosbach at apple.com Thu Jul 15 15:12:12 2010 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 15 Jul 2010 13:12:12 -0700 Subject: [llvm-commits] [llvm] r108328 - /llvm/trunk/lib/Target/ARM/README.txt In-Reply-To: <795E37E6-65DE-45CE-9FC2-4E6F9EC5E286@apple.com> References: <20100714065826.DE7A02A6C12C@llvm.org> <795E37E6-65DE-45CE-9FC2-4E6F9EC5E286@apple.com> Message-ID: <45071856-6877-484B-A71D-4C457AA6E59C@apple.com> Agreed. I'm looking at doing something about this. I don't think it'll be too horrible. -Jim On Jul 14, 2010, at 9:52 AM, Chris Lattner wrote: > Wow, nice catch. The thumb2 code in particular is really terrible, and this pattern occurs all the time for bitfield insertion. > > -Chris > > On Jul 13, 2010, at 11:58 PM, Eli Friedman wrote: > >> Author: efriedma >> Date: Wed Jul 14 01:58:26 2010 >> New Revision: 108328 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=108328&view=rev >> Log: >> A couple potential optimizations inspired by comment 4 in PR6773. >> >> >> Modified: >> llvm/trunk/lib/Target/ARM/README.txt >> >> Modified: llvm/trunk/lib/Target/ARM/README.txt >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/README.txt?rev=108328&r1=108327&r2=108328&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/README.txt (original) >> +++ llvm/trunk/lib/Target/ARM/README.txt Wed Jul 14 01:58:26 2010 >> @@ -590,3 +590,44 @@ >> associated with the comparison. Perhaps a pseudo-instruction for the comparison, >> with a post-codegen pass to clean up and handle the condition codes? >> See PR5694 for testcase. >> + >> +//===---------------------------------------------------------------------===// >> + >> +Given the following on armv5: >> +int test1(int A, int B) { >> + return (A&-8388481)|(B&8388480); >> +} >> + >> +We currently generate: >> + ldr r2, .LCPI0_0 >> + and r0, r0, r2 >> + ldr r2, .LCPI0_1 >> + and r1, r1, r2 >> + orr r0, r1, r0 >> + bx lr >> + >> +We should be able to replace the second ldr+and with a bic (i.e. reuse the >> +constant which was already loaded). Not sure what's necessary to do that. >> + >> +//===---------------------------------------------------------------------===// >> + >> +Given the following on ARMv7: >> +int test1(int A, int B) { >> + return (A&-8388481)|(B&8388480); >> +} >> + >> +We currently generate: >> + bfc r0, #7, #16 >> + movw r2, #:lower16:8388480 >> + movt r2, #:upper16:8388480 >> + and r1, r1, r2 >> + orr r0, r1, r0 >> + bx lr >> + >> +The following is much shorter: >> + lsr r1, r1, #7 >> + bfi r0, r1, #7, #16 >> + bx lr >> + >> + >> +//===---------------------------------------------------------------------===// >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From gohman at apple.com Thu Jul 15 15:12:42 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 15 Jul 2010 20:12:42 -0000 Subject: [llvm-commits] [llvm] r108453 - /llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Message-ID: <20100715201242.69A242A6C12C@llvm.org> Author: djg Date: Thu Jul 15 15:12:42 2010 New Revision: 108453 URL: http://llvm.org/viewvc/llvm-project?rev=108453&view=rev Log: Use dbgs() instead of errs() in a DEBUG. Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=108453&r1=108452&r2=108453&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Thu Jul 15 15:12:42 2010 @@ -2988,7 +2988,7 @@ if (Fixup.LUIdx == LUIdx) { Fixup.LUIdx = LUThatHas - &Uses.front(); Fixup.Offset += F.AM.BaseOffs; - DEBUG(errs() << "New fixup has offset " + DEBUG(dbgs() << "New fixup has offset " << Fixup.Offset << '\n'); } if (Fixup.LUIdx == NumUses-1) From sabre at nondot.org Thu Jul 15 15:13:34 2010 From: sabre at nondot.org (Chris Lattner) Date: Thu, 15 Jul 2010 20:13:34 -0000 Subject: [llvm-commits] [llvm] r108454 - /llvm/trunk/lib/Target/X86/X86InstrMMX.td Message-ID: <20100715201334.E12562A6C12C@llvm.org> Author: lattner Date: Thu Jul 15 15:13:34 2010 New Revision: 108454 URL: http://llvm.org/viewvc/llvm-project?rev=108454&view=rev Log: fix the encoding of MMX_MOVFR642Qrr, it starts with 0xF2 not 0xF3, this fixes rdar://8192860. Unfortunately it can only be triggered with llc because llvm-mc matches another (correctly encoded) version of this, so no testcase. Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrMMX.td?rev=108454&r1=108453&r2=108454&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrMMX.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrMMX.td Thu Jul 15 15:13:34 2010 @@ -164,7 +164,7 @@ def MMX_MOVQ2FR64rr: SSDIi8<0xD6, MRMSrcReg, (outs FR64:$dst), (ins VR64:$src), "movq2dq\t{$src, $dst|$dst, $src}", []>; -def MMX_MOVFR642Qrr: SSDIi8<0xD6, MRMSrcReg, (outs VR64:$dst), (ins FR64:$src), +def MMX_MOVFR642Qrr: SDIi8<0xD6, MRMSrcReg, (outs VR64:$dst), (ins FR64:$src), "movdq2q\t{$src, $dst|$dst, $src}", []>; def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src), From clattner at apple.com Thu Jul 15 15:16:27 2010 From: clattner at apple.com (Chris Lattner) Date: Thu, 15 Jul 2010 13:16:27 -0700 Subject: [llvm-commits] [llvm] r108440 - in /llvm/trunk/lib/CodeGen: AggressiveAntiDepBreaker.cpp AggressiveAntiDepBreaker.h In-Reply-To: References: <20100715184310.1D9332A6C12C@llvm.org> Message-ID: works for me, thanks. On Jul 15, 2010, at 1:08 PM, Bill Wendling wrote: > They need to be initialized. They shouldn't need resizing. :) > > -bw > > On Jul 15, 2010, at 12:51 PM, Chris Lattner wrote: > >> Doesn't something need to resize these? >> >> -Chris >> >> On Jul 15, 2010, at 11:43 AM, Bill Wendling wrote: >> >>> Author: void >>> Date: Thu Jul 15 13:43:09 2010 >>> New Revision: 108440 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=108440&view=rev >>> Log: >>> Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister. >>> >>> Modified: >>> llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp >>> llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h >>> >>> Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp?rev=108440&r1=108439&r2=108440&view=diff >>> ============================================================================== >>> --- llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp (original) >>> +++ llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp Thu Jul 15 13:43:09 2010 >>> @@ -145,8 +145,8 @@ >>> State = new AggressiveAntiDepState(TRI->getNumRegs(), BB); >>> >>> bool IsReturnBlock = (!BB->empty() && BB->back().getDesc().isReturn()); >>> - unsigned *KillIndices = State->GetKillIndices(); >>> - unsigned *DefIndices = State->GetDefIndices(); >>> + std::vector &KillIndices = State->GetKillIndices(); >>> + std::vector &DefIndices = State->GetDefIndices(); >>> >>> // Determine the live-out physregs for this block. >>> if (IsReturnBlock) { >>> @@ -226,7 +226,7 @@ >>> DEBUG(MI->dump()); >>> DEBUG(dbgs() << "\tRegs:"); >>> >>> - unsigned *DefIndices = State->GetDefIndices(); >>> + std::vector &DefIndices = State->GetDefIndices(); >>> for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { >>> // If Reg is current live, then mark that it can't be renamed as >>> // we don't know the extent of its live-range anymore (now that it >>> @@ -328,8 +328,8 @@ >>> const char *tag, >>> const char *header, >>> const char *footer) { >>> - unsigned *KillIndices = State->GetKillIndices(); >>> - unsigned *DefIndices = State->GetDefIndices(); >>> + std::vector &KillIndices = State->GetKillIndices(); >>> + std::vector &DefIndices = State->GetDefIndices(); >>> std::multimap& >>> RegRefs = State->GetRegRefs(); >>> >>> @@ -364,7 +364,7 @@ >>> void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI, >>> unsigned Count, >>> std::set& PassthruRegs) { >>> - unsigned *DefIndices = State->GetDefIndices(); >>> + std::vector &DefIndices = State->GetDefIndices(); >>> std::multimap& >>> RegRefs = State->GetRegRefs(); >>> >>> @@ -560,8 +560,8 @@ >>> unsigned AntiDepGroupIndex, >>> RenameOrderType& RenameOrder, >>> std::map &RenameMap) { >>> - unsigned *KillIndices = State->GetKillIndices(); >>> - unsigned *DefIndices = State->GetDefIndices(); >>> + std::vector &KillIndices = State->GetKillIndices(); >>> + std::vector &DefIndices = State->GetDefIndices(); >>> std::multimap& >>> RegRefs = State->GetRegRefs(); >>> >>> @@ -733,8 +733,8 @@ >>> MachineBasicBlock::iterator Begin, >>> MachineBasicBlock::iterator End, >>> unsigned InsertPosIndex) { >>> - unsigned *KillIndices = State->GetKillIndices(); >>> - unsigned *DefIndices = State->GetDefIndices(); >>> + std::vector &KillIndices = State->GetKillIndices(); >>> + std::vector &DefIndices = State->GetDefIndices(); >>> std::multimap& >>> RegRefs = State->GetRegRefs(); >>> >>> >>> Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h?rev=108440&r1=108439&r2=108440&view=diff >>> ============================================================================== >>> --- llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h (original) >>> +++ llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h Thu Jul 15 13:43:09 2010 >>> @@ -66,20 +66,20 @@ >>> >>> /// KillIndices - The index of the most recent kill (proceding bottom-up), >>> /// or ~0u if the register is not live. >>> - unsigned KillIndices[TargetRegisterInfo::FirstVirtualRegister]; >>> + std::vector KillIndices; >>> >>> /// DefIndices - The index of the most recent complete def (proceding bottom >>> /// up), or ~0u if the register is live. >>> - unsigned DefIndices[TargetRegisterInfo::FirstVirtualRegister]; >>> + std::vector DefIndices; >>> >>> public: >>> AggressiveAntiDepState(const unsigned TargetRegs, MachineBasicBlock *BB); >>> >>> /// GetKillIndices - Return the kill indices. >>> - unsigned *GetKillIndices() { return KillIndices; } >>> + std::vector &GetKillIndices() { return KillIndices; } >>> >>> /// GetDefIndices - Return the define indices. >>> - unsigned *GetDefIndices() { return DefIndices; } >>> + std::vector &GetDefIndices() { return DefIndices; } >>> >>> /// GetRegRefs - Return the RegRefs map. >>> std::multimap& GetRegRefs() { return RegRefs; } >>> >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From clattner at apple.com Thu Jul 15 15:16:40 2010 From: clattner at apple.com (Chris Lattner) Date: Thu, 15 Jul 2010 13:16:40 -0700 Subject: [llvm-commits] [llvm] r108328 - /llvm/trunk/lib/Target/ARM/README.txt In-Reply-To: <45071856-6877-484B-A71D-4C457AA6E59C@apple.com> References: <20100714065826.DE7A02A6C12C@llvm.org> <795E37E6-65DE-45CE-9FC2-4E6F9EC5E286@apple.com> <45071856-6877-484B-A71D-4C457AA6E59C@apple.com> Message-ID: <50043384-B144-4B6A-8667-5227F028C302@apple.com> Excellent, thanks! On Jul 15, 2010, at 1:12 PM, Jim Grosbach wrote: > Agreed. I'm looking at doing something about this. I don't think it'll be too horrible. > > -Jim > > On Jul 14, 2010, at 9:52 AM, Chris Lattner wrote: > >> Wow, nice catch. The thumb2 code in particular is really terrible, and this pattern occurs all the time for bitfield insertion. >> >> -Chris >> >> On Jul 13, 2010, at 11:58 PM, Eli Friedman wrote: >> >>> Author: efriedma >>> Date: Wed Jul 14 01:58:26 2010 >>> New Revision: 108328 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=108328&view=rev >>> Log: >>> A couple potential optimizations inspired by comment 4 in PR6773. >>> >>> >>> Modified: >>> llvm/trunk/lib/Target/ARM/README.txt >>> >>> Modified: llvm/trunk/lib/Target/ARM/README.txt >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/README.txt?rev=108328&r1=108327&r2=108328&view=diff >>> ============================================================================== >>> --- llvm/trunk/lib/Target/ARM/README.txt (original) >>> +++ llvm/trunk/lib/Target/ARM/README.txt Wed Jul 14 01:58:26 2010 >>> @@ -590,3 +590,44 @@ >>> associated with the comparison. Perhaps a pseudo-instruction for the comparison, >>> with a post-codegen pass to clean up and handle the condition codes? >>> See PR5694 for testcase. >>> + >>> +//===---------------------------------------------------------------------===// >>> + >>> +Given the following on armv5: >>> +int test1(int A, int B) { >>> + return (A&-8388481)|(B&8388480); >>> +} >>> + >>> +We currently generate: >>> + ldr r2, .LCPI0_0 >>> + and r0, r0, r2 >>> + ldr r2, .LCPI0_1 >>> + and r1, r1, r2 >>> + orr r0, r1, r0 >>> + bx lr >>> + >>> +We should be able to replace the second ldr+and with a bic (i.e. reuse the >>> +constant which was already loaded). Not sure what's necessary to do that. >>> + >>> +//===---------------------------------------------------------------------===// >>> + >>> +Given the following on ARMv7: >>> +int test1(int A, int B) { >>> + return (A&-8388481)|(B&8388480); >>> +} >>> + >>> +We currently generate: >>> + bfc r0, #7, #16 >>> + movw r2, #:lower16:8388480 >>> + movt r2, #:upper16:8388480 >>> + and r1, r1, r2 >>> + orr r0, r1, r0 >>> + bx lr >>> + >>> +The following is much shorter: >>> + lsr r1, r1, #7 >>> + bfi r0, r1, #7, #16 >>> + bx lr >>> + >>> + >>> +//===---------------------------------------------------------------------===// >>> >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From gohman at apple.com Thu Jul 15 15:24:58 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 15 Jul 2010 20:24:58 -0000 Subject: [llvm-commits] [llvm] r108455 - /llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Message-ID: <20100715202458.ABD8E2A6C12C@llvm.org> Author: djg Date: Thu Jul 15 15:24:58 2010 New Revision: 108455 URL: http://llvm.org/viewvc/llvm-project?rev=108455&view=rev Log: Don't merge uses when they are targetting fixup sites with different widths. In a use with a narrower fixup, formulae may be wider than the fixup, in which case the high bits aren't necessarily meaningful, so it isn't safe to reuse them for uses with wider fixups. This fixes PR7618, though the testcase is too large for a reasonable regression test, since it heavily dependes on hitting LSR's heuristics in a certain way. Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=108455&r1=108454&r2=108455&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Thu Jul 15 15:24:58 2010 @@ -965,6 +965,12 @@ /// may be used. bool AllFixupsOutsideLoop; + /// WidestFixupType - This records the widest use type for any fixup using + /// this LSRUse. FindUseWithSimilarFormula can't consider uses with different + /// max fixup widths to be equivalent, because the narrower one may be relying + /// on the implicit truncation to truncate away bogus bits. + const Type *WidestFixupType; + /// Formulae - A list of ways to build a value that can satisfy this user. /// After the list is populated, one of these is selected heuristically and /// used to formulate a replacement for OperandValToReplace in UserInst. @@ -976,7 +982,8 @@ LSRUse(KindType K, const Type *T) : Kind(K), AccessTy(T), MinOffset(INT64_MAX), MaxOffset(INT64_MIN), - AllFixupsOutsideLoop(true) {} + AllFixupsOutsideLoop(true), + WidestFixupType(0) {} bool HasFormulaWithSameRegs(const Formula &F) const; bool InsertFormula(const Formula &F); @@ -1083,6 +1090,9 @@ if (AllFixupsOutsideLoop) OS << ", all-fixups-outside-loop"; + + if (WidestFixupType) + OS << ", widest fixup type: " << *WidestFixupType; } void LSRUse::dump() const { @@ -1928,6 +1938,7 @@ if (&LU != &OrigLU && LU.Kind != LSRUse::ICmpZero && LU.Kind == OrigLU.Kind && OrigLU.AccessTy == LU.AccessTy && + LU.WidestFixupType == OrigLU.WidestFixupType && LU.HasFormulaWithSameRegs(OrigF)) { for (SmallVectorImpl::const_iterator I = LU.Formulae.begin(), E = LU.Formulae.end(); I != E; ++I) { @@ -2066,6 +2077,10 @@ LF.Offset = P.second; LSRUse &LU = Uses[LF.LUIdx]; LU.AllFixupsOutsideLoop &= LF.isUseFullyOutsideLoop(L); + if (!LU.WidestFixupType || + SE.getTypeSizeInBits(LU.WidestFixupType) < + SE.getTypeSizeInBits(LF.OperandValToReplace->getType())) + LU.WidestFixupType = LF.OperandValToReplace->getType(); // If this is the first use of this LSRUse, give it a formula. if (LU.Formulae.empty()) { @@ -2195,6 +2210,10 @@ LF.Offset = P.second; LSRUse &LU = Uses[LF.LUIdx]; LU.AllFixupsOutsideLoop &= LF.isUseFullyOutsideLoop(L); + if (!LU.WidestFixupType || + SE.getTypeSizeInBits(LU.WidestFixupType) < + SE.getTypeSizeInBits(LF.OperandValToReplace->getType())) + LU.WidestFixupType = LF.OperandValToReplace->getType(); InsertSupplementalFormula(U, LU, LF.LUIdx); CountRegisters(LU.Formulae.back(), Uses.size() - 1); break; From dpatel at apple.com Thu Jul 15 15:25:51 2010 From: dpatel at apple.com (Devang Patel) Date: Thu, 15 Jul 2010 20:25:51 -0000 Subject: [llvm-commits] [llvm] r108456 - /llvm/trunk/Makefile.rules Message-ID: <20100715202551.6343C2A6C12C@llvm.org> Author: dpatel Date: Thu Jul 15 15:25:51 2010 New Revision: 108456 URL: http://llvm.org/viewvc/llvm-project?rev=108456&view=rev Log: Revert 108444. It breaks a build. Modified: llvm/trunk/Makefile.rules Modified: llvm/trunk/Makefile.rules URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=108456&r1=108455&r2=108456&view=diff ============================================================================== --- llvm/trunk/Makefile.rules (original) +++ llvm/trunk/Makefile.rules Thu Jul 15 15:25:51 2010 @@ -1345,27 +1345,6 @@ endif endif -#--------------------------------------------------------- -# Tool Version Info Support -#--------------------------------------------------------- - -ifeq ($(HOST_OS),Darwin) -ifdef TOOL_INFO_PLIST - -LD.Flags += -Wl,-sectcreate,__TEXT,__info_plist,$(ObjDir)/$(TOOL_INFO_PLIST) - -$(ToolBuildPath): $(ObjDir)/$(TOOL_INFO_PLIST) - -$(ObjDir)/$(TOOL_INFO_PLIST): $(PROJ_SRC_DIR)/$(TOOL_INFO_PLIST).in - $(Echo) "Creating $(TOOLNAME) '$(TOOL_INFO_PLIST)' file..." - $(Verb)sed -e "s#@TOOL_INFO_UTI@#$(TOOL_INFO_UTI)#g" \ - -e "s#@TOOL_INFO_NAME@#$(TOOL_INFO_NAME)#g" \ - -e "s#@TOOL_INFO_VERSION@#$(TOOL_INFO_VERSION)#g" \ - -e "s#@TOOL_INFO_BUILD_VERSION@#$(TOOL_INFO_BUILD_VERSION)#g" \ - $< > $@ - -endif -endif #--------------------------------------------------------- # Provide targets for building the tools From dpatel at apple.com Thu Jul 15 15:57:09 2010 From: dpatel at apple.com (Devang Patel) Date: Thu, 15 Jul 2010 20:57:09 -0000 Subject: [llvm-commits] [llvm] r108458 - /llvm/trunk/Makefile.rules Message-ID: <20100715205709.E7D662A6C12C@llvm.org> Author: dpatel Date: Thu Jul 15 15:57:09 2010 New Revision: 108458 URL: http://llvm.org/viewvc/llvm-project?rev=108458&view=rev Log: Revert 108456. i.e. bring back r108444. Modified: llvm/trunk/Makefile.rules Modified: llvm/trunk/Makefile.rules URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=108458&r1=108457&r2=108458&view=diff ============================================================================== --- llvm/trunk/Makefile.rules (original) +++ llvm/trunk/Makefile.rules Thu Jul 15 15:57:09 2010 @@ -1345,6 +1345,27 @@ endif endif +#--------------------------------------------------------- +# Tool Version Info Support +#--------------------------------------------------------- + +ifeq ($(HOST_OS),Darwin) +ifdef TOOL_INFO_PLIST + +LD.Flags += -Wl,-sectcreate,__TEXT,__info_plist,$(ObjDir)/$(TOOL_INFO_PLIST) + +$(ToolBuildPath): $(ObjDir)/$(TOOL_INFO_PLIST) + +$(ObjDir)/$(TOOL_INFO_PLIST): $(PROJ_SRC_DIR)/$(TOOL_INFO_PLIST).in + $(Echo) "Creating $(TOOLNAME) '$(TOOL_INFO_PLIST)' file..." + $(Verb)sed -e "s#@TOOL_INFO_UTI@#$(TOOL_INFO_UTI)#g" \ + -e "s#@TOOL_INFO_NAME@#$(TOOL_INFO_NAME)#g" \ + -e "s#@TOOL_INFO_VERSION@#$(TOOL_INFO_VERSION)#g" \ + -e "s#@TOOL_INFO_BUILD_VERSION@#$(TOOL_INFO_BUILD_VERSION)#g" \ + $< > $@ + +endif +endif #--------------------------------------------------------- # Provide targets for building the tools From sabre at nondot.org Thu Jul 15 16:19:31 2010 From: sabre at nondot.org (Chris Lattner) Date: Thu, 15 Jul 2010 21:19:31 -0000 Subject: [llvm-commits] [llvm] r108460 - /llvm/trunk/lib/MC/MCParser/AsmParser.cpp Message-ID: <20100715211931.7AD792A6C12C@llvm.org> Author: lattner Date: Thu Jul 15 16:19:31 2010 New Revision: 108460 URL: http://llvm.org/viewvc/llvm-project?rev=108460&view=rev Log: fix indentation and 80 cols Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=108460&r1=108459&r2=108460&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Thu Jul 15 16:19:31 2010 @@ -1081,13 +1081,14 @@ bool UseCodeAlign = false; if (const MCSectionMachO *S = dyn_cast( getStreamer().getCurrentSection())) - UseCodeAlign = S->hasAttribute(MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS); + UseCodeAlign = S->hasAttribute(MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS); if ((!HasFillExpr || Lexer.getMAI().getTextAlignFillValue() == FillExpr) && ValueSize == 1 && UseCodeAlign) { getStreamer().EmitCodeAlignment(Alignment, MaxBytesToFill); } else { // FIXME: Target specific behavior about how the "extra" bytes are filled. - getStreamer().EmitValueToAlignment(Alignment, FillExpr, ValueSize, MaxBytesToFill); + getStreamer().EmitValueToAlignment(Alignment, FillExpr, ValueSize, + MaxBytesToFill); } return false; From sabre at nondot.org Thu Jul 15 16:22:00 2010 From: sabre at nondot.org (Chris Lattner) Date: Thu, 15 Jul 2010 21:22:00 -0000 Subject: [llvm-commits] [llvm] r108461 - in /llvm/trunk: lib/CodeGen/TargetLoweringObjectFileImpl.cpp test/CodeGen/X86/global-sections.ll Message-ID: <20100715212200.988392A6C12C@llvm.org> Author: lattner Date: Thu Jul 15 16:22:00 2010 New Revision: 108461 URL: http://llvm.org/viewvc/llvm-project?rev=108461&view=rev Log: fix the definitions of ConstTextCoalSection/ConstDataCoalSection to keep "Text" in sync with the "pure instructions" section attribute. Lack of this attribute was preventing the assembler from emitting multibyte noops instructions for templates (and inlines, and other coalesced stuff) and was causing the assembler to mismatch .o files. This fixes rdar://8018335 Modified: llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp llvm/trunk/test/CodeGen/X86/global-sections.ll Modified: llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp?rev=108461&r1=108460&r2=108461&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp (original) +++ llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp Thu Jul 15 16:22:00 2010 @@ -518,12 +518,13 @@ SectionKind::getText()); ConstTextCoalSection = getContext().getMachOSection("__TEXT", "__const_coal", - MCSectionMachO::S_COALESCED, + MCSectionMachO::S_COALESCED | + MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS, SectionKind::getText()); ConstDataCoalSection = getContext().getMachOSection("__DATA","__const_coal", MCSectionMachO::S_COALESCED, - SectionKind::getText()); + SectionKind::getReadOnly()); ConstDataSection // .const_data = getContext().getMachOSection("__DATA", "__const", 0, SectionKind::getReadOnlyWithRel()); Modified: llvm/trunk/test/CodeGen/X86/global-sections.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/global-sections.ll?rev=108461&r1=108460&r2=108461&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/global-sections.ll (original) +++ llvm/trunk/test/CodeGen/X86/global-sections.ll Thu Jul 15 16:22:00 2010 @@ -20,7 +20,7 @@ ; TODO: linux drops this into .rodata, we drop it into ".gnu.linkonce.r.G2" -; DARWIN: .section __TEXT,__const_coal,coalesced +; DARWIN: .section __TEXT,__const_coal,coalesced,pure_instructions ; DARWIN: _G2: ; DARWIN: .long 42 @@ -85,7 +85,7 @@ ; LINUX: .byte 1 ; LINUX: .size G6, 1 -; DARWIN: .section __TEXT,__const_coal,coalesced +; DARWIN: .section __TEXT,__const_coal,coalesced,pure_instructions ; DARWIN: .globl _G6 ; DARWIN: .weak_definition _G6 ; DARWIN:_G6: From sabre at nondot.org Thu Jul 15 16:24:02 2010 From: sabre at nondot.org (Chris Lattner) Date: Thu, 15 Jul 2010 21:24:02 -0000 Subject: [llvm-commits] [llvm] r108462 - /llvm/trunk/include/llvm/Support/IRBuilder.h Message-ID: <20100715212402.6C8852A6C12C@llvm.org> Author: lattner Date: Thu Jul 15 16:24:02 2010 New Revision: 108462 URL: http://llvm.org/viewvc/llvm-project?rev=108462&view=rev Log: remove some unneeded overloads that were causing ambiguity problems on some systems. Modified: llvm/trunk/include/llvm/Support/IRBuilder.h Modified: llvm/trunk/include/llvm/Support/IRBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/IRBuilder.h?rev=108462&r1=108461&r2=108462&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/IRBuilder.h (original) +++ llvm/trunk/include/llvm/Support/IRBuilder.h Thu Jul 15 16:24:02 2010 @@ -165,41 +165,21 @@ } /// getInt8 - Get a constant 8-bit value. - ConstantInt *getInt8(int8_t C) { - return ConstantInt::getSigned(getInt8Ty(), C); - } - - /// getInt8 - Get a constant 8-bit value. ConstantInt *getInt8(uint8_t C) { return ConstantInt::get(getInt8Ty(), C); } /// getInt16 - Get a constant 16-bit value. - ConstantInt *getInt16(int16_t C) { - return ConstantInt::getSigned(getInt16Ty(), C); - } - - /// getInt16 - Get a constant 16-bit value. ConstantInt *getInt16(uint16_t C) { return ConstantInt::get(getInt16Ty(), C); } /// getInt32 - Get a constant 32-bit value. - ConstantInt *getInt32(int32_t C) { - return ConstantInt::getSigned(getInt32Ty(), C); - } - - /// getInt32 - Get a constant 32-bit value. ConstantInt *getInt32(uint32_t C) { return ConstantInt::get(getInt32Ty(), C); } /// getInt64 - Get a constant 64-bit value. - ConstantInt *getInt64(int64_t C) { - return ConstantInt::getSigned(getInt64Ty(), C); - } - - /// getInt64 - Get a constant 64-bit value. ConstantInt *getInt64(uint64_t C) { return ConstantInt::get(getInt64Ty(), C); } From daniel at zuster.org Thu Jul 15 16:51:53 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 15 Jul 2010 21:51:53 -0000 Subject: [llvm-commits] [llvm] r108463 - /llvm/trunk/Makefile.rules Message-ID: <20100715215153.1BA342A6C12C@llvm.org> Author: ddunbar Date: Thu Jul 15 16:51:52 2010 New Revision: 108463 URL: http://llvm.org/viewvc/llvm-project?rev=108463&view=rev Log: build/Darwin: Add a missing directory dependency. Modified: llvm/trunk/Makefile.rules Modified: llvm/trunk/Makefile.rules URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=108463&r1=108462&r2=108463&view=diff ============================================================================== --- llvm/trunk/Makefile.rules (original) +++ llvm/trunk/Makefile.rules Thu Jul 15 16:51:52 2010 @@ -1356,7 +1356,7 @@ $(ToolBuildPath): $(ObjDir)/$(TOOL_INFO_PLIST) -$(ObjDir)/$(TOOL_INFO_PLIST): $(PROJ_SRC_DIR)/$(TOOL_INFO_PLIST).in +$(ObjDir)/$(TOOL_INFO_PLIST): $(PROJ_SRC_DIR)/$(TOOL_INFO_PLIST).in $(ObjDir)/.dir $(Echo) "Creating $(TOOLNAME) '$(TOOL_INFO_PLIST)' file..." $(Verb)sed -e "s#@TOOL_INFO_UTI@#$(TOOL_INFO_UTI)#g" \ -e "s#@TOOL_INFO_NAME@#$(TOOL_INFO_NAME)#g" \ From evan.cheng at apple.com Thu Jul 15 17:07:13 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 15 Jul 2010 22:07:13 -0000 Subject: [llvm-commits] [llvm] r108465 - in /llvm/trunk: include/llvm/Target/TargetOptions.h lib/CodeGen/Analysis.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp lib/Target/TargetMachine.cpp lib/Target/X86/X86ISelLowering.cpp test/CodeGen/ARM/fpcmp-opt.ll test/CodeGen/X86/2006-05-22-FPSetEQ.ll test/CodeGen/X86/fabs.ll test/CodeGen/X86/sse-minmax.ll Message-ID: <20100715220713.6A04E2A6C12C@llvm.org> Author: evancheng Date: Thu Jul 15 17:07:12 2010 New Revision: 108465 URL: http://llvm.org/viewvc/llvm-project?rev=108465&view=rev Log: Split -enable-finite-only-fp-math to two options: -enable-no-nans-fp-math and -enable-no-infs-fp-math. All of the current codegen fp math optimizations only care whether the fp arithmetics arguments and results can never be NaN. Modified: llvm/trunk/include/llvm/Target/TargetOptions.h llvm/trunk/lib/CodeGen/Analysis.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp llvm/trunk/lib/Target/TargetMachine.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/test/CodeGen/ARM/fpcmp-opt.ll llvm/trunk/test/CodeGen/X86/2006-05-22-FPSetEQ.ll llvm/trunk/test/CodeGen/X86/fabs.ll llvm/trunk/test/CodeGen/X86/sse-minmax.ll Modified: llvm/trunk/include/llvm/Target/TargetOptions.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetOptions.h?rev=108465&r1=108464&r2=108465&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetOptions.h (original) +++ llvm/trunk/include/llvm/Target/TargetOptions.h Thu Jul 15 17:07:12 2010 @@ -71,13 +71,18 @@ /// UnsafeFPMath implies LessPreciseFPMAD. extern bool UnsafeFPMath; - /// FiniteOnlyFPMath - This returns true when the -enable-finite-only-fp-math - /// option is specified on the command line. If this returns false (default), - /// the code generator is not allowed to assume that FP arithmetic arguments - /// and results are never NaNs or +-Infs. - extern bool FiniteOnlyFPMathOption; - extern bool FiniteOnlyFPMath(); - + /// NoInfsFPMath - This flag is enabled when the + /// -enable-no-infs-fp-math flag is specified on the command line. When + /// this flag is off (the default), the code generator is not allowed to + /// assume the FP arithmetic arguments and results are never +-Infs. + extern bool NoInfsFPMath; + + /// NoNaNsFPMath - This flag is enabled when the + /// -enable-no-nans-fp-math flag is specified on the command line. When + /// this flag is off (the default), the code generator is not allowed to + /// assume the FP arithmetic arguments and results are never NaNs. + extern bool NoNaNsFPMath; + /// HonorSignDependentRoundingFPMath - This returns true when the /// -enable-sign-dependent-rounding-fp-math is specified. If this returns /// false (the default), the code generator is allowed to assume that the Modified: llvm/trunk/lib/CodeGen/Analysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Analysis.cpp?rev=108465&r1=108464&r2=108465&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/Analysis.cpp (original) +++ llvm/trunk/lib/CodeGen/Analysis.cpp Thu Jul 15 17:07:12 2010 @@ -171,7 +171,7 @@ FOC = FPC = ISD::SETFALSE; break; } - if (FiniteOnlyFPMath()) + if (NoNaNsFPMath) return FOC; else return FPC; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=108465&r1=108464&r2=108465&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Jul 15 17:07:12 2010 @@ -2236,7 +2236,7 @@ bool SelectionDAG::isKnownNeverNaN(SDValue Op) const { // If we're told that NaNs won't happen, assume they won't. - if (FiniteOnlyFPMath()) + if (NoNaNsFPMath) return true; // If the value is a constant, we can obviously see if it is a NaN or not. Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=108465&r1=108464&r2=108465&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Jul 15 17:07:12 2010 @@ -2403,8 +2403,9 @@ bool SeenZero = false; if (canChangeToInt(LHS, SeenZero, Subtarget) && canChangeToInt(RHS, SeenZero, Subtarget) && - // If one of the operand is zero, it's safe to ignore the NaN case. - (FiniteOnlyFPMath() || SeenZero)) { + // If one of the operand is zero, it's safe to ignore the NaN case since + // we only care about equality comparisons. + (SeenZero || (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)))) { // If unsafe fp math optimization is enabled and there are no othter uses of // the CMP operands, and the condition code is EQ oe NE, we can optimize it // to an integer comparison. @@ -4561,7 +4562,7 @@ static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) { // If the target supports NEON, try to use vmax/vmin instructions for f32 - // selects like "x < y ? x : y". Unless the FiniteOnlyFPMath option is set, + // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set, // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is // a NaN; only do the transformation when it matches that behavior. Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp?rev=108465&r1=108464&r2=108465&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp Thu Jul 15 17:07:12 2010 @@ -1174,7 +1174,7 @@ Twine(ARMBuildAttrs::ABI_FP_exceptions) + ", 1"); } - if (FiniteOnlyFPMath()) + if (NoInfsFPMath && NoNaNsFPMath) OutStreamer.EmitRawText("\t.eabi_attribute " + Twine(ARMBuildAttrs::ABI_FP_number_model)+ ", 1"); else Modified: llvm/trunk/lib/Target/TargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetMachine.cpp?rev=108465&r1=108464&r2=108465&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetMachine.cpp (original) +++ llvm/trunk/lib/Target/TargetMachine.cpp Thu Jul 15 17:07:12 2010 @@ -30,7 +30,8 @@ bool NoFramePointerElimNonLeaf; bool NoExcessFPPrecision; bool UnsafeFPMath; - bool FiniteOnlyFPMathOption; + bool NoInfsFPMath; + bool NoNaNsFPMath; bool HonorSignDependentRoundingFPMathOption; bool UseSoftFloat; FloatABI::ABIType FloatABIType; @@ -80,9 +81,14 @@ cl::location(UnsafeFPMath), cl::init(false)); static cl::opt -EnableFiniteOnlyFPMath("enable-finite-only-fp-math", - cl::desc("Enable optimizations that assumes non- NaNs / +-Infs"), - cl::location(FiniteOnlyFPMathOption), +EnableNoInfsFPMath("enable-no-infs-fp-math", + cl::desc("Enable FP math optimizations that assume no +-Infs"), + cl::location(NoInfsFPMath), + cl::init(false)); +static cl::opt +EnableNoNaNsFPMath("enable-no-nans-fp-math", + cl::desc("Enable FP math optimizations that assume no NaNs"), + cl::location(NoNaNsFPMath), cl::init(false)); static cl::opt EnableHonorSignDependentRoundingFPMath("enable-sign-dependent-rounding-fp-math", @@ -290,12 +296,6 @@ /// result is "less precise" than doing those operations individually. bool LessPreciseFPMAD() { return UnsafeFPMath || LessPreciseFPMADOption; } - /// FiniteOnlyFPMath - This returns true when the -enable-finite-only-fp-math - /// option is specified on the command line. If this returns false (default), - /// the code generator is not allowed to assume that FP arithmetic arguments - /// and results are never NaNs or +-Infs. - bool FiniteOnlyFPMath() { return FiniteOnlyFPMathOption; } - /// HonorSignDependentRoundingFPMath - Return true if the codegen must assume /// that the rounding mode of the FPU can change from its default. bool HonorSignDependentRoundingFPMath() { Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=108465&r1=108464&r2=108465&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Jul 15 17:07:12 2010 @@ -9087,8 +9087,7 @@ // Converting this to a min would handle NaNs incorrectly, and swapping // the operands would cause it to handle comparisons between positive // and negative zero incorrectly. - if (!FiniteOnlyFPMath() && - (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) { + if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { if (!UnsafeFPMath && !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) break; @@ -9126,8 +9125,7 @@ // Converting this to a max would handle NaNs incorrectly, and swapping // the operands would cause it to handle comparisons between positive // and negative zero incorrectly. - if (!FiniteOnlyFPMath() && - (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) { + if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { if (!UnsafeFPMath && !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) break; @@ -9156,8 +9154,7 @@ // cause it to handle NaNs incorrectly. if (!UnsafeFPMath && !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) { - if (!FiniteOnlyFPMath() && - (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) + if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) break; std::swap(LHS, RHS); } @@ -9182,8 +9179,7 @@ case ISD::SETULT: // Converting this to a max would handle NaNs incorrectly. - if (!FiniteOnlyFPMath() && - (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) + if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) break; Opcode = X86ISD::FMAX; break; @@ -9193,8 +9189,7 @@ // cause it to handle NaNs incorrectly. if (!UnsafeFPMath && !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) { - if (!FiniteOnlyFPMath() && - (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) + if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) break; std::swap(LHS, RHS); } Modified: llvm/trunk/test/CodeGen/ARM/fpcmp-opt.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fpcmp-opt.ll?rev=108465&r1=108464&r2=108465&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fpcmp-opt.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fpcmp-opt.ll Thu Jul 15 17:07:12 2010 @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mcpu=cortex-a8 -mattr=+vfp2 -enable-unsafe-fp-math -enable-finite-only-fp-math | FileCheck -check-prefix=FINITE %s +; RUN: llc < %s -march=arm -mcpu=cortex-a8 -mattr=+vfp2 -enable-unsafe-fp-math -enable-no-nans-fp-math | FileCheck -check-prefix=FINITE %s ; RUN: llc < %s -march=arm -mcpu=cortex-a8 -mattr=+vfp2 -enable-unsafe-fp-math | FileCheck -check-prefix=NAN %s ; rdar://7461510 Modified: llvm/trunk/test/CodeGen/X86/2006-05-22-FPSetEQ.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2006-05-22-FPSetEQ.ll?rev=108465&r1=108464&r2=108465&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2006-05-22-FPSetEQ.ll (original) +++ llvm/trunk/test/CodeGen/X86/2006-05-22-FPSetEQ.ll Thu Jul 15 17:07:12 2010 @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=x86 | grep setnp -; RUN: llc < %s -march=x86 -enable-unsafe-fp-math -enable-finite-only-fp-math | \ +; RUN: llc < %s -march=x86 -enable-unsafe-fp-math -enable-no-nans-fp-math | \ ; RUN: not grep setnp define i32 @test(float %f) { Modified: llvm/trunk/test/CodeGen/X86/fabs.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fabs.ll?rev=108465&r1=108464&r2=108465&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/fabs.ll (original) +++ llvm/trunk/test/CodeGen/X86/fabs.ll Thu Jul 15 17:07:12 2010 @@ -1,7 +1,7 @@ ; Make sure this testcase codegens to the fabs instruction, not a call to fabsf ; RUN: llc < %s -march=x86 -mattr=-sse2,-sse3,-sse | grep fabs\$ | \ ; RUN: count 2 -; RUN: llc < %s -march=x86 -mattr=-sse,-sse2,-sse3 -enable-unsafe-fp-math -enable-finite-only-fp-math | \ +; RUN: llc < %s -march=x86 -mattr=-sse,-sse2,-sse3 -enable-unsafe-fp-math -enable-no-nans-fp-math | \ ; RUN: grep fabs\$ | count 3 declare float @fabsf(float) Modified: llvm/trunk/test/CodeGen/X86/sse-minmax.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-minmax.ll?rev=108465&r1=108464&r2=108465&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/sse-minmax.ll (original) +++ llvm/trunk/test/CodeGen/X86/sse-minmax.ll Thu Jul 15 17:07:12 2010 @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=x86-64 -asm-verbose=false | FileCheck %s -; RUN: llc < %s -march=x86-64 -asm-verbose=false -enable-unsafe-fp-math -enable-finite-only-fp-math | FileCheck -check-prefix=UNSAFE %s -; RUN: llc < %s -march=x86-64 -asm-verbose=false -enable-finite-only-fp-math | FileCheck -check-prefix=FINITE %s +; RUN: llc < %s -march=x86-64 -asm-verbose=false -enable-unsafe-fp-math -enable-no-nans-fp-math | FileCheck -check-prefix=UNSAFE %s +; RUN: llc < %s -march=x86-64 -asm-verbose=false -enable-no-nans-fp-math | FileCheck -check-prefix=FINITE %s ; Some of these patterns can be matched as SSE min or max. Some of ; then can be matched provided that the operands are swapped. From evan.cheng at apple.com Thu Jul 15 17:08:04 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 15 Jul 2010 22:08:04 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r108466 - /llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Message-ID: <20100715220804.5CF952A6C12C@llvm.org> Author: evancheng Date: Thu Jul 15 17:08:04 2010 New Revision: 108466 URL: http://llvm.org/viewvc/llvm-project?rev=108466&view=rev Log: -ffinite-math-only is now equal to "--enable-no-nans-fp-math --enable-no-infs-fp-math". Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=108466&r1=108465&r2=108466&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Thu Jul 15 17:08:04 2010 @@ -411,8 +411,10 @@ Args.push_back("--time-passes"); if (fast_math_flags_set_p()) Args.push_back("--enable-unsafe-fp-math"); - if (flag_finite_math_only) - Args.push_back("--enable-finite-only-fp-math"); + if (flag_finite_math_only) { + Args.push_back("--enable-no-nans-fp-math"); + Args.push_back("--enable-no-infs-fp-math"); + } if (!flag_omit_frame_pointer) Args.push_back("--disable-fp-elim"); if (!flag_zero_initialized_in_bss) From dimitry at andric.com Thu Jul 15 18:05:57 2010 From: dimitry at andric.com (Dimitry Andric) Date: Fri, 16 Jul 2010 01:05:57 +0200 Subject: [llvm-commits] Windows compilation warnings In-Reply-To: References: Message-ID: <4C3F9455.5010106@andric.com> On 2010-07-15 20:45, Villmow, Micah wrote: > There are a bunch of windows warnings, here is a patch that fixes some of them. I assume these are warning fixes for the x64 build on Windows? Because the Win32 ToT build just has some warnings about enum values being truncated, and a few switch statements that only have a default case. If these fixes are indeed for the Windows x64 build, I would propose not to simply "cast away" some of those warnings, as they might hide real issues. There are *lot* of silent 64-to-32 bit truncations in the codebase, for example where lengths (usually a size_t) are stuffed into plain int or unsigned, and ideally these should all be checked to verify there is no problem with that truncation. That said, I will apply your patch to an x64 build, and see how many of the (very many :) warnings go away. From evan.cheng at apple.com Thu Jul 15 18:10:17 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 15 Jul 2010 23:10:17 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r108472 - in /llvm-gcc-4.2/trunk/gcc: c-cppbuiltin.c common.opt doc/llvm-gcc.1 flags.h llvm-backend.cpp opts.c tree-eh.c Message-ID: <20100715231017.490602A6C12C@llvm.org> Author: evancheng Date: Thu Jul 15 18:10:17 2010 New Revision: 108472 URL: http://llvm.org/viewvc/llvm-project?rev=108472&view=rev Log: Added -fno-honor-nans (-fhonor-nans is the default) and -fno-honor-infinites (-fhonor-inifinites is the default). These allow optimizations for fp math to assume the arguments and results are not NaNs / +-Infs respectively. -ffinite-math-only implies -fno-honor-nans and -fno-honor-infinites. Modified: llvm-gcc-4.2/trunk/gcc/c-cppbuiltin.c llvm-gcc-4.2/trunk/gcc/common.opt llvm-gcc-4.2/trunk/gcc/doc/llvm-gcc.1 llvm-gcc-4.2/trunk/gcc/flags.h llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp llvm-gcc-4.2/trunk/gcc/opts.c llvm-gcc-4.2/trunk/gcc/tree-eh.c Modified: llvm-gcc-4.2/trunk/gcc/c-cppbuiltin.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/c-cppbuiltin.c?rev=108472&r1=108471&r2=108472&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/c-cppbuiltin.c (original) +++ llvm-gcc-4.2/trunk/gcc/c-cppbuiltin.c Thu Jul 15 18:10:17 2010 @@ -598,7 +598,8 @@ cpp_define (pfile, "__NO_INLINE__"); if (flag_signaling_nans) cpp_define (pfile, "__SUPPORT_SNAN__"); - if (flag_finite_math_only) + /* LLVM LOCAL */ + if (!flag_honor_infinites & !flag_honor_nans) cpp_define (pfile, "__FINITE_MATH_ONLY__=1"); else cpp_define (pfile, "__FINITE_MATH_ONLY__=0"); Modified: llvm-gcc-4.2/trunk/gcc/common.opt URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/common.opt?rev=108472&r1=108471&r2=108472&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/common.opt (original) +++ llvm-gcc-4.2/trunk/gcc/common.opt Thu Jul 15 18:10:17 2010 @@ -537,6 +537,16 @@ Assume no NaNs or infinities are generated ; APPLE LOCAL end optimization pragmas 3124235/3420242 +; LLVM LOCAL begin +fhonor-nans +Common Report Var(flag_honor_nans) Init(1) PerFunc +Assume no NaNs are generated + +fhonor-infinites +Common Report Var(flag_honor_infinites) Init(1) PerFunc +Assume no infinites are generated +; LLVM LOCAL end + ffixed- Common Joined RejectNegative -ffixed- Mark as being unavailable to the compiler Modified: llvm-gcc-4.2/trunk/gcc/doc/llvm-gcc.1 URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/doc/llvm-gcc.1?rev=108472&r1=108471&r2=108472&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/doc/llvm-gcc.1 (original) +++ llvm-gcc-4.2/trunk/gcc/doc/llvm-gcc.1 Thu Jul 15 18:10:17 2010 @@ -25,6 +25,14 @@ .Bl -tag -width -indent .It Fl flto Enables Link Time Optimization. Link Time Optimization is performed by ld(1) transparently using the LLVM optimizer. The object file generated contains intermediate LLVM bitcode instead of Mach-O objects. +.It Fl fno-honor-nans +Allow optimizations for floating-point arithmetic that assume that arguments and results are not NaNs. + +The default is -fhonor-nans. +.It Fl fno-honor-infinites +Allow optimizations for floating-point arithmetic that assume that arguments and results are not +-Infs. + +The default is -fhonor-infinites. .It Fl O4 Enables Link Time Optimization in addition to all optimizations enabled at -O3. .It Fl O Modified: llvm-gcc-4.2/trunk/gcc/flags.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/flags.h?rev=108472&r1=108471&r2=108472&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/flags.h (original) +++ llvm-gcc-4.2/trunk/gcc/flags.h Thu Jul 15 18:10:17 2010 @@ -284,16 +284,18 @@ x * 0 into 0, are not correct for NaN operands, and are normally disabled for modes with NaNs. The user can ask for them to be done anyway using the -funsafe-math-optimizations switch. */ +/* LLVM LOCAL */ #define HONOR_NANS(MODE) \ - (MODE_HAS_NANS (MODE) && !flag_finite_math_only) + (MODE_HAS_NANS (MODE) && flag_honor_nans) /* Like HONOR_NANs, but true if we honor signaling NaNs (or sNaNs). */ #define HONOR_SNANS(MODE) (flag_signaling_nans && HONOR_NANS (MODE)) /* As for HONOR_NANS, but true if the mode can represent infinity and the treatment of infinite values is important. */ +/* LLVM LOCAL */ #define HONOR_INFINITIES(MODE) \ - (MODE_HAS_INFINITIES (MODE) && !flag_finite_math_only) + (MODE_HAS_INFINITIES (MODE) && flag_honor_infinites) /* Like HONOR_NANS, but true if the given mode distinguishes between positive and negative zero, and the sign of zero is important. */ Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=108472&r1=108471&r2=108472&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Thu Jul 15 18:10:17 2010 @@ -411,10 +411,10 @@ Args.push_back("--time-passes"); if (fast_math_flags_set_p()) Args.push_back("--enable-unsafe-fp-math"); - if (flag_finite_math_only) { - Args.push_back("--enable-no-nans-fp-math"); + if (!flag_honor_infinites) Args.push_back("--enable-no-infs-fp-math"); - } + if (!flag_honor_nans) + Args.push_back("--enable-no-nans-fp-math"); if (!flag_omit_frame_pointer) Args.push_back("--disable-fp-elim"); if (!flag_zero_initialized_in_bss) Modified: llvm-gcc-4.2/trunk/gcc/opts.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/opts.c?rev=108472&r1=108471&r2=108472&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/opts.c (original) +++ llvm-gcc-4.2/trunk/gcc/opts.c Thu Jul 15 18:10:17 2010 @@ -1005,6 +1005,13 @@ set_fast_math_flags (value); break; + /* LLVM LOCAL begin */ + case OPT_ffinite_math_only: + flag_honor_infinites = !value; + flag_honor_nans = !value; + break; + /* LLVM LOCAL end */ + case OPT_ffixed_: fix_register (arg, 1, 1); break; @@ -1297,7 +1304,10 @@ { flag_trapping_math = !set; flag_unsafe_math_optimizations = set; - flag_finite_math_only = set; + /* LLVM LOCAL begin */ + flag_honor_infinites = !set; + flag_honor_nans = !set; + /* LLVM LOCAL end */ flag_errno_math = !set; if (set) { @@ -1313,7 +1323,10 @@ { return (!flag_trapping_math && flag_unsafe_math_optimizations - && flag_finite_math_only + /* LLVM LOCAL begin */ + && !flag_honor_infinites + && !flag_honor_nans + /* LLVM LOCAL end */ && !flag_errno_math); } Modified: llvm-gcc-4.2/trunk/gcc/tree-eh.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/tree-eh.c?rev=108472&r1=108471&r2=108472&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/tree-eh.c (original) +++ llvm-gcc-4.2/trunk/gcc/tree-eh.c Thu Jul 15 18:10:17 2010 @@ -1872,7 +1872,8 @@ fp_operation = FLOAT_TYPE_P (t); if (fp_operation) { - honor_nans = flag_trapping_math && !flag_finite_math_only; + /* LLVM LOCAL */ + honor_nans = flag_trapping_math && flag_honor_nans; honor_snans = flag_signaling_nans != 0; } else if (INTEGRAL_TYPE_P (t) && TYPE_OVERFLOW_TRAPS (t)) From Micah.Villmow at amd.com Thu Jul 15 18:11:26 2010 From: Micah.Villmow at amd.com (Villmow, Micah) Date: Thu, 15 Jul 2010 18:11:26 -0500 Subject: [llvm-commits] Windows compilation warnings In-Reply-To: <4C3F9455.5010106@andric.com> References: <4C3F9455.5010106@andric.com> Message-ID: Dimitry, might want to hold off a little bit. I can provide another patch in an hour or so that should fix ALL of the x64 build warnings. Most of them I'm dealing with by casting them away for now. When I get more time I'll go through and fix the silent 64-to-32 bit truncations. In many of the places, I don't see why there is a need for 64bit integers to be used where either size_t or uint32_t should be used instead. Micah -----Original Message----- From: Dimitry Andric [mailto:dimitry at andric.com] Sent: Thursday, July 15, 2010 4:06 PM To: Villmow, Micah Cc: llvm-commits Subject: Re: [llvm-commits] Windows compilation warnings On 2010-07-15 20:45, Villmow, Micah wrote: > There are a bunch of windows warnings, here is a patch that fixes some of them. I assume these are warning fixes for the x64 build on Windows? Because the Win32 ToT build just has some warnings about enum values being truncated, and a few switch statements that only have a default case. If these fixes are indeed for the Windows x64 build, I would propose not to simply "cast away" some of those warnings, as they might hide real issues. There are *lot* of silent 64-to-32 bit truncations in the codebase, for example where lengths (usually a size_t) are stuffed into plain int or unsigned, and ideally these should all be checked to verify there is no problem with that truncation. That said, I will apply your patch to an x64 build, and see how many of the (very many :) warnings go away. From isanbard at gmail.com Thu Jul 15 18:32:40 2010 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 15 Jul 2010 23:32:40 -0000 Subject: [llvm-commits] [llvm] r108473 - in /llvm/trunk: lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll test/CodeGen/X86/2008-01-25-EmptyFunction.ll Message-ID: <20100715233240.E42972A6C12C@llvm.org> Author: void Date: Thu Jul 15 18:32:40 2010 New Revision: 108473 URL: http://llvm.org/viewvc/llvm-project?rev=108473&view=rev Log: Handle code gen for the unreachable instruction if it's the only instruction in the function. We'll just turn it into a "trap" instruction instead. The problem with not handling this is that it might generate a prologue without the equivalent epilogue to go with it: $ cat t.ll define void @foo() { entry: unreachable } $ llc -o - t.ll -relocation-model=pic -disable-fp-elim -unwind-tables .section __TEXT,__text,regular,pure_instructions .globl _foo .align 4, 0x90 _foo: ## @foo Leh_func_begin0: ## BB#0: ## %entry pushq %rbp Ltmp0: movq %rsp, %rbp Ltmp1: Leh_func_end0: ... The unwind tables then have bad data in them causing all sorts of problems. Fixes . Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h llvm/trunk/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll llvm/trunk/test/CodeGen/X86/2008-01-25-EmptyFunction.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=108473&r1=108472&r2=108473&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Thu Jul 15 18:32:40 2010 @@ -796,6 +796,7 @@ #define HANDLE_INST(NUM, OPCODE, CLASS) \ case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break; #include "llvm/Instruction.def" +#undef HANDLE_INST } // Assign the ordering to the freshly created DAG nodes. @@ -2194,6 +2195,19 @@ getValue(I.getAddress()))); } +void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) { + // If the function consists of a single "unreachable" instruction, emit a + // "trap". This prevents the back-ends from generating empty functions or + // functions which have a prologue, but no epilogue. + const BasicBlock *BB = I.getParent(); + const Function *F = BB->getParent(); + + if (F->size() == 1 && BB->size() == 1 && + isa(BB->getTerminator())) + DAG.setRoot(DAG.getNode(ISD::TRAP, getCurDebugLoc(), + MVT::Other, getRoot())); +} + void SelectionDAGBuilder::visitFSub(const User &I) { // -0.0 - X --> fneg const Type *Ty = I.getType(); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h?rev=108473&r1=108472&r2=108473&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h Thu Jul 15 18:32:40 2010 @@ -385,7 +385,7 @@ void visitBr(const BranchInst &I); void visitSwitch(const SwitchInst &I); void visitIndirectBr(const IndirectBrInst &I); - void visitUnreachable(const UnreachableInst &I) { /* noop */ } + void visitUnreachable(const UnreachableInst &I); // Helpers for visitSwitch bool handleSmallSwitchRange(CaseRec& CR, Modified: llvm/trunk/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll?rev=108473&r1=108472&r2=108473&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll (original) +++ llvm/trunk/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll Thu Jul 15 18:32:40 2010 @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ppc32 | grep nop +; RUN: llc < %s -march=ppc32 | grep trap target triple = "powerpc-apple-darwin8" Modified: llvm/trunk/test/CodeGen/X86/2008-01-25-EmptyFunction.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-01-25-EmptyFunction.ll?rev=108473&r1=108472&r2=108473&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2008-01-25-EmptyFunction.ll (original) +++ llvm/trunk/test/CodeGen/X86/2008-01-25-EmptyFunction.ll Thu Jul 15 18:32:40 2010 @@ -1,8 +1,17 @@ -; RUN: llc < %s -march=x86 | grep nop +; RUN: llc < %s -march=x86 | FileCheck -check-prefix=NO-FP %s +; RUN: llc < %s -march=x86 -disable-fp-elim | FileCheck -check-prefix=FP %s target triple = "i686-apple-darwin8" +define void @func1() noreturn nounwind { +entry: +; NO-FP: ud2 + unreachable +} -define void @bork() noreturn nounwind { +define void @func2() noreturn nounwind { entry: +; FP: pushl %ebp +; FP: movl %esp, %ebp +; FP: ud2 unreachable } From gohman at apple.com Thu Jul 15 18:38:13 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 15 Jul 2010 23:38:13 -0000 Subject: [llvm-commits] [llvm] r108475 - in /llvm/trunk: lib/Analysis/ScalarEvolutionExpander.cpp test/Transforms/IndVarSimplify/uglygep.ll Message-ID: <20100715233813.9ED8F2A6C12C@llvm.org> Author: djg Date: Thu Jul 15 18:38:13 2010 New Revision: 108475 URL: http://llvm.org/viewvc/llvm-project?rev=108475&view=rev Log: Fix the order that SCEVExpander considers add operands in so that it doesn't miss an opportunity to form a GEP, regardless of the relative loop depths of the operands. This fixes rdar://8197217. Added: llvm/trunk/test/Transforms/IndVarSimplify/uglygep.ll Modified: llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp Modified: llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp?rev=108475&r1=108474&r2=108475&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp Thu Jul 15 18:38:13 2010 @@ -647,6 +647,11 @@ bool operator()(std::pair LHS, std::pair RHS) const { + // Keep pointer operands sorted at the end. + if (LHS.second->getType()->isPointerTy() != + RHS.second->getType()->isPointerTy()) + return LHS.second->getType()->isPointerTy(); + // Compare loops with PickMostRelevantLoop. if (LHS.first != RHS.first) return PickMostRelevantLoop(LHS.first, RHS.first, DT) != LHS.first; @@ -699,8 +704,15 @@ // The running sum expression is a pointer. Try to form a getelementptr // at this level with that as the base. SmallVector NewOps; - for (; I != E && I->first == CurLoop; ++I) - NewOps.push_back(I->second); + for (; I != E && I->first == CurLoop; ++I) { + // If the operand is SCEVUnknown and not instructions, peek through + // it, to enable more of it to be folded into the GEP. + const SCEV *X = I->second; + if (const SCEVUnknown *U = dyn_cast(X)) + if (!isa(U->getValue())) + X = SE.getSCEV(U->getValue()); + NewOps.push_back(X); + } Sum = expandAddToGEP(NewOps.begin(), NewOps.end(), PTy, Ty, Sum); } else if (const PointerType *PTy = dyn_cast(Op->getType())) { // The running sum is an integer, and there's a pointer at this level. Added: llvm/trunk/test/Transforms/IndVarSimplify/uglygep.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/uglygep.ll?rev=108475&view=auto ============================================================================== --- llvm/trunk/test/Transforms/IndVarSimplify/uglygep.ll (added) +++ llvm/trunk/test/Transforms/IndVarSimplify/uglygep.ll Thu Jul 15 18:38:13 2010 @@ -0,0 +1,40 @@ +; RUN: opt -indvars -S | not grep uglygep +; rdar://8197217 + +; Indvars should be able to emit a clean GEP here, not an uglygep. + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin11.0" + + at numf2s = external global i32 ; [#uses=1] + at numf1s = external global i32 ; [#uses=1] + at tds = external global double** ; [#uses=1] + +define void @init_td(i32 %tmp7) nounwind { +entry: + br label %bb4 + +bb4: ; preds = %bb3, %entry + %i.0 = phi i32 [ 0, %entry ], [ %tmp9, %bb3 ] ; [#uses=3] + br label %bb + +bb: ; preds = %bb4 + br label %bb2 + +bb2: ; preds = %bb1, %bb + %j.0 = phi i32 [ 0, %bb ], [ %tmp6, %bb1 ] ; [#uses=3] + %tmp8 = icmp slt i32 %j.0, %tmp7 ; [#uses=1] + br i1 %tmp8, label %bb1, label %bb3 + +bb1: ; preds = %bb2 + %tmp = load double*** @tds, align 8 ; [#uses=1] + %tmp1 = sext i32 %i.0 to i64 ; [#uses=1] + %tmp2 = getelementptr inbounds double** %tmp, i64 %tmp1 ; [#uses=1] + %tmp3 = load double** %tmp2, align 1 ; [#uses=1] + %tmp6 = add nsw i32 %j.0, 1 ; [#uses=1] + br label %bb2 + +bb3: ; preds = %bb2 + %tmp9 = add nsw i32 %i.0, 1 ; [#uses=1] + br label %bb4 +} From isanbard at gmail.com Thu Jul 15 18:42:21 2010 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 15 Jul 2010 23:42:21 -0000 Subject: [llvm-commits] [llvm] r108478 - in /llvm/trunk: lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll test/CodeGen/X86/2008-01-25-EmptyFunction.ll Message-ID: <20100715234222.16C3F2A6C12C@llvm.org> Author: void Date: Thu Jul 15 18:42:21 2010 New Revision: 108478 URL: http://llvm.org/viewvc/llvm-project?rev=108478&view=rev Log: Revert. This isn't the correct way to go. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h llvm/trunk/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll llvm/trunk/test/CodeGen/X86/2008-01-25-EmptyFunction.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=108478&r1=108477&r2=108478&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Thu Jul 15 18:42:21 2010 @@ -796,7 +796,6 @@ #define HANDLE_INST(NUM, OPCODE, CLASS) \ case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break; #include "llvm/Instruction.def" -#undef HANDLE_INST } // Assign the ordering to the freshly created DAG nodes. @@ -2195,19 +2194,6 @@ getValue(I.getAddress()))); } -void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) { - // If the function consists of a single "unreachable" instruction, emit a - // "trap". This prevents the back-ends from generating empty functions or - // functions which have a prologue, but no epilogue. - const BasicBlock *BB = I.getParent(); - const Function *F = BB->getParent(); - - if (F->size() == 1 && BB->size() == 1 && - isa(BB->getTerminator())) - DAG.setRoot(DAG.getNode(ISD::TRAP, getCurDebugLoc(), - MVT::Other, getRoot())); -} - void SelectionDAGBuilder::visitFSub(const User &I) { // -0.0 - X --> fneg const Type *Ty = I.getType(); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h?rev=108478&r1=108477&r2=108478&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h Thu Jul 15 18:42:21 2010 @@ -385,7 +385,7 @@ void visitBr(const BranchInst &I); void visitSwitch(const SwitchInst &I); void visitIndirectBr(const IndirectBrInst &I); - void visitUnreachable(const UnreachableInst &I); + void visitUnreachable(const UnreachableInst &I) { /* noop */ } // Helpers for visitSwitch bool handleSmallSwitchRange(CaseRec& CR, Modified: llvm/trunk/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll?rev=108478&r1=108477&r2=108478&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll (original) +++ llvm/trunk/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll Thu Jul 15 18:42:21 2010 @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ppc32 | grep trap +; RUN: llc < %s -march=ppc32 | grep nop target triple = "powerpc-apple-darwin8" Modified: llvm/trunk/test/CodeGen/X86/2008-01-25-EmptyFunction.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-01-25-EmptyFunction.ll?rev=108478&r1=108477&r2=108478&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2008-01-25-EmptyFunction.ll (original) +++ llvm/trunk/test/CodeGen/X86/2008-01-25-EmptyFunction.ll Thu Jul 15 18:42:21 2010 @@ -1,17 +1,8 @@ -; RUN: llc < %s -march=x86 | FileCheck -check-prefix=NO-FP %s -; RUN: llc < %s -march=x86 -disable-fp-elim | FileCheck -check-prefix=FP %s +; RUN: llc < %s -march=x86 | grep nop target triple = "i686-apple-darwin8" -define void @func1() noreturn nounwind { -entry: -; NO-FP: ud2 - unreachable -} -define void @func2() noreturn nounwind { +define void @bork() noreturn nounwind { entry: -; FP: pushl %ebp -; FP: movl %esp, %ebp -; FP: ud2 unreachable } From dalej at apple.com Thu Jul 15 19:02:09 2010 From: dalej at apple.com (Dale Johannesen) Date: Fri, 16 Jul 2010 00:02:09 -0000 Subject: [llvm-commits] [llvm] r108484 - in /llvm/trunk: lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h test/CodeGen/Thumb/2010-07-15-debugOrdering.ll Message-ID: <20100716000209.15D192A6C12C@llvm.org> Author: johannes Date: Thu Jul 15 19:02:08 2010 New Revision: 108484 URL: http://llvm.org/viewvc/llvm-project?rev=108484&view=rev Log: The SelectionDAGBuilder's handling of debug info, on rare occasions, caused code to be generated in a different order. All cases I've seen involved float softening in the type legalizer, and this could be perhaps be fixed there, but it's better not to generate things differently in the first place. 7797940 (6/29/2010..7/15/2010). Added: llvm/trunk/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=108484&r1=108483&r2=108484&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Thu Jul 15 19:02:08 2010 @@ -701,6 +701,7 @@ UnusedArgNodeMap.clear(); PendingLoads.clear(); PendingExports.clear(); + DanglingDebugInfoMap.clear(); CurDebugLoc = DebugLoc(); HasTailCall = false; } @@ -805,6 +806,33 @@ } } +// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V, +// generate the debug data structures now that we've seen its definition. +void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V, + SDValue Val) { + DanglingDebugInfo &DDI = DanglingDebugInfoMap[V]; + if (DDI.getDI()) { + const DbgValueInst *DI = DDI.getDI(); + DebugLoc dl = DDI.getdl(); + unsigned DbgSDNodeOrder = DDI.getSDNodeOrder(); + MDNode *Variable = DI->getVariable(); + uint64_t Offset = DI->getOffset(); + SDDbgValue *SDV; + if (Val.getNode()) { + if (!EmitFuncArgumentDbgValue(*DI, V, Variable, Offset, Val)) { + SDV = DAG.getDbgValue(Variable, Val.getNode(), + Val.getResNo(), Offset, dl, DbgSDNodeOrder); + DAG.AddDbgValue(SDV, Val.getNode(), false); + } + } else { + SDV = DAG.getDbgValue(Variable, UndefValue::get(V->getType()), + Offset, dl, SDNodeOrder); + DAG.AddDbgValue(SDV, 0, false); + } + DanglingDebugInfoMap[V] = DanglingDebugInfo(); + } +} + // getValue - Return an SDValue for the given Value. SDValue SelectionDAGBuilder::getValue(const Value *V) { // If we already have an SDValue for this value, use it. It's important @@ -826,6 +854,7 @@ // Otherwise create a new SDValue and remember it. SDValue Val = getValueImpl(V); NodeMap[V] = Val; + resolveDanglingDebugInfo(V, Val); return Val; } @@ -839,10 +868,11 @@ // Otherwise create a new SDValue and remember it. SDValue Val = getValueImpl(V); NodeMap[V] = Val; + resolveDanglingDebugInfo(V, Val); return Val; } -/// getValueImpl - Helper function for getValue and getMaterializedValue. +/// getValueImpl - Helper function for getValue and getNonRegisterValue. /// Create an SDValue for the given value. SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { if (const Constant *C = dyn_cast(V)) { @@ -4049,7 +4079,8 @@ DAG.AddDbgValue(SDV, 0, false); } else { bool createUndef = false; - // FIXME : Why not use getValue() directly ? + // Do not use getValue() in here; we don't want to generate code at + // this point if it hasn't been done yet. SDValue N = NodeMap[V]; if (!N.getNode() && isa(V)) // Check unused arguments map. @@ -4060,16 +4091,11 @@ N.getResNo(), Offset, dl, SDNodeOrder); DAG.AddDbgValue(SDV, N.getNode(), false); } - } else if (isa(V) && !V->use_empty()) { - SDValue N = getValue(V); - if (N.getNode()) { - if (!EmitFuncArgumentDbgValue(DI, V, Variable, Offset, N)) { - SDV = DAG.getDbgValue(Variable, N.getNode(), - N.getResNo(), Offset, dl, SDNodeOrder); - DAG.AddDbgValue(SDV, N.getNode(), false); - } - } else - createUndef = true; + } else if (isa(V) && !V->use_empty() ) { + // Do not call getValue(V) yet, as we don't want to generate code. + // Remember it for later. + DanglingDebugInfo DDI(&DI, dl, SDNodeOrder); + DanglingDebugInfoMap[V] = DDI; } else createUndef = true; if (createUndef) { Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h?rev=108484&r1=108483&r2=108484&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h Thu Jul 15 19:02:08 2010 @@ -64,6 +64,7 @@ class PtrToIntInst; class ReturnInst; class SDISelAsmOperandInfo; +class SDDbgValue; class SExtInst; class SelectInst; class ShuffleVectorInst; @@ -93,6 +94,24 @@ /// to preserve debug information for incoming arguments. DenseMap UnusedArgNodeMap; + /// DanglingDebugInfo - Helper type for DanglingDebugInfoMap. + class DanglingDebugInfo { + const DbgValueInst* DI; + DebugLoc dl; + unsigned SDNodeOrder; + public: + DanglingDebugInfo() : DI(0), dl(DebugLoc()), SDNodeOrder(0) { } + DanglingDebugInfo(const DbgValueInst *di, DebugLoc DL, unsigned SDNO) : + DI(di), dl(DL), SDNodeOrder(SDNO) { } + const DbgValueInst* getDI() { return DI; } + DebugLoc getdl() { return dl; } + unsigned getSDNodeOrder() { return SDNodeOrder; } + }; + + /// DanglingDebugInfoMap - Keeps track of dbg_values for which we have not + /// yet seen the referent. We defer handling these until we do see it. + DenseMap DanglingDebugInfoMap; + public: /// PendingLoads - Loads are not emitted to the program immediately. We bunch /// them up and then emit token factor nodes when possible. This allows us to @@ -345,6 +364,9 @@ void visit(unsigned Opcode, const User &I); + // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V, + // generate the debug data structures now that we've seen its definition. + void resolveDanglingDebugInfo(const Value *V, SDValue Val); SDValue getValue(const Value *V); SDValue getNonRegisterValue(const Value *V); SDValue getValueImpl(const Value *V); Added: llvm/trunk/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll?rev=108484&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll (added) +++ llvm/trunk/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll Thu Jul 15 19:02:08 2010 @@ -0,0 +1,147 @@ +; RUN: llc -mtriple=thumbv6-apple-darwin10 %s -o - | FileCheck %s +; RUN: opt -strip-debug < %s -o - | llc -mtriple=thumbv6-apple-darwin10 %s -o - | FileCheck %s +; Stripping out debug info formerly caused the last two multiplies to be emitted in +; the other order. 7797940 (part of it dated 6/29/2010..7/15/2010). + +%0 = type { [3 x double] } + + at llvm.used = appending global [1 x i8*] [i8* bitcast (void (%0*, i32, i32)* @_Z19getClosestDiagonal3ii to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] + +define void @_Z19getClosestDiagonal3ii(%0* noalias sret, i32, i32) nounwind { +; CHECK: blx ___muldf3 +; CHECK: blx ___muldf3 +; CHECK: beq LBB0_8 +; CHECK: blx ___muldf3 +;

""" % (compare_to.machine.name, compare_to.machine.number) - if existing_failures: - num_existing_failures = sum(map(len, existing_failures.values())) - print >>report, 'Total Existing Failures:', num_existing_failures - print >>report - - print >>html_report, """\ -

Total Existing Failures: %d

""" % num_existing_failures - # Generate the summary of the changes. items_info = (('New Failures', new_failures, False), ('New Passes', new_passes, False), ('Performance Regressions', perf_regressions, True), ('Performance Improvements', perf_improvements, True), ('Removed Tests', removed_tests, False), - ('Added Tests', added_tests, False)) + ('Added Tests', added_tests, False), + ('Existing Failures', existing_failures, False), + ('Unchanged Tests', unchanged_tests, False)) total_changes = sum([sum(map(len, items.values())) for _,items,_ in items_info]) graphs = [] - if total_changes: - print >>report, """===============""" - print >>report, """Changes Summary""" - print >>report, """===============""" - print >>report - print >>html_report, """ + print >>report, """===============""" + print >>report, """Tests Summary""" + print >>report, """===============""" + print >>report + print >>html_report, """
-

Changes Summary

+

Tests Summary

-""" - for name,items,_ in items_info: - if items: - num_items = sum(map(len, items.values())) - print >>report, '%s: %d' % (name, num_items) - print >>html_report, """ -""" % (name, num_items) - print >>report - print >>html_report, """ -
Change Kind#
%s%d
+Status Group# """ + for name,items,_ in items_info: + if items: + num_items = sum(map(len, items.values())) + print >>report, '%s: %d' % (name, num_items) + print >>html_report, """ +%s%d""" % (name, num_items) + print >>report, """Total Tests: %d""" % num_total_tests + print >>report + print >>html_report, """ + + Total Tests%d + + +""" % num_total_tests + if total_changes: print >>report, """==============""" print >>report, """Changes Detail""" print >>report, """==============""" From daniel at zuster.org Fri Jul 16 01:07:23 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Fri, 16 Jul 2010 06:07:23 -0000 Subject: [llvm-commits] [zorg] r108514 - /zorg/trunk/lnt/lnt/db/runinfo.py Message-ID: <20100716060723.6B07D2A6C12C@llvm.org> Author: ddunbar Date: Fri Jul 16 01:07:23 2010 New Revision: 108514 URL: http://llvm.org/viewvc/llvm-project?rev=108514&view=rev Log: LNT/simple: Don't report XFAILs as FAIL, and assume .status style reporting when no status indicator is present. Modified: zorg/trunk/lnt/lnt/db/runinfo.py Modified: zorg/trunk/lnt/lnt/db/runinfo.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/db/runinfo.py?rev=108514&r1=108513&r2=108514&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/db/runinfo.py (original) +++ zorg/trunk/lnt/lnt/db/runinfo.py Fri Jul 16 01:07:23 2010 @@ -1,6 +1,7 @@ from lnt.util import stats from lnt.viewer import Util from lnt.viewer.PerfDB import Sample +from lnt.testing import PASS, FAIL, XFAIL REGRESSED = 'REGRESSED' IMPROVED = 'IMPROVED' @@ -129,13 +130,15 @@ # previous runs. run_failed = prev_failed = False if not status_test_id: - run_failed = not run_values - prev_failed = not prev_values + # Assume status kind is '.status' if missing, in which case no + # values indicates success. + run_failed = bool(run_values) + prev_failed = bool(prev_values) else: run_status = self.sample_map.get((run.id,status_test_id)) prev_status = self.sample_map.get((compare_id,status_test_id)) - # FIXME: Support XFAILs. + # FIXME: Support XFAILs better. # # FIXME: What to do about the multiple entries here. We could start # by just treating non-matching samples as errors. @@ -143,8 +146,8 @@ run_failed = not run_status or not run_status[0] prev_failed = not prev_status or not prev_status[0] else: - run_failed = run_status and run_status[0] != 0 - prev_failed = prev_status and prev_status[0] != 0 + run_failed = run_status and run_status[0] == FAIL + prev_failed = prev_status and prev_status[0] == FAIL # Get the current and previous values. if run_values: From echristo at apple.com Fri Jul 16 01:13:24 2010 From: echristo at apple.com (Eric Christopher) Date: Fri, 16 Jul 2010 06:13:24 -0000 Subject: [llvm-commits] [llvm] r108516 - /llvm/trunk/Makefile.rules Message-ID: <20100716061324.4066E2A6C12C@llvm.org> Author: echristo Date: Fri Jul 16 01:13:24 2010 New Revision: 108516 URL: http://llvm.org/viewvc/llvm-project?rev=108516&view=rev Log: Remove unnecessary conditional. Modified: llvm/trunk/Makefile.rules Modified: llvm/trunk/Makefile.rules URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=108516&r1=108515&r2=108516&view=diff ============================================================================== --- llvm/trunk/Makefile.rules (original) +++ llvm/trunk/Makefile.rules Fri Jul 16 01:13:24 2010 @@ -622,7 +622,6 @@ # Adjust linker flags for building an executable ifneq ($(HOST_OS),Darwin) -ifneq ($(DARWIN_MAJVERS),4) ifdef TOOLNAME LD.Flags += $(RPATH) -Wl,'$$ORIGIN/../lib' ifdef EXAMPLE_TOOL @@ -631,7 +630,6 @@ LD.Flags += $(RPATH) -Wl,$(ToolDir) $(RDYNAMIC) endif endif -endif else ifneq ($(DARWIN_MAJVERS),4) LD.Flags += $(RPATH) -Wl, at executable_path/../lib From echristo at apple.com Fri Jul 16 01:14:41 2010 From: echristo at apple.com (Eric Christopher) Date: Thu, 15 Jul 2010 23:14:41 -0700 Subject: [llvm-commits] [llvm] r108416 - /llvm/trunk/Makefile.rules In-Reply-To: <68DEA7C2-5CB3-4D9E-869D-5803213E0279@apple.com> References: <20100715063657.3D8E02A6C12C@llvm.org> <68DEA7C2-5CB3-4D9E-869D-5803213E0279@apple.com> Message-ID: On Jul 15, 2010, at 1:21 AM, Eric Christopher wrote: > > On Jul 14, 2010, at 11:36 PM, Ted Kremenek wrote: > >> Author: kremenek >> Date: Thu Jul 15 01:36:57 2010 >> New Revision: 108416 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=108416&view=rev >> Log: >> Correctly set rpath on Mac OS X for executable tools. Note that I am not certain this is the best fix; the code immediately above looks confused, as it first checks to see if we are NOT on Darwin and then checks the Darwin version number. This fix allows c-index-test (in Clang) to run outside of running the regression test suite. I would appreciate if someone reviewed this. > > Yeah, line 625 can probably go away. I'll test that in the morning. Seems fine. I've removed the conditional and committed. Thanks Ted! -eric From nicholas at mxc.ca Fri Jul 16 01:31:13 2010 From: nicholas at mxc.ca (Nick Lewycky) Date: Fri, 16 Jul 2010 06:31:13 -0000 Subject: [llvm-commits] [llvm] r108517 - in /llvm/trunk: lib/Transforms/IPO/MergeFunctions.cpp test/Transforms/MergeFunc/vectors-and-arrays.ll Message-ID: <20100716063113.0E82C2A6C12C@llvm.org> Author: nicholas Date: Fri Jul 16 01:31:12 2010 New Revision: 108517 URL: http://llvm.org/viewvc/llvm-project?rev=108517&view=rev Log: Arrays and vectors with different numbers of elements are not equivalent. Added: llvm/trunk/test/Transforms/MergeFunc/vectors-and-arrays.ll Modified: llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp Modified: llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp?rev=108517&r1=108516&r2=108517&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp Fri Jul 16 01:31:12 2010 @@ -216,11 +216,17 @@ return true; } - case Type::ArrayTyID: + case Type::ArrayTyID: { + const ArrayType *ATy1 = cast(Ty1); + const ArrayType *ATy2 = cast(Ty2); + return ATy1->getNumElements() == ATy2->getNumElements() && + isEquivalentType(ATy1->getElementType(), ATy2->getElementType()); + } case Type::VectorTyID: { - const SequentialType *STy1 = cast(Ty1); - const SequentialType *STy2 = cast(Ty2); - return isEquivalentType(STy1->getElementType(), STy2->getElementType()); + const VectorType *VTy1 = cast(Ty1); + const VectorType *VTy2 = cast(Ty2); + return VTy1->getNumElements() == VTy2->getNumElements() && + isEquivalentType(VTy1->getElementType(), VTy2->getElementType()); } } } Added: llvm/trunk/test/Transforms/MergeFunc/vectors-and-arrays.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/MergeFunc/vectors-and-arrays.ll?rev=108517&view=auto ============================================================================== --- llvm/trunk/test/Transforms/MergeFunc/vectors-and-arrays.ll (added) +++ llvm/trunk/test/Transforms/MergeFunc/vectors-and-arrays.ll Fri Jul 16 01:31:12 2010 @@ -0,0 +1,18 @@ +; RUN: opt -mergefunc < %s -disable-output -stats | not grep merged +; This used to crash with an assert. + +define <2 x i8> @v1(<2 x i8> %x) { + ret <2 x i8> %x +} + +define <4 x i8> @v2(<4 x i8> %x) { + ret <4 x i8> %x +} + +define [2 x i8] @a1([2 x i8] %x) { + ret [2 x i8] %x +} + +define [4 x i8] @a2([4 x i8] %x) { + ret [4 x i8] %x +} From echristo at apple.com Fri Jul 16 01:33:36 2010 From: echristo at apple.com (Eric Christopher) Date: Fri, 16 Jul 2010 06:33:36 -0000 Subject: [llvm-commits] [llvm] r108518 - /llvm/trunk/projects/test-suite Message-ID: <20100716063336.E938E2A6C12C@llvm.org> Author: echristo Date: Fri Jul 16 01:33:36 2010 New Revision: 108518 URL: http://llvm.org/viewvc/llvm-project?rev=108518&view=rev Log: Remove bogus link. Removed: llvm/trunk/projects/test-suite Removed: llvm/trunk/projects/test-suite URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/projects/test-suite?rev=108517&view=auto ============================================================================== --- llvm/trunk/projects/test-suite (original) +++ llvm/trunk/projects/test-suite (removed) @@ -1 +0,0 @@ -link ../../test-suite \ No newline at end of file From nicholas at mxc.ca Fri Jul 16 01:35:01 2010 From: nicholas at mxc.ca (Nick Lewycky) Date: Thu, 15 Jul 2010 23:35:01 -0700 Subject: [llvm-commits] turn on function merging In-Reply-To: <4C3F20FB.9040609@free.fr> References: <4C396EC3.40709@mxc.ca> <4C3F20FB.9040609@free.fr> Message-ID: <4C3FFD95.3000409@mxc.ca> Thanks. That uncovered a very silly miscompile bug. Fixed in r108517. Duncan Sands wrote: > Hi Nick, I found the following problem by running mergefunc on the > dragonegg testsuite: > > $ opt -mergefunc merge.ll -disable-output > opt: /home/duncan/LLVM/llvm.top/llvm/lib/VMCore/Instructions.cpp:2662: > llvm::BitCastInst::BitCastInst(llvm::Value*, const llvm::Type*, const > llvm::Twine&, llvm::BasicBlock*): Assertion `castIsValid(getOpcode(), S, > Ty) && "Illegal BitCast"' failed. > > See attached file. > > Ciao, > > Duncan. > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From daniel at zuster.org Fri Jul 16 02:40:09 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Fri, 16 Jul 2010 00:40:09 -0700 Subject: [llvm-commits] [llvm] r108454 - /llvm/trunk/lib/Target/X86/X86InstrMMX.td In-Reply-To: <20100715201334.E12562A6C12C@llvm.org> References: <20100715201334.E12562A6C12C@llvm.org> Message-ID: On Thu, Jul 15, 2010 at 1:13 PM, Chris Lattner wrote: > Author: lattner > Date: Thu Jul 15 15:13:34 2010 > New Revision: 108454 > > URL: http://llvm.org/viewvc/llvm-project?rev=108454&view=rev > Log: > fix the encoding of MMX_MOVFR642Qrr, it starts with 0xF2 not 0xF3, > this fixes rdar://8192860. ?Unfortunately it can only be triggered > with llc because llvm-mc matches another (correctly encoded) version > of this, so no testcase. FWIW, I think llc with --show-mc-encoding can be used to make a reasonable test case. - Daniel > > Modified: > ? ?llvm/trunk/lib/Target/X86/X86InstrMMX.td > > Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrMMX.td?rev=108454&r1=108453&r2=108454&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/X86InstrMMX.td (original) > +++ llvm/trunk/lib/Target/X86/X86InstrMMX.td Thu Jul 15 15:13:34 2010 > @@ -164,7 +164,7 @@ > ?def MMX_MOVQ2FR64rr: SSDIi8<0xD6, MRMSrcReg, (outs FR64:$dst), (ins VR64:$src), > ? ? ? ? ? ? ? ? ? ? ? ? ? ?"movq2dq\t{$src, $dst|$dst, $src}", []>; > > -def MMX_MOVFR642Qrr: SSDIi8<0xD6, MRMSrcReg, (outs VR64:$dst), (ins FR64:$src), > +def MMX_MOVFR642Qrr: SDIi8<0xD6, MRMSrcReg, (outs VR64:$dst), (ins FR64:$src), > ? ? ? ? ? ? ? ? ? ? ? ? ? ?"movdq2q\t{$src, $dst|$dst, $src}", []>; > > ?def MMX_MOVNTQmr ?: MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src), > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From eli.friedman at gmail.com Fri Jul 16 02:48:07 2010 From: eli.friedman at gmail.com (Eli Friedman) Date: Fri, 16 Jul 2010 07:48:07 -0000 Subject: [llvm-commits] [llvm] r108519 - /llvm/trunk/include/llvm/Support/ELF.h Message-ID: <20100716074807.418D52A6C12D@llvm.org> Author: efriedma Date: Fri Jul 16 02:48:07 2010 New Revision: 108519 URL: http://llvm.org/viewvc/llvm-project?rev=108519&view=rev Log: A few more minor additions to ELF.h. Modified: llvm/trunk/include/llvm/Support/ELF.h Modified: llvm/trunk/include/llvm/Support/ELF.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ELF.h?rev=108519&r1=108518&r2=108519&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/ELF.h (original) +++ llvm/trunk/include/llvm/Support/ELF.h Fri Jul 16 02:48:07 2010 @@ -339,10 +339,19 @@ STT_FUNC = 2, // Symbol is executable code (function, etc.) STT_SECTION = 3, // Symbol refers to a section STT_FILE = 4, // Local, absolute symbol that refers to a file + STT_COMMON = 5, // An uninitialised common block + STT_TLS = 6, // Thread local data object STT_LOPROC = 13, // Lowest processor-specific symbol type STT_HIPROC = 15 // Highest processor-specific symbol type }; +enum { + STV_DEFAULT = 0, // Visibility is specified by binding type + STV_INTERNAL = 1, // Defined by processor supplements + STV_HIDDEN = 2, // Not visible to other components + STV_PROTECTED = 3 // Visible in other components but not preemptable +}; + // Relocation entry, without explicit addend. struct Elf32_Rel { Elf32_Addr r_offset; // Location (file byte offset, or program virtual addr) From eli.friedman at gmail.com Fri Jul 16 02:53:29 2010 From: eli.friedman at gmail.com (Eli Friedman) Date: Fri, 16 Jul 2010 07:53:29 -0000 Subject: [llvm-commits] [llvm] r108520 - in /llvm/trunk/lib: CodeGen/ELF.h CodeGen/ELFCodeEmitter.cpp CodeGen/ELFWriter.cpp CodeGen/ELFWriter.h ExecutionEngine/JIT/JITDebugRegisterer.cpp Message-ID: <20100716075329.E6DA82A6C12D@llvm.org> Author: efriedma Date: Fri Jul 16 02:53:29 2010 New Revision: 108520 URL: http://llvm.org/viewvc/llvm-project?rev=108520&view=rev Log: Get rid of a bunch of duplicated ELF enum values. Modified: llvm/trunk/lib/CodeGen/ELF.h llvm/trunk/lib/CodeGen/ELFCodeEmitter.cpp llvm/trunk/lib/CodeGen/ELFWriter.cpp llvm/trunk/lib/CodeGen/ELFWriter.h llvm/trunk/lib/ExecutionEngine/JIT/JITDebugRegisterer.cpp Modified: llvm/trunk/lib/CodeGen/ELF.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ELF.h?rev=108520&r1=108519&r2=108520&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ELF.h (original) +++ llvm/trunk/lib/CodeGen/ELF.h Fri Jul 16 02:53:29 2010 @@ -22,36 +22,12 @@ #include "llvm/CodeGen/BinaryObject.h" #include "llvm/CodeGen/MachineRelocation.h" +#include "llvm/Support/ELF.h" #include "llvm/System/DataTypes.h" namespace llvm { class GlobalValue; - // Identification Indexes - enum { - EI_MAG0 = 0, - EI_MAG1 = 1, - EI_MAG2 = 2, - EI_MAG3 = 3 - }; - - // File types - enum { - ET_NONE = 0, // No file type - ET_REL = 1, // Relocatable file - ET_EXEC = 2, // Executable file - ET_DYN = 3, // Shared object file - ET_CORE = 4, // Core file - ET_LOPROC = 0xff00, // Beginning of processor-specific codes - ET_HIPROC = 0xffff // Processor-specific - }; - - // Versioning - enum { - EV_NONE = 0, - EV_CURRENT = 1 - }; - /// ELFSym - This struct contains information about each symbol that is /// added to logical symbol table for the module. This is eventually /// turned into a real symbol table in the file. @@ -108,9 +84,9 @@ static ELFSym *getExtSym(const char *Ext) { ELFSym *Sym = new ELFSym(); Sym->Source.Ext = Ext; - Sym->setBind(STB_GLOBAL); - Sym->setType(STT_NOTYPE); - Sym->setVisibility(STV_DEFAULT); + Sym->setBind(ELF::STB_GLOBAL); + Sym->setType(ELF::STT_NOTYPE); + Sym->setVisibility(ELF::STV_DEFAULT); Sym->SourceType = isExtSym; return Sym; } @@ -118,9 +94,9 @@ // getSectionSym - Returns a elf symbol to represent an elf section static ELFSym *getSectionSym() { ELFSym *Sym = new ELFSym(); - Sym->setBind(STB_LOCAL); - Sym->setType(STT_SECTION); - Sym->setVisibility(STV_DEFAULT); + Sym->setBind(ELF::STB_LOCAL); + Sym->setType(ELF::STT_SECTION); + Sym->setVisibility(ELF::STV_DEFAULT); Sym->SourceType = isOther; return Sym; } @@ -128,9 +104,9 @@ // getFileSym - Returns a elf symbol to represent the module identifier static ELFSym *getFileSym() { ELFSym *Sym = new ELFSym(); - Sym->setBind(STB_LOCAL); - Sym->setType(STT_FILE); - Sym->setVisibility(STV_DEFAULT); + Sym->setBind(ELF::STB_LOCAL); + Sym->setType(ELF::STT_FILE); + Sym->setVisibility(ELF::STV_DEFAULT); Sym->SectionIdx = 0xfff1; // ELFSection::SHN_ABS; Sym->SourceType = isOther; return Sym; @@ -141,8 +117,8 @@ ELFSym *Sym = new ELFSym(); Sym->Source.GV = GV; Sym->setBind(Bind); - Sym->setType(STT_NOTYPE); - Sym->setVisibility(STV_DEFAULT); + Sym->setType(ELF::STT_NOTYPE); + Sym->setVisibility(ELF::STV_DEFAULT); Sym->SectionIdx = 0; //ELFSection::SHN_UNDEF; Sym->SourceType = isGV; return Sym; @@ -159,35 +135,14 @@ // Symbol index into the Symbol table unsigned SymTabIdx; - enum { - STB_LOCAL = 0, // Local sym, not visible outside obj file containing def - STB_GLOBAL = 1, // Global sym, visible to all object files being combined - STB_WEAK = 2 // Weak symbol, like global but lower-precedence - }; - - enum { - STT_NOTYPE = 0, // Symbol's type is not specified - STT_OBJECT = 1, // Symbol is a data object (variable, array, etc.) - STT_FUNC = 2, // Symbol is executable code (function, etc.) - STT_SECTION = 3, // Symbol refers to a section - STT_FILE = 4 // Local, absolute symbol that refers to a file - }; - - enum { - STV_DEFAULT = 0, // Visibility is specified by binding type - STV_INTERNAL = 1, // Defined by processor supplements - STV_HIDDEN = 2, // Not visible to other components - STV_PROTECTED = 3 // Visible in other components but not preemptable - }; - ELFSym() : SourceType(isOther), NameIdx(0), Value(0), - Size(0), Info(0), Other(STV_DEFAULT), SectionIdx(0), + Size(0), Info(0), Other(ELF::STV_DEFAULT), SectionIdx(0), SymTabIdx(0) {} unsigned getBind() const { return (Info >> 4) & 0xf; } unsigned getType() const { return Info & 0xf; } - bool isLocalBind() const { return getBind() == STB_LOCAL; } - bool isFileType() const { return getType() == STT_FILE; } + bool isLocalBind() const { return getBind() == ELF::STB_LOCAL; } + bool isFileType() const { return getType() == ELF::STT_FILE; } void setBind(unsigned X) { assert(X == (X & 0xF) && "Bind value out of range!"); @@ -222,51 +177,6 @@ unsigned Align; // sh_addralign - Alignment of section. unsigned EntSize; // sh_entsize - Size of entries in the section e - // Section Header Flags - enum { - SHF_WRITE = 1 << 0, // Writable - SHF_ALLOC = 1 << 1, // Mapped into the process addr space - SHF_EXECINSTR = 1 << 2, // Executable - SHF_MERGE = 1 << 4, // Might be merged if equal - SHF_STRINGS = 1 << 5, // Contains null-terminated strings - SHF_INFO_LINK = 1 << 6, // 'sh_info' contains SHT index - SHF_LINK_ORDER = 1 << 7, // Preserve order after combining - SHF_OS_NONCONFORMING = 1 << 8, // nonstandard OS support required - SHF_GROUP = 1 << 9, // Section is a member of a group - SHF_TLS = 1 << 10 // Section holds thread-local data - }; - - // Section Types - enum { - SHT_NULL = 0, // No associated section (inactive entry). - SHT_PROGBITS = 1, // Program-defined contents. - SHT_SYMTAB = 2, // Symbol table. - SHT_STRTAB = 3, // String table. - SHT_RELA = 4, // Relocation entries; explicit addends. - SHT_HASH = 5, // Symbol hash table. - SHT_DYNAMIC = 6, // Information for dynamic linking. - SHT_NOTE = 7, // Information about the file. - SHT_NOBITS = 8, // Data occupies no space in the file. - SHT_REL = 9, // Relocation entries; no explicit addends. - SHT_SHLIB = 10, // Reserved. - SHT_DYNSYM = 11, // Symbol table. - SHT_LOPROC = 0x70000000, // Lowest processor arch-specific type. - SHT_HIPROC = 0x7fffffff, // Highest processor arch-specific type. - SHT_LOUSER = 0x80000000, // Lowest type reserved for applications. - SHT_HIUSER = 0xffffffff // Highest type reserved for applications. - }; - - // Special section indices. - enum { - SHN_UNDEF = 0, // Undefined, missing, irrelevant - SHN_LORESERVE = 0xff00, // Lowest reserved index - SHN_LOPROC = 0xff00, // Lowest processor-specific index - SHN_HIPROC = 0xff1f, // Highest processor-specific index - SHN_ABS = 0xfff1, // Symbol has absolute value; no relocation - SHN_COMMON = 0xfff2, // FORTRAN COMMON or C external global variables - SHN_HIRESERVE = 0xffff // Highest reserved index - }; - /// SectionIdx - The number of the section in the Section Table. unsigned short SectionIdx; Modified: llvm/trunk/lib/CodeGen/ELFCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ELFCodeEmitter.cpp?rev=108520&r1=108519&r2=108520&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ELFCodeEmitter.cpp (original) +++ llvm/trunk/lib/CodeGen/ELFCodeEmitter.cpp Fri Jul 16 02:53:29 2010 @@ -71,7 +71,7 @@ bool ELFCodeEmitter::finishFunction(MachineFunction &MF) { // Add a symbol to represent the function. const Function *F = MF.getFunction(); - ELFSym *FnSym = ELFSym::getGV(F, EW.getGlobalELFBinding(F), ELFSym::STT_FUNC, + ELFSym *FnSym = ELFSym::getGV(F, EW.getGlobalELFBinding(F), ELF::STT_FUNC, EW.getGlobalELFVisibility(F)); FnSym->SectionIdx = ES->SectionIdx; FnSym->Size = ES->getCurrentPCOffset()-FnStartOff; Modified: llvm/trunk/lib/CodeGen/ELFWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ELFWriter.cpp?rev=108520&r1=108519&r2=108520&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ELFWriter.cpp (original) +++ llvm/trunk/lib/CodeGen/ELFWriter.cpp Fri Jul 16 02:53:29 2010 @@ -129,12 +129,12 @@ ElfHdr.emitByte(TEW->getEIClass()); // e_ident[EI_CLASS] ElfHdr.emitByte(TEW->getEIData()); // e_ident[EI_DATA] - ElfHdr.emitByte(EV_CURRENT); // e_ident[EI_VERSION] + ElfHdr.emitByte(ELF::EV_CURRENT); // e_ident[EI_VERSION] ElfHdr.emitAlignment(16); // e_ident[EI_NIDENT-EI_PAD] - ElfHdr.emitWord16(ET_REL); // e_type + ElfHdr.emitWord16(ELF::ET_REL); // e_type ElfHdr.emitWord16(TEW->getEMachine()); // e_machine = target - ElfHdr.emitWord32(EV_CURRENT); // e_version + ElfHdr.emitWord32(ELF::EV_CURRENT); // e_version ElfHdr.emitWord(0); // e_entry, no entry point in .o file ElfHdr.emitWord(0); // e_phoff, no program header for .o ELFHdr_e_shoff_Offset = ElfHdr.size(); @@ -252,7 +252,7 @@ // is true if the relocation section contains entries with addends. ELFSection &ELFWriter::getRelocSection(ELFSection &S) { unsigned SectionType = TEW->hasRelocationAddend() ? - ELFSection::SHT_RELA : ELFSection::SHT_REL; + ELF::SHT_RELA : ELF::SHT_REL; std::string SectionName(".rel"); if (TEW->hasRelocationAddend()) @@ -268,11 +268,11 @@ default: llvm_unreachable("unknown visibility type"); case GlobalValue::DefaultVisibility: - return ELFSym::STV_DEFAULT; + return ELF::STV_DEFAULT; case GlobalValue::HiddenVisibility: - return ELFSym::STV_HIDDEN; + return ELF::STV_HIDDEN; case GlobalValue::ProtectedVisibility: - return ELFSym::STV_PROTECTED; + return ELF::STV_PROTECTED; } return 0; } @@ -280,23 +280,23 @@ // getGlobalELFBinding - Returns the ELF specific binding type unsigned ELFWriter::getGlobalELFBinding(const GlobalValue *GV) { if (GV->hasInternalLinkage()) - return ELFSym::STB_LOCAL; + return ELF::STB_LOCAL; if (GV->isWeakForLinker() && !GV->hasCommonLinkage()) - return ELFSym::STB_WEAK; + return ELF::STB_WEAK; - return ELFSym::STB_GLOBAL; + return ELF::STB_GLOBAL; } // getGlobalELFType - Returns the ELF specific type for a global unsigned ELFWriter::getGlobalELFType(const GlobalValue *GV) { if (GV->isDeclaration()) - return ELFSym::STT_NOTYPE; + return ELF::STT_NOTYPE; if (isa(GV)) - return ELFSym::STT_FUNC; + return ELF::STT_FUNC; - return ELFSym::STT_OBJECT; + return ELF::STT_OBJECT; } // IsELFUndefSym - True if the global value must be marked as a symbol @@ -364,7 +364,7 @@ GblSym->Size = Size; if (S->HasCommonSymbols()) { // Symbol must go to a common section - GblSym->SectionIdx = ELFSection::SHN_COMMON; + GblSym->SectionIdx = ELF::SHN_COMMON; // A new linkonce section is created for each global in the // common section, the default alignment is 1 and the symbol Modified: llvm/trunk/lib/CodeGen/ELFWriter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ELFWriter.h?rev=108520&r1=108519&r2=108520&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ELFWriter.h (original) +++ llvm/trunk/lib/CodeGen/ELFWriter.h Fri Jul 16 02:53:29 2010 @@ -160,29 +160,29 @@ SN->SectionIdx = NumSections++; SN->Type = Type; SN->Flags = Flags; - SN->Link = ELFSection::SHN_UNDEF; + SN->Link = ELF::SHN_UNDEF; SN->Align = Align; return *SN; } ELFSection &getNonExecStackSection() { - return getSection(".note.GNU-stack", ELFSection::SHT_PROGBITS, 0, 1); + return getSection(".note.GNU-stack", ELF::SHT_PROGBITS, 0, 1); } ELFSection &getSymbolTableSection() { - return getSection(".symtab", ELFSection::SHT_SYMTAB, 0); + return getSection(".symtab", ELF::SHT_SYMTAB, 0); } ELFSection &getStringTableSection() { - return getSection(".strtab", ELFSection::SHT_STRTAB, 0, 1); + return getSection(".strtab", ELF::SHT_STRTAB, 0, 1); } ELFSection &getSectionHeaderStringTableSection() { - return getSection(".shstrtab", ELFSection::SHT_STRTAB, 0, 1); + return getSection(".shstrtab", ELF::SHT_STRTAB, 0, 1); } ELFSection &getNullSection() { - return getSection("", ELFSection::SHT_NULL, 0); + return getSection("", ELF::SHT_NULL, 0); } ELFSection &getDataSection(); Modified: llvm/trunk/lib/ExecutionEngine/JIT/JITDebugRegisterer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/JITDebugRegisterer.cpp?rev=108520&r1=108519&r2=108520&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/JIT/JITDebugRegisterer.cpp (original) +++ llvm/trunk/lib/ExecutionEngine/JIT/JITDebugRegisterer.cpp Fri Jul 16 02:53:29 2010 @@ -90,8 +90,8 @@ // section. This allows GDB to get a good stack trace, particularly on // linux x86_64. Mark this as a PROGBITS section that needs to be loaded // into memory at runtime. - ELFSection &EH = EW.getSection(".eh_frame", ELFSection::SHT_PROGBITS, - ELFSection::SHF_ALLOC); + ELFSection &EH = EW.getSection(".eh_frame", ELF::SHT_PROGBITS, + ELF::SHF_ALLOC); // Pointers in the DWARF EH info are all relative to the EH frame start, // which is stored here. EH.Addr = (uint64_t)I.EhStart; @@ -102,9 +102,9 @@ // Add this single function to the symbol table, so the debugger prints the // name instead of '???'. We give the symbol default global visibility. ELFSym *FnSym = ELFSym::getGV(F, - ELFSym::STB_GLOBAL, - ELFSym::STT_FUNC, - ELFSym::STV_DEFAULT); + ELF::STB_GLOBAL, + ELF::STT_FUNC, + ELF::STV_DEFAULT); FnSym->SectionIdx = Text.SectionIdx; FnSym->Size = I.FnEnd - I.FnStart; FnSym->Value = 0; // Offset from start of section. From ggreif at gmail.com Fri Jul 16 04:38:02 2010 From: ggreif at gmail.com (Gabor Greif) Date: Fri, 16 Jul 2010 09:38:02 -0000 Subject: [llvm-commits] [llvm] r108522 - in /llvm/trunk: include/llvm/Instructions.h include/llvm/Support/CallSite.h lib/Analysis/ConstantFolding.cpp lib/Transforms/InstCombine/InstCombineCalls.cpp lib/Transforms/Scalar/CodeGenPrepare.cpp lib/Transforms/Scalar/ScalarReplAggregates.cpp lib/Transforms/Utils/BuildLibCalls.cpp lib/VMCore/Instructions.cpp Message-ID: <20100716093802.69A182A6C12C@llvm.org> Author: ggreif Date: Fri Jul 16 04:38:02 2010 New Revision: 108522 URL: http://llvm.org/viewvc/llvm-project?rev=108522&view=rev Log: eliminate CallInst::ArgOffset Modified: llvm/trunk/include/llvm/Instructions.h llvm/trunk/include/llvm/Support/CallSite.h llvm/trunk/lib/Analysis/ConstantFolding.cpp llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp llvm/trunk/lib/VMCore/Instructions.cpp Modified: llvm/trunk/include/llvm/Instructions.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=108522&r1=108521&r2=108522&view=diff ============================================================================== --- llvm/trunk/include/llvm/Instructions.h (original) +++ llvm/trunk/include/llvm/Instructions.h Fri Jul 16 04:38:02 2010 @@ -964,10 +964,9 @@ # undef protected public: - enum { ArgOffset = 0 }; ///< temporary, do not use for new code! unsigned getNumArgOperands() const { return getNumOperands() - 1; } - Value *getArgOperand(unsigned i) const { return getOperand(i + ArgOffset); } - void setArgOperand(unsigned i, Value *v) { setOperand(i + ArgOffset, v); } + Value *getArgOperand(unsigned i) const { return getOperand(i); } + void setArgOperand(unsigned i, Value *v) { setOperand(i, v); } /// getCallingConv/setCallingConv - Get or set the calling convention of this /// function call. @@ -1056,17 +1055,17 @@ /// indirect function invocation. /// Function *getCalledFunction() const { - return dyn_cast(Op()); + return dyn_cast(Op<-1>()); } /// getCalledValue - Get a pointer to the function that is invoked by this /// instruction. - const Value *getCalledValue() const { return Op(); } - Value *getCalledValue() { return Op(); } + const Value *getCalledValue() const { return Op<-1>(); } + Value *getCalledValue() { return Op<-1>(); } /// setCalledFunction - Set the function called. void setCalledFunction(Value* Fn) { - Op() = Fn; + Op<-1>() = Fn; } // Methods for support type inquiry through isa, cast, and dyn_cast: Modified: llvm/trunk/include/llvm/Support/CallSite.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/CallSite.h?rev=108522&r1=108521&r2=108522&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/CallSite.h (original) +++ llvm/trunk/include/llvm/Support/CallSite.h Fri Jul 16 04:38:02 2010 @@ -254,18 +254,16 @@ private: /// Returns the operand number of the first argument + /// FIXME: remove this func! unsigned getArgumentOffset() const { - if (isCall()) - return CallInst::ArgOffset; // Skip Function (ATM) - else - return 0; // Args are at the front + return 0; // Args are at the front } unsigned getArgumentEndOffset() const { if (isCall()) - return CallInst::ArgOffset ? 0 : 1; // Unchanged (ATM) + return 1; // Skip Callee else - return 3; // Skip BB, BB, Function + return 3; // Skip BB, BB, Callee } IterTy getCallee() const { @@ -273,11 +271,9 @@ // of the op_*() functions here. See CallSite::getCallee. // if (isCall()) - return CallInst::ArgOffset - ? getInstruction()->op_begin() // Unchanged - : getInstruction()->op_end() - 1; // Skip Function + return getInstruction()->op_end() - 1; // Skip Callee else - return getInstruction()->op_end() - 3; // Skip BB, BB, Function + return getInstruction()->op_end() - 3; // Skip BB, BB, Callee } }; Modified: llvm/trunk/lib/Analysis/ConstantFolding.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ConstantFolding.cpp?rev=108522&r1=108521&r2=108522&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ConstantFolding.cpp (original) +++ llvm/trunk/lib/Analysis/ConstantFolding.cpp Fri Jul 16 04:38:02 2010 @@ -778,9 +778,9 @@ case Instruction::ICmp: case Instruction::FCmp: assert(0 && "Invalid for compares"); case Instruction::Call: - if (Function *F = dyn_cast(Ops[CallInst::ArgOffset ? 0:NumOps-1])) + if (Function *F = dyn_cast(Ops[NumOps - 1])) if (canConstantFoldCallTo(F)) - return ConstantFoldCall(F, Ops+CallInst::ArgOffset, NumOps-1); + return ConstantFoldCall(F, Ops, NumOps - 1); return 0; case Instruction::PtrToInt: // If the input is a inttoptr, eliminate the pair. This requires knowing Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp?rev=108522&r1=108521&r2=108522&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp Fri Jul 16 04:38:02 2010 @@ -772,13 +772,13 @@ NewInstruction = IC->ReplaceInstUsesWith(*CI, With); } bool isFoldable(unsigned SizeCIOp, unsigned SizeArgOp, bool isString) const { - if (ConstantInt *SizeCI = dyn_cast(CI->getArgOperand(SizeCIOp - CallInst::ArgOffset))) { + if (ConstantInt *SizeCI = dyn_cast(CI->getArgOperand(SizeCIOp))) { if (SizeCI->isAllOnesValue()) return true; if (isString) return SizeCI->getZExtValue() >= - GetStringLength(CI->getArgOperand(SizeArgOp - CallInst::ArgOffset)); - if (ConstantInt *Arg = dyn_cast(CI->getArgOperand(SizeArgOp - CallInst::ArgOffset))) + GetStringLength(CI->getArgOperand(SizeArgOp)); + if (ConstantInt *Arg = dyn_cast(CI->getArgOperand(SizeArgOp))) return SizeCI->getZExtValue() >= Arg->getZExtValue(); } return false; Modified: llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp?rev=108522&r1=108521&r2=108522&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp Fri Jul 16 04:38:02 2010 @@ -548,9 +548,9 @@ CI->eraseFromParent(); } bool isFoldable(unsigned SizeCIOp, unsigned, bool) const { - if (ConstantInt *SizeCI = dyn_cast(CI->getArgOperand(SizeCIOp - - CallInst::ArgOffset))) - return SizeCI->isAllOnesValue(); + if (ConstantInt *SizeCI = + dyn_cast(CI->getArgOperand(SizeCIOp))) + return SizeCI->isAllOnesValue(); return false; } }; Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=108522&r1=108521&r2=108522&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Fri Jul 16 04:38:02 2010 @@ -969,7 +969,7 @@ ConstantInt *Length = dyn_cast(MI->getLength()); if (Length) isSafeMemAccess(AI, Offset, Length->getZExtValue(), 0, - UI.getOperandNo() == CallInst::ArgOffset, Info); + UI.getOperandNo() == 0, Info); else MarkUnsafe(Info); } else if (LoadInst *LI = dyn_cast(User)) { @@ -1787,7 +1787,7 @@ if (isOffset) return false; // If the memintrinsic isn't using the alloca as the dest, reject it. - if (UI.getOperandNo() != CallInst::ArgOffset) return false; + if (UI.getOperandNo() != 0) return false; // If the source of the memcpy/move is not a constant global, reject it. if (!PointsToConstantGlobal(MI->getSource())) Modified: llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp?rev=108522&r1=108521&r2=108522&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/BuildLibCalls.cpp Fri Jul 16 04:38:02 2010 @@ -421,7 +421,7 @@ FT->getParamType(3) != TD->getIntPtrType(Context)) return false; - if (isFoldable(3 + CallInst::ArgOffset, 2 + CallInst::ArgOffset, false)) { + if (isFoldable(3, 2, false)) { EmitMemCpy(CI->getArgOperand(0), CI->getArgOperand(1), CI->getArgOperand(2), 1, false, B, TD); replaceCall(CI->getArgOperand(0)); @@ -444,7 +444,7 @@ FT->getParamType(3) != TD->getIntPtrType(Context)) return false; - if (isFoldable(3 + CallInst::ArgOffset, 2 + CallInst::ArgOffset, false)) { + if (isFoldable(3, 2, false)) { EmitMemMove(CI->getArgOperand(0), CI->getArgOperand(1), CI->getArgOperand(2), 1, false, B, TD); replaceCall(CI->getArgOperand(0)); @@ -462,7 +462,7 @@ FT->getParamType(3) != TD->getIntPtrType(Context)) return false; - if (isFoldable(3 + CallInst::ArgOffset, 2 + CallInst::ArgOffset, false)) { + if (isFoldable(3, 2, false)) { Value *Val = B.CreateIntCast(CI->getArgOperand(1), B.getInt8Ty(), false); EmitMemSet(CI->getArgOperand(0), Val, CI->getArgOperand(2), false, B, TD); @@ -487,7 +487,7 @@ // st[rp]cpy_chk call which may fail at runtime if the size is too long. // TODO: It might be nice to get a maximum length out of the possible // string lengths for varying. - if (isFoldable(2 + CallInst::ArgOffset, 1 + CallInst::ArgOffset, true)) { + if (isFoldable(2, 1, true)) { Value *Ret = EmitStrCpy(CI->getArgOperand(0), CI->getArgOperand(1), B, TD, Name.substr(2, 6)); replaceCall(Ret); @@ -505,7 +505,7 @@ FT->getParamType(3) != TD->getIntPtrType(Context)) return false; - if (isFoldable(3 + CallInst::ArgOffset, 2 + CallInst::ArgOffset, false)) { + if (isFoldable(3, 2, false)) { Value *Ret = EmitStrNCpy(CI->getArgOperand(0), CI->getArgOperand(1), CI->getArgOperand(2), B, TD, Name.substr(2, 7)); replaceCall(Ret); Modified: llvm/trunk/lib/VMCore/Instructions.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=108522&r1=108521&r2=108522&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Instructions.cpp (original) +++ llvm/trunk/lib/VMCore/Instructions.cpp Fri Jul 16 04:38:02 2010 @@ -33,10 +33,8 @@ User::op_iterator CallSite::getCallee() const { Instruction *II(getInstruction()); return isCall() - ? (CallInst::ArgOffset - ? cast(II)->op_begin() - : cast(II)->op_end() - 1) - : cast(II)->op_end() - 3; // Skip BB, BB, Function + ? cast(II)->op_end() - 1 // Skip Callee + : cast(II)->op_end() - 3; // Skip BB, BB, Callee } //===----------------------------------------------------------------------===// @@ -233,7 +231,7 @@ void CallInst::init(Value *Func, Value* const *Params, unsigned NumParams) { assert(NumOperands == NumParams+1 && "NumOperands not set up?"); - Op() = Func; + Op<-1>() = Func; const FunctionType *FTy = cast(cast(Func->getType())->getElementType()); @@ -246,15 +244,15 @@ assert((i >= FTy->getNumParams() || FTy->getParamType(i) == Params[i]->getType()) && "Calling a function with a bad signature!"); - OperandList[i + ArgOffset] = Params[i]; + OperandList[i] = Params[i]; } } void CallInst::init(Value *Func, Value *Actual1, Value *Actual2) { assert(NumOperands == 3 && "NumOperands not set up?"); - Op() = Func; - Op() = Actual1; - Op() = Actual2; + Op<-1>() = Func; + Op<0>() = Actual1; + Op<1>() = Actual2; const FunctionType *FTy = cast(cast(Func->getType())->getElementType()); @@ -273,8 +271,8 @@ void CallInst::init(Value *Func, Value *Actual) { assert(NumOperands == 2 && "NumOperands not set up?"); - Op() = Func; - Op() = Actual; + Op<-1>() = Func; + Op<0>() = Actual; const FunctionType *FTy = cast(cast(Func->getType())->getElementType()); @@ -290,7 +288,7 @@ void CallInst::init(Value *Func) { assert(NumOperands == 1 && "NumOperands not set up?"); - Op() = Func; + Op<-1>() = Func; const FunctionType *FTy = cast(cast(Func->getType())->getElementType()); From anton at korobeynikov.info Fri Jul 16 05:12:16 2010 From: anton at korobeynikov.info (Anton Korobeynikov) Date: Fri, 16 Jul 2010 14:12:16 +0400 Subject: [llvm-commits] [llvm] r108513 - in /llvm/trunk: lib/VMCore/Dominators.cpp test/Transforms/LoopSimplify/2010-07-15-IncorrectDomFrontierUpdate.ll In-Reply-To: <20100716055946.1D9692A6C12D@llvm.org> References: <20100716055946.1D9692A6C12D@llvm.org> Message-ID: Hell, Tobias > URL: http://llvm.org/viewvc/llvm-project?rev=108513&view=rev > Log: > LoopSimplify does not update domfrontier correctly. Shouldn't there be a change to LoopSimplify then, not to DomFrontier? -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From grosser at fim.uni-passau.de Fri Jul 16 07:07:57 2010 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Fri, 16 Jul 2010 14:07:57 +0200 Subject: [llvm-commits] [llvm] r108513 - in /llvm/trunk: lib/VMCore/Dominators.cpp test/Transforms/LoopSimplify/2010-07-15-IncorrectDomFrontierUpdate.ll In-Reply-To: <4712_1279275143_4C403087_4712_794_1_AANLkTimHrO1n8LMAZHihaZuKVpUao5czRaxPl-raLs-K@mail.gmail.com> References: <20100716055946.1D9692A6C12D@llvm.org> <4712_1279275143_4C403087_4712_794_1_AANLkTimHrO1n8LMAZHihaZuKVpUao5czRaxPl-raLs-K@mail.gmail.com> Message-ID: <4C404B9D.8040706@fim.uni-passau.de> On 07/16/10 12:12, Anton Korobeynikov wrote: > Hell, Tobias > >> URL: http://llvm.org/viewvc/llvm-project?rev=108513&view=rev >> Log: >> LoopSimplify does not update domfrontier correctly. > Shouldn't there be a change to LoopSimplify then, not to DomFrontier? > LoopSimplify is using DomFrontier::splitBlock() to update the dom frontier. To me it seemed the splitBlock implementation was incorrect. Probably the commit message was misleading. Tobi From benny.kra at googlemail.com Fri Jul 16 05:58:02 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Fri, 16 Jul 2010 10:58:02 -0000 Subject: [llvm-commits] [llvm] r108523 - /llvm/trunk/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll Message-ID: <20100716105802.BCE902A6C12C@llvm.org> Author: d0k Date: Fri Jul 16 05:58:02 2010 New Revision: 108523 URL: http://llvm.org/viewvc/llvm-project?rev=108523&view=rev Log: Feed the right output into FileCheck. Modified: llvm/trunk/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll Modified: llvm/trunk/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll?rev=108523&r1=108522&r2=108523&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll (original) +++ llvm/trunk/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll Fri Jul 16 05:58:02 2010 @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=thumbv6-apple-darwin10 %s -o - | FileCheck %s -; RUN: opt -strip-debug < %s -o - | llc -mtriple=thumbv6-apple-darwin10 %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv6-apple-darwin10 < %s | FileCheck %s +; RUN: opt -strip-debug < %s | llc -mtriple=thumbv6-apple-darwin10 | FileCheck %s ; Stripping out debug info formerly caused the last two multiplies to be emitted in ; the other order. 7797940 (part of it dated 6/29/2010..7/15/2010). From dimitry at andric.com Fri Jul 16 06:26:19 2010 From: dimitry at andric.com (Dimitry Andric) Date: Fri, 16 Jul 2010 13:26:19 +0200 Subject: [llvm-commits] Windows compilation warnings In-Reply-To: References: <4C3F9455.5010106@andric.com> Message-ID: <4C4041DB.7030800@andric.com> On 2010-07-16 04:00, Villmow, Micah wrote: > This patch set makes Windows build cleanly for 32bit binaries from a > 64bit machine. Hmm, I regularly build 32-bit binaries on my 64-bit Windows machine, but I never get many warnings about truncations, except the recently introduced ones about enums being truncated. It is only when I build the x64 project that I get a lot of those warnings. Are you compiling with non-standard settings? E.g. -Wp64 (which I remember is deprecated) or -W4, the maximum warning setting? > Some thoughts about what I saw while doing this. > > size_t is not used in places where it should be, return value of > size(), input value of resize(). Actually, in most cases, the class's "size_type", "difference_type" and so on should be used. AFAIK there is no guarantee these are always equivalent to size_t (although they usually are in practice). But indeed, the cases where size_types are stuffed into plain ints or unsigneds are many, although it may not be that easy to just change whatever variable holds them to size_type. For example, you may need to change function declarations to effectively do that, and such changes tend to "cascade" through a lot of the source. > getZExtValue()/getSExtValue() need 32bit explicit versions, this > would remove probably 60% of truncation casts. But you would still need to go over *all* the invocations, to replace them... and be extremely careful not to break anything by those replacements. > uint64_t is overused in places where uint32_t is sufficient. There may be reasons for those uses, but the only ones that can explain are the authors of the code in question. :) > unsigned/signed is used where uint32_t/int32_t should be used. > > Should there be something the developers notes about these? I think > it is better to explicitly specify the integer size instead on > relying on the compiler to pick the size. I am not sure if hardcoding the number of bits in the type is always the best solution in all cases. This really depends on the specific piece of code. Most of the times you just want to use plain int or unsigned, because that will always be the machine's default word. You only have to pay attention when mixing those with "size" types, such as object lengths and pointer differences. From stoklund at 2pi.dk Fri Jul 16 09:47:46 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Fri, 16 Jul 2010 07:47:46 -0700 Subject: [llvm-commits] [llvm] r108219 - /llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp In-Reply-To: References: <20100713002330.9D06F2A6C12C@llvm.org> Message-ID: <7620E798-21A8-4A13-8360-3F2CB778E4E0@2pi.dk> On Jul 14, 2010, at 8:46 PM, Daniel Dunbar wrote: > Hi Jakob, > > memcpy-inline.ll is currently failing on llvm-gcc-powerpc-darwin9, like this: > -- > ******************** TEST 'LLVM :: CodeGen/ARM/memcpy-inline.ll' > FAILED ********************Script: > -- > llc < /Users/buildslave/zorg/buildbot/smooshlab/slave/build.llvm-gcc-powerpc-darwin9/llvm.src/test/CodeGen/ARM/memcpy-inline.ll > -mtriple=arm-apple-darwin | grep ldmia > llc < /Users/buildslave/zorg/buildbot/smooshlab/slave/build.llvm-gcc-powerpc-darwin9/llvm.src/test/CodeGen/ARM/memcpy-inline.ll > -mtriple=arm-apple-darwin | grep stmia > llc < /Users/buildslave/zorg/buildbot/smooshlab/slave/build.llvm-gcc-powerpc-darwin9/llvm.src/test/CodeGen/ARM/memcpy-inline.ll > -mtriple=arm-apple-darwin | grep ldrb > llc < /Users/buildslave/zorg/buildbot/smooshlab/slave/build.llvm-gcc-powerpc-darwin9/llvm.src/test/CodeGen/ARM/memcpy-inline.ll > -mtriple=arm-apple-darwin | grep ldrh > -- > Exit Code: 1 > Command Output (stdout): > -- > Command has output on stderr! > > -- > Command Output (stderr): > -- > 0 llc 0x00b890cc llvm::sys::RunInterruptHandlers() + 1196 > 1 llc 0x00b897d8 llvm::sys::PrintStackTraceOnErrorSignal() + 1128 > 2 libSystem.B.dylib 0x966089fc _sigtramp + 68 > Stack dump: > 0. Program arguments: llc -mtriple=arm-apple-darwin > 1. Running pass 'Function Pass Manager' on module ''. > 2. Running pass 'ARM Instruction Selection' on function '@t' > -- > > ******************** > -- > > It started in this build: > http://smooshlab.apple.com:8010/builders/llvm-gcc-powerpc-darwin9/builds/3331 > and I think this change is the most likely culprit. Can you take a > look, or point the finger? I have verified that reverting my patch fixes the buildbot. However, that same patch fixes 5 nightly tests on ARM, and the code was definitely wrong before, so I am going to leave the patch in until I have figured out why it makes ppc fail. /jakob From dgregor at apple.com Fri Jul 16 10:03:23 2010 From: dgregor at apple.com (Douglas Gregor) Date: Fri, 16 Jul 2010 15:03:23 -0000 Subject: [llvm-commits] [llvm] r108525 - /llvm/trunk/include/llvm/Support/ELF.h Message-ID: <20100716150323.72EA42A6C12C@llvm.org> Author: dgregor Date: Fri Jul 16 10:03:23 2010 New Revision: 108525 URL: http://llvm.org/viewvc/llvm-project?rev=108525&view=rev Log: Remove extraneous semicolons after member functions Modified: llvm/trunk/include/llvm/Support/ELF.h Modified: llvm/trunk/include/llvm/Support/ELF.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ELF.h?rev=108525&r1=108524&r2=108525&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/ELF.h (original) +++ llvm/trunk/include/llvm/Support/ELF.h Fri Jul 16 10:03:23 2010 @@ -365,7 +365,7 @@ void setType(unsigned char t) { setSymbolAndType(getSymbol(), t); } void setSymbolAndType(Elf32_Word s, unsigned char t) { r_info = (s << 8) + t; - }; + } }; // Relocation entry with explicit addend. @@ -382,7 +382,7 @@ void setType(unsigned char t) { setSymbolAndType(getSymbol(), t); } void setSymbolAndType(Elf32_Word s, unsigned char t) { r_info = (s << 8) + t; - }; + } }; // Relocation entry, without explicit addend. @@ -400,7 +400,7 @@ void setType(unsigned char t) { setSymbolAndType(getSymbol(), t); } void setSymbolAndType(Elf64_Xword s, unsigned char t) { r_info = (s << 32) + (t&0xffffffffL); - }; + } }; // Relocation entry with explicit addend. @@ -419,7 +419,7 @@ void setType(unsigned char t) { setSymbolAndType(getSymbol(), t); } void setSymbolAndType(Elf64_Xword s, unsigned char t) { r_info = (s << 32) + (t&0xffffffffL); - }; + } }; // Program header for ELF32. From daniel at zuster.org Fri Jul 16 10:36:33 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Fri, 16 Jul 2010 08:36:33 -0700 Subject: [llvm-commits] [llvm] r107678 - in /llvm/trunk: lib/Target/X86/AsmPrinter/X86MCInstLower.cpp test/CodeGen/X86/2010-07-06-DbgCrash.ll In-Reply-To: <20100706181832.4A4402A6C12C@llvm.org> References: <20100706181832.4A4402A6C12C@llvm.org> Message-ID: Hi Devang, The valgrind buildbot is back online, and is reporting an error with this test. Can you take a look: http://google1.osuosl.org:8011/builders/llvm-i686-linux-vg_leak/builds/1076/steps/test-llvm/logs/2010-07-06-dbgcrash.ll - Daniel On Tue, Jul 6, 2010 at 11:18 AM, Devang Patel wrote: > Author: dpatel > Date: Tue Jul ?6 13:18:32 2010 > New Revision: 107678 > > URL: http://llvm.org/viewvc/llvm-project?rev=107678&view=rev > Log: > Fix PR7545 crash. > > Added: > ? ?llvm/trunk/test/CodeGen/X86/2010-07-06-DbgCrash.ll > Modified: > ? ?llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp > > Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp?rev=107678&r1=107677&r2=107678&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp (original) > +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp Tue Jul ?6 13:18:32 2010 > @@ -505,7 +505,6 @@ > ? O << V.getName(); > ? O << " <- "; > ? // Frame address. ?Currently handles register +- offset only. > - ?assert(MI->getOperand(0).isReg() && MI->getOperand(3).isImm()); > ? O << '['; printOperand(MI, 0, O); O << '+'; printOperand(MI, 3, O); > ? O << ']'; > ? O << "+"; > @@ -517,8 +516,9 @@ > ? MachineLocation Location; > ? assert (MI->getNumOperands() == 7 && "Invalid no. of machine operands!"); > ? // Frame address. ?Currently handles register +- offset only. > - ?assert(MI->getOperand(0).isReg() && MI->getOperand(3).isImm()); > - ?Location.set(MI->getOperand(0).getReg(), MI->getOperand(3).getImm()); > + > + ?if (MI->getOperand(0).isReg() && MI->getOperand(3).isImm()) > + ? ?Location.set(MI->getOperand(0).getReg(), MI->getOperand(3).getImm()); > ? return Location; > ?} > > > Added: llvm/trunk/test/CodeGen/X86/2010-07-06-DbgCrash.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-07-06-DbgCrash.ll?rev=107678&view=auto > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/2010-07-06-DbgCrash.ll (added) > +++ llvm/trunk/test/CodeGen/X86/2010-07-06-DbgCrash.ll Tue Jul ?6 13:18:32 2010 > @@ -0,0 +1,29 @@ > +; RUN: llc -O0 -relocation-model pic -o /dev/null > +; PR7545 > + at .str = private constant [4 x i8] c"one\00", align 1 ; <[4 x i8]*> [#uses=1] > + at .str1 = private constant [4 x i8] c"two\00", align 1 ; <[5 x i8]*> [#uses=1] > + at C.9.2167 = internal constant [2 x i8*] [i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), i8* getelementptr inbounds ([4 x i8]* @.str1, i64 0, i64 0)] > +!38 = metadata !{i32 524329, metadata !"pbmsrch.c", metadata !"/Users/grawp/LLVM/test-suite/MultiSource/Benchmarks/MiBench/office-stringsearch", metadata !39} ; [ DW_TAG_file_type ] > +!39 = metadata !{i32 524305, i32 0, i32 1, metadata !"pbmsrch.c", metadata !"/Users/grawp/LLVM/test-suite/MultiSource/Benchmarks/MiBench/office-stringsearch", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build 9999)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] > +!46 = metadata !{i32 524303, metadata !38, metadata !"", metadata !38, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !47} ; [ DW_TAG_pointer_type ]!97 = metadata !{i32 524334, i32 0, metadata !38, metadata !"main", metadata !"main", metadata !"main", metadata !38, i32 73, metadata !98, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]!101 = metadata !{[2 x i8*]* @C.9.2167} > +!47 = metadata !{i32 524324, metadata !38, metadata !"char", metadata !38, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] > +!97 = metadata !{i32 524334, i32 0, metadata !38, metadata !"main", metadata !"main", metadata !"main", metadata !38, i32 73, metadata !98, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ] > +!98 = metadata !{i32 524309, metadata !38, metadata !"", metadata !38, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !99, i32 0, null} ; [ DW_TAG_subroutine_type ] > +!99 = metadata !{metadata !100} > +!100 = metadata !{i32 524324, metadata !38, metadata !"int", metadata !38, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] > +!101 = metadata !{[2 x i8*]* @C.9.2167} > +!102 = metadata !{i32 524544, metadata !103, metadata !"find_strings", metadata !38, i32 75, metadata !104} ; [ DW_TAG_auto_variable ] > +!103 = metadata !{i32 524299, metadata !97, i32 73, i32 0} ; [ DW_TAG_lexical_block ] > +!104 = metadata !{i32 524289, metadata !38, metadata !"", metadata !38, i32 0, i64 85312, i64 64, i64 0, i32 0, metadata !46, metadata !105, i32 0, null} ; [ DW_TAG_array_type ] > +!105 = metadata !{metadata !106} > +!106 = metadata !{i32 524321, i64 0, i64 1332} ? ?; [ DW_TAG_subrange_type ] > +!107 = metadata !{i32 73, i32 0, metadata !103, null} > + > +define i32 @main() nounwind ssp { > +bb.nph: > + ?tail call void @llvm.dbg.declare(metadata !101, metadata !102), !dbg !107 > + ?ret i32 0, !dbg !107 > +} > + > +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone > + > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From stoklund at 2pi.dk Fri Jul 16 11:38:12 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Fri, 16 Jul 2010 16:38:12 -0000 Subject: [llvm-commits] [llvm] r108529 - in /llvm/trunk/lib/Target/X86: X86FloatingPoint.cpp X86TargetMachine.cpp Message-ID: <20100716163813.04C572A6C12C@llvm.org> Author: stoklund Date: Fri Jul 16 11:38:12 2010 New Revision: 108529 URL: http://llvm.org/viewvc/llvm-project?rev=108529&view=rev Log: Allow x87 FP registers to be alive globally in a function. FP_REG_KILL instructions are still inserted, but can be disabled by passing -live-x87 to llc. The X87FPRegKillInserterPass is going to be removed shortly. CFG edges are partioned into bundles where the x87 stack must be allocated identically. Code is insertad at the end of each basic block that shuffles the live FP registers to match the outgoing bundles expectations. This fix is in preparation for some upcoming register allocator improvements that may extend the live range of registers beyond a basic block, similar to LICM. It also provides a nice runtime speedup if you are building with -mfpmath=387. Modified: llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Modified: llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp?rev=108529&r1=108528&r2=108529&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp Fri Jul 16 11:38:12 2010 @@ -8,23 +8,18 @@ //===----------------------------------------------------------------------===// // // This file defines the pass which converts floating point instructions from -// virtual registers into register stack instructions. This pass uses live +// pseudo registers into register stack instructions. This pass uses live // variable information to indicate where the FPn registers are used and their // lifetimes. // -// This pass is hampered by the lack of decent CFG manipulation routines for -// machine code. In particular, this wants to be able to split critical edges -// as necessary, traverse the machine basic block CFG in depth-first order, and -// allow there to be multiple machine basic blocks for each LLVM basicblock -// (needed for critical edge splitting). +// The x87 hardware tracks liveness of the stack registers, so it is necessary +// to implement exact liveness tracking between basic blocks. The CFG edges are +// partitioned into bundles where the same FP registers must be live in +// identical stack positions. Instructions are inserted at the end of each basic +// block to rearrange the live registers to match the outgoing bundle. // -// In particular, this pass currently barfs on critical edges. Because of this, -// it requires the instruction selector to insert FP_REG_KILL instructions on -// the exits of any basic block that has critical edges going from it, or which -// branch to a critical basic block. -// -// FIXME: this is not implemented yet. The stackifier pass only works on local -// basic blocks. +// This approach avoids splitting critical edges at the potential cost of more +// live register shuffling instructions when critical edges are present. // //===----------------------------------------------------------------------===// @@ -32,6 +27,7 @@ #include "X86.h" #include "X86InstrInfo.h" #include "llvm/ADT/DepthFirstIterator.h" +#include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/Statistic.h" @@ -69,11 +65,71 @@ private: const TargetInstrInfo *TII; // Machine instruction info. + + // Two CFG edges are related if they leave the same block, or enter the same + // block. The transitive closure of an edge under this relation is a + // LiveBundle. It represents a set of CFG edges where the live FP stack + // registers must be allocated identically in the x87 stack. + // + // A LiveBundle is usually all the edges leaving a block, or all the edges + // entering a block, but it can contain more edges if critical edges are + // present. + // + // The set of live FP registers in a LiveBundle is calculated by bundleCFG, + // but the exact mapping of FP registers to stack slots is fixed later. + struct LiveBundle { + // Bit mask of live FP registers. Bit 0 = FP0, bit 1 = FP1, &c. + unsigned Mask; + + // Number of pre-assigned live registers in FixStack. This is 0 when the + // stack order has not yet been fixed. + unsigned FixCount; + + // Assigned stack order for live-in registers. + // FixStack[i] == getStackEntry(i) for all i < FixCount. + unsigned char FixStack[8]; + + LiveBundle(unsigned m = 0) : Mask(m), FixCount(0) {} + + // Have the live registers been assigned a stack order yet? + bool isFixed() const { return !Mask || FixCount; } + }; + + // Numbered LiveBundle structs. LiveBundles[0] is used for all CFG edges + // with no live FP registers. + SmallVector LiveBundles; + + // Map each MBB in the current function to an (ingoing, outgoing) index into + // LiveBundles. Blocks with no FP registers live in or out map to (0, 0) + // and are not actually stored in the map. + DenseMap > BlockBundle; + + // Return a bitmask of FP registers in block's live-in list. + unsigned calcLiveInMask(MachineBasicBlock *MBB) { + unsigned Mask = 0; + for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(), + E = MBB->livein_end(); I != E; ++I) { + unsigned Reg = *I - X86::FP0; + if (Reg < 8) + Mask |= 1 << Reg; + } + return Mask; + } + + // Partition all the CFG edges into LiveBundles. + void bundleCFG(MachineFunction &MF); + MachineBasicBlock *MBB; // Current basic block unsigned Stack[8]; // FP Registers in each stack slot... unsigned RegMap[8]; // Track which stack slot contains each register unsigned StackTop; // The current top of the FP stack. + // Set up our stack model to match the incoming registers to MBB. + void setupBlockStack(); + + // Shuffle live registers to match the expectations of successor blocks. + void finishBlockStack(); + void dumpStack() const { dbgs() << "Stack contents:"; for (unsigned i = 0; i != StackTop; ++i) { @@ -82,12 +138,12 @@ } dbgs() << "\n"; } - private: + /// isStackEmpty - Return true if the FP stack is empty. bool isStackEmpty() const { return StackTop == 0; } - + // getSlot - Return the stack slot number a particular register number is // in. unsigned getSlot(unsigned RegNo) const { @@ -95,6 +151,12 @@ return RegMap[RegNo]; } + // isLive - Is RegNo currently live in the stack? + bool isLive(unsigned RegNo) const { + unsigned Slot = getSlot(RegNo); + return Slot < StackTop && Stack[Slot] == RegNo; + } + // getStackEntry - Return the X86::FP register in register ST(i). unsigned getStackEntry(unsigned STi) const { assert(STi < StackTop && "Access past stack top!"); @@ -117,10 +179,9 @@ bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; } void moveToTop(unsigned RegNo, MachineBasicBlock::iterator I) { - MachineInstr *MI = I; - DebugLoc dl = MI->getDebugLoc(); + DebugLoc dl = I == MBB->end() ? DebugLoc() : I->getDebugLoc(); if (isAtTop(RegNo)) return; - + unsigned STReg = getSTReg(RegNo); unsigned RegOnTop = getStackEntry(0); @@ -137,7 +198,7 @@ } void duplicateToTop(unsigned RegNo, unsigned AsReg, MachineInstr *I) { - DebugLoc dl = I->getDebugLoc(); + DebugLoc dl = I == MBB->end() ? DebugLoc() : I->getDebugLoc(); unsigned STReg = getSTReg(RegNo); pushReg(AsReg); // New register on top of stack @@ -155,6 +216,19 @@ // of stack. void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg); + // freeStackSlotBefore - Just the pop, no folding. Return the inserted + // instruction. + MachineBasicBlock::iterator + freeStackSlotBefore(MachineBasicBlock::iterator I, unsigned FPRegNo); + + // Adjust the live registers to be the set in Mask. + void adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I); + + // Shuffle the top FixCount stack entries susch that FP reg FixStack[0] is + //st(0), FP reg FixStack[1] is st(1) etc. + void shuffleStackTop(const unsigned char *FixStack, unsigned FixCount, + MachineBasicBlock::iterator I); + bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB); void handleZeroArgFP(MachineBasicBlock::iterator &I); @@ -181,7 +255,6 @@ return Reg - X86::FP0; } - /// runOnMachineFunction - Loop over all of the basic blocks, transforming FP /// register references into FP stack references. /// @@ -201,6 +274,10 @@ if (!FPIsUsed) return false; TII = MF.getTarget().getInstrInfo(); + + // Prepare cross-MBB liveness. + bundleCFG(MF); + StackTop = 0; // Process the function in depth first order so that we process at least one @@ -215,16 +292,111 @@ Changed |= processBasicBlock(MF, **I); // Process any unreachable blocks in arbitrary order now. - if (MF.size() == Processed.size()) - return Changed; + if (MF.size() != Processed.size()) + for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB) + if (Processed.insert(BB)) + Changed |= processBasicBlock(MF, *BB); + + BlockBundle.clear(); + LiveBundles.clear(); - for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB) - if (Processed.insert(BB)) - Changed |= processBasicBlock(MF, *BB); - return Changed; } +/// bundleCFG - Scan all the basic blocks to determine consistent live-in and +/// live-out sets for the FP registers. Consistent means that the set of +/// registers live-out from a block is identical to the live-in set of all +/// successors. This is not enforced by the normal live-in lists since +/// registers may be implicitly defined, or not used by all successors. +void FPS::bundleCFG(MachineFunction &MF) { + assert(LiveBundles.empty() && "Stale data in LiveBundles"); + assert(BlockBundle.empty() && "Stale data in BlockBundle"); + SmallPtrSet PropDown, PropUp; + + // LiveBundle[0] is the empty live-in set. + LiveBundles.resize(1); + + // First gather the actual live-in masks for all MBBs. + for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) { + MachineBasicBlock *MBB = I; + const unsigned Mask = calcLiveInMask(MBB); + if (!Mask) + continue; + // Ingoing bundle index. + unsigned &Idx = BlockBundle[MBB].first; + // Already assigned an ingoing bundle? + if (Idx) + continue; + // Allocate a new LiveBundle struct for this block's live-ins. + const unsigned BundleIdx = Idx = LiveBundles.size(); + DEBUG(dbgs() << "Creating LB#" << BundleIdx << ": in:BB#" + << MBB->getNumber()); + LiveBundles.push_back(Mask); + LiveBundle &Bundle = LiveBundles.back(); + + // Make sure all predecessors have the same live-out set. + PropUp.insert(MBB); + + // Keep pushing liveness up and down the CFG until convergence. + // Only critical edges cause iteration here, but when they do, multiple + // blocks can be assigned to the same LiveBundle index. + do { + // Assign BundleIdx as liveout from predecessors in PropUp. + for (SmallPtrSet::iterator I = PropUp.begin(), + E = PropUp.end(); I != E; ++I) { + MachineBasicBlock *MBB = *I; + for (MachineBasicBlock::const_pred_iterator LinkI = MBB->pred_begin(), + LinkE = MBB->pred_end(); LinkI != LinkE; ++LinkI) { + MachineBasicBlock *PredMBB = *LinkI; + // PredMBB's liveout bundle should be set to LIIdx. + unsigned &Idx = BlockBundle[PredMBB].second; + if (Idx) { + assert(Idx == BundleIdx && "Inconsistent CFG"); + continue; + } + Idx = BundleIdx; + DEBUG(dbgs() << " out:BB#" << PredMBB->getNumber()); + // Propagate to siblings. + if (PredMBB->succ_size() > 1) + PropDown.insert(PredMBB); + } + } + PropUp.clear(); + + // Assign BundleIdx as livein to successors in PropDown. + for (SmallPtrSet::iterator I = PropDown.begin(), + E = PropDown.end(); I != E; ++I) { + MachineBasicBlock *MBB = *I; + for (MachineBasicBlock::const_succ_iterator LinkI = MBB->succ_begin(), + LinkE = MBB->succ_end(); LinkI != LinkE; ++LinkI) { + MachineBasicBlock *SuccMBB = *LinkI; + // LinkMBB's livein bundle should be set to BundleIdx. + unsigned &Idx = BlockBundle[SuccMBB].first; + if (Idx) { + assert(Idx == BundleIdx && "Inconsistent CFG"); + continue; + } + Idx = BundleIdx; + DEBUG(dbgs() << " in:BB#" << SuccMBB->getNumber()); + // Propagate to siblings. + if (SuccMBB->pred_size() > 1) + PropUp.insert(SuccMBB); + // Also accumulate the bundle liveness mask from the liveins here. + Bundle.Mask |= calcLiveInMask(SuccMBB); + } + } + PropDown.clear(); + } while (!PropUp.empty()); + DEBUG({ + dbgs() << " live:"; + for (unsigned i = 0; i < 8; ++i) + if (Bundle.Mask & (1<getDesc().TSFlags; - + unsigned FPInstClass = Flags & X86II::FPTypeMask; if (MI->isInlineAsm()) FPInstClass = X86II::SpecialFP; @@ -302,10 +476,82 @@ Changed = true; } - assert(isStackEmpty() && "Stack not empty at end of basic block?"); + finishBlockStack(); + return Changed; } +/// setupBlockStack - Use the BlockBundle map to set up our model of the stack +/// to match predecessors' live out stack. +void FPS::setupBlockStack() { + DEBUG(dbgs() << "\nSetting up live-ins for BB#" << MBB->getNumber() + << " derived from " << MBB->getName() << ".\n"); + StackTop = 0; + const LiveBundle &Bundle = LiveBundles[BlockBundle.lookup(MBB).first]; + + if (!Bundle.Mask) { + DEBUG(dbgs() << "Block has no FP live-ins.\n"); + return; + } + + // Depth-first iteration should ensure that we always have an assigned stack. + assert(Bundle.isFixed() && "Reached block before any predecessors"); + + // Push the fixed live-in registers. + for (unsigned i = Bundle.FixCount; i > 0; --i) { + MBB->addLiveIn(X86::ST0+i-1); + DEBUG(dbgs() << "Live-in st(" << (i-1) << "): %FP" + << unsigned(Bundle.FixStack[i-1]) << '\n'); + pushReg(Bundle.FixStack[i-1]); + } + + // Kill off unwanted live-ins. This can happen with a critical edge. + // FIXME: We could keep these live registers around as zombies. They may need + // to be revived at the end of a short block. It might save a few instrs. + adjustLiveRegs(calcLiveInMask(MBB), MBB->begin()); + DEBUG(MBB->dump()); +} + +/// finishBlockStack - Revive live-outs that are implicitly defined out of +/// MBB. Shuffle live registers to match the expected fixed stack of any +/// predecessors, and ensure that all predecessors are expecting the same +/// stack. +void FPS::finishBlockStack() { + // The RET handling below takes care of return blocks for us. + if (MBB->succ_empty()) + return; + + DEBUG(dbgs() << "Setting up live-outs for BB#" << MBB->getNumber() + << " derived from " << MBB->getName() << ".\n"); + + unsigned BundleIdx = BlockBundle.lookup(MBB).second; + LiveBundle &Bundle = LiveBundles[BundleIdx]; + + // We may need to kill and define some registers to match successors. + // FIXME: This can probably be combined with the shuffle below. + MachineBasicBlock::iterator Term = MBB->getFirstTerminator(); + adjustLiveRegs(Bundle.Mask, Term); + + if (!Bundle.Mask) { + DEBUG(dbgs() << "No live-outs.\n"); + return; + } + + // Has the stack order been fixed yet? + DEBUG(dbgs() << "LB#" << BundleIdx << ": "); + if (Bundle.isFixed()) { + DEBUG(dbgs() << "Shuffling stack to match.\n"); + shuffleStackTop(Bundle.FixStack, Bundle.FixCount, Term); + } else { + // Not fixed yet, we get to choose. + DEBUG(dbgs() << "Fixing stack order now.\n"); + Bundle.FixCount = StackTop; + for (unsigned i = 0; i < StackTop; ++i) + Bundle.FixStack[i] = getStackEntry(i); + } +} + + //===----------------------------------------------------------------------===// // Efficient Lookup Table Support //===----------------------------------------------------------------------===// @@ -597,6 +843,13 @@ // Otherwise, store the top of stack into the dead slot, killing the operand // without having to add in an explicit xchg then pop. // + I = freeStackSlotBefore(++I, FPRegNo); +} + +/// freeStackSlotBefore - Free the specified register without trying any +/// folding. +MachineBasicBlock::iterator +FPS::freeStackSlotBefore(MachineBasicBlock::iterator I, unsigned FPRegNo) { unsigned STReg = getSTReg(FPRegNo); unsigned OldSlot = getSlot(FPRegNo); unsigned TopReg = Stack[StackTop-1]; @@ -604,9 +857,90 @@ RegMap[TopReg] = OldSlot; RegMap[FPRegNo] = ~0; Stack[--StackTop] = ~0; - MachineInstr *MI = I; - DebugLoc dl = MI->getDebugLoc(); - I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(STReg); + return BuildMI(*MBB, I, DebugLoc(), TII->get(X86::ST_FPrr)).addReg(STReg); +} + +/// adjustLiveRegs - Kill and revive registers such that exactly the FP +/// registers with a bit in Mask are live. +void FPS::adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I) { + unsigned Defs = Mask; + unsigned Kills = 0; + for (unsigned i = 0; i < StackTop; ++i) { + unsigned RegNo = Stack[i]; + if (!(Defs & (1 << RegNo))) + // This register is live, but we don't want it. + Kills |= (1 << RegNo); + else + // We don't need to imp-def this live register. + Defs &= ~(1 << RegNo); + } + assert((Kills & Defs) == 0 && "Register needs killing and def'ing?"); + + // Produce implicit-defs for free by using killed registers. + while (Kills && Defs) { + unsigned KReg = CountTrailingZeros_32(Kills); + unsigned DReg = CountTrailingZeros_32(Defs); + DEBUG(dbgs() << "Renaming %FP" << KReg << " as imp %FP" << DReg << "\n"); + std::swap(Stack[getSlot(KReg)], Stack[getSlot(DReg)]); + std::swap(RegMap[KReg], RegMap[DReg]); + Kills &= ~(1 << KReg); + Defs &= ~(1 << DReg); + } + + // Kill registers by popping. + if (Kills && I != MBB->begin()) { + MachineBasicBlock::iterator I2 = llvm::prior(I); + for (;;) { + unsigned KReg = getStackEntry(0); + if (!(Kills & (1 << KReg))) + break; + DEBUG(dbgs() << "Popping %FP" << KReg << "\n"); + popStackAfter(I2); + Kills &= ~(1 << KReg); + } + } + + // Manually kill the rest. + while (Kills) { + unsigned KReg = CountTrailingZeros_32(Kills); + DEBUG(dbgs() << "Killing %FP" << KReg << "\n"); + freeStackSlotBefore(I, KReg); + Kills &= ~(1 << KReg); + } + + // Load zeros for all the imp-defs. + while(Defs) { + unsigned DReg = CountTrailingZeros_32(Defs); + DEBUG(dbgs() << "Defining %FP" << DReg << " as 0\n"); + BuildMI(*MBB, I, DebugLoc(), TII->get(X86::LD_F0)); + pushReg(DReg); + Defs &= ~(1 << DReg); + } + + // Now we should have the correct registers live. + DEBUG(dumpStack()); + assert(StackTop == CountPopulation_32(Mask) && "Live count mismatch"); +} + +/// shuffleStackTop - emit fxch instructions before I to shuffle the top +/// FixCount entries into the order given by FixStack. +/// FIXME: Is there a better algorithm than insertion sort? +void FPS::shuffleStackTop(const unsigned char *FixStack, + unsigned FixCount, + MachineBasicBlock::iterator I) { + // Move items into place, starting from the desired stack bottom. + while (FixCount--) { + // Old register at position FixCount. + unsigned OldReg = getStackEntry(FixCount); + // Desired register at position FixCount. + unsigned Reg = FixStack[FixCount]; + if (Reg == OldReg) + continue; + // (Reg st0) (OldReg st0) = (Reg OldReg st0) + moveToTop(Reg, I); + moveToTop(OldReg, I); + } + DEBUG(dumpStack()); } @@ -1119,11 +1453,11 @@ case X86::RETI: // If RET has an FP register use operand, pass the first one in ST(0) and // the second one in ST(1). - if (isStackEmpty()) return; // Quick check to see if any are possible. - + // Find the register operands. unsigned FirstFPRegOp = ~0U, SecondFPRegOp = ~0U; - + unsigned LiveMask = 0; + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &Op = MI->getOperand(i); if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6) @@ -1142,12 +1476,18 @@ assert(SecondFPRegOp == ~0U && "More than two fp operands!"); SecondFPRegOp = getFPReg(Op); } + LiveMask |= (1 << getFPReg(Op)); // Remove the operand so that later passes don't see it. MI->RemoveOperand(i); --i, --e; } - + + // We may have been carrying spurious live-ins, so make sure only the returned + // registers are left live. + adjustLiveRegs(LiveMask, MI); + if (!LiveMask) return; // Quick check to see if any are possible. + // There are only four possibilities here: // 1) we are returning a single FP value. In this case, it has to be in // ST(0) already, so just declare success by removing the value from the @@ -1197,7 +1537,14 @@ } I = MBB->erase(I); // Remove the pseudo instruction - --I; + + // We want to leave I pointing to the previous instruction, but what if we + // just erased the first instruction? + if (I == MBB->begin()) { + DEBUG(dbgs() << "Inserting dummy KILL\n"); + I = BuildMI(*MBB, I, DebugLoc(), TII->get(TargetOpcode::KILL)); + } else + --I; } // Translate a COPY instruction to a pseudo-op that handleSpecialFP understands. Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=108529&r1=108528&r2=108529&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original) +++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Fri Jul 16 11:38:12 2010 @@ -19,11 +19,15 @@ #include "llvm/CodeGen/Passes.h" #include "llvm/MC/MCCodeEmitter.h" #include "llvm/MC/MCStreamer.h" +#include "llvm/Support/CommandLine.h" #include "llvm/Support/FormattedStream.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetRegistry.h" using namespace llvm; +static cl::opt +LiveX87("live-x87", cl::desc("Allow live X87 registers across blocks")); + static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) { Triple TheTriple(TT); switch (TheTriple.getOS()) { @@ -183,7 +187,8 @@ bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel) { // Install a pass to insert x87 FP_REG_KILL instructions, as needed. - PM.add(createX87FPRegKillInserterPass()); + if (!LiveX87) + PM.add(createX87FPRegKillInserterPass()); PM.add(createX86MaxStackAlignmentHeuristicPass()); return false; // -print-machineinstr shouldn't print after this. From resistor at mac.com Fri Jul 16 11:39:00 2010 From: resistor at mac.com (Owen Anderson) Date: Fri, 16 Jul 2010 16:39:00 -0000 Subject: [llvm-commits] [llvm] r108530 - /llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp Message-ID: <20100716163900.D2A6E2A6C12C@llvm.org> Author: resistor Date: Fri Jul 16 11:39:00 2010 New Revision: 108530 URL: http://llvm.org/viewvc/llvm-project?rev=108530&view=rev Log: Remove the rest of my instcombine changes. Back to the drawing board on this one. Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp?rev=108530&r1=108529&r2=108530&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp Fri Jul 16 11:39:00 2010 @@ -699,34 +699,6 @@ SI.setOperand(2, TrueVal); return &SI; } - - // select (A == 0 | B == 0), T, F--> select (A != 0 & B != 0), F, T - // Note: This is a canonicalization rather than an optimization, and is used - // to expose opportunities to other instcombine transforms. - Instruction* CondInst = dyn_cast(CondVal); - if (CondInst && CondInst->hasOneUse() && - CondInst->getOpcode() == Instruction::Or) { - ICmpInst *LHSCmp = dyn_cast(CondInst->getOperand(0)); - ICmpInst *RHSCmp = dyn_cast(CondInst->getOperand(1)); - if (LHSCmp && LHSCmp->hasOneUse() && - LHSCmp->getPredicate() == ICmpInst::ICMP_EQ && - RHSCmp && RHSCmp->hasOneUse() && - RHSCmp->getPredicate() == ICmpInst::ICMP_EQ) { - ConstantInt* C1 = dyn_cast(LHSCmp->getOperand(1)); - ConstantInt* C2 = dyn_cast(RHSCmp->getOperand(1)); - if (C1 && C1->isZero() && C2 && C2->isZero()) { - LHSCmp->setPredicate(ICmpInst::ICMP_NE); - RHSCmp->setPredicate(ICmpInst::ICMP_NE); - Value *And = - InsertNewInstBefore(BinaryOperator::CreateAnd(LHSCmp, RHSCmp, - "and."+CondVal->getName()), SI); - SI.setOperand(0, And); - SI.setOperand(1, FalseVal); - SI.setOperand(2, TrueVal); - return &SI; - } - } - } return 0; } From stoklund at 2pi.dk Fri Jul 16 12:41:40 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Fri, 16 Jul 2010 17:41:40 -0000 Subject: [llvm-commits] [llvm] r108535 - /llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp Message-ID: <20100716174140.896302A6C12C@llvm.org> Author: stoklund Date: Fri Jul 16 12:41:40 2010 New Revision: 108535 URL: http://llvm.org/viewvc/llvm-project?rev=108535&view=rev Log: Search for a free FP register instead of just assuming FP7 is not in use. Modified: llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp Modified: llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp?rev=108535&r1=108534&r2=108535&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp Fri Jul 16 12:41:40 2010 @@ -157,6 +157,14 @@ return Slot < StackTop && Stack[Slot] == RegNo; } + // getScratchReg - Return an FP register that is not currently in use. + unsigned getScratchReg() { + for (int i = 7; i >= 0; --i) + if (!isLive(i)) + return i; + llvm_unreachable("Ran out of scratch FP registers"); + } + // getStackEntry - Return the X86::FP register in register ST(i). unsigned getStackEntry(unsigned STi) const { assert(STi < StackTop && "Access past stack top!"); @@ -994,7 +1002,7 @@ MI->getOpcode() == X86::ISTT_Fp32m80 || MI->getOpcode() == X86::ISTT_Fp64m80 || MI->getOpcode() == X86::ST_FpP80m)) { - duplicateToTop(Reg, 7 /*temp register*/, I); + duplicateToTop(Reg, getScratchReg(), I); } else { moveToTop(Reg, I); // Move to the top of the stack... } @@ -1347,8 +1355,7 @@ if (!MI->killsRegister(X86::FP0 + Op0)) { // Duplicate Op0 into a temporary on the stack top. - // This actually assumes that FP7 is dead. - duplicateToTop(Op0, 7, I); + duplicateToTop(Op0, getScratchReg(), I); } else { // Op0 is killed, so just swap it into position. moveToTop(Op0, I); @@ -1368,8 +1375,7 @@ ++StackTop; unsigned RegOnTop = getStackEntry(0); // This reg must remain in st(0). if (!MI->killsRegister(X86::FP0 + Op0)) { - // Assume FP6 is not live, use it as a scratch register. - duplicateToTop(Op0, 6, I); + duplicateToTop(Op0, getScratchReg(), I); moveToTop(RegOnTop, I); } else if (getSTReg(Op0) != X86::ST1) { // We have the wrong value at st(1). Shuffle! Untested! @@ -1513,7 +1519,7 @@ // Duplicate the TOS so that we return it twice. Just pick some other FPx // register to hold it. - unsigned NewReg = (FirstFPRegOp+1)%7; + unsigned NewReg = getScratchReg(); duplicateToTop(FirstFPRegOp, NewReg, MI); FirstFPRegOp = NewReg; } From stoklund at 2pi.dk Fri Jul 16 12:41:44 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Fri, 16 Jul 2010 17:41:44 -0000 Subject: [llvm-commits] [llvm] r108536 - in /llvm/trunk: lib/Target/X86/CMakeLists.txt lib/Target/X86/X86.h lib/Target/X86/X86CodeEmitter.cpp lib/Target/X86/X86FloatingPointRegKill.cpp lib/Target/X86/X86InstrFPStack.td lib/Target/X86/X86InstrInfo.cpp lib/Target/X86/X86TargetMachine.cpp test/CodeGen/X86/2007-06-14-branchfold.ll Message-ID: <20100716174144.AD5F12A6C12D@llvm.org> Author: stoklund Date: Fri Jul 16 12:41:44 2010 New Revision: 108536 URL: http://llvm.org/viewvc/llvm-project?rev=108536&view=rev Log: Remove the X86::FP_REG_KILL pseudo-instruction and the X86FloatingPointRegKill pass that inserted it. It is no longer necessary to limit the live ranges of FP registers to a single basic block. Removed: llvm/trunk/lib/Target/X86/X86FloatingPointRegKill.cpp llvm/trunk/test/CodeGen/X86/2007-06-14-branchfold.ll Modified: llvm/trunk/lib/Target/X86/CMakeLists.txt llvm/trunk/lib/Target/X86/X86.h llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp llvm/trunk/lib/Target/X86/X86InstrFPStack.td llvm/trunk/lib/Target/X86/X86InstrInfo.cpp llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Modified: llvm/trunk/lib/Target/X86/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/CMakeLists.txt?rev=108536&r1=108535&r2=108536&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/X86/CMakeLists.txt Fri Jul 16 12:41:44 2010 @@ -22,7 +22,6 @@ X86COFFMachineModuleInfo.cpp X86ELFWriterInfo.cpp X86FloatingPoint.cpp - X86FloatingPointRegKill.cpp X86ISelDAGToDAG.cpp X86ISelLowering.cpp X86InstrInfo.cpp Modified: llvm/trunk/lib/Target/X86/X86.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.h?rev=108536&r1=108535&r2=108536&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86.h (original) +++ llvm/trunk/lib/Target/X86/X86.h Fri Jul 16 12:41:44 2010 @@ -49,11 +49,6 @@ /// crossings. FunctionPass *createSSEDomainFixPass(); -/// createX87FPRegKillInserterPass - This function returns a pass which -/// inserts FP_REG_KILL instructions where needed. -/// -FunctionPass *createX87FPRegKillInserterPass(); - /// createX86CodeEmitterPass - Return a pass that emits the collected X86 code /// to the specified MCE object. FunctionPass *createX86JITCodeEmitterPass(X86TargetMachine &TM, Modified: llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp?rev=108536&r1=108535&r2=108536&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp Fri Jul 16 12:41:44 2010 @@ -622,7 +622,6 @@ case TargetOpcode::IMPLICIT_DEF: case TargetOpcode::KILL: - case X86::FP_REG_KILL: break; case X86::MOVPC32r: { // This emits the "call" portion of this pseudo instruction. Removed: llvm/trunk/lib/Target/X86/X86FloatingPointRegKill.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FloatingPointRegKill.cpp?rev=108535&view=auto ============================================================================== --- llvm/trunk/lib/Target/X86/X86FloatingPointRegKill.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FloatingPointRegKill.cpp (removed) @@ -1,153 +0,0 @@ -//===-- X86FloatingPoint.cpp - FP_REG_KILL inserter -----------------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file defines the pass which inserts FP_REG_KILL instructions. -// -//===----------------------------------------------------------------------===// - -#define DEBUG_TYPE "x86-codegen" -#include "X86.h" -#include "X86InstrInfo.h" -#include "llvm/Instructions.h" -#include "llvm/CodeGen/MachineFunctionPass.h" -#include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/CodeGen/Passes.h" -#include "llvm/Target/TargetMachine.h" -#include "llvm/Support/Debug.h" -#include "llvm/Support/CFG.h" -#include "llvm/ADT/Statistic.h" -using namespace llvm; - -STATISTIC(NumFPKill, "Number of FP_REG_KILL instructions added"); - -namespace { - struct FPRegKiller : public MachineFunctionPass { - static char ID; - FPRegKiller() : MachineFunctionPass(&ID) {} - - virtual void getAnalysisUsage(AnalysisUsage &AU) const { - AU.setPreservesCFG(); - AU.addPreservedID(MachineLoopInfoID); - AU.addPreservedID(MachineDominatorsID); - MachineFunctionPass::getAnalysisUsage(AU); - } - - virtual bool runOnMachineFunction(MachineFunction &MF); - - virtual const char *getPassName() const { - return "X86 FP_REG_KILL inserter"; - } - }; - char FPRegKiller::ID = 0; -} - -FunctionPass *llvm::createX87FPRegKillInserterPass() { - return new FPRegKiller(); -} - -/// isFPStackVReg - Return true if the specified vreg is from a fp stack -/// register class. -static bool isFPStackVReg(unsigned RegNo, const MachineRegisterInfo &MRI) { - if (!TargetRegisterInfo::isVirtualRegister(RegNo)) - return false; - - switch (MRI.getRegClass(RegNo)->getID()) { - default: return false; - case X86::RFP32RegClassID: - case X86::RFP64RegClassID: - case X86::RFP80RegClassID: - return true; - } -} - - -/// ContainsFPStackCode - Return true if the specific MBB has floating point -/// stack code, and thus needs an FP_REG_KILL. -static bool ContainsFPStackCode(MachineBasicBlock *MBB, - const MachineRegisterInfo &MRI) { - // Scan the block, looking for instructions that define or use fp stack vregs. - for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); - I != E; ++I) { - for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op) { - if (!I->getOperand(op).isReg()) - continue; - if (unsigned Reg = I->getOperand(op).getReg()) - if (isFPStackVReg(Reg, MRI)) - return true; - } - } - - // Check PHI nodes in successor blocks. These PHI's will be lowered to have - // a copy of the input value in this block, which is a definition of the - // value. - for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), - E = MBB->succ_end(); SI != E; ++ SI) { - MachineBasicBlock *SuccBB = *SI; - for (MachineBasicBlock::iterator I = SuccBB->begin(), E = SuccBB->end(); - I != E; ++I) { - // All PHI nodes are at the top of the block. - if (!I->isPHI()) break; - - if (isFPStackVReg(I->getOperand(0).getReg(), MRI)) - return true; - } - } - - return false; -} - -bool FPRegKiller::runOnMachineFunction(MachineFunction &MF) { - // If we are emitting FP stack code, scan the basic block to determine if this - // block defines or uses any FP values. If so, put an FP_REG_KILL instruction - // before the terminator of the block. - - // Note that FP stack instructions are used in all modes for long double, - // so we always need to do this check. - // Also note that it's possible for an FP stack register to be live across - // an instruction that produces multiple basic blocks (SSE CMOV) so we - // must check all the generated basic blocks. - - // Scan all of the machine instructions in these MBBs, checking for FP - // stores. (RFP32 and RFP64 will not exist in SSE mode, but RFP80 might.) - - // Fast-path: If nothing is using the x87 registers, we don't need to do - // any scanning. - const MachineRegisterInfo &MRI = MF.getRegInfo(); - if (MRI.getRegClassVirtRegs(X86::RFP80RegisterClass).empty() && - MRI.getRegClassVirtRegs(X86::RFP64RegisterClass).empty() && - MRI.getRegClassVirtRegs(X86::RFP32RegisterClass).empty()) - return false; - - bool Changed = false; - MachineFunction::iterator MBBI = MF.begin(); - MachineFunction::iterator EndMBB = MF.end(); - for (; MBBI != EndMBB; ++MBBI) { - MachineBasicBlock *MBB = MBBI; - - // If this block returns, ignore it. We don't want to insert an FP_REG_KILL - // before the return. - if (!MBB->empty()) { - MachineBasicBlock::iterator EndI = MBB->end(); - --EndI; - if (EndI->getDesc().isReturn()) - continue; - } - - // If we find any FP stack code, emit the FP_REG_KILL instruction. - if (ContainsFPStackCode(MBB, MRI)) { - BuildMI(*MBB, MBBI->getFirstTerminator(), DebugLoc(), - MF.getTarget().getInstrInfo()->get(X86::FP_REG_KILL)); - ++NumFPKill; - Changed = true; - } - } - - return Changed; -} Modified: llvm/trunk/lib/Target/X86/X86InstrFPStack.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFPStack.td?rev=108536&r1=108535&r2=108536&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrFPStack.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrFPStack.td Fri Jul 16 12:41:44 2010 @@ -108,10 +108,6 @@ [(X86fp_to_i64mem RFP80:$src, addr:$dst)]>; } -let isTerminator = 1 in - let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in - def FP_REG_KILL : I<0, Pseudo, (outs), (ins), "##FP_REG_KILL", []>; - // All FP Stack operations are represented with four instructions here. The // first three instructions, generated by the instruction selector, use "RFP32" // "RFP64" or "RFP80" registers: traditional register files to reference 32-bit, Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=108536&r1=108535&r2=108536&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Fri Jul 16 12:41:44 2010 @@ -1664,14 +1664,6 @@ return !isPredicated(MI); } -// For purposes of branch analysis do not count FP_REG_KILL as a terminator. -static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI, - const X86InstrInfo &TII) { - if (MI->getOpcode() == X86::FP_REG_KILL) - return false; - return TII.isUnpredicatedTerminator(MI); -} - bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, @@ -1688,7 +1680,7 @@ // Working from the bottom, when we see a non-terminator instruction, we're // done. - if (!isBrAnalysisUnpredicatedTerminator(I, *this)) + if (!isUnpredicatedTerminator(I)) break; // A terminator that isn't a branch can't easily be handled by this @@ -3341,7 +3333,6 @@ break; case TargetOpcode::IMPLICIT_DEF: case TargetOpcode::KILL: - case X86::FP_REG_KILL: break; case X86::MOVPC32r: { // This emits the "call" portion of this pseudo instruction. Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=108536&r1=108535&r2=108536&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original) +++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Fri Jul 16 12:41:44 2010 @@ -19,15 +19,11 @@ #include "llvm/CodeGen/Passes.h" #include "llvm/MC/MCCodeEmitter.h" #include "llvm/MC/MCStreamer.h" -#include "llvm/Support/CommandLine.h" #include "llvm/Support/FormattedStream.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetRegistry.h" using namespace llvm; -static cl::opt -LiveX87("live-x87", cl::desc("Allow live X87 registers across blocks")); - static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) { Triple TheTriple(TT); switch (TheTriple.getOS()) { @@ -186,10 +182,6 @@ bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel) { - // Install a pass to insert x87 FP_REG_KILL instructions, as needed. - if (!LiveX87) - PM.add(createX87FPRegKillInserterPass()); - PM.add(createX86MaxStackAlignmentHeuristicPass()); return false; // -print-machineinstr shouldn't print after this. } Removed: llvm/trunk/test/CodeGen/X86/2007-06-14-branchfold.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2007-06-14-branchfold.ll?rev=108535&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2007-06-14-branchfold.ll (original) +++ llvm/trunk/test/CodeGen/X86/2007-06-14-branchfold.ll (removed) @@ -1,133 +0,0 @@ -; RUN: llc < %s -march=x86 -mcpu=i686 | not grep jmp -; check that branch folding understands FP_REG_KILL is not a branch - -target triple = "i686-pc-linux-gnu" - %struct.FRAME.c34003a = type { float, float } - at report_E = global i8 0 ; [#uses=0] - -define void @main() { -entry: - %FRAME.31 = alloca %struct.FRAME.c34003a, align 8 ; <%struct.FRAME.c34003a*> [#uses=4] - %tmp20 = call i32 @report__ident_int( i32 -50 ) ; [#uses=1] - %tmp2021 = sitofp i32 %tmp20 to float ; [#uses=5] - %tmp23 = fcmp ult float %tmp2021, 0xC7EFFFFFE0000000 ; [#uses=1] - %tmp26 = fcmp ugt float %tmp2021, 0x47EFFFFFE0000000 ; [#uses=1] - %bothcond = or i1 %tmp23, %tmp26 ; [#uses=1] - br i1 %bothcond, label %bb, label %bb30 - -bb: ; preds = %entry - unwind - -bb30: ; preds = %entry - %tmp35 = call i32 @report__ident_int( i32 50 ) ; [#uses=1] - %tmp3536 = sitofp i32 %tmp35 to float ; [#uses=4] - %tmp38 = fcmp ult float %tmp3536, 0xC7EFFFFFE0000000 ; [#uses=1] - %tmp44 = fcmp ugt float %tmp3536, 0x47EFFFFFE0000000 ; [#uses=1] - %bothcond226 = or i1 %tmp38, %tmp44 ; [#uses=1] - br i1 %bothcond226, label %bb47, label %bb49 - -bb47: ; preds = %bb30 - unwind - -bb49: ; preds = %bb30 - %tmp60 = fcmp ult float %tmp3536, %tmp2021 ; [#uses=1] - %tmp60.not = xor i1 %tmp60, true ; [#uses=1] - %tmp65 = fcmp olt float %tmp2021, 0xC7EFFFFFE0000000 ; [#uses=1] - %bothcond227 = and i1 %tmp65, %tmp60.not ; [#uses=1] - br i1 %bothcond227, label %cond_true68, label %cond_next70 - -cond_true68: ; preds = %bb49 - unwind - -cond_next70: ; preds = %bb49 - %tmp71 = call i32 @report__ident_int( i32 -30 ) ; [#uses=1] - %tmp7172 = sitofp i32 %tmp71 to float ; [#uses=3] - %tmp74 = fcmp ult float %tmp7172, 0xC7EFFFFFE0000000 ; [#uses=1] - %tmp80 = fcmp ugt float %tmp7172, 0x47EFFFFFE0000000 ; [#uses=1] - %bothcond228 = or i1 %tmp74, %tmp80 ; [#uses=1] - br i1 %bothcond228, label %bb83, label %bb85 - -bb83: ; preds = %cond_next70 - unwind - -bb85: ; preds = %cond_next70 - %tmp90 = getelementptr %struct.FRAME.c34003a* %FRAME.31, i32 0, i32 1 ; [#uses=3] - store float %tmp7172, float* %tmp90 - %tmp92 = call i32 @report__ident_int( i32 30 ) ; [#uses=1] - %tmp9293 = sitofp i32 %tmp92 to float ; [#uses=7] - %tmp95 = fcmp ult float %tmp9293, 0xC7EFFFFFE0000000 ; [#uses=1] - %tmp101 = fcmp ugt float %tmp9293, 0x47EFFFFFE0000000 ; [#uses=1] - %bothcond229 = or i1 %tmp95, %tmp101 ; [#uses=1] - br i1 %bothcond229, label %bb104, label %bb106 - -bb104: ; preds = %bb85 - unwind - -bb106: ; preds = %bb85 - %tmp111 = getelementptr %struct.FRAME.c34003a* %FRAME.31, i32 0, i32 0 ; [#uses=2] - store float %tmp9293, float* %tmp111 - %tmp123 = load float* %tmp90 ; [#uses=4] - %tmp125 = fcmp ult float %tmp9293, %tmp123 ; [#uses=1] - br i1 %tmp125, label %cond_next147, label %cond_true128 - -cond_true128: ; preds = %bb106 - %tmp133 = fcmp olt float %tmp123, %tmp2021 ; [#uses=1] - %tmp142 = fcmp ogt float %tmp9293, %tmp3536 ; [#uses=1] - %bothcond230 = or i1 %tmp133, %tmp142 ; [#uses=1] - br i1 %bothcond230, label %bb145, label %cond_next147 - -bb145: ; preds = %cond_true128 - unwind - -cond_next147: ; preds = %cond_true128, %bb106 - %tmp157 = fcmp ugt float %tmp123, -3.000000e+01 ; [#uses=1] - %tmp165 = fcmp ult float %tmp9293, -3.000000e+01 ; [#uses=1] - %bothcond231 = or i1 %tmp157, %tmp165 ; [#uses=1] - br i1 %bothcond231, label %bb168, label %bb169 - -bb168: ; preds = %cond_next147 - unwind - -bb169: ; preds = %cond_next147 - %tmp176 = fcmp ugt float %tmp123, 3.000000e+01 ; [#uses=1] - %tmp184 = fcmp ult float %tmp9293, 3.000000e+01 ; [#uses=1] - %bothcond232 = or i1 %tmp176, %tmp184 ; [#uses=1] - br i1 %bothcond232, label %bb187, label %bb188 - -bb187: ; preds = %bb169 - unwind - -bb188: ; preds = %bb169 - %tmp192 = call fastcc float @c34003a__ident.154( %struct.FRAME.c34003a* %FRAME.31, float 3.000000e+01 ) ; [#uses=2] - %tmp194 = load float* %tmp90 ; [#uses=1] - %tmp196 = fcmp ugt float %tmp194, 0.000000e+00 ; [#uses=1] - br i1 %tmp196, label %bb207, label %cond_next200 - -cond_next200: ; preds = %bb188 - %tmp202 = load float* %tmp111 ; [#uses=1] - %tmp204 = fcmp ult float %tmp202, 0.000000e+00 ; [#uses=1] - br i1 %tmp204, label %bb207, label %bb208 - -bb207: ; preds = %cond_next200, %bb188 - unwind - -bb208: ; preds = %cond_next200 - %tmp212 = call fastcc float @c34003a__ident.154( %struct.FRAME.c34003a* %FRAME.31, float 0.000000e+00 ) ; [#uses=1] - %tmp214 = fcmp oge float %tmp212, %tmp192 ; [#uses=1] - %tmp217 = fcmp oge float %tmp192, 1.000000e+02 ; [#uses=1] - %tmp221 = or i1 %tmp214, %tmp217 ; [#uses=1] - br i1 %tmp221, label %cond_true224, label %UnifiedReturnBlock - -cond_true224: ; preds = %bb208 - call void @abort( ) noreturn - ret void - -UnifiedReturnBlock: ; preds = %bb208 - ret void -} - -declare fastcc float @c34003a__ident.154(%struct.FRAME.c34003a* %CHAIN.32, float %x) - -declare i32 @report__ident_int(i32 %x) - -declare void @abort() noreturn From Micah.Villmow at amd.com Fri Jul 16 12:44:27 2010 From: Micah.Villmow at amd.com (Villmow, Micah) Date: Fri, 16 Jul 2010 12:44:27 -0500 Subject: [llvm-commits] Windows compilation warnings In-Reply-To: <4C4041DB.7030800@andric.com> References: <4C3F9455.5010106@andric.com> <4C4041DB.7030800@andric.com> Message-ID: > -----Original Message----- > From: Dimitry Andric [mailto:dimitry at andric.com] > Sent: Friday, July 16, 2010 4:26 AM > To: Villmow, Micah > Cc: llvm-commits > Subject: Re: [llvm-commits] Windows compilation warnings > > On 2010-07-16 04:00, Villmow, Micah wrote: > > This patch set makes Windows build cleanly for 32bit binaries from a > > 64bit machine. > > Hmm, I regularly build 32-bit binaries on my 64-bit Windows machine, > but I never get many warnings about truncations, except the recently > introduced ones about enums being truncated. It is only when I build > the x64 project that I get a lot of those warnings. > > Are you compiling with non-standard settings? E.g. -Wp64 (which I > remember is deprecated) or -W4, the maximum warning setting? > [Villmow, Micah] Here are the options we are compiling with. -TC /Z7 /Od /Ob1 /W0 /GR /MTd /Zc:forScope /Zc:wchar_t /wd4996 /favor:blend /TP /arch:SSE2 /D__SSE__ /D__SSE2__ /GS- /fp:except- -c -DWIN32 -D_CRT_NONSTDC_NO_WARNINGS -D_CRT_SECURE_NO_DEPRECATE -D_CRT_SECURE_NO_WARNINGS -D_LIB -D_SCL_SECURE_NO_WARNINGS -D__STDC_CONSTANT_MACROS -D__STDC_LIMIT_MACROS Not sure if there are anything outrageous here. > > > Some thoughts about what I saw while doing this. > > > > size_t is not used in places where it should be, return value of > > size(), input value of resize(). > > Actually, in most cases, the class's "size_type", "difference_type" and > so on should be used. AFAIK there is no guarantee these are always > equivalent to size_t (although they usually are in practice). > > But indeed, the cases where size_types are stuffed into plain ints or > unsigneds are many, although it may not be that easy to just change > whatever variable holds them to size_type. For example, you may need > to > change function declarations to effectively do that, and such changes > tend to "cascade" through a lot of the source. > > > > getZExtValue()/getSExtValue() need 32bit explicit versions, this > > would remove probably 60% of truncation casts. > > But you would still need to go over *all* the invocations, to replace > them... and be extremely careful not to break anything by those > replacements. > [Villmow, Micah] Yeah, this patch isn't completely valid, some overnight internal testing we had broke, so I'm going to break it out into a sequence of smaller patches for each component. To very each one. > > > uint64_t is overused in places where uint32_t is sufficient. > > There may be reasons for those uses, but the only ones that can explain > are the authors of the code in question. :) > > > > unsigned/signed is used where uint32_t/int32_t should be used. > > > > Should there be something the developers notes about these? I think > > it is better to explicitly specify the integer size instead on > > relying on the compiler to pick the size. > > I am not sure if hardcoding the number of bits in the type is always > the > best solution in all cases. This really depends on the specific piece > of code. > > Most of the times you just want to use plain int or unsigned, because > that will always be the machine's default word. You only have to pay > attention when mixing those with "size" types, such as object lengths > and pointer differences. [Villmow, Micah] Any idea on how I should approach this? I do want to make llvm clean so we can turn on fail on warning internally for our whole build system on windows. Now that I've gone over all of them, it does give me an idea on how to fix them, but outside feedback would be appreciated. I think I'm going to focus on Tablegen for now, and worry about llvm proper later. Micah From gohman at apple.com Fri Jul 16 12:54:27 2010 From: gohman at apple.com (Dan Gohman) Date: Fri, 16 Jul 2010 17:54:27 -0000 Subject: [llvm-commits] [llvm] r108538 - in /llvm/trunk: include/llvm/CodeGen/MachineModuleInfo.h lib/CodeGen/MachineModuleInfo.cpp lib/CodeGen/SelectionDAG/FastISel.cpp lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Message-ID: <20100716175427.7AFA62A6C12C@llvm.org> Author: djg Date: Fri Jul 16 12:54:27 2010 New Revision: 108538 URL: http://llvm.org/viewvc/llvm-project?rev=108538&view=rev Log: Revert r108369, sorting llvm.dbg.declare information by source position, since it doesn't work for front-ends which don't emit column information (which includes llvm-gcc in its present configuration), and doesn't work for clang for K&R style variables where the variables are declared in a different order from the parameter list. Instead, make a separate pass through the instructions to collect the llvm.dbg.declare instructions in order. This ensures that the debug information for variables is emitted in this order. Modified: llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Modified: llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h?rev=108538&r1=108537&r2=108538&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineModuleInfo.h Fri Jul 16 12:54:27 2010 @@ -344,7 +344,7 @@ VariableDbgInfo.push_back(std::make_pair(N, std::make_pair(Slot, Loc))); } - VariableDbgInfoMapTy &getVariableDbgInfo(); + VariableDbgInfoMapTy &getVariableDbgInfo() { return VariableDbgInfo; } }; // End class MachineModuleInfo Modified: llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp?rev=108538&r1=108537&r2=108538&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp Fri Jul 16 12:54:27 2010 @@ -579,10 +579,3 @@ } }; } - -MachineModuleInfo::VariableDbgInfoMapTy & -MachineModuleInfo::getVariableDbgInfo() { - std::stable_sort(VariableDbgInfo.begin(), VariableDbgInfo.end(), - VariableDebugSorter()); - return VariableDbgInfo; -} Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=108538&r1=108537&r2=108538&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Fri Jul 16 12:54:27 2010 @@ -472,17 +472,7 @@ return true; const AllocaInst *AI = dyn_cast(Address); // Don't handle byval struct arguments or VLAs, for example. - // Note that if we have a byval struct argument, fast ISel is turned off; - // those are handled in SelectionDAGBuilder. - if (AI) { - DenseMap::iterator SI = - FuncInfo.StaticAllocaMap.find(AI); - if (SI == FuncInfo.StaticAllocaMap.end()) break; // VLAs. - int FI = SI->second; - if (!DI->getDebugLoc().isUnknown()) - FuncInfo.MF->getMMI().setVariableDbgInfo(DI->getVariable(), - FI, DI->getDebugLoc()); - } else + if (!AI) // Building the map above is target independent. Generating DBG_VALUE // inline is target dependent; do this now. (void)TargetSelectInstruction(cast(I)); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp?rev=108538&r1=108537&r2=108538&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp Fri Jul 16 12:54:27 2010 @@ -20,6 +20,7 @@ #include "llvm/IntrinsicInst.h" #include "llvm/LLVMContext.h" #include "llvm/Module.h" +#include "llvm/Analysis/DebugInfo.h" #include "llvm/CodeGen/Analysis.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFrameInfo.h" @@ -116,12 +117,43 @@ } for (; BB != EB; ++BB) - for (BasicBlock::const_iterator I = BB->begin(), E = BB->end(); I != E; ++I) + for (BasicBlock::const_iterator I = BB->begin(), E = BB->end(); I != E; ++I) { + // Mark values used outside their block as exported, by allocating + // a virtual register for them. if (isUsedOutsideOfDefiningBlock(I)) if (!isa(I) || !StaticAllocaMap.count(cast(I))) InitializeRegForValue(I); + // Collect llvm.dbg.declare information. This is done now instead of + // during the initial isel pass through the IR so that it is done + // in a predictable order. + if (const DbgDeclareInst *DI = dyn_cast(I)) { + MachineModuleInfo &MMI = MF->getMMI(); + if (MMI.hasDebugInfo() && + DIVariable(DI->getVariable()).Verify() && + !DI->getDebugLoc().isUnknown()) { + // Don't handle byval struct arguments or VLAs, for example. + // Non-byval arguments are handled here (they refer to the stack + // temporary alloca at this point). + const Value *Address = DI->getAddress(); + if (Address) { + if (const BitCastInst *BCI = dyn_cast(Address)) + Address = BCI->getOperand(0); + if (const AllocaInst *AI = dyn_cast(Address)) { + DenseMap::iterator SI = + StaticAllocaMap.find(AI); + if (SI != StaticAllocaMap.end()) { // Check for VLAs. + int FI = SI->second; + MMI.setVariableDbgInfo(DI->getVariable(), + FI, DI->getDebugLoc()); + } + } + } + } + } + } + // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This // also creates the initial PHI MachineInstrs, though none of the input // operands are populated. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=108538&r1=108537&r2=108538&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Fri Jul 16 12:54:27 2010 @@ -4009,20 +4009,6 @@ if (const BitCastInst *BCI = dyn_cast(Address)) Address = BCI->getOperand(0); const AllocaInst *AI = dyn_cast(Address); - if (AI) { - // Don't handle byval arguments or VLAs, for example. - // Non-byval arguments are handled here (they refer to the stack temporary - // alloca at this point). - DenseMap::iterator SI = - FuncInfo.StaticAllocaMap.find(AI); - if (SI == FuncInfo.StaticAllocaMap.end()) - return 0; // VLAs. - int FI = SI->second; - - MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); - if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo()) - MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc()); - } // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder // but do not always have a corresponding SDNode built. The SDNodeOrder From gohman at apple.com Fri Jul 16 12:58:45 2010 From: gohman at apple.com (Dan Gohman) Date: Fri, 16 Jul 2010 17:58:45 -0000 Subject: [llvm-commits] [llvm] r108539 - in /llvm/trunk/lib/Transforms: Scalar/LICM.cpp Scalar/LoopRotation.cpp Utils/LCSSA.cpp Utils/LoopSimplify.cpp Message-ID: <20100716175845.CBA882A6C12C@llvm.org> Author: djg Date: Fri Jul 16 12:58:45 2010 New Revision: 108539 URL: http://llvm.org/viewvc/llvm-project?rev=108539&view=rev Log: Reorder the contents of various getAnalysisUsage functions, eliminating a redundant loopsimplify run from the default -O2 sequence. Modified: llvm/trunk/lib/Transforms/Scalar/LICM.cpp llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp llvm/trunk/lib/Transforms/Utils/LCSSA.cpp llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LICM.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LICM.cpp?rev=108539&r1=108538&r2=108539&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LICM.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LICM.cpp Fri Jul 16 12:58:45 2010 @@ -75,10 +75,10 @@ /// virtual void getAnalysisUsage(AnalysisUsage &AU) const { AU.setPreservesCFG(); - AU.addRequiredID(LoopSimplifyID); - AU.addRequired(); AU.addRequired(); AU.addRequired(); // For scalar promotion (mem2reg) + AU.addRequired(); + AU.addRequiredID(LoopSimplifyID); AU.addRequired(); AU.addPreserved(); AU.addPreserved(); Modified: llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp?rev=108539&r1=108538&r2=108539&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp Fri Jul 16 12:58:45 2010 @@ -43,15 +43,15 @@ // LCSSA form makes instruction renaming easier. virtual void getAnalysisUsage(AnalysisUsage &AU) const { + AU.addPreserved(); + AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); AU.addRequiredID(LoopSimplifyID); AU.addPreservedID(LoopSimplifyID); AU.addRequiredID(LCSSAID); AU.addPreservedID(LCSSAID); AU.addPreserved(); - AU.addRequired(); - AU.addPreserved(); - AU.addPreserved(); - AU.addPreserved(); } // Helper functions Modified: llvm/trunk/lib/Transforms/Utils/LCSSA.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/LCSSA.cpp?rev=108539&r1=108538&r2=108539&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/LCSSA.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/LCSSA.cpp Fri Jul 16 12:58:45 2010 @@ -64,22 +64,18 @@ virtual void getAnalysisUsage(AnalysisUsage &AU) const { AU.setPreservesCFG(); + AU.addRequiredTransitive(); + AU.addPreserved(); + AU.addPreserved(); + AU.addRequiredTransitive(); + AU.addPreserved(); + // LCSSA doesn't actually require LoopSimplify, but the PassManager // doesn't know how to schedule LoopSimplify by itself. AU.addRequiredID(LoopSimplifyID); AU.addPreservedID(LoopSimplifyID); - AU.addRequiredTransitive(); - AU.addPreserved(); - AU.addRequiredTransitive(); - AU.addPreserved(); - AU.addPreserved(); - // Request DominanceFrontier now, even though LCSSA does - // not use it. This allows Pass Manager to schedule Dominance - // Frontier early enough such that one LPPassManager can handle - // multiple loop transformation passes. - AU.addRequired(); - AU.addPreserved(); + AU.addPreserved(); } private: bool ProcessInstruction(Instruction *Inst, Modified: llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp?rev=108539&r1=108538&r2=108539&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp Fri Jul 16 12:58:45 2010 @@ -77,12 +77,19 @@ virtual void getAnalysisUsage(AnalysisUsage &AU) const { // We need loop information to identify the loops... - AU.addRequiredTransitive(); AU.addRequiredTransitive(); - - AU.addPreserved(); AU.addPreserved(); + + // Request DominanceFrontier now, even though LoopSimplify does + // not use it. This allows Pass Manager to schedule Dominance + // Frontier early enough such that one LPPassManager can handle + // multiple loop transformation passes. + AU.addRequired(); AU.addPreserved(); + + AU.addRequiredTransitive(); + AU.addPreserved(); + AU.addPreserved(); AU.addPreserved(); AU.addPreservedID(BreakCriticalEdgesID); // No critical edges added. From stoklund at 2pi.dk Fri Jul 16 13:22:00 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Fri, 16 Jul 2010 18:22:00 -0000 Subject: [llvm-commits] [llvm] r108540 - /llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Message-ID: <20100716182200.5D9C02A6C12C@llvm.org> Author: stoklund Date: Fri Jul 16 13:22:00 2010 New Revision: 108540 URL: http://llvm.org/viewvc/llvm-project?rev=108540&view=rev Log: Teach PPCInstrInfo::storeRegToStackSlot and loadRegFromStackSlot to add memory operands. Hopefully this fixes the llvm-gcc-powerpc-darwin9 buildbot. It really shouldn't since missing memoperands should not affect correctness. Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=108540&r1=108539&r2=108540&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Fri Jul 16 13:22:00 2010 @@ -18,8 +18,11 @@ #include "PPCGenInstrInfo.inc" #include "PPCTargetMachine.h" #include "llvm/ADT/STLExtras.h" +#include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineMemOperand.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/PseudoSourceValue.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" @@ -524,6 +527,14 @@ for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) MBB.insert(MI, NewMIs[i]); + + const MachineFrameInfo &MFI = *MF.getFrameInfo(); + MachineMemOperand *MMO = + MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIdx), + MachineMemOperand::MOStore, /*Offset=*/0, + MFI.getObjectSize(FrameIdx), + MFI.getObjectAlignment(FrameIdx)); + NewMIs.back()->addMemOperand(MF, MMO); } void @@ -637,6 +648,14 @@ LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs); for (unsigned i = 0, e = NewMIs.size(); i != e; ++i) MBB.insert(MI, NewMIs[i]); + + const MachineFrameInfo &MFI = *MF.getFrameInfo(); + MachineMemOperand *MMO = + MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIdx), + MachineMemOperand::MOLoad, /*Offset=*/0, + MFI.getObjectSize(FrameIdx), + MFI.getObjectAlignment(FrameIdx)); + NewMIs.back()->addMemOperand(MF, MMO); } MachineInstr* From gohman at apple.com Fri Jul 16 13:28:07 2010 From: gohman at apple.com (Dan Gohman) Date: Fri, 16 Jul 2010 18:28:07 -0000 Subject: [llvm-commits] [llvm] r108543 - /llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp Message-ID: <20100716182808.04BEC2A6C12C@llvm.org> Author: djg Date: Fri Jul 16 13:28:07 2010 New Revision: 108543 URL: http://llvm.org/viewvc/llvm-project?rev=108543&view=rev Log: Make llvm-bcanalyzer print out the full enum name for all metadata code ids, not just some of them. Modified: llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp Modified: llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp?rev=108543&r1=108542&r2=108543&view=diff ============================================================================== --- llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp (original) +++ llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp Fri Jul 16 13:28:07 2010 @@ -259,11 +259,11 @@ case bitc::METADATA_BLOCK_ID: switch(CodeID) { default:return 0; - case bitc::METADATA_STRING: return "MDSTRING"; - case bitc::METADATA_NODE: return "MDNODE"; - case bitc::METADATA_FN_NODE: return "FN_MDNODE"; + case bitc::METADATA_STRING: return "METADATA_STRING"; + case bitc::METADATA_NODE: return "METADATA_NODE"; + case bitc::METADATA_FN_NODE: return "METADATA_FN_NODE"; case bitc::METADATA_NAME: return "METADATA_NAME"; - case bitc::METADATA_NAMED_NODE: return "NAMEDMDNODE"; + case bitc::METADATA_NAMED_NODE: return "METADATA_NAMED_NODE"; case bitc::METADATA_KIND: return "METADATA_KIND"; case bitc::METADATA_ATTACHMENT: return "METADATA_ATTACHMENT"; } From dalej at apple.com Fri Jul 16 13:35:46 2010 From: dalej at apple.com (Dale Johannesen) Date: Fri, 16 Jul 2010 18:35:46 -0000 Subject: [llvm-commits] [llvm] r108545 - /llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp Message-ID: <20100716183546.604172A6C12C@llvm.org> Author: johannes Date: Fri Jul 16 13:35:46 2010 New Revision: 108545 URL: http://llvm.org/viewvc/llvm-project?rev=108545&view=rev Log: Accept registers with P modifier. PR 5314. Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp?rev=108545&r1=108544&r2=108545&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp Fri Jul 16 13:35:46 2010 @@ -218,6 +218,10 @@ const MachineOperand &MO = MI->getOperand(OpNo); switch (MO.getType()) { default: llvm_unreachable("Unknown pcrel immediate operand"); + case MachineOperand::MO_Register: + // pc-relativeness was handled when computing the value in the reg. + printOperand(MI, OpNo, O); + return; case MachineOperand::MO_Immediate: O << MO.getImm(); return; From eli.friedman at gmail.com Fri Jul 16 13:47:20 2010 From: eli.friedman at gmail.com (Eli Friedman) Date: Fri, 16 Jul 2010 18:47:20 -0000 Subject: [llvm-commits] [llvm] r108547 - /llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Message-ID: <20100716184720.769A72A6C12C@llvm.org> Author: efriedma Date: Fri Jul 16 13:47:20 2010 New Revision: 108547 URL: http://llvm.org/viewvc/llvm-project?rev=108547&view=rev Log: Add missing attributes to cpp backend. Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp?rev=108547&r1=108546&r2=108547&view=diff ============================================================================== --- llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp (original) +++ llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Fri Jul 16 13:47:20 2010 @@ -471,14 +471,22 @@ HANDLE_ATTR(Nest); HANDLE_ATTR(ReadNone); HANDLE_ATTR(ReadOnly); - HANDLE_ATTR(InlineHint); HANDLE_ATTR(NoInline); HANDLE_ATTR(AlwaysInline); HANDLE_ATTR(OptimizeForSize); HANDLE_ATTR(StackProtect); HANDLE_ATTR(StackProtectReq); HANDLE_ATTR(NoCapture); + HANDLE_ATTR(NoRedZone); + HANDLE_ATTR(NoImplicitFloat); + HANDLE_ATTR(Naked); + HANDLE_ATTR(InlineHint); #undef HANDLE_ATTR + if (attrs & Attribute::StackAlignment) + Out << " | Attribute::constructStackAlignmentFromInt(" + << Attribute::getStackAlignmentFromAttrs(attrs) + << ")"; + attrs &= ~Attribute::StackAlignment; assert(attrs == 0 && "Unhandled attribute!"); Out << ";"; nl(Out); From dpatel at apple.com Fri Jul 16 15:16:30 2010 From: dpatel at apple.com (Devang Patel) Date: Fri, 16 Jul 2010 13:16:30 -0700 Subject: [llvm-commits] [llvm] r107678 - in /llvm/trunk: lib/Target/X86/AsmPrinter/X86MCInstLower.cpp test/CodeGen/X86/2010-07-06-DbgCrash.ll In-Reply-To: References: <20100706181832.4A4402A6C12C@llvm.org> Message-ID: <0CA13FB8-22D9-43AE-86A0-ECA778FAB91D@apple.com> Valgrind on my mac is not reporting this error. Is it possible for any one with linux box to shed a little light here ? - Devang On Jul 16, 2010, at 8:36 AM, Daniel Dunbar wrote: > Hi Devang, > > The valgrind buildbot is back online, and is reporting an error with > this test. Can you take a look: > http://google1.osuosl.org:8011/builders/llvm-i686-linux-vg_leak/builds/1076/steps/test-llvm/logs/2010-07-06-dbgcrash.ll > > - Daniel > > On Tue, Jul 6, 2010 at 11:18 AM, Devang Patel wrote: >> Author: dpatel >> Date: Tue Jul 6 13:18:32 2010 >> New Revision: 107678 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=107678&view=rev >> Log: >> Fix PR7545 crash. >> >> Added: >> llvm/trunk/test/CodeGen/X86/2010-07-06-DbgCrash.ll >> Modified: >> llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp >> >> Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp?rev=107678&r1=107677&r2=107678&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp (original) >> +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp Tue Jul 6 13:18:32 2010 >> @@ -505,7 +505,6 @@ >> O << V.getName(); >> O << " <- "; >> // Frame address. Currently handles register +- offset only. >> - assert(MI->getOperand(0).isReg() && MI->getOperand(3).isImm()); >> O << '['; printOperand(MI, 0, O); O << '+'; printOperand(MI, 3, O); >> O << ']'; >> O << "+"; >> @@ -517,8 +516,9 @@ >> MachineLocation Location; >> assert (MI->getNumOperands() == 7 && "Invalid no. of machine operands!"); >> // Frame address. Currently handles register +- offset only. >> - assert(MI->getOperand(0).isReg() && MI->getOperand(3).isImm()); >> - Location.set(MI->getOperand(0).getReg(), MI->getOperand(3).getImm()); >> + >> + if (MI->getOperand(0).isReg() && MI->getOperand(3).isImm()) >> + Location.set(MI->getOperand(0).getReg(), MI->getOperand(3).getImm()); >> return Location; >> } >> >> >> Added: llvm/trunk/test/CodeGen/X86/2010-07-06-DbgCrash.ll >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-07-06-DbgCrash.ll?rev=107678&view=auto >> ============================================================================== >> --- llvm/trunk/test/CodeGen/X86/2010-07-06-DbgCrash.ll (added) >> +++ llvm/trunk/test/CodeGen/X86/2010-07-06-DbgCrash.ll Tue Jul 6 13:18:32 2010 >> @@ -0,0 +1,29 @@ >> +; RUN: llc -O0 -relocation-model pic -o /dev/null >> +; PR7545 >> + at .str = private constant [4 x i8] c"one\00", align 1 ; <[4 x i8]*> [#uses=1] >> + at .str1 = private constant [4 x i8] c"two\00", align 1 ; <[5 x i8]*> [#uses=1] >> + at C.9.2167 = internal constant [2 x i8*] [i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), i8* getelementptr inbounds ([4 x i8]* @.str1, i64 0, i64 0)] >> +!38 = metadata !{i32 524329, metadata !"pbmsrch.c", metadata !"/Users/grawp/LLVM/test-suite/MultiSource/Benchmarks/MiBench/office-stringsearch", metadata !39} ; [ DW_TAG_file_type ] >> +!39 = metadata !{i32 524305, i32 0, i32 1, metadata !"pbmsrch.c", metadata !"/Users/grawp/LLVM/test-suite/MultiSource/Benchmarks/MiBench/office-stringsearch", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build 9999)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] >> +!46 = metadata !{i32 524303, metadata !38, metadata !"", metadata !38, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !47} ; [ DW_TAG_pointer_type ]!97 = metadata !{i32 524334, i32 0, metadata !38, metadata !"main", metadata !"main", metadata !"main", metadata !38, i32 73, metadata !98, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ]!101 = metadata !{[2 x i8*]* @C.9.2167} >> +!47 = metadata !{i32 524324, metadata !38, metadata !"char", metadata !38, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] >> +!97 = metadata !{i32 524334, i32 0, metadata !38, metadata !"main", metadata !"main", metadata !"main", metadata !38, i32 73, metadata !98, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ] >> +!98 = metadata !{i32 524309, metadata !38, metadata !"", metadata !38, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !99, i32 0, null} ; [ DW_TAG_subroutine_type ] >> +!99 = metadata !{metadata !100} >> +!100 = metadata !{i32 524324, metadata !38, metadata !"int", metadata !38, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] >> +!101 = metadata !{[2 x i8*]* @C.9.2167} >> +!102 = metadata !{i32 524544, metadata !103, metadata !"find_strings", metadata !38, i32 75, metadata !104} ; [ DW_TAG_auto_variable ] >> +!103 = metadata !{i32 524299, metadata !97, i32 73, i32 0} ; [ DW_TAG_lexical_block ] >> +!104 = metadata !{i32 524289, metadata !38, metadata !"", metadata !38, i32 0, i64 85312, i64 64, i64 0, i32 0, metadata !46, metadata !105, i32 0, null} ; [ DW_TAG_array_type ] >> +!105 = metadata !{metadata !106} >> +!106 = metadata !{i32 524321, i64 0, i64 1332} ; [ DW_TAG_subrange_type ] >> +!107 = metadata !{i32 73, i32 0, metadata !103, null} >> + >> +define i32 @main() nounwind ssp { >> +bb.nph: >> + tail call void @llvm.dbg.declare(metadata !101, metadata !102), !dbg !107 >> + ret i32 0, !dbg !107 >> +} >> + >> +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone >> + >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> From ggreif at gmail.com Fri Jul 16 15:35:19 2010 From: ggreif at gmail.com (Gabor Greif) Date: Fri, 16 Jul 2010 20:35:19 -0000 Subject: [llvm-commits] [llvm] r108549 - /llvm/trunk/lib/VMCore/Use.cpp Message-ID: <20100716203519.8EBF62A6C12C@llvm.org> Author: ggreif Date: Fri Jul 16 15:35:19 2010 New Revision: 108549 URL: http://llvm.org/viewvc/llvm-project?rev=108549&view=rev Log: get the first few tags from a precomputed table (count can be increased if desired) Modified: llvm/trunk/lib/VMCore/Use.cpp Modified: llvm/trunk/lib/VMCore/Use.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Use.cpp?rev=108549&r1=108548&r2=108549&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Use.cpp (original) +++ llvm/trunk/lib/VMCore/Use.cpp Fri Jul 16 15:35:19 2010 @@ -86,6 +86,15 @@ //===----------------------------------------------------------------------===// Use *Use::initTags(Use * const Start, Use *Stop, ptrdiff_t Done) { + while (Done < 6) { + if (Start == Stop--) + return Start; + static const PrevPtrTag tags[6] = { fullStopTag, oneDigitTag, stopTag, + oneDigitTag, oneDigitTag, stopTag }; + Stop->Prev.setFromOpaqueValue(reinterpret_cast(tags[Done++])); + Stop->Val = 0; + } + ptrdiff_t Count = Done; while (Start != Stop) { --Stop; From sabre at nondot.org Fri Jul 16 15:50:13 2010 From: sabre at nondot.org (Chris Lattner) Date: Fri, 16 Jul 2010 20:50:13 -0000 Subject: [llvm-commits] [llvm] r108553 - in /llvm/trunk: include/llvm/DerivedTypes.h lib/Transforms/IPO/GlobalOpt.cpp lib/VMCore/Type.cpp lib/VMCore/TypesContext.h Message-ID: <20100716205013.4B9A32A6C12C@llvm.org> Author: lattner Date: Fri Jul 16 15:50:13 2010 New Revision: 108553 URL: http://llvm.org/viewvc/llvm-project?rev=108553&view=rev Log: eliminate unlockedRefineAbstractTypeTo, types are all per-llvmcontext, so there is no locking involved in type refinement. Modified: llvm/trunk/include/llvm/DerivedTypes.h llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp llvm/trunk/lib/VMCore/Type.cpp llvm/trunk/lib/VMCore/TypesContext.h Modified: llvm/trunk/include/llvm/DerivedTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/DerivedTypes.h?rev=108553&r1=108552&r2=108553&view=diff ============================================================================== --- llvm/trunk/include/llvm/DerivedTypes.h (original) +++ llvm/trunk/include/llvm/DerivedTypes.h Fri Jul 16 15:50:13 2010 @@ -52,10 +52,6 @@ /// void dropAllTypeUses(); - /// unlockedRefineAbstractTypeTo - Internal version of refineAbstractTypeTo - /// that performs no locking. Only used for internal recursion. - void unlockedRefineAbstractTypeTo(const Type *NewType); - public: //===--------------------------------------------------------------------===// Modified: llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp?rev=108553&r1=108552&r2=108553&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/GlobalOpt.cpp Fri Jul 16 15:50:13 2010 @@ -1467,7 +1467,7 @@ TargetData *TD) { if (!TD) return false; - + // If this is a malloc of an abstract type, don't touch it. if (!AllocTy->isSized()) return false; Modified: llvm/trunk/lib/VMCore/Type.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Type.cpp?rev=108553&r1=108552&r2=108553&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Type.cpp (original) +++ llvm/trunk/lib/VMCore/Type.cpp Fri Jul 16 15:50:13 2010 @@ -1128,13 +1128,13 @@ } -// unlockedRefineAbstractTypeTo - This function is used when it is discovered +// refineAbstractTypeTo - This function is used when it is discovered // that the 'this' abstract type is actually equivalent to the NewType // specified. This causes all users of 'this' to switch to reference the more // concrete type NewType and for 'this' to be deleted. Only used for internal // callers. // -void DerivedType::unlockedRefineAbstractTypeTo(const Type *NewType) { +void DerivedType::refineAbstractTypeTo(const Type *NewType) { assert(isAbstract() && "refineAbstractTypeTo: Current type is not abstract!"); assert(this != NewType && "Can't refine to myself!"); assert(ForwardType == 0 && "This type has already been refined!"); @@ -1199,15 +1199,6 @@ // destroyed. } -// refineAbstractTypeTo - This function is used by external callers to notify -// us that this abstract type is equivalent to another type. -// -void DerivedType::refineAbstractTypeTo(const Type *NewType) { - // All recursive calls will go through unlockedRefineAbstractTypeTo, - // to avoid deadlock problems. - unlockedRefineAbstractTypeTo(NewType); -} - // notifyUsesThatTypeBecameConcrete - Notify AbstractTypeUsers of this type that // the current type has transitioned from being abstract to being concrete. // Modified: llvm/trunk/lib/VMCore/TypesContext.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/TypesContext.h?rev=108553&r1=108552&r2=108553&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/TypesContext.h (original) +++ llvm/trunk/lib/VMCore/TypesContext.h Fri Jul 16 15:50:13 2010 @@ -370,7 +370,7 @@ // We already have this type in the table. Get rid of the newly refined // type. TypeClass *NewTy = cast((Type*)I->second.get()); - Ty->unlockedRefineAbstractTypeTo(NewTy); + Ty->refineAbstractTypeTo(NewTy); return; } } else { @@ -406,7 +406,7 @@ } TypesByHash.erase(Entry); } - Ty->unlockedRefineAbstractTypeTo(NewTy); + Ty->refineAbstractTypeTo(NewTy); return; } } From dalej at apple.com Fri Jul 16 16:00:32 2010 From: dalej at apple.com (Dale Johannesen) Date: Fri, 16 Jul 2010 21:00:32 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r108554 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Message-ID: <20100716210032.1BE872A6C12C@llvm.org> Author: johannes Date: Fri Jul 16 16:00:31 2010 New Revision: 108554 URL: http://llvm.org/viewvc/llvm-project?rev=108554&view=rev Log: "p" constraint is a form of "m", not "r". PR 5314. Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=108554&r1=108553&r2=108554&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Fri Jul 16 16:00:31 2010 @@ -4429,12 +4429,11 @@ continue; } - // Translate 'p' to 'r'. This is supposed to check for a valid memory + // Translate 'p' to 'm'. This is supposed to check for a valid memory // address, but for inline assembly there is no way to know the mode of - // the data being addressed. Assume that a general register is always - // a valid address. + // the data being addressed. if (ConstraintChar == 'p') - ConstraintChar = 'r'; + ConstraintChar = 'm'; // See if this is a regclass constraint. unsigned RegClass; From stoklund at 2pi.dk Fri Jul 16 16:03:52 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Fri, 16 Jul 2010 21:03:52 -0000 Subject: [llvm-commits] [llvm] r108555 - in /llvm/trunk/lib/Target/PowerPC: PPCInstrInfo.cpp PPCInstrInfo.td Message-ID: <20100716210352.EB76E2A6C12C@llvm.org> Author: stoklund Date: Fri Jul 16 16:03:52 2010 New Revision: 108555 URL: http://llvm.org/viewvc/llvm-project?rev=108555&view=rev Log: Emit COPY instead of FMR/FMSD instructions for floating point conversion on PowerPC. Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=108555&r1=108554&r2=108555&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Fri Jul 16 16:03:52 2010 @@ -80,7 +80,7 @@ destReg = MI.getOperand(0).getReg(); return true; } - } else if (oc == PPC::FMR || oc == PPC::FMRSD) { // fmr r1, r2 + } else if (oc == PPC::FMR) { // fmr r1, r2 assert(MI.getNumOperands() >= 2 && MI.getOperand(0).isReg() && MI.getOperand(1).isReg() && Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=108555&r1=108554&r2=108555&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Fri Jul 16 16:03:52 2010 @@ -1022,9 +1022,7 @@ } } -/// FMR is split into 2 versions, one for 4/8 byte FP, and one for extending. -/// -/// Note that these are defined as pseudo-ops on the PPC970 because they are +/// Note that FMR is defined as pseudo-ops on the PPC970 because they are /// often coalesced away and we don't want the dispatch group builder to think /// that they will fill slots (which could cause the load of a LSU reject to /// sneak into a d-group with a store). @@ -1032,10 +1030,6 @@ "fmr $frD, $frB", FPGeneral, []>, // (set F4RC:$frD, F4RC:$frB) PPC970_Unit_Pseudo; -def FMRSD : XForm_26<63, 72, (outs F8RC:$frD), (ins F4RC:$frB), - "fmr $frD, $frB", FPGeneral, - [(set F8RC:$frD, (fextend F4RC:$frB))]>, - PPC970_Unit_Pseudo; let PPC970_Unit = 3 in { // FPU Operations. // These are artificially split into two different forms, for 4/8 byte FP. @@ -1476,10 +1470,13 @@ (LHZ iaddr:$src)>; def : Pat<(extloadi16 xaddr:$src), (LHZX xaddr:$src)>; -def : Pat<(extloadf32 iaddr:$src), - (FMRSD (LFS iaddr:$src))>; -def : Pat<(extloadf32 xaddr:$src), - (FMRSD (LFSX xaddr:$src))>; +def : Pat<(f64 (extloadf32 iaddr:$src)), + (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>; +def : Pat<(f64 (extloadf32 xaddr:$src)), + (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>; + +def : Pat<(f64 (fextend F4RC:$src)), + (COPY_TO_REGCLASS F4RC:$src, F8RC)>; // Memory barriers def : Pat<(membarrier (i32 imm /*ll*/), From stoklund at 2pi.dk Fri Jul 16 16:03:56 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Fri, 16 Jul 2010 21:03:56 -0000 Subject: [llvm-commits] [llvm] r108556 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/CalcSpillWeights.cpp lib/CodeGen/VirtRegRewriter.cpp Message-ID: <20100716210356.1396E2A6C12D@llvm.org> Author: stoklund Date: Fri Jul 16 16:03:55 2010 New Revision: 108556 URL: http://llvm.org/viewvc/llvm-project?rev=108556&view=rev Log: Remove remaining calls to TII::isMoveInstr. Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=108556&r1=108555&r2=108556&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Fri Jul 16 16:03:55 2010 @@ -113,22 +113,6 @@ return false; } - /// isIdentityCopy - Return true if the instruction is a copy (or - /// extract_subreg, insert_subreg, subreg_to_reg) where the source and - /// destination registers are the same. - bool isIdentityCopy(const MachineInstr &MI) const { - unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx; - if (isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) && - SrcReg == DstReg) - return true; - - if ((MI.getOpcode() == TargetOpcode::INSERT_SUBREG || - MI.getOpcode() == TargetOpcode::SUBREG_TO_REG) && - MI.getOperand(0).getReg() == MI.getOperand(2).getReg()) - return true; - return false; - } - /// isLoadFromStackSlot - If the specified machine instruction is a direct /// load from a stack slot, return the virtual or physical register number of /// the destination along with the FrameIndex of the loaded stack slot. If Modified: llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp?rev=108556&r1=108555&r2=108556&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp (original) +++ llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp Fri Jul 16 16:03:55 2010 @@ -43,7 +43,6 @@ LiveIntervals *lis = &getAnalysis(); MachineLoopInfo *loopInfo = &getAnalysis(); - const TargetInstrInfo *tii = fn.getTarget().getInstrInfo(); MachineRegisterInfo *mri = &fn.getRegInfo(); SmallSet processed; @@ -58,7 +57,7 @@ for (MachineBasicBlock::const_iterator mii = mbb->begin(), mie = mbb->end(); mii != mie; ++mii) { const MachineInstr *mi = mii; - if (tii->isIdentityCopy(*mi) || mi->isImplicitDef() || mi->isDebugValue()) + if (mi->isIdentityCopy() || mi->isImplicitDef() || mi->isDebugValue()) continue; for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) { Modified: llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp?rev=108556&r1=108555&r2=108556&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp (original) +++ llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp Fri Jul 16 16:03:55 2010 @@ -2442,28 +2442,6 @@ Spills.disallowClobberPhysReg(VirtReg); goto ProcessNextInst; } - unsigned Src, Dst, SrcSR, DstSR; - if (TII->isMoveInstr(MI, Src, Dst, SrcSR, DstSR) && - Src == Dst && SrcSR == DstSR && - !MI.findRegisterUseOperand(Src)->isUndef()) { - ++NumDCE; - DEBUG(dbgs() << "Removing now-noop copy: " << MI); - SmallVector KillRegs; - InvalidateKills(MI, TRI, RegKills, KillOps, &KillRegs); - if (MO.isDead() && !KillRegs.empty()) { - // Source register or an implicit super/sub-register use is killed. - assert(KillRegs[0] == Dst || - TRI->isSubRegister(KillRegs[0], Dst) || - TRI->isSuperRegister(KillRegs[0], Dst)); - // Last def is now dead. - TransferDeadness(Src, RegKills, KillOps); - } - VRM->RemoveMachineInstrFromMaps(&MI); - MBB->erase(&MI); - Erased = true; - Spills.disallowClobberPhysReg(VirtReg); - goto ProcessNextInst; - } // If it's not a no-op copy, it clobbers the value in the destreg. Spills.ClobberPhysReg(VirtReg); @@ -2541,20 +2519,6 @@ UpdateKills(*LastStore, TRI, RegKills, KillOps); goto ProcessNextInst; } - { - unsigned Src, Dst, SrcSR, DstSR; - if (TII->isMoveInstr(MI, Src, Dst, SrcSR, DstSR) && - Src == Dst && SrcSR == DstSR) { - ++NumDCE; - DEBUG(dbgs() << "Removing now-noop copy: " << MI); - InvalidateKills(MI, TRI, RegKills, KillOps); - VRM->RemoveMachineInstrFromMaps(&MI); - MBB->erase(&MI); - Erased = true; - UpdateKills(*LastStore, TRI, RegKills, KillOps); - goto ProcessNextInst; - } - } } } ProcessNextInst: From stoklund at 2pi.dk Fri Jul 16 16:17:08 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Fri, 16 Jul 2010 14:17:08 -0700 Subject: [llvm-commits] [llvm] r108540 - /llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp In-Reply-To: <20100716182200.5D9C02A6C12C@llvm.org> References: <20100716182200.5D9C02A6C12C@llvm.org> Message-ID: On Jul 16, 2010, at 11:22 AM, Jakob Stoklund Olesen wrote: > Author: stoklund > Date: Fri Jul 16 13:22:00 2010 > New Revision: 108540 > > URL: http://llvm.org/viewvc/llvm-project?rev=108540&view=rev > Log: > Teach PPCInstrInfo::storeRegToStackSlot and loadRegFromStackSlot to add memory > operands. > > Hopefully this fixes the llvm-gcc-powerpc-darwin9 buildbot. It really shouldn't > since missing memoperands should not affect correctness. And it did fix the buildbot. This is a weird miscompilation. Without the patch, llc will miscompile ARMSelectionDAGInfo::EmitTargetCodeForMemcpy. When the memory operand is put on loadFromStackSlot instructions, the function is compiled correctly. It should be the other way around since memory operands are supposed to be conservative. The difference is a moved load instruction. -------------- next part -------------- A non-text attachment was scrubbed... Name: armseldaginfo.bc Type: application/octet-stream Size: 16080 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100716/248dbdff/attachment.obj From dalej at apple.com Fri Jul 16 16:17:26 2010 From: dalej at apple.com (Dale Johannesen) Date: Fri, 16 Jul 2010 21:17:26 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r108558 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Message-ID: <20100716211726.6C50E2A6C12C@llvm.org> Author: johannes Date: Fri Jul 16 16:17:26 2010 New Revision: 108558 URL: http://llvm.org/viewvc/llvm-project?rev=108558&view=rev Log: "p" constraint also accepts constants. PR 5533. Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=108558&r1=108557&r2=108558&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Fri Jul 16 16:17:26 2010 @@ -4431,9 +4431,9 @@ // Translate 'p' to 'm'. This is supposed to check for a valid memory // address, but for inline assembly there is no way to know the mode of - // the data being addressed. + // the data being addressed. Peculiarly, it also accepts a constant. if (ConstraintChar == 'p') - ConstraintChar = 'm'; + Result += "im"; // See if this is a regclass constraint. unsigned RegClass; From sabre at nondot.org Fri Jul 16 16:20:46 2010 From: sabre at nondot.org (Chris Lattner) Date: Fri, 16 Jul 2010 21:20:46 -0000 Subject: [llvm-commits] [llvm] r108560 - in /llvm/trunk/lib/VMCore: Type.cpp TypesContext.h Message-ID: <20100716212046.BCBBA2A6C12C@llvm.org> Author: lattner Date: Fri Jul 16 16:20:46 2010 New Revision: 108560 URL: http://llvm.org/viewvc/llvm-project?rev=108560&view=rev Log: tidy up Modified: llvm/trunk/lib/VMCore/Type.cpp llvm/trunk/lib/VMCore/TypesContext.h Modified: llvm/trunk/lib/VMCore/Type.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Type.cpp?rev=108560&r1=108559&r2=108560&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Type.cpp (original) +++ llvm/trunk/lib/VMCore/Type.cpp Fri Jul 16 16:20:46 2010 @@ -603,8 +603,8 @@ static inline ChildIteratorType child_begin(NodeType *N) { if (N->isAbstract()) return N->subtype_begin(); - else // No need to process children of concrete types. - return N->subtype_end(); + // No need to process children of concrete types. + return N->subtype_end(); } static inline ChildIteratorType child_end(NodeType *N) { return N->subtype_end(); @@ -627,35 +627,35 @@ // Concrete types are leaves in the tree. Since an SCC will either be all // abstract or all concrete, we only need to check one type. - if (SCC[0]->isAbstract()) { - if (SCC[0]->isOpaqueTy()) - return; // Not going to be concrete, sorry. - - // If all of the children of all of the types in this SCC are concrete, - // then this SCC is now concrete as well. If not, neither this SCC, nor - // any parent SCCs will be concrete, so we might as well just exit. - for (unsigned i = 0, e = SCC.size(); i != e; ++i) - for (Type::subtype_iterator CI = SCC[i]->subtype_begin(), - E = SCC[i]->subtype_end(); CI != E; ++CI) - if ((*CI)->isAbstract()) - // If the child type is in our SCC, it doesn't make the entire SCC - // abstract unless there is a non-SCC abstract type. - if (std::find(SCC.begin(), SCC.end(), *CI) == SCC.end()) - return; // Not going to be concrete, sorry. - - // Okay, we just discovered this whole SCC is now concrete, mark it as - // such! - for (unsigned i = 0, e = SCC.size(); i != e; ++i) { - assert(SCC[i]->isAbstract() && "Why are we processing concrete types?"); - - SCC[i]->setAbstract(false); - } - - for (unsigned i = 0, e = SCC.size(); i != e; ++i) { - assert(!SCC[i]->isAbstract() && "Concrete type became abstract?"); - // The type just became concrete, notify all users! - cast(SCC[i])->notifyUsesThatTypeBecameConcrete(); - } + if (!SCC[0]->isAbstract()) continue; + + if (SCC[0]->isOpaqueTy()) + return; // Not going to be concrete, sorry. + + // If all of the children of all of the types in this SCC are concrete, + // then this SCC is now concrete as well. If not, neither this SCC, nor + // any parent SCCs will be concrete, so we might as well just exit. + for (unsigned i = 0, e = SCC.size(); i != e; ++i) + for (Type::subtype_iterator CI = SCC[i]->subtype_begin(), + E = SCC[i]->subtype_end(); CI != E; ++CI) + if ((*CI)->isAbstract()) + // If the child type is in our SCC, it doesn't make the entire SCC + // abstract unless there is a non-SCC abstract type. + if (std::find(SCC.begin(), SCC.end(), *CI) == SCC.end()) + return; // Not going to be concrete, sorry. + + // Okay, we just discovered this whole SCC is now concrete, mark it as + // such! + for (unsigned i = 0, e = SCC.size(); i != e; ++i) { + assert(SCC[i]->isAbstract() && "Why are we processing concrete types?"); + + SCC[i]->setAbstract(false); + } + + for (unsigned i = 0, e = SCC.size(); i != e; ++i) { + assert(!SCC[i]->isAbstract() && "Concrete type became abstract?"); + // The type just became concrete, notify all users! + cast(SCC[i])->notifyUsesThatTypeBecameConcrete(); } } } @@ -693,11 +693,15 @@ if (const IntegerType *ITy = dyn_cast(Ty)) { const IntegerType *ITy2 = cast(Ty2); return ITy->getBitWidth() == ITy2->getBitWidth(); - } else if (const PointerType *PTy = dyn_cast(Ty)) { + } + + if (const PointerType *PTy = dyn_cast(Ty)) { const PointerType *PTy2 = cast(Ty2); return PTy->getAddressSpace() == PTy2->getAddressSpace() && TypesEqual(PTy->getElementType(), PTy2->getElementType(), EqTypes); - } else if (const StructType *STy = dyn_cast(Ty)) { + } + + if (const StructType *STy = dyn_cast(Ty)) { const StructType *STy2 = cast(Ty2); if (STy->getNumElements() != STy2->getNumElements()) return false; if (STy->isPacked() != STy2->isPacked()) return false; @@ -705,22 +709,30 @@ if (!TypesEqual(STy->getElementType(i), STy2->getElementType(i), EqTypes)) return false; return true; - } else if (const UnionType *UTy = dyn_cast(Ty)) { + } + + if (const UnionType *UTy = dyn_cast(Ty)) { const UnionType *UTy2 = cast(Ty2); if (UTy->getNumElements() != UTy2->getNumElements()) return false; for (unsigned i = 0, e = UTy2->getNumElements(); i != e; ++i) if (!TypesEqual(UTy->getElementType(i), UTy2->getElementType(i), EqTypes)) return false; return true; - } else if (const ArrayType *ATy = dyn_cast(Ty)) { + } + + if (const ArrayType *ATy = dyn_cast(Ty)) { const ArrayType *ATy2 = cast(Ty2); return ATy->getNumElements() == ATy2->getNumElements() && TypesEqual(ATy->getElementType(), ATy2->getElementType(), EqTypes); - } else if (const VectorType *PTy = dyn_cast(Ty)) { + } + + if (const VectorType *PTy = dyn_cast(Ty)) { const VectorType *PTy2 = cast(Ty2); return PTy->getNumElements() == PTy2->getNumElements() && TypesEqual(PTy->getElementType(), PTy2->getElementType(), EqTypes); - } else if (const FunctionType *FTy = dyn_cast(Ty)) { + } + + if (const FunctionType *FTy = dyn_cast(Ty)) { const FunctionType *FTy2 = cast(Ty2); if (FTy->isVarArg() != FTy2->isVarArg() || FTy->getNumParams() != FTy2->getNumParams() || @@ -731,10 +743,10 @@ return false; } return true; - } else { - llvm_unreachable("Unknown derived type!"); - return false; } + + llvm_unreachable("Unknown derived type!"); + return false; } namespace llvm { // in namespace llvm so findable by ADL @@ -808,13 +820,13 @@ // Check for the built-in integer types switch (NumBits) { - case 1: return cast(Type::getInt1Ty(C)); - case 8: return cast(Type::getInt8Ty(C)); - case 16: return cast(Type::getInt16Ty(C)); - case 32: return cast(Type::getInt32Ty(C)); - case 64: return cast(Type::getInt64Ty(C)); - default: - break; + case 1: return cast(Type::getInt1Ty(C)); + case 8: return cast(Type::getInt8Ty(C)); + case 16: return cast(Type::getInt16Ty(C)); + case 32: return cast(Type::getInt32Ty(C)); + case 64: return cast(Type::getInt64Ty(C)); + default: + break; } LLVMContextImpl *pImpl = C.pImpl; @@ -902,8 +914,8 @@ } bool ArrayType::isValidElementType(const Type *ElemTy) { - return ElemTy->getTypeID() != VoidTyID && ElemTy->getTypeID() != LabelTyID && - ElemTy->getTypeID() != MetadataTyID && !ElemTy->isFunctionTy(); + return !ElemTy->isVoidTy() && !ElemTy->isLabelTy() && + !ElemTy->isMetadataTy() && !ElemTy->isFunctionTy(); } VectorType *VectorType::get(const Type *ElementType, unsigned NumElements) { @@ -1060,9 +1072,8 @@ } bool PointerType::isValidElementType(const Type *ElemTy) { - return ElemTy->getTypeID() != VoidTyID && - ElemTy->getTypeID() != LabelTyID && - ElemTy->getTypeID() != MetadataTyID; + return !ElemTy->isVoidTy() && !ElemTy->isLabelTy() && + !ElemTy->isMetadataTy(); } @@ -1071,8 +1082,7 @@ // OpaqueType *OpaqueType::get(LLVMContext &C) { - OpaqueType *OT = new OpaqueType(C); // All opaque types are distinct - + OpaqueType *OT = new OpaqueType(C); // All opaque types are distinct. LLVMContextImpl *pImpl = C.pImpl; pImpl->OpaqueTypes.insert(OT); return OT; @@ -1123,9 +1133,8 @@ << ">[" << (void*)this << "]" << "\n"); #endif - this->destroy(); + this->destroy(); } - } // refineAbstractTypeTo - This function is used when it is discovered Modified: llvm/trunk/lib/VMCore/TypesContext.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/TypesContext.h?rev=108560&r1=108559&r2=108560&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/TypesContext.h (original) +++ llvm/trunk/lib/VMCore/TypesContext.h Fri Jul 16 16:20:46 2010 @@ -385,31 +385,33 @@ if (I->second == Ty) { // Remember the position of the old type if we see it in our scan. Entry = I; + continue; + } + + if (!TypesEqual(Ty, I->second)) + continue; + + TypeClass *NewTy = cast((Type*)I->second.get()); + + // Remove the old entry form TypesByHash. If the hash values differ + // now, remove it from the old place. Otherwise, continue scanning + // withing this hashcode to reduce work. + if (NewTypeHash != OldTypeHash) { + RemoveFromTypesByHash(OldTypeHash, Ty); } else { - if (TypesEqual(Ty, I->second)) { - TypeClass *NewTy = cast((Type*)I->second.get()); - - // Remove the old entry form TypesByHash. If the hash values differ - // now, remove it from the old place. Otherwise, continue scanning - // withing this hashcode to reduce work. - if (NewTypeHash != OldTypeHash) { - RemoveFromTypesByHash(OldTypeHash, Ty); - } else { - if (Entry == E) { - // Find the location of Ty in the TypesByHash structure if we - // haven't seen it already. - while (I->second != Ty) { - ++I; - assert(I != E && "Structure doesn't contain type??"); - } - Entry = I; - } - TypesByHash.erase(Entry); + if (Entry == E) { + // Find the location of Ty in the TypesByHash structure if we + // haven't seen it already. + while (I->second != Ty) { + ++I; + assert(I != E && "Structure doesn't contain type??"); } - Ty->refineAbstractTypeTo(NewTy); - return; + Entry = I; } + TypesByHash.erase(Entry); } + Ty->refineAbstractTypeTo(NewTy); + return; } // If there is no existing type of the same structure, we reinsert an From stoklund at 2pi.dk Fri Jul 16 17:00:33 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Fri, 16 Jul 2010 22:00:33 -0000 Subject: [llvm-commits] [llvm] r108561 - /llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp Message-ID: <20100716220033.9D31F2A6C12D@llvm.org> Author: stoklund Date: Fri Jul 16 17:00:33 2010 New Revision: 108561 URL: http://llvm.org/viewvc/llvm-project?rev=108561&view=rev Log: Keep valgrind quiet. The isLive() method can read uninitialized memory, but it still gives correct results. Modified: llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp Modified: llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp?rev=108561&r1=108560&r2=108561&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp Fri Jul 16 17:00:33 2010 @@ -50,7 +50,12 @@ namespace { struct FPS : public MachineFunctionPass { static char ID; - FPS() : MachineFunctionPass(&ID) {} + FPS() : MachineFunctionPass(&ID) { + // This is really only to keep valgrind quiet. + // The logic in isLive() is too much for it. + memset(Stack, 0, sizeof(Stack)); + memset(RegMap, 0, sizeof(RegMap)); + } virtual void getAnalysisUsage(AnalysisUsage &AU) const { AU.setPreservesCFG(); From wdietz2 at illinois.edu Fri Jul 16 17:05:17 2010 From: wdietz2 at illinois.edu (Will Dietz) Date: Fri, 16 Jul 2010 22:05:17 -0000 Subject: [llvm-commits] [poolalloc] r108562 - /poolalloc/trunk/include/dsa/DataStructure.h Message-ID: <20100716220517.7B8412A6C12C@llvm.org> Author: wdietz2 Date: Fri Jul 16 17:05:17 2010 New Revision: 108562 URL: http://llvm.org/viewvc/llvm-project?rev=108562&view=rev Log: Make EQTD use EQBU like it was supposed to. Modified: poolalloc/trunk/include/dsa/DataStructure.h Modified: poolalloc/trunk/include/dsa/DataStructure.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/dsa/DataStructure.h?rev=108562&r1=108561&r2=108562&view=diff ============================================================================== --- poolalloc/trunk/include/dsa/DataStructure.h (original) +++ poolalloc/trunk/include/dsa/DataStructure.h Fri Jul 16 17:05:17 2010 @@ -369,7 +369,7 @@ public: static char ID; EQTDDataStructures() - :TDDataStructures((intptr_t)&ID, "eqtd.", false) + :TDDataStructures((intptr_t)&ID, "eqtd.", true) {} ~EQTDDataStructures(); }; From isanbard at gmail.com Fri Jul 16 17:20:36 2010 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 16 Jul 2010 22:20:36 -0000 Subject: [llvm-commits] [llvm] r108563 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/AsmPrinter/ lib/Target/ARM/ lib/Target/CellSPU/ lib/Target/MSP430/ lib/Target/PowerPC/ lib/Target/X86/ lib/Target/XCore/ utils/TableGen/ Message-ID: <20100716222036.607E82A6C12C@llvm.org> Author: void Date: Fri Jul 16 17:20:36 2010 New Revision: 108563 URL: http://llvm.org/viewvc/llvm-project?rev=108563&view=rev Log: Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission and thus is a much more meaningful name. Modified: llvm/trunk/include/llvm/CodeGen/MachineInstr.h llvm/trunk/include/llvm/Target/Target.td llvm/trunk/include/llvm/Target/TargetOpcodes.h llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.cpp llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp llvm/trunk/utils/TableGen/CodeGenTarget.cpp Modified: llvm/trunk/include/llvm/CodeGen/MachineInstr.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstr.h?rev=108563&r1=108562&r2=108563&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineInstr.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineInstr.h Fri Jul 16 17:20:36 2010 @@ -201,12 +201,14 @@ /// isLabel - Returns true if the MachineInstr represents a label. /// bool isLabel() const { - return getOpcode() == TargetOpcode::DBG_LABEL || + return getOpcode() == TargetOpcode::PROLOG_LABEL || getOpcode() == TargetOpcode::EH_LABEL || getOpcode() == TargetOpcode::GC_LABEL; } - bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; } + bool isPrologLabel() const { + return getOpcode() == TargetOpcode::PROLOG_LABEL; + } bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; } bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; } bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; } Modified: llvm/trunk/include/llvm/Target/Target.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=108563&r1=108562&r2=108563&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/Target.td (original) +++ llvm/trunk/include/llvm/Target/Target.td Fri Jul 16 17:20:36 2010 @@ -409,7 +409,7 @@ let InOperandList = (ins variable_ops); let AsmString = ""; } -def DBG_LABEL : Instruction { +def PROLOG_LABEL : Instruction { let OutOperandList = (outs); let InOperandList = (ins i32imm:$id); let AsmString = ""; Modified: llvm/trunk/include/llvm/Target/TargetOpcodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetOpcodes.h?rev=108563&r1=108562&r2=108563&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetOpcodes.h (original) +++ llvm/trunk/include/llvm/Target/TargetOpcodes.h Fri Jul 16 17:20:36 2010 @@ -25,7 +25,7 @@ enum { PHI = 0, INLINEASM = 1, - DBG_LABEL = 2, + PROLOG_LABEL = 2, EH_LABEL = 3, GC_LABEL = 4, Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=108563&r1=108562&r2=108563&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Fri Jul 16 17:20:36 2010 @@ -621,7 +621,7 @@ EmitComments(*II, OutStreamer.GetCommentOS()); switch (II->getOpcode()) { - case TargetOpcode::DBG_LABEL: + case TargetOpcode::PROLOG_LABEL: case TargetOpcode::EH_LABEL: case TargetOpcode::GC_LABEL: OutStreamer.EmitLabel(II->getOperand(0).getMCSymbol()); Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=108563&r1=108562&r2=108563&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Fri Jul 16 17:20:36 2010 @@ -501,7 +501,7 @@ llvm_unreachable("Unknown or unset size field for instr!"); case TargetOpcode::IMPLICIT_DEF: case TargetOpcode::KILL: - case TargetOpcode::DBG_LABEL: + case TargetOpcode::PROLOG_LABEL: case TargetOpcode::EH_LABEL: case TargetOpcode::DBG_VALUE: return 0; Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=108563&r1=108562&r2=108563&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Fri Jul 16 17:20:36 2010 @@ -662,7 +662,7 @@ } break; } - case TargetOpcode::DBG_LABEL: + case TargetOpcode::PROLOG_LABEL: case TargetOpcode::EH_LABEL: MCE.emitLabel(MI.getOperand(0).getMCSymbol()); break; Modified: llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp?rev=108563&r1=108562&r2=108563&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp Fri Jul 16 17:20:36 2010 @@ -417,7 +417,7 @@ if (hasDebugInfo) { // Mark effective beginning of when frame pointer becomes valid. FrameLabel = MMI.getContext().CreateTempSymbol(); - BuildMI(MBB, MBBI, dl, TII.get(SPU::DBG_LABEL)).addSym(FrameLabel); + BuildMI(MBB, MBBI, dl, TII.get(SPU::PROLOG_LABEL)).addSym(FrameLabel); } // Adjust stack pointer, spilling $lr -> 16($sp) and $sp -> -FrameSize($sp) @@ -476,7 +476,7 @@ // Mark effective beginning of when frame pointer is ready. MCSymbol *ReadyLabel = MMI.getContext().CreateTempSymbol(); - BuildMI(MBB, MBBI, dl, TII.get(SPU::DBG_LABEL)).addSym(ReadyLabel); + BuildMI(MBB, MBBI, dl, TII.get(SPU::PROLOG_LABEL)).addSym(ReadyLabel); MachineLocation FPDst(SPU::R1); MachineLocation FPSrc(MachineLocation::VirtualFP); @@ -491,7 +491,7 @@ dl = MBBI->getDebugLoc(); // Insert terminator label - BuildMI(MBB, MBBI, dl, TII.get(SPU::DBG_LABEL)) + BuildMI(MBB, MBBI, dl, TII.get(SPU::PROLOG_LABEL)) .addSym(MMI.getContext().CreateTempSymbol()); } } Modified: llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp?rev=108563&r1=108562&r2=108563&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp Fri Jul 16 17:20:36 2010 @@ -361,7 +361,7 @@ switch (Desc.getOpcode()) { default: assert(0 && "Unknown instruction size!"); - case TargetOpcode::DBG_LABEL: + case TargetOpcode::PROLOG_LABEL: case TargetOpcode::EH_LABEL: case TargetOpcode::IMPLICIT_DEF: case TargetOpcode::KILL: Modified: llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp?rev=108563&r1=108562&r2=108563&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp Fri Jul 16 17:20:36 2010 @@ -110,7 +110,7 @@ default: MCE.emitWordBE(getBinaryCodeForInstr(MI)); break; - case TargetOpcode::DBG_LABEL: + case TargetOpcode::PROLOG_LABEL: case TargetOpcode::EH_LABEL: MCE.emitLabel(MI.getOperand(0).getMCSymbol()); break; Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=108563&r1=108562&r2=108563&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Fri Jul 16 17:20:36 2010 @@ -686,7 +686,7 @@ const char *AsmStr = MI->getOperand(0).getSymbolName(); return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo()); } - case PPC::DBG_LABEL: + case PPC::PROLOG_LABEL: case PPC::EH_LABEL: case PPC::GC_LABEL: case PPC::DBG_VALUE: Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=108563&r1=108562&r2=108563&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Fri Jul 16 17:20:36 2010 @@ -1318,7 +1318,7 @@ if (needsFrameMoves) { // Mark effective beginning of when frame pointer becomes valid. FrameLabel = MMI.getContext().CreateTempSymbol(); - BuildMI(MBB, MBBI, dl, TII.get(PPC::DBG_LABEL)).addSym(FrameLabel); + BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(FrameLabel); // Show update of SP. if (NegFrameSize) { @@ -1361,7 +1361,7 @@ ReadyLabel = MMI.getContext().CreateTempSymbol(); // Mark effective beginning of when frame pointer is ready. - BuildMI(MBB, MBBI, dl, TII.get(PPC::DBG_LABEL)).addSym(ReadyLabel); + BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(ReadyLabel); MachineLocation FPDst(HasFP ? (isPPC64 ? PPC::X31 : PPC::R31) : (isPPC64 ? PPC::X1 : PPC::R1)); Modified: llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp?rev=108563&r1=108562&r2=108563&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp Fri Jul 16 17:20:36 2010 @@ -614,7 +614,7 @@ if (MI.getOperand(0).getSymbolName()[0]) report_fatal_error("JIT does not support inline asm!"); break; - case TargetOpcode::DBG_LABEL: + case TargetOpcode::PROLOG_LABEL: case TargetOpcode::GC_LABEL: case TargetOpcode::EH_LABEL: MCE.emitLabel(MI.getOperand(0).getMCSymbol()); Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=108563&r1=108562&r2=108563&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Fri Jul 16 17:20:36 2010 @@ -3327,7 +3327,7 @@ *MF->getTarget().getMCAsmInfo()); break; } - case TargetOpcode::DBG_LABEL: + case TargetOpcode::PROLOG_LABEL: case TargetOpcode::EH_LABEL: case TargetOpcode::DBG_VALUE: break; Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=108563&r1=108562&r2=108563&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Fri Jul 16 17:20:36 2010 @@ -979,7 +979,7 @@ if (needsFrameMoves) { // Mark the place where EBP/RBP was saved. MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol(); - BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addSym(FrameLabel); + BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(FrameLabel); // Define the current CFA rule to use the provided offset. if (StackSize) { @@ -1007,7 +1007,7 @@ if (needsFrameMoves) { // Mark effective beginning of when frame pointer becomes valid. MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol(); - BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addSym(FrameLabel); + BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(FrameLabel); // Define the current CFA to use the EBP/RBP register. MachineLocation FPDst(FramePtr); @@ -1047,7 +1047,7 @@ if (!HasFP && needsFrameMoves) { // Mark callee-saved push instruction. MCSymbol *Label = MMI.getContext().CreateTempSymbol(); - BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addSym(Label); + BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(Label); // Define the current CFA rule to use the provided offset. unsigned Ptr = StackSize ? @@ -1119,7 +1119,7 @@ if ((NumBytes || PushedRegs) && needsFrameMoves) { // Mark end of stack pointer adjustment. MCSymbol *Label = MMI.getContext().CreateTempSymbol(); - BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addSym(Label); + BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(Label); if (!HasFP && NumBytes) { // Define the current CFA rule to use the provided offset. Modified: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp?rev=108563&r1=108562&r2=108563&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp Fri Jul 16 17:20:36 2010 @@ -437,7 +437,7 @@ it->getFrameIdx(), RC, &RI); if (emitFrameMoves) { MCSymbol *SaveLabel = MF->getContext().CreateTempSymbol(); - BuildMI(MBB, MI, DL, get(XCore::DBG_LABEL)).addSym(SaveLabel); + BuildMI(MBB, MI, DL, get(XCore::PROLOG_LABEL)).addSym(SaveLabel); XFI->getSpillLabels().push_back(std::make_pair(SaveLabel, *it)); } } Modified: llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp?rev=108563&r1=108562&r2=108563&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp Fri Jul 16 17:20:36 2010 @@ -420,7 +420,7 @@ // Show update of SP. MCSymbol *FrameLabel = MMI->getContext().CreateTempSymbol(); - BuildMI(MBB, MBBI, dl, TII.get(XCore::DBG_LABEL)).addSym(FrameLabel); + BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(FrameLabel); MachineLocation SPDst(MachineLocation::VirtualFP); MachineLocation SPSrc(MachineLocation::VirtualFP, -FrameSize * 4); @@ -439,7 +439,7 @@ if (emitFrameMoves) { MCSymbol *SaveLRLabel = MMI->getContext().CreateTempSymbol(); - BuildMI(MBB, MBBI, dl, TII.get(XCore::DBG_LABEL)).addSym(SaveLRLabel); + BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(SaveLRLabel); MachineLocation CSDst(MachineLocation::VirtualFP, LRSpillOffset); MachineLocation CSSrc(XCore::LR); MMI->getFrameMoves().push_back(MachineMove(SaveLRLabel, CSDst, CSSrc)); @@ -455,7 +455,7 @@ MBB.addLiveIn(XCore::R10); if (emitFrameMoves) { MCSymbol *SaveR10Label = MMI->getContext().CreateTempSymbol(); - BuildMI(MBB, MBBI, dl, TII.get(XCore::DBG_LABEL)).addSym(SaveR10Label); + BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(SaveR10Label); MachineLocation CSDst(MachineLocation::VirtualFP, FPSpillOffset); MachineLocation CSSrc(XCore::R10); MMI->getFrameMoves().push_back(MachineMove(SaveR10Label, CSDst, CSSrc)); @@ -467,7 +467,7 @@ if (emitFrameMoves) { // Show FP is now valid. MCSymbol *FrameLabel = MMI->getContext().CreateTempSymbol(); - BuildMI(MBB, MBBI, dl, TII.get(XCore::DBG_LABEL)).addSym(FrameLabel); + BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(FrameLabel); MachineLocation SPDst(FramePtr); MachineLocation SPSrc(MachineLocation::VirtualFP); MMI->getFrameMoves().push_back(MachineMove(FrameLabel, SPDst, SPSrc)); Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=108563&r1=108562&r2=108563&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Fri Jul 16 17:20:36 2010 @@ -333,7 +333,7 @@ const char *const FixedInstrs[] = { "PHI", "INLINEASM", - "DBG_LABEL", + "PROLOG_LABEL", "EH_LABEL", "GC_LABEL", "KILL", From stoklund at 2pi.dk Fri Jul 16 17:35:32 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Fri, 16 Jul 2010 22:35:32 -0000 Subject: [llvm-commits] [llvm] r108564 - /llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp Message-ID: <20100716223532.ABDB82A6C12C@llvm.org> Author: stoklund Date: Fri Jul 16 17:35:32 2010 New Revision: 108564 URL: http://llvm.org/viewvc/llvm-project?rev=108564&view=rev Log: Use a small local function for a single remaining late isMoveInstr call in Thumb2ITBlockPass. Modified: llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp Modified: llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp?rev=108564&r1=108563&r2=108564&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp (original) +++ llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp Fri Jul 16 17:35:32 2010 @@ -91,35 +91,53 @@ } } +static bool isCopy(MachineInstr *MI) { + switch (MI->getOpcode()) { + default: + return false; + case ARM::MOVr: + case ARM::MOVr_TC: + case ARM::tMOVr: + case ARM::tMOVgpr2tgpr: + case ARM::tMOVtgpr2gpr: + case ARM::tMOVgpr2gpr: + case ARM::t2MOVr: + return true; + } +} + bool Thumb2ITBlockPass::MoveCopyOutOfITBlock(MachineInstr *MI, ARMCC::CondCodes CC, ARMCC::CondCodes OCC, SmallSet &Defs, SmallSet &Uses) { - unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx; - if (TII->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) { - assert(SrcSubIdx == 0 && DstSubIdx == 0 && - "Sub-register indices still around?"); - // llvm models select's as two-address instructions. That means a copy - // is inserted before a t2MOVccr, etc. If the copy is scheduled in - // between selects we would end up creating multiple IT blocks. - - // First check if it's safe to move it. - if (Uses.count(DstReg) || Defs.count(SrcReg)) - return false; - - // Then peek at the next instruction to see if it's predicated on CC or OCC. - // If not, then there is nothing to be gained by moving the copy. - MachineBasicBlock::iterator I = MI; ++I; - MachineBasicBlock::iterator E = MI->getParent()->end(); - while (I != E && I->isDebugValue()) - ++I; - if (I != E) { - unsigned NPredReg = 0; - ARMCC::CondCodes NCC = llvm::getITInstrPredicate(I, NPredReg); - if (NCC == CC || NCC == OCC) - return true; - } + if (!isCopy(MI)) + return false; + // llvm models select's as two-address instructions. That means a copy + // is inserted before a t2MOVccr, etc. If the copy is scheduled in + // between selects we would end up creating multiple IT blocks. + assert(MI->getOperand(0).getSubReg() == 0 && + MI->getOperand(1).getSubReg() == 0 && + "Sub-register indices still around?"); + + unsigned DstReg = MI->getOperand(0).getReg(); + unsigned SrcReg = MI->getOperand(1).getReg(); + + // First check if it's safe to move it. + if (Uses.count(DstReg) || Defs.count(SrcReg)) + return false; + + // Then peek at the next instruction to see if it's predicated on CC or OCC. + // If not, then there is nothing to be gained by moving the copy. + MachineBasicBlock::iterator I = MI; ++I; + MachineBasicBlock::iterator E = MI->getParent()->end(); + while (I != E && I->isDebugValue()) + ++I; + if (I != E) { + unsigned NPredReg = 0; + ARMCC::CondCodes NCC = llvm::getITInstrPredicate(I, NPredReg); + if (NCC == CC || NCC == OCC) + return true; } return false; } From stoklund at 2pi.dk Fri Jul 16 17:35:35 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Fri, 16 Jul 2010 22:35:35 -0000 Subject: [llvm-commits] [llvm] r108565 - /llvm/trunk/lib/Target/X86/X86FastISel.cpp Message-ID: <20100716223535.0D0EE2A6C12D@llvm.org> Author: stoklund Date: Fri Jul 16 17:35:34 2010 New Revision: 108565 URL: http://llvm.org/viewvc/llvm-project?rev=108565&view=rev Log: Use MI.isCopy. Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=108565&r1=108564&r2=108565&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Fri Jul 16 17:35:34 2010 @@ -1058,10 +1058,8 @@ const MachineInstr &MI = *RI; if (MI.definesRegister(Reg)) { - unsigned Src, Dst, SrcSR, DstSR; - - if (getInstrInfo()->isMoveInstr(MI, Src, Dst, SrcSR, DstSR)) { - Reg = Src; + if (MI.isCopy()) { + Reg = MI.getOperand(1).getReg(); continue; } From stoklund at 2pi.dk Fri Jul 16 17:35:37 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Fri, 16 Jul 2010 22:35:37 -0000 Subject: [llvm-commits] [llvm] r108566 - /llvm/trunk/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp Message-ID: <20100716223537.85F9B2A6C12E@llvm.org> Author: stoklund Date: Fri Jul 16 17:35:37 2010 New Revision: 108566 URL: http://llvm.org/viewvc/llvm-project?rev=108566&view=rev Log: Avoid isMoveInstr when printing XCore pseudo-moves. Modified: llvm/trunk/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp Modified: llvm/trunk/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp?rev=108566&r1=108565&r2=108566&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp Fri Jul 16 17:35:37 2010 @@ -264,15 +264,13 @@ void XCoreAsmPrinter::EmitInstruction(const MachineInstr *MI) { SmallString<128> Str; raw_svector_ostream O(Str); - + // Check for mov mnemonic - unsigned src, dst, srcSR, dstSR; - if (TM.getInstrInfo()->isMoveInstr(*MI, src, dst, srcSR, dstSR)) { - O << "\tmov " << getRegisterName(dst) << ", "; - O << getRegisterName(src); - } else { + if (MI->getOpcode() == XCore::ADD_2rus && !MI->getOperand(2).getImm()) + O << "\tmov " << getRegisterName(MI->getOperand(0).getReg()) << ", " + << getRegisterName(MI->getOperand(1).getReg()); + else printInstruction(MI, O); - } OutStreamer.EmitRawText(O.str()); } From stoklund at 2pi.dk Fri Jul 16 17:35:47 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Fri, 16 Jul 2010 22:35:47 -0000 Subject: [llvm-commits] [llvm] r108567 - in /llvm/trunk: docs/ include/llvm/Target/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CellSPU/ lib/Target/MBlaze/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PIC16/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/SystemZ/ lib/Target/X86/ lib/Target/XCore/ Message-ID: <20100716223547.84F432A6C12C@llvm.org> Author: stoklund Date: Fri Jul 16 17:35:46 2010 New Revision: 108567 URL: http://llvm.org/viewvc/llvm-project?rev=108567&view=rev Log: Remove the isMoveInstr() hook. Modified: llvm/trunk/docs/WritingAnLLVMBackend.html llvm/trunk/include/llvm/Target/TargetInstrInfo.h llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.h llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp llvm/trunk/lib/Target/Mips/MipsInstrInfo.h llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.h llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h llvm/trunk/lib/Target/X86/X86InstrInfo.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.h llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h Modified: llvm/trunk/docs/WritingAnLLVMBackend.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/WritingAnLLVMBackend.html?rev=108567&r1=108566&r2=108567&view=diff ============================================================================== --- llvm/trunk/docs/WritingAnLLVMBackend.html (original) +++ llvm/trunk/docs/WritingAnLLVMBackend.html Fri Jul 16 17:35:46 2010 @@ -1299,9 +1299,6 @@

    -
  • isMoveInstr — Return true if the instruction is a register to - register move; false, otherwise.
    • -
  • isLoadFromStackSlot — If the specified machine instruction is a direct load from a stack slot, return the register number of the destination and the FrameIndex of the stack slot.
    • Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Fri Jul 16 17:35:46 2010 @@ -92,15 +92,6 @@ AliasAnalysis *AA) const; public: - /// isMoveInstr - Return true if the instruction is a register to register - /// move and return the source and dest operands and their sub-register - /// indices by reference. - virtual bool isMoveInstr(const MachineInstr& MI, - unsigned& SrcReg, unsigned& DstReg, - unsigned& SrcSubIdx, unsigned& DstSubIdx) const { - return false; - } - /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" /// extension instruction. That is, it's like a copy where it's legal for the /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Fri Jul 16 17:35:46 2010 @@ -573,48 +573,6 @@ return 0; // Not reached } -/// Return true if the instruction is a register to register move and -/// leave the source and dest operands in the passed parameters. -/// -bool -ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI, - unsigned &SrcReg, unsigned &DstReg, - unsigned& SrcSubIdx, unsigned& DstSubIdx) const { - switch (MI.getOpcode()) { - default: break; - case ARM::VMOVS: - case ARM::VMOVD: - case ARM::VMOVDneon: - case ARM::VMOVQ: - case ARM::VMOVQQ : { - SrcReg = MI.getOperand(1).getReg(); - DstReg = MI.getOperand(0).getReg(); - SrcSubIdx = MI.getOperand(1).getSubReg(); - DstSubIdx = MI.getOperand(0).getSubReg(); - return true; - } - case ARM::MOVr: - case ARM::MOVr_TC: - case ARM::tMOVr: - case ARM::tMOVgpr2tgpr: - case ARM::tMOVtgpr2gpr: - case ARM::tMOVgpr2gpr: - case ARM::t2MOVr: { - assert(MI.getDesc().getNumOperands() >= 2 && - MI.getOperand(0).isReg() && - MI.getOperand(1).isReg() && - "Invalid ARM MOV instruction"); - SrcReg = MI.getOperand(1).getReg(); - DstReg = MI.getOperand(0).getReg(); - SrcSubIdx = MI.getOperand(1).getSubReg(); - DstSubIdx = MI.getOperand(0).getSubReg(); - return true; - } - } - - return false; -} - unsigned ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const { Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Fri Jul 16 17:35:46 2010 @@ -262,12 +262,6 @@ /// virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const; - /// Return true if the instruction is a register to register move and return - /// the source and dest operands and their sub-register indices by reference. - virtual bool isMoveInstr(const MachineInstr &MI, - unsigned &SrcReg, unsigned &DstReg, - unsigned &SrcSubIdx, unsigned &DstSubIdx) const; - virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; virtual unsigned isStoreToStackSlot(const MachineInstr *MI, Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp Fri Jul 16 17:35:46 2010 @@ -27,32 +27,6 @@ RI(*this) { } -bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI, - unsigned& sourceReg, unsigned& destReg, - unsigned& SrcSR, unsigned& DstSR) const { - unsigned oc = MI.getOpcode(); - if (oc == Alpha::BISr || - oc == Alpha::CPYSS || - oc == Alpha::CPYST || - oc == Alpha::CPYSSt || - oc == Alpha::CPYSTs) { - // or r1, r2, r2 - // cpys(s|t) r1 r2 r2 - assert(MI.getNumOperands() >= 3 && - MI.getOperand(0).isReg() && - MI.getOperand(1).isReg() && - MI.getOperand(2).isReg() && - "invalid Alpha BIS instruction!"); - if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) { - sourceReg = MI.getOperand(1).getReg(); - destReg = MI.getOperand(0).getReg(); - SrcSR = DstSR = 0; - return true; - } - } - return false; -} - unsigned AlphaInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const { Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h (original) +++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h Fri Jul 16 17:35:46 2010 @@ -30,12 +30,6 @@ /// virtual const AlphaRegisterInfo &getRegisterInfo() const { return RI; } - /// Return true if the instruction is a register to register move and return - /// the source and dest operands and their sub-register indices by reference. - virtual bool isMoveInstr(const MachineInstr &MI, - unsigned &SrcReg, unsigned &DstReg, - unsigned &SrcSubIdx, unsigned &DstSubIdx) const; - virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; virtual unsigned isStoreToStackSlot(const MachineInstr *MI, Modified: llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp Fri Jul 16 17:35:46 2010 @@ -28,34 +28,6 @@ RI(ST, *this), Subtarget(ST) {} -/// Return true if the instruction is a register to register move and -/// leave the source and dest operands in the passed parameters. -bool BlackfinInstrInfo::isMoveInstr(const MachineInstr &MI, - unsigned &SrcReg, - unsigned &DstReg, - unsigned &SrcSR, - unsigned &DstSR) const { - SrcSR = DstSR = 0; // No sub-registers. - switch (MI.getOpcode()) { - case BF::MOVE: - case BF::MOVE_ncccc: - case BF::MOVE_ccncc: - case BF::MOVECC_zext: - case BF::MOVECC_nz: - DstReg = MI.getOperand(0).getReg(); - SrcReg = MI.getOperand(1).getReg(); - return true; - case BF::SLL16i: - if (MI.getOperand(2).getImm()!=0) - return false; - DstReg = MI.getOperand(0).getReg(); - SrcReg = MI.getOperand(1).getReg(); - return true; - default: - return false; - } -} - /// isLoadFromStackSlot - If the specified machine instruction is a direct /// load from a stack slot, return the virtual or physical register number of /// the destination along with the FrameIndex of the loaded stack slot. If Modified: llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.h (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.h Fri Jul 16 17:35:46 2010 @@ -30,10 +30,6 @@ /// always be able to get register info as well (through this method). virtual const BlackfinRegisterInfo &getRegisterInfo() const { return RI; } - virtual bool isMoveInstr(const MachineInstr &MI, - unsigned &SrcReg, unsigned &DstReg, - unsigned &SrcSubIdx, unsigned &DstSubIdx) const; - virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp Fri Jul 16 17:35:46 2010 @@ -54,148 +54,6 @@ RI(*TM.getSubtargetImpl(), *this) { /* NOP */ } -bool -SPUInstrInfo::isMoveInstr(const MachineInstr& MI, - unsigned& sourceReg, - unsigned& destReg, - unsigned& SrcSR, unsigned& DstSR) const { - SrcSR = DstSR = 0; // No sub-registers. - - switch (MI.getOpcode()) { - default: - break; - case SPU::ORIv4i32: - case SPU::ORIr32: - case SPU::ORHIv8i16: - case SPU::ORHIr16: - case SPU::ORHIi8i16: - case SPU::ORBIv16i8: - case SPU::ORBIr8: - case SPU::ORIi16i32: - case SPU::ORIi8i32: - case SPU::AHIvec: - case SPU::AHIr16: - case SPU::AIv4i32: - assert(MI.getNumOperands() == 3 && - MI.getOperand(0).isReg() && - MI.getOperand(1).isReg() && - MI.getOperand(2).isImm() && - "invalid SPU ORI/ORHI/ORBI/AHI/AI/SFI/SFHI instruction!"); - if (MI.getOperand(2).getImm() == 0) { - sourceReg = MI.getOperand(1).getReg(); - destReg = MI.getOperand(0).getReg(); - return true; - } - break; - case SPU::AIr32: - assert(MI.getNumOperands() == 3 && - "wrong number of operands to AIr32"); - if (MI.getOperand(0).isReg() && - MI.getOperand(1).isReg() && - (MI.getOperand(2).isImm() && - MI.getOperand(2).getImm() == 0)) { - sourceReg = MI.getOperand(1).getReg(); - destReg = MI.getOperand(0).getReg(); - return true; - } - break; - case SPU::LRr8: - case SPU::LRr16: - case SPU::LRr32: - case SPU::LRf32: - case SPU::LRr64: - case SPU::LRf64: - case SPU::LRr128: - case SPU::LRv16i8: - case SPU::LRv8i16: - case SPU::LRv4i32: - case SPU::LRv4f32: - case SPU::LRv2i64: - case SPU::LRv2f64: - case SPU::ORv16i8_i8: - case SPU::ORv8i16_i16: - case SPU::ORv4i32_i32: - case SPU::ORv2i64_i64: - case SPU::ORv4f32_f32: - case SPU::ORv2f64_f64: - case SPU::ORi8_v16i8: - case SPU::ORi16_v8i16: - case SPU::ORi32_v4i32: - case SPU::ORi64_v2i64: - case SPU::ORf32_v4f32: - case SPU::ORf64_v2f64: -/* - case SPU::ORi128_r64: - case SPU::ORi128_f64: - case SPU::ORi128_r32: - case SPU::ORi128_f32: - case SPU::ORi128_r16: - case SPU::ORi128_r8: -*/ - case SPU::ORi128_vec: -/* - case SPU::ORr64_i128: - case SPU::ORf64_i128: - case SPU::ORr32_i128: - case SPU::ORf32_i128: - case SPU::ORr16_i128: - case SPU::ORr8_i128: -*/ - case SPU::ORvec_i128: -/* - case SPU::ORr16_r32: - case SPU::ORr8_r32: - case SPU::ORf32_r32: - case SPU::ORr32_f32: - case SPU::ORr32_r16: - case SPU::ORr32_r8: - case SPU::ORr16_r64: - case SPU::ORr8_r64: - case SPU::ORr64_r16: - case SPU::ORr64_r8: -*/ - case SPU::ORr64_r32: - case SPU::ORr32_r64: - case SPU::ORf32_r32: - case SPU::ORr32_f32: - case SPU::ORf64_r64: - case SPU::ORr64_f64: { - assert(MI.getNumOperands() == 2 && - MI.getOperand(0).isReg() && - MI.getOperand(1).isReg() && - "invalid SPU OR_ or LR instruction!"); - sourceReg = MI.getOperand(1).getReg(); - destReg = MI.getOperand(0).getReg(); - return true; - break; - } - case SPU::ORv16i8: - case SPU::ORv8i16: - case SPU::ORv4i32: - case SPU::ORv2i64: - case SPU::ORr8: - case SPU::ORr16: - case SPU::ORr32: - case SPU::ORr64: - case SPU::ORr128: - case SPU::ORf32: - case SPU::ORf64: - assert(MI.getNumOperands() == 3 && - MI.getOperand(0).isReg() && - MI.getOperand(1).isReg() && - MI.getOperand(2).isReg() && - "invalid SPU OR(vec|r32|r64|gprc) instruction!"); - if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) { - sourceReg = MI.getOperand(1).getReg(); - destReg = MI.getOperand(0).getReg(); - return true; - } - break; - } - - return false; -} - unsigned SPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const { Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h (original) +++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h Fri Jul 16 17:35:46 2010 @@ -32,12 +32,6 @@ /// virtual const SPURegisterInfo &getRegisterInfo() const { return RI; } - /// Return true if the instruction is a register to register move and return - /// the source and dest operands and their sub-register indices by reference. - virtual bool isMoveInstr(const MachineInstr &MI, - unsigned &SrcReg, unsigned &DstReg, - unsigned &SrcSubIdx, unsigned &DstSubIdx) const; - unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; unsigned isStoreToStackSlot(const MachineInstr *MI, Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp Fri Jul 16 17:35:46 2010 @@ -30,41 +30,6 @@ return op.isImm() && op.getImm() == 0; } -/// Return true if the instruction is a register to register move and -/// leave the source and dest operands in the passed parameters. -bool MBlazeInstrInfo:: -isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, - unsigned &SrcSubIdx, unsigned &DstSubIdx) const { - SrcSubIdx = DstSubIdx = 0; // No sub-registers. - - // add $dst, $src, $zero || addu $dst, $zero, $src - // or $dst, $src, $zero || or $dst, $zero, $src - if ((MI.getOpcode() == MBlaze::ADD) || (MI.getOpcode() == MBlaze::OR)) { - if (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == MBlaze::R0) { - DstReg = MI.getOperand(0).getReg(); - SrcReg = MI.getOperand(2).getReg(); - return true; - } else if (MI.getOperand(2).isReg() && - MI.getOperand(2).getReg() == MBlaze::R0) { - DstReg = MI.getOperand(0).getReg(); - SrcReg = MI.getOperand(1).getReg(); - return true; - } - } - - // addi $dst, $src, 0 - // ori $dst, $src, 0 - if ((MI.getOpcode() == MBlaze::ADDI) || (MI.getOpcode() == MBlaze::ORI)) { - if ((MI.getOperand(1).isReg()) && (isZeroImm(MI.getOperand(2)))) { - DstReg = MI.getOperand(0).getReg(); - SrcReg = MI.getOperand(1).getReg(); - return true; - } - } - - return false; -} - /// isLoadFromStackSlot - If the specified machine instruction is a direct /// load from a stack slot, return the virtual or physical register number of /// the destination along with the FrameIndex of the loaded stack slot. If Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h Fri Jul 16 17:35:46 2010 @@ -173,12 +173,6 @@ /// virtual const MBlazeRegisterInfo &getRegisterInfo() const { return RI; } - /// Return true if the instruction is a register to register move and return - /// the source and dest operands and their sub-register indices by reference. - virtual bool isMoveInstr(const MachineInstr &MI, - unsigned &SrcReg, unsigned &DstReg, - unsigned &SrcSubIdx, unsigned &DstSubIdx) const; - /// isLoadFromStackSlot - If the specified machine instruction is a direct /// load from a stack slot, return the virtual or physical register number of /// the destination along with the FrameIndex of the loaded stack slot. If Modified: llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp Fri Jul 16 17:35:46 2010 @@ -100,27 +100,6 @@ } bool -MSP430InstrInfo::isMoveInstr(const MachineInstr& MI, - unsigned &SrcReg, unsigned &DstReg, - unsigned &SrcSubIdx, unsigned &DstSubIdx) const { - SrcSubIdx = DstSubIdx = 0; // No sub-registers yet. - - switch (MI.getOpcode()) { - default: - return false; - case MSP430::MOV8rr: - case MSP430::MOV16rr: - assert(MI.getNumOperands() >= 2 && - MI.getOperand(0).isReg() && - MI.getOperand(1).isReg() && - "invalid register-register move instruction"); - SrcReg = MI.getOperand(1).getReg(); - DstReg = MI.getOperand(0).getReg(); - return true; - } -} - -bool MSP430InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector &CSI, Modified: llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h (original) +++ llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h Fri Jul 16 17:35:46 2010 @@ -54,10 +54,6 @@ unsigned DestReg, unsigned SrcReg, bool KillSrc) const; - bool isMoveInstr(const MachineInstr& MI, - unsigned &SrcReg, unsigned &DstReg, - unsigned &SrcSubIdx, unsigned &DstSubIdx) const; - virtual void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Fri Jul 16 17:35:46 2010 @@ -30,53 +30,6 @@ return op.isImm() && op.getImm() == 0; } -/// Return true if the instruction is a register to register move and -/// leave the source and dest operands in the passed parameters. -bool MipsInstrInfo:: -isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, - unsigned &SrcSubIdx, unsigned &DstSubIdx) const -{ - SrcSubIdx = DstSubIdx = 0; // No sub-registers. - - // addu $dst, $src, $zero || addu $dst, $zero, $src - // or $dst, $src, $zero || or $dst, $zero, $src - if ((MI.getOpcode() == Mips::ADDu) || (MI.getOpcode() == Mips::OR)) { - if (MI.getOperand(1).getReg() == Mips::ZERO) { - DstReg = MI.getOperand(0).getReg(); - SrcReg = MI.getOperand(2).getReg(); - return true; - } else if (MI.getOperand(2).getReg() == Mips::ZERO) { - DstReg = MI.getOperand(0).getReg(); - SrcReg = MI.getOperand(1).getReg(); - return true; - } - } - - // mov $fpDst, $fpSrc - // mfc $gpDst, $fpSrc - // mtc $fpDst, $gpSrc - if (MI.getOpcode() == Mips::FMOV_S32 || - MI.getOpcode() == Mips::FMOV_D32 || - MI.getOpcode() == Mips::MFC1 || - MI.getOpcode() == Mips::MTC1 || - MI.getOpcode() == Mips::MOVCCRToCCR) { - DstReg = MI.getOperand(0).getReg(); - SrcReg = MI.getOperand(1).getReg(); - return true; - } - - // addiu $dst, $src, 0 - if (MI.getOpcode() == Mips::ADDiu) { - if ((MI.getOperand(1).isReg()) && (isZeroImm(MI.getOperand(2)))) { - DstReg = MI.getOperand(0).getReg(); - SrcReg = MI.getOperand(1).getReg(); - return true; - } - } - - return false; -} - /// isLoadFromStackSlot - If the specified machine instruction is a direct /// load from a stack slot, return the virtual or physical register number of /// the destination along with the FrameIndex of the loaded stack slot. If Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.h (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.h Fri Jul 16 17:35:46 2010 @@ -174,12 +174,6 @@ /// virtual const MipsRegisterInfo &getRegisterInfo() const { return RI; } - /// Return true if the instruction is a register to register move and return - /// the source and dest operands and their sub-register indices by reference. - virtual bool isMoveInstr(const MachineInstr &MI, - unsigned &SrcReg, unsigned &DstReg, - unsigned &SrcSubIdx, unsigned &DstSubIdx) const; - /// isLoadFromStackSlot - If the specified machine instruction is a direct /// load from a stack slot, return the virtual or physical register number of /// the destination along with the FrameIndex of the loaded stack slot. If Modified: llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff ============================================================================== --- llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp Fri Jul 16 17:35:46 2010 @@ -167,21 +167,6 @@ .addReg(SrcReg, getKillRegState(KillSrc)); } -bool PIC16InstrInfo::isMoveInstr(const MachineInstr &MI, - unsigned &SrcReg, unsigned &DestReg, - unsigned &SrcSubIdx, unsigned &DstSubIdx) const { - SrcSubIdx = DstSubIdx = 0; // No sub-registers. - - if (MI.getOpcode() == PIC16::copy_fsr - || MI.getOpcode() == PIC16::copy_w) { - DestReg = MI.getOperand(0).getReg(); - SrcReg = MI.getOperand(1).getReg(); - return true; - } - - return false; -} - /// InsertBranch - Insert a branch into the end of the specified /// MachineBasicBlock. This operands to this method are the same as those /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch Modified: llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff ============================================================================== --- llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.h (original) +++ llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.h Fri Jul 16 17:35:46 2010 @@ -61,10 +61,6 @@ MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const; - virtual bool isMoveInstr(const MachineInstr &MI, - unsigned &SrcReg, unsigned &DstReg, - unsigned &SrcSubIdx, unsigned &DstSubIdx) const; - virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Fri Jul 16 17:35:46 2010 @@ -39,67 +39,6 @@ : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm), RI(*TM.getSubtargetImpl(), *this) {} -bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI, - unsigned& sourceReg, - unsigned& destReg, - unsigned& sourceSubIdx, - unsigned& destSubIdx) const { - sourceSubIdx = destSubIdx = 0; // No sub-registers. - - unsigned oc = MI.getOpcode(); - if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR || - oc == PPC::OR4To8 || oc == PPC::OR8To4) { // or r1, r2, r2 - assert(MI.getNumOperands() >= 3 && - MI.getOperand(0).isReg() && - MI.getOperand(1).isReg() && - MI.getOperand(2).isReg() && - "invalid PPC OR instruction!"); - if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) { - sourceReg = MI.getOperand(1).getReg(); - destReg = MI.getOperand(0).getReg(); - return true; - } - } else if (oc == PPC::ADDI) { // addi r1, r2, 0 - assert(MI.getNumOperands() >= 3 && - MI.getOperand(0).isReg() && - MI.getOperand(2).isImm() && - "invalid PPC ADDI instruction!"); - if (MI.getOperand(1).isReg() && MI.getOperand(2).getImm() == 0) { - sourceReg = MI.getOperand(1).getReg(); - destReg = MI.getOperand(0).getReg(); - return true; - } - } else if (oc == PPC::ORI) { // ori r1, r2, 0 - assert(MI.getNumOperands() >= 3 && - MI.getOperand(0).isReg() && - MI.getOperand(1).isReg() && - MI.getOperand(2).isImm() && - "invalid PPC ORI instruction!"); - if (MI.getOperand(2).getImm() == 0) { - sourceReg = MI.getOperand(1).getReg(); - destReg = MI.getOperand(0).getReg(); - return true; - } - } else if (oc == PPC::FMR) { // fmr r1, r2 - assert(MI.getNumOperands() >= 2 && - MI.getOperand(0).isReg() && - MI.getOperand(1).isReg() && - "invalid PPC FMR instruction"); - sourceReg = MI.getOperand(1).getReg(); - destReg = MI.getOperand(0).getReg(); - return true; - } else if (oc == PPC::MCRF) { // mcrf cr1, cr2 - assert(MI.getNumOperands() >= 2 && - MI.getOperand(0).isReg() && - MI.getOperand(1).isReg() && - "invalid PPC MCRF instruction"); - sourceReg = MI.getOperand(1).getReg(); - destReg = MI.getOperand(0).getReg(); - return true; - } - return false; -} - unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const { switch (MI->getOpcode()) { Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h Fri Jul 16 17:35:46 2010 @@ -82,12 +82,6 @@ /// virtual const PPCRegisterInfo &getRegisterInfo() const { return RI; } - /// Return true if the instruction is a register to register move and return - /// the source and dest operands and their sub-register indices by reference. - virtual bool isMoveInstr(const MachineInstr &MI, - unsigned &SrcReg, unsigned &DstReg, - unsigned &SrcSubIdx, unsigned &DstSubIdx) const; - unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; unsigned isStoreToStackSlot(const MachineInstr *MI, Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp Fri Jul 16 17:35:46 2010 @@ -28,46 +28,6 @@ RI(ST, *this), Subtarget(ST) { } -static bool isZeroImm(const MachineOperand &op) { - return op.isImm() && op.getImm() == 0; -} - -/// Return true if the instruction is a register to register move and -/// leave the source and dest operands in the passed parameters. -/// -bool SparcInstrInfo::isMoveInstr(const MachineInstr &MI, - unsigned &SrcReg, unsigned &DstReg, - unsigned &SrcSR, unsigned &DstSR) const { - SrcSR = DstSR = 0; // No sub-registers. - - // We look for 3 kinds of patterns here: - // or with G0 or 0 - // add with G0 or 0 - // fmovs or FpMOVD (pseudo double move). - if (MI.getOpcode() == SP::ORrr || MI.getOpcode() == SP::ADDrr) { - if (MI.getOperand(1).getReg() == SP::G0) { - DstReg = MI.getOperand(0).getReg(); - SrcReg = MI.getOperand(2).getReg(); - return true; - } else if (MI.getOperand(2).getReg() == SP::G0) { - DstReg = MI.getOperand(0).getReg(); - SrcReg = MI.getOperand(1).getReg(); - return true; - } - } else if ((MI.getOpcode() == SP::ORri || MI.getOpcode() == SP::ADDri) && - isZeroImm(MI.getOperand(2)) && MI.getOperand(1).isReg()) { - DstReg = MI.getOperand(0).getReg(); - SrcReg = MI.getOperand(1).getReg(); - return true; - } else if (MI.getOpcode() == SP::FMOVS || MI.getOpcode() == SP::FpMOVD || - MI.getOpcode() == SP::FMOVD) { - SrcReg = MI.getOperand(1).getReg(); - DstReg = MI.getOperand(0).getReg(); - return true; - } - return false; -} - /// isLoadFromStackSlot - If the specified machine instruction is a direct /// load from a stack slot, return the virtual or physical register number of /// the destination along with the FrameIndex of the loaded stack slot. If Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h (original) +++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h Fri Jul 16 17:35:46 2010 @@ -43,12 +43,6 @@ /// virtual const SparcRegisterInfo &getRegisterInfo() const { return RI; } - /// Return true if the instruction is a register to register move and return - /// the source and dest operands and their sub-register indices by reference. - virtual bool isMoveInstr(const MachineInstr &MI, - unsigned &SrcReg, unsigned &DstReg, - unsigned &SrcSubIdx, unsigned &DstSubIdx) const; - /// isLoadFromStackSlot - If the specified machine instruction is a direct /// load from a stack slot, return the virtual or physical register number of /// the destination along with the FrameIndex of the loaded stack slot. If Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp Fri Jul 16 17:35:46 2010 @@ -141,31 +141,6 @@ .addReg(SrcReg, getKillRegState(KillSrc)); } -bool -SystemZInstrInfo::isMoveInstr(const MachineInstr& MI, - unsigned &SrcReg, unsigned &DstReg, - unsigned &SrcSubIdx, unsigned &DstSubIdx) const { - switch (MI.getOpcode()) { - default: - return false; - case SystemZ::MOV32rr: - case SystemZ::MOV64rr: - case SystemZ::MOV64rrP: - case SystemZ::MOV128rr: - case SystemZ::FMOV32rr: - case SystemZ::FMOV64rr: - assert(MI.getNumOperands() >= 2 && - MI.getOperand(0).isReg() && - MI.getOperand(1).isReg() && - "invalid register-register move instruction"); - SrcReg = MI.getOperand(1).getReg(); - DstReg = MI.getOperand(0).getReg(); - SrcSubIdx = MI.getOperand(1).getSubReg(); - DstSubIdx = MI.getOperand(0).getSubReg(); - return true; - } -} - unsigned SystemZInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const { switch (MI->getOpcode()) { Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h Fri Jul 16 17:35:46 2010 @@ -65,9 +65,6 @@ unsigned DestReg, unsigned SrcReg, bool KillSrc) const; - bool isMoveInstr(const MachineInstr& MI, - unsigned &SrcReg, unsigned &DstReg, - unsigned &SrcSubIdx, unsigned &DstSubIdx) const; unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const; Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Fri Jul 16 17:35:46 2010 @@ -667,46 +667,6 @@ assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?"); } -bool X86InstrInfo::isMoveInstr(const MachineInstr& MI, - unsigned &SrcReg, unsigned &DstReg, - unsigned &SrcSubIdx, unsigned &DstSubIdx) const { - switch (MI.getOpcode()) { - default: - return false; - case X86::MOV8rr: - case X86::MOV8rr_NOREX: - case X86::MOV16rr: - case X86::MOV32rr: - case X86::MOV64rr: - case X86::MOV32rr_TC: - case X86::MOV64rr_TC: - - // FP Stack register class copies - case X86::MOV_Fp3232: case X86::MOV_Fp6464: case X86::MOV_Fp8080: - case X86::MOV_Fp3264: case X86::MOV_Fp3280: - case X86::MOV_Fp6432: case X86::MOV_Fp8032: - - // Note that MOVSSrr and MOVSDrr are not considered copies. FR32 and FR64 - // copies are done with FsMOVAPSrr and FsMOVAPDrr. - - case X86::FsMOVAPSrr: - case X86::FsMOVAPDrr: - case X86::MOVAPSrr: - case X86::MOVAPDrr: - case X86::MOVDQArr: - case X86::MMX_MOVQ64rr: - assert(MI.getNumOperands() >= 2 && - MI.getOperand(0).isReg() && - MI.getOperand(1).isReg() && - "invalid register-register move instruction"); - SrcReg = MI.getOperand(1).getReg(); - DstReg = MI.getOperand(0).getReg(); - SrcSubIdx = MI.getOperand(1).getSubReg(); - DstSubIdx = MI.getOperand(0).getSubReg(); - return true; - } -} - bool X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Fri Jul 16 17:35:46 2010 @@ -610,12 +610,6 @@ /// virtual const X86RegisterInfo &getRegisterInfo() const { return RI; } - /// Return true if the instruction is a register to register move and return - /// the source and dest operands and their sub-register indices by reference. - virtual bool isMoveInstr(const MachineInstr &MI, - unsigned &SrcReg, unsigned &DstReg, - unsigned &SrcSubIdx, unsigned &DstSubIdx) const; - /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" /// extension instruction. That is, it's like a copy where it's legal for the /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns Modified: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp Fri Jul 16 17:35:46 2010 @@ -46,33 +46,6 @@ return op.isImm() && op.getImm() == 0; } -/// Return true if the instruction is a register to register move and -/// leave the source and dest operands in the passed parameters. -/// -bool XCoreInstrInfo::isMoveInstr(const MachineInstr &MI, - unsigned &SrcReg, unsigned &DstReg, - unsigned &SrcSR, unsigned &DstSR) const { - SrcSR = DstSR = 0; // No sub-registers. - - // We look for 4 kinds of patterns here: - // add dst, src, 0 - // sub dst, src, 0 - // or dst, src, src - // and dst, src, src - if ((MI.getOpcode() == XCore::ADD_2rus || MI.getOpcode() == XCore::SUB_2rus) - && isZeroImm(MI.getOperand(2))) { - DstReg = MI.getOperand(0).getReg(); - SrcReg = MI.getOperand(1).getReg(); - return true; - } else if ((MI.getOpcode() == XCore::OR_3r || MI.getOpcode() == XCore::AND_3r) - && MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) { - DstReg = MI.getOperand(0).getReg(); - SrcReg = MI.getOperand(1).getReg(); - return true; - } - return false; -} - /// isLoadFromStackSlot - If the specified machine instruction is a direct /// load from a stack slot, return the virtual or physical register number of /// the destination along with the FrameIndex of the loaded stack slot. If Modified: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h (original) +++ llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h Fri Jul 16 17:35:46 2010 @@ -30,12 +30,6 @@ /// virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; } - /// Return true if the instruction is a register to register move and return - /// the source and dest operands and their sub-register indices by reference. - virtual bool isMoveInstr(const MachineInstr &MI, - unsigned &SrcReg, unsigned &DstReg, - unsigned &SrcSubIdx, unsigned &DstSubIdx) const; - /// isLoadFromStackSlot - If the specified machine instruction is a direct /// load from a stack slot, return the virtual or physical register number of /// the destination along with the FrameIndex of the loaded stack slot. If From isanbard at gmail.com Fri Jul 16 17:51:10 2010 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 16 Jul 2010 22:51:10 -0000 Subject: [llvm-commits] [llvm] r108568 - in /llvm/trunk: lib/CodeGen/AsmPrinter/AsmPrinter.cpp test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll test/CodeGen/PowerPC/empty-functions.ll test/CodeGen/X86/2008-01-25-EmptyFunction.ll test/CodeGen/X86/empty-functions.ll Message-ID: <20100716225110.9D1992A6C12C@llvm.org> Author: void Date: Fri Jul 16 17:51:10 2010 New Revision: 108568 URL: http://llvm.org/viewvc/llvm-project?rev=108568&view=rev Log: Consider this function: void foo() { __builtin_unreachable(); } It will output the following on Darwin X86: _func1: Leh_func_begin0: pushq %rbp Ltmp0: movq %rsp, %rbp Ltmp1: Leh_func_end0: This prolog adds a new Call Frame Information (CFI) row to the FDE with an address that is not within the address range of the code it describes -- part is equal to the end of the function -- and therefore results in an invalid EH frame. If we emit a nop in this situation, then the CFI row is now within the address range. Added: llvm/trunk/test/CodeGen/PowerPC/empty-functions.ll - copied, changed from r108562, llvm/trunk/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll llvm/trunk/test/CodeGen/X86/empty-functions.ll Removed: llvm/trunk/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll llvm/trunk/test/CodeGen/X86/2008-01-25-EmptyFunction.ll Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=108568&r1=108567&r2=108568&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Fri Jul 16 17:51:10 2010 @@ -599,12 +599,15 @@ // Print out code for the function. bool HasAnyRealCode = false; + const MachineInstr *LastMI = 0; for (MachineFunction::const_iterator I = MF->begin(), E = MF->end(); I != E; ++I) { // Print a label for the basic block. EmitBasicBlockStart(I); for (MachineBasicBlock::const_iterator II = I->begin(), IE = I->end(); II != IE; ++II) { + LastMI = II; + // Print the assembly for the instruction. if (!II->isLabel() && !II->isImplicitDef() && !II->isKill() && !II->isDebugValue()) { @@ -652,11 +655,18 @@ } } } - + + // If the last instruction was a prolog label, then we have a situation where + // we emitted a prolog but no function body. This results in the ending prolog + // label equaling the end of function label and an invalid "row" in the + // FDE. We need to emit a noop in this situation so that the FDE's rows are + // valid. + bool RequiresNoop = LastMI && LastMI->getOpcode()==TargetOpcode::PROLOG_LABEL; + // If the function is empty and the object file uses .subsections_via_symbols, // then we need to emit *something* to the function body to prevent the // labels from collapsing together. Just emit a noop. - if (MAI->hasSubsectionsViaSymbols() && !HasAnyRealCode) { + if ((MAI->hasSubsectionsViaSymbols() && !HasAnyRealCode) || RequiresNoop) { MCInst Noop; TM.getInstrInfo()->getNoopForMachoTarget(Noop); if (Noop.getOpcode()) { Removed: llvm/trunk/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll?rev=108567&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll (original) +++ llvm/trunk/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll (removed) @@ -1,8 +0,0 @@ -; RUN: llc < %s -march=ppc32 | grep nop -target triple = "powerpc-apple-darwin8" - - -define void @bork() noreturn nounwind { -entry: - unreachable -} Copied: llvm/trunk/test/CodeGen/PowerPC/empty-functions.ll (from r108562, llvm/trunk/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/empty-functions.ll?p2=llvm/trunk/test/CodeGen/PowerPC/empty-functions.ll&p1=llvm/trunk/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll&r1=108562&r2=108568&rev=108568&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll (original) +++ llvm/trunk/test/CodeGen/PowerPC/empty-functions.ll Fri Jul 16 17:51:10 2010 @@ -1,8 +1,12 @@ -; RUN: llc < %s -march=ppc32 | grep nop -target triple = "powerpc-apple-darwin8" +; RUN: llc < %s -mtriple=powerpc-apple-darwin | FileCheck -check-prefix=CHECK-NO-FP %s +; RUN: llc < %s -mtriple=powerpc-apple-darwin -disable-fp-elim | FileCheck -check-prefix=CHECK-FP %s - -define void @bork() noreturn nounwind { +define void @func() { entry: - unreachable + unreachable } +; CHECK-NO-FP: _func: +; CHECK-NO-FP: nop + +; CHECK-FP: _func: +; CHECK-FP: nop Removed: llvm/trunk/test/CodeGen/X86/2008-01-25-EmptyFunction.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-01-25-EmptyFunction.ll?rev=108567&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2008-01-25-EmptyFunction.ll (original) +++ llvm/trunk/test/CodeGen/X86/2008-01-25-EmptyFunction.ll (removed) @@ -1,8 +0,0 @@ -; RUN: llc < %s -march=x86 | grep nop -target triple = "i686-apple-darwin8" - - -define void @bork() noreturn nounwind { -entry: - unreachable -} Added: llvm/trunk/test/CodeGen/X86/empty-functions.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/empty-functions.ll?rev=108568&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/empty-functions.ll (added) +++ llvm/trunk/test/CodeGen/X86/empty-functions.ll Fri Jul 16 17:51:10 2010 @@ -0,0 +1,15 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck -check-prefix=CHECK-NO-FP %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin -disable-fp-elim | FileCheck -check-prefix=CHECK-FP %s + +define void @func() { +entry: + unreachable +} +; CHECK-NO-FP: _func: +; CHECK-NO-FP-NOT: movq %rsp, %rbp +; CHECK-NO-FP: nop + +; CHECK-FP: _func: +; CHECK-FP: movq %rsp, %rbp +; CHECK-FP-NEXT: Ltmp1: +; CHECK-FP: nop From gohman at apple.com Fri Jul 16 17:58:39 2010 From: gohman at apple.com (Dan Gohman) Date: Fri, 16 Jul 2010 22:58:39 -0000 Subject: [llvm-commits] [llvm] r108569 - /llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.cpp Message-ID: <20100716225839.61BE22A6C12C@llvm.org> Author: djg Date: Fri Jul 16 17:58:39 2010 New Revision: 108569 URL: http://llvm.org/viewvc/llvm-project?rev=108569&view=rev Log: Fix whitespace. Modified: llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.cpp Modified: llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.cpp?rev=108569&r1=108568&r2=108569&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.cpp (original) +++ llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.cpp Fri Jul 16 17:58:39 2010 @@ -388,8 +388,8 @@ NumModuleValues = Values.size(); // Adding function arguments to the value table. - for(Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); - I != E; ++I) + for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); + I != E; ++I) EnumerateValue(I); FirstFuncConstantID = Values.size(); From grosbach at apple.com Fri Jul 16 18:05:05 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 16 Jul 2010 23:05:05 -0000 Subject: [llvm-commits] [llvm] r108570 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMISelLowering.h lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h test/CodeGen/ARM/bfi.ll test/CodeGen/Thumb2/bfi.ll Message-ID: <20100716230505.5DAB52A6C12C@llvm.org> Author: grosbach Date: Fri Jul 16 18:05:05 2010 New Revision: 108570 URL: http://llvm.org/viewvc/llvm-project?rev=108570&view=rev Log: Add basic support to code-gen the ARM/Thumb2 bit-field insert (BFI) instruction and a combine pattern to use it for setting a bit-field to a constant value. More to come for non-constant stores. Added: llvm/trunk/test/CodeGen/ARM/bfi.ll llvm/trunk/test/CodeGen/Thumb2/bfi.ll Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.h llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=108570&r1=108569&r2=108570&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri Jul 16 18:05:05 2010 @@ -530,6 +530,9 @@ setTargetDAGCombine(ISD::SUB); setTargetDAGCombine(ISD::MUL); + if (Subtarget->hasV6T2Ops()) + setTargetDAGCombine(ISD::OR); + setStackPointerRegisterToSaveRestore(ARM::SP); if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2()) @@ -4232,6 +4235,53 @@ return SDValue(); } +/// PerformORCombine - Target-specific dag combine xforms for ISD::OR +static SDValue PerformORCombine(SDNode *N, + TargetLowering::DAGCombinerInfo &DCI, + const ARMSubtarget *Subtarget) { + // BFI is only available on V6T2+ + if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops()) + return SDValue(); + + SelectionDAG &DAG = DCI.DAG; + SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); + // or (and A, mask), val => ARMbfi A, val, mask + // iff (val & mask) == val + if (N0->getOpcode() != ISD::AND) + return SDValue(); + + EVT VT = N->getValueType(0); + if (VT != MVT::i32) + return SDValue(); + + // The value and the mask need to be constants so we can verify this is + // actually a bitfield set. If the mask is 0xffff, we can do better + // via a movt instruction, so don't use BFI in that case. + ConstantSDNode *C = dyn_cast(N0.getOperand(1)); + if (!C) + return SDValue(); + unsigned Mask = C->getZExtValue(); + if (Mask == 0xffff) + return SDValue(); + C = dyn_cast(N1); + if (!C) + return SDValue(); + unsigned Val = C->getZExtValue(); + if (ARM::isBitFieldInvertedMask(Mask) && (Val & ~Mask) != Val) + return SDValue(); + Val >>= CountTrailingZeros_32(~Mask); + + DebugLoc DL = N->getDebugLoc(); + SDValue Res = DAG.getNode(ARMISD::BFI, DL, VT, N0.getOperand(0), + DAG.getConstant(Val, MVT::i32), + DAG.getConstant(Mask, MVT::i32)); + + // Do not add new nodes to DAG combiner worklist. + DCI.CombineTo(N, Res, false); + + return SDValue(); +} + /// PerformVMOVRRDCombine - Target-specific dag combine xforms for /// ARMISD::VMOVRRD. static SDValue PerformVMOVRRDCombine(SDNode *N, @@ -4649,6 +4699,7 @@ case ISD::ADD: return PerformADDCombine(N, DCI); case ISD::SUB: return PerformSUBCombine(N, DCI); case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget); + case ISD::OR: return PerformORCombine(N, DCI, Subtarget); case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI); case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI); case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG); @@ -5380,6 +5431,21 @@ return ((int)Sign << 7) | (Exp << 4) | Mantissa; } +bool ARM::isBitFieldInvertedMask(unsigned v) { + if (v == 0xffffffff) + return 0; + // there can be 1's on either or both "outsides", all the "inside" + // bits must be 0's + unsigned int lsb = 0, msb = 31; + while (v & (1 << msb)) --msb; + while (v & (1 << lsb)) ++lsb; + for (unsigned int i = lsb; i <= msb; ++i) { + if (v & (1 << i)) + return 0; + } + return 1; +} + /// isFPImmLegal - Returns true if the target can instruction select the /// specified FP immediate natively. If false, the legalizer will /// materialize the FP immediate as a load from a constant pool. Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=108570&r1=108569&r2=108570&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Fri Jul 16 18:05:05 2010 @@ -150,7 +150,10 @@ // Floating-point max and min: FMAX, - FMIN + FMIN, + + // Bit-field insert + BFI }; } @@ -162,6 +165,7 @@ /// returns -1. int getVFPf32Imm(const APFloat &FPImm); int getVFPf64Imm(const APFloat &FPImm); + bool isBitFieldInvertedMask(unsigned v); } //===--------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=108570&r1=108569&r2=108570&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Fri Jul 16 18:05:05 2010 @@ -61,6 +61,9 @@ def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; +def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, + SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; + // Node definitions. def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>; def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>; @@ -131,6 +134,9 @@ def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET, [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>; + +def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>; + //===----------------------------------------------------------------------===// // ARM Instruction Predicate Definitions. // @@ -221,19 +227,7 @@ /// e.g., 0xf000ffff def bf_inv_mask_imm : Operand, PatLeaf<(imm), [{ - uint32_t v = (uint32_t)N->getZExtValue(); - if (v == 0xffffffff) - return 0; - // there can be 1's on either or both "outsides", all the "inside" - // bits must be 0's - unsigned int lsb = 0, msb = 31; - while (v & (1 << msb)) --msb; - while (v & (1 << lsb)) ++lsb; - for (unsigned int i = lsb; i <= msb; ++i) { - if (v & (1 << i)) - return 0; - } - return 1; + return ARM::isBitFieldInvertedMask(N->getZExtValue()); }] > { let PrintMethod = "printBitfieldInvMaskImmOperand"; } @@ -1858,11 +1852,11 @@ } // A8.6.18 BFI - Bitfield insert (Encoding A1) -// Added for disassembler with the pattern field purposely left blank. -def BFI : I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm), +def BFI : I<(outs GPR:$dst), (ins GPR:$src, GPR:$val, bf_inv_mask_imm:$imm), AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi, - "bfi", "\t$dst, $src, $imm", "", - [/* For disassembly only; pattern left blank */]>, + "bfi", "\t$dst, $val, $imm", "$src = $dst", + [(set GPR:$dst, (ARMbfi GPR:$src, GPR:$val, + bf_inv_mask_imm:$imm))]>, Requires<[IsARM, HasV6T2]> { let Inst{27-21} = 0b0111110; let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15 Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=108570&r1=108569&r2=108570&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Fri Jul 16 18:05:05 2010 @@ -1666,10 +1666,12 @@ } // A8.6.18 BFI - Bitfield insert (Encoding T1) -// Added for disassembler with the pattern field purposely left blank. -// FIXME: Utilize this instruction in codgen. -def t2BFI : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width), - IIC_iALUi, "bfi", "\t$dst, $src, $lsb, $width", []> { +let Constraints = "$src = $dst" in +def t2BFI : T2I<(outs GPR:$dst), + (ins GPR:$src, GPR:$val, bf_inv_mask_imm:$imm), + IIC_iALUi, "bfi", "\t$dst, $val, $imm", + [(set GPR:$dst, (ARMbfi GPR:$src, GPR:$val, + bf_inv_mask_imm:$imm))]> { let Inst{31-27} = 0b11110; let Inst{25} = 1; let Inst{24-20} = 0b10110; Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=108570&r1=108569&r2=108570&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Fri Jul 16 18:05:05 2010 @@ -989,10 +989,12 @@ // Special-case handling of BFC/BFI/SBFX/UBFX. if (Opcode == ARM::BFC || Opcode == ARM::BFI) { - // TIED_TO operand skipped for BFC and Inst{3-0} (Reg) for BFI. - MI.addOperand(MCOperand::CreateReg(Opcode == ARM::BFC ? 0 - : getRegisterEnum(B, ARM::GPRRegClassID, + MI.addOperand(MCOperand::CreateReg(0)); + if (Opcode == ARM::BFI) { + MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, decodeRm(insn)))); + ++OpIdx; + } uint32_t mask = 0; if (!getBFCInvMask(insn, mask)) return false; Modified: llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h?rev=108570&r1=108569&r2=108570&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h Fri Jul 16 18:05:05 2010 @@ -1555,6 +1555,13 @@ ++OpIdx; } + if (Opcode == ARM::t2BFI) { + // Add val reg operand. + MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, + decodeRn(insn)))); + ++OpIdx; + } + assert(OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef() && "Pure imm operand expected"); @@ -1567,7 +1574,7 @@ MI.addOperand(MCOperand::CreateImm(getIImm3Imm8(insn))); else if (Opcode == ARM::t2MOVi16 || Opcode == ARM::t2MOVTi16) MI.addOperand(MCOperand::CreateImm(getImm16(insn))); - else if (Opcode == ARM::t2BFC) { + else if (Opcode == ARM::t2BFC || Opcode == ARM::t2BFI) { uint32_t mask = 0; if (getBitfieldInvMask(insn, mask)) MI.addOperand(MCOperand::CreateImm(mask)); @@ -1575,17 +1582,10 @@ return false; } else { // Handle the case of: lsb width - assert((Opcode == ARM::t2SBFX || Opcode == ARM::t2UBFX || - Opcode == ARM::t2BFI) && "Unexpected opcode"); + assert((Opcode == ARM::t2SBFX || Opcode == ARM::t2UBFX) + && "Unexpected opcode"); MI.addOperand(MCOperand::CreateImm(getLsb(insn))); - if (Opcode == ARM::t2BFI) { - if (getMsb(insn) < getLsb(insn)) { - DEBUG(errs() << "Encoding error: msb < lsb\n"); - return false; - } - MI.addOperand(MCOperand::CreateImm(getMsb(insn) - getLsb(insn) + 1)); - } else - MI.addOperand(MCOperand::CreateImm(getWidthMinus1(insn) + 1)); + MI.addOperand(MCOperand::CreateImm(getWidthMinus1(insn) + 1)); ++OpIdx; } Added: llvm/trunk/test/CodeGen/ARM/bfi.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/bfi.ll?rev=108570&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/bfi.ll (added) +++ llvm/trunk/test/CodeGen/ARM/bfi.ll Fri Jul 16 18:05:05 2010 @@ -0,0 +1,17 @@ +; RUN: llc -march=arm -mattr=+v6t2 < %s | FileCheck %s + +%struct.F = type { [3 x i8], i8 } + + at X = common global %struct.F zeroinitializer, align 4 ; <%struct.F*> [#uses=1] + +define void @f1([1 x i32] %f.coerce0) nounwind { +entry: +; CHECK: f1 +; CHECK: mov r2, #10 +; CHECK: bfi r1, r2, #22, #4 + %0 = load i32* bitcast (%struct.F* @X to i32*), align 4 ; [#uses=1] + %1 = and i32 %0, -62914561 ; [#uses=1] + %2 = or i32 %1, 41943040 ; [#uses=1] + store i32 %2, i32* bitcast (%struct.F* @X to i32*), align 4 + ret void +} Added: llvm/trunk/test/CodeGen/Thumb2/bfi.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/bfi.ll?rev=108570&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/bfi.ll (added) +++ llvm/trunk/test/CodeGen/Thumb2/bfi.ll Fri Jul 16 18:05:05 2010 @@ -0,0 +1,17 @@ +; RUN: llc -march=thumb -mattr=+v6t2 < %s | FileCheck %s + +%struct.F = type { [3 x i8], i8 } + + at X = common global %struct.F zeroinitializer, align 4 ; <%struct.F*> [#uses=1] + +define void @f1([1 x i32] %f.coerce0) nounwind { +entry: +; CHECK: f1 +; CHECK: movs r2, #10 +; CHECK: bfi r1, r2, #22, #4 + %0 = load i32* bitcast (%struct.F* @X to i32*), align 4 ; [#uses=1] + %1 = and i32 %0, -62914561 ; [#uses=1] + %2 = or i32 %1, 41943040 ; [#uses=1] + store i32 %2, i32* bitcast (%struct.F* @X to i32*), align 4 + ret void +} From isanbard at gmail.com Fri Jul 16 18:10:00 2010 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 16 Jul 2010 23:10:00 -0000 Subject: [llvm-commits] [llvm] r108571 - /llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp Message-ID: <20100716231000.748252A6C12C@llvm.org> Author: void Date: Fri Jul 16 18:10:00 2010 New Revision: 108571 URL: http://llvm.org/viewvc/llvm-project?rev=108571&view=rev Log: Update comment. Modified: llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp Modified: llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp?rev=108571&r1=108570&r2=108571&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp Fri Jul 16 18:10:00 2010 @@ -115,7 +115,7 @@ for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { const AsmWriterInst *Inst = getAsmWriterInstByID(i); - if (Inst == 0) continue; // PHI, INLINEASM, DBG_LABEL, etc. + if (Inst == 0) continue; // PHI, INLINEASM, PROLOG_LABEL, etc. std::string Command; if (Inst->Operands.empty()) From wdietz2 at illinois.edu Fri Jul 16 18:28:26 2010 From: wdietz2 at illinois.edu (Will Dietz) Date: Fri, 16 Jul 2010 23:28:26 -0000 Subject: [llvm-commits] [poolalloc] r108575 - /poolalloc/trunk/test/dsa/regression/2010-07-16.CBU_MissingGraph.ll Message-ID: <20100716232826.125F52A6C12C@llvm.org> Author: wdietz2 Date: Fri Jul 16 18:28:25 2010 New Revision: 108575 URL: http://llvm.org/viewvc/llvm-project?rev=108575&view=rev Log: Added test that causes CBU to fail because it assumes all callees in callgraph have entries in the global graph. Added: poolalloc/trunk/test/dsa/regression/2010-07-16.CBU_MissingGraph.ll Added: poolalloc/trunk/test/dsa/regression/2010-07-16.CBU_MissingGraph.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/regression/2010-07-16.CBU_MissingGraph.ll?rev=108575&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/regression/2010-07-16.CBU_MissingGraph.ll (added) +++ poolalloc/trunk/test/dsa/regression/2010-07-16.CBU_MissingGraph.ll Fri Jul 16 18:28:25 2010 @@ -0,0 +1,53 @@ +;This test presently fails because cbu isn't robust to callee's not being in +; the globals graph... which happens all the time--direct call's callees +; don't get entries, for example. +;RUN: dsaopt %s -dsa-cbu +; ModuleID = 'bugpoint-reduced-simplified.bc' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.4" + +%struct.OP = type { %struct.OP*, %struct.OP*, %struct.OP* ()*, i32, i16, i16, i8, i8 } +%struct.REGEXP = type { i32, i8**, i8**, %struct.regnode*, i32, i32, i32, i32, i8*, i8*, i8*, i8*, i16, i16, %struct.reg_substr_data*, %struct.reg_data*, [1 x %struct.regnode] } +%struct.SV = type { i8*, i32, i32 } +%struct.__va_list_tag = type { i32, i32, i8*, i8* } +%struct.reg_data = type { i32, i8*, [1 x i8*] } +%struct.reg_substr_data = type { [3 x %struct.reg_substr_datum] } +%struct.reg_substr_datum = type { i32, i32, %struct.SV* } +%struct.regnode = type { i8, i8, i16 } + + at .str1239 = external constant [1 x i8], align 1 ; <[1 x i8]*> [#uses=1] + at PL_sv_undef = external global %struct.SV, align 16 ; <%struct.SV*> [#uses=1] + +define %struct.SV* @Perl_amagic_call(%struct.SV* %left, %struct.SV* %right, i32 %method, i32 %flags) nounwind ssp { +entry: + call void @Perl_sv_setsv(%struct.SV* %left, %struct.SV* undef) nounwind + ret %struct.SV* %left +} + +define %struct.OP* @Perl_pp_sort() nounwind ssp { +entry: + %storemerge1 = select i1 undef, i32 (%struct.SV*, %struct.SV*)* @Perl_sv_cmp, i32 (%struct.SV*, %struct.SV*)* @amagic_cmp ; [#uses=1] + %0 = call i32 %storemerge1(%struct.SV* undef, %struct.SV* undef) nounwind ; [#uses=0] + unreachable +} + +declare i32 @amagic_cmp(%struct.SV*, %struct.SV*) nounwind ssp + +define i8* @Perl_sv_2pv(%struct.SV* %sv, i64* %lp) nounwind ssp { +entry: + %0 = call %struct.SV* @Perl_amagic_call(%struct.SV* %sv, %struct.SV* @PL_sv_undef, i32 4, i32 9) nounwind ; <%struct.SV*> [#uses=0] + unreachable +} + +define i32 @Perl_sv_cmp(%struct.SV* %str1, %struct.SV* %str2) nounwind ssp { +entry: + %0 = call i8* @Perl_sv_2pv(%struct.SV* %str1, i64* undef) nounwind ssp ; [#uses=0] + unreachable +} + +define void @Perl_sv_setsv(%struct.SV* %dstr, %struct.SV* %sstr) nounwind ssp { +entry: + %0 = tail call i32 @Perl_sv_cmp(%struct.SV* undef, %struct.SV* undef) nounwind ssp ; [#uses=0] + unreachable +} + From wdietz2 at illinois.edu Fri Jul 16 18:53:05 2010 From: wdietz2 at illinois.edu (Will Dietz) Date: Fri, 16 Jul 2010 23:53:05 -0000 Subject: [llvm-commits] [poolalloc] r108576 - in /poolalloc/trunk/test/dsa/regression: 2010-07-16.CBU_MissingGraph.ll 2010-07-16.MissingIndirectCallee.ll 2010-07-16.SimpleLoop.ll Message-ID: <20100716235305.27DCB2A6C12C@llvm.org> Author: wdietz2 Date: Fri Jul 16 18:53:04 2010 New Revision: 108576 URL: http://llvm.org/viewvc/llvm-project?rev=108576&view=rev Log: Added test for EQ that demonstrates the 'Simple loop in callgraph' error. Added 'MissingIndirectCallee' test, passes presently but important case. Added 'disble-output' to CBU_MissingGraph test. One day I'll remember. Added: poolalloc/trunk/test/dsa/regression/2010-07-16.MissingIndirectCallee.ll poolalloc/trunk/test/dsa/regression/2010-07-16.SimpleLoop.ll Modified: poolalloc/trunk/test/dsa/regression/2010-07-16.CBU_MissingGraph.ll Modified: poolalloc/trunk/test/dsa/regression/2010-07-16.CBU_MissingGraph.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/regression/2010-07-16.CBU_MissingGraph.ll?rev=108576&r1=108575&r2=108576&view=diff ============================================================================== --- poolalloc/trunk/test/dsa/regression/2010-07-16.CBU_MissingGraph.ll (original) +++ poolalloc/trunk/test/dsa/regression/2010-07-16.CBU_MissingGraph.ll Fri Jul 16 18:53:04 2010 @@ -1,7 +1,7 @@ ;This test presently fails because cbu isn't robust to callee's not being in ; the globals graph... which happens all the time--direct call's callees ; don't get entries, for example. -;RUN: dsaopt %s -dsa-cbu +;RUN: dsaopt %s -dsa-cbu -disable-output ; ModuleID = 'bugpoint-reduced-simplified.bc' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-apple-darwin10.4" Added: poolalloc/trunk/test/dsa/regression/2010-07-16.MissingIndirectCallee.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/regression/2010-07-16.MissingIndirectCallee.ll?rev=108576&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/regression/2010-07-16.MissingIndirectCallee.ll (added) +++ poolalloc/trunk/test/dsa/regression/2010-07-16.MissingIndirectCallee.ll Fri Jul 16 18:53:04 2010 @@ -0,0 +1,347 @@ +;RUN: dsaopt %s -dsa-cbu -disable-output +; ModuleID = 'bugpoint-reduced-simplified.bc' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.4" + +%0 = type { %struct.block } +%struct.AV = type { %struct.XPVAV*, i32, i32 } +%struct.COP = type { %struct.OP*, %struct.OP*, %struct.OP* ()*, i32, i16, i16, i8, i8, i8*, %struct.HV*, %struct.GV*, i32, i32, i16 } +%struct.CV = type { %struct.XPVCV*, i32, i32 } +%struct.DIR = type { i32, i64, i64, i8*, i32, i64, i64, i32, %struct.__darwin_pthread_mutex_t, %struct._telldir* } +%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 } +%struct.GP = type { %struct.SV*, i32, %struct.io*, %struct.CV*, %struct.AV*, %struct.HV*, %struct.GV*, %struct.CV*, i32, i32, i16, %struct.GV* } +%struct.GV = type { %struct.XPVGV*, i32, i32 } +%struct.HE = type { %struct.HE*, %struct.HEK*, %struct.SV* } +%struct.HEK = type { i32, i32, [1 x i8] } +%struct.HV = type { %struct.XPVHV*, i32, i32 } +%struct.MAGIC = type { %struct.MAGIC*, %struct.MGVTBL*, i16, i8, i8, %struct.SV*, i8*, i32 } +%struct.MGVTBL = type { i32 (%struct.SV*, %struct.MAGIC*)*, i32 (%struct.SV*, %struct.MAGIC*)*, i32 (%struct.SV*, %struct.MAGIC*)*, i32 (%struct.SV*, %struct.MAGIC*)*, i32 (%struct.SV*, %struct.MAGIC*)* } +%struct.OP = type { %struct.OP*, %struct.OP*, %struct.OP* ()*, i32, i16, i16, i8, i8 } +%struct.PERL_CONTEXT = type { i32, %0 } +%struct.PMOP = type { %struct.OP*, %struct.OP*, %struct.OP* ()*, i32, i16, i16, i8, i8, %struct.OP*, %struct.OP*, i32, %struct.OP*, %struct.OP*, %struct.PMOP*, %struct.REGEXP*, i16, i16, i8 } +%struct.REGEXP = type { i32, i8**, i8**, %struct.regnode*, i32, i32, i32, i32, i8*, i8*, i8*, i8*, i16, i16, %struct.reg_substr_data*, %struct.reg_data*, [1 x %struct.regnode] } +%struct.SV = type { i8*, i32, i32 } +%struct.XPVAV = type { i8*, i64, i64, i64, double, %struct.MAGIC*, %struct.HV*, %struct.SV**, %struct.SV*, i8 } +%struct.XPVCV = type { i8*, i64, i64, i64, double, %struct.MAGIC*, %struct.HV*, %struct.HV*, %struct.OP*, %struct.OP*, void (%struct.CV*)*, %union.ANY, %struct.GV*, %struct.GV*, i64, %struct.AV*, %struct.CV*, i16 } +%struct.XPVGV = type { i8*, i64, i64, i64, double, %struct.MAGIC*, %struct.HV*, %struct.GP*, i8*, i64, %struct.HV*, i8 } +%struct.XPVHV = type { i8*, i64, i64, i64, double, %struct.MAGIC*, %struct.HV*, i32, %struct.HE*, %struct.PMOP*, i8* } +%struct.XPVIO = type { i8*, i64, i64, i64, double, %struct.MAGIC*, %struct.HV*, %struct.FILE*, %struct.FILE*, %struct.DIR*, i64, i64, i64, i64, i8*, %struct.GV*, i8*, %struct.GV*, i8*, %struct.GV*, i16, i8, i8 } +%struct.__darwin_pthread_mutex_t = type { i64, [56 x i8] } +%struct.__sFILEX = type opaque +%struct.__sbuf = type { i8*, i32 } +%struct._telldir = type opaque +%struct.block = type { i32, %struct.COP*, i32, i32, i32, %struct.PMOP*, i8, %union.anon } +%struct.block_loop = type { i8*, i32, %struct.OP*, %struct.OP*, %struct.OP*, %struct.SV**, %struct.SV*, %struct.SV*, %struct.AV*, i64, i64 } +%struct.io = type { %struct.XPVIO*, i32, i32 } +%struct.reg_data = type { i32, i8*, [1 x i8*] } +%struct.reg_substr_data = type { [3 x %struct.reg_substr_datum] } +%struct.reg_substr_datum = type { i32, i32, %struct.SV* } +%struct.regnode = type { i8, i8, i16 } +%union.ANY = type { i8* } +%union.anon = type { %struct.block_loop } + + at PL_sv_root = external global %struct.SV* ; <%struct.SV**> [#uses=3] + at PL_stack_sp = external global %struct.SV** ; <%struct.SV***> [#uses=2] + at PL_curpad = external global %struct.SV** ; <%struct.SV***> [#uses=3] + at PL_savestack = external global %union.ANY* ; <%union.ANY**> [#uses=1] + +declare void @XS_MD5_digest(%struct.CV* nocapture) nounwind ssp + +define %struct.OP* @Perl_pp_require_DIRECT() nounwind ssp { +entry: + %tmp = load %struct.SV*** @PL_stack_sp, align 8 ; <%struct.SV**> [#uses=1] + %tmp1 = load %struct.SV** %tmp, align 8 ; <%struct.SV*> [#uses=1] + br i1 undef, label %bb12, label %bb11 + +bb11: ; preds = %entry + %tmp38 = getelementptr inbounds %struct.SV* %tmp1, i64 0, i32 0 ; [#uses=1] + %tmp43 = load i8** %tmp38, align 8 ; [#uses=1] + %tmp44 = bitcast i8* %tmp43 to i8** ; [#uses=1] + %tmp45 = load i8** %tmp44, align 8 ; [#uses=1] + br i1 undef, label %bb16, label %bb14 + +bb12: ; preds = %entry + unreachable + +bb14: ; preds = %bb11 + br i1 undef, label %bb16, label %bb15 + +bb15: ; preds = %bb14 + br i1 undef, label %bb16, label %bb17 + +bb16: ; preds = %bb15, %bb14, %bb11 + ret %struct.OP* undef + +bb17: ; preds = %bb15 + br i1 undef, label %bb31, label %bb32 + +bb31: ; preds = %bb17 + unreachable + +bb32: ; preds = %bb17 + br i1 undef, label %bb34, label %bb35 + +bb34: ; preds = %bb32 + unreachable + +bb35: ; preds = %bb32 + %tmp107 = load %struct.SV** @PL_sv_root, align 8 ; <%struct.SV*> [#uses=2] + br i1 undef, label %bb1.i, label %bb.i4 + +bb.i4: ; preds = %bb35 + %tmp109 = getelementptr inbounds %struct.SV* %tmp107, i64 0, i32 0 ; [#uses=1] + %tmp110 = load i8** %tmp109, align 8 ; [#uses=1] + %tmp111 = bitcast i8* %tmp110 to %struct.SV* ; <%struct.SV*> [#uses=1] + store %struct.SV* %tmp111, %struct.SV** @PL_sv_root, align 8 + %tmp115 = getelementptr inbounds %struct.SV* %tmp107, i64 0, i32 0 ; [#uses=1] + br label %bb46 + +bb1.i: ; preds = %bb35 + unreachable + +bb36: ; preds = %bb48 + %tmp148 = load i8** %tmp115, align 8 ; [#uses=1] + %tmp149 = bitcast i8* %tmp148 to i8** ; [#uses=1] + %tmp150 = load i8** %tmp149, align 8 ; [#uses=1] + br label %bb46 + +bb46: ; preds = %bb36, %bb.i4 + %tryname.1 = phi i8* [ %tmp150, %bb36 ], [ null, %bb.i4 ] ; [#uses=1] + br i1 undef, label %bb48, label %bb47 + +bb47: ; preds = %bb46 + unreachable + +bb48: ; preds = %bb46 + br i1 undef, label %bb50, label %bb36 + +bb50: ; preds = %bb48 + %storemerge4 = select i1 undef, i8* %tmp45, i8* %tryname.1 ; [#uses=0] + unreachable +} + +define %struct.OP* @Perl_pp_goto_DIRECT() nounwind ssp { +entry: + %tmp1 = load %struct.SV*** @PL_stack_sp, align 8 ; <%struct.SV**> [#uses=1] + %tmp11 = load %struct.SV** %tmp1, align 8 ; <%struct.SV*> [#uses=1] + br i1 undef, label %bb117, label %bb1 + +bb1: ; preds = %entry + %tmp17 = getelementptr inbounds %struct.SV* %tmp11, i64 0, i32 0 ; [#uses=1] + %tmp18 = load i8** %tmp17, align 8 ; [#uses=1] + %tmp19 = bitcast i8* %tmp18 to %struct.SV** ; <%struct.SV**> [#uses=1] + %tmp20 = load %struct.SV** %tmp19, align 8 ; <%struct.SV*> [#uses=1] + br i1 undef, label %bb2, label %bb117 + +bb2: ; preds = %bb1 + %tmp25 = bitcast %struct.SV* %tmp20 to %struct.CV* ; <%struct.CV*> [#uses=3] + %tmp26 = getelementptr inbounds %struct.CV* %tmp25, i64 0, i32 0 ; <%struct.XPVCV**> [#uses=1] + %tmp90 = load %struct.PERL_CONTEXT** undef, align 8 ; <%struct.PERL_CONTEXT*> [#uses=2] + br i1 undef, label %bb.i.i, label %dopoptosub.exit + +bb.i.i: ; preds = %bb2 + br label %dopoptosub.exit + +dopoptosub.exit: ; preds = %bb.i.i, %bb2 + br i1 undef, label %bb13, label %bb14 + +bb13: ; preds = %dopoptosub.exit + ret %struct.OP* undef + +bb14: ; preds = %dopoptosub.exit + br i1 undef, label %bb15, label %bb16 + +bb15: ; preds = %bb14 + unreachable + +bb16: ; preds = %bb14 + switch i32 undef, label %bb37 [ + i32 2, label %bb18 + i32 1, label %bb20 + ] + +bb18: ; preds = %bb16 + ret %struct.OP* undef + +bb20: ; preds = %bb16 + br i1 undef, label %bb37, label %bb21 + +bb21: ; preds = %bb20 + br i1 undef, label %bb22, label %bb23 + +bb22: ; preds = %bb21 + br label %bb23 + +bb23: ; preds = %bb22, %bb21 + br i1 undef, label %bb28, label %bb27 + +bb27: ; preds = %bb23 + br label %bb28 + +bb28: ; preds = %bb27, %bb23 + unreachable + +bb37: ; preds = %bb20, %bb16 + br i1 undef, label %bb41, label %bb42 + +bb41: ; preds = %bb37 + unreachable + +bb42: ; preds = %bb37 + br i1 undef, label %bb.i1, label %entry.bb1_crit_edge.i + +entry.bb1_crit_edge.i: ; preds = %bb42 + br i1 undef, label %bb51, label %bb43 + +bb.i1: ; preds = %bb42 + unreachable + +bb43: ; preds = %entry.bb1_crit_edge.i + br i1 undef, label %bb47, label %bb45.preheader + +bb45.preheader: ; preds = %bb43 + unreachable + +bb47: ; preds = %bb43 + br i1 undef, label %bb48, label %bb49 + +bb48: ; preds = %bb47 + unreachable + +bb49: ; preds = %bb47 + %tmp336 = load %struct.XPVCV** %tmp26, align 8 ; <%struct.XPVCV*> [#uses=1] + %tmp337 = getelementptr inbounds %struct.XPVCV* %tmp336, i64 0, i32 10 ; [#uses=1] + %tmp338 = load void (%struct.CV*)** %tmp337, align 8 ; [#uses=1] + call void %tmp338(%struct.CV* %tmp25) nounwind + unreachable + +bb51: ; preds = %entry.bb1_crit_edge.i + %tmp380 = bitcast i8* undef to %struct.SV** ; <%struct.SV**> [#uses=2] + br i1 undef, label %bb52, label %bb53 + +bb52: ; preds = %bb51 + br label %bb53 + +bb53: ; preds = %bb52, %bb51 + %tmp391 = getelementptr inbounds %struct.PERL_CONTEXT* %tmp90, i64 undef, i32 1, i32 0, i32 7, i32 0, i32 0 ; [#uses=1] + %.c = bitcast %struct.CV* %tmp25 to i8* ; [#uses=1] + store i8* %.c, i8** %tmp391 + br i1 undef, label %bb83, label %bb57 + +bb57: ; preds = %bb53 + br i1 undef, label %bb61, label %bb83 + +bb61: ; preds = %bb57 + %tmp446 = getelementptr inbounds %struct.SV** %tmp380, i64 undef ; <%struct.SV**> [#uses=1] + %tmp447 = load %struct.SV** %tmp446, align 8 ; <%struct.SV*> [#uses=1] + %tmp448 = getelementptr inbounds %struct.SV* %tmp447, i64 0, i32 0 ; [#uses=1] + %tmp449 = load i8** %tmp448, align 8 ; [#uses=1] + %tmp450 = bitcast i8* %tmp449 to i8** ; [#uses=1] + %tmp451 = load i8** %tmp450, align 8 ; [#uses=1] + br i1 undef, label %bb.nph28, label %bb79 + +bb.nph28: ; preds = %bb61 + %scevgep66 = getelementptr i8* %tmp451, i64 undef ; [#uses=0] + unreachable + +bb79: ; preds = %bb61 + unreachable + +bb83: ; preds = %bb57, %bb53 + br i1 undef, label %bb.i25, label %entry.bb1_crit_edge.i23 + +entry.bb1_crit_edge.i23: ; preds = %bb83 + %.pre1.i22 = load %union.ANY** @PL_savestack, align 8 ; <%union.ANY*> [#uses=2] + %tmp620 = load %struct.SV*** @PL_curpad, align 8 ; <%struct.SV**> [#uses=1] + %tmp621 = getelementptr inbounds %union.ANY* %.pre1.i22, i64 undef, i32 0 ; [#uses=1] + %tmp622 = bitcast %struct.SV** %tmp620 to i8* ; [#uses=1] + store i8* %tmp622, i8** %tmp621, align 8 + %tmp625 = getelementptr inbounds %union.ANY* %.pre1.i22, i64 undef, i32 0 ; [#uses=1] + store i8* bitcast (%struct.SV*** @PL_curpad to i8*), i8** %tmp625, align 8 + %tmp634 = getelementptr inbounds %struct.SV** %tmp380, i64 undef ; <%struct.SV**> [#uses=1] + %tmp635 = load %struct.SV** %tmp634, align 8 ; <%struct.SV*> [#uses=1] + %tmp636 = bitcast %struct.SV* %tmp635 to %struct.XPVAV** ; <%struct.XPVAV**> [#uses=1] + %tmp637 = load %struct.XPVAV** %tmp636, align 8 ; <%struct.XPVAV*> [#uses=1] + %tmp638 = getelementptr inbounds %struct.XPVAV* %tmp637, i64 0, i32 0 ; [#uses=1] + %tmp639 = load i8** %tmp638, align 8 ; [#uses=1] + %tmp640 = bitcast i8* %tmp639 to %struct.SV** ; <%struct.SV**> [#uses=2] + store %struct.SV** %tmp640, %struct.SV*** @PL_curpad, align 8 + %tmp646 = load %struct.SV** %tmp640, align 8 ; <%struct.SV*> [#uses=1] + %tmp664 = getelementptr inbounds %struct.PERL_CONTEXT* %tmp90, i64 undef, i32 1, i32 0, i32 7, i32 0, i32 4 ; <%struct.OP**> [#uses=1] + %.c4 = bitcast %struct.SV* %tmp646 to %struct.OP* ; <%struct.OP*> [#uses=1] + store %struct.OP* %.c4, %struct.OP** %tmp664 + unreachable + +bb.i25: ; preds = %bb83 + unreachable + +bb117: ; preds = %bb1, %entry + br i1 undef, label %bb119, label %bb118 + +bb118: ; preds = %bb117 + br i1 undef, label %bb163, label %bb164 + +bb119: ; preds = %bb117 + unreachable + +bb163: ; preds = %bb118 + br label %bb164 + +bb164: ; preds = %bb163, %bb118 + ret %struct.OP* null +} + +define fastcc void @Perl_newXS_SPEC3() nounwind ssp { +entry: + br i1 undef, label %bb22, label %bb7 + +bb7: ; preds = %entry + br label %bb22 + +bb22: ; preds = %bb7, %entry + br i1 undef, label %bb1.i, label %bb.i + +bb.i: ; preds = %bb22 + br label %Perl_newSV.exit + +bb1.i: ; preds = %bb22 + br label %Perl_newSV.exit + +Perl_newSV.exit: ; preds = %bb1.i, %bb.i + br i1 undef, label %bb31, label %bb34 + +bb31: ; preds = %Perl_newSV.exit + ret void + +bb34: ; preds = %Perl_newSV.exit + unreachable +} + +define fastcc void @Perl_newXS_SPEC4() nounwind ssp { +entry: + %tmp53 = load %struct.SV** @PL_sv_root, align 8 ; <%struct.SV*> [#uses=1] + br i1 undef, label %bb1.i, label %bb.i + +bb.i: ; preds = %entry + %tmp64 = bitcast %struct.SV* %tmp53 to %struct.CV* ; <%struct.CV*> [#uses=1] + %tmp76 = getelementptr inbounds %struct.CV* %tmp64, i64 0, i32 0 ; <%struct.XPVCV**> [#uses=1] + br i1 undef, label %bb26, label %bb25 + +bb1.i: ; preds = %entry + unreachable + +bb25: ; preds = %bb.i + br label %bb26 + +bb26: ; preds = %bb25, %bb.i + %tmp86 = load %struct.XPVCV** %tmp76, align 8 ; <%struct.XPVCV*> [#uses=1] + %tmp87 = getelementptr inbounds %struct.XPVCV* %tmp86, i64 0, i32 10 ; [#uses=1] + store void (%struct.CV*)* @XS_MD5_digest, void (%struct.CV*)** %tmp87, align 8 + br i1 undef, label %bb30, label %bb28 + +bb28: ; preds = %bb26 + br label %bb30 + +bb30: ; preds = %bb28, %bb26 + unreachable +} Added: poolalloc/trunk/test/dsa/regression/2010-07-16.SimpleLoop.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/regression/2010-07-16.SimpleLoop.ll?rev=108576&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/regression/2010-07-16.SimpleLoop.ll (added) +++ poolalloc/trunk/test/dsa/regression/2010-07-16.SimpleLoop.ll Fri Jul 16 18:53:04 2010 @@ -0,0 +1,680 @@ +;dsaopt %s -dsa-eq -disable-output +; I have no idea, but as formulated above dsa works. But compile it into +; .bc and then things happen. Not going to investigate now. +;RUN: llvm-as %s -o - | dsaopt -dsa-eq -disable-output +; ModuleID = 'bugpoint-reduced-simplified.bc' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.4" + +%struct.AV = type { %struct.XPVAV*, i32, i32 } +%struct.COP = type { %struct.OP*, %struct.OP*, %struct.OP* ()*, i32, i16, i16, i8, i8, i8*, %struct.HV*, %struct.GV*, i32, i32, i16 } +%struct.CV = type { %struct.XPVCV*, i32, i32 } +%struct.DIR = type { i32, i64, i64, i8*, i32, i64, i64, i32, %struct.__darwin_pthread_mutex_t, %struct._telldir* } +%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 } +%struct.GP = type { %struct.SV*, i32, %struct.io*, %struct.CV*, %struct.AV*, %struct.HV*, %struct.GV*, %struct.CV*, i32, i32, i16, %struct.GV* } +%struct.GV = type { %struct.XPVGV*, i32, i32 } +%struct.HE = type { %struct.HE*, %struct.HEK*, %struct.SV* } +%struct.HEK = type { i32, i32, [1 x i8] } +%struct.HV = type { %struct.XPVHV*, i32, i32 } +%struct.MAGIC = type { %struct.MAGIC*, %struct.MGVTBL*, i16, i8, i8, %struct.SV*, i8*, i32 } +%struct.MGVTBL = type { i32 (%struct.SV*, %struct.MAGIC*)*, i32 (%struct.SV*, %struct.MAGIC*)*, i32 (%struct.SV*, %struct.MAGIC*)*, i32 (%struct.SV*, %struct.MAGIC*)*, i32 (%struct.SV*, %struct.MAGIC*)* } +%struct.OP = type { %struct.OP*, %struct.OP*, %struct.OP* ()*, i32, i16, i16, i8, i8 } +%struct.PMOP = type { %struct.OP*, %struct.OP*, %struct.OP* ()*, i32, i16, i16, i8, i8, %struct.OP*, %struct.OP*, i32, %struct.OP*, %struct.OP*, %struct.PMOP*, %struct.REGEXP*, i16, i16, i8 } +%struct.REGEXP = type { i32, i8**, i8**, %struct.regnode*, i32, i32, i32, i32, i8*, i8*, i8*, i8*, i16, i16, %struct.reg_substr_data*, %struct.reg_data*, [1 x %struct.regnode] } +%struct.SV = type { i8*, i32, i32 } +%struct.XPVAV = type { i8*, i64, i64, i64, double, %struct.MAGIC*, %struct.HV*, %struct.SV**, %struct.SV*, i8 } +%struct.XPVCV = type { i8*, i64, i64, i64, double, %struct.MAGIC*, %struct.HV*, %struct.HV*, %struct.OP*, %struct.OP*, void (%struct.CV*)*, %union.ANY, %struct.GV*, %struct.GV*, i64, %struct.AV*, %struct.CV*, i16 } +%struct.XPVGV = type { i8*, i64, i64, i64, double, %struct.MAGIC*, %struct.HV*, %struct.GP*, i8*, i64, %struct.HV*, i8 } +%struct.XPVHV = type { i8*, i64, i64, i64, double, %struct.MAGIC*, %struct.HV*, i32, %struct.HE*, %struct.PMOP*, i8* } +%struct.XPVIO = type { i8*, i64, i64, i64, double, %struct.MAGIC*, %struct.HV*, %struct.FILE*, %struct.FILE*, %struct.DIR*, i64, i64, i64, i64, i8*, %struct.GV*, i8*, %struct.GV*, i8*, %struct.GV*, i16, i8, i8 } +%struct.__darwin_pthread_mutex_t = type { i64, [56 x i8] } +%struct.__sFILEX = type opaque +%struct.__sbuf = type { i8*, i32 } +%struct.__va_list_tag = type { i32, i32, i8*, i8* } +%struct._telldir = type opaque +%struct.io = type { %struct.XPVIO*, i32, i32 } +%struct.reg_data = type { i32, i8*, [1 x i8*] } +%struct.reg_substr_data = type { [3 x %struct.reg_substr_datum] } +%struct.reg_substr_datum = type { i32, i32, %struct.SV* } +%struct.regnode = type { i8, i8, i16 } +%union.ANY = type { i8* } + + at PL_sv_undef = external global %struct.SV, align 16 ; <%struct.SV*> [#uses=1] + at PL_sv_no = external global %struct.SV, align 16 ; <%struct.SV*> [#uses=1] + at PL_sv_yes = external global %struct.SV, align 16 ; <%struct.SV*> [#uses=2] + at PL_lex_casestack = external global i8* ; [#uses=2] + at PL_sv_root = external global %struct.SV* ; <%struct.SV**> [#uses=3] + at PL_savestack = external global %union.ANY* ; <%union.ANY**> [#uses=2] + +define fastcc i8* @Perl_scan_word(i8* %s, i8* %dest, i64 %destlen, i32 %allow_package, i64* nocapture %slp) nounwind ssp { +entry: + unreachable +} + +define fastcc void @Perl_yyerror(i8* %s) nounwind ssp { +entry: + unreachable +} + +define fastcc i32 @Perl_start_subparse(i32 %is_format, i32 %flags) nounwind ssp { +entry: + unreachable +} + +define fastcc void @Perl_check_uni() nounwind ssp { +entry: + ret void +} + +define fastcc %struct.SV* @new_constant(i8* %s, i64 %len, i8* %key, %struct.SV* %sv, %struct.SV* %pv, i8* %type) nounwind ssp { +entry: + unreachable +} + +define fastcc i8* @Perl_scan_num(i8* %start) nounwind ssp { +entry: + unreachable +} + +define fastcc i32 @Perl_keyword(i8* %d, i32 %len) nounwind ssp { +entry: + unreachable +} + +define fastcc void @Perl_force_ident(i8* %s, i32 %kind) nounwind ssp { +entry: + ret void +} + +define fastcc void @Perl_no_op(i8* %what, i8* %s) nounwind ssp { +entry: + unreachable +} + +define void @restore_rsfp(i8* %f) nounwind ssp { +entry: + ret void +} + +define fastcc void @Perl_checkcomma(i8* %s, i8* %what) nounwind ssp { +entry: + unreachable +} + +define fastcc %struct.SV* @tokeq(%struct.SV* %sv) nounwind ssp { +entry: + unreachable +} + +define fastcc i32 @sublex_start() nounwind ssp { +entry: + unreachable +} + +define fastcc void @incline(i8* %s) nounwind ssp { +entry: + unreachable +} + +define fastcc void @missingterm(i8* %s) nounwind ssp { +entry: + unreachable +} + +define fastcc i32 @Perl_filter_read(i32 %idx, %struct.SV* %buf_sv) nounwind ssp { +entry: + unreachable +} + +define fastcc i8* @filter_gets(%struct.SV* %sv, %struct.FILE* nocapture %fp) nounwind ssp { +entry: + unreachable +} + +define fastcc i8* @Perl_skipspace(i8* %s) nounwind ssp { +entry: + unreachable +} + +define fastcc i8* @Perl_scan_ident(i8* %s, i8* %send, i8* %dest, i64 %destlen, i32 %ck_uni) nounwind ssp { +entry: + unreachable +} + +define fastcc i32 @Perl_intuit_more(i8* %s) nounwind ssp { +entry: + unreachable +} + +define fastcc i32 @intuit_method(i8* %start, %struct.GV* %gv) nounwind ssp { +entry: + unreachable +} + +define fastcc i8* @Perl_scan_str(i8* %start) nounwind ssp { +entry: + unreachable +} + +define fastcc i8* @Perl_scan_pat(i8* %start, i32 %type) nounwind ssp { +entry: + unreachable +} + +define fastcc i8* @Perl_scan_trans(i8* %start) nounwind ssp { +entry: + unreachable +} + +define fastcc i8* @Perl_force_word(i8* %start, i32 %token, i32 %check_keyword, i32 %allow_pack, i32 %allow_initial_tick) nounwind ssp { +entry: + unreachable +} + +define fastcc i8* @force_version(i8* %s) nounwind ssp { +entry: + unreachable +} + +define fastcc i32 @lop(i32 %f, i32 %x, i8* %s) nounwind ssp { +entry: + br i1 undef, label %bb, label %bb2 + +bb: ; preds = %entry + unreachable + +bb2: ; preds = %entry + ret i32 286 +} + +define fastcc i32 @Perl_yylex() nounwind ssp { +entry: + unreachable +} + +define fastcc i32 @sublex_done() nounwind ssp { +entry: + unreachable +} + +define fastcc void @Perl_lex_start(%struct.SV* %line) nounwind ssp { +entry: + br i1 undef, label %bb.i, label %entry.Perl_save_I32.exit_crit_edge + +entry.Perl_save_I32.exit_crit_edge: ; preds = %entry + br i1 undef, label %bb.i2, label %Perl_save_I32.exit3 + +bb.i: ; preds = %entry + unreachable + +bb.i2: ; preds = %entry.Perl_save_I32.exit_crit_edge + unreachable + +Perl_save_I32.exit3: ; preds = %entry.Perl_save_I32.exit_crit_edge + br i1 undef, label %bb.i5, label %Perl_save_I32.exit6 + +bb.i5: ; preds = %Perl_save_I32.exit3 + unreachable + +Perl_save_I32.exit6: ; preds = %Perl_save_I32.exit3 + br i1 undef, label %bb.i8, label %Perl_save_I32.exit9 + +bb.i8: ; preds = %Perl_save_I32.exit6 + unreachable + +Perl_save_I32.exit9: ; preds = %Perl_save_I32.exit6 + br i1 undef, label %bb.i11, label %Perl_save_I32.exit12 + +bb.i11: ; preds = %Perl_save_I32.exit9 + br label %Perl_save_I32.exit12 + +Perl_save_I32.exit12: ; preds = %bb.i11, %Perl_save_I32.exit9 + br i1 undef, label %bb.i14, label %Perl_save_I32.exit15 + +bb.i14: ; preds = %Perl_save_I32.exit12 + %tmp137 = bitcast i8* undef to %union.ANY* ; <%union.ANY*> [#uses=2] + store %union.ANY* %tmp137, %union.ANY** @PL_savestack, align 8 + br label %Perl_save_I32.exit15 + +Perl_save_I32.exit15: ; preds = %bb.i14, %Perl_save_I32.exit12 + %tmp139 = phi %union.ANY* [ undef, %Perl_save_I32.exit12 ], [ %tmp137, %bb.i14 ] ; <%union.ANY*> [#uses=2] + br i1 undef, label %bb.i16, label %Perl_save_sptr.exit + +bb.i16: ; preds = %Perl_save_I32.exit15 + unreachable + +Perl_save_sptr.exit: ; preds = %Perl_save_I32.exit15 + br i1 undef, label %bb.i18, label %Perl_save_I32.exit19 + +bb.i18: ; preds = %Perl_save_sptr.exit + unreachable + +Perl_save_I32.exit19: ; preds = %Perl_save_sptr.exit + %tmp203 = getelementptr inbounds %struct.COP* undef, i64 0, i32 13 ; [#uses=1] + br i1 undef, label %bb.i1, label %Perl_save_I16.exit + +bb.i1: ; preds = %Perl_save_I32.exit19 + unreachable + +Perl_save_I16.exit: ; preds = %Perl_save_I32.exit19 + %tmp223 = getelementptr inbounds %union.ANY* %tmp139, i64 undef, i32 0 ; [#uses=1] + %tmp224 = bitcast i16* %tmp203 to i8* ; [#uses=1] + store i8* %tmp224, i8** %tmp223, align 8 + br i1 undef, label %bb.i6, label %Perl_save_pptr.exit + +bb.i6: ; preds = %Perl_save_I16.exit + unreachable + +Perl_save_pptr.exit: ; preds = %Perl_save_I16.exit + br i1 undef, label %bb.i10, label %Perl_save_pptr.exit11 + +bb.i10: ; preds = %Perl_save_pptr.exit + unreachable + +Perl_save_pptr.exit11: ; preds = %Perl_save_pptr.exit + br i1 false, label %bb.i15, label %Perl_save_pptr.exit16 + +bb.i15: ; preds = %Perl_save_pptr.exit11 + unreachable + +Perl_save_pptr.exit16: ; preds = %Perl_save_pptr.exit11 + br i1 undef, label %bb.i20, label %Perl_save_pptr.exit21 + +bb.i20: ; preds = %Perl_save_pptr.exit16 + unreachable + +Perl_save_pptr.exit21: ; preds = %Perl_save_pptr.exit16 + br i1 undef, label %bb.i26, label %Perl_save_pptr.exit27 + +bb.i26: ; preds = %Perl_save_pptr.exit21 + unreachable + +Perl_save_pptr.exit27: ; preds = %Perl_save_pptr.exit21 + br i1 undef, label %bb.i21, label %Perl_save_sptr.exit22 + +bb.i21: ; preds = %Perl_save_pptr.exit27 + unreachable + +Perl_save_sptr.exit22: ; preds = %Perl_save_pptr.exit27 + br i1 undef, label %bb.i32, label %Perl_save_pptr.exit33 + +bb.i32: ; preds = %Perl_save_sptr.exit22 + unreachable + +Perl_save_pptr.exit33: ; preds = %Perl_save_sptr.exit22 + br i1 undef, label %bb.i37, label %Perl_save_pptr.exit38 + +bb.i37: ; preds = %Perl_save_pptr.exit33 + br label %Perl_save_pptr.exit38 + +Perl_save_pptr.exit38: ; preds = %bb.i37, %Perl_save_pptr.exit33 + %tmp404 = phi %union.ANY* [ undef, %bb.i37 ], [ %tmp139, %Perl_save_pptr.exit33 ] ; <%union.ANY*> [#uses=3] + %tmp407 = load i8** @PL_lex_casestack, align 8 ; [#uses=1] + %tmp408 = getelementptr inbounds %union.ANY* %tmp404, i64 undef, i32 0 ; [#uses=1] + store i8* %tmp407, i8** %tmp408, align 8 + %tmp411 = getelementptr inbounds %union.ANY* %tmp404, i64 undef, i32 0 ; [#uses=1] + store i8* bitcast (i8** @PL_lex_casestack to i8*), i8** %tmp411, align 8 + br i1 undef, label %bb.i23, label %Perl_save_destructor.exit + +bb.i23: ; preds = %Perl_save_pptr.exit38 + unreachable + +Perl_save_destructor.exit: ; preds = %Perl_save_pptr.exit38 + %tmp433 = getelementptr inbounds %union.ANY* %tmp404, i64 undef, i32 0 ; [#uses=1] + store i8* bitcast (void (i8*)* @restore_rsfp to i8*), i8** %tmp433 + br i1 undef, label %bb.i25, label %Perl_save_sptr.exit26 + +bb.i25: ; preds = %Perl_save_destructor.exit + unreachable + +Perl_save_sptr.exit26: ; preds = %Perl_save_destructor.exit + unreachable +} + +define fastcc signext i8 @Perl_sv_derived_from(%struct.SV* %sv, i8* %name) nounwind ssp { +entry: + br i1 undef, label %bb1, label %bb + +bb: ; preds = %entry + unreachable + +bb1: ; preds = %entry + br i1 undef, label %bb10, label %bb8 + +bb8: ; preds = %bb1 + %tmp41 = call fastcc %struct.SV* @isa_lookup(%struct.HV* undef, i8* %name, i32 undef, i32 0) nounwind ssp ; <%struct.SV*> [#uses=0] + ret i8 undef + +bb10: ; preds = %bb1 + ret i8 0 +} + +define void @XS_UNIVERSAL_isa(%struct.CV* nocapture %cv) nounwind ssp { +entry: + br i1 undef, label %bb1, label %bb + +bb: ; preds = %entry + unreachable + +bb1: ; preds = %entry + br i1 undef, label %bb3, label %bb2 + +bb2: ; preds = %bb1 + %tmp38 = call fastcc signext i8 @Perl_sv_derived_from(%struct.SV* undef, i8* undef) nounwind ; [#uses=0] + %storemerge1 = select i1 undef, %struct.SV* @PL_sv_no, %struct.SV* @PL_sv_yes ; <%struct.SV*> [#uses=0] + ret void + +bb3: ; preds = %bb1 + unreachable +} + +define void @XS_UNIVERSAL_can(%struct.CV* nocapture %cv) nounwind ssp { +entry: + unreachable +} + +define void @XS_UNIVERSAL_VERSION(%struct.CV* nocapture %cv) nounwind ssp { +entry: + unreachable +} + +define fastcc %struct.SV* @isa_lookup(%struct.HV* %stash, i8* %name, i32 %len, i32 %level) nounwind ssp { +entry: + br i1 undef, label %bb36, label %bb1 + +bb1: ; preds = %entry + br i1 undef, label %bb36, label %bb3 + +bb3: ; preds = %bb1 + br i1 undef, label %bb4, label %bb5 + +bb4: ; preds = %bb3 + unreachable + +bb5: ; preds = %bb3 + br i1 undef, label %bb32, label %bb12 + +bb12: ; preds = %bb5 + br i1 undef, label %bb32, label %bb13 + +bb13: ; preds = %bb12 + br i1 undef, label %bb32, label %bb14 + +bb14: ; preds = %bb13 + br i1 undef, label %bb15, label %bb21 + +bb15: ; preds = %bb14 + unreachable + +bb21: ; preds = %bb14 + br i1 undef, label %bb32, label %bb22 + +bb22: ; preds = %bb21 + br i1 undef, label %bb31, label %bb24 + +bb24: ; preds = %bb22 + br i1 false, label %bb27, label %bb28 + +bb27: ; preds = %bb24 + unreachable + +bb28: ; preds = %bb24 + %tmp87 = call fastcc %struct.SV* @isa_lookup(%struct.HV* undef, i8* %name, i32 %len, i32 undef) nounwind ssp ; <%struct.SV*> [#uses=0] + unreachable + +bb31: ; preds = %bb22 + unreachable + +bb32: ; preds = %bb21, %bb13, %bb12, %bb5 + ret %struct.SV* undef + +bb36: ; preds = %bb1, %entry + %.0 = phi %struct.SV* [ @PL_sv_undef, %entry ], [ @PL_sv_yes, %bb1 ] ; <%struct.SV*> [#uses=1] + ret %struct.SV* %.0 +} + +define fastcc i8* @Perl_screaminstr(%struct.SV* nocapture %bigstr, %struct.SV* nocapture %littlestr, i32 %start_shift, i32 %end_shift, i32* nocapture %old_posp, i32 %last) nounwind ssp { +entry: + unreachable +} + +define void @sig_trap(i32 %signo) nounwind ssp { +entry: + ret void +} + +define fastcc i8* @Perl_fbm_instr(i8* %big, i8* %bigend, %struct.SV* %littlestr) nounwind ssp { +entry: + unreachable +} + +define fastcc void @Perl_fbm_compile(%struct.SV* %sv) nounwind ssp { +entry: + unreachable +} + +define fastcc i8* @Perl_mess(i8* %pat, [1 x %struct.__va_list_tag]* %args) nounwind ssp { +entry: + unreachable +} + +define void @Perl_warn(i8* %pat, ...) nounwind ssp { +entry: + br i1 undef, label %bb17, label %bb + +bb: ; preds = %entry + br i1 undef, label %bb.i1, label %Perl_pop_scope.exit + +bb.i1: ; preds = %bb + unreachable + +Perl_pop_scope.exit: ; preds = %bb + br i1 undef, label %bb17, label %bb5 + +bb5: ; preds = %Perl_pop_scope.exit + br i1 undef, label %bb6, label %bb17 + +bb6: ; preds = %bb5 + br i1 undef, label %bb.i2, label %bb8.Perl_push_scope.exit3_crit_edge + +bb8.Perl_push_scope.exit3_crit_edge: ; preds = %bb6 + %tmp86 = load %struct.SV** @PL_sv_root, align 8 ; <%struct.SV*> [#uses=1] + br i1 undef, label %bb1.i, label %bb.i5 + +bb.i2: ; preds = %bb6 + unreachable + +bb.i5: ; preds = %bb8.Perl_push_scope.exit3_crit_edge + br label %Perl_newSVpv.exit + +bb1.i: ; preds = %bb8.Perl_push_scope.exit3_crit_edge + br label %Perl_newSVpv.exit + +Perl_newSVpv.exit: ; preds = %bb1.i, %bb.i5 + %sv.0.i = phi %struct.SV* [ undef, %bb1.i ], [ %tmp86, %bb.i5 ] ; <%struct.SV*> [#uses=1] + br i1 undef, label %bb.i4, label %Perl_push_scope.exit3.Perl_save_freesv.exit_crit_edge + +Perl_push_scope.exit3.Perl_save_freesv.exit_crit_edge: ; preds = %Perl_newSVpv.exit + %.pre14 = load %union.ANY** @PL_savestack, align 8 ; <%union.ANY*> [#uses=1] + %tmp116 = getelementptr inbounds %union.ANY* %.pre14, i64 undef, i32 0 ; [#uses=1] + %tmp117 = bitcast %struct.SV* %sv.0.i to i8* ; [#uses=1] + store i8* %tmp117, i8** %tmp116, align 8 + br i1 undef, label %bb9, label %bb10 + +bb.i4: ; preds = %Perl_newSVpv.exit + unreachable + +bb9: ; preds = %Perl_push_scope.exit3.Perl_save_freesv.exit_crit_edge + unreachable + +bb10: ; preds = %Perl_push_scope.exit3.Perl_save_freesv.exit_crit_edge + unreachable + +bb17: ; preds = %bb5, %Perl_pop_scope.exit, %entry + ret void +} + +define fastcc i64 @Perl_scan_hex(i8* %start, i32 %len, i32* nocapture %retlen) nounwind ssp { +entry: + unreachable +} + +define fastcc i64 @Perl_scan_oct(i8* nocapture %start, i32 %len, i32* nocapture %retlen) nounwind ssp { +entry: + unreachable +} + +define void @Perl_croak(i8* %pat, ...) nounwind ssp { +entry: + unreachable +} + +define fastcc i32 @Perl_wait4pid(i32 %pid, i32* %statusp, i32 %flags) nounwind ssp { +entry: + unreachable +} + +define fastcc i32 @Perl_my_pclose(%struct.FILE* nocapture %ptr) nounwind ssp { +entry: + unreachable +} + +define fastcc %struct.FILE* @Perl_my_popen(i8* %cmd, i8* %mode) nounwind ssp { +entry: + unreachable +} + +define %struct.OP* @Perl_die(i8* %pat, ...) nounwind ssp { +entry: + unreachable +} + +define i8* @Perl_form(i8* %pat, ...) nounwind ssp { +entry: + unreachable +} + +define fastcc i8* @Perl_savepvn(i8* %sv, i32 %len) nounwind ssp { +entry: + unreachable +} + +define fastcc i8* @Perl_savepv(i8* %sv) nounwind ssp { +entry: + ret i8* undef +} + +define fastcc i8* @Perl_saferealloc(i8* %where, i64 %size) nounwind ssp { +entry: + unreachable +} + +define fastcc void @Perl_my_setenv(i8* %nam, i8* %val) nounwind ssp { +entry: + br i1 undef, label %Perl_setenv_getix.exit, label %bb.i5 + +bb.i5: ; preds = %entry + unreachable + +Perl_setenv_getix.exit: ; preds = %entry + unreachable +} + +define void @Perl_magic_get_DIRECT(%struct.SV* %sv, %struct.MAGIC* nocapture %mg) nounwind ssp { +entry: + unreachable +} + +define %struct.OP* @Perl_ck_sort_DIRECT(%struct.OP* %o) nounwind ssp { +entry: + unreachable +} + +define %struct.OP* @Perl_ck_subr_DIRECT(%struct.OP* %o) nounwind ssp { +entry: + unreachable +} + +define %struct.OP* @Perl_ck_fun_DIRECT(%struct.OP* %o) nounwind ssp { +entry: + ret %struct.OP* %o +} + +define void @Perl_pp_anonlist_DIRECT() nounwind ssp { +entry: + unreachable +} + +define %struct.OP* @Perl_pp_entereval_DIRECT() nounwind ssp { +entry: + unreachable +} + +define %struct.OP* @Perl_pp_require_DIRECT() nounwind ssp { +entry: + unreachable +} + +define %struct.OP* @Perl_pp_goto_DIRECT() nounwind ssp { +entry: + unreachable +} + +define fastcc void @Perl_newXS_SPEC1() nounwind ssp { +entry: + unreachable +} + +define fastcc void @Perl_newXS_SPEC2() nounwind ssp { +entry: + unreachable +} + +define fastcc void @Perl_newXS_SPEC3() nounwind ssp { +entry: + unreachable +} + +define fastcc void @Perl_newXS_SPEC4() nounwind ssp { +entry: + unreachable +} + +define fastcc void @Perl_newXS_SPEC5() nounwind ssp { +entry: + %tmp53 = load %struct.SV** @PL_sv_root, align 8 ; <%struct.SV*> [#uses=1] + br i1 undef, label %bb1.i, label %bb.i + +bb.i: ; preds = %entry + %tmp64 = bitcast %struct.SV* %tmp53 to %struct.CV* ; <%struct.CV*> [#uses=1] + %tmp76 = getelementptr inbounds %struct.CV* %tmp64, i64 0, i32 0 ; <%struct.XPVCV**> [#uses=1] + %tmp86 = load %struct.XPVCV** %tmp76, align 8 ; <%struct.XPVCV*> [#uses=1] + %tmp87 = getelementptr inbounds %struct.XPVCV* %tmp86, i64 0, i32 10 ; [#uses=1] + store void (%struct.CV*)* @XS_UNIVERSAL_isa, void (%struct.CV*)** %tmp87, align 8 + unreachable + +bb1.i: ; preds = %entry + unreachable +} + +define fastcc void @Perl_newXS_SPEC7() nounwind ssp { +entry: + %tmp53 = load %struct.SV** @PL_sv_root, align 8 ; <%struct.SV*> [#uses=1] + br i1 undef, label %bb1.i, label %bb.i + +bb.i: ; preds = %entry + %tmp64 = bitcast %struct.SV* %tmp53 to %struct.CV* ; <%struct.CV*> [#uses=1] + %tmp76 = getelementptr inbounds %struct.CV* %tmp64, i64 0, i32 0 ; <%struct.XPVCV**> [#uses=1] + %tmp86 = load %struct.XPVCV** %tmp76, align 8 ; <%struct.XPVCV*> [#uses=1] + %tmp87 = getelementptr inbounds %struct.XPVCV* %tmp86, i64 0, i32 10 ; [#uses=1] + store void (%struct.CV*)* @XS_UNIVERSAL_VERSION, void (%struct.CV*)** %tmp87, align 8 + unreachable + +bb1.i: ; preds = %entry + unreachable +} + +define fastcc void @Perl_newXS_SPEC9() nounwind ssp { +entry: + unreachable +} From wdietz2 at illinois.edu Fri Jul 16 19:02:12 2010 From: wdietz2 at illinois.edu (Will Dietz) Date: Sat, 17 Jul 2010 00:02:12 -0000 Subject: [llvm-commits] [poolalloc] r108577 - /poolalloc/trunk/lib/DSA/CompleteBottomUp.cpp Message-ID: <20100717000212.6C6402A6C12C@llvm.org> Author: wdietz2 Date: Fri Jul 16 19:02:12 2010 New Revision: 108577 URL: http://llvm.org/viewvc/llvm-project?rev=108577&view=rev Log: In CBU, be robust to callee's that don't exist. Additionally added sanity check that we have entries that we expect to have. Modified: poolalloc/trunk/lib/DSA/CompleteBottomUp.cpp Modified: poolalloc/trunk/lib/DSA/CompleteBottomUp.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/CompleteBottomUp.cpp?rev=108577&r1=108576&r2=108577&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/CompleteBottomUp.cpp (original) +++ poolalloc/trunk/lib/DSA/CompleteBottomUp.cpp Fri Jul 16 19:02:12 2010 @@ -51,16 +51,48 @@ //mege nodes in the global graph for these functions for (DSCallGraph::callee_key_iterator ii = callgraph.key_begin(), ee = callgraph.key_end(); ii != ee; ++ii) { + +#ifndef NDEBUG + // --Verify that for every callee of an indirect function call + // we have an entry in the GlobalsGraph + bool isIndirect = ((*ii).getCalledFunction() == NULL); + + if (isIndirect) { + DSCallGraph::callee_iterator csii = callgraph.callee_begin(*ii), + csee = callgraph.callee_end(*ii); + + for (; csii != csee; ++csii) { + // Declarations don't have to have entries + if(!(*csii)->isDeclaration()) + assert(SM.count(*csii) && "Indirect function callee not in globals?"); + } + + } +#endif + // FIXME: Given the above is a valid assertion, we could probably replace + // this code with something that *assumes* we have entries. However because + // I'm not convinced that we can just *skip* direct calls in this function + // this code is careful to handle callees not existing in the globals graph + // In other words what we have here should be correct, but might be overkill + // that we can trim down later as needed. + DSCallGraph::callee_iterator csi = callgraph.callee_begin(*ii), cse = callgraph.callee_end(*ii); - if (csi != cse && SM.find(*csi) != SM.end()) { - assert((SM.find(*csi) != SM.end()) && "Function not in Global graph?"); - DSNodeHandle& SrcNH = SM.find(*csi)->second; + + // Grab the first callee we have an entry for... + while (csi != cse && !SM.count(*csi)) ++csi; - for (; csi != cse; ++csi) { - assert((SM.find(*csi) != SM.end()) && "Function not in Global graph?"); + + // If we have no entries, we're done. + if (csi == cse) break; + + DSNodeHandle& SrcNH = SM.find(*csi)->second; + + // Merge the rest of the callees (that we have entries for) together + // with the first one. + for (; csi != cse; ++csi) { + if (SM.count(*csi)) SrcNH.mergeWith(SM.find(*csi)->second); - } } } } From echristo at apple.com Fri Jul 16 19:25:41 2010 From: echristo at apple.com (Eric Christopher) Date: Sat, 17 Jul 2010 00:25:41 -0000 Subject: [llvm-commits] [llvm] r108581 - /llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Message-ID: <20100717002541.F25152A6C12C@llvm.org> Author: echristo Date: Fri Jul 16 19:25:41 2010 New Revision: 108581 URL: http://llvm.org/viewvc/llvm-project?rev=108581&view=rev Log: Make comment a bit more clear as well as return statement since needsStackRealignment is currently checking the can conditions as well. Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=108581&r1=108580&r2=108581&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Fri Jul 16 19:25:41 2010 @@ -462,12 +462,12 @@ // FIXME: Currently we don't support stack realignment for functions with // variable-sized allocas. - // FIXME: Temporary disable the error - it seems to be too conservative. + // FIXME: It's more complicated than this... if (0 && requiresRealignment && MFI->hasVarSizedObjects()) report_fatal_error( "Stack realignment in presense of dynamic allocas is not supported"); - return (requiresRealignment && !MFI->hasVarSizedObjects()); + return requiresRealignment && canRealignStack(MF); } bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const { From echristo at apple.com Fri Jul 16 19:27:24 2010 From: echristo at apple.com (Eric Christopher) Date: Sat, 17 Jul 2010 00:27:24 -0000 Subject: [llvm-commits] [llvm] r108582 - /llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Message-ID: <20100717002724.D7D932A6C12C@llvm.org> Author: echristo Date: Fri Jul 16 19:27:24 2010 New Revision: 108582 URL: http://llvm.org/viewvc/llvm-project?rev=108582&view=rev Log: Make more explicit and add some currently disabled error messages for stack realignment on ARM. Also check for function attributes as we do on X86 as well as make explicit that we're checking can as well as needs in this function. Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=108582&r1=108581&r2=108582&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Fri Jul 16 19:27:24 2010 @@ -627,12 +627,26 @@ bool ARMBaseRegisterInfo:: needsStackRealignment(const MachineFunction &MF) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); + const Function *F = MF.getFunction(); const ARMFunctionInfo *AFI = MF.getInfo(); unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); - return (RealignStack && - !AFI->isThumb1OnlyFunction() && - (MFI->getMaxAlignment() > StackAlign) && - !MFI->hasVarSizedObjects()); + bool requiresRealignment = + RealignStack && ((MFI->getMaxAlignment() > StackAlign) || + F->hasFnAttr(Attribute::StackAlignment)); + + // FIXME: Currently we don't support stack realignment for functions with + // variable-sized allocas. + // FIXME: It's more complicated than this... + if (0 && requiresRealignment && MFI->hasVarSizedObjects()) + report_fatal_error( + "Stack realignment in presense of dynamic allocas is not supported"); + + // FIXME: This probably isn't the right place for this. + if (0 && requiresRealignment && AFI->isThumb1OnlyFunction()) + report_fatal_error( + "Stack realignment in thumb1 functions is not supported"); + + return requiresRealignment && canRealignStack(MF); } bool ARMBaseRegisterInfo:: From echristo at apple.com Fri Jul 16 19:28:22 2010 From: echristo at apple.com (Eric Christopher) Date: Sat, 17 Jul 2010 00:28:22 -0000 Subject: [llvm-commits] [llvm] r108583 - in /llvm/trunk: include/llvm/CodeGen/MachineFrameInfo.h lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Message-ID: <20100717002822.6EBC82A6C12C@llvm.org> Author: echristo Date: Fri Jul 16 19:28:22 2010 New Revision: 108583 URL: http://llvm.org/viewvc/llvm-project?rev=108583&view=rev Log: Propagate alloca alignment information via variable size object frame information. No functional change yet. Modified: llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Modified: llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h?rev=108583&r1=108582&r2=108583&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h Fri Jul 16 19:28:22 2010 @@ -417,9 +417,10 @@ /// variable sized object is created, whether or not the index returned is /// actually used. /// - int CreateVariableSizedObject() { + int CreateVariableSizedObject(unsigned Alignment) { HasVarSizedObjects = true; - Objects.push_back(StackObject(0, 1, 0, false, false)); + Objects.push_back(StackObject(0, Alignment, 0, false, false)); + MaxAlignment = std::max(MaxAlignment, Alignment); return (int)Objects.size()-NumFixedObjects-1; } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=108583&r1=108582&r2=108583&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Fri Jul 16 19:28:22 2010 @@ -2848,7 +2848,7 @@ // Inform the Frame Information that we have just allocated a variable-sized // object. - FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(); + FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1); } void SelectionDAGBuilder::visitLoad(const LoadInst &I) { From echristo at apple.com Fri Jul 16 19:33:05 2010 From: echristo at apple.com (Eric Christopher) Date: Sat, 17 Jul 2010 00:33:05 -0000 Subject: [llvm-commits] [llvm] r108588 - in /llvm/trunk/lib/Target: ARM/ARMBaseRegisterInfo.cpp X86/X86RegisterInfo.cpp Message-ID: <20100717003305.1A3C62A6C12C@llvm.org> Author: echristo Date: Fri Jul 16 19:33:04 2010 New Revision: 108588 URL: http://llvm.org/viewvc/llvm-project?rev=108588&view=rev Log: Remove unnecessary check that was subsumed into canRealignStack. Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=108588&r1=108587&r2=108588&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Fri Jul 16 19:33:04 2010 @@ -630,9 +630,8 @@ const Function *F = MF.getFunction(); const ARMFunctionInfo *AFI = MF.getInfo(); unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); - bool requiresRealignment = - RealignStack && ((MFI->getMaxAlignment() > StackAlign) || - F->hasFnAttr(Attribute::StackAlignment)); + bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) || + F->hasFnAttr(Attribute::StackAlignment)); // FIXME: Currently we don't support stack realignment for functions with // variable-sized allocas. Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=108588&r1=108587&r2=108588&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Fri Jul 16 19:33:04 2010 @@ -456,9 +456,8 @@ bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); const Function *F = MF.getFunction(); - bool requiresRealignment = - RealignStack && ((MFI->getMaxAlignment() > StackAlign) || - F->hasFnAttr(Attribute::StackAlignment)); + bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) || + F->hasFnAttr(Attribute::StackAlignment)); // FIXME: Currently we don't support stack realignment for functions with // variable-sized allocas. From grosbach at apple.com Fri Jul 16 20:22:19 2010 From: grosbach at apple.com (Jim Grosbach) Date: Sat, 17 Jul 2010 01:22:19 -0000 Subject: [llvm-commits] [llvm] r108601 - /llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Message-ID: <20100717012219.872752A6C12C@llvm.org> Author: grosbach Date: Fri Jul 16 20:22:19 2010 New Revision: 108601 URL: http://llvm.org/viewvc/llvm-project?rev=108601&view=rev Log: Fix logic think-o Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=108601&r1=108600&r2=108601&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri Jul 16 20:22:19 2010 @@ -4267,7 +4267,7 @@ if (!C) return SDValue(); unsigned Val = C->getZExtValue(); - if (ARM::isBitFieldInvertedMask(Mask) && (Val & ~Mask) != Val) + if (!ARM::isBitFieldInvertedMask(Mask) || (Val & ~Mask) != Val) return SDValue(); Val >>= CountTrailingZeros_32(~Mask); From grosbach at apple.com Fri Jul 16 20:50:57 2010 From: grosbach at apple.com (Jim Grosbach) Date: Sat, 17 Jul 2010 01:50:57 -0000 Subject: [llvm-commits] [llvm] r108603 - /llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Message-ID: <20100717015057.472EF2A6C12C@llvm.org> Author: grosbach Date: Fri Jul 16 20:50:57 2010 New Revision: 108603 URL: http://llvm.org/viewvc/llvm-project?rev=108603&view=rev Log: add BFI to getTargetNodeName() Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=108603&r1=108602&r2=108603&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri Jul 16 20:50:57 2010 @@ -641,6 +641,7 @@ case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR"; case ARMISD::FMAX: return "ARMISD::FMAX"; case ARMISD::FMIN: return "ARMISD::FMIN"; + case ARMISD::BFI: return "ARMISD::BFI"; } } From daniel at zuster.org Fri Jul 16 21:26:10 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Sat, 17 Jul 2010 02:26:10 -0000 Subject: [llvm-commits] [llvm] r108604 - in /llvm/trunk: include/llvm/MC/MCParser/AsmParser.h include/llvm/MC/MCParser/MCAsmParser.h lib/MC/MCParser/AsmParser.cpp lib/MC/MCParser/MCAsmParser.cpp Message-ID: <20100717022610.78A572A6C12C@llvm.org> Author: ddunbar Date: Fri Jul 16 21:26:10 2010 New Revision: 108604 URL: http://llvm.org/viewvc/llvm-project?rev=108604&view=rev Log: MC/AsmParser: Lift Run() and TargetParser to base class. Also, add constructor function for creating AsmParser instances. Modified: llvm/trunk/include/llvm/MC/MCParser/AsmParser.h llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h llvm/trunk/lib/MC/MCParser/AsmParser.cpp llvm/trunk/lib/MC/MCParser/MCAsmParser.cpp Modified: llvm/trunk/include/llvm/MC/MCParser/AsmParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/AsmParser.h?rev=108604&r1=108603&r2=108604&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCParser/AsmParser.h (original) +++ llvm/trunk/include/llvm/MC/MCParser/AsmParser.h Fri Jul 16 21:26:10 2010 @@ -46,7 +46,6 @@ SourceMgr &SrcMgr; MCAsmParserExtension *GenericParser; MCAsmParserExtension *PlatformParser; - TargetAsmParser *TargetParser; /// This is the current buffer index we're lexing from as managed by the /// SourceMgr object. @@ -65,7 +64,7 @@ const MCAsmInfo &MAI); ~AsmParser(); - bool Run(bool NoInitialTextSection, bool NoFinalize = false); + virtual bool Run(bool NoInitialTextSection, bool NoFinalize = false); void AddDirectiveHandler(MCAsmParserExtension *Object, StringRef Directive, @@ -74,9 +73,6 @@ } public: - TargetAsmParser &getTargetParser() const { return *TargetParser; } - void setTargetParser(TargetAsmParser &P); - /// @name MCAsmParser Interface /// { Modified: llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h?rev=108604&r1=108603&r2=108604&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h (original) +++ llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h Fri Jul 16 21:26:10 2010 @@ -14,6 +14,7 @@ namespace llvm { class AsmToken; +class MCAsmInfo; class MCAsmLexer; class MCAsmParserExtension; class MCContext; @@ -22,6 +23,8 @@ class SMLoc; class SourceMgr; class StringRef; +class Target; +class TargetAsmParser; class Twine; /// MCAsmParser - Generic assembler parser interface, for use by target specific @@ -33,6 +36,9 @@ private: MCAsmParser(const MCAsmParser &); // DO NOT IMPLEMENT void operator=(const MCAsmParser &); // DO NOT IMPLEMENT + + TargetAsmParser *TargetParser; + protected: // Can only create subclasses. MCAsmParser(); @@ -52,6 +58,12 @@ /// getStreamer - Return the output streamer for the assembler. virtual MCStreamer &getStreamer() = 0; + TargetAsmParser &getTargetParser() const { return *TargetParser; } + void setTargetParser(TargetAsmParser &P); + + /// Run - Run the parser on the input source buffer. + virtual bool Run(bool NoInitialTextSection, bool NoFinalize = false) = 0; + /// Warning - Emit a warning at the location \arg L, with the message \arg /// Msg. virtual void Warning(SMLoc L, const Twine &Msg) = 0; @@ -102,6 +114,10 @@ virtual bool ParseAbsoluteExpression(int64_t &Res) = 0; }; +/// \brief Create an MCAsmParser instance. +MCAsmParser *createMCAsmParser(const Target &, SourceMgr &, MCContext &, + MCStreamer &, const MCAsmInfo &); + } // End llvm namespace #endif Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=108604&r1=108603&r2=108604&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Fri Jul 16 21:26:10 2010 @@ -69,7 +69,7 @@ MCStreamer &_Out, const MCAsmInfo &_MAI) : Lexer(_MAI), Ctx(_Ctx), Out(_Out), SrcMgr(_SM), GenericParser(new GenericAsmParser), PlatformParser(0), - TargetParser(0), CurBuffer(0) { + CurBuffer(0) { Lexer.setBuffer(SrcMgr.getMemoryBuffer(CurBuffer)); // Initialize the generic parser. @@ -93,12 +93,6 @@ delete GenericParser; } -void AsmParser::setTargetParser(TargetAsmParser &P) { - assert(!TargetParser && "Target parser is already initialized!"); - TargetParser = &P; - TargetParser->Initialize(*this); -} - void AsmParser::Warning(SMLoc L, const Twine &Msg) { PrintMessage(L, Msg.str(), "warning"); } @@ -1487,3 +1481,10 @@ return false; } + +/// \brief Create an MCAsmParser instance. +MCAsmParser *llvm::createMCAsmParser(const Target &T, SourceMgr &SM, + MCContext &C, MCStreamer &Out, + const MCAsmInfo &MAI) { + return new AsmParser(T, SM, C, Out, MAI); +} Modified: llvm/trunk/lib/MC/MCParser/MCAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/MCAsmParser.cpp?rev=108604&r1=108603&r2=108604&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/MCAsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/MCAsmParser.cpp Fri Jul 16 21:26:10 2010 @@ -12,14 +12,21 @@ #include "llvm/MC/MCParser/MCAsmLexer.h" #include "llvm/MC/MCParser/MCParsedAsmOperand.h" #include "llvm/Support/SourceMgr.h" +#include "llvm/Target/TargetAsmParser.h" using namespace llvm; -MCAsmParser::MCAsmParser() { +MCAsmParser::MCAsmParser() : TargetParser(0) { } MCAsmParser::~MCAsmParser() { } +void MCAsmParser::setTargetParser(TargetAsmParser &P) { + assert(!TargetParser && "Target parser is already initialized!"); + TargetParser = &P; + TargetParser->Initialize(*this); +} + const AsmToken &MCAsmParser::getTok() { return getLexer().getTok(); } From eli.friedman at gmail.com Fri Jul 16 22:09:18 2010 From: eli.friedman at gmail.com (Eli Friedman) Date: Sat, 17 Jul 2010 03:09:18 -0000 Subject: [llvm-commits] [llvm] r108606 - /llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp Message-ID: <20100717030918.45E5F2A6C12C@llvm.org> Author: efriedma Date: Fri Jul 16 22:09:18 2010 New Revision: 108606 URL: http://llvm.org/viewvc/llvm-project?rev=108606&view=rev Log: Add support for parsing .size directives for ELF. Modified: llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp Modified: llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp?rev=108606&r1=108605&r2=108606&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp Fri Jul 16 22:09:18 2010 @@ -31,6 +31,8 @@ &ELFAsmParser::ParseSectionDirectiveData)); Parser.AddDirectiveHandler(this, ".text", MCAsmParser::DirectiveHandler( &ELFAsmParser::ParseSectionDirectiveText)); + Parser.AddDirectiveHandler(this, ".size", MCAsmParser::DirectiveHandler( + &ELFAsmParser::ParseSizeDirective)); } bool ParseSectionDirectiveData(StringRef, SMLoc) { @@ -43,6 +45,7 @@ MCSectionELF::SHF_EXECINSTR | MCSectionELF::SHF_ALLOC, SectionKind::getText()); } + bool ParseSizeDirective(StringRef, SMLoc); }; } @@ -59,6 +62,27 @@ return false; } +bool ELFAsmParser::ParseSizeDirective(StringRef, SMLoc) { + StringRef Name; + if (getParser().ParseIdentifier(Name)) + return TokError("expected identifier in directive"); + MCSymbol *Sym = getContext().GetOrCreateSymbol(Name);; + + if (getLexer().isNot(AsmToken::Comma)) + return TokError("unexpected token in directive"); + Lex(); + + const MCExpr *Expr; + if (getParser().ParseExpression(Expr)) + return true; + + if (getLexer().isNot(AsmToken::EndOfStatement)) + return TokError("unexpected token in directive"); + + getStreamer().EmitELFSize(Sym, Expr); + return false; +} + namespace llvm { MCAsmParserExtension *createELFAsmParser() { From eli.friedman at gmail.com Fri Jul 16 22:15:25 2010 From: eli.friedman at gmail.com (Eli Friedman) Date: Sat, 17 Jul 2010 03:15:25 -0000 Subject: [llvm-commits] [llvm] r108607 - /llvm/trunk/test/MC/AsmParser/directive_elf_size.s Message-ID: <20100717031525.1ECB72A6C12C@llvm.org> Author: efriedma Date: Fri Jul 16 22:15:24 2010 New Revision: 108607 URL: http://llvm.org/viewvc/llvm-project?rev=108607&view=rev Log: Test for ELF .size directive. Added: llvm/trunk/test/MC/AsmParser/directive_elf_size.s Added: llvm/trunk/test/MC/AsmParser/directive_elf_size.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/directive_elf_size.s?rev=108607&view=auto ============================================================================== --- llvm/trunk/test/MC/AsmParser/directive_elf_size.s (added) +++ llvm/trunk/test/MC/AsmParser/directive_elf_size.s Fri Jul 16 22:15:24 2010 @@ -0,0 +1,8 @@ +# RUN: llvm-mc -triple i386-pc-linux-gnu %s | FileCheck %s + +a: + ret +.Lt: +# CHECK: .size a, .Lt-a + .size a, .Lt-a + From grosbach at apple.com Fri Jul 16 22:30:54 2010 From: grosbach at apple.com (Jim Grosbach) Date: Sat, 17 Jul 2010 03:30:54 -0000 Subject: [llvm-commits] [llvm] r108608 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/README.txt test/CodeGen/ARM/bfi.ll test/CodeGen/Thumb2/bfi.ll Message-ID: <20100717033054.9DFE32A6C12C@llvm.org> Author: grosbach Date: Fri Jul 16 22:30:54 2010 New Revision: 108608 URL: http://llvm.org/viewvc/llvm-project?rev=108608&view=rev Log: Add combiner patterns to more effectively utilize the BFI (bitfield insert) instruction for non-constant operands. This includes the case referenced in the README.txt regarding a bitfield copy. Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/ARM/README.txt llvm/trunk/test/CodeGen/ARM/bfi.ll llvm/trunk/test/CodeGen/Thumb2/bfi.ll Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=108608&r1=108607&r2=108608&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri Jul 16 22:30:54 2010 @@ -4240,21 +4240,33 @@ static SDValue PerformORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) { + // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when + // reasonable. + // BFI is only available on V6T2+ if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops()) return SDValue(); SelectionDAG &DAG = DCI.DAG; SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); - // or (and A, mask), val => ARMbfi A, val, mask - // iff (val & mask) == val - if (N0->getOpcode() != ISD::AND) + DebugLoc DL = N->getDebugLoc(); + // 1) or (and A, mask), val => ARMbfi A, val, mask + // iff (val & mask) == val + // + // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask + // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2) + // && CountPopulation_32(mask) == CountPopulation_32(~mask2) + // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2) + // && CountPopulation_32(mask) == CountPopulation_32(~mask2) + // (i.e., copy a bitfield value into another bitfield of the same width) + if (N0.getOpcode() != ISD::AND) return SDValue(); EVT VT = N->getValueType(0); if (VT != MVT::i32) return SDValue(); + // The value and the mask need to be constants so we can verify this is // actually a bitfield set. If the mask is 0xffff, we can do better // via a movt instruction, so don't use BFI in that case. @@ -4264,21 +4276,61 @@ unsigned Mask = C->getZExtValue(); if (Mask == 0xffff) return SDValue(); - C = dyn_cast(N1); - if (!C) - return SDValue(); - unsigned Val = C->getZExtValue(); - if (!ARM::isBitFieldInvertedMask(Mask) || (Val & ~Mask) != Val) - return SDValue(); - Val >>= CountTrailingZeros_32(~Mask); + SDValue Res; + // Case (1): or (and A, mask), val => ARMbfi A, val, mask + if ((C = dyn_cast(N1))) { + unsigned Val = C->getZExtValue(); + if (!ARM::isBitFieldInvertedMask(Mask) || (Val & ~Mask) != Val) + return SDValue(); + Val >>= CountTrailingZeros_32(~Mask); - DebugLoc DL = N->getDebugLoc(); - SDValue Res = DAG.getNode(ARMISD::BFI, DL, VT, N0.getOperand(0), - DAG.getConstant(Val, MVT::i32), - DAG.getConstant(Mask, MVT::i32)); + Res = DAG.getNode(ARMISD::BFI, DL, VT, N0.getOperand(0), + DAG.getConstant(Val, MVT::i32), + DAG.getConstant(Mask, MVT::i32)); + + // Do not add new nodes to DAG combiner worklist. + DCI.CombineTo(N, Res, false); + } else if (N1.getOpcode() == ISD::AND) { + // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask + C = dyn_cast(N1.getOperand(1)); + if (!C) + return SDValue(); + unsigned Mask2 = C->getZExtValue(); - // Do not add new nodes to DAG combiner worklist. - DCI.CombineTo(N, Res, false); + if (ARM::isBitFieldInvertedMask(Mask) && + ARM::isBitFieldInvertedMask(~Mask2) && + (CountPopulation_32(Mask) == CountPopulation_32(~Mask2))) { + // The pack halfword instruction works better for masks that fit it, + // so use that when it's available. + if (Subtarget->hasT2ExtractPack() && + (Mask == 0xffff || Mask == 0xffff0000)) + return SDValue(); + // 2a + unsigned lsb = CountTrailingZeros_32(Mask2); + Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0), + DAG.getConstant(lsb, MVT::i32)); + Res = DAG.getNode(ARMISD::BFI, DL, VT, N0.getOperand(0), Res, + DAG.getConstant(Mask, MVT::i32)); + // Do not add new nodes to DAG combiner worklist. + DCI.CombineTo(N, Res, false); + } else if (ARM::isBitFieldInvertedMask(~Mask) && + ARM::isBitFieldInvertedMask(Mask2) && + (CountPopulation_32(~Mask) == CountPopulation_32(Mask2))) { + // The pack halfword instruction works better for masks that fit it, + // so use that when it's available. + if (Subtarget->hasT2ExtractPack() && + (Mask2 == 0xffff || Mask2 == 0xffff0000)) + return SDValue(); + // 2b + unsigned lsb = CountTrailingZeros_32(Mask); + Res = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), + DAG.getConstant(lsb, MVT::i32)); + Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res, + DAG.getConstant(Mask2, MVT::i32)); + // Do not add new nodes to DAG combiner worklist. + DCI.CombineTo(N, Res, false); + } + } return SDValue(); } Modified: llvm/trunk/lib/Target/ARM/README.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/README.txt?rev=108608&r1=108607&r2=108608&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/README.txt (original) +++ llvm/trunk/lib/Target/ARM/README.txt Fri Jul 16 22:30:54 2010 @@ -611,27 +611,6 @@ //===---------------------------------------------------------------------===// -Given the following on ARMv7: -int test1(int A, int B) { - return (A&-8388481)|(B&8388480); -} - -We currently generate: - bfc r0, #7, #16 - movw r2, #:lower16:8388480 - movt r2, #:upper16:8388480 - and r1, r1, r2 - orr r0, r1, r0 - bx lr - -The following is much shorter: - lsr r1, r1, #7 - bfi r0, r1, #7, #16 - bx lr - - -//===---------------------------------------------------------------------===// - The code generated for bswap on armv4/5 (CPUs without rev) is less than ideal: int a(int x) { return __builtin_bswap32(x); } Modified: llvm/trunk/test/CodeGen/ARM/bfi.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/bfi.ll?rev=108608&r1=108607&r2=108608&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/bfi.ll (original) +++ llvm/trunk/test/CodeGen/ARM/bfi.ll Fri Jul 16 22:30:54 2010 @@ -15,3 +15,26 @@ store i32 %2, i32* bitcast (%struct.F* @X to i32*), align 4 ret void } + +define i32 @f2(i32 %A, i32 %B) nounwind readnone optsize { +entry: +; CHECK: f2 +; CHECK: mov r1, r1, lsr #7 +; CHECK: bfi r0, r1, #7, #16 + %and = and i32 %A, -8388481 ; [#uses=1] + %and2 = and i32 %B, 8388480 ; [#uses=1] + %or = or i32 %and2, %and ; [#uses=1] + ret i32 %or +} + +define i32 @f3(i32 %A, i32 %B) nounwind readnone optsize { +entry: +; CHECK: f3 +; CHECK: mov r2, r0, lsr #7 +; CHECK: mov r0, r1 +; CHECK: bfi r0, r2, #7, #16 + %and = and i32 %A, 8388480 ; [#uses=1] + %and2 = and i32 %B, -8388481 ; [#uses=1] + %or = or i32 %and2, %and ; [#uses=1] + ret i32 %or +} Modified: llvm/trunk/test/CodeGen/Thumb2/bfi.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/bfi.ll?rev=108608&r1=108607&r2=108608&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/bfi.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/bfi.ll Fri Jul 16 22:30:54 2010 @@ -15,3 +15,26 @@ store i32 %2, i32* bitcast (%struct.F* @X to i32*), align 4 ret void } + +define i32 @f2(i32 %A, i32 %B) nounwind readnone optsize { +entry: +; CHECK: f2 +; CHECK: lsrs r1, r1, #7 +; CHECK: bfi r0, r1, #7, #16 + %and = and i32 %A, -8388481 ; [#uses=1] + %and2 = and i32 %B, 8388480 ; [#uses=1] + %or = or i32 %and2, %and ; [#uses=1] + ret i32 %or +} + +define i32 @f3(i32 %A, i32 %B) nounwind readnone optsize { +entry: +; CHECK: f3 +; CHECK: lsrs r2, r0, #7 +; CHECK: mov r0, r1 +; CHECK: bfi r0, r2, #7, #16 + %and = and i32 %A, 8388480 ; [#uses=1] + %and2 = and i32 %B, -8388481 ; [#uses=1] + %or = or i32 %and2, %and ; [#uses=1] + ret i32 %or +} From grosbach at apple.com Fri Jul 16 22:36:07 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 16 Jul 2010 20:36:07 -0700 Subject: [llvm-commits] [llvm] r108328 - /llvm/trunk/lib/Target/ARM/README.txt In-Reply-To: <50043384-B144-4B6A-8667-5227F028C302@apple.com> References: <20100714065826.DE7A02A6C12C@llvm.org> <795E37E6-65DE-45CE-9FC2-4E6F9EC5E286@apple.com> <45071856-6877-484B-A71D-4C457AA6E59C@apple.com> <50043384-B144-4B6A-8667-5227F028C302@apple.com> Message-ID: Done (the v7 case) in r108608. On Jul 15, 2010, at 1:16 PM, Chris Lattner wrote: > Excellent, thanks! > > On Jul 15, 2010, at 1:12 PM, Jim Grosbach wrote: > >> Agreed. I'm looking at doing something about this. I don't think it'll be too horrible. >> >> -Jim >> >> On Jul 14, 2010, at 9:52 AM, Chris Lattner wrote: >> >>> Wow, nice catch. The thumb2 code in particular is really terrible, and this pattern occurs all the time for bitfield insertion. >>> >>> -Chris >>> >>> On Jul 13, 2010, at 11:58 PM, Eli Friedman wrote: >>> >>>> Author: efriedma >>>> Date: Wed Jul 14 01:58:26 2010 >>>> New Revision: 108328 >>>> >>>> URL: http://llvm.org/viewvc/llvm-project?rev=108328&view=rev >>>> Log: >>>> A couple potential optimizations inspired by comment 4 in PR6773. >>>> >>>> >>>> Modified: >>>> llvm/trunk/lib/Target/ARM/README.txt >>>> >>>> Modified: llvm/trunk/lib/Target/ARM/README.txt >>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/README.txt?rev=108328&r1=108327&r2=108328&view=diff >>>> ============================================================================== >>>> --- llvm/trunk/lib/Target/ARM/README.txt (original) >>>> +++ llvm/trunk/lib/Target/ARM/README.txt Wed Jul 14 01:58:26 2010 >>>> @@ -590,3 +590,44 @@ >>>> associated with the comparison. Perhaps a pseudo-instruction for the comparison, >>>> with a post-codegen pass to clean up and handle the condition codes? >>>> See PR5694 for testcase. >>>> + >>>> +//===---------------------------------------------------------------------===// >>>> + >>>> +Given the following on armv5: >>>> +int test1(int A, int B) { >>>> + return (A&-8388481)|(B&8388480); >>>> +} >>>> + >>>> +We currently generate: >>>> + ldr r2, .LCPI0_0 >>>> + and r0, r0, r2 >>>> + ldr r2, .LCPI0_1 >>>> + and r1, r1, r2 >>>> + orr r0, r1, r0 >>>> + bx lr >>>> + >>>> +We should be able to replace the second ldr+and with a bic (i.e. reuse the >>>> +constant which was already loaded). Not sure what's necessary to do that. >>>> + >>>> +//===---------------------------------------------------------------------===// >>>> + >>>> +Given the following on ARMv7: >>>> +int test1(int A, int B) { >>>> + return (A&-8388481)|(B&8388480); >>>> +} >>>> + >>>> +We currently generate: >>>> + bfc r0, #7, #16 >>>> + movw r2, #:lower16:8388480 >>>> + movt r2, #:upper16:8388480 >>>> + and r1, r1, r2 >>>> + orr r0, r1, r0 >>>> + bx lr >>>> + >>>> +The following is much shorter: >>>> + lsr r1, r1, #7 >>>> + bfi r0, r1, #7, #16 >>>> + bx lr >>>> + >>>> + >>>> +//===---------------------------------------------------------------------===// >>>> >>>> >>>> _______________________________________________ >>>> llvm-commits mailing list >>>> llvm-commits at cs.uiuc.edu >>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>> >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> > From eli.friedman at gmail.com Fri Jul 16 23:29:04 2010 From: eli.friedman at gmail.com (Eli Friedman) Date: Sat, 17 Jul 2010 04:29:04 -0000 Subject: [llvm-commits] [llvm] r108609 - /llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp Message-ID: <20100717042904.9CDE52A6C12C@llvm.org> Author: efriedma Date: Fri Jul 16 23:29:04 2010 New Revision: 108609 URL: http://llvm.org/viewvc/llvm-project?rev=108609&view=rev Log: Work-in-progress parsing for ELF .section directive. Modified: llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp Modified: llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp?rev=108609&r1=108608&r2=108609&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp Fri Jul 16 23:29:04 2010 @@ -8,10 +8,11 @@ //===----------------------------------------------------------------------===// #include "llvm/MC/MCParser/MCAsmParserExtension.h" -#include "llvm/MC/MCSectionELF.h" +#include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCContext.h" -#include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCParser/MCAsmLexer.h" +#include "llvm/MC/MCSectionELF.h" +#include "llvm/MC/MCStreamer.h" using namespace llvm; namespace { @@ -31,8 +32,10 @@ &ELFAsmParser::ParseSectionDirectiveData)); Parser.AddDirectiveHandler(this, ".text", MCAsmParser::DirectiveHandler( &ELFAsmParser::ParseSectionDirectiveText)); + Parser.AddDirectiveHandler(this, ".section", MCAsmParser::DirectiveHandler( + &ELFAsmParser::ParseDirectiveSection)); Parser.AddDirectiveHandler(this, ".size", MCAsmParser::DirectiveHandler( - &ELFAsmParser::ParseSizeDirective)); + &ELFAsmParser::ParseDirectiveSize)); } bool ParseSectionDirectiveData(StringRef, SMLoc) { @@ -45,7 +48,8 @@ MCSectionELF::SHF_EXECINSTR | MCSectionELF::SHF_ALLOC, SectionKind::getText()); } - bool ParseSizeDirective(StringRef, SMLoc); + bool ParseDirectiveSection(StringRef, SMLoc); + bool ParseDirectiveSize(StringRef, SMLoc); }; } @@ -62,7 +66,7 @@ return false; } -bool ELFAsmParser::ParseSizeDirective(StringRef, SMLoc) { +bool ELFAsmParser::ParseDirectiveSize(StringRef, SMLoc) { StringRef Name; if (getParser().ParseIdentifier(Name)) return TokError("expected identifier in directive"); @@ -83,6 +87,110 @@ return false; } +// FIXME: This is a work in progress. +bool ELFAsmParser::ParseDirectiveSection(StringRef, SMLoc) { + StringRef SectionName; + // FIXME: This doesn't parse section names like ".note.GNU-stack" correctly. + if (getParser().ParseIdentifier(SectionName)) + return TokError("expected identifier in directive"); + + std::string FlagsStr; + StringRef TypeName; + int64_t Size = 0; + if (getLexer().is(AsmToken::Comma)) { + Lex(); + + if (getLexer().isNot(AsmToken::String)) + return TokError("expected string in directive"); + + FlagsStr = getTok().getStringContents(); + Lex(); + + AsmToken::TokenKind TypeStartToken; + if (getContext().getAsmInfo().getCommentString()[0] == '@') + TypeStartToken = AsmToken::Percent; + else + TypeStartToken = AsmToken::At; + + if (getLexer().is(AsmToken::Comma)) { + Lex(); + if (getLexer().is(TypeStartToken)) { + Lex(); + if (getParser().ParseIdentifier(TypeName)) + return TokError("expected identifier in directive"); + + if (getLexer().is(AsmToken::Comma)) { + Lex(); + + if (getParser().ParseAbsoluteExpression(Size)) + return true; + + if (Size <= 0) + return TokError("section size must be positive"); + } + } + } + } + + if (getLexer().isNot(AsmToken::EndOfStatement)) + return TokError("unexpected token in directive"); + + unsigned Flags = 0; + for (unsigned i = 0; i < FlagsStr.size(); i++) { + switch (FlagsStr[i]) { + case 'a': + Flags |= MCSectionELF::SHF_ALLOC; + break; + case 'x': + Flags |= MCSectionELF::SHF_EXECINSTR; + break; + case 'w': + Flags |= MCSectionELF::SHF_WRITE; + break; + case 'M': + Flags |= MCSectionELF::SHF_MERGE; + break; + case 'S': + Flags |= MCSectionELF::SHF_STRINGS; + break; + case 'T': + Flags |= MCSectionELF::SHF_TLS; + break; + case 'c': + Flags |= MCSectionELF::XCORE_SHF_CP_SECTION; + break; + case 'd': + Flags |= MCSectionELF::XCORE_SHF_DP_SECTION; + break; + default: + return TokError("unknown flag"); + } + } + + unsigned Type = MCSectionELF::SHT_NULL; + if (!TypeName.empty()) { + if (TypeName == "init_array") + Type = MCSectionELF::SHT_INIT_ARRAY; + else if (TypeName == "fini_array") + Type = MCSectionELF::SHT_FINI_ARRAY; + else if (TypeName == "preinit_array") + Type = MCSectionELF::SHT_PREINIT_ARRAY; + else if (TypeName == "nobits") + Type = MCSectionELF::SHT_NOBITS; + else if (TypeName == "progbits") + Type = MCSectionELF::SHT_PROGBITS; + else + return TokError("unknown section type"); + } + + SectionKind Kind = (Flags & MCSectionELF::SHF_EXECINSTR) + ? SectionKind::getText() + : SectionKind::getDataRel(); + getStreamer().SwitchSection(getContext().getELFSection(SectionName, Type, + Flags, Kind, false)); + return false; +} + namespace llvm { MCAsmParserExtension *createELFAsmParser() { From sabre at nondot.org Sat Jul 17 01:13:52 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 17 Jul 2010 06:13:52 -0000 Subject: [llvm-commits] [llvm] r108610 - in /llvm/trunk/lib/VMCore: Constants.cpp ConstantsContext.h Message-ID: <20100717061352.A99642A6C12C@llvm.org> Author: lattner Date: Sat Jul 17 01:13:52 2010 New Revision: 108610 URL: http://llvm.org/viewvc/llvm-project?rev=108610&view=rev Log: Fix PR7658, a problem where type refinement can trigger constant replacement which was botching its handling of types. Use of getType() instead of getRawType() was causing the type map in constant folding to be updated wrong. Modified: llvm/trunk/lib/VMCore/Constants.cpp llvm/trunk/lib/VMCore/ConstantsContext.h Modified: llvm/trunk/lib/VMCore/Constants.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Constants.cpp?rev=108610&r1=108609&r2=108610&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Constants.cpp (original) +++ llvm/trunk/lib/VMCore/Constants.cpp Sat Jul 17 01:13:52 2010 @@ -956,14 +956,14 @@ /// destroyConstant - Remove the constant from the constant table... /// void ConstantAggregateZero::destroyConstant() { - getType()->getContext().pImpl->AggZeroConstants.remove(this); + getRawType()->getContext().pImpl->AggZeroConstants.remove(this); destroyConstantImpl(); } /// destroyConstant - Remove the constant from the constant table... /// void ConstantArray::destroyConstant() { - getType()->getContext().pImpl->ArrayConstants.remove(this); + getRawType()->getContext().pImpl->ArrayConstants.remove(this); destroyConstantImpl(); } @@ -1027,21 +1027,21 @@ // destroyConstant - Remove the constant from the constant table... // void ConstantStruct::destroyConstant() { - getType()->getContext().pImpl->StructConstants.remove(this); + getRawType()->getContext().pImpl->StructConstants.remove(this); destroyConstantImpl(); } // destroyConstant - Remove the constant from the constant table... // void ConstantUnion::destroyConstant() { - getType()->getContext().pImpl->UnionConstants.remove(this); + getRawType()->getContext().pImpl->UnionConstants.remove(this); destroyConstantImpl(); } // destroyConstant - Remove the constant from the constant table... // void ConstantVector::destroyConstant() { - getType()->getContext().pImpl->VectorConstants.remove(this); + getRawType()->getContext().pImpl->VectorConstants.remove(this); destroyConstantImpl(); } @@ -1082,7 +1082,7 @@ // destroyConstant - Remove the constant from the constant table... // void ConstantPointerNull::destroyConstant() { - getType()->getContext().pImpl->NullPtrConstants.remove(this); + getRawType()->getContext().pImpl->NullPtrConstants.remove(this); destroyConstantImpl(); } @@ -1097,7 +1097,7 @@ // destroyConstant - Remove the constant from the constant table. // void UndefValue::destroyConstant() { - getType()->getContext().pImpl->UndefValueConstants.remove(this); + getRawType()->getContext().pImpl->UndefValueConstants.remove(this); destroyConstantImpl(); } @@ -1131,7 +1131,7 @@ // destroyConstant - Remove the constant from the constant table. // void BlockAddress::destroyConstant() { - getFunction()->getType()->getContext().pImpl + getFunction()->getRawType()->getContext().pImpl ->BlockAddresses.erase(std::make_pair(getFunction(), getBasicBlock())); getBasicBlock()->AdjustBlockAddressRefCount(-1); destroyConstantImpl(); @@ -1930,7 +1930,7 @@ // destroyConstant - Remove the constant from the constant table... // void ConstantExpr::destroyConstant() { - getType()->getContext().pImpl->ExprConstants.remove(this); + getRawType()->getContext().pImpl->ExprConstants.remove(this); destroyConstantImpl(); } @@ -1971,11 +1971,10 @@ assert(isa(To) && "Cannot make Constant refer to non-constant!"); Constant *ToC = cast(To); - LLVMContext &Context = getType()->getContext(); - LLVMContextImpl *pImpl = Context.pImpl; + LLVMContextImpl *pImpl = getRawType()->getContext().pImpl; std::pair Lookup; - Lookup.first.first = getType(); + Lookup.first.first = cast(getRawType()); Lookup.second = this; std::vector &Values = Lookup.first.second; @@ -2009,7 +2008,7 @@ Constant *Replacement = 0; if (isAllZeros) { - Replacement = ConstantAggregateZero::get(getType()); + Replacement = ConstantAggregateZero::get(getRawType()); } else { // Check to see if we have this array type already. bool Exists; @@ -2060,7 +2059,7 @@ assert(getOperand(OperandToUpdate) == From && "ReplaceAllUsesWith broken!"); std::pair Lookup; - Lookup.first.first = getType(); + Lookup.first.first = cast(getRawType()); Lookup.second = this; std::vector &Values = Lookup.first.second; Values.reserve(getNumOperands()); // Build replacement struct. @@ -2082,14 +2081,13 @@ } Values[OperandToUpdate] = ToC; - LLVMContext &Context = getType()->getContext(); - LLVMContextImpl *pImpl = Context.pImpl; + LLVMContextImpl *pImpl = getRawType()->getContext().pImpl; Constant *Replacement = 0; if (isAllZeros) { - Replacement = ConstantAggregateZero::get(getType()); + Replacement = ConstantAggregateZero::get(getRawType()); } else { - // Check to see if we have this array type already. + // Check to see if we have this struct type already. bool Exists; LLVMContextImpl::StructConstantsTy::MapTy::iterator I = pImpl->StructConstants.InsertOrGetItem(Lookup, Exists); @@ -2128,16 +2126,15 @@ assert(getOperand(0) == From && "ReplaceAllUsesWith broken!"); std::pair Lookup; - Lookup.first.first = getType(); + Lookup.first.first = cast(getRawType()); Lookup.second = this; Lookup.first.second = ToC; - LLVMContext &Context = getType()->getContext(); - LLVMContextImpl *pImpl = Context.pImpl; + LLVMContextImpl *pImpl = getRawType()->getContext().pImpl; Constant *Replacement = 0; if (ToC->isNullValue()) { - Replacement = ConstantAggregateZero::get(getType()); + Replacement = ConstantAggregateZero::get(getRawType()); } else { // Check to see if we have this union type already. bool Exists; @@ -2180,7 +2177,7 @@ Values.push_back(Val); } - Constant *Replacement = get(getType(), Values); + Constant *Replacement = get(cast(getRawType()), Values); assert(Replacement != this && "I didn't contain From!"); // Everyone using this now uses the replacement. @@ -2227,7 +2224,7 @@ &Indices[0], Indices.size()); } else if (isCast()) { assert(getOperand(0) == From && "Cast only has one use!"); - Replacement = ConstantExpr::getCast(getOpcode(), To, getType()); + Replacement = ConstantExpr::getCast(getOpcode(), To, getRawType()); } else if (getOpcode() == Instruction::Select) { Constant *C1 = getOperand(0); Constant *C2 = getOperand(1); Modified: llvm/trunk/lib/VMCore/ConstantsContext.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/ConstantsContext.h?rev=108610&r1=108609&r2=108610&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/ConstantsContext.h (original) +++ llvm/trunk/lib/VMCore/ConstantsContext.h Sat Jul 17 01:13:52 2010 @@ -757,9 +757,13 @@ // If this constant is the representative element for its abstract type, // update the AbstractTypeMap so that the representative element is I. - if (C->getType()->isAbstract()) { + // + // This must use getRawType() because if the type is under refinement, we + // will get the refineAbstractType callback below, and we don't want to + // kick union find in on the constant. + if (C->getRawType()->isAbstract()) { typename AbstractTypeMapTy::iterator ATI = - AbstractTypeMap.find(C->getType()); + AbstractTypeMap.find(cast(C->getRawType())); assert(ATI != AbstractTypeMap.end() && "Abstract type not in AbstractTypeMap?"); if (ATI->second == OldI) From sabre at nondot.org Sat Jul 17 01:14:03 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 17 Jul 2010 06:14:03 -0000 Subject: [llvm-commits] [llvm] r108611 - /llvm/trunk/unittests/VMCore/DerivedTypesTest.cpp Message-ID: <20100717061403.D4AB32A6C12C@llvm.org> Author: lattner Date: Sat Jul 17 01:14:03 2010 New Revision: 108611 URL: http://llvm.org/viewvc/llvm-project?rev=108611&view=rev Log: unit test to go along with r108610 Modified: llvm/trunk/unittests/VMCore/DerivedTypesTest.cpp Modified: llvm/trunk/unittests/VMCore/DerivedTypesTest.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/VMCore/DerivedTypesTest.cpp?rev=108611&r1=108610&r2=108611&view=diff ============================================================================== --- llvm/trunk/unittests/VMCore/DerivedTypesTest.cpp (original) +++ llvm/trunk/unittests/VMCore/DerivedTypesTest.cpp Sat Jul 17 01:14:03 2010 @@ -9,13 +9,66 @@ #include "gtest/gtest.h" #include "../lib/VMCore/LLVMContextImpl.h" -#include "llvm/Type.h" #include "llvm/DerivedTypes.h" #include "llvm/LLVMContext.h" +#include "llvm/Constants.h" +#include "llvm/Support/ValueHandle.h" using namespace llvm; namespace { +static void PR7658() { + LLVMContext ctx; + + WeakVH NullPtr; + PATypeHolder h1; + { + OpaqueType *o1 = OpaqueType::get(ctx); + PointerType *p1 = PointerType::get(o1, 0); + + std::vector t1; + t1.push_back(IntegerType::get(ctx, 32)); + t1.push_back(p1); + NullPtr = ConstantPointerNull::get(p1); + OpaqueType *o2 = OpaqueType::get (ctx); + PointerType *p2 = PointerType::get (o2, 0); + t1.push_back(p2); + + + StructType *s1 = StructType::get(ctx, t1); + h1 = s1; + o1->refineAbstractTypeTo(s1); + o2->refineAbstractTypeTo(h1.get()); // h1 = { i32, \2*, \2* } + } + + + OpaqueType *o3 = OpaqueType::get(ctx); + PointerType *p3 = PointerType::get(o3, 0); // p3 = opaque* + + std::vector t2; + t2.push_back(IntegerType::get(ctx, 32)); + t2.push_back(p3); + + std::vector v2; + v2.push_back(ConstantInt::get(IntegerType::get(ctx, 32), 14)); + v2.push_back(ConstantPointerNull::get(p3)); + + OpaqueType *o4 = OpaqueType::get(ctx); + { + PointerType *p4 = PointerType::get(o4, 0); + t2.push_back(p4); + v2.push_back(ConstantPointerNull::get(p4)); + } + + WeakVH CS = ConstantStruct::get(ctx, v2, false); // { i32 14, opaque* null, opaque* null} + + StructType *s2 = StructType::get(ctx, t2); + PATypeHolder h2(s2); + o3->refineAbstractTypeTo(s2); + o4->refineAbstractTypeTo(h2.get()); +} + + TEST(OpaqueTypeTest, RegisterWithContext) { LLVMContext C; LLVMContextImpl *pImpl = C.pImpl; @@ -28,6 +81,8 @@ EXPECT_EQ(2u, pImpl->OpaqueTypes.size()); } EXPECT_EQ(1u, pImpl->OpaqueTypes.size()); + + PR7658(); } } // namespace From clattner at apple.com Sat Jul 17 01:26:00 2010 From: clattner at apple.com (Chris Lattner) Date: Fri, 16 Jul 2010 23:26:00 -0700 Subject: [llvm-commits] [llvm] r108567 - in /llvm/trunk: docs/ include/llvm/Target/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CellSPU/ lib/Target/MBlaze/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PIC16/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/SystemZ/ lib/Target/X86/ lib/Target/XCore/ In-Reply-To: <20100716223547.84F432A6C12C@llvm.org> References: <20100716223547.84F432A6C12C@llvm.org> Message-ID: On Jul 16, 2010, at 3:35 PM, Jakob Stoklund Olesen wrote: > Author: stoklund > Date: Fri Jul 16 17:35:46 2010 > New Revision: 108567 > > URL: http://llvm.org/viewvc/llvm-project?rev=108567&view=rev > Log: > Remove the isMoveInstr() hook. Huzzah! From eli.friedman at gmail.com Sat Jul 17 01:27:28 2010 From: eli.friedman at gmail.com (Eli Friedman) Date: Sat, 17 Jul 2010 06:27:28 -0000 Subject: [llvm-commits] [llvm] r108612 - /llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp Message-ID: <20100717062728.D59DB2A6C12C@llvm.org> Author: efriedma Date: Sat Jul 17 01:27:28 2010 New Revision: 108612 URL: http://llvm.org/viewvc/llvm-project?rev=108612&view=rev Log: Start of .sleb128/.uleb128 parsing support. Modified: llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp Modified: llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp?rev=108612&r1=108611&r2=108612&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp Sat Jul 17 01:27:28 2010 @@ -8,6 +8,7 @@ //===----------------------------------------------------------------------===// #include "llvm/MC/MCParser/MCAsmParserExtension.h" +#include "llvm/ADT/Twine.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCParser/MCAsmLexer.h" @@ -36,6 +37,10 @@ &ELFAsmParser::ParseDirectiveSection)); Parser.AddDirectiveHandler(this, ".size", MCAsmParser::DirectiveHandler( &ELFAsmParser::ParseDirectiveSize)); + Parser.AddDirectiveHandler(this, ".sleb128", MCAsmParser::DirectiveHandler( + &ELFAsmParser::ParseDirectiveLEB128)); + Parser.AddDirectiveHandler(this, ".uleb128", MCAsmParser::DirectiveHandler( + &ELFAsmParser::ParseDirectiveLEB128)); } bool ParseSectionDirectiveData(StringRef, SMLoc) { @@ -48,6 +53,7 @@ MCSectionELF::SHF_EXECINSTR | MCSectionELF::SHF_ALLOC, SectionKind::getText()); } + bool ParseDirectiveLEB128(StringRef, SMLoc); bool ParseDirectiveSection(StringRef, SMLoc); bool ParseDirectiveSize(StringRef, SMLoc); }; @@ -191,6 +197,26 @@ return false; } +bool ELFAsmParser::ParseDirectiveLEB128(StringRef DirName, SMLoc) { + int64_t Value; + if (getParser().ParseAbsoluteExpression(Value)) + return true; + + if (getLexer().isNot(AsmToken::EndOfStatement)) + return TokError("unexpected token in directive"); + + // FIXME: Add proper MC support. + if (getContext().getAsmInfo().hasLEB128()) { + if (DirName[1] == 's') + getStreamer().EmitRawText("\t.sleb128\t" + Twine(Value)); + else + getStreamer().EmitRawText("\t.uleb128\t" + Twine(Value)); + return false; + } + // FIXME: This shouldn't be an error! + return TokError("LEB128 not supported yet"); +} + namespace llvm { MCAsmParserExtension *createELFAsmParser() { From clattner at apple.com Sat Jul 17 01:29:34 2010 From: clattner at apple.com (Chris Lattner) Date: Fri, 16 Jul 2010 23:29:34 -0700 Subject: [llvm-commits] [llvm] r108609 - /llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp In-Reply-To: <20100717042904.9CDE52A6C12C@llvm.org> References: <20100717042904.9CDE52A6C12C@llvm.org> Message-ID: <27836458-53C7-48F0-9230-5AD1E3D48500@apple.com> On Jul 16, 2010, at 9:29 PM, Eli Friedman wrote: > Author: efriedma > Date: Fri Jul 16 23:29:04 2010 > New Revision: 108609 > > URL: http://llvm.org/viewvc/llvm-project?rev=108609&view=rev > Log: > Work-in-progress parsing for ELF .section directive. Cool. If you're working on this, please keep in mind isValidSectionSpecifier in clang/lib/Basic/Targets.cpp. The MachO implementation of this allows clang to diagnose invalid attribute(section)'s in sema, it would be nice for ELF to support a similar thing. The Clang implementation for MachO looks like this: virtual std::string isValidSectionSpecifier(llvm::StringRef SR) const { // Let MCSectionMachO validate this. llvm::StringRef Segment, Section; unsigned TAA, StubSize; return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, TAA, StubSize); } -Chris From lhames at gmail.com Sat Jul 17 01:31:41 2010 From: lhames at gmail.com (Lang Hames) Date: Sat, 17 Jul 2010 06:31:41 -0000 Subject: [llvm-commits] [llvm] r108613 - in /llvm/trunk/lib/CodeGen: PBQP/Heuristics/Briggs.h RegAllocPBQP.cpp Message-ID: <20100717063141.7237E2A6C12C@llvm.org> Author: lhames Date: Sat Jul 17 01:31:41 2010 New Revision: 108613 URL: http://llvm.org/viewvc/llvm-project?rev=108613&view=rev Log: Iterating over sets of pointers in a heuristic was a bad idea. Switching any command line paramater changed the register allocation produced by PBQP. Turns out variety is not the spice of life. Fixed some comparators, added others. All good now. Modified: llvm/trunk/lib/CodeGen/PBQP/Heuristics/Briggs.h llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp Modified: llvm/trunk/lib/CodeGen/PBQP/Heuristics/Briggs.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PBQP/Heuristics/Briggs.h?rev=108613&r1=108612&r2=108613&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PBQP/Heuristics/Briggs.h (original) +++ llvm/trunk/lib/CodeGen/PBQP/Heuristics/Briggs.h Sat Jul 17 01:31:41 2010 @@ -52,9 +52,7 @@ bool operator()(Graph::NodeItr n1Itr, Graph::NodeItr n2Itr) const { if (s->getSolverDegree(n1Itr) > s->getSolverDegree(n2Itr)) return true; - if (s->getSolverDegree(n1Itr) < s->getSolverDegree(n2Itr)) - return false; - return (&*n1Itr < &*n2Itr); + return false; } private: HeuristicSolverImpl *s; @@ -69,9 +67,7 @@ cost2 = g->getNodeCosts(n2Itr)[0] / s->getSolverDegree(n2Itr); if (cost1 < cost2) return true; - if (cost1 > cost2) - return false; - return (&*n1Itr < &*n2Itr); + return false; } private: Modified: llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp?rev=108613&r1=108612&r2=108613&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp Sat Jul 17 01:31:41 2010 @@ -104,7 +104,15 @@ virtual bool runOnMachineFunction(MachineFunction &MF); private: - typedef std::map LI2NodeMap; + + class LIOrdering { + public: + bool operator()(const LiveInterval *li1, const LiveInterval *li2) const { + return li1->reg < li2->reg; + } + }; + + typedef std::map LI2NodeMap; typedef std::vector Node2LIMap; typedef std::vector AllowedSet; typedef std::vector AllowedSetMap; @@ -112,7 +120,7 @@ typedef std::pair RegPair; typedef std::map CoalesceMap; - typedef std::set LiveIntervalSet; + typedef std::set LiveIntervalSet; typedef std::vector NodeVector; From resistor at mac.com Sat Jul 17 01:56:35 2010 From: resistor at mac.com (Owen Anderson) Date: Sat, 17 Jul 2010 06:56:35 -0000 Subject: [llvm-commits] [llvm] r108614 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineAndOrXor.cpp test/Transforms/InstCombine/bit-checks.ll Message-ID: <20100717065635.EBD872A6C12C@llvm.org> Author: resistor Date: Sat Jul 17 01:56:35 2010 New Revision: 108614 URL: http://llvm.org/viewvc/llvm-project?rev=108614&view=rev Log: Another attempt at getting the clang self-host to like my instcombine patch. Added: llvm/trunk/test/Transforms/InstCombine/bit-checks.ll Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp?rev=108614&r1=108613&r2=108614&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp Sat Jul 17 01:56:35 2010 @@ -472,6 +472,22 @@ Value *NewOr = Builder->CreateOr(Val, Val2); return Builder->CreateICmp(LHSCC, NewOr, LHSCst); } + + // (icmp ne (A & C1), 0) & (icmp ne (A & C2), 0) --> + // (icmp eq (A & (C1|C2)), (C1|C2)) where C1 and C2 are non-zero POT + if (LHSCC == ICmpInst::ICMP_NE && LHSCst->isZero()) { + Value *Op1 = 0, *Op2 = 0; + ConstantInt *CI1 = 0, *CI2 = 0; + if (match(LHS->getOperand(0), m_And(m_Value(Op1), m_ConstantInt(CI1))) && + match(RHS->getOperand(0), m_And(m_Value(Op2), m_ConstantInt(CI2)))) { + if (Op1 == Op2 && !CI1->isZero() && !CI2->isZero() && + CI1->getValue().isPowerOf2() && CI2->getValue().isPowerOf2()) { + Constant *ConstOr = ConstantExpr::getOr(CI1, CI2); + Value *NewAnd = Builder->CreateAnd(Op1, ConstOr); + return Builder->CreateICmp(ICmpInst::ICMP_EQ, NewAnd, ConstOr); + } + } + } } // From here on, we only handle: @@ -1158,6 +1174,22 @@ return Builder->CreateICmp(LHSCC, NewOr, LHSCst); } + // (icmp eq (A & C1), 0) | (icmp eq (A & C2), 0) --> + // (icmp ne (A & (C1|C2)), (C1|C2)) where C1 and C2 are non-zero POT + if (LHSCC == ICmpInst::ICMP_EQ && LHSCst->isZero()) { + Value *Op1 = 0, *Op2 = 0; + ConstantInt *CI1 = 0, *CI2 = 0; + if (match(LHS->getOperand(0), m_And(m_Value(Op1), m_ConstantInt(CI1))) && + match(RHS->getOperand(0), m_And(m_Value(Op2), m_ConstantInt(CI2)))) { + if (Op1 == Op2 && !CI1->isZero() && !CI2->isZero() && + CI1->getValue().isPowerOf2() && CI2->getValue().isPowerOf2()) { + Constant *ConstOr = ConstantExpr::getOr(CI1, CI2); + Value *NewAnd = Builder->CreateAnd(Op1, ConstOr); + return Builder->CreateICmp(ICmpInst::ICMP_NE, NewAnd, ConstOr); + } + } + } + // From here on, we only handle: // (icmp1 A, C1) | (icmp2 A, C2) --> something simpler. if (Val != Val2) return 0; Added: llvm/trunk/test/Transforms/InstCombine/bit-checks.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/bit-checks.ll?rev=108614&view=auto ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/bit-checks.ll (added) +++ llvm/trunk/test/Transforms/InstCombine/bit-checks.ll Sat Jul 17 01:56:35 2010 @@ -0,0 +1,26 @@ +; This test makes sure that these instructions are properly eliminated. +; +; RUN: opt < %s -instcombine -S | \ +; RUN: not grep {tobool} +; END. +define i32 @main(i32 %argc, i8** %argv) nounwind ssp { +entry: + %and = and i32 %argc, 1 ; [#uses=1] + %tobool = icmp ne i32 %and, 0 ; [#uses=1] + %and2 = and i32 %argc, 2 ; [#uses=1] + %tobool3 = icmp ne i32 %and2, 0 ; [#uses=1] + %or.cond = and i1 %tobool, %tobool3 ; [#uses=1] + %retval.0 = select i1 %or.cond, i32 2, i32 1 ; [#uses=1] + ret i32 %retval.0 +} + +define i32 @main2(i32 %argc, i8** nocapture %argv) nounwind readnone ssp { +entry: + %and = and i32 %argc, 1 ; [#uses=1] + %tobool = icmp eq i32 %and, 0 ; [#uses=1] + %and2 = and i32 %argc, 2 ; [#uses=1] + %tobool3 = icmp eq i32 %and2, 0 ; [#uses=1] + %or.cond = or i1 %tobool, %tobool3 ; [#uses=1] + %storemerge = select i1 %or.cond, i32 0, i32 1 ; [#uses=1] + ret i32 %storemerge +} \ No newline at end of file From lhames at gmail.com Sat Jul 17 02:34:01 2010 From: lhames at gmail.com (Lang Hames) Date: Sat, 17 Jul 2010 07:34:01 -0000 Subject: [llvm-commits] [llvm] r108615 - in /llvm/trunk: include/llvm/Analysis/LoopInfo.h include/llvm/CodeGen/LiveIntervalAnalysis.h lib/CodeGen/Splitter.cpp lib/CodeGen/Splitter.h Message-ID: <20100717073401.79A5A2A6C12D@llvm.org> Author: lhames Date: Sat Jul 17 02:34:01 2010 New Revision: 108615 URL: http://llvm.org/viewvc/llvm-project?rev=108615&view=rev Log: LoopSplitter - intended to split live intervals over loop boundaries. Still very much under development. Comments and fixes will be forthcoming. (This commit includes some small tweaks to LiveIntervals & LoopInfo to support the splitter) Added: llvm/trunk/lib/CodeGen/Splitter.cpp llvm/trunk/lib/CodeGen/Splitter.h Modified: llvm/trunk/include/llvm/Analysis/LoopInfo.h llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h Modified: llvm/trunk/include/llvm/Analysis/LoopInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/LoopInfo.h?rev=108615&r1=108614&r2=108615&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/LoopInfo.h (original) +++ llvm/trunk/include/llvm/Analysis/LoopInfo.h Sat Jul 17 02:34:01 2010 @@ -229,9 +229,12 @@ return 0; } + /// Edge type. + typedef std::pair Edge; + /// getExitEdges - Return all pairs of (_inside_block_,_outside_block_). - typedef std::pair Edge; - void getExitEdges(SmallVectorImpl &ExitEdges) const { + template + void getExitEdges(SmallVectorImpl &ExitEdges) const { // Sort the blocks vector so that we can use binary search to do quick // lookups. SmallVector LoopBBs(block_begin(), block_end()); @@ -244,7 +247,7 @@ I != E; ++I) if (!std::binary_search(LoopBBs.begin(), LoopBBs.end(), *I)) // Not in current loop? It must be an exit block. - ExitEdges.push_back(std::make_pair(*BI, *I)); + ExitEdges.push_back(EdgeT(*BI, *I)); } /// getLoopPreheader - If there is a preheader for this loop, return it. A Modified: llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h?rev=108615&r1=108614&r2=108615&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h (original) +++ llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h Sat Jul 17 02:34:01 2010 @@ -197,6 +197,26 @@ return indexes_->getMBBEndIdx(mbb); } + bool isLiveInToMBB(const LiveInterval &li, + const MachineBasicBlock *mbb) const { + return li.liveAt(getMBBStartIdx(mbb)); + } + + LiveRange* findEnteringRange(LiveInterval &li, + const MachineBasicBlock *mbb) { + return li.getLiveRangeContaining(getMBBStartIdx(mbb)); + } + + bool isLiveOutOfMBB(const LiveInterval &li, + const MachineBasicBlock *mbb) const { + return li.liveAt(getMBBEndIdx(mbb).getPrevSlot()); + } + + LiveRange* findExitingRange(LiveInterval &li, + const MachineBasicBlock *mbb) { + return li.getLiveRangeContaining(getMBBEndIdx(mbb).getPrevSlot()); + } + MachineBasicBlock* getMBBFromIndex(SlotIndex index) const { return indexes_->getMBBFromIndex(index); } @@ -217,6 +237,10 @@ indexes_->replaceMachineInstrInMaps(MI, NewMI); } + void InsertMBBInMaps(MachineBasicBlock *MBB) { + indexes_->insertMBBInMaps(MBB); + } + bool findLiveInMBBs(SlotIndex Start, SlotIndex End, SmallVectorImpl &MBBs) const { return indexes_->findLiveInMBBs(Start, End, MBBs); Added: llvm/trunk/lib/CodeGen/Splitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Splitter.cpp?rev=108615&view=auto ============================================================================== --- llvm/trunk/lib/CodeGen/Splitter.cpp (added) +++ llvm/trunk/lib/CodeGen/Splitter.cpp Sat Jul 17 02:34:01 2010 @@ -0,0 +1,819 @@ +//===-- llvm/CodeGen/Splitter.cpp - Splitter -----------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#define DEBUG_TYPE "loopsplitter" + +#include "Splitter.h" + +#include "SimpleRegisterCoalescing.h" +#include "llvm/Module.h" +#include "llvm/CodeGen/CalcSpillWeights.h" +#include "llvm/CodeGen/LiveIntervalAnalysis.h" +#include "llvm/CodeGen/LiveStackAnalysis.h" +#include "llvm/CodeGen/MachineDominators.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/SlotIndexes.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/raw_ostream.h" +#include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetInstrInfo.h" + +using namespace llvm; + +char LoopSplitter::ID = 0; +static RegisterPass +X("loop-splitting", "Split virtual regists across loop boundaries."); + +namespace llvm { + + class StartSlotComparator { + public: + StartSlotComparator(LiveIntervals &lis) : lis(lis) {} + bool operator()(const MachineBasicBlock *mbb1, + const MachineBasicBlock *mbb2) const { + return lis.getMBBStartIdx(mbb1) < lis.getMBBStartIdx(mbb2); + } + private: + LiveIntervals &lis; + }; + + class LoopSplit { + public: + LoopSplit(LoopSplitter &ls, LiveInterval &li, MachineLoop &loop) + : ls(ls), li(li), loop(loop), valid(true), inSplit(false), newLI(0) { + assert(TargetRegisterInfo::isVirtualRegister(li.reg) && + "Cannot split physical registers."); + } + + LiveInterval& getLI() const { return li; } + + MachineLoop& getLoop() const { return loop; } + + bool isValid() const { return valid; } + + bool isWorthwhile() const { return valid && (inSplit || !outSplits.empty()); } + + void invalidate() { valid = false; } + + void splitIncoming() { inSplit = true; } + + void splitOutgoing(MachineLoop::Edge &edge) { outSplits.insert(edge); } + + void addLoopInstr(MachineInstr *i) { loopInstrs.push_back(i); } + + void apply() { + assert(valid && "Attempt to apply invalid split."); + applyIncoming(); + applyOutgoing(); + copyRanges(); + renameInside(); + } + + private: + LoopSplitter &ls; + LiveInterval &li; + MachineLoop &loop; + bool valid, inSplit; + std::set outSplits; + std::vector loopInstrs; + + LiveInterval *newLI; + std::map vniMap; + + LiveInterval* getNewLI() { + if (newLI == 0) { + const TargetRegisterClass *trc = ls.mri->getRegClass(li.reg); + unsigned vreg = ls.mri->createVirtualRegister(trc); + newLI = &ls.lis->getOrCreateInterval(vreg); + } + return newLI; + } + + VNInfo* getNewVNI(VNInfo *oldVNI) { + VNInfo *newVNI = vniMap[oldVNI]; + + if (newVNI == 0) { + newVNI = getNewLI()->createValueCopy(oldVNI, + ls.lis->getVNInfoAllocator()); + vniMap[oldVNI] = newVNI; + } + + return newVNI; + } + + void applyIncoming() { + if (!inSplit) { + return; + } + + MachineBasicBlock *preHeader = loop.getLoopPreheader(); + if (preHeader == 0) { + assert(ls.canInsertPreHeader(loop) && + "Can't insert required preheader."); + preHeader = &ls.insertPreHeader(loop); + } + + LiveRange *preHeaderRange = + ls.lis->findExitingRange(li, preHeader); + assert(preHeaderRange != 0 && "Range not live into preheader."); + + // Insert the new copy. + MachineInstr *copy = BuildMI(*preHeader, + preHeader->getFirstTerminator(), + DebugLoc(), + ls.tii->get(TargetOpcode::COPY)) + .addReg(getNewLI()->reg, RegState::Define) + .addReg(li.reg, RegState::Kill); + + ls.lis->InsertMachineInstrInMaps(copy); + + SlotIndex copyDefIdx = ls.lis->getInstructionIndex(copy).getDefIndex(); + + VNInfo *newVal = getNewVNI(preHeaderRange->valno); + newVal->def = copyDefIdx; + newVal->setCopy(copy); + newVal->setIsDefAccurate(true); + li.removeRange(copyDefIdx, ls.lis->getMBBEndIdx(preHeader), true); + + getNewLI()->addRange(LiveRange(copyDefIdx, + ls.lis->getMBBEndIdx(preHeader), + newVal)); + } + + void applyOutgoing() { + + for (std::set::iterator osItr = outSplits.begin(), + osEnd = outSplits.end(); + osItr != osEnd; ++osItr) { + MachineLoop::Edge edge = *osItr; + MachineBasicBlock *outBlock = edge.second; + if (ls.isCriticalEdge(edge)) { + assert(ls.canSplitEdge(edge) && "Unsplitable critical edge."); + outBlock = &ls.splitEdge(edge, loop); + } + LiveRange *outRange = ls.lis->findEnteringRange(li, outBlock); + assert(outRange != 0 && "No exiting range?"); + + MachineInstr *copy = BuildMI(*outBlock, outBlock->begin(), + DebugLoc(), + ls.tii->get(TargetOpcode::COPY)) + .addReg(li.reg, RegState::Define) + .addReg(getNewLI()->reg, RegState::Kill); + + ls.lis->InsertMachineInstrInMaps(copy); + + SlotIndex copyDefIdx = ls.lis->getInstructionIndex(copy).getDefIndex(); + + // Blow away output range definition. + outRange->valno->def = ls.lis->getInvalidIndex(); + outRange->valno->setIsDefAccurate(false); + li.removeRange(ls.lis->getMBBStartIdx(outBlock), copyDefIdx); + + VNInfo *newVal = + getNewLI()->getNextValue(SlotIndex(ls.lis->getMBBStartIdx(outBlock), + true), + 0, false, ls.lis->getVNInfoAllocator()); + + getNewLI()->addRange(LiveRange(ls.lis->getMBBStartIdx(outBlock), + copyDefIdx, newVal)); + + } + } + + void copyRange(LiveRange &lr) { + std::pair lsr = + ls.getLoopSubRange(lr, loop); + + if (!lsr.first) + return; + + LiveRange loopRange(lsr.second.first, lsr.second.second, + getNewVNI(lr.valno)); + + li.removeRange(loopRange.start, loopRange.end, true); + + getNewLI()->addRange(loopRange); + } + + void copyRanges() { + for (std::vector::iterator iItr = loopInstrs.begin(), + iEnd = loopInstrs.end(); + iItr != iEnd; ++iItr) { + MachineInstr &instr = **iItr; + SlotIndex instrIdx = ls.lis->getInstructionIndex(&instr); + if (instr.modifiesRegister(li.reg, 0)) { + LiveRange *defRange = + li.getLiveRangeContaining(instrIdx.getDefIndex()); + if (defRange != 0) // May have caught this already. + copyRange(*defRange); + } + if (instr.readsRegister(li.reg, 0)) { + LiveRange *useRange = + li.getLiveRangeContaining(instrIdx.getUseIndex()); + if (useRange != 0) { // May have caught this already. + copyRange(*useRange); + } + } + } + + for (MachineLoop::block_iterator bbItr = loop.block_begin(), + bbEnd = loop.block_end(); + bbItr != bbEnd; ++bbItr) { + MachineBasicBlock &loopBlock = **bbItr; + LiveRange *enteringRange = + ls.lis->findEnteringRange(li, &loopBlock); + if (enteringRange != 0) { + copyRange(*enteringRange); + } + } + } + + void renameInside() { + for (std::vector::iterator iItr = loopInstrs.begin(), + iEnd = loopInstrs.end(); + iItr != iEnd; ++iItr) { + MachineInstr &instr = **iItr; + for (unsigned i = 0; i < instr.getNumOperands(); ++i) { + MachineOperand &mop = instr.getOperand(i); + if (mop.isReg() && mop.getReg() == li.reg) { + mop.setReg(getNewLI()->reg); + } + } + } + } + + }; + + void LoopSplitter::getAnalysisUsage(AnalysisUsage &au) const { + au.addRequired(); + au.addPreserved(); + au.addRequired(); + au.addPreserved(); + au.addPreserved(); + au.addPreserved(); + au.addPreserved(); + au.addRequired(); + au.addPreserved(); + au.addRequired(); + au.addPreserved(); + MachineFunctionPass::getAnalysisUsage(au); + } + + bool LoopSplitter::runOnMachineFunction(MachineFunction &fn) { + + mf = &fn; + mri = &mf->getRegInfo(); + tii = mf->getTarget().getInstrInfo(); + tri = mf->getTarget().getRegisterInfo(); + sis = &getAnalysis(); + lis = &getAnalysis(); + mli = &getAnalysis(); + mdt = &getAnalysis(); + + fqn = mf->getFunction()->getParent()->getModuleIdentifier() + "." + + mf->getFunction()->getName().str(); + + dbgs() << "Splitting " << mf->getFunction()->getName() << "."; + + dumpOddTerminators(); + +// dbgs() << "----------------------------------------\n"; +// lis->dump(); +// dbgs() << "----------------------------------------\n"; + +// std::deque loops; +// std::copy(mli->begin(), mli->end(), std::back_inserter(loops)); +// dbgs() << "Loops:\n"; +// while (!loops.empty()) { +// MachineLoop &loop = *loops.front(); +// loops.pop_front(); +// std::copy(loop.begin(), loop.end(), std::back_inserter(loops)); + +// dumpLoopInfo(loop); +// } + + //lis->dump(); + //exit(0); + + // Setup initial intervals. + for (LiveIntervals::iterator liItr = lis->begin(), liEnd = lis->end(); + liItr != liEnd; ++liItr) { + LiveInterval *li = liItr->second; + + if (TargetRegisterInfo::isVirtualRegister(li->reg) && + !lis->intervalIsInOneMBB(*li)) { + intervals.push_back(li); + } + } + + processIntervals(); + + intervals.clear(); + +// dbgs() << "----------------------------------------\n"; +// lis->dump(); +// dbgs() << "----------------------------------------\n"; + + dumpOddTerminators(); + + //exit(1); + + return false; + } + + void LoopSplitter::releaseMemory() { + fqn.clear(); + intervals.clear(); + loopRangeMap.clear(); + } + + void LoopSplitter::dumpOddTerminators() { + for (MachineFunction::iterator bbItr = mf->begin(), bbEnd = mf->end(); + bbItr != bbEnd; ++bbItr) { + MachineBasicBlock *mbb = &*bbItr; + MachineBasicBlock *a = 0, *b = 0; + SmallVector c; + if (tii->AnalyzeBranch(*mbb, a, b, c)) { + dbgs() << "MBB#" << mbb->getNumber() << " has multiway terminator.\n"; + dbgs() << " Terminators:\n"; + for (MachineBasicBlock::iterator iItr = mbb->begin(), iEnd = mbb->end(); + iItr != iEnd; ++iItr) { + MachineInstr *instr= &*iItr; + dbgs() << " " << *instr << ""; + } + dbgs() << "\n Listed successors: [ "; + for (MachineBasicBlock::succ_iterator sItr = mbb->succ_begin(), sEnd = mbb->succ_end(); + sItr != sEnd; ++sItr) { + MachineBasicBlock *succMBB = *sItr; + dbgs() << succMBB->getNumber() << " "; + } + dbgs() << "]\n\n"; + } + } + } + + void LoopSplitter::dumpLoopInfo(MachineLoop &loop) { + MachineBasicBlock &headerBlock = *loop.getHeader(); + typedef SmallVector ExitEdgesList; + ExitEdgesList exitEdges; + loop.getExitEdges(exitEdges); + + dbgs() << " Header: BB#" << headerBlock.getNumber() << ", Contains: [ "; + for (std::vector::const_iterator + subBlockItr = loop.getBlocks().begin(), + subBlockEnd = loop.getBlocks().end(); + subBlockItr != subBlockEnd; ++subBlockItr) { + MachineBasicBlock &subBlock = **subBlockItr; + dbgs() << "BB#" << subBlock.getNumber() << " "; + } + dbgs() << "], Exit edges: [ "; + for (ExitEdgesList::iterator exitEdgeItr = exitEdges.begin(), + exitEdgeEnd = exitEdges.end(); + exitEdgeItr != exitEdgeEnd; ++exitEdgeItr) { + MachineLoop::Edge &exitEdge = *exitEdgeItr; + dbgs() << "(MBB#" << exitEdge.first->getNumber() + << ", MBB#" << exitEdge.second->getNumber() << ") "; + } + dbgs() << "], Sub-Loop Headers: [ "; + for (MachineLoop::iterator subLoopItr = loop.begin(), + subLoopEnd = loop.end(); + subLoopItr != subLoopEnd; ++subLoopItr) { + MachineLoop &subLoop = **subLoopItr; + MachineBasicBlock &subLoopBlock = *subLoop.getHeader(); + dbgs() << "BB#" << subLoopBlock.getNumber() << " "; + } + dbgs() << "]\n"; + } + + void LoopSplitter::updateTerminators(MachineBasicBlock &mbb) { + mbb.updateTerminator(); + + for (MachineBasicBlock::iterator miItr = mbb.begin(), miEnd = mbb.end(); + miItr != miEnd; ++miItr) { + if (lis->isNotInMIMap(miItr)) { + lis->InsertMachineInstrInMaps(miItr); + } + } + } + + bool LoopSplitter::canInsertPreHeader(MachineLoop &loop) { + MachineBasicBlock *header = loop.getHeader(); + MachineBasicBlock *a = 0, *b = 0; + SmallVector c; + + for (MachineBasicBlock::pred_iterator pbItr = header->pred_begin(), + pbEnd = header->pred_end(); + pbItr != pbEnd; ++pbItr) { + MachineBasicBlock *predBlock = *pbItr; + if (!!tii->AnalyzeBranch(*predBlock, a, b, c)) { + return false; + } + } + + MachineFunction::iterator headerItr(header); + if (headerItr == mf->begin()) + return true; + MachineBasicBlock *headerLayoutPred = llvm::prior(headerItr); + assert(headerLayoutPred != 0 && "Header should have layout pred."); + + return (!tii->AnalyzeBranch(*headerLayoutPred, a, b, c)); + } + + MachineBasicBlock& LoopSplitter::insertPreHeader(MachineLoop &loop) { + assert(loop.getLoopPreheader() == 0 && "Loop already has preheader."); + + MachineBasicBlock &header = *loop.getHeader(); + + // Save the preds - we'll need to update them once we insert the preheader. + typedef std::set HeaderPreds; + HeaderPreds headerPreds; + + for (MachineBasicBlock::pred_iterator predItr = header.pred_begin(), + predEnd = header.pred_end(); + predItr != predEnd; ++predItr) { + if (!loop.contains(*predItr)) + headerPreds.insert(*predItr); + } + + assert(!headerPreds.empty() && "No predecessors for header?"); + + //dbgs() << fqn << " MBB#" << header.getNumber() << " inserting preheader..."; + + MachineBasicBlock *preHeader = + mf->CreateMachineBasicBlock(header.getBasicBlock()); + + assert(preHeader != 0 && "Failed to create pre-header."); + + mf->insert(header, preHeader); + + for (HeaderPreds::iterator hpItr = headerPreds.begin(), + hpEnd = headerPreds.end(); + hpItr != hpEnd; ++hpItr) { + assert(*hpItr != 0 && "How'd a null predecessor get into this set?"); + MachineBasicBlock &hp = **hpItr; + hp.ReplaceUsesOfBlockWith(&header, preHeader); + } + preHeader->addSuccessor(&header); + + MachineBasicBlock *oldLayoutPred = + llvm::prior(MachineFunction::iterator(preHeader)); + if (oldLayoutPred != 0) { + updateTerminators(*oldLayoutPred); + } + + lis->InsertMBBInMaps(preHeader); + + if (MachineLoop *parentLoop = loop.getParentLoop()) { + assert(parentLoop->getHeader() != loop.getHeader() && + "Parent loop has same header?"); + parentLoop->addBasicBlockToLoop(preHeader, mli->getBase()); + + // Invalidate all parent loop ranges. + while (parentLoop != 0) { + loopRangeMap.erase(parentLoop); + parentLoop = parentLoop->getParentLoop(); + } + } + + for (LiveIntervals::iterator liItr = lis->begin(), + liEnd = lis->end(); + liItr != liEnd; ++liItr) { + LiveInterval &li = *liItr->second; + + // Is this safe for physregs? + // TargetRegisterInfo::isPhysicalRegister(li.reg) || + if (!lis->isLiveInToMBB(li, &header)) + continue; + + if (lis->isLiveInToMBB(li, preHeader)) { + assert(lis->isLiveOutOfMBB(li, preHeader) && + "Range terminates in newly added preheader?"); + continue; + } + + bool insertRange = false; + + for (MachineBasicBlock::pred_iterator predItr = preHeader->pred_begin(), + predEnd = preHeader->pred_end(); + predItr != predEnd; ++predItr) { + MachineBasicBlock *predMBB = *predItr; + if (lis->isLiveOutOfMBB(li, predMBB)) { + insertRange = true; + break; + } + } + + if (!insertRange) + continue; + + VNInfo *newVal = li.getNextValue(lis->getMBBStartIdx(preHeader), + 0, false, lis->getVNInfoAllocator()); + li.addRange(LiveRange(lis->getMBBStartIdx(preHeader), + lis->getMBBEndIdx(preHeader), + newVal)); + } + + + //dbgs() << "Dumping SlotIndexes:\n"; + //sis->dump(); + + //dbgs() << "done. (Added MBB#" << preHeader->getNumber() << ")\n"; + + return *preHeader; + } + + bool LoopSplitter::isCriticalEdge(MachineLoop::Edge &edge) { + assert(edge.first->succ_size() > 1 && "Non-sensical edge."); + if (edge.second->pred_size() > 1) + return true; + return false; + } + + bool LoopSplitter::canSplitEdge(MachineLoop::Edge &edge) { + MachineFunction::iterator outBlockItr(edge.second); + if (outBlockItr == mf->begin()) + return true; + MachineBasicBlock *outBlockLayoutPred = llvm::prior(outBlockItr); + assert(outBlockLayoutPred != 0 && "Should have a layout pred if out!=begin."); + MachineBasicBlock *a = 0, *b = 0; + SmallVector c; + return (!tii->AnalyzeBranch(*outBlockLayoutPred, a, b, c) && + !tii->AnalyzeBranch(*edge.first, a, b, c)); + } + + MachineBasicBlock& LoopSplitter::splitEdge(MachineLoop::Edge &edge, + MachineLoop &loop) { + + MachineBasicBlock &inBlock = *edge.first; + MachineBasicBlock &outBlock = *edge.second; + + assert((inBlock.succ_size() > 1) && (outBlock.pred_size() > 1) && + "Splitting non-critical edge?"); + + //dbgs() << fqn << " Splitting edge (MBB#" << inBlock.getNumber() + // << " -> MBB#" << outBlock.getNumber() << ")..."; + + MachineBasicBlock *splitBlock = + mf->CreateMachineBasicBlock(); + + assert(splitBlock != 0 && "Failed to create split block."); + + mf->insert(&outBlock, splitBlock); + + inBlock.ReplaceUsesOfBlockWith(&outBlock, splitBlock); + splitBlock->addSuccessor(&outBlock); + + MachineBasicBlock *oldLayoutPred = + llvm::prior(MachineFunction::iterator(splitBlock)); + if (oldLayoutPred != 0) { + updateTerminators(*oldLayoutPred); + } + + lis->InsertMBBInMaps(splitBlock); + + loopRangeMap.erase(&loop); + + MachineLoop *splitParentLoop = loop.getParentLoop(); + while (splitParentLoop != 0 && + !splitParentLoop->contains(&outBlock)) { + splitParentLoop = splitParentLoop->getParentLoop(); + } + + if (splitParentLoop != 0) { + assert(splitParentLoop->contains(&loop) && + "Split-block parent doesn't contain original loop?"); + splitParentLoop->addBasicBlockToLoop(splitBlock, mli->getBase()); + + // Invalidate all parent loop ranges. + while (splitParentLoop != 0) { + loopRangeMap.erase(splitParentLoop); + splitParentLoop = splitParentLoop->getParentLoop(); + } + } + + + for (LiveIntervals::iterator liItr = lis->begin(), + liEnd = lis->end(); + liItr != liEnd; ++liItr) { + LiveInterval &li = *liItr->second; + bool intersects = lis->isLiveOutOfMBB(li, &inBlock) && + lis->isLiveInToMBB(li, &outBlock); + if (lis->isLiveInToMBB(li, splitBlock)) { + if (!intersects) { + li.removeRange(lis->getMBBStartIdx(splitBlock), + lis->getMBBEndIdx(splitBlock), true); + } + } else if (intersects) { + VNInfo *newVal = li.getNextValue(lis->getMBBStartIdx(splitBlock), + 0, false, lis->getVNInfoAllocator()); + li.addRange(LiveRange(lis->getMBBStartIdx(splitBlock), + lis->getMBBEndIdx(splitBlock), + newVal)); + } + } + + //dbgs() << "done. (Added MBB#" << splitBlock->getNumber() << ")\n"; + + return *splitBlock; + } + + LoopSplitter::LoopRanges& LoopSplitter::getLoopRanges(MachineLoop &loop) { + typedef std::set LoopMBBSet; + LoopRangeMap::iterator lrItr = loopRangeMap.find(&loop); + if (lrItr == loopRangeMap.end()) { + LoopMBBSet loopMBBs((StartSlotComparator(*lis))); + std::copy(loop.block_begin(), loop.block_end(), + std::inserter(loopMBBs, loopMBBs.begin())); + + assert(!loopMBBs.empty() && "No blocks in loop?"); + + LoopRanges &loopRanges = loopRangeMap[&loop]; + assert(loopRanges.empty() && "Loop encountered but not processed?"); + SlotIndex oldEnd = lis->getMBBEndIdx(*loopMBBs.begin()); + loopRanges.push_back( + std::make_pair(lis->getMBBStartIdx(*loopMBBs.begin()), + lis->getInvalidIndex())); + for (LoopMBBSet::iterator curBlockItr = llvm::next(loopMBBs.begin()), + curBlockEnd = loopMBBs.end(); + curBlockItr != curBlockEnd; ++curBlockItr) { + SlotIndex newStart = lis->getMBBStartIdx(*curBlockItr); + if (newStart != oldEnd) { + loopRanges.back().second = oldEnd; + loopRanges.push_back(std::make_pair(newStart, + lis->getInvalidIndex())); + } + oldEnd = lis->getMBBEndIdx(*curBlockItr); + } + + loopRanges.back().second = + lis->getMBBEndIdx(*llvm::prior(loopMBBs.end())); + + return loopRanges; + } + return lrItr->second; + } + + std::pair LoopSplitter::getLoopSubRange( + const LiveRange &lr, + MachineLoop &loop) { + LoopRanges &loopRanges = getLoopRanges(loop); + LoopRanges::iterator lrItr = loopRanges.begin(), + lrEnd = loopRanges.end(); + while (lrItr != lrEnd && lr.start >= lrItr->second) { + ++lrItr; + } + + if (lrItr == lrEnd) { + SlotIndex invalid = lis->getInvalidIndex(); + return std::make_pair(false, SlotPair(invalid, invalid)); + } + + SlotIndex srStart(lr.start < lrItr->first ? lrItr->first : lr.start); + SlotIndex srEnd(lr.end > lrItr->second ? lrItr->second : lr.end); + + return std::make_pair(true, SlotPair(srStart, srEnd)); + } + + void LoopSplitter::dumpLoopRanges(MachineLoop &loop) { + LoopRanges &loopRanges = getLoopRanges(loop); + dbgs() << "For loop MBB#" << loop.getHeader()->getNumber() << ", subranges are: [ "; + for (LoopRanges::iterator lrItr = loopRanges.begin(), lrEnd = loopRanges.end(); + lrItr != lrEnd; ++lrItr) { + dbgs() << "[" << lrItr->first << ", " << lrItr->second << ") "; + } + dbgs() << "]\n"; + } + + void LoopSplitter::processHeader(LoopSplit &split) { + MachineBasicBlock &header = *split.getLoop().getHeader(); + //dbgs() << " Processing loop header BB#" << header.getNumber() << "\n"; + + if (!lis->isLiveInToMBB(split.getLI(), &header)) + return; // Not live in, but nothing wrong so far. + + MachineBasicBlock *preHeader = split.getLoop().getLoopPreheader(); + if (!preHeader) { + + if (!canInsertPreHeader(split.getLoop())) { + split.invalidate(); + return; // Couldn't insert a pre-header. Bail on this interval. + } + + for (MachineBasicBlock::pred_iterator predItr = header.pred_begin(), + predEnd = header.pred_end(); + predItr != predEnd; ++predItr) { + if (lis->isLiveOutOfMBB(split.getLI(), *predItr)) { + split.splitIncoming(); + break; + } + } + } else if (lis->isLiveOutOfMBB(split.getLI(), preHeader)) { + split.splitIncoming(); + } + } + + void LoopSplitter::processLoopExits(LoopSplit &split) { + typedef SmallVector ExitEdgesList; + ExitEdgesList exitEdges; + split.getLoop().getExitEdges(exitEdges); + + //dbgs() << " Processing loop exits:\n"; + + for (ExitEdgesList::iterator exitEdgeItr = exitEdges.begin(), + exitEdgeEnd = exitEdges.end(); + exitEdgeItr != exitEdgeEnd; ++exitEdgeItr) { + MachineLoop::Edge exitEdge = *exitEdgeItr; + + LiveRange *inRange = + split.getLI().getLiveRangeContaining(lis->getMBBEndIdx(exitEdge.first).getPrevSlot()); + LiveRange *outRange = + split.getLI().getLiveRangeContaining(lis->getMBBStartIdx(exitEdge.second)); + + if (outRange != 0) { + if (isCriticalEdge(exitEdge) && !canSplitEdge(exitEdge)) { + split.invalidate(); + return; + } + + split.splitOutgoing(exitEdge); + } + } + } + + void LoopSplitter::processLoopUses(LoopSplit &split) { + std::set processed; + + for (MachineRegisterInfo::reg_iterator + rItr = mri->reg_begin(split.getLI().reg), + rEnd = mri->reg_end(); + rItr != rEnd; ++rItr) { + MachineInstr &instr = *rItr; + if (split.getLoop().contains(&instr) && processed.count(&instr) == 0) { + split.addLoopInstr(&instr); + processed.insert(&instr); + } + } + + //dbgs() << " Rewriting reg" << li.reg << " to reg" << newLI->reg + // << " in blocks [ "; + //dbgs() << "]\n"; + } + + bool LoopSplitter::splitOverLoop(LiveInterval &li, MachineLoop &loop) { + assert(TargetRegisterInfo::isVirtualRegister(li.reg) && + "Attempt to split physical register."); + + LoopSplit split(*this, li, loop); + processHeader(split); + if (split.isValid()) + processLoopExits(split); + if (split.isValid()) + processLoopUses(split); + if (split.isValid() /* && split.isWorthwhile() */) { + split.apply(); + DEBUG(dbgs() << "Success.\n"); + return true; + } + DEBUG(dbgs() << "Failed.\n"); + return false; + } + + void LoopSplitter::processInterval(LiveInterval &li) { + std::deque loops; + std::copy(mli->begin(), mli->end(), std::back_inserter(loops)); + + while (!loops.empty()) { + MachineLoop &loop = *loops.front(); + loops.pop_front(); + DEBUG( + dbgs() << fqn << " reg" << li.reg << " " << li.weight << " BB#" + << loop.getHeader()->getNumber() << " "; + ); + if (!splitOverLoop(li, loop)) { + // Couldn't split over outer loop, schedule sub-loops to be checked. + std::copy(loop.begin(), loop.end(), std::back_inserter(loops)); + } + } + } + + void LoopSplitter::processIntervals() { + while (!intervals.empty()) { + LiveInterval &li = *intervals.front(); + intervals.pop_front(); + + assert(!lis->intervalIsInOneMBB(li) && + "Single interval in process worklist."); + + processInterval(li); + } + } + +} Added: llvm/trunk/lib/CodeGen/Splitter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Splitter.h?rev=108615&view=auto ============================================================================== --- llvm/trunk/lib/CodeGen/Splitter.h (added) +++ llvm/trunk/lib/CodeGen/Splitter.h Sat Jul 17 02:34:01 2010 @@ -0,0 +1,99 @@ +//===-- llvm/CodeGen/Splitter.h - Splitter -*- C++ -*----------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CODEGEN_SPLITTER_H +#define LLVM_CODEGEN_SPLITTER_H + +#include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachineLoopInfo.h" +#include "llvm/CodeGen/SlotIndexes.h" + +#include +#include +#include +#include + +namespace llvm { + + class LiveInterval; + class LiveIntervals; + class LiveRange; + class LoopSplit; + class MachineDominatorTree; + class MachineRegisterInfo; + class SlotIndexes; + class TargetInstrInfo; + class VNInfo; + + class LoopSplitter : public MachineFunctionPass { + friend class LoopSplit; + public: + static char ID; + + LoopSplitter() : MachineFunctionPass(&ID) {} + + virtual void getAnalysisUsage(AnalysisUsage &au) const; + + virtual bool runOnMachineFunction(MachineFunction &fn); + + virtual void releaseMemory(); + + + private: + + MachineFunction *mf; + LiveIntervals *lis; + MachineLoopInfo *mli; + MachineRegisterInfo *mri; + MachineDominatorTree *mdt; + SlotIndexes *sis; + const TargetInstrInfo *tii; + const TargetRegisterInfo *tri; + + std::string fqn; + std::deque intervals; + + typedef std::pair SlotPair; + typedef std::vector LoopRanges; + typedef std::map LoopRangeMap; + LoopRangeMap loopRangeMap; + + void dumpLoopInfo(MachineLoop &loop); + + void dumpOddTerminators(); + + void updateTerminators(MachineBasicBlock &mbb); + + bool canInsertPreHeader(MachineLoop &loop); + MachineBasicBlock& insertPreHeader(MachineLoop &loop); + + bool isCriticalEdge(MachineLoop::Edge &edge); + bool canSplitEdge(MachineLoop::Edge &edge); + MachineBasicBlock& splitEdge(MachineLoop::Edge &edge, MachineLoop &loop); + + LoopRanges& getLoopRanges(MachineLoop &loop); + std::pair getLoopSubRange(const LiveRange &lr, + MachineLoop &loop); + + void dumpLoopRanges(MachineLoop &loop); + + void processHeader(LoopSplit &split); + void processLoopExits(LoopSplit &split); + void processLoopUses(LoopSplit &split); + + bool splitOverLoop(LiveInterval &li, MachineLoop &loop); + + void processInterval(LiveInterval &li); + + void processIntervals(); + }; + +} + +#endif From lhames at gmail.com Sat Jul 17 02:39:49 2010 From: lhames at gmail.com (Lang Hames) Date: Sat, 17 Jul 2010 17:39:49 +1000 Subject: [llvm-commits] [llvm] r108615 - in /llvm/trunk: include/llvm/Analysis/LoopInfo.h include/llvm/CodeGen/LiveIntervalAnalysis.h lib/CodeGen/Splitter.cpp lib/CodeGen/Splitter.h In-Reply-To: <20100717073401.79A5A2A6C12D@llvm.org> References: <20100717073401.79A5A2A6C12D@llvm.org> Message-ID: Also not hooked up to anything yet. At present if you require this pass in your register allocator it'll go ahead aggressively split all your intervals, undoing half of the SimpleRegisterCoalescer's good work. I'll change this to more sane behaviour soon. Cheers, Lang. On Sat, Jul 17, 2010 at 5:34 PM, Lang Hames wrote: > Author: lhames > Date: Sat Jul 17 02:34:01 2010 > New Revision: 108615 > > URL: http://llvm.org/viewvc/llvm-project?rev=108615&view=rev > Log: > LoopSplitter - intended to split live intervals over loop boundaries. > Still very much under development. Comments and fixes will be forthcoming. > > (This commit includes some small tweaks to LiveIntervals & LoopInfo to > support the splitter) > > > Added: > llvm/trunk/lib/CodeGen/Splitter.cpp > llvm/trunk/lib/CodeGen/Splitter.h > Modified: > llvm/trunk/include/llvm/Analysis/LoopInfo.h > llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h > > Modified: llvm/trunk/include/llvm/Analysis/LoopInfo.h > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/LoopInfo.h?rev=108615&r1=108614&r2=108615&view=diff > > ============================================================================== > --- llvm/trunk/include/llvm/Analysis/LoopInfo.h (original) > +++ llvm/trunk/include/llvm/Analysis/LoopInfo.h Sat Jul 17 02:34:01 2010 > @@ -229,9 +229,12 @@ > return 0; > } > > + /// Edge type. > + typedef std::pair Edge; > + > /// getExitEdges - Return all pairs of (_inside_block_,_outside_block_). > - typedef std::pair Edge; > - void getExitEdges(SmallVectorImpl &ExitEdges) const { > + template > + void getExitEdges(SmallVectorImpl &ExitEdges) const { > // Sort the blocks vector so that we can use binary search to do quick > // lookups. > SmallVector LoopBBs(block_begin(), block_end()); > @@ -244,7 +247,7 @@ > I != E; ++I) > if (!std::binary_search(LoopBBs.begin(), LoopBBs.end(), *I)) > // Not in current loop? It must be an exit block. > - ExitEdges.push_back(std::make_pair(*BI, *I)); > + ExitEdges.push_back(EdgeT(*BI, *I)); > } > > /// getLoopPreheader - If there is a preheader for this loop, return it. > A > > Modified: llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h?rev=108615&r1=108614&r2=108615&view=diff > > ============================================================================== > --- llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h (original) > +++ llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h Sat Jul 17 > 02:34:01 2010 > @@ -197,6 +197,26 @@ > return indexes_->getMBBEndIdx(mbb); > } > > + bool isLiveInToMBB(const LiveInterval &li, > + const MachineBasicBlock *mbb) const { > + return li.liveAt(getMBBStartIdx(mbb)); > + } > + > + LiveRange* findEnteringRange(LiveInterval &li, > + const MachineBasicBlock *mbb) { > + return li.getLiveRangeContaining(getMBBStartIdx(mbb)); > + } > + > + bool isLiveOutOfMBB(const LiveInterval &li, > + const MachineBasicBlock *mbb) const { > + return li.liveAt(getMBBEndIdx(mbb).getPrevSlot()); > + } > + > + LiveRange* findExitingRange(LiveInterval &li, > + const MachineBasicBlock *mbb) { > + return li.getLiveRangeContaining(getMBBEndIdx(mbb).getPrevSlot()); > + } > + > MachineBasicBlock* getMBBFromIndex(SlotIndex index) const { > return indexes_->getMBBFromIndex(index); > } > @@ -217,6 +237,10 @@ > indexes_->replaceMachineInstrInMaps(MI, NewMI); > } > > + void InsertMBBInMaps(MachineBasicBlock *MBB) { > + indexes_->insertMBBInMaps(MBB); > + } > + > bool findLiveInMBBs(SlotIndex Start, SlotIndex End, > SmallVectorImpl &MBBs) const { > return indexes_->findLiveInMBBs(Start, End, MBBs); > > Added: llvm/trunk/lib/CodeGen/Splitter.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Splitter.cpp?rev=108615&view=auto > > ============================================================================== > --- llvm/trunk/lib/CodeGen/Splitter.cpp (added) > +++ llvm/trunk/lib/CodeGen/Splitter.cpp Sat Jul 17 02:34:01 2010 > @@ -0,0 +1,819 @@ > +//===-- llvm/CodeGen/Splitter.cpp - Splitter > -----------------------------===// > +// > +// The LLVM Compiler Infrastructure > +// > +// This file is distributed under the University of Illinois Open Source > +// License. See LICENSE.TXT for details. > +// > > +//===----------------------------------------------------------------------===// > + > +#define DEBUG_TYPE "loopsplitter" > + > +#include "Splitter.h" > + > +#include "SimpleRegisterCoalescing.h" > +#include "llvm/Module.h" > +#include "llvm/CodeGen/CalcSpillWeights.h" > +#include "llvm/CodeGen/LiveIntervalAnalysis.h" > +#include "llvm/CodeGen/LiveStackAnalysis.h" > +#include "llvm/CodeGen/MachineDominators.h" > +#include "llvm/CodeGen/MachineInstrBuilder.h" > +#include "llvm/CodeGen/MachineFunction.h" > +#include "llvm/CodeGen/MachineRegisterInfo.h" > +#include "llvm/CodeGen/SlotIndexes.h" > +#include "llvm/Support/Debug.h" > +#include "llvm/Support/raw_ostream.h" > +#include "llvm/Target/TargetMachine.h" > +#include "llvm/Target/TargetInstrInfo.h" > + > +using namespace llvm; > + > +char LoopSplitter::ID = 0; > +static RegisterPass > +X("loop-splitting", "Split virtual regists across loop boundaries."); > + > +namespace llvm { > + > + class StartSlotComparator { > + public: > + StartSlotComparator(LiveIntervals &lis) : lis(lis) {} > + bool operator()(const MachineBasicBlock *mbb1, > + const MachineBasicBlock *mbb2) const { > + return lis.getMBBStartIdx(mbb1) < lis.getMBBStartIdx(mbb2); > + } > + private: > + LiveIntervals &lis; > + }; > + > + class LoopSplit { > + public: > + LoopSplit(LoopSplitter &ls, LiveInterval &li, MachineLoop &loop) > + : ls(ls), li(li), loop(loop), valid(true), inSplit(false), newLI(0) > { > + assert(TargetRegisterInfo::isVirtualRegister(li.reg) && > + "Cannot split physical registers."); > + } > + > + LiveInterval& getLI() const { return li; } > + > + MachineLoop& getLoop() const { return loop; } > + > + bool isValid() const { return valid; } > + > + bool isWorthwhile() const { return valid && (inSplit || > !outSplits.empty()); } > + > + void invalidate() { valid = false; } > + > + void splitIncoming() { inSplit = true; } > + > + void splitOutgoing(MachineLoop::Edge &edge) { outSplits.insert(edge); > } > + > + void addLoopInstr(MachineInstr *i) { loopInstrs.push_back(i); } > + > + void apply() { > + assert(valid && "Attempt to apply invalid split."); > + applyIncoming(); > + applyOutgoing(); > + copyRanges(); > + renameInside(); > + } > + > + private: > + LoopSplitter &ls; > + LiveInterval &li; > + MachineLoop &loop; > + bool valid, inSplit; > + std::set outSplits; > + std::vector loopInstrs; > + > + LiveInterval *newLI; > + std::map vniMap; > + > + LiveInterval* getNewLI() { > + if (newLI == 0) { > + const TargetRegisterClass *trc = ls.mri->getRegClass(li.reg); > + unsigned vreg = ls.mri->createVirtualRegister(trc); > + newLI = &ls.lis->getOrCreateInterval(vreg); > + } > + return newLI; > + } > + > + VNInfo* getNewVNI(VNInfo *oldVNI) { > + VNInfo *newVNI = vniMap[oldVNI]; > + > + if (newVNI == 0) { > + newVNI = getNewLI()->createValueCopy(oldVNI, > + > ls.lis->getVNInfoAllocator()); > + vniMap[oldVNI] = newVNI; > + } > + > + return newVNI; > + } > + > + void applyIncoming() { > + if (!inSplit) { > + return; > + } > + > + MachineBasicBlock *preHeader = loop.getLoopPreheader(); > + if (preHeader == 0) { > + assert(ls.canInsertPreHeader(loop) && > + "Can't insert required preheader."); > + preHeader = &ls.insertPreHeader(loop); > + } > + > + LiveRange *preHeaderRange = > + ls.lis->findExitingRange(li, preHeader); > + assert(preHeaderRange != 0 && "Range not live into preheader."); > + > + // Insert the new copy. > + MachineInstr *copy = BuildMI(*preHeader, > + preHeader->getFirstTerminator(), > + DebugLoc(), > + ls.tii->get(TargetOpcode::COPY)) > + .addReg(getNewLI()->reg, RegState::Define) > + .addReg(li.reg, RegState::Kill); > + > + ls.lis->InsertMachineInstrInMaps(copy); > + > + SlotIndex copyDefIdx = > ls.lis->getInstructionIndex(copy).getDefIndex(); > + > + VNInfo *newVal = getNewVNI(preHeaderRange->valno); > + newVal->def = copyDefIdx; > + newVal->setCopy(copy); > + newVal->setIsDefAccurate(true); > + li.removeRange(copyDefIdx, ls.lis->getMBBEndIdx(preHeader), true); > + > + getNewLI()->addRange(LiveRange(copyDefIdx, > + ls.lis->getMBBEndIdx(preHeader), > + newVal)); > + } > + > + void applyOutgoing() { > + > + for (std::set::iterator osItr = > outSplits.begin(), > + osEnd = outSplits.end(); > + osItr != osEnd; ++osItr) { > + MachineLoop::Edge edge = *osItr; > + MachineBasicBlock *outBlock = edge.second; > + if (ls.isCriticalEdge(edge)) { > + assert(ls.canSplitEdge(edge) && "Unsplitable critical edge."); > + outBlock = &ls.splitEdge(edge, loop); > + } > + LiveRange *outRange = ls.lis->findEnteringRange(li, outBlock); > + assert(outRange != 0 && "No exiting range?"); > + > + MachineInstr *copy = BuildMI(*outBlock, outBlock->begin(), > + DebugLoc(), > + ls.tii->get(TargetOpcode::COPY)) > + .addReg(li.reg, RegState::Define) > + .addReg(getNewLI()->reg, RegState::Kill); > + > + ls.lis->InsertMachineInstrInMaps(copy); > + > + SlotIndex copyDefIdx = > ls.lis->getInstructionIndex(copy).getDefIndex(); > + > + // Blow away output range definition. > + outRange->valno->def = ls.lis->getInvalidIndex(); > + outRange->valno->setIsDefAccurate(false); > + li.removeRange(ls.lis->getMBBStartIdx(outBlock), copyDefIdx); > + > + VNInfo *newVal = > + > getNewLI()->getNextValue(SlotIndex(ls.lis->getMBBStartIdx(outBlock), > + true), > + 0, false, > ls.lis->getVNInfoAllocator()); > + > + getNewLI()->addRange(LiveRange(ls.lis->getMBBStartIdx(outBlock), > + copyDefIdx, newVal)); > + > + } > + } > + > + void copyRange(LiveRange &lr) { > + std::pair lsr = > + ls.getLoopSubRange(lr, loop); > + > + if (!lsr.first) > + return; > + > + LiveRange loopRange(lsr.second.first, lsr.second.second, > + getNewVNI(lr.valno)); > + > + li.removeRange(loopRange.start, loopRange.end, true); > + > + getNewLI()->addRange(loopRange); > + } > + > + void copyRanges() { > + for (std::vector::iterator iItr = loopInstrs.begin(), > + iEnd = loopInstrs.end(); > + iItr != iEnd; ++iItr) { > + MachineInstr &instr = **iItr; > + SlotIndex instrIdx = ls.lis->getInstructionIndex(&instr); > + if (instr.modifiesRegister(li.reg, 0)) { > + LiveRange *defRange = > + li.getLiveRangeContaining(instrIdx.getDefIndex()); > + if (defRange != 0) // May have caught this already. > + copyRange(*defRange); > + } > + if (instr.readsRegister(li.reg, 0)) { > + LiveRange *useRange = > + li.getLiveRangeContaining(instrIdx.getUseIndex()); > + if (useRange != 0) { // May have caught this already. > + copyRange(*useRange); > + } > + } > + } > + > + for (MachineLoop::block_iterator bbItr = loop.block_begin(), > + bbEnd = loop.block_end(); > + bbItr != bbEnd; ++bbItr) { > + MachineBasicBlock &loopBlock = **bbItr; > + LiveRange *enteringRange = > + ls.lis->findEnteringRange(li, &loopBlock); > + if (enteringRange != 0) { > + copyRange(*enteringRange); > + } > + } > + } > + > + void renameInside() { > + for (std::vector::iterator iItr = loopInstrs.begin(), > + iEnd = loopInstrs.end(); > + iItr != iEnd; ++iItr) { > + MachineInstr &instr = **iItr; > + for (unsigned i = 0; i < instr.getNumOperands(); ++i) { > + MachineOperand &mop = instr.getOperand(i); > + if (mop.isReg() && mop.getReg() == li.reg) { > + mop.setReg(getNewLI()->reg); > + } > + } > + } > + } > + > + }; > + > + void LoopSplitter::getAnalysisUsage(AnalysisUsage &au) const { > + au.addRequired(); > + au.addPreserved(); > + au.addRequired(); > + au.addPreserved(); > + au.addPreserved(); > + au.addPreserved(); > + au.addPreserved(); > + au.addRequired(); > + au.addPreserved(); > + au.addRequired(); > + au.addPreserved(); > + MachineFunctionPass::getAnalysisUsage(au); > + } > + > + bool LoopSplitter::runOnMachineFunction(MachineFunction &fn) { > + > + mf = &fn; > + mri = &mf->getRegInfo(); > + tii = mf->getTarget().getInstrInfo(); > + tri = mf->getTarget().getRegisterInfo(); > + sis = &getAnalysis(); > + lis = &getAnalysis(); > + mli = &getAnalysis(); > + mdt = &getAnalysis(); > + > + fqn = mf->getFunction()->getParent()->getModuleIdentifier() + "." + > + mf->getFunction()->getName().str(); > + > + dbgs() << "Splitting " << mf->getFunction()->getName() << "."; > + > + dumpOddTerminators(); > + > +// dbgs() << "----------------------------------------\n"; > +// lis->dump(); > +// dbgs() << "----------------------------------------\n"; > + > +// std::deque loops; > +// std::copy(mli->begin(), mli->end(), std::back_inserter(loops)); > +// dbgs() << "Loops:\n"; > +// while (!loops.empty()) { > +// MachineLoop &loop = *loops.front(); > +// loops.pop_front(); > +// std::copy(loop.begin(), loop.end(), std::back_inserter(loops)); > + > +// dumpLoopInfo(loop); > +// } > + > + //lis->dump(); > + //exit(0); > + > + // Setup initial intervals. > + for (LiveIntervals::iterator liItr = lis->begin(), liEnd = lis->end(); > + liItr != liEnd; ++liItr) { > + LiveInterval *li = liItr->second; > + > + if (TargetRegisterInfo::isVirtualRegister(li->reg) && > + !lis->intervalIsInOneMBB(*li)) { > + intervals.push_back(li); > + } > + } > + > + processIntervals(); > + > + intervals.clear(); > + > +// dbgs() << "----------------------------------------\n"; > +// lis->dump(); > +// dbgs() << "----------------------------------------\n"; > + > + dumpOddTerminators(); > + > + //exit(1); > + > + return false; > + } > + > + void LoopSplitter::releaseMemory() { > + fqn.clear(); > + intervals.clear(); > + loopRangeMap.clear(); > + } > + > + void LoopSplitter::dumpOddTerminators() { > + for (MachineFunction::iterator bbItr = mf->begin(), bbEnd = mf->end(); > + bbItr != bbEnd; ++bbItr) { > + MachineBasicBlock *mbb = &*bbItr; > + MachineBasicBlock *a = 0, *b = 0; > + SmallVector c; > + if (tii->AnalyzeBranch(*mbb, a, b, c)) { > + dbgs() << "MBB#" << mbb->getNumber() << " has multiway > terminator.\n"; > + dbgs() << " Terminators:\n"; > + for (MachineBasicBlock::iterator iItr = mbb->begin(), iEnd = > mbb->end(); > + iItr != iEnd; ++iItr) { > + MachineInstr *instr= &*iItr; > + dbgs() << " " << *instr << ""; > + } > + dbgs() << "\n Listed successors: [ "; > + for (MachineBasicBlock::succ_iterator sItr = mbb->succ_begin(), > sEnd = mbb->succ_end(); > + sItr != sEnd; ++sItr) { > + MachineBasicBlock *succMBB = *sItr; > + dbgs() << succMBB->getNumber() << " "; > + } > + dbgs() << "]\n\n"; > + } > + } > + } > + > + void LoopSplitter::dumpLoopInfo(MachineLoop &loop) { > + MachineBasicBlock &headerBlock = *loop.getHeader(); > + typedef SmallVector ExitEdgesList; > + ExitEdgesList exitEdges; > + loop.getExitEdges(exitEdges); > + > + dbgs() << " Header: BB#" << headerBlock.getNumber() << ", Contains: [ > "; > + for (std::vector::const_iterator > + subBlockItr = loop.getBlocks().begin(), > + subBlockEnd = loop.getBlocks().end(); > + subBlockItr != subBlockEnd; ++subBlockItr) { > + MachineBasicBlock &subBlock = **subBlockItr; > + dbgs() << "BB#" << subBlock.getNumber() << " "; > + } > + dbgs() << "], Exit edges: [ "; > + for (ExitEdgesList::iterator exitEdgeItr = exitEdges.begin(), > + exitEdgeEnd = exitEdges.end(); > + exitEdgeItr != exitEdgeEnd; ++exitEdgeItr) { > + MachineLoop::Edge &exitEdge = *exitEdgeItr; > + dbgs() << "(MBB#" << exitEdge.first->getNumber() > + << ", MBB#" << exitEdge.second->getNumber() << ") "; > + } > + dbgs() << "], Sub-Loop Headers: [ "; > + for (MachineLoop::iterator subLoopItr = loop.begin(), > + subLoopEnd = loop.end(); > + subLoopItr != subLoopEnd; ++subLoopItr) { > + MachineLoop &subLoop = **subLoopItr; > + MachineBasicBlock &subLoopBlock = *subLoop.getHeader(); > + dbgs() << "BB#" << subLoopBlock.getNumber() << " "; > + } > + dbgs() << "]\n"; > + } > + > + void LoopSplitter::updateTerminators(MachineBasicBlock &mbb) { > + mbb.updateTerminator(); > + > + for (MachineBasicBlock::iterator miItr = mbb.begin(), miEnd = > mbb.end(); > + miItr != miEnd; ++miItr) { > + if (lis->isNotInMIMap(miItr)) { > + lis->InsertMachineInstrInMaps(miItr); > + } > + } > + } > + > + bool LoopSplitter::canInsertPreHeader(MachineLoop &loop) { > + MachineBasicBlock *header = loop.getHeader(); > + MachineBasicBlock *a = 0, *b = 0; > + SmallVector c; > + > + for (MachineBasicBlock::pred_iterator pbItr = header->pred_begin(), > + pbEnd = header->pred_end(); > + pbItr != pbEnd; ++pbItr) { > + MachineBasicBlock *predBlock = *pbItr; > + if (!!tii->AnalyzeBranch(*predBlock, a, b, c)) { > + return false; > + } > + } > + > + MachineFunction::iterator headerItr(header); > + if (headerItr == mf->begin()) > + return true; > + MachineBasicBlock *headerLayoutPred = llvm::prior(headerItr); > + assert(headerLayoutPred != 0 && "Header should have layout pred."); > + > + return (!tii->AnalyzeBranch(*headerLayoutPred, a, b, c)); > + } > + > + MachineBasicBlock& LoopSplitter::insertPreHeader(MachineLoop &loop) { > + assert(loop.getLoopPreheader() == 0 && "Loop already has preheader."); > + > + MachineBasicBlock &header = *loop.getHeader(); > + > + // Save the preds - we'll need to update them once we insert the > preheader. > + typedef std::set HeaderPreds; > + HeaderPreds headerPreds; > + > + for (MachineBasicBlock::pred_iterator predItr = header.pred_begin(), > + predEnd = header.pred_end(); > + predItr != predEnd; ++predItr) { > + if (!loop.contains(*predItr)) > + headerPreds.insert(*predItr); > + } > + > + assert(!headerPreds.empty() && "No predecessors for header?"); > + > + //dbgs() << fqn << " MBB#" << header.getNumber() << " inserting > preheader..."; > + > + MachineBasicBlock *preHeader = > + mf->CreateMachineBasicBlock(header.getBasicBlock()); > + > + assert(preHeader != 0 && "Failed to create pre-header."); > + > + mf->insert(header, preHeader); > + > + for (HeaderPreds::iterator hpItr = headerPreds.begin(), > + hpEnd = headerPreds.end(); > + hpItr != hpEnd; ++hpItr) { > + assert(*hpItr != 0 && "How'd a null predecessor get into this > set?"); > + MachineBasicBlock &hp = **hpItr; > + hp.ReplaceUsesOfBlockWith(&header, preHeader); > + } > + preHeader->addSuccessor(&header); > + > + MachineBasicBlock *oldLayoutPred = > + llvm::prior(MachineFunction::iterator(preHeader)); > + if (oldLayoutPred != 0) { > + updateTerminators(*oldLayoutPred); > + } > + > + lis->InsertMBBInMaps(preHeader); > + > + if (MachineLoop *parentLoop = loop.getParentLoop()) { > + assert(parentLoop->getHeader() != loop.getHeader() && > + "Parent loop has same header?"); > + parentLoop->addBasicBlockToLoop(preHeader, mli->getBase()); > + > + // Invalidate all parent loop ranges. > + while (parentLoop != 0) { > + loopRangeMap.erase(parentLoop); > + parentLoop = parentLoop->getParentLoop(); > + } > + } > + > + for (LiveIntervals::iterator liItr = lis->begin(), > + liEnd = lis->end(); > + liItr != liEnd; ++liItr) { > + LiveInterval &li = *liItr->second; > + > + // Is this safe for physregs? > + // TargetRegisterInfo::isPhysicalRegister(li.reg) || > + if (!lis->isLiveInToMBB(li, &header)) > + continue; > + > + if (lis->isLiveInToMBB(li, preHeader)) { > + assert(lis->isLiveOutOfMBB(li, preHeader) && > + "Range terminates in newly added preheader?"); > + continue; > + } > + > + bool insertRange = false; > + > + for (MachineBasicBlock::pred_iterator predItr = > preHeader->pred_begin(), > + predEnd = > preHeader->pred_end(); > + predItr != predEnd; ++predItr) { > + MachineBasicBlock *predMBB = *predItr; > + if (lis->isLiveOutOfMBB(li, predMBB)) { > + insertRange = true; > + break; > + } > + } > + > + if (!insertRange) > + continue; > + > + VNInfo *newVal = li.getNextValue(lis->getMBBStartIdx(preHeader), > + 0, false, > lis->getVNInfoAllocator()); > + li.addRange(LiveRange(lis->getMBBStartIdx(preHeader), > + lis->getMBBEndIdx(preHeader), > + newVal)); > + } > + > + > + //dbgs() << "Dumping SlotIndexes:\n"; > + //sis->dump(); > + > + //dbgs() << "done. (Added MBB#" << preHeader->getNumber() << ")\n"; > + > + return *preHeader; > + } > + > + bool LoopSplitter::isCriticalEdge(MachineLoop::Edge &edge) { > + assert(edge.first->succ_size() > 1 && "Non-sensical edge."); > + if (edge.second->pred_size() > 1) > + return true; > + return false; > + } > + > + bool LoopSplitter::canSplitEdge(MachineLoop::Edge &edge) { > + MachineFunction::iterator outBlockItr(edge.second); > + if (outBlockItr == mf->begin()) > + return true; > + MachineBasicBlock *outBlockLayoutPred = llvm::prior(outBlockItr); > + assert(outBlockLayoutPred != 0 && "Should have a layout pred if > out!=begin."); > + MachineBasicBlock *a = 0, *b = 0; > + SmallVector c; > + return (!tii->AnalyzeBranch(*outBlockLayoutPred, a, b, c) && > + !tii->AnalyzeBranch(*edge.first, a, b, c)); > + } > + > + MachineBasicBlock& LoopSplitter::splitEdge(MachineLoop::Edge &edge, > + MachineLoop &loop) { > + > + MachineBasicBlock &inBlock = *edge.first; > + MachineBasicBlock &outBlock = *edge.second; > + > + assert((inBlock.succ_size() > 1) && (outBlock.pred_size() > 1) && > + "Splitting non-critical edge?"); > + > + //dbgs() << fqn << " Splitting edge (MBB#" << inBlock.getNumber() > + // << " -> MBB#" << outBlock.getNumber() << ")..."; > + > + MachineBasicBlock *splitBlock = > + mf->CreateMachineBasicBlock(); > + > + assert(splitBlock != 0 && "Failed to create split block."); > + > + mf->insert(&outBlock, splitBlock); > + > + inBlock.ReplaceUsesOfBlockWith(&outBlock, splitBlock); > + splitBlock->addSuccessor(&outBlock); > + > + MachineBasicBlock *oldLayoutPred = > + llvm::prior(MachineFunction::iterator(splitBlock)); > + if (oldLayoutPred != 0) { > + updateTerminators(*oldLayoutPred); > + } > + > + lis->InsertMBBInMaps(splitBlock); > + > + loopRangeMap.erase(&loop); > + > + MachineLoop *splitParentLoop = loop.getParentLoop(); > + while (splitParentLoop != 0 && > + !splitParentLoop->contains(&outBlock)) { > + splitParentLoop = splitParentLoop->getParentLoop(); > + } > + > + if (splitParentLoop != 0) { > + assert(splitParentLoop->contains(&loop) && > + "Split-block parent doesn't contain original loop?"); > + splitParentLoop->addBasicBlockToLoop(splitBlock, mli->getBase()); > + > + // Invalidate all parent loop ranges. > + while (splitParentLoop != 0) { > + loopRangeMap.erase(splitParentLoop); > + splitParentLoop = splitParentLoop->getParentLoop(); > + } > + } > + > + > + for (LiveIntervals::iterator liItr = lis->begin(), > + liEnd = lis->end(); > + liItr != liEnd; ++liItr) { > + LiveInterval &li = *liItr->second; > + bool intersects = lis->isLiveOutOfMBB(li, &inBlock) && > + lis->isLiveInToMBB(li, &outBlock); > + if (lis->isLiveInToMBB(li, splitBlock)) { > + if (!intersects) { > + li.removeRange(lis->getMBBStartIdx(splitBlock), > + lis->getMBBEndIdx(splitBlock), true); > + } > + } else if (intersects) { > + VNInfo *newVal = li.getNextValue(lis->getMBBStartIdx(splitBlock), > + 0, false, > lis->getVNInfoAllocator()); > + li.addRange(LiveRange(lis->getMBBStartIdx(splitBlock), > + lis->getMBBEndIdx(splitBlock), > + newVal)); > + } > + } > + > + //dbgs() << "done. (Added MBB#" << splitBlock->getNumber() << ")\n"; > + > + return *splitBlock; > + } > + > + LoopSplitter::LoopRanges& LoopSplitter::getLoopRanges(MachineLoop &loop) > { > + typedef std::set LoopMBBSet; > + LoopRangeMap::iterator lrItr = loopRangeMap.find(&loop); > + if (lrItr == loopRangeMap.end()) { > + LoopMBBSet loopMBBs((StartSlotComparator(*lis))); > + std::copy(loop.block_begin(), loop.block_end(), > + std::inserter(loopMBBs, loopMBBs.begin())); > + > + assert(!loopMBBs.empty() && "No blocks in loop?"); > + > + LoopRanges &loopRanges = loopRangeMap[&loop]; > + assert(loopRanges.empty() && "Loop encountered but not processed?"); > + SlotIndex oldEnd = lis->getMBBEndIdx(*loopMBBs.begin()); > + loopRanges.push_back( > + std::make_pair(lis->getMBBStartIdx(*loopMBBs.begin()), > + lis->getInvalidIndex())); > + for (LoopMBBSet::iterator curBlockItr = > llvm::next(loopMBBs.begin()), > + curBlockEnd = loopMBBs.end(); > + curBlockItr != curBlockEnd; ++curBlockItr) { > + SlotIndex newStart = lis->getMBBStartIdx(*curBlockItr); > + if (newStart != oldEnd) { > + loopRanges.back().second = oldEnd; > + loopRanges.push_back(std::make_pair(newStart, > + lis->getInvalidIndex())); > + } > + oldEnd = lis->getMBBEndIdx(*curBlockItr); > + } > + > + loopRanges.back().second = > + lis->getMBBEndIdx(*llvm::prior(loopMBBs.end())); > + > + return loopRanges; > + } > + return lrItr->second; > + } > + > + std::pair LoopSplitter::getLoopSubRange( > + const LiveRange > &lr, > + MachineLoop > &loop) { > + LoopRanges &loopRanges = getLoopRanges(loop); > + LoopRanges::iterator lrItr = loopRanges.begin(), > + lrEnd = loopRanges.end(); > + while (lrItr != lrEnd && lr.start >= lrItr->second) { > + ++lrItr; > + } > + > + if (lrItr == lrEnd) { > + SlotIndex invalid = lis->getInvalidIndex(); > + return std::make_pair(false, SlotPair(invalid, invalid)); > + } > + > + SlotIndex srStart(lr.start < lrItr->first ? lrItr->first : lr.start); > + SlotIndex srEnd(lr.end > lrItr->second ? lrItr->second : lr.end); > + > + return std::make_pair(true, SlotPair(srStart, srEnd)); > + } > + > + void LoopSplitter::dumpLoopRanges(MachineLoop &loop) { > + LoopRanges &loopRanges = getLoopRanges(loop); > + dbgs() << "For loop MBB#" << loop.getHeader()->getNumber() << ", > subranges are: [ "; > + for (LoopRanges::iterator lrItr = loopRanges.begin(), lrEnd = > loopRanges.end(); > + lrItr != lrEnd; ++lrItr) { > + dbgs() << "[" << lrItr->first << ", " << lrItr->second << ") "; > + } > + dbgs() << "]\n"; > + } > + > + void LoopSplitter::processHeader(LoopSplit &split) { > + MachineBasicBlock &header = *split.getLoop().getHeader(); > + //dbgs() << " Processing loop header BB#" << header.getNumber() << > "\n"; > + > + if (!lis->isLiveInToMBB(split.getLI(), &header)) > + return; // Not live in, but nothing wrong so far. > + > + MachineBasicBlock *preHeader = split.getLoop().getLoopPreheader(); > + if (!preHeader) { > + > + if (!canInsertPreHeader(split.getLoop())) { > + split.invalidate(); > + return; // Couldn't insert a pre-header. Bail on this interval. > + } > + > + for (MachineBasicBlock::pred_iterator predItr = header.pred_begin(), > + predEnd = header.pred_end(); > + predItr != predEnd; ++predItr) { > + if (lis->isLiveOutOfMBB(split.getLI(), *predItr)) { > + split.splitIncoming(); > + break; > + } > + } > + } else if (lis->isLiveOutOfMBB(split.getLI(), preHeader)) { > + split.splitIncoming(); > + } > + } > + > + void LoopSplitter::processLoopExits(LoopSplit &split) { > + typedef SmallVector ExitEdgesList; > + ExitEdgesList exitEdges; > + split.getLoop().getExitEdges(exitEdges); > + > + //dbgs() << " Processing loop exits:\n"; > + > + for (ExitEdgesList::iterator exitEdgeItr = exitEdges.begin(), > + exitEdgeEnd = exitEdges.end(); > + exitEdgeItr != exitEdgeEnd; ++exitEdgeItr) { > + MachineLoop::Edge exitEdge = *exitEdgeItr; > + > + LiveRange *inRange = > + > split.getLI().getLiveRangeContaining(lis->getMBBEndIdx(exitEdge.first).getPrevSlot()); > + LiveRange *outRange = > + > split.getLI().getLiveRangeContaining(lis->getMBBStartIdx(exitEdge.second)); > + > + if (outRange != 0) { > + if (isCriticalEdge(exitEdge) && !canSplitEdge(exitEdge)) { > + split.invalidate(); > + return; > + } > + > + split.splitOutgoing(exitEdge); > + } > + } > + } > + > + void LoopSplitter::processLoopUses(LoopSplit &split) { > + std::set processed; > + > + for (MachineRegisterInfo::reg_iterator > + rItr = mri->reg_begin(split.getLI().reg), > + rEnd = mri->reg_end(); > + rItr != rEnd; ++rItr) { > + MachineInstr &instr = *rItr; > + if (split.getLoop().contains(&instr) && processed.count(&instr) == > 0) { > + split.addLoopInstr(&instr); > + processed.insert(&instr); > + } > + } > + > + //dbgs() << " Rewriting reg" << li.reg << " to reg" << newLI->reg > + // << " in blocks [ "; > + //dbgs() << "]\n"; > + } > + > + bool LoopSplitter::splitOverLoop(LiveInterval &li, MachineLoop &loop) { > + assert(TargetRegisterInfo::isVirtualRegister(li.reg) && > + "Attempt to split physical register."); > + > + LoopSplit split(*this, li, loop); > + processHeader(split); > + if (split.isValid()) > + processLoopExits(split); > + if (split.isValid()) > + processLoopUses(split); > + if (split.isValid() /* && split.isWorthwhile() */) { > + split.apply(); > + DEBUG(dbgs() << "Success.\n"); > + return true; > + } > + DEBUG(dbgs() << "Failed.\n"); > + return false; > + } > + > + void LoopSplitter::processInterval(LiveInterval &li) { > + std::deque loops; > + std::copy(mli->begin(), mli->end(), std::back_inserter(loops)); > + > + while (!loops.empty()) { > + MachineLoop &loop = *loops.front(); > + loops.pop_front(); > + DEBUG( > + dbgs() << fqn << " reg" << li.reg << " " << li.weight << " BB#" > + << loop.getHeader()->getNumber() << " "; > + ); > + if (!splitOverLoop(li, loop)) { > + // Couldn't split over outer loop, schedule sub-loops to be > checked. > + std::copy(loop.begin(), loop.end(), std::back_inserter(loops)); > + } > + } > + } > + > + void LoopSplitter::processIntervals() { > + while (!intervals.empty()) { > + LiveInterval &li = *intervals.front(); > + intervals.pop_front(); > + > + assert(!lis->intervalIsInOneMBB(li) && > + "Single interval in process worklist."); > + > + processInterval(li); > + } > + } > + > +} > > Added: llvm/trunk/lib/CodeGen/Splitter.h > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Splitter.h?rev=108615&view=auto > > ============================================================================== > --- llvm/trunk/lib/CodeGen/Splitter.h (added) > +++ llvm/trunk/lib/CodeGen/Splitter.h Sat Jul 17 02:34:01 2010 > @@ -0,0 +1,99 @@ > +//===-- llvm/CodeGen/Splitter.h - Splitter -*- C++ > -*----------------------===// > +// > +// The LLVM Compiler Infrastructure > +// > +// This file is distributed under the University of Illinois Open Source > +// License. See LICENSE.TXT for details. > +// > > +//===----------------------------------------------------------------------===// > + > +#ifndef LLVM_CODEGEN_SPLITTER_H > +#define LLVM_CODEGEN_SPLITTER_H > + > +#include "llvm/CodeGen/MachineFunctionPass.h" > +#include "llvm/CodeGen/MachineLoopInfo.h" > +#include "llvm/CodeGen/SlotIndexes.h" > + > +#include > +#include > +#include > +#include > + > +namespace llvm { > + > + class LiveInterval; > + class LiveIntervals; > + class LiveRange; > + class LoopSplit; > + class MachineDominatorTree; > + class MachineRegisterInfo; > + class SlotIndexes; > + class TargetInstrInfo; > + class VNInfo; > + > + class LoopSplitter : public MachineFunctionPass { > + friend class LoopSplit; > + public: > + static char ID; > + > + LoopSplitter() : MachineFunctionPass(&ID) {} > + > + virtual void getAnalysisUsage(AnalysisUsage &au) const; > + > + virtual bool runOnMachineFunction(MachineFunction &fn); > + > + virtual void releaseMemory(); > + > + > + private: > + > + MachineFunction *mf; > + LiveIntervals *lis; > + MachineLoopInfo *mli; > + MachineRegisterInfo *mri; > + MachineDominatorTree *mdt; > + SlotIndexes *sis; > + const TargetInstrInfo *tii; > + const TargetRegisterInfo *tri; > + > + std::string fqn; > + std::deque intervals; > + > + typedef std::pair SlotPair; > + typedef std::vector LoopRanges; > + typedef std::map LoopRangeMap; > + LoopRangeMap loopRangeMap; > + > + void dumpLoopInfo(MachineLoop &loop); > + > + void dumpOddTerminators(); > + > + void updateTerminators(MachineBasicBlock &mbb); > + > + bool canInsertPreHeader(MachineLoop &loop); > + MachineBasicBlock& insertPreHeader(MachineLoop &loop); > + > + bool isCriticalEdge(MachineLoop::Edge &edge); > + bool canSplitEdge(MachineLoop::Edge &edge); > + MachineBasicBlock& splitEdge(MachineLoop::Edge &edge, MachineLoop > &loop); > + > + LoopRanges& getLoopRanges(MachineLoop &loop); > + std::pair getLoopSubRange(const LiveRange &lr, > + MachineLoop &loop); > + > + void dumpLoopRanges(MachineLoop &loop); > + > + void processHeader(LoopSplit &split); > + void processLoopExits(LoopSplit &split); > + void processLoopUses(LoopSplit &split); > + > + bool splitOverLoop(LiveInterval &li, MachineLoop &loop); > + > + void processInterval(LiveInterval &li); > + > + void processIntervals(); > + }; > + > +} > + > +#endif > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100717/cd32a6d9/attachment.html From lhames at gmail.com Sat Jul 17 04:21:53 2010 From: lhames at gmail.com (Lang Hames) Date: Sat, 17 Jul 2010 09:21:53 -0000 Subject: [llvm-commits] [llvm] r108616 - /llvm/trunk/include/llvm/Analysis/LoopInfo.h Message-ID: <20100717092153.81E7B2A6C12C@llvm.org> Author: lhames Date: Sat Jul 17 04:21:53 2010 New Revision: 108616 URL: http://llvm.org/viewvc/llvm-project?rev=108616&view=rev Log: Switched to array_pod_sort as per Chris's suggestion. Modified: llvm/trunk/include/llvm/Analysis/LoopInfo.h Modified: llvm/trunk/include/llvm/Analysis/LoopInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/LoopInfo.h?rev=108616&r1=108615&r2=108616&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/LoopInfo.h (original) +++ llvm/trunk/include/llvm/Analysis/LoopInfo.h Sat Jul 17 04:21:53 2010 @@ -35,6 +35,7 @@ #include "llvm/ADT/DepthFirstIterator.h" #include "llvm/ADT/GraphTraits.h" #include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/STLExtras.h" #include "llvm/Analysis/Dominators.h" #include "llvm/Support/CFG.h" #include "llvm/Support/raw_ostream.h" @@ -238,7 +239,7 @@ // Sort the blocks vector so that we can use binary search to do quick // lookups. SmallVector LoopBBs(block_begin(), block_end()); - std::sort(LoopBBs.begin(), LoopBBs.end()); + array_pod_sort(LoopBBs.begin(), LoopBBs.end()); typedef GraphTraits BlockTraits; for (block_iterator BI = block_begin(), BE = block_end(); BI != BE; ++BI) From lhames at gmail.com Sat Jul 17 06:43:07 2010 From: lhames at gmail.com (Lang Hames) Date: Sat, 17 Jul 2010 11:43:07 -0000 Subject: [llvm-commits] [llvm] r108618 - /llvm/trunk/lib/CodeGen/Splitter.cpp Message-ID: <20100717114307.B06E02A6C12C@llvm.org> Author: lhames Date: Sat Jul 17 06:43:07 2010 New Revision: 108618 URL: http://llvm.org/viewvc/llvm-project?rev=108618&view=rev Log: Removed unused inRange variable. Modified: llvm/trunk/lib/CodeGen/Splitter.cpp Modified: llvm/trunk/lib/CodeGen/Splitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Splitter.cpp?rev=108618&r1=108617&r2=108618&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/Splitter.cpp (original) +++ llvm/trunk/lib/CodeGen/Splitter.cpp Sat Jul 17 06:43:07 2010 @@ -732,8 +732,6 @@ exitEdgeItr != exitEdgeEnd; ++exitEdgeItr) { MachineLoop::Edge exitEdge = *exitEdgeItr; - LiveRange *inRange = - split.getLI().getLiveRangeContaining(lis->getMBBEndIdx(exitEdge.first).getPrevSlot()); LiveRange *outRange = split.getLI().getLiveRangeContaining(lis->getMBBStartIdx(exitEdge.second)); From xuzhongxing at gmail.com Sat Jul 17 07:12:42 2010 From: xuzhongxing at gmail.com (Zhongxing Xu) Date: Sat, 17 Jul 2010 12:12:42 -0000 Subject: [llvm-commits] [llvm] r108620 - /llvm/trunk/lib/CodeGen/CMakeLists.txt Message-ID: <20100717121242.DF7AF2A6C12C@llvm.org> Author: zhongxingxu Date: Sat Jul 17 07:12:42 2010 New Revision: 108620 URL: http://llvm.org/viewvc/llvm-project?rev=108620&view=rev Log: update CMakeLists.txt Modified: llvm/trunk/lib/CodeGen/CMakeLists.txt Modified: llvm/trunk/lib/CodeGen/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CMakeLists.txt?rev=108620&r1=108619&r2=108620&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CMakeLists.txt (original) +++ llvm/trunk/lib/CodeGen/CMakeLists.txt Sat Jul 17 07:12:42 2010 @@ -67,6 +67,7 @@ SjLjEHPrepare.cpp SlotIndexes.cpp Spiller.cpp + Splitter.cpp StackProtector.cpp StackSlotColoring.cpp StrongPHIElimination.cpp From clattner at apple.com Sat Jul 17 11:02:02 2010 From: clattner at apple.com (Chris Lattner) Date: Sat, 17 Jul 2010 09:02:02 -0700 Subject: [llvm-commits] [llvm] r108615 - in /llvm/trunk: include/llvm/Analysis/LoopInfo.h include/llvm/CodeGen/LiveIntervalAnalysis.h lib/CodeGen/Splitter.cpp lib/CodeGen/Splitter.h In-Reply-To: References: <20100717073401.79A5A2A6C12D@llvm.org> Message-ID: On Jul 17, 2010, at 12:39 AM, Lang Hames wrote: > Also not hooked up to anything yet. > > At present if you require this pass in your register allocator it'll go ahead aggressively split all your intervals, undoing half of the SimpleRegisterCoalescer's good work. I'll change this to more sane behaviour soon. Hey Lang, Wouldn't it make more sense to integrate splitting with the spilling policy? It seems that it makes the most sense to do splitting while iteratively handling spilling. If you have enough registers, there is no reason to split. -Chris From clattner at apple.com Sat Jul 17 12:18:51 2010 From: clattner at apple.com (Chris Lattner) Date: Sat, 17 Jul 2010 10:18:51 -0700 Subject: [llvm-commits] [llvm] r108568 - in /llvm/trunk: lib/CodeGen/AsmPrinter/AsmPrinter.cpp test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll test/CodeGen/PowerPC/empty-functions.ll test/CodeGen/X86/2008-01-25-EmptyFunction.ll test/CodeGen/X86/empty-functions.ll In-Reply-To: <20100716225110.9D1992A6C12C@llvm.org> References: <20100716225110.9D1992A6C12C@llvm.org> Message-ID: <09796731-B45C-48F1-9FA1-070739862B2E@apple.com> On Jul 16, 2010, at 3:51 PM, Bill Wendling wrote: > Author: void > Date: Fri Jul 16 17:51:10 2010 > New Revision: 108568 > > URL: http://llvm.org/viewvc/llvm-project?rev=108568&view=rev > Log: > Consider this function: > > void foo() { __builtin_unreachable(); } Great solution Bill! One minor tweak: > > + // If the last instruction was a prolog label, then we have a situation where > + // we emitted a prolog but no function body. This results in the ending prolog > + // label equaling the end of function label and an invalid "row" in the > + // FDE. We need to emit a noop in this situation so that the FDE's rows are > + // valid. > + bool RequiresNoop = LastMI && LastMI->getOpcode()==TargetOpcode::PROLOG_LABEL; Please use LastMI->isPrologLabel() Thanks! -Chris From clattner at apple.com Sat Jul 17 12:37:11 2010 From: clattner at apple.com (Chris Lattner) Date: Sat, 17 Jul 2010 10:37:11 -0700 Subject: [llvm-commits] [llvm] r108555 - in /llvm/trunk/lib/Target/PowerPC: PPCInstrInfo.cpp PPCInstrInfo.td In-Reply-To: References: <20100716210352.EB76E2A6C12C@llvm.org> <17710B28-F44B-4BEC-9D8F-AA690F138E17@apple.com> Message-ID: On Jul 16, 2010, at 2:35 PM, Jakob Stoklund Olesen wrote: > > On Jul 16, 2010, at 2:22 PM, Chris Lattner wrote: > >> With COPY, would it be reasonable/possible to write patterns for copy instructions in td files now? > > Do you mean like this: > > def : Pat<(f64 (fextend F4RC:$src)), (COPY F4RC:$src)> > > That might work. The code for inferring the register class of that COPY def is a bit weak ATM. Ideally, the register class could be inferred from the uses, and we could get rid of COPY_TO_REGCLASS entirely. That would also be nice, but I was thinking something more like changing: let neverHasSideEffects = 1 in { def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src), "mov{b}\t{$src, $dst|$dst, $src}", []>; def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize; def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), "mov{l}\t{$src, $dst|$dst, $src}", []>; } to: def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src), "mov{b}\t{$src, $dst|$dst, $src}", [(set GR8:$dst, (copy GR8:$src)]>; This has two benefits: neverHasSideEffects (and others) can now be inferred, and tblgen could conceptually generate the code for X86InstrInfo::copyPhysReg. For risc targets that don't have actual copy instructions, using a Pat<> pattern to map into into an "or" instruction (or whatever is the preferred idiom) should also be possible in theory. -Chris From clattner at apple.com Sat Jul 17 12:38:34 2010 From: clattner at apple.com (Chris Lattner) Date: Sat, 17 Jul 2010 10:38:34 -0700 Subject: [llvm-commits] [llvm] r108536 - in /llvm/trunk: lib/Target/X86/CMakeLists.txt lib/Target/X86/X86.h lib/Target/X86/X86CodeEmitter.cpp lib/Target/X86/X86FloatingPointRegKill.cpp lib/Target/X86/X86InstrFPStack.td lib/Target/X86/X86InstrInfo.cpp lib/Target/X86/X86TargetMachine.cpp test/CodeGen/X86/2007-06-14-branchfold.ll In-Reply-To: <20100716174144.AD5F12A6C12D@llvm.org> References: <20100716174144.AD5F12A6C12D@llvm.org> Message-ID: On Jul 16, 2010, at 10:41 AM, Jakob Stoklund Olesen wrote: > Author: stoklund > Date: Fri Jul 16 12:41:44 2010 > New Revision: 108536 > > URL: http://llvm.org/viewvc/llvm-project?rev=108536&view=rev > Log: > Remove the X86::FP_REG_KILL pseudo-instruction and the X86FloatingPointRegKill > pass that inserted it. > > It is no longer necessary to limit the live ranges of FP registers to a single > basic block. This is *really really* awesome Jakob. This was a huge long-standing code quality deficiency of LLVM vs other compilers, thanks for doing it! -Chris From clattner at apple.com Sat Jul 17 12:39:34 2010 From: clattner at apple.com (Chris Lattner) Date: Sat, 17 Jul 2010 10:39:34 -0700 Subject: [llvm-commits] [llvm] r108555 - in /llvm/trunk/lib/Target/PowerPC: PPCInstrInfo.cpp PPCInstrInfo.td In-Reply-To: References: <20100716210352.EB76E2A6C12C@llvm.org> <17710B28-F44B-4BEC-9D8F-AA690F138E17@apple.com> Message-ID: > to: > > def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src), > "mov{b}\t{$src, $dst|$dst, $src}", > [(set GR8:$dst, (copy GR8:$src)]>; > > This has two benefits: neverHasSideEffects (and others) can now be inferred, and tblgen could conceptually generate the code for X86InstrInfo::copyPhysReg. On reflection, I realized that this has nothing to do with copy. The input pattern should just be written "(set GR8:$dst, GR8:$src)", sorry for the noise. -Chris From sabre at nondot.org Sat Jul 17 12:40:52 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 17 Jul 2010 17:40:52 -0000 Subject: [llvm-commits] [llvm] r108625 - /llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp Message-ID: <20100717174052.105762A6C12C@llvm.org> Author: lattner Date: Sat Jul 17 12:40:51 2010 New Revision: 108625 URL: http://llvm.org/viewvc/llvm-project?rev=108625&view=rev Log: doxygenify some comments. Modified: llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp Modified: llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp?rev=108625&r1=108624&r2=108625&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp Sat Jul 17 12:40:51 2010 @@ -149,20 +149,20 @@ return StackTop == 0; } - // getSlot - Return the stack slot number a particular register number is - // in. + /// getSlot - Return the stack slot number a particular register number is + /// in. unsigned getSlot(unsigned RegNo) const { assert(RegNo < 8 && "Regno out of range!"); return RegMap[RegNo]; } - // isLive - Is RegNo currently live in the stack? + /// isLive - Is RegNo currently live in the stack? bool isLive(unsigned RegNo) const { unsigned Slot = getSlot(RegNo); return Slot < StackTop && Stack[Slot] == RegNo; } - // getScratchReg - Return an FP register that is not currently in use. + /// getScratchReg - Return an FP register that is not currently in use. unsigned getScratchReg() { for (int i = 7; i >= 0; --i) if (!isLive(i)) @@ -170,14 +170,14 @@ llvm_unreachable("Ran out of scratch FP registers"); } - // getStackEntry - Return the X86::FP register in register ST(i). + /// getStackEntry - Return the X86::FP register in register ST(i). unsigned getStackEntry(unsigned STi) const { assert(STi < StackTop && "Access past stack top!"); return Stack[StackTop-1-STi]; } - // getSTReg - Return the X86::ST(i) register which contains the specified - // FP register. + /// getSTReg - Return the X86::ST(i) register which contains the specified + /// FP register. unsigned getSTReg(unsigned RegNo) const { return StackTop - 1 - getSlot(RegNo) + llvm::X86::ST0; } @@ -218,27 +218,27 @@ BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg); } - // popStackAfter - Pop the current value off of the top of the FP stack - // after the specified instruction. + /// popStackAfter - Pop the current value off of the top of the FP stack + /// after the specified instruction. void popStackAfter(MachineBasicBlock::iterator &I); - // freeStackSlotAfter - Free the specified register from the register stack, - // so that it is no longer in a register. If the register is currently at - // the top of the stack, we just pop the current instruction, otherwise we - // store the current top-of-stack into the specified slot, then pop the top - // of stack. + /// freeStackSlotAfter - Free the specified register from the register + /// stack, so that it is no longer in a register. If the register is + /// currently at the top of the stack, we just pop the current instruction, + /// otherwise we store the current top-of-stack into the specified slot, + /// then pop the top of stack. void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg); - // freeStackSlotBefore - Just the pop, no folding. Return the inserted - // instruction. + /// freeStackSlotBefore - Just the pop, no folding. Return the inserted + /// instruction. MachineBasicBlock::iterator freeStackSlotBefore(MachineBasicBlock::iterator I, unsigned FPRegNo); - // Adjust the live registers to be the set in Mask. + /// Adjust the live registers to be the set in Mask. void adjustLiveRegs(unsigned Mask, MachineBasicBlock::iterator I); - // Shuffle the top FixCount stack entries susch that FP reg FixStack[0] is - //st(0), FP reg FixStack[1] is st(1) etc. + /// Shuffle the top FixCount stack entries susch that FP reg FixStack[0] is + /// st(0), FP reg FixStack[1] is st(1) etc. void shuffleStackTop(const unsigned char *FixStack, unsigned FixCount, MachineBasicBlock::iterator I); From sabre at nondot.org Sat Jul 17 12:42:04 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 17 Jul 2010 17:42:04 -0000 Subject: [llvm-commits] [llvm] r108626 - /llvm/trunk/lib/Target/X86/README-FPStack.txt Message-ID: <20100717174204.3D3C62A6C12C@llvm.org> Author: lattner Date: Sat Jul 17 12:42:04 2010 New Revision: 108626 URL: http://llvm.org/viewvc/llvm-project?rev=108626&view=rev Log: the stackifier is global! Modified: llvm/trunk/lib/Target/X86/README-FPStack.txt Modified: llvm/trunk/lib/Target/X86/README-FPStack.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/README-FPStack.txt?rev=108626&r1=108625&r2=108626&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/README-FPStack.txt (original) +++ llvm/trunk/lib/Target/X86/README-FPStack.txt Sat Jul 17 12:42:04 2010 @@ -27,8 +27,8 @@ //===---------------------------------------------------------------------===// -The FP stackifier needs to be global. Also, it should handle simple permutates -to reduce number of shuffle instructions, e.g. turning: +The FP stackifier should handle simple permutates to reduce number of shuffle +instructions, e.g. turning: fld P -> fld Q fld Q fld P From benny.kra at googlemail.com Sat Jul 17 13:33:01 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Sat, 17 Jul 2010 20:33:01 +0200 Subject: [llvm-commits] [llvm] r107678 - in /llvm/trunk: lib/Target/X86/AsmPrinter/X86MCInstLower.cpp test/CodeGen/X86/2010-07-06-DbgCrash.ll In-Reply-To: <0CA13FB8-22D9-43AE-86A0-ECA778FAB91D@apple.com> References: <20100706181832.4A4402A6C12C@llvm.org> <0CA13FB8-22D9-43AE-86A0-ECA778FAB91D@apple.com> Message-ID: On 16.07.2010, at 22:16, Devang Patel wrote: > Valgrind on my mac is not reporting this error. Is it possible for any one with linux box to shed a little light here ? It only shows up on x86, probably due to register allocation differences. Here's a line to reproduce in darwin: valgrind llc -march=x86 -O0 -relocation-model pic < test/CodeGen/X86/2010-07-06-DbgCrash.ll -o /dev/null From stoklund at 2pi.dk Sat Jul 17 13:48:49 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Sat, 17 Jul 2010 11:48:49 -0700 Subject: [llvm-commits] [llvm] r108536 - in /llvm/trunk: lib/Target/X86/CMakeLists.txt lib/Target/X86/X86.h lib/Target/X86/X86CodeEmitter.cpp lib/Target/X86/X86FloatingPointRegKill.cpp lib/Target/X86/X86InstrFPStack.td lib/Target/X86/X86InstrInfo.cpp lib/Target/X86/X86TargetMachine.cpp test/CodeGen/X86/2007-06-14-branchfold.ll In-Reply-To: References: <20100716174144.AD5F12A6C12D@llvm.org> Message-ID: <05115E25-2943-49B1-8DC4-F6DA0F523BE2@2pi.dk> On Jul 17, 2010, at 10:38 AM, Chris Lattner wrote: > > On Jul 16, 2010, at 10:41 AM, Jakob Stoklund Olesen wrote: > >> Author: stoklund >> Date: Fri Jul 16 12:41:44 2010 >> New Revision: 108536 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=108536&view=rev >> Log: >> Remove the X86::FP_REG_KILL pseudo-instruction and the X86FloatingPointRegKill >> pass that inserted it. >> >> It is no longer necessary to limit the live ranges of FP registers to a single >> basic block. > > This is *really really* awesome Jakob. This was a huge long-standing code quality deficiency of LLVM vs other compilers, thanks for doing it! No problem, we really needed to lose the arbitrary constraints on FP registers for LICM and live range splitting. I ran the nightly test suite with -arch i386 -mfpmath=387 -mcpu=pentium, and the global stackifier as llcbeta. These are the double-digit improvements: Program | LLC LLC-BETA LLC/LLC-BETA SingleSource/Benchmarks/Misc-C++/stepanov_v1p2 | 25.5900 7.6800 3.33 SingleSource/Benchmarks/Misc-C++/oopack_v1p8 | 0.3800 0.1400 2.71 SingleSource/Benchmarks/Adobe-C++/stepanov_abstraction | 12.0300 5.1200 2.35 SingleSource/Benchmarks/Misc/fp-convert | 5.6900 2.8400 2.00 SingleSource/Benchmarks/Adobe-C++/stepanov_vector | 6.0600 3.1800 1.91 SingleSource/Benchmarks/Misc-C++/mandel-text | 3.2800 1.7300 1.90 SingleSource/Benchmarks/Misc/mandel-2 | 1.5500 0.8700 1.78 SingleSource/Benchmarks/Adobe-C++/simple_types_constant_folding | 2.9700 1.6800 1.77 MultiSource/Benchmarks/FreeBench/neural/neural | 0.3000 0.1700 1.76 MultiSource/Benchmarks/McCat/04-bisect/bisect | 0.1600 0.1300 1.23 SingleSource/Benchmarks/Misc/flops-3 | 2.9100 2.4400 1.19 MultiSource/Benchmarks/ASC_Sequoia/CrystalMk/CrystalMk | 10.4000 8.7200 1.19 SingleSource/Benchmarks/CoyoteBench/almabench | 11.5000 9.7800 1.18 External/SPEC/CFP2006/447.dealII/447.dealII | 22.5700 19.1700 1.18 SingleSource/Benchmarks/Misc/whetstone | 1.5500 1.3400 1.16 SingleSource/Benchmarks/Misc/perlin | 7.8100 6.7200 1.16 MultiSource/Benchmarks/ASC_Sequoia/AMGmk/AMGmk | 16.5200 14.3000 1.16 SingleSource/Benchmarks/Shootout-C++/moments | 0.1600 0.1400 1.14 SingleSource/Benchmarks/Misc/flops-4 | 1.3800 1.2100 1.14 SingleSource/Benchmarks/Misc-C++/Large/ray | 4.7500 4.1900 1.13 MultiSource/Benchmarks/MiBench/consumer-lame/consumer-lame | 0.3500 0.3100 1.13 SingleSource/Benchmarks/Misc/flops-8 | 2.4500 2.2300 1.10 SingleSource/Benchmarks/Misc/flops-2 | 2.1000 1.9200 1.09 SingleSource/Benchmarks/Dhrystone/fldry | 1.4600 1.3400 1.09 SingleSource/Benchmarks/Adobe-C++/simple_types_loop_invariant | 4.6600 4.2700 1.09 SingleSource/Benchmarks/Adobe-C++/functionobjects | 4.5100 4.1200 1.09 External/SPEC/CFP2000/179.art/179.art | 2.2000 2.0100 1.09 And the worst regressions: MultiSource/Benchmarks/FreeBench/fourinarow/fourinarow | 0.8800 0.8900 0.99 SingleSource/Benchmarks/Shootout-C++/ary3 | 2.0100 2.0500 0.98 SingleSource/Benchmarks/CoyoteBench/huffbench | 20.4700 20.8700 0.98 MultiSource/Applications/sqlite3/sqlite3 | 5.3400 5.4300 0.98 MultiSource/Applications/siod/siod | 3.5400 3.6200 0.98 SingleSource/Benchmarks/Shootout-C++/methcall | 5.6600 5.8300 0.97 MultiSource/Benchmarks/Olden/bh/bh | 1.7000 1.7500 0.97 External/SPEC/CINT2006/400.perlbench/400.perlbench | 7.2000 7.4300 0.97 SingleSource/Benchmarks/Shootout/strcat | 0.2400 0.2500 0.96 SingleSource/Benchmarks/Dhrystone/dry | 0.3500 0.3700 0.95 SPEC floating point: External/SPEC/CFP2000/177.mesa/177.mesa | 3.2900 3.2300 1.02 External/SPEC/CFP2000/179.art/179.art | 2.2000 2.0100 1.09 External/SPEC/CFP2000/183.equake/183.equake | 7.7700 7.6900 1.01 External/SPEC/CFP2000/188.ammp/188.ammp | 16.3700 15.9300 1.03 External/SPEC/CFP2006/433.milc/433.milc | 8.3900 8.3400 1.01 External/SPEC/CFP2006/444.namd/444.namd | 18.6700 17.5100 1.07 External/SPEC/CFP2006/447.dealII/447.dealII | 22.5700 19.1700 1.18 External/SPEC/CFP2006/470.lbm/470.lbm | 3.4700 3.4100 1.02 -------------- next part -------------- A non-text attachment was scrubbed... Name: smime.p7s Type: application/pkcs7-signature Size: 1929 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100717/2cb289c8/attachment.bin From isanbard at gmail.com Sat Jul 17 14:18:44 2010 From: isanbard at gmail.com (Bill Wendling) Date: Sat, 17 Jul 2010 19:18:44 -0000 Subject: [llvm-commits] [llvm] r108628 - /llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Message-ID: <20100717191844.AF3082A6C12C@llvm.org> Author: void Date: Sat Jul 17 14:18:44 2010 New Revision: 108628 URL: http://llvm.org/viewvc/llvm-project?rev=108628&view=rev Log: Use isPrologLabel() instead of checking the opcode directly. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=108628&r1=108627&r2=108628&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Sat Jul 17 14:18:44 2010 @@ -661,7 +661,7 @@ // label equaling the end of function label and an invalid "row" in the // FDE. We need to emit a noop in this situation so that the FDE's rows are // valid. - bool RequiresNoop = LastMI && LastMI->getOpcode()==TargetOpcode::PROLOG_LABEL; + bool RequiresNoop = LastMI && LastMI->isPrologLabel(); // If the function is empty and the object file uses .subsections_via_symbols, // then we need to emit *something* to the function body to prevent the From clattner at apple.com Sat Jul 17 14:32:45 2010 From: clattner at apple.com (Chris Lattner) Date: Sat, 17 Jul 2010 12:32:45 -0700 Subject: [llvm-commits] [llvm] r108536 - in /llvm/trunk: lib/Target/X86/CMakeLists.txt lib/Target/X86/X86.h lib/Target/X86/X86CodeEmitter.cpp lib/Target/X86/X86FloatingPointRegKill.cpp lib/Target/X86/X86InstrFPStack.td lib/Target/X86/X86InstrInfo.cpp lib/Target/X86/X86TargetMachine.cpp test/CodeGen/X86/2007-06-14-branchfold.ll In-Reply-To: <05115E25-2943-49B1-8DC4-F6DA0F523BE2@2pi.dk> References: <20100716174144.AD5F12A6C12D@llvm.org> <05115E25-2943-49B1-8DC4-F6DA0F523BE2@2pi.dk> Message-ID: On Jul 17, 2010, at 11:48 AM, Jakob Stoklund Olesen wrote: > > On Jul 17, 2010, at 10:38 AM, Chris Lattner wrote: > >> >> On Jul 16, 2010, at 10:41 AM, Jakob Stoklund Olesen wrote: >> >>> Author: stoklund >>> Date: Fri Jul 16 12:41:44 2010 >>> New Revision: 108536 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=108536&view=rev >>> Log: >>> Remove the X86::FP_REG_KILL pseudo-instruction and the X86FloatingPointRegKill >>> pass that inserted it. >>> >>> It is no longer necessary to limit the live ranges of FP registers to a single >>> basic block. >> >> This is *really really* awesome Jakob. This was a huge long-standing code quality deficiency of LLVM vs other compilers, thanks for doing it! > > No problem, we really needed to lose the arbitrary constraints on FP registers for LICM and live range splitting. > > I ran the nightly test suite with -arch i386 -mfpmath=387 -mcpu=pentium, and the global stackifier as llcbeta. These are the double-digit improvements: Wow, great results. Users of long double will be very happy also :) -Chris From baldrick at free.fr Sat Jul 17 15:23:38 2010 From: baldrick at free.fr (Duncan Sands) Date: Sat, 17 Jul 2010 20:23:38 -0000 Subject: [llvm-commits] [llvm] r108629 - /llvm/trunk/tools/llvmc/example/mcc16/plugins/PIC16Base/PluginMain.cpp Message-ID: <20100717202338.230602A6C12C@llvm.org> Author: baldrick Date: Sat Jul 17 15:23:37 2010 New Revision: 108629 URL: http://llvm.org/viewvc/llvm-project?rev=108629&view=rev Log: Fix what seems like a clear buffer overflow, noticed by cppcheck. Modified: llvm/trunk/tools/llvmc/example/mcc16/plugins/PIC16Base/PluginMain.cpp Modified: llvm/trunk/tools/llvmc/example/mcc16/plugins/PIC16Base/PluginMain.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/example/mcc16/plugins/PIC16Base/PluginMain.cpp?rev=108629&r1=108628&r2=108629&view=diff ============================================================================== --- llvm/trunk/tools/llvmc/example/mcc16/plugins/PIC16Base/PluginMain.cpp (original) +++ llvm/trunk/tools/llvmc/example/mcc16/plugins/PIC16Base/PluginMain.cpp Sat Jul 17 15:23:37 2010 @@ -35,7 +35,7 @@ } std::string LowerCase; - for (unsigned i = 0; i <= Partname.size(); i++) { + for (unsigned i = 0; i < Partname.size(); i++) { LowerCase.push_back(std::tolower(Partname[i])); } @@ -52,7 +52,7 @@ } std::string UpperCase; - for (unsigned i = 0; i <= Partname.size(); i++) { + for (unsigned i = 0; i < Partname.size(); i++) { UpperCase.push_back(std::toupper(Partname[i])); } From ggreif at gmail.com Sat Jul 17 15:52:46 2010 From: ggreif at gmail.com (Gabor Greif) Date: Sat, 17 Jul 2010 20:52:46 -0000 Subject: [llvm-commits] [llvm] r108631 - /llvm/trunk/lib/VMCore/Use.cpp Message-ID: <20100717205246.898A12A6C12C@llvm.org> Author: ggreif Date: Sat Jul 17 15:52:46 2010 New Revision: 108631 URL: http://llvm.org/viewvc/llvm-project?rev=108631&view=rev Log: fullStopTag cannot happen here, it is handled above Modified: llvm/trunk/lib/VMCore/Use.cpp Modified: llvm/trunk/lib/VMCore/Use.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Use.cpp?rev=108631&r1=108630&r2=108631&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Use.cpp (original) +++ llvm/trunk/lib/VMCore/Use.cpp Sat Jul 17 15:52:46 2010 @@ -100,9 +100,7 @@ --Stop; Stop->Val = 0; if (!Count) { - Stop->Prev.setFromOpaqueValue(reinterpret_cast(Done == 0 - ? fullStopTag - : stopTag)); + Stop->Prev.setFromOpaqueValue(reinterpret_cast(stopTag)); ++Done; Count = Done; } else { From espindola at google.com Sat Jul 17 16:06:11 2010 From: espindola at google.com (Rafael Espindola) Date: Sat, 17 Jul 2010 17:06:11 -0400 Subject: [llvm-commits] [llvm] r108567 - in /llvm/trunk: docs/ include/llvm/Target/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CellSPU/ lib/Target/MBlaze/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PIC16/ lib/Target/PowerPC/ lib Message-ID: Thanks! On Jul 16, 2010 6:38 PM, "Jakob Stoklund Olesen" wrote: > Author: stoklund > Date: Fri Jul 16 17:35:46 2010 > New Revision: 108567 > > URL: http://llvm.org/viewvc/llvm-project?rev=108567&view=rev > Log: > Remove the isMoveInstr() hook. > > Modified: > llvm/trunk/docs/WritingAnLLVMBackend.html > llvm/trunk/include/llvm/Target/TargetInstrInfo.h > llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp > llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h > llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp > llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h > llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp > llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.h > llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp > llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h > llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp > llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h > llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp > llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h > llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp > llvm/trunk/lib/Target/Mips/MipsInstrInfo.h > llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp > llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.h > llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp > llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h > llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp > llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h > llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp > llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h > llvm/trunk/lib/Target/X86/X86InstrInfo.cpp > llvm/trunk/lib/Target/X86/X86InstrInfo.h > llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp > llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h > > Modified: llvm/trunk/docs/WritingAnLLVMBackend.html > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/WritingAnLLVMBackend.html?rev=108567&r1=108566&r2=108567&view=diff > ============================================================================== > --- llvm/trunk/docs/WritingAnLLVMBackend.html (original) > +++ llvm/trunk/docs/WritingAnLLVMBackend.html Fri Jul 16 17:35:46 2010 > @@ -1299,9 +1299,6 @@ >

    > >
      > -
    • isMoveInstr — Return true if the instruction is a register to > - register move; false, otherwise.
      • > - >
    • isLoadFromStackSlot — If the specified machine instruction is > a direct load from a stack slot, return the register number of the > destination and the FrameIndex of the stack slot.
      • > > Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original) > +++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Fri Jul 16 17:35:46 2010 > @@ -92,15 +92,6 @@ > AliasAnalysis *AA) const; > > public: > - /// isMoveInstr - Return true if the instruction is a register to register > - /// move and return the source and dest operands and their sub-register > - /// indices by reference. > - virtual bool isMoveInstr(const MachineInstr& MI, > - unsigned& SrcReg, unsigned& DstReg, > - unsigned& SrcSubIdx, unsigned& DstSubIdx) const { > - return false; > - } > - > /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" > /// extension instruction. That is, it's like a copy where it's legal for the > /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns > > Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Fri Jul 16 17:35:46 2010 > @@ -573,48 +573,6 @@ > return 0; // Not reached > } > > -/// Return true if the instruction is a register to register move and > -/// leave the source and dest operands in the passed parameters. > -/// > -bool > -ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI, > - unsigned &SrcReg, unsigned &DstReg, > - unsigned& SrcSubIdx, unsigned& DstSubIdx) const { > - switch (MI.getOpcode()) { > - default: break; > - case ARM::VMOVS: > - case ARM::VMOVD: > - case ARM::VMOVDneon: > - case ARM::VMOVQ: > - case ARM::VMOVQQ : { > - SrcReg = MI.getOperand(1).getReg(); > - DstReg = MI.getOperand(0).getReg(); > - SrcSubIdx = MI.getOperand(1).getSubReg(); > - DstSubIdx = MI.getOperand(0).getSubReg(); > - return true; > - } > - case ARM::MOVr: > - case ARM::MOVr_TC: > - case ARM::tMOVr: > - case ARM::tMOVgpr2tgpr: > - case ARM::tMOVtgpr2gpr: > - case ARM::tMOVgpr2gpr: > - case ARM::t2MOVr: { > - assert(MI.getDesc().getNumOperands() >= 2 && > - MI.getOperand(0).isReg() && > - MI.getOperand(1).isReg() && > - "Invalid ARM MOV instruction"); > - SrcReg = MI.getOperand(1).getReg(); > - DstReg = MI.getOperand(0).getReg(); > - SrcSubIdx = MI.getOperand(1).getSubReg(); > - DstSubIdx = MI.getOperand(0).getSubReg(); > - return true; > - } > - } > - > - return false; > -} > - > unsigned > ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, > int &FrameIndex) const { > > Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h (original) > +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Fri Jul 16 17:35:46 2010 > @@ -262,12 +262,6 @@ > /// > virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const; > > - /// Return true if the instruction is a register to register move and return > - /// the source and dest operands and their sub-register indices by reference. > - virtual bool isMoveInstr(const MachineInstr &MI, > - unsigned &SrcReg, unsigned &DstReg, > - unsigned &SrcSubIdx, unsigned &DstSubIdx) const; > - > virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, > int &FrameIndex) const; > virtual unsigned isStoreToStackSlot(const MachineInstr *MI, > > Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp (original) > +++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp Fri Jul 16 17:35:46 2010 > @@ -27,32 +27,6 @@ > RI(*this) { } > > > -bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI, > - unsigned& sourceReg, unsigned& destReg, > - unsigned& SrcSR, unsigned& DstSR) const { > - unsigned oc = MI.getOpcode(); > - if (oc == Alpha::BISr || > - oc == Alpha::CPYSS || > - oc == Alpha::CPYST || > - oc == Alpha::CPYSSt || > - oc == Alpha::CPYSTs) { > - // or r1, r2, r2 > - // cpys(s|t) r1 r2 r2 > - assert(MI.getNumOperands() >= 3 && > - MI.getOperand(0).isReg() && > - MI.getOperand(1).isReg() && > - MI.getOperand(2).isReg() && > - "invalid Alpha BIS instruction!"); > - if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) { > - sourceReg = MI.getOperand(1).getReg(); > - destReg = MI.getOperand(0).getReg(); > - SrcSR = DstSR = 0; > - return true; > - } > - } > - return false; > -} > - > unsigned > AlphaInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, > int &FrameIndex) const { > > Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h (original) > +++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h Fri Jul 16 17:35:46 2010 > @@ -30,12 +30,6 @@ > /// > virtual const AlphaRegisterInfo &getRegisterInfo() const { return RI; } > > - /// Return true if the instruction is a register to register move and return > - /// the source and dest operands and their sub-register indices by reference. > - virtual bool isMoveInstr(const MachineInstr &MI, > - unsigned &SrcReg, unsigned &DstReg, > - unsigned &SrcSubIdx, unsigned &DstSubIdx) const; > - > virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, > int &FrameIndex) const; > virtual unsigned isStoreToStackSlot(const MachineInstr *MI, > > Modified: llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp (original) > +++ llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp Fri Jul 16 17:35:46 2010 > @@ -28,34 +28,6 @@ > RI(ST, *this), > Subtarget(ST) {} > > -/// Return true if the instruction is a register to register move and > -/// leave the source and dest operands in the passed parameters. > -bool BlackfinInstrInfo::isMoveInstr(const MachineInstr &MI, > - unsigned &SrcReg, > - unsigned &DstReg, > - unsigned &SrcSR, > - unsigned &DstSR) const { > - SrcSR = DstSR = 0; // No sub-registers. > - switch (MI.getOpcode()) { > - case BF::MOVE: > - case BF::MOVE_ncccc: > - case BF::MOVE_ccncc: > - case BF::MOVECC_zext: > - case BF::MOVECC_nz: > - DstReg = MI.getOperand(0).getReg(); > - SrcReg = MI.getOperand(1).getReg(); > - return true; > - case BF::SLL16i: > - if (MI.getOperand(2).getImm()!=0) > - return false; > - DstReg = MI.getOperand(0).getReg(); > - SrcReg = MI.getOperand(1).getReg(); > - return true; > - default: > - return false; > - } > -} > - > /// isLoadFromStackSlot - If the specified machine instruction is a direct > /// load from a stack slot, return the virtual or physical register number of > /// the destination along with the FrameIndex of the loaded stack slot. If > > Modified: llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.h (original) > +++ llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.h Fri Jul 16 17:35:46 2010 > @@ -30,10 +30,6 @@ > /// always be able to get register info as well (through this method). > virtual const BlackfinRegisterInfo &getRegisterInfo() const { return RI; } > > - virtual bool isMoveInstr(const MachineInstr &MI, > - unsigned &SrcReg, unsigned &DstReg, > - unsigned &SrcSubIdx, unsigned &DstSubIdx) const; > - > virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, > int &FrameIndex) const; > > > Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp (original) > +++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp Fri Jul 16 17:35:46 2010 > @@ -54,148 +54,6 @@ > RI(*TM.getSubtargetImpl(), *this) > { /* NOP */ } > > -bool > -SPUInstrInfo::isMoveInstr(const MachineInstr& MI, > - unsigned& sourceReg, > - unsigned& destReg, > - unsigned& SrcSR, unsigned& DstSR) const { > - SrcSR = DstSR = 0; // No sub-registers. > - > - switch (MI.getOpcode()) { > - default: > - break; > - case SPU::ORIv4i32: > - case SPU::ORIr32: > - case SPU::ORHIv8i16: > - case SPU::ORHIr16: > - case SPU::ORHIi8i16: > - case SPU::ORBIv16i8: > - case SPU::ORBIr8: > - case SPU::ORIi16i32: > - case SPU::ORIi8i32: > - case SPU::AHIvec: > - case SPU::AHIr16: > - case SPU::AIv4i32: > - assert(MI.getNumOperands() == 3 && > - MI.getOperand(0).isReg() && > - MI.getOperand(1).isReg() && > - MI.getOperand(2).isImm() && > - "invalid SPU ORI/ORHI/ORBI/AHI/AI/SFI/SFHI instruction!"); > - if (MI.getOperand(2).getImm() == 0) { > - sourceReg = MI.getOperand(1).getReg(); > - destReg = MI.getOperand(0).getReg(); > - return true; > - } > - break; > - case SPU::AIr32: > - assert(MI.getNumOperands() == 3 && > - "wrong number of operands to AIr32"); > - if (MI.getOperand(0).isReg() && > - MI.getOperand(1).isReg() && > - (MI.getOperand(2).isImm() && > - MI.getOperand(2).getImm() == 0)) { > - sourceReg = MI.getOperand(1).getReg(); > - destReg = MI.getOperand(0).getReg(); > - return true; > - } > - break; > - case SPU::LRr8: > - case SPU::LRr16: > - case SPU::LRr32: > - case SPU::LRf32: > - case SPU::LRr64: > - case SPU::LRf64: > - case SPU::LRr128: > - case SPU::LRv16i8: > - case SPU::LRv8i16: > - case SPU::LRv4i32: > - case SPU::LRv4f32: > - case SPU::LRv2i64: > - case SPU::LRv2f64: > - case SPU::ORv16i8_i8: > - case SPU::ORv8i16_i16: > - case SPU::ORv4i32_i32: > - case SPU::ORv2i64_i64: > - case SPU::ORv4f32_f32: > - case SPU::ORv2f64_f64: > - case SPU::ORi8_v16i8: > - case SPU::ORi16_v8i16: > - case SPU::ORi32_v4i32: > - case SPU::ORi64_v2i64: > - case SPU::ORf32_v4f32: > - case SPU::ORf64_v2f64: > -/* > - case SPU::ORi128_r64: > - case SPU::ORi128_f64: > - case SPU::ORi128_r32: > - case SPU::ORi128_f32: > - case SPU::ORi128_r16: > - case SPU::ORi128_r8: > -*/ > - case SPU::ORi128_vec: > -/* > - case SPU::ORr64_i128: > - case SPU::ORf64_i128: > - case SPU::ORr32_i128: > - case SPU::ORf32_i128: > - case SPU::ORr16_i128: > - case SPU::ORr8_i128: > -*/ > - case SPU::ORvec_i128: > -/* > - case SPU::ORr16_r32: > - case SPU::ORr8_r32: > - case SPU::ORf32_r32: > - case SPU::ORr32_f32: > - case SPU::ORr32_r16: > - case SPU::ORr32_r8: > - case SPU::ORr16_r64: > - case SPU::ORr8_r64: > - case SPU::ORr64_r16: > - case SPU::ORr64_r8: > -*/ > - case SPU::ORr64_r32: > - case SPU::ORr32_r64: > - case SPU::ORf32_r32: > - case SPU::ORr32_f32: > - case SPU::ORf64_r64: > - case SPU::ORr64_f64: { > - assert(MI.getNumOperands() == 2 && > - MI.getOperand(0).isReg() && > - MI.getOperand(1).isReg() && > - "invalid SPU OR_ or LR instruction!"); > - sourceReg = MI.getOperand(1).getReg(); > - destReg = MI.getOperand(0).getReg(); > - return true; > - break; > - } > - case SPU::ORv16i8: > - case SPU::ORv8i16: > - case SPU::ORv4i32: > - case SPU::ORv2i64: > - case SPU::ORr8: > - case SPU::ORr16: > - case SPU::ORr32: > - case SPU::ORr64: > - case SPU::ORr128: > - case SPU::ORf32: > - case SPU::ORf64: > - assert(MI.getNumOperands() == 3 && > - MI.getOperand(0).isReg() && > - MI.getOperand(1).isReg() && > - MI.getOperand(2).isReg() && > - "invalid SPU OR(vec|r32|r64|gprc) instruction!"); > - if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) { > - sourceReg = MI.getOperand(1).getReg(); > - destReg = MI.getOperand(0).getReg(); > - return true; > - } > - break; > - } > - > - return false; > -} > - > unsigned > SPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, > int &FrameIndex) const { > > Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h (original) > +++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h Fri Jul 16 17:35:46 2010 > @@ -32,12 +32,6 @@ > /// > virtual const SPURegisterInfo &getRegisterInfo() const { return RI; } > > - /// Return true if the instruction is a register to register move and return > - /// the source and dest operands and their sub-register indices by reference. > - virtual bool isMoveInstr(const MachineInstr &MI, > - unsigned &SrcReg, unsigned &DstReg, > - unsigned &SrcSubIdx, unsigned &DstSubIdx) const; > - > unsigned isLoadFromStackSlot(const MachineInstr *MI, > int &FrameIndex) const; > unsigned isStoreToStackSlot(const MachineInstr *MI, > > Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp (original) > +++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp Fri Jul 16 17:35:46 2010 > @@ -30,41 +30,6 @@ > return op.isImm() && op.getImm() == 0; > } > > -/// Return true if the instruction is a register to register move and > -/// leave the source and dest operands in the passed parameters. > -bool MBlazeInstrInfo:: > -isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, > - unsigned &SrcSubIdx, unsigned &DstSubIdx) const { > - SrcSubIdx = DstSubIdx = 0; // No sub-registers. > - > - // add $dst, $src, $zero || addu $dst, $zero, $src > - // or $dst, $src, $zero || or $dst, $zero, $src > - if ((MI.getOpcode() == MBlaze::ADD) || (MI.getOpcode() == MBlaze::OR)) { > - if (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == MBlaze::R0) { > - DstReg = MI.getOperand(0).getReg(); > - SrcReg = MI.getOperand(2).getReg(); > - return true; > - } else if (MI.getOperand(2).isReg() && > - MI.getOperand(2).getReg() == MBlaze::R0) { > - DstReg = MI.getOperand(0).getReg(); > - SrcReg = MI.getOperand(1).getReg(); > - return true; > - } > - } > - > - // addi $dst, $src, 0 > - // ori $dst, $src, 0 > - if ((MI.getOpcode() == MBlaze::ADDI) || (MI.getOpcode() == MBlaze::ORI)) { > - if ((MI.getOperand(1).isReg()) && (isZeroImm(MI.getOperand(2)))) { > - DstReg = MI.getOperand(0).getReg(); > - SrcReg = MI.getOperand(1).getReg(); > - return true; > - } > - } > - > - return false; > -} > - > /// isLoadFromStackSlot - If the specified machine instruction is a direct > /// load from a stack slot, return the virtual or physical register number of > /// the destination along with the FrameIndex of the loaded stack slot. If > > Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h (original) > +++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h Fri Jul 16 17:35:46 2010 > @@ -173,12 +173,6 @@ > /// > virtual const MBlazeRegisterInfo &getRegisterInfo() const { return RI; } > > - /// Return true if the instruction is a register to register move and return > - /// the source and dest operands and their sub-register indices by reference. > - virtual bool isMoveInstr(const MachineInstr &MI, > - unsigned &SrcReg, unsigned &DstReg, > - unsigned &SrcSubIdx, unsigned &DstSubIdx) const; > - > /// isLoadFromStackSlot - If the specified machine instruction is a direct > /// load from a stack slot, return the virtual or physical register number of > /// the destination along with the FrameIndex of the loaded stack slot. If > > Modified: llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp (original) > +++ llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp Fri Jul 16 17:35:46 2010 > @@ -100,27 +100,6 @@ > } > > bool > -MSP430InstrInfo::isMoveInstr(const MachineInstr& MI, > - unsigned &SrcReg, unsigned &DstReg, > - unsigned &SrcSubIdx, unsigned &DstSubIdx) const { > - SrcSubIdx = DstSubIdx = 0; // No sub-registers yet. > - > - switch (MI.getOpcode()) { > - default: > - return false; > - case MSP430::MOV8rr: > - case MSP430::MOV16rr: > - assert(MI.getNumOperands() >= 2 && > - MI.getOperand(0).isReg() && > - MI.getOperand(1).isReg() && > - "invalid register-register move instruction"); > - SrcReg = MI.getOperand(1).getReg(); > - DstReg = MI.getOperand(0).getReg(); > - return true; > - } > -} > - > -bool > MSP430InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, > MachineBasicBlock::iterator MI, > const std::vector &CSI, > > Modified: llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h (original) > +++ llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h Fri Jul 16 17:35:46 2010 > @@ -54,10 +54,6 @@ > unsigned DestReg, unsigned SrcReg, > bool KillSrc) const; > > - bool isMoveInstr(const MachineInstr& MI, > - unsigned &SrcReg, unsigned &DstReg, > - unsigned &SrcSubIdx, unsigned &DstSubIdx) const; > - > virtual void storeRegToStackSlot(MachineBasicBlock &MBB, > MachineBasicBlock::iterator MI, > unsigned SrcReg, bool isKill, > > Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original) > +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Fri Jul 16 17:35:46 2010 > @@ -30,53 +30,6 @@ > return op.isImm() && op.getImm() == 0; > } > > -/// Return true if the instruction is a register to register move and > -/// leave the source and dest operands in the passed parameters. > -bool MipsInstrInfo:: > -isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, > - unsigned &SrcSubIdx, unsigned &DstSubIdx) const > -{ > - SrcSubIdx = DstSubIdx = 0; // No sub-registers. > - > - // addu $dst, $src, $zero || addu $dst, $zero, $src > - // or $dst, $src, $zero || or $dst, $zero, $src > - if ((MI.getOpcode() == Mips::ADDu) || (MI.getOpcode() == Mips::OR)) { > - if (MI.getOperand(1).getReg() == Mips::ZERO) { > - DstReg = MI.getOperand(0).getReg(); > - SrcReg = MI.getOperand(2).getReg(); > - return true; > - } else if (MI.getOperand(2).getReg() == Mips::ZERO) { > - DstReg = MI.getOperand(0).getReg(); > - SrcReg = MI.getOperand(1).getReg(); > - return true; > - } > - } > - > - // mov $fpDst, $fpSrc > - // mfc $gpDst, $fpSrc > - // mtc $fpDst, $gpSrc > - if (MI.getOpcode() == Mips::FMOV_S32 || > - MI.getOpcode() == Mips::FMOV_D32 || > - MI.getOpcode() == Mips::MFC1 || > - MI.getOpcode() == Mips::MTC1 || > - MI.getOpcode() == Mips::MOVCCRToCCR) { > - DstReg = MI.getOperand(0).getReg(); > - SrcReg = MI.getOperand(1).getReg(); > - return true; > - } > - > - // addiu $dst, $src, 0 > - if (MI.getOpcode() == Mips::ADDiu) { > - if ((MI.getOperand(1).isReg()) && (isZeroImm(MI.getOperand(2)))) { > - DstReg = MI.getOperand(0).getReg(); > - SrcReg = MI.getOperand(1).getReg(); > - return true; > - } > - } > - > - return false; > -} > - > /// isLoadFromStackSlot - If the specified machine instruction is a direct > /// load from a stack slot, return the virtual or physical register number of > /// the destination along with the FrameIndex of the loaded stack slot. If > > Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.h (original) > +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.h Fri Jul 16 17:35:46 2010 > @@ -174,12 +174,6 @@ > /// > virtual const MipsRegisterInfo &getRegisterInfo() const { return RI; } > > - /// Return true if the instruction is a register to register move and return > - /// the source and dest operands and their sub-register indices by reference. > - virtual bool isMoveInstr(const MachineInstr &MI, > - unsigned &SrcReg, unsigned &DstReg, > - unsigned &SrcSubIdx, unsigned &DstSubIdx) const; > - > /// isLoadFromStackSlot - If the specified machine instruction is a direct > /// load from a stack slot, return the virtual or physical register number of > /// the destination along with the FrameIndex of the loaded stack slot. If > > Modified: llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp (original) > +++ llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.cpp Fri Jul 16 17:35:46 2010 > @@ -167,21 +167,6 @@ > .addReg(SrcReg, getKillRegState(KillSrc)); > } > > -bool PIC16InstrInfo::isMoveInstr(const MachineInstr &MI, > - unsigned &SrcReg, unsigned &DestReg, > - unsigned &SrcSubIdx, unsigned &DstSubIdx) const { > - SrcSubIdx = DstSubIdx = 0; // No sub-registers. > - > - if (MI.getOpcode() == PIC16::copy_fsr > - || MI.getOpcode() == PIC16::copy_w) { > - DestReg = MI.getOperand(0).getReg(); > - SrcReg = MI.getOperand(1).getReg(); > - return true; > - } > - > - return false; > -} > - > /// InsertBranch - Insert a branch into the end of the specified > /// MachineBasicBlock. This operands to this method are the same as those > /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch > > Modified: llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.h (original) > +++ llvm/trunk/lib/Target/PIC16/PIC16InstrInfo.h Fri Jul 16 17:35:46 2010 > @@ -61,10 +61,6 @@ > MachineBasicBlock::iterator I, DebugLoc DL, > unsigned DestReg, unsigned SrcReg, > bool KillSrc) const; > - virtual bool isMoveInstr(const MachineInstr &MI, > - unsigned &SrcReg, unsigned &DstReg, > - unsigned &SrcSubIdx, unsigned &DstSubIdx) const; > - > virtual > unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, > MachineBasicBlock *FBB, > > Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original) > +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Fri Jul 16 17:35:46 2010 > @@ -39,67 +39,6 @@ > : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm), > RI(*TM.getSubtargetImpl(), *this) {} > > -bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI, > - unsigned& sourceReg, > - unsigned& destReg, > - unsigned& sourceSubIdx, > - unsigned& destSubIdx) const { > - sourceSubIdx = destSubIdx = 0; // No sub-registers. > - > - unsigned oc = MI.getOpcode(); > - if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR || > - oc == PPC::OR4To8 || oc == PPC::OR8To4) { // or r1, r2, r2 > - assert(MI.getNumOperands() >= 3 && > - MI.getOperand(0).isReg() && > - MI.getOperand(1).isReg() && > - MI.getOperand(2).isReg() && > - "invalid PPC OR instruction!"); > - if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) { > - sourceReg = MI.getOperand(1).getReg(); > - destReg = MI.getOperand(0).getReg(); > - return true; > - } > - } else if (oc == PPC::ADDI) { // addi r1, r2, 0 > - assert(MI.getNumOperands() >= 3 && > - MI.getOperand(0).isReg() && > - MI.getOperand(2).isImm() && > - "invalid PPC ADDI instruction!"); > - if (MI.getOperand(1).isReg() && MI.getOperand(2).getImm() == 0) { > - sourceReg = MI.getOperand(1).getReg(); > - destReg = MI.getOperand(0).getReg(); > - return true; > - } > - } else if (oc == PPC::ORI) { // ori r1, r2, 0 > - assert(MI.getNumOperands() >= 3 && > - MI.getOperand(0).isReg() && > - MI.getOperand(1).isReg() && > - MI.getOperand(2).isImm() && > - "invalid PPC ORI instruction!"); > - if (MI.getOperand(2).getImm() == 0) { > - sourceReg = MI.getOperand(1).getReg(); > - destReg = MI.getOperand(0).getReg(); > - return true; > - } > - } else if (oc == PPC::FMR) { // fmr r1, r2 > - assert(MI.getNumOperands() >= 2 && > - MI.getOperand(0).isReg() && > - MI.getOperand(1).isReg() && > - "invalid PPC FMR instruction"); > - sourceReg = MI.getOperand(1).getReg(); > - destReg = MI.getOperand(0).getReg(); > - return true; > - } else if (oc == PPC::MCRF) { // mcrf cr1, cr2 > - assert(MI.getNumOperands() >= 2 && > - MI.getOperand(0).isReg() && > - MI.getOperand(1).isReg() && > - "invalid PPC MCRF instruction"); > - sourceReg = MI.getOperand(1).getReg(); > - destReg = MI.getOperand(0).getReg(); > - return true; > - } > - return false; > -} > - > unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, > int &FrameIndex) const { > switch (MI->getOpcode()) { > > Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h (original) > +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h Fri Jul 16 17:35:46 2010 > @@ -82,12 +82,6 @@ > /// > virtual const PPCRegisterInfo &getRegisterInfo() const { return RI; } > > - /// Return true if the instruction is a register to register move and return > - /// the source and dest operands and their sub-register indices by reference. > - virtual bool isMoveInstr(const MachineInstr &MI, > - unsigned &SrcReg, unsigned &DstReg, > - unsigned &SrcSubIdx, unsigned &DstSubIdx) const; > - > unsigned isLoadFromStackSlot(const MachineInstr *MI, > int &FrameIndex) const; > unsigned isStoreToStackSlot(const MachineInstr *MI, > > Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp (original) > +++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp Fri Jul 16 17:35:46 2010 > @@ -28,46 +28,6 @@ > RI(ST, *this), Subtarget(ST) { > } > > -static bool isZeroImm(const MachineOperand &op) { > - return op.isImm() && op.getImm() == 0; > -} > - > -/// Return true if the instruction is a register to register move and > -/// leave the source and dest operands in the passed parameters. > -/// > -bool SparcInstrInfo::isMoveInstr(const MachineInstr &MI, > - unsigned &SrcReg, unsigned &DstReg, > - unsigned &SrcSR, unsigned &DstSR) const { > - SrcSR = DstSR = 0; // No sub-registers. > - > - // We look for 3 kinds of patterns here: > - // or with G0 or 0 > - // add with G0 or 0 > - // fmovs or FpMOVD (pseudo double move). > - if (MI.getOpcode() == SP::ORrr || MI.getOpcode() == SP::ADDrr) { > - if (MI.getOperand(1).getReg() == SP::G0) { > - DstReg = MI.getOperand(0).getReg(); > - SrcReg = MI.getOperand(2).getReg(); > - return true; > - } else if (MI.getOperand(2).getReg() == SP::G0) { > - DstReg = MI.getOperand(0).getReg(); > - SrcReg = MI.getOperand(1).getReg(); > - return true; > - } > - } else if ((MI.getOpcode() == SP::ORri || MI.getOpcode() == SP::ADDri) && > - isZeroImm(MI.getOperand(2)) && MI.getOperand(1).isReg()) { > - DstReg = MI.getOperand(0).getReg(); > - SrcReg = MI.getOperand(1).getReg(); > - return true; > - } else if (MI.getOpcode() == SP::FMOVS || MI.getOpcode() == SP::FpMOVD || > - MI.getOpcode() == SP::FMOVD) { > - SrcReg = MI.getOperand(1).getReg(); > - DstReg = MI.getOperand(0).getReg(); > - return true; > - } > - return false; > -} > - > /// isLoadFromStackSlot - If the specified machine instruction is a direct > /// load from a stack slot, return the virtual or physical register number of > /// the destination along with the FrameIndex of the loaded stack slot. If > > Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h (original) > +++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h Fri Jul 16 17:35:46 2010 > @@ -43,12 +43,6 @@ > /// > virtual const SparcRegisterInfo &getRegisterInfo() const { return RI; } > > - /// Return true if the instruction is a register to register move and return > - /// the source and dest operands and their sub-register indices by reference. > - virtual bool isMoveInstr(const MachineInstr &MI, > - unsigned &SrcReg, unsigned &DstReg, > - unsigned &SrcSubIdx, unsigned &DstSubIdx) const; > - > /// isLoadFromStackSlot - If the specified machine instruction is a direct > /// load from a stack slot, return the virtual or physical register number of > /// the destination along with the FrameIndex of the loaded stack slot. If > > Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp (original) > +++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp Fri Jul 16 17:35:46 2010 > @@ -141,31 +141,6 @@ > .addReg(SrcReg, getKillRegState(KillSrc)); > } > > -bool > -SystemZInstrInfo::isMoveInstr(const MachineInstr& MI, > - unsigned &SrcReg, unsigned &DstReg, > - unsigned &SrcSubIdx, unsigned &DstSubIdx) const { > - switch (MI.getOpcode()) { > - default: > - return false; > - case SystemZ::MOV32rr: > - case SystemZ::MOV64rr: > - case SystemZ::MOV64rrP: > - case SystemZ::MOV128rr: > - case SystemZ::FMOV32rr: > - case SystemZ::FMOV64rr: > - assert(MI.getNumOperands() >= 2 && > - MI.getOperand(0).isReg() && > - MI.getOperand(1).isReg() && > - "invalid register-register move instruction"); > - SrcReg = MI.getOperand(1).getReg(); > - DstReg = MI.getOperand(0).getReg(); > - SrcSubIdx = MI.getOperand(1).getSubReg(); > - DstSubIdx = MI.getOperand(0).getSubReg(); > - return true; > - } > -} > - > unsigned SystemZInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, > int &FrameIndex) const { > switch (MI->getOpcode()) { > > Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h (original) > +++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h Fri Jul 16 17:35:46 2010 > @@ -65,9 +65,6 @@ > unsigned DestReg, unsigned SrcReg, > bool KillSrc) const; > > - bool isMoveInstr(const MachineInstr& MI, > - unsigned &SrcReg, unsigned &DstReg, > - unsigned &SrcSubIdx, unsigned &DstSubIdx) const; > unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; > unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const; > > > Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) > +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Fri Jul 16 17:35:46 2010 > @@ -667,46 +667,6 @@ > assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?"); > } > > -bool X86InstrInfo::isMoveInstr(const MachineInstr& MI, > - unsigned &SrcReg, unsigned &DstReg, > - unsigned &SrcSubIdx, unsigned &DstSubIdx) const { > - switch (MI.getOpcode()) { > - default: > - return false; > - case X86::MOV8rr: > - case X86::MOV8rr_NOREX: > - case X86::MOV16rr: > - case X86::MOV32rr: > - case X86::MOV64rr: > - case X86::MOV32rr_TC: > - case X86::MOV64rr_TC: > - > - // FP Stack register class copies > - case X86::MOV_Fp3232: case X86::MOV_Fp6464: case X86::MOV_Fp8080: > - case X86::MOV_Fp3264: case X86::MOV_Fp3280: > - case X86::MOV_Fp6432: case X86::MOV_Fp8032: > - > - // Note that MOVSSrr and MOVSDrr are not considered copies. FR32 and FR64 > - // copies are done with FsMOVAPSrr and FsMOVAPDrr. > - > - case X86::FsMOVAPSrr: > - case X86::FsMOVAPDrr: > - case X86::MOVAPSrr: > - case X86::MOVAPDrr: > - case X86::MOVDQArr: > - case X86::MMX_MOVQ64rr: > - assert(MI.getNumOperands() >= 2 && > - MI.getOperand(0).isReg() && > - MI.getOperand(1).isReg() && > - "invalid register-register move instruction"); > - SrcReg = MI.getOperand(1).getReg(); > - DstReg = MI.getOperand(0).getReg(); > - SrcSubIdx = MI.getOperand(1).getSubReg(); > - DstSubIdx = MI.getOperand(0).getSubReg(); > - return true; > - } > -} > - > bool > X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI, > unsigned &SrcReg, unsigned &DstReg, > > Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original) > +++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Fri Jul 16 17:35:46 2010 > @@ -610,12 +610,6 @@ > /// > virtual const X86RegisterInfo &getRegisterInfo() const { return RI; } > > - /// Return true if the instruction is a register to register move and return > - /// the source and dest operands and their sub-register indices by reference. > - virtual bool isMoveInstr(const MachineInstr &MI, > - unsigned &SrcReg, unsigned &DstReg, > - unsigned &SrcSubIdx, unsigned &DstSubIdx) const; > - > /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" > /// extension instruction. That is, it's like a copy where it's legal for the > /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns > > Modified: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp?rev=108567&r1=108566&r2=108567&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp (original) > +++ llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp Fri Jul 16 17:35:46 2010 > @@ -46,33 +46,6 @@ > return op.isImm() && op.getImm() == 0; > } > > -/// Return true if the instruction is a register to register move and > -/// leave the source and dest operands in the passed parameters. > -/// > -bool XCoreInstrInfo::isMoveInstr(const MachineInstr &MI, > - unsigned &SrcReg, unsigned &DstReg, > - unsigned &SrcSR, unsigned &DstSR) const { > - SrcSR = DstSR = 0; // No sub-registers. > - > - // We look for 4 kinds of patterns here: > - // add dst, src, 0 > - // sub dst, src, 0 > - // or dst, src, src > - // and dst, src, src > - if ((MI.getOpcode() == XCore::ADD_2rus || MI.getOpcode() == XCore::SUB_2rus) > - && isZeroImm(MI.getOperand(2))) { > - DstReg = MI.getOperand(0).getReg(); > - SrcReg = MI.getOperand(1).getReg(); > - return true; > - } else if ((MI.getOpcode() == XCore::OR_3r || MI.getOpcode() == XCore::AND_3r) > - && MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) { > - DstReg = MI.getOperand(0).getReg(); > - SrcReg = MI.getOperand(1).getReg(); > - return true; > - } > - return false; > -} > - > /// isLoadFromStackSlot - If the specified machine instruction is a direct > /// load from a stack slot, return the virtual or physical register number of > /// the destination along with the FrameIndex of the loaded stack slot. If > > Modified: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h?rev=108567&r1=108566&r2=108567&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h (original) > +++ llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h Fri Jul 16 17:35:46 2010 > @@ -30,12 +30,6 @@ > /// > virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; } > > - /// Return true if the instruction is a register to register move and return > - /// the source and dest operands and their sub-register indices by reference. > - virtual bool isMoveInstr(const MachineInstr &MI, > - unsigned &SrcReg, unsigned &DstReg, > - unsigned &SrcSubIdx, unsigned &DstSubIdx) const; > - > /// isLoadFromStackSlot - If the specified machine instruction is a direct > /// load from a stack slot, return the virtual or physical register number of > /// the destination along with the FrameIndex of the loaded stack slot. If > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100717/8500cf0d/attachment.html From lhames at gmail.com Sat Jul 17 19:10:04 2010 From: lhames at gmail.com (Lang Hames) Date: Sun, 18 Jul 2010 10:10:04 +1000 Subject: [llvm-commits] [llvm] r108615 - in /llvm/trunk: include/llvm/Analysis/LoopInfo.h include/llvm/CodeGen/LiveIntervalAnalysis.h lib/CodeGen/Splitter.cpp lib/CodeGen/Splitter.h In-Reply-To: References: <20100717073401.79A5A2A6C12D@llvm.org> Message-ID: Hi Chris, > Wouldn't it make more sense to integrate splitting with the spilling policy? It seems that it makes the most sense to do splitting while iteratively handling spilling. If you have enough registers, there is no reason to split. Yep - that's where I'm headed. The current setup is just meant to be a trial-by-fire for splitter correctness. Cheers, Lang. On Sun, Jul 18, 2010 at 2:02 AM, Chris Lattner wrote: > > On Jul 17, 2010, at 12:39 AM, Lang Hames wrote: > > > Also not hooked up to anything yet. > > > > At present if you require this pass in your register allocator it'll go > ahead aggressively split all your intervals, undoing half of the > SimpleRegisterCoalescer's good work. I'll change this to more sane behaviour > soon. > > Hey Lang, > > Wouldn't it make more sense to integrate splitting with the spilling > policy? It seems that it makes the most sense to do splitting while > iteratively handling spilling. If you have enough registers, there is no > reason to split. > > -Chris > > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100718/54f506f0/attachment.html From lhames at gmail.com Sat Jul 17 19:57:59 2010 From: lhames at gmail.com (Lang Hames) Date: Sun, 18 Jul 2010 00:57:59 -0000 Subject: [llvm-commits] [llvm] r108634 - /llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp Message-ID: <20100718005759.D1C182A6C12C@llvm.org> Author: lhames Date: Sat Jul 17 19:57:59 2010 New Revision: 108634 URL: http://llvm.org/viewvc/llvm-project?rev=108634&view=rev Log: Added -pbqp-pre-coalescing flag to PBQP. If enabled this will cause PBQP to require LoopSplitter be run prior to register allocation. Entirely for testing purposes at the moment. Modified: llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp Modified: llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp?rev=108634&r1=108633&r2=108634&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp Sat Jul 17 19:57:59 2010 @@ -34,6 +34,7 @@ #include "PBQP/HeuristicSolver.h" #include "PBQP/Graph.h" #include "PBQP/Heuristics/Briggs.h" +#include "Splitter.h" #include "VirtRegMap.h" #include "VirtRegRewriter.h" #include "llvm/CodeGen/CalcSpillWeights.h" @@ -65,6 +66,11 @@ cl::desc("Attempt coalescing during PBQP register allocation."), cl::init(false), cl::Hidden); +static cl::opt +pbqpPreSplitting("pbqp-pre-splitting", + cl::desc("Pre-splite before PBQP register allocation."), + cl::init(false), cl::Hidden); + namespace { /// @@ -96,6 +102,8 @@ au.addPreserved(); au.addRequired(); au.addPreserved(); + if (pbqpPreSplitting) + au.addRequired(); au.addRequired(); MachineFunctionPass::getAnalysisUsage(au); } From daniel at zuster.org Sat Jul 17 23:31:09 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Sun, 18 Jul 2010 04:31:09 -0000 Subject: [llvm-commits] [zorg] r108636 - /zorg/trunk/lnt/lnt/tests/nt.py Message-ID: <20100718043109.4FDB72A6C12C@llvm.org> Author: ddunbar Date: Sat Jul 17 23:31:09 2010 New Revision: 108636 URL: http://llvm.org/viewvc/llvm-project?rev=108636&view=rev Log: LNT/nt: Change default build mode to 'Release+Asserts', to match new naming convention. Unfortunately this breaks testing against older LLVM versions, at least for now... sigh. Modified: zorg/trunk/lnt/lnt/tests/nt.py Modified: zorg/trunk/lnt/lnt/tests/nt.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/tests/nt.py?rev=108636&r1=108635&r2=108636&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/tests/nt.py (original) +++ zorg/trunk/lnt/lnt/tests/nt.py Sat Jul 17 23:31:09 2010 @@ -582,7 +582,7 @@ group = OptionGroup(parser, "Test Selection") group.add_option("", "--build-mode", dest="build_mode", metavar="NAME", help="Select the LLVM build mode to use [%default]", - type=str, action="store", default='Release') + type=str, action="store", default='Release+Asserts') group.add_option("", "--simple", dest="test_simple", help="Use TEST=simple instead of TEST=nightly", From daniel at zuster.org Sat Jul 17 23:31:11 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Sun, 18 Jul 2010 04:31:11 -0000 Subject: [llvm-commits] [zorg] r108637 - /zorg/trunk/lnt/lnt/tests/nt.py Message-ID: <20100718043111.B23B62A6C12D@llvm.org> Author: ddunbar Date: Sat Jul 17 23:31:11 2010 New Revision: 108637 URL: http://llvm.org/viewvc/llvm-project?rev=108637&view=rev Log: LNT/nt: Apple Clang is also Clang. Modified: zorg/trunk/lnt/lnt/tests/nt.py Modified: zorg/trunk/lnt/lnt/tests/nt.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/tests/nt.py?rev=108637&r1=108636&r2=108637&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/tests/nt.py (original) +++ zorg/trunk/lnt/lnt/tests/nt.py Sat Jul 17 23:31:11 2010 @@ -134,7 +134,7 @@ target_flags) # Set CC_UNDER_TEST_IS_CLANG when appropriate. - if cc_info.get('cc_name') == 'clang': + if cc_info.get('cc_name') in ('apple_clang', 'clang'): make_variables['CC_UNDER_TEST_IS_CLANG'] = '1' # Set ARCH appropriately, based on the inferred target. From resistor at mac.com Sun Jul 18 03:47:54 2010 From: resistor at mac.com (Owen Anderson) Date: Sun, 18 Jul 2010 08:47:54 -0000 Subject: [llvm-commits] [llvm] r108639 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <20100718084754.EB5022A6C12C@llvm.org> Author: resistor Date: Sun Jul 18 03:47:54 2010 New Revision: 108639 URL: http://llvm.org/viewvc/llvm-project?rev=108639&view=rev Log: Add a DAGCombine xform to fold away redundant float->double->float conversions around sqrt instructions. I am assured by people more knowledgeable than me that there are no rounding issues in eliminating this. This fixed . Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=108639&r1=108638&r2=108639&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sun Jul 18 03:47:54 2010 @@ -4926,6 +4926,19 @@ return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, Tmp, N0.getOperand(1)); } + + // (f32 fp_round (f64 sqrt (f64 fp_extend (f32)))) -> (f32 sqrt) + EVT VT0 = N0.getValueType(); + if (VT == MVT::f32 && + N0.getOpcode() == ISD::FSQRT && VT0 == MVT::f64) { + SDValue N1 = N0.getOperand(0); + EVT VT1 = N1.getValueType(); + if (N1.getOpcode() == ISD::FP_EXTEND && VT1 == MVT::f64 && + N1.getOperand(0).getValueType() == MVT::f32) { + return DAG.getNode(ISD::FSQRT, N->getDebugLoc(), MVT::f32, + N1.getOperand(0), N->getOperand(1)); + } + } return SDValue(); } From resistor at mac.com Sun Jul 18 03:57:19 2010 From: resistor at mac.com (Owen Anderson) Date: Sun, 18 Jul 2010 08:57:19 -0000 Subject: [llvm-commits] [llvm] r108640 - /llvm/trunk/test/CodeGen/X86/2010-07-18-sqrt.ll Message-ID: <20100718085719.568C52A6C12C@llvm.org> Author: resistor Date: Sun Jul 18 03:57:19 2010 New Revision: 108640 URL: http://llvm.org/viewvc/llvm-project?rev=108640&view=rev Log: Add a testcase for r108639. Added: llvm/trunk/test/CodeGen/X86/2010-07-18-sqrt.ll Added: llvm/trunk/test/CodeGen/X86/2010-07-18-sqrt.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-07-18-sqrt.ll?rev=108640&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2010-07-18-sqrt.ll (added) +++ llvm/trunk/test/CodeGen/X86/2010-07-18-sqrt.ll Sun Jul 18 03:57:19 2010 @@ -0,0 +1,17 @@ +; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.0.0" + +define float @foo(float %x) nounwind readnone ssp { +entry: +; CHECK-NOT: cvtss2sd +; CHECK-NOT: sqrtsd +; CHECK-NOT: cvtsd2ss +; CHECK: sqrtss + %conv = fpext float %x to double ; [#uses=1] + %call = tail call double @sqrt(double %conv) nounwind ; [#uses=1] + %conv1 = fptrunc double %call to float ; [#uses=1] + ret float %conv1 +} + +declare double @sqrt(double) readnone From lhames at gmail.com Sun Jul 18 04:09:50 2010 From: lhames at gmail.com (Lang Hames) Date: Sun, 18 Jul 2010 19:09:50 +1000 Subject: [llvm-commits] [llvm] r108118 - /llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp In-Reply-To: <20100712014538.AC33A2A6C12C@llvm.org> References: <20100712014538.AC33A2A6C12C@llvm.org> Message-ID: > I think that the test for virtual registers is more strict than it needs to be, > it should be possible to coalesce two virtual registers the class of one > is a subclass of the other. That certainly sounds safe if the destination class is a subclass of the source class. I assume going the other way is dangerous, in that it could leave junk in the non-aliased portion of the super-register? Cheers, Lang. On Mon, Jul 12, 2010 at 11:45 AM, Rafael Espindola < rafael.espindola at gmail.com> wrote: > Author: rafael > Date: Sun Jul 11 20:45:38 2010 > New Revision: 108118 > > URL: http://llvm.org/viewvc/llvm-project?rev=108118&view=rev > Log: > Don't use getPhysicalRegisterRegClass in PBQP. The existing checks that the > physical register can be allocated in the class of the virtual are > sufficient. > > I think that the test for virtual registers is more strict than it needs to > be, > it should be possible to coalesce two virtual registers the class of one > is a subclass of the other. > > Modified: > llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp > > Modified: llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp?rev=108118&r1=108117&r2=108118&view=diff > > ============================================================================== > --- llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp (original) > +++ llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp Sun Jul 11 20:45:38 2010 > @@ -396,28 +396,23 @@ > if (srcRegIsPhysical && dstRegIsPhysical) > continue; > > - // If it's a copy that includes a virtual register but the source > and > - // destination classes differ then we can't coalesce, so continue > with > - // the next instruction. > - const TargetRegisterClass *srcRegClass = srcRegIsPhysical ? > - tri->getPhysicalRegisterRegClass(srcReg) : > mri->getRegClass(srcReg); > - > - const TargetRegisterClass *dstRegClass = dstRegIsPhysical ? > - tri->getPhysicalRegisterRegClass(dstReg) : > mri->getRegClass(dstReg); > - > - if (srcRegClass != dstRegClass) > + // If it's a copy that includes two virtual register but the source > and > + // destination classes differ then we can't coalesce. > + if (!srcRegIsPhysical && !dstRegIsPhysical && > + mri->getRegClass(srcReg) != mri->getRegClass(dstReg)) > continue; > > - // We also need any physical regs to be allocable, coalescing with > - // a non-allocable register is invalid. > - if (srcRegIsPhysical) { > + // If one is physical and one is virtual, check that the physical is > + // allocatable in the class of the virtual. > + if (srcRegIsPhysical && !dstRegIsPhysical) { > + const TargetRegisterClass *dstRegClass = mri->getRegClass(dstReg); > if (std::find(dstRegClass->allocation_order_begin(*mf), > dstRegClass->allocation_order_end(*mf), srcReg) == > dstRegClass->allocation_order_end(*mf)) > continue; > } > - > - if (dstRegIsPhysical) { > + if (!srcRegIsPhysical && dstRegIsPhysical) { > + const TargetRegisterClass *srcRegClass = mri->getRegClass(srcReg); > if (std::find(srcRegClass->allocation_order_begin(*mf), > srcRegClass->allocation_order_end(*mf), dstReg) == > srcRegClass->allocation_order_end(*mf)) > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100718/b011cd4f/attachment.html From dgregor at apple.com Sun Jul 18 06:47:56 2010 From: dgregor at apple.com (Douglas Gregor) Date: Sun, 18 Jul 2010 11:47:56 -0000 Subject: [llvm-commits] [llvm] r108642 - /llvm/trunk/lib/CodeGen/Splitter.h Message-ID: <20100718114756.F2A362A6C12C@llvm.org> Author: dgregor Date: Sun Jul 18 06:47:56 2010 New Revision: 108642 URL: http://llvm.org/viewvc/llvm-project?rev=108642&view=rev Log: Fix struct/class mismatch Modified: llvm/trunk/lib/CodeGen/Splitter.h Modified: llvm/trunk/lib/CodeGen/Splitter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Splitter.h?rev=108642&r1=108641&r2=108642&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/Splitter.h (original) +++ llvm/trunk/lib/CodeGen/Splitter.h Sun Jul 18 06:47:56 2010 @@ -23,7 +23,7 @@ class LiveInterval; class LiveIntervals; - class LiveRange; + struct LiveRange; class LoopSplit; class MachineDominatorTree; class MachineRegisterInfo; From clattner at apple.com Sun Jul 18 12:50:37 2010 From: clattner at apple.com (Chris Lattner) Date: Sun, 18 Jul 2010 10:50:37 -0700 Subject: [llvm-commits] [llvm] r108639 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp In-Reply-To: <20100718084754.EB5022A6C12C@llvm.org> References: <20100718084754.EB5022A6C12C@llvm.org> Message-ID: <9A1C9E46-38B4-4B1E-9B56-2DA374BF9E8A@apple.com> On Jul 18, 2010, at 1:47 AM, Owen Anderson wrote: > Author: resistor > Date: Sun Jul 18 03:47:54 2010 > New Revision: 108639 > > URL: http://llvm.org/viewvc/llvm-project?rev=108639&view=rev > Log: > Add a DAGCombine xform to fold away redundant float->double->float conversions around sqrt instructions. > I am assured by people more knowledgeable than me that there are no rounding issues in eliminating this. > > This fixed . Why a dag combine? I thought that instcombine or simplifylibcalls already did this? Doing this in the optimizer exposes other opportunities (e.g. when it is cross-block). -Chris > > Modified: > llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=108639&r1=108638&r2=108639&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sun Jul 18 03:47:54 2010 > @@ -4926,6 +4926,19 @@ > return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, > Tmp, N0.getOperand(1)); > } > + > + // (f32 fp_round (f64 sqrt (f64 fp_extend (f32)))) -> (f32 sqrt) > + EVT VT0 = N0.getValueType(); > + if (VT == MVT::f32 && > + N0.getOpcode() == ISD::FSQRT && VT0 == MVT::f64) { > + SDValue N1 = N0.getOperand(0); > + EVT VT1 = N1.getValueType(); > + if (N1.getOpcode() == ISD::FP_EXTEND && VT1 == MVT::f64 && > + N1.getOperand(0).getValueType() == MVT::f32) { > + return DAG.getNode(ISD::FSQRT, N->getDebugLoc(), MVT::f32, > + N1.getOperand(0), N->getOperand(1)); > + } > + } > > return SDValue(); > } > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From resistor at mac.com Sun Jul 18 13:21:14 2010 From: resistor at mac.com (Owen Anderson) Date: Sun, 18 Jul 2010 11:21:14 -0700 Subject: [llvm-commits] [llvm] r108639 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp In-Reply-To: <9A1C9E46-38B4-4B1E-9B56-2DA374BF9E8A@apple.com> References: <20100718084754.EB5022A6C12C@llvm.org> <9A1C9E46-38B4-4B1E-9B56-2DA374BF9E8A@apple.com> Message-ID: <15083EB0-FA01-4730-88DF-2B92CB0FB549@mac.com> On Jul 18, 2010, at 10:50 AM, Chris Lattner wrote: > > On Jul 18, 2010, at 1:47 AM, Owen Anderson wrote: > >> Author: resistor >> Date: Sun Jul 18 03:47:54 2010 >> New Revision: 108639 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=108639&view=rev >> Log: >> Add a DAGCombine xform to fold away redundant float->double->float conversions around sqrt instructions. >> I am assured by people more knowledgeable than me that there are no rounding issues in eliminating this. >> >> This fixed . > > Why a dag combine? I thought that instcombine or simplifylibcalls already did this? Doing this in the optimizer exposes other opportunities (e.g. when it is cross-block). The code this comes from is of the form: double foo(double x) { return sqrt(x); } The call to sqrt() does not get eliminated from the IR before it hits code-gen, so InstCombine definitely won't be doing anything about it. We could conceivably have SimplifyLibCalls convert sqrt() into an intrinsic on platforms where it's supported, and then have InstCombine optimize this extend->sqrt->round patten, but SelectionDAG is basically doing the same thing (converts sqrt() to intrinsic, and then we can optimize it there). --Owen From daniel at zuster.org Sun Jul 18 13:31:29 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Sun, 18 Jul 2010 18:31:29 -0000 Subject: [llvm-commits] [llvm] r108644 - /llvm/trunk/tools/llvm-mc/llvm-mc.cpp Message-ID: <20100718183129.1A1562A6C12C@llvm.org> Author: ddunbar Date: Sun Jul 18 13:31:28 2010 New Revision: 108644 URL: http://llvm.org/viewvc/llvm-project?rev=108644&view=rev Log: llvm-mc: Fix llvm-mc -as-lex. Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=108644&r1=108643&r2=108644&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original) +++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Sun Jul 18 13:31:28 2010 @@ -165,9 +165,9 @@ assert(MAI && "Unable to create target asm info!"); AsmLexer Lexer(*MAI); - + Lexer.setBuffer(SrcMgr.getMemoryBuffer(0)); + bool Error = false; - while (Lexer.Lex().isNot(AsmToken::Eof)) { switch (Lexer.getKind()) { default: From daniel at zuster.org Sun Jul 18 13:31:34 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Sun, 18 Jul 2010 18:31:34 -0000 Subject: [llvm-commits] [llvm] r108645 - in /llvm/trunk: lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp tools/edis/EDDisassembler.cpp tools/llvm-mc/llvm-mc.cpp Message-ID: <20100718183134.16B6C2A6C12D@llvm.org> Author: ddunbar Date: Sun Jul 18 13:31:33 2010 New Revision: 108645 URL: http://llvm.org/viewvc/llvm-project?rev=108645&view=rev Log: MC: Move several clients to using AsmParser constructor function. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp llvm/trunk/tools/edis/EDDisassembler.cpp llvm/trunk/tools/llvm-mc/llvm-mc.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp?rev=108645&r1=108644&r2=108645&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp Sun Jul 18 13:31:33 2010 @@ -22,7 +22,6 @@ #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSymbol.h" -#include "llvm/MC/MCParser/AsmParser.h" #include "llvm/Target/TargetAsmParser.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetRegistry.h" @@ -72,16 +71,18 @@ // Tell SrcMgr about this buffer, it takes ownership of the buffer. SrcMgr.AddNewSourceBuffer(Buffer, SMLoc()); - AsmParser Parser(TM.getTarget(), SrcMgr, OutContext, OutStreamer, *MAI); - OwningPtr TAP(TM.getTarget().createAsmParser(Parser)); + OwningPtr Parser(createMCAsmParser(TM.getTarget(), SrcMgr, + OutContext, OutStreamer, + *MAI)); + OwningPtr TAP(TM.getTarget().createAsmParser(*Parser)); if (!TAP) report_fatal_error("Inline asm not supported by this streamer because" " we don't have an asm parser for this target\n"); - Parser.setTargetParser(*TAP.get()); + Parser->setTargetParser(*TAP.get()); // Don't implicitly switch to the text section before the asm. - int Res = Parser.Run(/*NoInitialTextSection*/ true, - /*NoFinalize*/ true); + int Res = Parser->Run(/*NoInitialTextSection*/ true, + /*NoFinalize*/ true); if (Res && !HasDiagHandler) report_fatal_error("Error parsing inline asm\n"); } Modified: llvm/trunk/tools/edis/EDDisassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/edis/EDDisassembler.cpp?rev=108645&r1=108644&r2=108645&view=diff ============================================================================== --- llvm/trunk/tools/edis/EDDisassembler.cpp (original) +++ llvm/trunk/tools/edis/EDDisassembler.cpp Sun Jul 18 13:31:33 2010 @@ -27,7 +27,6 @@ #include "llvm/MC/MCInstPrinter.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCParser/AsmLexer.h" -#include "llvm/MC/MCParser/AsmParser.h" #include "llvm/MC/MCParser/MCAsmParser.h" #include "llvm/MC/MCParser/MCParsedAsmOperand.h" #include "llvm/Support/MemoryBuffer.h" @@ -364,11 +363,13 @@ sourceMgr.AddNewSourceBuffer(buf, SMLoc()); // ownership of buf handed over MCContext context(*AsmInfo); OwningPtr streamer(createNullStreamer(context)); - AsmParser genericParser(*Tgt, sourceMgr, context, *streamer, *AsmInfo); - OwningPtr TargetParser(Tgt->createAsmParser(genericParser)); + OwningPtr genericParser(createMCAsmParser(*Tgt, sourceMgr, + context, *streamer, + *AsmInfo)); + OwningPtr TargetParser(Tgt->createAsmParser(*genericParser)); - AsmToken OpcodeToken = genericParser.Lex(); - AsmToken NextToken = genericParser.Lex(); // consume next token, because specificParser expects us to + AsmToken OpcodeToken = genericParser->Lex(); + AsmToken NextToken = genericParser->Lex(); // consume next token, because specificParser expects us to if (OpcodeToken.is(AsmToken::Identifier)) { instName = OpcodeToken.getString(); Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=108645&r1=108644&r2=108645&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original) +++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Sun Jul 18 13:31:33 2010 @@ -12,13 +12,13 @@ // //===----------------------------------------------------------------------===// +#include "llvm/MC/MCParser/AsmLexer.h" #include "llvm/MC/MCParser/MCAsmLexer.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCCodeEmitter.h" #include "llvm/MC/MCInstPrinter.h" #include "llvm/MC/MCSectionMachO.h" #include "llvm/MC/MCStreamer.h" -#include "llvm/MC/MCParser/AsmParser.h" #include "llvm/Target/TargetAsmBackend.h" #include "llvm/Target/TargetAsmParser.h" #include "llvm/Target/TargetData.h" @@ -312,17 +312,18 @@ Str.reset(createLoggingStreamer(Str.take(), errs())); } - AsmParser Parser(*TheTarget, SrcMgr, Ctx, *Str.get(), *MAI); - OwningPtr TAP(TheTarget->createAsmParser(Parser)); + OwningPtr Parser(createMCAsmParser(*TheTarget, SrcMgr, Ctx, + *Str.get(), *MAI)); + OwningPtr TAP(TheTarget->createAsmParser(*Parser)); if (!TAP) { errs() << ProgName << ": error: this target does not support assembly parsing.\n"; return 1; } - Parser.setTargetParser(*TAP.get()); + Parser->setTargetParser(*TAP.get()); - int Res = Parser.Run(NoInitialTextSection); + int Res = Parser->Run(NoInitialTextSection); delete Out; // Delete output on errors. From daniel at zuster.org Sun Jul 18 13:31:38 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Sun, 18 Jul 2010 18:31:38 -0000 Subject: [llvm-commits] [llvm] r108646 - in /llvm/trunk: include/llvm/MC/MCParser/AsmParser.h lib/MC/MCParser/AsmParser.cpp Message-ID: <20100718183138.587D02A6C12C@llvm.org> Author: ddunbar Date: Sun Jul 18 13:31:38 2010 New Revision: 108646 URL: http://llvm.org/viewvc/llvm-project?rev=108646&view=rev Log: MC/AsmParser: Hide the AsmParser implementation. Removed: llvm/trunk/include/llvm/MC/MCParser/AsmParser.h Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp Removed: llvm/trunk/include/llvm/MC/MCParser/AsmParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/AsmParser.h?rev=108645&view=auto ============================================================================== --- llvm/trunk/include/llvm/MC/MCParser/AsmParser.h (original) +++ llvm/trunk/include/llvm/MC/MCParser/AsmParser.h (removed) @@ -1,148 +0,0 @@ -//===- AsmParser.h - Parser for Assembly Files ------------------*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This class declares the parser for assembly files. -// -//===----------------------------------------------------------------------===// - -#ifndef ASMPARSER_H -#define ASMPARSER_H - -#include "llvm/MC/MCParser/AsmLexer.h" -#include "llvm/MC/MCParser/AsmCond.h" -#include "llvm/MC/MCParser/MCAsmParser.h" -#include "llvm/MC/MCSectionMachO.h" -#include "llvm/MC/MCStreamer.h" -#include "llvm/MC/MCAsmInfo.h" -#include "llvm/ADT/StringMap.h" -#include - -namespace llvm { -class AsmCond; -class AsmToken; -class MCAsmParserExtension; -class MCContext; -class MCExpr; -class MCInst; -class MCStreamer; -class MCAsmInfo; -class SourceMgr; -class TargetAsmParser; -class Twine; - -class AsmParser : public MCAsmParser { - AsmParser(const AsmParser &); // DO NOT IMPLEMENT - void operator=(const AsmParser &); // DO NOT IMPLEMENT -private: - AsmLexer Lexer; - MCContext &Ctx; - MCStreamer &Out; - SourceMgr &SrcMgr; - MCAsmParserExtension *GenericParser; - MCAsmParserExtension *PlatformParser; - - /// This is the current buffer index we're lexing from as managed by the - /// SourceMgr object. - int CurBuffer; - - AsmCond TheCondState; - std::vector TheCondStack; - - /// DirectiveMap - This is a table handlers for directives. Each handler is - /// invoked after the directive identifier is read and is responsible for - /// parsing and validating the rest of the directive. The handler is passed - /// in the directive name and the location of the directive keyword. - StringMap > DirectiveMap; -public: - AsmParser(const Target &T, SourceMgr &SM, MCContext &Ctx, MCStreamer &Out, - const MCAsmInfo &MAI); - ~AsmParser(); - - virtual bool Run(bool NoInitialTextSection, bool NoFinalize = false); - - void AddDirectiveHandler(MCAsmParserExtension *Object, - StringRef Directive, - DirectiveHandler Handler) { - DirectiveMap[Directive] = std::make_pair(Object, Handler); - } - -public: - /// @name MCAsmParser Interface - /// { - - virtual SourceMgr &getSourceManager() { return SrcMgr; } - virtual MCAsmLexer &getLexer() { return Lexer; } - virtual MCContext &getContext() { return Ctx; } - virtual MCStreamer &getStreamer() { return Out; } - - virtual void Warning(SMLoc L, const Twine &Meg); - virtual bool Error(SMLoc L, const Twine &Msg); - - const AsmToken &Lex(); - - bool ParseExpression(const MCExpr *&Res); - virtual bool ParseExpression(const MCExpr *&Res, SMLoc &EndLoc); - virtual bool ParseParenExpression(const MCExpr *&Res, SMLoc &EndLoc); - virtual bool ParseAbsoluteExpression(int64_t &Res); - - /// } - -private: - bool ParseStatement(); - - void PrintMessage(SMLoc Loc, const std::string &Msg, const char *Type) const; - - /// EnterIncludeFile - Enter the specified file. This returns true on failure. - bool EnterIncludeFile(const std::string &Filename); - - void EatToEndOfStatement(); - - bool ParseAssignment(StringRef Name); - - bool ParsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc); - bool ParseBinOpRHS(unsigned Precedence, const MCExpr *&Res, SMLoc &EndLoc); - bool ParseParenExpr(const MCExpr *&Res, SMLoc &EndLoc); - - /// ParseIdentifier - Parse an identifier or string (as a quoted identifier) - /// and set \arg Res to the identifier contents. - bool ParseIdentifier(StringRef &Res); - - // Directive Parsing. - bool ParseDirectiveAscii(bool ZeroTerminated); // ".ascii", ".asciiz" - bool ParseDirectiveValue(unsigned Size); // ".byte", ".long", ... - bool ParseDirectiveFill(); // ".fill" - bool ParseDirectiveSpace(); // ".space" - bool ParseDirectiveSet(); // ".set" - bool ParseDirectiveOrg(); // ".org" - // ".align{,32}", ".p2align{,w,l}" - bool ParseDirectiveAlign(bool IsPow2, unsigned ValueSize); - - /// ParseDirectiveSymbolAttribute - Parse a directive like ".globl" which - /// accepts a single symbol (which should be a label or an external). - bool ParseDirectiveSymbolAttribute(MCSymbolAttr Attr); - bool ParseDirectiveELFType(); // ELF specific ".type" - - bool ParseDirectiveComm(bool IsLocal); // ".comm" and ".lcomm" - - bool ParseDirectiveAbort(); // ".abort" - bool ParseDirectiveInclude(); // ".include" - - bool ParseDirectiveIf(SMLoc DirectiveLoc); // ".if" - bool ParseDirectiveElseIf(SMLoc DirectiveLoc); // ".elseif" - bool ParseDirectiveElse(SMLoc DirectiveLoc); // ".else" - bool ParseDirectiveEndIf(SMLoc DirectiveLoc); // .endif - - /// ParseEscapedString - Parse the current token as a string which may include - /// escaped characters and return the string contents. - bool ParseEscapedString(std::string &Data); -}; - -} // end namespace llvm - -#endif Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=108646&r1=108645&r2=108646&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Sun Jul 18 13:31:38 2010 @@ -11,25 +11,139 @@ // //===----------------------------------------------------------------------===// -#include "llvm/MC/MCParser/AsmParser.h" #include "llvm/ADT/SmallString.h" +#include "llvm/ADT/StringMap.h" #include "llvm/ADT/StringSwitch.h" #include "llvm/ADT/Twine.h" +#include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" +#include "llvm/MC/MCParser/AsmCond.h" +#include "llvm/MC/MCParser/AsmLexer.h" +#include "llvm/MC/MCParser/MCAsmParser.h" +#include "llvm/MC/MCParser/MCParsedAsmOperand.h" +#include "llvm/MC/MCSectionMachO.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSymbol.h" -#include "llvm/MC/MCParser/MCParsedAsmOperand.h" #include "llvm/Support/Compiler.h" -#include "llvm/Support/SourceMgr.h" #include "llvm/Support/MemoryBuffer.h" +#include "llvm/Support/SourceMgr.h" #include "llvm/Support/raw_ostream.h" #include "llvm/Target/TargetAsmParser.h" +#include using namespace llvm; namespace { +/// \brief The concrete assembly parser instance. +class AsmParser : public MCAsmParser { + AsmParser(const AsmParser &); // DO NOT IMPLEMENT + void operator=(const AsmParser &); // DO NOT IMPLEMENT +private: + AsmLexer Lexer; + MCContext &Ctx; + MCStreamer &Out; + SourceMgr &SrcMgr; + MCAsmParserExtension *GenericParser; + MCAsmParserExtension *PlatformParser; + + /// This is the current buffer index we're lexing from as managed by the + /// SourceMgr object. + int CurBuffer; + + AsmCond TheCondState; + std::vector TheCondStack; + + /// DirectiveMap - This is a table handlers for directives. Each handler is + /// invoked after the directive identifier is read and is responsible for + /// parsing and validating the rest of the directive. The handler is passed + /// in the directive name and the location of the directive keyword. + StringMap > DirectiveMap; +public: + AsmParser(const Target &T, SourceMgr &SM, MCContext &Ctx, MCStreamer &Out, + const MCAsmInfo &MAI); + ~AsmParser(); + + virtual bool Run(bool NoInitialTextSection, bool NoFinalize = false); + + void AddDirectiveHandler(MCAsmParserExtension *Object, + StringRef Directive, + DirectiveHandler Handler) { + DirectiveMap[Directive] = std::make_pair(Object, Handler); + } + +public: + /// @name MCAsmParser Interface + /// { + + virtual SourceMgr &getSourceManager() { return SrcMgr; } + virtual MCAsmLexer &getLexer() { return Lexer; } + virtual MCContext &getContext() { return Ctx; } + virtual MCStreamer &getStreamer() { return Out; } + + virtual void Warning(SMLoc L, const Twine &Meg); + virtual bool Error(SMLoc L, const Twine &Msg); + + const AsmToken &Lex(); + + bool ParseExpression(const MCExpr *&Res); + virtual bool ParseExpression(const MCExpr *&Res, SMLoc &EndLoc); + virtual bool ParseParenExpression(const MCExpr *&Res, SMLoc &EndLoc); + virtual bool ParseAbsoluteExpression(int64_t &Res); + + /// } + +private: + bool ParseStatement(); + + void PrintMessage(SMLoc Loc, const std::string &Msg, const char *Type) const; + + /// EnterIncludeFile - Enter the specified file. This returns true on failure. + bool EnterIncludeFile(const std::string &Filename); + + void EatToEndOfStatement(); + + bool ParseAssignment(StringRef Name); + + bool ParsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc); + bool ParseBinOpRHS(unsigned Precedence, const MCExpr *&Res, SMLoc &EndLoc); + bool ParseParenExpr(const MCExpr *&Res, SMLoc &EndLoc); + + /// ParseIdentifier - Parse an identifier or string (as a quoted identifier) + /// and set \arg Res to the identifier contents. + bool ParseIdentifier(StringRef &Res); + + // Directive Parsing. + bool ParseDirectiveAscii(bool ZeroTerminated); // ".ascii", ".asciiz" + bool ParseDirectiveValue(unsigned Size); // ".byte", ".long", ... + bool ParseDirectiveFill(); // ".fill" + bool ParseDirectiveSpace(); // ".space" + bool ParseDirectiveSet(); // ".set" + bool ParseDirectiveOrg(); // ".org" + // ".align{,32}", ".p2align{,w,l}" + bool ParseDirectiveAlign(bool IsPow2, unsigned ValueSize); + + /// ParseDirectiveSymbolAttribute - Parse a directive like ".globl" which + /// accepts a single symbol (which should be a label or an external). + bool ParseDirectiveSymbolAttribute(MCSymbolAttr Attr); + bool ParseDirectiveELFType(); // ELF specific ".type" + + bool ParseDirectiveComm(bool IsLocal); // ".comm" and ".lcomm" + + bool ParseDirectiveAbort(); // ".abort" + bool ParseDirectiveInclude(); // ".include" + + bool ParseDirectiveIf(SMLoc DirectiveLoc); // ".if" + bool ParseDirectiveElseIf(SMLoc DirectiveLoc); // ".elseif" + bool ParseDirectiveElse(SMLoc DirectiveLoc); // ".else" + bool ParseDirectiveEndIf(SMLoc DirectiveLoc); // .endif + + /// ParseEscapedString - Parse the current token as a string which may include + /// escaped characters and return the string contents. + bool ParseEscapedString(std::string &Data); +}; + /// \brief Generic implementations of directive handling, etc. which is shared /// (or the default, at least) for all assembler parser. class GenericAsmParser : public MCAsmParserExtension { From daniel at zuster.org Sun Jul 18 13:31:42 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Sun, 18 Jul 2010 18:31:42 -0000 Subject: [llvm-commits] [llvm] r108647 - in /llvm/trunk: include/llvm/MC/MCParser/MCAsmParser.h include/llvm/MC/MCParser/MCAsmParserExtension.h lib/MC/MCParser/ELFAsmParser.cpp lib/MC/MCParser/MCAsmParser.cpp Message-ID: <20100718183142.B28112A6C12D@llvm.org> Author: ddunbar Date: Sun Jul 18 13:31:42 2010 New Revision: 108647 URL: http://llvm.org/viewvc/llvm-project?rev=108647&view=rev Log: MC/AsmParser: Fix TokError() to accept a Twine. Modified: llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h llvm/trunk/include/llvm/MC/MCParser/MCAsmParserExtension.h llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp llvm/trunk/lib/MC/MCParser/MCAsmParser.cpp Modified: llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h?rev=108647&r1=108646&r2=108647&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h (original) +++ llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h Sun Jul 18 13:31:42 2010 @@ -83,7 +83,7 @@ const AsmToken &getTok(); /// \brief Report an error at the current lexer location. - bool TokError(const char *Msg); + bool TokError(const Twine &Msg); /// ParseIdentifier - Parse an identifier or string (as a quoted identifier) /// and set \arg Res to the identifier contents. Modified: llvm/trunk/include/llvm/MC/MCParser/MCAsmParserExtension.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/MCAsmParserExtension.h?rev=108647&r1=108646&r2=108647&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCParser/MCAsmParserExtension.h (original) +++ llvm/trunk/include/llvm/MC/MCParser/MCAsmParserExtension.h Sun Jul 18 13:31:42 2010 @@ -14,6 +14,7 @@ #include "llvm/Support/SMLoc.h" namespace llvm { +class Twine; /// \brief Generic interface for extending the MCAsmParser, /// which is implemented by target and object file assembly parser @@ -49,15 +50,14 @@ bool Error(SMLoc L, const Twine &Msg) { return getParser().Error(L, Msg); } + bool TokError(const Twine &Msg) { + return getParser().TokError(Msg); + } const AsmToken &Lex() { return getParser().Lex(); } const AsmToken &getTok() { return getParser().getTok(); } - bool TokError(const char *Msg) { - return getParser().TokError(Msg); - } - /// @} }; Modified: llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp?rev=108647&r1=108646&r2=108647&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp Sun Jul 18 13:31:42 2010 @@ -14,6 +14,7 @@ #include "llvm/MC/MCParser/MCAsmLexer.h" #include "llvm/MC/MCSectionELF.h" #include "llvm/MC/MCStreamer.h" +#include "llvm/ADT/Twine.h" using namespace llvm; namespace { Modified: llvm/trunk/lib/MC/MCParser/MCAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/MCAsmParser.cpp?rev=108647&r1=108646&r2=108647&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/MCAsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/MCAsmParser.cpp Sun Jul 18 13:31:42 2010 @@ -31,7 +31,7 @@ return getLexer().getTok(); } -bool MCAsmParser::TokError(const char *Msg) { +bool MCAsmParser::TokError(const Twine &Msg) { Error(getLexer().getLoc(), Msg); return true; } From daniel at zuster.org Sun Jul 18 13:31:45 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Sun, 18 Jul 2010 18:31:45 -0000 Subject: [llvm-commits] [llvm] r108648 - /llvm/trunk/lib/MC/MCParser/AsmParser.cpp Message-ID: <20100718183145.8645A2A6C12C@llvm.org> Author: ddunbar Date: Sun Jul 18 13:31:45 2010 New Revision: 108648 URL: http://llvm.org/viewvc/llvm-project?rev=108648&view=rev Log: MC/AsmParser: Use Error() instead of calling PrintMessage() directly. Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=108648&r1=108647&r2=108648&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Sun Jul 18 13:31:45 2010 @@ -249,7 +249,7 @@ } if (tok->is(AsmToken::Error)) - PrintMessage(Lexer.getErrLoc(), Lexer.getErr(), "error"); + Error(Lexer.getErrLoc(), Lexer.getErr()); return *tok; } @@ -1395,9 +1395,7 @@ // Attempt to switch the lexer to the included file before consuming the end // of statement to avoid losing it when we switch. if (EnterIncludeFile(Filename)) { - PrintMessage(IncludeLoc, - "Could not find include file '" + Filename + "'", - "error"); + Error(IncludeLoc, "Could not find include file '" + Filename + "'"); return true; } From daniel at zuster.org Sun Jul 18 13:38:02 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Sun, 18 Jul 2010 18:38:02 -0000 Subject: [llvm-commits] [llvm] r108649 - in /llvm/trunk: lib/MC/MCParser/AsmParser.cpp test/MC/AsmParser/macros-parsing.s Message-ID: <20100718183802.4597E2A6C12C@llvm.org> Author: ddunbar Date: Sun Jul 18 13:38:02 2010 New Revision: 108649 URL: http://llvm.org/viewvc/llvm-project?rev=108649&view=rev Log: MC/AsmParser: Add .macros_{off,on} support, not that makes sense since we don't support macros. Added: llvm/trunk/test/MC/AsmParser/macros-parsing.s Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=108649&r1=108648&r2=108649&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Sun Jul 18 13:38:02 2010 @@ -38,6 +38,8 @@ /// \brief The concrete assembly parser instance. class AsmParser : public MCAsmParser { + friend class GenericAsmParser; + AsmParser(const AsmParser &); // DO NOT IMPLEMENT void operator=(const AsmParser &); // DO NOT IMPLEMENT private: @@ -47,7 +49,7 @@ SourceMgr &SrcMgr; MCAsmParserExtension *GenericParser; MCAsmParserExtension *PlatformParser; - + /// This is the current buffer index we're lexing from as managed by the /// SourceMgr object. int CurBuffer; @@ -60,6 +62,10 @@ /// parsing and validating the rest of the directive. The handler is passed /// in the directive name and the location of the directive keyword. StringMap > DirectiveMap; + + /// Boolean tracking whether macro substitution is enabled. + unsigned MacrosEnabled : 1; + public: AsmParser(const Target &T, SourceMgr &SM, MCContext &Ctx, MCStreamer &Out, const MCAsmInfo &MAI); @@ -150,6 +156,10 @@ public: GenericAsmParser() {} + AsmParser &getParser() { + return (AsmParser&) this->MCAsmParserExtension::getParser(); + } + virtual void Initialize(MCAsmParser &Parser) { // Call the base implementation. this->MCAsmParserExtension::Initialize(Parser); @@ -161,11 +171,20 @@ &GenericAsmParser::ParseDirectiveLine)); Parser.AddDirectiveHandler(this, ".loc", MCAsmParser::DirectiveHandler( &GenericAsmParser::ParseDirectiveLoc)); + + // Macro directives. + Parser.AddDirectiveHandler(this, ".macros_on", + MCAsmParser::DirectiveHandler( + &GenericAsmParser::ParseDirectiveMacrosOnOff)); + Parser.AddDirectiveHandler(this, ".macros_off", + MCAsmParser::DirectiveHandler( + &GenericAsmParser::ParseDirectiveMacrosOnOff)); } - bool ParseDirectiveFile(StringRef, SMLoc DirectiveLoc); // ".file" - bool ParseDirectiveLine(StringRef, SMLoc DirectiveLoc); // ".line" - bool ParseDirectiveLoc(StringRef, SMLoc DirectiveLoc); // ".loc" + bool ParseDirectiveFile(StringRef, SMLoc DirectiveLoc); + bool ParseDirectiveLine(StringRef, SMLoc DirectiveLoc); + bool ParseDirectiveLoc(StringRef, SMLoc DirectiveLoc); + bool ParseDirectiveMacrosOnOff(StringRef, SMLoc DirectiveLoc); }; } @@ -183,7 +202,7 @@ MCStreamer &_Out, const MCAsmInfo &_MAI) : Lexer(_MAI), Ctx(_Ctx), Out(_Out), SrcMgr(_SM), GenericParser(new GenericAsmParser), PlatformParser(0), - CurBuffer(0) { + CurBuffer(0), MacrosEnabled(true) { Lexer.setBuffer(SrcMgr.getMemoryBuffer(CurBuffer)); // Initialize the generic parser. @@ -1593,6 +1612,19 @@ return false; } +/// ParseDirectiveMacrosOnOff +/// ::= .macros_on +/// ::= .macros_off +bool GenericAsmParser::ParseDirectiveMacrosOnOff(StringRef Directive, + SMLoc DirectiveLoc) { + if (getLexer().isNot(AsmToken::EndOfStatement)) + return Error(getLexer().getLoc(), + "unexpected token in '" + Directive + "' directive"); + + getParser().MacrosEnabled = Directive == ".macros_on"; + + return false; +} /// \brief Create an MCAsmParser instance. MCAsmParser *llvm::createMCAsmParser(const Target &T, SourceMgr &SM, Added: llvm/trunk/test/MC/AsmParser/macros-parsing.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/macros-parsing.s?rev=108649&view=auto ============================================================================== --- llvm/trunk/test/MC/AsmParser/macros-parsing.s (added) +++ llvm/trunk/test/MC/AsmParser/macros-parsing.s Sun Jul 18 13:38:02 2010 @@ -0,0 +1,8 @@ +// RUN: llvm-mc %s 2> %t.err +// RUN: FileCheck --check-prefix=CHECK-ERRORS %s < %t.err + +.macros_on +.macros_off + +// CHECK-ERRORS: .abort '"end"' detected +.abort "end" From sabre at nondot.org Sun Jul 18 13:42:18 2010 From: sabre at nondot.org (Chris Lattner) Date: Sun, 18 Jul 2010 18:42:18 -0000 Subject: [llvm-commits] [llvm] r108650 - /llvm/trunk/test/Makefile Message-ID: <20100718184219.068122A6C12C@llvm.org> Author: lattner Date: Sun Jul 18 13:42:18 2010 New Revision: 108650 URL: http://llvm.org/viewvc/llvm-project?rev=108650&view=rev Log: daniel doesn't hate me, he hates macpython 2.5, which is a very reasonable position on life! Modified: llvm/trunk/test/Makefile Modified: llvm/trunk/test/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Makefile?rev=108650&r1=108649&r2=108650&view=diff ============================================================================== --- llvm/trunk/test/Makefile (original) +++ llvm/trunk/test/Makefile Sun Jul 18 13:42:18 2010 @@ -203,6 +203,3 @@ -e "s#@SHLIBPATH_VAR@#$(SHLIBPATH_VAR)#g" \ $(PROJ_SRC_DIR)/Unit/lit.site.cfg.in > $@ -# Daniel hates Chris. -chris-lit: - make check-lit LIT_ARGS='-j16 -s' From clattner at apple.com Sun Jul 18 13:46:16 2010 From: clattner at apple.com (Chris Lattner) Date: Sun, 18 Jul 2010 11:46:16 -0700 Subject: [llvm-commits] [llvm] r108639 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp In-Reply-To: <15083EB0-FA01-4730-88DF-2B92CB0FB549@mac.com> References: <20100718084754.EB5022A6C12C@llvm.org> <9A1C9E46-38B4-4B1E-9B56-2DA374BF9E8A@apple.com> <15083EB0-FA01-4730-88DF-2B92CB0FB549@mac.com> Message-ID: On Jul 18, 2010, at 11:21 AM, Owen Anderson wrote: > > On Jul 18, 2010, at 10:50 AM, Chris Lattner wrote: > >> >> On Jul 18, 2010, at 1:47 AM, Owen Anderson wrote: >> >>> Author: resistor >>> Date: Sun Jul 18 03:47:54 2010 >>> New Revision: 108639 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=108639&view=rev >>> Log: >>> Add a DAGCombine xform to fold away redundant float->double->float conversions around sqrt instructions. >>> I am assured by people more knowledgeable than me that there are no rounding issues in eliminating this. >>> >>> This fixed . >> >> Why a dag combine? I thought that instcombine or simplifylibcalls already did this? Doing this in the optimizer exposes other opportunities (e.g. when it is cross-block). > > The code this comes from is of the form: > > double foo(double x) { > return sqrt(x); > } The code in the radar is: #include float foo(float x) { return sqrt(x); } which is float/float. -Chris From daniel at zuster.org Sun Jul 18 13:47:21 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Sun, 18 Jul 2010 18:47:21 -0000 Subject: [llvm-commits] [llvm] r108652 - in /llvm/trunk: lib/MC/MCParser/AsmParser.cpp test/MC/AsmParser/macros-parsing.s Message-ID: <20100718184721.99EAC2A6C12C@llvm.org> Author: ddunbar Date: Sun Jul 18 13:47:21 2010 New Revision: 108652 URL: http://llvm.org/viewvc/llvm-project?rev=108652&view=rev Log: MC/AsmParser: Add basic parsing support for .macro definitions. Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp llvm/trunk/test/MC/AsmParser/macros-parsing.s Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=108652&r1=108651&r2=108652&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Sun Jul 18 13:47:21 2010 @@ -36,6 +36,15 @@ namespace { +/// \brief Helper class for tracking macro definitions. +struct Macro { + StringRef Name; + StringRef Body; + +public: + Macro(StringRef N, StringRef B) : Name(N), Body(B) {} +}; + /// \brief The concrete assembly parser instance. class AsmParser : public MCAsmParser { friend class GenericAsmParser; @@ -63,6 +72,9 @@ /// in the directive name and the location of the directive keyword. StringMap > DirectiveMap; + /// MacroMap - Map of currently defined macros. + StringMap MacroMap; + /// Boolean tracking whether macro substitution is enabled. unsigned MacrosEnabled : 1; @@ -179,12 +191,21 @@ Parser.AddDirectiveHandler(this, ".macros_off", MCAsmParser::DirectiveHandler( &GenericAsmParser::ParseDirectiveMacrosOnOff)); + Parser.AddDirectiveHandler(this, ".macro", MCAsmParser::DirectiveHandler( + &GenericAsmParser::ParseDirectiveMacro)); + Parser.AddDirectiveHandler(this, ".endm", MCAsmParser::DirectiveHandler( + &GenericAsmParser::ParseDirectiveEndMacro)); + Parser.AddDirectiveHandler(this, ".endmacro", MCAsmParser::DirectiveHandler( + &GenericAsmParser::ParseDirectiveEndMacro)); } bool ParseDirectiveFile(StringRef, SMLoc DirectiveLoc); bool ParseDirectiveLine(StringRef, SMLoc DirectiveLoc); bool ParseDirectiveLoc(StringRef, SMLoc DirectiveLoc); + bool ParseDirectiveMacrosOnOff(StringRef, SMLoc DirectiveLoc); + bool ParseDirectiveMacro(StringRef, SMLoc DirectiveLoc); + bool ParseDirectiveEndMacro(StringRef, SMLoc DirectiveLoc); }; } @@ -785,6 +806,17 @@ if (IDVal == ".include") return ParseDirectiveInclude(); + // If macros are enabled, check to see if this is a macro instantiation. + if (MacrosEnabled) { + if (const Macro *M = MacroMap.lookup(IDVal)) { + (void) M; + + Error(IDLoc, "macros are not yet supported"); + EatToEndOfStatement(); + return false; + } + } + // Look up the handler in the handler table. std::pair Handler = DirectiveMap.lookup(IDVal); @@ -1626,6 +1658,70 @@ return false; } +/// ParseDirectiveMacro +/// ::= .macro name +bool GenericAsmParser::ParseDirectiveMacro(StringRef Directive, + SMLoc DirectiveLoc) { + StringRef Name; + if (getParser().ParseIdentifier(Name)) + return TokError("expected identifier in directive"); + + if (getLexer().isNot(AsmToken::EndOfStatement)) + return TokError("unexpected token in '.macro' directive"); + + // Eat the end of statement. + Lex(); + + AsmToken EndToken, StartToken = getTok(); + + // Lex the macro definition. + for (;;) { + // Check whether we have reached the end of the file. + if (getLexer().is(AsmToken::Eof)) + return Error(DirectiveLoc, "no matching '.endmacro' in definition"); + + // Otherwise, check whether we have reach the .endmacro. + if (getLexer().is(AsmToken::Identifier) && + (getTok().getIdentifier() == ".endm" || + getTok().getIdentifier() == ".endmacro")) { + EndToken = getTok(); + Lex(); + if (getLexer().isNot(AsmToken::EndOfStatement)) + return TokError("unexpected token in '" + EndToken.getIdentifier() + + "' directive"); + break; + } + + // Otherwise, scan til the end of the statement. + getParser().EatToEndOfStatement(); + } + + if (getParser().MacroMap.lookup(Name)) { + return Error(DirectiveLoc, "macro '" + Name + "' is already defined"); + } + + const char *BodyStart = StartToken.getLoc().getPointer(); + const char *BodyEnd = EndToken.getLoc().getPointer(); + StringRef Body = StringRef(BodyStart, BodyEnd - BodyStart); + getParser().MacroMap[Name] = new Macro(Name, Body); + return false; +} + +/// ParseDirectiveEndMacro +/// ::= .endm +/// ::= .endmacro +bool GenericAsmParser::ParseDirectiveEndMacro(StringRef Directive, + SMLoc DirectiveLoc) { + if (getLexer().isNot(AsmToken::EndOfStatement)) + return TokError("unexpected token in '" + Directive + "' directive"); + + // If we see a .endmacro directly, it is a stray entry in the file; well + // formed .endmacro directives are handled during the macro definition + // parsing. + return TokError("unexpected '" + Directive + "' in file, " + "no current macro definition"); +} + /// \brief Create an MCAsmParser instance. MCAsmParser *llvm::createMCAsmParser(const Target &T, SourceMgr &SM, MCContext &C, MCStreamer &Out, Modified: llvm/trunk/test/MC/AsmParser/macros-parsing.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/macros-parsing.s?rev=108652&r1=108651&r2=108652&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/macros-parsing.s (original) +++ llvm/trunk/test/MC/AsmParser/macros-parsing.s Sun Jul 18 13:47:21 2010 @@ -1,8 +1,23 @@ -// RUN: llvm-mc %s 2> %t.err +// RUN: not llvm-mc %s 2> %t.err // RUN: FileCheck --check-prefix=CHECK-ERRORS %s < %t.err -.macros_on +.macro .test0 +.endmacro + .macros_off +// CHECK-ERRORS: 9:1: warning: ignoring directive for now +.test0 +.macros_on +// CHECK-ERRORS: 12:1: error: macros are not yet supported +.test0 + +// CHECK-ERRORS: macro '.test0' is already defined +.macro .test0 +.endmacro + +// CHECK-ERRORS: unexpected '.endmacro' in file +.endmacro + +// CHECK-ERRORS: no matching '.endmacro' in definition +.macro dummy -// CHECK-ERRORS: .abort '"end"' detected -.abort "end" From resistor at mac.com Sun Jul 18 13:47:33 2010 From: resistor at mac.com (Owen Anderson) Date: Sun, 18 Jul 2010 11:47:33 -0700 Subject: [llvm-commits] [llvm] r108639 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp In-Reply-To: References: <20100718084754.EB5022A6C12C@llvm.org> <9A1C9E46-38B4-4B1E-9B56-2DA374BF9E8A@apple.com> <15083EB0-FA01-4730-88DF-2B92CB0FB549@mac.com> Message-ID: <93873D0A-7686-47FD-8B2B-EEB48F83226D@mac.com> On Jul 18, 2010, at 11:46 AM, Chris Lattner wrote: > > The code in the radar is: > > #include > float foo(float x) { > return sqrt(x); > } > > which is float/float. > Sorry, I was recreating it from memory. The rest of my message was correct, as is the transform. --Owen From daniel at zuster.org Sun Jul 18 13:54:12 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Sun, 18 Jul 2010 18:54:12 -0000 Subject: [llvm-commits] [llvm] r108653 - in /llvm/trunk: lib/MC/MCParser/AsmParser.cpp test/MC/AsmParser/macros-parsing.s Message-ID: <20100718185412.0FCAB2A6C12C@llvm.org> Author: ddunbar Date: Sun Jul 18 13:54:11 2010 New Revision: 108653 URL: http://llvm.org/viewvc/llvm-project?rev=108653&view=rev Log: MC/AsmParser: Add basic support for macro instantiation. Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp llvm/trunk/test/MC/AsmParser/macros-parsing.s Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=108653&r1=108652&r2=108653&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Sun Jul 18 13:54:11 2010 @@ -45,6 +45,25 @@ Macro(StringRef N, StringRef B) : Name(N), Body(B) {} }; +/// \brief Helper class for storing information about an active macro +/// instantiation. +struct MacroInstantiation { + /// The macro being instantiated. + const Macro *TheMacro; + + /// The macro instantiation with substitutions. + MemoryBuffer *Instantiation; + + /// The location of the instantiation. + SMLoc InstantiationLoc; + + /// The location where parsing should resume upon instantiation completion. + SMLoc ExitLoc; + +public: + MacroInstantiation(const Macro *M, SMLoc IL, SMLoc EL); +}; + /// \brief The concrete assembly parser instance. class AsmParser : public MCAsmParser { friend class GenericAsmParser; @@ -75,6 +94,9 @@ /// MacroMap - Map of currently defined macros. StringMap MacroMap; + /// ActiveMacros - Stack of active macro instantiations. + std::vector ActiveMacros; + /// Boolean tracking whether macro substitution is enabled. unsigned MacrosEnabled : 1; @@ -115,11 +137,20 @@ private: bool ParseStatement(); + bool HandleMacroEntry(StringRef Name, SMLoc NameLoc, const Macro *M); + void HandleMacroExit(); + + void PrintMacroInstantiations(); void PrintMessage(SMLoc Loc, const std::string &Msg, const char *Type) const; /// EnterIncludeFile - Enter the specified file. This returns true on failure. bool EnterIncludeFile(const std::string &Filename); - + + /// \brief Reset the current lexer position to that given by \arg Loc. The + /// current token is not set; clients should ensure Lex() is called + /// subsequently. + void JumpToLoc(SMLoc Loc); + void EatToEndOfStatement(); bool ParseAssignment(StringRef Name); @@ -247,12 +278,22 @@ delete GenericParser; } +void AsmParser::PrintMacroInstantiations() { + // Print the active macro instantiation stack. + for (std::vector::const_reverse_iterator + it = ActiveMacros.rbegin(), ie = ActiveMacros.rend(); it != ie; ++it) + PrintMessage((*it)->InstantiationLoc, "while in macro instantiation", + "note"); +} + void AsmParser::Warning(SMLoc L, const Twine &Msg) { PrintMessage(L, Msg.str(), "warning"); + PrintMacroInstantiations(); } bool AsmParser::Error(SMLoc L, const Twine &Msg) { PrintMessage(L, Msg.str(), "error"); + PrintMacroInstantiations(); return true; } @@ -272,7 +313,12 @@ return false; } - + +void AsmParser::JumpToLoc(SMLoc Loc) { + CurBuffer = SrcMgr.FindBufferContainingLoc(Loc); + Lexer.setBuffer(SrcMgr.getMemoryBuffer(CurBuffer), Loc.getPointer()); +} + const AsmToken &AsmParser::Lex() { const AsmToken *tok = &Lexer.Lex(); @@ -281,9 +327,7 @@ // include stack. SMLoc ParentIncludeLoc = SrcMgr.getParentIncludeLoc(CurBuffer); if (ParentIncludeLoc != SMLoc()) { - CurBuffer = SrcMgr.FindBufferContainingLoc(ParentIncludeLoc); - Lexer.setBuffer(SrcMgr.getMemoryBuffer(CurBuffer), - ParentIncludeLoc.getPointer()); + JumpToLoc(ParentIncludeLoc); tok = &Lexer.Lex(); } } @@ -716,7 +760,12 @@ default: // Normal instruction or directive. break; } - + + // If macros are enabled, check to see if this is a macro instantiation. + if (MacrosEnabled) + if (const Macro *M = MacroMap.lookup(IDVal)) + return HandleMacroEntry(IDVal, IDLoc, M); + // Otherwise, we have a normal instruction or directive. if (IDVal[0] == '.') { // Assembler features @@ -806,17 +855,6 @@ if (IDVal == ".include") return ParseDirectiveInclude(); - // If macros are enabled, check to see if this is a macro instantiation. - if (MacrosEnabled) { - if (const Macro *M = MacroMap.lookup(IDVal)) { - (void) M; - - Error(IDLoc, "macros are not yet supported"); - EatToEndOfStatement(); - return false; - } - } - // Look up the handler in the handler table. std::pair Handler = DirectiveMap.lookup(IDVal); @@ -871,6 +909,54 @@ return HadError; } +MacroInstantiation::MacroInstantiation(const Macro *M, SMLoc IL, SMLoc EL) + : TheMacro(M), InstantiationLoc(IL), ExitLoc(EL) +{ + // Macro instantiation is lexical, unfortunately. We construct a new buffer + // to hold the macro body with substitutions. + llvm::SmallString<256> Buf; + Buf += M->Body; + + // We include the .endmacro in the buffer as our queue to exit the macro + // instantiation. + Buf += ".endmacro\n"; + + Instantiation = MemoryBuffer::getMemBufferCopy(Buf, ""); +} + +bool AsmParser::HandleMacroEntry(StringRef Name, SMLoc NameLoc, + const Macro *M) { + // Arbitrarily limit macro nesting depth, to match 'as'. We can eliminate + // this, although we should protect against infinite loops. + if (ActiveMacros.size() == 20) + return TokError("macros cannot be nested more than 20 levels deep"); + + EatToEndOfStatement(); + + // Create the macro instantiation object and add to the current macro + // instantiation stack. + MacroInstantiation *MI = new MacroInstantiation(M, NameLoc, + getTok().getLoc()); + ActiveMacros.push_back(MI); + + // Jump to the macro instantiation and prime the lexer. + CurBuffer = SrcMgr.AddNewSourceBuffer(MI->Instantiation, SMLoc()); + Lexer.setBuffer(SrcMgr.getMemoryBuffer(CurBuffer)); + Lex(); + + return false; +} + +void AsmParser::HandleMacroExit() { + // Jump to the EndOfStatement we should return to, and consume it. + JumpToLoc(ActiveMacros.back()->ExitLoc); + Lex(); + + // Pop the instantiation entry. + delete ActiveMacros.back(); + ActiveMacros.pop_back(); +} + bool AsmParser::ParseAssignment(StringRef Name) { // FIXME: Use better location, we should use proper tokens. SMLoc EqualLoc = Lexer.getLoc(); @@ -1715,9 +1801,15 @@ if (getLexer().isNot(AsmToken::EndOfStatement)) return TokError("unexpected token in '" + Directive + "' directive"); - // If we see a .endmacro directly, it is a stray entry in the file; well - // formed .endmacro directives are handled during the macro definition - // parsing. + // If we are inside a macro instantiation, terminate the current + // instantiation. + if (!getParser().ActiveMacros.empty()) { + getParser().HandleMacroExit(); + return false; + } + + // Otherwise, this .endmacro is a stray entry in the file; well formed + // .endmacro directives are handled during the macro definition parsing. return TokError("unexpected '" + Directive + "' in file, " "no current macro definition"); } Modified: llvm/trunk/test/MC/AsmParser/macros-parsing.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/macros-parsing.s?rev=108653&r1=108652&r2=108653&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/macros-parsing.s (original) +++ llvm/trunk/test/MC/AsmParser/macros-parsing.s Sun Jul 18 13:54:11 2010 @@ -8,7 +8,7 @@ // CHECK-ERRORS: 9:1: warning: ignoring directive for now .test0 .macros_on -// CHECK-ERRORS: 12:1: error: macros are not yet supported + .test0 // CHECK-ERRORS: macro '.test0' is already defined From daniel at zuster.org Sun Jul 18 14:00:10 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Sun, 18 Jul 2010 19:00:10 -0000 Subject: [llvm-commits] [llvm] r108654 - in /llvm/trunk: lib/MC/MCParser/AsmParser.cpp test/MC/AsmParser/macro-def-in-instantiation.s test/MC/AsmParser/macros.s Message-ID: <20100718190010.678222A6C12C@llvm.org> Author: ddunbar Date: Sun Jul 18 14:00:10 2010 New Revision: 108654 URL: http://llvm.org/viewvc/llvm-project?rev=108654&view=rev Log: MC/AsmParser: Add macro argument substitution support. Added: llvm/trunk/test/MC/AsmParser/macro-def-in-instantiation.s llvm/trunk/test/MC/AsmParser/macros.s Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=108654&r1=108653&r2=108654&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Sun Jul 18 14:00:10 2010 @@ -61,7 +61,8 @@ SMLoc ExitLoc; public: - MacroInstantiation(const Macro *M, SMLoc IL, SMLoc EL); + MacroInstantiation(const Macro *M, SMLoc IL, SMLoc EL, + const std::vector > &A); }; /// \brief The concrete assembly parser instance. @@ -909,19 +910,71 @@ return HadError; } -MacroInstantiation::MacroInstantiation(const Macro *M, SMLoc IL, SMLoc EL) +MacroInstantiation::MacroInstantiation(const Macro *M, SMLoc IL, SMLoc EL, + const std::vector > &A) : TheMacro(M), InstantiationLoc(IL), ExitLoc(EL) { // Macro instantiation is lexical, unfortunately. We construct a new buffer // to hold the macro body with substitutions. - llvm::SmallString<256> Buf; - Buf += M->Body; + SmallString<256> Buf; + raw_svector_ostream OS(Buf); + + StringRef Body = M->Body; + while (!Body.empty()) { + // Scan for the next substitution. + std::size_t End = Body.size(), Pos = 0; + for (; Pos != End; ++Pos) { + // Check for a substitution or escape. + if (Body[Pos] != '$' || Pos + 1 == End) + continue; + + char Next = Body[Pos + 1]; + if (Next == '$' || Next == 'n' || isdigit(Next)) + break; + } + + // Add the prefix. + OS << Body.slice(0, Pos); + + // Check if we reached the end. + if (Pos == End) + break; + + switch (Body[Pos+1]) { + // $$ => $ + case '$': + OS << '$'; + break; + + // $n => number of arguments + case 'n': + OS << A.size(); + break; + + // $[0-9] => argument + default: { + // Missing arguments are ignored. + unsigned Index = Body[Pos+1] - '0'; + if (Index >= A.size()) + break; + + // Otherwise substitute with the token values, with spaces eliminated. + for (std::vector::const_iterator it = A[Index].begin(), + ie = A[Index].end(); it != ie; ++it) + OS << it->getString(); + break; + } + } + + // Update the scan point. + Body = Body.substr(Pos + 2); + } // We include the .endmacro in the buffer as our queue to exit the macro // instantiation. - Buf += ".endmacro\n"; + OS << ".endmacro\n"; - Instantiation = MemoryBuffer::getMemBufferCopy(Buf, ""); + Instantiation = MemoryBuffer::getMemBufferCopy(OS.str(), ""); } bool AsmParser::HandleMacroEntry(StringRef Name, SMLoc NameLoc, @@ -931,12 +984,36 @@ if (ActiveMacros.size() == 20) return TokError("macros cannot be nested more than 20 levels deep"); - EatToEndOfStatement(); + // Parse the macro instantiation arguments. + std::vector > MacroArguments; + MacroArguments.push_back(std::vector()); + unsigned ParenLevel = 0; + for (;;) { + if (Lexer.is(AsmToken::Eof)) + return TokError("unexpected token in macro instantiation"); + if (Lexer.is(AsmToken::EndOfStatement)) + break; + + // If we aren't inside parentheses and this is a comma, start a new token + // list. + if (ParenLevel == 0 && Lexer.is(AsmToken::Comma)) { + MacroArguments.push_back(std::vector()); + } else if (Lexer.is(AsmToken::LParen)) { + ++ParenLevel; + } else if (Lexer.is(AsmToken::RParen)) { + if (ParenLevel) + --ParenLevel; + } else { + MacroArguments.back().push_back(getTok()); + } + Lex(); + } // Create the macro instantiation object and add to the current macro // instantiation stack. MacroInstantiation *MI = new MacroInstantiation(M, NameLoc, - getTok().getLoc()); + getTok().getLoc(), + MacroArguments); ActiveMacros.push_back(MI); // Jump to the macro instantiation and prime the lexer. Added: llvm/trunk/test/MC/AsmParser/macro-def-in-instantiation.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/macro-def-in-instantiation.s?rev=108654&view=auto ============================================================================== --- llvm/trunk/test/MC/AsmParser/macro-def-in-instantiation.s (added) +++ llvm/trunk/test/MC/AsmParser/macro-def-in-instantiation.s Sun Jul 18 14:00:10 2010 @@ -0,0 +1,13 @@ +// RUN: llvm-mc %s | FileCheck %s + +.macro .make_macro +$0 $1 +$2 $3 +$4 +.endmacro + +.make_macro .macro,.mybyte,.byte,$0,.endmacro + +.data +// CHECK: .byte 10 +.mybyte 10 Added: llvm/trunk/test/MC/AsmParser/macros.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/macros.s?rev=108654&view=auto ============================================================================== --- llvm/trunk/test/MC/AsmParser/macros.s (added) +++ llvm/trunk/test/MC/AsmParser/macros.s Sun Jul 18 14:00:10 2010 @@ -0,0 +1,32 @@ +// RUN: llvm-mc %s 2> %t.err | FileCheck %s +// RUN: FileCheck --check-prefix=CHECK-ERRORS %s < %t.err + +.macro .test0 +.macrobody0 +.endmacro +.macro .test1 +.test0 +.endmacro + +.test1 +// CHECK-ERRORS: :1:1: warning: ignoring directive for now +// CHECK-ERRORS-NEXT: macrobody0 +// CHECK-ERRORS-NEXT: ^ +// CHECK-ERRORS: :1:1: note: while in macro instantiation +// CHECK-ERRORS-NEXT: .test0 +// CHECK-ERRORS-NEXT: ^ +// CHECK-ERRORS: 11:1: note: while in macro instantiation +// CHECK-ERRORS-NEXT: .test1 +// CHECK-ERRORS-NEXT: ^ + +.macro test2 +.byte $0 +.endmacro +test2 10 + +.macro test3 +.globl "$0 $1 $2 $$3 $n" +.endmacro + +// CHECK: .globl "1 23 $3 2" +test3 1,2 3 From clattner at apple.com Sun Jul 18 14:04:53 2010 From: clattner at apple.com (Chris Lattner) Date: Sun, 18 Jul 2010 12:04:53 -0700 Subject: [llvm-commits] [llvm] r108639 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp In-Reply-To: <93873D0A-7686-47FD-8B2B-EEB48F83226D@mac.com> References: <20100718084754.EB5022A6C12C@llvm.org> <9A1C9E46-38B4-4B1E-9B56-2DA374BF9E8A@apple.com> <15083EB0-FA01-4730-88DF-2B92CB0FB549@mac.com> <93873D0A-7686-47FD-8B2B-EEB48F83226D@mac.com> Message-ID: On Jul 18, 2010, at 11:47 AM, Owen Anderson wrote: > > On Jul 18, 2010, at 11:46 AM, Chris Lattner wrote: >> >> The code in the radar is: >> >> #include >> float foo(float x) { >> return sqrt(x); >> } >> >> which is float/float. >> > > Sorry, I was recreating it from memory. The rest of my message was correct, as is the transform. I agree that the xform is correct. Why not do it on IR though? -Chris From espindola at google.com Sun Jul 18 14:39:12 2010 From: espindola at google.com (Rafael Espindola) Date: Sun, 18 Jul 2010 15:39:12 -0400 Subject: [llvm-commits] [llvm] r108118 - /llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp In-Reply-To: References: <20100712014538.AC33A2A6C12C@llvm.org> Message-ID: On 18 July 2010 05:09, Lang Hames wrote: >> I think that the test for virtual registers is more strict than it needs >> to be, >> it should be possible to coalesce two virtual registers the class of one >> is a subclass of the other. > > That certainly sounds safe if the destination class is a subclass of the > source class. I assume going the other way is dangerous, in that it could > leave junk in the non-aliased portion of the super-register? Note that this *subclass*, not *subregister". I don't think in general it is safe to coalesce if the two classes have different value types (which is an interesting limitation now that I think of it). Lets say we have two virtual registers V0 and V1. The first one is in class S1 with physical registers R0, R1 and R2. The second one is in class S2 with registers R0, R1 and R3. If we coalesce V0 and V1, what physical registers can be used for the coalesced reg? R0 and R1. In general, we should be able to coalesce two virtual registers if they have the same value types and the resulting reg class is in the intersection of the two original ones. I wonder what would it take to be able to coalesce, for example, a vector and a fp virtual register. Just moving the value type out of the register class and into the individual operations? > Cheers, > Lang. Cheers, -- Rafael ?vila de Esp?ndola From evan.cheng at apple.com Sun Jul 18 14:39:30 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Sun, 18 Jul 2010 12:39:30 -0700 Subject: [llvm-commits] [llvm] r108628 - /llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp In-Reply-To: <20100717191844.AF3082A6C12C@llvm.org> References: <20100717191844.AF3082A6C12C@llvm.org> Message-ID: <374B992E-A486-48B3-95E8-4B1DD4164E7E@apple.com> Does this work if the code is compiled without -g? Evan On Jul 17, 2010, at 12:18 PM, Bill Wendling wrote: > Author: void > Date: Sat Jul 17 14:18:44 2010 > New Revision: 108628 > > URL: http://llvm.org/viewvc/llvm-project?rev=108628&view=rev > Log: > Use isPrologLabel() instead of checking the opcode directly. > > Modified: > llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp > > Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=108628&r1=108627&r2=108628&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original) > +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Sat Jul 17 14:18:44 2010 > @@ -661,7 +661,7 @@ > // label equaling the end of function label and an invalid "row" in the > // FDE. We need to emit a noop in this situation so that the FDE's rows are > // valid. > - bool RequiresNoop = LastMI && LastMI->getOpcode()==TargetOpcode::PROLOG_LABEL; > + bool RequiresNoop = LastMI && LastMI->isPrologLabel(); > > // If the function is empty and the object file uses .subsections_via_symbols, > // then we need to emit *something* to the function body to prevent the > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From resistor at mac.com Sun Jul 18 14:44:01 2010 From: resistor at mac.com (Owen Anderson) Date: Sun, 18 Jul 2010 12:44:01 -0700 Subject: [llvm-commits] [llvm] r108639 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp In-Reply-To: References: <20100718084754.EB5022A6C12C@llvm.org> <9A1C9E46-38B4-4B1E-9B56-2DA374BF9E8A@apple.com> <15083EB0-FA01-4730-88DF-2B92CB0FB549@mac.com> <93873D0A-7686-47FD-8B2B-EEB48F83226D@mac.com> Message-ID: On Jul 18, 2010, at 12:04 PM, Chris Lattner wrote: > I agree that the xform is correct. Why not do it on IR though? For the reasons I laid out in the earlier email, namely that it would require adding a sqrt() -> intrinsic transform at the IR level, which SelectionDAG is already doing, so it seemed like extraneous effort on the optimizer's part. If you really want, I can re-implement it as a SimplifyLibCalls+InstCombine xform, though. --Owen From evan.cheng at apple.com Sun Jul 18 14:44:59 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Sun, 18 Jul 2010 12:44:59 -0700 Subject: [llvm-commits] [llvm] r108536 - in /llvm/trunk: lib/Target/X86/CMakeLists.txt lib/Target/X86/X86.h lib/Target/X86/X86CodeEmitter.cpp lib/Target/X86/X86FloatingPointRegKill.cpp lib/Target/X86/X86InstrFPStack.td lib/Target/X86/X86InstrInfo.cpp lib/Target/X86/X86TargetMachine.cpp test/CodeGen/X86/2007-06-14-branchfold.ll In-Reply-To: <05115E25-2943-49B1-8DC4-F6DA0F523BE2@2pi.dk> References: <20100716174144.AD5F12A6C12D@llvm.org> <05115E25-2943-49B1-8DC4-F6DA0F523BE2@2pi.dk> Message-ID: <3AB6F056-58D9-4354-86C1-4C247AA82994@apple.com> Fantastic results! Thanks. Are the (few) regressions real though? Are they due to register spills? Evan On Jul 17, 2010, at 11:48 AM, Jakob Stoklund Olesen wrote: > > On Jul 17, 2010, at 10:38 AM, Chris Lattner wrote: > >> >> On Jul 16, 2010, at 10:41 AM, Jakob Stoklund Olesen wrote: >> >>> Author: stoklund >>> Date: Fri Jul 16 12:41:44 2010 >>> New Revision: 108536 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=108536&view=rev >>> Log: >>> Remove the X86::FP_REG_KILL pseudo-instruction and the X86FloatingPointRegKill >>> pass that inserted it. >>> >>> It is no longer necessary to limit the live ranges of FP registers to a single >>> basic block. >> >> This is *really really* awesome Jakob. This was a huge long-standing code quality deficiency of LLVM vs other compilers, thanks for doing it! > > No problem, we really needed to lose the arbitrary constraints on FP registers for LICM and live range splitting. > > I ran the nightly test suite with -arch i386 -mfpmath=387 -mcpu=pentium, and the global stackifier as llcbeta. These are the double-digit improvements: > > Program | LLC LLC-BETA LLC/LLC-BETA > SingleSource/Benchmarks/Misc-C++/stepanov_v1p2 | 25.5900 7.6800 3.33 > SingleSource/Benchmarks/Misc-C++/oopack_v1p8 | 0.3800 0.1400 2.71 > SingleSource/Benchmarks/Adobe-C++/stepanov_abstraction | 12.0300 5.1200 2.35 > SingleSource/Benchmarks/Misc/fp-convert | 5.6900 2.8400 2.00 > SingleSource/Benchmarks/Adobe-C++/stepanov_vector | 6.0600 3.1800 1.91 > SingleSource/Benchmarks/Misc-C++/mandel-text | 3.2800 1.7300 1.90 > SingleSource/Benchmarks/Misc/mandel-2 | 1.5500 0.8700 1.78 > SingleSource/Benchmarks/Adobe-C++/simple_types_constant_folding | 2.9700 1.6800 1.77 > MultiSource/Benchmarks/FreeBench/neural/neural | 0.3000 0.1700 1.76 > MultiSource/Benchmarks/McCat/04-bisect/bisect | 0.1600 0.1300 1.23 > SingleSource/Benchmarks/Misc/flops-3 | 2.9100 2.4400 1.19 > MultiSource/Benchmarks/ASC_Sequoia/CrystalMk/CrystalMk | 10.4000 8.7200 1.19 > SingleSource/Benchmarks/CoyoteBench/almabench | 11.5000 9.7800 1.18 > External/SPEC/CFP2006/447.dealII/447.dealII | 22.5700 19.1700 1.18 > SingleSource/Benchmarks/Misc/whetstone | 1.5500 1.3400 1.16 > SingleSource/Benchmarks/Misc/perlin | 7.8100 6.7200 1.16 > MultiSource/Benchmarks/ASC_Sequoia/AMGmk/AMGmk | 16.5200 14.3000 1.16 > SingleSource/Benchmarks/Shootout-C++/moments | 0.1600 0.1400 1.14 > SingleSource/Benchmarks/Misc/flops-4 | 1.3800 1.2100 1.14 > SingleSource/Benchmarks/Misc-C++/Large/ray | 4.7500 4.1900 1.13 > MultiSource/Benchmarks/MiBench/consumer-lame/consumer-lame | 0.3500 0.3100 1.13 > SingleSource/Benchmarks/Misc/flops-8 | 2.4500 2.2300 1.10 > SingleSource/Benchmarks/Misc/flops-2 | 2.1000 1.9200 1.09 > SingleSource/Benchmarks/Dhrystone/fldry | 1.4600 1.3400 1.09 > SingleSource/Benchmarks/Adobe-C++/simple_types_loop_invariant | 4.6600 4.2700 1.09 > SingleSource/Benchmarks/Adobe-C++/functionobjects | 4.5100 4.1200 1.09 > External/SPEC/CFP2000/179.art/179.art | 2.2000 2.0100 1.09 > > And the worst regressions: > > MultiSource/Benchmarks/FreeBench/fourinarow/fourinarow | 0.8800 0.8900 0.99 > SingleSource/Benchmarks/Shootout-C++/ary3 | 2.0100 2.0500 0.98 > SingleSource/Benchmarks/CoyoteBench/huffbench | 20.4700 20.8700 0.98 > MultiSource/Applications/sqlite3/sqlite3 | 5.3400 5.4300 0.98 > MultiSource/Applications/siod/siod | 3.5400 3.6200 0.98 > SingleSource/Benchmarks/Shootout-C++/methcall | 5.6600 5.8300 0.97 > MultiSource/Benchmarks/Olden/bh/bh | 1.7000 1.7500 0.97 > External/SPEC/CINT2006/400.perlbench/400.perlbench | 7.2000 7.4300 0.97 > SingleSource/Benchmarks/Shootout/strcat | 0.2400 0.2500 0.96 > SingleSource/Benchmarks/Dhrystone/dry | 0.3500 0.3700 0.95 > > SPEC floating point: > > External/SPEC/CFP2000/177.mesa/177.mesa | 3.2900 3.2300 1.02 > External/SPEC/CFP2000/179.art/179.art | 2.2000 2.0100 1.09 > External/SPEC/CFP2000/183.equake/183.equake | 7.7700 7.6900 1.01 > External/SPEC/CFP2000/188.ammp/188.ammp | 16.3700 15.9300 1.03 > External/SPEC/CFP2006/433.milc/433.milc | 8.3900 8.3400 1.01 > External/SPEC/CFP2006/444.namd/444.namd | 18.6700 17.5100 1.07 > External/SPEC/CFP2006/447.dealII/447.dealII | 22.5700 19.1700 1.18 > External/SPEC/CFP2006/470.lbm/470.lbm | 3.4700 3.4100 1.02 > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Sun Jul 18 14:51:45 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Sun, 18 Jul 2010 12:51:45 -0700 Subject: [llvm-commits] [llvm] r108332 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td In-Reply-To: <4C3DEA6C.50302@gmail.com> References: <20100714160213.4D9C62A6C12C@llvm.org> <4C3DEA6C.50302@gmail.com> Message-ID: <7D53B004-DE00-4EAA-BB99-B9FE8D767C88@apple.com> This is not Cortex-M3 specific. It could break all Thumb2 targets. Looks like most of the time we are able to shrink the instruction so it hasn't shown up much before. Evan On Jul 14, 2010, at 9:48 AM, bagel wrote: >> Wow. How would code work without this? >> >> Evan > > It didn't. Took me a long time to track it down. Am I the only person > using LLVM to generate code for a Cortex-M3 target? > > bagel > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From clattner at apple.com Sun Jul 18 14:52:34 2010 From: clattner at apple.com (Chris Lattner) Date: Sun, 18 Jul 2010 12:52:34 -0700 Subject: [llvm-commits] [llvm] r108639 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp In-Reply-To: References: <20100718084754.EB5022A6C12C@llvm.org> <9A1C9E46-38B4-4B1E-9B56-2DA374BF9E8A@apple.com> <15083EB0-FA01-4730-88DF-2B92CB0FB549@mac.com> <93873D0A-7686-47FD-8B2B-EEB48F83226D@mac.com> Message-ID: <74CCA0EE-E64A-4FD9-B697-CF4E6D2CE1C3@apple.com> On Jul 18, 2010, at 12:44 PM, Owen Anderson wrote: > > On Jul 18, 2010, at 12:04 PM, Chris Lattner wrote: >> I agree that the xform is correct. Why not do it on IR though? > > For the reasons I laid out in the earlier email, namely that it would require adding a sqrt() -> intrinsic transform at the IR level, which SelectionDAG is already doing, so it seemed like extraneous effort on the optimizer's part. If you really want, I can re-implement it as a SimplifyLibCalls+InstCombine xform, though. I would prefer for this to happen in InstCombiner::visitFPTrunc. Both because we already have the infrastructure to do this there, but also because your code only handles the -fno-math-errno case. Normal calls to libm sqrt should be transformed, not just llvm.sqrt. -Chris From isanbard at gmail.com Sun Jul 18 14:57:02 2010 From: isanbard at gmail.com (Bill Wendling) Date: Sun, 18 Jul 2010 12:57:02 -0700 Subject: [llvm-commits] [llvm] r108628 - /llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp In-Reply-To: <374B992E-A486-48B3-95E8-4B1DD4164E7E@apple.com> References: <20100717191844.AF3082A6C12C@llvm.org> <374B992E-A486-48B3-95E8-4B1DD4164E7E@apple.com> Message-ID: <611C44BD-D8B5-4B21-8147-CAFED3573A1A@gmail.com> The prolog is emitted with labels with or without the -g option. -bw On Jul 18, 2010, at 12:39 PM, Evan Cheng wrote: > Does this work if the code is compiled without -g? > > Evan > > On Jul 17, 2010, at 12:18 PM, Bill Wendling wrote: > >> Author: void >> Date: Sat Jul 17 14:18:44 2010 >> New Revision: 108628 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=108628&view=rev >> Log: >> Use isPrologLabel() instead of checking the opcode directly. >> >> Modified: >> llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp >> >> Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=108628&r1=108627&r2=108628&view=diff >> ============================================================================== >> --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original) >> +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Sat Jul 17 14:18:44 2010 >> @@ -661,7 +661,7 @@ >> // label equaling the end of function label and an invalid "row" in the >> // FDE. We need to emit a noop in this situation so that the FDE's rows are >> // valid. >> - bool RequiresNoop = LastMI && LastMI->getOpcode()==TargetOpcode::PROLOG_LABEL; >> + bool RequiresNoop = LastMI && LastMI->isPrologLabel(); >> >> // If the function is empty and the object file uses .subsections_via_symbols, >> // then we need to emit *something* to the function body to prevent the >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From resistor at mac.com Sun Jul 18 15:02:55 2010 From: resistor at mac.com (Owen Anderson) Date: Sun, 18 Jul 2010 13:02:55 -0700 Subject: [llvm-commits] [llvm] r108639 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp In-Reply-To: <74CCA0EE-E64A-4FD9-B697-CF4E6D2CE1C3@apple.com> References: <20100718084754.EB5022A6C12C@llvm.org> <9A1C9E46-38B4-4B1E-9B56-2DA374BF9E8A@apple.com> <15083EB0-FA01-4730-88DF-2B92CB0FB549@mac.com> <93873D0A-7686-47FD-8B2B-EEB48F83226D@mac.com> <74CCA0EE-E64A-4FD9-B697-CF4E6D2CE1C3@apple.com> Message-ID: <8E04AB0D-30A8-4A52-9D6B-3CB0F0FB3F96@mac.com> On Jul 18, 2010, at 12:52 PM, Chris Lattner wrote: > > I would prefer for this to happen in InstCombiner::visitFPTrunc. Both because we already have the infrastructure to do this there, but also because your code only handles the -fno-math-errno case. Normal calls to libm sqrt should be transformed, not just llvm.sqrt. Do we really want InstCombine assigning semantic value to random functions named sqrt()? I understand SimplifyLibCalls doing this, since it implicitly assumes that we're using libc, but I'm wary of making InstCombine assume it. --Owen From clattner at apple.com Sun Jul 18 15:12:57 2010 From: clattner at apple.com (Chris Lattner) Date: Sun, 18 Jul 2010 13:12:57 -0700 Subject: [llvm-commits] [llvm] r108639 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp In-Reply-To: <8E04AB0D-30A8-4A52-9D6B-3CB0F0FB3F96@mac.com> References: <20100718084754.EB5022A6C12C@llvm.org> <9A1C9E46-38B4-4B1E-9B56-2DA374BF9E8A@apple.com> <15083EB0-FA01-4730-88DF-2B92CB0FB549@mac.com> <93873D0A-7686-47FD-8B2B-EEB48F83226D@mac.com> <74CCA0EE-E64A-4FD9-B697-CF4E6D2CE1C3@apple.com> <8E04AB0D-30A8-4A52-9D6B-3CB0F0FB3F96@mac.com> Message-ID: <2AD332F8-BCA8-44CA-89B6-F957DE67F33E@apple.com> On Jul 18, 2010, at 1:02 PM, Owen Anderson wrote: On Jul 18, 2010, at 12:52 PM, Chris Lattner wrote: >> >> I would prefer for this to happen in InstCombiner::visitFPTrunc. Both because we already have the infrastructure to do this there, but also because your code only handles the -fno-math-errno case. Normal calls to libm sqrt should be transformed, not just llvm.sqrt. > > Do we really want InstCombine assigning semantic value to random functions named sqrt()? I understand SimplifyLibCalls doing this, since it implicitly assumes that we're using libc, but I'm wary of making InstCombine assume it. Yes we do. When/if we support -fno-builtin-sqrt, we will do this by adding a "not a builtin" function attribute, which optimizations like this should listen to. -Chris From daniel at zuster.org Sun Jul 18 15:15:59 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Sun, 18 Jul 2010 20:15:59 -0000 Subject: [llvm-commits] [llvm] r108655 - in /llvm/trunk: include/llvm/MC/MCParser/MCAsmParser.h lib/MC/MCParser/AsmParser.cpp lib/MC/MCParser/DarwinAsmParser.cpp test/MC/AsmParser/directive_abort.s Message-ID: <20100718201559.F0D9D2A6C12C@llvm.org> Author: ddunbar Date: Sun Jul 18 15:15:59 2010 New Revision: 108655 URL: http://llvm.org/viewvc/llvm-project?rev=108655&view=rev Log: MC/AsmParser: Fix .abort and .secure_log_unique to accept arbitrary token sequences, not just strings. Modified: llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h llvm/trunk/lib/MC/MCParser/AsmParser.cpp llvm/trunk/lib/MC/MCParser/DarwinAsmParser.cpp llvm/trunk/test/MC/AsmParser/directive_abort.s Modified: llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h?rev=108655&r1=108654&r2=108655&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h (original) +++ llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h Sun Jul 18 15:15:59 2010 @@ -89,6 +89,11 @@ /// and set \arg Res to the identifier contents. virtual bool ParseIdentifier(StringRef &Res) = 0; + /// \brief Parse up to the end of statement and return the contents from the + /// current token until the end of the statement; the current token on exit + /// will be either the EndOfStatement or EOF. + virtual StringRef ParseStringToEndOfStatement() = 0; + /// ParseExpression - Parse an arbitrary expression. /// /// @param Res - The value of the expression. The result is undefined Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=108655&r1=108654&r2=108655&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Sun Jul 18 15:15:59 2010 @@ -153,7 +153,12 @@ void JumpToLoc(SMLoc Loc); void EatToEndOfStatement(); - + + /// \brief Parse up to the end of statement and a return the contents from the + /// current token until the end of the statement; the current token on exit + /// will be either the EndOfStatement or EOF. + StringRef ParseStringToEndOfStatement(); + bool ParseAssignment(StringRef Name); bool ParsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc); @@ -387,6 +392,16 @@ Lex(); } +StringRef AsmParser::ParseStringToEndOfStatement() { + const char *Start = getTok().getLoc().getPointer(); + + while (Lexer.isNot(AsmToken::EndOfStatement) && + Lexer.isNot(AsmToken::Eof)) + Lex(); + + const char *End = getTok().getLoc().getPointer(); + return StringRef(Start, End - Start); +} /// ParseParenExpr - Parse a paren expression and return it. /// NOTE: This assumes the leading '(' has already been consumed. @@ -1561,31 +1576,22 @@ } /// ParseDirectiveAbort -/// ::= .abort [ "abort_string" ] +/// ::= .abort [... message ...] bool AsmParser::ParseDirectiveAbort() { // FIXME: Use loc from directive. SMLoc Loc = getLexer().getLoc(); - StringRef Str = ""; - if (getLexer().isNot(AsmToken::EndOfStatement)) { - if (getLexer().isNot(AsmToken::String)) - return TokError("expected string in '.abort' directive"); - - Str = getTok().getString(); - - Lex(); - } - + StringRef Str = ParseStringToEndOfStatement(); if (getLexer().isNot(AsmToken::EndOfStatement)) return TokError("unexpected token in '.abort' directive"); - + Lex(); - // FIXME: Handle here. if (Str.empty()) Error(Loc, ".abort detected. Assembly stopping."); else Error(Loc, ".abort '" + Str + "' detected. Assembly stopping."); + // FIXME: Actually abort assembly here. return false; } Modified: llvm/trunk/lib/MC/MCParser/DarwinAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/DarwinAsmParser.cpp?rev=108655&r1=108654&r2=108655&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/DarwinAsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/DarwinAsmParser.cpp Sun Jul 18 15:15:59 2010 @@ -537,28 +537,22 @@ } /// ParseDirectiveSecureLogUnique -/// ::= .secure_log_unique "log message" +/// ::= .secure_log_unique ... message ... bool DarwinAsmParser::ParseDirectiveSecureLogUnique(StringRef, SMLoc IDLoc) { - std::string LogMessage; - - if (getLexer().isNot(AsmToken::String)) - LogMessage = ""; - else{ - LogMessage = getTok().getString(); - Lex(); - } - + StringRef LogMessage = getParser().ParseStringToEndOfStatement(); if (getLexer().isNot(AsmToken::EndOfStatement)) return TokError("unexpected token in '.secure_log_unique' directive"); if (getContext().getSecureLogUsed() != false) return Error(IDLoc, ".secure_log_unique specified multiple times"); - char *SecureLogFile = getContext().getSecureLogFile(); + // Get the secure log path. + const char *SecureLogFile = getContext().getSecureLogFile(); if (SecureLogFile == NULL) return Error(IDLoc, ".secure_log_unique used but AS_SECURE_LOG_FILE " "environment variable unset."); + // Open the secure log file if we haven't already. raw_ostream *OS = getContext().getSecureLog(); if (OS == NULL) { std::string Err; @@ -571,6 +565,7 @@ getContext().setSecureLog(OS); } + // Write the message. int CurBuf = getSourceManager().FindBufferContainingLoc(IDLoc); *OS << getSourceManager().getBufferInfo(CurBuf).Buffer->getBufferIdentifier() << ":" << getSourceManager().FindLineNumber(IDLoc, CurBuf) << ":" Modified: llvm/trunk/test/MC/AsmParser/directive_abort.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/directive_abort.s?rev=108655&r1=108654&r2=108655&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/directive_abort.s (original) +++ llvm/trunk/test/MC/AsmParser/directive_abort.s Sun Jul 18 15:15:59 2010 @@ -1,6 +1,6 @@ # RUN: llvm-mc -triple i386-unknown-unknown %s 2> %t # RUN: FileCheck -input-file %t %s -# CHECK: .abort "please stop assembing" -TEST0: - .abort "please stop assembing" +# CHECK: error: .abort 'please stop assembing' +TEST0: + .abort please stop assembing From daniel at zuster.org Sun Jul 18 16:16:10 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Sun, 18 Jul 2010 21:16:10 -0000 Subject: [llvm-commits] [llvm] r108658 - in /llvm/trunk/test/MC/AsmParser: macros-parsing.s macros.s Message-ID: <20100718211610.CE5D12A6C12C@llvm.org> Author: ddunbar Date: Sun Jul 18 16:16:10 2010 New Revision: 108658 URL: http://llvm.org/viewvc/llvm-project?rev=108658&view=rev Log: tests: Force triples. Modified: llvm/trunk/test/MC/AsmParser/macros-parsing.s llvm/trunk/test/MC/AsmParser/macros.s Modified: llvm/trunk/test/MC/AsmParser/macros-parsing.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/macros-parsing.s?rev=108658&r1=108657&r2=108658&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/macros-parsing.s (original) +++ llvm/trunk/test/MC/AsmParser/macros-parsing.s Sun Jul 18 16:16:10 2010 @@ -1,4 +1,4 @@ -// RUN: not llvm-mc %s 2> %t.err +// RUN: not llvm-mc -triple x86_64-apple-darwin10 %s 2> %t.err // RUN: FileCheck --check-prefix=CHECK-ERRORS %s < %t.err .macro .test0 Modified: llvm/trunk/test/MC/AsmParser/macros.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/macros.s?rev=108658&r1=108657&r2=108658&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/macros.s (original) +++ llvm/trunk/test/MC/AsmParser/macros.s Sun Jul 18 16:16:10 2010 @@ -1,4 +1,4 @@ -// RUN: llvm-mc %s 2> %t.err | FileCheck %s +// RUN: llvm-mc -triple x86_64-apple-darwin10 %s 2> %t.err | FileCheck %s // RUN: FileCheck --check-prefix=CHECK-ERRORS %s < %t.err .macro .test0 From daniel at zuster.org Sun Jul 18 17:22:07 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Sun, 18 Jul 2010 22:22:07 -0000 Subject: [llvm-commits] [llvm] r108661 - in /llvm/trunk: include/llvm/MC/MCParser/MCAsmParser.h include/llvm/MC/MCParser/MCAsmParserExtension.h lib/MC/MCParser/AsmParser.cpp lib/MC/MCParser/DarwinAsmParser.cpp lib/MC/MCParser/ELFAsmParser.cpp Message-ID: <20100718222207.F172C2A6C12C@llvm.org> Author: ddunbar Date: Sun Jul 18 17:22:07 2010 New Revision: 108661 URL: http://llvm.org/viewvc/llvm-project?rev=108661&view=rev Log: MC/AsmParser: Stop playing unsafe member function pointer calls, this isn't portable enough. - Downside is we now double dispatch through a stub function, but this isn't performance critical. Modified: llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h llvm/trunk/include/llvm/MC/MCParser/MCAsmParserExtension.h llvm/trunk/lib/MC/MCParser/AsmParser.cpp llvm/trunk/lib/MC/MCParser/DarwinAsmParser.cpp llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp Modified: llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h?rev=108661&r1=108660&r2=108661&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h (original) +++ llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h Sun Jul 18 17:22:07 2010 @@ -31,7 +31,7 @@ /// assembly parsers. class MCAsmParser { public: - typedef bool (MCAsmParserExtension::*DirectiveHandler)(StringRef, SMLoc); + typedef bool (*DirectiveHandler)(MCAsmParserExtension*, StringRef, SMLoc); private: MCAsmParser(const MCAsmParser &); // DO NOT IMPLEMENT Modified: llvm/trunk/include/llvm/MC/MCParser/MCAsmParserExtension.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/MCAsmParserExtension.h?rev=108661&r1=108660&r2=108661&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCParser/MCAsmParserExtension.h (original) +++ llvm/trunk/include/llvm/MC/MCParser/MCAsmParserExtension.h Sun Jul 18 17:22:07 2010 @@ -11,6 +11,7 @@ #define LLVM_MC_MCASMPARSEREXTENSION_H #include "llvm/MC/MCParser/MCAsmParser.h" +#include "llvm/ADT/StringRef.h" #include "llvm/Support/SMLoc.h" namespace llvm { @@ -28,6 +29,15 @@ protected: MCAsmParserExtension(); + // Helper template for implementing static dispatch functions. + template + static bool HandleDirective(MCAsmParserExtension *Target, + StringRef Directive, + SMLoc DirectiveLoc) { + T *Obj = static_cast(Target); + return (Obj->*Handler)(Directive, DirectiveLoc); + } + public: virtual ~MCAsmParserExtension(); Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=108661&r1=108660&r2=108661&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Sun Jul 18 17:22:07 2010 @@ -202,6 +202,12 @@ /// \brief Generic implementations of directive handling, etc. which is shared /// (or the default, at least) for all assembler parser. class GenericAsmParser : public MCAsmParserExtension { + template + void AddDirectiveHandler(StringRef Directive) { + getParser().AddDirectiveHandler(this, Directive, + HandleDirective); + } + public: GenericAsmParser() {} @@ -214,26 +220,18 @@ this->MCAsmParserExtension::Initialize(Parser); // Debugging directives. - Parser.AddDirectiveHandler(this, ".file", MCAsmParser::DirectiveHandler( - &GenericAsmParser::ParseDirectiveFile)); - Parser.AddDirectiveHandler(this, ".line", MCAsmParser::DirectiveHandler( - &GenericAsmParser::ParseDirectiveLine)); - Parser.AddDirectiveHandler(this, ".loc", MCAsmParser::DirectiveHandler( - &GenericAsmParser::ParseDirectiveLoc)); + AddDirectiveHandler<&GenericAsmParser::ParseDirectiveFile>(".file"); + AddDirectiveHandler<&GenericAsmParser::ParseDirectiveLine>(".line"); + AddDirectiveHandler<&GenericAsmParser::ParseDirectiveLoc>(".loc"); // Macro directives. - Parser.AddDirectiveHandler(this, ".macros_on", - MCAsmParser::DirectiveHandler( - &GenericAsmParser::ParseDirectiveMacrosOnOff)); - Parser.AddDirectiveHandler(this, ".macros_off", - MCAsmParser::DirectiveHandler( - &GenericAsmParser::ParseDirectiveMacrosOnOff)); - Parser.AddDirectiveHandler(this, ".macro", MCAsmParser::DirectiveHandler( - &GenericAsmParser::ParseDirectiveMacro)); - Parser.AddDirectiveHandler(this, ".endm", MCAsmParser::DirectiveHandler( - &GenericAsmParser::ParseDirectiveEndMacro)); - Parser.AddDirectiveHandler(this, ".endmacro", MCAsmParser::DirectiveHandler( - &GenericAsmParser::ParseDirectiveEndMacro)); + AddDirectiveHandler<&GenericAsmParser::ParseDirectiveMacrosOnOff>( + ".macros_on"); + AddDirectiveHandler<&GenericAsmParser::ParseDirectiveMacrosOnOff>( + ".macros_off"); + AddDirectiveHandler<&GenericAsmParser::ParseDirectiveMacro>(".macro"); + AddDirectiveHandler<&GenericAsmParser::ParseDirectiveEndMacro>(".endm"); + AddDirectiveHandler<&GenericAsmParser::ParseDirectiveEndMacro>(".endmacro"); } bool ParseDirectiveFile(StringRef, SMLoc DirectiveLoc); @@ -875,7 +873,7 @@ std::pair Handler = DirectiveMap.lookup(IDVal); if (Handler.first) - return (Handler.first->*Handler.second)(IDVal, IDLoc); + return (*Handler.second)(Handler.first, IDVal, IDLoc); // Target hook for parsing target specific directives. if (!getTargetParser().ParseDirective(ID)) Modified: llvm/trunk/lib/MC/MCParser/DarwinAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/DarwinAsmParser.cpp?rev=108661&r1=108660&r2=108661&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/DarwinAsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/DarwinAsmParser.cpp Sun Jul 18 17:22:07 2010 @@ -25,6 +25,12 @@ /// \brief Implementation of directive handling which is shared across all /// Darwin targets. class DarwinAsmParser : public MCAsmParserExtension { + template + void AddDirectiveHandler(StringRef Directive) { + getParser().AddDirectiveHandler(this, Directive, + HandleDirective); + } + bool ParseSectionSwitch(const char *Segment, const char *Section, unsigned TAA = 0, unsigned ImplicitAlign = 0, unsigned StubSize = 0); @@ -36,168 +42,70 @@ // Call the base implementation. this->MCAsmParserExtension::Initialize(Parser); - Parser.AddDirectiveHandler(this, ".desc", MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseDirectiveDesc)); - Parser.AddDirectiveHandler(this, ".lsym", MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseDirectiveLsym)); - Parser.AddDirectiveHandler(this, ".subsections_via_symbols", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseDirectiveSubsectionsViaSymbols)); - Parser.AddDirectiveHandler(this, ".dump", MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseDirectiveDumpOrLoad)); - Parser.AddDirectiveHandler(this, ".load", MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseDirectiveDumpOrLoad)); - Parser.AddDirectiveHandler(this, ".section", MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseDirectiveSection)); - Parser.AddDirectiveHandler(this, ".secure_log_unique", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseDirectiveSecureLogUnique)); - Parser.AddDirectiveHandler(this, ".secure_log_reset", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseDirectiveSecureLogReset)); - Parser.AddDirectiveHandler(this, ".tbss", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseDirectiveTBSS)); - Parser.AddDirectiveHandler(this, ".zerofill", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseDirectiveZerofill)); + AddDirectiveHandler<&DarwinAsmParser::ParseDirectiveDesc>(".desc"); + AddDirectiveHandler<&DarwinAsmParser::ParseDirectiveLsym>(".lsym"); + AddDirectiveHandler<&DarwinAsmParser::ParseDirectiveSubsectionsViaSymbols>( + ".subsections_via_symbols"); + AddDirectiveHandler<&DarwinAsmParser::ParseDirectiveDumpOrLoad>(".dump"); + AddDirectiveHandler<&DarwinAsmParser::ParseDirectiveDumpOrLoad>(".load"); + AddDirectiveHandler<&DarwinAsmParser::ParseDirectiveSection>(".section"); + AddDirectiveHandler<&DarwinAsmParser::ParseDirectiveSecureLogUnique>( + ".secure_log_unique"); + AddDirectiveHandler<&DarwinAsmParser::ParseDirectiveSecureLogReset>( + ".secure_log_reset"); + AddDirectiveHandler<&DarwinAsmParser::ParseDirectiveTBSS>(".tbss"); + AddDirectiveHandler<&DarwinAsmParser::ParseDirectiveZerofill>(".zerofill"); // Special section directives. - Parser.AddDirectiveHandler(this, ".const", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveConst)); - Parser.AddDirectiveHandler(this, ".const_data", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveConstData)); - Parser.AddDirectiveHandler(this, ".constructor", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveConstructor)); - Parser.AddDirectiveHandler(this, ".cstring", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveCString)); - Parser.AddDirectiveHandler(this, ".data", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveData)); - Parser.AddDirectiveHandler(this, ".destructor", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveDestructor)); - Parser.AddDirectiveHandler(this, ".dyld", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveDyld)); - Parser.AddDirectiveHandler(this, ".fvmlib_init0", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveFVMLibInit0)); - Parser.AddDirectiveHandler(this, ".fvmlib_init1", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveFVMLibInit1)); - Parser.AddDirectiveHandler(this, ".lazy_symbol_pointer", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveLazySymbolPointers)); - Parser.AddDirectiveHandler(this, ".literal16", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveLiteral16)); - Parser.AddDirectiveHandler(this, ".literal4", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveLiteral4)); - Parser.AddDirectiveHandler(this, ".literal8", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveLiteral8)); - Parser.AddDirectiveHandler(this, ".mod_init_func", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveModInitFunc)); - Parser.AddDirectiveHandler(this, ".mod_term_func", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveModTermFunc)); - Parser.AddDirectiveHandler(this, ".non_lazy_symbol_pointer", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveNonLazySymbolPointers)); - Parser.AddDirectiveHandler(this, ".objc_cat_cls_meth", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveObjCCatClsMeth)); - Parser.AddDirectiveHandler(this, ".objc_cat_inst_meth", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveObjCCatInstMeth)); - Parser.AddDirectiveHandler(this, ".objc_category", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveObjCCategory)); - Parser.AddDirectiveHandler(this, ".objc_class", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveObjCClass)); - Parser.AddDirectiveHandler(this, ".objc_class_names", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveObjCClassNames)); - Parser.AddDirectiveHandler(this, ".objc_class_vars", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveObjCClassVars)); - Parser.AddDirectiveHandler(this, ".objc_cls_meth", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveObjCClsMeth)); - Parser.AddDirectiveHandler(this, ".objc_cls_refs", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveObjCClsRefs)); - Parser.AddDirectiveHandler(this, ".objc_inst_meth", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveObjCInstMeth)); - Parser.AddDirectiveHandler(this, ".objc_instance_vars", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveObjCInstanceVars)); - Parser.AddDirectiveHandler(this, ".objc_message_refs", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveObjCMessageRefs)); - Parser.AddDirectiveHandler(this, ".objc_meta_class", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveObjCMetaClass)); - Parser.AddDirectiveHandler(this, ".objc_meth_var_names", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveObjCMethVarNames)); - Parser.AddDirectiveHandler(this, ".objc_meth_var_types", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveObjCMethVarTypes)); - Parser.AddDirectiveHandler(this, ".objc_module_info", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveObjCModuleInfo)); - Parser.AddDirectiveHandler(this, ".objc_protocol", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveObjCProtocol)); - Parser.AddDirectiveHandler(this, ".objc_selector_strs", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveObjCSelectorStrs)); - Parser.AddDirectiveHandler(this, ".objc_string_object", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveObjCStringObject)); - Parser.AddDirectiveHandler(this, ".objc_symbols", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveObjCSymbols)); - Parser.AddDirectiveHandler(this, ".picsymbol_stub", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectivePICSymbolStub)); - Parser.AddDirectiveHandler(this, ".static_const", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveStaticConst)); - Parser.AddDirectiveHandler(this, ".static_data", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveStaticData)); - Parser.AddDirectiveHandler(this, ".symbol_stub", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveSymbolStub)); - Parser.AddDirectiveHandler(this, ".tdata", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveTData)); - Parser.AddDirectiveHandler(this, ".text", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveText)); - Parser.AddDirectiveHandler(this, ".thread_init_func", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveThreadInitFunc)); - Parser.AddDirectiveHandler(this, ".tlv", - MCAsmParser::DirectiveHandler( - &DarwinAsmParser::ParseSectionDirectiveTLV)); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveConst>(".const"); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveConstData>(".const_data"); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveConstructor>(".constructor"); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveCString>(".cstring"); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveData>(".data"); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveDestructor>(".destructor"); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveDyld>(".dyld"); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveFVMLibInit0>(".fvmlib_init0"); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveFVMLibInit1>(".fvmlib_init1"); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveLazySymbolPointers>(".lazy_symbol_pointer"); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveLiteral16>(".literal16"); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveLiteral4>(".literal4"); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveLiteral8>(".literal8"); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveModInitFunc>(".mod_init_func"); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveModTermFunc>(".mod_term_func"); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveNonLazySymbolPointers>(".non_lazy_symbol_pointer"); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveObjCCatClsMeth>(".objc_cat_cls_meth"); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveObjCCatInstMeth>(".objc_cat_inst_meth"); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveObjCCategory>(".objc_category"); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveObjCClass>(".objc_class"); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveObjCClassNames>(".objc_class_names"); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveObjCClassVars>(".objc_class_vars"); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveObjCClsMeth>(".objc_cls_meth"); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveObjCClsRefs>(".objc_cls_refs"); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveObjCInstMeth>(".objc_inst_meth"); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveObjCInstanceVars>(".objc_instance_vars"); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveObjCMessageRefs>(".objc_message_refs"); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveObjCMetaClass>(".objc_meta_class"); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveObjCMethVarNames>(".objc_meth_var_names"); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveObjCMethVarTypes>(".objc_meth_var_types"); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveObjCModuleInfo>(".objc_module_info"); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveObjCProtocol>(".objc_protocol"); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveObjCSelectorStrs>(".objc_selector_strs"); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveObjCStringObject>(".objc_string_object"); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveObjCSymbols>(".objc_symbols"); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectivePICSymbolStub>(".picsymbol_stub"); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveStaticConst>(".static_const"); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveStaticData>(".static_data"); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveSymbolStub>(".symbol_stub"); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveTData>(".tdata"); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveText>(".text"); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveThreadInitFunc>(".thread_init_func"); + AddDirectiveHandler<&DarwinAsmParser::ParseSectionDirectiveTLV>(".tlv"); } bool ParseDirectiveDesc(StringRef, SMLoc); bool ParseDirectiveDumpOrLoad(StringRef, SMLoc); bool ParseDirectiveLsym(StringRef, SMLoc); - bool ParseDirectiveSection(); + bool ParseDirectiveSection(StringRef, SMLoc); bool ParseDirectiveSecureLogReset(StringRef, SMLoc); bool ParseDirectiveSecureLogUnique(StringRef, SMLoc); bool ParseDirectiveSubsectionsViaSymbols(StringRef, SMLoc); @@ -493,7 +401,7 @@ /// ParseDirectiveSection: /// ::= .section identifier (',' identifier)* -bool DarwinAsmParser::ParseDirectiveSection() { +bool DarwinAsmParser::ParseDirectiveSection(StringRef, SMLoc) { SMLoc Loc = getLexer().getLoc(); StringRef SectionName; Modified: llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp?rev=108661&r1=108660&r2=108661&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp Sun Jul 18 17:22:07 2010 @@ -20,6 +20,12 @@ namespace { class ELFAsmParser : public MCAsmParserExtension { + template + void AddDirectiveHandler(StringRef Directive) { + getParser().AddDirectiveHandler(this, Directive, + HandleDirective); + } + bool ParseSectionSwitch(StringRef Section, unsigned Type, unsigned Flags, SectionKind Kind); @@ -30,18 +36,12 @@ // Call the base implementation. this->MCAsmParserExtension::Initialize(Parser); - Parser.AddDirectiveHandler(this, ".data", MCAsmParser::DirectiveHandler( - &ELFAsmParser::ParseSectionDirectiveData)); - Parser.AddDirectiveHandler(this, ".text", MCAsmParser::DirectiveHandler( - &ELFAsmParser::ParseSectionDirectiveText)); - Parser.AddDirectiveHandler(this, ".section", MCAsmParser::DirectiveHandler( - &ELFAsmParser::ParseDirectiveSection)); - Parser.AddDirectiveHandler(this, ".size", MCAsmParser::DirectiveHandler( - &ELFAsmParser::ParseDirectiveSize)); - Parser.AddDirectiveHandler(this, ".sleb128", MCAsmParser::DirectiveHandler( - &ELFAsmParser::ParseDirectiveLEB128)); - Parser.AddDirectiveHandler(this, ".uleb128", MCAsmParser::DirectiveHandler( - &ELFAsmParser::ParseDirectiveLEB128)); + AddDirectiveHandler<&ELFAsmParser::ParseSectionDirectiveData>(".data"); + AddDirectiveHandler<&ELFAsmParser::ParseSectionDirectiveText>(".text"); + AddDirectiveHandler<&ELFAsmParser::ParseDirectiveSection>(".section"); + AddDirectiveHandler<&ELFAsmParser::ParseDirectiveSize>(".size"); + AddDirectiveHandler<&ELFAsmParser::ParseDirectiveLEB128>(".sleb128"); + AddDirectiveHandler<&ELFAsmParser::ParseDirectiveLEB128>(".uleb128"); } bool ParseSectionDirectiveData(StringRef, SMLoc) { From bigcheesegs at gmail.com Sun Jul 18 18:46:13 2010 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Sun, 18 Jul 2010 23:46:13 -0000 Subject: [llvm-commits] [llvm] r108662 - /llvm/trunk/CREDITS.TXT Message-ID: <20100718234613.5B46C2A6C12C@llvm.org> Author: mspencer Date: Sun Jul 18 18:46:13 2010 New Revision: 108662 URL: http://llvm.org/viewvc/llvm-project?rev=108662&view=rev Log: Test commit Modified: llvm/trunk/CREDITS.TXT Modified: llvm/trunk/CREDITS.TXT URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CREDITS.TXT?rev=108662&r1=108661&r2=108662&view=diff ============================================================================== --- llvm/trunk/CREDITS.TXT (original) +++ llvm/trunk/CREDITS.TXT Sun Jul 18 18:46:13 2010 @@ -340,3 +340,7 @@ E: peckw at wesleypeck.com W: http://wesleypeck.com/ D: MicroBlaze backend + +N: Michael J. Spencer +E: bigcheesegs at gmail.com +D: Shepherding Windows COFF support into MC. From daniel at zuster.org Sun Jul 18 19:33:43 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 19 Jul 2010 00:33:43 -0000 Subject: [llvm-commits] [llvm] r108663 - in /llvm/trunk/tools/edis: EDDisassembler.cpp EDDisassembler.h Message-ID: <20100719003343.5692C2A6C12C@llvm.org> Author: ddunbar Date: Sun Jul 18 19:33:43 2010 New Revision: 108663 URL: http://llvm.org/viewvc/llvm-project?rev=108663&view=rev Log: edis: Save the TargetMachine in the EDDisassembler object. Modified: llvm/trunk/tools/edis/EDDisassembler.cpp llvm/trunk/tools/edis/EDDisassembler.h Modified: llvm/trunk/tools/edis/EDDisassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/edis/EDDisassembler.cpp?rev=108663&r1=108662&r2=108663&view=diff ============================================================================== --- llvm/trunk/tools/edis/EDDisassembler.cpp (original) +++ llvm/trunk/tools/edis/EDDisassembler.cpp Sun Jul 18 19:33:43 2010 @@ -175,11 +175,10 @@ std::string featureString; - OwningPtr - targetMachine(Tgt->createTargetMachine(tripleString, - featureString)); + TargetMachine.reset(Tgt->createTargetMachine(tripleString, + featureString)); - const TargetRegisterInfo *registerInfo = targetMachine->getRegisterInfo(); + const TargetRegisterInfo *registerInfo = TargetMachine->getRegisterInfo(); if (!registerInfo) return; @@ -209,7 +208,7 @@ SpecificAsmLexer.reset(Tgt->createAsmLexer(*AsmInfo)); SpecificAsmLexer->InstallLexer(*GenericAsmLexer); - initMaps(*targetMachine->getRegisterInfo()); + initMaps(*TargetMachine->getRegisterInfo()); Valid = true; } Modified: llvm/trunk/tools/edis/EDDisassembler.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/edis/EDDisassembler.h?rev=108663&r1=108662&r2=108663&view=diff ============================================================================== --- llvm/trunk/tools/edis/EDDisassembler.h (original) +++ llvm/trunk/tools/edis/EDDisassembler.h Sun Jul 18 19:33:43 2010 @@ -47,6 +47,7 @@ template class SmallVectorImpl; class SourceMgr; class Target; +class TargetMachine; class TargetRegisterInfo; struct EDInstInfo; @@ -127,6 +128,8 @@ CPUKey Key; /// The LLVM target corresponding to the disassembler const llvm::Target *Tgt; + /// The target machien instance. + llvm::OwningPtr TargetMachine; /// The assembly information for the target architecture llvm::OwningPtr AsmInfo; /// The disassembler for the target architecture From daniel at zuster.org Sun Jul 18 19:33:49 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 19 Jul 2010 00:33:49 -0000 Subject: [llvm-commits] [llvm] r108664 - in /llvm/trunk: include/llvm/Target/TargetRegistry.h lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp lib/Target/ARM/AsmParser/ARMAsmParser.cpp lib/Target/X86/AsmParser/X86AsmParser.cpp tools/edis/EDDisassembler.cpp tools/llvm-mc/llvm-mc.cpp Message-ID: <20100719003349.9799A2A6C12D@llvm.org> Author: ddunbar Date: Sun Jul 18 19:33:49 2010 New Revision: 108664 URL: http://llvm.org/viewvc/llvm-project?rev=108664&view=rev Log: Target: Give the TargetAsmParser access to the TargetMachine. - Unfortunate, but necessary for now to handle subtarget instruction matching. Eventually we should factor out the lower level target machine information so we don't need to do this. Modified: llvm/trunk/include/llvm/Target/TargetRegistry.h llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/tools/edis/EDDisassembler.cpp llvm/trunk/tools/llvm-mc/llvm-mc.cpp Modified: llvm/trunk/include/llvm/Target/TargetRegistry.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegistry.h?rev=108664&r1=108663&r2=108664&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetRegistry.h (original) +++ llvm/trunk/include/llvm/Target/TargetRegistry.h Sun Jul 18 19:33:49 2010 @@ -65,7 +65,8 @@ const std::string &TT); typedef TargetAsmLexer *(*AsmLexerCtorTy)(const Target &T, const MCAsmInfo &MAI); - typedef TargetAsmParser *(*AsmParserCtorTy)(const Target &T,MCAsmParser &P); + typedef TargetAsmParser *(*AsmParserCtorTy)(const Target &T,MCAsmParser &P, + TargetMachine &TM); typedef MCDisassembler *(*MCDisassemblerCtorTy)(const Target &T); typedef MCInstPrinter *(*MCInstPrinterCtorTy)(const Target &T, unsigned SyntaxVariant, @@ -237,10 +238,11 @@ /// /// \arg Parser - The target independent parser implementation to use for /// parsing and lexing. - TargetAsmParser *createAsmParser(MCAsmParser &Parser) const { + TargetAsmParser *createAsmParser(MCAsmParser &Parser, + TargetMachine &TM) const { if (!AsmParserCtorFn) return 0; - return AsmParserCtorFn(*this, Parser); + return AsmParserCtorFn(*this, Parser, TM); } /// createAsmPrinter - Create a target specific assembly printer pass. This @@ -667,8 +669,9 @@ } private: - static TargetAsmParser *Allocator(const Target &T, MCAsmParser &P) { - return new AsmParserImpl(T, P); + static TargetAsmParser *Allocator(const Target &T, MCAsmParser &P, + TargetMachine &TM) { + return new AsmParserImpl(T, P, TM); } }; Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp?rev=108664&r1=108663&r2=108664&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp Sun Jul 18 19:33:49 2010 @@ -74,7 +74,7 @@ OwningPtr Parser(createMCAsmParser(TM.getTarget(), SrcMgr, OutContext, OutStreamer, *MAI)); - OwningPtr TAP(TM.getTarget().createAsmParser(*Parser)); + OwningPtr TAP(TM.getTarget().createAsmParser(*Parser, TM)); if (!TAP) report_fatal_error("Inline asm not supported by this streamer because" " we don't have an asm parser for this target\n"); Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=108664&r1=108663&r2=108664&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Sun Jul 18 19:33:49 2010 @@ -37,6 +37,7 @@ class ARMAsmParser : public TargetAsmParser { MCAsmParser &Parser; + TargetMachine &TM; private: MCAsmParser &getParser() const { return Parser; } @@ -94,8 +95,8 @@ public: - ARMAsmParser(const Target &T, MCAsmParser &_Parser) - : TargetAsmParser(T), Parser(_Parser) {} + ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM) + : TargetAsmParser(T), Parser(_Parser), TM(_TM) {} virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc, SmallVectorImpl &Operands); Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=108664&r1=108663&r2=108664&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Sun Jul 18 19:33:49 2010 @@ -28,6 +28,7 @@ class X86ATTAsmParser : public TargetAsmParser { MCAsmParser &Parser; + TargetMachine &TM; protected: unsigned Is64Bit : 1; @@ -62,8 +63,8 @@ /// } public: - X86ATTAsmParser(const Target &T, MCAsmParser &_Parser) - : TargetAsmParser(T), Parser(_Parser) {} + X86ATTAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &TM) + : TargetAsmParser(T), Parser(_Parser), TM(TM) {} virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc, SmallVectorImpl &Operands); @@ -73,16 +74,16 @@ class X86_32ATTAsmParser : public X86ATTAsmParser { public: - X86_32ATTAsmParser(const Target &T, MCAsmParser &_Parser) - : X86ATTAsmParser(T, _Parser) { + X86_32ATTAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &TM) + : X86ATTAsmParser(T, _Parser, TM) { Is64Bit = false; } }; class X86_64ATTAsmParser : public X86ATTAsmParser { public: - X86_64ATTAsmParser(const Target &T, MCAsmParser &_Parser) - : X86ATTAsmParser(T, _Parser) { + X86_64ATTAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &TM) + : X86ATTAsmParser(T, _Parser, TM) { Is64Bit = true; } }; Modified: llvm/trunk/tools/edis/EDDisassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/edis/EDDisassembler.cpp?rev=108664&r1=108663&r2=108664&view=diff ============================================================================== --- llvm/trunk/tools/edis/EDDisassembler.cpp (original) +++ llvm/trunk/tools/edis/EDDisassembler.cpp Sun Jul 18 19:33:49 2010 @@ -365,7 +365,8 @@ OwningPtr genericParser(createMCAsmParser(*Tgt, sourceMgr, context, *streamer, *AsmInfo)); - OwningPtr TargetParser(Tgt->createAsmParser(*genericParser)); + OwningPtr TargetParser(Tgt->createAsmParser(*genericParser, + *TargetMachine)); AsmToken OpcodeToken = genericParser->Lex(); AsmToken NextToken = genericParser->Lex(); // consume next token, because specificParser expects us to Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=108664&r1=108663&r2=108664&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original) +++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Sun Jul 18 19:33:49 2010 @@ -314,7 +314,7 @@ OwningPtr Parser(createMCAsmParser(*TheTarget, SrcMgr, Ctx, *Str.get(), *MAI)); - OwningPtr TAP(TheTarget->createAsmParser(*Parser)); + OwningPtr TAP(TheTarget->createAsmParser(*Parser, *TM)); if (!TAP) { errs() << ProgName << ": error: this target does not support assembly parsing.\n"; From daniel at zuster.org Sun Jul 18 19:43:58 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 19 Jul 2010 00:43:58 -0000 Subject: [llvm-commits] [llvm] r108666 - /llvm/trunk/test/MC/AsmParser/macro-def-in-instantiation.s Message-ID: <20100719004358.83D5D2A6C12C@llvm.org> Author: ddunbar Date: Sun Jul 18 19:43:58 2010 New Revision: 108666 URL: http://llvm.org/viewvc/llvm-project?rev=108666&view=rev Log: tests: Force another triple. Modified: llvm/trunk/test/MC/AsmParser/macro-def-in-instantiation.s Modified: llvm/trunk/test/MC/AsmParser/macro-def-in-instantiation.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/macro-def-in-instantiation.s?rev=108666&r1=108665&r2=108666&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/macro-def-in-instantiation.s (original) +++ llvm/trunk/test/MC/AsmParser/macro-def-in-instantiation.s Sun Jul 18 19:43:58 2010 @@ -1,4 +1,4 @@ -// RUN: llvm-mc %s | FileCheck %s +// RUN: llvm-mc -triple x86_64-apple-darwin10 %s | FileCheck %s .macro .make_macro $0 $1 From stoklund at 2pi.dk Sun Jul 18 20:33:36 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Sun, 18 Jul 2010 18:33:36 -0700 Subject: [llvm-commits] [llvm] r108118 - /llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp In-Reply-To: References: <20100712014538.AC33A2A6C12C@llvm.org> Message-ID: On Jul 18, 2010, at 12:39 PM, Rafael Espindola wrote: > On 18 July 2010 05:09, Lang Hames wrote: >>> I think that the test for virtual registers is more strict than it needs >>> to be, >>> it should be possible to coalesce two virtual registers the class of one >>> is a subclass of the other. >> >> That certainly sounds safe if the destination class is a subclass of the >> source class. I assume going the other way is dangerous, in that it could >> leave junk in the non-aliased portion of the super-register? > > Note that this *subclass*, not *subregister". I don't think in general > it is safe to coalesce if the two classes have different value types > (which is an interesting limitation now that I think of it). It is. Value types are only used during instruction selection. They don't matter after that. The type-specific operations are encoded in the instructions, compare padd, addps, addpd. > Lets say we have two virtual registers V0 and V1. The first one is in > class S1 with physical registers R0, R1 and R2. The second one is in > class S2 with registers R0, R1 and R3. If we coalesce V0 and V1, what > physical registers can be used for the coalesced reg? R0 and R1. Right. We may