From anton at korobeynikov.info Mon Aug 30 01:09:10 2010 From: anton at korobeynikov.info (Anton Korobeynikov) Date: Mon, 30 Aug 2010 10:09:10 +0400 Subject: [llvm-commits] [PATCH] PR3897: suppress invoking __main() from JIT on Cygwin and Mingw In-Reply-To: References: Message-ID: Hello, Takumi > EE/JIT: We don't want to invoke parent's ctors/dtors from main(), to fix PR3897. Who and how will run them then? -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From nicholas at mxc.ca Mon Aug 30 01:48:24 2010 From: nicholas at mxc.ca (Nick Lewycky) Date: Sun, 29 Aug 2010 23:48:24 -0700 Subject: [llvm-commits] PATCH: add ContextualDenseMap In-Reply-To: <4C7686B5.7060605@mxc.ca> References: <4C7686B5.7060605@mxc.ca> Message-ID: <4C7B5438.3030203@mxc.ca> Ping! I've already ported MergeFunctions to use this, but I'd appreciate someone taking a look and making sure that the way I've factored them is sane (I did what FoldingSet / ContextualFoldingSet did). Nick Lewycky wrote: > This patch adds a new ContextualDenseMap and sinks most of the dense map > logic into DenseMapImpl. A ContextualDenseMap takes a > ContextualDenseMapInfo pointer instead of just a typename. I need this > for mergefuncs where I want a comparison operation that involves target > data. > > The four map info functions (getTombstoneKey, getEmptyKey, getHashValue > and isEqual) are made virtual in DenseMapImpl and then implemented once > in DenseMap and again in ContextualDenseMap. This implementation is > modelled after the relationship between ContextualFoldingSet and > FoldingSet. > > Please review! > > Nick > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From baldrick at free.fr Mon Aug 30 02:23:47 2010 From: baldrick at free.fr (Duncan Sands) Date: Mon, 30 Aug 2010 09:23:47 +0200 Subject: [llvm-commits] [llvm] r112420 - /llvm/trunk/include/llvm/Support/StandardPasses.h In-Reply-To: <185E017A-A97C-42D7-9F77-52F3E786972A@apple.com> References: <20100829070551.59E0E2A6C12C@llvm.org> <4C7A0B2D.8040806@free.fr> <185E017A-A97C-42D7-9F77-52F3E786972A@apple.com> Message-ID: <4C7B5C83.2060206@free.fr> Hi Chris, >>> I never got around to changing it to use the SSA updator. That >>> said, I could easily change it to not promote the alloca to a >>> register. Since it's only used if an exception is raised, that >>> wouldn't be a big loss. > > I took care of this. I need to refactor some code, but it's done. thanks for doing this. I would have done it somewhat differently; since you reverted your commit I will give my alternative approach a go (hopefully I will finish this on Wednesday). Ciao, Duncan. From chandlerc at gmail.com Mon Aug 30 02:25:54 2010 From: chandlerc at gmail.com (Chandler Carruth) Date: Mon, 30 Aug 2010 07:25:54 -0000 Subject: [llvm-commits] [llvm] r112464 - in /llvm/trunk: CMakeLists.txt cmake/modules/LLVMLibDeps.cmake Message-ID: <20100830072554.717142A6C12C@llvm.org> Author: chandlerc Date: Mon Aug 30 02:25:54 2010 New Revision: 112464 URL: http://llvm.org/viewvc/llvm-project?rev=112464&view=rev Log: Attempt to remove the MSIL backend from CMake as well based on Chris's r112375. Modified: llvm/trunk/CMakeLists.txt llvm/trunk/cmake/modules/LLVMLibDeps.cmake Modified: llvm/trunk/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CMakeLists.txt?rev=112464&r1=112463&r2=112464&view=diff ============================================================================== --- llvm/trunk/CMakeLists.txt (original) +++ llvm/trunk/CMakeLists.txt Mon Aug 30 02:25:54 2010 @@ -63,7 +63,6 @@ CppBackend Mips MBlaze - MSIL MSP430 PIC16 PowerPC Modified: llvm/trunk/cmake/modules/LLVMLibDeps.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/LLVMLibDeps.cmake?rev=112464&r1=112463&r2=112464&view=diff ============================================================================== --- llvm/trunk/cmake/modules/LLVMLibDeps.cmake (original) +++ llvm/trunk/cmake/modules/LLVMLibDeps.cmake Mon Aug 30 02:25:54 2010 @@ -33,10 +33,8 @@ set(MSVC_LIB_DEPS_LLVMMBlazeCodeGen LLVMCodeGen LLVMCore LLVMMBlazeInfo LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget) set(MSVC_LIB_DEPS_LLVMMBlazeInfo LLVMSupport) set(MSVC_LIB_DEPS_LLVMMC LLVMSupport LLVMSystem) -set(MSVC_LIB_DEPS_LLVMMCDisassembler LLVMARMAsmParser LLVMARMCodeGen LLVMARMInfo LLVMAlphaAsmPrinter LLVMAlphaCodeGen LLVMAlphaInfo LLVMBlackfinAsmPrinter LLVMBlackfinCodeGen LLVMBlackfinInfo LLVMCBackend LLVMCBackendInfo LLVMCellSPUAsmPrinter LLVMCellSPUCodeGen LLVMCellSPUInfo LLVMCppBackend LLVMCppBackendInfo LLVMMBlazeAsmPrinter LLVMMBlazeCodeGen LLVMMBlazeInfo LLVMMC LLVMMCParser LLVMMSIL LLVMMSILInfo LLVMMSP430AsmPrinter LLVMMSP430CodeGen LLVMMSP430Info LLVMMipsAsmPrinter LLVMMipsCodeGen LLVMMipsInfo LLVMPIC16AsmPrinter LLVMPIC16CodeGen LLVMPIC16Info LLVMPowerPCAsmPrinter LLVMPowerPCCodeGen LLVMPowerPCInfo LLVMSparcAsmPrinter LLVMSparcCodeGen LLVMSparcInfo LLVMSupport LLVMSystem LLVMSystemZAsmPrinter LLVMSystemZCodeGen LLVMSystemZInfo LLVMX86AsmParser LLVMX86CodeGen LLVMX86Disassembler LLVMX86Info LLVMXCoreAsmPrinter LLVMXCoreCodeGen LLVMXCoreInfo) +set(MSVC_LIB_DEPS_LLVMMCDisassembler LLVMARMAsmParser LLVMARMCodeGen LLVMARMInfo LLVMAlphaAsmPrinter LLVMAlphaCodeGen LLVMAlphaInfo LLVMBlackfinAsmPrinter LLVMBlackfinCodeGen LLVMBlackfinInfo LLVMCBackend LLVMCBackendInfo LLVMCellSPUAsmPrinter LLVMCellSPUCodeGen LLVMCellSPUInfo LLVMCppBackend LLVMCppBackendInfo LLVMMBlazeAsmPrinter LLVMMBlazeCodeGen LLVMMBlazeInfo LLVMMC LLVMMCParser LLVMMSP430AsmPrinter LLVMMSP430CodeGen LLVMMSP430Info LLVMMipsAsmPrinter LLVMMipsCodeGen LLVMMipsInfo LLVMPIC16AsmPrinter LLVMPIC16CodeGen LLVMPIC16Info LLVMPowerPCAsmPrinter LLVMPowerPCCodeGen LLVMPowerPCInfo LLVMSparcAsmPrinter LLVMSparcCodeGen LLVMSparcInfo LLVMSupport LLVMSystem LLVMSystemZAsmPrinter LLVMSystemZCodeGen LLVMSystemZInfo LLVMX86AsmParser LLVMX86CodeGen LLVMX86Disassembler LLVMX86Info LLVMXCoreAsmPrinter LLVMXCoreCodeGen LLVMXCoreInfo) set(MSVC_LIB_DEPS_LLVMMCParser LLVMMC LLVMSupport) -set(MSVC_LIB_DEPS_LLVMMSIL LLVMAnalysis LLVMCodeGen LLVMCore LLVMMSILInfo LLVMScalarOpts LLVMSupport LLVMTarget LLVMTransformUtils LLVMipa) -set(MSVC_LIB_DEPS_LLVMMSILInfo LLVMSupport) set(MSVC_LIB_DEPS_LLVMMSP430AsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMMSP430Info LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMMSP430CodeGen LLVMCodeGen LLVMCore LLVMMC LLVMMSP430Info LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget) set(MSVC_LIB_DEPS_LLVMMSP430Info LLVMSupport) From resistor at mac.com Mon Aug 30 02:33:39 2010 From: resistor at mac.com (Owen Anderson) Date: Mon, 30 Aug 2010 07:33:39 -0000 Subject: [llvm-commits] [llvm] r112465 - in /llvm/trunk/examples: Makefile TracingBrainF/ TracingBrainF/BrainF.h TracingBrainF/BrainFCodeGen.cpp TracingBrainF/BrainFInterpreter.cpp TracingBrainF/BrainFOpcodes.cpp TracingBrainF/BrainFTraceRecorder.cpp TracingBrainF/BrainFVM.h TracingBrainF/Makefile TracingBrainF/README Message-ID: <20100830073339.A1A352A6C12D@llvm.org> Author: resistor Date: Mon Aug 30 02:33:39 2010 New Revision: 112465 URL: http://llvm.org/viewvc/llvm-project?rev=112465&view=rev Log: Add a new example to the LLVM distribution: a trace-based Brainfuck compiler that uses LLVM as its code generator. Added: llvm/trunk/examples/TracingBrainF/ llvm/trunk/examples/TracingBrainF/BrainF.h llvm/trunk/examples/TracingBrainF/BrainFCodeGen.cpp llvm/trunk/examples/TracingBrainF/BrainFInterpreter.cpp llvm/trunk/examples/TracingBrainF/BrainFOpcodes.cpp llvm/trunk/examples/TracingBrainF/BrainFTraceRecorder.cpp llvm/trunk/examples/TracingBrainF/BrainFVM.h llvm/trunk/examples/TracingBrainF/Makefile llvm/trunk/examples/TracingBrainF/README Modified: llvm/trunk/examples/Makefile Modified: llvm/trunk/examples/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/Makefile?rev=112465&r1=112464&r2=112465&view=diff ============================================================================== --- llvm/trunk/examples/Makefile (original) +++ llvm/trunk/examples/Makefile Mon Aug 30 02:33:39 2010 @@ -10,7 +10,8 @@ include $(LEVEL)/Makefile.config -PARALLEL_DIRS:= BrainF Fibonacci HowToUseJIT Kaleidoscope ModuleMaker +PARALLEL_DIRS:= BrainF Fibonacci HowToUseJIT Kaleidoscope ModuleMaker \ + TracingBrainF ifeq ($(HAVE_PTHREAD),1) PARALLEL_DIRS += ParallelJIT Added: llvm/trunk/examples/TracingBrainF/BrainF.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/TracingBrainF/BrainF.h?rev=112465&view=auto ============================================================================== --- llvm/trunk/examples/TracingBrainF/BrainF.h (added) +++ llvm/trunk/examples/TracingBrainF/BrainF.h Mon Aug 30 02:33:39 2010 @@ -0,0 +1,77 @@ +//===-- BrainF.h - BrainF compiler class ----------------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===--------------------------------------------------------------------===// + +#ifndef BRAINF_H +#define BRAINF_H + +#include "llvm/LLVMContext.h" +#include "llvm/Module.h" +#include "llvm/ExecutionEngine/GenericValue.h" +#include "llvm/ExecutionEngine/JIT.h" +#include "llvm/PassManager.h" +#include "llvm/Support/IRBuilder.h" +#include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/DenseSet.h" + + +using namespace llvm; + +class BrainFTraceRecorder { + struct BrainFTraceNode { + uint8_t opcode; + size_t pc; + BrainFTraceNode(uint8_t o, size_t p) + : opcode(o), pc(p), left(0), right(0) { } + void dump(unsigned level); + + // On an if, left is the x != 0 edge. + // A value of 0 indicates an un-traced edge. + // A value of ~0ULL indicates an edge to the trace head. + BrainFTraceNode *left, *right; + }; + + uint8_t prev_opcode; + uint8_t *iteration_count; + std::pair *trace_begin, *trace_end, *trace_tail; + DenseMap trace_map; + Module *module; + BasicBlock *Header; + Value *DataPtr; + PHINode *HeaderPHI; + ExecutionEngine *EE; + + const IntegerType *int_type; + const FunctionType *op_type; + GlobalValue *bytecode_array, *executed_flag; + Value *getchar_func, *putchar_func; + FunctionPassManager *FPM; + + + void commit(); + void initialize_module(); + void compile(BrainFTraceNode* trace); + void compile_opcode(BrainFTraceNode *node, IRBuilder<>& builder); + void compile_plus(BrainFTraceNode *node, IRBuilder<>& builder); + void compile_minus(BrainFTraceNode *node, IRBuilder<>& builder); + void compile_left(BrainFTraceNode *node, IRBuilder<>& builder); + void compile_right(BrainFTraceNode *node, IRBuilder<>& builder); + void compile_put(BrainFTraceNode *node, IRBuilder<>& builder); + void compile_get(BrainFTraceNode *node, IRBuilder<>& builder); + void compile_if(BrainFTraceNode *node, IRBuilder<>& builder); + void compile_back(BrainFTraceNode *node, IRBuilder<>& builder); + +public: + BrainFTraceRecorder(); + ~BrainFTraceRecorder(); + + void record(size_t pc, uint8_t opcode); + void record_simple(size_t pc, uint8_t opcode); +}; + +#endif Added: llvm/trunk/examples/TracingBrainF/BrainFCodeGen.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/TracingBrainF/BrainFCodeGen.cpp?rev=112465&view=auto ============================================================================== --- llvm/trunk/examples/TracingBrainF/BrainFCodeGen.cpp (added) +++ llvm/trunk/examples/TracingBrainF/BrainFCodeGen.cpp Mon Aug 30 02:33:39 2010 @@ -0,0 +1,351 @@ +//===-- BrainFCodeGen.cpp - BrainF trace compiler -----------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===--------------------------------------------------------------------===// + +#include "BrainF.h" +#include "BrainFVM.h" +#include "llvm/Attributes.h" +#include "llvm/Support/StandardPasses.h" +#include "llvm/Target/TargetData.h" +#include "llvm/Target/TargetSelect.h" +#include "llvm/Transforms/Scalar.h" +#include "llvm/ADT/StringExtras.h" + +/// initialize_module - perform setup of the LLVM code generation system. +void BrainFTraceRecorder::initialize_module() { + LLVMContext &Context = module->getContext(); + + // Initialize the code generator, and enable aggressive code generation. + InitializeNativeTarget(); + EngineBuilder builder(module); + builder.setOptLevel(CodeGenOpt::Aggressive); + EE = builder.create(); + + // Create a FunctionPassManager to handle running optimization passes + // on our generated code. Setup a basic suite of optimizations for it. + FPM = new llvm::FunctionPassManager(module); + FPM->add(createInstructionCombiningPass()); + FPM->add(createCFGSimplificationPass()); + FPM->add(createScalarReplAggregatesPass()); + FPM->add(createSimplifyLibCallsPass()); + FPM->add(createInstructionCombiningPass()); + FPM->add(createJumpThreadingPass()); + FPM->add(createCFGSimplificationPass()); + FPM->add(createInstructionCombiningPass()); + FPM->add(createCFGSimplificationPass()); + FPM->add(createReassociatePass()); + FPM->add(createLoopRotatePass()); + FPM->add(createLICMPass()); + FPM->add(createLoopUnswitchPass(false)); + FPM->add(createInstructionCombiningPass()); + FPM->add(createIndVarSimplifyPass()); + FPM->add(createLoopDeletionPass()); + FPM->add(createLoopUnrollPass()); + FPM->add(createInstructionCombiningPass()); + FPM->add(createGVNPass()); + FPM->add(createSCCPPass()); + FPM->add(createInstructionCombiningPass()); + FPM->add(createJumpThreadingPass()); + FPM->add(createDeadStoreEliminationPass()); + FPM->add(createAggressiveDCEPass()); + FPM->add(createCFGSimplificationPass()); + + // Cache the LLVM type signature of an opcode function + int_type = sizeof(size_t) == 4 ? + IntegerType::getInt32Ty(Context) : + IntegerType::getInt64Ty(Context); + const Type *data_type = + PointerType::getUnqual(IntegerType::getInt8Ty(Context)); + std::vector args; + args.push_back(int_type); + args.push_back(data_type); + op_type = + FunctionType::get(Type::getVoidTy(Context), args, false); + + // Setup a global variable in the LLVM module to represent the bytecode + // array. Bind it to the actual bytecode array at JIT time. + const Type *bytecode_type = PointerType::getUnqual(op_type); + bytecode_array = cast(module-> + getOrInsertGlobal("BytecodeArray", bytecode_type)); + EE->addGlobalMapping(bytecode_array, BytecodeArray); + + // Setup a similar mapping for the global executed flag. + const IntegerType *flag_type = IntegerType::get(Context, 8); + executed_flag = + cast(module->getOrInsertGlobal("executed", flag_type)); + EE->addGlobalMapping(executed_flag, &executed); + + // Cache LLVM declarations for putchar() and getchar(). + const Type *int_type = sizeof(int) == 4 ? IntegerType::getInt32Ty(Context) + : IntegerType::getInt64Ty(Context); + putchar_func = + module->getOrInsertFunction("putchar", int_type, int_type, NULL); + getchar_func = module->getOrInsertFunction("getchar", int_type, NULL); +} + +void BrainFTraceRecorder::compile(BrainFTraceNode* trace) { + LLVMContext &Context = module->getContext(); + + // Create a new function for the trace we're compiling. + Function *curr_func = cast(module-> + getOrInsertFunction("trace_"+utostr(trace->pc), op_type)); + + // Create an entry block, which branches directly to a header block. + // This is necessary because the entry block cannot be the target of + // a loop. + BasicBlock *Entry = BasicBlock::Create(Context, "entry", curr_func); + Header = BasicBlock::Create(Context, utostr(trace->pc), curr_func); + + // Mark the array pointer as noalias, and setup compiler state. + IRBuilder<> builder(Entry); + Argument *Arg1 = ++curr_func->arg_begin(); + Arg1->addAttr(Attribute::NoAlias); + DataPtr = Arg1; + + // Emit code to set the executed flag. This signals to the recorder + // that the preceding opcode was executed as a part of a compiled trace. + const IntegerType *flag_type = IntegerType::get(Context, 8); + ConstantInt *True = ConstantInt::get(flag_type, 1); + builder.CreateStore(True, executed_flag); + builder.CreateBr(Header); + + // Header will be the root of our trace tree. As such, all loop back-edges + // will be targetting it. Setup a PHI node to merge together incoming values + // for the current array pointer as we loop. + builder.SetInsertPoint(Header); + HeaderPHI = builder.CreatePHI(DataPtr->getType()); + HeaderPHI->addIncoming(DataPtr, Entry); + DataPtr = HeaderPHI; + + // Recursively descend the trace tree, emitting code for the opcodes as we go. + compile_opcode(trace, builder); + + // Run out optimization suite on our newly generated trace. + FPM->run(*curr_func); + + // Compile our trace to machine code, and install function pointer to it + // into the bytecode array so that it will be executed every time the + // trace-head PC is reached. + void *code = EE->getPointerToFunction(curr_func); + BytecodeArray[trace->pc] = + (opcode_func_t)(intptr_t)code; +} + +/// compile_plus - Emit code for '+' +void BrainFTraceRecorder::compile_plus(BrainFTraceNode *node, + IRBuilder<>& builder) { + Value *CellValue = builder.CreateLoad(DataPtr); + Constant *One = + ConstantInt::get(IntegerType::getInt8Ty(Header->getContext()), 1); + Value *UpdatedValue = builder.CreateAdd(CellValue, One); + builder.CreateStore(UpdatedValue, DataPtr); + + if (node->left != (BrainFTraceNode*)~0ULL) + compile_opcode(node->left, builder); + else { + HeaderPHI->addIncoming(DataPtr, builder.GetInsertBlock()); + builder.CreateBr(Header); + } +} + +/// compile_minus - Emit code for '-' +void BrainFTraceRecorder::compile_minus(BrainFTraceNode *node, + IRBuilder<>& builder) { + Value *CellValue = builder.CreateLoad(DataPtr); + Constant *One = + ConstantInt::get(IntegerType::getInt8Ty(Header->getContext()), 1); + Value *UpdatedValue = builder.CreateSub(CellValue, One); + builder.CreateStore(UpdatedValue, DataPtr); + + if (node->left != (BrainFTraceNode*)~0ULL) + compile_opcode(node->left, builder); + else { + HeaderPHI->addIncoming(DataPtr, builder.GetInsertBlock()); + builder.CreateBr(Header); + } +} + +/// compile_left - Emit code for '<' +void BrainFTraceRecorder::compile_left(BrainFTraceNode *node, + IRBuilder<>& builder) { + Value *OldPtr = DataPtr; + DataPtr = builder.CreateConstInBoundsGEP1_32(DataPtr, -1); + if (node->left != (BrainFTraceNode*)~0ULL) + compile_opcode(node->left, builder); + else { + HeaderPHI->addIncoming(DataPtr, builder.GetInsertBlock()); + builder.CreateBr(Header); + } + DataPtr = OldPtr; +} + +/// compile_right - Emit code for '>' +void BrainFTraceRecorder::compile_right(BrainFTraceNode *node, + IRBuilder<>& builder) { + Value *OldPtr = DataPtr; + DataPtr = builder.CreateConstInBoundsGEP1_32(DataPtr, 1); + if (node->left != (BrainFTraceNode*)~0ULL) + compile_opcode(node->left, builder); + else { + HeaderPHI->addIncoming(DataPtr, builder.GetInsertBlock()); + builder.CreateBr(Header); + } + DataPtr = OldPtr; +} + + +/// compile_put - Emit code for '.' +void BrainFTraceRecorder::compile_put(BrainFTraceNode *node, + IRBuilder<>& builder) { + Value *Loaded = builder.CreateLoad(DataPtr); + Value *Print = + builder.CreateSExt(Loaded, IntegerType::get(Loaded->getContext(), 32)); + builder.CreateCall(putchar_func, Print); + if (node->left != (BrainFTraceNode*)~0ULL) + compile_opcode(node->left, builder); + else { + HeaderPHI->addIncoming(DataPtr, builder.GetInsertBlock()); + builder.CreateBr(Header); + } +} + +/// compile_get - Emit code for ',' +void BrainFTraceRecorder::compile_get(BrainFTraceNode *node, + IRBuilder<>& builder) { + Value *Ret = builder.CreateCall(getchar_func); + Value *Trunc = + builder.CreateTrunc(Ret, IntegerType::get(Ret->getContext(), 8)); + builder.CreateStore(Ret, Trunc); + if (node->left != (BrainFTraceNode*)~0ULL) + compile_opcode(node->left, builder); + else { + HeaderPHI->addIncoming(DataPtr, builder.GetInsertBlock()); + builder.CreateBr(Header); + } +} + +/// compile_if - Emit code for '[' +void BrainFTraceRecorder::compile_if(BrainFTraceNode *node, + IRBuilder<>& builder) { + BasicBlock *ZeroChild = 0; + BasicBlock *NonZeroChild = 0; + + IRBuilder<> oldBuilder = builder; + + LLVMContext &Context = Header->getContext(); + + // If both directions of the branch go back to the trace-head, just + // jump there directly. + if (node->left == (BrainFTraceNode*)~0ULL && + node->right == (BrainFTraceNode*)~0ULL) { + HeaderPHI->addIncoming(DataPtr, builder.GetInsertBlock()); + builder.CreateBr(Header); + return; + } + + // Otherwise, there are two cases to handle for each direction: + // ~0ULL - A branch back to the trace head + // 0 - A branch out of the trace + // * - A branch to a node we haven't compiled yet. + // Go ahead and generate code for both targets. + + if (node->left == (BrainFTraceNode*)~0ULL) { + NonZeroChild = Header; + HeaderPHI->addIncoming(DataPtr, builder.GetInsertBlock()); + } else if (node->left == 0) { + NonZeroChild = BasicBlock::Create(Context, + "exit_left_"+utostr(node->pc), + Header->getParent()); + builder.SetInsertPoint(NonZeroChild); + ConstantInt *NewPc = ConstantInt::get(int_type, node->pc+1); + Value *BytecodeIndex = + builder.CreateConstInBoundsGEP1_32(bytecode_array, node->pc+1); + Value *Target = builder.CreateLoad(BytecodeIndex); + CallInst *Call =cast(builder.CreateCall2(Target, NewPc, DataPtr)); + Call->setTailCall(); + builder.CreateRetVoid(); + } else { + NonZeroChild = BasicBlock::Create(Context, + utostr(node->left->pc), + Header->getParent()); + builder.SetInsertPoint(NonZeroChild); + compile_opcode(node->left, builder); + } + + if (node->right == (BrainFTraceNode*)~0ULL) { + ZeroChild = Header; + HeaderPHI->addIncoming(DataPtr, builder.GetInsertBlock()); + } else if (node->right == 0) { + ZeroChild = BasicBlock::Create(Context, + "exit_right_"+utostr(node->pc), + Header->getParent()); + builder.SetInsertPoint(ZeroChild); + ConstantInt *NewPc = ConstantInt::get(int_type, JumpMap[node->pc]+1); + Value *BytecodeIndex = + builder.CreateConstInBoundsGEP1_32(bytecode_array, JumpMap[node->pc]+1); + Value *Target = builder.CreateLoad(BytecodeIndex); + CallInst *Call =cast(builder.CreateCall2(Target, NewPc, DataPtr)); + Call->setTailCall(); + builder.CreateRetVoid(); + } else { + ZeroChild = BasicBlock::Create(Context, + utostr(node->right->pc), + Header->getParent()); + builder.SetInsertPoint(ZeroChild); + compile_opcode(node->right, builder); + } + + // Generate the test and branch to select between the targets. + Value *Loaded = oldBuilder.CreateLoad(DataPtr); + Value *Cmp = oldBuilder.CreateICmpEQ(Loaded, + ConstantInt::get(Loaded->getType(), 0)); + oldBuilder.CreateCondBr(Cmp, ZeroChild, NonZeroChild); +} + +/// compile_back - Emit code for ']' +void BrainFTraceRecorder::compile_back(BrainFTraceNode *node, + IRBuilder<>& builder) { + if (node->right != (BrainFTraceNode*)~0ULL) + compile_opcode(node->right, builder); + else { + HeaderPHI->addIncoming(DataPtr, builder.GetInsertBlock()); + builder.CreateBr(Header); + } +} + +/// compile_opcode - Dispatch to a more specific compiler function based +/// on the opcode of the current node. +void BrainFTraceRecorder::compile_opcode(BrainFTraceNode *node, + IRBuilder<>& builder) { + switch (node->opcode) { + case '+': + compile_plus(node, builder); + break; + case '-': + compile_minus(node, builder); + break; + case '<': + compile_left(node, builder); + break; + case '>': + compile_right(node, builder); + break; + case '.': + compile_put(node, builder); + break; + case ',': + compile_get(node, builder); + break; + case '[': + compile_if(node, builder); + break; + case ']': + compile_back(node, builder); + break; + } +} Added: llvm/trunk/examples/TracingBrainF/BrainFInterpreter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/TracingBrainF/BrainFInterpreter.cpp?rev=112465&view=auto ============================================================================== --- llvm/trunk/examples/TracingBrainF/BrainFInterpreter.cpp (added) +++ llvm/trunk/examples/TracingBrainF/BrainFInterpreter.cpp Mon Aug 30 02:33:39 2010 @@ -0,0 +1,116 @@ +//===-- BrainFInterpreter.cpp - BrainF trace compiler interpreter -------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===--------------------------------------------------------------------===// + +#include "BrainF.h" +#include "BrainFVM.h" +#include "llvm/Support/CommandLine.h" +#include "llvm/Support/MemoryBuffer.h" +#include "llvm/Support/raw_ostream.h" +#include +using namespace llvm; + +//Command line options + +static cl::opt +InputFilename(cl::Positional, cl::desc("")); + +int main(int argc, char **argv) { + cl::ParseCommandLineOptions(argc, argv, " BrainF compiler\n"); + + if (InputFilename == "") { + errs() << "Error: You must specify the filename of the program to " + "be compiled. Use --help to see the options.\n"; + abort(); + } + + // Read the input file. + MemoryBuffer *Code = MemoryBuffer::getFileOrSTDIN(InputFilename); + const uint8_t *CodeBegin = (const uint8_t*)(Code->getBufferStart()); + + // Create a new buffer to hold the preprocessed code. + MemoryBuffer *ParsedCode = + MemoryBuffer::getNewMemBuffer(sizeof(opcode_func_t) * + (Code->getBufferSize()+1)); + BytecodeArray = (opcode_func_t*)(ParsedCode->getBufferStart()); + size_t BytecodeOffset = 0; + + // Create JumpMap, a special on-the-side data array used to implement + // efficient jumps in the interpreter. + JumpMap = new size_t[Code->getBufferSize()]; + memset(JumpMap, 0, sizeof(size_t) * Code->getBufferSize()); + std::vector Stack; + + // Preprocess the input source code, performing three tasks: + // 1 - Remove non-instruction characters + // 2 - Replace character literals with opcode function pointers + // 3 - Precompute the jump targets for [ and ] instructions in JumpMap + for (size_t i = 0; i < Code->getBufferSize(); ++i) { + uint8_t opcode = CodeBegin[i]; + switch (opcode) { + case '>': + BytecodeArray[BytecodeOffset++] = &op_right; + break; + case '<': + BytecodeArray[BytecodeOffset++] = &op_left; + break; + case '+': + BytecodeArray[BytecodeOffset++] = &op_plus; + break; + case '-': + BytecodeArray[BytecodeOffset++] = &op_minus; + break; + case '.': + BytecodeArray[BytecodeOffset++] = &op_put; + break; + case ',': + BytecodeArray[BytecodeOffset++] = &op_get; + break; + case '[': + Stack.push_back(BytecodeOffset); + BytecodeArray[BytecodeOffset++] = &op_if; + break; + case ']': + JumpMap[Stack.back()] = BytecodeOffset; + JumpMap[BytecodeOffset] = Stack.back(); + Stack.pop_back(); + BytecodeArray[BytecodeOffset++] = &op_back; + break; + default: + continue; + } + } + + // Fill in the suffix of the preprocessed source for op_exit. + // Thus, if we reach the end of the source, the program will terminate. + while (BytecodeOffset < Code->getBufferSize()+1) { + BytecodeArray[BytecodeOffset++] = &op_end; + } + + // Setup the array. + uint8_t *BrainFArray = new uint8_t[32768]; + memset(BrainFArray, 0, 32768); + + // Setup the trace recorder. + Recorder = new BrainFTraceRecorder(); + + // Main interpreter loop. + // Note the lack of a explicit loop: every opcode is a tail-recursive + // function that calls its own successor by indexing into BytecodeArray. + uint8_t* data = BrainFArray; + BytecodeArray[0](0, data); + + //Clean up + delete Recorder; + delete Code; + delete ParsedCode; + delete[] BrainFArray; + delete[] JumpMap; + + return 0; +} Added: llvm/trunk/examples/TracingBrainF/BrainFOpcodes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/TracingBrainF/BrainFOpcodes.cpp?rev=112465&view=auto ============================================================================== --- llvm/trunk/examples/TracingBrainF/BrainFOpcodes.cpp (added) +++ llvm/trunk/examples/TracingBrainF/BrainFOpcodes.cpp Mon Aug 30 02:33:39 2010 @@ -0,0 +1,68 @@ +//===-- BrainFOpcodes.cpp - BrainF interpreter opcodes ------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===--------------------------------------------------------------------===// + +#include "BrainFVM.h" +#include + +opcode_func_t *BytecodeArray = 0; +size_t *JumpMap = 0; +uint8_t executed = 0; + +BrainFTraceRecorder *Recorder = 0; + +void op_plus(size_t pc, uint8_t *data) { + Recorder->record_simple(pc, '+'); + *data += 1; + BytecodeArray[pc+1](pc+1, data); +} + +void op_minus(size_t pc, uint8_t *data) { + Recorder->record_simple(pc, '-'); + *data -= 1; + BytecodeArray[pc+1](pc+1, data); +} + +void op_left(size_t pc, uint8_t *data) { + Recorder->record_simple(pc, '<'); + BytecodeArray[pc+1](pc+1, data-1); +} + +void op_right(size_t pc, uint8_t *data) { + Recorder->record_simple(pc, '>'); + BytecodeArray[pc+1](pc+1, data+1); +} + +void op_put(size_t pc, uint8_t *data) { + Recorder->record_simple(pc, '.'); + putchar(*data); + BytecodeArray[pc+1](pc+1, data); +} + +void op_get(size_t pc, uint8_t *data) { + Recorder->record_simple(pc, ','); + *data = getchar(); + BytecodeArray[pc+1](pc+1, data); +} + +void op_if(size_t pc, uint8_t *data) { + Recorder->record(pc, '['); + size_t new_pc = pc+1; + if (!*data) new_pc = JumpMap[pc]+1; + BytecodeArray[new_pc](new_pc, data); +} + +void op_back(size_t pc, uint8_t *data) { + Recorder->record_simple(pc, ']'); + size_t new_pc = JumpMap[pc]; + BytecodeArray[new_pc](new_pc, data); +} + +void op_end(size_t, uint8_t *) { + return; +} Added: llvm/trunk/examples/TracingBrainF/BrainFTraceRecorder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/TracingBrainF/BrainFTraceRecorder.cpp?rev=112465&view=auto ============================================================================== --- llvm/trunk/examples/TracingBrainF/BrainFTraceRecorder.cpp (added) +++ llvm/trunk/examples/TracingBrainF/BrainFTraceRecorder.cpp Mon Aug 30 02:33:39 2010 @@ -0,0 +1,155 @@ +//===-- BrainFTraceRecorder.cpp - BrainF trace recorder ------------------==// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===--------------------------------------------------------------------===// +// +// This class observes the execution trace of the interpreter, identifying +// hot traces and eventually compiling them to native code. +// +// The operation of the recorder can be divided into four parts: +// 1) Interation Counting - To identify hot traces, we track the execution +// counts of all loop headers ('[' instructions). We use a fixed-size +// array of counters for this, since lack of precision does not affect +// correctness. +// +// 2) Trace Buffering - Once a header has passed a hotness threshold, we +// begin buffering the execution trace beginning from that header the +// next time it is executed. This buffer is of a fixed length, though +// that choice can be tuned for performance. If the end of the buffer +// is reached without execution returning to the header, we throw out +// the trace. +// +// 3) Trace Commit - If the buffered trace returns to the header before +// the buffer limit is reached, that trace is commited to form a trace +// tree. This tree aggregates all execution traces that have been +// observed originating from the header since it passed the hotness +// threshold. The buffer is then cleared to allow a new trace to be +// recorded. +// +// 4) Trace Compilation - Once a secondary hotness threshold is reached, +// trace recording is terminated and the set of observed traces encoded +// in the trace tree are compiled to native code, and a function pointer +// to that trace is installed into the bytecode array in place of one of +// the normal opcode functions. Details of this compilation are in +// BrainFCodeGen.cpp +//===--------------------------------------------------------------------===// + +#include "BrainF.h" +#include "BrainFVM.h" +#include "llvm/Support/raw_ostream.h" + +#define ITERATION_BUF_SIZE 1024 +#define TRACE_BUF_SIZE 256 +#define TRACE_THRESHOLD 50 +#define COMPILE_THRESHOLD 200 + +void BrainFTraceRecorder::BrainFTraceNode::dump(unsigned lvl) { + for (unsigned i = 0; i < lvl; ++i) + outs() << '.'; + outs() << opcode << " : " << pc << "\n"; + if (left && left != (BrainFTraceNode*)~0ULL) left->dump(lvl+1); + if (right && right != (BrainFTraceNode*)~0ULL) right->dump(lvl+1); +} + +BrainFTraceRecorder::BrainFTraceRecorder() + : prev_opcode('+'), iteration_count(new uint8_t[ITERATION_BUF_SIZE]), + trace_begin(new std::pair[TRACE_BUF_SIZE]), + trace_end(trace_begin + TRACE_BUF_SIZE), + trace_tail(trace_begin), + module(new Module("BrainF", getGlobalContext())) { + memset(iteration_count, 0, ITERATION_BUF_SIZE); + memset(trace_begin, 0, sizeof(std::pair) * TRACE_BUF_SIZE); + + initialize_module(); +} + +BrainFTraceRecorder::~BrainFTraceRecorder() { + delete[] iteration_count; + delete[] trace_begin; + delete FPM; + delete EE; +} + +void BrainFTraceRecorder::commit() { + BrainFTraceNode *&Head = trace_map[trace_begin->second]; + if (!Head) + Head = new BrainFTraceNode(trace_begin->first, trace_begin->second); + + BrainFTraceNode *Parent = Head; + std::pair *trace_iter = trace_begin+1; + while (trace_iter != trace_tail) { + BrainFTraceNode *Child = 0; + + if (trace_iter->second == Parent->pc+1) { + if (Parent->left) Child = Parent->left; + else Child = Parent->left = + new BrainFTraceNode(trace_iter->first, trace_iter->second); + } else { + if (Parent->right) Child = Parent->right; + else Child = Parent->right = + new BrainFTraceNode(trace_iter->first, trace_iter->second); + } + + Parent = Child; + ++trace_iter; + } + + if (Parent->pc+1 == Head->pc) + Parent->left = (BrainFTraceNode*)~0ULL; + else + Parent->right = (BrainFTraceNode*)~0ULL; +} + +void BrainFTraceRecorder::record_simple(size_t pc, uint8_t opcode) { + if (executed) { + executed = false; + trace_tail = trace_begin; + } + + if (trace_tail != trace_begin) { + if (trace_tail == trace_end) { + trace_tail = trace_begin; + } else { + trace_tail->first = opcode; + trace_tail->second = pc; + ++trace_tail; + } + } + prev_opcode = opcode; +} + +void BrainFTraceRecorder::record(size_t pc, uint8_t opcode) { + if (executed) { + executed = false; + trace_tail = trace_begin; + } + + if (trace_tail != trace_begin) { + if (pc == trace_begin->second) { + commit(); + trace_tail = trace_begin; + } else if (trace_tail == trace_end) { + trace_tail = trace_begin; + } else { + trace_tail->first = opcode; + trace_tail->second = pc; + ++trace_tail; + } + } else if (opcode == '[' && prev_opcode == ']'){ + size_t hash = pc % ITERATION_BUF_SIZE; + if (iteration_count[hash] == 255) iteration_count[hash] = 254; + if (++iteration_count[hash] > COMPILE_THRESHOLD && trace_map.count(pc)) { + compile(trace_map[pc]); + } else if (++iteration_count[hash] > TRACE_THRESHOLD) { + trace_tail->first = opcode; + trace_tail->second = pc; + ++trace_tail; + } + } + + prev_opcode = opcode; +} \ No newline at end of file Added: llvm/trunk/examples/TracingBrainF/BrainFVM.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/TracingBrainF/BrainFVM.h?rev=112465&view=auto ============================================================================== --- llvm/trunk/examples/TracingBrainF/BrainFVM.h (added) +++ llvm/trunk/examples/TracingBrainF/BrainFVM.h Mon Aug 30 02:33:39 2010 @@ -0,0 +1,63 @@ +//===-- BrainFVM.h - BrainF interpreter header ----------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===--------------------------------------------------------------------===// + +#ifndef BRAINF_VM_H +#define BRAINF_VM_H + +#include "BrainF.h" +#include "stdint.h" +#include + +/// opcode_func_t - A function pointer signature for all opcode functions. +typedef void(*opcode_func_t)(size_t pc, uint8_t* data); + +/// BytecodeArray - An array of function pointers representing the +/// source program. Indexed by PC address. +extern opcode_func_t *BytecodeArray; + +/// JumpMap - An array of on-the-side data used by the interpreter. +/// Indexed by PC address. +extern size_t *JumpMap; + +/// executed - A flag indicating whether the preceding opcode was evaluated +/// within a compiled trace execution. Used by the trace recorder. +extern uint8_t executed; + +/// Recorder - The trace recording engine. +extern BrainFTraceRecorder *Recorder; + +/// op_plus - Implements the '+' instruction. +void op_plus(size_t, uint8_t*); + +/// op_minus - Implements the '-' instruction. +void op_minus(size_t, uint8_t*); + +// op_left - Implements the '<' instruction. +void op_left(size_t, uint8_t*); + +// op_right - Implements the '>' instruction. +void op_right(size_t, uint8_t*); + +// op_put - Implements the '.' instruction. +void op_put(size_t, uint8_t*); + +// op_get - Implements the ',' instruction. +void op_get(size_t, uint8_t*); + +// op_if - Implements the '[' instruction. +void op_if(size_t, uint8_t*); + +// op_back - Implements the ']' instruction. +void op_back(size_t, uint8_t*); + +// op_end - Terminates an execution. +void op_end(size_t, uint8_t*); + + +#endif \ No newline at end of file Added: llvm/trunk/examples/TracingBrainF/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/TracingBrainF/Makefile?rev=112465&view=auto ============================================================================== --- llvm/trunk/examples/TracingBrainF/Makefile (added) +++ llvm/trunk/examples/TracingBrainF/Makefile Mon Aug 30 02:33:39 2010 @@ -0,0 +1,17 @@ +##===- examples/TracingBrainF/Makefile ------------------- -*- Makefile -*-===## +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open Source +# License. See LICENSE.TXT for details. +# +##===----------------------------------------------------------------------===## +LEVEL = ../.. +TOOLNAME = TracingBrainF +EXAMPLE_TOOL = 1 + +CXXFLAGS += -foptimize-sibling-calls + +LINK_COMPONENTS := scalaropts jit nativecodegen + +include $(LEVEL)/Makefile.common Added: llvm/trunk/examples/TracingBrainF/README URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/TracingBrainF/README?rev=112465&view=auto ============================================================================== --- llvm/trunk/examples/TracingBrainF/README (added) +++ llvm/trunk/examples/TracingBrainF/README Mon Aug 30 02:33:39 2010 @@ -0,0 +1 @@ +This is an example trace-based JIT for Brainfuck, using LLVM as its code generation engine. To compile it, simply drop this directory within llvm/examples in an LLVM source tree, and do `make` in that directory. From baldrick at free.fr Mon Aug 30 05:48:30 2010 From: baldrick at free.fr (Duncan Sands) Date: Mon, 30 Aug 2010 10:48:30 -0000 Subject: [llvm-commits] [llvm] r112469 - in /llvm/trunk/test: CodeGen/ARM/ CodeGen/Mips/ CodeGen/SystemZ/ CodeGen/Thumb/ CodeGen/X86/ Transforms/GVN/ Transforms/IndVarSimplify/ Transforms/LoopStrengthReduce/ Transforms/SimplifyCFG/ Message-ID: <20100830104830.6A7202A6C12C@llvm.org> Author: baldrick Date: Mon Aug 30 05:48:29 2010 New Revision: 112469 URL: http://llvm.org/viewvc/llvm-project?rev=112469&view=rev Log: Correct bogus module triple specifications. Modified: llvm/trunk/test/CodeGen/ARM/2007-03-26-RegScavengerAssert.ll llvm/trunk/test/CodeGen/ARM/2007-05-31-RegScavengerInfiniteLoop.ll llvm/trunk/test/CodeGen/ARM/fpowi.ll llvm/trunk/test/CodeGen/Mips/2008-06-05-Carry.ll llvm/trunk/test/CodeGen/Mips/2008-07-03-SRet.ll llvm/trunk/test/CodeGen/Mips/2008-07-05-ByVal.ll llvm/trunk/test/CodeGen/Mips/2008-07-06-fadd64.ll llvm/trunk/test/CodeGen/Mips/2008-07-07-FPExtend.ll llvm/trunk/test/CodeGen/Mips/2008-07-07-Float2Int.ll llvm/trunk/test/CodeGen/Mips/2008-07-07-IntDoubleConvertions.ll llvm/trunk/test/CodeGen/Mips/2008-07-15-InternalConstant.ll llvm/trunk/test/CodeGen/Mips/2008-07-15-SmallSection.ll llvm/trunk/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll llvm/trunk/test/CodeGen/Mips/2008-07-22-Cstpool.ll llvm/trunk/test/CodeGen/Mips/2008-07-23-fpcmp.ll llvm/trunk/test/CodeGen/Mips/2008-07-29-icmp.ll llvm/trunk/test/CodeGen/Mips/2008-07-31-fcopysign.ll llvm/trunk/test/CodeGen/Mips/2008-08-01-AsmInline.ll llvm/trunk/test/CodeGen/Mips/2008-08-03-fabs64.ll llvm/trunk/test/CodeGen/Mips/2008-08-04-Bitconvert.ll llvm/trunk/test/CodeGen/Mips/2008-08-06-Alloca.ll llvm/trunk/test/CodeGen/Mips/2008-08-07-CC.ll llvm/trunk/test/CodeGen/Mips/2008-08-07-FPRound.ll llvm/trunk/test/CodeGen/Mips/2008-08-08-ctlz.ll llvm/trunk/test/CodeGen/SystemZ/05-MemLoadsStores.ll llvm/trunk/test/CodeGen/SystemZ/05-MemLoadsStores16.ll llvm/trunk/test/CodeGen/SystemZ/07-BrUnCond.ll llvm/trunk/test/CodeGen/SystemZ/09-DynamicAlloca.ll llvm/trunk/test/CodeGen/SystemZ/09-Globals.ll llvm/trunk/test/CodeGen/SystemZ/10-FuncsPic.ll llvm/trunk/test/CodeGen/SystemZ/10-GlobalsPic.ll llvm/trunk/test/CodeGen/SystemZ/11-BSwap.ll llvm/trunk/test/CodeGen/SystemZ/2009-06-02-Rotate.ll llvm/trunk/test/CodeGen/SystemZ/2009-07-04-Shl32.ll llvm/trunk/test/CodeGen/SystemZ/2009-07-05-Shifts.ll llvm/trunk/test/CodeGen/SystemZ/2009-07-10-BadIncomingArgOffset.ll llvm/trunk/test/CodeGen/SystemZ/2009-07-11-FloatBitConvert.ll llvm/trunk/test/CodeGen/SystemZ/2009-07-11-InvalidRIISel.ll llvm/trunk/test/CodeGen/Thumb/2007-05-05-InvalidPushPop.ll llvm/trunk/test/CodeGen/X86/dllexport.ll llvm/trunk/test/CodeGen/X86/stdcall.ll llvm/trunk/test/Transforms/GVN/2009-07-13-MemDepSortFail.ll llvm/trunk/test/Transforms/IndVarSimplify/2009-05-24-useafterfree.ll llvm/trunk/test/Transforms/IndVarSimplify/loop_evaluate10.ll llvm/trunk/test/Transforms/LoopStrengthReduce/pr3571.ll llvm/trunk/test/Transforms/SimplifyCFG/2008-04-27-MultipleReturnCrash.ll Modified: llvm/trunk/test/CodeGen/ARM/2007-03-26-RegScavengerAssert.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2007-03-26-RegScavengerAssert.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2007-03-26-RegScavengerAssert.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2007-03-26-RegScavengerAssert.ll Mon Aug 30 05:48:29 2010 @@ -2,7 +2,7 @@ ; PR1266 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "arm-linux-gnueabi" +target triple = "arm-unknown-linux-gnueabi" %struct.CUMULATIVE_ARGS = type { i32, i32, i32, i32, i32, i32 } %struct.FILE = type { i32, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, %struct._IO_marker*, %struct.FILE*, i32, i32, i32, i16, i8, [1 x i8], i8*, i64, i8*, i8*, i32, [52 x i8] } %struct.VEC_edge = type { i32, i32, [1 x %struct.edge_def*] } Modified: llvm/trunk/test/CodeGen/ARM/2007-05-31-RegScavengerInfiniteLoop.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2007-05-31-RegScavengerInfiniteLoop.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2007-05-31-RegScavengerInfiniteLoop.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2007-05-31-RegScavengerInfiniteLoop.ll Mon Aug 30 05:48:29 2010 @@ -2,7 +2,7 @@ ; PR1424 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "arm-linux-gnueabi" +target triple = "arm-unknown-linux-gnueabi" %struct.AVClass = type { i8*, i8* (i8*)*, %struct.AVOption* } %struct.AVCodec = type { i8*, i32, i32, i32, i32 (%struct.AVCodecContext*)*, i32 (%struct.AVCodecContext*, i8*, i32, i8*)*, i32 (%struct.AVCodecContext*)*, i32 (%struct.AVCodecContext*, i8*, i32*, i8*, i32)*, i32, %struct.AVCodec*, void (%struct.AVCodecContext*)*, %struct.AVRational*, i32* } %struct.AVCodecContext = type { %struct.AVClass*, i32, i32, i32, i32, i32, i8*, i32, %struct.AVRational, i32, i32, i32, i32, i32, void (%struct.AVCodecContext*, %struct.AVFrame*, i32*, i32, i32, i32)*, i32, i32, i32, i32, i32, i32, i32, float, float, i32, i32, i32, i32, float, i32, i32, i32, %struct.AVCodec*, i8*, i32, i32, void (%struct.AVCodecContext*, i8*, i32, i32)*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, [32 x i8], i32, i32, i32, i32, i32, i32, i32, float, i32, i32 (%struct.AVCodecContext*, %struct.AVFrame*)*, void (%struct.AVCodecContext*, %struct.AVFrame*)*, i32, i32, i32, i32, i8*, i8*, float, float, i32, %struct.RcOverride*, i32, i8*, i32, i32, i32, float, float, float, float, i32, float, float, float, float, float, i32, i32, i32, i32*, i32, i32, i32, i32, %struct.AVRational, %struct.AVFrame*, i32, i32, [4 x i64], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 (%struct.AVCodecContext*, i32*)*, i32, i32, i32, i32, i32, i32, i8*, i32, i32, i32, i32, i32, i32, i16*, i16*, i32, i32, i32, i32, %struct.AVPaletteControl*, i32, i32 (%struct.AVCodecContext*, %struct.AVFrame*)*, i32, i32, i32, i32, i32, i32, i32, i32 (%struct.AVCodecContext*, i32 (%struct.AVCodecContext*, i8*)*, i8**, i32*, i32)*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64 } Modified: llvm/trunk/test/CodeGen/ARM/fpowi.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fpowi.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fpowi.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fpowi.ll Mon Aug 30 05:48:29 2010 @@ -3,7 +3,7 @@ ; ModuleID = '' target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "arm-linux-gnueabi" +target triple = "arm-unknown-linux-gnueabi" define double @_ZSt3powdi(double %__x, i32 %__i) { entry: Modified: llvm/trunk/test/CodeGen/Mips/2008-06-05-Carry.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-06-05-Carry.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Mips/2008-06-05-Carry.ll (original) +++ llvm/trunk/test/CodeGen/Mips/2008-06-05-Carry.ll Mon Aug 30 05:48:29 2010 @@ -4,7 +4,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "mipsallegrexel-psp-elf" +target triple = "mipsallegrexel-unknown-psp-elf" define i64 @add64(i64 %u, i64 %v) nounwind { entry: Modified: llvm/trunk/test/CodeGen/Mips/2008-07-03-SRet.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-07-03-SRet.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Mips/2008-07-03-SRet.ll (original) +++ llvm/trunk/test/CodeGen/Mips/2008-07-03-SRet.ll Mon Aug 30 05:48:29 2010 @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=mips | grep {sw.*(\$4)} | count 3 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "mipsallegrexel-psp-elf" +target triple = "mipsallegrexel-unknown-psp-elf" %struct.sret0 = type { i32, i32, i32 } define void @test0(%struct.sret0* noalias sret %agg.result, i32 %dummy) nounwind { Modified: llvm/trunk/test/CodeGen/Mips/2008-07-05-ByVal.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-07-05-ByVal.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Mips/2008-07-05-ByVal.ll (original) +++ llvm/trunk/test/CodeGen/Mips/2008-07-05-ByVal.ll Mon Aug 30 05:48:29 2010 @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=mips | grep {lw.*(\$4)} | count 2 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "mipsallegrexel-psp-elf" +target triple = "mipsallegrexel-unknown-psp-elf" %struct.byval0 = type { i32, i32 } define i64 @test0(%struct.byval0* byval %b, i64 %sum) nounwind { Modified: llvm/trunk/test/CodeGen/Mips/2008-07-06-fadd64.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-07-06-fadd64.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Mips/2008-07-06-fadd64.ll (original) +++ llvm/trunk/test/CodeGen/Mips/2008-07-06-fadd64.ll Mon Aug 30 05:48:29 2010 @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=mips | grep __adddf3 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "mipsallegrexel-psp-elf" +target triple = "mipsallegrexel-unknown-psp-elf" define double @dofloat(double %a, double %b) nounwind { entry: Modified: llvm/trunk/test/CodeGen/Mips/2008-07-07-FPExtend.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-07-07-FPExtend.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Mips/2008-07-07-FPExtend.ll (original) +++ llvm/trunk/test/CodeGen/Mips/2008-07-07-FPExtend.ll Mon Aug 30 05:48:29 2010 @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=mips | grep __extendsfdf2 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "mipsallegrexel-psp-elf" +target triple = "mipsallegrexel-unknown-psp-elf" define double @dofloat(float %a) nounwind { entry: Modified: llvm/trunk/test/CodeGen/Mips/2008-07-07-Float2Int.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-07-07-Float2Int.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Mips/2008-07-07-Float2Int.ll (original) +++ llvm/trunk/test/CodeGen/Mips/2008-07-07-Float2Int.ll Mon Aug 30 05:48:29 2010 @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=mips | grep trunc.w.s | count 3 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "mipsallegrexel-psp-elf" +target triple = "mipsallegrexel-unknown-psp-elf" define i32 @fptoint(float %a) nounwind { entry: Modified: llvm/trunk/test/CodeGen/Mips/2008-07-07-IntDoubleConvertions.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-07-07-IntDoubleConvertions.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Mips/2008-07-07-IntDoubleConvertions.ll (original) +++ llvm/trunk/test/CodeGen/Mips/2008-07-07-IntDoubleConvertions.ll Mon Aug 30 05:48:29 2010 @@ -5,7 +5,7 @@ ; RUN: grep __fixunsdfsi %t | count 1 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "mipsallegrexel-psp-elf" +target triple = "mipsallegrexel-unknown-psp-elf" define double @int2fp(i32 %a) nounwind { entry: Modified: llvm/trunk/test/CodeGen/Mips/2008-07-15-InternalConstant.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-07-15-InternalConstant.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Mips/2008-07-15-InternalConstant.ll (original) +++ llvm/trunk/test/CodeGen/Mips/2008-07-15-InternalConstant.ll Mon Aug 30 05:48:29 2010 @@ -6,7 +6,7 @@ ; RUN: not grep {gp_rel} %t target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "mipsallegrexel-psp-elf" +target triple = "mipsallegrexel-unknown-psp-elf" @.str = internal constant [10 x i8] c"AAAAAAAAA\00" @i0 = internal constant [5 x i32] [ i32 0, i32 1, i32 2, i32 3, i32 4 ] Modified: llvm/trunk/test/CodeGen/Mips/2008-07-15-SmallSection.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-07-15-SmallSection.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Mips/2008-07-15-SmallSection.ll (original) +++ llvm/trunk/test/CodeGen/Mips/2008-07-15-SmallSection.ll Mon Aug 30 05:48:29 2010 @@ -10,7 +10,7 @@ ; RUN: grep {\%lo} %t1 | count 2 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "mipsallegrexel-psp-elf" +target triple = "mipsallegrexel-unknown-psp-elf" %struct.anon = type { i32, i32 } @s0 = global [8 x i8] c"AAAAAAA\00", align 4 Modified: llvm/trunk/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll (original) +++ llvm/trunk/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll Mon Aug 30 05:48:29 2010 @@ -3,7 +3,7 @@ ; RUN: grep seb %t | count 1 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "mipsallegrexel-psp-elf" +target triple = "mipsallegrexel-unknown-psp-elf" define i8 @A(i8 %e.0, i8 signext %sum) signext nounwind { entry: Modified: llvm/trunk/test/CodeGen/Mips/2008-07-22-Cstpool.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-07-22-Cstpool.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Mips/2008-07-22-Cstpool.ll (original) +++ llvm/trunk/test/CodeGen/Mips/2008-07-22-Cstpool.ll Mon Aug 30 05:48:29 2010 @@ -2,7 +2,7 @@ ; RUN: grep {CPI\[01\]_\[01\]:} %t | count 2 ; RUN: grep {rodata.cst4,"aM", at progbits} %t | count 1 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "mipsallegrexel-psp-elf" +target triple = "mipsallegrexel-unknown-psp-elf" define float @F(float %a) nounwind { entry: Modified: llvm/trunk/test/CodeGen/Mips/2008-07-23-fpcmp.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-07-23-fpcmp.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Mips/2008-07-23-fpcmp.ll (original) +++ llvm/trunk/test/CodeGen/Mips/2008-07-23-fpcmp.ll Mon Aug 30 05:48:29 2010 @@ -3,7 +3,7 @@ ; RUN: grep {bc1\[tf\]} %t | count 3 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "mipsallegrexel-psp-elf" +target triple = "mipsallegrexel-unknown-psp-elf" define float @A(float %a, float %b) nounwind { entry: Modified: llvm/trunk/test/CodeGen/Mips/2008-07-29-icmp.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-07-29-icmp.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Mips/2008-07-29-icmp.ll (original) +++ llvm/trunk/test/CodeGen/Mips/2008-07-29-icmp.ll Mon Aug 30 05:48:29 2010 @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=mips | grep {b\[ne\]\[eq\]} | count 1 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "mipsallegrexel-psp-elf" +target triple = "mipsallegrexel-unknown-psp-elf" define float @A(float %a, float %b, i32 %j) nounwind { entry: Modified: llvm/trunk/test/CodeGen/Mips/2008-07-31-fcopysign.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-07-31-fcopysign.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Mips/2008-07-31-fcopysign.ll (original) +++ llvm/trunk/test/CodeGen/Mips/2008-07-31-fcopysign.ll Mon Aug 30 05:48:29 2010 @@ -3,7 +3,7 @@ ; RUN: grep neg.s %t | count 1 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "mipsallegrexel-psp-elf" +target triple = "mipsallegrexel-unknown-psp-elf" define float @A(float %i, float %j) nounwind { entry: Modified: llvm/trunk/test/CodeGen/Mips/2008-08-01-AsmInline.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-08-01-AsmInline.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Mips/2008-08-01-AsmInline.ll (original) +++ llvm/trunk/test/CodeGen/Mips/2008-08-01-AsmInline.ll Mon Aug 30 05:48:29 2010 @@ -4,7 +4,7 @@ ; RUN: grep multu %t | count 1 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "mipsallegrexel-psp-elf" +target triple = "mipsallegrexel-unknown-psp-elf" %struct.DWstruct = type { i32, i32 } define i32 @A0(i32 %u, i32 %v) nounwind { Modified: llvm/trunk/test/CodeGen/Mips/2008-08-03-fabs64.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-08-03-fabs64.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Mips/2008-08-03-fabs64.ll (original) +++ llvm/trunk/test/CodeGen/Mips/2008-08-03-fabs64.ll Mon Aug 30 05:48:29 2010 @@ -3,7 +3,7 @@ ; RUN: grep {ori.*65535} %t | count 1 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "mipsallegrexel-psp-elf" +target triple = "mipsallegrexel-unknown-psp-elf" define double @A(double %c, double %d) nounwind readnone { entry: Modified: llvm/trunk/test/CodeGen/Mips/2008-08-04-Bitconvert.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-08-04-Bitconvert.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Mips/2008-08-04-Bitconvert.ll (original) +++ llvm/trunk/test/CodeGen/Mips/2008-08-04-Bitconvert.ll Mon Aug 30 05:48:29 2010 @@ -3,7 +3,7 @@ ; RUN: grep mfc1 %t | count 1 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "mipsallegrexel-psp-elf" +target triple = "mipsallegrexel-unknown-psp-elf" define float @A(i32 %u) nounwind { entry: Modified: llvm/trunk/test/CodeGen/Mips/2008-08-06-Alloca.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-08-06-Alloca.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Mips/2008-08-06-Alloca.ll (original) +++ llvm/trunk/test/CodeGen/Mips/2008-08-06-Alloca.ll Mon Aug 30 05:48:29 2010 @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=mips | grep {subu.*sp} | count 2 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "mipsallegrexel-psp-elf" +target triple = "mipsallegrexel-unknown-psp-elf" define i32 @twoalloca(i32 %size) nounwind { entry: Modified: llvm/trunk/test/CodeGen/Mips/2008-08-07-CC.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-08-07-CC.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Mips/2008-08-07-CC.ll (original) +++ llvm/trunk/test/CodeGen/Mips/2008-08-07-CC.ll Mon Aug 30 05:48:29 2010 @@ -3,7 +3,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "mipsallegrexel-psp-elf" +target triple = "mipsallegrexel-unknown-psp-elf" define internal fastcc i32 @A(i32 %u) nounwind { entry: Modified: llvm/trunk/test/CodeGen/Mips/2008-08-07-FPRound.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-08-07-FPRound.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Mips/2008-08-07-FPRound.ll (original) +++ llvm/trunk/test/CodeGen/Mips/2008-08-07-FPRound.ll Mon Aug 30 05:48:29 2010 @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=mips | grep __truncdfsf2 | count 1 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "mipsallegrexel-psp-elf" +target triple = "mipsallegrexel-unknown-psp-elf" define float @round2float(double %a) nounwind { entry: Modified: llvm/trunk/test/CodeGen/Mips/2008-08-08-ctlz.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-08-08-ctlz.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Mips/2008-08-08-ctlz.ll (original) +++ llvm/trunk/test/CodeGen/Mips/2008-08-08-ctlz.ll Mon Aug 30 05:48:29 2010 @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=mips | grep clz | count 1 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "mipsallegrexel-psp-elf" +target triple = "mipsallegrexel-unknown-psp-elf" define i32 @A0(i32 %u) nounwind { entry: Modified: llvm/trunk/test/CodeGen/SystemZ/05-MemLoadsStores.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/05-MemLoadsStores.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/SystemZ/05-MemLoadsStores.ll (original) +++ llvm/trunk/test/CodeGen/SystemZ/05-MemLoadsStores.ll Mon Aug 30 05:48:29 2010 @@ -4,7 +4,7 @@ ; RUN: llc < %s | grep {st %} | count 2 target datalayout = "E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-a0:16:16" -target triple = "s390x-linux" +target triple = "s390x-ibm-linux" define void @foo1(i32* nocapture %foo, i32* nocapture %bar) nounwind { entry: Modified: llvm/trunk/test/CodeGen/SystemZ/05-MemLoadsStores16.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/05-MemLoadsStores16.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/SystemZ/05-MemLoadsStores16.ll (original) +++ llvm/trunk/test/CodeGen/SystemZ/05-MemLoadsStores16.ll Mon Aug 30 05:48:29 2010 @@ -4,7 +4,7 @@ ; RUN: llc < %s | grep {sth.%} | count 2 target datalayout = "E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-a0:16:16" -target triple = "s390x-linux" +target triple = "s390x-ibm-linux" define void @foo1(i16* nocapture %foo, i16* nocapture %bar) nounwind { entry: Modified: llvm/trunk/test/CodeGen/SystemZ/07-BrUnCond.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/07-BrUnCond.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/SystemZ/07-BrUnCond.ll (original) +++ llvm/trunk/test/CodeGen/SystemZ/07-BrUnCond.ll Mon Aug 30 05:48:29 2010 @@ -1,7 +1,7 @@ ; RUN: llc < %s target datalayout = "E-p:64:64:64-i1:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128" -target triple = "s390x-linux" +target triple = "s390x-ibm-linux" define void @foo() noreturn nounwind { entry: Modified: llvm/trunk/test/CodeGen/SystemZ/09-DynamicAlloca.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/09-DynamicAlloca.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/SystemZ/09-DynamicAlloca.ll (original) +++ llvm/trunk/test/CodeGen/SystemZ/09-DynamicAlloca.ll Mon Aug 30 05:48:29 2010 @@ -1,7 +1,7 @@ ; RUN: llc < %s target datalayout = "E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-a0:16:16" -target triple = "s390x-linux" +target triple = "s390x-ibm-linux" define void @foo(i64 %N) nounwind { entry: Modified: llvm/trunk/test/CodeGen/SystemZ/09-Globals.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/09-Globals.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/SystemZ/09-Globals.ll (original) +++ llvm/trunk/test/CodeGen/SystemZ/09-Globals.ll Mon Aug 30 05:48:29 2010 @@ -1,7 +1,7 @@ ; RUN: llc < %s | grep larl | count 3 target datalayout = "E-p:64:64:64-i1:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128" -target triple = "s390x-linux" +target triple = "s390x-ibm-linux" @bar = common global i64 0, align 8 ; [#uses=3] define i64 @foo() nounwind readonly { Modified: llvm/trunk/test/CodeGen/SystemZ/10-FuncsPic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/10-FuncsPic.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/SystemZ/10-FuncsPic.ll (original) +++ llvm/trunk/test/CodeGen/SystemZ/10-FuncsPic.ll Mon Aug 30 05:48:29 2010 @@ -2,7 +2,7 @@ ; RUN: llc < %s -relocation-model=pic | grep PLT | count 1 target datalayout = "E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-a0:16:16" -target triple = "s390x-linux" +target triple = "s390x-ibm-linux" @ptr = external global void (...)* ; [#uses=2] define void @foo1() nounwind { Modified: llvm/trunk/test/CodeGen/SystemZ/10-GlobalsPic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/10-GlobalsPic.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/SystemZ/10-GlobalsPic.ll (original) +++ llvm/trunk/test/CodeGen/SystemZ/10-GlobalsPic.ll Mon Aug 30 05:48:29 2010 @@ -1,7 +1,7 @@ ; RUN: llc < %s -relocation-model=pic | grep GOTENT | count 6 target datalayout = "E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-a0:16:16" -target triple = "s390x-linux" +target triple = "s390x-ibm-linux" @src = external global i32 ; [#uses=2] @dst = external global i32 ; [#uses=2] @ptr = external global i32* ; [#uses=2] Modified: llvm/trunk/test/CodeGen/SystemZ/11-BSwap.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/11-BSwap.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/SystemZ/11-BSwap.ll (original) +++ llvm/trunk/test/CodeGen/SystemZ/11-BSwap.ll Mon Aug 30 05:48:29 2010 @@ -2,7 +2,7 @@ target datalayout = "E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-a0:16:16" -target triple = "s390x-linux" +target triple = "s390x-ibm-linux" define i16 @foo(i16 zeroext %a) zeroext { Modified: llvm/trunk/test/CodeGen/SystemZ/2009-06-02-Rotate.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/2009-06-02-Rotate.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/SystemZ/2009-06-02-Rotate.ll (original) +++ llvm/trunk/test/CodeGen/SystemZ/2009-06-02-Rotate.ll Mon Aug 30 05:48:29 2010 @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=systemz | grep rll target datalayout = "E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-a0:16:16" -target triple = "s390x-linux" +target triple = "s390x-ibm-linux" define i32 @rotl(i32 %x, i32 %y, i32 %z) nounwind readnone { entry: Modified: llvm/trunk/test/CodeGen/SystemZ/2009-07-04-Shl32.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/2009-07-04-Shl32.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/SystemZ/2009-07-04-Shl32.ll (original) +++ llvm/trunk/test/CodeGen/SystemZ/2009-07-04-Shl32.ll Mon Aug 30 05:48:29 2010 @@ -1,7 +1,7 @@ ; RUN: llc < %s target datalayout = "E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-a0:16:16" -target triple = "s390x-linux" +target triple = "s390x-ibm-linux" define void @compdecomp(i8* nocapture %data, i64 %data_len) nounwind { entry: Modified: llvm/trunk/test/CodeGen/SystemZ/2009-07-05-Shifts.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/2009-07-05-Shifts.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/SystemZ/2009-07-05-Shifts.ll (original) +++ llvm/trunk/test/CodeGen/SystemZ/2009-07-05-Shifts.ll Mon Aug 30 05:48:29 2010 @@ -1,7 +1,7 @@ ; RUN: llc < %s target datalayout = "E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-a0:16:16" -target triple = "s390x-linux" +target triple = "s390x-ibm-linux" define signext i32 @bit_place_piece(i32 signext %col, i32 signext %player, i64* nocapture %b1, i64* nocapture %b2) nounwind { entry: Modified: llvm/trunk/test/CodeGen/SystemZ/2009-07-10-BadIncomingArgOffset.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/2009-07-10-BadIncomingArgOffset.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/SystemZ/2009-07-10-BadIncomingArgOffset.ll (original) +++ llvm/trunk/test/CodeGen/SystemZ/2009-07-10-BadIncomingArgOffset.ll Mon Aug 30 05:48:29 2010 @@ -1,7 +1,7 @@ ; RUN: llc < %s | FileCheck %s target datalayout = "E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-a0:16:16" -target triple = "s390x-linux" +target triple = "s390x-ibm-linux" declare void @rdft(i32 signext, i32 signext, double*, i32* nocapture, double*) nounwind Modified: llvm/trunk/test/CodeGen/SystemZ/2009-07-11-FloatBitConvert.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/2009-07-11-FloatBitConvert.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/SystemZ/2009-07-11-FloatBitConvert.ll (original) +++ llvm/trunk/test/CodeGen/SystemZ/2009-07-11-FloatBitConvert.ll Mon Aug 30 05:48:29 2010 @@ -1,7 +1,7 @@ ; RUN: llc < %s target datalayout = "E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-a0:16:16" -target triple = "s390x-linux" +target triple = "s390x-ibm-linux" define float @foo(i32 signext %a) { entry: Modified: llvm/trunk/test/CodeGen/SystemZ/2009-07-11-InvalidRIISel.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/2009-07-11-InvalidRIISel.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/SystemZ/2009-07-11-InvalidRIISel.ll (original) +++ llvm/trunk/test/CodeGen/SystemZ/2009-07-11-InvalidRIISel.ll Mon Aug 30 05:48:29 2010 @@ -1,7 +1,7 @@ ; RUN: llc < %s target datalayout = "E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-a0:16:16" -target triple = "s390x-linux" +target triple = "s390x-ibm-linux" define signext i32 @dfg_parse() nounwind { entry: Modified: llvm/trunk/test/CodeGen/Thumb/2007-05-05-InvalidPushPop.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/2007-05-05-InvalidPushPop.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/2007-05-05-InvalidPushPop.ll (original) +++ llvm/trunk/test/CodeGen/Thumb/2007-05-05-InvalidPushPop.ll Mon Aug 30 05:48:29 2010 @@ -1,6 +1,6 @@ ; RUN: llc < %s | not grep r11 -target triple = "thumb-linux-gnueabi" +target triple = "thumb-unknown-linux-gnueabi" %struct.__sched_param = type { i32 } %struct.pthread_attr_t = type { i32, i32, %struct.__sched_param, i32, i32, i32, i32, i8*, i32 } @i.1882 = internal global i32 1 ; [#uses=2] Modified: llvm/trunk/test/CodeGen/X86/dllexport.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dllexport.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/dllexport.ll (original) +++ llvm/trunk/test/CodeGen/X86/dllexport.ll Mon Aug 30 05:48:29 2010 @@ -1,7 +1,7 @@ ; RUN: llc < %s | FileCheck %s ; PR2936 -target triple = "i386-mingw32" +target triple = "i386-pc-mingw32" define dllexport x86_fastcallcc i32 @foo() nounwind { entry: Modified: llvm/trunk/test/CodeGen/X86/stdcall.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/stdcall.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/stdcall.ll (original) +++ llvm/trunk/test/CodeGen/X86/stdcall.ll Mon Aug 30 05:48:29 2010 @@ -2,7 +2,7 @@ ; PR5851 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32" -target triple = "i386-mingw32" +target triple = "i386-pc-mingw32" %0 = type { void (...)* } Modified: llvm/trunk/test/Transforms/GVN/2009-07-13-MemDepSortFail.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GVN/2009-07-13-MemDepSortFail.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/Transforms/GVN/2009-07-13-MemDepSortFail.ll (original) +++ llvm/trunk/test/Transforms/GVN/2009-07-13-MemDepSortFail.ll Mon Aug 30 05:48:29 2010 @@ -1,7 +1,7 @@ ; RUN: opt < %s -gvn | llvm-dis ; PR4256 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" -target triple = "i386-linux-gnu" +target triple = "i386-pc-linux-gnu" %llvm.dbg.anchor.type = type { i32, i32 } %struct.cset = type { i8*, i8, i8, i32, i8* } %struct.lmat = type { %struct.re_guts*, i32, %llvm.dbg.anchor.type*, i8*, i8*, i8*, i8*, i8**, i32, i8*, i8*, i8*, i8*, i8* } Modified: llvm/trunk/test/Transforms/IndVarSimplify/2009-05-24-useafterfree.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/2009-05-24-useafterfree.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/Transforms/IndVarSimplify/2009-05-24-useafterfree.ll (original) +++ llvm/trunk/test/Transforms/IndVarSimplify/2009-05-24-useafterfree.ll Mon Aug 30 05:48:29 2010 @@ -1,7 +1,7 @@ ; RUN: opt < %s -indvars ; PR4258 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" -target triple = "i386-linux-gnu" +target triple = "i386-pc-linux-gnu" define void @0(i32*, i32*, i32, i32) nounwind { br i1 false, label %bb.nph1.preheader, label %.outer._crit_edge Modified: llvm/trunk/test/Transforms/IndVarSimplify/loop_evaluate10.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/loop_evaluate10.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/Transforms/IndVarSimplify/loop_evaluate10.ll (original) +++ llvm/trunk/test/Transforms/IndVarSimplify/loop_evaluate10.ll Mon Aug 30 05:48:29 2010 @@ -5,7 +5,7 @@ ; exit is taken. Indvars should correctly compute the exit values. target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" -target triple = "x86_64-linux-gnu" +target triple = "x86_64-pc-linux-gnu" %struct..0anon = type <{ i8, [3 x i8] }> define i32 @main() nounwind { Modified: llvm/trunk/test/Transforms/LoopStrengthReduce/pr3571.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopStrengthReduce/pr3571.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/Transforms/LoopStrengthReduce/pr3571.ll (original) +++ llvm/trunk/test/Transforms/LoopStrengthReduce/pr3571.ll Mon Aug 30 05:48:29 2010 @@ -1,7 +1,7 @@ ; RUN: opt < %s -loop-reduce | llvm-dis ; PR3571 -target triple = "i386-mingw32" +target triple = "i386-pc-mingw32" define void @_ZNK18qdesigner_internal10TreeWidget12drawBranchesEP8QPainterRK5QRectRK11QModelIndex() nounwind { entry: br label %_ZNK11QModelIndex7isValidEv.exit.i Modified: llvm/trunk/test/Transforms/SimplifyCFG/2008-04-27-MultipleReturnCrash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/2008-04-27-MultipleReturnCrash.ll?rev=112469&r1=112468&r2=112469&view=diff ============================================================================== --- llvm/trunk/test/Transforms/SimplifyCFG/2008-04-27-MultipleReturnCrash.ll (original) +++ llvm/trunk/test/Transforms/SimplifyCFG/2008-04-27-MultipleReturnCrash.ll Mon Aug 30 05:48:29 2010 @@ -1,7 +1,7 @@ ; RUN: opt < %s -simplifycfg -disable-output ; PR2256 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" -target triple = "x86_64-mingw32" +target triple = "x86_64-pc-mingw32" define { x86_fp80, x86_fp80 } @catanl({ x86_fp80, x86_fp80 }* byval %Z, i1 %cond) nounwind { bb: ; preds = %entry From baldrick at free.fr Mon Aug 30 05:57:54 2010 From: baldrick at free.fr (Duncan Sands) Date: Mon, 30 Aug 2010 10:57:54 -0000 Subject: [llvm-commits] [llvm] r112470 - in /llvm/trunk: docs/ReleaseNotes.html lib/Support/Triple.cpp Message-ID: <20100830105754.440652A6C12C@llvm.org> Author: baldrick Date: Mon Aug 30 05:57:54 2010 New Revision: 112470 URL: http://llvm.org/viewvc/llvm-project?rev=112470&view=rev Log: Remove a hack that tries to understand incorrect triples from the Triple class constructor. Only valid triples should now be used inside LLVM - front-ends are now responsable for rejecting or correcting invalid target triples. The Triple::normalize method can be used to straighten out funky triples provided by users. Give this a whirl through the buildbots to see if I caught all places where triples enter LLVM. Modified: llvm/trunk/docs/ReleaseNotes.html llvm/trunk/lib/Support/Triple.cpp Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=112470&r1=112469&r2=112470&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Mon Aug 30 05:57:54 2010 @@ -348,6 +348,11 @@ SMDiagnostic takes different parameters now. //FIXME: how to upgrade?
  • + The constructor for the Triple class no longer tries to understand odd triple + specifications. Frontends should ensure that they only pass valid triples to + LLVM. The Triple::normalize utility method has been added to help front-ends + deal with funky triples. +
  • Some APIs got renamed:
    • llvm_report_error -> report_fatal_error
      • Modified: llvm/trunk/lib/Support/Triple.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Triple.cpp?rev=112470&r1=112469&r2=112470&view=diff ============================================================================== --- llvm/trunk/lib/Support/Triple.cpp (original) +++ llvm/trunk/lib/Support/Triple.cpp Mon Aug 30 05:57:54 2010 @@ -323,22 +323,6 @@ Vendor = ParseVendor(getVendorName()); OS = ParseOS(getOSName()); - // Handle some exceptional cases where the OS / environment components are - // stuck into the vendor field. - // TODO: Remove this logic and have places that need it use 'normalize'. - if (StringRef(getTriple()).count('-') == 1) { - StringRef VendorName = getVendorName(); - - if (VendorName.startswith("mingw32")) { // 'i386-mingw32', etc. - Vendor = PC; - OS = MinGW32; - return; - } - - // arm-elf is another example, but we don't currently parse anything about - // the environment. - } - assert(isInitialized() && "Failed to initialize!"); } From benny.kra at googlemail.com Mon Aug 30 06:56:55 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Mon, 30 Aug 2010 11:56:55 -0000 Subject: [llvm-commits] [llvm] r112471 - /llvm/trunk/lib/MC/MCELFStreamer.cpp Message-ID: <20100830115655.E06322A6C12C@llvm.org> Author: d0k Date: Mon Aug 30 06:56:55 2010 New Revision: 112471 URL: http://llvm.org/viewvc/llvm-project?rev=112471&view=rev Log: Mark all common symbols external. This is not exactly correct but it lets apps link for now and can be adjusted later. Patch by Roman Divacky. Modified: llvm/trunk/lib/MC/MCELFStreamer.cpp Modified: llvm/trunk/lib/MC/MCELFStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCELFStreamer.cpp?rev=112471&r1=112470&r2=112471&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCELFStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCELFStreamer.cpp Mon Aug 30 06:56:55 2010 @@ -249,10 +249,11 @@ SD.setFragment(F); Symbol->setSection(*Section); SD.setSize(MCConstantExpr::Create(Size, getContext())); - } else { - SD.setExternal(true); } + SD.setFlags(SD.getFlags() | ELF_STB_Global); + SD.setExternal(true); + SD.setCommon(Size, ByteAlignment); } From benny.kra at googlemail.com Mon Aug 30 06:59:29 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Mon, 30 Aug 2010 11:59:29 -0000 Subject: [llvm-commits] [llvm] r112472 - /llvm/trunk/lib/MC/ELFObjectWriter.cpp Message-ID: <20100830115929.8EEB82A6C12C@llvm.org> Author: d0k Date: Mon Aug 30 06:59:29 2010 New Revision: 112472 URL: http://llvm.org/viewvc/llvm-project?rev=112472&view=rev Log: Index external symbols by symbol table instead of parent section, by Roman Divacky. Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=112472&r1=112471&r2=112472&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Mon Aug 30 06:59:29 2010 @@ -470,7 +470,7 @@ MCFragment *F = SD.getFragment(); if (Base) { - if (F && (!Symbol->isInSection() || SD.isCommon())) { + if (F && (!Symbol->isInSection() || SD.isCommon()) && !SD.isExternal()) { Index = F->getParent()->getOrdinal() + LocalSymbolData.size() + 1; Value += Layout.getSymbolAddress(&SD); } else From benny.kra at googlemail.com Mon Aug 30 07:00:16 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Mon, 30 Aug 2010 12:00:16 -0000 Subject: [llvm-commits] [llvm] r112473 - /llvm/trunk/lib/MC/ELFObjectWriter.cpp Message-ID: <20100830120016.E09222A6C12C@llvm.org> Author: d0k Date: Mon Aug 30 07:00:16 2010 New Revision: 112473 URL: http://llvm.org/viewvc/llvm-project?rev=112473&view=rev Log: The value is offset from the start of the section for non-common symbols, submitted by Jordan Gordeev. Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=112473&r1=112472&r2=112473&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Mon Aug 30 07:00:16 2010 @@ -384,6 +384,8 @@ } } else if (ESize->getKind() == MCExpr::Constant) { Size = static_cast(ESize)->getValue(); + MCFragment *F = Data.getFragment(); + Value = Layout.getSymbolAddress(&Data) - Layout.getSectionAddress(F->getParent()); } else { assert(0 && "Unsupported size expression"); } From geek4civic at gmail.com Mon Aug 30 09:00:29 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Mon, 30 Aug 2010 14:00:29 -0000 Subject: [llvm-commits] [llvm] r112474 - /llvm/trunk/lib/ExecutionEngine/JIT/Intercept.cpp Message-ID: <20100830140029.A16DB2A6C12C@llvm.org> Author: chapuni Date: Mon Aug 30 09:00:29 2010 New Revision: 112474 URL: http://llvm.org/viewvc/llvm-project?rev=112474&view=rev Log: EE/JIT: Do not invoke parent's ctors/dtors from main()! (PR3897) On Mingw and Cygwin, the symbol __main is resolved to callee's(eg. tools/lli) one, to invoke wrong duplicated ctors (and register wrong callee's dtors with atexit(3)). We expect, by callee, ExecutionEngine::runStaticConstructorsDestructors() is called before ExecutionEngine::runFunctionAsMain() is called. Modified: llvm/trunk/lib/ExecutionEngine/JIT/Intercept.cpp Modified: llvm/trunk/lib/ExecutionEngine/JIT/Intercept.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/Intercept.cpp?rev=112474&r1=112473&r2=112474&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/JIT/Intercept.cpp (original) +++ llvm/trunk/lib/ExecutionEngine/JIT/Intercept.cpp Mon Aug 30 09:00:29 2010 @@ -89,6 +89,10 @@ return 0; // Always successful } +static int jit_noop() { + return 0; +} + //===----------------------------------------------------------------------===// // /// getPointerToNamedFunction - This method returns the address of the specified @@ -104,6 +108,14 @@ if (Name == "exit") return (void*)(intptr_t)&jit_exit; if (Name == "atexit") return (void*)(intptr_t)&jit_atexit; + // We shuold not invoke parent's ctors/dtors from main()! (PR3897) + // On Mingw and Cygwin, the symbol __main is resolved to + // callee's(eg. tools/lli) one, to invoke wrong duplicated ctors + // (and register wrong callee's dtors with atexit(3)). + // We expect ExecutionEngine::runStaticConstructorsDestructors() + // is called before ExecutionEngine::runFunctionAsMain() is called. + if (Name == "__main") return (void*)(intptr_t)&jit_noop; + const char *NameStr = Name.c_str(); // If this is an asm specifier, skip the sentinal. if (NameStr[0] == 1) ++NameStr; From geek4civic at gmail.com Mon Aug 30 09:12:07 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Mon, 30 Aug 2010 23:12:07 +0900 Subject: [llvm-commits] [PATCH] PR3897: suppress invoking __main() from JIT on Cygwin and Mingw In-Reply-To: References: Message-ID: committed as r112474. 2010/8/30 Anton Korobeynikov : >> EE/JIT: We don't want to invoke parent's ctors/dtors from main(), to fix PR3897. > Who and how will run them then? I told to Anton, on the IRC. We already have ExecutionEngine::runStaticConstructorsDestructors() to invoke ctors/dtors in bitcodes. __main did not invoke bitcode's ctors but parent's(callee context) ctors. ...Takumi From benny.kra at googlemail.com Mon Aug 30 09:46:54 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Mon, 30 Aug 2010 14:46:54 -0000 Subject: [llvm-commits] [llvm] r112479 - /llvm/trunk/lib/Analysis/AliasSetTracker.cpp Message-ID: <20100830144654.0AAEA2A6C12C@llvm.org> Author: d0k Date: Mon Aug 30 09:46:53 2010 New Revision: 112479 URL: http://llvm.org/viewvc/llvm-project?rev=112479&view=rev Log: Don't print two "0x" prefixes. Use a raw_ostream overload instead of llvm::format. Modified: llvm/trunk/lib/Analysis/AliasSetTracker.cpp Modified: llvm/trunk/lib/Analysis/AliasSetTracker.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasSetTracker.cpp?rev=112479&r1=112478&r2=112479&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/AliasSetTracker.cpp (original) +++ llvm/trunk/lib/Analysis/AliasSetTracker.cpp Mon Aug 30 09:46:53 2010 @@ -22,7 +22,6 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/InstIterator.h" -#include "llvm/Support/Format.h" #include "llvm/Support/raw_ostream.h" using namespace llvm; @@ -518,7 +517,7 @@ //===----------------------------------------------------------------------===// void AliasSet::print(raw_ostream &OS) const { - OS << " AliasSet[" << format("0x%p", (void*)this) << "," << RefCount << "] "; + OS << " AliasSet[" << (void*)this << ", " << RefCount << "] "; OS << (AliasTy == MustAlias ? "must" : "may") << " alias, "; switch (AccessTy) { case NoModRef: OS << "No access "; break; From bigcheesegs at gmail.com Mon Aug 30 09:49:00 2010 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Mon, 30 Aug 2010 14:49:00 -0000 Subject: [llvm-commits] [llvm] r112480 - in /llvm/trunk/test: CMakeLists.txt LLVMC/Alias.td LLVMC/AppendCmdHook.td LLVMC/EmptyCompilationGraph.td LLVMC/EnvParentheses.td LLVMC/ForwardAs.td LLVMC/ForwardTransformedValue.td LLVMC/ForwardValue.td LLVMC/HookWithArguments.td LLVMC/HookWithInFile.td LLVMC/Init.td LLVMC/LanguageMap.td LLVMC/MultiValuedOption.td LLVMC/MultipleCompilationGraphs.td LLVMC/NoActions.td LLVMC/NoCompilationGraph.td LLVMC/OneOrMore.td LLVMC/OptionPreprocessor.td LLVMC/OutputSuffixHook.td Makefile lit.cfg Message-ID: <20100830144900.B69BE2A6C12C@llvm.org> Author: mspencer Date: Mon Aug 30 09:49:00 2010 New Revision: 112480 URL: http://llvm.org/viewvc/llvm-project?rev=112480&view=rev Log: Test: Fix LLVMC tests on CMake. The CMake build didn't define TEST_COMPILE_CXX_CMD. The tests assumed gcc. Modified: llvm/trunk/test/CMakeLists.txt llvm/trunk/test/LLVMC/Alias.td llvm/trunk/test/LLVMC/AppendCmdHook.td llvm/trunk/test/LLVMC/EmptyCompilationGraph.td llvm/trunk/test/LLVMC/EnvParentheses.td llvm/trunk/test/LLVMC/ForwardAs.td llvm/trunk/test/LLVMC/ForwardTransformedValue.td llvm/trunk/test/LLVMC/ForwardValue.td llvm/trunk/test/LLVMC/HookWithArguments.td llvm/trunk/test/LLVMC/HookWithInFile.td llvm/trunk/test/LLVMC/Init.td llvm/trunk/test/LLVMC/LanguageMap.td llvm/trunk/test/LLVMC/MultiValuedOption.td llvm/trunk/test/LLVMC/MultipleCompilationGraphs.td llvm/trunk/test/LLVMC/NoActions.td llvm/trunk/test/LLVMC/NoCompilationGraph.td llvm/trunk/test/LLVMC/OneOrMore.td llvm/trunk/test/LLVMC/OptionPreprocessor.td llvm/trunk/test/LLVMC/OutputSuffixHook.td llvm/trunk/test/Makefile llvm/trunk/test/lit.cfg Modified: llvm/trunk/test/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CMakeLists.txt?rev=112480&r1=112479&r2=112480&view=diff ============================================================================== --- llvm/trunk/test/CMakeLists.txt (original) +++ llvm/trunk/test/CMakeLists.txt Mon Aug 30 09:49:00 2010 @@ -24,6 +24,23 @@ include(FindPythonInterp) if(PYTHONINTERP_FOUND) + get_directory_property(DEFINITIONS COMPILE_DEFINITIONS) + foreach(DEF ${DEFINITIONS}) + set(DEFS "${DEFS} -D${DEF}") + endforeach() + get_directory_property(INC_DIRS INCLUDE_DIRECTORIES) + foreach(INC_DIR ${INC_DIRS}) + set(IDIRS "${IDIRS} -I${INC_DIR}") + endforeach() + string(REPLACE "" "${CMAKE_CXX_COMPILER}" TEST_COMPILE_CXX_CMD ${CMAKE_CXX_COMPILE_OBJECT}) + string(REPLACE "" "${DEFS}" TEST_COMPILE_CXX_CMD ${TEST_COMPILE_CXX_CMD}) + string(REPLACE "" "${CMAKE_CXX_FLAGS}" TEST_COMPILE_CXX_CMD ${TEST_COMPILE_CXX_CMD}) + string(REPLACE "-o" "" TEST_COMPILE_CXX_CMD ${TEST_COMPILE_CXX_CMD}) + string(REGEX REPLACE "<[^>]+>" "" TEST_COMPILE_CXX_CMD ${TEST_COMPILE_CXX_CMD}) + set(TEST_COMPILE_CXX_CMD "${TEST_COMPILE_CXX_CMD} ${IDIRS}") + if(NOT MSVC) + set(TEST_COMPILE_CXX_CMD "${TEST_COMPILE_CXX_CMD} -x c++") + endif() configure_file( ${CMAKE_CURRENT_SOURCE_DIR}/site.exp.in ${CMAKE_CURRENT_BINARY_DIR}/site.exp) Modified: llvm/trunk/test/LLVMC/Alias.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/LLVMC/Alias.td?rev=112480&r1=112479&r2=112480&view=diff ============================================================================== --- llvm/trunk/test/LLVMC/Alias.td (original) +++ llvm/trunk/test/LLVMC/Alias.td Mon Aug 30 09:49:00 2010 @@ -1,7 +1,7 @@ // Test alias generation. // RUN: tblgen -I %p/../../include --gen-llvmc %s -o %t // RUN: FileCheck -input-file %t %s -// RUN: %compile_cxx -x c++ %t +// RUN: %compile_cxx %t // XFAIL: vg_leak include "llvm/CompilerDriver/Common.td" Modified: llvm/trunk/test/LLVMC/AppendCmdHook.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/LLVMC/AppendCmdHook.td?rev=112480&r1=112479&r2=112480&view=diff ============================================================================== --- llvm/trunk/test/LLVMC/AppendCmdHook.td (original) +++ llvm/trunk/test/LLVMC/AppendCmdHook.td Mon Aug 30 09:49:00 2010 @@ -1,7 +1,7 @@ // Check that hooks can be invoked from 'append_cmd'. // RUN: tblgen -I %p/../../include --gen-llvmc %s -o %t // RUN: FileCheck -input-file %t %s -// RUN: %compile_cxx -x c++ %t +// RUN: %compile_cxx %t // XFAIL: vg_leak include "llvm/CompilerDriver/Common.td" Modified: llvm/trunk/test/LLVMC/EmptyCompilationGraph.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/LLVMC/EmptyCompilationGraph.td?rev=112480&r1=112479&r2=112480&view=diff ============================================================================== --- llvm/trunk/test/LLVMC/EmptyCompilationGraph.td (original) +++ llvm/trunk/test/LLVMC/EmptyCompilationGraph.td Mon Aug 30 09:49:00 2010 @@ -1,6 +1,6 @@ // Check that the compilation graph can be empty. // RUN: tblgen -I %p/../../include --gen-llvmc %s -o %t -// RUN: %compile_cxx -x c++ %t +// RUN: %compile_cxx %t // XFAIL: vg_leak include "llvm/CompilerDriver/Common.td" Modified: llvm/trunk/test/LLVMC/EnvParentheses.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/LLVMC/EnvParentheses.td?rev=112480&r1=112479&r2=112480&view=diff ============================================================================== --- llvm/trunk/test/LLVMC/EnvParentheses.td (original) +++ llvm/trunk/test/LLVMC/EnvParentheses.td Mon Aug 30 09:49:00 2010 @@ -2,7 +2,7 @@ // http://llvm.org/bugs/show_bug.cgi?id=4157 // RUN: tblgen -I %p/../../include --gen-llvmc %s -o %t // RUN: not grep {FOO")));} %t -// RUN: %compile_cxx -x c++ %t +// RUN: %compile_cxx %t // XFAIL: vg_leak include "llvm/CompilerDriver/Common.td" Modified: llvm/trunk/test/LLVMC/ForwardAs.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/LLVMC/ForwardAs.td?rev=112480&r1=112479&r2=112480&view=diff ============================================================================== --- llvm/trunk/test/LLVMC/ForwardAs.td (original) +++ llvm/trunk/test/LLVMC/ForwardAs.td Mon Aug 30 09:49:00 2010 @@ -2,7 +2,7 @@ // http://llvm.org/bugs/show_bug.cgi?id=4159 // RUN: tblgen -I %p/../../include --gen-llvmc %s -o %t // RUN: FileCheck -input-file %t %s -// RUN: %compile_cxx -x c++ %t +// RUN: %compile_cxx %t // XFAIL: vg_leak include "llvm/CompilerDriver/Common.td" Modified: llvm/trunk/test/LLVMC/ForwardTransformedValue.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/LLVMC/ForwardTransformedValue.td?rev=112480&r1=112479&r2=112480&view=diff ============================================================================== --- llvm/trunk/test/LLVMC/ForwardTransformedValue.td (original) +++ llvm/trunk/test/LLVMC/ForwardTransformedValue.td Mon Aug 30 09:49:00 2010 @@ -2,7 +2,7 @@ // The dummy tool and graph are required to silence warnings. // RUN: tblgen -I %p/../../include --gen-llvmc %s -o %t // RUN: FileCheck -input-file %t %s -// RUN: %compile_cxx -x c++ %t +// RUN: %compile_cxx %t // XFAIL: vg_leak include "llvm/CompilerDriver/Common.td" Modified: llvm/trunk/test/LLVMC/ForwardValue.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/LLVMC/ForwardValue.td?rev=112480&r1=112479&r2=112480&view=diff ============================================================================== --- llvm/trunk/test/LLVMC/ForwardValue.td (original) +++ llvm/trunk/test/LLVMC/ForwardValue.td Mon Aug 30 09:49:00 2010 @@ -2,7 +2,7 @@ // The dummy tool and graph are required to silence warnings. // RUN: tblgen -I %p/../../include --gen-llvmc %s -o %t // RUN: FileCheck -input-file %t %s -// RUN: %compile_cxx -x c++ %t +// RUN: %compile_cxx %t // XFAIL: vg_leak include "llvm/CompilerDriver/Common.td" Modified: llvm/trunk/test/LLVMC/HookWithArguments.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/LLVMC/HookWithArguments.td?rev=112480&r1=112479&r2=112480&view=diff ============================================================================== --- llvm/trunk/test/LLVMC/HookWithArguments.td (original) +++ llvm/trunk/test/LLVMC/HookWithArguments.td Mon Aug 30 09:49:00 2010 @@ -1,7 +1,7 @@ // Check that hooks with arguments work. // RUN: tblgen -I %p/../../include --gen-llvmc %s -o %t // RUN: FileCheck -input-file %t %s -// RUN: %compile_cxx -x c++ %t +// RUN: %compile_cxx %t // XFAIL: vg_leak include "llvm/CompilerDriver/Common.td" Modified: llvm/trunk/test/LLVMC/HookWithInFile.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/LLVMC/HookWithInFile.td?rev=112480&r1=112479&r2=112480&view=diff ============================================================================== --- llvm/trunk/test/LLVMC/HookWithInFile.td (original) +++ llvm/trunk/test/LLVMC/HookWithInFile.td Mon Aug 30 09:49:00 2010 @@ -1,7 +1,7 @@ // Check that a hook can be given $INFILE as an argument. // RUN: tblgen -I %p/../../include --gen-llvmc %s -o %t // RUN: FileCheck -input-file %t %s -// RUN: %compile_cxx -x c++ %t +// RUN: %compile_cxx %t // XFAIL: vg_leak include "llvm/CompilerDriver/Common.td" Modified: llvm/trunk/test/LLVMC/Init.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/LLVMC/Init.td?rev=112480&r1=112479&r2=112480&view=diff ============================================================================== --- llvm/trunk/test/LLVMC/Init.td (original) +++ llvm/trunk/test/LLVMC/Init.td Mon Aug 30 09:49:00 2010 @@ -1,7 +1,7 @@ // Check that (init true/false) and (init "str") work. // RUN: tblgen -I %p/../../include --gen-llvmc %s -o %t // RUN: FileCheck -input-file %t %s -// RUN: %compile_cxx -x c++ %t +// RUN: %compile_cxx %t // XFAIL: vg_leak include "llvm/CompilerDriver/Common.td" Modified: llvm/trunk/test/LLVMC/LanguageMap.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/LLVMC/LanguageMap.td?rev=112480&r1=112479&r2=112480&view=diff ============================================================================== --- llvm/trunk/test/LLVMC/LanguageMap.td (original) +++ llvm/trunk/test/LLVMC/LanguageMap.td Mon Aug 30 09:49:00 2010 @@ -1,7 +1,7 @@ // Check that LanguageMap is processed properly. // RUN: tblgen -I %p/../../include --gen-llvmc %s -o %t // RUN: FileCheck -input-file %t %s -// RUN: %compile_cxx -x c++ %t +// RUN: %compile_cxx %t // XFAIL: vg_leak include "llvm/CompilerDriver/Common.td" Modified: llvm/trunk/test/LLVMC/MultiValuedOption.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/LLVMC/MultiValuedOption.td?rev=112480&r1=112479&r2=112480&view=diff ============================================================================== --- llvm/trunk/test/LLVMC/MultiValuedOption.td (original) +++ llvm/trunk/test/LLVMC/MultiValuedOption.td Mon Aug 30 09:49:00 2010 @@ -2,7 +2,7 @@ // The dummy tool and graph are required to silence warnings. // RUN: tblgen -I %p/../../include --gen-llvmc %s -o %t // RUN: FileCheck -input-file %t %s -// RUN: %compile_cxx -x c++ %t +// RUN: %compile_cxx %t // XFAIL: vg_leak include "llvm/CompilerDriver/Common.td" Modified: llvm/trunk/test/LLVMC/MultipleCompilationGraphs.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/LLVMC/MultipleCompilationGraphs.td?rev=112480&r1=112479&r2=112480&view=diff ============================================================================== --- llvm/trunk/test/LLVMC/MultipleCompilationGraphs.td (original) +++ llvm/trunk/test/LLVMC/MultipleCompilationGraphs.td Mon Aug 30 09:49:00 2010 @@ -1,6 +1,6 @@ // Check that multiple compilation graphs are allowed. // RUN: tblgen -I %p/../../include --gen-llvmc %s -o %t -// RUN: %compile_cxx -x c++ %t +// RUN: %compile_cxx %t // XFAIL: vg_leak include "llvm/CompilerDriver/Common.td" Modified: llvm/trunk/test/LLVMC/NoActions.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/LLVMC/NoActions.td?rev=112480&r1=112479&r2=112480&view=diff ============================================================================== --- llvm/trunk/test/LLVMC/NoActions.td (original) +++ llvm/trunk/test/LLVMC/NoActions.td Mon Aug 30 09:49:00 2010 @@ -1,7 +1,7 @@ // Check that tools without associated actions are accepted. // RUN: tblgen -I %p/../../include --gen-llvmc %s -o %t // RUN: FileCheck -input-file %t %s -// RUN: %compile_cxx -x c++ %t +// RUN: %compile_cxx %t // XFAIL: vg_leak include "llvm/CompilerDriver/Common.td" Modified: llvm/trunk/test/LLVMC/NoCompilationGraph.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/LLVMC/NoCompilationGraph.td?rev=112480&r1=112479&r2=112480&view=diff ============================================================================== --- llvm/trunk/test/LLVMC/NoCompilationGraph.td (original) +++ llvm/trunk/test/LLVMC/NoCompilationGraph.td Mon Aug 30 09:49:00 2010 @@ -1,6 +1,6 @@ // Check that the compilation graph is not required. // RUN: tblgen -I %p/../../include --gen-llvmc %s -o %t -// RUN: %compile_cxx -x c++ %t +// RUN: %compile_cxx %t // XFAIL: vg_leak include "llvm/CompilerDriver/Common.td" Modified: llvm/trunk/test/LLVMC/OneOrMore.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/LLVMC/OneOrMore.td?rev=112480&r1=112479&r2=112480&view=diff ============================================================================== --- llvm/trunk/test/LLVMC/OneOrMore.td (original) +++ llvm/trunk/test/LLVMC/OneOrMore.td Mon Aug 30 09:49:00 2010 @@ -2,7 +2,7 @@ // The dummy tool and graph are required to silence warnings. // RUN: tblgen -I %p/../../include --gen-llvmc %s -o %t // RUN: FileCheck -input-file %t %s -// RUN: %compile_cxx -x c++ %t +// RUN: %compile_cxx %t // XFAIL: vg_leak include "llvm/CompilerDriver/Common.td" Modified: llvm/trunk/test/LLVMC/OptionPreprocessor.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/LLVMC/OptionPreprocessor.td?rev=112480&r1=112479&r2=112480&view=diff ============================================================================== --- llvm/trunk/test/LLVMC/OptionPreprocessor.td (original) +++ llvm/trunk/test/LLVMC/OptionPreprocessor.td Mon Aug 30 09:49:00 2010 @@ -1,7 +1,7 @@ // Test for the OptionPreprocessor and related functionality. // RUN: tblgen -I %p/../../include --gen-llvmc %s -o %t // RUN: FileCheck -input-file %t %s -// RUN: %compile_cxx -x c++ %t +// RUN: %compile_cxx %t // XFAIL: vg_leak include "llvm/CompilerDriver/Common.td" Modified: llvm/trunk/test/LLVMC/OutputSuffixHook.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/LLVMC/OutputSuffixHook.td?rev=112480&r1=112479&r2=112480&view=diff ============================================================================== --- llvm/trunk/test/LLVMC/OutputSuffixHook.td (original) +++ llvm/trunk/test/LLVMC/OutputSuffixHook.td Mon Aug 30 09:49:00 2010 @@ -1,7 +1,7 @@ // Check that hooks can be invoked from 'output_suffix'. // RUN: tblgen -I %p/../../include --gen-llvmc %s -o %t // RUN: FileCheck -input-file %t %s -// RUN: %compile_cxx -x c++ %t +// RUN: %compile_cxx %t // XFAIL: vg_leak include "llvm/CompilerDriver/Common.td" Modified: llvm/trunk/test/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Makefile?rev=112480&r1=112479&r2=112480&view=diff ============================================================================== --- llvm/trunk/test/Makefile (original) +++ llvm/trunk/test/Makefile Mon Aug 30 09:49:00 2010 @@ -145,8 +145,8 @@ @echo 'set objdir "$(LLVM_OBJ_ROOT)/test"' >>site.tmp @echo 'set gccpath "$(CC)"' >>site.tmp @echo 'set gxxpath "$(CXX)"' >>site.tmp - @echo 'set compile_c "' $(CC) $(CPP.Flags) $(TargetCommonOpts) $(CompileCommonOpts) -c '"' >>site.tmp - @echo 'set compile_cxx "' $(CXX) $(CPP.Flags) $(CXX.Flags) $(TargetCommonOpts) $(CompileCommonOpts) -c '"' >> site.tmp + @echo 'set compile_c "' $(CC) $(CPP.Flags) $(TargetCommonOpts) $(CompileCommonOpts) -c -x c '"' >>site.tmp + @echo 'set compile_cxx "' $(CXX) $(CPP.Flags) $(CXX.Flags) $(TargetCommonOpts) $(CompileCommonOpts) -c -x c++ '"' >> site.tmp @echo 'set link "' $(CXX) $(CPP.Flags) $(CXX.Flags) $(TargetCommonOpts) $(CompileCommonOpts) $(LD.Flags) '"' >>site.tmp @echo 'set llvmgcc "$(LLVMGCC) $(TargetCommonOpts) $(EXTRA_OPTIONS)"' >> site.tmp @echo 'set llvmgxx "$(LLVMGCC) $(TargetCommonOpts) $(EXTRA_OPTIONS)"' >> site.tmp Modified: llvm/trunk/test/lit.cfg URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/lit.cfg?rev=112480&r1=112479&r2=112480&view=diff ============================================================================== --- llvm/trunk/test/lit.cfg (original) +++ llvm/trunk/test/lit.cfg Mon Aug 30 09:49:00 2010 @@ -49,6 +49,14 @@ if 'HOME' in os.environ: config.environment['HOME'] = os.environ['HOME'] +# Propogate 'INCLUDE' through the environment. +if 'INCLUDE' in os.environ: + config.environment['INCLUDE'] = os.environ['INCLUDE'] + +# Propogate 'LIB' through the environment. +if 'LIB' in os.environ: + config.environment['LIB'] = os.environ['LIB'] + # Propogate LLVM_SRC_ROOT into the environment. config.environment['LLVM_SRC_ROOT'] = getattr(config, 'llvm_src_root', '') From bigcheesegs at gmail.com Mon Aug 30 10:08:02 2010 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Mon, 30 Aug 2010 15:08:02 -0000 Subject: [llvm-commits] [llvm] r112483 - /llvm/trunk/test/Analysis/BasicAA/constant-over-index.ll Message-ID: <20100830150803.03B7F2A6C12C@llvm.org> Author: mspencer Date: Mon Aug 30 10:08:02 2010 New Revision: 112483 URL: http://llvm.org/viewvc/llvm-project?rev=112483&view=rev Log: Fix constant-over-index.ll test on windows. Modified: llvm/trunk/test/Analysis/BasicAA/constant-over-index.ll Modified: llvm/trunk/test/Analysis/BasicAA/constant-over-index.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/BasicAA/constant-over-index.ll?rev=112483&r1=112482&r2=112483&view=diff ============================================================================== --- llvm/trunk/test/Analysis/BasicAA/constant-over-index.ll (original) +++ llvm/trunk/test/Analysis/BasicAA/constant-over-index.ll Mon Aug 30 10:08:02 2010 @@ -1,7 +1,8 @@ -; RUN: opt < %s -aa-eval -print-all-alias-modref-info \ -; RUN: |& grep {MayAlias: double\\* \[%\]p.0.i.0, double\\* \[%\]p3\$} +; RUN: opt < %s -aa-eval -print-all-alias-modref-info |& FileCheck %s ; PR4267 +; CHECK: MayAlias: double* %p.0.i.0, double* %p3 + ; %p3 is equal to %p.0.i.0 on the second iteration of the loop, ; so MayAlias is needed. From grosbach at apple.com Mon Aug 30 10:14:33 2010 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 30 Aug 2010 08:14:33 -0700 Subject: [llvm-commits] [llvm] r112322 - in /llvm/trunk: lib/Target/ARM/ARMAddressingModes.h lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMCodeEmitter.cpp lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/ARM/ARMInstrNEON.td lib/Target/ARM/ARMInstrVFP.td lib/Target/ARM/ARMLoadStoreOptimizer.cpp lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp test/CodeGen/ARM/vst3.ll In-Reply-To: <20100827231817.A14EF2A6C12C@llvm.org> References: <20100827231817.A14EF2A6C12C@llvm.org> Message-ID: Very nice! Glad to see this worked out cleanly. -jim On Aug 27, 2010, at 4:18 PM, Bob Wilson wrote: > Author: bwilson > Date: Fri Aug 27 18:18:17 2010 > New Revision: 112322 > > URL: http://llvm.org/viewvc/llvm-project?rev=112322&view=rev > Log: > Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just like > all the other LDM/STM instructions. This fixes asm printer crashes when > compiling with -O0. I've changed one of the NEON tests (vst3.ll) to run > with -O0 to check this in the future. > > Prior to this change VLDM/VSTM used addressing mode #5, but not really. > The offset field was used to hold a count of the number of registers being > loaded or stored, and the AM5 opcode field was expanded to specify the IA > or DB mode, instead of the standard ADD/SUB specifier. Much of the backend > was not aware of these special cases. The crashes occured when rewriting > a frameindex caused the AM5 offset field to be changed so that it did not > have a valid submode. I don't know exactly what changed to expose this now. > Maybe we've never done much with -O0 and NEON. Regardless, there's no longer > any reason to keep a count of the VLDM/VSTM registers, so we can use > addressing mode #4 and clean things up in a lot of places. > > Modified: > llvm/trunk/lib/Target/ARM/ARMAddressingModes.h > llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp > llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp > llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp > llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp > llvm/trunk/lib/Target/ARM/ARMInstrNEON.td > llvm/trunk/lib/Target/ARM/ARMInstrVFP.td > llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp > llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp > llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp > llvm/trunk/test/CodeGen/ARM/vst3.ll > > Modified: llvm/trunk/lib/Target/ARM/ARMAddressingModes.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAddressingModes.h?rev=112322&r1=112321&r2=112322&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMAddressingModes.h (original) > +++ llvm/trunk/lib/Target/ARM/ARMAddressingModes.h Fri Aug 27 18:18:17 2010 > @@ -458,6 +458,7 @@ > // IB - Increment before > // DA - Decrement after > // DB - Decrement before > + // For VFP instructions, only the IA and DB modes are valid. > > static inline AMSubMode getAM4SubMode(unsigned Mode) { > return (AMSubMode)(Mode & 0x7); > @@ -477,14 +478,6 @@ > // > // The first operand is always a Reg. The second operand encodes the > // operation in bit 8 and the immediate in bits 0-7. > - // > - // This is also used for FP load/store multiple ops. The second operand > - // encodes the number of registers (or 2 times the number of registers > - // for DPR ops) in bits 0-7. In addition, bits 8-10 encode one of the > - // following two sub-modes: > - // > - // IA - Increment after > - // DB - Decrement before > > /// getAM5Opc - This function encodes the addrmode5 opc field. > static inline unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset) { > @@ -498,17 +491,6 @@ > return ((AM5Opc >> 8) & 1) ? sub : add; > } > > - /// getAM5Opc - This function encodes the addrmode5 opc field for VLDM and > - /// VSTM instructions. > - static inline unsigned getAM5Opc(AMSubMode SubMode, unsigned char Offset) { > - assert((SubMode == ia || SubMode == db) && > - "Illegal addressing mode 5 sub-mode!"); > - return ((int)SubMode << 8) | Offset; > - } > - static inline AMSubMode getAM5SubMode(unsigned AM5Opc) { > - return (AMSubMode)((AM5Opc >> 8) & 0x7); > - } > - > //===--------------------------------------------------------------------===// > // Addressing Mode #6 > //===--------------------------------------------------------------------===// > > Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=112322&r1=112321&r2=112322&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Fri Aug 27 18:18:17 2010 > @@ -607,16 +607,6 @@ > > assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg())); > > - if (Modifier && strcmp(Modifier, "submode") == 0) { > - ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm()); > - O << ARM_AM::getAMSubModeStr(Mode); > - return; > - } else if (Modifier && strcmp(Modifier, "base") == 0) { > - // Used for FSTM{D|S} and LSTM{D|S} operations. > - O << getRegisterName(MO1.getReg()); > - return; > - } > - > O << "[" << getRegisterName(MO1.getReg()); > > if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) { > > Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=112322&r1=112321&r2=112322&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Fri Aug 27 18:18:17 2010 > @@ -757,7 +757,7 @@ > AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQ)) > .addReg(SrcReg, getKillRegState(isKill)) > .addFrameIndex(FI) > - .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)) > + .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia)) > .addMemOperand(MMO)); > } > break; > @@ -777,7 +777,7 @@ > MachineInstrBuilder MIB = > AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD)) > .addFrameIndex(FI) > - .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))) > + .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia))) > .addMemOperand(MMO); > MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); > MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); > @@ -789,7 +789,7 @@ > MachineInstrBuilder MIB = > AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD)) > .addFrameIndex(FI) > - .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))) > + .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia))) > .addMemOperand(MMO); > MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); > MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); > @@ -853,7 +853,7 @@ > } else { > AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQ), DestReg) > .addFrameIndex(FI) > - .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)) > + .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia)) > .addMemOperand(MMO)); > } > break; > @@ -870,7 +870,7 @@ > MachineInstrBuilder MIB = > AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD)) > .addFrameIndex(FI) > - .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))) > + .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia))) > .addMemOperand(MMO); > MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI); > MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI); > @@ -882,7 +882,7 @@ > MachineInstrBuilder MIB = > AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD)) > .addFrameIndex(FI) > - .addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))) > + .addImm(ARM_AM::getAM4ModeImm(ARM_AM::ia))) > .addMemOperand(MMO); > MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI); > MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI); > > Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=112322&r1=112321&r2=112322&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Fri Aug 27 18:18:17 2010 > @@ -1549,7 +1549,7 @@ > > // Set addressing mode by modifying bits U(23) and P(24) > const MachineOperand &MO = MI.getOperand(OpIdx++); > - Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm())); > + Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm())); > > // Set bit W(21) > if (IsUpdating) > @@ -1558,7 +1558,7 @@ > // First register is encoded in Dd. > Binary |= encodeVFPRd(MI, OpIdx+2); > > - // Number of registers are encoded in offset field. > + // Count the number of registers. > unsigned NumRegs = 1; > for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) { > const MachineOperand &MO = MI.getOperand(i); > > Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=112322&r1=112321&r2=112322&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Fri Aug 27 18:18:17 2010 > @@ -2052,15 +2052,15 @@ > if (ResNode) > return ResNode; > > - // VLDMQ must be custom-selected for "v2f64 load" to set the AM5Opc value. > + // VLDMQ must be custom-selected for "v2f64 load" to set the AM4 value. > if (Subtarget->hasVFP2() && > N->getValueType(0).getSimpleVT().SimpleTy == MVT::v2f64) { > SDValue Chain = N->getOperand(0); > - SDValue AM5Opc = > - CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::ia, 4), MVT::i32); > + SDValue AM4Imm = > + CurDAG->getTargetConstant(ARM_AM::getAM4ModeImm(ARM_AM::ia), MVT::i32); > SDValue Pred = getAL(CurDAG); > SDValue PredReg = CurDAG->getRegister(0, MVT::i32); > - SDValue Ops[] = { N->getOperand(1), AM5Opc, Pred, PredReg, Chain }; > + SDValue Ops[] = { N->getOperand(1), AM4Imm, Pred, PredReg, Chain }; > MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); > MemOp[0] = cast(N)->getMemOperand(); > SDNode *Ret = CurDAG->getMachineNode(ARM::VLDMQ, dl, > @@ -2072,16 +2072,16 @@ > break; > } > case ISD::STORE: { > - // VSTMQ must be custom-selected for "v2f64 store" to set the AM5Opc value. > + // VSTMQ must be custom-selected for "v2f64 store" to set the AM4 value. > if (Subtarget->hasVFP2() && > N->getOperand(1).getValueType().getSimpleVT().SimpleTy == MVT::v2f64) { > SDValue Chain = N->getOperand(0); > - SDValue AM5Opc = > - CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::ia, 4), MVT::i32); > + SDValue AM4Imm = > + CurDAG->getTargetConstant(ARM_AM::getAM4ModeImm(ARM_AM::ia), MVT::i32); > SDValue Pred = getAL(CurDAG); > SDValue PredReg = CurDAG->getRegister(0, MVT::i32); > SDValue Ops[] = { N->getOperand(1), N->getOperand(2), > - AM5Opc, Pred, PredReg, Chain }; > + AM4Imm, Pred, PredReg, Chain }; > MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); > MemOp[0] = cast(N)->getMemOperand(); > SDNode *Ret = CurDAG->getMachineNode(ARM::VSTMQ, dl, MVT::Other, Ops, 6); > > Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=112322&r1=112321&r2=112322&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) > +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Fri Aug 27 18:18:17 2010 > @@ -129,9 +129,9 @@ > // This is equivalent to VLDMD except that it has a Q register operand > // instead of a pair of D registers. > def VLDMQ > - : AXDI5<(outs QPR:$dst), (ins addrmode5:$addr, pred:$p), > + : AXDI5<(outs QPR:$dst), (ins addrmode4:$addr, pred:$p), > IndexModeNone, IIC_fpLoadm, > - "vldm${addr:submode}${p}\t${addr:base}, ${dst:dregpair}", "", []>; > + "vldm${addr:submode}${p}\t$addr, ${dst:dregpair}", "", []>; > > // Use vld1 to load a Q register as a D register pair. > // This alternative to VLDMQ allows an alignment to be specified. > @@ -146,9 +146,9 @@ > // This is equivalent to VSTMD except that it has a Q register operand > // instead of a pair of D registers. > def VSTMQ > - : AXDI5<(outs), (ins QPR:$src, addrmode5:$addr, pred:$p), > + : AXDI5<(outs), (ins QPR:$src, addrmode4:$addr, pred:$p), > IndexModeNone, IIC_fpStorem, > - "vstm${addr:submode}${p}\t${addr:base}, ${src:dregpair}", "", []>; > + "vstm${addr:submode}${p}\t$addr, ${src:dregpair}", "", []>; > > // Use vst1 to store a Q register as a D register pair. > // This alternative to VSTMQ allows an alignment to be specified. > > Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=112322&r1=112321&r2=112322&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original) > +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Fri Aug 27 18:18:17 2010 > @@ -77,61 +77,61 @@ > // > > let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in { > -def VLDMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dsts, > +def VLDMD : AXDI5<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts, > variable_ops), IndexModeNone, IIC_fpLoadm, > - "vldm${addr:submode}${p}\t${addr:base}, $dsts", "", []> { > + "vldm${addr:submode}${p}\t$addr, $dsts", "", []> { > let Inst{20} = 1; > } > > -def VLDMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dsts, > +def VLDMS : AXSI5<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts, > variable_ops), IndexModeNone, IIC_fpLoadm, > - "vldm${addr:submode}${p}\t${addr:base}, $dsts", "", []> { > + "vldm${addr:submode}${p}\t$addr, $dsts", "", []> { > let Inst{20} = 1; > } > > -def VLDMD_UPD : AXDI5<(outs GPR:$wb), (ins addrmode5:$addr, pred:$p, > +def VLDMD_UPD : AXDI5<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, > reglist:$dsts, variable_ops), > IndexModeUpd, IIC_fpLoadm, > - "vldm${addr:submode}${p}\t${addr:base}!, $dsts", > - "$addr.base = $wb", []> { > + "vldm${addr:submode}${p}\t$addr!, $dsts", > + "$addr.addr = $wb", []> { > let Inst{20} = 1; > } > > -def VLDMS_UPD : AXSI5<(outs GPR:$wb), (ins addrmode5:$addr, pred:$p, > +def VLDMS_UPD : AXSI5<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, > reglist:$dsts, variable_ops), > IndexModeUpd, IIC_fpLoadm, > - "vldm${addr:submode}${p}\t${addr:base}!, $dsts", > - "$addr.base = $wb", []> { > + "vldm${addr:submode}${p}\t$addr!, $dsts", > + "$addr.addr = $wb", []> { > let Inst{20} = 1; > } > } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq > > let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in { > -def VSTMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$srcs, > +def VSTMD : AXDI5<(outs), (ins addrmode4:$addr, pred:$p, reglist:$srcs, > variable_ops), IndexModeNone, IIC_fpStorem, > - "vstm${addr:submode}${p}\t${addr:base}, $srcs", "", []> { > + "vstm${addr:submode}${p}\t$addr, $srcs", "", []> { > let Inst{20} = 0; > } > > -def VSTMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$srcs, > +def VSTMS : AXSI5<(outs), (ins addrmode4:$addr, pred:$p, reglist:$srcs, > variable_ops), IndexModeNone, IIC_fpStorem, > - "vstm${addr:submode}${p}\t${addr:base}, $srcs", "", []> { > + "vstm${addr:submode}${p}\t$addr, $srcs", "", []> { > let Inst{20} = 0; > } > > -def VSTMD_UPD : AXDI5<(outs GPR:$wb), (ins addrmode5:$addr, pred:$p, > +def VSTMD_UPD : AXDI5<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, > reglist:$srcs, variable_ops), > IndexModeUpd, IIC_fpStorem, > - "vstm${addr:submode}${p}\t${addr:base}!, $srcs", > - "$addr.base = $wb", []> { > + "vstm${addr:submode}${p}\t$addr!, $srcs", > + "$addr.addr = $wb", []> { > let Inst{20} = 0; > } > > -def VSTMS_UPD : AXSI5<(outs GPR:$wb), (ins addrmode5:$addr, pred:$p, > +def VSTMS_UPD : AXSI5<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, > reglist:$srcs, variable_ops), > IndexModeUpd, IIC_fpStorem, > - "vstm${addr:submode}${p}\t${addr:base}!, $srcs", > - "$addr.base = $wb", []> { > + "vstm${addr:submode}${p}\t$addr!, $srcs", > + "$addr.addr = $wb", []> { > let Inst{20} = 0; > } > } // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq > > Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=112322&r1=112321&r2=112322&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Fri Aug 27 18:18:17 2010 > @@ -193,18 +193,18 @@ > return false; > > ARM_AM::AMSubMode Mode = ARM_AM::ia; > - bool isAM4 = isi32Load(Opcode) || isi32Store(Opcode); > - if (isAM4 && Offset == 4) { > + bool isNotVFP = isi32Load(Opcode) || isi32Store(Opcode); > + if (isNotVFP && Offset == 4) { > if (isThumb2) > // Thumb2 does not support ldmib / stmib. > return false; > Mode = ARM_AM::ib; > - } else if (isAM4 && Offset == -4 * (int)NumRegs + 4) { > + } else if (isNotVFP && Offset == -4 * (int)NumRegs + 4) { > if (isThumb2) > // Thumb2 does not support ldmda / stmda. > return false; > Mode = ARM_AM::da; > - } else if (isAM4 && Offset == -4 * (int)NumRegs) { > + } else if (isNotVFP && Offset == -4 * (int)NumRegs) { > Mode = ARM_AM::db; > } else if (Offset != 0) { > // If starting offset isn't zero, insert a MI to materialize a new base. > @@ -246,18 +246,12 @@ > BaseKill = true; // New base is always killed right its use. > } > > - bool isDPR = (Opcode == ARM::VLDRD || Opcode == ARM::VSTRD); > bool isDef = (isi32Load(Opcode) || Opcode == ARM::VLDRS || > Opcode == ARM::VLDRD); > Opcode = getLoadStoreMultipleOpcode(Opcode); > - MachineInstrBuilder MIB = (isAM4) > - ? BuildMI(MBB, MBBI, dl, TII->get(Opcode)) > - .addReg(Base, getKillRegState(BaseKill)) > - .addImm(ARM_AM::getAM4ModeImm(Mode)).addImm(Pred).addReg(PredReg) > - : BuildMI(MBB, MBBI, dl, TII->get(Opcode)) > - .addReg(Base, getKillRegState(BaseKill)) > - .addImm(ARM_AM::getAM5Opc(Mode, isDPR ? NumRegs<<1 : NumRegs)) > - .addImm(Pred).addReg(PredReg); > + MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(Opcode)) > + .addReg(Base, getKillRegState(BaseKill)) > + .addImm(ARM_AM::getAM4ModeImm(Mode)).addImm(Pred).addReg(PredReg); > for (unsigned i = 0; i != NumRegs; ++i) > MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef) > | getKillRegState(Regs[i].second)); > @@ -348,7 +342,7 @@ > ARMCC::CondCodes Pred, unsigned PredReg, > unsigned Scratch, MemOpQueue &MemOps, > SmallVector &Merges) { > - bool isAM4 = isi32Load(Opcode) || isi32Store(Opcode); > + bool isNotVFP = isi32Load(Opcode) || isi32Store(Opcode); > int Offset = MemOps[SIndex].Offset; > int SOffset = Offset; > unsigned insertAfter = SIndex; > @@ -366,12 +360,12 @@ > unsigned Reg = MO.getReg(); > unsigned RegNum = MO.isUndef() ? UINT_MAX > : ARMRegisterInfo::getRegisterNumbering(Reg); > - // AM4 - register numbers in ascending order. > - // AM5 - consecutive register numbers in ascending order. > - // Can only do up to 16 double-word registers per insn. > + // Register numbers must be in ascending order. For VFP, the registers > + // must also be consecutive and there is a limit of 16 double-word > + // registers per instruction. > if (Reg != ARM::SP && > NewOffset == Offset + (int)Size && > - ((isAM4 && RegNum > PRegNum) > + ((isNotVFP && RegNum > PRegNum) > || ((Size < 8 || Count < 16) && RegNum == PRegNum+1))) { > Offset += Size; > PRegNum = RegNum; > @@ -464,12 +458,11 @@ > case ARM::STM: > case ARM::t2LDM: > case ARM::t2STM: > - return (MI->getNumOperands() - 4) * 4; > case ARM::VLDMS: > case ARM::VSTMS: > case ARM::VLDMD: > case ARM::VSTMD: > - return ARM_AM::getAM5Offset(MI->getOperand(1).getImm()) * 4; > + return (MI->getNumOperands() - 4) * 4; > } > } > > @@ -512,26 +505,17 @@ > ARMCC::CondCodes Pred = llvm::getInstrPredicate(MI, PredReg); > int Opcode = MI->getOpcode(); > DebugLoc dl = MI->getDebugLoc(); > - bool isAM4 = (Opcode == ARM::LDM || Opcode == ARM::t2LDM || > - Opcode == ARM::STM || Opcode == ARM::t2STM); > > bool DoMerge = false; > ARM_AM::AMSubMode Mode = ARM_AM::ia; > - unsigned Offset = 0; > > - if (isAM4) { > - // Can't use an updating ld/st if the base register is also a dest > - // register. e.g. ldmdb r0!, {r0, r1, r2}. The behavior is undefined. > - for (unsigned i = 3, e = MI->getNumOperands(); i != e; ++i) { > - if (MI->getOperand(i).getReg() == Base) > - return false; > - } > - Mode = ARM_AM::getAM4SubMode(MI->getOperand(1).getImm()); > - } else { > - // VLDM{D|S}, VSTM{D|S} addressing mode 5 ops. > - Mode = ARM_AM::getAM5SubMode(MI->getOperand(1).getImm()); > - Offset = ARM_AM::getAM5Offset(MI->getOperand(1).getImm()); > + // Can't use an updating ld/st if the base register is also a dest > + // register. e.g. ldmdb r0!, {r0, r1, r2}. The behavior is undefined. > + for (unsigned i = 3, e = MI->getNumOperands(); i != e; ++i) { > + if (MI->getOperand(i).getReg() == Base) > + return false; > } > + Mode = ARM_AM::getAM4SubMode(MI->getOperand(1).getImm()); > > // Try merging with the previous instruction. > MachineBasicBlock::iterator BeginMBBI = MBB.begin(); > @@ -539,22 +523,14 @@ > MachineBasicBlock::iterator PrevMBBI = prior(MBBI); > while (PrevMBBI != BeginMBBI && PrevMBBI->isDebugValue()) > --PrevMBBI; > - if (isAM4) { > - if (Mode == ARM_AM::ia && > - isMatchingDecrement(PrevMBBI, Base, Bytes, 0, Pred, PredReg)) { > - DoMerge = true; > - Mode = ARM_AM::db; > - } else if (isAM4 && Mode == ARM_AM::ib && > - isMatchingDecrement(PrevMBBI, Base, Bytes, 0, Pred, PredReg)) { > - DoMerge = true; > - Mode = ARM_AM::da; > - } > - } else { > - if (Mode == ARM_AM::ia && > - isMatchingDecrement(PrevMBBI, Base, Bytes, 0, Pred, PredReg)) { > - Mode = ARM_AM::db; > - DoMerge = true; > - } > + if (Mode == ARM_AM::ia && > + isMatchingDecrement(PrevMBBI, Base, Bytes, 0, Pred, PredReg)) { > + Mode = ARM_AM::db; > + DoMerge = true; > + } else if (Mode == ARM_AM::ib && > + isMatchingDecrement(PrevMBBI, Base, Bytes, 0, Pred, PredReg)) { > + Mode = ARM_AM::da; > + DoMerge = true; > } > if (DoMerge) > MBB.erase(PrevMBBI); > @@ -566,19 +542,12 @@ > MachineBasicBlock::iterator NextMBBI = llvm::next(MBBI); > while (NextMBBI != EndMBBI && NextMBBI->isDebugValue()) > ++NextMBBI; > - if (isAM4) { > - if ((Mode == ARM_AM::ia || Mode == ARM_AM::ib) && > - isMatchingIncrement(NextMBBI, Base, Bytes, 0, Pred, PredReg)) { > - DoMerge = true; > - } else if ((Mode == ARM_AM::da || Mode == ARM_AM::db) && > - isMatchingDecrement(NextMBBI, Base, Bytes, 0, Pred, PredReg)) { > - DoMerge = true; > - } > - } else { > - if (Mode == ARM_AM::ia && > - isMatchingIncrement(NextMBBI, Base, Bytes, 0, Pred, PredReg)) { > - DoMerge = true; > - } > + if ((Mode == ARM_AM::ia || Mode == ARM_AM::ib) && > + isMatchingIncrement(NextMBBI, Base, Bytes, 0, Pred, PredReg)) { > + DoMerge = true; > + } else if ((Mode == ARM_AM::da || Mode == ARM_AM::db) && > + isMatchingDecrement(NextMBBI, Base, Bytes, 0, Pred, PredReg)) { > + DoMerge = true; > } > if (DoMerge) { > if (NextMBBI == I) { > @@ -595,16 +564,9 @@ > unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode); > MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(NewOpc)) > .addReg(Base, getDefRegState(true)) // WB base register > - .addReg(Base, getKillRegState(BaseKill)); > - if (isAM4) { > - // [t2]LDM_UPD, [t2]STM_UPD > - MIB.addImm(ARM_AM::getAM4ModeImm(Mode)) > - .addImm(Pred).addReg(PredReg); > - } else { > - // VLDM[SD}_UPD, VSTM[SD]_UPD > - MIB.addImm(ARM_AM::getAM5Opc(Mode, Offset)) > - .addImm(Pred).addReg(PredReg); > - } > + .addReg(Base, getKillRegState(BaseKill)) > + .addImm(ARM_AM::getAM4ModeImm(Mode)) > + .addImm(Pred).addReg(PredReg); > // Transfer the rest of operands. > for (unsigned OpNum = 4, e = MI->getNumOperands(); OpNum != e; ++OpNum) > MIB.addOperand(MI->getOperand(OpNum)); > @@ -736,11 +698,10 @@ > if (!DoMerge) > return false; > > - bool isDPR = NewOpc == ARM::VLDMD || NewOpc == ARM::VSTMD; > unsigned Offset = 0; > if (isAM5) > - Offset = ARM_AM::getAM5Opc(AddSub == ARM_AM::sub ? ARM_AM::db : ARM_AM::ia, > - (isDPR ? 2 : 1)); > + Offset = ARM_AM::getAM4ModeImm(AddSub == ARM_AM::sub ? > + ARM_AM::db : ARM_AM::ia); > else if (isAM2) > Offset = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift); > else > @@ -748,6 +709,9 @@ > > if (isAM5) { > // VLDM[SD}_UPD, VSTM[SD]_UPD > + // (There are no base-updating versions of VLDR/VSTR instructions, but the > + // updating load/store-multiple instructions can be used with only one > + // register.) > MachineOperand &MO = MI->getOperand(0); > BuildMI(MBB, MBBI, dl, TII->get(NewOpc)) > .addReg(Base, getDefRegState(true)) // WB base register > > Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp?rev=112322&r1=112321&r2=112322&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp (original) > +++ llvm/trunk/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp Fri Aug 27 18:18:17 2010 > @@ -158,7 +158,7 @@ > if ((MI->getOpcode() == ARM::VSTMS_UPD || MI->getOpcode() ==ARM::VSTMD_UPD) && > MI->getOperand(0).getReg() == ARM::SP) { > const MCOperand &MO1 = MI->getOperand(2); > - if (ARM_AM::getAM5SubMode(MO1.getImm()) == ARM_AM::db) { > + if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) { > O << '\t' << "vpush"; > printPredicateOperand(MI, 3, O); > O << '\t'; > @@ -171,7 +171,7 @@ > if ((MI->getOpcode() == ARM::VLDMS_UPD || MI->getOpcode() ==ARM::VLDMD_UPD) && > MI->getOperand(0).getReg() == ARM::SP) { > const MCOperand &MO1 = MI->getOperand(2); > - if (ARM_AM::getAM5SubMode(MO1.getImm()) == ARM_AM::ia) { > + if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) { > O << '\t' << "vpop"; > printPredicateOperand(MI, 3, O); > O << '\t'; > @@ -412,16 +412,6 @@ > return; > } > > - if (Modifier && strcmp(Modifier, "submode") == 0) { > - ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm()); > - O << ARM_AM::getAMSubModeStr(Mode); > - return; > - } else if (Modifier && strcmp(Modifier, "base") == 0) { > - // Used for FSTM{D|S} and LSTM{D|S} operations. > - O << getRegisterName(MO1.getReg()); > - return; > - } > - > O << "[" << getRegisterName(MO1.getReg()); > > if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) { > > Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=112322&r1=112321&r2=112322&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original) > +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Fri Aug 27 18:18:17 2010 > @@ -1863,7 +1863,7 @@ > > assert(NumOps >= 3 && "VFPLdStFrm expects NumOps >= 3"); > > - bool isSPVFP = (Opcode == ARM::VLDRS || Opcode == ARM::VSTRS) ? true : false; > + bool isSPVFP = (Opcode == ARM::VLDRS || Opcode == ARM::VSTRS); > unsigned RegClassID = isSPVFP ? ARM::SPRRegClassID : ARM::DPRRegClassID; > > // Extract Dd/Sd for operand 0. > @@ -1886,7 +1886,7 @@ > > // VFP Load/Store Multiple Instructions. > // This is similar to the algorithm for LDM/STM in that operand 0 (the base) and > -// operand 1 (the AM5 mode imm) is followed by two predicate operands. It is > +// operand 1 (the AM4 mode imm) is followed by two predicate operands. It is > // followed by a reglist of either DPR(s) or SPR(s). > // > // VLDMD[_UPD], VLDMS[_UPD], VSTMD[_UPD], VSTMS[_UPD] > @@ -1910,16 +1910,14 @@ > > MI.addOperand(MCOperand::CreateReg(Base)); > > - // Next comes the AM5 Opcode. > + // Next comes the AM4 Opcode. > ARM_AM::AMSubMode SubMode = getAMSubModeForBits(getPUBits(insn)); > // Must be either "ia" or "db" submode. > if (SubMode != ARM_AM::ia && SubMode != ARM_AM::db) { > - DEBUG(errs() << "Illegal addressing mode 5 sub-mode!\n"); > + DEBUG(errs() << "Illegal addressing mode 4 sub-mode!\n"); > return false; > } > - > - unsigned char Imm8 = insn & 0xFF; > - MI.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(SubMode, Imm8))); > + MI.addOperand(MCOperand::CreateImm(ARM_AM::getAM4ModeImm(SubMode))); > > // Handling the two predicate operands before the reglist. > int64_t CondVal = insn >> ARMII::CondShift; > @@ -1929,13 +1927,14 @@ > OpIdx += 4; > > bool isSPVFP = (Opcode == ARM::VLDMS || Opcode == ARM::VLDMS_UPD || > - Opcode == ARM::VSTMS || Opcode == ARM::VSTMS_UPD) ? true : false; > + Opcode == ARM::VSTMS || Opcode == ARM::VSTMS_UPD); > unsigned RegClassID = isSPVFP ? ARM::SPRRegClassID : ARM::DPRRegClassID; > > // Extract Dd/Sd. > unsigned RegD = decodeVFPRd(insn, isSPVFP); > > // Fill the variadic part of reglist. > + unsigned char Imm8 = insn & 0xFF; > unsigned Regs = isSPVFP ? Imm8 : Imm8/2; > for (unsigned i = 0; i < Regs; ++i) { > MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RegClassID, > > Modified: llvm/trunk/test/CodeGen/ARM/vst3.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vst3.ll?rev=112322&r1=112321&r2=112322&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/ARM/vst3.ll (original) > +++ llvm/trunk/test/CodeGen/ARM/vst3.ll Fri Aug 27 18:18:17 2010 > @@ -1,4 +1,4 @@ > -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s > +; RUN: llc < %s -march=arm -mattr=+neon -O0 | FileCheck %s > > define void @vst3i8(i8* %A, <8 x i8>* %B) nounwind { > ;CHECK: vst3i8: > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From geek4civic at gmail.com Mon Aug 30 10:19:56 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Mon, 30 Aug 2010 15:19:56 -0000 Subject: [llvm-commits] [llvm] r112485 - /llvm/trunk/test/Scripts/coff-dump.py Message-ID: <20100830151956.819CB2A6C12C@llvm.org> Author: chapuni Date: Mon Aug 30 10:19:56 2010 New Revision: 112485 URL: http://llvm.org/viewvc/llvm-project?rev=112485&view=rev Log: coff-dump.py: Fix PR7996. Now it is compatible to Python-2.4. Modified: llvm/trunk/test/Scripts/coff-dump.py Modified: llvm/trunk/test/Scripts/coff-dump.py URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Scripts/coff-dump.py?rev=112485&r1=112484&r2=112485&view=diff ============================================================================== --- llvm/trunk/test/Scripts/coff-dump.py (original) +++ llvm/trunk/test/Scripts/coff-dump.py Mon Aug 30 10:19:56 2010 @@ -397,8 +397,11 @@ selector = read_value (definitions [0]) definitions = definitions [1] [selector] - description = definitions[value] if value in definitions else "unknown" - + if value in definitions: + description = definitions[value] + else: + description = "unknown" + write ("%s (" % description) write_value (oformat, value) write (")") From grosbach at apple.com Mon Aug 30 10:27:30 2010 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 30 Aug 2010 08:27:30 -0700 Subject: [llvm-commits] [llvm] r112393 - in /llvm/trunk/lib/Target/ARM: ARMISelLowering.cpp ARMISelLowering.h ARMInstrThumb2.td In-Reply-To: <20100829030211.F060B2A6C12C@llvm.org> References: <20100829030211.F060B2A6C12C@llvm.org> Message-ID: <1E7726C2-E213-467D-B536-25DA196E2476@apple.com> Hi Bill, I'm not sure I follow why this is needed. I'm probably just missing some context. Mind dropping by to enlighten me? Thanks, -Jim On Aug 28, 2010, at 8:02 PM, Bill Wendling wrote: > Author: void > Date: Sat Aug 28 22:02:11 2010 > New Revision: 112393 > > URL: http://llvm.org/viewvc/llvm-project?rev=112393&view=rev > Log: > Create an ARMISD::AND node. This node is exactly like the "ARM::AND" node, but > it sets the CPSR register. > > Modified: > llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp > llvm/trunk/lib/Target/ARM/ARMISelLowering.h > llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td > > Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=112393&r1=112392&r2=112393&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Sat Aug 28 22:02:11 2010 > @@ -609,6 +609,7 @@ > case ARMISD::BR2_JT: return "ARMISD::BR2_JT"; > case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG"; > case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD"; > + case ARMISD::AND: return "ARMISD::AND"; > case ARMISD::CMP: return "ARMISD::CMP"; > case ARMISD::CMPZ: return "ARMISD::CMPZ"; > case ARMISD::CMPFP: return "ARMISD::CMPFP"; > > Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=112393&r1=112392&r2=112393&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original) > +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Sat Aug 28 22:02:11 2010 > @@ -47,6 +47,8 @@ > > PIC_ADD, // Add with a PC operand and a PIC label. > > + AND, // ARM "and" instruction that sets the 's' flag in CPSR. > + > CMP, // ARM compare instructions. > CMPZ, // ARM compare that sets only Z flag. > CMPFP, // ARM VFP compare instruction, sets FPSCR. > > Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=112393&r1=112392&r2=112393&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) > +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Sat Aug 28 22:02:11 2010 > @@ -1631,6 +1631,10 @@ > defm t2BIC : T2I_bin_w_irs<0b0001, "bic", > BinOpFrag<(and node:$LHS, (not node:$RHS))>>; > > +let Defs = [CPSR] in > +defm t2ANDflag : T2I_bin_w_irs<0b0000, "and", > + BinOpFrag<(ARMand node:$LHS, node:$RHS)>, 1>; > + > let Constraints = "$src = $dst" in > def t2BFC : T2I<(outs rGPR:$dst), (ins rGPR:$src, bf_inv_mask_imm:$imm), > IIC_iUNAsi, "bfc", "\t$dst, $imm", > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From bigcheesegs at gmail.com Mon Aug 30 10:34:08 2010 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Mon, 30 Aug 2010 15:34:08 -0000 Subject: [llvm-commits] [llvm] r112486 - /llvm/trunk/test/Makefile Message-ID: <20100830153408.DB83F2A6C12C@llvm.org> Author: mspencer Date: Mon Aug 30 10:34:08 2010 New Revision: 112486 URL: http://llvm.org/viewvc/llvm-project?rev=112486&view=rev Log: Partially revert r112480. Caused test failures. Modified: llvm/trunk/test/Makefile Modified: llvm/trunk/test/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Makefile?rev=112486&r1=112485&r2=112486&view=diff ============================================================================== --- llvm/trunk/test/Makefile (original) +++ llvm/trunk/test/Makefile Mon Aug 30 10:34:08 2010 @@ -145,7 +145,7 @@ @echo 'set objdir "$(LLVM_OBJ_ROOT)/test"' >>site.tmp @echo 'set gccpath "$(CC)"' >>site.tmp @echo 'set gxxpath "$(CXX)"' >>site.tmp - @echo 'set compile_c "' $(CC) $(CPP.Flags) $(TargetCommonOpts) $(CompileCommonOpts) -c -x c '"' >>site.tmp + @echo 'set compile_c "' $(CC) $(CPP.Flags) $(TargetCommonOpts) $(CompileCommonOpts) -c '"' >>site.tmp @echo 'set compile_cxx "' $(CXX) $(CPP.Flags) $(CXX.Flags) $(TargetCommonOpts) $(CompileCommonOpts) -c -x c++ '"' >> site.tmp @echo 'set link "' $(CXX) $(CPP.Flags) $(CXX.Flags) $(TargetCommonOpts) $(CompileCommonOpts) $(LD.Flags) '"' >>site.tmp @echo 'set llvmgcc "$(LLVMGCC) $(TargetCommonOpts) $(EXTRA_OPTIONS)"' >> site.tmp From clattner at apple.com Mon Aug 30 11:42:16 2010 From: clattner at apple.com (Chris Lattner) Date: Mon, 30 Aug 2010 09:42:16 -0700 Subject: [llvm-commits] [llvm] r112420 - /llvm/trunk/include/llvm/Support/StandardPasses.h In-Reply-To: <4C7B5C83.2060206@free.fr> References: <20100829070551.59E0E2A6C12C@llvm.org> <4C7A0B2D.8040806@free.fr> <185E017A-A97C-42D7-9F77-52F3E786972A@apple.com> <4C7B5C83.2060206@free.fr> Message-ID: On Aug 30, 2010, at 12:23 AM, Duncan Sands wrote: > Hi Chris, > >>>> I never got around to changing it to use the SSA updator. That >>>> said, I could easily change it to not promote the alloca to a >>>> register. Since it's only used if an exception is raised, that >>>> wouldn't be a big loss. >> >> I took care of this. I need to refactor some code, but it's done. > > thanks for doing this. I would have done it somewhat differently; > since you reverted your commit I will give my alternative approach > a go (hopefully I will finish this on Wednesday). Sounds great! I went with the approach that didn't require me to understand the code, doing something smarter than a "general alloca promotion" would be much better. I reverted it because it caused some failures on self host and the testsuite, but they are linux specific, so I can't repro :-( -Chris From resistor at mac.com Mon Aug 30 12:03:45 2010 From: resistor at mac.com (Owen Anderson) Date: Mon, 30 Aug 2010 17:03:45 -0000 Subject: [llvm-commits] [llvm] r112489 - /llvm/trunk/lib/Analysis/LazyValueInfo.cpp Message-ID: <20100830170345.7B1562A6C12C@llvm.org> Author: resistor Date: Mon Aug 30 12:03:45 2010 New Revision: 112489 URL: http://llvm.org/viewvc/llvm-project?rev=112489&view=rev Log: It is possible to try to merge a not-constant with a constantrage, when dealing with ptrtoint ConstantExpr's. Unfortunately, the only testcase I have for this is huge and doesn't reduce well because the error is sensitive to iteration-order issues, since the problem only occurs when merging values in a particular order. Modified: llvm/trunk/lib/Analysis/LazyValueInfo.cpp Modified: llvm/trunk/lib/Analysis/LazyValueInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/LazyValueInfo.cpp?rev=112489&r1=112488&r2=112489&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/LazyValueInfo.cpp (original) +++ llvm/trunk/lib/Analysis/LazyValueInfo.cpp Mon Aug 30 12:03:45 2010 @@ -196,13 +196,14 @@ isa(RHS.getNotConstant())) return markOverdefined(); return false; - } - if (isConstant()) { + } else if (isConstant()) { if (getConstant() == RHS.getNotConstant() || isa(RHS.getNotConstant()) || isa(getConstant())) return markOverdefined(); return markNotConstant(RHS.getNotConstant()); + } else if (isConstantRange()) { + return markOverdefined(); } assert(isUndefined() && "Unexpected lattice"); From benny.kra at googlemail.com Mon Aug 30 12:20:17 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Mon, 30 Aug 2010 17:20:17 -0000 Subject: [llvm-commits] [llvm] r112492 - /llvm/trunk/lib/MC/ELFObjectWriter.cpp Message-ID: <20100830172017.E03872A6C12C@llvm.org> Author: d0k Date: Mon Aug 30 12:20:17 2010 New Revision: 112492 URL: http://llvm.org/viewvc/llvm-project?rev=112492&view=rev Log: MCELF: The value of all common symbols is the offset from the start of the section. Patch by Roman Divacky. Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=112492&r1=112491&r2=112492&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Mon Aug 30 12:20:17 2010 @@ -367,6 +367,11 @@ if (Data.isCommon() && Data.isExternal()) Value = Data.getCommonAlignment(); + if (!Data.isCommon()) + if (MCFragment *FF = Data.getFragment()) + Value = Layout.getSymbolAddress(&Data) - + Layout.getSectionAddress(FF->getParent()); + ESize = Data.getSize(); if (Data.getSize()) { MCValue Res; @@ -380,12 +385,9 @@ Layout.getAssembler().getSymbolData(Res.getSymB()->getSymbol()); Size = Layout.getSymbolAddress(&A) - Layout.getSymbolAddress(&B); - Value = Layout.getSymbolAddress(&Data); } } else if (ESize->getKind() == MCExpr::Constant) { Size = static_cast(ESize)->getValue(); - MCFragment *F = Data.getFragment(); - Value = Layout.getSymbolAddress(&Data) - Layout.getSectionAddress(F->getParent()); } else { assert(0 && "Unsupported size expression"); } From clattner at apple.com Mon Aug 30 12:25:28 2010 From: clattner at apple.com (Chris Lattner) Date: Mon, 30 Aug 2010 10:25:28 -0700 Subject: [llvm-commits] [llvm] r112474 - /llvm/trunk/lib/ExecutionEngine/JIT/Intercept.cpp In-Reply-To: <20100830140029.A16DB2A6C12C@llvm.org> References: <20100830140029.A16DB2A6C12C@llvm.org> Message-ID: <4AB40126-ABA2-428F-86D1-679CF573FC89@apple.com> On Aug 30, 2010, at 7:00 AM, NAKAMURA Takumi wrote: > URL: http://llvm.org/viewvc/llvm-project?rev=112474&view=rev > Log: > EE/JIT: Do not invoke parent's ctors/dtors from main()! (PR3897) > > On Mingw and Cygwin, the symbol __main is resolved to > callee's(eg. tools/lli) one, to invoke wrong duplicated ctors > (and register wrong callee's dtors with atexit(3)). > We expect, by callee, ExecutionEngine::runStaticConstructorsDestructors() > is called before ExecutionEngine::runFunctionAsMain() is called. Ok: > @@ -104,6 +108,14 @@ > if (Name == "exit") return (void*)(intptr_t)&jit_exit; > if (Name == "atexit") return (void*)(intptr_t)&jit_atexit; > > + // We shuold not invoke parent's ctors/dtors from main()! (PR3897) typo "should", also, please don't put PR#'s into the code. Thanks for fixing this! -Chris From bob.wilson at apple.com Mon Aug 30 13:10:48 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Mon, 30 Aug 2010 18:10:48 -0000 Subject: [llvm-commits] [llvm] r112494 - /llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Message-ID: <20100830181048.2D6EA2A6C12C@llvm.org> Author: bwilson Date: Mon Aug 30 13:10:48 2010 New Revision: 112494 URL: http://llvm.org/viewvc/llvm-project?rev=112494&view=rev Log: When expanding NEON VST pseudo instructions, if the original super-register operand is killed, add it to the expanded instruction as an implicit kill operand instead of marking the individual subregs with kill flags. This should work better in general and also handles the case for VST3 where one of the subregs was not referenced in the expanded instruction and so was not marked killed. Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=112494&r1=112493&r2=112494&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Mon Aug 30 13:10:48 2010 @@ -118,14 +118,16 @@ D3 = TRI->getSubReg(SrcReg, ARM::dsub_7); } - MIB.addReg(D0, getKillRegState(SrcIsKill)) - .addReg(D1, getKillRegState(SrcIsKill)); + MIB.addReg(D0).addReg(D1); if (NumRegs > 2) - MIB.addReg(D2, getKillRegState(SrcIsKill)); + MIB.addReg(D2); if (NumRegs > 3) - MIB.addReg(D3, getKillRegState(SrcIsKill)); + MIB.addReg(D3); MIB = AddDefaultPred(MIB); TransferImpOps(MI, MIB, MIB); + if (SrcIsKill) + // Add an implicit kill for the super-reg. + (*MIB).addRegisterKilled(SrcReg, TRI, true); MI.eraseFromParent(); } From sabre at nondot.org Mon Aug 30 13:12:35 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 30 Aug 2010 18:12:35 -0000 Subject: [llvm-commits] [llvm] r112496 - in /llvm/trunk: lib/CodeGen/TargetLoweringObjectFileImpl.cpp test/CodeGen/X86/global-sections.ll Message-ID: <20100830181235.927A92A6C12C@llvm.org> Author: lattner Date: Mon Aug 30 13:12:35 2010 New Revision: 112496 URL: http://llvm.org/viewvc/llvm-project?rev=112496&view=rev Log: two changes: 1) nuke ConstDataCoalSection, which is dead. 2) revise my previous patch for rdar://8018335, which was completely wrong. Specifically, it doesn't make sense to mark __TEXT,__const_coal as PURE_INSTRUCTIONS, because it is for readonly data. templates (it turns out) go to const_coal_nt. The real fix for rdar://8018335 was to give ConstTextCoalSection a section kind of ReadOnly instead of Text. Modified: llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp llvm/trunk/test/CodeGen/X86/global-sections.ll Modified: llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp?rev=112496&r1=112495&r2=112496&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp (original) +++ llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp Mon Aug 30 13:12:35 2010 @@ -518,11 +518,6 @@ SectionKind::getText()); ConstTextCoalSection = getContext().getMachOSection("__TEXT", "__const_coal", - MCSectionMachO::S_COALESCED | - MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS, - SectionKind::getText()); - ConstDataCoalSection - = getContext().getMachOSection("__DATA","__const_coal", MCSectionMachO::S_COALESCED, SectionKind::getReadOnly()); ConstDataSection // .const_data Modified: llvm/trunk/test/CodeGen/X86/global-sections.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/global-sections.ll?rev=112496&r1=112495&r2=112496&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/global-sections.ll (original) +++ llvm/trunk/test/CodeGen/X86/global-sections.ll Mon Aug 30 13:12:35 2010 @@ -20,7 +20,7 @@ ; TODO: linux drops this into .rodata, we drop it into ".gnu.linkonce.r.G2" -; DARWIN: .section __TEXT,__const_coal,coalesced,pure_instructions +; DARWIN: .section __TEXT,__const_coal,coalesced ; DARWIN: _G2: ; DARWIN: .long 42 @@ -85,7 +85,7 @@ ; LINUX: .byte 1 ; LINUX: .size G6, 1 -; DARWIN: .section __TEXT,__const_coal,coalesced,pure_instructions +; DARWIN: .section __TEXT,__const_coal,coalesced ; DARWIN: .globl _G6 ; DARWIN: .weak_definition _G6 ; DARWIN:_G6: From sabre at nondot.org Mon Aug 30 13:16:27 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 30 Aug 2010 18:16:27 -0000 Subject: [llvm-commits] [llvm] r112497 - /llvm/trunk/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h Message-ID: <20100830181627.ECF902A6C12C@llvm.org> Author: lattner Date: Mon Aug 30 13:16:27 2010 New Revision: 112497 URL: http://llvm.org/viewvc/llvm-project?rev=112497&view=rev Log: nuke dead ivar which was supposed to be committed with r112496 Modified: llvm/trunk/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h Modified: llvm/trunk/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h?rev=112497&r1=112496&r2=112497&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h (original) +++ llvm/trunk/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h Mon Aug 30 13:16:27 2010 @@ -105,7 +105,6 @@ const MCSection *UStringSection; const MCSection *TextCoalSection; const MCSection *ConstTextCoalSection; - const MCSection *ConstDataCoalSection; const MCSection *ConstDataSection; const MCSection *DataCoalSection; const MCSection *DataCommonSection; From echristo at apple.com Mon Aug 30 13:31:44 2010 From: echristo at apple.com (Eric Christopher) Date: Mon, 30 Aug 2010 18:31:44 -0000 Subject: [llvm-commits] [llvm] r112498 - /llvm/trunk/include/llvm/ADT/STLExtras.h Message-ID: <20100830183144.8AF2D2A6C12C@llvm.org> Author: echristo Date: Mon Aug 30 13:31:44 2010 New Revision: 112498 URL: http://llvm.org/viewvc/llvm-project?rev=112498&view=rev Log: Kill a couple of unused variables. Modified: llvm/trunk/include/llvm/ADT/STLExtras.h Modified: llvm/trunk/include/llvm/ADT/STLExtras.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/STLExtras.h?rev=112498&r1=112497&r2=112498&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/STLExtras.h (original) +++ llvm/trunk/include/llvm/ADT/STLExtras.h Mon Aug 30 13:31:44 2010 @@ -225,7 +225,7 @@ /// Find the length of an array. template -inline size_t array_lengthof(T (&x)[N]) { +inline size_t array_lengthof(T (&)[N]) { return N; } @@ -243,7 +243,7 @@ /// get_array_pad_sort_comparator - This is an internal helper function used to /// get type deduction of T right. template -static int (*get_array_pad_sort_comparator(const T &X)) +static int (*get_array_pad_sort_comparator(const T &)) (const void*, const void*) { return array_pod_sort_comparator; } From echristo at apple.com Mon Aug 30 13:34:48 2010 From: echristo at apple.com (Eric Christopher) Date: Mon, 30 Aug 2010 18:34:48 -0000 Subject: [llvm-commits] [llvm] r112499 - in /llvm/trunk: autoconf/configure.ac cmake/config-ix.cmake configure include/llvm-c/Target.h include/llvm/Config/config.h.cmake include/llvm/Config/config.h.in include/llvm/Config/llvm-config.h.cmake include/llvm/Config/llvm-config.h.in include/llvm/Target/TargetSelect.h Message-ID: <20100830183449.0871B2A6C12C@llvm.org> Author: echristo Date: Mon Aug 30 13:34:48 2010 New Revision: 112499 URL: http://llvm.org/viewvc/llvm-project?rev=112499&view=rev Log: Fix LLVM target initialization to deal with sociopathic outside projects that like to randomly define things like "X86", regenerate autoconf bits and update cmake. Fixes PR7852. Patch by Xerxes R?nby! Modified: llvm/trunk/autoconf/configure.ac llvm/trunk/cmake/config-ix.cmake llvm/trunk/configure llvm/trunk/include/llvm-c/Target.h llvm/trunk/include/llvm/Config/config.h.cmake llvm/trunk/include/llvm/Config/config.h.in llvm/trunk/include/llvm/Config/llvm-config.h.cmake llvm/trunk/include/llvm/Config/llvm-config.h.in llvm/trunk/include/llvm/Target/TargetSelect.h Modified: llvm/trunk/autoconf/configure.ac URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=112499&r1=112498&r2=112499&view=diff ============================================================================== --- llvm/trunk/autoconf/configure.ac (original) +++ llvm/trunk/autoconf/configure.ac Mon Aug 30 13:34:48 2010 @@ -596,11 +596,17 @@ # If so, define LLVM_NATIVE_ARCH to that LLVM target. for a_target in $TARGETS_TO_BUILD; do if test "$a_target" = "$LLVM_NATIVE_ARCH"; then - LLVM_NATIVE_ARCHTARGET="${LLVM_NATIVE_ARCH}Target" - AC_DEFINE_UNQUOTED(LLVM_NATIVE_ARCHNAME,$LLVM_NATIVE_ARCH, - [Short LLVM architecture name for the native architecture, if available]) - AC_DEFINE_UNQUOTED(LLVM_NATIVE_ARCH,$LLVM_NATIVE_ARCHTARGET, + AC_DEFINE_UNQUOTED(LLVM_NATIVE_ARCH, $LLVM_NATIVE_ARCH, [LLVM architecture name for the native architecture, if available]) + LLVM_NATIVE_TARGET="LLVMInitialize${LLVM_NATIVE_ARCH}Target" + LLVM_NATIVE_TARGETINFO="LLVMInitialize${LLVM_NATIVE_ARCH}TargetInfo" + LLVM_NATIVE_ASMPRINTER="LLVMInitialize${LLVM_NATIVE_ARCH}AsmPrinter" + AC_DEFINE_UNQUOTED(LLVM_NATIVE_TARGET, $LLVM_NATIVE_TARGET, + [LLVM name for the native Target init function, if available]) + AC_DEFINE_UNQUOTED(LLVM_NATIVE_TARGETINFO, $LLVM_NATIVE_TARGETINFO, + [LLVM name for the native TargetInfo init function, if available]) + AC_DEFINE_UNQUOTED(LLVM_NATIVE_ASMPRINTER, $LLVM_NATIVE_ASMPRINTER, + [LLVM name for the native AsmPrinter init function, if available]) fi done Modified: llvm/trunk/cmake/config-ix.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/config-ix.cmake?rev=112499&r1=112498&r2=112499&view=diff ============================================================================== --- llvm/trunk/cmake/config-ix.cmake (original) +++ llvm/trunk/cmake/config-ix.cmake Mon Aug 30 13:34:48 2010 @@ -207,7 +207,9 @@ endif () if (LLVM_NATIVE_ARCH) - set(LLVM_NATIVE_ARCHNAME ${LLVM_NATIVE_ARCH}) + set(LLVM_NATIVE_TARGET LLVMInitialize${LLVM_NATIVE_ARCH}Target) + set(LLVM_NATIVE_TARGETINFO LLVMInitialize${LLVM_NATIVE_ARCH}TargetInfo) + set(LLVM_NATIVE_ASMPRINTER LLVMInitialize${LLVM_NATIVE_ARCH}AsmPrinter) list(FIND LLVM_TARGETS_TO_BUILD ${LLVM_NATIVE_ARCH} NATIVE_ARCH_IDX) if (NATIVE_ARCH_IDX EQUAL -1) message(STATUS Modified: llvm/trunk/configure URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=112499&r1=112498&r2=112499&view=diff ============================================================================== --- llvm/trunk/configure (original) +++ llvm/trunk/configure Mon Aug 30 13:34:48 2010 @@ -1414,8 +1414,8 @@ --enable-targets Build specific host targets: all or target1,target2,... Valid targets are: host, x86, x86_64, sparc, powerpc, alpha, arm, mips, spu, - pic16, xcore, msp430, systemz, blackfin, cbe, - and cpp (default=all) + pic16, xcore, msp430, systemz, blackfin, cbe, and + cpp (default=all) --enable-cbe-printf-a Enable C Backend output with hex floating point via %a (default is YES) --enable-bindings Build specific language bindings: @@ -5007,15 +5007,27 @@ # If so, define LLVM_NATIVE_ARCH to that LLVM target. for a_target in $TARGETS_TO_BUILD; do if test "$a_target" = "$LLVM_NATIVE_ARCH"; then - LLVM_NATIVE_ARCHTARGET="${LLVM_NATIVE_ARCH}Target" cat >>confdefs.h <<_ACEOF -#define LLVM_NATIVE_ARCHNAME $LLVM_NATIVE_ARCH +#define LLVM_NATIVE_ARCH $LLVM_NATIVE_ARCH _ACEOF + LLVM_NATIVE_TARGET="LLVMInitialize${LLVM_NATIVE_ARCH}Target" + LLVM_NATIVE_TARGETINFO="LLVMInitialize${LLVM_NATIVE_ARCH}TargetInfo" + LLVM_NATIVE_ASMPRINTER="LLVMInitialize${LLVM_NATIVE_ARCH}AsmPrinter" cat >>confdefs.h <<_ACEOF -#define LLVM_NATIVE_ARCH $LLVM_NATIVE_ARCHTARGET +#define LLVM_NATIVE_TARGET $LLVM_NATIVE_TARGET +_ACEOF + + +cat >>confdefs.h <<_ACEOF +#define LLVM_NATIVE_TARGETINFO $LLVM_NATIVE_TARGETINFO +_ACEOF + + +cat >>confdefs.h <<_ACEOF +#define LLVM_NATIVE_ASMPRINTER $LLVM_NATIVE_ASMPRINTER _ACEOF fi @@ -11377,7 +11389,7 @@ lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext < References: <20100829030211.F060B2A6C12C@llvm.org> <1E7726C2-E213-467D-B536-25DA196E2476@apple.com> Message-ID: <4B7A920B-41E4-4543-AF91-B8D7AE1C0F7F@gmail.com> Hi Jim, It's for a future optimization I have in mind. I want to generate good code for this function: int x(int a) { if (a & 256) return -26; return 0; } Right now, we generate something like this: tst r0, r0, 256 mvn r0, #25 it eq moveq r0, #0 gcc generates something like this: ands r0, r0, 256 it ne mvnne r0, #25 I want to do this transformation during instruction selection time. So basically I have something like: (ARMISD::MOVCC CC, (ARMISD::CMPZ (and X, 256), 0), -26) This will be converted to: (ARM::t2MOVCC nCC, -26, (ARM::t2ANDri X, 256)) where the ARM::t2ANDri instruction sets CPSR and the t2MOVCC acts upon that flag, and nCC is the opposite condcode of CC. So, um, that's why. :-) It's vague and I'll talk to you in person more in depth... -bw On Aug 30, 2010, at 8:27 AM, Jim Grosbach wrote: > Hi Bill, > > I'm not sure I follow why this is needed. I'm probably just missing some context. Mind dropping by to enlighten me? > > Thanks, > -Jim > > On Aug 28, 2010, at 8:02 PM, Bill Wendling wrote: > >> Author: void >> Date: Sat Aug 28 22:02:11 2010 >> New Revision: 112393 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=112393&view=rev >> Log: >> Create an ARMISD::AND node. This node is exactly like the "ARM::AND" node, but >> it sets the CPSR register. >> >> Modified: >> llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp >> llvm/trunk/lib/Target/ARM/ARMISelLowering.h >> llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td >> >> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=112393&r1=112392&r2=112393&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) >> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Sat Aug 28 22:02:11 2010 >> @@ -609,6 +609,7 @@ >> case ARMISD::BR2_JT: return "ARMISD::BR2_JT"; >> case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG"; >> case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD"; >> + case ARMISD::AND: return "ARMISD::AND"; >> case ARMISD::CMP: return "ARMISD::CMP"; >> case ARMISD::CMPZ: return "ARMISD::CMPZ"; >> case ARMISD::CMPFP: return "ARMISD::CMPFP"; >> >> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=112393&r1=112392&r2=112393&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original) >> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Sat Aug 28 22:02:11 2010 >> @@ -47,6 +47,8 @@ >> >> PIC_ADD, // Add with a PC operand and a PIC label. >> >> + AND, // ARM "and" instruction that sets the 's' flag in CPSR. >> + >> CMP, // ARM compare instructions. >> CMPZ, // ARM compare that sets only Z flag. >> CMPFP, // ARM VFP compare instruction, sets FPSCR. >> >> Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=112393&r1=112392&r2=112393&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) >> +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Sat Aug 28 22:02:11 2010 >> @@ -1631,6 +1631,10 @@ >> defm t2BIC : T2I_bin_w_irs<0b0001, "bic", >> BinOpFrag<(and node:$LHS, (not node:$RHS))>>; >> >> +let Defs = [CPSR] in >> +defm t2ANDflag : T2I_bin_w_irs<0b0000, "and", >> + BinOpFrag<(ARMand node:$LHS, node:$RHS)>, 1>; >> + >> let Constraints = "$src = $dst" in >> def t2BFC : T2I<(outs rGPR:$dst), (ins rGPR:$src, bf_inv_mask_imm:$imm), >> IIC_iUNAsi, "bfc", "\t$dst, $imm", >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From clattner at apple.com Mon Aug 30 14:43:28 2010 From: clattner at apple.com (Chris Lattner) Date: Mon, 30 Aug 2010 12:43:28 -0700 Subject: [llvm-commits] [llvm] r112465 - in /llvm/trunk/examples: Makefile TracingBrainF/ TracingBrainF/BrainF.h TracingBrainF/BrainFCodeGen.cpp TracingBrainF/BrainFInterpreter.cpp TracingBrainF/BrainFOpcodes.cpp TracingBrainF/BrainFTraceRecorder.cpp TracingBrainF/BrainFVM.h TracingBrainF/Makefile TracingBrainF/README In-Reply-To: <20100830073339.A1A352A6C12D@llvm.org> References: <20100830073339.A1A352A6C12D@llvm.org> Message-ID: <06E83978-57C6-4FC0-87E9-42AC9DE2993F@apple.com> On Aug 30, 2010, at 12:33 AM, Owen Anderson wrote: > Author: resistor > Date: Mon Aug 30 02:33:39 2010 > New Revision: 112465 > > URL: http://llvm.org/viewvc/llvm-project?rev=112465&view=rev > Log: > Add a new example to the LLVM distribution: a trace-based Brainfuck compiler that uses LLVM as its code generator. This sounds like a somewhat useful example, but its utility is limited by it compiling brainfuck (which noone knows and whose lessons don't apply directly to other languages). Why not turn this into a tutorial or something instead of an example in the main distribution? -Chris From grosbach at apple.com Mon Aug 30 14:49:58 2010 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 30 Aug 2010 19:49:58 -0000 Subject: [llvm-commits] [llvm] r112503 - in /llvm/trunk/lib/Target/ARM: ARMInstrInfo.td ARMInstrThumb.td ARMInstrThumb2.td Message-ID: <20100830194959.109DE2A6C12C@llvm.org> Author: grosbach Date: Mon Aug 30 14:49:58 2010 New Revision: 112503 URL: http://llvm.org/viewvc/llvm-project?rev=112503&view=rev Log: Make ARM add rN, sp, #imm instructions rematerializable. That's how the address of locals is calculated, so this should help relieve register pressure a bit. Recalculating the local address is almost always going to be better than spilling. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrThumb.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=112503&r1=112502&r2=112503&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Aug 30 14:49:58 2010 @@ -452,11 +452,15 @@ /// binop that produces a value. multiclass AsI1_bin_irs opcod, string opc, PatFrag opnode, bit Commutable = 0> { + // The register-immediate version is re-materializable. This is useful + // in particular for taking the address of a local. + let isReMaterializable = 1 in { def ri : AsI1 { let Inst{25} = 1; } + } def rr : AsI1 { Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=112503&r1=112502&r2=112503&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Mon Aug 30 14:49:58 2010 @@ -221,9 +221,13 @@ T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10 // ADD rd, sp, #imm8 +// This is rematerializable, which is particularly useful for taking the +// address of locals. +let isReMaterializable = 1 in { def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi, "add\t$dst, $sp, $rhs", []>, T1Encoding<{1,0,1,0,1,?}>; // A6.2 & A8.6.8 +} // ADD sp, sp, #imm7 def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi, Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=112503&r1=112502&r2=112503&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Aug 30 14:49:58 2010 @@ -382,6 +382,9 @@ multiclass T2I_bin_ii12rs op23_21, string opc, PatFrag opnode, bit Commutable = 0> { // shifted imm + // The register-immediate version is re-materializable. This is useful + // in particular for taking the address of a local. + let isReMaterializable = 1 in { def ri : T2sI<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi, opc, ".w\t$dst, $lhs, $rhs", [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> { @@ -392,6 +395,7 @@ let Inst{20} = 0; // The S bit. let Inst{15} = 0; } + } // 12-bit imm def ri12 : T2I<(outs rGPR:$dst), (ins GPR:$lhs, imm0_4095:$rhs), IIC_iALUi, !strconcat(opc, "w"), "\t$dst, $lhs, $rhs", From resistor at mac.com Mon Aug 30 14:58:35 2010 From: resistor at mac.com (Owen Anderson) Date: Mon, 30 Aug 2010 12:58:35 -0700 Subject: [llvm-commits] [llvm] r112465 - in /llvm/trunk/examples: Makefile TracingBrainF/ TracingBrainF/BrainF.h TracingBrainF/BrainFCodeGen.cpp TracingBrainF/BrainFInterpreter.cpp TracingBrainF/BrainFOpcodes.cpp TracingBrainF/BrainFTraceRecorder.cpp TracingBrainF/BrainFVM.h TracingBrainF/Makefile TracingBrainF/README In-Reply-To: <06E83978-57C6-4FC0-87E9-42AC9DE2993F@apple.com> References: <20100830073339.A1A352A6C12D@llvm.org> <06E83978-57C6-4FC0-87E9-42AC9DE2993F@apple.com> Message-ID: <2562A51C-2385-46E6-B7A8-B6922703E0C9@mac.com> On Aug 30, 2010, at 12:43 PM, Chris Lattner wrote: > This sounds like a somewhat useful example, but its utility is limited by it compiling brainfuck (which noone knows and whose lessons don't apply directly to other languages). Why not turn this into a tutorial or something instead of an example in the main distribution? I do, in fact, have a sequence of tutorials in mind based on that, similar to the Kaleidoscope tutorials. Also, while I agree that it's not useful as a tool itself, I think most of the techniques I used in this should work for any language bytecode-compilable language. I just went with brainfuck because a small opcode set makes it easy to implement. :-) --Owen From baldrick at free.fr Mon Aug 30 15:00:45 2010 From: baldrick at free.fr (Duncan Sands) Date: Mon, 30 Aug 2010 20:00:45 -0000 Subject: [llvm-commits] [zorg] r112505 - /zorg/trunk/buildbot/osuosl/master/config/slaves.py Message-ID: <20100830200045.988892A6C12C@llvm.org> Author: baldrick Date: Mon Aug 30 15:00:45 2010 New Revision: 112505 URL: http://llvm.org/viewvc/llvm-project?rev=112505&view=rev Log: Add some additional gcc compile farm buildbots. Modified: zorg/trunk/buildbot/osuosl/master/config/slaves.py Modified: zorg/trunk/buildbot/osuosl/master/config/slaves.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/slaves.py?rev=112505&r1=112504&r2=112505&view=diff ============================================================================== --- zorg/trunk/buildbot/osuosl/master/config/slaves.py (original) +++ zorg/trunk/buildbot/osuosl/master/config/slaves.py Mon Aug 30 15:00:45 2010 @@ -52,14 +52,36 @@ # Win XP SP2, Intel Core2 Duo 2.99GHz -E6850, 2.93 GB create_slave("adobe1", properties={'jobs' : 2}, max_builds=1), - # GCC Farm Slaves, for DragonEgg - create_slave("baldrick11", properties={'jobs' : 4}, max_builds=1), - create_slave("baldrick12", properties={'jobs' : 4}, max_builds=1), - create_slave("baldrick13", properties={'jobs' : 4}, max_builds=1), - create_slave("baldrick14", properties={'jobs' : 8}, max_builds=1), - create_slave("baldrick15", properties={'jobs' : 2}, max_builds=1), - create_slave("baldrick16", properties={'jobs' : 8}, max_builds=1), - create_slave("baldrick17", properties={'jobs' : 8}, max_builds=1), + # GCC Farm Slaves + create_slave("baldrick10", properties={'jobs' : 12}, max_builds=1), # gcc10 2TB 2x12x1.5 GHz 2x Opteron Magny-Cours / 64 GB RAM / Supermicro AS-1022G-BTF + create_slave("baldrick11", properties={'jobs' : 2}, max_builds=1), # gcc11 580G 2x 2x2.0 GHz Opteron 2212 / 4GB RAM / Dell SC1345 + create_slave("baldrick12", properties={'jobs' : 2}, max_builds=1), # gcc12 580G 2x 2x2.0 GHz Opteron 2212 / 4GB RAM / Dell SC1345 + create_slave("baldrick13", properties={'jobs' : 2}, max_builds=1), # gcc13 580G 2x2x2.0 GHz Opteron 2212 / 4GB RAM / Dell SC1345 + create_slave("baldrick14", properties={'jobs' : 4}, max_builds=1), # gcc14 750G 2x4x3.0 GHz Xeon X5450 / 16GB RAM / Dell Poweredge 1950 + create_slave("baldrick15", properties={'jobs' : 1}, max_builds=1), # gcc15 160G 1x2x2.8 GHz Xeon dual core "paxville" / 1 GB RAM / Dell SC1425 + create_slave("baldrick16", properties={'jobs' : 4}, max_builds=1), # gcc16 580G 2x4x2.2 GHz Opteron 8354 "Barcelona B3" / 16 GB RAM + create_slave("baldrick17", properties={'jobs' : 4}, max_builds=1), # gcc17 580G 2x4x2.2 GHz Opteron 8354 "Barcelona B3" / 16 GB RAM + create_slave("baldrick35", properties={'jobs' : 1}, max_builds=1), # gcc35 19035 1TB 0.8 GHz Freescale i.MX515 (ARM Cortex-A8) / 512 MB RAM / Efika MX Client Dev Board + create_slave("baldrick38", properties={'jobs' : 1}, max_builds=1), # gcc38 19038 1TB 3.2 GHz Sony Playstation 3 / Cell / SPE + create_slave("baldrick40", properties={'jobs' : 1}, max_builds=1), # gcc40 9090 160G 1.8 GHz PowerPC 970 G5 / 512 MB RAM / PowerMac G5 + create_slave("baldrick42", properties={'jobs' : 1}, max_builds=1), # gcc42 9092 160G 0.8 GHz MIPS Loongson 2F / 1 GB RAM / Lemote Fuloong 6004 Linux mini PC + create_slave("baldrick43", properties={'jobs' : 1}, max_builds=1), # gcc43 9093 60G 1.4 GHz Powerpc G4 7447A / 1GB RAM / Apple Mac Mini + create_slave("baldrick50", properties={'jobs' : 1}, max_builds=1), # gcc50 9080 250G 0.6 GHz ARM XScale-80219 / 512 MB RAM / Thecus N2100 NAS + create_slave("baldrick51", properties={'jobs' : 1}, max_builds=1), # gcc51 9081 60G 0.8 GHz MIPS Loongson 2F / 1 GB RAM / Lemote YeeLoong 8089 notebook + create_slave("baldrick52", properties={'jobs' : 1}, max_builds=1), # gcc52 9082 1TB 0.8 GHz MIPS Loongson 2F / 512 MB RAM / Gdium Liberty 1000 notebook Mandriva 2009.1 + create_slave("baldrick53", properties={'jobs' : 1}, max_builds=1), # gcc53 9083 80G 2x1.25 GHz PowerPC 7455 G4 / 1.5 GB RAM / PowerMac G4 dual processor + create_slave("baldrick54", properties={'jobs' : 1}, max_builds=1), # gcc54 9084 36G 0.5 GHz TI UltraSparc IIe (Hummingbird) / 1.5 GB RAM / Sun Netra T1 200 / Debian sparc64 + create_slave("baldrick55", properties={'jobs' : 1}, max_builds=1), # gcc55 9085 250G 1.2 GHz ARM Feroceon 88FR131 (kirkwood) / 512 MB RAM / Marvell SheevaPlug + create_slave("baldrick56", properties={'jobs' : 1}, max_builds=1), # gcc56 9086 320G 1.2 GHz ARM Feroceon 88FR131 (kirkwood) / 512 MB RAM / Marvell SheevaPlug + create_slave("baldrick57", properties={'jobs' : 1}, max_builds=1), # gcc57 9087 320G 1.2 GHz ARM Feroceon 88FR131 (kirkwood) / 512 MB RAM / Marvell SheevaPlug + create_slave("baldrick60", properties={'jobs' : 1}, max_builds=1), # gcc60 9200 72G 2x1.3 GHz Madison / 6 GB RAM / HP zx6000 + create_slave("baldrick61", properties={'jobs' : 1}, max_builds=1), # gcc61 9201 36G 2x0.55 GHz PA8600 / 3.5 GB RAM / HP 9000/785/J6000 + create_slave("baldrick62", properties={'jobs' : 3}, max_builds=1), # gcc62 9202 36G 6x0.4GHz TI UltraSparc II (BlackBird) / 5 GB RAM / Sun Enterprise 4500 / Debian sparc64 + create_slave("baldrick63", properties={'jobs' : 16}, max_builds=1), # gcc63 9203 72G 8x4x1GHz UltraSparc T1 (Niagara) 1 GHz 8 core 32 threads / 8 GB RAM / Sun Fire T1000 / Debian sparc64 + create_slave("baldrick64", properties={'jobs' : 1}, max_builds=1), # gcc64 9204 72G 1x1GHz UltraSPARC-IIIi / 1 GB RAM / Sun V210 / OpenBSD 4.6 sparc64 + create_slave("baldrick101", properties={'jobs' : 1}, max_builds=1), # gcc101 1TB 2x2.6 GHz Opteron 252 / 1GB RAM running FreeBSD 8 x86_64 + create_slave("baldrick200", properties={'jobs' : 2}, max_builds=1), # gcc200 8010 80G 4x0.4GHz TI UltraSparc II (BlackBird) / 4 GB RAM / Sun E250 / Gentoo sparc64 + create_slave("baldrick201", properties={'jobs' : 2}, max_builds=1), # gcc201 8011 80G 4x0.4GHz TI UltraSparc II (BlackBird) / 4 GB RAM / Sun E250 / Gentoo sparc64 # Debian x86_64, 2 x 6-core Opteron 2.6 GHz create_slave("osu7", properties={'jobs' : 6}, max_builds=4), From bob.wilson at apple.com Mon Aug 30 15:01:06 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Mon, 30 Aug 2010 20:01:06 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r112506 - /llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp Message-ID: <20100830200106.D6F582A6C12C@llvm.org> Author: bwilson Date: Mon Aug 30 15:01:06 2010 New Revision: 112506 URL: http://llvm.org/viewvc/llvm-project?rev=112506&view=rev Log: Translate NEON vmovn builtin to a vector truncation instead of using an llvm intrinsic. Modified: llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp Modified: llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp?rev=112506&r1=112505&r2=112506&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp Mon Aug 30 15:01:06 2010 @@ -1718,11 +1718,9 @@ case NEON_BUILTIN_vmovn: if (datatype == neon_datatype_signed || datatype == neon_datatype_unsigned) - intID = Intrinsic::arm_neon_vmovn; + Result = Builder.CreateTrunc(Ops[0], ResultType); else return BadImmediateError(exp, Result); - intFn = Intrinsic::getDeclaration(TheModule, intID, &ResultType, 1); - Result = Builder.CreateCall(intFn, Ops[0]); break; case NEON_BUILTIN_vqmovn: From bob.wilson at apple.com Mon Aug 30 15:02:31 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Mon, 30 Aug 2010 20:02:31 -0000 Subject: [llvm-commits] [llvm] r112507 - in /llvm/trunk: include/llvm/IntrinsicsARM.td lib/Target/ARM/ARMInstrNEON.td lib/VMCore/AutoUpgrade.cpp test/Bitcode/neon-intrinsics.ll test/Bitcode/neon-intrinsics.ll.bc test/CodeGen/ARM/vmov.ll Message-ID: <20100830200231.2044C2A6C12C@llvm.org> Author: bwilson Date: Mon Aug 30 15:02:30 2010 New Revision: 112507 URL: http://llvm.org/viewvc/llvm-project?rev=112507&view=rev Log: Remove NEON vmovn intrinsic, replacing it with vector truncate operations. Auto-upgrade the old intrinsic and update tests. Modified: llvm/trunk/include/llvm/IntrinsicsARM.td llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/lib/VMCore/AutoUpgrade.cpp llvm/trunk/test/Bitcode/neon-intrinsics.ll llvm/trunk/test/Bitcode/neon-intrinsics.ll.bc llvm/trunk/test/CodeGen/ARM/vmov.ll Modified: llvm/trunk/include/llvm/IntrinsicsARM.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsARM.td?rev=112507&r1=112506&r2=112507&view=diff ============================================================================== --- llvm/trunk/include/llvm/IntrinsicsARM.td (original) +++ llvm/trunk/include/llvm/IntrinsicsARM.td Mon Aug 30 15:02:30 2010 @@ -303,7 +303,6 @@ def int_arm_neon_vcvtfxu2fp : Neon_CvtFxToFP_Intrinsic; // Narrowing and Lengthening Vector Moves. -def int_arm_neon_vmovn : Neon_1Arg_Narrow_Intrinsic; def int_arm_neon_vqmovns : Neon_1Arg_Narrow_Intrinsic; def int_arm_neon_vqmovnu : Neon_1Arg_Narrow_Intrinsic; def int_arm_neon_vqmovnsu : Neon_1Arg_Narrow_Intrinsic; Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=112507&r1=112506&r2=112507&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Aug 30 15:02:30 2010 @@ -956,6 +956,15 @@ (ins QPR:$src), itin, OpcodeStr, Dt, "$dst, $src", "", [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>; +// Narrow 2-register operations. +class N2VN op24_23, bits<2> op21_20, bits<2> op19_18, + bits<2> op17_16, bits<5> op11_7, bit op6, bit op4, + InstrItinClass itin, string OpcodeStr, string Dt, + ValueType TyD, ValueType TyQ, SDNode OpNode> + : N2V; + // Narrow 2-register intrinsics. class N2VNInt op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16, bits<5> op11_7, bit op6, bit op4, @@ -1579,6 +1588,23 @@ } +// Neon Narrowing 2-register vector operations, +// source operand element sizes of 16, 32 and 64 bits: +multiclass N2VN_HSD op24_23, bits<2> op21_20, bits<2> op17_16, + bits<5> op11_7, bit op6, bit op4, + InstrItinClass itin, string OpcodeStr, string Dt, + SDNode OpNode> { + def v8i8 : N2VN; + def v4i16 : N2VN; + def v2i32 : N2VN; +} + // Neon Narrowing 2-register vector intrinsics, // source operand element sizes of 16, 32 and 64 bits: multiclass N2VNInt_HSD op24_23, bits<2> op21_20, bits<2> op17_16, @@ -3221,8 +3247,8 @@ [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>; // VMOVN : Vector Narrowing Move -defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVD, - "vmovn", "i", int_arm_neon_vmovn>; +defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVD, + "vmovn", "i", trunc>; // VQMOVN : Vector Saturating Narrowing Move defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD, "vqmovn", "s", int_arm_neon_vqmovns>; Modified: llvm/trunk/lib/VMCore/AutoUpgrade.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AutoUpgrade.cpp?rev=112507&r1=112506&r2=112507&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/AutoUpgrade.cpp (original) +++ llvm/trunk/lib/VMCore/AutoUpgrade.cpp Mon Aug 30 15:02:30 2010 @@ -88,7 +88,9 @@ ((Name.compare(14, 5, "vaddw", 5) == 0 || Name.compare(14, 5, "vsubw", 5) == 0) && (Name.compare(19, 2, "s.", 2) == 0 || - Name.compare(19, 2, "u.", 2) == 0))) { + Name.compare(19, 2, "u.", 2) == 0)) || + + (Name.compare(14, 6, "vmovn.", 6) == 0)) { // Calls to these are transformed into IR without intrinsics. NewFn = 0; @@ -401,6 +403,9 @@ else NewI = BinaryOperator::CreateSub(V0, V1,"upgraded."+CI->getName(),CI); + } else if (Name.compare(14, 6, "vmovn.", 6) == 0) { + NewI = new TruncInst(CI->getArgOperand(0), CI->getType(), + "upgraded." + CI->getName(), CI); } else { llvm_unreachable("Unknown arm.neon function for CallInst upgrade."); } Modified: llvm/trunk/test/Bitcode/neon-intrinsics.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bitcode/neon-intrinsics.ll?rev=112507&r1=112506&r2=112507&view=diff ============================================================================== --- llvm/trunk/test/Bitcode/neon-intrinsics.ll (original) +++ llvm/trunk/test/Bitcode/neon-intrinsics.ll Mon Aug 30 15:02:30 2010 @@ -76,6 +76,20 @@ ; CHECK: zext <4 x i16> ; CHECK-NEXT: sub <4 x i32> +; vmovn should be auto-upgraded to trunc + +; CHECK: vmovni16 +; CHECK-NOT: arm.neon.vmovn.v8i8 +; CHECK: trunc <8 x i16> + +; CHECK: vmovni32 +; CHECK-NOT: arm.neon.vmovn.v4i16 +; CHECK: trunc <4 x i32> + +; CHECK: vmovni64 +; CHECK-NOT: arm.neon.vmovn.v2i32 +; CHECK: trunc <2 x i64> + ; vld* and vst* intrinsic calls need an alignment argument (defaulted to 1) ; CHECK: vld1i8 Modified: llvm/trunk/test/Bitcode/neon-intrinsics.ll.bc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bitcode/neon-intrinsics.ll.bc?rev=112507&r1=112506&r2=112507&view=diff ============================================================================== Binary files - no diff available. Modified: llvm/trunk/test/CodeGen/ARM/vmov.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vmov.ll?rev=112507&r1=112506&r2=112507&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vmov.ll (original) +++ llvm/trunk/test/CodeGen/ARM/vmov.ll Mon Aug 30 15:02:30 2010 @@ -240,7 +240,7 @@ ;CHECK: vmovni16: ;CHECK: vmovn.i16 %tmp1 = load <8 x i16>* %A - %tmp2 = call <8 x i8> @llvm.arm.neon.vmovn.v8i8(<8 x i16> %tmp1) + %tmp2 = trunc <8 x i16> %tmp1 to <8 x i8> ret <8 x i8> %tmp2 } @@ -248,7 +248,7 @@ ;CHECK: vmovni32: ;CHECK: vmovn.i32 %tmp1 = load <4 x i32>* %A - %tmp2 = call <4 x i16> @llvm.arm.neon.vmovn.v4i16(<4 x i32> %tmp1) + %tmp2 = trunc <4 x i32> %tmp1 to <4 x i16> ret <4 x i16> %tmp2 } @@ -256,14 +256,10 @@ ;CHECK: vmovni64: ;CHECK: vmovn.i64 %tmp1 = load <2 x i64>* %A - %tmp2 = call <2 x i32> @llvm.arm.neon.vmovn.v2i32(<2 x i64> %tmp1) + %tmp2 = trunc <2 x i64> %tmp1 to <2 x i32> ret <2 x i32> %tmp2 } -declare <8 x i8> @llvm.arm.neon.vmovn.v8i8(<8 x i16>) nounwind readnone -declare <4 x i16> @llvm.arm.neon.vmovn.v4i16(<4 x i32>) nounwind readnone -declare <2 x i32> @llvm.arm.neon.vmovn.v2i32(<2 x i64>) nounwind readnone - define <8 x i8> @vqmovns16(<8 x i16>* %A) nounwind { ;CHECK: vqmovns16: ;CHECK: vqmovn.s16 From rafael.espindola at gmail.com Mon Aug 30 15:52:59 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Mon, 30 Aug 2010 20:52:59 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r112522 - /llvm-gcc-4.2/trunk/gcc/gcc.c Message-ID: <20100830205259.4311B2A6C12C@llvm.org> Author: rafael Date: Mon Aug 30 15:52:59 2010 New Revision: 112522 URL: http://llvm.org/viewvc/llvm-project?rev=112522&view=rev Log: Pass -plugin-opt=as-arg=--32 and -plugin-opt=as-arg=--64 if -m32 or -m64 is passed to gcc. This should fix the issue Luke reported. Modified: llvm-gcc-4.2/trunk/gcc/gcc.c Modified: llvm-gcc-4.2/trunk/gcc/gcc.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/gcc.c?rev=112522&r1=112521&r2=112522&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/gcc.c (original) +++ llvm-gcc-4.2/trunk/gcc/gcc.c Mon Aug 30 15:52:59 2010 @@ -721,6 +721,7 @@ %{use-gold-plugin: \ -plugin %(gold_plugin_file) \ -plugin-opt=as=%(gold_plugin_as) \ + %{m32:-plugin-opt=as-arg=--32} %{m64:-plugin-opt=as-arg=--64} \ } \ %l " LINK_PIE_SPEC "%X %{o*} %{A} %{d} % References: <20100830073339.A1A352A6C12D@llvm.org> <06E83978-57C6-4FC0-87E9-42AC9DE2993F@apple.com> <2562A51C-2385-46E6-B7A8-B6922703E0C9@mac.com> Message-ID: <4F5EC0B7-85DE-433F-BDF8-F4127786B711@apple.com> On Aug 30, 2010, at 12:58 PM, Owen Anderson wrote: > > On Aug 30, 2010, at 12:43 PM, Chris Lattner wrote: >> This sounds like a somewhat useful example, but its utility is limited by it compiling brainfuck (which noone knows and whose lessons don't apply directly to other languages). Why not turn this into a tutorial or something instead of an example in the main distribution? > > I do, in fact, have a sequence of tutorials in mind based on that, similar to the Kaleidoscope tutorials. > > Also, while I agree that it's not useful as a tool itself, I think most of the techniques I used in this should work for any language bytecode-compilable language. I just went with brainfuck because a small opcode set makes it easy to implement. :-) So back to the original point: why should this be in the tree? -Chris From clattner at apple.com Mon Aug 30 16:03:57 2010 From: clattner at apple.com (Chris Lattner) Date: Mon, 30 Aug 2010 14:03:57 -0700 Subject: [llvm-commits] PATCH: add ContextualDenseMap In-Reply-To: <4C7686B5.7060605@mxc.ca> References: <4C7686B5.7060605@mxc.ca> Message-ID: On Aug 26, 2010, at 8:22 AM, Nick Lewycky wrote: > This patch adds a new ContextualDenseMap and sinks most of the dense map logic into DenseMapImpl. A ContextualDenseMap takes a ContextualDenseMapInfo pointer instead of just a typename. I need this for mergefuncs where I want a comparison operation that involves target data. > > The four map info functions (getTombstoneKey, getEmptyKey, getHashValue and isEqual) are made virtual in DenseMapImpl and then implemented once in DenseMap and again in ContextualDenseMap. This implementation is modelled after the relationship between ContextualFoldingSet and FoldingSet. This seems like it will slow down densemap, perhaps substantially, by introducing virtual methods. It's also not clear to me what this is actually doing. Please explain what you are trying to do and why the current densemap can't do it. -Chris From criswell at uiuc.edu Mon Aug 30 16:13:14 2010 From: criswell at uiuc.edu (John Criswell) Date: Mon, 30 Aug 2010 21:13:14 -0000 Subject: [llvm-commits] [poolalloc] r112525 - /poolalloc/trunk/include/dsa/DSCallGraph.h Message-ID: <20100830211314.C14F02A6C12C@llvm.org> Author: criswell Date: Mon Aug 30 16:13:14 2010 New Revision: 112525 URL: http://llvm.org/viewvc/llvm-project?rev=112525&view=rev Log: Added spaces between comment delimiter and comment text. No functionality changes. Modified: poolalloc/trunk/include/dsa/DSCallGraph.h Modified: poolalloc/trunk/include/dsa/DSCallGraph.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/dsa/DSCallGraph.h?rev=112525&r1=112524&r2=112525&view=diff ============================================================================== --- poolalloc/trunk/include/dsa/DSCallGraph.h (original) +++ poolalloc/trunk/include/dsa/DSCallGraph.h Mon Aug 30 16:13:14 2010 @@ -31,24 +31,25 @@ typedef std::map SimpleCalleesTy; private: - //ActualCallees contains CallSite -> Function mappings + // ActualCallees contains CallSite -> set of Function mappings ActualCalleesTy ActualCallees; - //SimpleCallees contains Function -> Function mappings + + // SimpleCallees contains Function -> set of Functions mappings SimpleCalleesTy SimpleCallees; - //These are used for returning empty sets when the caller has no callees + // These are used for returning empty sets when the caller has no callees FuncSet EmptyActual; FuncSet EmptySimple; - //An equivalence class is exactly an SCC + // An equivalence class is exactly an SCC llvm::EquivalenceClasses SCCs; - //Functions we know about that aren't called + // Functions we know about that aren't called svset knownRoots; svset completeCS; - //Types for SCC construction + // Types for SCC construction typedef std::map TFMap; typedef std::vector TFStack; @@ -179,7 +180,7 @@ assert(F == SCCs.getLeaderValue(F) && "Not Leader?"); } - //common helper, no good reason for it to be here rather than elsewhere + // common helper; no good reason for it to be here rather than elsewhere static bool hasPointers(const llvm::Function* F); static bool hasPointers(llvm::CallSite& CS); From criswell at uiuc.edu Mon Aug 30 16:14:14 2010 From: criswell at uiuc.edu (John Criswell) Date: Mon, 30 Aug 2010 21:14:14 -0000 Subject: [llvm-commits] [poolalloc] r112526 - /poolalloc/trunk/lib/DSA/DSCallGraph.cpp Message-ID: <20100830211415.0EC3A2A6C12C@llvm.org> Author: criswell Date: Mon Aug 30 16:14:14 2010 New Revision: 112526 URL: http://llvm.org/viewvc/llvm-project?rev=112526&view=rev Log: Inserted comment and improved formatting. No functionality changes. Modified: poolalloc/trunk/lib/DSA/DSCallGraph.cpp Modified: poolalloc/trunk/lib/DSA/DSCallGraph.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DSCallGraph.cpp?rev=112526&r1=112525&r2=112526&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/DSCallGraph.cpp (original) +++ poolalloc/trunk/lib/DSA/DSCallGraph.cpp Mon Aug 30 16:14:14 2010 @@ -205,8 +205,22 @@ llvm::errs() << "\n"; } -//Filter all call edges. We only want pointer edges. -void DSCallGraph::insert(llvm::CallSite CS, const llvm::Function* F) { +// +// Method: insert() +// +// Description: +// Insert a new entry into the call graph. This entry says that the specified +// call site calls the specified function. +// +// Inputs: +// CS - The call site which calls the specified function. +// F - The function which is called. This is permitted to be NULL. It is +// possible to have call sites that don't have any targets, and sometimes +// users just want to ensure that a call site has an entry within the +// call graph. +// +void +DSCallGraph::insert(llvm::CallSite CS, const llvm::Function* F) { // // Find the function to which the call site belongs. // From clattner at apple.com Mon Aug 30 16:15:09 2010 From: clattner at apple.com (Chris Lattner) Date: Mon, 30 Aug 2010 14:15:09 -0700 Subject: [llvm-commits] [llvm] r112198 - in /llvm/trunk: lib/Transforms/Scalar/JumpThreading.cpp test/Transforms/JumpThreading/2010-08-26-and.ll In-Reply-To: <20100826174024.58E092A6C12C@llvm.org> References: <20100826174024.58E092A6C12C@llvm.org> Message-ID: <73DA2794-393C-430C-AB2C-6092A2FEC3DE@apple.com> On Aug 26, 2010, at 10:40 AM, Owen Anderson wrote: > URL: http://llvm.org/viewvc/llvm-project?rev=112198&view=rev > Log: > Make JumpThreading smart enough to properly thread StrSwitch when it's compiled with clang++. Thanks for working on this Owen, some feedback: > +++ llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Thu Aug 26 12:40:24 2010 > @@ -322,6 +322,12 @@ > if (isa(InVal) || isa(InVal)) { > ConstantInt *CI = dyn_cast(InVal); > Result.push_back(std::make_pair(CI, PN->getIncomingBlock(i))); > + } else if (LVI) { > + Constant *CI = LVI->getConstantOnEdge(InVal, > + PN->getIncomingBlock(i), BB); > + ConstantInt *CInt = dyn_cast_or_null(CI); > + if (CInt) > + Result.push_back(std::make_pair(CInt, PN->getIncomingBlock(i))); This should handle the case when "CI" is undefvalue as well (like the code right above it). > } > } > return !Result.empty(); > @@ -367,6 +373,10 @@ > } > } > return !Result.empty(); > + > + // Try to process a few other binary operator patterns. > + } else if (isa(I)) { > + > } This is cruft, please remove. > @@ -384,6 +394,21 @@ > cast(ConstantExpr::getNot(Result[i].first)); > return true; > } > + > + // Try to simplify some other binary operator values. > + } else if (BinaryOperator *BO = dyn_cast(I)) { > + // AND or OR of a value with itself is that value. > + ConstantInt *CI = dyn_cast(BO->getOperand(1)); > + if (CI && (BO->getOpcode() == Instruction::And || > + BO->getOpcode() == Instruction::Or)) { Indentation. > + SmallVector, 8> LHSVals; > + ComputeValueKnownInPredecessors(BO->getOperand(0), BB, LHSVals); > + for (unsigned i = 0, e = LHSVals.size(); i != e; ++i) > + if (LHSVals[i].first == CI) > + Result.push_back(std::make_pair(CI, LHSVals[i].second)); Indentation. I don't follow this logic. Why do you care if the constant*'s are equal? All you should care about is that LHSVals[i].first is treated like undef if null, then constant fold the and/or. > @@ -423,28 +448,63 @@ > // If comparing a live-in value against a constant, see if we know the > // live-in value on any predecessors. > if (LVI && isa(Cmp->getOperand(1)) && > + Cmp->getType()->isIntegerTy()) { > + if (!isa(Cmp->getOperand(0)) || > + cast(Cmp->getOperand(0))->getParent() != BB) { Indentation. Why would you want to accept non-instruction values here? It seems like the || should be an &&. > + Constant *RHSCst = cast(Cmp->getOperand(1)); > + > + for (pred_iterator PI = pred_begin(BB), E = pred_end(BB);PI != E; ++PI){ > + BasicBlock *P = *PI; > + // If the value is known by LazyValueInfo to be a constant in a > + // predecessor, use that information to try to thread this block. > + LazyValueInfo::Tristate Res = > + LVI->getPredicateOnEdge(Cmp->getPredicate(), Cmp->getOperand(0), > + RHSCst, P, BB); > + if (Res == LazyValueInfo::Unknown) > + continue; > > + Constant *ResC = ConstantInt::get(Cmp->getType(), Res); > + Result.push_back(std::make_pair(cast(ResC), P)); > + } > > - Constant *ResC = ConstantInt::get(Cmp->getType(), Res); > - Result.push_back(std::make_pair(cast(ResC), P)); > + return !Result.empty(); > + } > + > + // Try to find a constant value for the LHS of an equality comparison, > + // and evaluate it statically if we can. > + if (Cmp->getPredicate() == CmpInst::ICMP_EQ || > + Cmp->getPredicate() == CmpInst::ICMP_NE) { > + SmallVector, 8> LHSVals; > + ComputeValueKnownInPredecessors(I->getOperand(0), BB, LHSVals); > + > + ConstantInt *True = ConstantInt::getTrue(I->getContext()); > + ConstantInt *False = ConstantInt::getFalse(I->getContext()); > + if (Cmp->getPredicate() == CmpInst::ICMP_NE) std::swap(True, False); > + > + for (unsigned i = 0, e = LHSVals.size(); i != e; ++i) { > + if (LHSVals[i].first == Cmp->getOperand(1)) > + Result.push_back(std::make_pair(True, LHSVals[i].second)); > + else > + Result.push_back(std::make_pair(False, LHSVals[i].second)); > + } This is incorrect when ComputeValueKnownInPredecessors returns an entry of undef (aka null). As above, why are you limiting this to pointer equality of the ConstantInt's? Why don't you just use the existing constant folding apis, which would allow all comparisons to be handled? > + if (LVI) { > + // If all else fails, see if LVI can figure out a constant value for us. > + Constant *CI = LVI->getConstant(V, BB); > + ConstantInt *CInt = dyn_cast_or_null(CI); > + if (CInt) { > + for (pred_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI) > + Result.push_back(std::make_pair(CInt, *PI)); > + } > + > + return !Result.empty(); > + } Is this actually adding value over the code at ~line 300? > +++ llvm/trunk/test/Transforms/JumpThreading/2010-08-26-and.ll Thu Aug 26 12:40:24 2010 > @@ -0,0 +1,162 @@ > +; RUN: opt -jump-threading -enable-jump-threading-lvi -S < %s | FileCheck %s > + This is a useful macro-level testcase, but every major change that you committed in this patch should have a micro-level test. Jumpthreading has great tests already, please don't stop this tradition. -Chris > +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" > +target triple = "x86_64-apple-darwin10.0.0" > + > +%class.StringSwitch = type { i8*, i32, i32, i8 } > + > + at .str = private constant [4 x i8] c"red\00" ; <[4 x i8]*> [#uses=1] > + at .str1 = private constant [7 x i8] c"orange\00" ; <[7 x i8]*> [#uses=1] > + at .str2 = private constant [7 x i8] c"yellow\00" ; <[7 x i8]*> [#uses=1] > + at .str3 = private constant [6 x i8] c"green\00" ; <[6 x i8]*> [#uses=1] > + at .str4 = private constant [5 x i8] c"blue\00" ; <[5 x i8]*> [#uses=1] > + at .str5 = private constant [7 x i8] c"indigo\00" ; <[7 x i8]*> [#uses=1] > + at .str6 = private constant [7 x i8] c"violet\00" ; <[7 x i8]*> [#uses=1] > + at .str7 = private constant [12 x i8] c"Color = %d\0A\00" ; <[12 x i8]*> [#uses=1] > + > +define i32 @main(i32 %argc, i8** nocapture %argv) nounwind ssp { > +entry: > + %cmp142 = icmp sgt i32 %argc, 1 ; [#uses=1] > + br i1 %cmp142, label %bb.nph, label %for.end > + > +bb.nph: ; preds = %entry > + %tmp = add i32 %argc, -2 ; [#uses=1] > + %tmp144 = zext i32 %tmp to i64 ; [#uses=1] > + %tmp145 = add i64 %tmp144, 1 ; [#uses=1] > + br label %land.lhs.true.i > + > +land.lhs.true.i: ; preds = %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit134, %bb.nph > + %retval.0.i.pre161 = phi i32 [ undef, %bb.nph ], [ %retval.0.i.pre, %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit134 ] ; [#uses=3] > + %indvar = phi i64 [ 0, %bb.nph ], [ %tmp146, %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit134 ] ; [#uses=1] > + %tmp146 = add i64 %indvar, 1 ; [#uses=3] > + %arrayidx = getelementptr i8** %argv, i64 %tmp146 ; [#uses=1] > + %tmp6 = load i8** %arrayidx, align 8 ; [#uses=8] > + %call.i.i = call i64 @strlen(i8* %tmp6) nounwind ; [#uses=1] > + %conv.i.i = trunc i64 %call.i.i to i32 ; [#uses=6]\ > +; CHECK: switch i32 %conv.i.i > +; CHECK-NOT: if.then.i40 > +; CHECK: } > + switch i32 %conv.i.i, label %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit [ > + i32 3, label %land.lhs.true5.i > + i32 6, label %land.lhs.true5.i37 > + ] > + > +land.lhs.true5.i: ; preds = %land.lhs.true.i > + %call.i = call i32 @memcmp(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), i8* %tmp6, i64 4) nounwind ; [#uses=1] > + %cmp9.i = icmp eq i32 %call.i, 0 ; [#uses=1] > + br i1 %cmp9.i, label %_ZN12StringSwitchI5ColorE4CaseILj4EEERS1_RAT__KcRKS0_.exit, label %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit > + > +_ZN12StringSwitchI5ColorE4CaseILj4EEERS1_RAT__KcRKS0_.exit: ; preds = %land.lhs.true5.i > + br label %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit > + > +land.lhs.true5.i37: ; preds = %land.lhs.true.i > + %call.i35 = call i32 @memcmp(i8* getelementptr inbounds ([7 x i8]* @.str1, i64 0, i64 0), i8* %tmp6, i64 7) nounwind ; [#uses=1] > + %cmp9.i36 = icmp eq i32 %call.i35, 0 ; [#uses=1] > + br i1 %cmp9.i36, label %if.then.i40, label %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit > + > +if.then.i40: ; preds = %land.lhs.true5.i37 > + br label %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit > + > +_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit: ; preds = %if.then.i40, %land.lhs.true5.i37, %_ZN12StringSwitchI5ColorE4CaseILj4EEERS1_RAT__KcRKS0_.exit, %land.lhs.true5.i, %land.lhs.true.i > + %retval.0.i.pre159 = phi i32 [ 1, %_ZN12StringSwitchI5ColorE4CaseILj4EEERS1_RAT__KcRKS0_.exit ], [ %retval.0.i.pre161, %land.lhs.true5.i37 ], [ 2, %if.then.i40 ], [ %retval.0.i.pre161, %land.lhs.true5.i ], [ %retval.0.i.pre161, %land.lhs.true.i ] ; [#uses=2] > + %tmp2.i44 = phi i8 [ 1, %_ZN12StringSwitchI5ColorE4CaseILj4EEERS1_RAT__KcRKS0_.exit ], [ 0, %land.lhs.true5.i37 ], [ 1, %if.then.i40 ], [ 0, %land.lhs.true5.i ], [ 0, %land.lhs.true.i ] ; [#uses=3] > + %tobool.i46 = icmp eq i8 %tmp2.i44, 0 ; [#uses=1] > + %cmp.i49 = icmp eq i32 %conv.i.i, 6 ; [#uses=1] > + %or.cond = and i1 %tobool.i46, %cmp.i49 ; [#uses=1] > + br i1 %or.cond, label %land.lhs.true5.i55, label %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit60 > + > +land.lhs.true5.i55: ; preds = %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit > + %call.i53 = call i32 @memcmp(i8* getelementptr inbounds ([7 x i8]* @.str2, i64 0, i64 0), i8* %tmp6, i64 7) nounwind ; [#uses=1] > + %cmp9.i54 = icmp eq i32 %call.i53, 0 ; [#uses=1] > + br i1 %cmp9.i54, label %if.then.i58, label %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit60 > + > +if.then.i58: ; preds = %land.lhs.true5.i55 > + br label %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit60 > + > +_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit60: ; preds = %if.then.i58, %land.lhs.true5.i55, %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit > + %retval.0.i.pre158 = phi i32 [ %retval.0.i.pre159, %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit ], [ %retval.0.i.pre159, %land.lhs.true5.i55 ], [ 3, %if.then.i58 ] ; [#uses=2] > + %tmp2.i63 = phi i8 [ %tmp2.i44, %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit ], [ %tmp2.i44, %land.lhs.true5.i55 ], [ 1, %if.then.i58 ] ; [#uses=3] > + %tmp14.i64 = and i8 %tmp2.i63, 1 ; [#uses=1] > + %tobool.i65 = icmp eq i8 %tmp14.i64, 0 ; [#uses=1] > + %cmp.i68 = icmp eq i32 %conv.i.i, 5 ; [#uses=1] > + %or.cond168 = and i1 %tobool.i65, %cmp.i68 ; [#uses=1] > + br i1 %or.cond168, label %land.lhs.true5.i74, label %_ZN12StringSwitchI5ColorE4CaseILj6EEERS1_RAT__KcRKS0_.exit > + > +land.lhs.true5.i74: ; preds = %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit60 > + %call.i72 = call i32 @memcmp(i8* getelementptr inbounds ([6 x i8]* @.str3, i64 0, i64 0), i8* %tmp6, i64 6) nounwind ; [#uses=1] > + %cmp9.i73 = icmp eq i32 %call.i72, 0 ; [#uses=1] > + br i1 %cmp9.i73, label %if.then.i77, label %_ZN12StringSwitchI5ColorE4CaseILj6EEERS1_RAT__KcRKS0_.exit > + > +if.then.i77: ; preds = %land.lhs.true5.i74 > + br label %_ZN12StringSwitchI5ColorE4CaseILj6EEERS1_RAT__KcRKS0_.exit > + > +_ZN12StringSwitchI5ColorE4CaseILj6EEERS1_RAT__KcRKS0_.exit: ; preds = %if.then.i77, %land.lhs.true5.i74, %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit60 > + %retval.0.i.pre157 = phi i32 [ %retval.0.i.pre158, %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit60 ], [ %retval.0.i.pre158, %land.lhs.true5.i74 ], [ 4, %if.then.i77 ] ; [#uses=2] > + %tmp2.i81 = phi i8 [ %tmp2.i63, %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit60 ], [ %tmp2.i63, %land.lhs.true5.i74 ], [ 1, %if.then.i77 ] ; [#uses=3] > + %tmp14.i82 = and i8 %tmp2.i81, 1 ; [#uses=1] > + %tobool.i83 = icmp eq i8 %tmp14.i82, 0 ; [#uses=1] > + %cmp.i86 = icmp eq i32 %conv.i.i, 4 ; [#uses=1] > + %or.cond169 = and i1 %tobool.i83, %cmp.i86 ; [#uses=1] > + br i1 %or.cond169, label %land.lhs.true5.i92, label %_ZN12StringSwitchI5ColorE4CaseILj5EEERS1_RAT__KcRKS0_.exit > + > +land.lhs.true5.i92: ; preds = %_ZN12StringSwitchI5ColorE4CaseILj6EEERS1_RAT__KcRKS0_.exit > + %call.i90 = call i32 @memcmp(i8* getelementptr inbounds ([5 x i8]* @.str4, i64 0, i64 0), i8* %tmp6, i64 5) nounwind ; [#uses=1] > + %cmp9.i91 = icmp eq i32 %call.i90, 0 ; [#uses=1] > + br i1 %cmp9.i91, label %if.then.i95, label %_ZN12StringSwitchI5ColorE4CaseILj5EEERS1_RAT__KcRKS0_.exit > + > +if.then.i95: ; preds = %land.lhs.true5.i92 > + br label %_ZN12StringSwitchI5ColorE4CaseILj5EEERS1_RAT__KcRKS0_.exit > + > +_ZN12StringSwitchI5ColorE4CaseILj5EEERS1_RAT__KcRKS0_.exit: ; preds = %if.then.i95, %land.lhs.true5.i92, %_ZN12StringSwitchI5ColorE4CaseILj6EEERS1_RAT__KcRKS0_.exit > + %retval.0.i.pre156 = phi i32 [ %retval.0.i.pre157, %_ZN12StringSwitchI5ColorE4CaseILj6EEERS1_RAT__KcRKS0_.exit ], [ %retval.0.i.pre157, %land.lhs.true5.i92 ], [ 5, %if.then.i95 ] ; [#uses=2] > + %tmp2.i99 = phi i8 [ %tmp2.i81, %_ZN12StringSwitchI5ColorE4CaseILj6EEERS1_RAT__KcRKS0_.exit ], [ %tmp2.i81, %land.lhs.true5.i92 ], [ 1, %if.then.i95 ] ; [#uses=3] > + %tmp14.i100 = and i8 %tmp2.i99, 1 ; [#uses=1] > + %tobool.i101 = icmp eq i8 %tmp14.i100, 0 ; [#uses=1] > + %cmp.i104 = icmp eq i32 %conv.i.i, 6 ; [#uses=1] > + %or.cond170 = and i1 %tobool.i101, %cmp.i104 ; [#uses=1] > + br i1 %or.cond170, label %land.lhs.true5.i110, label %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit115 > + > +land.lhs.true5.i110: ; preds = %_ZN12StringSwitchI5ColorE4CaseILj5EEERS1_RAT__KcRKS0_.exit > + %call.i108 = call i32 @memcmp(i8* getelementptr inbounds ([7 x i8]* @.str5, i64 0, i64 0), i8* %tmp6, i64 7) nounwind ; [#uses=1] > + %cmp9.i109 = icmp eq i32 %call.i108, 0 ; [#uses=1] > + br i1 %cmp9.i109, label %if.then.i113, label %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit115 > + > +if.then.i113: ; preds = %land.lhs.true5.i110 > + br label %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit115 > + > +_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit115: ; preds = %if.then.i113, %land.lhs.true5.i110, %_ZN12StringSwitchI5ColorE4CaseILj5EEERS1_RAT__KcRKS0_.exit > + %retval.0.i.pre155 = phi i32 [ %retval.0.i.pre156, %_ZN12StringSwitchI5ColorE4CaseILj5EEERS1_RAT__KcRKS0_.exit ], [ %retval.0.i.pre156, %land.lhs.true5.i110 ], [ 6, %if.then.i113 ] ; [#uses=2] > + %tmp2.i118 = phi i8 [ %tmp2.i99, %_ZN12StringSwitchI5ColorE4CaseILj5EEERS1_RAT__KcRKS0_.exit ], [ %tmp2.i99, %land.lhs.true5.i110 ], [ 1, %if.then.i113 ] ; [#uses=3] > + %tmp14.i119 = and i8 %tmp2.i118, 1 ; [#uses=1] > + %tobool.i120 = icmp eq i8 %tmp14.i119, 0 ; [#uses=1] > + %cmp.i123 = icmp eq i32 %conv.i.i, 6 ; [#uses=1] > + %or.cond171 = and i1 %tobool.i120, %cmp.i123 ; [#uses=1] > + br i1 %or.cond171, label %land.lhs.true5.i129, label %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit134 > + > +land.lhs.true5.i129: ; preds = %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit115 > + %call.i127 = call i32 @memcmp(i8* getelementptr inbounds ([7 x i8]* @.str6, i64 0, i64 0), i8* %tmp6, i64 7) nounwind ; [#uses=1] > + %cmp9.i128 = icmp eq i32 %call.i127, 0 ; [#uses=1] > + br i1 %cmp9.i128, label %if.then.i132, label %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit134 > + > +if.then.i132: ; preds = %land.lhs.true5.i129 > + br label %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit134 > + > +_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit134: ; preds = %if.then.i132, %land.lhs.true5.i129, %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit115 > + %retval.0.i.pre = phi i32 [ %retval.0.i.pre155, %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit115 ], [ %retval.0.i.pre155, %land.lhs.true5.i129 ], [ 7, %if.then.i132 ] ; [#uses=2] > + %tmp2.i137 = phi i8 [ %tmp2.i118, %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit115 ], [ %tmp2.i118, %land.lhs.true5.i129 ], [ 1, %if.then.i132 ] ; [#uses=1] > + %tmp7.i138 = and i8 %tmp2.i137, 1 ; [#uses=1] > + %tobool.i139 = icmp eq i8 %tmp7.i138, 0 ; [#uses=1] > + %retval.0.i = select i1 %tobool.i139, i32 0, i32 %retval.0.i.pre ; [#uses=1] > + %call22 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([12 x i8]* @.str7, i64 0, i64 0), i32 %retval.0.i) ; [#uses=0] > + %exitcond = icmp eq i64 %tmp146, %tmp145 ; [#uses=1] > + br i1 %exitcond, label %for.end, label %land.lhs.true.i > + > +for.end: ; preds = %_ZN12StringSwitchI5ColorE4CaseILj7EEERS1_RAT__KcRKS0_.exit134, %entry > + ret i32 0 > +} > + > +declare i32 @printf(i8* nocapture, ...) nounwind > + > +declare i32 @memcmp(i8* nocapture, i8* nocapture, i64) nounwind readonly > + > +declare i64 @strlen(i8* nocapture) nounwind readonly > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From gohman at apple.com Mon Aug 30 16:18:41 2010 From: gohman at apple.com (Dan Gohman) Date: Mon, 30 Aug 2010 21:18:41 -0000 Subject: [llvm-commits] [llvm] r112528 - /llvm/trunk/lib/VMCore/Metadata.cpp Message-ID: <20100830211841.D2C952A6C12C@llvm.org> Author: djg Date: Mon Aug 30 16:18:41 2010 New Revision: 112528 URL: http://llvm.org/viewvc/llvm-project?rev=112528&view=rev Log: Add comments explaining why it's not necessary to include the is-function-local flag in metadata uniquing bits. Modified: llvm/trunk/lib/VMCore/Metadata.cpp Modified: llvm/trunk/lib/VMCore/Metadata.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Metadata.cpp?rev=112528&r1=112527&r2=112528&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Metadata.cpp (original) +++ llvm/trunk/lib/VMCore/Metadata.cpp Mon Aug 30 16:18:41 2010 @@ -190,6 +190,8 @@ // Add all the operand pointers. Note that we don't have to add the // isFunctionLocal bit because that's implied by the operands. + // Note that if the operands are later nulled out, the node will be + // removed from the uniquing map. FoldingSetNodeID ID; for (unsigned i = 0; i != NumVals; ++i) ID.AddPointer(Vals[i]); @@ -276,6 +278,8 @@ void MDNode::Profile(FoldingSetNodeID &ID) const { // Add all the operand pointers. Note that we don't have to add the // isFunctionLocal bit because that's implied by the operands. + // Note that if the operands are later nulled out, the node will be + // removed from the uniquing map. for (unsigned i = 0, e = getNumOperands(); i != e; ++i) ID.AddPointer(getOperand(i)); } @@ -326,7 +330,8 @@ // If we are dropping an argument to null, we choose to not unique the MDNode // anymore. This commonly occurs during destruction, and uniquing these - // brings little reuse. + // brings little reuse. Also, this means we don't need to include + // isFunctionLocal bits in FoldingSetNodeIDs for MDNodes. if (To == 0) { setIsNotUniqued(); return; From resistor at mac.com Mon Aug 30 16:22:45 2010 From: resistor at mac.com (Owen Anderson) Date: Mon, 30 Aug 2010 14:22:45 -0700 Subject: [llvm-commits] [llvm] r112465 - in /llvm/trunk/examples: Makefile TracingBrainF/ TracingBrainF/BrainF.h TracingBrainF/BrainFCodeGen.cpp TracingBrainF/BrainFInterpreter.cpp TracingBrainF/BrainFOpcodes.cpp TracingBrainF/BrainFTraceRecorder.cpp TracingBrainF/BrainFVM.h TracingBrainF/Makefile TracingBrainF/README In-Reply-To: <4F5EC0B7-85DE-433F-BDF8-F4127786B711@apple.com> References: <20100830073339.A1A352A6C12D@llvm.org> <06E83978-57C6-4FC0-87E9-42AC9DE2993F@apple.com> <2562A51C-2385-46E6-B7A8-B6922703E0C9@mac.com> <4F5EC0B7-85DE-433F-BDF8-F4127786B711@apple.com> Message-ID: <03DC4E98-155B-4BF1-B6CA-0E6D7B791A55@mac.com> On Aug 30, 2010, at 1:57 PM, Chris Lattner wrote: > So back to the original point: why should this be in the tree? In principle, because I thought it was a useful example on the level with our existing ones. If tutorialize-it, I would like to keep a copy in-tree, just like we do for Kaleidoscope, so that we can detect when API changes require an update. That said, I'll be happy to host it out-of-tree until such time as the tutorial is written, if you'd prefer. --Owen -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100830/0ed6c6a3/attachment.html From clattner at apple.com Mon Aug 30 16:26:20 2010 From: clattner at apple.com (Chris Lattner) Date: Mon, 30 Aug 2010 14:26:20 -0700 Subject: [llvm-commits] [llvm] r111665 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp test/Transforms/InstCombine/2010-08-19-StoreNarrowing.ll In-Reply-To: <20100820182443.4552E2A6C12E@llvm.org> References: <20100820182443.4552E2A6C12E@llvm.org> Message-ID: On Aug 20, 2010, at 11:24 AM, Owen Anderson wrote: > Author: resistor > Date: Fri Aug 20 13:24:43 2010 > New Revision: 111665 > > URL: http://llvm.org/viewvc/llvm-project?rev=111665&view=rev > Log: > Re-apply r111568 with a fix for the clang self-host. Alright. Please include a useful commit message though, so I don't have to go look at r111568 to find out what this does. Some thoughts: > @@ -473,6 +475,51 @@ > > if (SI.isVolatile()) return 0; // Don't hack volatile stores. > > + // Attempt to narrow sequences where we load a wide value, perform bitmasks > + // that only affect the low bits of it, and then store it back. This > + // typically arises from bitfield initializers in C++. Why is this better to do in instcombine than dagcombine? Unless the code is already type-unsafe, we typically do *not* want to do this in the mid-level. In your specific testcase, there is a bitcast of the pointer and you're actually *improving* type safety, but there is nothing in the xform that encourages this. > + ConstantInt *CI1 =0, *CI2 = 0; > + Value *Ld = 0; > + if (getTargetData() && > + match(SI.getValueOperand(), > + m_And(m_Or(m_Value(Ld), m_ConstantInt(CI1)), m_ConstantInt(CI2))) && > + isa(Ld) && > + equivalentAddressValues(cast(Ld)->getPointerOperand(), Ptr)) { I don't see where you check to make sure you don't have something like: x = load P store 123 -> Q ;; might alias P! x' = stuff(x) store x' -> P How do you know the loaded value hasn't been changed in memory? Also, you don't check for a volatile load here. > + APInt OrMask = CI1->getValue(); > + APInt AndMask = CI2->getValue(); No need to copy the APInt's. > + // Compute the prefix of the value that is unmodified by the bitmasking. > + unsigned LeadingAndOnes = AndMask.countLeadingOnes(); > + unsigned LeadingOrZeros = OrMask.countLeadingZeros(); > + unsigned Prefix = std::min(LeadingAndOnes, LeadingOrZeros); > + uint64_t NewWidth = AndMask.getBitWidth() - Prefix; > + while (NewWidth < AndMask.getBitWidth() && > + getTargetData()->isIllegalInteger(NewWidth)) > + NewWidth = NextPowerOf2(NewWidth); It would be cleaner to just use TD directly instead of calling getTargetData() all over. > + // If we can find a power-of-2 prefix (and if the values we're working with > + // are themselves POT widths), then we can narrow the store. We rely on > + // later iterations of instcombine to propagate the demanded bits to narrow > + // the other computations in the chain. > + if (NewWidth < AndMask.getBitWidth() && > + getTargetData()->isLegalInteger(NewWidth)) { > + const Type *NewType = IntegerType::get(Ptr->getContext(), NewWidth); > + const Type *NewPtrType = PointerType::getUnqual(NewType); This pointer type needs to be in the same address space as the original load/store. > +++ llvm/trunk/test/Transforms/InstCombine/2010-08-19-StoreNarrowing.ll Fri Aug 20 13:24:43 2010 This should be folded into an existing testcase, and should not be dated. > @@ -0,0 +1,21 @@ > +; RUN: opt -S -instcombine %s | not grep and This should use filecheck. Have you looked at what instcombine turns this into? I suspect it isn't what you're expecting. > +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" > +target triple = "x86_64-apple-darwin10.0.0" > + > +%class.A = type { i8, [3 x i8] } > + > +define void @_ZN1AC2Ev(%class.A* %this) nounwind ssp align 2 { This should not use a mangled name. -Chris > +entry: > + %0 = bitcast %class.A* %this to i32* ; [#uses=5] > + %1 = load i32* %0, align 4 ; [#uses=1] > + %2 = and i32 %1, -8 ; [#uses=2] > + store i32 %2, i32* %0, align 4 > + %3 = and i32 %2, -57 ; [#uses=1] > + %4 = or i32 %3, 8 ; [#uses=2] > + store i32 %4, i32* %0, align 4 > + %5 = and i32 %4, -65 ; [#uses=2] > + store i32 %5, i32* %0, align 4 > + %6 = and i32 %5, -129 ; [#uses=1] > + store i32 %6, i32* %0, align 4 > + ret void > +} > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From clattner at apple.com Mon Aug 30 16:32:43 2010 From: clattner at apple.com (Chris Lattner) Date: Mon, 30 Aug 2010 14:32:43 -0700 Subject: [llvm-commits] [llvm] r110382 - in /llvm/trunk: lib/Analysis/BasicAliasAnalysis.cpp lib/Analysis/MemoryDependenceAnalysis.cpp test/Analysis/BasicAA/getmodrefinfo-cs-cs.ll In-Reply-To: <20100805220915.C1C152A6C12C@llvm.org> References: <20100805220915.C1C152A6C12C@llvm.org> Message-ID: <376524FB-B764-4C0C-9CEE-7E64FB0C8969@apple.com> On Aug 5, 2010, at 3:09 PM, Dan Gohman wrote: > Author: djg > Date: Thu Aug 5 17:09:15 2010 > New Revision: 110382 > > URL: http://llvm.org/viewvc/llvm-project?rev=110382&view=rev > Log: > Fix memdep's code for reasoning about dependences between two calls. A Ref > response from getModRefInfo is not useful here. Instead, check for identical > calls only in the NoModRef case. > > Reapply r110270, and strengthen it to compensate for the memdep changes. > When both calls are readonly, there is no dependence between them. Hi Dan, if you're changing the semantics of the mod/ref queries here, please update this comment in AliasAnalysis.h: /// getModRefInfo - Return information about whether two call sites may refer /// to the same set of memory locations. This function returns NoModRef if /// the two calls refer to disjoint memory locations, Ref if CS1 reads memory /// written by CS2, Mod if CS1 writes to memory read or written by CS2, or /// ModRef if CS1 might read or write memory accessed by CS2. /// virtual ModRefResult getModRefInfo(ImmutableCallSite CS1, ImmutableCallSite CS2); also here: http://llvm.org/docs/AliasAnalysis.html#ModRefInfo Note that the call/call modref query should probably return its own (richer) enum than ModRefResult if you're interested in this going forward. -Chris From clattner at apple.com Mon Aug 30 16:33:51 2010 From: clattner at apple.com (Chris Lattner) Date: Mon, 30 Aug 2010 14:33:51 -0700 Subject: [llvm-commits] [llvm] r112465 - in /llvm/trunk/examples: Makefile TracingBrainF/ TracingBrainF/BrainF.h TracingBrainF/BrainFCodeGen.cpp TracingBrainF/BrainFInterpreter.cpp TracingBrainF/BrainFOpcodes.cpp TracingBrainF/BrainFTraceRecorder.cpp TracingBrainF/BrainFVM.h TracingBrainF/Makefile TracingBrainF/README In-Reply-To: <03DC4E98-155B-4BF1-B6CA-0E6D7B791A55@mac.com> References: <20100830073339.A1A352A6C12D@llvm.org> <06E83978-57C6-4FC0-87E9-42AC9DE2993F@apple.com> <2562A51C-2385-46E6-B7A8-B6922703E0C9@mac.com> <4F5EC0B7-85DE-433F-BDF8-F4127786B711@apple.com> <03DC4E98-155B-4BF1-B6CA-0E6D7B791A55@mac.com> Message-ID: <09B83E91-64AA-4872-AA57-D744C9F30BE0@apple.com> On Aug 30, 2010, at 2:22 PM, Owen Anderson wrote: > > On Aug 30, 2010, at 1:57 PM, Chris Lattner wrote: > >> So back to the original point: why should this be in the tree? > > In principle, because I thought it was a useful example on the level with our existing ones. If tutorialize-it, I would like to keep a copy in-tree, just like we do for Kaleidoscope, so that we can detect when API changes require an update. > > That said, I'll be happy to host it out-of-tree until such time as the tutorial is written, if you'd prefer. I'd prefer it to be out of three. The bar for examples (and tutorials) should be very high, I don't think anything relating to brainfuck passes that bar. And yes, I strongly support removing the BrainF example. -Chris -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100830/286a5f00/attachment.html From resistor at mac.com Mon Aug 30 16:34:26 2010 From: resistor at mac.com (Owen Anderson) Date: Mon, 30 Aug 2010 21:34:26 -0000 Subject: [llvm-commits] [llvm] r112529 - /llvm/trunk/examples/TracingBrainF/ Message-ID: <20100830213426.E9B622A6C12C@llvm.org> Author: resistor Date: Mon Aug 30 16:34:26 2010 New Revision: 112529 URL: http://llvm.org/viewvc/llvm-project?rev=112529&view=rev Log: Remove this from the main tree. I'll host it out of tree. Removed: llvm/trunk/examples/TracingBrainF/ From stuart at apple.com Mon Aug 30 16:40:50 2010 From: stuart at apple.com (Stuart Hastings) Date: Mon, 30 Aug 2010 21:40:50 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r112531 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Message-ID: <20100830214050.BD6D92A6C12C@llvm.org> Author: stuart Date: Mon Aug 30 16:40:50 2010 New Revision: 112531 URL: http://llvm.org/viewvc/llvm-project?rev=112531&view=rev Log: Fix an assertion in the GCC DejaGNU testsuite. Radar 8251350. Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=112531&r1=112530&r2=112531&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Mon Aug 30 16:40:50 2010 @@ -5519,6 +5519,10 @@ EmitBuiltinUnaryOp(Amt, Result, Intrinsic::ctpop); Result = Builder.CreateBinOp(Instruction::And, Result, ConstantInt::get(Result->getType(), 1)); + const Type *DestTy = ConvertType(TREE_TYPE(exp)); + Result = Builder.CreateIntCast(Result, DestTy, + !TYPE_UNSIGNED(TREE_TYPE(exp)), + "cast"); return true; } case BUILT_IN_POPCOUNT: // These GCC builtins always return int. From gohman at apple.com Mon Aug 30 16:41:21 2010 From: gohman at apple.com (Dan Gohman) Date: Mon, 30 Aug 2010 21:41:21 -0000 Subject: [llvm-commits] [llvm] r112532 - /llvm/trunk/tools/llc/llc.cpp Message-ID: <20100830214121.168B22A6C12C@llvm.org> Author: djg Date: Mon Aug 30 16:41:20 2010 New Revision: 112532 URL: http://llvm.org/viewvc/llvm-project?rev=112532&view=rev Log: Fix llc to run the verifier once, not twice. Modified: llvm/trunk/tools/llc/llc.cpp Modified: llvm/trunk/tools/llc/llc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llc/llc.cpp?rev=112532&r1=112531&r2=112532&view=diff ============================================================================== --- llvm/trunk/tools/llc/llc.cpp (original) +++ llvm/trunk/tools/llc/llc.cpp Mon Aug 30 16:41:20 2010 @@ -18,7 +18,6 @@ #include "llvm/PassManager.h" #include "llvm/Pass.h" #include "llvm/ADT/Triple.h" -#include "llvm/Analysis/Verifier.h" #include "llvm/Support/IRReader.h" #include "llvm/CodeGen/LinkAllAsmWriterComponents.h" #include "llvm/CodeGen/LinkAllCodegenComponents.h" @@ -295,14 +294,6 @@ case '3': OLvl = CodeGenOpt::Aggressive; break; } - // Request that addPassesToEmitFile run the Verifier after running - // passes which modify the IR. -#ifndef NDEBUG - bool DisableVerify = false; -#else - bool DisableVerify = true; -#endif - // Build up all of the passes that we want to do to the module. PassManager PM; @@ -312,9 +303,6 @@ else PM.add(new TargetData(&mod)); - if (!NoVerify) - PM.add(createVerifierPass()); - // Override default to generate verbose assembly. Target.setAsmVerbosityDefault(true); @@ -328,7 +316,7 @@ // Ask the target to add backend passes as necessary. if (Target.addPassesToEmitFile(PM, *Out, FileType, OLvl, - DisableVerify)) { + NoVerify)) { errs() << argv[0] << ": target does not support generation of this" << " file type!\n"; return 1; From nlewycky at google.com Mon Aug 30 16:52:30 2010 From: nlewycky at google.com (Nick Lewycky) Date: Mon, 30 Aug 2010 14:52:30 -0700 Subject: [llvm-commits] PATCH: add ContextualDenseMap In-Reply-To: References: <4C7686B5.7060605@mxc.ca> Message-ID: On 30 August 2010 14:03, Chris Lattner wrote: > > On Aug 26, 2010, at 8:22 AM, Nick Lewycky wrote: > > > This patch adds a new ContextualDenseMap and sinks most of the dense map > logic into DenseMapImpl. A ContextualDenseMap takes a ContextualDenseMapInfo > pointer instead of just a typename. I need this for mergefuncs where I want > a comparison operation that involves target data. > > > > The four map info functions (getTombstoneKey, getEmptyKey, getHashValue > and isEqual) are made virtual in DenseMapImpl and then implemented once in > DenseMap and again in ContextualDenseMap. This implementation is modelled > after the relationship between ContextualFoldingSet and FoldingSet. > > This seems like it will slow down densemap, perhaps substantially, by > introducing virtual methods. That matches my reaction when looking at FoldingSet but I decided that someone else probably knows more than I do. I'll change this, and probably FoldingSet too. > It's also not clear to me what this is actually doing. Please explain what > you are trying to do and why the current densemap can't do it. > My implementation of isEqual for MergeFunctions requires a TargetData object. Because the existing DenseMap takes a type and not an object, and the DenseMapInfo methods are all static, I can't give it a TargetData* to use unless I'm willing to stick it in a global variable. (And if you prefer that, let me know; I'd ruled it out.) I use the TargetData to determine whether or not two GEPs are going to advance the pointer by the same number of bytes. There is some lousy fallback code for when TargetData is not available, and I could try enhancing that instead, but it will never work as well as just using the TD. Nick -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100830/3b342847/attachment.html From stoklund at 2pi.dk Mon Aug 30 16:52:40 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 30 Aug 2010 21:52:40 -0000 Subject: [llvm-commits] [llvm] r112534 - /llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Message-ID: <20100830215240.61EE42A6C12C@llvm.org> Author: stoklund Date: Mon Aug 30 16:52:40 2010 New Revision: 112534 URL: http://llvm.org/viewvc/llvm-project?rev=112534&view=rev Log: Remember to clear the shadow kill flag at the same time as clearing the real kill flag. This could cause duplicate kill flags when the same register was used twice in a continuous sequence of STRs. There is no small test case. Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=112534&r1=112533&r2=112534&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Mon Aug 30 16:52:40 2010 @@ -324,6 +324,7 @@ if (KilledRegs.count(Reg)) { unsigned j = Killer[Reg]; memOps[j].MBBI->getOperand(0).setIsKill(false); + memOps[j].isKill = false; } } MBB.erase(memOps[i].MBBI); From geek4civic at gmail.com Mon Aug 30 16:54:03 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Mon, 30 Aug 2010 21:54:03 -0000 Subject: [llvm-commits] [llvm] r112535 - /llvm/trunk/lib/ExecutionEngine/JIT/Intercept.cpp Message-ID: <20100830215403.5AB092A6C12C@llvm.org> Author: chapuni Date: Mon Aug 30 16:54:03 2010 New Revision: 112535 URL: http://llvm.org/viewvc/llvm-project?rev=112535&view=rev Log: Fix a comment. Modified: llvm/trunk/lib/ExecutionEngine/JIT/Intercept.cpp Modified: llvm/trunk/lib/ExecutionEngine/JIT/Intercept.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/Intercept.cpp?rev=112535&r1=112534&r2=112535&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/JIT/Intercept.cpp (original) +++ llvm/trunk/lib/ExecutionEngine/JIT/Intercept.cpp Mon Aug 30 16:54:03 2010 @@ -108,7 +108,7 @@ if (Name == "exit") return (void*)(intptr_t)&jit_exit; if (Name == "atexit") return (void*)(intptr_t)&jit_atexit; - // We shuold not invoke parent's ctors/dtors from main()! (PR3897) + // We should not invoke parent's ctors/dtors from generated main()! // On Mingw and Cygwin, the symbol __main is resolved to // callee's(eg. tools/lli) one, to invoke wrong duplicated ctors // (and register wrong callee's dtors with atexit(3)). From geek4civic at gmail.com Mon Aug 30 16:57:37 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Tue, 31 Aug 2010 06:57:37 +0900 Subject: [llvm-commits] [llvm] r112474 - /llvm/trunk/lib/ExecutionEngine/JIT/Intercept.cpp In-Reply-To: <4AB40126-ABA2-428F-86D1-679CF573FC89@apple.com> References: <20100830140029.A16DB2A6C12C@llvm.org> <4AB40126-ABA2-428F-86D1-679CF573FC89@apple.com> Message-ID: 2010/8/31 Chris Lattner : >> + ? ?// We shuold not invoke parent's ctors/dtors from main()! (PR3897) > > typo "should", also, please don't put PR#'s into the code. ?Thanks for fixing this! I have fixed in r112535. Thank you to point out. good morning...Takumi From isanbard at gmail.com Mon Aug 30 17:05:23 2010 From: isanbard at gmail.com (Bill Wendling) Date: Mon, 30 Aug 2010 22:05:23 -0000 Subject: [llvm-commits] [llvm] r112538 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrThumb2.td Message-ID: <20100830220523.4D0892A6C12C@llvm.org> Author: void Date: Mon Aug 30 17:05:23 2010 New Revision: 112538 URL: http://llvm.org/viewvc/llvm-project?rev=112538&view=rev Log: Use the existing T2I_bin_s_irs pattern instead of creating T2I_bin_sw_irs, which is meant to do exactly the same thing. Thanks to Jim Grosbach for pointing this out! :-) Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=112538&r1=112537&r2=112538&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Mon Aug 30 17:05:23 2010 @@ -1148,22 +1148,6 @@ list Predicates = [IsThumb2]; } -// Same as Thumb2sI except it does modify CPSR. Note it's modeled as an input -// operand since by default it's a zero register. It will become an implicit def -// once it's "flipped". -// FIXME: This uses unified syntax so {s} comes before {p}. We should make it -// more consistent. -class Thumb2sI_cpsr pattern> - : InstARM { - let OutOperandList = oops; - let InOperandList = !con(iops, (ins pred:$p, s_cc_out:$s)); - let AsmString = !strconcat(opc, !strconcat("${s}${p}", asm)); - let Pattern = pattern; - list Predicates = [IsThumb2]; -} - // Special cases class Thumb2XI pattern> : Thumb2sI; -class T2sI_cpsr pattern> - : Thumb2sI_cpsr; - class T2XI pattern> : Thumb2XI; Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=112538&r1=112537&r2=112538&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Aug 30 17:05:23 2010 @@ -249,57 +249,12 @@ } } -/// T2I_bin_cpsr_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for -/// a binary operation that produces a value. These are predicable and modify -/// CPSR. -multiclass T2I_bin_cpsr_irs opcod, string opc, PatFrag opnode, - bit Commutable = 0, string wide = ""> { - // shifted imm - def ri : T2sI_cpsr<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_imm:$rhs), - IIC_iALUi, opc, "\t$dst, $lhs, $rhs", - [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_imm:$rhs))]> { - let Inst{31-27} = 0b11110; - let Inst{25} = 0; - let Inst{24-21} = opcod; - let Inst{20} = 1; // The S bit. - let Inst{15} = 0; - } - // register - def rr : T2sI_cpsr<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs), - IIC_iALUr, opc, !strconcat(wide, "\t$dst, $lhs, $rhs"), - [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]> { - let isCommutable = Commutable; - let Inst{31-27} = 0b11101; - let Inst{26-25} = 0b01; - let Inst{24-21} = opcod; - let Inst{20} = 1; // The S bit. - let Inst{14-12} = 0b000; // imm3 - let Inst{7-6} = 0b00; // imm2 - let Inst{5-4} = 0b00; // type - } - // shifted register - def rs : T2sI_cpsr<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_reg:$rhs), - IIC_iALUsi, opc, !strconcat(wide, "\t$dst, $lhs, $rhs"), - [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_reg:$rhs))]> { - let Inst{31-27} = 0b11101; - let Inst{26-25} = 0b01; - let Inst{24-21} = opcod; - let Inst{20} = 1; // The S bit. - } -} - /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need // the ".w" prefix to indicate that they are wide. multiclass T2I_bin_w_irs opcod, string opc, PatFrag opnode, bit Commutable = 0> : T2I_bin_irs; -/// T2I_bin_sw_irs - Same as T2I_bin_w_irs except these operations set -// the 'S' bit. -multiclass T2I_bin_sw_irs opcod, string opc, PatFrag opnode, - bit Commutable = 0> : - T2I_bin_cpsr_irs; - /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are /// reversed. The 'rr' form is only defined for the disassembler; for codegen /// it is equivalent to the T2I_bin_irs counterpart. @@ -1680,9 +1635,8 @@ defm t2BIC : T2I_bin_w_irs<0b0001, "bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>; -//let Defs = [CPSR] in -defm t2ANDS : T2I_bin_sw_irs<0b0000, "and", - BinOpFrag<(ARMand node:$LHS, node:$RHS)>, 1>; +defm t2ANDS : T2I_bin_s_irs<0b0000, "and", + BinOpFrag<(ARMand node:$LHS, node:$RHS)>, 1>; let Constraints = "$src = $dst" in def t2BFC : T2I<(outs rGPR:$dst), (ins rGPR:$src, bf_inv_mask_imm:$imm), From resistor at mac.com Mon Aug 30 17:07:52 2010 From: resistor at mac.com (Owen Anderson) Date: Mon, 30 Aug 2010 22:07:52 -0000 Subject: [llvm-commits] [llvm] r112539 - /llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Message-ID: <20100830220752.E4D952A6C12C@llvm.org> Author: resistor Date: Mon Aug 30 17:07:52 2010 New Revision: 112539 URL: http://llvm.org/viewvc/llvm-project?rev=112539&view=rev Log: Fixes and cleanups pointed out by Chris. In general, be careful to handle 0 results from ComputeValueKnownInPredecessors (indicating undef), and re-use existing constant folding APIs. Modified: llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Modified: llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp?rev=112539&r1=112538&r2=112539&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Mon Aug 30 17:07:52 2010 @@ -16,6 +16,7 @@ #include "llvm/IntrinsicInst.h" #include "llvm/LLVMContext.h" #include "llvm/Pass.h" +#include "llvm/Analysis/ConstantFolding.h" #include "llvm/Analysis/InstructionSimplify.h" #include "llvm/Analysis/LazyValueInfo.h" #include "llvm/Analysis/Loads.h" @@ -86,6 +87,7 @@ virtual void getAnalysisUsage(AnalysisUsage &AU) const { if (EnableLVI) AU.addRequired(); + AU.addPreserved(); } void FindLoopHeaders(Function &F); @@ -325,9 +327,10 @@ } else if (LVI) { Constant *CI = LVI->getConstantOnEdge(InVal, PN->getIncomingBlock(i), BB); - ConstantInt *CInt = dyn_cast_or_null(CI); - if (CInt) - Result.push_back(std::make_pair(CInt, PN->getIncomingBlock(i))); + // LVI returns null is no value could be determined. + if (!CI) continue; + ConstantInt *CInt = dyn_cast(CI); + Result.push_back(std::make_pair(CInt, PN->getIncomingBlock(i))); } } return !Result.empty(); @@ -373,10 +376,6 @@ } } return !Result.empty(); - - // Try to process a few other binary operator patterns. - } else if (isa(I)) { - } // Handle the NOT form of XOR. @@ -400,12 +399,14 @@ // AND or OR of a value with itself is that value. ConstantInt *CI = dyn_cast(BO->getOperand(1)); if (CI && (BO->getOpcode() == Instruction::And || - BO->getOpcode() == Instruction::Or)) { + BO->getOpcode() == Instruction::Or)) { SmallVector, 8> LHSVals; ComputeValueKnownInPredecessors(BO->getOperand(0), BB, LHSVals); - for (unsigned i = 0, e = LHSVals.size(); i != e; ++i) - if (LHSVals[i].first == CI) - Result.push_back(std::make_pair(CI, LHSVals[i].second)); + for (unsigned i = 0, e = LHSVals.size(); i != e; ++i) + if (LHSVals[i].first == 0) + Result.push_back(std::make_pair((ConstantInt*)0, LHSVals[i].second)); + else if (LHSVals[i].first == CI) + Result.push_back(std::make_pair(CI, LHSVals[i].second)); return !Result.empty(); } @@ -450,7 +451,7 @@ if (LVI && isa(Cmp->getOperand(1)) && Cmp->getType()->isIntegerTy()) { if (!isa(Cmp->getOperand(0)) || - cast(Cmp->getOperand(0))->getParent() != BB) { + cast(Cmp->getOperand(0))->getParent() != BB) { Constant *RHSCst = cast(Cmp->getOperand(1)); for (pred_iterator PI = pred_begin(BB), E = pred_end(BB);PI != E; ++PI){ @@ -472,17 +473,20 @@ // Try to find a constant value for the LHS of an equality comparison, // and evaluate it statically if we can. - if (Cmp->getPredicate() == CmpInst::ICMP_EQ || - Cmp->getPredicate() == CmpInst::ICMP_NE) { + if (Constant *CmpConst = dyn_cast(Cmp->getOperand(1))) { SmallVector, 8> LHSVals; ComputeValueKnownInPredecessors(I->getOperand(0), BB, LHSVals); ConstantInt *True = ConstantInt::getTrue(I->getContext()); ConstantInt *False = ConstantInt::getFalse(I->getContext()); - if (Cmp->getPredicate() == CmpInst::ICMP_NE) std::swap(True, False); for (unsigned i = 0, e = LHSVals.size(); i != e; ++i) { - if (LHSVals[i].first == Cmp->getOperand(1)) + if (LHSVals[i].first == 0) + Result.push_back(std::make_pair((ConstantInt*)0, + LHSVals[i].second)); + else if (ConstantFoldCompareInstOperands(Cmp->getPredicate(), + LHSVals[i].first, + CmpConst)) Result.push_back(std::make_pair(True, LHSVals[i].second)); else Result.push_back(std::make_pair(False, LHSVals[i].second)); From resistor at mac.com Mon Aug 30 17:09:05 2010 From: resistor at mac.com (Owen Anderson) Date: Mon, 30 Aug 2010 15:09:05 -0700 Subject: [llvm-commits] [llvm] r112198 - in /llvm/trunk: lib/Transforms/Scalar/JumpThreading.cpp test/Transforms/JumpThreading/2010-08-26-and.ll In-Reply-To: <73DA2794-393C-430C-AB2C-6092A2FEC3DE@apple.com> References: <20100826174024.58E092A6C12C@llvm.org> <73DA2794-393C-430C-AB2C-6092A2FEC3DE@apple.com> Message-ID: <230E263E-0B88-4A76-B416-BCC626ECE6B9@mac.com> Fixes are in r112539, except as commented below. Expanded testcases forthcoming. On Aug 30, 2010, at 2:15 PM, Chris Lattner wrote: >> + SmallVector, 8> LHSVals; >> + ComputeValueKnownInPredecessors(BO->getOperand(0), BB, LHSVals); >> + for (unsigned i = 0, e = LHSVals.size(); i != e; ++i) >> + if (LHSVals[i].first == CI) >> + Result.push_back(std::make_pair(CI, LHSVals[i].second)); > > Indentation. > > I don't follow this logic. Why do you care if the constant*'s are equal? All you should care about is that LHSVals[i].first is treated like undef if null, then constant fold the and/or. The ConstantFold* APIs can't handle this without instantiating a new instruction for each potential incoming value, and then trying to constant fold that. >> @@ -423,28 +448,63 @@ >> // If comparing a live-in value against a constant, see if we know the >> // live-in value on any predecessors. >> if (LVI && isa(Cmp->getOperand(1)) && >> + Cmp->getType()->isIntegerTy()) { >> + if (!isa(Cmp->getOperand(0)) || >> + cast(Cmp->getOperand(0))->getParent() != BB) { > > Indentation. Why would you want to accept non-instruction values here? It seems like the || should be an &&. Function arguments are the most obvious non-instruction value that the input might have correlated comparisons on. >> + if (LVI) { >> + // If all else fails, see if LVI can figure out a constant value for us. >> + Constant *CI = LVI->getConstant(V, BB); >> + ConstantInt *CInt = dyn_cast_or_null(CI); >> + if (CInt) { >> + for (pred_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI) >> + Result.push_back(std::make_pair(CInt, *PI)); >> + } >> + >> + return !Result.empty(); >> + } > > Is this actually adding value over the code at ~line 300? The code around line 300 is a special case for handling values not defined in the current block. The code is question is a last-ditch attempt to figure out (most likely through range propagation) the value of an instruction in the current block. While they implement the same concept, reusing the line 300 code (looping over the preds, and calling getConstantOnEdge) here would require JumpThreading to know how to join all those values based on the current instruction. Fortunately, LVI already knows how to do this! --Owen From clattner at apple.com Mon Aug 30 17:15:53 2010 From: clattner at apple.com (Chris Lattner) Date: Mon, 30 Aug 2010 15:15:53 -0700 Subject: [llvm-commits] [llvm] r112198 - in /llvm/trunk: lib/Transforms/Scalar/JumpThreading.cpp test/Transforms/JumpThreading/2010-08-26-and.ll In-Reply-To: <230E263E-0B88-4A76-B416-BCC626ECE6B9@mac.com> References: <20100826174024.58E092A6C12C@llvm.org> <73DA2794-393C-430C-AB2C-6092A2FEC3DE@apple.com> <230E263E-0B88-4A76-B416-BCC626ECE6B9@mac.com> Message-ID: On Aug 30, 2010, at 3:09 PM, Owen Anderson wrote: > Fixes are in r112539, except as commented below. Expanded testcases forthcoming. > > On Aug 30, 2010, at 2:15 PM, Chris Lattner wrote: >>> + SmallVector, 8> LHSVals; >>> + ComputeValueKnownInPredecessors(BO->getOperand(0), BB, LHSVals); >>> + for (unsigned i = 0, e = LHSVals.size(); i != e; ++i) >>> + if (LHSVals[i].first == CI) >>> + Result.push_back(std::make_pair(CI, LHSVals[i].second)); >> >> Indentation. >> >> I don't follow this logic. Why do you care if the constant*'s are equal? All you should care about is that LHSVals[i].first is treated like undef if null, then constant fold the and/or. > > The ConstantFold* APIs can't handle this without instantiating a new instruction for each potential incoming value, and then trying to constant fold that. ConstantExpr::get( ? >>> @@ -423,28 +448,63 @@ >>> // If comparing a live-in value against a constant, see if we know the >>> // live-in value on any predecessors. >>> if (LVI && isa(Cmp->getOperand(1)) && >>> + Cmp->getType()->isIntegerTy()) { >>> + if (!isa(Cmp->getOperand(0)) || >>> + cast(Cmp->getOperand(0))->getParent() != BB) { >> >> Indentation. Why would you want to accept non-instruction values here? It seems like the || should be an &&. > > Function arguments are the most obvious non-instruction value that the input might have correlated comparisons on. Ah, makes sense! >>> + if (LVI) { >>> + // If all else fails, see if LVI can figure out a constant value for us. >>> + Constant *CI = LVI->getConstant(V, BB); >>> + ConstantInt *CInt = dyn_cast_or_null(CI); >>> + if (CInt) { >>> + for (pred_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI) >>> + Result.push_back(std::make_pair(CInt, *PI)); >>> + } >>> + >>> + return !Result.empty(); >>> + } >> >> Is this actually adding value over the code at ~line 300? > > The code around line 300 is a special case for handling values not defined in the current block. The code is question is a last-ditch attempt to figure out (most likely through range propagation) the value of an instruction in the current block. > > While they implement the same concept, reusing the line 300 code (looping over the preds, and calling getConstantOnEdge) here would require JumpThreading to know how to join all those values based on the current instruction. Fortunately, LVI already knows how to do this! Do you have examples of this? Again, please add testcases. -Chris From clattner at apple.com Mon Aug 30 17:22:11 2010 From: clattner at apple.com (Chris Lattner) Date: Mon, 30 Aug 2010 15:22:11 -0700 Subject: [llvm-commits] [llvm] r112539 - /llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp In-Reply-To: <20100830220752.E4D952A6C12C@llvm.org> References: <20100830220752.E4D952A6C12C@llvm.org> Message-ID: On Aug 30, 2010, at 3:07 PM, Owen Anderson wrote: > URL: http://llvm.org/viewvc/llvm-project?rev=112539&view=rev > Log: > Fixes and cleanups pointed out by Chris. In general, be careful to handle 0 results from ComputeValueKnownInPredecessors > (indicating undef), and re-use existing constant folding APIs. Thanks, > @@ -86,6 +87,7 @@ > virtual void getAnalysisUsage(AnalysisUsage &AU) const { > if (EnableLVI) > AU.addRequired(); > + AU.addPreserved(); > } Does this preserve LVI if LVI is not enabled? What does "preserving LVI" actually mean? > @@ -400,12 +399,14 @@ > // AND or OR of a value with itself is that value. > ConstantInt *CI = dyn_cast(BO->getOperand(1)); > if (CI && (BO->getOpcode() == Instruction::And || > + BO->getOpcode() == Instruction::Or)) { > SmallVector, 8> LHSVals; > ComputeValueKnownInPredecessors(BO->getOperand(0), BB, LHSVals); > + for (unsigned i = 0, e = LHSVals.size(); i != e; ++i) > + if (LHSVals[i].first == 0) > + Result.push_back(std::make_pair((ConstantInt*)0, LHSVals[i].second)); > + else if (LHSVals[i].first == CI) > + Result.push_back(std::make_pair(CI, LHSVals[i].second)); This isn't safe: undef & 0 = 0, not undef. Also, why use == here? Just use ConstantExpr::get. > @@ -472,17 +473,20 @@ > > // Try to find a constant value for the LHS of an equality comparison, > // and evaluate it statically if we can. > + if (Constant *CmpConst = dyn_cast(Cmp->getOperand(1))) { > SmallVector, 8> LHSVals; > ComputeValueKnownInPredecessors(I->getOperand(0), BB, LHSVals); > > ConstantInt *True = ConstantInt::getTrue(I->getContext()); > ConstantInt *False = ConstantInt::getFalse(I->getContext()); > > for (unsigned i = 0, e = LHSVals.size(); i != e; ++i) { > - if (LHSVals[i].first == Cmp->getOperand(1)) > + if (LHSVals[i].first == 0) > + Result.push_back(std::make_pair((ConstantInt*)0, > + LHSVals[i].second)); > + else if (ConstantFoldCompareInstOperands(Cmp->getPredicate(), > + LHSVals[i].first, > + CmpConst)) > Result.push_back(std::make_pair(True, LHSVals[i].second)); > else > Result.push_back(std::make_pair(False, LHSVals[i].second)); ConstantFoldCompareInstOperands is overkill, just use ConstantExpr::get. This also eliminates the need for "True", "False" and fix the miscompilation you just introduced. (ConstantFoldCompareInstOperands doesn't return bool). -Chris From resistor at mac.com Mon Aug 30 17:23:55 2010 From: resistor at mac.com (Owen Anderson) Date: Mon, 30 Aug 2010 15:23:55 -0700 Subject: [llvm-commits] [llvm] r112539 - /llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp In-Reply-To: References: <20100830220752.E4D952A6C12C@llvm.org> Message-ID: <65D5E23F-6052-472A-8FCB-C4F8FD8476AB@mac.com> On Aug 30, 2010, at 3:22 PM, Chris Lattner wrote: > Does this preserve LVI if LVI is not enabled? What does "preserving LVI" actually mean? Oops, that was actually part of another patch I was working on, where I want to avoid destructing LVI between running JumpThreading and running ValuePropagation. --Owen From resistor at mac.com Mon Aug 30 17:33:42 2010 From: resistor at mac.com (Owen Anderson) Date: Mon, 30 Aug 2010 22:33:42 -0000 Subject: [llvm-commits] [llvm] r112543 - /llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Message-ID: <20100830223342.2B8F62A6C12C@llvm.org> Author: resistor Date: Mon Aug 30 17:33:41 2010 New Revision: 112543 URL: http://llvm.org/viewvc/llvm-project?rev=112543&view=rev Log: Revert r112539. It accidentally introduced a miscompilation. Modified: llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Modified: llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp?rev=112543&r1=112542&r2=112543&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Mon Aug 30 17:33:41 2010 @@ -16,7 +16,6 @@ #include "llvm/IntrinsicInst.h" #include "llvm/LLVMContext.h" #include "llvm/Pass.h" -#include "llvm/Analysis/ConstantFolding.h" #include "llvm/Analysis/InstructionSimplify.h" #include "llvm/Analysis/LazyValueInfo.h" #include "llvm/Analysis/Loads.h" @@ -87,7 +86,6 @@ virtual void getAnalysisUsage(AnalysisUsage &AU) const { if (EnableLVI) AU.addRequired(); - AU.addPreserved(); } void FindLoopHeaders(Function &F); @@ -327,10 +325,9 @@ } else if (LVI) { Constant *CI = LVI->getConstantOnEdge(InVal, PN->getIncomingBlock(i), BB); - // LVI returns null is no value could be determined. - if (!CI) continue; - ConstantInt *CInt = dyn_cast(CI); - Result.push_back(std::make_pair(CInt, PN->getIncomingBlock(i))); + ConstantInt *CInt = dyn_cast_or_null(CI); + if (CInt) + Result.push_back(std::make_pair(CInt, PN->getIncomingBlock(i))); } } return !Result.empty(); @@ -376,6 +373,10 @@ } } return !Result.empty(); + + // Try to process a few other binary operator patterns. + } else if (isa(I)) { + } // Handle the NOT form of XOR. @@ -399,14 +400,12 @@ // AND or OR of a value with itself is that value. ConstantInt *CI = dyn_cast(BO->getOperand(1)); if (CI && (BO->getOpcode() == Instruction::And || - BO->getOpcode() == Instruction::Or)) { + BO->getOpcode() == Instruction::Or)) { SmallVector, 8> LHSVals; ComputeValueKnownInPredecessors(BO->getOperand(0), BB, LHSVals); - for (unsigned i = 0, e = LHSVals.size(); i != e; ++i) - if (LHSVals[i].first == 0) - Result.push_back(std::make_pair((ConstantInt*)0, LHSVals[i].second)); - else if (LHSVals[i].first == CI) - Result.push_back(std::make_pair(CI, LHSVals[i].second)); + for (unsigned i = 0, e = LHSVals.size(); i != e; ++i) + if (LHSVals[i].first == CI) + Result.push_back(std::make_pair(CI, LHSVals[i].second)); return !Result.empty(); } @@ -451,7 +450,7 @@ if (LVI && isa(Cmp->getOperand(1)) && Cmp->getType()->isIntegerTy()) { if (!isa(Cmp->getOperand(0)) || - cast(Cmp->getOperand(0))->getParent() != BB) { + cast(Cmp->getOperand(0))->getParent() != BB) { Constant *RHSCst = cast(Cmp->getOperand(1)); for (pred_iterator PI = pred_begin(BB), E = pred_end(BB);PI != E; ++PI){ @@ -473,20 +472,17 @@ // Try to find a constant value for the LHS of an equality comparison, // and evaluate it statically if we can. - if (Constant *CmpConst = dyn_cast(Cmp->getOperand(1))) { + if (Cmp->getPredicate() == CmpInst::ICMP_EQ || + Cmp->getPredicate() == CmpInst::ICMP_NE) { SmallVector, 8> LHSVals; ComputeValueKnownInPredecessors(I->getOperand(0), BB, LHSVals); ConstantInt *True = ConstantInt::getTrue(I->getContext()); ConstantInt *False = ConstantInt::getFalse(I->getContext()); + if (Cmp->getPredicate() == CmpInst::ICMP_NE) std::swap(True, False); for (unsigned i = 0, e = LHSVals.size(); i != e; ++i) { - if (LHSVals[i].first == 0) - Result.push_back(std::make_pair((ConstantInt*)0, - LHSVals[i].second)); - else if (ConstantFoldCompareInstOperands(Cmp->getPredicate(), - LHSVals[i].first, - CmpConst)) + if (LHSVals[i].first == Cmp->getOperand(1)) Result.push_back(std::make_pair(True, LHSVals[i].second)); else Result.push_back(std::make_pair(False, LHSVals[i].second)); From asl at math.spbu.ru Mon Aug 30 17:37:44 2010 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Mon, 30 Aug 2010 22:37:44 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r112544 - in /llvm-gcc-4.2/trunk: Makefile.def Makefile.in Message-ID: <20100830223744.955022A6C12C@llvm.org> Author: asl Date: Mon Aug 30 17:37:44 2010 New Revision: 112544 URL: http://llvm.org/viewvc/llvm-project?rev=112544&view=rev Log: Fix broken newlib build dependencies (otherwise parallel build will apparently fail). Patch backported from mainline, where is was committed under GPLv2. Patch suggested by Sandeep Patel! Modified: llvm-gcc-4.2/trunk/Makefile.def llvm-gcc-4.2/trunk/Makefile.in Modified: llvm-gcc-4.2/trunk/Makefile.def URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/Makefile.def?rev=112544&r1=112543&r2=112544&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/Makefile.def (original) +++ llvm-gcc-4.2/trunk/Makefile.def Mon Aug 30 17:37:44 2010 @@ -481,7 +481,8 @@ lang_env_dependencies = { module=winsup; }; lang_env_dependencies = { module=qthreads; }; -dependencies = { module=all-target-libgloss; on=configure-target-newlib; }; +// LLVM LOCAL mainline +dependencies = { module=all-target-libgloss; on=all-target-newlib; }; dependencies = { module=all-target-winsup; on=all-target-libiberty; }; dependencies = { module=all-target-winsup; on=all-target-libtermcap; }; Modified: llvm-gcc-4.2/trunk/Makefile.in URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/Makefile.in?rev=112544&r1=112543&r2=112544&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/Makefile.in (original) +++ llvm-gcc-4.2/trunk/Makefile.in Mon Aug 30 17:37:44 2010 @@ -43792,7 +43792,8 @@ all-target-libstdc++-v3: maybe-all-target-libiberty install-target-libssp: maybe-install-gcc install-target-libgomp: maybe-install-gcc -all-target-libgloss: maybe-configure-target-newlib +# LLVM LOCAL mainline +all-target-libgloss: maybe-all-target-newlib all-target-winsup: maybe-all-target-libiberty all-target-winsup: maybe-all-target-libtermcap From resistor at mac.com Mon Aug 30 17:45:55 2010 From: resistor at mac.com (Owen Anderson) Date: Mon, 30 Aug 2010 22:45:55 -0000 Subject: [llvm-commits] [llvm] r112545 - /llvm/trunk/lib/Transforms/Scalar/ValuePropagation.cpp Message-ID: <20100830224555.4A6542A6C12C@llvm.org> Author: resistor Date: Mon Aug 30 17:45:55 2010 New Revision: 112545 URL: http://llvm.org/viewvc/llvm-project?rev=112545&view=rev Log: Add statistics to evaluate this pass. Modified: llvm/trunk/lib/Transforms/Scalar/ValuePropagation.cpp Modified: llvm/trunk/lib/Transforms/Scalar/ValuePropagation.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ValuePropagation.cpp?rev=112545&r1=112544&r2=112545&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ValuePropagation.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ValuePropagation.cpp Mon Aug 30 17:45:55 2010 @@ -18,8 +18,12 @@ #include "llvm/Pass.h" #include "llvm/Analysis/LazyValueInfo.h" #include "llvm/Transforms/Utils/Local.h" +#include "llvm/ADT/Statistic.h" using namespace llvm; +STATISTIC(NumPhis, "Number of phis propagated"); +STATISTIC(NumSelects, "Number of selects propagated"); + namespace { class ValuePropagation : public FunctionPass { LazyValueInfo *LVI; @@ -65,6 +69,8 @@ assert(0 && "Select on constant is neither 0 nor 1?"); } + ++NumSelects; + return true; } @@ -88,6 +94,8 @@ changed = true; } + ++NumPhis; + return changed; } From clattner at apple.com Mon Aug 30 17:46:35 2010 From: clattner at apple.com (Chris Lattner) Date: Mon, 30 Aug 2010 15:46:35 -0700 Subject: [llvm-commits] [llvm] r112325 - in /llvm/trunk: include/llvm/LinkAllPasses.h include/llvm/Transforms/Scalar.h lib/Transforms/Scalar/ValuePropagation.cpp test/Transforms/ValuePropagation/ test/Transforms/ValuePropagation/dg.exp test/Transforms/ValuePropagation/phi.ll test/Transforms/ValuePropagation/select.ll In-Reply-To: <20100827233136.5F7A72A6C12C@llvm.org> References: <20100827233136.5F7A72A6C12C@llvm.org> Message-ID: On Aug 27, 2010, at 4:31 PM, Owen Anderson wrote: > URL: http://llvm.org/viewvc/llvm-project?rev=112325&view=rev > Log: > Add a prototype of a new peephole optimizing pass that uses LazyValue info to simplify PHIs and select's. > This pass addresses the missed optimizations from PR2581 and PR4420. nifty, > +++ llvm/trunk/lib/Transforms/Scalar/ValuePropagation.cpp Fri Aug 27 18:31:36 2010 > @@ -0,0 +1,113 @@ > +//===- ValuePropagation.cpp - Propagate information derived control flow --===// > +// > +// The LLVM Compiler Infrastructure > +// > +// This file is distributed under the University of Illinois Open Source > +// License. See LICENSE.TXT for details. > +// > +//===----------------------------------------------------------------------===// > +// > +// This file implements the Value Propagation pass. The name of this pass is very generic. Can you think of something better? It's not really propagating values afterall. > +bool ValuePropagation::processSelect(SelectInst *S) { > + Constant *C = LVI->getConstant(S->getOperand(0), S->getParent()); > + if (!C) return false; Does LVI work on vectors? If not, you should check that the operand of the select is an integer. > + if (CI->isZero()) { > + S->replaceAllUsesWith(S->getOperand(2)); > + S->eraseFromParent(); > + } else if (CI->isOne()) { > + S->replaceAllUsesWith(S->getOperand(1)); > + S->eraseFromParent(); > + } else { > + assert(0 && "Select on constant is neither 0 nor 1?"); > + } Instead of three-way, this should be two way: > + if (CI->isZero()) { > + S->replaceAllUsesWith(S->getOperand(2)); > + S->eraseFromParent(); > + } else { > + assert(CI->isOne() && "Select on constant isn't a bool?");); > + S->replaceAllUsesWith(S->getOperand(1)); > + S->eraseFromParent(); > + } Better yet, use: S->replaceAllUsesWith(S->getOperand(CI->isOne() ? 1 : 2)); S->eraseFromParent(); Redundancy is bad. > +bool ValuePropagation::processPHI(PHINode *P) { > + bool changed = false; Please capitalize Changed. > + > + BasicBlock *BB = P->getParent(); > + for (unsigned i = 0; i < P->getNumIncomingValues(); ++i) { Don't evaluate P->getNumIncomingValues() every iteration. > + Constant *C = LVI->getConstantOnEdge(P->getIncomingValue(i), > + P->getIncomingBlock(i), > + BB); > + if (!C || C == P->getIncomingValue(i)) continue; This shouldn't even do the query if the incoming value is already a constant. > + > + P->setIncomingValue(i, C); > + changed = true; > + } > + > + if (Value *ConstVal = P->hasConstantValue()) { > + P->replaceAllUsesWith(ConstVal); > + P->eraseFromParent(); > + changed = true; > + } > + > + return changed; > +} > + > +bool ValuePropagation::runOnFunction(Function &F) { > + LVI = &getAnalysis(); > + > + bool changed = false; > + > + for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI) > + for (BasicBlock::iterator BI = FI->begin(), BE = FI->end(); BI != BE; ) { > + Instruction *II = BI++; > + if (SelectInst *SI = dyn_cast(II)) > + changed |= processSelect(SI); > + else if (PHINode *P = dyn_cast(II)) > + changed |= processPHI(P); > + } > + > + if (changed) > + for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI) > + SimplifyInstructionsInBlock(FI); This loop is very odd... what does it do and why? Why does it belong here? > > +; CHECK: ret i32 10 > + ret i32 10 > +} > \ No newline at end of file Please beware that your editor is not adding newlines at the end of files and try to fix it. -Chris > > Added: llvm/trunk/test/Transforms/ValuePropagation/select.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ValuePropagation/select.ll?rev=112325&view=auto > ============================================================================== > --- llvm/trunk/test/Transforms/ValuePropagation/select.ll (added) > +++ llvm/trunk/test/Transforms/ValuePropagation/select.ll Fri Aug 27 18:31:36 2010 Why make each of these their own file? This should go into a basic.ll which tests basic functionality of the pass. -Chris > @@ -0,0 +1,25 @@ > +; RUN: opt < %s -value-propagation -S | FileCheck %s > +; PR4420 > + > +declare i1 @ext() > +; CHECK: @foo > +define i1 @foo() { > +entry: > + %cond = tail call i1 @ext() ; [#uses=2] > + br i1 %cond, label %bb1, label %bb2 > + > +bb1: ; preds = %entry > + %cond2 = tail call i1 @ext() ; [#uses=1] > + br i1 %cond2, label %bb3, label %bb2 > + > +bb2: ; preds = %bb1, %entry > +; CHECK-NOT: phi i1 > + %cond_merge = phi i1 [ %cond, %entry ], [ false, %bb1 ] ; [#uses=1] > +; CHECK: ret i1 false > + ret i1 %cond_merge > + > +bb3: ; preds = %bb1 > + %res = tail call i1 @ext() ; [#uses=1] > +; CHECK: ret i1 %res > + ret i1 %res > +} > \ No newline at end of file > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From clattner at apple.com Mon Aug 30 17:50:11 2010 From: clattner at apple.com (Chris Lattner) Date: Mon, 30 Aug 2010 15:50:11 -0700 Subject: [llvm-commits] PATCH: add ContextualDenseMap In-Reply-To: References: <4C7686B5.7060605@mxc.ca> Message-ID: <6644A46A-EC23-447F-9D4C-A800FCF6540F@apple.com> On Aug 30, 2010, at 2:52 PM, Nick Lewycky wrote: > On 30 August 2010 14:03, Chris Lattner wrote: > > On Aug 26, 2010, at 8:22 AM, Nick Lewycky wrote: > > > This patch adds a new ContextualDenseMap and sinks most of the dense map logic into DenseMapImpl. A ContextualDenseMap takes a ContextualDenseMapInfo pointer instead of just a typename. I need this for mergefuncs where I want a comparison operation that involves target data. > > > > The four map info functions (getTombstoneKey, getEmptyKey, getHashValue and isEqual) are made virtual in DenseMapImpl and then implemented once in DenseMap and again in ContextualDenseMap. This implementation is modelled after the relationship between ContextualFoldingSet and FoldingSet. > > This seems like it will slow down densemap, perhaps substantially, by introducing virtual methods. > > That matches my reaction when looking at FoldingSet but I decided that someone else probably knows more than I do. I'll change this, and probably FoldingSet too. DenseMap and FoldingSet are used by very different clients. The cost of the virtual method in FoldingSet is far less of an issue because the cost of populating Profile info is much higher than the cost of computing a hash value. > It's also not clear to me what this is actually doing. Please explain what you are trying to do and why the current densemap can't do it. > > My implementation of isEqual for MergeFunctions requires a TargetData object. Because the existing DenseMap takes a type and not an object, and the DenseMapInfo methods are all static, I can't give it a TargetData* to use unless I'm willing to stick it in a global variable. (And if you prefer that, let me know; I'd ruled it out.) Why not make the value in the hash table a struct that contains a Function* and a TargetData* (and a cached hash value)? -Chris -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100830/dd369d15/attachment.html From asl at math.spbu.ru Mon Aug 30 17:50:36 2010 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Mon, 30 Aug 2010 22:50:36 -0000 Subject: [llvm-commits] [llvm] r112546 - /llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Message-ID: <20100830225036.DEECE2A6C12C@llvm.org> Author: asl Date: Mon Aug 30 17:50:36 2010 New Revision: 112546 URL: http://llvm.org/viewvc/llvm-project?rev=112546&view=rev Log: Expand MOVi32imm in ARM mode after regalloc. This provides scheduling opportunities (extra instruction can go in between MOVT / MOVW pair removing the stall). Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=112546&r1=112545&r2=112546&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Mon Aug 30 17:50:36 2010 @@ -167,6 +167,7 @@ break; } + case ARM::MOVi32imm: case ARM::t2MOVi32imm: { unsigned PredReg = 0; ARMCC::CondCodes Pred = llvm::getInstrPredicate(&MI, PredReg); @@ -175,9 +176,13 @@ const MachineOperand &MO = MI.getOperand(1); MachineInstrBuilder LO16, HI16; - LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::t2MOVi16), + LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), + TII->get(Opcode == ARM::MOVi32imm ? + ARM::MOVi16 : ARM::t2MOVi16), DstReg); - HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::t2MOVTi16)) + HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), + TII->get(Opcode == ARM::MOVi32imm ? + ARM::MOVTi16 : ARM::t2MOVTi16)) .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead)) .addReg(DstReg); From resistor at mac.com Mon Aug 30 18:22:36 2010 From: resistor at mac.com (Owen Anderson) Date: Mon, 30 Aug 2010 23:22:36 -0000 Subject: [llvm-commits] [llvm] r112550 - /llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Message-ID: <20100830232236.310EE2A6C12F@llvm.org> Author: resistor Date: Mon Aug 30 18:22:36 2010 New Revision: 112550 URL: http://llvm.org/viewvc/llvm-project?rev=112550&view=rev Log: Re-apply r112539, being more careful to respect the return values of the constant folding methods. Additionally, use the ConstantExpr::get*() methods to simplify some constant folding. Modified: llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Modified: llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp?rev=112550&r1=112549&r2=112550&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Mon Aug 30 18:22:36 2010 @@ -16,6 +16,7 @@ #include "llvm/IntrinsicInst.h" #include "llvm/LLVMContext.h" #include "llvm/Pass.h" +#include "llvm/Analysis/ConstantFolding.h" #include "llvm/Analysis/InstructionSimplify.h" #include "llvm/Analysis/LazyValueInfo.h" #include "llvm/Analysis/Loads.h" @@ -325,9 +326,10 @@ } else if (LVI) { Constant *CI = LVI->getConstantOnEdge(InVal, PN->getIncomingBlock(i), BB); - ConstantInt *CInt = dyn_cast_or_null(CI); - if (CInt) - Result.push_back(std::make_pair(CInt, PN->getIncomingBlock(i))); + // LVI returns null is no value could be determined. + if (!CI) continue; + ConstantInt *CInt = dyn_cast(CI); + Result.push_back(std::make_pair(CInt, PN->getIncomingBlock(i))); } } return !Result.empty(); @@ -373,10 +375,6 @@ } } return !Result.empty(); - - // Try to process a few other binary operator patterns. - } else if (isa(I)) { - } // Handle the NOT form of XOR. @@ -400,12 +398,19 @@ // AND or OR of a value with itself is that value. ConstantInt *CI = dyn_cast(BO->getOperand(1)); if (CI && (BO->getOpcode() == Instruction::And || - BO->getOpcode() == Instruction::Or)) { + BO->getOpcode() == Instruction::Or)) { SmallVector, 8> LHSVals; ComputeValueKnownInPredecessors(BO->getOperand(0), BB, LHSVals); - for (unsigned i = 0, e = LHSVals.size(); i != e; ++i) - if (LHSVals[i].first == CI) - Result.push_back(std::make_pair(CI, LHSVals[i].second)); + for (unsigned i = 0, e = LHSVals.size(); i != e; ++i) + if (LHSVals[i].first == 0) { + ConstantInt *Zero = + cast(ConstantInt::get(BO->getType(), 0)); + Result.push_back(std::make_pair(Zero, LHSVals[i].second)); + } else if (Constant *Folded = ConstantExpr::get(BO->getOpcode(), + LHSVals[i].first, CI)) { + Result.push_back(std::make_pair(cast(Folded), + LHSVals[i].second)); + } return !Result.empty(); } @@ -450,7 +455,7 @@ if (LVI && isa(Cmp->getOperand(1)) && Cmp->getType()->isIntegerTy()) { if (!isa(Cmp->getOperand(0)) || - cast(Cmp->getOperand(0))->getParent() != BB) { + cast(Cmp->getOperand(0))->getParent() != BB) { Constant *RHSCst = cast(Cmp->getOperand(1)); for (pred_iterator PI = pred_begin(BB), E = pred_end(BB);PI != E; ++PI){ @@ -472,20 +477,18 @@ // Try to find a constant value for the LHS of an equality comparison, // and evaluate it statically if we can. - if (Cmp->getPredicate() == CmpInst::ICMP_EQ || - Cmp->getPredicate() == CmpInst::ICMP_NE) { + if (Constant *CmpConst = dyn_cast(Cmp->getOperand(1))) { SmallVector, 8> LHSVals; ComputeValueKnownInPredecessors(I->getOperand(0), BB, LHSVals); - ConstantInt *True = ConstantInt::getTrue(I->getContext()); - ConstantInt *False = ConstantInt::getFalse(I->getContext()); - if (Cmp->getPredicate() == CmpInst::ICMP_NE) std::swap(True, False); - for (unsigned i = 0, e = LHSVals.size(); i != e; ++i) { - if (LHSVals[i].first == Cmp->getOperand(1)) - Result.push_back(std::make_pair(True, LHSVals[i].second)); - else - Result.push_back(std::make_pair(False, LHSVals[i].second)); + if (LHSVals[i].first == 0) + Result.push_back(std::make_pair((ConstantInt*)0, + LHSVals[i].second)); + else if (Constant *Folded = ConstantExpr::getCompare( + Cmp->getPredicate(), LHSVals[i].first, CmpConst)) + Result.push_back(std::make_pair(cast(Folded), + LHSVals[i].second)); } return !Result.empty(); From resistor at mac.com Mon Aug 30 18:34:08 2010 From: resistor at mac.com (Owen Anderson) Date: Mon, 30 Aug 2010 16:34:08 -0700 Subject: [llvm-commits] [llvm] r112325 - in /llvm/trunk: include/llvm/LinkAllPasses.h include/llvm/Transforms/Scalar.h lib/Transforms/Scalar/ValuePropagation.cpp test/Transforms/ValuePropagation/ test/Transforms/ValuePropagation/dg.exp test/Transforms/ValuePropagation/phi.ll test/Transforms/ValuePropagation/select.ll In-Reply-To: References: <20100827233136.5F7A72A6C12C@llvm.org> Message-ID: <97AFEA28-0E1F-48C6-A8F1-222AAD4DA53E@mac.com> On Aug 30, 2010, at 3:46 PM, Chris Lattner wrote: >> +++ llvm/trunk/lib/Transforms/Scalar/ValuePropagation.cpp Fri Aug 27 18:31:36 2010 >> @@ -0,0 +1,113 @@ >> +//===- ValuePropagation.cpp - Propagate information derived control flow --===// >> +// >> +// The LLVM Compiler Infrastructure >> +// >> +// This file is distributed under the University of Illinois Open Source >> +// License. See LICENSE.TXT for details. >> +// >> +//===----------------------------------------------------------------------===// >> +// >> +// This file implements the Value Propagation pass. > > The name of this pass is very generic. Can you think of something better? It's not really propagating values afterall. I don't really have a better idea for it. I'm open to suggestions. >> + >> + if (changed) >> + for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI) >> + SimplifyInstructionsInBlock(FI); > > This loop is very odd... what does it do and why? Why does it belong here? The actual value propagation will tend to leave a lot of unused values and/or newly-constant PHI nodes sitting around. These can't be removed/simplified during the main loop without invalidating the BasicBlock::iterator. If ValuePropagation is run early enough, this probably isn't necessary as later runs of instcombine should clean up after it. However, if we want to run it reasonably late, we probably want it to clean up after itself. --Owen From resistor at mac.com Mon Aug 30 18:34:17 2010 From: resistor at mac.com (Owen Anderson) Date: Mon, 30 Aug 2010 23:34:17 -0000 Subject: [llvm-commits] [llvm] r112553 - /llvm/trunk/lib/Transforms/Scalar/ValuePropagation.cpp Message-ID: <20100830233417.BD2212A6C130@llvm.org> Author: resistor Date: Mon Aug 30 18:34:17 2010 New Revision: 112553 URL: http://llvm.org/viewvc/llvm-project?rev=112553&view=rev Log: Cleanups suggested by Chris. Modified: llvm/trunk/lib/Transforms/Scalar/ValuePropagation.cpp Modified: llvm/trunk/lib/Transforms/Scalar/ValuePropagation.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ValuePropagation.cpp?rev=112553&r1=112552&r2=112553&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ValuePropagation.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ValuePropagation.cpp Mon Aug 30 18:34:17 2010 @@ -53,67 +53,65 @@ } bool ValuePropagation::processSelect(SelectInst *S) { + if (S->getType()->isVectorTy()) return false; + Constant *C = LVI->getConstant(S->getOperand(0), S->getParent()); if (!C) return false; ConstantInt *CI = dyn_cast(C); if (!CI) return false; - if (CI->isZero()) { - S->replaceAllUsesWith(S->getOperand(2)); - S->eraseFromParent(); - } else if (CI->isOne()) { - S->replaceAllUsesWith(S->getOperand(1)); - S->eraseFromParent(); - } else { - assert(0 && "Select on constant is neither 0 nor 1?"); - } - + S->replaceAllUsesWith(S->getOperand(CI->isOne() ? 1 : 2)); + S->eraseFromParent(); + ++NumSelects; return true; } bool ValuePropagation::processPHI(PHINode *P) { - bool changed = false; + bool Changed = false; BasicBlock *BB = P->getParent(); - for (unsigned i = 0; i < P->getNumIncomingValues(); ++i) { + for (unsigned i = 0, e = P->getNumIncomingValues(); i < e; ++i) { + Value *Incoming = P->getIncomingValue(i); + if (isa(Incoming)) continue; + Constant *C = LVI->getConstantOnEdge(P->getIncomingValue(i), P->getIncomingBlock(i), BB); - if (!C || C == P->getIncomingValue(i)) continue; + if (!C) continue; P->setIncomingValue(i, C); - changed = true; + Changed = true; } if (Value *ConstVal = P->hasConstantValue()) { P->replaceAllUsesWith(ConstVal); P->eraseFromParent(); - changed = true; + Changed = true; } ++NumPhis; - return changed; + return Changed; } bool ValuePropagation::runOnFunction(Function &F) { LVI = &getAnalysis(); - bool changed = false; + bool Changed = false; for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI) for (BasicBlock::iterator BI = FI->begin(), BE = FI->end(); BI != BE; ) { Instruction *II = BI++; if (SelectInst *SI = dyn_cast(II)) - changed |= processSelect(SI); + Changed |= processSelect(SI); else if (PHINode *P = dyn_cast(II)) - changed |= processPHI(P); + Changed |= processPHI(P); } - if (changed) + if (Changed) for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI) SimplifyInstructionsInBlock(FI); From resistor at mac.com Mon Aug 30 18:37:42 2010 From: resistor at mac.com (Owen Anderson) Date: Mon, 30 Aug 2010 23:37:42 -0000 Subject: [llvm-commits] [llvm] r112554 - in /llvm/trunk/test/Transforms/ValuePropagation: basic.ll phi.ll select.ll Message-ID: <20100830233742.2DCE02A6C132@llvm.org> Author: resistor Date: Mon Aug 30 18:37:41 2010 New Revision: 112554 URL: http://llvm.org/viewvc/llvm-project?rev=112554&view=rev Log: Combine these two tests, and make sure there's a newline at the end of the file. Added: llvm/trunk/test/Transforms/ValuePropagation/basic.ll Removed: llvm/trunk/test/Transforms/ValuePropagation/phi.ll llvm/trunk/test/Transforms/ValuePropagation/select.ll Added: llvm/trunk/test/Transforms/ValuePropagation/basic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ValuePropagation/basic.ll?rev=112554&view=auto ============================================================================== --- llvm/trunk/test/Transforms/ValuePropagation/basic.ll (added) +++ llvm/trunk/test/Transforms/ValuePropagation/basic.ll Mon Aug 30 18:37:41 2010 @@ -0,0 +1,40 @@ +; RUN: opt < %s -value-propagation -S | FileCheck %s +; PR2581 + +; CHECK: @test1 +define i32 @test1(i1 %C) nounwind { + br i1 %C, label %exit, label %body + +body: ; preds = %0 +; CHECK-NOT: select + %A = select i1 %C, i32 10, i32 11 ; [#uses=1] +; CHECK: ret i32 11 + ret i32 %A + +exit: ; preds = %0 +; CHECK: ret i32 10 + ret i32 10 +} + +declare i1 @ext() +; CHECK: @test2 +define i1 @test2() { +entry: + %cond = tail call i1 @ext() ; [#uses=2] + br i1 %cond, label %bb1, label %bb2 + +bb1: ; preds = %entry + %cond2 = tail call i1 @ext() ; [#uses=1] + br i1 %cond2, label %bb3, label %bb2 + +bb2: ; preds = %bb1, %entry +; CHECK-NOT: phi i1 + %cond_merge = phi i1 [ %cond, %entry ], [ false, %bb1 ] ; [#uses=1] +; CHECK: ret i1 false + ret i1 %cond_merge + +bb3: ; preds = %bb1 + %res = tail call i1 @ext() ; [#uses=1] +; CHECK: ret i1 %res + ret i1 %res +} Removed: llvm/trunk/test/Transforms/ValuePropagation/phi.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ValuePropagation/phi.ll?rev=112553&view=auto ============================================================================== --- llvm/trunk/test/Transforms/ValuePropagation/phi.ll (original) +++ llvm/trunk/test/Transforms/ValuePropagation/phi.ll (removed) @@ -1,17 +0,0 @@ -; RUN: opt < %s -value-propagation -S | FileCheck %s -; PR2581 - -; CHECK: @run -define i32 @run(i1 %C) nounwind { - br i1 %C, label %exit, label %body - -body: ; preds = %0 -; CHECK-NOT: select - %A = select i1 %C, i32 10, i32 11 ; [#uses=1] -; CHECK: ret i32 11 - ret i32 %A - -exit: ; preds = %0 -; CHECK: ret i32 10 - ret i32 10 -} \ No newline at end of file Removed: llvm/trunk/test/Transforms/ValuePropagation/select.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ValuePropagation/select.ll?rev=112553&view=auto ============================================================================== --- llvm/trunk/test/Transforms/ValuePropagation/select.ll (original) +++ llvm/trunk/test/Transforms/ValuePropagation/select.ll (removed) @@ -1,25 +0,0 @@ -; RUN: opt < %s -value-propagation -S | FileCheck %s -; PR4420 - -declare i1 @ext() -; CHECK: @foo -define i1 @foo() { -entry: - %cond = tail call i1 @ext() ; [#uses=2] - br i1 %cond, label %bb1, label %bb2 - -bb1: ; preds = %entry - %cond2 = tail call i1 @ext() ; [#uses=1] - br i1 %cond2, label %bb3, label %bb2 - -bb2: ; preds = %bb1, %entry -; CHECK-NOT: phi i1 - %cond_merge = phi i1 [ %cond, %entry ], [ false, %bb1 ] ; [#uses=1] -; CHECK: ret i1 false - ret i1 %cond_merge - -bb3: ; preds = %bb1 - %res = tail call i1 @ext() ; [#uses=1] -; CHECK: ret i1 %res - ret i1 %res -} \ No newline at end of file From asl at math.spbu.ru Mon Aug 30 18:41:49 2010 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Mon, 30 Aug 2010 23:41:49 -0000 Subject: [llvm-commits] [llvm] r112555 - /llvm/trunk/test/CodeGen/ARM/t2-imm.ll Message-ID: <20100830234149.AE5432A6C132@llvm.org> Author: asl Date: Mon Aug 30 18:41:49 2010 New Revision: 112555 URL: http://llvm.org/viewvc/llvm-project?rev=112555&view=rev Log: Fix borken test Modified: llvm/trunk/test/CodeGen/ARM/t2-imm.ll Modified: llvm/trunk/test/CodeGen/ARM/t2-imm.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/t2-imm.ll?rev=112555&r1=112554&r2=112555&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/t2-imm.ll (original) +++ llvm/trunk/test/CodeGen/ARM/t2-imm.ll Mon Aug 30 18:41:49 2010 @@ -1,9 +1,9 @@ -; RUN: llc < %s -march=arm -mattr=+thumb2 | FileCheck %s +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s define i32 @f6(i32 %a) { ; CHECK:f6 -; CHECK: movw r0, #:lower16:65537123 -; CHECK: movt r0, #:upper16:65537123 +; CHECK: movw r0, #1123 +; CHECK: movt r0, #1000 %tmp = add i32 0, 65537123 ret i32 %tmp } From resistor at mac.com Mon Aug 30 18:47:09 2010 From: resistor at mac.com (Owen Anderson) Date: Mon, 30 Aug 2010 16:47:09 -0700 Subject: [llvm-commits] [llvm] r111665 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp test/Transforms/InstCombine/2010-08-19-StoreNarrowing.ll In-Reply-To: References: <20100820182443.4552E2A6C12E@llvm.org> Message-ID: <74D55FC8-5CD1-4F1D-8512-4C4BFC06AD4C@mac.com> On Aug 30, 2010, at 2:26 PM, Chris Lattner wrote: > > >> + ConstantInt *CI1 =0, *CI2 = 0; >> + Value *Ld = 0; >> + if (getTargetData() && >> + match(SI.getValueOperand(), >> + m_And(m_Or(m_Value(Ld), m_ConstantInt(CI1)), m_ConstantInt(CI2))) && >> + isa(Ld) && >> + equivalentAddressValues(cast(Ld)->getPointerOperand(), Ptr)) { > > I don't see where you check to make sure you don't have something like: > > x = load P > store 123 -> Q ;; might alias P! > x' = stuff(x) > store x' -> P > > How do you know the loaded value hasn't been changed in memory? Also, you don't check for a volatile load here. Good catch. Is this even reasonably fixable within the context of instcombine? It looks like we'd want to use something like memdep to guarantee that there are no intervening writes to P. --Owen -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100830/f9118c6d/attachment.html From gohman at apple.com Mon Aug 30 18:47:24 2010 From: gohman at apple.com (Dan Gohman) Date: Mon, 30 Aug 2010 23:47:24 -0000 Subject: [llvm-commits] [llvm] r112557 - in /llvm/trunk: docs/AliasAnalysis.html include/llvm/Analysis/AliasAnalysis.h Message-ID: <20100830234724.BC85F2A6C133@llvm.org> Author: djg Date: Mon Aug 30 18:47:24 2010 New Revision: 112557 URL: http://llvm.org/viewvc/llvm-project?rev=112557&view=rev Log: Update the descriptions of NoModRef and ModRef to be consistent with the descriptions of Mod and Ref. Modified: llvm/trunk/docs/AliasAnalysis.html llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Modified: llvm/trunk/docs/AliasAnalysis.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/AliasAnalysis.html?rev=112557&r1=112556&r2=112557&view=diff ============================================================================== --- llvm/trunk/docs/AliasAnalysis.html (original) +++ llvm/trunk/docs/AliasAnalysis.html Mon Aug 30 18:47:24 2010 @@ -238,10 +238,10 @@

      The AliasAnalysis class also provides a getModRefInfo method for testing dependencies between function calls. This method takes two -call sites (CS1 & CS2), returns NoModRef if the two calls refer to disjoint -memory locations, Ref if CS1 reads memory written by CS2, Mod if CS1 writes to -memory read or written by CS2, or ModRef if CS1 might read or write memory -accessed by CS2. Note that this relation is not commutative.

      +call sites (CS1 & CS2), returns NoModRef if neither call writes to memory +read or written by the other, Ref if CS1 reads memory written by CS2, Mod if CS1 +writes to memory read or written by CS2, or ModRef if CS1 might read or write +memory written to by CS2. Note that this relation is not commutative.

      Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/AliasAnalysis.h?rev=112557&r1=112556&r2=112557&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/AliasAnalysis.h (original) +++ llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Mon Aug 30 18:47:24 2010 @@ -231,11 +231,9 @@ const Value *P, unsigned Size); /// getModRefInfo - Return information about whether two call sites may refer - /// to the same set of memory locations. This function returns NoModRef if - /// the two calls refer to disjoint memory locations, Ref if CS1 reads memory - /// written by CS2, Mod if CS1 writes to memory read or written by CS2, or - /// ModRef if CS1 might read or write memory accessed by CS2. - /// + /// to the same set of memory locations. See + /// http://llvm.org/docs/AliasAnalysis.html#ModRefInfo + /// for details. virtual ModRefResult getModRefInfo(ImmutableCallSite CS1, ImmutableCallSite CS2); From echristo at apple.com Mon Aug 30 18:48:26 2010 From: echristo at apple.com (Eric Christopher) Date: Mon, 30 Aug 2010 23:48:26 -0000 Subject: [llvm-commits] [llvm] r112559 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20100830234826.DBCAB2A6C136@llvm.org> Author: echristo Date: Mon Aug 30 18:48:26 2010 New Revision: 112559 URL: http://llvm.org/viewvc/llvm-project?rev=112559&view=rev Log: If we have an unhandled type then assert, we shouldn't get here for things we can't handle. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=112559&r1=112558&r2=112559&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Mon Aug 30 18:48:26 2010 @@ -396,7 +396,9 @@ assert(VT.isSimple() && "Non-simple types are invalid here!"); switch (VT.getSimpleVT().SimpleTy) { - default: return false; + default: + assert(false && "Trying to emit for an unhandled type!"); + return false; case MVT::i32: { ResultReg = createResultReg(ARM::GPRRegisterClass); // TODO: Fix the Addressing modes so that these can share some code. From gohman at apple.com Mon Aug 30 18:49:59 2010 From: gohman at apple.com (Dan Gohman) Date: Mon, 30 Aug 2010 16:49:59 -0700 Subject: [llvm-commits] [llvm] r110382 - in /llvm/trunk: lib/Analysis/BasicAliasAnalysis.cpp lib/Analysis/MemoryDependenceAnalysis.cpp test/Analysis/BasicAA/getmodrefinfo-cs-cs.ll In-Reply-To: <376524FB-B764-4C0C-9CEE-7E64FB0C8969@apple.com> References: <20100805220915.C1C152A6C12C@llvm.org> <376524FB-B764-4C0C-9CEE-7E64FB0C8969@apple.com> Message-ID: <1098E2A4-8A9E-4330-B95D-E81C81FCE190@apple.com> On Aug 30, 2010, at 2:32 PM, Chris Lattner wrote: > > On Aug 5, 2010, at 3:09 PM, Dan Gohman wrote: > >> Author: djg >> Date: Thu Aug 5 17:09:15 2010 >> New Revision: 110382 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=110382&view=rev >> Log: >> Fix memdep's code for reasoning about dependences between two calls. A Ref >> response from getModRefInfo is not useful here. Instead, check for identical >> calls only in the NoModRef case. >> >> Reapply r110270, and strengthen it to compensate for the memdep changes. >> When both calls are readonly, there is no dependence between them. > > Hi Dan, if you're changing the semantics of the mod/ref queries here, please update this comment in AliasAnalysis.h: > > /// getModRefInfo - Return information about whether two call sites may refer > /// to the same set of memory locations. This function returns NoModRef if > /// the two calls refer to disjoint memory locations, Ref if CS1 reads memory > /// written by CS2, Mod if CS1 writes to memory read or written by CS2, or > /// ModRef if CS1 might read or write memory accessed by CS2. > /// > virtual ModRefResult getModRefInfo(ImmutableCallSite CS1, > ImmutableCallSite CS2); > > also here: > http://llvm.org/docs/AliasAnalysis.html#ModRefInfo My intent was to make the code follow what appeared to be the intent of the documentation, not to change the intent. I've committed r112557 to clarify the documentation. > Note that the call/call modref query should probably return its own (richer) enum than ModRefResult if you're interested in this going forward. Yep. It's not an immediate priority for me though. Dan From resistor at mac.com Mon Aug 30 18:59:30 2010 From: resistor at mac.com (Owen Anderson) Date: Mon, 30 Aug 2010 23:59:30 -0000 Subject: [llvm-commits] [llvm] r112560 - /llvm/trunk/lib/Transforms/Scalar/ValuePropagation.cpp Message-ID: <20100830235930.4B6852A6C136@llvm.org> Author: resistor Date: Mon Aug 30 18:59:30 2010 New Revision: 112560 URL: http://llvm.org/viewvc/llvm-project?rev=112560&view=rev Log: Fix a typo. Modified: llvm/trunk/lib/Transforms/Scalar/ValuePropagation.cpp Modified: llvm/trunk/lib/Transforms/Scalar/ValuePropagation.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ValuePropagation.cpp?rev=112560&r1=112559&r2=112560&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ValuePropagation.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ValuePropagation.cpp Mon Aug 30 18:59:30 2010 @@ -115,5 +115,5 @@ for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI) SimplifyInstructionsInBlock(FI); - return changed; + return Changed; } From clattner at apple.com Mon Aug 30 19:17:25 2010 From: clattner at apple.com (Chris Lattner) Date: Mon, 30 Aug 2010 17:17:25 -0700 Subject: [llvm-commits] [llvm] r110382 - in /llvm/trunk: lib/Analysis/BasicAliasAnalysis.cpp lib/Analysis/MemoryDependenceAnalysis.cpp test/Analysis/BasicAA/getmodrefinfo-cs-cs.ll In-Reply-To: <1098E2A4-8A9E-4330-B95D-E81C81FCE190@apple.com> References: <20100805220915.C1C152A6C12C@llvm.org> <376524FB-B764-4C0C-9CEE-7E64FB0C8969@apple.com> <1098E2A4-8A9E-4330-B95D-E81C81FCE190@apple.com> Message-ID: <164BF6B2-0F8A-4E2A-8341-9BD1381A4DA1@apple.com> On Aug 30, 2010, at 4:49 PM, Dan Gohman wrote: > > On Aug 30, 2010, at 2:32 PM, Chris Lattner wrote: > >> >> On Aug 5, 2010, at 3:09 PM, Dan Gohman wrote: >> >>> Author: djg >>> Date: Thu Aug 5 17:09:15 2010 >>> New Revision: 110382 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=110382&view=rev >>> Log: >>> Fix memdep's code for reasoning about dependences between two calls. A Ref >>> response from getModRefInfo is not useful here. Instead, check for identical >>> calls only in the NoModRef case. >>> >>> Reapply r110270, and strengthen it to compensate for the memdep changes. >>> When both calls are readonly, there is no dependence between them. >> >> Hi Dan, if you're changing the semantics of the mod/ref queries here, please update this comment in AliasAnalysis.h: >> >> /// getModRefInfo - Return information about whether two call sites may refer >> /// to the same set of memory locations. This function returns NoModRef if >> /// the two calls refer to disjoint memory locations, Ref if CS1 reads memory >> /// written by CS2, Mod if CS1 writes to memory read or written by CS2, or >> /// ModRef if CS1 might read or write memory accessed by CS2. >> /// >> virtual ModRefResult getModRefInfo(ImmutableCallSite CS1, >> ImmutableCallSite CS2); >> >> also here: >> http://llvm.org/docs/AliasAnalysis.html#ModRefInfo > > My intent was to make the code follow what appeared to be the intent > of the documentation, not to change the intent. I've committed r112557 > to clarify the documentation. Thanks! >> Note that the call/call modref query should probably return its own (richer) enum than ModRefResult if you're interested in this going forward. > > Yep. It's not an immediate priority for me though. Yep, I'm just admitting to a crappy and confusing api :-) -Chris From clattner at apple.com Mon Aug 30 19:17:54 2010 From: clattner at apple.com (Chris Lattner) Date: Mon, 30 Aug 2010 17:17:54 -0700 Subject: [llvm-commits] [llvm] r111665 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp test/Transforms/InstCombine/2010-08-19-StoreNarrowing.ll In-Reply-To: <74D55FC8-5CD1-4F1D-8512-4C4BFC06AD4C@mac.com> References: <20100820182443.4552E2A6C12E@llvm.org> <74D55FC8-5CD1-4F1D-8512-4C4BFC06AD4C@mac.com> Message-ID: On Aug 30, 2010, at 4:47 PM, Owen Anderson wrote: > > On Aug 30, 2010, at 2:26 PM, Chris Lattner wrote: >> >> >>> + ConstantInt *CI1 =0, *CI2 = 0; >>> + Value *Ld = 0; >>> + if (getTargetData() && >>> + match(SI.getValueOperand(), >>> + m_And(m_Or(m_Value(Ld), m_ConstantInt(CI1)), m_ConstantInt(CI2))) && >>> + isa(Ld) && >>> + equivalentAddressValues(cast(Ld)->getPointerOperand(), Ptr)) { >> >> I don't see where you check to make sure you don't have something like: >> >> x = load P >> store 123 -> Q ;; might alias P! >> x' = stuff(x) >> store x' -> P >> >> How do you know the loaded value hasn't been changed in memory? Also, you don't check for a volatile load here. > > Good catch. Is this even reasonably fixable within the context of instcombine? It looks like we'd want to use something like memdep to guarantee that there are no intervening writes to P. This is best done in dag combine, where the chains tell you this. Please revert your instcombine change. -Chris -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100830/d54f3355/attachment.html From clattner at apple.com Mon Aug 30 19:23:24 2010 From: clattner at apple.com (Chris Lattner) Date: Mon, 30 Aug 2010 17:23:24 -0700 Subject: [llvm-commits] [llvm] r112550 - /llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp In-Reply-To: <20100830232236.310EE2A6C12F@llvm.org> References: <20100830232236.310EE2A6C12F@llvm.org> Message-ID: On Aug 30, 2010, at 4:22 PM, Owen Anderson wrote: > Re-apply r112539, being more careful to respect the return values of the constant folding methods. Additionally, > use the ConstantExpr::get*() methods to simplify some constant folding. Thanks. > +++ llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Mon Aug 30 18:22:36 2010 > @@ -16,6 +16,7 @@ > #include "llvm/IntrinsicInst.h" > #include "llvm/LLVMContext.h" > #include "llvm/Pass.h" > +#include "llvm/Analysis/ConstantFolding.h" This isn't needed. > @@ -325,9 +326,10 @@ > } else if (LVI) { > Constant *CI = LVI->getConstantOnEdge(InVal, > PN->getIncomingBlock(i), BB); > + // LVI returns null is no value could be determined. > + if (!CI) continue; > + ConstantInt *CInt = dyn_cast(CI); > + Result.push_back(std::make_pair(CInt, PN->getIncomingBlock(i))); I'm pretty sure that this is not safe/correct if CI is a constantexpr. > @@ -400,12 +398,19 @@ > // AND or OR of a value with itself is that value. > ConstantInt *CI = dyn_cast(BO->getOperand(1)); > if (CI && (BO->getOpcode() == Instruction::And || > + BO->getOpcode() == Instruction::Or)) { > SmallVector, 8> LHSVals; > ComputeValueKnownInPredecessors(BO->getOperand(0), BB, LHSVals); > + for (unsigned i = 0, e = LHSVals.size(); i != e; ++i) > + if (LHSVals[i].first == 0) { > + ConstantInt *Zero = > + cast(ConstantInt::get(BO->getType(), 0)); > + Result.push_back(std::make_pair(Zero, LHSVals[i].second)); This isn't correct for 'or'. undef | x -> -1. It would be best to turn "null" into an UndefValue, then pass *that* into ConstantExpr::get, then decode that back into undef/ConstantInt/other. > @@ -472,20 +477,18 @@ > > // Try to find a constant value for the LHS of an equality comparison, > // and evaluate it statically if we can. > + if (Constant *CmpConst = dyn_cast(Cmp->getOperand(1))) { > SmallVector, 8> LHSVals; > ComputeValueKnownInPredecessors(I->getOperand(0), BB, LHSVals); > > for (unsigned i = 0, e = LHSVals.size(); i != e; ++i) { > + if (LHSVals[i].first == 0) > + Result.push_back(std::make_pair((ConstantInt*)0, > + LHSVals[i].second)); > + else if (Constant *Folded = ConstantExpr::getCompare( > + Cmp->getPredicate(), LHSVals[i].first, CmpConst)) > + Result.push_back(std::make_pair(cast(Folded), > + LHSVals[i].second)); This will abort if ConstantExpr::getCompare returns a ConstantExpr, which it can. I'm still waiting for testcases. -Chris From clattner at apple.com Mon Aug 30 19:24:51 2010 From: clattner at apple.com (Chris Lattner) Date: Mon, 30 Aug 2010 17:24:51 -0700 Subject: [llvm-commits] [llvm] r112325 - in /llvm/trunk: include/llvm/LinkAllPasses.h include/llvm/Transforms/Scalar.h lib/Transforms/Scalar/ValuePropagation.cpp test/Transforms/ValuePropagation/ test/Transforms/ValuePropagation/dg.exp test/Transforms/ValuePropagation/phi.ll test/Transforms/ValuePropagation/select.ll In-Reply-To: <97AFEA28-0E1F-48C6-A8F1-222AAD4DA53E@mac.com> References: <20100827233136.5F7A72A6C12C@llvm.org> <97AFEA28-0E1F-48C6-A8F1-222AAD4DA53E@mac.com> Message-ID: On Aug 30, 2010, at 4:34 PM, Owen Anderson wrote: > On Aug 30, 2010, at 3:46 PM, Chris Lattner wrote: >>> +++ llvm/trunk/lib/Transforms/Scalar/ValuePropagation.cpp Fri Aug 27 18:31:36 2010 >>> @@ -0,0 +1,113 @@ >>> +//===- ValuePropagation.cpp - Propagate information derived control flow --===// >>> +// >>> +// The LLVM Compiler Infrastructure >>> +// >>> +// This file is distributed under the University of Illinois Open Source >>> +// License. See LICENSE.TXT for details. >>> +// >>> +//===----------------------------------------------------------------------===// >>> +// >>> +// This file implements the Value Propagation pass. >> >> The name of this pass is very generic. Can you think of something better? It's not really propagating values afterall. > > I don't really have a better idea for it. I'm open to suggestions. How about "correlated value prop" or something like that? >>> + if (changed) >>> + for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI) >>> + SimplifyInstructionsInBlock(FI); >> >> This loop is very odd... what does it do and why? Why does it belong here? > > The actual value propagation will tend to leave a lot of unused values and/or newly-constant PHI nodes sitting around. These can't be removed/simplified during the main loop without invalidating the BasicBlock::iterator. Why not leave it to a later pass to clean up? Why not clean up each basic block after you walk if if any changes were made in that block? > If ValuePropagation is run early enough, this probably isn't necessary as later runs of instcombine should clean up after it. However, if we want to run it reasonably late, we probably want it to clean up after itself. What's the right answer? -Chris From clattner at apple.com Mon Aug 30 20:15:11 2010 From: clattner at apple.com (Chris Lattner) Date: Mon, 30 Aug 2010 18:15:11 -0700 Subject: [llvm-commits] [llvm] r112270 - in /llvm/trunk: lib/Analysis/LazyValueInfo.cpp lib/Transforms/Scalar/JumpThreading.cpp test/Transforms/JumpThreading/basic.ll test/Transforms/JumpThreading/lvi-load.ll In-Reply-To: <20100827171230.148632A6C12C@llvm.org> References: <20100827171230.148632A6C12C@llvm.org> Message-ID: <790FB0EB-2369-4BB6-AF68-73720AFFF3EF@apple.com> On Aug 27, 2010, at 10:12 AM, Owen Anderson wrote: > URL: http://llvm.org/viewvc/llvm-project?rev=112270&view=rev > Log: > Use LVI to eliminate conditional branches where we've tested a related condition previously. Update tests for this change. > This fixes PR5652. Ok. > + // For predecessor edge, determine if the comparison is true or false > + // on that edge. If they're all true or all false, we can simplify the > + // branch. > + // FIXME: We could handle mixed true/false by duplicating code. > + unsigned Trues = 0, Falses = 0, predcount = 0; > + for (pred_iterator PI = pred_begin(BB), PE = pred_end(BB);PI != PE; ++PI){ > + ++predcount; > + LazyValueInfo::Tristate Ret = > + LVI->getPredicateOnEdge(CondCmp->getPredicate(), > + CondCmp->getOperand(0), CondConst, *PI, BB); > + if (Ret == LazyValueInfo::True) > + ++Trues; > + else if (Ret == LazyValueInfo::False) > + ++Falses; > + } This loop is serious overkill. You evaluate getPredicateOnEdge for every predecessor, even when it is clear that nothing will be done. It would be better to factor this out into a helper function, then call it once for the first pred. If the first pred is true/false, walk through the rest of the preds while they are true/false. If ever there is a mismatch, bail out. > + // If we can determine the branch direction statically, converted > + // the conditional branch to an unconditional one. > + if (Trues && Trues == predcount) { > + RemovePredecessorAndSimplify(CondBr->getSuccessor(1), BB, TD); > + BranchInst::Create(CondBr->getSuccessor(0), CondBr); > + CondBr->eraseFromParent(); > + return true; > + } else if (Falses && Falses == predcount) { Minor nit, you don't need an 'else' after a return. > +++ llvm/trunk/test/Transforms/JumpThreading/basic.ll Fri Aug 27 12:12:29 2010 > @@ -147,11 +147,17 @@ I see that this changes some tests (so you can claim that it is tested), but it also seems that you should be adding a specific test (e.g. to basic.ll) with an example distilled from PR5652. -Chris > ; CHECK: @test6 > %tmp455 = icmp eq i32 %A, 42 > br i1 %tmp455, label %BB1, label %BB2 > - > -BB2: > + > +; CHECK: call i32 @f2() > +; CHECK-NEXT: ret i32 3 > + > ; CHECK: call i32 @f1() > -; CHECK-NEXT: call void @f3() > -; CHECK-NEXT: ret i32 4 > +; CHECK-NOT: br > +; CHECK: call void @f3() > +; CHECK-NOT: br > +; CHECK: ret i32 4 > + > +BB2: > call i32 @f1() > br label %BB1 > > > Modified: llvm/trunk/test/Transforms/JumpThreading/lvi-load.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/JumpThreading/lvi-load.ll?rev=112270&r1=112269&r2=112270&view=diff > ============================================================================== > --- llvm/trunk/test/Transforms/JumpThreading/lvi-load.ll (original) > +++ llvm/trunk/test/Transforms/JumpThreading/lvi-load.ll Fri Aug 27 12:12:29 2010 > @@ -1,4 +1,4 @@ > -; RUN: opt -S -jump-threading -enable-jump-threading-lvi < %s | FileCheck %s > +; RUN: opt -S -jump-threading -enable-jump-threading-lvi -dce < %s | FileCheck %s > target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" > target triple = "x86_64-apple-darwin10.4" > > @@ -25,6 +25,7 @@ > %toBoolnot.i.i = icmp ult i8 %1, 21 ; [#uses=1] > br i1 %toBoolnot.i.i, label %bb6.i.i, label %_ZN4llvm8dyn_castINS_11InstructionEPNS_5ValueEEENS_10cast_rettyIT_T0_E8ret_typeERKS6_.exit > > +; CHECK-NOT: assert > bb6.i.i: ; preds = %bb.i > tail call void @__assert_rtn(i8* getelementptr inbounds ([5 x i8]* @_ZZN4llvm4castINS_11InstructionEPNS_5ValueEEENS_10cast_rettyIT_T0_E8ret_typeERKS6_E8__func__, i64 0, i64 0), i8* getelementptr inbounds ([31 x i8]* @.str, i64 0, i64 0), i32 202, i8* getelementptr inbounds ([59 x i8]* @.str1, i64 0, i64 0)) noreturn > unreachable > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From stoklund at 2pi.dk Mon Aug 30 20:27:50 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 31 Aug 2010 01:27:50 -0000 Subject: [llvm-commits] [llvm] r112567 - /llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Message-ID: <20100831012750.25FCE2A6C12D@llvm.org> Author: stoklund Date: Mon Aug 30 20:27:49 2010 New Revision: 112567 URL: http://llvm.org/viewvc/llvm-project?rev=112567&view=rev Log: Add experimental -disable-physical-join command line option. Eventually, we want to disable physreg coalescing completely, and let the register allocator do its job using hints. This option makes it possible to measure the impact of disabling physreg coalescing. Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=112567&r1=112566&r2=112567&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original) +++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Mon Aug 30 20:27:49 2010 @@ -59,6 +59,11 @@ cl::desc("Avoid coalescing cross register class copies"), cl::init(false), cl::Hidden); +static cl::opt +DisablePhysicalJoin("disable-physical-join", + cl::desc("Avoid coalescing physical register copies"), + cl::init(false), cl::Hidden); + INITIALIZE_AG_PASS(SimpleRegisterCoalescing, RegisterCoalescer, "simple-register-coalescing", "Simple Register Coalescing", false, false, true); @@ -1036,6 +1041,11 @@ return false; // Not coalescable. } + if (DisablePhysicalJoin && CP.isPhys()) { + DEBUG(dbgs() << "\tPhysical joins disabled.\n"); + return false; + } + DEBUG(dbgs() << "\tConsidering merging %reg" << CP.getSrcReg()); // Enforce policies. From echristo at apple.com Mon Aug 30 20:28:42 2010 From: echristo at apple.com (Eric Christopher) Date: Tue, 31 Aug 2010 01:28:42 -0000 Subject: [llvm-commits] [llvm] r112568 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20100831012842.99DC52A6C12D@llvm.org> Author: echristo Date: Mon Aug 30 20:28:42 2010 New Revision: 112568 URL: http://llvm.org/viewvc/llvm-project?rev=112568&view=rev Log: Rewrite slightly so we can expand for floating point types easier. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=112568&r1=112567&r2=112568&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Mon Aug 30 20:28:42 2010 @@ -318,8 +318,9 @@ // Only handle simple types. if (VT == MVT::Other || !VT.isSimple()) return false; - // For now, only handle 32-bit types. - return VT == MVT::i32; + // Handle all legal types, i.e. a register that will directly hold this + // value. + return TLI.isTypeLegal(VT); } // Computes the Reg+Offset to get to an object. @@ -387,7 +388,6 @@ return true; } } - return false; } @@ -395,25 +395,33 @@ unsigned Reg, int Offset) { assert(VT.isSimple() && "Non-simple types are invalid here!"); + + bool isThumb = AFI->isThumbFunction(); + unsigned Opc; + switch (VT.getSimpleVT().SimpleTy) { default: assert(false && "Trying to emit for an unhandled type!"); return false; - case MVT::i32: { - ResultReg = createResultReg(ARM::GPRRegisterClass); - // TODO: Fix the Addressing modes so that these can share some code. - // Since this is a Thumb1 load this will work in Thumb1 or 2 mode. - if (AFI->isThumbFunction()) - AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, - TII.get(ARM::tLDR), ResultReg) - .addReg(Reg).addImm(Offset).addReg(0)); - else - AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, - TII.get(ARM::LDR), ResultReg) - .addReg(Reg).addReg(0).addImm(Offset)); - return true; - } - } + case MVT::i32: + Opc = isThumb ? ARM::tLDR : ARM::LDR; + break; + } + + ResultReg = createResultReg(TLI.getRegClassFor(VT)); + + // TODO: Fix the Addressing modes so that these can share some code. + // Since this is a Thumb1 load this will work in Thumb1 or 2 mode. + if (isThumb) + AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, + TII.get(Opc), ResultReg) + .addReg(Reg).addImm(Offset).addReg(0)); + else + AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, + TII.get(Opc), ResultReg) + .addReg(Reg).addReg(0).addImm(Offset)); + + return true; } bool ARMFastISel::ARMSelectLoad(const Instruction *I) { From bruno.cardoso at gmail.com Mon Aug 30 21:26:40 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 31 Aug 2010 02:26:40 -0000 Subject: [llvm-commits] [llvm] r112570 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20100831022640.DA6242A6C12D@llvm.org> Author: bruno Date: Mon Aug 30 21:26:40 2010 New Revision: 112570 URL: http://llvm.org/viewvc/llvm-project?rev=112570&view=rev Log: Use X86ISD::MOVSS and MOVSD to represent the movl mask pattern, also fix the handling of those nodes when seeking for scalars inside vector shuffles Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=112570&r1=112569&r2=112570&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Aug 30 21:26:40 2010 @@ -3656,11 +3656,13 @@ if (isTargetShuffle(Opcode)) { switch(Opcode) { case X86ISD::MOVSS: - case X86ISD::MOVSD: - // Only care about the second operand, which can contain - // a scalar_to_vector which we are looking for. - return getShuffleScalarElt(V.getOperand(1).getNode(), - 0 /* Index */, DAG); + case X86ISD::MOVSD: { + // The index 0 always comes from the first element of the second source, + // this is why MOVSS and MOVSD are used in the first place. The other + // elements come from the other positions of the first source vector. + unsigned OpNum = (Index == 0) ? 1 : 0; + return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG); + } default: assert("not implemented for target shuffle node"); return SDValue(); @@ -5098,8 +5100,13 @@ return V2; if (ISD::isBuildVectorAllZeros(V1.getNode())) return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); - if (!isMMX) - return Op; + if (!isMMX && !X86::isMOVLPMask(SVOp)) { + if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64)) + return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); + + if (VT == MVT::v4i32 || VT == MVT::v4f32) + return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); + } } // FIXME: fold these into legal mask. From bruno.cardoso at gmail.com Mon Aug 30 21:36:20 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 31 Aug 2010 02:36:20 -0000 Subject: [llvm-commits] [llvm] r112571 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAG.h lib/CodeGen/SelectionDAG/SelectionDAG.cpp Message-ID: <20100831023620.546B72A6C12D@llvm.org> Author: bruno Date: Mon Aug 30 21:36:20 2010 New Revision: 112571 URL: http://llvm.org/viewvc/llvm-project?rev=112571&view=rev Log: zap unused method. x86 is the only user and already has a more powerfull version Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=112571&r1=112570&r2=112571&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Mon Aug 30 21:36:20 2010 @@ -977,10 +977,6 @@ /// been verified as a debug information descriptor. bool isVerifiedDebugInfoDesc(SDValue Op) const; - /// getShuffleScalarElt - Returns the scalar element that will make up the ith - /// element of the result of the vector shuffle. - SDValue getShuffleScalarElt(const ShuffleVectorSDNode *N, unsigned Idx); - /// UnrollVectorOp - Utility function used by legalize and lowering to /// "unroll" a vector operation by splitting out the scalars and operating /// on each element individually. If the ResNE is 0, fully unroll the vector Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=112571&r1=112570&r2=112571&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Aug 30 21:36:20 2010 @@ -2281,35 +2281,6 @@ } -/// getShuffleScalarElt - Returns the scalar element that will make up the ith -/// element of the result of the vector shuffle. -SDValue SelectionDAG::getShuffleScalarElt(const ShuffleVectorSDNode *N, - unsigned i) { - EVT VT = N->getValueType(0); - if (N->getMaskElt(i) < 0) - return getUNDEF(VT.getVectorElementType()); - unsigned Index = N->getMaskElt(i); - unsigned NumElems = VT.getVectorNumElements(); - SDValue V = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); - Index %= NumElems; - - if (V.getOpcode() == ISD::BIT_CONVERT) { - V = V.getOperand(0); - EVT VVT = V.getValueType(); - if (!VVT.isVector() || VVT.getVectorNumElements() != (unsigned)NumElems) - return SDValue(); - } - if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) - return (Index == 0) ? V.getOperand(0) - : getUNDEF(VT.getVectorElementType()); - if (V.getOpcode() == ISD::BUILD_VECTOR) - return V.getOperand(Index); - if (const ShuffleVectorSDNode *SVN = dyn_cast(V)) - return getShuffleScalarElt(SVN, Index); - return SDValue(); -} - - /// getNode - Gets or creates the specified node. /// SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT) { From aggarwa4 at illinois.edu Mon Aug 30 22:59:09 2010 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Tue, 31 Aug 2010 03:59:09 -0000 Subject: [llvm-commits] [poolalloc] r112572 - /poolalloc/trunk/README Message-ID: <20100831035909.C89512A6C12C@llvm.org> Author: aggarwa4 Date: Mon Aug 30 22:59:09 2010 New Revision: 112572 URL: http://llvm.org/viewvc/llvm-project?rev=112572&view=rev Log: Test Commit Modified: poolalloc/trunk/README Modified: poolalloc/trunk/README URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/README?rev=112572&r1=112571&r2=112572&view=diff ============================================================================== --- poolalloc/trunk/README (original) +++ poolalloc/trunk/README Mon Aug 30 22:59:09 2010 @@ -82,5 +82,3 @@ The LLVM Developer's Mailing List provides announcements and general discussion about LLVM. The list is low volume. You can subscribe to it at http://mail.cs.uiuc.edu/mailman/listinfo/llvmdev. - - From aggarwa4 at illinois.edu Mon Aug 30 23:04:31 2010 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Tue, 31 Aug 2010 04:04:31 -0000 Subject: [llvm-commits] [poolalloc] r112573 - /poolalloc/trunk/lib/DSA/TopDownClosure.cpp Message-ID: <20100831040431.832A02A6C12C@llvm.org> Author: aggarwa4 Date: Mon Aug 30 23:04:31 2010 New Revision: 112573 URL: http://llvm.org/viewvc/llvm-project?rev=112573&view=rev Log: Fixed test/dsa/regression/2010-08-23-InlineCallersSegfault.ll Modified: poolalloc/trunk/lib/DSA/TopDownClosure.cpp Modified: poolalloc/trunk/lib/DSA/TopDownClosure.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/TopDownClosure.cpp?rev=112573&r1=112572&r2=112573&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/TopDownClosure.cpp (original) +++ poolalloc/trunk/lib/DSA/TopDownClosure.cpp Mon Aug 30 23:04:31 2010 @@ -353,6 +353,10 @@ E = callgraph.callee_end(CI->getCallSite()); I != E; ++I) if (!(*I)->isDeclaration()) Callees.push_back(*I); + + // If all of the callees are declarations, there is no need to merge the calls. + if(Callees.empty()) + continue; std::sort(Callees.begin(), Callees.end()); std::map, DSGraph*>::iterator IndCallRecI = From aggarwa4 at illinois.edu Mon Aug 30 23:15:49 2010 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Tue, 31 Aug 2010 04:15:49 -0000 Subject: [llvm-commits] [poolalloc] r112574 - /poolalloc/trunk/lib/DSA/CompleteBottomUp.cpp Message-ID: <20100831041549.67C9F2A6C12C@llvm.org> Author: aggarwa4 Date: Mon Aug 30 23:15:49 2010 New Revision: 112574 URL: http://llvm.org/viewvc/llvm-project?rev=112574&view=rev Log: Fix for dsa/regression/2010-07-16.CBU_MissingGraph.ll. The DSCallGraph replaced the call targets of an indirect function call site with the leader of the SCC, in which the callee lies. CBU would then look for an entry for the leader in the GlobalsGraph, which did not exist because the leader of the SCC was never address taken. The fix, goes through all functions, in the SCC of the callees at a call site, and merges all the functions that have entries in the GlobalsGraph Modified: poolalloc/trunk/lib/DSA/CompleteBottomUp.cpp Modified: poolalloc/trunk/lib/DSA/CompleteBottomUp.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/CompleteBottomUp.cpp?rev=112574&r1=112573&r2=112574&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/CompleteBottomUp.cpp (original) +++ poolalloc/trunk/lib/DSA/CompleteBottomUp.cpp Mon Aug 30 23:15:49 2010 @@ -88,6 +88,14 @@ #ifndef NDEBUG // --Verify that for every callee of an indirect function call // we have an entry in the GlobalsGraph + + // If any function in an SCC is a callee of an indirect function + // call, the DScallgraph contains the leader of the SCC as the + // callee of the indirect call. + // The leasder of the SCC may not have an entry in the Globals + // Graph, but at least one of the functions in the SCC + // should have an entry in the GlobalsGraph + bool isIndirect = ((*ii).getCalledFunction() == NULL); if (isIndirect) { @@ -101,9 +109,16 @@ // class leader instead of the global itself. // const Function * F = *csii; - if (!(F->isDeclaration())) - assert (SM.count (SM.getLeaderForGlobal(F)) && + if (!(F->isDeclaration())){ + DSCallGraph::scc_iterator sccii = callgraph.scc_begin(F), + sccee = callgraph.scc_end(F); + bool flag = false; + for(; sccii != sccee; ++sccii) { + flag |= SM.count(SM.getLeaderForGlobal(*sccii)); + } + assert (flag && "Indirect function callee not in globals?"); + } } } @@ -131,23 +146,55 @@ DSCallGraph::callee_iterator csi = callgraph.callee_begin(*ii), cse = callgraph.callee_end(*ii); - // Grab the first callee we have an entry for... - while (csi != cse && !SM.count(*csi)) + + // We get all the callees, and then for all functions in that SCC, find the + // ones that have entries in the GlobalsGraph. + + // We merge all the functions in the SCC that have entries, and then move + // on to the next callee and repeat. + + // If an SCC has functions that have entries in the GlobalsGraph, and are + // targets of an indirect function call site, they will be merged. + + // However, if an SCC has functions, that have entries in the GlobalsGraph, + // bur are not the targets of an indirect function call site, they will not + // be merged by CBU. + + DSNodeHandle SrcNH; + while(csi != cse) { + const Function *F = *csi; + DSCallGraph::scc_iterator sccii = callgraph.scc_begin(F), + sccee = callgraph.scc_end(F); + while(sccii != sccee && SM.find(*sccii) == SM.end()) { + ++sccii; + } + if(sccii == sccee) { + ++csi; + continue; + } + DSNodeHandle SrcNH = SM.find(*sccii)->second; + ++sccii; + for(;sccii != sccee; ++sccii) { + DSGraph::ScalarMapTy::const_iterator I = SM.find(*sccii); + if (I != SM.end()) { + SrcNH.mergeWith(I->second); + } + } ++csi; - - // - // If we have no entries, we're done. Move on to the next call site. - // - if (csi == cse) continue; - - DSNodeHandle& SrcNH = SM.find(*csi)->second; - - // Merge the rest of the callees (that we have entries for) together - // with the first one. - for (; csi != cse; ++csi) { - if (SM.count(*csi)) { - SrcNH.mergeWith(SM.find(*csi)->second); + break; + } + + while(csi != cse) { + const Function *F = *csi; + DSCallGraph::scc_iterator sccii = callgraph.scc_begin(F), + sccee = callgraph.scc_end(F); + for(;sccii != sccee; ++sccii) { + DSGraph::ScalarMapTy::const_iterator I = SM.find(*sccii); + if (I != SM.end()) { + SrcNH.mergeWith(I->second); + } } + ++csi; } } } From resistor at mac.com Mon Aug 30 23:41:06 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 31 Aug 2010 04:41:06 -0000 Subject: [llvm-commits] [llvm] r112575 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp test/Transforms/InstCombine/2010-08-19-StoreNarrowing.ll Message-ID: <20100831044106.918252A6C12C@llvm.org> Author: resistor Date: Mon Aug 30 23:41:06 2010 New Revision: 112575 URL: http://llvm.org/viewvc/llvm-project?rev=112575&view=rev Log: Remove r111665, which implemented store-narrowing in InstCombine. Chris discovered a miscompilation in it, and it's not easily fixable at the optimizer level. I'll investigate reimplementing it in DAGCombine. Removed: llvm/trunk/test/Transforms/InstCombine/2010-08-19-StoreNarrowing.ll Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp?rev=112575&r1=112574&r2=112575&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp Mon Aug 30 23:41:06 2010 @@ -14,13 +14,11 @@ #include "InstCombine.h" #include "llvm/IntrinsicInst.h" #include "llvm/Analysis/Loads.h" -#include "llvm/Support/PatternMatch.h" #include "llvm/Target/TargetData.h" #include "llvm/Transforms/Utils/BasicBlockUtils.h" #include "llvm/Transforms/Utils/Local.h" #include "llvm/ADT/Statistic.h" using namespace llvm; -using namespace PatternMatch; STATISTIC(NumDeadStore, "Number of dead stores eliminated"); @@ -475,51 +473,6 @@ if (SI.isVolatile()) return 0; // Don't hack volatile stores. - // Attempt to narrow sequences where we load a wide value, perform bitmasks - // that only affect the low bits of it, and then store it back. This - // typically arises from bitfield initializers in C++. - ConstantInt *CI1 =0, *CI2 = 0; - Value *Ld = 0; - if (getTargetData() && - match(SI.getValueOperand(), - m_And(m_Or(m_Value(Ld), m_ConstantInt(CI1)), m_ConstantInt(CI2))) && - isa(Ld) && - equivalentAddressValues(cast(Ld)->getPointerOperand(), Ptr)) { - APInt OrMask = CI1->getValue(); - APInt AndMask = CI2->getValue(); - - // Compute the prefix of the value that is unmodified by the bitmasking. - unsigned LeadingAndOnes = AndMask.countLeadingOnes(); - unsigned LeadingOrZeros = OrMask.countLeadingZeros(); - unsigned Prefix = std::min(LeadingAndOnes, LeadingOrZeros); - uint64_t NewWidth = AndMask.getBitWidth() - Prefix; - while (NewWidth < AndMask.getBitWidth() && - getTargetData()->isIllegalInteger(NewWidth)) - NewWidth = NextPowerOf2(NewWidth); - - // If we can find a power-of-2 prefix (and if the values we're working with - // are themselves POT widths), then we can narrow the store. We rely on - // later iterations of instcombine to propagate the demanded bits to narrow - // the other computations in the chain. - if (NewWidth < AndMask.getBitWidth() && - getTargetData()->isLegalInteger(NewWidth)) { - const Type *NewType = IntegerType::get(Ptr->getContext(), NewWidth); - const Type *NewPtrType = PointerType::getUnqual(NewType); - - Value *NewVal = Builder->CreateTrunc(SI.getValueOperand(), NewType); - Value *NewPtr = Builder->CreateBitCast(Ptr, NewPtrType); - - // On big endian targets, we need to offset from the original pointer - // in order to store to the low-bit suffix. - if (getTargetData()->isBigEndian()) { - uint64_t GEPOffset = (AndMask.getBitWidth() - NewWidth) / 8; - NewPtr = Builder->CreateConstGEP1_64(NewPtr, GEPOffset); - } - - return new StoreInst(NewVal, NewPtr); - } - } - // store X, null -> turns into 'unreachable' in SimplifyCFG if (isa(Ptr) && SI.getPointerAddressSpace() == 0) { if (!isa(Val)) { Removed: llvm/trunk/test/Transforms/InstCombine/2010-08-19-StoreNarrowing.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/2010-08-19-StoreNarrowing.ll?rev=112574&view=auto ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/2010-08-19-StoreNarrowing.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/2010-08-19-StoreNarrowing.ll (removed) @@ -1,21 +0,0 @@ -; RUN: opt -S -instcombine %s | not grep and -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" -target triple = "x86_64-apple-darwin10.0.0" - -%class.A = type { i8, [3 x i8] } - -define void @_ZN1AC2Ev(%class.A* %this) nounwind ssp align 2 { -entry: - %0 = bitcast %class.A* %this to i32* ; [#uses=5] - %1 = load i32* %0, align 4 ; [#uses=1] - %2 = and i32 %1, -8 ; [#uses=2] - store i32 %2, i32* %0, align 4 - %3 = and i32 %2, -57 ; [#uses=1] - %4 = or i32 %3, 8 ; [#uses=2] - store i32 %4, i32* %0, align 4 - %5 = and i32 %4, -65 ; [#uses=2] - store i32 %5, i32* %0, align 4 - %6 = and i32 %5, -129 ; [#uses=1] - store i32 %6, i32* %0, align 4 - ret void -} From wdietz2 at illinois.edu Mon Aug 30 23:57:41 2010 From: wdietz2 at illinois.edu (Will Dietz) Date: Tue, 31 Aug 2010 04:57:41 -0000 Subject: [llvm-commits] [poolalloc] r112576 - /poolalloc/trunk/test/dsa/regression/2010-07-16.CBU_MissingGraph.ll Message-ID: <20100831045741.7A4E62A6C12C@llvm.org> Author: wdietz2 Date: Mon Aug 30 23:57:41 2010 New Revision: 112576 URL: http://llvm.org/viewvc/llvm-project?rev=112576&view=rev Log: Fix typo in test RUN line: daopt->dsaopt Modified: poolalloc/trunk/test/dsa/regression/2010-07-16.CBU_MissingGraph.ll Modified: poolalloc/trunk/test/dsa/regression/2010-07-16.CBU_MissingGraph.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/regression/2010-07-16.CBU_MissingGraph.ll?rev=112576&r1=112575&r2=112576&view=diff ============================================================================== --- poolalloc/trunk/test/dsa/regression/2010-07-16.CBU_MissingGraph.ll (original) +++ poolalloc/trunk/test/dsa/regression/2010-07-16.CBU_MissingGraph.ll Mon Aug 30 23:57:41 2010 @@ -6,9 +6,8 @@ ;RUN: -dsa-no-filter-callcc=true \ ;RUN: -dsa-no-filter-vararg=true \ ;RUN: -dsa-no-filter-intfp=true -;RUN: dsaopt %s -dsa-cbu -disable-output ;--verify this works with filtering -;RUN: daopt %s -dsa-cbu -disable-output +;RUN: dsaopt %s -dsa-cbu -disable-output ; ModuleID = 'bugpoint-reduced-simplified.bc' target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-apple-darwin10.4" From nicholas at mxc.ca Tue Aug 31 00:30:24 2010 From: nicholas at mxc.ca (Nick Lewycky) Date: Mon, 30 Aug 2010 22:30:24 -0700 Subject: [llvm-commits] PATCH: add ContextualDenseMap In-Reply-To: <6644A46A-EC23-447F-9D4C-A800FCF6540F@apple.com> References: <4C7686B5.7060605@mxc.ca> <6644A46A-EC23-447F-9D4C-A800FCF6540F@apple.com> Message-ID: <4C7C9370.1080700@mxc.ca> Chris Lattner wrote: > > On Aug 30, 2010, at 2:52 PM, Nick Lewycky wrote: > >> On 30 August 2010 14:03, Chris Lattner > > wrote: >> >> >> On Aug 26, 2010, at 8:22 AM, Nick Lewycky wrote: >> >> > This patch adds a new ContextualDenseMap and sinks most of the >> dense map logic into DenseMapImpl. A ContextualDenseMap takes a >> ContextualDenseMapInfo pointer instead of just a typename. I need >> this for mergefuncs where I want a comparison operation that >> involves target data. >> > >> > The four map info functions (getTombstoneKey, getEmptyKey, >> getHashValue and isEqual) are made virtual in DenseMapImpl and >> then implemented once in DenseMap and again in ContextualDenseMap. >> This implementation is modelled after the relationship between >> ContextualFoldingSet and FoldingSet. >> >> This seems like it will slow down densemap, perhaps substantially, >> by introducing virtual methods. >> >> >> That matches my reaction when looking at FoldingSet but I decided that >> someone else probably knows more than I do. I'll change this, and >> probably FoldingSet too. > > DenseMap and FoldingSet are used by very different clients. The cost of > the virtual method in FoldingSet is far less of an issue because the > cost of populating Profile info is much higher than the cost of > computing a hash value. > >> It's also not clear to me what this is actually doing. Please >> explain what you are trying to do and why the current densemap >> can't do it. >> >> >> My implementation of isEqual for MergeFunctions requires a TargetData >> object. Because the existing DenseMap takes a type and not an object, >> and the DenseMapInfo methods are all static, I can't give it a >> TargetData* to use unless I'm willing to stick it in a global >> variable. (And if you prefer that, let me know; I'd ruled it out.) > > Why not make the value in the hash table a struct that contains a > Function* and a TargetData* (and a cached hash value)? Thanks Chris, that works great. Nick From nicholas at mxc.ca Tue Aug 31 00:53:05 2010 From: nicholas at mxc.ca (Nick Lewycky) Date: Tue, 31 Aug 2010 05:53:05 -0000 Subject: [llvm-commits] [llvm] r112582 - /llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp Message-ID: <20100831055305.42B902A6C12C@llvm.org> Author: nicholas Date: Tue Aug 31 00:53:05 2010 New Revision: 112582 URL: http://llvm.org/viewvc/llvm-project?rev=112582&view=rev Log: Switch to DenseSet, simplifying much more code. We now have a single iteration where we hash, compare and fold, instead of one iteration where we build up the hash buckets and a second one to fold. Modified: llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp Modified: llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp?rev=112582&r1=112581&r2=112582&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp Tue Aug 31 00:53:05 2010 @@ -45,10 +45,11 @@ #define DEBUG_TYPE "mergefunc" #include "llvm/Transforms/IPO.h" -#include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/DenseSet.h" #include "llvm/ADT/FoldingSet.h" #include "llvm/ADT/SmallSet.h" #include "llvm/ADT/Statistic.h" +#include "llvm/ADT/STLExtras.h" #include "llvm/Constants.h" #include "llvm/InlineAsm.h" #include "llvm/Instructions.h" @@ -59,10 +60,9 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/IRBuilder.h" +#include "llvm/Support/ValueHandle.h" #include "llvm/Support/raw_ostream.h" #include "llvm/Target/TargetData.h" -#include -#include using namespace llvm; STATISTIC(NumFunctionsMerged, "Number of functions merged"); @@ -81,14 +81,9 @@ bool runOnModule(Module &M); private: - /// PairwiseCompareAndMerge - Given a list of functions, compare each pair - /// and merge the pairs of equivalent functions. - bool PairwiseCompareAndMerge(std::vector &FnVec); - - /// MergeTwoFunctions - Merge two equivalent functions. Upon completion, - /// FnVec[j] should never be visited again. - void MergeTwoFunctions(std::vector &FnVec, - unsigned i, unsigned j) const; + /// MergeTwoFunctions - Merge two equivalent functions. Upon completion, G + /// is deleted. + void MergeTwoFunctions(Function *F, Function *G) const; /// WriteThunk - Replace G with a simple tail call to bitcast(F). Also /// replace direct uses of G with bitcast(F). @@ -112,7 +107,8 @@ /// side of claiming that two functions are different). class FunctionComparator { public: - FunctionComparator(TargetData *TD, Function *F1, Function *F2) + FunctionComparator(const TargetData *TD, const Function *F1, + const Function *F2) : F1(F1), F2(F2), TD(TD), IDMap1Count(0), IDMap2Count(0) {} /// Compare - test whether the two functions have equivalent behaviour. @@ -144,9 +140,9 @@ bool isEquivalentType(const Type *Ty1, const Type *Ty2) const; // The two functions undergoing comparison. - Function *F1, *F2; + const Function *F1, *F2; - TargetData *TD; + const TargetData *TD; typedef DenseMap IDMap; IDMap Map1, Map2; @@ -154,22 +150,6 @@ }; } -/// Compute a hash guaranteed to be equal for two equivalent functions, but -/// very likely to be different for different functions. -static unsigned long ProfileFunction(const Function *F) { - const FunctionType *FTy = F->getFunctionType(); - - FoldingSetNodeID ID; - ID.AddInteger(F->size()); - ID.AddInteger(F->getCallingConv()); - ID.AddBoolean(F->hasGC()); - ID.AddBoolean(FTy->isVarArg()); - ID.AddInteger(FTy->getReturnType()->getTypeID()); - for (unsigned i = 0, e = FTy->getNumParams(); i != e; ++i) - ID.AddInteger(FTy->getParamType(i)->getTypeID()); - return ID.ComputeHash(); -} - /// isEquivalentType - any two pointers in the same address space are /// equivalent. Otherwise, standard type equivalence rules apply. bool FunctionComparator::isEquivalentType(const Type *Ty1, @@ -545,17 +525,8 @@ } /// MergeTwoFunctions - Merge two equivalent functions. Upon completion, -/// FnVec[j] is deleted but not removed from the vector. -void MergeFunctions::MergeTwoFunctions(std::vector &FnVec, - unsigned i, unsigned j) const { - Function *F = FnVec[i]; - Function *G = FnVec[j]; - - if (F->isWeakForLinker() && !G->isWeakForLinker()) { - std::swap(FnVec[i], FnVec[j]); - std::swap(F, G); - } - +/// Function G is deleted. +void MergeFunctions::MergeTwoFunctions(Function *F, Function *G) const { if (F->isWeakForLinker()) { assert(G->isWeakForLinker()); @@ -580,54 +551,88 @@ ++NumFunctionsMerged; } -/// PairwiseCompareAndMerge - Given a list of functions, compare each pair and -/// merge the pairs of equivalent functions. -bool MergeFunctions::PairwiseCompareAndMerge(std::vector &FnVec) { - bool Changed = false; - for (int i = 0, e = FnVec.size(); i != e; ++i) { - for (int j = i + 1; j != e; ++j) { - bool isEqual = FunctionComparator(TD, FnVec[i], FnVec[j]).Compare(); - - DEBUG(dbgs() << " " << FnVec[i]->getName() - << (isEqual ? " == " : " != ") << FnVec[j]->getName() << "\n"); - - if (isEqual) { - MergeTwoFunctions(FnVec, i, j); - Changed = true; - FnVec.erase(FnVec.begin() + j); - --j, --e; - } - } - } - return Changed; -} +static unsigned ProfileFunction(const Function *F) { + const FunctionType *FTy = F->getFunctionType(); -bool MergeFunctions::runOnModule(Module &M) { - bool Changed = false; + FoldingSetNodeID ID; + ID.AddInteger(F->size()); + ID.AddInteger(F->getCallingConv()); + ID.AddBoolean(F->hasGC()); + ID.AddBoolean(FTy->isVarArg()); + ID.AddInteger(FTy->getReturnType()->getTypeID()); + for (unsigned i = 0, e = FTy->getNumParams(); i != e; ++i) + ID.AddInteger(FTy->getParamType(i)->getTypeID()); + return ID.ComputeHash(); +} - std::map > FnMap; +class ComparableFunction { +public: + ComparableFunction(Function *Func, TargetData *TD) + : Func(Func), Hash(ProfileFunction(Func)), TD(TD) {} - for (Module::iterator F = M.begin(), E = M.end(); F != E; ++F) { - if (F->isDeclaration() || F->hasAvailableExternallyLinkage()) - continue; + AssertingVH const Func; + const unsigned Hash; + TargetData * const TD; +}; - FnMap[ProfileFunction(F)].push_back(F); +struct MergeFunctionsEqualityInfo { + static ComparableFunction *getEmptyKey() { + return reinterpret_cast(0); + } + static ComparableFunction *getTombstoneKey() { + return reinterpret_cast(-1); + } + static unsigned getHashValue(const ComparableFunction *CF) { + return CF->Hash; + } + static bool isEqual(const ComparableFunction *LHS, + const ComparableFunction *RHS) { + if (LHS == RHS) + return true; + if (LHS == getEmptyKey() || LHS == getTombstoneKey() || + RHS == getEmptyKey() || RHS == getTombstoneKey()) + return false; + assert(LHS->TD == RHS->TD && "Comparing functions for different targets"); + return FunctionComparator(LHS->TD, LHS->Func, RHS->Func).Compare(); } +}; + +bool MergeFunctions::runOnModule(Module &M) { + bool Changed = false; TD = getAnalysisIfAvailable(); - bool LocalChanged; - do { - LocalChanged = false; - DEBUG(dbgs() << "size: " << FnMap.size() << "\n"); - for (std::map >::iterator - I = FnMap.begin(), E = FnMap.end(); I != E; ++I) { - std::vector &FnVec = I->second; - DEBUG(dbgs() << "hash (" << I->first << "): " << FnVec.size() << "\n"); - LocalChanged |= PairwiseCompareAndMerge(FnVec); + typedef DenseSet FnSetType; + FnSetType FnSet; + for (Module::iterator F = M.begin(), E = M.end(); F != E;) { + if (F->isDeclaration() || F->hasAvailableExternallyLinkage()) { + ++F; + continue; } - Changed |= LocalChanged; - } while (LocalChanged); + ComparableFunction *NewF = new ComparableFunction(F, TD); + ++F; + std::pair Result = FnSet.insert(NewF); + if (!Result.second) { + ComparableFunction *&OldF = *Result.first; + assert(OldF && "Expected a hash collision"); + + // NewF will be deleted in favour of OldF unless NewF is strong and OldF + // is weak in which case swap them to keep the strong definition. + + if (OldF->Func->isWeakForLinker() && !NewF->Func->isWeakForLinker()) + std::swap(OldF, NewF); + + DEBUG(dbgs() << " " << OldF->Func->getName() << " == " + << NewF->Func->getName() << '\n'); + + Changed = true; + Function *DeleteF = NewF->Func; + delete NewF; + MergeTwoFunctions(OldF->Func, DeleteF); + } + } + + DeleteContainerPointers(FnSet); return Changed; } From dpatel at apple.com Tue Aug 31 01:11:28 2010 From: dpatel at apple.com (Devang Patel) Date: Tue, 31 Aug 2010 06:11:28 -0000 Subject: [llvm-commits] [llvm] r112583 - in /llvm/trunk/lib/CodeGen/AsmPrinter: DwarfDebug.cpp DwarfDebug.h Message-ID: <20100831061128.B1D842A6C12C@llvm.org> Author: dpatel Date: Tue Aug 31 01:11:28 2010 New Revision: 112583 URL: http://llvm.org/viewvc/llvm-project?rev=112583&view=rev Log: Simplify. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=112583&r1=112582&r2=112583&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Tue Aug 31 01:11:28 2010 @@ -583,10 +583,15 @@ addUInt(Die, dwarf::DW_AT_decl_line, 0, Line); } -/// addVariableAddress - Add DW_AT_location attribute for a DbgVariable. -void DwarfDebug::addVariableAddress(DbgVariable *&DV, DIE *Die, - unsigned Attribute, - const MachineLocation &Location) { +/// addVariableAddress - Add DW_AT_location attribute for a DbgVariable based +/// on provided frame index. +void DwarfDebug::addVariableAddress(DbgVariable *&DV, DIE *Die, int64_t FI) { + MachineLocation Location; + unsigned FrameReg; + const TargetRegisterInfo *RI = Asm->TM.getRegisterInfo(); + int Offset = RI->getFrameIndexReference(*Asm->MF, FI, FrameReg); + Location.set(FrameReg, Offset); + if (DV->variableHasComplexAddress()) addComplexAddress(DV, Die, dwarf::DW_AT_location, Location); else if (DV->isBlockByrefVariable()) @@ -1653,15 +1658,10 @@ } // .. else use frame index, if available. - MachineLocation Location; - unsigned FrameReg; - const TargetRegisterInfo *RI = Asm->TM.getRegisterInfo(); int FI = 0; - if (findVariableFrameIndex(DV, &FI)) { - int Offset = RI->getFrameIndexReference(*Asm->MF, FI, FrameReg); - Location.set(FrameReg, Offset); - addVariableAddress(DV, VariableDie, dwarf::DW_AT_location, Location); - } + if (findVariableFrameIndex(DV, &FI)) + addVariableAddress(DV, VariableDie, FI); + DV->setDIE(VariableDie); return VariableDie; Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h?rev=112583&r1=112582&r2=112583&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Tue Aug 31 01:11:28 2010 @@ -375,9 +375,9 @@ void addBlockByrefAddress(DbgVariable *&DV, DIE *Die, unsigned Attribute, const MachineLocation &Location); - /// addVariableAddress - Add DW_AT_location attribute for a DbgVariable. - void addVariableAddress(DbgVariable *&DV, DIE *Die, unsigned Attribute, - const MachineLocation &Location); + /// addVariableAddress - Add DW_AT_location attribute for a DbgVariable based + /// on provided frame index. + void addVariableAddress(DbgVariable *&DV, DIE *Die, int64_t FI); /// addToContextOwner - Add Die into the list of its context owner's children. void addToContextOwner(DIE *Die, DIDescriptor Context); From dpatel at apple.com Tue Aug 31 01:12:08 2010 From: dpatel at apple.com (Devang Patel) Date: Tue, 31 Aug 2010 06:12:08 -0000 Subject: [llvm-commits] [llvm] r112584 - in /llvm/trunk/lib/CodeGen/SelectionDAG: SelectionDAGBuilder.cpp SelectionDAGBuilder.h Message-ID: <20100831061208.9CBEE2A6C12C@llvm.org> Author: dpatel Date: Tue Aug 31 01:12:08 2010 New Revision: 112584 URL: http://llvm.org/viewvc/llvm-project?rev=112584&view=rev Log: Offset is not always unsigned number. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=112584&r1=112583&r2=112584&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Tue Aug 31 01:12:08 2010 @@ -3915,7 +3915,7 @@ /// At the end of instruction selection, they will be inserted to the entry BB. bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, - uint64_t Offset, + int64_t Offset, const SDValue &N) { if (!isa(V)) return false; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h?rev=112584&r1=112583&r2=112584&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h Tue Aug 31 01:12:08 2010 @@ -529,7 +529,7 @@ /// corresponding DBG_VALUE machine instruction for it now. At the end of /// instruction selection, they will be inserted to the entry BB. bool EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, - uint64_t Offset, const SDValue &N); + int64_t Offset, const SDValue &N); }; } // end namespace llvm From baldrick at free.fr Tue Aug 31 01:31:53 2010 From: baldrick at free.fr (Duncan Sands) Date: Tue, 31 Aug 2010 08:31:53 +0200 Subject: [llvm-commits] [llvm-gcc-4.2] r112522 - /llvm-gcc-4.2/trunk/gcc/gcc.c In-Reply-To: <20100830205259.4311B2A6C12C@llvm.org> References: <20100830205259.4311B2A6C12C@llvm.org> Message-ID: <4C7CA1D9.7000307@free.fr> Hi Rafael, > Pass -plugin-opt=as-arg=--32 and -plugin-opt=as-arg=--64 if -m32 or -m64 is > passed to gcc. how is this issue handled in gcc mainline? Ciao, Duncan. From baldrick at free.fr Tue Aug 31 01:34:15 2010 From: baldrick at free.fr (Duncan Sands) Date: Tue, 31 Aug 2010 08:34:15 +0200 Subject: [llvm-commits] [llvm-gcc-4.2] r112531 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp In-Reply-To: <20100830214050.BD6D92A6C12C@llvm.org> References: <20100830214050.BD6D92A6C12C@llvm.org> Message-ID: <4C7CA267.7030907@free.fr> Hi Stuart, > Fix an assertion in the GCC DejaGNU testsuite. Radar 8251350. which gcc testcase are you referring to? Thanks, Duncan. From bigcheesegs at gmail.com Tue Aug 31 01:36:22 2010 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Tue, 31 Aug 2010 06:36:22 -0000 Subject: [llvm-commits] [llvm] r112585 - /llvm/trunk/include/llvm/System/Path.h Message-ID: <20100831063622.65A7E2A6C12C@llvm.org> Author: mspencer Date: Tue Aug 31 01:36:22 2010 New Revision: 112585 URL: http://llvm.org/viewvc/llvm-project?rev=112585&view=rev Log: Fix spelling/typo. Modified: llvm/trunk/include/llvm/System/Path.h Modified: llvm/trunk/include/llvm/System/Path.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/System/Path.h?rev=112585&r1=112584&r2=112585&view=diff ============================================================================== --- llvm/trunk/include/llvm/System/Path.h (original) +++ llvm/trunk/include/llvm/System/Path.h Tue Aug 31 01:36:22 2010 @@ -336,9 +336,9 @@ /// native Dynamic Library (shared library, shared object) by looking at /// the file's magic number. The Path object must reference a file, not a /// directory. - /// @return strue if the file starts with the magid number for a native + /// @returns true if the file starts with the magic number for a native /// shared library. - /// @brief Determine if the path reference a dynamic library. + /// @brief Determine if the path references a dynamic library. bool isDynamicLibrary() const; /// This function determines if the path name references an existing file From bigcheesegs at gmail.com Tue Aug 31 01:36:33 2010 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Tue, 31 Aug 2010 06:36:33 -0000 Subject: [llvm-commits] [llvm] r112586 - /llvm/trunk/lib/System/Win32/Path.inc Message-ID: <20100831063633.BCF832A6C12C@llvm.org> Author: mspencer Date: Tue Aug 31 01:36:33 2010 New Revision: 112586 URL: http://llvm.org/viewvc/llvm-project?rev=112586&view=rev Log: System: Fix getMagicNumber on windows. getMagicNumber was treating the _binary_ data it read in as a null terminated string. This resulted in the std::string calculating the length, and causing an assert in other code that assumed that the length it passed was the same as the length of the string it would get back. Modified: llvm/trunk/lib/System/Win32/Path.inc Modified: llvm/trunk/lib/System/Win32/Path.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Win32/Path.inc?rev=112586&r1=112585&r2=112586&view=diff ============================================================================== --- llvm/trunk/lib/System/Win32/Path.inc (original) +++ llvm/trunk/lib/System/Win32/Path.inc Tue Aug 31 01:36:33 2010 @@ -722,7 +722,7 @@ bool Path::getMagicNumber(std::string& Magic, unsigned len) const { assert(len < 1024 && "Request for magic string too long"); - char* buf = (char*) alloca(1 + len); + char* buf = reinterpret_cast(alloca(len)); HANDLE h = CreateFile(path.c_str(), GENERIC_READ, @@ -741,8 +741,7 @@ if (!ret || nRead != len) return false; - buf[len] = '\0'; - Magic = buf; + Magic = std::string(buf, len); return true; } From bigcheesegs at gmail.com Tue Aug 31 01:36:46 2010 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Tue, 31 Aug 2010 06:36:46 -0000 Subject: [llvm-commits] [llvm] r112587 - in /llvm/trunk: lib/System/Path.cpp tools/llvm-nm/llvm-nm.cpp Message-ID: <20100831063646.4C0D92A6C12C@llvm.org> Author: mspencer Date: Tue Aug 31 01:36:46 2010 New Revision: 112587 URL: http://llvm.org/viewvc/llvm-project?rev=112587&view=rev Log: Cleanup Whitespace. Modified: llvm/trunk/lib/System/Path.cpp llvm/trunk/tools/llvm-nm/llvm-nm.cpp Modified: llvm/trunk/lib/System/Path.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Path.cpp?rev=112587&r1=112586&r2=112587&view=diff ============================================================================== --- llvm/trunk/lib/System/Path.cpp (original) +++ llvm/trunk/lib/System/Path.cpp Tue Aug 31 01:36:46 2010 @@ -61,7 +61,7 @@ if (memcmp(magic,"!\n",8) == 0) return Archive_FileType; break; - + case '\177': if (magic[1] == 'E' && magic[2] == 'L' && magic[3] == 'F') { if (length >= 18 && magic[17] == 0) @@ -76,11 +76,11 @@ break; case 0xCA: - if (magic[1] == char(0xFE) && magic[2] == char(0xBA) && + if (magic[1] == char(0xFE) && magic[2] == char(0xBA) && magic[3] == char(0xBE)) { - // This is complicated by an overlap with Java class files. + // This is complicated by an overlap with Java class files. // See the Mach-O section in /usr/share/file/magic for details. - if (length >= 8 && magic[7] < 43) + if (length >= 8 && magic[7] < 43) // FIXME: Universal Binary of any type. return Mach_O_DynamicallyLinkedSharedLib_FileType; } @@ -89,18 +89,18 @@ case 0xFE: case 0xCE: { uint16_t type = 0; - if (magic[0] == char(0xFE) && magic[1] == char(0xED) && + if (magic[0] == char(0xFE) && magic[1] == char(0xED) && magic[2] == char(0xFA) && magic[3] == char(0xCE)) { /* Native endian */ if (length >= 16) type = magic[14] << 8 | magic[15]; - } else if (magic[0] == char(0xCE) && magic[1] == char(0xFA) && + } else if (magic[0] == char(0xCE) && magic[1] == char(0xFA) && magic[2] == char(0xED) && magic[3] == char(0xFE)) { /* Reverse endian */ if (length >= 14) type = magic[13] << 8 | magic[12]; } switch (type) { - default: break; - case 1: return Mach_O_Object_FileType; + default: break; + case 1: return Mach_O_Object_FileType; case 2: return Mach_O_Executable_FileType; case 3: return Mach_O_FixedVirtualMemorySharedLib_FileType; case 4: return Mach_O_Core_FileType; @@ -219,38 +219,38 @@ "Sep must be a 1-character string literal."); if (path.empty()) return "."; - + // If the path is all slashes, return a single slash. // Otherwise, remove all trailing slashes. - + signed pos = static_cast(path.size()) - 1; - + while (pos >= 0 && path[pos] == Sep[0]) --pos; - + if (pos < 0) return path[0] == Sep[0] ? Sep : "."; - + // Any slashes left? signed i = 0; - + while (i < pos && path[i] != Sep[0]) ++i; - + if (i == pos) // No slashes? Return "." return "."; - - // There is at least one slash left. Remove all trailing non-slashes. + + // There is at least one slash left. Remove all trailing non-slashes. while (pos >= 0 && path[pos] != Sep[0]) --pos; - + // Remove any trailing slashes. while (pos >= 0 && path[pos] == Sep[0]) --pos; - + if (pos < 0) return path[0] == Sep[0] ? Sep : "."; - + return path.substr(0, pos+1); } Modified: llvm/trunk/tools/llvm-nm/llvm-nm.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-nm/llvm-nm.cpp?rev=112587&r1=112586&r2=112587&view=diff ============================================================================== --- llvm/trunk/tools/llvm-nm/llvm-nm.cpp (original) +++ llvm/trunk/tools/llvm-nm/llvm-nm.cpp Tue Aug 31 01:36:46 2010 @@ -94,7 +94,7 @@ GV.hasLinkerPrivateWeakDefAutoLinkage() || GV.hasAvailableExternallyLinkage()) return; - + const std::string SymbolAddrStr = " "; // Not used yet... char TypeChar = TypeCharForSymbol(GV); if ((TypeChar != 'U') && UndefinedOnly) @@ -148,13 +148,13 @@ Module *Result = 0; if (Buffer.get()) Result = ParseBitcodeFile(Buffer.get(), Context, &ErrorMessage); - + if (Result) { DumpSymbolNamesFromModule(Result); delete Result; } else errs() << ToolName << ": " << Filename << ": " << ErrorMessage << "\n"; - + } else if (aPath.isArchive()) { std::string ErrMsg; Archive* archive = Archive::OpenAndLoad(sys::Path(Filename), Context, @@ -179,7 +179,7 @@ // Print a stack trace if we signal out. sys::PrintStackTraceOnErrorSignal(); PrettyStackTraceProgram X(argc, argv); - + llvm_shutdown_obj Y; // Call llvm_shutdown() on exit. cl::ParseCommandLineOptions(argc, argv, "llvm symbol table dumper\n"); From resistor at mac.com Tue Aug 31 02:36:35 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 31 Aug 2010 07:36:35 -0000 Subject: [llvm-commits] [llvm] r112589 - in /llvm/trunk: lib/Transforms/Scalar/JumpThreading.cpp test/Transforms/JumpThreading/2010-08-31-InfiniteRecursion.ll Message-ID: <20100831073635.272B62A6C12D@llvm.org> Author: resistor Date: Tue Aug 31 02:36:34 2010 New Revision: 112589 URL: http://llvm.org/viewvc/llvm-project?rev=112589&view=rev Log: More Chris-inspired JumpThreading fixes: use ConstantExpr to correctly constant-fold undef, and be more careful with its return value. This actually exposed an infinite recursion bug in ComputeValueKnownInPredecessors which theoretically already existed (in JumpThreading's handling of and/or of i1's), but never manifested before. This patch adds a tracking set to prevent this case. Added: llvm/trunk/test/Transforms/JumpThreading/2010-08-31-InfiniteRecursion.ll Modified: llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Modified: llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp?rev=112589&r1=112588&r2=112589&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Tue Aug 31 02:36:34 2010 @@ -16,7 +16,6 @@ #include "llvm/IntrinsicInst.h" #include "llvm/LLVMContext.h" #include "llvm/Pass.h" -#include "llvm/Analysis/ConstantFolding.h" #include "llvm/Analysis/InstructionSimplify.h" #include "llvm/Analysis/LazyValueInfo.h" #include "llvm/Analysis/Loads.h" @@ -25,6 +24,7 @@ #include "llvm/Transforms/Utils/SSAUpdater.h" #include "llvm/Target/TargetData.h" #include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/DenseSet.h" #include "llvm/ADT/Statistic.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallPtrSet.h" @@ -78,6 +78,7 @@ #else SmallSet, 16> LoopHeaders; #endif + DenseSet > RecursionSet; public: static char ID; // Pass identification JumpThreading() : FunctionPass(ID) {} @@ -270,12 +271,17 @@ /// bool JumpThreading:: ComputeValueKnownInPredecessors(Value *V, BasicBlock *BB,PredValueInfo &Result){ + if (!RecursionSet.insert(std::make_pair(V, BB)).second) + return false; + // If V is a constantint, then it is known in all predecessors. if (isa(V) || isa(V)) { ConstantInt *CI = dyn_cast(V); for (pred_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI) Result.push_back(std::make_pair(CI, *PI)); + + RecursionSet.erase(std::make_pair(V, BB)); return true; } @@ -310,9 +316,11 @@ Result.push_back(std::make_pair(dyn_cast(PredCst), P)); } + RecursionSet.erase(std::make_pair(V, BB)); return !Result.empty(); } + RecursionSet.erase(std::make_pair(V, BB)); return false; } @@ -328,10 +336,15 @@ PN->getIncomingBlock(i), BB); // LVI returns null is no value could be determined. if (!CI) continue; - ConstantInt *CInt = dyn_cast(CI); - Result.push_back(std::make_pair(CInt, PN->getIncomingBlock(i))); + if (ConstantInt *CInt = dyn_cast(CI)) + Result.push_back(std::make_pair(CInt, PN->getIncomingBlock(i))); + else if (isa(CI)) + Result.push_back(std::make_pair((ConstantInt*)0, + PN->getIncomingBlock(i))); } } + + RecursionSet.erase(std::make_pair(V, BB)); return !Result.empty(); } @@ -346,8 +359,10 @@ ComputeValueKnownInPredecessors(I->getOperand(0), BB, LHSVals); ComputeValueKnownInPredecessors(I->getOperand(1), BB, RHSVals); - if (LHSVals.empty() && RHSVals.empty()) + if (LHSVals.empty() && RHSVals.empty()) { + RecursionSet.erase(std::make_pair(V, BB)); return false; + } ConstantInt *InterestingVal; if (I->getOpcode() == Instruction::Or) @@ -374,6 +389,8 @@ Result.back().first = InterestingVal; } } + + RecursionSet.erase(std::make_pair(V, BB)); return !Result.empty(); } @@ -382,38 +399,48 @@ isa(I->getOperand(1)) && cast(I->getOperand(1))->isOne()) { ComputeValueKnownInPredecessors(I->getOperand(0), BB, Result); - if (Result.empty()) + if (Result.empty()) { + RecursionSet.erase(std::make_pair(V, BB)); return false; + } // Invert the known values. for (unsigned i = 0, e = Result.size(); i != e; ++i) if (Result[i].first) Result[i].first = cast(ConstantExpr::getNot(Result[i].first)); + + RecursionSet.erase(std::make_pair(V, BB)); return true; } // Try to simplify some other binary operator values. } else if (BinaryOperator *BO = dyn_cast(I)) { - // AND or OR of a value with itself is that value. ConstantInt *CI = dyn_cast(BO->getOperand(1)); - if (CI && (BO->getOpcode() == Instruction::And || - BO->getOpcode() == Instruction::Or)) { + if (CI) { SmallVector, 8> LHSVals; ComputeValueKnownInPredecessors(BO->getOperand(0), BB, LHSVals); - for (unsigned i = 0, e = LHSVals.size(); i != e; ++i) + + // Try to use constant folding to simplify the binary operator. + for (unsigned i = 0, e = LHSVals.size(); i != e; ++i) { + Constant *Folded = 0; if (LHSVals[i].first == 0) { - ConstantInt *Zero = - cast(ConstantInt::get(BO->getType(), 0)); - Result.push_back(std::make_pair(Zero, LHSVals[i].second)); - } else if (Constant *Folded = ConstantExpr::get(BO->getOpcode(), - LHSVals[i].first, CI)) { - Result.push_back(std::make_pair(cast(Folded), - LHSVals[i].second)); + Folded = ConstantExpr::get(BO->getOpcode(), + UndefValue::get(BO->getType()), + CI); + } else { + Folded = ConstantExpr::get(BO->getOpcode(), LHSVals[i].first, CI); } - - return !Result.empty(); + + if (ConstantInt *FoldedCInt = dyn_cast(Folded)) + Result.push_back(std::make_pair(FoldedCInt, LHSVals[i].second)); + else if (isa(Folded)) + Result.push_back(std::make_pair((ConstantInt*)0, LHSVals[i].second)); + } } + + RecursionSet.erase(std::make_pair(V, BB)); + return !Result.empty(); } // Handle compare with phi operand, where the PHI is defined in this block. @@ -446,6 +473,7 @@ Result.push_back(std::make_pair(CI, PredBB)); } + RecursionSet.erase(std::make_pair(V, BB)); return !Result.empty(); } @@ -472,25 +500,32 @@ Result.push_back(std::make_pair(cast(ResC), P)); } + RecursionSet.erase(std::make_pair(V, BB)); return !Result.empty(); } - // Try to find a constant value for the LHS of an equality comparison, + // Try to find a constant value for the LHS of a comparison, // and evaluate it statically if we can. if (Constant *CmpConst = dyn_cast(Cmp->getOperand(1))) { SmallVector, 8> LHSVals; ComputeValueKnownInPredecessors(I->getOperand(0), BB, LHSVals); for (unsigned i = 0, e = LHSVals.size(); i != e; ++i) { + Constant * Folded = 0; if (LHSVals[i].first == 0) - Result.push_back(std::make_pair((ConstantInt*)0, - LHSVals[i].second)); - else if (Constant *Folded = ConstantExpr::getCompare( - Cmp->getPredicate(), LHSVals[i].first, CmpConst)) - Result.push_back(std::make_pair(cast(Folded), - LHSVals[i].second)); + Folded = ConstantExpr::getCompare(Cmp->getPredicate(), + UndefValue::get(CmpConst->getType()), CmpConst); + else + Folded = ConstantExpr::getCompare(Cmp->getPredicate(), + LHSVals[i].first, CmpConst); + + if (ConstantInt *FoldedCInt = dyn_cast(Folded)) + Result.push_back(std::make_pair(FoldedCInt, LHSVals[i].second)); + else if (isa(Folded)) + Result.push_back(std::make_pair((ConstantInt*)0,LHSVals[i].second)); } + RecursionSet.erase(std::make_pair(V, BB)); return !Result.empty(); } } @@ -505,9 +540,11 @@ Result.push_back(std::make_pair(CInt, *PI)); } + RecursionSet.erase(std::make_pair(V, BB)); return !Result.empty(); } + RecursionSet.erase(std::make_pair(V, BB)); return false; } @@ -1126,8 +1163,9 @@ return false; SmallVector, 8> PredValues; - if (!ComputeValueKnownInPredecessors(Cond, BB, PredValues)) + if (!ComputeValueKnownInPredecessors(Cond, BB, PredValues)) { return false; + } assert(!PredValues.empty() && "ComputeValueKnownInPredecessors returned true with no values"); Added: llvm/trunk/test/Transforms/JumpThreading/2010-08-31-InfiniteRecursion.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/JumpThreading/2010-08-31-InfiniteRecursion.ll?rev=112589&view=auto ============================================================================== --- llvm/trunk/test/Transforms/JumpThreading/2010-08-31-InfiniteRecursion.ll (added) +++ llvm/trunk/test/Transforms/JumpThreading/2010-08-31-InfiniteRecursion.ll Tue Aug 31 02:36:34 2010 @@ -0,0 +1,91 @@ +; RUN: opt < %s -jump-threading -disable-output +; ModuleID = 'bugpoint-reduced-simplified.bc' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.4" + +define void @encode_one_macroblock_highfast() nounwind ssp { +entry: + switch i32 undef, label %bb13 [ + i32 1, label %bb10 + i32 2, label %bb12 + ] + +bb10: ; preds = %entry + unreachable + +bb12: ; preds = %entry + unreachable + +bb13: ; preds = %entry + br i1 undef, label %bb137, label %bb292 + +bb137: ; preds = %bb13 + br i1 undef, label %bb150, label %bb154 + +bb150: ; preds = %bb137 + unreachable + +bb154: ; preds = %bb137 + br i1 undef, label %bb292, label %bb246 + +bb246: ; preds = %bb154 + br i1 undef, label %bb292, label %bb247 + +bb247: ; preds = %bb246 + br i1 undef, label %bb248, label %bb292 + +bb248: ; preds = %bb247 + br i1 undef, label %bb249, label %bb292 + +bb249: ; preds = %bb248 + br i1 undef, label %bb254, label %bb250 + +bb250: ; preds = %bb249 + unreachable + +bb254: ; preds = %bb249 + br i1 undef, label %bb292, label %bb255 + +bb255: ; preds = %bb288.bb289.loopexit_crit_edge, %bb254 + br i1 undef, label %bb.nph.split.us, label %bb269 + +bb.nph.split.us: ; preds = %bb255 + br i1 undef, label %bb.nph.split.us.split.us, label %bb269.us.us31 + +bb.nph.split.us.split.us: ; preds = %bb.nph.split.us + br i1 undef, label %bb269.us.us, label %bb269.us.us.us + +bb269.us.us.us: ; preds = %bb287.us.us.us, %bb.nph.split.us.split.us + %indvar = phi i64 [ %indvar.next, %bb287.us.us.us ], [ 0, %bb.nph.split.us.split.us ] ; [#uses=1] + %0 = icmp eq i16 undef, 0 ; [#uses=1] + br i1 %0, label %bb287.us.us.us, label %bb286.us.us.us + +bb287.us.us.us: ; preds = %bb269.us.us.us + %indvar.next = add i64 %indvar, 1 ; [#uses=2] + %exitcond = icmp eq i64 %indvar.next, 4 ; [#uses=1] + br i1 %exitcond, label %bb288.bb289.loopexit_crit_edge, label %bb269.us.us.us + +bb286.us.us.us: ; preds = %bb269.us.us.us + unreachable + +bb269.us.us: ; preds = %bb287.us.us, %bb.nph.split.us.split.us + br i1 undef, label %bb287.us.us, label %bb286.us.us + +bb287.us.us: ; preds = %bb269.us.us + br i1 undef, label %bb288.bb289.loopexit_crit_edge, label %bb269.us.us + +bb286.us.us: ; preds = %bb269.us.us + unreachable + +bb269.us.us31: ; preds = %bb.nph.split.us + unreachable + +bb269: ; preds = %bb255 + unreachable + +bb288.bb289.loopexit_crit_edge: ; preds = %bb287.us.us, %bb287.us.us.us + br i1 undef, label %bb292, label %bb255 + +bb292: ; preds = %bb288.bb289.loopexit_crit_edge, %bb254, %bb248, %bb247, %bb246, %bb154, %bb13 + unreachable +} From resistor at mac.com Tue Aug 31 02:41:39 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 31 Aug 2010 07:41:39 -0000 Subject: [llvm-commits] [llvm] r112590 - in /llvm/trunk/lib/Transforms/Scalar: CMakeLists.txt CorrelatedValuePropagation.cpp ValuePropagation.cpp Message-ID: <20100831074139.579372A6C12D@llvm.org> Author: resistor Date: Tue Aug 31 02:41:39 2010 New Revision: 112590 URL: http://llvm.org/viewvc/llvm-project?rev=112590&view=rev Log: Rename file to something more descriptive. Added: llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp - copied unchanged from r112587, llvm/trunk/lib/Transforms/Scalar/ValuePropagation.cpp Removed: llvm/trunk/lib/Transforms/Scalar/ValuePropagation.cpp Modified: llvm/trunk/lib/Transforms/Scalar/CMakeLists.txt Modified: llvm/trunk/lib/Transforms/Scalar/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CMakeLists.txt?rev=112590&r1=112589&r2=112590&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/CMakeLists.txt (original) +++ llvm/trunk/lib/Transforms/Scalar/CMakeLists.txt Tue Aug 31 02:41:39 2010 @@ -3,6 +3,7 @@ BasicBlockPlacement.cpp CodeGenPrepare.cpp ConstantProp.cpp + CorrelatedValuePropagation.cpp DCE.cpp DeadStoreElimination.cpp GEPSplitter.cpp @@ -29,7 +30,6 @@ Sink.cpp TailDuplication.cpp TailRecursionElimination.cpp - ValuePropagation.cpp ) target_link_libraries (LLVMScalarOpts LLVMTransformUtils) Removed: llvm/trunk/lib/Transforms/Scalar/ValuePropagation.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ValuePropagation.cpp?rev=112589&view=auto ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ValuePropagation.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ValuePropagation.cpp (removed) @@ -1,119 +0,0 @@ -//===- ValuePropagation.cpp - Propagate information derived control flow --===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file implements the Value Propagation pass. -// -//===----------------------------------------------------------------------===// - -#define DEBUG_TYPE "value-propagation" -#include "llvm/Transforms/Scalar.h" -#include "llvm/Function.h" -#include "llvm/Instructions.h" -#include "llvm/Pass.h" -#include "llvm/Analysis/LazyValueInfo.h" -#include "llvm/Transforms/Utils/Local.h" -#include "llvm/ADT/Statistic.h" -using namespace llvm; - -STATISTIC(NumPhis, "Number of phis propagated"); -STATISTIC(NumSelects, "Number of selects propagated"); - -namespace { - class ValuePropagation : public FunctionPass { - LazyValueInfo *LVI; - - bool processSelect(SelectInst *SI); - bool processPHI(PHINode *P); - - public: - static char ID; - ValuePropagation(): FunctionPass(ID) { } - - bool runOnFunction(Function &F); - - virtual void getAnalysisUsage(AnalysisUsage &AU) const { - AU.addRequired(); - } - }; -} - -char ValuePropagation::ID = 0; -INITIALIZE_PASS(ValuePropagation, "value-propagation", - "Value Propagation", false, false); - -// Public interface to the Value Propagation pass -Pass *llvm::createValuePropagationPass() { - return new ValuePropagation(); -} - -bool ValuePropagation::processSelect(SelectInst *S) { - if (S->getType()->isVectorTy()) return false; - - Constant *C = LVI->getConstant(S->getOperand(0), S->getParent()); - if (!C) return false; - - ConstantInt *CI = dyn_cast(C); - if (!CI) return false; - - S->replaceAllUsesWith(S->getOperand(CI->isOne() ? 1 : 2)); - S->eraseFromParent(); - - ++NumSelects; - - return true; -} - -bool ValuePropagation::processPHI(PHINode *P) { - bool Changed = false; - - BasicBlock *BB = P->getParent(); - for (unsigned i = 0, e = P->getNumIncomingValues(); i < e; ++i) { - Value *Incoming = P->getIncomingValue(i); - if (isa(Incoming)) continue; - - Constant *C = LVI->getConstantOnEdge(P->getIncomingValue(i), - P->getIncomingBlock(i), - BB); - if (!C) continue; - - P->setIncomingValue(i, C); - Changed = true; - } - - if (Value *ConstVal = P->hasConstantValue()) { - P->replaceAllUsesWith(ConstVal); - P->eraseFromParent(); - Changed = true; - } - - ++NumPhis; - - return Changed; -} - -bool ValuePropagation::runOnFunction(Function &F) { - LVI = &getAnalysis(); - - bool Changed = false; - - for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI) - for (BasicBlock::iterator BI = FI->begin(), BE = FI->end(); BI != BE; ) { - Instruction *II = BI++; - if (SelectInst *SI = dyn_cast(II)) - Changed |= processSelect(SI); - else if (PHINode *P = dyn_cast(II)) - Changed |= processPHI(P); - } - - if (Changed) - for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI) - SimplifyInstructionsInBlock(FI); - - return Changed; -} From resistor at mac.com Tue Aug 31 02:48:34 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 31 Aug 2010 07:48:34 -0000 Subject: [llvm-commits] [llvm] r112591 - in /llvm/trunk: include/llvm/LinkAllPasses.h include/llvm/Transforms/Scalar.h lib/Transforms/Scalar/CorrelatedValuePropagation.cpp test/Transforms/ValuePropagation/basic.ll Message-ID: <20100831074834.82A7C2A6C12D@llvm.org> Author: resistor Date: Tue Aug 31 02:48:34 2010 New Revision: 112591 URL: http://llvm.org/viewvc/llvm-project?rev=112591&view=rev Log: Rename ValuePropagation to a more descriptive CorrelatedValuePropagation. Modified: llvm/trunk/include/llvm/LinkAllPasses.h llvm/trunk/include/llvm/Transforms/Scalar.h llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp llvm/trunk/test/Transforms/ValuePropagation/basic.ll Modified: llvm/trunk/include/llvm/LinkAllPasses.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/LinkAllPasses.h?rev=112591&r1=112590&r2=112591&view=diff ============================================================================== --- llvm/trunk/include/llvm/LinkAllPasses.h (original) +++ llvm/trunk/include/llvm/LinkAllPasses.h Tue Aug 31 02:48:34 2010 @@ -146,7 +146,7 @@ (void) llvm::createLintPass(); (void) llvm::createSinkingPass(); (void) llvm::createLowerAtomicPass(); - (void) llvm::createValuePropagationPass(); + (void) llvm::createCorrelatedValuePropagationPass(); (void)new llvm::IntervalPartition(); (void)new llvm::FindUsedTypes(); Modified: llvm/trunk/include/llvm/Transforms/Scalar.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/Scalar.h?rev=112591&r1=112590&r2=112591&view=diff ============================================================================== --- llvm/trunk/include/llvm/Transforms/Scalar.h (original) +++ llvm/trunk/include/llvm/Transforms/Scalar.h Tue Aug 31 02:48:34 2010 @@ -327,7 +327,7 @@ // // ValuePropagation - Propagate CFG-derived value information // -Pass *createValuePropagationPass(); +Pass *createCorrelatedValuePropagationPass(); } // End llvm namespace Modified: llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp?rev=112591&r1=112590&r2=112591&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp Tue Aug 31 02:48:34 2010 @@ -1,4 +1,4 @@ -//===- ValuePropagation.cpp - Propagate information derived control flow --===// +//===- CorrelatedValuePropagation.cpp - Propagate CFG-derived info --------===// // // The LLVM Compiler Infrastructure // @@ -7,11 +7,11 @@ // //===----------------------------------------------------------------------===// // -// This file implements the Value Propagation pass. +// This file implements the Correlated Value Propagation pass. // //===----------------------------------------------------------------------===// -#define DEBUG_TYPE "value-propagation" +#define DEBUG_TYPE "correlated-value-propagation" #include "llvm/Transforms/Scalar.h" #include "llvm/Function.h" #include "llvm/Instructions.h" @@ -25,7 +25,7 @@ STATISTIC(NumSelects, "Number of selects propagated"); namespace { - class ValuePropagation : public FunctionPass { + class CorrelatedValuePropagation : public FunctionPass { LazyValueInfo *LVI; bool processSelect(SelectInst *SI); @@ -33,7 +33,7 @@ public: static char ID; - ValuePropagation(): FunctionPass(ID) { } + CorrelatedValuePropagation(): FunctionPass(ID) { } bool runOnFunction(Function &F); @@ -43,16 +43,16 @@ }; } -char ValuePropagation::ID = 0; -INITIALIZE_PASS(ValuePropagation, "value-propagation", +char CorrelatedValuePropagation::ID = 0; +INITIALIZE_PASS(CorrelatedValuePropagation, "correlated-propagation", "Value Propagation", false, false); // Public interface to the Value Propagation pass -Pass *llvm::createValuePropagationPass() { - return new ValuePropagation(); +Pass *llvm::createCorrelatedValuePropagationPass() { + return new CorrelatedValuePropagation(); } -bool ValuePropagation::processSelect(SelectInst *S) { +bool CorrelatedValuePropagation::processSelect(SelectInst *S) { if (S->getType()->isVectorTy()) return false; Constant *C = LVI->getConstant(S->getOperand(0), S->getParent()); @@ -69,7 +69,7 @@ return true; } -bool ValuePropagation::processPHI(PHINode *P) { +bool CorrelatedValuePropagation::processPHI(PHINode *P) { bool Changed = false; BasicBlock *BB = P->getParent(); @@ -97,7 +97,7 @@ return Changed; } -bool ValuePropagation::runOnFunction(Function &F) { +bool CorrelatedValuePropagation::runOnFunction(Function &F) { LVI = &getAnalysis(); bool Changed = false; Modified: llvm/trunk/test/Transforms/ValuePropagation/basic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ValuePropagation/basic.ll?rev=112591&r1=112590&r2=112591&view=diff ============================================================================== --- llvm/trunk/test/Transforms/ValuePropagation/basic.ll (original) +++ llvm/trunk/test/Transforms/ValuePropagation/basic.ll Tue Aug 31 02:48:34 2010 @@ -1,4 +1,4 @@ -; RUN: opt < %s -value-propagation -S | FileCheck %s +; RUN: opt < %s -correlated-propagation -S | FileCheck %s ; PR2581 ; CHECK: @test1 From resistor at mac.com Tue Aug 31 02:50:31 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 31 Aug 2010 07:50:31 -0000 Subject: [llvm-commits] [llvm] r112592 - in /llvm/trunk/test/Transforms: CorrelatedValuePropagation/ ValuePropagation/ Message-ID: <20100831075031.DFA352A6C12D@llvm.org> Author: resistor Date: Tue Aug 31 02:50:31 2010 New Revision: 112592 URL: http://llvm.org/viewvc/llvm-project?rev=112592&view=rev Log: Rename test directory to reflect new pass name. Added: llvm/trunk/test/Transforms/CorrelatedValuePropagation/ - copied from r112591, llvm/trunk/test/Transforms/ValuePropagation/ Removed: llvm/trunk/test/Transforms/ValuePropagation/ From isanbard at gmail.com Tue Aug 31 02:50:46 2010 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 31 Aug 2010 07:50:46 -0000 Subject: [llvm-commits] [llvm] r112593 - /llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Message-ID: <20100831075046.458272A6C12D@llvm.org> Author: void Date: Tue Aug 31 02:50:46 2010 New Revision: 112593 URL: http://llvm.org/viewvc/llvm-project?rev=112593&view=rev Log: - Cleanup some whitespaces. - Convert {0,1} and friends into 0b01, which is identical and more consistent. Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=112593&r1=112592&r2=112593&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Aug 31 02:50:46 2010 @@ -88,21 +88,21 @@ class AddrMode val> { bits<4> Value = val; } -def AddrModeNone : AddrMode<0>; -def AddrMode1 : AddrMode<1>; -def AddrMode2 : AddrMode<2>; -def AddrMode3 : AddrMode<3>; -def AddrMode4 : AddrMode<4>; -def AddrMode5 : AddrMode<5>; -def AddrMode6 : AddrMode<6>; -def AddrModeT1_1 : AddrMode<7>; -def AddrModeT1_2 : AddrMode<8>; -def AddrModeT1_4 : AddrMode<9>; -def AddrModeT1_s : AddrMode<10>; -def AddrModeT2_i12: AddrMode<11>; -def AddrModeT2_i8 : AddrMode<12>; -def AddrModeT2_so : AddrMode<13>; -def AddrModeT2_pc : AddrMode<14>; +def AddrModeNone : AddrMode<0>; +def AddrMode1 : AddrMode<1>; +def AddrMode2 : AddrMode<2>; +def AddrMode3 : AddrMode<3>; +def AddrMode4 : AddrMode<4>; +def AddrMode5 : AddrMode<5>; +def AddrMode6 : AddrMode<6>; +def AddrModeT1_1 : AddrMode<7>; +def AddrModeT1_2 : AddrMode<8>; +def AddrModeT1_4 : AddrMode<9>; +def AddrModeT1_s : AddrMode<10>; +def AddrModeT2_i12 : AddrMode<11>; +def AddrModeT2_i8 : AddrMode<12>; +def AddrModeT2_so : AddrMode<13>; +def AddrModeT2_pc : AddrMode<14>; def AddrModeT2_i8s4 : AddrMode<15>; // Instruction size. @@ -247,6 +247,7 @@ let Pattern = pattern; list Predicates = [IsARM]; } + // A few are not predicable class InoP; - // Atomic load/store instructions - class AIldrex opcod, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : I { let Inst{27-23} = 0b00011; let Inst{22-21} = opcod; - let Inst{20} = 1; + let Inst{20} = 1; let Inst{11-0} = 0b111110011111; } class AIstrex opcod, dag oops, dag iops, InstrItinClass itin, @@ -347,7 +346,7 @@ opc, asm, "", pattern> { let Inst{27-23} = 0b00011; let Inst{22-21} = opcod; - let Inst{20} = 0; + let Inst{20} = 0; let Inst{11-4} = 0b11111001; } @@ -357,21 +356,21 @@ : I { let Inst{24-21} = opcod; - let Inst{27-26} = {0,0}; + let Inst{27-26} = 0b00; } class AsI1 opcod, dag oops, dag iops, Format f, InstrItinClass itin, string opc, string asm, list pattern> : sI { let Inst{24-21} = opcod; - let Inst{27-26} = {0,0}; + let Inst{27-26} = 0b00; } class AXI1 opcod, dag oops, dag iops, Format f, InstrItinClass itin, string asm, list pattern> : XI { let Inst{24-21} = opcod; - let Inst{27-26} = {0,0}; + let Inst{27-26} = 0b00; } class AI1x2 pattern> @@ -384,7 +383,7 @@ string opc, string asm, list pattern> : I { - let Inst{27-26} = {0,1}; + let Inst{27-26} = 0b01; } // loads @@ -396,7 +395,7 @@ let Inst{21} = 0; // W bit let Inst{22} = 0; // B bit let Inst{24} = 1; // P bit - let Inst{27-26} = {0,1}; + let Inst{27-26} = 0b01; } class AXI2ldw pattern> @@ -406,7 +405,7 @@ let Inst{21} = 0; // W bit let Inst{22} = 0; // B bit let Inst{24} = 1; // P bit - let Inst{27-26} = {0,1}; + let Inst{27-26} = 0b01; } class AI2ldb pattern> @@ -416,7 +415,7 @@ let Inst{21} = 0; // W bit let Inst{22} = 1; // B bit let Inst{24} = 1; // P bit - let Inst{27-26} = {0,1}; + let Inst{27-26} = 0b01; } class AXI2ldb pattern> @@ -426,7 +425,7 @@ let Inst{21} = 0; // W bit let Inst{22} = 1; // B bit let Inst{24} = 1; // P bit - let Inst{27-26} = {0,1}; + let Inst{27-26} = 0b01; } // stores @@ -438,7 +437,7 @@ let Inst{21} = 0; // W bit let Inst{22} = 0; // B bit let Inst{24} = 1; // P bit - let Inst{27-26} = {0,1}; + let Inst{27-26} = 0b01; } class AXI2stw pattern> @@ -448,7 +447,7 @@ let Inst{21} = 0; // W bit let Inst{22} = 0; // B bit let Inst{24} = 1; // P bit - let Inst{27-26} = {0,1}; + let Inst{27-26} = 0b01; } class AI2stb pattern> @@ -458,7 +457,7 @@ let Inst{21} = 0; // W bit let Inst{22} = 1; // B bit let Inst{24} = 1; // P bit - let Inst{27-26} = {0,1}; + let Inst{27-26} = 0b01; } class AXI2stb pattern> @@ -468,7 +467,7 @@ let Inst{21} = 0; // W bit let Inst{22} = 1; // B bit let Inst{24} = 1; // P bit - let Inst{27-26} = {0,1}; + let Inst{27-26} = 0b01; } // Pre-indexed loads @@ -480,7 +479,7 @@ let Inst{21} = 1; // W bit let Inst{22} = 0; // B bit let Inst{24} = 1; // P bit - let Inst{27-26} = {0,1}; + let Inst{27-26} = 0b01; } class AI2ldbpr pattern> @@ -490,7 +489,7 @@ let Inst{21} = 1; // W bit let Inst{22} = 1; // B bit let Inst{24} = 1; // P bit - let Inst{27-26} = {0,1}; + let Inst{27-26} = 0b01; } // Pre-indexed stores @@ -502,7 +501,7 @@ let Inst{21} = 1; // W bit let Inst{22} = 0; // B bit let Inst{24} = 1; // P bit - let Inst{27-26} = {0,1}; + let Inst{27-26} = 0b01; } class AI2stbpr pattern> @@ -512,7 +511,7 @@ let Inst{21} = 1; // W bit let Inst{22} = 1; // B bit let Inst{24} = 1; // P bit - let Inst{27-26} = {0,1}; + let Inst{27-26} = 0b01; } // Post-indexed loads @@ -524,7 +523,7 @@ let Inst{21} = 0; // W bit let Inst{22} = 0; // B bit let Inst{24} = 0; // P bit - let Inst{27-26} = {0,1}; + let Inst{27-26} = 0b01; } class AI2ldbpo pattern> @@ -534,7 +533,7 @@ let Inst{21} = 0; // W bit let Inst{22} = 1; // B bit let Inst{24} = 0; // P bit - let Inst{27-26} = {0,1}; + let Inst{27-26} = 0b01; } // Post-indexed stores @@ -546,7 +545,7 @@ let Inst{21} = 0; // W bit let Inst{22} = 0; // B bit let Inst{24} = 0; // P bit - let Inst{27-26} = {0,1}; + let Inst{27-26} = 0b01; } class AI2stbpo pattern> @@ -556,7 +555,7 @@ let Inst{21} = 0; // W bit let Inst{22} = 1; // B bit let Inst{24} = 0; // P bit - let Inst{27-26} = {0,1}; + let Inst{27-26} = 0b01; } // addrmode3 instructions @@ -984,7 +983,7 @@ Encoding { let Inst{31-27} = opcod1; let Inst{15-14} = opcod2; - let Inst{12} = opcod3; + let Inst{12} = opcod3; } // BR_JT instructions @@ -1106,13 +1105,13 @@ // A6.2.4 Load/store single data item encoding. class T1LoadStore opA, bits<3> opB> : Encoding16 { let Inst{15-12} = opA; - let Inst{11-9} = opB; + let Inst{11-9} = opB; } -class T1LdSt opB> : T1LoadStore<0b0101, opB>; +class T1LdSt opB> : T1LoadStore<0b0101, opB>; class T1LdSt4Imm opB> : T1LoadStore<0b0110, opB>; // Immediate, 4 bytes class T1LdSt1Imm opB> : T1LoadStore<0b0111, opB>; // Immediate, 1 byte class T1LdSt2Imm opB> : T1LoadStore<0b1000, opB>; // Immediate, 2 bytes -class T1LdStSP opB> : T1LoadStore<0b1001, opB>; // SP relative +class T1LdStSP opB> : T1LoadStore<0b1001, opB>; // SP relative // A6.2.5 Miscellaneous 16-bit instructions encoding. class T1Misc opcode> : Encoding16 { @@ -1132,9 +1131,10 @@ list Predicates = [IsThumb2]; } -// Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as -// an input operand since by default it's a zero register. It will -// become an implicit def once it's "flipped". +// Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an +// input operand since by default it's a zero register. It will become an +// implicit def once it's "flipped". +// // FIXME: This uses unified syntax so {s} comes before {p}. We should make it // more consistent. class Thumb2sI { let Inst{31-27} = 0b11101; let Inst{26-25} = 0b00; - let Inst{24} = P; - let Inst{23} = ?; // The U bit. - let Inst{22} = 1; - let Inst{21} = W; - let Inst{20} = load; + let Inst{24} = P; + let Inst{23} = ?; // The U bit. + let Inst{22} = 1; + let Inst{21} = W; + let Inst{20} = load; } class T2sI Predicates = [IsThumb2]; let Inst{31-27} = 0b11111; let Inst{26-25} = 0b00; - let Inst{24} = signed; - let Inst{23} = 0; + let Inst{24} = signed; + let Inst{23} = 0; let Inst{22-21} = opcod; - let Inst{20} = load; - let Inst{11} = 1; + let Inst{20} = load; + let Inst{11} = 1; // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed - let Inst{10} = pre; // The P bit. - let Inst{8} = 1; // The W bit. + let Inst{10} = pre; // The P bit. + let Inst{8} = 1; // The W bit. } // Helper class for disassembly only @@ -1250,9 +1250,9 @@ : T2I { let Inst{31-27} = 0b11111; let Inst{26-24} = 0b011; - let Inst{23} = long; + let Inst{23} = long; let Inst{22-20} = op22_20; - let Inst{7-4} = op7_4; + let Inst{7-4} = op7_4; } // Tv5Pat - Same as Pat<>, but requires V5T Thumb mode. @@ -1374,8 +1374,8 @@ let Inst{27-23} = opcod1; let Inst{21-20} = opcod2; let Inst{11-8} = 0b1011; - let Inst{6} = op6; - let Inst{4} = op4; + let Inst{6} = op6; + let Inst{4} = op4; } // Double precision, binary, VML[AS] (for additional predicate) @@ -1386,12 +1386,11 @@ let Inst{27-23} = opcod1; let Inst{21-20} = opcod2; let Inst{11-8} = 0b1011; - let Inst{6} = op6; - let Inst{4} = op4; + let Inst{6} = op6; + let Inst{4} = op4; list Predicates = [HasVFP2, UseVMLx]; } - // Single precision, unary class ASuI opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4, bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc, @@ -1422,8 +1421,8 @@ let Inst{27-23} = opcod1; let Inst{21-20} = opcod2; let Inst{11-8} = 0b1010; - let Inst{6} = op6; - let Inst{4} = op4; + let Inst{6} = op6; + let Inst{4} = op4; } // Single precision binary, if no NEON @@ -1528,10 +1527,10 @@ : NeonI { let Inst{31-24} = 0b11110100; - let Inst{23} = op23; + let Inst{23} = op23; let Inst{21-20} = op21_20; - let Inst{11-8} = op11_8; - let Inst{7-4} = op7_4; + let Inst{11-8} = op11_8; + let Inst{7-4} = op7_4; } class PseudoNLdSt @@ -1563,13 +1562,13 @@ string opc, string dt, string asm, string cstr, list pattern> : NDataI { - let Inst{23} = op23; + let Inst{23} = op23; let Inst{21-19} = op21_19; - let Inst{11-8} = op11_8; - let Inst{7} = op7; - let Inst{6} = op6; - let Inst{5} = op5; - let Inst{4} = op4; + let Inst{11-8} = op11_8; + let Inst{7} = op7; + let Inst{6} = op6; + let Inst{5} = op5; + let Inst{4} = op4; } // NEON 2 vector register format. @@ -1582,9 +1581,9 @@ let Inst{21-20} = op21_20; let Inst{19-18} = op19_18; let Inst{17-16} = op17_16; - let Inst{11-7} = op11_7; - let Inst{6} = op6; - let Inst{4} = op4; + let Inst{11-7} = op11_7; + let Inst{6} = op6; + let Inst{4} = op4; } // Same as N2V except it doesn't have a datatype suffix. @@ -1597,9 +1596,9 @@ let Inst{21-20} = op21_20; let Inst{19-18} = op19_18; let Inst{17-16} = op17_16; - let Inst{11-7} = op11_7; - let Inst{6} = op6; - let Inst{4} = op4; + let Inst{11-7} = op11_7; + let Inst{6} = op6; + let Inst{4} = op4; } // NEON 2 vector register with immediate. @@ -1607,12 +1606,12 @@ dag oops, dag iops, Format f, InstrItinClass itin, string opc, string dt, string asm, string cstr, list pattern> : NDataI { - let Inst{24} = op24; - let Inst{23} = op23; + let Inst{24} = op24; + let Inst{23} = op23; let Inst{11-8} = op11_8; - let Inst{7} = op7; - let Inst{6} = op6; - let Inst{4} = op4; + let Inst{7} = op7; + let Inst{6} = op6; + let Inst{4} = op4; } // NEON 3 vector register format. @@ -1620,12 +1619,12 @@ dag oops, dag iops, Format f, InstrItinClass itin, string opc, string dt, string asm, string cstr, list pattern> : NDataI { - let Inst{24} = op24; - let Inst{23} = op23; + let Inst{24} = op24; + let Inst{23} = op23; let Inst{21-20} = op21_20; - let Inst{11-8} = op11_8; - let Inst{6} = op6; - let Inst{4} = op4; + let Inst{11-8} = op11_8; + let Inst{6} = op6; + let Inst{4} = op4; } // Same as N3V except it doesn't have a data type suffix. @@ -1634,12 +1633,12 @@ dag oops, dag iops, Format f, InstrItinClass itin, string opc, string asm, string cstr, list pattern> : NDataXI { - let Inst{24} = op24; - let Inst{23} = op23; + let Inst{24} = op24; + let Inst{23} = op23; let Inst{21-20} = op21_20; - let Inst{11-8} = op11_8; - let Inst{6} = op6; - let Inst{4} = op4; + let Inst{11-8} = op11_8; + let Inst{6} = op6; + let Inst{4} = op4; } // NEON VMOVs between scalar and core registers. @@ -1649,9 +1648,9 @@ : InstARM { let Inst{27-20} = opcod1; - let Inst{11-8} = opcod2; - let Inst{6-5} = opcod3; - let Inst{4} = 1; + let Inst{11-8} = opcod2; + let Inst{6-5} = opcod3; + let Inst{4} = 1; let OutOperandList = oops; let InOperandList = !con(iops, (ins pred:$p)); @@ -1685,9 +1684,9 @@ let Inst{24-23} = 0b11; let Inst{21-20} = 0b11; let Inst{19-16} = op19_16; - let Inst{11-7} = 0b11000; - let Inst{6} = op6; - let Inst{4} = 0; + let Inst{11-7} = 0b11000; + let Inst{6} = op6; + let Inst{4} = 0; } // NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON From resistor at mac.com Tue Aug 31 02:55:56 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 31 Aug 2010 07:55:56 -0000 Subject: [llvm-commits] [llvm] r112594 - /llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp Message-ID: <20100831075556.C9F7B2A6C12D@llvm.org> Author: resistor Date: Tue Aug 31 02:55:56 2010 New Revision: 112594 URL: http://llvm.org/viewvc/llvm-project?rev=112594&view=rev Log: Don't perform an extra traversal of the function just to do cleanup. We can safely simplify instructions after each block has been processed without worrying about iterator invalidation. Modified: llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp Modified: llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp?rev=112594&r1=112593&r2=112594&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp Tue Aug 31 02:55:56 2010 @@ -102,7 +102,7 @@ bool Changed = false; - for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI) + for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI) { for (BasicBlock::iterator BI = FI->begin(), BE = FI->end(); BI != BE; ) { Instruction *II = BI++; if (SelectInst *SI = dyn_cast(II)) @@ -110,10 +110,9 @@ else if (PHINode *P = dyn_cast(II)) Changed |= processPHI(P); } - - if (Changed) - for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI) - SimplifyInstructionsInBlock(FI); + + SimplifyInstructionsInBlock(FI); + } return Changed; } From nicholas at mxc.ca Tue Aug 31 03:29:37 2010 From: nicholas at mxc.ca (Nick Lewycky) Date: Tue, 31 Aug 2010 08:29:37 -0000 Subject: [llvm-commits] [llvm] r112595 - /llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp Message-ID: <20100831082937.BF8752A6C12C@llvm.org> Author: nicholas Date: Tue Aug 31 03:29:37 2010 New Revision: 112595 URL: http://llvm.org/viewvc/llvm-project?rev=112595&view=rev Log: Fix an infinite loop; merging two functions will create a new function (if the two are weak, we make them thunks to a new strong function) so don't iterate through the function list as we're modifying it. Also add back the outermost loop which got removed during the cleanups. Modified: llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp Modified: llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp?rev=112595&r1=112594&r2=112595&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp Tue Aug 31 03:29:37 2010 @@ -63,6 +63,7 @@ #include "llvm/Support/ValueHandle.h" #include "llvm/Support/raw_ostream.h" #include "llvm/Target/TargetData.h" +#include using namespace llvm; STATISTIC(NumFunctionsMerged, "Number of functions merged"); @@ -82,7 +83,8 @@ private: /// MergeTwoFunctions - Merge two equivalent functions. Upon completion, G - /// is deleted. + /// may be deleted, or may be converted into a thunk. In either case, it + /// should never be visited again. void MergeTwoFunctions(Function *F, Function *G) const; /// WriteThunk - Replace G with a simple tail call to bitcast(F). Also @@ -598,41 +600,53 @@ }; bool MergeFunctions::runOnModule(Module &M) { - bool Changed = false; + typedef DenseSet FnSetType; + bool Changed = false; TD = getAnalysisIfAvailable(); - typedef DenseSet FnSetType; - FnSetType FnSet; - for (Module::iterator F = M.begin(), E = M.end(); F != E;) { - if (F->isDeclaration() || F->hasAvailableExternallyLinkage()) { - ++F; - continue; - } + std::vector Funcs; + for (Module::iterator F = M.begin(), E = M.end(); F != E; ++F) { + if (!F->isDeclaration() && !F->hasAvailableExternallyLinkage()) + Funcs.push_back(F); + } + + bool LocalChanged; + do { + LocalChanged = false; - ComparableFunction *NewF = new ComparableFunction(F, TD); - ++F; - std::pair Result = FnSet.insert(NewF); - if (!Result.second) { - ComparableFunction *&OldF = *Result.first; - assert(OldF && "Expected a hash collision"); - - // NewF will be deleted in favour of OldF unless NewF is strong and OldF - // is weak in which case swap them to keep the strong definition. - - if (OldF->Func->isWeakForLinker() && !NewF->Func->isWeakForLinker()) - std::swap(OldF, NewF); - - DEBUG(dbgs() << " " << OldF->Func->getName() << " == " - << NewF->Func->getName() << '\n'); - - Changed = true; - Function *DeleteF = NewF->Func; - delete NewF; - MergeTwoFunctions(OldF->Func, DeleteF); + FnSetType FnSet; + for (unsigned i = 0, e = Funcs.size(); i != e;) { + Function *F = Funcs[i]; + ComparableFunction *NewF = new ComparableFunction(F, TD); + std::pair Result = FnSet.insert(NewF); + if (!Result.second) { + ComparableFunction *&OldF = *Result.first; + assert(OldF && "Expected a hash collision"); + + // NewF will be deleted in favour of OldF unless NewF is strong and + // OldF is weak in which case swap them to keep the strong definition. + + if (OldF->Func->isWeakForLinker() && !NewF->Func->isWeakForLinker()) + std::swap(OldF, NewF); + + DEBUG(dbgs() << " " << OldF->Func->getName() << " == " + << NewF->Func->getName() << '\n'); + + Funcs.erase(Funcs.begin() + i); + --e; + + Function *DeleteF = NewF->Func; + delete NewF; + MergeTwoFunctions(OldF->Func, DeleteF); + LocalChanged = true; + Changed = true; + } else { + ++i; + } } - } + DeleteContainerPointers(FnSet); + } while (LocalChanged); - DeleteContainerPointers(FnSet); return Changed; } From baldrick at free.fr Tue Aug 31 03:38:56 2010 From: baldrick at free.fr (Duncan Sands) Date: Tue, 31 Aug 2010 08:38:56 -0000 Subject: [llvm-commits] [dragonegg] r112596 - /dragonegg/trunk/gcc_revision_tested_with Message-ID: <20100831083856.BBCE12A6C12C@llvm.org> Author: baldrick Date: Tue Aug 31 03:38:56 2010 New Revision: 112596 URL: http://llvm.org/viewvc/llvm-project?rev=112596&view=rev Log: Moved to latest gcc-4.5. Modified: dragonegg/trunk/gcc_revision_tested_with Modified: dragonegg/trunk/gcc_revision_tested_with URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/gcc_revision_tested_with?rev=112596&r1=112595&r2=112596&view=diff ============================================================================== --- dragonegg/trunk/gcc_revision_tested_with (original) +++ dragonegg/trunk/gcc_revision_tested_with Tue Aug 31 03:38:56 2010 @@ -1 +1 @@ -162458 +163634 From baldrick at free.fr Tue Aug 31 04:05:07 2010 From: baldrick at free.fr (Duncan Sands) Date: Tue, 31 Aug 2010 09:05:07 -0000 Subject: [llvm-commits] [llvm] r112597 - in /llvm/trunk: include/llvm/CodeGen/Passes.h lib/CodeGen/DwarfEHPrepare.cpp lib/CodeGen/LLVMTargetMachine.cpp Message-ID: <20100831090507.174362A6C12E@llvm.org> Author: baldrick Date: Tue Aug 31 04:05:06 2010 New Revision: 112597 URL: http://llvm.org/viewvc/llvm-project?rev=112597&view=rev Log: Stop using the dom frontier in DwarfEHPrepare by not promoting alloca's any more. I plan to reimplement alloca promotion using SSAUpdater later. It looks like Bill's URoR logic really always needs domtree, so the pass now always asks for domtree info. Modified: llvm/trunk/include/llvm/CodeGen/Passes.h llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Modified: llvm/trunk/include/llvm/CodeGen/Passes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/Passes.h?rev=112597&r1=112596&r2=112597&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/Passes.h (original) +++ llvm/trunk/include/llvm/CodeGen/Passes.h Tue Aug 31 04:05:06 2010 @@ -192,7 +192,7 @@ /// createDwarfEHPass - This pass mulches exception handling code into a form /// adapted to code generation. Required if using dwarf exception handling. - FunctionPass *createDwarfEHPass(const TargetMachine *tm, bool fast); + FunctionPass *createDwarfEHPass(const TargetMachine *tm); /// createSjLjEHPass - This pass adapts exception handling code to use /// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control flow. Modified: llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp?rev=112597&r1=112596&r2=112597&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp (original) +++ llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp Tue Aug 31 04:05:06 2010 @@ -25,7 +25,6 @@ #include "llvm/Support/CallSite.h" #include "llvm/Target/TargetLowering.h" #include "llvm/Transforms/Utils/BasicBlockUtils.h" -#include "llvm/Transforms/Utils/PromoteMemToReg.h" using namespace llvm; STATISTIC(NumLandingPadsSplit, "Number of landing pads split"); @@ -37,7 +36,6 @@ class DwarfEHPrepare : public FunctionPass { const TargetMachine *TM; const TargetLowering *TLI; - bool CompileFast; // The eh.exception intrinsic. Function *ExceptionValueIntrinsic; @@ -54,9 +52,8 @@ // _Unwind_Resume or the target equivalent. Constant *RewindFunction; - // Dominator info is used when turning stack temporaries into registers. + // We both use and preserve dominator info. DominatorTree *DT; - DominanceFrontier *DF; // The function we are running on. Function *F; @@ -72,7 +69,6 @@ bool LowerUnwinds(); bool MoveExceptionValueCalls(); bool FinishStackTemporaries(); - bool PromoteStackTemporaries(); Instruction *CreateExceptionValueCall(BasicBlock *BB); Instruction *CreateValueLoad(BasicBlock *BB); @@ -112,49 +108,10 @@ bool FindSelectorAndURoR(Instruction *Inst, bool &URoRInvoke, SmallPtrSet &SelCalls); - /// PromoteStoreInst - Perform Mem2Reg on a StoreInst. - bool PromoteStoreInst(StoreInst *SI) { - if (!SI || !DT || !DF) return false; - - AllocaInst *AI = dyn_cast(SI->getOperand(1)); - if (!AI || !isAllocaPromotable(AI)) return false; - - // Turn the alloca into a register. - std::vector Allocas(1, AI); - PromoteMemToReg(Allocas, *DT, *DF); - return true; - } - - /// PromoteEHPtrStore - Promote the storing of an EH pointer into a - /// register. This should get rid of the store and subsequent loads. - bool PromoteEHPtrStore(IntrinsicInst *II) { - if (!DT || !DF) return false; - - bool Changed = false; - StoreInst *SI; - - while (1) { - SI = 0; - for (Value::use_iterator - I = II->use_begin(), E = II->use_end(); I != E; ++I) { - SI = dyn_cast(*I); - if (SI) break; - } - - if (!PromoteStoreInst(SI)) - break; - - Changed = true; - } - - return Changed; - } - public: static char ID; // Pass identification, replacement for typeid. - DwarfEHPrepare(const TargetMachine *tm, bool fast) : + DwarfEHPrepare(const TargetMachine *tm) : FunctionPass(ID), TM(tm), TLI(TM->getTargetLowering()), - CompileFast(fast), ExceptionValueIntrinsic(0), SelectorIntrinsic(0), URoR(0), EHCatchAllValue(0), RewindFunction(0) {} @@ -162,12 +119,8 @@ // getAnalysisUsage - We need dominance frontiers for memory promotion. virtual void getAnalysisUsage(AnalysisUsage &AU) const { - if (!CompileFast) - AU.addRequired(); + AU.addRequired(); AU.addPreserved(); - if (!CompileFast) - AU.addRequired(); - AU.addPreserved(); } const char *getPassName() const { @@ -179,8 +132,8 @@ char DwarfEHPrepare::ID = 0; -FunctionPass *llvm::createDwarfEHPass(const TargetMachine *tm, bool fast) { - return new DwarfEHPrepare(tm, fast); +FunctionPass *llvm::createDwarfEHPass(const TargetMachine *tm) { + return new DwarfEHPrepare(tm); } /// HasCatchAllInSelector - Return true if the intrinsic instruction has a @@ -261,7 +214,6 @@ SmallPtrSet SeenPHIs; bool Changed = false; - restart: for (Value::use_iterator I = Inst->use_begin(), E = Inst->use_end(); I != E; ++I) { Instruction *II = dyn_cast(*I); @@ -275,11 +227,6 @@ URoRInvoke = true; } else if (CastInst *CI = dyn_cast(II)) { Changed |= FindSelectorAndURoR(CI, URoRInvoke, SelCalls); - } else if (StoreInst *SI = dyn_cast(II)) { - if (!PromoteStoreInst(SI)) continue; - Changed = true; - SeenPHIs.clear(); - goto restart; // Uses may have changed, restart loop. } else if (PHINode *PN = dyn_cast(II)) { if (SeenPHIs.insert(PN)) // Don't process a PHI node more than once. @@ -311,10 +258,6 @@ SmallPtrSet CatchAllSels; FindAllCleanupSelectors(Sels, CatchAllSels); - if (!DT) - // We require DominatorTree information. - return CleanupSelectors(CatchAllSels); - if (!URoR) { URoR = F->getParent()->getFunction("_Unwind_Resume_or_Rethrow"); if (!URoR) return CleanupSelectors(CatchAllSels); @@ -356,8 +299,6 @@ IntrinsicInst *EHPtr = dyn_cast(*I); if (!EHPtr || EHPtr->getParent()->getParent() != F) continue; - Changed |= PromoteEHPtrStore(EHPtr); - bool URoRInvoke = false; SmallPtrSet SelCalls; Changed |= FindSelectorAndURoR(EHPtr, URoRInvoke, SelCalls); @@ -525,11 +466,8 @@ // Add a fallthrough from NewBB to the original landing pad. BranchInst::Create(LPad, NewBB); - // Now update DominatorTree and DominanceFrontier analysis information. - if (DT) - DT->splitBlock(NewBB); - if (DF) - DF->splitBlock(NewBB); + // Now update DominatorTree analysis information. + DT->splitBlock(NewBB); // Remember the newly constructed landing pad. The original landing pad // LPad is no longer a landing pad now that all unwind edges have been @@ -652,18 +590,6 @@ return Changed; } -/// PromoteStackTemporaries - Turn any stack temporaries we introduced into -/// registers if possible. -bool DwarfEHPrepare::PromoteStackTemporaries() { - if (ExceptionValueVar && DT && DF && isAllocaPromotable(ExceptionValueVar)) { - // Turn the exception temporary into registers and phi nodes if possible. - std::vector Allocas(1, ExceptionValueVar); - PromoteMemToReg(Allocas, *DT, *DF); - return true; - } - return false; -} - /// CreateExceptionValueCall - Insert a call to the eh.exception intrinsic at /// the start of the basic block (unless there already is one, in which case /// the existing call is returned). @@ -711,8 +637,7 @@ bool Changed = false; // Initialize internal state. - DT = getAnalysisIfAvailable(); - DF = getAnalysisIfAvailable(); + DT = &getAnalysis(); ExceptionValueVar = 0; F = &Fn; @@ -731,9 +656,7 @@ // Initialize any stack temporaries we introduced. Changed |= FinishStackTemporaries(); - // Turn any stack temporaries into registers if possible. - if (!CompileFast) - Changed |= PromoteStackTemporaries(); + // TODO: Turn any stack temporaries into registers if possible. Changed |= HandleURoRInvokes(); Modified: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp?rev=112597&r1=112596&r2=112597&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp (original) +++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp Tue Aug 31 04:05:06 2010 @@ -289,7 +289,7 @@ PM.add(createSjLjEHPass(getTargetLowering())); // FALLTHROUGH case ExceptionHandling::Dwarf: - PM.add(createDwarfEHPass(this, OptLevel==CodeGenOpt::None)); + PM.add(createDwarfEHPass(this)); break; case ExceptionHandling::None: PM.add(createLowerInvokePass(getTargetLowering())); From geek4civic at gmail.com Tue Aug 31 05:31:27 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Tue, 31 Aug 2010 19:31:27 +0900 Subject: [llvm-commits] [PATCH] lit: makes 'where' available on cygwin In-Reply-To: References: Message-ID: It was wrong, to prevent tests on win32. It finds "test/Scripts/macho-dump test/Scripts/coff-dump.py" even if *.bat exists. ...Takumi 2010/8/24 NAKAMURA Takumi : > Hello, > > This patch makes lit available to clang-test on cygwin. > > - on cygwin, os.pathsep==':' but Cygwin does not modify the variable PATHEXT. > ?it might be enough separator is ';' with PATHEXT > ?because PATHEXT is, AFAIK, Win32-specific. > - When PATHEXT exists, it makes seek suffix-less file. > ?on cygwin, "/path/to/a" hits to "/path/to/a.exe". > ?I quoted 2 lines from http://bugs.python.org/file16459/which.py > > Please take a look, thank you! > > ...Takumi > From aggarwa4 at illinois.edu Tue Aug 31 09:37:24 2010 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Tue, 31 Aug 2010 14:37:24 -0000 Subject: [llvm-commits] [poolalloc] r112599 - in /poolalloc/trunk/test/dsa/td: ./ call.c call.ll call1.c call1.ll call2.c call2.ll dg.exp params.c params.ll params1.c params1.ll params2.ll recur.c recur.ll recur1.c recur1.ll recur2.c recur2.ll recur3.c testcase.c testcase.ll Message-ID: <20100831143724.E966A2A6C12C@llvm.org> Author: aggarwa4 Date: Tue Aug 31 09:37:24 2010 New Revision: 112599 URL: http://llvm.org/viewvc/llvm-project?rev=112599&view=rev Log: More Tests Added: poolalloc/trunk/test/dsa/td/ poolalloc/trunk/test/dsa/td/call.c poolalloc/trunk/test/dsa/td/call.ll poolalloc/trunk/test/dsa/td/call1.c poolalloc/trunk/test/dsa/td/call1.ll poolalloc/trunk/test/dsa/td/call2.c poolalloc/trunk/test/dsa/td/call2.ll poolalloc/trunk/test/dsa/td/dg.exp poolalloc/trunk/test/dsa/td/params.c poolalloc/trunk/test/dsa/td/params.ll poolalloc/trunk/test/dsa/td/params1.c poolalloc/trunk/test/dsa/td/params1.ll poolalloc/trunk/test/dsa/td/params2.ll poolalloc/trunk/test/dsa/td/recur.c poolalloc/trunk/test/dsa/td/recur.ll poolalloc/trunk/test/dsa/td/recur1.c poolalloc/trunk/test/dsa/td/recur1.ll poolalloc/trunk/test/dsa/td/recur2.c poolalloc/trunk/test/dsa/td/recur2.ll poolalloc/trunk/test/dsa/td/recur3.c poolalloc/trunk/test/dsa/td/testcase.c poolalloc/trunk/test/dsa/td/testcase.ll Added: poolalloc/trunk/test/dsa/td/call.c URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/td/call.c?rev=112599&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/td/call.c (added) +++ poolalloc/trunk/test/dsa/td/call.c Tue Aug 31 09:37:24 2010 @@ -0,0 +1,27 @@ +//--Make sure we can run DSA on it! +//RUN: llvm-gcc %s -c --emit-llvm -o - | \ +//RUN: dsaopt -dsa-bu -dsa-td -disable-output + + +#include + + +int* test() { + int* a2 = (int*)malloc(sizeof(int)); + *a2 = 10; + + if(*a2 > 5 ) { + return a2; + } + + int *b2 = (int*)malloc(sizeof(int)); + return b2; + +} + +void func() { + + int *a1 = test(); + int *b1 = test(); +} + Added: poolalloc/trunk/test/dsa/td/call.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/td/call.ll?rev=112599&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/td/call.ll (added) +++ poolalloc/trunk/test/dsa/td/call.ll Tue Aug 31 09:37:24 2010 @@ -0,0 +1,66 @@ + +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "func:a1:0+I" +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "func:b1:0+I" +;RUN: dsaopt %s -dsa-td -analyze -verify-flags "func:a1:0+HMR-I" +;RUN: dsaopt %s -dsa-td -analyze -verify-flags "func:b1:0+HMR-I" + +; ModuleID = 'call.bc' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" + +define i32* @test() nounwind { +entry: + %retval = alloca i32* ; [#uses=2] + %0 = alloca i32* ; [#uses=3] + %a2 = alloca i32* ; [#uses=4] + %b2 = alloca i32* ; [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + %1 = call noalias i8* @malloc(i64 4) nounwind ; [#uses=1] + %2 = bitcast i8* %1 to i32* ; [#uses=1] + store i32* %2, i32** %a2, align 8 + %3 = load i32** %a2, align 8 ; [#uses=1] + store i32 10, i32* %3, align 4 + %4 = load i32** %a2, align 8 ; [#uses=1] + %5 = load i32* %4, align 4 ; [#uses=1] + %6 = icmp sgt i32 %5, 5 ; [#uses=1] + br i1 %6, label %bb, label %bb1 + +bb: ; preds = %entry + %7 = load i32** %a2, align 8 ; [#uses=1] + store i32* %7, i32** %0, align 8 + br label %bb2 + +bb1: ; preds = %entry + %8 = call noalias i8* @malloc(i64 4) nounwind ; [#uses=1] + %9 = bitcast i8* %8 to i32* ; [#uses=1] + store i32* %9, i32** %b2, align 8 + %10 = load i32** %b2, align 8 ; [#uses=1] + store i32* %10, i32** %0, align 8 + br label %bb2 + +bb2: ; preds = %bb1, %bb + %11 = load i32** %0, align 8 ; [#uses=1] + store i32* %11, i32** %retval, align 8 + br label %return + +return: ; preds = %bb2 + %retval3 = load i32** %retval ; [#uses=1] + ret i32* %retval3 +} + +declare noalias i8* @malloc(i64) nounwind + +define void @func() nounwind { +entry: + %a1 = alloca i32* ; [#uses=1] + %b1 = alloca i32* ; [#uses=1] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + %0 = call i32* @test() nounwind ; [#uses=1] + store i32* %0, i32** %a1, align 8 + %1 = call i32* @test() nounwind ; [#uses=1] + store i32* %1, i32** %b1, align 8 + br label %return + +return: ; preds = %entry + ret void +} Added: poolalloc/trunk/test/dsa/td/call1.c URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/td/call1.c?rev=112599&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/td/call1.c (added) +++ poolalloc/trunk/test/dsa/td/call1.c Tue Aug 31 09:37:24 2010 @@ -0,0 +1,24 @@ +//--Make sure we can run DSA on it! +//RUN: llvm-gcc %s -c --emit-llvm -o - | \ +//RUN: dsaopt -dsa-bu -dsa-td -disable-output + + +#include + +int* test(int **a2, int **b2) { + int *temp; + temp = *a2; + a2 = b2; + *b2 = temp; + + return *a2; +} + +void func() { + + int* mem1 = (int *)malloc(sizeof(int)); + int* mem2 = (int *)malloc(sizeof(int)); + int *a1 = test(&mem1, &mem2); + int *b1 = test(&mem2, &mem1); +} + Added: poolalloc/trunk/test/dsa/td/call1.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/td/call1.ll?rev=112599&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/td/call1.ll (added) +++ poolalloc/trunk/test/dsa/td/call1.ll Tue Aug 31 09:37:24 2010 @@ -0,0 +1,76 @@ +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "test:b2:0+I" +;RUN: dsaopt %s -dsa-td -analyze -verify-flags "test:b2:0+IHM" +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "test:a2:0+I" +;RUN: dsaopt %s -dsa-td -analyze -verify-flags "test:a2:0+IHM" +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "test:a2+IMRE" +;RUN: dsaopt %s -dsa-td -analyze -verify-flags "test:a2+SIMRE" + + +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "func:a1+SM" +;RUN: dsaopt %s -dsa-td -analyze -verify-flags "func:a1+SM" +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "func:b1+SM" +;RUN: dsaopt %s -dsa-td -analyze -verify-flags "func:b1+SM" +;RUN: dsaopt %s -dsa-td -analyze -check-same-node=func:mem1,func:mem2 +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "func:mem1:0+HI" +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "func:mem2:0+HI" +;RUN: dsaopt %s -dsa-td -analyze -verify-flags "func:mem1:0+HM" + + +; ModuleID = 'call1.bc' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" + +define i32* @test(i32** %a2, i32** %b2) nounwind { +entry: + %a2_addr = alloca i32** ; [#uses=4] + %b2_addr = alloca i32** ; [#uses=3] + %retval = alloca i32* ; [#uses=2] + %0 = alloca i32* ; [#uses=2] + %temp = alloca i32* ; [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store i32** %a2, i32*** %a2_addr + store i32** %b2, i32*** %b2_addr + %1 = load i32*** %a2_addr, align 8 ; [#uses=1] + %2 = load i32** %1, align 8 ; [#uses=1] + store i32* %2, i32** %temp, align 8 + %3 = load i32*** %b2_addr, align 8 ; [#uses=1] + store i32** %3, i32*** %a2_addr, align 8 + %4 = load i32*** %b2_addr, align 8 ; [#uses=1] + %5 = load i32** %temp, align 8 ; [#uses=1] + store i32* %5, i32** %4, align 8 + %6 = load i32*** %a2_addr, align 8 ; [#uses=1] + %7 = load i32** %6, align 8 ; [#uses=1] + store i32* %7, i32** %0, align 8 + %8 = load i32** %0, align 8 ; [#uses=1] + store i32* %8, i32** %retval, align 8 + br label %return + +return: ; preds = %entry + %retval1 = load i32** %retval ; [#uses=1] + ret i32* %retval1 +} + +define void @func() nounwind { +entry: + %mem1 = alloca i32* ; [#uses=3] + %mem2 = alloca i32* ; [#uses=3] + %a1 = alloca i32* ; [#uses=1] + %b1 = alloca i32* ; [#uses=1] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + %0 = call noalias i8* @malloc(i64 4) nounwind ; [#uses=1] + %1 = bitcast i8* %0 to i32* ; [#uses=1] + store i32* %1, i32** %mem1, align 8 + %2 = call noalias i8* @malloc(i64 4) nounwind ; [#uses=1] + %3 = bitcast i8* %2 to i32* ; [#uses=1] + store i32* %3, i32** %mem2, align 8 + %4 = call i32* @test(i32** %mem1, i32** %mem2) nounwind ; [#uses=1] + store i32* %4, i32** %a1, align 8 + %5 = call i32* @test(i32** %mem2, i32** %mem1) nounwind ; [#uses=1] + store i32* %5, i32** %b1, align 8 + br label %return + +return: ; preds = %entry + ret void +} + +declare noalias i8* @malloc(i64) nounwind Added: poolalloc/trunk/test/dsa/td/call2.c URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/td/call2.c?rev=112599&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/td/call2.c (added) +++ poolalloc/trunk/test/dsa/td/call2.c Tue Aug 31 09:37:24 2010 @@ -0,0 +1,24 @@ +//--Make sure we can run DSA on it! +//RUN: llvm-gcc %s -c --emit-llvm -o - | \ +//RUN: dsaopt -dsa-bu -dsa-td -disable-output + + +#include + +int* test(int **a2, int **b2) { + int *temp; + temp = *a2; + a2 = b2; + *b2 = temp; + + return *a2; +} + +void func() { + + int* mem1 = (int *)malloc(sizeof(int)); + int* mem2 = (int *)malloc(sizeof(int)); + int *a1 = test(&mem1, &mem2); + int *b1 = test(&mem1, &mem2); +} + Added: poolalloc/trunk/test/dsa/td/call2.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/td/call2.ll?rev=112599&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/td/call2.ll (added) +++ poolalloc/trunk/test/dsa/td/call2.ll Tue Aug 31 09:37:24 2010 @@ -0,0 +1,75 @@ +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "test:b2:0+I" +;RUN: dsaopt %s -dsa-td -analyze -verify-flags "test:b2:0+IHM" +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "test:a2:0+I" +;RUN: dsaopt %s -dsa-td -analyze -verify-flags "test:a2:0+IHM" +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "test:a2+IMRE" +;RUN: dsaopt %s -dsa-td -analyze -verify-flags "test:a2+SIMRE" + + +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "func:a1+SM" +;RUN: dsaopt %s -dsa-td -analyze -verify-flags "func:a1+SM" +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "func:b1+SM" +;RUN: dsaopt %s -dsa-td -analyze -verify-flags "func:b1+SM" +;RUN: dsaopt %s -dsa-td -analyze -check-same-node=func:mem1,func:mem2 +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "func:mem1:0+HI" +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "func:mem2:0+HI" +;RUN: dsaopt %s -dsa-td -analyze -verify-flags "func:mem1:0+HM" + +; ModuleID = 'call2.bc' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" + +define i32* @test(i32** %a2, i32** %b2) nounwind { +entry: + %a2_addr = alloca i32** ; [#uses=4] + %b2_addr = alloca i32** ; [#uses=3] + %retval = alloca i32* ; [#uses=2] + %0 = alloca i32* ; [#uses=2] + %temp = alloca i32* ; [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store i32** %a2, i32*** %a2_addr + store i32** %b2, i32*** %b2_addr + %1 = load i32*** %a2_addr, align 8 ; [#uses=1] + %2 = load i32** %1, align 8 ; [#uses=1] + store i32* %2, i32** %temp, align 8 + %3 = load i32*** %b2_addr, align 8 ; [#uses=1] + store i32** %3, i32*** %a2_addr, align 8 + %4 = load i32*** %b2_addr, align 8 ; [#uses=1] + %5 = load i32** %temp, align 8 ; [#uses=1] + store i32* %5, i32** %4, align 8 + %6 = load i32*** %a2_addr, align 8 ; [#uses=1] + %7 = load i32** %6, align 8 ; [#uses=1] + store i32* %7, i32** %0, align 8 + %8 = load i32** %0, align 8 ; [#uses=1] + store i32* %8, i32** %retval, align 8 + br label %return + +return: ; preds = %entry + %retval1 = load i32** %retval ; [#uses=1] + ret i32* %retval1 +} + +define void @func() nounwind { +entry: + %mem1 = alloca i32* ; [#uses=3] + %mem2 = alloca i32* ; [#uses=3] + %a1 = alloca i32* ; [#uses=1] + %b1 = alloca i32* ; [#uses=1] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + %0 = call noalias i8* @malloc(i64 4) nounwind ; [#uses=1] + %1 = bitcast i8* %0 to i32* ; [#uses=1] + store i32* %1, i32** %mem1, align 8 + %2 = call noalias i8* @malloc(i64 4) nounwind ; [#uses=1] + %3 = bitcast i8* %2 to i32* ; [#uses=1] + store i32* %3, i32** %mem2, align 8 + %4 = call i32* @test(i32** %mem1, i32** %mem2) nounwind ; [#uses=1] + store i32* %4, i32** %a1, align 8 + %5 = call i32* @test(i32** %mem1, i32** %mem2) nounwind ; [#uses=1] + store i32* %5, i32** %b1, align 8 + br label %return + +return: ; preds = %entry + ret void +} + +declare noalias i8* @malloc(i64) nounwind Added: poolalloc/trunk/test/dsa/td/dg.exp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/td/dg.exp?rev=112599&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/td/dg.exp (added) +++ poolalloc/trunk/test/dsa/td/dg.exp Tue Aug 31 09:37:24 2010 @@ -0,0 +1,3 @@ +load_lib llvm.exp + +RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,cpp}]] Added: poolalloc/trunk/test/dsa/td/params.c URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/td/params.c?rev=112599&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/td/params.c (added) +++ poolalloc/trunk/test/dsa/td/params.c Tue Aug 31 09:37:24 2010 @@ -0,0 +1,33 @@ +//--Make sure we can run DSA on it! +//RUN: llvm-gcc %s -c --emit-llvm -o - | \ +//RUN: dsaopt -dsa-bu -dsa-td -disable-output + + +#include + +int* test(int **a2, int **b2) { + int *temp = *a2; + int *temp1 = *b2; + if(*temp1 < *temp) { + return *b2; + } + else { + int *temp2 = (int*)malloc(sizeof(int)); + a2 = &temp2; + } + + return *a2; +} + +void func() { + + int* mem1; + int* mem2; + int r1 = 5; + int r2 = 6; + mem1 = &r1; + mem2 = &r2; + int *a1 = test(&mem1, &mem2); + int *b1 = test(&mem2, &mem1); +} + Added: poolalloc/trunk/test/dsa/td/params.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/td/params.ll?rev=112599&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/td/params.ll (added) +++ poolalloc/trunk/test/dsa/td/params.ll Tue Aug 31 09:37:24 2010 @@ -0,0 +1,122 @@ +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "func:mem1:0+SIM" +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "func:mem2:0+SIM" +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "func:a1+SM" +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "func:b1+SM" + +;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "func:mem1:0+SHMR" +;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "func:mem2:0+SHMR" +;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "func:a1+SM" +;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "func:b1+SM" + +;RUN: dsaopt %s -dsa-bu -analyze -check-same-node=func:a1:0,func:b1:0,func:mem2:0,func:mem1:0,func:r1,func:r2 + +;RUN: dsaopt %s -dsa-td -analyze -verify-flags "func:mem1:0+SHMR" +;RUN: dsaopt %s -dsa-td -analyze -verify-flags "func:mem2:0+SHMR" +;RUN: dsaopt %s -dsa-td -analyze -verify-flags "func:a1+SM" +;RUN: dsaopt %s -dsa-td -analyze -verify-flags "func:b1+SM" + +;RUN: dsaopt %s -dsa-td -analyze -check-same-node=func:a1:0,func:b1:0,func:mem2:0,func:mem1:0,func:r1,func:r2 + +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "test:b2:0+HIR" +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "test:a2:0+HIR" +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "test:a2+SIMRE" +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "test:temp:0+HIR" +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "test:temp1:0+HIR" +;RUN: dsaopt %s -dsa-local -analyze -check-same-node=test:temp2:0,test:a2:0,test:temp1:0,test:temp:0,test:b2:0 + +;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "test:b2:0+HIMR" +;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "test:a2:0+HIMR" +;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "test:a2+SIMRE" +;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "test:temp+SMR" +;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "test:temp1+SMR" +;RUN: dsaopt %s -dsa-bu -analyze -check-same-node=test:temp2:0,test:a2:0,test:temp1:0,test:temp:0,test:b2:0 +;RUN: dsaopt %s -dsa-bu -analyze -check-same-node=test:a2,test:temp2 + + +;RUN: dsaopt %s -dsa-td -analyze -verify-flags "test:b2:0+SHIMR" +;RUN: dsaopt %s -dsa-td -analyze -verify-flags "test:a2:0+SHIMR" +;RUN: dsaopt %s -dsa-td -analyze -verify-flags "test:a2+SIMRE" +;RUN: dsaopt %s -dsa-td -analyze -verify-flags "test:temp+SMR" +;RUN: dsaopt %s -dsa-td -analyze -verify-flags "test:temp1+SMR" +;RUN: dsaopt %s -dsa-td -analyze -check-same-node=test:temp2:0,test:a2:0,test:temp1:0,test:temp:0,test:b2:0 +;RUN: dsaopt %s -dsa-td -analyze -check-same-node=test:a2,test:b2,test:temp2 + +; ModuleID = 'params.bc' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" + +define i32* @test(i32** %a2, i32** %b2) nounwind { +entry: + %a2_addr = alloca i32** ; [#uses=4] + %b2_addr = alloca i32** ; [#uses=3] + %retval = alloca i32* ; [#uses=2] + %0 = alloca i32* ; [#uses=3] + %temp = alloca i32* ; [#uses=2] + %temp1 = alloca i32* ; [#uses=2] + %temp2 = alloca i32* ; [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store i32** %a2, i32*** %a2_addr + store i32** %b2, i32*** %b2_addr + %1 = load i32*** %a2_addr, align 8 ; [#uses=1] + %2 = load i32** %1, align 8 ; [#uses=1] + store i32* %2, i32** %temp, align 8 + %3 = load i32*** %b2_addr, align 8 ; [#uses=1] + %4 = load i32** %3, align 8 ; [#uses=1] + store i32* %4, i32** %temp1, align 8 + %5 = load i32** %temp1, align 8 ; [#uses=1] + %6 = load i32* %5, align 4 ; [#uses=1] + %7 = load i32** %temp, align 8 ; [#uses=1] + %8 = load i32* %7, align 4 ; [#uses=1] + %9 = icmp slt i32 %6, %8 ; [#uses=1] + br i1 %9, label %bb, label %bb1 + +bb: ; preds = %entry + %10 = load i32*** %b2_addr, align 8 ; [#uses=1] + %11 = load i32** %10, align 8 ; [#uses=1] + store i32* %11, i32** %0, align 8 + br label %bb2 + +bb1: ; preds = %entry + %12 = call noalias i8* @malloc(i64 4) nounwind ; [#uses=1] + %13 = bitcast i8* %12 to i32* ; [#uses=1] + store i32* %13, i32** %temp2, align 8 + store i32** %temp2, i32*** %a2_addr, align 8 + %14 = load i32*** %a2_addr, align 8 ; [#uses=1] + %15 = load i32** %14, align 8 ; [#uses=1] + store i32* %15, i32** %0, align 8 + br label %bb2 + +bb2: ; preds = %bb1, %bb + %16 = load i32** %0, align 8 ; [#uses=1] + store i32* %16, i32** %retval, align 8 + br label %return + +return: ; preds = %bb2 + %retval3 = load i32** %retval ; [#uses=1] + ret i32* %retval3 +} + +declare noalias i8* @malloc(i64) nounwind + +define void @func() nounwind { +entry: + %mem1 = alloca i32* ; [#uses=3] + %mem2 = alloca i32* ; [#uses=3] + %r1 = alloca i32 ; [#uses=2] + %r2 = alloca i32 ; [#uses=2] + %a1 = alloca i32* ; [#uses=1] + %b1 = alloca i32* ; [#uses=1] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store i32 5, i32* %r1, align 4 + store i32 6, i32* %r2, align 4 + store i32* %r1, i32** %mem1, align 8 + store i32* %r2, i32** %mem2, align 8 + %0 = call i32* @test(i32** %mem1, i32** %mem2) nounwind ; [#uses=1] + store i32* %0, i32** %a1, align 8 + %1 = call i32* @test(i32** %mem2, i32** %mem1) nounwind ; [#uses=1] + store i32* %1, i32** %b1, align 8 + br label %return + +return: ; preds = %entry + ret void +} Added: poolalloc/trunk/test/dsa/td/params1.c URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/td/params1.c?rev=112599&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/td/params1.c (added) +++ poolalloc/trunk/test/dsa/td/params1.c Tue Aug 31 09:37:24 2010 @@ -0,0 +1,39 @@ +//--Make sure we can run DSA on it! +//RUN: llvm-gcc %s -c --emit-llvm -o - | \ +//RUN: dsaopt -dsa-bu -dsa-td -disable-output + + +#include + +struct InfoStruct { + int count; + int valid; + float factor; +}; + +void initialize(struct InfoStruct **arr, int size) { + struct InfoStruct *temp = *arr; + while(temp < (*arr + size)) { + temp->count = 0; + temp->valid = 0; + temp->factor = 0.0; + temp++; + } +} + +void process(struct InfoStruct **arr, int loc, int count, float fact) { + + struct InfoStruct *ptr = *arr; + struct InfoStruct obj; + obj.count = count; + obj.factor = fact; + obj.valid = 1; + ptr[loc]=obj; +} + +int main() { + + struct InfoStruct* InfoArray= (struct InfoStruct*)malloc(sizeof(struct InfoStruct) * 10); + initialize(&InfoArray, 10); + process(&InfoArray, 4, 3, 5.5); +} Added: poolalloc/trunk/test/dsa/td/params1.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/td/params1.ll?rev=112599&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/td/params1.ll (added) +++ poolalloc/trunk/test/dsa/td/params1.ll Tue Aug 31 09:37:24 2010 @@ -0,0 +1,138 @@ +;RUN: dsaopt %s -dsa-local -analyze -check-same-node=initialize:temp:0,initialize:arr:0 +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "initialize:temp:0+IR" +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "initialize:arr+IRE" + +;RUN: dsaopt %s -dsa-bu -analyze -check-same-node=initialize:temp:0,initialize:arr:0 +;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "initialize:temp:0+IR" +;RUN: dsaopt %s -dsa-bu -analyze -verify-flags "initialize:arr+IRE" + +;RUN: dsaopt %s -dsa-td -analyze -check-same-node=initialize:temp:0,initialize:arr:0 +;RUN: dsaopt %s -dsa-td -analyze -verify-flags "initialize:temp:0+HIMR" +;RUN: dsaopt %s -dsa-td -analyze -verify-flags "initialize:arr+SIMRE" + +; ModuleID = 'params1.bc' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" + +%struct.InfoStruct = type { i32, i32, float } + +define void @initialize(%struct.InfoStruct** %arr, i32 %size) nounwind { +entry: + %arr_addr = alloca %struct.InfoStruct** ; <%struct.InfoStruct***> [#uses=3] + %size_addr = alloca i32 ; [#uses=2] + %temp = alloca %struct.InfoStruct* ; <%struct.InfoStruct**> [#uses=5] + %elem = alloca %struct.InfoStruct ; <%struct.InfoStruct*> [#uses=6] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store %struct.InfoStruct** %arr, %struct.InfoStruct*** %arr_addr + store i32 %size, i32* %size_addr + %0 = load %struct.InfoStruct*** %arr_addr, align 8 ; <%struct.InfoStruct**> [#uses=1] + %1 = load %struct.InfoStruct** %0, align 8 ; <%struct.InfoStruct*> [#uses=1] + store %struct.InfoStruct* %1, %struct.InfoStruct** %temp, align 8 + br label %bb1 + +bb: ; preds = %bb1 + %2 = load %struct.InfoStruct** %temp, align 8 ; <%struct.InfoStruct*> [#uses=3] + %3 = getelementptr inbounds %struct.InfoStruct* %elem, i32 0, i32 0 ; [#uses=1] + %4 = getelementptr inbounds %struct.InfoStruct* %2, i32 0, i32 0 ; [#uses=1] + %5 = load i32* %4, align 4 ; [#uses=1] + store i32 %5, i32* %3, align 4 + %6 = getelementptr inbounds %struct.InfoStruct* %elem, i32 0, i32 1 ; [#uses=1] + %7 = getelementptr inbounds %struct.InfoStruct* %2, i32 0, i32 1 ; [#uses=1] + %8 = load i32* %7, align 4 ; [#uses=1] + store i32 %8, i32* %6, align 4 + %9 = getelementptr inbounds %struct.InfoStruct* %elem, i32 0, i32 2 ; [#uses=1] + %10 = getelementptr inbounds %struct.InfoStruct* %2, i32 0, i32 2 ; [#uses=1] + %11 = load float* %10, align 4 ; [#uses=1] + store float %11, float* %9, align 4 + %12 = getelementptr inbounds %struct.InfoStruct* %elem, i32 0, i32 0 ; [#uses=1] + store i32 0, i32* %12, align 4 + %13 = getelementptr inbounds %struct.InfoStruct* %elem, i32 0, i32 1 ; [#uses=1] + store i32 0, i32* %13, align 4 + %14 = getelementptr inbounds %struct.InfoStruct* %elem, i32 0, i32 2 ; [#uses=1] + store float 0.000000e+00, float* %14, align 4 + %15 = load %struct.InfoStruct** %temp, align 8 ; <%struct.InfoStruct*> [#uses=1] + %16 = getelementptr inbounds %struct.InfoStruct* %15, i64 1 ; <%struct.InfoStruct*> [#uses=1] + store %struct.InfoStruct* %16, %struct.InfoStruct** %temp, align 8 + br label %bb1 + +bb1: ; preds = %bb, %entry + %17 = load %struct.InfoStruct*** %arr_addr, align 8 ; <%struct.InfoStruct**> [#uses=1] + %18 = load %struct.InfoStruct** %17, align 8 ; <%struct.InfoStruct*> [#uses=1] + %19 = load i32* %size_addr, align 4 ; [#uses=1] + %20 = sext i32 %19 to i64 ; [#uses=1] + %21 = getelementptr inbounds %struct.InfoStruct* %18, i64 %20 ; <%struct.InfoStruct*> [#uses=1] + %22 = load %struct.InfoStruct** %temp, align 8 ; <%struct.InfoStruct*> [#uses=1] + %23 = icmp ugt %struct.InfoStruct* %21, %22 ; [#uses=1] + br i1 %23, label %bb, label %bb2 + +bb2: ; preds = %bb1 + br label %return + +return: ; preds = %bb2 + ret void +} + +define void @process(%struct.InfoStruct** %arr, i32 %loc, i32 %count, float %fact) nounwind { +entry: + %arr_addr = alloca %struct.InfoStruct** ; <%struct.InfoStruct***> [#uses=2] + %loc_addr = alloca i32 ; [#uses=2] + %count_addr = alloca i32 ; [#uses=2] + %fact_addr = alloca float ; [#uses=2] + %ptr = alloca %struct.InfoStruct* ; <%struct.InfoStruct**> [#uses=2] + %obj = alloca %struct.InfoStruct ; <%struct.InfoStruct*> [#uses=6] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store %struct.InfoStruct** %arr, %struct.InfoStruct*** %arr_addr + store i32 %loc, i32* %loc_addr + store i32 %count, i32* %count_addr + store float %fact, float* %fact_addr + %0 = load %struct.InfoStruct*** %arr_addr, align 8 ; <%struct.InfoStruct**> [#uses=1] + %1 = load %struct.InfoStruct** %0, align 8 ; <%struct.InfoStruct*> [#uses=1] + store %struct.InfoStruct* %1, %struct.InfoStruct** %ptr, align 8 + %2 = load %struct.InfoStruct** %ptr, align 8 ; <%struct.InfoStruct*> [#uses=1] + %3 = load i32* %loc_addr, align 4 ; [#uses=1] + %4 = sext i32 %3 to i64 ; [#uses=1] + %5 = getelementptr inbounds %struct.InfoStruct* %2, i64 %4 ; <%struct.InfoStruct*> [#uses=3] + %6 = getelementptr inbounds %struct.InfoStruct* %obj, i32 0, i32 0 ; [#uses=1] + %7 = getelementptr inbounds %struct.InfoStruct* %5, i32 0, i32 0 ; [#uses=1] + %8 = load i32* %7, align 1 ; [#uses=1] + store i32 %8, i32* %6, align 1 + %9 = getelementptr inbounds %struct.InfoStruct* %obj, i32 0, i32 1 ; [#uses=1] + %10 = getelementptr inbounds %struct.InfoStruct* %5, i32 0, i32 1 ; [#uses=1] + %11 = load i32* %10, align 1 ; [#uses=1] + store i32 %11, i32* %9, align 1 + %12 = getelementptr inbounds %struct.InfoStruct* %obj, i32 0, i32 2 ; [#uses=1] + %13 = getelementptr inbounds %struct.InfoStruct* %5, i32 0, i32 2 ; [#uses=1] + %14 = load float* %13, align 1 ; [#uses=1] + store float %14, float* %12, align 1 + %15 = getelementptr inbounds %struct.InfoStruct* %obj, i32 0, i32 0 ; [#uses=1] + %16 = load i32* %count_addr, align 4 ; [#uses=1] + store i32 %16, i32* %15, align 4 + %17 = getelementptr inbounds %struct.InfoStruct* %obj, i32 0, i32 2 ; [#uses=1] + %18 = load float* %fact_addr, align 4 ; [#uses=1] + store float %18, float* %17, align 4 + %19 = getelementptr inbounds %struct.InfoStruct* %obj, i32 0, i32 1 ; [#uses=1] + store i32 1, i32* %19, align 4 + br label %return + +return: ; preds = %entry + ret void +} + +define i32 @main() nounwind { +entry: + %retval = alloca i32 ; [#uses=1] + %InfoArray = alloca %struct.InfoStruct* ; <%struct.InfoStruct**> [#uses=3] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + %0 = call noalias i8* @malloc(i64 120) nounwind ; [#uses=1] + %1 = bitcast i8* %0 to %struct.InfoStruct* ; <%struct.InfoStruct*> [#uses=1] + store %struct.InfoStruct* %1, %struct.InfoStruct** %InfoArray, align 8 + call void @initialize(%struct.InfoStruct** %InfoArray, i32 10) nounwind + call void @process(%struct.InfoStruct** %InfoArray, i32 4, i32 3, float 5.500000e+00) nounwind + br label %return + +return: ; preds = %entry + %retval1 = load i32* %retval ; [#uses=1] + ret i32 %retval1 +} + +declare noalias i8* @malloc(i64) nounwind Added: poolalloc/trunk/test/dsa/td/params2.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/td/params2.ll?rev=112599&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/td/params2.ll (added) +++ poolalloc/trunk/test/dsa/td/params2.ll Tue Aug 31 09:37:24 2010 @@ -0,0 +1,115 @@ +; ModuleID = 'params2.bc' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" + +%struct.InfoStruct = type { i32, i32, float } + +define void @initialize(%struct.InfoStruct** %arr, i32 %size) nounwind { +entry: + %arr_addr = alloca %struct.InfoStruct** ; <%struct.InfoStruct***> [#uses=3] + %size_addr = alloca i32 ; [#uses=2] + %temp = alloca %struct.InfoStruct* ; <%struct.InfoStruct**> [#uses=7] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store %struct.InfoStruct** %arr, %struct.InfoStruct*** %arr_addr + store i32 %size, i32* %size_addr + %0 = load %struct.InfoStruct*** %arr_addr, align 8 ; <%struct.InfoStruct**> [#uses=1] + %1 = load %struct.InfoStruct** %0, align 8 ; <%struct.InfoStruct*> [#uses=1] + store %struct.InfoStruct* %1, %struct.InfoStruct** %temp, align 8 + br label %bb1 + +bb: ; preds = %bb1 + %2 = load %struct.InfoStruct** %temp, align 8 ; <%struct.InfoStruct*> [#uses=1] + %3 = getelementptr inbounds %struct.InfoStruct* %2, i32 0, i32 0 ; [#uses=1] + store i32 0, i32* %3, align 4 + %4 = load %struct.InfoStruct** %temp, align 8 ; <%struct.InfoStruct*> [#uses=1] + %5 = getelementptr inbounds %struct.InfoStruct* %4, i32 0, i32 1 ; [#uses=1] + store i32 0, i32* %5, align 4 + %6 = load %struct.InfoStruct** %temp, align 8 ; <%struct.InfoStruct*> [#uses=1] + %7 = getelementptr inbounds %struct.InfoStruct* %6, i32 0, i32 2 ; [#uses=1] + store float 0.000000e+00, float* %7, align 4 + %8 = load %struct.InfoStruct** %temp, align 8 ; <%struct.InfoStruct*> [#uses=1] + %9 = getelementptr inbounds %struct.InfoStruct* %8, i64 1 ; <%struct.InfoStruct*> [#uses=1] + store %struct.InfoStruct* %9, %struct.InfoStruct** %temp, align 8 + br label %bb1 + +bb1: ; preds = %bb, %entry + %10 = load %struct.InfoStruct*** %arr_addr, align 8 ; <%struct.InfoStruct**> [#uses=1] + %11 = load %struct.InfoStruct** %10, align 8 ; <%struct.InfoStruct*> [#uses=1] + %12 = load i32* %size_addr, align 4 ; [#uses=1] + %13 = sext i32 %12 to i64 ; [#uses=1] + %14 = getelementptr inbounds %struct.InfoStruct* %11, i64 %13 ; <%struct.InfoStruct*> [#uses=1] + %15 = load %struct.InfoStruct** %temp, align 8 ; <%struct.InfoStruct*> [#uses=1] + %16 = icmp ugt %struct.InfoStruct* %14, %15 ; [#uses=1] + br i1 %16, label %bb, label %bb2 + +bb2: ; preds = %bb1 + br label %return + +return: ; preds = %bb2 + ret void +} + +define void @process(%struct.InfoStruct** %arr, i32 %loc, i32 %count, float %fact) nounwind { +entry: + %arr_addr = alloca %struct.InfoStruct** ; <%struct.InfoStruct***> [#uses=2] + %loc_addr = alloca i32 ; [#uses=2] + %count_addr = alloca i32 ; [#uses=2] + %fact_addr = alloca float ; [#uses=2] + %ptr = alloca %struct.InfoStruct* ; <%struct.InfoStruct**> [#uses=2] + %obj = alloca %struct.InfoStruct ; <%struct.InfoStruct*> [#uses=6] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store %struct.InfoStruct** %arr, %struct.InfoStruct*** %arr_addr + store i32 %loc, i32* %loc_addr + store i32 %count, i32* %count_addr + store float %fact, float* %fact_addr + %0 = load %struct.InfoStruct*** %arr_addr, align 8 ; <%struct.InfoStruct**> [#uses=1] + %1 = load %struct.InfoStruct** %0, align 8 ; <%struct.InfoStruct*> [#uses=1] + store %struct.InfoStruct* %1, %struct.InfoStruct** %ptr, align 8 + %2 = getelementptr inbounds %struct.InfoStruct* %obj, i32 0, i32 0 ; [#uses=1] + %3 = load i32* %count_addr, align 4 ; [#uses=1] + store i32 %3, i32* %2, align 4 + %4 = getelementptr inbounds %struct.InfoStruct* %obj, i32 0, i32 2 ; [#uses=1] + %5 = load float* %fact_addr, align 4 ; [#uses=1] + store float %5, float* %4, align 4 + %6 = getelementptr inbounds %struct.InfoStruct* %obj, i32 0, i32 1 ; [#uses=1] + store i32 1, i32* %6, align 4 + %7 = load %struct.InfoStruct** %ptr, align 8 ; <%struct.InfoStruct*> [#uses=1] + %8 = load i32* %loc_addr, align 4 ; [#uses=1] + %9 = sext i32 %8 to i64 ; [#uses=1] + %10 = getelementptr inbounds %struct.InfoStruct* %7, i64 %9 ; <%struct.InfoStruct*> [#uses=3] + %11 = getelementptr inbounds %struct.InfoStruct* %10, i32 0, i32 0 ; [#uses=1] + %12 = getelementptr inbounds %struct.InfoStruct* %obj, i32 0, i32 0 ; [#uses=1] + %13 = load i32* %12, align 1 ; [#uses=1] + store i32 %13, i32* %11, align 1 + %14 = getelementptr inbounds %struct.InfoStruct* %10, i32 0, i32 1 ; [#uses=1] + %15 = getelementptr inbounds %struct.InfoStruct* %obj, i32 0, i32 1 ; [#uses=1] + %16 = load i32* %15, align 1 ; [#uses=1] + store i32 %16, i32* %14, align 1 + %17 = getelementptr inbounds %struct.InfoStruct* %10, i32 0, i32 2 ; [#uses=1] + %18 = getelementptr inbounds %struct.InfoStruct* %obj, i32 0, i32 2 ; [#uses=1] + %19 = load float* %18, align 1 ; [#uses=1] + store float %19, float* %17, align 1 + br label %return + +return: ; preds = %entry + ret void +} + +define i32 @main() nounwind { +entry: + %retval = alloca i32 ; [#uses=1] + %InfoArray = alloca %struct.InfoStruct* ; <%struct.InfoStruct**> [#uses=3] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + %0 = call noalias i8* @malloc(i64 120) nounwind ; [#uses=1] + %1 = bitcast i8* %0 to %struct.InfoStruct* ; <%struct.InfoStruct*> [#uses=1] + store %struct.InfoStruct* %1, %struct.InfoStruct** %InfoArray, align 8 + call void @initialize(%struct.InfoStruct** %InfoArray, i32 10) nounwind + call void @process(%struct.InfoStruct** %InfoArray, i32 4, i32 3, float 5.500000e+00) nounwind + br label %return + +return: ; preds = %entry + %retval1 = load i32* %retval ; [#uses=1] + ret i32 %retval1 +} + +declare noalias i8* @malloc(i64) nounwind Added: poolalloc/trunk/test/dsa/td/recur.c URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/td/recur.c?rev=112599&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/td/recur.c (added) +++ poolalloc/trunk/test/dsa/td/recur.c Tue Aug 31 09:37:24 2010 @@ -0,0 +1,27 @@ +//--Make sure we can run DSA on it! +//RUN: llvm-gcc %s -c --emit-llvm -o - | \ +//RUN: dsaopt -dsa-bu -dsa-td -disable-output + + +#include + + +int* test() { + int* a2 = (int*)malloc(sizeof(int)); + *a2 = 10; + + if(*a2 > 5 ) { + return test(); + } + + int *b2 = (int*)malloc(sizeof(int)); + return b2; + +} + +void func() { + + int *a1 = test(); + int *b1 = test(); +} + Added: poolalloc/trunk/test/dsa/td/recur.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/td/recur.ll?rev=112599&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/td/recur.ll (added) +++ poolalloc/trunk/test/dsa/td/recur.ll Tue Aug 31 09:37:24 2010 @@ -0,0 +1,63 @@ +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "test:b2:0+HI" +;RUN: dsaopt %s -dsa-td -analyze -verify-flags "test:b2:0+HIM" + +; ModuleID = 'recur.bc' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" + +define i32* @test() nounwind { +entry: + %retval = alloca i32* ; [#uses=2] + %0 = alloca i32* ; [#uses=3] + %a2 = alloca i32* ; [#uses=3] + %b2 = alloca i32* ; [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + %1 = call noalias i8* @malloc(i64 4) nounwind ; [#uses=1] + %2 = bitcast i8* %1 to i32* ; [#uses=1] + store i32* %2, i32** %a2, align 8 + %3 = load i32** %a2, align 8 ; [#uses=1] + store i32 10, i32* %3, align 4 + %4 = load i32** %a2, align 8 ; [#uses=1] + %5 = load i32* %4, align 4 ; [#uses=1] + %6 = icmp sgt i32 %5, 5 ; [#uses=1] + br i1 %6, label %bb, label %bb1 + +bb: ; preds = %entry + %7 = call i32* @test() nounwind ; [#uses=1] + store i32* %7, i32** %0, align 8 + br label %bb2 + +bb1: ; preds = %entry + %8 = call noalias i8* @malloc(i64 4) nounwind ; [#uses=1] + %9 = bitcast i8* %8 to i32* ; [#uses=1] + store i32* %9, i32** %b2, align 8 + %10 = load i32** %b2, align 8 ; [#uses=1] + store i32* %10, i32** %0, align 8 + br label %bb2 + +bb2: ; preds = %bb1, %bb + %11 = load i32** %0, align 8 ; [#uses=1] + store i32* %11, i32** %retval, align 8 + br label %return + +return: ; preds = %bb2 + %retval3 = load i32** %retval ; [#uses=1] + ret i32* %retval3 +} + +declare noalias i8* @malloc(i64) nounwind + +define void @func() nounwind { +entry: + %a1 = alloca i32* ; [#uses=1] + %b1 = alloca i32* ; [#uses=1] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + %0 = call i32* @test() nounwind ; [#uses=1] + store i32* %0, i32** %a1, align 8 + %1 = call i32* @test() nounwind ; [#uses=1] + store i32* %1, i32** %b1, align 8 + br label %return + +return: ; preds = %entry + ret void +} Added: poolalloc/trunk/test/dsa/td/recur1.c URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/td/recur1.c?rev=112599&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/td/recur1.c (added) +++ poolalloc/trunk/test/dsa/td/recur1.c Tue Aug 31 09:37:24 2010 @@ -0,0 +1,30 @@ +//--Make sure we can run DSA on it! +//RUN: llvm-gcc %s -c --emit-llvm -o - | \ +//RUN: dsaopt -dsa-bu -dsa-td -disable-output + + +#include + +int*test1(int *b3) { + return b3+1; +} + +int* test() { + int* a2 = (int*)malloc(sizeof(int)); + *a2 = 10; + + if(*a2 > 5 ) { + return test(); + } + + int *b2 = (int*)malloc(sizeof(int)); + return test1(b2); + +} + +void func() { + + int *a1 = test(); + int *b1 = test(); +} + Added: poolalloc/trunk/test/dsa/td/recur1.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/td/recur1.ll?rev=112599&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/td/recur1.ll (added) +++ poolalloc/trunk/test/dsa/td/recur1.ll Tue Aug 31 09:37:24 2010 @@ -0,0 +1,83 @@ +;RUN: dsaopt %s -dsa-td -analyze -verify-flags "test:b2:0+HM" +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "test:b2:0+HI" + +; ModuleID = 'recur1.bc' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" + +define i32* @test1(i32* %b3) nounwind { +entry: + %b3_addr = alloca i32* ; [#uses=2] + %retval = alloca i32* ; [#uses=2] + %0 = alloca i32* ; [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store i32* %b3, i32** %b3_addr + %1 = load i32** %b3_addr, align 8 ; [#uses=1] + %2 = getelementptr inbounds i32* %1, i64 1 ; [#uses=1] + store i32* %2, i32** %0, align 8 + %3 = load i32** %0, align 8 ; [#uses=1] + store i32* %3, i32** %retval, align 8 + br label %return + +return: ; preds = %entry + %retval1 = load i32** %retval ; [#uses=1] + ret i32* %retval1 +} + +define i32* @test() nounwind { +entry: + %retval = alloca i32* ; [#uses=2] + %0 = alloca i32* ; [#uses=3] + %a2 = alloca i32* ; [#uses=3] + %b2 = alloca i32* ; [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + %1 = call noalias i8* @malloc(i64 4) nounwind ; [#uses=1] + %2 = bitcast i8* %1 to i32* ; [#uses=1] + store i32* %2, i32** %a2, align 8 + %3 = load i32** %a2, align 8 ; [#uses=1] + store i32 10, i32* %3, align 4 + %4 = load i32** %a2, align 8 ; [#uses=1] + %5 = load i32* %4, align 4 ; [#uses=1] + %6 = icmp sgt i32 %5, 5 ; [#uses=1] + br i1 %6, label %bb, label %bb1 + +bb: ; preds = %entry + %7 = call i32* @test() nounwind ; [#uses=1] + store i32* %7, i32** %0, align 8 + br label %bb2 + +bb1: ; preds = %entry + %8 = call noalias i8* @malloc(i64 4) nounwind ; [#uses=1] + %9 = bitcast i8* %8 to i32* ; [#uses=1] + store i32* %9, i32** %b2, align 8 + %10 = load i32** %b2, align 8 ; [#uses=1] + %11 = call i32* @test1(i32* %10) nounwind ; [#uses=1] + store i32* %11, i32** %0, align 8 + br label %bb2 + +bb2: ; preds = %bb1, %bb + %12 = load i32** %0, align 8 ; [#uses=1] + store i32* %12, i32** %retval, align 8 + br label %return + +return: ; preds = %bb2 + %retval3 = load i32** %retval ; [#uses=1] + ret i32* %retval3 +} + +declare noalias i8* @malloc(i64) nounwind + +define void @func() nounwind { +entry: + %a1 = alloca i32* ; [#uses=1] + %b1 = alloca i32* ; [#uses=1] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + %0 = call i32* @test() nounwind ; [#uses=1] + store i32* %0, i32** %a1, align 8 + %1 = call i32* @test() nounwind ; [#uses=1] + store i32* %1, i32** %b1, align 8 + br label %return + +return: ; preds = %entry + ret void +} Added: poolalloc/trunk/test/dsa/td/recur2.c URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/td/recur2.c?rev=112599&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/td/recur2.c (added) +++ poolalloc/trunk/test/dsa/td/recur2.c Tue Aug 31 09:37:24 2010 @@ -0,0 +1,31 @@ +//--Make sure we can run DSA on it! +//RUN: llvm-gcc %s -c --emit-llvm -o - | \ +//RUN: dsaopt -dsa-bu -dsa-td -disable-output + + +#include +int* test1(int*); + +int* test() { + int* a2 = (int*)malloc(sizeof(int)); + *a2 = 10; + + if(*a2 > 5 ) { + return test(); + } + + int *b2 = (int*)malloc(sizeof(int)); + return test1(b2); + +} + +int*test1(int *b3) { + return test()+*b3; +} + +void func() { + + int *a1 = test(); + int *b1 = test(); +} + Added: poolalloc/trunk/test/dsa/td/recur2.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/td/recur2.ll?rev=112599&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/td/recur2.ll (added) +++ poolalloc/trunk/test/dsa/td/recur2.ll Tue Aug 31 09:37:24 2010 @@ -0,0 +1,86 @@ +;RUN: dsaopt %s -dsa-td -analyze -verify-flags "test:b2:0+HM" +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "test:b2:0+HI" + +; ModuleID = 'recur2.bc' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" + +define i32* @test() nounwind { +entry: + %retval = alloca i32* ; [#uses=2] + %0 = alloca i32* ; [#uses=3] + %a2 = alloca i32* ; [#uses=3] + %b2 = alloca i32* ; [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + %1 = call noalias i8* @malloc(i64 4) nounwind ; [#uses=1] + %2 = bitcast i8* %1 to i32* ; [#uses=1] + store i32* %2, i32** %a2, align 8 + %3 = load i32** %a2, align 8 ; [#uses=1] + store i32 10, i32* %3, align 4 + %4 = load i32** %a2, align 8 ; [#uses=1] + %5 = load i32* %4, align 4 ; [#uses=1] + %6 = icmp sgt i32 %5, 5 ; [#uses=1] + br i1 %6, label %bb, label %bb1 + +bb: ; preds = %entry + %7 = call i32* @test() nounwind ; [#uses=1] + store i32* %7, i32** %0, align 8 + br label %bb2 + +bb1: ; preds = %entry + %8 = call noalias i8* @malloc(i64 4) nounwind ; [#uses=1] + %9 = bitcast i8* %8 to i32* ; [#uses=1] + store i32* %9, i32** %b2, align 8 + %10 = load i32** %b2, align 8 ; [#uses=1] + %11 = call i32* @test1(i32* %10) nounwind ; [#uses=1] + store i32* %11, i32** %0, align 8 + br label %bb2 + +bb2: ; preds = %bb1, %bb + %12 = load i32** %0, align 8 ; [#uses=1] + store i32* %12, i32** %retval, align 8 + br label %return + +return: ; preds = %bb2 + %retval3 = load i32** %retval ; [#uses=1] + ret i32* %retval3 +} + +declare noalias i8* @malloc(i64) nounwind + +define i32* @test1(i32* %b3) nounwind { +entry: + %b3_addr = alloca i32* ; [#uses=2] + %retval = alloca i32* ; [#uses=2] + %0 = alloca i32* ; [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store i32* %b3, i32** %b3_addr + %1 = call i32* @test() nounwind ; [#uses=1] + %2 = load i32** %b3_addr, align 8 ; [#uses=1] + %3 = load i32* %2, align 4 ; [#uses=1] + %4 = sext i32 %3 to i64 ; [#uses=1] + %5 = getelementptr inbounds i32* %1, i64 %4 ; [#uses=1] + store i32* %5, i32** %0, align 8 + %6 = load i32** %0, align 8 ; [#uses=1] + store i32* %6, i32** %retval, align 8 + br label %return + +return: ; preds = %entry + %retval1 = load i32** %retval ; [#uses=1] + ret i32* %retval1 +} + +define void @func() nounwind { +entry: + %a1 = alloca i32* ; [#uses=1] + %b1 = alloca i32* ; [#uses=1] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + %0 = call i32* @test() nounwind ; [#uses=1] + store i32* %0, i32** %a1, align 8 + %1 = call i32* @test() nounwind ; [#uses=1] + store i32* %1, i32** %b1, align 8 + br label %return + +return: ; preds = %entry + ret void +} Added: poolalloc/trunk/test/dsa/td/recur3.c URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/td/recur3.c?rev=112599&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/td/recur3.c (added) +++ poolalloc/trunk/test/dsa/td/recur3.c Tue Aug 31 09:37:24 2010 @@ -0,0 +1,34 @@ +//--Make sure we can run DSA on it! +//RUN: llvm-gcc %s -c --emit-llvm -o - | \ +//RUN: dsaopt -dsa-bu -dsa-td -disable-output + + +#include +int* test1(int*); + +int* test() { + int* a2 = (int*)malloc(sizeof(int)); + *a2 = 10; + + if(*a2 > 5 ) { + return test(); + } + + int *b2 = (int*)malloc(sizeof(int)); + return test1(b2); + +} + +int*test1(int *b3) { + return test()+*b3; +} + +int *test2(int *b4) { + return test() + *b4; +} +void func() { + + int *a1 = test(); + int *b1 = test(); +} + Added: poolalloc/trunk/test/dsa/td/testcase.c URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/td/testcase.c?rev=112599&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/td/testcase.c (added) +++ poolalloc/trunk/test/dsa/td/testcase.c Tue Aug 31 09:37:24 2010 @@ -0,0 +1,19 @@ +//--Make sure we can run DSA on it! +//RUN: llvm-gcc %s -c --emit-llvm -o - | \ +//RUN: dsaopt -dsa-bu -dsa-td -disable-output + + +#include + + +int* test() { + int* a2 = (int*)malloc(sizeof(int)); + return a2; + +} + +void func() { + + int *a1 = test(); +} + Added: poolalloc/trunk/test/dsa/td/testcase.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/td/testcase.ll?rev=112599&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/td/testcase.ll (added) +++ poolalloc/trunk/test/dsa/td/testcase.ll Tue Aug 31 09:37:24 2010 @@ -0,0 +1,40 @@ +;RUN: dsaopt %s -dsa-local -analyze -verify-flags "func:a1:0+I" +;RUN: dsaopt %s -dsa-td -analyze -verify-flags "func:a1:0+HM-I" + +; ModuleID = 'testcase.bc' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" + +define i32* @test() nounwind { +entry: + %retval = alloca i32* ; [#uses=2] + %0 = alloca i32* ; [#uses=2] + %a2 = alloca i32* ; [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + %1 = call noalias i8* @malloc(i64 4) nounwind ; [#uses=1] + %2 = bitcast i8* %1 to i32* ; [#uses=1] + store i32* %2, i32** %a2, align 8 + %3 = load i32** %a2, align 8 ; [#uses=1] + store i32* %3, i32** %0, align 8 + %4 = load i32** %0, align 8 ; [#uses=1] + store i32* %4, i32** %retval, align 8 + br label %return + +return: ; preds = %entry + %retval1 = load i32** %retval ; [#uses=1] + ret i32* %retval1 +} + +declare noalias i8* @malloc(i64) nounwind + +define void @func() nounwind { +entry: + %a1 = alloca i32* ; [#uses=1] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + %0 = call i32* @test() nounwind ; [#uses=1] + store i32* %0, i32** %a1, align 8 + br label %return + +return: ; preds = %entry + ret void +} From daniel at zuster.org Tue Aug 31 10:00:18 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Tue, 31 Aug 2010 15:00:18 -0000 Subject: [llvm-commits] [test-suite] r112601 - /test-suite/trunk/MultiSource/Benchmarks/Bullet/Makefile Message-ID: <20100831150018.1A93F2A6C12C@llvm.org> Author: ddunbar Date: Tue Aug 31 10:00:17 2010 New Revision: 112601 URL: http://llvm.org/viewvc/llvm-project?rev=112601&view=rev Log: Increase Bullet time limit, it is hitting it at -O0 -g for ARMv7. Modified: test-suite/trunk/MultiSource/Benchmarks/Bullet/Makefile Modified: test-suite/trunk/MultiSource/Benchmarks/Bullet/Makefile URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/MultiSource/Benchmarks/Bullet/Makefile?rev=112601&r1=112600&r2=112601&view=diff ============================================================================== --- test-suite/trunk/MultiSource/Benchmarks/Bullet/Makefile (original) +++ test-suite/trunk/MultiSource/Benchmarks/Bullet/Makefile Tue Aug 31 10:00:17 2010 @@ -4,7 +4,7 @@ LDFLAGS = -lstdc++ -lm # This test can take more than the default 500s timeout on Thumb1 -RUNTIMELIMIT:=750 +RUNTIMELIMIT:=850 include $(LEVEL)/Makefile.config From clattner at apple.com Tue Aug 31 12:00:30 2010 From: clattner at apple.com (Chris Lattner) Date: Tue, 31 Aug 2010 10:00:30 -0700 Subject: [llvm-commits] [llvm] r112582 - /llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp In-Reply-To: <20100831055305.42B902A6C12C@llvm.org> References: <20100831055305.42B902A6C12C@llvm.org> Message-ID: On Aug 30, 2010, at 10:53 PM, Nick Lewycky wrote: > Author: nicholas > Date: Tue Aug 31 00:53:05 2010 > New Revision: 112582 > > URL: http://llvm.org/viewvc/llvm-project?rev=112582&view=rev > Log: > Switch to DenseSet, simplifying much more code. We now have a single iteration > where we hash, compare and fold, instead of one iteration where we build up > the hash buckets and a second one to fold. Looks great. I'd suggest changing: > + typedef DenseSet FnSetType; > + FnSetType FnSet; to: > + typedef DenseSet FnSetType; > + FnSetType FnSet; Storing them by-value prevents having to separately new/delete them, and means you can define the hashing stuff as a trait instead of having to name it. -Chris From rjmccall at apple.com Tue Aug 31 12:01:16 2010 From: rjmccall at apple.com (John McCall) Date: Tue, 31 Aug 2010 10:01:16 -0700 Subject: [llvm-commits] [llvm] r112597 - in /llvm/trunk: include/llvm/CodeGen/Passes.h lib/CodeGen/DwarfEHPrepare.cpp lib/CodeGen/LLVMTargetMachine.cpp In-Reply-To: <20100831090507.174362A6C12E@llvm.org> References: <20100831090507.174362A6C12E@llvm.org> Message-ID: On Aug 31, 2010, at 2:05 AM, Duncan Sands wrote: > Author: baldrick > Date: Tue Aug 31 04:05:06 2010 > New Revision: 112597 > > URL: http://llvm.org/viewvc/llvm-project?rev=112597&view=rev > Log: > Stop using the dom frontier in DwarfEHPrepare by not promoting alloca's > any more. I plan to reimplement alloca promotion using SSAUpdater later. > It looks like Bill's URoR logic really always needs domtree, so the pass > now always asks for domtree info. I've brought this up with Bill before, but it really doesn't need domtree; dominance is the wrong analysis for this task. The question is reachability. John. From clattner at apple.com Tue Aug 31 12:02:45 2010 From: clattner at apple.com (Chris Lattner) Date: Tue, 31 Aug 2010 10:02:45 -0700 Subject: [llvm-commits] [llvm] r112597 - in /llvm/trunk: include/llvm/CodeGen/Passes.h lib/CodeGen/DwarfEHPrepare.cpp lib/CodeGen/LLVMTargetMachine.cpp In-Reply-To: <20100831090507.174362A6C12E@llvm.org> References: <20100831090507.174362A6C12E@llvm.org> Message-ID: <1236C0A7-06E9-45F2-91D6-F6FFB1270D88@apple.com> On Aug 31, 2010, at 2:05 AM, Duncan Sands wrote: > Author: baldrick > Date: Tue Aug 31 04:05:06 2010 > New Revision: 112597 > > URL: http://llvm.org/viewvc/llvm-project?rev=112597&view=rev > Log: > Stop using the dom frontier in DwarfEHPrepare by not promoting alloca's > any more. I plan to reimplement alloca promotion using SSAUpdater later. > It looks like Bill's URoR logic really always needs domtree, so the pass > now always asks for domtree info. Works for me, thanks Duncan! -Chris From benny.kra at googlemail.com Tue Aug 31 12:03:33 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Tue, 31 Aug 2010 17:03:33 -0000 Subject: [llvm-commits] [llvm] r112605 - /llvm/trunk/lib/MC/ELFObjectWriter.cpp Message-ID: <20100831170333.C6B892A6C12C@llvm.org> Author: d0k Date: Tue Aug 31 12:03:33 2010 New Revision: 112605 URL: http://llvm.org/viewvc/llvm-project?rev=112605&view=rev Log: Allow creation of SHT_NULL sections, from Roman Divacky. Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=112605&r1=112604&r2=112605&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Tue Aug 31 12:03:33 2010 @@ -919,6 +919,7 @@ case ELF::SHT_PROGBITS: case ELF::SHT_STRTAB: case ELF::SHT_NOBITS: + case ELF::SHT_NULL: // Nothing to do. break; From clattner at apple.com Tue Aug 31 12:11:19 2010 From: clattner at apple.com (Chris Lattner) Date: Tue, 31 Aug 2010 10:11:19 -0700 Subject: [llvm-commits] [llvm] r112594 - /llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp In-Reply-To: <20100831075556.C9F7B2A6C12D@llvm.org> References: <20100831075556.C9F7B2A6C12D@llvm.org> Message-ID: <23312749-654B-40AB-9E60-DDCBCA597567@apple.com> On Aug 31, 2010, at 12:55 AM, Owen Anderson wrote: > Author: resistor > Date: Tue Aug 31 02:55:56 2010 > New Revision: 112594 > > URL: http://llvm.org/viewvc/llvm-project?rev=112594&view=rev > Log: > Don't perform an extra traversal of the function just to do cleanup. We can safely simplify instructions after each block has been processed without worrying about iterator invalidation. Should this only be done if(Changed)? If not, you need to make sure to keep Changed up to date if simplify changes the block. -Chris > > Modified: > llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp > > Modified: llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp?rev=112594&r1=112593&r2=112594&view=diff > ============================================================================== > --- llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp (original) > +++ llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp Tue Aug 31 02:55:56 2010 > @@ -102,7 +102,7 @@ > > bool Changed = false; > > - for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI) > + for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI) { > for (BasicBlock::iterator BI = FI->begin(), BE = FI->end(); BI != BE; ) { > Instruction *II = BI++; > if (SelectInst *SI = dyn_cast(II)) > @@ -110,10 +110,9 @@ > else if (PHINode *P = dyn_cast(II)) > Changed |= processPHI(P); > } > - > - if (Changed) > - for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI) > - SimplifyInstructionsInBlock(FI); > + > + SimplifyInstructionsInBlock(FI); > + } > > return Changed; > } > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From clattner at apple.com Tue Aug 31 12:22:42 2010 From: clattner at apple.com (Chris Lattner) Date: Tue, 31 Aug 2010 10:22:42 -0700 Subject: [llvm-commits] [llvm] r112589 - in /llvm/trunk: lib/Transforms/Scalar/JumpThreading.cpp test/Transforms/JumpThreading/2010-08-31-InfiniteRecursion.ll In-Reply-To: <20100831073635.272B62A6C12D@llvm.org> References: <20100831073635.272B62A6C12D@llvm.org> Message-ID: On Aug 31, 2010, at 12:36 AM, Owen Anderson wrote: > Author: resistor > Date: Tue Aug 31 02:36:34 2010 > New Revision: 112589 > > URL: http://llvm.org/viewvc/llvm-project?rev=112589&view=rev > Log: > More Chris-inspired JumpThreading fixes: use ConstantExpr to correctly constant-fold undef, and be more careful with its return value. > This actually exposed an infinite recursion bug in ComputeValueKnownInPredecessors which theoretically already existed (in JumpThreading's > handling of and/or of i1's), but never manifested before. This patch adds a tracking set to prevent this case. Thanks. > @@ -270,12 +271,17 @@ > /// > bool JumpThreading:: > ComputeValueKnownInPredecessors(Value *V, BasicBlock *BB,PredValueInfo &Result){ > + if (!RecursionSet.insert(std::make_pair(V, BB)).second) > + return false; Please add a comment explaining what this is about. > + > // If V is a constantint, then it is known in all predecessors. > if (isa(V) || isa(V)) { > ConstantInt *CI = dyn_cast(V); > > for (pred_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI) > Result.push_back(std::make_pair(CI, *PI)); > + > + RecursionSet.erase(std::make_pair(V, BB)); > return true; You do this in many places throughout the function, please replace the insert/erase pair with an RAII object. Otherwise, it will certainly get unbalanced someday. > @@ -382,38 +399,48 @@ > // Try to simplify some other binary operator values. > } else if (BinaryOperator *BO = dyn_cast(I)) { > ConstantInt *CI = dyn_cast(BO->getOperand(1)); > + if (CI) { You can put the dyn_cast in the 'if'. > SmallVector, 8> LHSVals; > ComputeValueKnownInPredecessors(BO->getOperand(0), BB, LHSVals); > + > + // Try to use constant folding to simplify the binary operator. > + for (unsigned i = 0, e = LHSVals.size(); i != e; ++i) { > + Constant *Folded = 0; > if (LHSVals[i].first == 0) { > + Folded = ConstantExpr::get(BO->getOpcode(), > + UndefValue::get(BO->getType()), > + CI); > + } else { > + Folded = ConstantExpr::get(BO->getOpcode(), LHSVals[i].first, CI); > } Please factor this better, you're duplicating a bunch of code. The key part of this is something like: Value *V = LHSVals[i].first ? LHSVals[i].first : UndefValue::get(BO->getType()); Strive for minimality, if you find yourself duplicating code, "something is wrong". > + // Try to find a constant value for the LHS of a comparison, > // and evaluate it statically if we can. > if (Constant *CmpConst = dyn_cast(Cmp->getOperand(1))) { > SmallVector, 8> LHSVals; > ComputeValueKnownInPredecessors(I->getOperand(0), BB, LHSVals); > > for (unsigned i = 0, e = LHSVals.size(); i != e; ++i) { > + Constant * Folded = 0; > if (LHSVals[i].first == 0) > + Folded = ConstantExpr::getCompare(Cmp->getPredicate(), > + UndefValue::get(CmpConst->getType()), CmpConst); > + else > + Folded = ConstantExpr::getCompare(Cmp->getPredicate(), > + LHSVals[i].first, CmpConst); Needless repetition again. > + > + if (ConstantInt *FoldedCInt = dyn_cast(Folded)) > + Result.push_back(std::make_pair(FoldedCInt, LHSVals[i].second)); > + else if (isa(Folded)) > + Result.push_back(std::make_pair((ConstantInt*)0,LHSVals[i].second)); This pattern is occurring enough that it is probably also worth factoring out to a static helper function. > } > > + RecursionSet.erase(std::make_pair(V, BB)); > return !Result.empty(); > } > } > @@ -505,9 +540,11 @@ > Result.push_back(std::make_pair(CInt, *PI)); > } > > + RecursionSet.erase(std::make_pair(V, BB)); > return !Result.empty(); > } > > + RecursionSet.erase(std::make_pair(V, BB)); > return false; > } Ick. > @@ -1126,8 +1163,9 @@ > return false; > > SmallVector, 8> PredValues; > - if (!ComputeValueKnownInPredecessors(Cond, BB, PredValues)) > + if (!ComputeValueKnownInPredecessors(Cond, BB, PredValues)) { > return false; > + } this isn't needed :) > +++ llvm/trunk/test/Transforms/JumpThreading/2010-08-31-InfiniteRecursion.ll Tue Aug 31 02:36:34 2010 I appreciate the testcase, but: 1) please hand minimizing it. Bugpoint is a useful tool to get the testcase started, it is not the one true answer for providing testcases you can just throw in the testsuite. 2) when you get it smaller, please add it to Transforms/JumpThreading/crash.ll 3) I'm still waiting for testcases for all the other stuff you added to jump threading. You claim that they do useful things, prove it with minimal testcases. There are lots of examples showing this for other things in jumpthreading, it is *very* important that you add them. If you don't, I will eventually come back and rip out the code, see that nothing breaks in the testsuite, and we'll regress. Please document every major addition to jump threading (and any other optimizer) with a minimal testcase. -Chris > @@ -0,0 +1,91 @@ > +; RUN: opt < %s -jump-threading -disable-output > +; ModuleID = 'bugpoint-reduced-simplified.bc' > +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" > +target triple = "x86_64-apple-darwin10.4" > + > +define void @encode_one_macroblock_highfast() nounwind ssp { > +entry: > + switch i32 undef, label %bb13 [ > + i32 1, label %bb10 > + i32 2, label %bb12 > + ] > + > +bb10: ; preds = %entry > + unreachable > + > +bb12: ; preds = %entry > + unreachable > + > +bb13: ; preds = %entry > + br i1 undef, label %bb137, label %bb292 > + > +bb137: ; preds = %bb13 > + br i1 undef, label %bb150, label %bb154 > + > +bb150: ; preds = %bb137 > + unreachable > + > +bb154: ; preds = %bb137 > + br i1 undef, label %bb292, label %bb246 > + > +bb246: ; preds = %bb154 > + br i1 undef, label %bb292, label %bb247 > + > +bb247: ; preds = %bb246 > + br i1 undef, label %bb248, label %bb292 > + > +bb248: ; preds = %bb247 > + br i1 undef, label %bb249, label %bb292 > + > +bb249: ; preds = %bb248 > + br i1 undef, label %bb254, label %bb250 > + > +bb250: ; preds = %bb249 > + unreachable > + > +bb254: ; preds = %bb249 > + br i1 undef, label %bb292, label %bb255 > + > +bb255: ; preds = %bb288.bb289.loopexit_crit_edge, %bb254 > + br i1 undef, label %bb.nph.split.us, label %bb269 > + > +bb.nph.split.us: ; preds = %bb255 > + br i1 undef, label %bb.nph.split.us.split.us, label %bb269.us.us31 > + > +bb.nph.split.us.split.us: ; preds = %bb.nph.split.us > + br i1 undef, label %bb269.us.us, label %bb269.us.us.us > + > +bb269.us.us.us: ; preds = %bb287.us.us.us, %bb.nph.split.us.split.us > + %indvar = phi i64 [ %indvar.next, %bb287.us.us.us ], [ 0, %bb.nph.split.us.split.us ] ; [#uses=1] > + %0 = icmp eq i16 undef, 0 ; [#uses=1] > + br i1 %0, label %bb287.us.us.us, label %bb286.us.us.us > + > +bb287.us.us.us: ; preds = %bb269.us.us.us > + %indvar.next = add i64 %indvar, 1 ; [#uses=2] > + %exitcond = icmp eq i64 %indvar.next, 4 ; [#uses=1] > + br i1 %exitcond, label %bb288.bb289.loopexit_crit_edge, label %bb269.us.us.us > + > +bb286.us.us.us: ; preds = %bb269.us.us.us > + unreachable > + > +bb269.us.us: ; preds = %bb287.us.us, %bb.nph.split.us.split.us > + br i1 undef, label %bb287.us.us, label %bb286.us.us > + > +bb287.us.us: ; preds = %bb269.us.us > + br i1 undef, label %bb288.bb289.loopexit_crit_edge, label %bb269.us.us > + > +bb286.us.us: ; preds = %bb269.us.us > + unreachable > + > +bb269.us.us31: ; preds = %bb.nph.split.us > + unreachable > + > +bb269: ; preds = %bb255 > + unreachable > + > +bb288.bb289.loopexit_crit_edge: ; preds = %bb287.us.us, %bb287.us.us.us > + br i1 undef, label %bb292, label %bb255 > + > +bb292: ; preds = %bb288.bb289.loopexit_crit_edge, %bb254, %bb248, %bb247, %bb246, %bb154, %bb13 > + unreachable > +} > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From stuart at apple.com Tue Aug 31 12:37:08 2010 From: stuart at apple.com (Stuart Hastings) Date: Tue, 31 Aug 2010 10:37:08 -0700 Subject: [llvm-commits] [llvm-gcc-4.2] r112531 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp In-Reply-To: <4C7CA267.7030907@free.fr> References: <20100830214050.BD6D92A6C12C@llvm.org> <4C7CA267.7030907@free.fr> Message-ID: <142A2E95-68A6-44CE-A3A7-7D43C228DEB1@apple.com> On Aug 30, 2010, at 11:34 PM, Duncan Sands wrote: > Hi Stuart, > >> Fix an assertion in the GCC DejaGNU testsuite. Radar 8251350. > > which gcc testcase are you referring to? gcc.c-torture/execute/builtin-bitops-1.c stuart From gohman at apple.com Tue Aug 31 12:56:47 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 31 Aug 2010 17:56:47 -0000 Subject: [llvm-commits] [llvm] r112608 - /llvm/trunk/lib/Analysis/ScalarEvolution.cpp Message-ID: <20100831175647.B895A2A6C12C@llvm.org> Author: djg Date: Tue Aug 31 12:56:47 2010 New Revision: 112608 URL: http://llvm.org/viewvc/llvm-project?rev=112608&view=rev Log: Speculatively revert r112433. Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=112608&r1=112607&r2=112608&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Tue Aug 31 12:56:47 2010 @@ -1886,30 +1886,27 @@ // there are multiple AddRec's with the same loop induction variable being // multiplied together. If so, we can fold them. for (unsigned OtherIdx = Idx+1; - OtherIdx < Ops.size() && isa(Ops[OtherIdx]); - ++OtherIdx) - if (AddRecLoop == cast(Ops[OtherIdx])->getLoop()) { - // F * G, where F = {A,+,B} and G = {C,+,D} --> - // {A*C,+,F*D + G*B + B*D} - for (; OtherIdx != Ops.size() && isa(Ops[OtherIdx]); - ++OtherIdx) - if (const SCEVAddRecExpr *OtherAddRec = - dyn_cast(Ops[OtherIdx])) - if (OtherAddRec->getLoop() == AddRecLoop) { - const SCEVAddRecExpr *F = AddRec, *G = OtherAddRec; - const SCEV *NewStart = getMulExpr(F->getStart(), G->getStart()); - const SCEV *B = F->getStepRecurrence(*this); - const SCEV *D = G->getStepRecurrence(*this); - const SCEV *NewStep = getAddExpr(getMulExpr(F, D), - getMulExpr(G, B), - getMulExpr(B, D)); - const SCEV *NewAddRec = getAddRecExpr(NewStart, NewStep, - F->getLoop()); - if (Ops.size() == 2) return NewAddRec; - Ops[Idx] = AddRec = cast(NewAddRec); - Ops.erase(Ops.begin() + OtherIdx); --OtherIdx; - } - return getMulExpr(Ops); + OtherIdx < Ops.size() && isa(Ops[OtherIdx]);++OtherIdx) + if (OtherIdx != Idx) { + const SCEVAddRecExpr *OtherAddRec = cast(Ops[OtherIdx]); + if (AddRecLoop == OtherAddRec->getLoop()) { + // F * G --> {A,+,B} * {C,+,D} --> {A*C,+,F*D + G*B + B*D} + const SCEVAddRecExpr *F = AddRec, *G = OtherAddRec; + const SCEV *NewStart = getMulExpr(F->getStart(), G->getStart()); + const SCEV *B = F->getStepRecurrence(*this); + const SCEV *D = G->getStepRecurrence(*this); + const SCEV *NewStep = getAddExpr(getMulExpr(F, D), + getMulExpr(G, B), + getMulExpr(B, D)); + const SCEV *NewAddRec = getAddRecExpr(NewStart, NewStep, + F->getLoop()); + if (Ops.size() == 2) return NewAddRec; + + Ops.erase(Ops.begin()+Idx); + Ops.erase(Ops.begin()+OtherIdx-1); + Ops.push_back(NewAddRec); + return getMulExpr(Ops); + } } // Otherwise couldn't fold anything into this recurrence. Move onto the From grosbach at apple.com Tue Aug 31 12:58:19 2010 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 31 Aug 2010 17:58:19 -0000 Subject: [llvm-commits] [llvm] r112609 - /llvm/trunk/lib/CodeGen/LocalStackSlotAllocation.cpp Message-ID: <20100831175819.388452A6C12C@llvm.org> Author: grosbach Date: Tue Aug 31 12:58:19 2010 New Revision: 112609 URL: http://llvm.org/viewvc/llvm-project?rev=112609&view=rev Log: Improve virtual frame base register allocation heuristics. 1. Allocate them in the entry block of the function to enable function-wide re-use. The instructions to create them should be re-materializable, so there shouldn't be additional cost compared to creating them local to the basic blocks where they are used. 2. Collect all of the frame index references for the function and sort them by the local offset referenced. Iterate over the sorted list to allocate the virtual base registers. This enables creation of base registers optimized for positive-offset access of frame references. (Note: This may be appropriate to later be a target hook to do the sorting in a target appropriate manner. For now it's done here for simplicity.) Modified: llvm/trunk/lib/CodeGen/LocalStackSlotAllocation.cpp Modified: llvm/trunk/lib/CodeGen/LocalStackSlotAllocation.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LocalStackSlotAllocation.cpp?rev=112609&r1=112608&r2=112609&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LocalStackSlotAllocation.cpp (original) +++ llvm/trunk/lib/CodeGen/LocalStackSlotAllocation.cpp Tue Aug 31 12:58:19 2010 @@ -24,6 +24,7 @@ #include "llvm/Pass.h" #include "llvm/ADT/SmallSet.h" #include "llvm/ADT/Statistic.h" +#include "llvm/ADT/STLExtras.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunctionPass.h" @@ -42,6 +43,18 @@ STATISTIC(NumReplacements, "Number of frame indices references replaced"); namespace { + class FrameRef { + MachineBasicBlock::iterator MI; // Instr referencing the frame + int64_t LocalOffset; // Local offset of the frame idx referenced + public: + FrameRef(MachineBasicBlock::iterator I, int64_t Offset) : + MI(I), LocalOffset(Offset) {} + bool operator<(const FrameRef &RHS) const { + return LocalOffset < RHS.LocalOffset; + } + MachineBasicBlock::iterator getMachineInstr() { return MI; } + }; + class LocalStackSlotPass: public MachineFunctionPass { SmallVector LocalOffsets; @@ -217,22 +230,24 @@ const TargetFrameInfo &TFI = *Fn.getTarget().getFrameInfo(); bool StackGrowsDown = TFI.getStackGrowthDirection() == TargetFrameInfo::StackGrowsDown; + MachineBasicBlock::iterator InsertionPt = Fn.begin()->begin(); - for (MachineFunction::iterator BB = Fn.begin(), - E = Fn.end(); BB != E; ++BB) { - // A base register definition is a register+offset pair. - SmallVector, 8> BaseRegisters; + // Collect all of the instructions in the block that reference + // a frame index. Also store the frame index referenced to ease later + // lookup. (For any insn that has more than one FI reference, we arbitrarily + // choose the first one). + SmallVector FrameReferenceInsns; + // A base register definition is a register+offset pair. + SmallVector, 8> BaseRegisters; + + for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { for (MachineBasicBlock::iterator I = BB->begin(); I != BB->end(); ++I) { MachineInstr *MI = I; // Debug value instructions can't be out of range, so they don't need // any updates. - // FIXME: When we extend this stuff to handle functions with both - // VLAs and dynamic realignment, we should update the debug values - // to reference the new base pointer when possible. if (MI->isDebugValue()) continue; - // For now, allocate the base register(s) within the basic block // where they're used, and don't try to keep them around outside // of that. It may be beneficial to try sharing them more broadly @@ -243,73 +258,94 @@ // Consider replacing all frame index operands that reference // an object allocated in the local block. if (MI->getOperand(i).isFI()) { - int FrameIdx = MI->getOperand(i).getIndex(); - // Don't try this with values not in the local block. - if (!MFI->isObjectPreAllocated(FrameIdx)) - continue; + if (!MFI->isObjectPreAllocated(MI->getOperand(i).getIndex())) + break; + FrameReferenceInsns. + push_back(FrameRef(MI, LocalOffsets[MI->getOperand(i).getIndex()])); + break; + } + } + } + } + // Sort the frame references by local offset + array_pod_sort(FrameReferenceInsns.begin(), FrameReferenceInsns.end()); - DEBUG(dbgs() << "Considering: " << *MI); - if (TRI->needsFrameBaseReg(MI, LocalOffsets[FrameIdx])) { - unsigned BaseReg = 0; - int64_t Offset = 0; - int64_t FrameSizeAdjust = StackGrowsDown ? MFI->getLocalFrameSize() - : 0; - - DEBUG(dbgs() << " Replacing FI in: " << *MI); - - // If we have a suitable base register available, use it; otherwise - // create a new one. Note that any offset encoded in the - // instruction itself will be taken into account by the target, - // so we don't have to adjust for it here when reusing a base - // register. - std::pair RegOffset; - if (lookupCandidateBaseReg(BaseRegisters, RegOffset, - FrameSizeAdjust, - LocalOffsets[FrameIdx], - MI, TRI)) { - DEBUG(dbgs() << " Reusing base register " << - RegOffset.first << "\n"); - // We found a register to reuse. - BaseReg = RegOffset.first; - Offset = FrameSizeAdjust + LocalOffsets[FrameIdx] - - RegOffset.second; - } else { - // No previously defined register was in range, so create a - // new one. - int64_t InstrOffset = TRI->getFrameIndexInstrOffset(MI, i); - const TargetRegisterClass *RC = TRI->getPointerRegClass(); - BaseReg = Fn.getRegInfo().createVirtualRegister(RC); - - DEBUG(dbgs() << " Materializing base register " << BaseReg << - " at frame local offset " << - LocalOffsets[FrameIdx] + InstrOffset << "\n"); - // Tell the target to insert the instruction to initialize - // the base register. - TRI->materializeFrameBaseRegister(I, BaseReg, FrameIdx, - InstrOffset); - - // The base register already includes any offset specified - // by the instruction, so account for that so it doesn't get - // applied twice. - Offset = -InstrOffset; - - int64_t BaseOffset = FrameSizeAdjust + LocalOffsets[FrameIdx] + - InstrOffset; - BaseRegisters.push_back( - std::pair(BaseReg, BaseOffset)); - ++NumBaseRegisters; - UsedBaseReg = true; - } - assert(BaseReg != 0 && "Unable to allocate virtual base register!"); - - // Modify the instruction to use the new base register rather - // than the frame index operand. - TRI->resolveFrameIndex(I, BaseReg, Offset); - DEBUG(dbgs() << "Resolved: " << *MI); - ++NumReplacements; + // Loop throught the frame references and allocate for them as necessary + for (int ref = 0, e = FrameReferenceInsns.size(); ref < e ; ++ref) { + MachineBasicBlock::iterator I = + FrameReferenceInsns[ref].getMachineInstr(); + MachineInstr *MI = I; + for (unsigned idx = 0, e = MI->getNumOperands(); idx != e; ++idx) { + // Consider replacing all frame index operands that reference + // an object allocated in the local block. + if (MI->getOperand(idx).isFI()) { + int FrameIdx = MI->getOperand(idx).getIndex(); + + assert(MFI->isObjectPreAllocated(FrameIdx) && + "Only pre-allocated locals expected!"); + + DEBUG(dbgs() << "Considering: " << *MI); + if (TRI->needsFrameBaseReg(MI, LocalOffsets[FrameIdx])) { + unsigned BaseReg = 0; + int64_t Offset = 0; + int64_t FrameSizeAdjust = + StackGrowsDown ? MFI->getLocalFrameSize() : 0; + + DEBUG(dbgs() << " Replacing FI in: " << *MI); + + // If we have a suitable base register available, use it; otherwise + // create a new one. Note that any offset encoded in the + // instruction itself will be taken into account by the target, + // so we don't have to adjust for it here when reusing a base + // register. + std::pair RegOffset; + if (lookupCandidateBaseReg(BaseRegisters, RegOffset, + FrameSizeAdjust, + LocalOffsets[FrameIdx], + MI, TRI)) { + DEBUG(dbgs() << " Reusing base register " << + RegOffset.first << "\n"); + // We found a register to reuse. + BaseReg = RegOffset.first; + Offset = FrameSizeAdjust + LocalOffsets[FrameIdx] - + RegOffset.second; + } else { + // No previously defined register was in range, so create a + // new one. + int64_t InstrOffset = TRI->getFrameIndexInstrOffset(MI, idx); + const TargetRegisterClass *RC = TRI->getPointerRegClass(); + BaseReg = Fn.getRegInfo().createVirtualRegister(RC); + + DEBUG(dbgs() << " Materializing base register " << BaseReg << + " at frame local offset " << + LocalOffsets[FrameIdx] + InstrOffset << "\n"); + // Tell the target to insert the instruction to initialize + // the base register. + TRI->materializeFrameBaseRegister(InsertionPt, BaseReg, + FrameIdx, InstrOffset); + + // The base register already includes any offset specified + // by the instruction, so account for that so it doesn't get + // applied twice. + Offset = -InstrOffset; + + int64_t BaseOffset = FrameSizeAdjust + LocalOffsets[FrameIdx] + + InstrOffset; + BaseRegisters.push_back( + std::pair(BaseReg, BaseOffset)); + ++NumBaseRegisters; + UsedBaseReg = true; } + assert(BaseReg != 0 && "Unable to allocate virtual base register!"); + + // Modify the instruction to use the new base register rather + // than the frame index operand. + TRI->resolveFrameIndex(I, BaseReg, Offset); + DEBUG(dbgs() << "Resolved: " << *MI); + + ++NumReplacements; } } } From grosbach at apple.com Tue Aug 31 12:58:47 2010 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 31 Aug 2010 17:58:47 -0000 Subject: [llvm-commits] [llvm] r112610 - /llvm/trunk/test/CodeGen/Thumb/vargs.ll Message-ID: <20100831175847.CA56B2A6C12C@llvm.org> Author: grosbach Date: Tue Aug 31 12:58:47 2010 New Revision: 112610 URL: http://llvm.org/viewvc/llvm-project?rev=112610&view=rev Log: Update test for 112609 Modified: llvm/trunk/test/CodeGen/Thumb/vargs.ll Modified: llvm/trunk/test/CodeGen/Thumb/vargs.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/vargs.ll?rev=112610&r1=112609&r2=112610&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/vargs.ll (original) +++ llvm/trunk/test/CodeGen/Thumb/vargs.ll Tue Aug 31 12:58:47 2010 @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=thumb -; RUN: llc < %s -mtriple=thumb-linux | grep pop | count 1 +; RUN: llc < %s -mtriple=thumb-linux | grep pop | count 2 ; RUN: llc < %s -mtriple=thumb-darwin | grep pop | count 2 @str = internal constant [4 x i8] c"%d\0A\00" ; <[4 x i8]*> [#uses=1] From resistor at mac.com Tue Aug 31 12:59:07 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 31 Aug 2010 17:59:07 -0000 Subject: [llvm-commits] [llvm] r112611 - /llvm/trunk/test/Transforms/JumpThreading/basic.ll Message-ID: <20100831175907.350C12A6C12C@llvm.org> Author: resistor Date: Tue Aug 31 12:59:07 2010 New Revision: 112611 URL: http://llvm.org/viewvc/llvm-project?rev=112611&view=rev Log: Add a micro-test for the transforms I added to JumpThreading. I have not been able to find a way to test each in isolation, for a few reasons: 1) The ability to look-through non-i1 BinaryOperator's requires the ability to look through non-constant ICmps in order for it to ever trigger. 2) The ability to do LVI-powered PHI value determination only matters in cases that ProcessBranchOnPHI can't handle. Since it already handles all the cases without other instructions in the def-use chain between the PHI and the branch, it requires the ability to look through ICmps and/or BinaryOperators as well. Modified: llvm/trunk/test/Transforms/JumpThreading/basic.ll Modified: llvm/trunk/test/Transforms/JumpThreading/basic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/JumpThreading/basic.ll?rev=112611&r1=112610&r2=112611&view=diff ============================================================================== --- llvm/trunk/test/Transforms/JumpThreading/basic.ll (original) +++ llvm/trunk/test/Transforms/JumpThreading/basic.ll Tue Aug 31 12:59:07 2010 @@ -421,4 +421,34 @@ ; CHECK-NEXT: br i1 %N, label %T2, label %F2 } +; CHECK: @test14 +define i32 @test14(i32 %in) { +entry: + %A = icmp eq i32 %in, 0 +; CHECK: br i1 %A, label %right_ret, label %merge + br i1 %A, label %left, label %right + +; CHECK-NOT: left: +left: + br label %merge + +; CHECK-NOT: right: +right: + %B = call i32 @f1() + br label %merge + +merge: +; CHECK-NOT: %C = phi i32 [%in, %left], [%B, %right] + %C = phi i32 [%in, %left], [%B, %right] + %D = add i32 %C, 1 + %E = icmp eq i32 %D, 2 + br i1 %E, label %left_ret, label %right_ret + +; CHECK: left_ret: +left_ret: + ret i32 0 + +right_ret: + ret i32 1 +} From sabre at nondot.org Tue Aug 31 13:05:09 2010 From: sabre at nondot.org (Chris Lattner) Date: Tue, 31 Aug 2010 18:05:09 -0000 Subject: [llvm-commits] [llvm] r112613 - in /llvm/trunk/test/Transforms/TailCallElim: accum_recursion.ll accum_recursion_constant_arg.ll Message-ID: <20100831180509.25AE42A6C12C@llvm.org> Author: lattner Date: Tue Aug 31 13:05:08 2010 New Revision: 112613 URL: http://llvm.org/viewvc/llvm-project?rev=112613&view=rev Log: merge two tests and convert to filecheck. Removed: llvm/trunk/test/Transforms/TailCallElim/accum_recursion_constant_arg.ll Modified: llvm/trunk/test/Transforms/TailCallElim/accum_recursion.ll Modified: llvm/trunk/test/Transforms/TailCallElim/accum_recursion.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/TailCallElim/accum_recursion.ll?rev=112613&r1=112612&r2=112613&view=diff ============================================================================== --- llvm/trunk/test/Transforms/TailCallElim/accum_recursion.ll (original) +++ llvm/trunk/test/Transforms/TailCallElim/accum_recursion.ll Tue Aug 31 13:05:08 2010 @@ -1,15 +1,40 @@ -; RUN: opt < %s -tailcallelim -S | not grep call +; RUN: opt < %s -tailcallelim -S | FileCheck %s -define i32 @factorial(i32 %x) { +define i32 @test1_factorial(i32 %x) { entry: %tmp.1 = icmp sgt i32 %x, 0 ; [#uses=1] br i1 %tmp.1, label %then, label %else then: ; preds = %entry %tmp.6 = add i32 %x, -1 ; [#uses=1] - %tmp.4 = call i32 @factorial( i32 %tmp.6 ) ; [#uses=1] + %tmp.4 = call i32 @test1_factorial( i32 %tmp.6 ) ; [#uses=1] %tmp.7 = mul i32 %tmp.4, %x ; [#uses=1] ret i32 %tmp.7 else: ; preds = %entry ret i32 1 } +; CHECK: define i32 @test1_factorial +; CHECK: phi i32 +; CHECK-NOT: call i32 +; CHECK: else: + +; This is a more aggressive form of accumulator recursion insertion, which +; requires noticing that X doesn't change as we perform the tailcall. + +define i32 @test2_mul(i32 %x, i32 %y) { +entry: + %tmp.1 = icmp eq i32 %y, 0 ; [#uses=1] + br i1 %tmp.1, label %return, label %endif +endif: ; preds = %entry + %tmp.8 = add i32 %y, -1 ; [#uses=1] + %tmp.5 = call i32 @test2_mul( i32 %x, i32 %tmp.8 ) ; [#uses=1] + %tmp.9 = add i32 %tmp.5, %x ; [#uses=1] + ret i32 %tmp.9 +return: ; preds = %entry + ret i32 %x +} + +; CHECK: define i32 @test2_mul +; CHECK: phi i32 +; CHECK-NOT: call i32 +; CHECK: return: \ No newline at end of file Removed: llvm/trunk/test/Transforms/TailCallElim/accum_recursion_constant_arg.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/TailCallElim/accum_recursion_constant_arg.ll?rev=112612&view=auto ============================================================================== --- llvm/trunk/test/Transforms/TailCallElim/accum_recursion_constant_arg.ll (original) +++ llvm/trunk/test/Transforms/TailCallElim/accum_recursion_constant_arg.ll (removed) @@ -1,20 +0,0 @@ -; This is a more aggressive form of accumulator recursion insertion, which -; requires noticing that X doesn't change as we perform the tailcall. Thanks -; go out to the anonymous users of the demo script for "suggesting" -; optimizations that should be done. :) - -; RUN: opt < %s -tailcallelim -S | not grep call - -define i32 @mul(i32 %x, i32 %y) { -entry: - %tmp.1 = icmp eq i32 %y, 0 ; [#uses=1] - br i1 %tmp.1, label %return, label %endif -endif: ; preds = %entry - %tmp.8 = add i32 %y, -1 ; [#uses=1] - %tmp.5 = call i32 @mul( i32 %x, i32 %tmp.8 ) ; [#uses=1] - %tmp.9 = add i32 %tmp.5, %x ; [#uses=1] - ret i32 %tmp.9 -return: ; preds = %entry - ret i32 %x -} - From resistor at mac.com Tue Aug 31 13:16:30 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 31 Aug 2010 18:16:30 -0000 Subject: [llvm-commits] [llvm] r112615 - /llvm/trunk/test/Transforms/JumpThreading/2010-08-31-InfiniteRecursion.ll Message-ID: <20100831181630.0D8EE2A6C12C@llvm.org> Author: resistor Date: Tue Aug 31 13:16:29 2010 New Revision: 112615 URL: http://llvm.org/viewvc/llvm-project?rev=112615&view=rev Log: Manually reduce this testcase. Modified: llvm/trunk/test/Transforms/JumpThreading/2010-08-31-InfiniteRecursion.ll Modified: llvm/trunk/test/Transforms/JumpThreading/2010-08-31-InfiniteRecursion.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/JumpThreading/2010-08-31-InfiniteRecursion.ll?rev=112615&r1=112614&r2=112615&view=diff ============================================================================== --- llvm/trunk/test/Transforms/JumpThreading/2010-08-31-InfiniteRecursion.ll (original) +++ llvm/trunk/test/Transforms/JumpThreading/2010-08-31-InfiniteRecursion.ll Tue Aug 31 13:16:29 2010 @@ -1,91 +1,25 @@ ; RUN: opt < %s -jump-threading -disable-output -; ModuleID = 'bugpoint-reduced-simplified.bc' -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" -target triple = "x86_64-apple-darwin10.4" -define void @encode_one_macroblock_highfast() nounwind ssp { +define void @test() nounwind ssp { entry: - switch i32 undef, label %bb13 [ - i32 1, label %bb10 - i32 2, label %bb12 - ] - -bb10: ; preds = %entry - unreachable - -bb12: ; preds = %entry - unreachable - -bb13: ; preds = %entry - br i1 undef, label %bb137, label %bb292 - -bb137: ; preds = %bb13 - br i1 undef, label %bb150, label %bb154 - -bb150: ; preds = %bb137 - unreachable - -bb154: ; preds = %bb137 - br i1 undef, label %bb292, label %bb246 - -bb246: ; preds = %bb154 - br i1 undef, label %bb292, label %bb247 - -bb247: ; preds = %bb246 - br i1 undef, label %bb248, label %bb292 - -bb248: ; preds = %bb247 - br i1 undef, label %bb249, label %bb292 - -bb249: ; preds = %bb248 - br i1 undef, label %bb254, label %bb250 - -bb250: ; preds = %bb249 - unreachable - -bb254: ; preds = %bb249 - br i1 undef, label %bb292, label %bb255 - -bb255: ; preds = %bb288.bb289.loopexit_crit_edge, %bb254 - br i1 undef, label %bb.nph.split.us, label %bb269 - -bb.nph.split.us: ; preds = %bb255 - br i1 undef, label %bb.nph.split.us.split.us, label %bb269.us.us31 - -bb.nph.split.us.split.us: ; preds = %bb.nph.split.us br i1 undef, label %bb269.us.us, label %bb269.us.us.us -bb269.us.us.us: ; preds = %bb287.us.us.us, %bb.nph.split.us.split.us - %indvar = phi i64 [ %indvar.next, %bb287.us.us.us ], [ 0, %bb.nph.split.us.split.us ] ; [#uses=1] - %0 = icmp eq i16 undef, 0 ; [#uses=1] +bb269.us.us.us: + %indvar = phi i64 [ %indvar.next, %bb287.us.us.us ], [ 0, %entry ] + %0 = icmp eq i16 undef, 0 br i1 %0, label %bb287.us.us.us, label %bb286.us.us.us -bb287.us.us.us: ; preds = %bb269.us.us.us - %indvar.next = add i64 %indvar, 1 ; [#uses=2] - %exitcond = icmp eq i64 %indvar.next, 4 ; [#uses=1] +bb287.us.us.us: + %indvar.next = add i64 %indvar, 1 + %exitcond = icmp eq i64 %indvar.next, 4 br i1 %exitcond, label %bb288.bb289.loopexit_crit_edge, label %bb269.us.us.us -bb286.us.us.us: ; preds = %bb269.us.us.us - unreachable - -bb269.us.us: ; preds = %bb287.us.us, %bb.nph.split.us.split.us - br i1 undef, label %bb287.us.us, label %bb286.us.us - -bb287.us.us: ; preds = %bb269.us.us - br i1 undef, label %bb288.bb289.loopexit_crit_edge, label %bb269.us.us - -bb286.us.us: ; preds = %bb269.us.us - unreachable - -bb269.us.us31: ; preds = %bb.nph.split.us - unreachable - -bb269: ; preds = %bb255 +bb286.us.us.us: unreachable -bb288.bb289.loopexit_crit_edge: ; preds = %bb287.us.us, %bb287.us.us.us - br i1 undef, label %bb292, label %bb255 +bb269.us.us: + unreachable -bb292: ; preds = %bb288.bb289.loopexit_crit_edge, %bb254, %bb248, %bb247, %bb246, %bb154, %bb13 +bb288.bb289.loopexit_crit_edge: unreachable } From wendling at apple.com Tue Aug 31 13:39:56 2010 From: wendling at apple.com (Bill Wendling) Date: Tue, 31 Aug 2010 11:39:56 -0700 Subject: [llvm-commits] [llvm] r112597 - in /llvm/trunk: include/llvm/CodeGen/Passes.h lib/CodeGen/DwarfEHPrepare.cpp lib/CodeGen/LLVMTargetMachine.cpp In-Reply-To: <20100831090507.174362A6C12E@llvm.org> References: <20100831090507.174362A6C12E@llvm.org> Message-ID: <5372C6E6-CC04-4AA2-A6AA-828291B944AE@apple.com> On Aug 31, 2010, at 2:05 AM, Duncan Sands wrote: > Author: baldrick > Date: Tue Aug 31 04:05:06 2010 > New Revision: 112597 > > URL: http://llvm.org/viewvc/llvm-project?rev=112597&view=rev > Log: > Stop using the dom frontier in DwarfEHPrepare by not promoting alloca's > any more. I plan to reimplement alloca promotion using SSAUpdater later. > It looks like Bill's URoR logic really always needs domtree, so the pass > now always asks for domtree info. > I'm fine with this, but please do the alloca promotion using SSAUpdater soon. Otherwise my horrible hack won't work for all of the cases I need it to. As John mentioned, I need to do reachability and not dominance. I'll fix it so that the DomTree stuff isn't needed. Thanks. -bw From sabre at nondot.org Tue Aug 31 13:44:03 2010 From: sabre at nondot.org (Chris Lattner) Date: Tue, 31 Aug 2010 18:44:03 -0000 Subject: [llvm-commits] [llvm] r112617 - in /llvm/trunk/test/Transforms/TailCallElim: accum_recursion.ll switch.ll Message-ID: <20100831184403.91F922A6C12C@llvm.org> Author: lattner Date: Tue Aug 31 13:44:03 2010 New Revision: 112617 URL: http://llvm.org/viewvc/llvm-project?rev=112617&view=rev Log: merge two tests. Removed: llvm/trunk/test/Transforms/TailCallElim/switch.ll Modified: llvm/trunk/test/Transforms/TailCallElim/accum_recursion.ll Modified: llvm/trunk/test/Transforms/TailCallElim/accum_recursion.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/TailCallElim/accum_recursion.ll?rev=112617&r1=112616&r2=112617&view=diff ============================================================================== --- llvm/trunk/test/Transforms/TailCallElim/accum_recursion.ll (original) +++ llvm/trunk/test/Transforms/TailCallElim/accum_recursion.ll Tue Aug 31 13:44:03 2010 @@ -37,4 +37,38 @@ ; CHECK: define i32 @test2_mul ; CHECK: phi i32 ; CHECK-NOT: call i32 -; CHECK: return: \ No newline at end of file +; CHECK: return: + + +define i64 @test3_fib(i64 %n) nounwind readnone { +; CHECK: @test3_fib +entry: +; CHECK: tailrecurse: +; CHECK: %accumulator.tr = phi i64 [ %n, %entry ], [ %3, %bb1 ] +; CHECK: %n.tr = phi i64 [ %n, %entry ], [ %2, %bb1 ] + switch i64 %n, label %bb1 [ +; CHECK: switch i64 %n.tr, label %bb1 [ + i64 0, label %bb2 + i64 1, label %bb2 + ] + +bb1: +; CHECK: bb1: + %0 = add i64 %n, -1 +; CHECK: %0 = add i64 %n.tr, -1 + %1 = tail call i64 @test3_fib(i64 %0) nounwind +; CHECK: %1 = tail call i64 @test3_fib(i64 %0) + %2 = add i64 %n, -2 +; CHECK: %2 = add i64 %n.tr, -2 + %3 = tail call i64 @test3_fib(i64 %2) nounwind +; CHECK-NOT: tail call i64 @test3_fib + %4 = add nsw i64 %3, %1 +; CHECK: add nsw i64 %accumulator.tr, %1 + ret i64 %4 +; CHECK: br label %tailrecurse + +bb2: +; CHECK: bb2: + ret i64 %n +; CHECK: ret i64 %accumulator.tr +} Removed: llvm/trunk/test/Transforms/TailCallElim/switch.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/TailCallElim/switch.ll?rev=112616&view=auto ============================================================================== --- llvm/trunk/test/Transforms/TailCallElim/switch.ll (original) +++ llvm/trunk/test/Transforms/TailCallElim/switch.ll (removed) @@ -1,34 +0,0 @@ -; RUN: opt %s -tailcallelim -S | FileCheck %s - -define i64 @fib(i64 %n) nounwind readnone { -; CHECK: @fib -entry: -; CHECK: tailrecurse: -; CHECK: %accumulator.tr = phi i64 [ %n, %entry ], [ %3, %bb1 ] -; CHECK: %n.tr = phi i64 [ %n, %entry ], [ %2, %bb1 ] - switch i64 %n, label %bb1 [ -; CHECK: switch i64 %n.tr, label %bb1 [ - i64 0, label %bb2 - i64 1, label %bb2 - ] - -bb1: -; CHECK: bb1: - %0 = add i64 %n, -1 -; CHECK: %0 = add i64 %n.tr, -1 - %1 = tail call i64 @fib(i64 %0) nounwind -; CHECK: %1 = tail call i64 @fib(i64 %0) - %2 = add i64 %n, -2 -; CHECK: %2 = add i64 %n.tr, -2 - %3 = tail call i64 @fib(i64 %2) nounwind -; CHECK-NOT: tail call i64 @fib - %4 = add nsw i64 %3, %1 -; CHECK: add nsw i64 %accumulator.tr, %1 - ret i64 %4 -; CHECK: br label %tailrecurse - -bb2: -; CHECK: bb2: - ret i64 %n -; CHECK: ret i64 %accumulator.tr -} From resistor at mac.com Tue Aug 31 13:48:48 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 31 Aug 2010 18:48:48 -0000 Subject: [llvm-commits] [llvm] r112620 - /llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Message-ID: <20100831184848.F2D8C2A6C12C@llvm.org> Author: resistor Date: Tue Aug 31 13:48:48 2010 New Revision: 112620 URL: http://llvm.org/viewvc/llvm-project?rev=112620&view=rev Log: Refactor my fix for PR5652 to terminate the predecessor lookups after the first failure. Modified: llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Modified: llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp?rev=112620&r1=112619&r2=112620&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Tue Aug 31 13:48:48 2010 @@ -715,37 +715,36 @@ // the branch based on that. BranchInst *CondBr = dyn_cast(BB->getTerminator()); Constant *CondConst = dyn_cast(CondCmp->getOperand(1)); - if (LVI && CondBr && CondConst && CondBr->isConditional() && + pred_iterator PI = pred_begin(BB), PE = pred_end(BB); + if (LVI && CondBr && CondConst && CondBr->isConditional() && PI != PE && (!isa(CondCmp->getOperand(0)) || cast(CondCmp->getOperand(0))->getParent() != BB)) { // For predecessor edge, determine if the comparison is true or false // on that edge. If they're all true or all false, we can simplify the // branch. // FIXME: We could handle mixed true/false by duplicating code. - unsigned Trues = 0, Falses = 0, predcount = 0; - for (pred_iterator PI = pred_begin(BB), PE = pred_end(BB);PI != PE; ++PI){ - ++predcount; - LazyValueInfo::Tristate Ret = - LVI->getPredicateOnEdge(CondCmp->getPredicate(), - CondCmp->getOperand(0), CondConst, *PI, BB); - if (Ret == LazyValueInfo::True) - ++Trues; - else if (Ret == LazyValueInfo::False) - ++Falses; - } - - // If we can determine the branch direction statically, convert - // the conditional branch to an unconditional one. - if (Trues && Trues == predcount) { - RemovePredecessorAndSimplify(CondBr->getSuccessor(1), BB, TD); - BranchInst::Create(CondBr->getSuccessor(0), CondBr); - CondBr->eraseFromParent(); - return true; - } else if (Falses && Falses == predcount) { - RemovePredecessorAndSimplify(CondBr->getSuccessor(0), BB, TD); - BranchInst::Create(CondBr->getSuccessor(1), CondBr); - CondBr->eraseFromParent(); - return true; + LazyValueInfo::Tristate Baseline = + LVI->getPredicateOnEdge(CondCmp->getPredicate(), CondCmp->getOperand(0), + CondConst, *PI, BB); + if (Baseline != LazyValueInfo::Unknown) { + // Check that all remaining incoming values match the first one. + while (++PI != PE) { + LazyValueInfo::Tristate Ret = LVI->getPredicateOnEdge( + CondCmp->getPredicate(), + CondCmp->getOperand(0), + CondConst, *PI, BB); + if (Ret != Baseline) break; + } + + // If we terminated early, then one of the values didn't match. + if (PI == PE) { + unsigned ToRemove = Baseline == LazyValueInfo::True ? 1 : 0; + unsigned ToKeep = Baseline == LazyValueInfo::True ? 0 : 1; + RemovePredecessorAndSimplify(CondBr->getSuccessor(ToRemove), BB, TD); + BranchInst::Create(CondBr->getSuccessor(ToKeep), CondBr); + CondBr->eraseFromParent(); + return true; + } } } } From resistor at mac.com Tue Aug 31 13:49:12 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 31 Aug 2010 18:49:12 -0000 Subject: [llvm-commits] [llvm] r112621 - /llvm/trunk/test/Transforms/JumpThreading/basic.ll Message-ID: <20100831184912.5B1C92A6C12C@llvm.org> Author: resistor Date: Tue Aug 31 13:49:12 2010 New Revision: 112621 URL: http://llvm.org/viewvc/llvm-project?rev=112621&view=rev Log: Add a test for the duplicated-conditional situation illutrated by PR5652. Modified: llvm/trunk/test/Transforms/JumpThreading/basic.ll Modified: llvm/trunk/test/Transforms/JumpThreading/basic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/JumpThreading/basic.ll?rev=112621&r1=112620&r2=112621&view=diff ============================================================================== --- llvm/trunk/test/Transforms/JumpThreading/basic.ll (original) +++ llvm/trunk/test/Transforms/JumpThreading/basic.ll Tue Aug 31 13:49:12 2010 @@ -452,3 +452,27 @@ ret i32 1 } +; PR5652 +; CHECK: @test15 +define i32 @test15(i32 %len) { +entry: +; CHECK: icmp ult i32 %len, 13 + %tmp = icmp ult i32 %len, 13 + br i1 %tmp, label %check, label %exit0 + +exit0: + ret i32 0 + +check: + %tmp9 = icmp ult i32 %len, 21 + br i1 %tmp9, label %exit1, label %exit2 + +exit2: +; CHECK-NOT: ret i32 2 + ret i32 2 + +exit1: + ret i32 1 +; CHECK: } +} + From grosbach at apple.com Tue Aug 31 13:49:31 2010 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 31 Aug 2010 18:49:31 -0000 Subject: [llvm-commits] [llvm] r112622 - /llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Message-ID: <20100831184931.A69AB2A6C12C@llvm.org> Author: grosbach Date: Tue Aug 31 13:49:31 2010 New Revision: 112622 URL: http://llvm.org/viewvc/llvm-project?rev=112622&view=rev Log: this assert should just be a condition, since this function is just asking if the offset is legally encodable, not actually trying to do the encoding. Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=112622&r1=112621&r2=112622&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Tue Aug 31 13:49:31 2010 @@ -1605,11 +1605,14 @@ } Offset += getFrameIndexInstrOffset(MI, i); - assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); + // Make sure the offset is encodable for instructions that scale the + // immediate. + if ((Offset & (Scale-1)) != 0) + return false; + if (isSigned && Offset < 0) Offset = -Offset; - unsigned Mask = (1 << NumBits) - 1; if ((unsigned)Offset <= Mask * Scale) return true; From dpatel at apple.com Tue Aug 31 13:50:09 2010 From: dpatel at apple.com (Devang Patel) Date: Tue, 31 Aug 2010 18:50:09 -0000 Subject: [llvm-commits] [llvm] r112623 - in /llvm/trunk: include/llvm/CodeGen/FunctionLoweringInfo.h lib/CodeGen/AsmPrinter/DwarfDebug.cpp lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp test/FrontendC++/2010-08-31-ByValArg.cpp Message-ID: <20100831185009.C616C2A6C12C@llvm.org> Author: dpatel Date: Tue Aug 31 13:50:09 2010 New Revision: 112623 URL: http://llvm.org/viewvc/llvm-project?rev=112623&view=rev Log: Remember byval argument's frame index during argument lowering and use this info to emit debug info. Fixes Radar 8367011. Added: llvm/trunk/test/FrontendC++/2010-08-31-ByValArg.cpp Modified: llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Modified: llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h?rev=112623&r1=112622&r2=112623&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h (original) +++ llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h Tue Aug 31 13:50:09 2010 @@ -77,6 +77,9 @@ /// anywhere in the function. DenseMap StaticAllocaMap; + /// ByValArgFrameIndexMap - Keep track of frame indices for byval arguments. + DenseMap ByValArgFrameIndexMap; + /// ArgDbgValues - A list of DBG_VALUE instructions created during isel for /// function arguments that are inserted after scheduling is completed. SmallVector ArgDbgValues; @@ -138,6 +141,13 @@ assert(R == 0 && "Already initialized this value register!"); return R = CreateRegs(V->getType()); } + + /// setByValArgumentFrameIndex - Record frame index for the byval + /// argument. + void setByValArgumentFrameIndex(const Argument *A, int FI); + + /// getByValArgumentFrameIndex - Get frame index for the byval argument. + int getByValArgumentFrameIndex(const Argument *A); }; /// AddCatchInfo - Extract the personality and type infos from an eh.selector Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=112623&r1=112622&r2=112623&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Tue Aug 31 13:50:09 2010 @@ -1629,9 +1629,16 @@ bool updated = false; // FIXME : Handle getNumOperands != 3 if (DVInsn->getNumOperands() == 3) { - if (DVInsn->getOperand(0).isReg()) - updated = - addRegisterAddress(VariableDie, DVLabel, DVInsn->getOperand(0)); + if (DVInsn->getOperand(0).isReg()) { + const MachineOperand RegOp = DVInsn->getOperand(0); + const TargetRegisterInfo *TRI = Asm->TM.getRegisterInfo(); + if (DVInsn->getOperand(1).isImm() && + TRI->getFrameRegister(*Asm->MF) == RegOp.getReg()) { + addVariableAddress(DV, VariableDie, DVInsn->getOperand(1).getImm()); + updated = true; + } else + updated = addRegisterAddress(VariableDie, DVLabel, RegOp); + } else if (DVInsn->getOperand(0).isImm()) updated = addConstantValue(VariableDie, DVLabel, DVInsn->getOperand(0)); else if (DVInsn->getOperand(0).isFPImm()) Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp?rev=112623&r1=112622&r2=112623&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp Tue Aug 31 13:50:09 2010 @@ -254,6 +254,29 @@ return FirstReg; } +/// setByValArgumentFrameIndex - Record frame index for the byval +/// argument. This overrides previous frame index entry for this argument, +/// if any. +void FunctionLoweringInfo::setByValArgumentFrameIndex(const Argument *A, + int FI) { + assert (A->hasByValAttr() && "Argument does not have byval attribute!"); + ByValArgFrameIndexMap[A] = FI; +} + +/// getByValArgumentFrameIndex - Get frame index for the byval argument. +/// This routine must be used after the argument's frame index is set. +/// If the argument does not have any entry in the map then assertion +/// will be raised. +int FunctionLoweringInfo::getByValArgumentFrameIndex(const Argument *A) { + assert (A->hasByValAttr() && "Argument does not have byval attribute!"); + DenseMap::iterator I = + ByValArgFrameIndexMap.find(A); + assert (I != ByValArgFrameIndexMap.end() && + "Argument does not have assigned frame index!"); + return I->second; + +} + /// AddCatchInfo - Extract the personality and type infos from an eh.selector /// call, and add them to the specified machine basic block. void llvm::AddCatchInfo(const CallInst &I, MachineModuleInfo *MMI, Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=112623&r1=112622&r2=112623&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Tue Aug 31 13:50:09 2010 @@ -3917,7 +3917,8 @@ SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, int64_t Offset, const SDValue &N) { - if (!isa(V)) + const Argument *Arg = dyn_cast(V); + if (!Arg) return false; MachineFunction &MF = DAG.getMachineFunction(); @@ -3931,6 +3932,14 @@ return false; unsigned Reg = 0; + if (Arg->hasByValAttr()) { + // Byval arguments' frame index is recorded during argument lowering. + // Use this info directly. + const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); + Reg = TRI->getFrameRegister(MF); + Offset = FuncInfo.getByValArgumentFrameIndex(Arg); + } + if (N.getNode() && N.getOpcode() == ISD::CopyFromReg) { Reg = cast(N.getOperand(1))->getReg(); if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) { @@ -6131,6 +6140,12 @@ i += NumParts; } + // Note down frame index for byval arguments. + if (I->hasByValAttr() && !ArgValues.empty()) + if (FrameIndexSDNode *FI = + dyn_cast(ArgValues[0].getNode())) + FuncInfo->setByValArgumentFrameIndex(I, FI->getIndex()); + if (!I->use_empty()) { SDValue Res; if (!ArgValues.empty()) Added: llvm/trunk/test/FrontendC++/2010-08-31-ByValArg.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2010-08-31-ByValArg.cpp?rev=112623&view=auto ============================================================================== --- llvm/trunk/test/FrontendC++/2010-08-31-ByValArg.cpp (added) +++ llvm/trunk/test/FrontendC++/2010-08-31-ByValArg.cpp Tue Aug 31 13:50:09 2010 @@ -0,0 +1,53 @@ +// This regression test checks byval arguments' debug info. +// Radar 8367011 +// RUN: %llvmgcc -S -O0 -g %s -o - | \ +// RUN: llc --disable-fp-elim -o %t.s -O0 -relocation-model=pic +// RUN: %compile_c %t.s -o %t.o +// RUN: %link %t.o -o %t.exe +// RUN: echo {break get\nrun\np missing_arg.b} > %t.in +// RUN: gdb -q -batch -n -x %t.in %t.exe | tee %t.out | \ +// RUN: grep {1 = 4242} + +// XTARGET: x86_64-apple-darwin + +class EVT { +public: + int a; + int b; + int c; +}; + +class VAL { +public: + int x; + int y; +}; +void foo(EVT e); +EVT bar(); + +void get(int *i, unsigned dl, VAL v, VAL *p, unsigned n, EVT missing_arg) { +//CHECK: .ascii "missing_arg" + EVT e = bar(); + if (dl == n) + foo(missing_arg); +} + + +EVT bar() { + EVT e; + return e; +} + +void foo(EVT e) {} + +int main(){ + VAL v; + EVT ma; + ma.a = 1; + ma.b = 4242; + ma.c = 3; + int i = 42; + get (&i, 1, v, &v, 2, ma); + return 0; +} + From grosbach at apple.com Tue Aug 31 13:52:31 2010 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 31 Aug 2010 18:52:31 -0000 Subject: [llvm-commits] [llvm] r112624 - /llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Message-ID: <20100831185231.AAE612A6C12C@llvm.org> Author: grosbach Date: Tue Aug 31 13:52:31 2010 New Revision: 112624 URL: http://llvm.org/viewvc/llvm-project?rev=112624&view=rev Log: SP relative offsets need to be adjusted by the local allocation size when determining if they're likely to be in range of the SP when resolving frame references. Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=112624&r1=112623&r2=112624&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Tue Aug 31 13:52:31 2010 @@ -1480,7 +1480,11 @@ if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction()) FPOffset -= 80; // Estimate an offset from the stack pointer. + // The incoming offset is relating to the SP at the start of the function, + // but when we access the local it'll be relative to the SP after local + // allocation, so adjust our SP-relative offset by that allocation size. Offset = -Offset; + Offset += MFI->getLocalFrameSize(); // Assume that we'll have at least some spill slots allocated. // FIXME: This is a total SWAG number. We should run some statistics // and pick a real one. From resistor at mac.com Tue Aug 31 13:55:52 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 31 Aug 2010 18:55:52 -0000 Subject: [llvm-commits] [llvm] r112625 - /llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp Message-ID: <20100831185552.7294A2A6C12C@llvm.org> Author: resistor Date: Tue Aug 31 13:55:52 2010 New Revision: 112625 URL: http://llvm.org/viewvc/llvm-project?rev=112625&view=rev Log: Only try to clean up the current block if we changed that block already. Modified: llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp Modified: llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp?rev=112625&r1=112624&r2=112625&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp Tue Aug 31 13:55:52 2010 @@ -100,19 +100,25 @@ bool CorrelatedValuePropagation::runOnFunction(Function &F) { LVI = &getAnalysis(); - bool Changed = false; + bool FnChanged = false; for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI) { + bool BBChanged = false; for (BasicBlock::iterator BI = FI->begin(), BE = FI->end(); BI != BE; ) { Instruction *II = BI++; if (SelectInst *SI = dyn_cast(II)) - Changed |= processSelect(SI); + BBChanged |= processSelect(SI); else if (PHINode *P = dyn_cast(II)) - Changed |= processPHI(P); + BBChanged |= processPHI(P); } - SimplifyInstructionsInBlock(FI); + // Propagating correlated values might leave cruft around. + // Try to clean it up before we continue. + if (BBChanged) + SimplifyInstructionsInBlock(FI); + + FnChanged |= BBChanged; } - return Changed; + return FnChanged; } From resistor at mac.com Tue Aug 31 14:24:27 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 31 Aug 2010 19:24:27 -0000 Subject: [llvm-commits] [llvm] r112628 - /llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Message-ID: <20100831192427.91C212A6C12C@llvm.org> Author: resistor Date: Tue Aug 31 14:24:27 2010 New Revision: 112628 URL: http://llvm.org/viewvc/llvm-project?rev=112628&view=rev Log: Add an RAII helper to make cleanup of the RecursionSet more fool-proof. Modified: llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Modified: llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp?rev=112628&r1=112627&r2=112628&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Tue Aug 31 14:24:27 2010 @@ -79,6 +79,20 @@ SmallSet, 16> LoopHeaders; #endif DenseSet > RecursionSet; + + // RAII helper for updating the recursion stack. + struct RecursionSetRemover { + DenseSet > &TheSet; + std::pair ThePair; + + RecursionSetRemover(DenseSet > &S, + std::pair P) + : TheSet(S), ThePair(P) { } + + ~RecursionSetRemover() { + TheSet.erase(ThePair); + } + }; public: static char ID; // Pass identification JumpThreading() : FunctionPass(ID) {} @@ -271,9 +285,17 @@ /// bool JumpThreading:: ComputeValueKnownInPredecessors(Value *V, BasicBlock *BB,PredValueInfo &Result){ + // This method walks up use-def chains recursively. Because of this, we could + // get into an infinite loop going around loops in the use-def chain. To + // prevent this, keep track of what (value, block) pairs we've already visited + // and terminate the search if we loop back to them if (!RecursionSet.insert(std::make_pair(V, BB)).second) return false; + // An RAII help to remove this pair from the recursion set once the recursion + // stack pops back out again. + RecursionSetRemover remover(RecursionSet, std::make_pair(V, BB)); + // If V is a constantint, then it is known in all predecessors. if (isa(V) || isa(V)) { ConstantInt *CI = dyn_cast(V); @@ -281,7 +303,6 @@ for (pred_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI) Result.push_back(std::make_pair(CI, *PI)); - RecursionSet.erase(std::make_pair(V, BB)); return true; } @@ -316,11 +337,9 @@ Result.push_back(std::make_pair(dyn_cast(PredCst), P)); } - RecursionSet.erase(std::make_pair(V, BB)); return !Result.empty(); } - RecursionSet.erase(std::make_pair(V, BB)); return false; } @@ -344,7 +363,6 @@ } } - RecursionSet.erase(std::make_pair(V, BB)); return !Result.empty(); } @@ -359,10 +377,8 @@ ComputeValueKnownInPredecessors(I->getOperand(0), BB, LHSVals); ComputeValueKnownInPredecessors(I->getOperand(1), BB, RHSVals); - if (LHSVals.empty() && RHSVals.empty()) { - RecursionSet.erase(std::make_pair(V, BB)); + if (LHSVals.empty() && RHSVals.empty()) return false; - } ConstantInt *InterestingVal; if (I->getOpcode() == Instruction::Or) @@ -390,7 +406,6 @@ } } - RecursionSet.erase(std::make_pair(V, BB)); return !Result.empty(); } @@ -399,10 +414,8 @@ isa(I->getOperand(1)) && cast(I->getOperand(1))->isOne()) { ComputeValueKnownInPredecessors(I->getOperand(0), BB, Result); - if (Result.empty()) { - RecursionSet.erase(std::make_pair(V, BB)); + if (Result.empty()) return false; - } // Invert the known values. for (unsigned i = 0, e = Result.size(); i != e; ++i) @@ -410,7 +423,6 @@ Result[i].first = cast(ConstantExpr::getNot(Result[i].first)); - RecursionSet.erase(std::make_pair(V, BB)); return true; } @@ -439,7 +451,6 @@ } } - RecursionSet.erase(std::make_pair(V, BB)); return !Result.empty(); } @@ -473,7 +484,6 @@ Result.push_back(std::make_pair(CI, PredBB)); } - RecursionSet.erase(std::make_pair(V, BB)); return !Result.empty(); } @@ -500,7 +510,6 @@ Result.push_back(std::make_pair(cast(ResC), P)); } - RecursionSet.erase(std::make_pair(V, BB)); return !Result.empty(); } @@ -525,7 +534,6 @@ Result.push_back(std::make_pair((ConstantInt*)0,LHSVals[i].second)); } - RecursionSet.erase(std::make_pair(V, BB)); return !Result.empty(); } } @@ -540,11 +548,9 @@ Result.push_back(std::make_pair(CInt, *PI)); } - RecursionSet.erase(std::make_pair(V, BB)); return !Result.empty(); } - RecursionSet.erase(std::make_pair(V, BB)); return false; } From baldrick at free.fr Tue Aug 31 14:28:09 2010 From: baldrick at free.fr (Duncan Sands) Date: Tue, 31 Aug 2010 21:28:09 +0200 Subject: [llvm-commits] [llvm] r112597 - in /llvm/trunk: include/llvm/CodeGen/Passes.h lib/CodeGen/DwarfEHPrepare.cpp lib/CodeGen/LLVMTargetMachine.cpp In-Reply-To: <5372C6E6-CC04-4AA2-A6AA-828291B944AE@apple.com> References: <20100831090507.174362A6C12E@llvm.org> <5372C6E6-CC04-4AA2-A6AA-828291B944AE@apple.com> Message-ID: <4C7D57C9.4060307@free.fr> Hi Bill, > I'm fine with this, but please do the alloca promotion using SSAUpdater soon. Otherwise my horrible hack won't work for all of the cases I need it to. As John mentioned, I need to do reachability and not dominance. I'll fix it so that the DomTree stuff isn't needed. we never did any alloca promotion at -O0, so does that mean this already sometimes wasn't working properly at -O0? Also, I wasn't actually planning to do alloca promotion for your 'orrible hack code because it makes my head hurt, but perhaps I can be persuaded... Ciao, Duncan. From baldrick at free.fr Tue Aug 31 14:40:21 2010 From: baldrick at free.fr (Duncan Sands) Date: Tue, 31 Aug 2010 19:40:21 -0000 Subject: [llvm-commits] [llvm] r112630 - /llvm/trunk/docs/GCCFEBuildInstrs.html Message-ID: <20100831194021.498E52A6C12C@llvm.org> Author: baldrick Date: Tue Aug 31 14:40:21 2010 New Revision: 112630 URL: http://llvm.org/viewvc/llvm-project?rev=112630&view=rev Log: Update the Ada instructions to LLVM 2.7 (from LLVM 2.5). Modified: llvm/trunk/docs/GCCFEBuildInstrs.html Modified: llvm/trunk/docs/GCCFEBuildInstrs.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/GCCFEBuildInstrs.html?rev=112630&r1=112629&r2=112630&view=diff ============================================================================== --- llvm/trunk/docs/GCCFEBuildInstrs.html (original) +++ llvm/trunk/docs/GCCFEBuildInstrs.html Tue Aug 31 14:40:21 2010 @@ -84,7 +84,7 @@

    • The build requires having a compiler that supports Ada, C and C++. The Ada front-end is written in Ada so an Ada compiler is needed to build it. Compilers known to work with the - LLVM 2.5 release + LLVM 2.7 release are gcc-4.2 and the 2005, 2006 and 2007 versions of the GNAT GPL Edition. @@ -116,9 +116,9 @@ and unpack it:

      -wget http://llvm.org/releases/2.5/llvm-2.5.tar.gz
-tar xzf llvm-2.5.tar.gz
-mv llvm-2.5 llvm
+wget http://llvm.org/releases/2.7/llvm-2.7.tgz
+tar xzf llvm-2.7.tgz
+mv llvm-2.7 llvm

      or check out the @@ -133,9 +133,9 @@ and unpack it:

      -wget http://llvm.org/releases/2.5/llvm-gcc-4.2-2.5.source.tar.gz
-tar xzf llvm-gcc-4.2-2.5.source.tar.gz
-mv llvm-gcc4.2-2.5.source llvm-gcc-4.2
+wget http://llvm.org/releases/2.7/llvm-gcc-4.2-2.7.source.tgz
+tar xzf llvm-gcc-4.2-2.7.source.tgz
+mv llvm-gcc-4.2-2.7.source llvm-gcc-4.2

      or check out the From dpatel at apple.com Tue Aug 31 14:41:04 2010 From: dpatel at apple.com (Devang Patel) Date: Tue, 31 Aug 2010 19:41:04 -0000 Subject: [llvm-commits] [llvm] r112631 - in /llvm/trunk: include/llvm/CodeGen/FunctionLoweringInfo.h lib/CodeGen/AsmPrinter/DwarfDebug.cpp lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp test/FrontendC++/2010-08-31-ByValArg.cpp Message-ID: <20100831194104.3D48C2A6C12C@llvm.org> Author: dpatel Date: Tue Aug 31 14:41:03 2010 New Revision: 112631 URL: http://llvm.org/viewvc/llvm-project?rev=112631&view=rev Log: Revert r112623. It is causing self host build failures. Removed: llvm/trunk/test/FrontendC++/2010-08-31-ByValArg.cpp Modified: llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Modified: llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h?rev=112631&r1=112630&r2=112631&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h (original) +++ llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h Tue Aug 31 14:41:03 2010 @@ -77,9 +77,6 @@ /// anywhere in the function. DenseMap StaticAllocaMap; - /// ByValArgFrameIndexMap - Keep track of frame indices for byval arguments. - DenseMap ByValArgFrameIndexMap; - /// ArgDbgValues - A list of DBG_VALUE instructions created during isel for /// function arguments that are inserted after scheduling is completed. SmallVector ArgDbgValues; @@ -141,13 +138,6 @@ assert(R == 0 && "Already initialized this value register!"); return R = CreateRegs(V->getType()); } - - /// setByValArgumentFrameIndex - Record frame index for the byval - /// argument. - void setByValArgumentFrameIndex(const Argument *A, int FI); - - /// getByValArgumentFrameIndex - Get frame index for the byval argument. - int getByValArgumentFrameIndex(const Argument *A); }; /// AddCatchInfo - Extract the personality and type infos from an eh.selector Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=112631&r1=112630&r2=112631&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Tue Aug 31 14:41:03 2010 @@ -1629,16 +1629,9 @@ bool updated = false; // FIXME : Handle getNumOperands != 3 if (DVInsn->getNumOperands() == 3) { - if (DVInsn->getOperand(0).isReg()) { - const MachineOperand RegOp = DVInsn->getOperand(0); - const TargetRegisterInfo *TRI = Asm->TM.getRegisterInfo(); - if (DVInsn->getOperand(1).isImm() && - TRI->getFrameRegister(*Asm->MF) == RegOp.getReg()) { - addVariableAddress(DV, VariableDie, DVInsn->getOperand(1).getImm()); - updated = true; - } else - updated = addRegisterAddress(VariableDie, DVLabel, RegOp); - } + if (DVInsn->getOperand(0).isReg()) + updated = + addRegisterAddress(VariableDie, DVLabel, DVInsn->getOperand(0)); else if (DVInsn->getOperand(0).isImm()) updated = addConstantValue(VariableDie, DVLabel, DVInsn->getOperand(0)); else if (DVInsn->getOperand(0).isFPImm()) Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp?rev=112631&r1=112630&r2=112631&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp Tue Aug 31 14:41:03 2010 @@ -254,29 +254,6 @@ return FirstReg; } -/// setByValArgumentFrameIndex - Record frame index for the byval -/// argument. This overrides previous frame index entry for this argument, -/// if any. -void FunctionLoweringInfo::setByValArgumentFrameIndex(const Argument *A, - int FI) { - assert (A->hasByValAttr() && "Argument does not have byval attribute!"); - ByValArgFrameIndexMap[A] = FI; -} - -/// getByValArgumentFrameIndex - Get frame index for the byval argument. -/// This routine must be used after the argument's frame index is set. -/// If the argument does not have any entry in the map then assertion -/// will be raised. -int FunctionLoweringInfo::getByValArgumentFrameIndex(const Argument *A) { - assert (A->hasByValAttr() && "Argument does not have byval attribute!"); - DenseMap::iterator I = - ByValArgFrameIndexMap.find(A); - assert (I != ByValArgFrameIndexMap.end() && - "Argument does not have assigned frame index!"); - return I->second; - -} - /// AddCatchInfo - Extract the personality and type infos from an eh.selector /// call, and add them to the specified machine basic block. void llvm::AddCatchInfo(const CallInst &I, MachineModuleInfo *MMI, Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=112631&r1=112630&r2=112631&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Tue Aug 31 14:41:03 2010 @@ -3917,8 +3917,7 @@ SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, int64_t Offset, const SDValue &N) { - const Argument *Arg = dyn_cast(V); - if (!Arg) + if (!isa(V)) return false; MachineFunction &MF = DAG.getMachineFunction(); @@ -3932,14 +3931,6 @@ return false; unsigned Reg = 0; - if (Arg->hasByValAttr()) { - // Byval arguments' frame index is recorded during argument lowering. - // Use this info directly. - const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); - Reg = TRI->getFrameRegister(MF); - Offset = FuncInfo.getByValArgumentFrameIndex(Arg); - } - if (N.getNode() && N.getOpcode() == ISD::CopyFromReg) { Reg = cast(N.getOperand(1))->getReg(); if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) { @@ -6140,12 +6131,6 @@ i += NumParts; } - // Note down frame index for byval arguments. - if (I->hasByValAttr() && !ArgValues.empty()) - if (FrameIndexSDNode *FI = - dyn_cast(ArgValues[0].getNode())) - FuncInfo->setByValArgumentFrameIndex(I, FI->getIndex()); - if (!I->use_empty()) { SDValue Res; if (!ArgValues.empty()) Removed: llvm/trunk/test/FrontendC++/2010-08-31-ByValArg.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2010-08-31-ByValArg.cpp?rev=112630&view=auto ============================================================================== --- llvm/trunk/test/FrontendC++/2010-08-31-ByValArg.cpp (original) +++ llvm/trunk/test/FrontendC++/2010-08-31-ByValArg.cpp (removed) @@ -1,53 +0,0 @@ -// This regression test checks byval arguments' debug info. -// Radar 8367011 -// RUN: %llvmgcc -S -O0 -g %s -o - | \ -// RUN: llc --disable-fp-elim -o %t.s -O0 -relocation-model=pic -// RUN: %compile_c %t.s -o %t.o -// RUN: %link %t.o -o %t.exe -// RUN: echo {break get\nrun\np missing_arg.b} > %t.in -// RUN: gdb -q -batch -n -x %t.in %t.exe | tee %t.out | \ -// RUN: grep {1 = 4242} - -// XTARGET: x86_64-apple-darwin - -class EVT { -public: - int a; - int b; - int c; -}; - -class VAL { -public: - int x; - int y; -}; -void foo(EVT e); -EVT bar(); - -void get(int *i, unsigned dl, VAL v, VAL *p, unsigned n, EVT missing_arg) { -//CHECK: .ascii "missing_arg" - EVT e = bar(); - if (dl == n) - foo(missing_arg); -} - - -EVT bar() { - EVT e; - return e; -} - -void foo(EVT e) {} - -int main(){ - VAL v; - EVT ma; - ma.a = 1; - ma.b = 4242; - ma.c = 3; - int i = 42; - get (&i, 1, v, &v, 2, ma); - return 0; -} - From stoklund at 2pi.dk Tue Aug 31 14:54:25 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 31 Aug 2010 19:54:25 -0000 Subject: [llvm-commits] [llvm] r112632 - /llvm/trunk/lib/CodeGen/RegAllocFast.cpp Message-ID: <20100831195425.480482A6C12D@llvm.org> Author: stoklund Date: Tue Aug 31 14:54:25 2010 New Revision: 112632 URL: http://llvm.org/viewvc/llvm-project?rev=112632&view=rev Log: Ignore unallocatable registers in RegAllocFast. Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=112632&r1=112631&r2=112632&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocFast.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp Tue Aug 31 14:54:25 2010 @@ -736,7 +736,8 @@ // Add live-in registers as live. for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(), E = MBB->livein_end(); I != E; ++I) - definePhysReg(MII, *I, regReserved); + if (Allocatable.test(*I)) + definePhysReg(MII, *I, regReserved); SmallVector VirtDead; SmallVector Coalesced; From wendling at apple.com Tue Aug 31 15:03:55 2010 From: wendling at apple.com (Bill Wendling) Date: Tue, 31 Aug 2010 13:03:55 -0700 Subject: [llvm-commits] [llvm] r112597 - in /llvm/trunk: include/llvm/CodeGen/Passes.h lib/CodeGen/DwarfEHPrepare.cpp lib/CodeGen/LLVMTargetMachine.cpp In-Reply-To: <4C7D57C9.4060307@free.fr> References: <20100831090507.174362A6C12E@llvm.org> <5372C6E6-CC04-4AA2-A6AA-828291B944AE@apple.com> <4C7D57C9.4060307@free.fr> Message-ID: On Aug 31, 2010, at 12:28 PM, Duncan Sands wrote: > Hi Bill, > >> I'm fine with this, but please do the alloca promotion using SSAUpdater soon. Otherwise my horrible hack won't work for all of the cases I need it to. As John mentioned, I need to do reachability and not dominance. I'll fix it so that the DomTree stuff isn't needed. > > we never did any alloca promotion at -O0, so does that mean this already > sometimes wasn't working properly at -O0? Also, I wasn't actually planning > to do alloca promotion for your 'orrible hack code because it makes my head > hurt, but perhaps I can be persuaded... > The horrible hack is there mostly for inlining, which doesn't occur at -O0. We can get away with it in most cases. But it's quite easy to generate a case where it won't work. My guess is that it's a hand-written case that would fail. I just don't want a regression, and since you took the code out I thought you would replace it. :-) But if it works, then it's fine being omitted. -bw From dpatel at apple.com Tue Aug 31 15:07:31 2010 From: dpatel at apple.com (Devang Patel) Date: Tue, 31 Aug 2010 13:07:31 -0700 Subject: [llvm-commits] [llvm] r112597 - in /llvm/trunk: include/llvm/CodeGen/Passes.h lib/CodeGen/DwarfEHPrepare.cpp lib/CodeGen/LLVMTargetMachine.cpp In-Reply-To: References: <20100831090507.174362A6C12E@llvm.org> <5372C6E6-CC04-4AA2-A6AA-828291B944AE@apple.com> <4C7D57C9.4060307@free.fr> Message-ID: <18868193-B873-4639-B37C-A103184C4C3A@apple.com> On Aug 31, 2010, at 1:03 PM, Bill Wendling wrote: > On Aug 31, 2010, at 12:28 PM, Duncan Sands wrote: > >> Hi Bill, >> >>> I'm fine with this, but please do the alloca promotion using SSAUpdater soon. Otherwise my horrible hack won't work for all of the cases I need it to. As John mentioned, I need to do reachability and not dominance. I'll fix it so that the DomTree stuff isn't needed. >> >> we never did any alloca promotion at -O0, so does that mean this already >> sometimes wasn't working properly at -O0? Also, I wasn't actually planning >> to do alloca promotion for your 'orrible hack code because it makes my head >> hurt, but perhaps I can be persuaded... >> > The horrible hack is there mostly for inlining, which doesn't occur at -O0. attribute always_inline will trigger inlining at -O0. > We can get away with it in most cases. But it's quite easy to generate a case where it won't work. My guess is that it's a hand-written case that would fail. > > I just don't want a regression, and since you took the code out I thought you would replace it. :-) But if it works, then it's fine being omitted. > > -bw > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From baldrick at free.fr Tue Aug 31 15:11:07 2010 From: baldrick at free.fr (Duncan Sands) Date: Tue, 31 Aug 2010 22:11:07 +0200 Subject: [llvm-commits] [llvm] r112597 - in /llvm/trunk: include/llvm/CodeGen/Passes.h lib/CodeGen/DwarfEHPrepare.cpp lib/CodeGen/LLVMTargetMachine.cpp In-Reply-To: References: <20100831090507.174362A6C12E@llvm.org> <5372C6E6-CC04-4AA2-A6AA-828291B944AE@apple.com> <4C7D57C9.4060307@free.fr> Message-ID: <4C7D61DB.3060009@free.fr> Hi Bill, >>> I'm fine with this, but please do the alloca promotion using SSAUpdater soon. Otherwise my horrible hack won't work for all of the cases I need it to. As John mentioned, I need to do reachability and not dominance. I'll fix it so that the DomTree stuff isn't needed. >> >> we never did any alloca promotion at -O0, so does that mean this already >> sometimes wasn't working properly at -O0? Also, I wasn't actually planning >> to do alloca promotion for your 'orrible hack code because it makes my head >> hurt, but perhaps I can be persuaded... >> > The horrible hack is there mostly for inlining, which doesn't occur at -O0. aren't you confusing -O0 at the IR level and -O0 codegen? I can optimize some bitcode with -std-compile-opts and then pass it to "llc -O0"... So in theory llc needs to deal correctly with inlined code even at -O0. We can get away with it in most cases. But it's quite easy to generate a case where it won't work. My guess is that it's a hand-written case that would fail. Sounds like a good testcase to have in the testsuite! > I just don't want a regression, and since you took the code out I thought you would replace it. :-) There is something to what you say :) But if it works, then it's fine being omitted. I think I'd better test it harder... Ciao, Duncan. From tonic at nondot.org Tue Aug 31 15:22:50 2010 From: tonic at nondot.org (Tanya Lattner) Date: Tue, 31 Aug 2010 20:22:50 -0000 Subject: [llvm-commits] [www] r112633 - /www/trunk/devmtg/talk.php Message-ID: <20100831202250.A7FB92A6C12C@llvm.org> Author: tbrethou Date: Tue Aug 31 15:22:50 2010 New Revision: 112633 URL: http://llvm.org/viewvc/llvm-project?rev=112633&view=rev Log: Update. Modified: www/trunk/devmtg/talk.php Modified: www/trunk/devmtg/talk.php URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/talk.php?rev=112633&r1=112632&r2=112633&view=diff ============================================================================== --- www/trunk/devmtg/talk.php (original) +++ www/trunk/devmtg/talk.php Tue Aug 31 15:22:50 2010 @@ -1,8 +1,7 @@ -'; @@ -203,12 +201,9 @@

      LLVM Developers' Meeting - Talk Proposal
      -Talk proposals are closed for this year. - - From resistor at mac.com Tue Aug 31 15:26:04 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 31 Aug 2010 20:26:04 -0000 Subject: [llvm-commits] [llvm] r112634 - /llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Message-ID: <20100831202604.6F5DF2A6C12C@llvm.org> Author: resistor Date: Tue Aug 31 15:26:04 2010 New Revision: 112634 URL: http://llvm.org/viewvc/llvm-project?rev=112634&view=rev Log: More cleanups of my JumpThreading transforms, including extracting some duplicated code into a helper function. Modified: llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Modified: llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp?rev=112634&r1=112633&r2=112634&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Tue Aug 31 15:26:04 2010 @@ -276,6 +276,17 @@ LoopHeaders.insert(const_cast(Edges[i].second)); } +// Helper method for ComputeValueKnownInPredecessors. If Value is a +// ConstantInt, push it. If it's an undef, push 0. Otherwise, do nothing. +static void PushConstantIntOrUndef(SmallVectorImpl > &Result, + Constant *Value, BasicBlock* BB){ + if (ConstantInt *FoldedCInt = dyn_cast(Value)) + Result.push_back(std::make_pair(FoldedCInt, BB)); + else if (isa(Value)) + Result.push_back(std::make_pair((ConstantInt*)0, BB)); +} + /// ComputeValueKnownInPredecessors - Given a basic block BB and a value V, see /// if we can infer that the value is a known ConstantInt in any of our /// predecessors. If so, return the known list of value and pred BB in the @@ -355,11 +366,7 @@ PN->getIncomingBlock(i), BB); // LVI returns null is no value could be determined. if (!CI) continue; - if (ConstantInt *CInt = dyn_cast(CI)) - Result.push_back(std::make_pair(CInt, PN->getIncomingBlock(i))); - else if (isa(CI)) - Result.push_back(std::make_pair((ConstantInt*)0, - PN->getIncomingBlock(i))); + PushConstantIntOrUndef(Result, CI, PN->getIncomingBlock(i)); } } @@ -428,26 +435,17 @@ // Try to simplify some other binary operator values. } else if (BinaryOperator *BO = dyn_cast(I)) { - ConstantInt *CI = dyn_cast(BO->getOperand(1)); - if (CI) { + if (ConstantInt *CI = dyn_cast(BO->getOperand(1))) { SmallVector, 8> LHSVals; ComputeValueKnownInPredecessors(BO->getOperand(0), BB, LHSVals); // Try to use constant folding to simplify the binary operator. for (unsigned i = 0, e = LHSVals.size(); i != e; ++i) { - Constant *Folded = 0; - if (LHSVals[i].first == 0) { - Folded = ConstantExpr::get(BO->getOpcode(), - UndefValue::get(BO->getType()), - CI); - } else { - Folded = ConstantExpr::get(BO->getOpcode(), LHSVals[i].first, CI); - } + Constant *V = LHSVals[i].first ? LHSVals[i].first : + cast(UndefValue::get(BO->getType())); + Constant *Folded = ConstantExpr::get(BO->getOpcode(), V, CI); - if (ConstantInt *FoldedCInt = dyn_cast(Folded)) - Result.push_back(std::make_pair(FoldedCInt, LHSVals[i].second)); - else if (isa(Folded)) - Result.push_back(std::make_pair((ConstantInt*)0, LHSVals[i].second)); + PushConstantIntOrUndef(Result, Folded, LHSVals[i].second); } } @@ -478,10 +476,8 @@ Res = ConstantInt::get(Type::getInt1Ty(LHS->getContext()), ResT); } - if (isa(Res)) - Result.push_back(std::make_pair((ConstantInt*)0, PredBB)); - else if (ConstantInt *CI = dyn_cast(Res)) - Result.push_back(std::make_pair(CI, PredBB)); + if (Constant *ConstRes = dyn_cast(Res)) + PushConstantIntOrUndef(Result, ConstRes, PredBB); } return !Result.empty(); @@ -520,18 +516,11 @@ ComputeValueKnownInPredecessors(I->getOperand(0), BB, LHSVals); for (unsigned i = 0, e = LHSVals.size(); i != e; ++i) { - Constant * Folded = 0; - if (LHSVals[i].first == 0) - Folded = ConstantExpr::getCompare(Cmp->getPredicate(), - UndefValue::get(CmpConst->getType()), CmpConst); - else - Folded = ConstantExpr::getCompare(Cmp->getPredicate(), - LHSVals[i].first, CmpConst); - - if (ConstantInt *FoldedCInt = dyn_cast(Folded)) - Result.push_back(std::make_pair(FoldedCInt, LHSVals[i].second)); - else if (isa(Folded)) - Result.push_back(std::make_pair((ConstantInt*)0,LHSVals[i].second)); + Constant *V = LHSVals[i].first ? LHSVals[i].first : + cast(UndefValue::get(CmpConst->getType())); + Constant *Folded = ConstantExpr::getCompare(Cmp->getPredicate(), + V, CmpConst); + PushConstantIntOrUndef(Result, Folded, LHSVals[i].second); } return !Result.empty(); @@ -1168,9 +1157,9 @@ return false; SmallVector, 8> PredValues; - if (!ComputeValueKnownInPredecessors(Cond, BB, PredValues)) { + if (!ComputeValueKnownInPredecessors(Cond, BB, PredValues)) return false; - } + assert(!PredValues.empty() && "ComputeValueKnownInPredecessors returned true with no values"); From resistor at mac.com Tue Aug 31 15:27:17 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 31 Aug 2010 20:27:17 -0000 Subject: [llvm-commits] [llvm] r112635 - in /llvm/trunk/test/Transforms/JumpThreading: 2010-08-31-InfiniteRecursion.ll crash.ll Message-ID: <20100831202717.B6F782A6C12C@llvm.org> Author: resistor Date: Tue Aug 31 15:27:17 2010 New Revision: 112635 URL: http://llvm.org/viewvc/llvm-project?rev=112635&view=rev Log: Merge 2010-08-31-InfiniteRecursion.ll into crash.ll. Removed: llvm/trunk/test/Transforms/JumpThreading/2010-08-31-InfiniteRecursion.ll Modified: llvm/trunk/test/Transforms/JumpThreading/crash.ll Removed: llvm/trunk/test/Transforms/JumpThreading/2010-08-31-InfiniteRecursion.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/JumpThreading/2010-08-31-InfiniteRecursion.ll?rev=112634&view=auto ============================================================================== --- llvm/trunk/test/Transforms/JumpThreading/2010-08-31-InfiniteRecursion.ll (original) +++ llvm/trunk/test/Transforms/JumpThreading/2010-08-31-InfiniteRecursion.ll (removed) @@ -1,25 +0,0 @@ -; RUN: opt < %s -jump-threading -disable-output - -define void @test() nounwind ssp { -entry: - br i1 undef, label %bb269.us.us, label %bb269.us.us.us - -bb269.us.us.us: - %indvar = phi i64 [ %indvar.next, %bb287.us.us.us ], [ 0, %entry ] - %0 = icmp eq i16 undef, 0 - br i1 %0, label %bb287.us.us.us, label %bb286.us.us.us - -bb287.us.us.us: - %indvar.next = add i64 %indvar, 1 - %exitcond = icmp eq i64 %indvar.next, 4 - br i1 %exitcond, label %bb288.bb289.loopexit_crit_edge, label %bb269.us.us.us - -bb286.us.us.us: - unreachable - -bb269.us.us: - unreachable - -bb288.bb289.loopexit_crit_edge: - unreachable -} Modified: llvm/trunk/test/Transforms/JumpThreading/crash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/JumpThreading/crash.ll?rev=112635&r1=112634&r2=112635&view=diff ============================================================================== --- llvm/trunk/test/Transforms/JumpThreading/crash.ll (original) +++ llvm/trunk/test/Transforms/JumpThreading/crash.ll Tue Aug 31 15:27:17 2010 @@ -461,3 +461,26 @@ ret void } +define void @test17() { +entry: + br i1 undef, label %bb269.us.us, label %bb269.us.us.us + +bb269.us.us.us: + %indvar = phi i64 [ %indvar.next, %bb287.us.us.us ], [ 0, %entry ] + %0 = icmp eq i16 undef, 0 + br i1 %0, label %bb287.us.us.us, label %bb286.us.us.us + +bb287.us.us.us: + %indvar.next = add i64 %indvar, 1 + %exitcond = icmp eq i64 %indvar.next, 4 + br i1 %exitcond, label %bb288.bb289.loopexit_crit_edge, label %bb269.us.us.us + +bb286.us.us.us: + unreachable + +bb269.us.us: + unreachable + +bb288.bb289.loopexit_crit_edge: + unreachable +} From wendling at apple.com Tue Aug 31 15:41:44 2010 From: wendling at apple.com (Bill Wendling) Date: Tue, 31 Aug 2010 13:41:44 -0700 Subject: [llvm-commits] [llvm] r112597 - in /llvm/trunk: include/llvm/CodeGen/Passes.h lib/CodeGen/DwarfEHPrepare.cpp lib/CodeGen/LLVMTargetMachine.cpp In-Reply-To: <4C7D61DB.3060009@free.fr> References: <20100831090507.174362A6C12E@llvm.org> <5372C6E6-CC04-4AA2-A6AA-828291B944AE@apple.com> <4C7D57C9.4060307@free.fr> <4C7D61DB.3060009@free.fr> Message-ID: On Aug 31, 2010, at 1:11 PM, Duncan Sands wrote: > Hi Bill, > >>>> I'm fine with this, but please do the alloca promotion using SSAUpdater soon. Otherwise my horrible hack won't work for all of the cases I need it to. As John mentioned, I need to do reachability and not dominance. I'll fix it so that the DomTree stuff isn't needed. >>> >>> we never did any alloca promotion at -O0, so does that mean this already >>> sometimes wasn't working properly at -O0? Also, I wasn't actually planning >>> to do alloca promotion for your 'orrible hack code because it makes my head >>> hurt, but perhaps I can be persuaded... >>> >> The horrible hack is there mostly for inlining, which doesn't occur at -O0. > > aren't you confusing -O0 at the IR level and -O0 codegen? I can optimize some > bitcode with -std-compile-opts and then pass it to "llc -O0"... So in theory > llc needs to deal correctly with inlined code even at -O0. > > We can get away with it in most cases. But it's quite easy to generate a case where it won't work. My guess is that it's a hand-written case that would fail. > > Sounds like a good testcase to have in the testsuite! > In that case, there shouldn't be any load/stores of the EH pointer laying around; at least I hope. Therefore, it would be okay. As for the hand-written test case, it's been noted before that this code won't work for every thing. I tried my best to cover as many cases as I could, but it's sure to have deficiencies. >> I just don't want a regression, and since you took the code out I thought you would replace it. :-) > > There is something to what you say :) > > But if it works, then it's fine being omitted. > > I think I'd better test it harder... > Thanks! :-) -bw From gohman at apple.com Tue Aug 31 15:58:44 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 31 Aug 2010 20:58:44 -0000 Subject: [llvm-commits] [llvm] r112638 - /llvm/trunk/lib/Analysis/ScalarEvolution.cpp Message-ID: <20100831205845.0FD0C2A6C12C@llvm.org> Author: djg Date: Tue Aug 31 15:58:44 2010 New Revision: 112638 URL: http://llvm.org/viewvc/llvm-project?rev=112638&view=rev Log: Revert r112432. It appears to be exposing a problem in the emacs build. Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=112638&r1=112637&r2=112638&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Tue Aug 31 15:58:44 2010 @@ -3332,16 +3332,11 @@ // LLVM IR canonical form means we need only traverse the left operands. SmallVector AddOps; AddOps.push_back(getSCEV(U->getOperand(1))); - for (Value *Op = U->getOperand(0); ; Op = U->getOperand(0)) { - unsigned Opcode = Op->getValueID() - Value::InstructionVal; - if (Opcode != Instruction::Add && Opcode != Instruction::Sub) - break; + for (Value *Op = U->getOperand(0); + Op->getValueID() == Instruction::Add + Value::InstructionVal; + Op = U->getOperand(0)) { U = cast(Op); - const SCEV *Op1 = getSCEV(U->getOperand(1)); - if (Opcode == Instruction::Sub) - AddOps.push_back(getNegativeSCEV(Op1)); - else - AddOps.push_back(Op1); + AddOps.push_back(getSCEV(U->getOperand(1))); } AddOps.push_back(getSCEV(U->getOperand(0))); return getAddExpr(AddOps); From geek4civic at gmail.com Tue Aug 31 16:05:14 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Wed, 1 Sep 2010 06:05:14 +0900 Subject: [llvm-commits] [PATCH] Bugpoint/Support: Fix llvm::FindExecutable not looking for files ending with .exe In-Reply-To: References: <4CAB5B77-B4EB-4E91-B861-D9DE27867AE7@apple.com> Message-ID: Michael, An refined patch is attached. Please take a look. Confirmed on mingw, mingw-cross, f12 and centos5. - get rid of extra sys::Path variable FoundPath - suppose value of FindProgramByName() must be valid when it is not empty ...Takumi -------------- next part -------------- diff --git a/lib/Support/SystemUtils.cpp b/lib/Support/SystemUtils.cpp index 299032f..421b381 100644 --- a/lib/Support/SystemUtils.cpp +++ b/lib/Support/SystemUtils.cpp @@ -49,6 +49,10 @@ sys::Path llvm::FindExecutable(const std::string &ExeName, Result.appendComponent(ExeName); if (Result.canExecute()) return Result; + // Expect to retrieve the pathname with suffix .exe. + Result = sys::Program::FindProgramByName(Result.str()); + if (!Result.empty()) + return Result; } return sys::Path(); From tonic at nondot.org Tue Aug 31 16:04:30 2010 From: tonic at nondot.org (Tanya Lattner) Date: Tue, 31 Aug 2010 21:04:30 -0000 Subject: [llvm-commits] [www] r112639 - /www/trunk/devmtg/students.php Message-ID: <20100831210430.4334B2A6C12C@llvm.org> Author: tbrethou Date: Tue Aug 31 16:04:30 2010 New Revision: 112639 URL: http://llvm.org/viewvc/llvm-project?rev=112639&view=rev Log: Update Modified: www/trunk/devmtg/students.php Modified: www/trunk/devmtg/students.php URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/students.php?rev=112639&r1=112638&r2=112639&view=diff ============================================================================== --- www/trunk/devmtg/students.php (original) +++ www/trunk/devmtg/students.php Tue Aug 31 16:04:30 2010 @@ -245,13 +245,9 @@
      LLVM Developers' Meeting - Student & Active Contributor Funding Request
      -Student Funding is closed for this year. - - - From tonic at nondot.org Tue Aug 31 16:08:25 2010 From: tonic at nondot.org (Tanya Lattner) Date: Tue, 31 Aug 2010 21:08:25 -0000 Subject: [llvm-commits] [www] r112641 - /www/trunk/devmtg/students.php Message-ID: <20100831210825.A45E02A6C12C@llvm.org> Author: tbrethou Date: Tue Aug 31 16:08:25 2010 New Revision: 112641 URL: http://llvm.org/viewvc/llvm-project?rev=112641&view=rev Log: Update Modified: www/trunk/devmtg/students.php Modified: www/trunk/devmtg/students.php URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/students.php?rev=112641&r1=112640&r2=112641&view=diff ============================================================================== --- www/trunk/devmtg/students.php (original) +++ www/trunk/devmtg/students.php Tue Aug 31 16:08:25 2010 @@ -1,5 +1,5 @@ -'; @@ -244,7 +243,7 @@ ?>
      LLVM Developers' Meeting - Student & Active Contributor Funding Request
      - + Author: bruno Date: Tue Aug 31 16:15:21 2010 New Revision: 112642 URL: http://llvm.org/viewvc/llvm-project?rev=112642&view=rev Log: Use MOVLHPS and MOVHLPS x86 nodes whenever possible. Also remove some useless nodes Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.h llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=112642&r1=112641&r2=112642&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Aug 31 16:15:21 2010 @@ -2623,6 +2623,7 @@ switch(Opc) { default: llvm_unreachable("Unknown x86 shuffle node"); case X86ISD::MOVLHPS: + case X86ISD::MOVLHPD: case X86ISD::MOVSS: case X86ISD::MOVSD: case X86ISD::PUNPCKLDQ: @@ -5004,6 +5005,22 @@ return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); } +static +SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, + bool HasSSE2) { + SDValue V1 = Op.getOperand(0); + SDValue V2 = Op.getOperand(1); + EVT VT = Op.getValueType(); + + assert(VT != MVT::v2i64 && "unsupported shuffle type"); + + if (HasSSE2 && VT == MVT::v2f64) + return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG); + + // v4f32 or v4i32 + return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V2, DAG); +} + SDValue X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { ShuffleVectorSDNode *SVOp = cast(Op); @@ -5110,12 +5127,16 @@ } // FIXME: fold these into legal mask. - if (!isMMX && (X86::isMOVSHDUPMask(SVOp) || - X86::isMOVSLDUPMask(SVOp) || - X86::isMOVHLPSMask(SVOp) || - X86::isMOVLHPSMask(SVOp) || - X86::isMOVLPMask(SVOp))) - return Op; + if (!isMMX) { + if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp)) + return getMOVLowToHigh(Op, dl, DAG, HasSSE2); + + if (X86::isMOVSHDUPMask(SVOp) || + X86::isMOVSLDUPMask(SVOp) || + X86::isMOVHLPSMask(SVOp) || + X86::isMOVLPMask(SVOp)) + return Op; + } if (ShouldXformToMOVHLPS(SVOp) || ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp)) @@ -8362,13 +8383,9 @@ case X86ISD::SHUFPS: return "X86ISD::SHUFPS"; case X86ISD::SHUFPD: return "X86ISD::SHUFPD"; case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS"; - case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS"; case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD"; + case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS"; case X86ISD::MOVHLPD: return "X86ISD::MOVHLPD"; - case X86ISD::MOVHPS: return "X86ISD::MOVHPS"; - case X86ISD::MOVLPS: return "X86ISD::MOVLPS"; - case X86ISD::MOVHPD: return "X86ISD::MOVHPD"; - case X86ISD::MOVLPD: return "X86ISD::MOVLPD"; case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP"; case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP"; case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP"; Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=112642&r1=112641&r2=112642&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Tue Aug 31 16:15:21 2010 @@ -266,13 +266,9 @@ MOVSHDUP_LD, MOVSLDUP_LD, MOVLHPS, - MOVHLPS, MOVLHPD, + MOVHLPS, MOVHLPD, - MOVHPS, - MOVHPD, - MOVLPS, - MOVLPD, MOVSD, MOVSS, UNPCKLPS, Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=112642&r1=112641&r2=112642&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Tue Aug 31 16:15:21 2010 @@ -166,14 +166,11 @@ def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>; def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>; -def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>; def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>; + +def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>; def X86Movhlpd : SDNode<"X86ISD::MOVHLPD", SDTShuff2Op>; -def X86MovhpsLd : SDNode<"X86ISD::MOVHPS", SDTShuff2OpLd, - [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; -def X86MovhpdLd : SDNode<"X86ISD::MOVHPD", SDTShuff2OpLd, - [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; def X86MovlpsLd : SDNode<"X86ISD::MOVLPS", SDTShuff2OpLd, [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; def X86MovlpdLd : SDNode<"X86ISD::MOVLPD", SDTShuff2OpLd, Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=112642&r1=112641&r2=112642&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Aug 31 16:15:21 2010 @@ -5664,22 +5664,6 @@ def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))), (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>; -// Shuffle with MOVLHPS instruction -def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)), - (VMOVLHPSrr (v4f32 VR128:$src1), VR128:$src2)>, Requires<[HasAVX]>; -def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)), - (MOVLHPSrr (v4f32 VR128:$src1), VR128:$src2)>; - -def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)), - (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>, Requires<[HasAVX]>; -def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)), - (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>; - -def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)), - (VMOVLHPSrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>; -def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)), - (MOVLHPSrr VR128:$src1, VR128:$src2)>; - // Shuffle with MOVHLPS instruction def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)), (MOVHLPSrr VR128:$src1, VR128:$src2)>; @@ -5817,28 +5801,25 @@ def : Pat<(v2i64 (X86Punpckhqdq VR128:$src1, VR128:$src2)), (PUNPCKHQDQrr VR128:$src1, VR128:$src2)>; -// Shuffle with MOVHPS -def : Pat<(v4f32 (X86MovhpsLd VR128:$src1, addr:$src2)), +// Shuffle with MOVLHPS +def : Pat<(X86Movlhps VR128:$src1, + (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))), (MOVHPSrm VR128:$src1, addr:$src2)>; -def : Pat<(v4i32 (X86MovhpsLd VR128:$src1, addr:$src2)), +def : Pat<(X86Movlhps VR128:$src1, + (bc_v4i32 (v2i64 (X86vzload addr:$src2)))), (MOVHPSrm VR128:$src1, addr:$src2)>; +def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)), + (MOVLHPSrr VR128:$src1, VR128:$src2)>; +def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)), + (MOVLHPSrr VR128:$src1, VR128:$src2)>; +def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)), + (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>; -// Shuffle with MOVHPD -def : Pat<(v2f64 (X86MovhpdLd VR128:$src1, addr:$src2)), +// Shuffle with MOVLHPD +def : Pat<(v2f64 (X86Movlhpd VR128:$src1, + (scalar_to_vector (loadf64 addr:$src2)))), (MOVHPDrm VR128:$src1, addr:$src2)>; -// Shuffle with MOVLPS -def : Pat<(v4f32 (X86MovlpsLd VR128:$src1, addr:$src2)), - (MOVLPSrm VR128:$src1, addr:$src2)>; -def : Pat<(v4i32 (X86MovlpsLd VR128:$src1, addr:$src2)), - (MOVLPSrm VR128:$src1, addr:$src2)>; - -// Shuffle with MOVLPD -def : Pat<(v2f64 (X86MovlpdLd VR128:$src1, addr:$src2)), - (MOVLPDrm VR128:$src1, addr:$src2)>; -def : Pat<(v2i64 (X86MovlpdLd VR128:$src1, addr:$src2)), - (MOVLPDrm VR128:$src1, addr:$src2)>; - // Shuffle with MOVSS def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))), (MOVSSrr VR128:$src1, FR32:$src2)>; @@ -5928,13 +5909,3 @@ (v2f64 (X86Unpckhpd VR128:$src, (undef))), (iPTR 0))),addr:$dst), (MOVHPDmr addr:$dst, VR128:$src)>; -def : Pat<(store (v2f64 (X86MovlpdLd VR128:$src1, addr:$src2)),addr:$src2), - (MOVLPDmr addr:$src2, VR128:$src1)>; -def : Pat<(store (v2i64 (X86MovlpdLd VR128:$src1, addr:$src2)),addr:$src2), - (MOVLPDmr addr:$src2, VR128:$src1)>; - -def : Pat<(store (v4f32 (X86MovlpsLd VR128:$src1, addr:$src2)),addr:$src2), - (MOVLPSmr addr:$src2, VR128:$src1)>; -def : Pat<(store (v4i32 (X86MovlpsLd VR128:$src1, addr:$src2)),addr:$src2), - (MOVLPSmr addr:$src2, VR128:$src1)>; - From sabre at nondot.org Tue Aug 31 16:21:25 2010 From: sabre at nondot.org (Chris Lattner) Date: Tue, 31 Aug 2010 21:21:25 -0000 Subject: [llvm-commits] [llvm] r112643 - /llvm/trunk/lib/Transforms/Scalar/TailRecursionElimination.cpp Message-ID: <20100831212125.3ABF02A6C12C@llvm.org> Author: lattner Date: Tue Aug 31 16:21:25 2010 New Revision: 112643 URL: http://llvm.org/viewvc/llvm-project?rev=112643&view=rev Log: tidy up Modified: llvm/trunk/lib/Transforms/Scalar/TailRecursionElimination.cpp Modified: llvm/trunk/lib/Transforms/Scalar/TailRecursionElimination.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/TailRecursionElimination.cpp?rev=112643&r1=112642&r2=112643&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/TailRecursionElimination.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/TailRecursionElimination.cpp Tue Aug 31 16:21:25 2010 @@ -278,22 +278,22 @@ Function *F = CI->getParent()->getParent(); Value *ReturnedValue = 0; - for (Function::iterator BBI = F->begin(), E = F->end(); BBI != E; ++BBI) - if (ReturnInst *RI = dyn_cast(BBI->getTerminator())) - if (RI != IgnoreRI) { - Value *RetOp = RI->getOperand(0); - - // We can only perform this transformation if the value returned is - // evaluatable at the start of the initial invocation of the function, - // instead of at the end of the evaluation. - // - if (!isDynamicConstant(RetOp, CI, RI)) - return 0; - - if (ReturnedValue && RetOp != ReturnedValue) - return 0; // Cannot transform if differing values are returned. - ReturnedValue = RetOp; - } + for (Function::iterator BBI = F->begin(), E = F->end(); BBI != E; ++BBI) { + ReturnInst *RI = dyn_cast(BBI->getTerminator()); + if (RI == 0 || RI == IgnoreRI) continue; + + // We can only perform this transformation if the value returned is + // evaluatable at the start of the initial invocation of the function, + // instead of at the end of the evaluation. + // + Value *RetOp = RI->getOperand(0); + if (!isDynamicConstant(RetOp, CI, RI)) + return 0; + + if (ReturnedValue && RetOp != ReturnedValue) + return 0; // Cannot transform if differing values are returned. + ReturnedValue = RetOp; + } return ReturnedValue; } @@ -307,7 +307,7 @@ assert(I->getNumOperands() == 2 && "Associative/commutative operations should have 2 args!"); - // Exactly one operand should be the result of the call instruction... + // Exactly one operand should be the result of the call instruction. if ((I->getOperand(0) == CI && I->getOperand(1) == CI) || (I->getOperand(0) != CI && I->getOperand(1) != CI)) return 0; @@ -387,21 +387,22 @@ // tail call if all of the instructions between the call and the return are // movable to above the call itself, leaving the call next to the return. // Check that this is the case now. - for (BBI = CI, ++BBI; &*BBI != Ret; ++BBI) - if (!CanMoveAboveCall(BBI, CI)) { - // If we can't move the instruction above the call, it might be because it - // is an associative and commutative operation that could be tranformed - // using accumulator recursion elimination. Check to see if this is the - // case, and if so, remember the initial accumulator value for later. - if ((AccumulatorRecursionEliminationInitVal = - CanTransformAccumulatorRecursion(BBI, CI))) { - // Yes, this is accumulator recursion. Remember which instruction - // accumulates. - AccumulatorRecursionInstr = BBI; - } else { - return false; // Otherwise, we cannot eliminate the tail recursion! - } + for (BBI = CI, ++BBI; &*BBI != Ret; ++BBI) { + if (CanMoveAboveCall(BBI, CI)) continue; + + // If we can't move the instruction above the call, it might be because it + // is an associative and commutative operation that could be tranformed + // using accumulator recursion elimination. Check to see if this is the + // case, and if so, remember the initial accumulator value for later. + if ((AccumulatorRecursionEliminationInitVal = + CanTransformAccumulatorRecursion(BBI, CI))) { + // Yes, this is accumulator recursion. Remember which instruction + // accumulates. + AccumulatorRecursionInstr = BBI; + } else { + return false; // Otherwise, we cannot eliminate the tail recursion! } + } // We can only transform call/return pairs that either ignore the return value // of the call and return void, ignore the value of the call and return a From bruno.cardoso at gmail.com Tue Aug 31 16:38:49 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 31 Aug 2010 21:38:49 -0000 Subject: [llvm-commits] [llvm] r112644 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20100831213850.210842A6C12C@llvm.org> Author: bruno Date: Tue Aug 31 16:38:49 2010 New Revision: 112644 URL: http://llvm.org/viewvc/llvm-project?rev=112644&view=rev Log: Use MOVHLPS node instead of matching using movhlps and movhlps_undef pattern fragments Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=112644&r1=112643&r2=112644&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Aug 31 16:38:49 2010 @@ -2585,6 +2585,7 @@ case X86ISD::SHUFPD: case X86ISD::SHUFPS: case X86ISD::MOVLHPS: + case X86ISD::MOVHLPS: case X86ISD::MOVSS: case X86ISD::MOVSD: case X86ISD::PUNPCKLDQ: @@ -2624,6 +2625,7 @@ default: llvm_unreachable("Unknown x86 shuffle node"); case X86ISD::MOVLHPS: case X86ISD::MOVLHPD: + case X86ISD::MOVHLPS: case X86ISD::MOVSS: case X86ISD::MOVSD: case X86ISD::PUNPCKLDQ: @@ -5021,6 +5023,22 @@ return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V2, DAG); } +static +SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) { + SDValue V1 = Op.getOperand(0); + SDValue V2 = Op.getOperand(1); + EVT VT = Op.getValueType(); + + assert((VT == MVT::v4i32 || VT == MVT::v4f32) && + "unsupported shuffle type"); + + if (V2.getOpcode() == ISD::UNDEF) + V2 = V1; + + // v4i32 or v4f32 + return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG); +} + SDValue X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { ShuffleVectorSDNode *SVOp = cast(Op); @@ -5131,6 +5149,9 @@ if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp)) return getMOVLowToHigh(Op, dl, DAG, HasSSE2); + if (X86::isMOVHLPSMask(SVOp)) + return getMOVHighToLow(Op, dl, DAG); + if (X86::isMOVSHDUPMask(SVOp) || X86::isMOVSLDUPMask(SVOp) || X86::isMOVHLPSMask(SVOp) || From geek4civic at gmail.com Tue Aug 31 16:47:53 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Wed, 1 Sep 2010 06:47:53 +0900 Subject: [llvm-commits] [PATCH] test/ shlibdir-aware Message-ID: Good September! (in here) With ENABLE_SHARED on win32, DLL files are located not to lib but bin. Some of tests assume modules might be in %llvmlibsdir. My patch provides %llvmshlibdir to let some tests pass on Cygwin and Mingw. Please review mine. TODO: I don't have CMake environments yet. Known issue: BugpointPasses.dll and LLVMHello.dll might be rebased explicitly. ...Takumi -------------- next part -------------- diff --git a/test/Analysis/Profiling/profiling-tool-chain.ll b/test/Analysis/Profiling/profiling-tool-chain.ll index 5ac31b5..ad2dd13 100644 --- a/test/Analysis/Profiling/profiling-tool-chain.ll +++ b/test/Analysis/Profiling/profiling-tool-chain.ll @@ -9,8 +9,8 @@ ; Test the creation, reading and displaying of profile ; RUX: rm -f llvmprof.out -; RUX: lli -load %llvmlibsdir/profile_rt%shlibext %t2 -; RUX: lli -load %llvmlibsdir/profile_rt%shlibext %t2 1 2 +; RUX: lli -load %llvmshlisdir/profile_rt%shlibext %t2 +; RUX: lli -load %llvmshlisdir/profile_rt%shlibext %t2 1 2 ; RUX: llvm-prof -print-all-code %t1 | FileCheck --check-prefix=PROF %s ; Test the loaded profile also with verifier. diff --git a/test/BugPoint/crash-narrowfunctiontest.ll b/test/BugPoint/crash-narrowfunctiontest.ll index 18a31eb..df0b07f 100644 --- a/test/BugPoint/crash-narrowfunctiontest.ll +++ b/test/BugPoint/crash-narrowfunctiontest.ll @@ -1,7 +1,7 @@ ; Test that bugpoint can narrow down the testcase to the important function ; FIXME: This likely fails on windows ; -; RUN: bugpoint -load %llvmlibsdir/BugpointPasses%shlibext %s -output-prefix %t -bugpoint-crashcalls -silence-passes > /dev/null +; RUN: bugpoint -load %llvmshlibdir/BugpointPasses%shlibext %s -output-prefix %t -bugpoint-crashcalls -silence-passes > /dev/null ; XFAIL: mingw define i32 @foo() { ret i32 1 } diff --git a/test/BugPoint/metadata.ll b/test/BugPoint/metadata.ll index f2541ee..eda234a 100644 --- a/test/BugPoint/metadata.ll +++ b/test/BugPoint/metadata.ll @@ -1,4 +1,4 @@ -; RUN: bugpoint -load %llvmlibsdir/BugpointPasses%shlibext %s -output-prefix %t -bugpoint-crashcalls -silence-passes > /dev/null +; RUN: bugpoint -load %llvmshlibdir/BugpointPasses%shlibext %s -output-prefix %t -bugpoint-crashcalls -silence-passes > /dev/null ; RUN: llvm-dis %t-reduced-simplified.bc -o - | FileCheck %s ; XFAIL: mingw diff --git a/test/BugPoint/remove_arguments_test.ll b/test/BugPoint/remove_arguments_test.ll index 791ec69..bed4c02 100644 --- a/test/BugPoint/remove_arguments_test.ll +++ b/test/BugPoint/remove_arguments_test.ll @@ -1,5 +1,5 @@ ; FIXME: This likely fails on windows -; RUN: bugpoint -load %llvmlibsdir/BugpointPasses%shlibext %s -output-prefix %t -bugpoint-crashcalls -silence-passes +; RUN: bugpoint -load %llvmshlibdir/BugpointPasses%shlibext %s -output-prefix %t -bugpoint-crashcalls -silence-passes ; RUN: llvm-dis %t-reduced-simplified.bc -o - | FileCheck %s ; XFAIL: mingw diff --git a/test/Feature/load_module.ll b/test/Feature/load_module.ll index e2e222f..11eb6fe 100644 --- a/test/Feature/load_module.ll +++ b/test/Feature/load_module.ll @@ -1,5 +1,5 @@ ; PR1318 -; RUN: opt < %s -load=%llvmlibsdir/LLVMHello%shlibext -hello \ +; RUN: opt < %s -load=%llvmshlibdir/LLVMHello%shlibext -hello \ ; RUN: -disable-output |& grep Hello @junk = global i32 0 diff --git a/test/Makefile b/test/Makefile index 7ca46be..bd46b1d 100644 --- a/test/Makefile +++ b/test/Makefile @@ -138,6 +138,7 @@ site.exp: FORCE @echo 'set llvmgcc_langs "$(LLVMGCC_LANGS)"' >> site.tmp @echo 'set llvmtoolsdir "$(ToolDir)"' >>site.tmp @echo 'set llvmlibsdir "$(LibDir)"' >>site.tmp + @echo 'set llvmshlibdir "$(SharedLibDir)"' >>site.tmp @echo 'set llvm_bindings "$(BINDINGS_TO_BUILD)"' >> site.tmp @echo 'set srcroot "$(LLVM_SRC_ROOT)"' >>site.tmp @echo 'set objroot "$(LLVM_OBJ_ROOT)"' >>site.tmp @@ -180,6 +181,7 @@ Unit/lit.site.cfg: $(PROJ_OBJ_DIR)/Unit/.dir FORCE -e "s#@LLVMGCCDIR@#$(LLVMGCCDIR)#g" \ -e "s#@LLVM_BUILD_MODE@#$(BuildMode)#g" \ -e "s#@ENABLE_SHARED@#$(ENABLE_SHARED)#g" \ + -e "s#@SHLIBDIR@#$(SharedLibDir)#g" \ -e "s#@SHLIBPATH_VAR@#$(SHLIBPATH_VAR)#g" \ $(PROJ_SRC_DIR)/Unit/lit.site.cfg.in > $@ diff --git a/test/Unit/lit.cfg b/test/Unit/lit.cfg index 5fe0732..a41f093 100644 --- a/test/Unit/lit.cfg +++ b/test/Unit/lit.cfg @@ -25,11 +25,10 @@ config.test_format = lit.formats.GoogleTest(llvm_build_mode, 'Tests') # If necessary, point the dynamic loader at libLLVM.so. if config.enable_shared: - libdir = os.path.join(config.llvm_obj_root, config.llvm_build_mode, 'lib') shlibpath = config.environment.get(config.shlibpath_var,'') if shlibpath: - shlibpath = ':' + shlibpath - shlibpath = libdir + shlibpath + shlibpath = os.pathsep + shlibpath + shlibpath = config.shlibdir + shlibpath config.environment[config.shlibpath_var] = shlibpath # Check that the object root is known. diff --git a/test/Unit/lit.site.cfg.in b/test/Unit/lit.site.cfg.in index 51b5bc4..37de065 100644 --- a/test/Unit/lit.site.cfg.in +++ b/test/Unit/lit.site.cfg.in @@ -6,6 +6,7 @@ config.llvm_tools_dir = "@LLVM_TOOLS_DIR@" config.llvmgcc_dir = "@LLVMGCCDIR@" config.llvm_build_mode = "@LLVM_BUILD_MODE@" config.enable_shared = @ENABLE_SHARED@ +config.shlibdir = "@SHLIBDIR@" config.shlibpath_var = "@SHLIBPATH_VAR@" # Let the main config do the real work. diff --git a/test/lit.cfg b/test/lit.cfg index f15777c..0db6d1e 100644 --- a/test/lit.cfg +++ b/test/lit.cfg @@ -126,7 +126,8 @@ for line in open(os.path.join(config.llvm_obj_root, 'test', 'site.exp')): # Add substitutions. config.substitutions.append(('%llvmgcc_only', site_exp['llvmgcc'])) for sub in ['llvmgcc', 'llvmgxx', 'compile_cxx', 'compile_c', - 'link', 'shlibext', 'ocamlopt', 'llvmdsymutil', 'llvmlibsdir', + 'link', 'ocamlopt', 'llvmdsymutil', 'llvmlibsdir', + 'llvmshlibdir', 'shlibext', 'bugpoint_topts']: if sub in ('llvmgcc', 'llvmgxx'): config.substitutions.append(('%' + sub, From aggarwa4 at illinois.edu Tue Aug 31 16:47:33 2010 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Tue, 31 Aug 2010 21:47:33 -0000 Subject: [llvm-commits] [poolalloc] r112645 - /poolalloc/trunk/lib/DSA/BottomUpClosure.cpp Message-ID: <20100831214733.EC8A02A6C12C@llvm.org> Author: aggarwa4 Date: Tue Aug 31 16:47:33 2010 New Revision: 112645 URL: http://llvm.org/viewvc/llvm-project?rev=112645&view=rev Log: The \!hasDSGraph was wrong, as all functions have DSGraphs at this point. The check needs to be whether or not the function has been visited yet. Modified: poolalloc/trunk/lib/DSA/BottomUpClosure.cpp Modified: poolalloc/trunk/lib/DSA/BottomUpClosure.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/BottomUpClosure.cpp?rev=112645&r1=112644&r2=112645&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/BottomUpClosure.cpp (original) +++ poolalloc/trunk/lib/DSA/BottomUpClosure.cpp Tue Aug 31 16:47:33 2010 @@ -327,7 +327,7 @@ // Calculate the graphs for any functions that are unreachable from main... // for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I) - if (!I->isDeclaration() && !hasDSGraph(*I)) { + if (!I->isDeclaration() && !ValMap.count(I)) { if (MainFunc) DEBUG(errs() << debugname << ": Function unreachable from main: " << I->getName() << "\n"); From tonic at nondot.org Tue Aug 31 16:49:31 2010 From: tonic at nondot.org (Tanya Lattner) Date: Tue, 31 Aug 2010 21:49:31 -0000 Subject: [llvm-commits] [www] r112647 - /www/trunk/devmtg/2010-11/index.html Message-ID: <20100831214931.A1FAC2A6C12C@llvm.org> Author: tbrethou Date: Tue Aug 31 16:49:31 2010 New Revision: 112647 URL: http://llvm.org/viewvc/llvm-project?rev=112647&view=rev Log: Add information about 2010 developers meeting. Modified: www/trunk/devmtg/2010-11/index.html Modified: www/trunk/devmtg/2010-11/index.html URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2010-11/index.html?rev=112647&r1=112646&r2=112647&view=diff ============================================================================== --- www/trunk/devmtg/2010-11/index.html (original) +++ www/trunk/devmtg/2010-11/index.html Tue Aug 31 16:49:31 2010 @@ -4,7 +4,10 @@
        +
      1. Registration & Logistics
      2. Call for Speakers
        3. +
      3. Sponsors Needed
        4. +
      4. Funding for Active Contributors/Students
        @@ -12,7 +15,8 @@
      • Why: To get acquainted, learn how LLVM is used, and exchange ideas.
        • -
      • When: November X, 2010
        • +
      • When: November 4, 2010
        • +
      • Where: San Jose, CA (Details coming soon)
      @@ -33,6 +37,28 @@
    • Those interested in using compiler technology in novel and interesting ways.
    +
    Registration & Logistics
    + +Registration and logistical information coming soon. Please stay tuned. + +
    Call for Speakers
    + +

    We are looking for speakers for this year's developers meeting! Specifically +we'd love talks on the LLVM or Clang core infrastructure or new uses of LLVM or Clang.

    +

    If you are interested in presenting at this year's LLVM Developers' +Meeting, please submit your talk proposal to us by September 22, 2010 via +the website.

    + +
    Sponsors Needed
    + +

    We are looking for companies to fund active contributors or students to present at this years meeting. We are also looking for companies to sponsor a dinner event after the meeting. Please email us if your company is able to help.

    + +
    Funding for Active Contributors/Students
    + +

    At this time, we are not sure if there will be funding for active contributors or students to attend the event. However, we are hopeful that we will have company sponsorship to make this happen. Those who are funded are required to present at the meeting and may have other requirements from their sponsor (ie. writing a blog post, etc).

    + +

    If you need funding to attend the meeting, please submit your request to us by September 22, 2010 via the website.

    +
    From tonic at nondot.org Tue Aug 31 16:50:40 2010 From: tonic at nondot.org (Tanya Lattner) Date: Tue, 31 Aug 2010 21:50:40 -0000 Subject: [llvm-commits] [www] r112648 - /www/trunk/devmtg/2010-11/index.html Message-ID: <20100831215040.2C1382A6C12C@llvm.org> Author: tbrethou Date: Tue Aug 31 16:50:39 2010 New Revision: 112648 URL: http://llvm.org/viewvc/llvm-project?rev=112648&view=rev Log: Add p tags. Modified: www/trunk/devmtg/2010-11/index.html Modified: www/trunk/devmtg/2010-11/index.html URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2010-11/index.html?rev=112648&r1=112647&r2=112648&view=diff ============================================================================== --- www/trunk/devmtg/2010-11/index.html (original) +++ www/trunk/devmtg/2010-11/index.html Tue Aug 31 16:50:39 2010 @@ -39,7 +39,7 @@
    Registration & Logistics
    -Registration and logistical information coming soon. Please stay tuned. +

    Registration and logistical information coming soon. Please stay tuned.

    Call for Speakers
    From stoklund at 2pi.dk Tue Aug 31 16:51:05 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 31 Aug 2010 21:51:05 -0000 Subject: [llvm-commits] [llvm] r112649 - /llvm/trunk/lib/CodeGen/DeadMachineInstructionElim.cpp Message-ID: <20100831215105.6073F2A6C12C@llvm.org> Author: stoklund Date: Tue Aug 31 16:51:05 2010 New Revision: 112649 URL: http://llvm.org/viewvc/llvm-project?rev=112649&view=rev Log: Track liveness of unallocatable, unreserved registers in machine DCE. Reserved registers are unpredictable, and are treated as always live by machine DCE. Allocatable registers are never reserved, and can be used for virtual registers. Unreserved, unallocatable registers can not be used for virtual registers, but otherwise behave like a normal allocatable register. Most targets only have the flag register in this set. Modified: llvm/trunk/lib/CodeGen/DeadMachineInstructionElim.cpp Modified: llvm/trunk/lib/CodeGen/DeadMachineInstructionElim.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DeadMachineInstructionElim.cpp?rev=112649&r1=112648&r2=112649&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/DeadMachineInstructionElim.cpp (original) +++ llvm/trunk/lib/CodeGen/DeadMachineInstructionElim.cpp Tue Aug 31 16:51:05 2010 @@ -80,9 +80,8 @@ TRI = MF.getTarget().getRegisterInfo(); TII = MF.getTarget().getInstrInfo(); - // Compute a bitvector to represent all non-allocatable physregs. - BitVector NonAllocatableRegs = TRI->getAllocatableSet(MF); - NonAllocatableRegs.flip(); + // Treat reserved registers as always live. + BitVector ReservedRegs = TRI->getReservedRegs(MF); // Loop over all instructions in all blocks, from bottom to top, so that it's // more likely that chains of dependent but ultimately dead instructions will @@ -91,9 +90,8 @@ I != E; ++I) { MachineBasicBlock *MBB = &*I; - // Start out assuming that all non-allocatable registers are live - // out of this block. - LivePhysRegs = NonAllocatableRegs; + // Start out assuming that reserved registers are live out of this block. + LivePhysRegs = ReservedRegs; // Also add any explicit live-out physregs for this block. if (!MBB->empty() && MBB->back().getDesc().isReturn()) @@ -104,6 +102,10 @@ LivePhysRegs.set(Reg); } + // FIXME: Add live-ins from sucessors to LivePhysRegs. Normally, physregs + // are not live across blocks, but some targets (x86) can have flags live + // out of a block. + // Now scan the instructions and delete dead ones, tracking physreg // liveness as we go. for (MachineBasicBlock::reverse_iterator MII = MBB->rbegin(), From stoklund at 2pi.dk Tue Aug 31 16:51:07 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 31 Aug 2010 21:51:07 -0000 Subject: [llvm-commits] [llvm] r112650 - /llvm/trunk/lib/Target/X86/X86RegisterInfo.td Message-ID: <20100831215108.012CD2A6C12D@llvm.org> Author: stoklund Date: Tue Aug 31 16:51:07 2010 New Revision: 112650 URL: http://llvm.org/viewvc/llvm-project?rev=112650&view=rev Log: Make %EFLAGS unallocatable. No CCR virtual registers should exist, and %EFLAGS is used in ways that can surprise RegAllocFast. Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=112650&r1=112649&r2=112650&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Tue Aug 31 16:51:07 2010 @@ -833,4 +833,15 @@ // Status flags registers. def CCR : RegisterClass<"X86", [i32], 32, [EFLAGS]> { let CopyCost = -1; // Don't allow copying of status registers. + + // EFLAGS is not allocatable. + let MethodProtos = [{ + iterator allocation_order_end(const MachineFunction &MF) const; + }]; + let MethodBodies = [{ + CCRClass::iterator + CCRClass::allocation_order_end(const MachineFunction &MF) const { + return allocation_order_begin(MF); + } + }]; } From tonic at nondot.org Tue Aug 31 16:52:51 2010 From: tonic at nondot.org (Tanya Lattner) Date: Tue, 31 Aug 2010 21:52:51 -0000 Subject: [llvm-commits] [www] r112651 - /www/trunk/devmtg/2010-11/index.html Message-ID: <20100831215251.C9DE02A6C12C@llvm.org> Author: tbrethou Date: Tue Aug 31 16:52:51 2010 New Revision: 112651 URL: http://llvm.org/viewvc/llvm-project?rev=112651&view=rev Log: Cleanup. Modified: www/trunk/devmtg/2010-11/index.html Modified: www/trunk/devmtg/2010-11/index.html URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2010-11/index.html?rev=112651&r1=112650&r2=112651&view=diff ============================================================================== --- www/trunk/devmtg/2010-11/index.html (original) +++ www/trunk/devmtg/2010-11/index.html Tue Aug 31 16:52:51 2010 @@ -66,7 +66,7 @@ src="http://jigsaw.w3.org/css-validator/images/vcss" alt="Valid CSS!"> Valid HTML 4.01! -
    Last modified: $Date: 2009/12/01 05:29:47 $ +
    From dalej at apple.com Tue Aug 31 16:53:15 2010 From: dalej at apple.com (Dale Johannesen) Date: Tue, 31 Aug 2010 21:53:15 -0000 Subject: [llvm-commits] [llvm] r112652 - /llvm/trunk/include/llvm/Intrinsics.td Message-ID: <20100831215315.B733A2A6C12C@llvm.org> Author: johannes Date: Tue Aug 31 16:53:15 2010 New Revision: 112652 URL: http://llvm.org/viewvc/llvm-project?rev=112652&view=rev Log: Comment typo. Modified: llvm/trunk/include/llvm/Intrinsics.td Modified: llvm/trunk/include/llvm/Intrinsics.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Intrinsics.td?rev=112652&r1=112651&r2=112652&view=diff ============================================================================== --- llvm/trunk/include/llvm/Intrinsics.td (original) +++ llvm/trunk/include/llvm/Intrinsics.td Tue Aug 31 16:53:15 2010 @@ -114,7 +114,7 @@ def llvm_v8i8_ty : LLVMType; // 8 x i8 def llvm_v16i8_ty : LLVMType; // 16 x i8 def llvm_v32i8_ty : LLVMType; // 32 x i8 -def llvm_v2i16_ty : LLVMType; // 4 x i16 +def llvm_v2i16_ty : LLVMType; // 2 x i16 def llvm_v4i16_ty : LLVMType; // 4 x i16 def llvm_v8i16_ty : LLVMType; // 8 x i16 def llvm_v16i16_ty : LLVMType; // 16 x i16 From geek4civic at gmail.com Tue Aug 31 17:00:11 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Wed, 1 Sep 2010 07:00:11 +0900 Subject: [llvm-commits] [PATCH] test/CodeGen/X86 patches for win32 Message-ID: Good morning. This patch is set of tweaks for win32 to test/CodeGen/X86 Some issues are on win32. - EH is disabled by default. - @main() with extra calling __main. - stack allocatoin In fact, all tests in CodeGen/X86 pass on Cygwin, but I am not sure my patch would be reasonable. Please review it. ...Takumi -------------- next part -------------- diff --git a/test/CodeGen/X86/2009-03-13-PHIElimBug.ll b/test/CodeGen/X86/2009-03-13-PHIElimBug.ll index 8d42627..7652587 100644 --- a/test/CodeGen/X86/2009-03-13-PHIElimBug.ll +++ b/test/CodeGen/X86/2009-03-13-PHIElimBug.ll @@ -2,6 +2,9 @@ ; Check the register copy comes after the call to f and before the call to g ; PR3784 +; EH is not supported by default on codegen win32. +; XFAIL: cygwin,mingw,win32 + declare i32 @f() declare i32 @g() diff --git a/test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll b/test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll index da493d4..d089d36 100644 --- a/test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll +++ b/test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll @@ -1,6 +1,9 @@ ; RUN: llc < %s -march=x86 -asm-verbose | FileCheck %s ; Check that register copies in the landing pad come after the EH_LABEL +; EH is not supported by default on codegen win32. +; XFAIL: cygwin,mingw,win32 + declare i32 @f() define i32 @phi(i32 %x) { diff --git a/test/CodeGen/X86/dyn-stackalloc.ll b/test/CodeGen/X86/dyn-stackalloc.ll index 1df0920..d25c570 100644 --- a/test/CodeGen/X86/dyn-stackalloc.ll +++ b/test/CodeGen/X86/dyn-stackalloc.ll @@ -2,6 +2,9 @@ ; RUN: llc < %s -march=x86 | egrep {\\\$4294967280|-16} ; RUN: llc < %s -march=x86-64 | grep {\\-16} +; XFAIL: cygwin,mingw,win32 +; FIXME: This works with -mtriple=linux. + define void @t() nounwind { A: br label %entry diff --git a/test/CodeGen/X86/loop-strength-reduce4.ll b/test/CodeGen/X86/loop-strength-reduce4.ll index 6c0eb8c..6556fde 100644 --- a/test/CodeGen/X86/loop-strength-reduce4.ll +++ b/test/CodeGen/X86/loop-strength-reduce4.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=x86 -relocation-model=static -mtriple=i686-apple-darwin | FileCheck %s -check-prefix=STATIC -; RUN: llc < %s -march=x86 -relocation-model=pic | FileCheck %s -check-prefix=PIC +; RUN: llc < %s -mtriple=i686-apple-darwin -relocation-model=static | FileCheck %s -check-prefix=STATIC +; RUN: llc < %s -mtriple=i686-apple-darwin -relocation-model=pic | FileCheck %s -check-prefix=PIC ; By starting the IV at -64 instead of 0, a cmp is eliminated, ; as the flags from the add can be used directly. diff --git a/test/CodeGen/X86/twoaddr-coalesce.ll b/test/CodeGen/X86/twoaddr-coalesce.ll index 4c37225..6f6d6f2 100644 --- a/test/CodeGen/X86/twoaddr-coalesce.ll +++ b/test/CodeGen/X86/twoaddr-coalesce.ll @@ -3,7 +3,7 @@ @"\01LC" = internal constant [4 x i8] c"%d\0A\00" ; <[4 x i8]*> [#uses=1] -define i32 @main() nounwind { +define i32 @foo() nounwind { bb1.thread: br label %bb1 From stoklund at 2pi.dk Tue Aug 31 17:01:07 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 31 Aug 2010 22:01:07 -0000 Subject: [llvm-commits] [llvm] r112653 - /llvm/trunk/docs/CodeGenerator.html Message-ID: <20100831220107.9336E2A6C12C@llvm.org> Author: stoklund Date: Tue Aug 31 17:01:07 2010 New Revision: 112653 URL: http://llvm.org/viewvc/llvm-project?rev=112653&view=rev Log: Stack slot access methods are in TargetInstrInfo. Modified: llvm/trunk/docs/CodeGenerator.html Modified: llvm/trunk/docs/CodeGenerator.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CodeGenerator.html?rev=112653&r1=112652&r2=112653&view=diff ============================================================================== --- llvm/trunk/docs/CodeGenerator.html (original) +++ llvm/trunk/docs/CodeGenerator.html Tue Aug 31 17:01:07 2010 @@ -1457,8 +1457,8 @@ order to get and store values in memory. To assign a physical register to a virtual register present in a given operand, use MachineOperand::setReg(p_reg). To insert a store instruction, - use TargetRegisterInfo::storeRegToStackSlot(...), and to insert a - load instruction, use TargetRegisterInfo::loadRegFromStackSlot.

    + use TargetInstrInfo::storeRegToStackSlot(...), and to insert a + load instruction, use TargetInstrInfo::loadRegFromStackSlot.

    The indirect mapping shields the application developer from the complexities of inserting load and store instructions. In order to map a virtual register From isanbard at gmail.com Tue Aug 31 17:05:37 2010 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 31 Aug 2010 22:05:37 -0000 Subject: [llvm-commits] [llvm] r112654 - /llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Message-ID: <20100831220537.6EE3A2A6C12C@llvm.org> Author: void Date: Tue Aug 31 17:05:37 2010 New Revision: 112654 URL: http://llvm.org/viewvc/llvm-project?rev=112654&view=rev Log: And ANDS pattern to match the t2ANDS pattern. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=112654&r1=112653&r2=112654&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Aug 31 17:05:37 2010 @@ -1856,6 +1856,8 @@ defm AND : AsI1_bin_irs<0b0000, "and", BinOpFrag<(and node:$LHS, node:$RHS)>, 1>; +defm ANDS : AI1_bin_s_irs<0b0000, "and", + BinOpFrag<(ARMand node:$LHS, node:$RHS)>, 1>; defm ORR : AsI1_bin_irs<0b1100, "orr", BinOpFrag<(or node:$LHS, node:$RHS)>, 1>; defm EOR : AsI1_bin_irs<0b0001, "eor", From bruno.cardoso at gmail.com Tue Aug 31 17:22:11 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 31 Aug 2010 22:22:11 -0000 Subject: [llvm-commits] [llvm] r112657 - in /llvm/trunk/lib/Target/X86: X86ISelLowering.cpp X86InstrSSE.td Message-ID: <20100831222211.7CDA72A6C12C@llvm.org> Author: bruno Date: Tue Aug 31 17:22:11 2010 New Revision: 112657 URL: http://llvm.org/viewvc/llvm-project?rev=112657&view=rev Log: Use x86 specific MOVSHDUP node and add more patterns to match it Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=112657&r1=112656&r2=112657&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Aug 31 17:22:11 2010 @@ -2586,6 +2586,7 @@ case X86ISD::SHUFPS: case X86ISD::MOVLHPS: case X86ISD::MOVHLPS: + case X86ISD::MOVSHDUP: case X86ISD::MOVSS: case X86ISD::MOVSD: case X86ISD::PUNPCKLDQ: @@ -2595,6 +2596,17 @@ } static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, + SDValue V1, SelectionDAG &DAG) { + switch(Opc) { + default: llvm_unreachable("Unknown x86 shuffle node"); + case X86ISD::MOVSHDUP: + return DAG.getNode(Opc, dl, VT, V1); + } + + return SDValue(); +} + +static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, SDValue V1, unsigned TargetMask, SelectionDAG &DAG) { switch(Opc) { default: llvm_unreachable("Unknown x86 shuffle node"); @@ -5053,6 +5065,7 @@ bool V1IsSplat = false; bool V2IsSplat = false; bool HasSSE2 = Subtarget->hasSSE2() || Subtarget->hasAVX(); + bool HasSSE3 = Subtarget->hasSSE3() || Subtarget->hasAVX(); MachineFunction &MF = DAG.getMachineFunction(); bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize); @@ -5152,8 +5165,10 @@ if (X86::isMOVHLPSMask(SVOp)) return getMOVHighToLow(Op, dl, DAG); - if (X86::isMOVSHDUPMask(SVOp) || - X86::isMOVSLDUPMask(SVOp) || + if (X86::isMOVSHDUPMask(SVOp) && HasSSE3 && V2IsUndef && NumElems == 4) + return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG); + + if (X86::isMOVSLDUPMask(SVOp) || X86::isMOVHLPSMask(SVOp) || X86::isMOVLPMask(SVOp)) return Op; Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=112657&r1=112656&r2=112657&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Aug 31 17:22:11 2010 @@ -5847,12 +5847,12 @@ // Shuffle with MOVSHDUP def : Pat<(v4i32 (X86Movshdup VR128:$src)), (MOVSHDUPrr VR128:$src)>; -def : Pat<(v4i32 (X86MovshdupLd addr:$src)), +def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))), (MOVSHDUPrm addr:$src)>; def : Pat<(v4f32 (X86Movshdup VR128:$src)), (MOVSHDUPrr VR128:$src)>; -def : Pat<(v4f32 (X86MovshdupLd addr:$src)), +def : Pat<(X86Movshdup (memopv4f32 addr:$src)), (MOVSHDUPrm addr:$src)>; // Shuffle with MOVSLDUP From tonic at nondot.org Tue Aug 31 17:22:13 2010 From: tonic at nondot.org (Tanya Lattner) Date: Tue, 31 Aug 2010 22:22:13 -0000 Subject: [llvm-commits] [www] r112658 - in /www/trunk: devmtg/index.html header.incl index.html Message-ID: <20100831222214.16D332A6C12D@llvm.org> Author: tbrethou Date: Tue Aug 31 17:22:13 2010 New Revision: 112658 URL: http://llvm.org/viewvc/llvm-project?rev=112658&view=rev Log: Add dev meeting information. Modified: www/trunk/devmtg/index.html www/trunk/header.incl www/trunk/index.html Modified: www/trunk/devmtg/index.html URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/index.html?rev=112658&r1=112657&r2=112658&view=diff ============================================================================== --- www/trunk/devmtg/index.html (original) +++ www/trunk/devmtg/index.html Tue Aug 31 17:22:13 2010 @@ -2,6 +2,8 @@

    LLVM Developers' Meeting
    +

    The upcoming developer's meeting is on November 4, 2010.

    +

    We have had these meetings so far:

      Modified: www/trunk/header.incl URL: http://llvm.org/viewvc/llvm-project/www/trunk/header.incl?rev=112658&r1=112657&r2=112658&view=diff ============================================================================== --- www/trunk/header.incl (original) +++ www/trunk/header.incl Tue Aug 31 17:22:13 2010 @@ -117,6 +117,7 @@ Developer Mtgs
      + Nov 4, 2010
      Oct 2, 2009
      Aug 23, 2008
      Aug 1, 2008
      Modified: www/trunk/index.html URL: http://llvm.org/viewvc/llvm-project/www/trunk/index.html?rev=112658&r1=112657&r2=112658&view=diff ============================================================================== --- www/trunk/index.html (original) +++ www/trunk/index.html Tue Aug 31 17:22:13 2010 @@ -148,7 +148,7 @@
      Upcoming Meeting
      -

      Sometime 2010.

      +

      November 4, 2010


      From dpatel at apple.com Tue Aug 31 17:22:42 2010 From: dpatel at apple.com (Devang Patel) Date: Tue, 31 Aug 2010 22:22:42 -0000 Subject: [llvm-commits] [llvm] r112659 - in /llvm/trunk: include/llvm/CodeGen/FunctionLoweringInfo.h lib/CodeGen/AsmPrinter/DwarfDebug.cpp lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp test/FrontendC++/2010-08-31-ByValArg.cpp Message-ID: <20100831222242.AB2A22A6C12C@llvm.org> Author: dpatel Date: Tue Aug 31 17:22:42 2010 New Revision: 112659 URL: http://llvm.org/viewvc/llvm-project?rev=112659&view=rev Log: Reapply r112623. Included additional check for unused byval argument. Added: llvm/trunk/test/FrontendC++/2010-08-31-ByValArg.cpp Modified: llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Modified: llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h?rev=112659&r1=112658&r2=112659&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h (original) +++ llvm/trunk/include/llvm/CodeGen/FunctionLoweringInfo.h Tue Aug 31 17:22:42 2010 @@ -77,6 +77,9 @@ /// anywhere in the function. DenseMap StaticAllocaMap; + /// ByValArgFrameIndexMap - Keep track of frame indices for byval arguments. + DenseMap ByValArgFrameIndexMap; + /// ArgDbgValues - A list of DBG_VALUE instructions created during isel for /// function arguments that are inserted after scheduling is completed. SmallVector ArgDbgValues; @@ -138,6 +141,13 @@ assert(R == 0 && "Already initialized this value register!"); return R = CreateRegs(V->getType()); } + + /// setByValArgumentFrameIndex - Record frame index for the byval + /// argument. + void setByValArgumentFrameIndex(const Argument *A, int FI); + + /// getByValArgumentFrameIndex - Get frame index for the byval argument. + int getByValArgumentFrameIndex(const Argument *A); }; /// AddCatchInfo - Extract the personality and type infos from an eh.selector Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=112659&r1=112658&r2=112659&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Tue Aug 31 17:22:42 2010 @@ -1629,9 +1629,16 @@ bool updated = false; // FIXME : Handle getNumOperands != 3 if (DVInsn->getNumOperands() == 3) { - if (DVInsn->getOperand(0).isReg()) - updated = - addRegisterAddress(VariableDie, DVLabel, DVInsn->getOperand(0)); + if (DVInsn->getOperand(0).isReg()) { + const MachineOperand RegOp = DVInsn->getOperand(0); + const TargetRegisterInfo *TRI = Asm->TM.getRegisterInfo(); + if (DVInsn->getOperand(1).isImm() && + TRI->getFrameRegister(*Asm->MF) == RegOp.getReg()) { + addVariableAddress(DV, VariableDie, DVInsn->getOperand(1).getImm()); + updated = true; + } else + updated = addRegisterAddress(VariableDie, DVLabel, RegOp); + } else if (DVInsn->getOperand(0).isImm()) updated = addConstantValue(VariableDie, DVLabel, DVInsn->getOperand(0)); else if (DVInsn->getOperand(0).isFPImm()) Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp?rev=112659&r1=112658&r2=112659&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp Tue Aug 31 17:22:42 2010 @@ -221,6 +221,7 @@ #endif LiveOutRegInfo.clear(); ArgDbgValues.clear(); + ByValArgFrameIndexMap.clear(); RegFixups.clear(); } @@ -254,6 +255,28 @@ return FirstReg; } +/// setByValArgumentFrameIndex - Record frame index for the byval +/// argument. This overrides previous frame index entry for this argument, +/// if any. +void FunctionLoweringInfo::setByValArgumentFrameIndex(const Argument *A, + int FI) { + assert (A->hasByValAttr() && "Argument does not have byval attribute!"); + ByValArgFrameIndexMap[A] = FI; +} + +/// getByValArgumentFrameIndex - Get frame index for the byval argument. +/// If the argument does not have any assigned frame index then 0 is +/// returned. +int FunctionLoweringInfo::getByValArgumentFrameIndex(const Argument *A) { + assert (A->hasByValAttr() && "Argument does not have byval attribute!"); + DenseMap::iterator I = + ByValArgFrameIndexMap.find(A); + if (I != ByValArgFrameIndexMap.end()) + return I->second; + DEBUG(dbgs() << "Argument does not have assigned frame index!"); + return 0; +} + /// AddCatchInfo - Extract the personality and type infos from an eh.selector /// call, and add them to the specified machine basic block. void llvm::AddCatchInfo(const CallInst &I, MachineModuleInfo *MMI, Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=112659&r1=112658&r2=112659&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Tue Aug 31 17:22:42 2010 @@ -3917,7 +3917,8 @@ SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, int64_t Offset, const SDValue &N) { - if (!isa(V)) + const Argument *Arg = dyn_cast(V); + if (!Arg) return false; MachineFunction &MF = DAG.getMachineFunction(); @@ -3931,6 +3932,14 @@ return false; unsigned Reg = 0; + if (Arg->hasByValAttr()) { + // Byval arguments' frame index is recorded during argument lowering. + // Use this info directly. + const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); + Reg = TRI->getFrameRegister(MF); + Offset = FuncInfo.getByValArgumentFrameIndex(Arg); + } + if (N.getNode() && N.getOpcode() == ISD::CopyFromReg) { Reg = cast(N.getOperand(1))->getReg(); if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) { @@ -4075,6 +4084,9 @@ // debug info exists. ++SDNodeOrder; SDValue &N = NodeMap[Address]; + if (!N.getNode() && isa(Address)) + // Check unused arguments map. + N = UnusedArgNodeMap[Address]; SDDbgValue *SDV; if (N.getNode()) { if (isParameter && !AI) { @@ -6131,6 +6143,12 @@ i += NumParts; } + // Note down frame index for byval arguments. + if (I->hasByValAttr() && !ArgValues.empty()) + if (FrameIndexSDNode *FI = + dyn_cast(ArgValues[0].getNode())) + FuncInfo->setByValArgumentFrameIndex(I, FI->getIndex()); + if (!I->use_empty()) { SDValue Res; if (!ArgValues.empty()) Added: llvm/trunk/test/FrontendC++/2010-08-31-ByValArg.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/2010-08-31-ByValArg.cpp?rev=112659&view=auto ============================================================================== --- llvm/trunk/test/FrontendC++/2010-08-31-ByValArg.cpp (added) +++ llvm/trunk/test/FrontendC++/2010-08-31-ByValArg.cpp Tue Aug 31 17:22:42 2010 @@ -0,0 +1,53 @@ +// This regression test checks byval arguments' debug info. +// Radar 8367011 +// RUN: %llvmgcc -S -O0 -g %s -o - | \ +// RUN: llc --disable-fp-elim -o %t.s -O0 -relocation-model=pic +// RUN: %compile_c %t.s -o %t.o +// RUN: %link %t.o -o %t.exe +// RUN: echo {break get\nrun\np missing_arg.b} > %t.in +// RUN: gdb -q -batch -n -x %t.in %t.exe | tee %t.out | \ +// RUN: grep {1 = 4242} + +// XTARGET: x86_64-apple-darwin + +class EVT { +public: + int a; + int b; + int c; +}; + +class VAL { +public: + int x; + int y; +}; +void foo(EVT e); +EVT bar(); + +void get(int *i, unsigned dl, VAL v, VAL *p, unsigned n, EVT missing_arg) { +//CHECK: .ascii "missing_arg" + EVT e = bar(); + if (dl == n) + foo(missing_arg); +} + + +EVT bar() { + EVT e; + return e; +} + +void foo(EVT e) {} + +int main(){ + VAL v; + EVT ma; + ma.a = 1; + ma.b = 4242; + ma.c = 3; + int i = 42; + get (&i, 1, v, &v, 2, ma); + return 0; +} + From bruno.cardoso at gmail.com Tue Aug 31 17:35:05 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 31 Aug 2010 22:35:05 -0000 Subject: [llvm-commits] [llvm] r112661 - in /llvm/trunk/lib/Target/X86: X86ISelLowering.cpp X86InstrFragmentsSIMD.td X86InstrSSE.td Message-ID: <20100831223505.D5B762A6C12C@llvm.org> Author: bruno Date: Tue Aug 31 17:35:05 2010 New Revision: 112661 URL: http://llvm.org/viewvc/llvm-project?rev=112661&view=rev Log: Use x86 specific MOVSLDUP node, add more patterns to match it and remove useless load nodes Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=112661&r1=112660&r2=112661&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Aug 31 17:35:05 2010 @@ -2587,6 +2587,7 @@ case X86ISD::MOVLHPS: case X86ISD::MOVHLPS: case X86ISD::MOVSHDUP: + case X86ISD::MOVSLDUP: case X86ISD::MOVSS: case X86ISD::MOVSD: case X86ISD::PUNPCKLDQ: @@ -2600,6 +2601,7 @@ switch(Opc) { default: llvm_unreachable("Unknown x86 shuffle node"); case X86ISD::MOVSHDUP: + case X86ISD::MOVSLDUP: return DAG.getNode(Opc, dl, VT, V1); } @@ -5168,9 +5170,10 @@ if (X86::isMOVSHDUPMask(SVOp) && HasSSE3 && V2IsUndef && NumElems == 4) return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG); - if (X86::isMOVSLDUPMask(SVOp) || - X86::isMOVHLPSMask(SVOp) || - X86::isMOVLPMask(SVOp)) + if (X86::isMOVSLDUPMask(SVOp) && HasSSE3 && V2IsUndef && NumElems == 4) + return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG); + + if (X86::isMOVLPMask(SVOp)) return Op; } Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=112661&r1=112660&r2=112661&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Tue Aug 31 17:35:05 2010 @@ -134,7 +134,6 @@ def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisInt<3>]>; -def SDTShuff1OpLd : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisPtrTy<1>]>; def SDTShuff2OpLd : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, SDTCisPtrTy<2>]>; @@ -157,11 +156,6 @@ def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>; def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>; -def X86MovshdupLd : SDNode<"X86ISD::MOVSHDUP_LD", SDTShuff1OpLd, - [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; -def X86MovsldupLd : SDNode<"X86ISD::MOVSLDUP_LD", SDTShuff1OpLd, - [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; - def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>; def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>; Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=112661&r1=112660&r2=112661&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Aug 31 17:35:05 2010 @@ -5847,7 +5847,7 @@ // Shuffle with MOVSHDUP def : Pat<(v4i32 (X86Movshdup VR128:$src)), (MOVSHDUPrr VR128:$src)>; -def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))), +def : Pat<(X86Movshdup (bc_v4i32 (memopv2i64 addr:$src))), (MOVSHDUPrm addr:$src)>; def : Pat<(v4f32 (X86Movshdup VR128:$src)), @@ -5858,12 +5858,12 @@ // Shuffle with MOVSLDUP def : Pat<(v4i32 (X86Movsldup VR128:$src)), (MOVSLDUPrr VR128:$src)>; -def : Pat<(v4i32 (X86MovsldupLd addr:$src)), +def : Pat<(X86Movsldup (bc_v4i32 (memopv2i64 addr:$src))), (MOVSLDUPrm addr:$src)>; def : Pat<(v4f32 (X86Movsldup VR128:$src)), (MOVSLDUPrr VR128:$src)>; -def : Pat<(v4f32 (X86MovsldupLd addr:$src)), +def : Pat<(X86Movsldup (memopv4f32 addr:$src)), (MOVSLDUPrm addr:$src)>; // Shuffle with PSHUFHW From asl at math.spbu.ru Tue Aug 31 17:38:01 2010 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Tue, 31 Aug 2010 22:38:01 -0000 Subject: [llvm-commits] [llvm] r112662 - /llvm/trunk/lib/System/Unix/Path.inc Message-ID: <20100831223801.216A22A6C12C@llvm.org> Author: asl Date: Tue Aug 31 17:38:00 2010 New Revision: 112662 URL: http://llvm.org/viewvc/llvm-project?rev=112662&view=rev Log: Some fixes for NetBSD Modified: llvm/trunk/lib/System/Unix/Path.inc Modified: llvm/trunk/lib/System/Unix/Path.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Unix/Path.inc?rev=112662&r1=112661&r2=112662&view=diff ============================================================================== --- llvm/trunk/lib/System/Unix/Path.inc (original) +++ llvm/trunk/lib/System/Unix/Path.inc Tue Aug 31 17:38:00 2010 @@ -282,7 +282,7 @@ return Path(pathname); } -#ifdef __FreeBSD__ +#if defined(__FreeBSD__) || defined (__NetBSD__) static int test_dir(char buf[PATH_MAX], char ret[PATH_MAX], const char *dir, const char *bin) @@ -334,7 +334,7 @@ free(pv); return (NULL); } -#endif // __FreeBSD__ +#endif // __FreeBSD__ || __NetBSD__ /// GetMainExecutable - Return the path to the main executable, given the /// value of argv[0] from program startup. @@ -350,7 +350,7 @@ if (realpath(exe_path, link_path)) return Path(std::string(link_path)); } -#elif defined(__FreeBSD__) +#elif defined(__FreeBSD__) || defined (__NetBSD__) char exe_path[PATH_MAX]; if (getprogpath(exe_path, argv0) != NULL) From echristo at apple.com Tue Aug 31 17:39:04 2010 From: echristo at apple.com (Eric Christopher) Date: Tue, 31 Aug 2010 15:39:04 -0700 Subject: [llvm-commits] [llvm] r112661 - in /llvm/trunk/lib/Target/X86: X86ISelLowering.cpp X86InstrFragmentsSIMD.td X86InstrSSE.td In-Reply-To: <20100831223505.D5B762A6C12C@llvm.org> References: <20100831223505.D5B762A6C12C@llvm.org> Message-ID: On Aug 31, 2010, at 3:35 PM, Bruno Cardoso Lopes wrote: > Author: bruno > Date: Tue Aug 31 17:35:05 2010 > New Revision: 112661 > > URL: http://llvm.org/viewvc/llvm-project?rev=112661&view=rev > Log: > Use x86 specific MOVSLDUP node, add more patterns to match it and remove useless load nodes Testcases for this last pile of commits? -eric From isanbard at gmail.com Tue Aug 31 17:41:22 2010 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 31 Aug 2010 22:41:22 -0000 Subject: [llvm-commits] [llvm] r112664 - in /llvm/trunk: lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td test/CodeGen/ARM/mvncc.ll test/CodeGen/Thumb2/thumb2-mvncc.ll Message-ID: <20100831224122.6BA6E2A6C12E@llvm.org> Author: void Date: Tue Aug 31 17:41:22 2010 New Revision: 112664 URL: http://llvm.org/viewvc/llvm-project?rev=112664&view=rev Log: We have a chance for an optimization. Consider this code: int x(int t) { if (t & 256) return -26; return 0; } We generate this: tst.w r0, #256 mvn r0, #25 it eq moveq r0, #0 while gcc generates this: ands r0, r0, #256 it ne mvnne r0, #25 bx lr Scandalous really! During ISel time, we can look for this particular pattern. One where we have a "MOVCC" that uses the flag off of a CMPZ that itself is comparing an AND instruction to 0. Something like this (greatly simplified): %r0 = ISD::AND ... ARMISD::CMPZ %r0, 0 @ sets [CPSR] %r0 = ARMISD::MOVCC 0, -26 @ reads [CPSR] All we have to do is convert the "ISD::AND" into an "ARM::ANDS" that sets [CPSR] when it's zero. The zero value will all ready be in the %r0 register and we only need to change it if the AND wasn't zero. Easy! Added: llvm/trunk/test/CodeGen/ARM/mvncc.ll llvm/trunk/test/CodeGen/Thumb2/thumb2-mvncc.ll Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=112664&r1=112663&r2=112664&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Tue Aug 31 17:41:22 2010 @@ -180,6 +180,9 @@ SDNode *SelectARMCMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag); + SDNode *OptimizeCMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, + ARMCC::CondCodes CCVal, SDValue CCR, + SDValue InFlag, bool IsThumb2); SDNode *SelectConcatVector(SDNode *N); @@ -1641,6 +1644,92 @@ return 0; } +/// OptimizeCMOVSoImmOp - It's possible to save an instruction or two be +/// recognizing that the TST and AND instructions perform the same function +/// (they "and" the two values). See inside for more details. +SDNode *ARMDAGToDAGISel:: +OptimizeCMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, + ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag, + bool IsThumb2) { + // Convert: + // + // tst.w r0, #256 + // mvn r0, #25 + // it eq + // moveq r0, #0 + // + // into: + // + // ands.w r0, r0, #256 + // it ne + // mvnne.w r0, #25 + // + if (InFlag.getOpcode() != ARMISD::CMPZ || + InFlag.getOperand(0).getOpcode() != ISD::AND) + return 0; + + // The true value needs to be zero, as that's the result of the AND + // instruction. + ConstantSDNode *True = dyn_cast(TrueVal); + if (!True || True->getZExtValue() != 0) + return 0; + + // Bail if the false value isn't an immediate. + ConstantSDNode *False = dyn_cast(FalseVal); + if (!False) + return 0; + + bool UseMVN = false; + if ((IsThumb2 && !Pred_t2_so_imm(FalseVal.getNode())) || + (!IsThumb2 && !Pred_so_imm(FalseVal.getNode()))) { + // The false value isn't a proper immediate. Check to see if we can use the + // bitwise NOT version. + if ((IsThumb2 && ARM_AM::getT2SOImmVal(~False->getZExtValue()) != -1) || + (!IsThumb2 && ARM_AM::getSOImmVal(~False->getZExtValue()) != -1)) { + UseMVN = true; + FalseVal = CurDAG->getTargetConstant(~False->getZExtValue(), MVT::i32); + } else { + return 0; + } + } else { + FalseVal = CurDAG->getTargetConstant(False->getZExtValue(), MVT::i32); + } + + // A comparison against zero corresponds with the flag AND sets if the result + // is zero. + ConstantSDNode *CmpVal = dyn_cast(InFlag.getOperand(1)); + if (!CmpVal || CmpVal->getZExtValue() != 0) + return 0; + + ARMCC::CondCodes NegCC = ARMCC::getOppositeCondition(CCVal); + SDValue OrigAnd = InFlag.getOperand(0); + SDValue NewAnd = + CurDAG->getNode(ARMISD::AND, N->getDebugLoc(), + CurDAG->getVTList(OrigAnd.getValueType(), MVT::Flag), + OrigAnd->getOperand(0), OrigAnd->getOperand(1)); + + unsigned Opcode = !UseMVN ? + (IsThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi) : + (IsThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi); + + SDValue Ops[] = { + NewAnd.getValue(0), + FalseVal, + CurDAG->getTargetConstant(NegCC, MVT::i32), + CCR, NewAnd.getValue(1) + }; + SDNode *ResNode = CurDAG->SelectNodeTo(N, Opcode, MVT::i32, Ops, 5); + + // Manually run "Select" on the newly created "ARMISD::AND" node to make + // sure that it's converted properly. + SDNode *AndNode = Select(NewAnd.getNode()); + if (AndNode && NewAnd.getNode() != AndNode && + NewAnd.getNode()->getOpcode() != ISD::DELETED_NODE) + ReplaceUses(NewAnd.getNode(), AndNode); + + return ResNode; +} + SDNode *ARMDAGToDAGISel:: SelectT2CMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) { @@ -1649,6 +1738,10 @@ return 0; if (Pred_t2_so_imm(TrueVal.getNode())) { + SDNode *ResNode = OptimizeCMOVSoImmOp(N, FalseVal, TrueVal, CCVal, CCR, + InFlag, true); + if (ResNode) return ResNode; + SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32); SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32); SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag }; @@ -1666,6 +1759,10 @@ return 0; if (Pred_so_imm(TrueVal.getNode())) { + SDNode *ResNode = OptimizeCMOVSoImmOp(N, FalseVal, TrueVal, CCVal, CCR, + InFlag, false); + if (ResNode) return ResNode; + SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32); SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32); SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag }; Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=112664&r1=112663&r2=112664&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Aug 31 17:41:22 2010 @@ -2419,6 +2419,14 @@ RegConstraint<"$false = $dst">, UnaryDP { let Inst{25} = 1; } + +def MVNCCi : AI1<0b1111, (outs GPR:$dst), + (ins GPR:$false, so_imm:$true), DPFrm, IIC_iCMOVi, + "mvn", "\t$dst, $true", + [/*(set GPR:$dst, (ARMcmov GPR:$false,so_imm_not:$true,imm:$cc,CCR:$ccr))*/]>, + RegConstraint<"$false = $dst">, UnaryDP { + let Inst{25} = 0; +} } // neverHasSideEffects //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=112664&r1=112663&r2=112664&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Aug 31 17:41:22 2010 @@ -2195,6 +2195,18 @@ let Inst{15} = 0; } +def t2MVNCCi : T2I<(outs rGPR:$dst), (ins rGPR:$false, t2_so_imm:$true), + IIC_iCMOVi, "mvn", ".w\t$dst, $true", +[/*(set rGPR:$dst,(ARMcmov rGPR:$false,t2_so_imm_not:$true,imm:$cc,CCR:$ccr))*/]>, + RegConstraint<"$false = $dst"> { + let Inst{31-27} = 0b11110; + let Inst{25} = 0; + let Inst{24-21} = 0b0011; + let Inst{20} = 0; // The S bit. + let Inst{19-16} = 0b1111; // Rn + let Inst{15} = 0; +} + class T2I_movcc_sh opcod, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : T2I { Added: llvm/trunk/test/CodeGen/ARM/mvncc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/mvncc.ll?rev=112664&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/mvncc.ll (added) +++ llvm/trunk/test/CodeGen/ARM/mvncc.ll Tue Aug 31 17:41:22 2010 @@ -0,0 +1,12 @@ +; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s + +define i32 @f1(i32 %t) nounwind { +; CHECK: f1 +; CHECK-NOT: tst +; CHECK: and +; CHECK: mvnne + %and = and i32 %t, 256 + %tobool = icmp eq i32 %and, 0 + %retval.0 = select i1 %tobool, i32 0, i32 -26 + ret i32 %retval.0 +} Added: llvm/trunk/test/CodeGen/Thumb2/thumb2-mvncc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-mvncc.ll?rev=112664&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-mvncc.ll (added) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-mvncc.ll Tue Aug 31 17:41:22 2010 @@ -0,0 +1,13 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s + +define i32 @f1(i32 %t) nounwind { +; CHECK: f1 +; CHECK-NOT: tst +; CHECK: ands +; CHECK: it ne +; CHECK: mvnne + %and = and i32 %t, 256 + %tobool = icmp eq i32 %and, 0 + %retval.0 = select i1 %tobool, i32 0, i32 -26 + ret i32 %retval.0 +} From bruno.cardoso at gmail.com Tue Aug 31 17:42:42 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 31 Aug 2010 15:42:42 -0700 Subject: [llvm-commits] [llvm] r112661 - in /llvm/trunk/lib/Target/X86: X86ISelLowering.cpp X86InstrFragmentsSIMD.td X86InstrSSE.td In-Reply-To: References: <20100831223505.D5B762A6C12C@llvm.org> Message-ID: This is a rewrite of matching masks that the x86 shuffle tests already test! On Tue, Aug 31, 2010 at 3:39 PM, Eric Christopher wrote: > > On Aug 31, 2010, at 3:35 PM, Bruno Cardoso Lopes wrote: > >> Author: bruno >> Date: Tue Aug 31 17:35:05 2010 >> New Revision: 112661 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=112661&view=rev >> Log: >> Use x86 specific MOVSLDUP node, add more patterns to match it and remove useless load nodes > > Testcases for this last pile of commits? > > -eric -- Bruno Cardoso Lopes http://www.brunocardoso.cc From echristo at apple.com Tue Aug 31 17:43:50 2010 From: echristo at apple.com (Eric Christopher) Date: Tue, 31 Aug 2010 15:43:50 -0700 Subject: [llvm-commits] [llvm] r112661 - in /llvm/trunk/lib/Target/X86: X86ISelLowering.cpp X86InstrFragmentsSIMD.td X86InstrSSE.td In-Reply-To: References: <20100831223505.D5B762A6C12C@llvm.org> Message-ID: On Aug 31, 2010, at 3:42 PM, Bruno Cardoso Lopes wrote: > This is a rewrite of matching masks that the x86 shuffle tests already test! OK :) -eric From echristo at apple.com Tue Aug 31 17:49:25 2010 From: echristo at apple.com (Eric Christopher) Date: Tue, 31 Aug 2010 15:49:25 -0700 Subject: [llvm-commits] [llvm] r112664 - in /llvm/trunk: lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td test/CodeGen/ARM/mvncc.ll test/CodeGen/Thumb2/thumb2-mvncc.ll In-Reply-To: <20100831224122.6BA6E2A6C12E@llvm.org> References: <20100831224122.6BA6E2A6C12E@llvm.org> Message-ID: <2F3F6800-6F8E-4EB7-B055-C29C8F89DFFD@apple.com> You can merge these two tests together and use a check prefix. -eric On Aug 31, 2010, at 3:41 PM, Bill Wendling wrote: > Added: llvm/trunk/test/CodeGen/ARM/mvncc.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/mvncc.ll?rev=112664&view=auto > ============================================================================== > --- llvm/trunk/test/CodeGen/ARM/mvncc.ll (added) > +++ llvm/trunk/test/CodeGen/ARM/mvncc.ll Tue Aug 31 17:41:22 2010 > @@ -0,0 +1,12 @@ > +; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s > + > +define i32 @f1(i32 %t) nounwind { > +; CHECK: f1 > +; CHECK-NOT: tst > +; CHECK: and > +; CHECK: mvnne > + %and = and i32 %t, 256 > + %tobool = icmp eq i32 %and, 0 > + %retval.0 = select i1 %tobool, i32 0, i32 -26 > + ret i32 %retval.0 > +} > > Added: llvm/trunk/test/CodeGen/Thumb2/thumb2-mvncc.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-mvncc.ll?rev=112664&view=auto > ============================================================================== > --- llvm/trunk/test/CodeGen/Thumb2/thumb2-mvncc.ll (added) > +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-mvncc.ll Tue Aug 31 17:41:22 2010 > @@ -0,0 +1,13 @@ > +; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s > + > +define i32 @f1(i32 %t) nounwind { > +; CHECK: f1 > +; CHECK-NOT: tst > +; CHECK: ands > +; CHECK: it ne > +; CHECK: mvnne > + %and = and i32 %t, 256 > + %tobool = icmp eq i32 %and, 0 > + %retval.0 = select i1 %tobool, i32 0, i32 -26 > + ret i32 %retval.0 > +} From gohman at apple.com Tue Aug 31 17:50:31 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 31 Aug 2010 22:50:31 -0000 Subject: [llvm-commits] [llvm] r112665 - /llvm/trunk/lib/Analysis/ScalarEvolution.cpp Message-ID: <20100831225031.B1B932A6C12E@llvm.org> Author: djg Date: Tue Aug 31 17:50:31 2010 New Revision: 112665 URL: http://llvm.org/viewvc/llvm-project?rev=112665&view=rev Log: Revert r110916. This patch is buggy because the code inside the inner loop doesn't update all the variables in the outer loop. Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=112665&r1=112664&r2=112665&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Tue Aug 31 17:50:31 2010 @@ -1589,7 +1589,6 @@ } // Check this multiply against other multiplies being added together. - bool AnyFold = false; for (unsigned OtherMulIdx = Idx+1; OtherMulIdx < Ops.size() && isa(Ops[OtherMulIdx]); ++OtherMulIdx) { @@ -1617,14 +1616,12 @@ const SCEV *InnerMulSum = getAddExpr(InnerMul1,InnerMul2); const SCEV *OuterMul = getMulExpr(MulOpSCEV, InnerMulSum); if (Ops.size() == 2) return OuterMul; - Ops[Idx] = OuterMul; - Ops.erase(Ops.begin()+OtherMulIdx); - OtherMulIdx = Idx; - AnyFold = true; + Ops.erase(Ops.begin()+Idx); + Ops.erase(Ops.begin()+OtherMulIdx-1); + Ops.push_back(OuterMul); + return getAddExpr(Ops); } } - if (AnyFold) - return getAddExpr(Ops); } } From gohman at apple.com Tue Aug 31 17:52:13 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 31 Aug 2010 22:52:13 -0000 Subject: [llvm-commits] [llvm] r112666 - /llvm/trunk/lib/Analysis/ScalarEvolution.cpp Message-ID: <20100831225213.2A3F12A6C12E@llvm.org> Author: djg Date: Tue Aug 31 17:52:12 2010 New Revision: 112666 URL: http://llvm.org/viewvc/llvm-project?rev=112666&view=rev Log: Reapply r112433, now that the real problem is addressed. Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=112666&r1=112665&r2=112666&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Tue Aug 31 17:52:12 2010 @@ -1883,27 +1883,30 @@ // there are multiple AddRec's with the same loop induction variable being // multiplied together. If so, we can fold them. for (unsigned OtherIdx = Idx+1; - OtherIdx < Ops.size() && isa(Ops[OtherIdx]);++OtherIdx) - if (OtherIdx != Idx) { - const SCEVAddRecExpr *OtherAddRec = cast(Ops[OtherIdx]); - if (AddRecLoop == OtherAddRec->getLoop()) { - // F * G --> {A,+,B} * {C,+,D} --> {A*C,+,F*D + G*B + B*D} - const SCEVAddRecExpr *F = AddRec, *G = OtherAddRec; - const SCEV *NewStart = getMulExpr(F->getStart(), G->getStart()); - const SCEV *B = F->getStepRecurrence(*this); - const SCEV *D = G->getStepRecurrence(*this); - const SCEV *NewStep = getAddExpr(getMulExpr(F, D), - getMulExpr(G, B), - getMulExpr(B, D)); - const SCEV *NewAddRec = getAddRecExpr(NewStart, NewStep, - F->getLoop()); - if (Ops.size() == 2) return NewAddRec; - - Ops.erase(Ops.begin()+Idx); - Ops.erase(Ops.begin()+OtherIdx-1); - Ops.push_back(NewAddRec); - return getMulExpr(Ops); - } + OtherIdx < Ops.size() && isa(Ops[OtherIdx]); + ++OtherIdx) + if (AddRecLoop == cast(Ops[OtherIdx])->getLoop()) { + // F * G, where F = {A,+,B} and G = {C,+,D} --> + // {A*C,+,F*D + G*B + B*D} + for (; OtherIdx != Ops.size() && isa(Ops[OtherIdx]); + ++OtherIdx) + if (const SCEVAddRecExpr *OtherAddRec = + dyn_cast(Ops[OtherIdx])) + if (OtherAddRec->getLoop() == AddRecLoop) { + const SCEVAddRecExpr *F = AddRec, *G = OtherAddRec; + const SCEV *NewStart = getMulExpr(F->getStart(), G->getStart()); + const SCEV *B = F->getStepRecurrence(*this); + const SCEV *D = G->getStepRecurrence(*this); + const SCEV *NewStep = getAddExpr(getMulExpr(F, D), + getMulExpr(G, B), + getMulExpr(B, D)); + const SCEV *NewAddRec = getAddRecExpr(NewStart, NewStep, + F->getLoop()); + if (Ops.size() == 2) return NewAddRec; + Ops[Idx] = AddRec = cast(NewAddRec); + Ops.erase(Ops.begin() + OtherIdx); --OtherIdx; + } + return getMulExpr(Ops); } // Otherwise couldn't fold anything into this recurrence. Move onto the From gohman at apple.com Tue Aug 31 17:53:17 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 31 Aug 2010 22:53:17 -0000 Subject: [llvm-commits] [llvm] r112667 - /llvm/trunk/lib/Analysis/ScalarEvolution.cpp Message-ID: <20100831225317.A39B02A6C12E@llvm.org> Author: djg Date: Tue Aug 31 17:53:17 2010 New Revision: 112667 URL: http://llvm.org/viewvc/llvm-project?rev=112667&view=rev Log: Reapply r112432, now that the real problem is addressed. Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=112667&r1=112666&r2=112667&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Tue Aug 31 17:53:17 2010 @@ -3332,11 +3332,16 @@ // LLVM IR canonical form means we need only traverse the left operands. SmallVector AddOps; AddOps.push_back(getSCEV(U->getOperand(1))); - for (Value *Op = U->getOperand(0); - Op->getValueID() == Instruction::Add + Value::InstructionVal; - Op = U->getOperand(0)) { + for (Value *Op = U->getOperand(0); ; Op = U->getOperand(0)) { + unsigned Opcode = Op->getValueID() - Value::InstructionVal; + if (Opcode != Instruction::Add && Opcode != Instruction::Sub) + break; U = cast(Op); - AddOps.push_back(getSCEV(U->getOperand(1))); + const SCEV *Op1 = getSCEV(U->getOperand(1)); + if (Opcode == Instruction::Sub) + AddOps.push_back(getNegativeSCEV(Op1)); + else + AddOps.push_back(Op1); } AddOps.push_back(getSCEV(U->getOperand(0))); return getAddExpr(AddOps); From enderby at apple.com Tue Aug 31 17:55:11 2010 From: enderby at apple.com (Kevin Enderby) Date: Tue, 31 Aug 2010 22:55:11 -0000 Subject: [llvm-commits] [llvm] r112668 - in /llvm/trunk: include/llvm/MC/MCContext.h include/llvm/MC/MCDwarf.h lib/MC/MCContext.cpp lib/MC/MCMachOStreamer.cpp Message-ID: <20100831225511.40A2E2A6C12E@llvm.org> Author: enderby Date: Tue Aug 31 17:55:11 2010 New Revision: 112668 URL: http://llvm.org/viewvc/llvm-project?rev=112668&view=rev Log: This is the second of three patches to implement support for the .loc directive and output the dwarf line number tables. This takes the current loc info after an instruction is assembled and saves the needed info into an object that has vector and for each section. These objects will be used for the final patch to build and emit the encoded dwarf line number tables. Again for now this is only in the Mach-O streamer but at some point will move to a more generic place. Modified: llvm/trunk/include/llvm/MC/MCContext.h llvm/trunk/include/llvm/MC/MCDwarf.h llvm/trunk/lib/MC/MCContext.cpp llvm/trunk/lib/MC/MCMachOStreamer.cpp Modified: llvm/trunk/include/llvm/MC/MCContext.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCContext.h?rev=112668&r1=112667&r2=112668&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCContext.h (original) +++ llvm/trunk/include/llvm/MC/MCContext.h Tue Aug 31 17:55:11 2010 @@ -26,6 +26,7 @@ class MCLabel; class MCDwarfFile; class MCDwarfLoc; + class MCLineSection; class StringRef; class Twine; class MCSectionMachO; @@ -75,6 +76,10 @@ MCDwarfLoc CurrentDwarfLoc; bool DwarfLocSeen; + /// The dwarf line information from the .loc directives for the sections + /// with assembled machine instructions have after seeing .loc directives. + DenseMap MCLineSections; + /// Allocator - Allocator object used for creating machine code objects. /// /// We use a bump pointer allocator to avoid the need to track all allocated @@ -163,6 +168,9 @@ const std::vector &getMCDwarfDirs() { return MCDwarfDirs; } + DenseMap &getMCLineSections() { + return MCLineSections; + } /// setCurrentDwarfLoc - saves the information from the currently parsed /// dwarf .loc directive and sets DwarfLocSeen. When the next instruction /// is assembled an entry in the line number table with this information and @@ -176,6 +184,10 @@ CurrentDwarfLoc.setIsa(Isa); DwarfLocSeen = true; } + void clearDwarfLocSeen() { DwarfLocSeen = false; } + + bool getDwarfLocSeen() { return DwarfLocSeen; } + const MCDwarfLoc &getCurrentDwarfLoc() { return CurrentDwarfLoc; } /// @} Modified: llvm/trunk/include/llvm/MC/MCDwarf.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCDwarf.h?rev=112668&r1=112667&r2=112668&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCDwarf.h (original) +++ llvm/trunk/include/llvm/MC/MCDwarf.h Tue Aug 31 17:55:11 2010 @@ -17,9 +17,12 @@ #define LLVM_MC_MCDWARF_H #include "llvm/ADT/StringRef.h" +#include namespace llvm { class MCContext; + class MCSection; + class MCSymbol; class raw_ostream; /// MCDwarfFile - Instances of this class represent the name of the dwarf @@ -57,6 +60,11 @@ void dump() const; }; + inline raw_ostream &operator<<(raw_ostream &OS, const MCDwarfFile &DwarfFile){ + DwarfFile.print(OS); + return OS; + } + /// MCDwarfLoc - Instances of this class represent the information from a /// dwarf .loc directive. class MCDwarfLoc { @@ -78,12 +86,14 @@ private: // MCContext manages these friend class MCContext; + friend class MCLineEntry; MCDwarfLoc(unsigned fileNum, unsigned line, unsigned column, unsigned flags, unsigned isa) : FileNum(fileNum), Line(line), Column(column), Flags(flags), Isa(isa) {} - MCDwarfLoc(const MCDwarfLoc&); // DO NOT IMPLEMENT - void operator=(const MCDwarfLoc&); // DO NOT IMPLEMENT + // Allow the default copy constructor and assignment operator to be used + // for an MCDwarfLoc object. + public: /// setFileNum - Set the FileNum of this MCDwarfLoc. void setFileNum(unsigned fileNum) { FileNum = fileNum; } @@ -101,10 +111,46 @@ void setIsa(unsigned isa) { Isa = isa; } }; - inline raw_ostream &operator<<(raw_ostream &OS, const MCDwarfFile &DwarfFile){ - DwarfFile.print(OS); - return OS; - } + /// MCLineEntry - Instances of this class represent the line information for + /// the dwarf line table entries. Which is created after a machine + /// instruction is assembled and uses an address from a temporary label + /// created at the current address in the current section and the info from + /// the last .loc directive seen as stored in the context. + class MCLineEntry : public MCDwarfLoc { + MCSymbol *Label; + + private: + // Allow the default copy constructor and assignment operator to be used + // for an MCLineEntry object. + + public: + // Constructor to create an MCLineEntry given a symbol and the dwarf loc. + MCLineEntry(MCSymbol *label, const MCDwarfLoc loc) : MCDwarfLoc(loc), + Label(label) {} + }; + + /// MCLineSection - Instances of this class represent the line information + /// for a section where machine instructions have been assembled after seeing + /// .loc directives. This is the information used to build the dwarf line + /// table for a section. + class MCLineSection { + std::vector MCLineEntries; + + private: + MCLineSection(const MCLineSection&); // DO NOT IMPLEMENT + void operator=(const MCLineSection&); // DO NOT IMPLEMENT + + public: + // Constructor to create an MCLineSection with an empty MCLineEntries + // vector. + MCLineSection(): MCLineEntries() {}; + + // addLineEntry - adds an entry to this MCLineSection's line entries + void addLineEntry(const MCLineEntry &LineEntry) { + MCLineEntries.push_back(LineEntry); + } + }; + } // end namespace llvm #endif Modified: llvm/trunk/lib/MC/MCContext.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCContext.cpp?rev=112668&r1=112667&r2=112668&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCContext.cpp (original) +++ llvm/trunk/lib/MC/MCContext.cpp Tue Aug 31 17:55:11 2010 @@ -227,7 +227,7 @@ Name = Slash.second; for (DirIndex = 0; DirIndex < MCDwarfDirs.size(); DirIndex++) { if (Directory == MCDwarfDirs[DirIndex]) - break; + break; } if (DirIndex >= MCDwarfDirs.size()) { char *Buf = static_cast(Allocate(Directory.size())); Modified: llvm/trunk/lib/MC/MCMachOStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCMachOStreamer.cpp?rev=112668&r1=112667&r2=112668&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCMachOStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCMachOStreamer.cpp Tue Aug 31 17:55:11 2010 @@ -33,6 +33,7 @@ void EmitInstToFragment(const MCInst &Inst); void EmitInstToData(const MCInst &Inst); // FIXME: These will likely moved to a better place. + void MakeLineEntryForSection(const MCSection *Section); const MCExpr * MakeStartMinusEndExpr(MCSymbol *Start, MCSymbol *End, int IntVal); void EmitDwarfFileTable(void); @@ -409,6 +410,10 @@ getCurrentSectionData()->setHasInstructions(true); + // Now that a machine instruction has been assembled into this section, make + // a line entry for any .loc directive that has been seen. + MakeLineEntryForSection(getCurrentSection()); + // If this instruction doesn't need relaxation, just emit it as data. if (!getAssembler().getBackend().MayNeedRelaxation(Inst)) { EmitInstToData(Inst); @@ -431,6 +436,47 @@ } // +// This is called when an instruction is assembled into the specified section +// and if there is information from the last .loc directive that has yet to have +// a line entry made for it is made. +// +void MCMachOStreamer::MakeLineEntryForSection(const MCSection *Section) { + if (!getContext().getDwarfLocSeen()) + return; + + // Create a symbol at in the current section for use in the line entry. + MCSymbol *LineSym = getContext().CreateTempSymbol(); + // Set the value of the symbol to use for the MCLineEntry. + EmitLabel(LineSym); + + // Get the current .loc info saved in the context. + const MCDwarfLoc &DwarfLoc = getContext().getCurrentDwarfLoc(); + + // Create a (local) line entry with the symbol and the current .loc info. + MCLineEntry LineEntry(LineSym, DwarfLoc); + + // clear DwarfLocSeen saying the current .loc info is now used. + getContext().clearDwarfLocSeen(); + + // Get the MCLineSection for this section, if one does not exist for this + // section create it. + DenseMap &MCLineSections = + getContext().getMCLineSections(); + MCLineSection *LineSection = MCLineSections[Section]; + if (!LineSection) { + // Create a new MCLineSection. This will be deleted after the dwarf line + // table is created using it by iterating through the MCLineSections + // DenseMap. + LineSection = new MCLineSection; + // Save a pointer to the new LineSection into the MCLineSections DenseMap. + MCLineSections[Section] = LineSection; + } + + // Add the line entry to this section's entries. + LineSection->addLineEntry(LineEntry); +} + +// // This helper routine returns an expression of End - Start + IntVal for use // by EmitDwarfFileTable() below. // @@ -552,6 +598,16 @@ // TODO: This is the point where the line tables would be emitted. + // Delete the MCLineSections that were created in + // MCMachOStreamer::MakeLineEntryForSection() and used to emit the line + // tables. + DenseMap &MCLineSections = + getContext().getMCLineSections(); + for (DenseMap::iterator it = + MCLineSections.begin(), ie = MCLineSections.end(); it != ie; ++it) { + delete it->second; + } + // If there are no line tables emited then we emit: // The following DW_LNE_set_address sequence to set the address to zero // TODO test for 32-bit or 64-bit output From sabre at nondot.org Tue Aug 31 18:00:16 2010 From: sabre at nondot.org (Chris Lattner) Date: Tue, 31 Aug 2010 23:00:16 -0000 Subject: [llvm-commits] [llvm] r112669 - in /llvm/trunk: lib/Transforms/Scalar/LICM.cpp test/Transforms/LICM/hoisting.ll test/Transforms/LICM/scalar_promote.ll Message-ID: <20100831230016.C93D82A6C12C@llvm.org> Author: lattner Date: Tue Aug 31 18:00:16 2010 New Revision: 112669 URL: http://llvm.org/viewvc/llvm-project?rev=112669&view=rev Log: licm is wasting time hoisting constant foldable operations, instead of hoisting them, just fold them away. This occurs in the testcase for PR8041, for example. Modified: llvm/trunk/lib/Transforms/Scalar/LICM.cpp llvm/trunk/test/Transforms/LICM/hoisting.ll llvm/trunk/test/Transforms/LICM/scalar_promote.ll Modified: llvm/trunk/lib/Transforms/Scalar/LICM.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LICM.cpp?rev=112669&r1=112668&r2=112669&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LICM.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LICM.cpp Tue Aug 31 18:00:16 2010 @@ -36,11 +36,11 @@ #include "llvm/DerivedTypes.h" #include "llvm/IntrinsicInst.h" #include "llvm/Instructions.h" -#include "llvm/Target/TargetData.h" -#include "llvm/Analysis/LoopInfo.h" -#include "llvm/Analysis/LoopPass.h" #include "llvm/Analysis/AliasAnalysis.h" #include "llvm/Analysis/AliasSetTracker.h" +#include "llvm/Analysis/ConstantFolding.h" +#include "llvm/Analysis/LoopInfo.h" +#include "llvm/Analysis/LoopPass.h" #include "llvm/Analysis/Dominators.h" #include "llvm/Analysis/ScalarEvolution.h" #include "llvm/Transforms/Utils/Local.h" @@ -353,6 +353,18 @@ for (BasicBlock::iterator II = BB->begin(), E = BB->end(); II != E; ) { Instruction &I = *II++; + // Try constant folding this instruction. If all the operands are + // constants, it is technically hoistable, but it would be better to just + // fold it. + if (Constant *C = ConstantFoldInstruction(&I)) { + DEBUG(dbgs() << "LICM folding inst: " << I << " --> " << *C << '\n'); + CurAST->copyValue(&I, C); + CurAST->deleteValue(&I); + I.replaceAllUsesWith(C); + I.eraseFromParent(); + continue; + } + // Try hoisting the instruction out to the preheader. We can only do this // if all of the operands of the instruction are loop invariant and if it // is safe to hoist the instruction. @@ -360,7 +372,7 @@ if (isLoopInvariantInst(I) && canSinkOrHoistInst(I) && isSafeToExecuteUnconditionally(I)) hoist(I); - } + } const std::vector &Children = N->getChildren(); for (unsigned i = 0, e = Children.size(); i != e; ++i) Modified: llvm/trunk/test/Transforms/LICM/hoisting.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LICM/hoisting.ll?rev=112669&r1=112668&r2=112669&view=diff ============================================================================== --- llvm/trunk/test/Transforms/LICM/hoisting.ll (original) +++ llvm/trunk/test/Transforms/LICM/hoisting.ll Tue Aug 31 18:00:16 2010 @@ -48,3 +48,19 @@ %C = sub i32 %A, %B ; [#uses=1] ret i32 %C } + + +; This loop invariant instruction should be constant folded, not hoisted. +define i32 @test3(i1 %c) { +; CHECK: define i32 @test3 +; CHECK: call void @foo2(i32 6) + %A = load i32* @X ; [#uses=2] + br label %Loop +Loop: + %B = add i32 4, 2 ; [#uses=2] + call void @foo2( i32 %B ) + br i1 %c, label %Loop, label %Out +Out: ; preds = %Loop + %C = sub i32 %A, %B ; [#uses=1] + ret i32 %C +} Modified: llvm/trunk/test/Transforms/LICM/scalar_promote.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LICM/scalar_promote.ll?rev=112669&r1=112668&r2=112669&view=diff ============================================================================== --- llvm/trunk/test/Transforms/LICM/scalar_promote.ll (original) +++ llvm/trunk/test/Transforms/LICM/scalar_promote.ll Tue Aug 31 18:00:16 2010 @@ -1,4 +1,6 @@ ; RUN: opt < %s -licm -S | FileCheck %s +target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128" + @X = global i32 7 ; [#uses=4] define void @test1(i32 %i) { @@ -32,23 +34,21 @@ br label %Loop ; CHECK: @test2 ; CHECK: Entry: -; CHECK-NEXT: %X1 = getelementptr i32* @X, i64 0 -; CHECK-NEXT: %X2 = getelementptr i32* @X, i64 0 -; CHECK-NEXT: %X1.promoted = load i32* %X1 +; CHECK-NEXT: %.promoted = load i32* getelementptr inbounds (i32* @X, i64 1) ; CHECK-NEXT: br label %Loop Loop: ; preds = %Loop, %0 - %X1 = getelementptr i32* @X, i64 0 ; [#uses=1] + %X1 = getelementptr i32* @X, i64 1 ; [#uses=1] %A = load i32* %X1 ; [#uses=1] %V = add i32 %A, 1 ; [#uses=1] - %X2 = getelementptr i32* @X, i64 0 ; [#uses=1] + %X2 = getelementptr i32* @X, i64 1 ; [#uses=1] store i32 %V, i32* %X2 br i1 false, label %Loop, label %Exit Exit: ; preds = %Loop ret void ; CHECK: Exit: -; CHECK-NEXT: store i32 %V, i32* %X1 +; CHECK-NEXT: store i32 %V, i32* getelementptr inbounds (i32* @X, i64 1) ; CHECK-NEXT: ret void } From benny.kra at googlemail.com Tue Aug 31 18:38:14 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Tue, 31 Aug 2010 23:38:14 -0000 Subject: [llvm-commits] [llvm] r112673 - /llvm/trunk/include/llvm/MC/MCDwarf.h Message-ID: <20100831233814.2401C2A6C12C@llvm.org> Author: d0k Date: Tue Aug 31 18:38:13 2010 New Revision: 112673 URL: http://llvm.org/viewvc/llvm-project?rev=112673&view=rev Log: Remove noisy semicolon. Modified: llvm/trunk/include/llvm/MC/MCDwarf.h Modified: llvm/trunk/include/llvm/MC/MCDwarf.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCDwarf.h?rev=112673&r1=112672&r2=112673&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCDwarf.h (original) +++ llvm/trunk/include/llvm/MC/MCDwarf.h Tue Aug 31 18:38:13 2010 @@ -143,7 +143,7 @@ public: // Constructor to create an MCLineSection with an empty MCLineEntries // vector. - MCLineSection(): MCLineEntries() {}; + MCLineSection() {} // addLineEntry - adds an entry to this MCLineSection's line entries void addLineEntry(const MCLineEntry &LineEntry) { From dalej at apple.com Tue Aug 31 18:43:23 2010 From: dalej at apple.com (Dale Johannesen) Date: Tue, 31 Aug 2010 23:43:23 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r112674 - in /llvm-gcc-4.2/trunk/gcc: llvm-convert.cpp llvm-internal.h Message-ID: <20100831234323.1F11E2A6C12C@llvm.org> Author: johannes Date: Tue Aug 31 18:43:22 2010 New Revision: 112674 URL: http://llvm.org/viewvc/llvm-project?rev=112674&view=rev Log: Fix semantics of function-local asm "register" variables. Handling of these was allowing the value of the variable to be clobbered because the RAs allocated the register to something else. 8305081. Both gcc and llvm-gcc refer to "register variables", but that is not really what they are. The real requirements are much looser: "Defining such a register variable does not reserve the register; it remains available for other uses in places where flow control determines the variable's value is not live. This option does not guarantee that GCC will generate code that has this variable in the register you specify at all times. You may not code an explicit reference to this register in the assembler instruction template part of an asm statement and assume it will always refer to this variable. However, using the variable as an asm operand guarantees that the specified register is used for the operand." So, we can just allocate the variable normally, and use magical asm pixie dust to get its value into the right register around asm's (in practice, it's done after all loads, in the hope that this will help optimizations keep the value in the appropriate register all the time when there are enough registers to do that - works in small examples anyway). The RA need not be bothered at all. Clang doesn't currently support this feature at all but it should be able to imitate what llvm-gcc generates easily. The existing code is retained so handling of global asm register variables doesn't crash; they don't work any better than before, though. Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp llvm-gcc-4.2/trunk/gcc/llvm-internal.h Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=112674&r1=112673&r2=112674&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Tue Aug 31 18:43:22 2010 @@ -2444,14 +2444,14 @@ // ... Expressions ... //===----------------------------------------------------------------------===// -static bool canEmitRegisterVariable(tree exp) { +static bool canEmitLocalRegisterVariable(tree exp) { // Only variables can be marked as 'register'. if (TREE_CODE(exp) != VAR_DECL || !DECL_REGISTER(exp)) return false; - // We can emit inline assembler for access to global register variables. + // Global register variables are not accepted here. if (TREE_STATIC(exp) || DECL_EXTERNAL(exp) || TREE_PUBLIC(exp)) - return true; + return false; // Emit inline asm if this is local variable with assembler name on it. if (DECL_ASSEMBLER_NAME_SET_P(exp)) @@ -2461,6 +2461,19 @@ return false; } +static bool canEmitGlobalRegisterVariable(tree exp) { + // Only variables can be marked as 'register'. + if (TREE_CODE(exp) != VAR_DECL || !DECL_REGISTER(exp)) + return false; + + // Local register variables are not accepted here. + if (TREE_STATIC(exp) || DECL_EXTERNAL(exp) || TREE_PUBLIC(exp)) + return true; + + // Otherwise - it's normal automatic variable, or local register variable. + return false; +} + /// EmitLoadOfLValue - When an l-value expression is used in a context that /// requires an r-value, this method emits the lvalue computation, then loads @@ -2478,10 +2491,10 @@ DECL_GIMPLE_FORMAL_TEMP_P(exp) = 0; EmitAutomaticVariableDecl(exp); // Fall through. - } else if (canEmitRegisterVariable(exp)) { - // If this is a register variable, EmitLV can't handle it (there is no - // l-value of a register variable). Emit an inline asm node that copies the - // value out of the specified register. + } else if (canEmitGlobalRegisterVariable(exp)) { + // If this is a global register variable, EmitLV can't handle it (there is + // no l-value of a global register variable). Emit an inline asm node that + // copies the value out of the specified register. return EmitReadOfRegisterVariable(exp, DestLoc); } @@ -2496,7 +2509,11 @@ Value *Ptr = BitCastToType(LV.Ptr, Ty->getPointerTo()); LoadInst *LI = Builder.CreateLoad(Ptr, isVolatile); LI->setAlignment(Alignment); - return LI; + if (canEmitLocalRegisterVariable(exp)) { + // For register variable, move the loaded variable into the right reg. + return EmitMoveOfRegVariableToRightReg(LI, exp); + } else + return LI; } else { EmitAggregateCopy(*DestLoc, MemRef(LV.Ptr, Alignment, isVolatile), TREE_TYPE(exp)); @@ -3283,10 +3300,10 @@ Builder.Insert(Cast); SET_DECL_LLVM(lhs, Cast); return Cast; - } else if (canEmitRegisterVariable(lhs)) { - // If this is a store to a register variable, EmitLV can't handle the dest - // (there is no l-value of a register variable). Emit an inline asm node - // that copies the value into the specified register. + } else if (canEmitGlobalRegisterVariable(lhs)) { + // If this is a store to a global register variable, EmitLV can't handle the + // dest (there is no l-value of a global register variable). Emit an inline + // asm node that copies the value into the specified register. Value *RHS = Emit(rhs, 0); RHS = CastToAnyType(RHS, RHSSigned, ConvertType(TREE_TYPE(lhs)), LHSSigned); EmitModifyOfRegisterVariable(lhs, RHS); @@ -4301,8 +4318,8 @@ #define LLVM_CANONICAL_ADDRESS_CONSTRAINTS "r" #endif -/// Reads from register variables are handled by emitting an inline asm node -/// that copies the value out of the specified register. + /// Reads from global register variables are handled by emitting an inline + /// asm node that copies the value out of the specified register. Value *TreeToLLVM::EmitReadOfRegisterVariable(tree decl, const MemRef *DestLoc) { const Type *Ty = ConvertType(TREE_TYPE(decl)); @@ -4327,8 +4344,43 @@ return Call; } -/// Stores to register variables are handled by emitting an inline asm node -/// that copies the value into the specified register. +/// Reads from register variables are handled by emitting an inline asm node +/// that copies the value out of the specified register. +Value *TreeToLLVM::EmitMoveOfRegVariableToRightReg(Instruction *I, tree var) { + // Create a 'call void asm sideeffect "", "{reg}"(Ty %RHS)'. + const Type *Ty = I->getType(); + + // If there was an error, return something bogus. + if (ValidateRegisterVariable(var)) { + if (Ty->isSingleValueType()) + return UndefValue::get(Ty); + return 0; // Just don't copy something into DestLoc. + } + + std::vector ArgTys; + ArgTys.push_back(Ty); + FunctionType *FTy = FunctionType::get(Type::getVoidTy(Context), + ArgTys, false); + const char *Name = extractRegisterName(var); + int RegNum = decode_reg_name(Name); + Name = LLVM_GET_REG_NAME(Name, RegNum); + InlineAsm *IA = InlineAsm::get(FTy, "", "{"+std::string(Name)+"}", + true); + CallInst *Call = Builder.CreateCall(IA, I); + Call->setDoesNotThrow(); + // Create another asm with the same reg, this time producing an output. + // Turn this into a 'tmp = call Ty asm "", "={reg}"()'. + FunctionType *FTy2 = FunctionType::get(Ty, std::vector(), + false); + InlineAsm *IA2 = InlineAsm::get(FTy2, "", "={"+std::string(Name)+"}", + true); + CallInst *Call2 = Builder.CreateCall(IA2); + Call2->setDoesNotThrow(); + return Call2; +} + +/// Stores to global register variables are handled by emitting an inline asm +/// node that copies the value into the specified register. void TreeToLLVM::EmitModifyOfRegisterVariable(tree decl, Value *RHS) { // If there was an error, bail out. if (ValidateRegisterVariable(decl)) Modified: llvm-gcc-4.2/trunk/gcc/llvm-internal.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-internal.h?rev=112674&r1=112673&r2=112674&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-internal.h (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-internal.h Tue Aug 31 18:43:22 2010 @@ -540,6 +540,7 @@ Value *EmitASM_EXPR(tree_node *exp); Value *EmitReadOfRegisterVariable(tree_node *vardecl, const MemRef *DestLoc); void EmitModifyOfRegisterVariable(tree_node *vardecl, Value *RHS); + Value *EmitMoveOfRegVariableToRightReg(Instruction *I, tree_node *decl); // Helpers for Builtin Function Expansion. void EmitMemoryBarrier(bool ll, bool ls, bool sl, bool ss, bool device); From dalej at apple.com Tue Aug 31 18:43:55 2010 From: dalej at apple.com (Dale Johannesen) Date: Tue, 31 Aug 2010 23:43:55 -0000 Subject: [llvm-commits] [llvm] r112675 - /llvm/trunk/test/FrontendC/asm-reg-var-local.c Message-ID: <20100831234355.E1CAE2A6C12C@llvm.org> Author: johannes Date: Tue Aug 31 18:43:55 2010 New Revision: 112675 URL: http://llvm.org/viewvc/llvm-project?rev=112675&view=rev Log: Testcase for llvm checkin 112674. Added: llvm/trunk/test/FrontendC/asm-reg-var-local.c Added: llvm/trunk/test/FrontendC/asm-reg-var-local.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/asm-reg-var-local.c?rev=112675&view=auto ============================================================================== --- llvm/trunk/test/FrontendC/asm-reg-var-local.c (added) +++ llvm/trunk/test/FrontendC/asm-reg-var-local.c Tue Aug 31 18:43:55 2010 @@ -0,0 +1,32 @@ +// RUN: %llvmgcc %s -m64 -S -o - | FileCheck %s +// Exercise various use cases for local asm "register variables". +// XFAIL: * +// XTARGET: x86_64 + +int foo() { +// CHECK: %a = alloca i32 + + register int a asm("rsi")=5; +// CHECK: store i32 5, i32* %a, align 4 + + asm volatile("; %0 This asm defines rsi" : "=r"(a)); +// CHECK: %asmtmp = call i32 asm sideeffect "; $0 This asm defines rsi", "={rsi} +// CHECK: store i32 %asmtmp, i32* %a + + a = 42; +// CHECK: store i32 42, i32* %a, align 4 + + asm volatile("; %0 This asm uses rsi" : : "r"(a)); +// CHECK: %1 = load i32* %a, align 4 +// CHECK: call void asm sideeffect "", "{rsi}"(i32 %1) nounwind +// CHECK: %2 = call i32 asm sideeffect "", "={rsi}"() nounwind +// CHECK: call void asm sideeffect "; $0 This asm uses rsi", "{rsi},~{dirflag},~{fpsr},~{flags}"(i32 %2) + + return a; +// CHECK: %3 = load i32* %a, align 4 +// CHECK: call void asm sideeffect "", "{rsi}"(i32 %3) nounwind +// CHECK: %4 = call i32 asm sideeffect "", "={rsi}"() nounwind +// CHECK: store i32 %4, i32* %0, align 4 +// CHECK: %5 = load i32* %0, align 4 +// CHECK: store i32 %5, i32* %retval, align 4 +} From dpatel at apple.com Tue Aug 31 18:50:19 2010 From: dpatel at apple.com (Devang Patel) Date: Tue, 31 Aug 2010 23:50:19 -0000 Subject: [llvm-commits] [llvm] r112678 - in /llvm/trunk: include/llvm/MC/MCAsmInfo.h lib/CodeGen/AsmPrinter/DwarfDebug.cpp lib/MC/MCAsmInfo.cpp lib/MC/MCAsmInfoDarwin.cpp Message-ID: <20100831235020.02AFF2A6C12C@llvm.org> Author: dpatel Date: Tue Aug 31 18:50:19 2010 New Revision: 112678 URL: http://llvm.org/viewvc/llvm-project?rev=112678&view=rev Log: Use absolute label for DW_AT_stmt_list if a target does not prefer offset here. This patch was developed on top of original patch by Artur Pietrek. Modified: llvm/trunk/include/llvm/MC/MCAsmInfo.h llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp llvm/trunk/lib/MC/MCAsmInfo.cpp llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp Modified: llvm/trunk/include/llvm/MC/MCAsmInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAsmInfo.h?rev=112678&r1=112677&r2=112678&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCAsmInfo.h (original) +++ llvm/trunk/include/llvm/MC/MCAsmInfo.h Tue Aug 31 18:50:19 2010 @@ -255,6 +255,10 @@ /// DwarfSectionOffsetDirective - Special section offset directive. const char* DwarfSectionOffsetDirective; // Defaults to NULL + /// DwarfUsesAbsoluteLabelForStmtList - True if DW_AT_stmt_list needs + /// absolute label instead of offset. + bool DwarfUsesAbsoluteLabelForStmtList; // Defaults to true; + //===--- CBE Asm Translation Table -----------------------------------===// const char *const *AsmTransCBE; // Defaults to empty @@ -417,6 +421,9 @@ const char *getDwarfSectionOffsetDirective() const { return DwarfSectionOffsetDirective; } + bool doesDwarfUsesAbsoluteLabelForStmtList() const { + return DwarfUsesAbsoluteLabelForStmtList; + } const char *const *getAsmCBE() const { return AsmTransCBE; } Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=112678&r1=112677&r2=112678&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Tue Aug 31 18:50:19 2010 @@ -1815,7 +1815,11 @@ addUInt(Die, dwarf::DW_AT_entry_pc, dwarf::DW_FORM_addr, 0); // DW_AT_stmt_list is a offset of line number information for this // compile unit in debug_line section. - addUInt(Die, dwarf::DW_AT_stmt_list, dwarf::DW_FORM_data4, 0); + if (Asm->MAI->doesDwarfUsesAbsoluteLabelForStmtList()) + addLabel(Die, dwarf::DW_AT_stmt_list, dwarf::DW_FORM_addr, + Asm->GetTempSymbol("section_line")); + else + addUInt(Die, dwarf::DW_AT_stmt_list, dwarf::DW_FORM_data4, 0); if (!Dir.empty()) addString(Die, dwarf::DW_AT_comp_dir, dwarf::DW_FORM_string, Dir); Modified: llvm/trunk/lib/MC/MCAsmInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmInfo.cpp?rev=112678&r1=112677&r2=112678&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAsmInfo.cpp (original) +++ llvm/trunk/lib/MC/MCAsmInfo.cpp Tue Aug 31 18:50:19 2010 @@ -68,6 +68,7 @@ ExceptionsType = ExceptionHandling::None; DwarfRequiresFrameSection = true; DwarfUsesInlineInfoSection = false; + DwarfUsesAbsoluteLabelForStmtList = true; DwarfSectionOffsetDirective = 0; HasMicrosoftFastStdCallMangling = false; Modified: llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp?rev=112678&r1=112677&r2=112678&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp (original) +++ llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp Tue Aug 31 18:50:19 2010 @@ -44,5 +44,7 @@ HasDotTypeDotSizeDirective = false; HasNoDeadStrip = true; + + DwarfUsesAbsoluteLabelForStmtList = false; } From dalej at apple.com Tue Aug 31 19:40:10 2010 From: dalej at apple.com (Dale Johannesen) Date: Wed, 01 Sep 2010 00:40:10 -0000 Subject: [llvm-commits] [llvm] r112685 - /llvm/trunk/include/llvm/IntrinsicsX86.td Message-ID: <20100901004010.19D382A6C12C@llvm.org> Author: johannes Date: Tue Aug 31 19:40:09 2010 New Revision: 112685 URL: http://llvm.org/viewvc/llvm-project?rev=112685&view=rev Log: Add some MMX intrinsics that duplicate functionality available in normal llvm operators. We aren't going to use those for MMX any more because it's unsafe for the optimizers to synthesize new MMX instructions. Modified: llvm/trunk/include/llvm/IntrinsicsX86.td Modified: llvm/trunk/include/llvm/IntrinsicsX86.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsX86.td?rev=112685&r1=112684&r2=112685&view=diff ============================================================================== --- llvm/trunk/include/llvm/IntrinsicsX86.td (original) +++ llvm/trunk/include/llvm/IntrinsicsX86.td Tue Aug 31 19:40:09 2010 @@ -1324,6 +1324,19 @@ // Integer arithmetic ops. let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". // Addition + def int_x86_mmx_padd_b : GCCBuiltin<"__builtin_ia32_paddb">, + Intrinsic<[llvm_v8i8_ty], [llvm_v8i8_ty, llvm_v8i8_ty], + [IntrNoMem]>; + def int_x86_mmx_padd_w : GCCBuiltin<"__builtin_ia32_paddw">, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_v4i16_ty], + [IntrNoMem]>; + def int_x86_mmx_padd_d : GCCBuiltin<"__builtin_ia32_paddd">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty], + [IntrNoMem]>; + def int_x86_mmx_padd_q : GCCBuiltin<"__builtin_ia32_paddq">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty], + [IntrNoMem]>; + def int_x86_mmx_padds_b : GCCBuiltin<"__builtin_ia32_paddsb">, Intrinsic<[llvm_v8i8_ty], [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem, Commutative]>; @@ -1339,6 +1352,19 @@ llvm_v4i16_ty], [IntrNoMem, Commutative]>; // Subtraction + def int_x86_mmx_psub_b : GCCBuiltin<"__builtin_ia32_psubb">, + Intrinsic<[llvm_v8i8_ty], [llvm_v8i8_ty, llvm_v8i8_ty], + [IntrNoMem]>; + def int_x86_mmx_psub_w : GCCBuiltin<"__builtin_ia32_psubw">, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_v4i16_ty], + [IntrNoMem]>; + def int_x86_mmx_psub_d : GCCBuiltin<"__builtin_ia32_psubd">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty], + [IntrNoMem]>; + def int_x86_mmx_psub_q : GCCBuiltin<"__builtin_ia32_psubq">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty], + [IntrNoMem]>; + def int_x86_mmx_psubs_b : GCCBuiltin<"__builtin_ia32_psubsb">, Intrinsic<[llvm_v8i8_ty], [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>; @@ -1357,6 +1383,9 @@ def int_x86_mmx_pmulh_w : GCCBuiltin<"__builtin_ia32_pmulhw">, Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem, Commutative]>; + def int_x86_mmx_pmull_w : GCCBuiltin<"__builtin_ia32_pmullw">, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, + llvm_v4i16_ty], [IntrNoMem, Commutative]>; def int_x86_mmx_pmulhu_w : GCCBuiltin<"__builtin_ia32_pmulhuw">, Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem, Commutative]>; @@ -1367,6 +1396,20 @@ Intrinsic<[llvm_v2i32_ty], [llvm_v4i16_ty, llvm_v4i16_ty], [IntrNoMem, Commutative]>; + // Bitwise operations + def int_x86_mmx_pand : GCCBuiltin<"__builtin_ia32_pand">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty], + [IntrNoMem]>; + def int_x86_mmx_pandn : GCCBuiltin<"__builtin_ia32_pandn">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty], + [IntrNoMem]>; + def int_x86_mmx_por : GCCBuiltin<"__builtin_ia32_por">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty], + [IntrNoMem]>; + def int_x86_mmx_pxor : GCCBuiltin<"__builtin_ia32_pxor">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, llvm_v1i64_ty], + [IntrNoMem]>; + // Averages def int_x86_mmx_pavg_b : GCCBuiltin<"__builtin_ia32_pavgb">, Intrinsic<[llvm_v8i8_ty], [llvm_v8i8_ty, @@ -1468,6 +1511,28 @@ llvm_v4i16_ty], [IntrNoMem]>; } +// Unpacking ops. +let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". + def int_x86_mmx_punpckhbw : GCCBuiltin<"__builtin_ia32_punpckhbw">, + Intrinsic<[llvm_v8i8_ty], [llvm_v8i8_ty, llvm_v8i8_ty], + [IntrNoMem]>; + def int_x86_mmx_punpckhwd : GCCBuiltin<"__builtin_ia32_punpckhwd">, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_v4i16_ty], + [IntrNoMem]>; + def int_x86_mmx_punpckhdq : GCCBuiltin<"__builtin_ia32_punpckhdq">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty], + [IntrNoMem]>; + def int_x86_mmx_punpcklbw : GCCBuiltin<"__builtin_ia32_punpcklbw">, + Intrinsic<[llvm_v8i8_ty], [llvm_v8i8_ty, llvm_v8i8_ty], + [IntrNoMem]>; + def int_x86_mmx_punpcklwd : GCCBuiltin<"__builtin_ia32_punpcklwd">, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_v4i16_ty], + [IntrNoMem]>; + def int_x86_mmx_punpckldq : GCCBuiltin<"__builtin_ia32_punpckldq">, + Intrinsic<[llvm_v2i32_ty], [llvm_v2i32_ty, llvm_v2i32_ty], + [IntrNoMem]>; +} + // Integer comparison ops let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". def int_x86_mmx_pcmpeq_b : GCCBuiltin<"__builtin_ia32_pcmpeqb">, @@ -1501,4 +1566,13 @@ def int_x86_mmx_movnt_dq : GCCBuiltin<"__builtin_ia32_movntq">, Intrinsic<[], [llvm_ptr_ty, llvm_v1i64_ty], []>; + + def int_x86_mmx_cvtsi32_MMX : GCCBuiltin<"__builtin_ia32_vec_init_v2si">, + Intrinsic<[llvm_v1i64_ty], [llvm_i32_ty], [IntrNoMem]>; + def int_x86_mmx_cvtsi64_MMX : + Intrinsic<[llvm_v1i64_ty], [llvm_i64_ty], [IntrNoMem]>; + def int_x86_mmx_MMX_si32 : GCCBuiltin<"__builtin_ia32_vec_ext_v2si">, + Intrinsic<[llvm_i32_ty], [llvm_v1i64_ty], [IntrNoMem]>; + def int_x86_mmx_MMX_si64 : + Intrinsic<[llvm_i64_ty], [llvm_v1i64_ty], [IntrNoMem]>; } From bruno.cardoso at gmail.com Tue Aug 31 19:51:36 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Wed, 01 Sep 2010 00:51:36 -0000 Subject: [llvm-commits] [llvm] r112687 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20100901005136.63F4F2A6C12C@llvm.org> Author: bruno Date: Tue Aug 31 19:51:36 2010 New Revision: 112687 URL: http://llvm.org/viewvc/llvm-project?rev=112687&view=rev Log: Move some functions around so they can be used for some other to come function Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=112687&r1=112686&r2=112687&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Aug 31 19:51:36 2010 @@ -2576,6 +2576,14 @@ // Other Lowering Hooks //===----------------------------------------------------------------------===// +static bool MayFoldLoad(SDValue Op) { + return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode()); +} + +static bool MayFoldIntoStore(SDValue Op) { + return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin()); +} + static bool isTargetShuffle(unsigned Opcode) { switch(Opcode) { default: return false; @@ -10563,14 +10571,6 @@ } } -static bool MayFoldLoad(SDValue Op) { - return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode()); -} - -static bool MayFoldIntoStore(SDValue Op) { - return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin()); -} - /// IsDesirableToPromoteOp - This method query the target whether it is /// beneficial for dag combiner to promote the specified node. If true, it /// should return the desired promotion type by reference. From bruno.cardoso at gmail.com Tue Aug 31 19:57:08 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Wed, 01 Sep 2010 00:57:08 -0000 Subject: [llvm-commits] [llvm] r112689 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20100901005708.841F12A6C12C@llvm.org> Author: bruno Date: Tue Aug 31 19:57:08 2010 New Revision: 112689 URL: http://llvm.org/viewvc/llvm-project?rev=112689&view=rev Log: minor change, simplify some logic Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=112689&r1=112688&r2=112689&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Aug 31 19:57:08 2010 @@ -5127,10 +5127,10 @@ unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp); - if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32)) + if (HasSSE2 && NumElems == 4) return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG); - if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64)) + if (HasSSE2 && NumElems == 2) return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V1, TargetMask, DAG); @@ -5159,10 +5159,10 @@ if (ISD::isBuildVectorAllZeros(V1.getNode())) return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); if (!isMMX && !X86::isMOVLPMask(SVOp)) { - if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64)) + if (HasSSE2 && NumElems == 2) return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); - if (VT == MVT::v4i32 || VT == MVT::v4f32) + if (NumElems == 4) return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); } } From grosser at fim.uni-passau.de Tue Aug 31 19:57:46 2010 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Wed, 01 Sep 2010 02:57:46 +0200 Subject: [llvm-commits] [PATCH]: Fix for DW_at_stmt_list offset In-Reply-To: <30742_1282810219_4C76216A_30742_1176_1_AANLkTimZcWYwypKEJRfSfejDAQtToYsCjswzt=CUddV+@mail.gmail.com> References: <30742_1282810219_4C76216A_30742_1176_1_AANLkTimZcWYwypKEJRfSfejDAQtToYsCjswzt=CUddV+@mail.gmail.com> Message-ID: <4C7DA50A.6040207@fim.uni-passau.de> On 08/26/2010 10:08 AM, Krister Wombell wrote: > In the compilation unit DIE, DW_at_stmt_list is supposed to be an offset > into the debug_line information where the line program for this compile > unit begins. > > It needs to be a label so that a relocation is emitted and during final > linking the offset is adjusted. Without this all CUs contain offset 0 > (and only 1 of them will be correct) > > Mostly been able to debug an ELF program under gdb now. > > Krister Hey Krister, I tried your patch and it solved the issue that I was not even able to set break points at a specific line. With your patch this works nicely in gdb. One thing I realized is that this patch needs the patch in "[PATCH] fix debug_ranges for ELF targets". Furthermore the following change is in both patches. I suppose it should be part of the "fix debug_ranges" patch? Index: lib/CodeGen/AsmPrinter/DwarfDebug.cpp =================================================================== --- lib/CodeGen/AsmPrinter/DwarfDebug.cpp (revision 112155) +++ lib/CodeGen/AsmPrinter/DwarfDebug.cpp (working copy) @@ -3119,9 +3120,8 @@ case dwarf::DW_AT_ranges: { // DW_AT_range Value encodes offset in debug_range section. DIEInteger *V = cast(Values[i]); - Asm->EmitLabelOffsetDifference(DwarfDebugRangeSectionSym, + Asm->EmitLabelPlusOffset(DwarfDebugRangeSectionSym, V->getValue(), - DwarfDebugRangeSectionSym, 4); break; } @everybody: Could someone knowing DWARF review these patches. It is really nice to have usable debugging in gdb with programs consisting of more than one CU. Cheers Tobi From isanbard at gmail.com Tue Aug 31 20:05:07 2010 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 31 Aug 2010 18:05:07 -0700 Subject: [llvm-commits] [llvm] r112664 - in /llvm/trunk: lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td test/CodeGen/ARM/mvncc.ll test/CodeGen/Thumb2/thumb2-mvncc.ll In-Reply-To: <2F3F6800-6F8E-4EB7-B055-C29C8F89DFFD@apple.com> References: <20100831224122.6BA6E2A6C12E@llvm.org> <2F3F6800-6F8E-4EB7-B055-C29C8F89DFFD@apple.com> Message-ID: True. I didn't know what the protocol was for this. :) -bw On Aug 31, 2010, at 3:49 PM, Eric Christopher wrote: > You can merge these two tests together and use a check prefix. > > -eric > > On Aug 31, 2010, at 3:41 PM, Bill Wendling wrote: > >> Added: llvm/trunk/test/CodeGen/ARM/mvncc.ll >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/mvncc.ll?rev=112664&view=auto >> ============================================================================== >> --- llvm/trunk/test/CodeGen/ARM/mvncc.ll (added) >> +++ llvm/trunk/test/CodeGen/ARM/mvncc.ll Tue Aug 31 17:41:22 2010 >> @@ -0,0 +1,12 @@ >> +; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s >> + >> +define i32 @f1(i32 %t) nounwind { >> +; CHECK: f1 >> +; CHECK-NOT: tst >> +; CHECK: and >> +; CHECK: mvnne >> + %and = and i32 %t, 256 >> + %tobool = icmp eq i32 %and, 0 >> + %retval.0 = select i1 %tobool, i32 0, i32 -26 >> + ret i32 %retval.0 >> +} >> >> Added: llvm/trunk/test/CodeGen/Thumb2/thumb2-mvncc.ll >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-mvncc.ll?rev=112664&view=auto >> ============================================================================== >> --- llvm/trunk/test/CodeGen/Thumb2/thumb2-mvncc.ll (added) >> +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-mvncc.ll Tue Aug 31 17:41:22 2010 >> @@ -0,0 +1,13 @@ >> +; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s >> + >> +define i32 @f1(i32 %t) nounwind { >> +; CHECK: f1 >> +; CHECK-NOT: tst >> +; CHECK: ands >> +; CHECK: it ne >> +; CHECK: mvnne >> + %and = and i32 %t, 256 >> + %tobool = icmp eq i32 %and, 0 >> + %retval.0 = select i1 %tobool, i32 0, i32 -26 >> + ret i32 %retval.0 >> +} > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dalej at apple.com Tue Aug 31 20:08:18 2010 From: dalej at apple.com (Dale Johannesen) Date: Tue, 31 Aug 2010 18:08:18 -0700 Subject: [llvm-commits] [LLVMdev] Build warning on TOT In-Reply-To: <24001F31-2FC2-40A5-8BB6-DD810C3FC95A@apple.com> References: <24001F31-2FC2-40A5-8BB6-DD810C3FC95A@apple.com> Message-ID: <0481E63E-DBD0-4D45-B28E-F2D3F93D5723@apple.com> Yes, and it's a recent regression. Building without -j shows where it really is: llvm[3]: Building ARM.td decoder tables with tblgen Decoding Conflict: ____0001111_........________.... ____0001111_.................... ____0001111..................... ____0001..1..................... ____0001........................ ____00.......................... ____............................ ................................ MVNCCi ____0001111_____________________ MVNs ____0001111_____________________ llvm[3]: Building ARM.td enhanced disassembly information with tblgen On Aug 31, 2010, at 5:51 PMPDT, Cameron Esfahani wrote: > Anyone seeing the following: > > llvm[3]: Compiling SelectionDAGISel.cpp for Release+Asserts build > Decoding Conflict: > ____0001111_........________.... > ____0001111_.................... > ____0001111..................... > ____0001..1..................... > ____0001........................ > ____00.......................... > ____............................ > ................................ > MVNCCi ____0001111_____________________ > MVNs ____0001111_____________________ > > Cameron Esfahani > dirty at apple.com > > "All that is necessary for the triumph of evil is that good men do > nothing." > > > > > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev From gohman at apple.com Tue Aug 31 20:45:53 2010 From: gohman at apple.com (Dan Gohman) Date: Wed, 01 Sep 2010 01:45:53 -0000 Subject: [llvm-commits] [llvm] r112692 - in /llvm/trunk: include/llvm/Analysis/IVUsers.h lib/Analysis/IVUsers.cpp lib/Transforms/Scalar/LoopStrengthReduce.cpp test/CodeGen/X86/lsr-reuse.ll Message-ID: <20100901014553.B2F3F2A6C12C@llvm.org> Author: djg Date: Tue Aug 31 20:45:53 2010 New Revision: 112692 URL: http://llvm.org/viewvc/llvm-project?rev=112692&view=rev Log: Revert 112442 and 112440 until the compile time problems introduced by 112440 are resolved. Modified: llvm/trunk/include/llvm/Analysis/IVUsers.h llvm/trunk/lib/Analysis/IVUsers.cpp llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp llvm/trunk/test/CodeGen/X86/lsr-reuse.ll Modified: llvm/trunk/include/llvm/Analysis/IVUsers.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/IVUsers.h?rev=112692&r1=112691&r2=112692&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/IVUsers.h (original) +++ llvm/trunk/include/llvm/Analysis/IVUsers.h Tue Aug 31 20:45:53 2010 @@ -27,7 +27,6 @@ class IVUsers; class ScalarEvolution; class SCEV; -class SCEVAddRecExpr; class IVUsers; /// IVStrideUse - Keep track of one use of a strided induction variable. @@ -123,7 +122,7 @@ LoopInfo *LI; DominatorTree *DT; ScalarEvolution *SE; - SmallPtrSet Processed; + SmallPtrSet Processed; /// IVUses - A list of all tracked IV uses of induction variable expressions /// we are interested in. @@ -135,16 +134,14 @@ virtual void releaseMemory(); - const SCEVAddRecExpr *findInterestingAddRec(const SCEV *S) const; - bool isInterestingUser(const Instruction *User) const; - public: static char ID; // Pass ID, replacement for typeid IVUsers(); - /// AddUsersIfInteresting - Inspect the def-use graph starting at the - /// specified Instruction and add IVUsers. - void AddUsersIfInteresting(Instruction *I); + /// AddUsersIfInteresting - Inspect the specified Instruction. If it is a + /// reducible SCEV, recursively add its users to the IVUsesByStride set and + /// return true. Otherwise, return false. + bool AddUsersIfInteresting(Instruction *I); IVStrideUse &AddUser(Instruction *User, Value *Operand); Modified: llvm/trunk/lib/Analysis/IVUsers.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/IVUsers.cpp?rev=112692&r1=112691&r2=112692&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/IVUsers.cpp (original) +++ llvm/trunk/lib/Analysis/IVUsers.cpp Tue Aug 31 20:45:53 2010 @@ -35,123 +35,112 @@ return new IVUsers(); } -/// findInterestingAddRec - Test whether the given expression is interesting. -/// Return the addrec with the current loop which makes it interesting, or -/// null if it is not interesting. -const SCEVAddRecExpr *IVUsers::findInterestingAddRec(const SCEV *S) const { +/// isInteresting - Test whether the given expression is "interesting" when +/// used by the given expression, within the context of analyzing the +/// given loop. +static bool isInteresting(const SCEV *S, const Instruction *I, const Loop *L, + ScalarEvolution *SE) { // An addrec is interesting if it's affine or if it has an interesting start. if (const SCEVAddRecExpr *AR = dyn_cast(S)) { // Keep things simple. Don't touch loop-variant strides. if (AR->getLoop() == L) - return AR; - // We don't yet know how to do effective SCEV expansions for addrecs - // with interesting steps. - if (findInterestingAddRec(AR->getStepRecurrence(*SE))) - return 0; - // Otherwise recurse to see if the start value is interesting. - return findInterestingAddRec(AR->getStart()); + return AR->isAffine() || !L->contains(I); + // Otherwise recurse to see if the start value is interesting, and that + // the step value is not interesting, since we don't yet know how to + // do effective SCEV expansions for addrecs with interesting steps. + return isInteresting(AR->getStart(), I, L, SE) && + !isInteresting(AR->getStepRecurrence(*SE), I, L, SE); } // An add is interesting if exactly one of its operands is interesting. if (const SCEVAddExpr *Add = dyn_cast(S)) { + bool AnyInterestingYet = false; for (SCEVAddExpr::op_iterator OI = Add->op_begin(), OE = Add->op_end(); OI != OE; ++OI) - if (const SCEVAddRecExpr *AR = findInterestingAddRec(*OI)) - return AR; - return 0; + if (isInteresting(*OI, I, L, SE)) { + if (AnyInterestingYet) + return false; + AnyInterestingYet = true; + } + return AnyInterestingYet; } // Nothing else is interesting here. - return 0; + return false; } -bool IVUsers::isInterestingUser(const Instruction *User) const { - // Void and FP expressions cannot be reduced. - if (!SE->isSCEVable(User->getType())) - return false; +/// AddUsersIfInteresting - Inspect the specified instruction. If it is a +/// reducible SCEV, recursively add its users to the IVUsesByStride set and +/// return true. Otherwise, return false. +bool IVUsers::AddUsersIfInteresting(Instruction *I) { + if (!SE->isSCEVable(I->getType())) + return false; // Void and FP expressions cannot be reduced. // LSR is not APInt clean, do not touch integers bigger than 64-bits. - if (SE->getTypeSizeInBits(User->getType()) > 64) - return false; - - // Don't descend into PHI nodes outside the current loop. - if (LI->getLoopFor(User->getParent()) != L && - isa(User)) + if (SE->getTypeSizeInBits(I->getType()) > 64) return false; - // Otherwise, it may be interesting. - return true; -} - -/// AddUsersIfInteresting - Inspect the specified instruction. If it is a -/// reducible SCEV, recursively add its users to the IVUsesByStride set and -/// return true. Otherwise, return false. -void IVUsers::AddUsersIfInteresting(Instruction *I) { - // Stop if we've seen this before. if (!Processed.insert(I)) - return; + return true; // Instruction already handled. - // If this PHI node is not SCEVable, ignore it. - if (!SE->isSCEVable(I->getType())) - return; + // Get the symbolic expression for this instruction. + const SCEV *ISE = SE->getSCEV(I); - // If this PHI node is not an addrec for this loop, ignore it. - const SCEVAddRecExpr *Expr = findInterestingAddRec(SE->getSCEV(I)); - if (!Expr) - return; - - // Walk the def-use graph. - SmallVector, 16> Worklist; - Worklist.push_back(std::make_pair(I, Expr)); - do { - std::pair P = - Worklist.pop_back_val(); - Instruction *Op = P.first; - const SCEVAddRecExpr *OpAR = P.second; - - // Visit Op's users. - SmallPtrSet VisitedUsers; - for (Value::use_iterator UI = Op->use_begin(), E = Op->use_end(); - UI != E; ++UI) { - // Don't visit any individual user more than once. - Instruction *User = cast(*UI); - if (!VisitedUsers.insert(User)) - continue; - - // If it's an affine addrec (which we can pretty safely re-expand) inside - // the loop, or a potentially non-affine addrec outside the loop (which - // we can evaluate outside of the loop), follow it. - if (OpAR->isAffine() || !L->contains(User)) { - if (isInterestingUser(User)) { - const SCEV *UserExpr = SE->getSCEV(User); - - if (const SCEVAddRecExpr *AR = findInterestingAddRec(UserExpr)) { - // Interesting. Keep searching. - if (Processed.insert(User)) - Worklist.push_back(std::make_pair(User, AR)); - continue; - } - } + // If we've come to an uninteresting expression, stop the traversal and + // call this a user. + if (!isInteresting(ISE, I, L, SE)) + return false; + + SmallPtrSet UniqueUsers; + for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); + UI != E; ++UI) { + Instruction *User = cast(*UI); + if (!UniqueUsers.insert(User)) + continue; + + // Do not infinitely recurse on PHI nodes. + if (isa(User) && Processed.count(User)) + continue; + + // Descend recursively, but not into PHI nodes outside the current loop. + // It's important to see the entire expression outside the loop to get + // choices that depend on addressing mode use right, although we won't + // consider references outside the loop in all cases. + // If User is already in Processed, we don't want to recurse into it again, + // but do want to record a second reference in the same instruction. + bool AddUserToIVUsers = false; + if (LI->getLoopFor(User->getParent()) != L) { + if (isa(User) || Processed.count(User) || + !AddUsersIfInteresting(User)) { + DEBUG(dbgs() << "FOUND USER in other loop: " << *User << '\n' + << " OF SCEV: " << *ISE << '\n'); + AddUserToIVUsers = true; } + } else if (Processed.count(User) || + !AddUsersIfInteresting(User)) { + DEBUG(dbgs() << "FOUND USER: " << *User << '\n' + << " OF SCEV: " << *ISE << '\n'); + AddUserToIVUsers = true; + } - // Otherwise, this is the point where the def-use chain - // becomes uninteresting. Call it an IV User. - AddUser(User, Op); + if (AddUserToIVUsers) { + // Okay, we found a user that we cannot reduce. + IVUses.push_back(new IVStrideUse(this, User, I)); + IVStrideUse &NewUse = IVUses.back(); + // Transform the expression into a normalized form. + ISE = TransformForPostIncUse(NormalizeAutodetect, + ISE, User, I, + NewUse.PostIncLoops, + *SE, *DT); + DEBUG(dbgs() << " NORMALIZED TO: " << *ISE << '\n'); } - } while (!Worklist.empty()); + } + return true; } IVStrideUse &IVUsers::AddUser(Instruction *User, Value *Operand) { IVUses.push_back(new IVStrideUse(this, User, Operand)); - IVStrideUse &NewUse = IVUses.back(); - - // Auto-detect and remember post-inc loops for this expression. - const SCEV *S = SE->getSCEV(Operand); - (void)TransformForPostIncUse(NormalizeAutodetect, - S, User, Operand, - NewUse.PostIncLoops, - *SE, *DT); - return NewUse; + return IVUses.back(); } IVUsers::IVUsers() @@ -176,7 +165,7 @@ // them by stride. Start by finding all of the PHI nodes in the header for // this loop. If they are induction variables, inspect their uses. for (BasicBlock::iterator I = L->getHeader()->begin(); isa(I); ++I) - AddUsersIfInteresting(I); + (void)AddUsersIfInteresting(I); return false; } Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=112692&r1=112691&r2=112692&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Tue Aug 31 20:45:53 2010 @@ -113,7 +113,6 @@ public: void CountRegister(const SCEV *Reg, size_t LUIdx); void DropRegister(const SCEV *Reg, size_t LUIdx); - void DropUse(size_t LUIdx, size_t NewLUIdx); void DropUse(size_t LUIdx); bool isRegUsedByUsesOtherThan(const SCEV *Reg, size_t LUIdx) const; @@ -152,24 +151,6 @@ RSD.UsedByIndices.reset(LUIdx); } -/// DropUse - Clear out reference by use LUIdx, and prepare for use NewLUIdx -/// to be swapped into LUIdx's position. -void -RegUseTracker::DropUse(size_t LUIdx, size_t NewLUIdx) { - // Remove the use index from every register's use list. - for (RegUsesTy::iterator I = RegUsesMap.begin(), E = RegUsesMap.end(); - I != E; ++I) { - SmallBitVector &UsedByIndices = I->second.UsedByIndices; - UsedByIndices.resize(std::max(UsedByIndices.size(), NewLUIdx + 1)); - if (LUIdx < UsedByIndices.size()) { - UsedByIndices[LUIdx] = UsedByIndices[NewLUIdx]; - UsedByIndices.reset(NewLUIdx); - } else - UsedByIndices.reset(LUIdx); - } -} - -/// DropUse - Clear out reference by use LUIdx. void RegUseTracker::DropUse(size_t LUIdx) { // Remove the use index from every register's use list. @@ -1353,9 +1334,7 @@ UseMapDenseMapInfo> UseMapTy; UseMapTy UseMap; - bool reconcileNewOffset(LSRUse &LU, - int64_t NewMinOffset, int64_t NewMaxOffset, - bool HasBaseReg, + bool reconcileNewOffset(LSRUse &LU, int64_t NewOffset, bool HasBaseReg, LSRUse::KindType Kind, const Type *AccessTy); std::pair getUse(const SCEV *&Expr, @@ -1364,8 +1343,7 @@ void DeleteUse(LSRUse &LU); - LSRUse *FindUseWithSimilarFormula(const Formula &F, const LSRUse &OrigLU, - int64_t &NewBaseOffs); + LSRUse *FindUseWithSimilarFormula(const Formula &F, const LSRUse &OrigLU); public: void InsertInitialFormula(const SCEV *S, LSRUse &LU, size_t LUIdx); @@ -1866,13 +1844,11 @@ /// at the given offset and other details. If so, update the use and /// return true. bool -LSRInstance::reconcileNewOffset(LSRUse &LU, - int64_t NewMinOffset, int64_t NewMaxOffset, - bool HasBaseReg, +LSRInstance::reconcileNewOffset(LSRUse &LU, int64_t NewOffset, bool HasBaseReg, LSRUse::KindType Kind, const Type *AccessTy) { - int64_t ResultMinOffset = LU.MinOffset; - int64_t ResultMaxOffset = LU.MaxOffset; - const Type *ResultAccessTy = AccessTy; + int64_t NewMinOffset = LU.MinOffset; + int64_t NewMaxOffset = LU.MaxOffset; + const Type *NewAccessTy = AccessTy; // Check for a mismatched kind. It's tempting to collapse mismatched kinds to // something conservative, however this can pessimize in the case that one of @@ -1880,27 +1856,29 @@ if (LU.Kind != Kind) return false; // Conservatively assume HasBaseReg is true for now. - if (NewMinOffset < LU.MinOffset) { - if (!isAlwaysFoldable(LU.MaxOffset - NewMinOffset, 0, HasBaseReg, + if (NewOffset < LU.MinOffset) { + if (!isAlwaysFoldable(LU.MaxOffset - NewOffset, 0, HasBaseReg, Kind, AccessTy, TLI)) return false; - ResultMinOffset = NewMinOffset; - } else if (NewMaxOffset > LU.MaxOffset) { - if (!isAlwaysFoldable(NewMaxOffset - LU.MinOffset, 0, HasBaseReg, + NewMinOffset = NewOffset; + } else if (NewOffset > LU.MaxOffset) { + if (!isAlwaysFoldable(NewOffset - LU.MinOffset, 0, HasBaseReg, Kind, AccessTy, TLI)) return false; - ResultMaxOffset = NewMaxOffset; + NewMaxOffset = NewOffset; } // Check for a mismatched access type, and fall back conservatively as needed. // TODO: Be less conservative when the type is similar and can use the same // addressing modes. if (Kind == LSRUse::Address && AccessTy != LU.AccessTy) - ResultAccessTy = Type::getVoidTy(AccessTy->getContext()); + NewAccessTy = Type::getVoidTy(AccessTy->getContext()); // Update the use. - LU.MinOffset = ResultMinOffset; - LU.MaxOffset = ResultMaxOffset; - LU.AccessTy = ResultAccessTy; + LU.MinOffset = NewMinOffset; + LU.MaxOffset = NewMaxOffset; + LU.AccessTy = NewAccessTy; + if (NewOffset != LU.Offsets.back()) + LU.Offsets.push_back(NewOffset); return true; } @@ -1925,12 +1903,9 @@ // A use already existed with this base. size_t LUIdx = P.first->second; LSRUse &LU = Uses[LUIdx]; - if (reconcileNewOffset(LU, Offset, Offset, - /*HasBaseReg=*/true, Kind, AccessTy)) { - LU.Offsets.push_back(Offset); + if (reconcileNewOffset(LU, Offset, /*HasBaseReg=*/true, Kind, AccessTy)) // Reuse this use. return std::make_pair(LUIdx, Offset); - } } // Create a new use. @@ -1939,7 +1914,11 @@ Uses.push_back(LSRUse(Kind, AccessTy)); LSRUse &LU = Uses[LUIdx]; - LU.Offsets.push_back(Offset); + // We don't need to track redundant offsets, but we don't need to go out + // of our way here to avoid them. + if (LU.Offsets.empty() || Offset != LU.Offsets.back()) + LU.Offsets.push_back(Offset); + LU.MinOffset = Offset; LU.MaxOffset = Offset; return std::make_pair(LUIdx, Offset); @@ -1947,12 +1926,8 @@ /// DeleteUse - Delete the given use from the Uses list. void LSRInstance::DeleteUse(LSRUse &LU) { - if (&LU != &Uses.back()) { + if (&LU != &Uses.back()) std::swap(LU, Uses.back()); - RegUses.DropUse(&LU - Uses.begin(), Uses.size() - 1); - } else { - RegUses.DropUse(&LU - Uses.begin()); - } Uses.pop_back(); } @@ -1960,9 +1935,8 @@ /// a formula that has the same registers as the given formula. LSRUse * LSRInstance::FindUseWithSimilarFormula(const Formula &OrigF, - const LSRUse &OrigLU, - int64_t &NewBaseOffs) { - // Search all uses for a formula similar to OrigF. This could be more clever. + const LSRUse &OrigLU) { + // Search all uses for the formula. This could be more clever. for (size_t LUIdx = 0, NumUses = Uses.size(); LUIdx != NumUses; ++LUIdx) { LSRUse &LU = Uses[LUIdx]; // Check whether this use is close enough to OrigLU, to see whether it's @@ -1985,15 +1959,8 @@ F.ScaledReg == OrigF.ScaledReg && F.AM.BaseGV == OrigF.AM.BaseGV && F.AM.Scale == OrigF.AM.Scale) { - // Ok, all the registers and symbols matched. Check to see if the - // immediate looks nicer than our old one. - if (OrigF.AM.BaseOffs == INT64_MIN || - (F.AM.BaseOffs != INT64_MIN && - abs64(F.AM.BaseOffs) < abs64(OrigF.AM.BaseOffs))) { - // Looks good. Take it. - NewBaseOffs = F.AM.BaseOffs; + if (F.AM.BaseOffs == 0) return &LU; - } // This is the formula where all the registers and symbols matched; // there aren't going to be any others. Since we declined it, we // can skip the rest of the formulae and procede to the next LSRUse. @@ -2634,17 +2601,6 @@ WorkItem(size_t LI, int64_t I, const SCEV *R) : LUIdx(LI), Imm(I), OrigReg(R) {} - bool operator==(const WorkItem &that) const { - return LUIdx == that.LUIdx && Imm == that.Imm && OrigReg == that.OrigReg; - } - bool operator<(const WorkItem &that) const { - if (LUIdx != that.LUIdx) - return LUIdx < that.LUIdx; - if (Imm != that.Imm) - return Imm < that.Imm; - return OrigReg < that.OrigReg; - } - void print(raw_ostream &OS) const; void dump() const; }; @@ -2684,7 +2640,8 @@ // Now examine each set of registers with the same base value. Build up // a list of work to do and do the work in a separate step so that we're // not adding formulae and register counts while we're searching. - SmallSetVector WorkItems; + SmallVector WorkItems; + SmallSet, 32> UniqueItems; for (SmallVectorImpl::const_iterator I = Sequence.begin(), E = Sequence.end(); I != E; ++I) { const SCEV *Reg = *I; @@ -2727,10 +2684,10 @@ // Compute the difference between the two. int64_t Imm = (uint64_t)JImm - M->first; for (int LUIdx = UsedByIndices.find_first(); LUIdx != -1; - LUIdx = UsedByIndices.find_next(LUIdx)) { + LUIdx = UsedByIndices.find_next(LUIdx)) // Make a memo of this use, offset, and register tuple. - WorkItems.insert(WorkItem(LUIdx, Imm, OrigReg)); - } + if (UniqueItems.insert(std::make_pair(LUIdx, Imm))) + WorkItems.push_back(WorkItem(LUIdx, Imm, OrigReg)); } } } @@ -2738,6 +2695,7 @@ Map.clear(); Sequence.clear(); UsedByIndicesMap.clear(); + UniqueItems.clear(); // Now iterate through the worklist and add new formulae. for (SmallVectorImpl::const_iterator I = WorkItems.begin(), @@ -3034,12 +2992,8 @@ E = LU.Formulae.end(); I != E; ++I) { const Formula &F = *I; if (F.AM.BaseOffs != 0 && F.AM.Scale == 0) { - int64_t NewBaseOffs; - if (LSRUse *LUThatHas = FindUseWithSimilarFormula(F, LU, - NewBaseOffs)) { - if (reconcileNewOffset(*LUThatHas, - F.AM.BaseOffs + LU.MinOffset - NewBaseOffs, - F.AM.BaseOffs + LU.MaxOffset - NewBaseOffs, + if (LSRUse *LUThatHas = FindUseWithSimilarFormula(F, LU)) { + if (reconcileNewOffset(*LUThatHas, F.AM.BaseOffs, /*HasBaseReg=*/false, LU.Kind, LU.AccessTy)) { DEBUG(dbgs() << " Deleting use "; LU.print(dbgs()); @@ -3047,30 +3001,6 @@ LUThatHas->AllFixupsOutsideLoop &= LU.AllFixupsOutsideLoop; - // Update the relocs to reference the new use. - // Do this first so that MinOffset and MaxOffset are updated - // before we begin to determine which formulae to delete. - for (SmallVectorImpl::iterator I = Fixups.begin(), - E = Fixups.end(); I != E; ++I) { - LSRFixup &Fixup = *I; - if (Fixup.LUIdx == LUIdx) { - Fixup.LUIdx = LUThatHas - &Uses.front(); - Fixup.Offset += F.AM.BaseOffs - NewBaseOffs; - DEBUG(dbgs() << "New fixup has offset " - << Fixup.Offset << '\n'); - LUThatHas->Offsets.push_back(Fixup.Offset); - if (Fixup.Offset > LUThatHas->MaxOffset) - LUThatHas->MaxOffset = Fixup.Offset; - if (Fixup.Offset < LUThatHas->MinOffset) - LUThatHas->MinOffset = Fixup.Offset; - } - // DeleteUse will do a swap+pop_back, so if this fixup is - // now pointing to the last LSRUse, update it to point to the - // position it'll be swapped to. - if (Fixup.LUIdx == NumUses-1) - Fixup.LUIdx = LUIdx; - } - // Delete formulae from the new use which are no longer legal. bool Any = false; for (size_t i = 0, e = LUThatHas->Formulae.size(); i != e; ++i) { @@ -3089,6 +3019,20 @@ if (Any) LUThatHas->RecomputeRegs(LUThatHas - &Uses.front(), RegUses); + // Update the relocs to reference the new use. + for (SmallVectorImpl::iterator I = Fixups.begin(), + E = Fixups.end(); I != E; ++I) { + LSRFixup &Fixup = *I; + if (Fixup.LUIdx == LUIdx) { + Fixup.LUIdx = LUThatHas - &Uses.front(); + Fixup.Offset += F.AM.BaseOffs; + DEBUG(dbgs() << "New fixup has offset " + << Fixup.Offset << '\n'); + } + if (Fixup.LUIdx == NumUses-1) + Fixup.LUIdx = LUIdx; + } + // Delete the old use. DeleteUse(LU); --LUIdx; Modified: llvm/trunk/test/CodeGen/X86/lsr-reuse.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lsr-reuse.ll?rev=112692&r1=112691&r2=112692&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/lsr-reuse.ll (original) +++ llvm/trunk/test/CodeGen/X86/lsr-reuse.ll Tue Aug 31 20:45:53 2010 @@ -452,8 +452,8 @@ ; CHECK-NEXT: addss %xmm{{.*}}, %xmm{{.*}} ; CHECK-NEXT: mulss (%r{{[^,]*}}), %xmm{{.*}} ; CHECK-NEXT: movss %xmm{{.*}}, (%r{{[^,]*}}) -; CHECK-NEXT: decq %r{{.*}} ; CHECK-NEXT: addq $4, %r{{.*}} +; CHECK-NEXT: decq %r{{.*}} ; CHECK-NEXT: addq $4, %r{{.*}} ; CHECK-NEXT: movaps %xmm{{.*}}, %xmm{{.*}} ; CHECK-NEXT: BB10_2: From bruno.cardoso at gmail.com Wed Sep 1 00:08:25 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Wed, 01 Sep 2010 05:08:25 -0000 Subject: [llvm-commits] [llvm] r112694 - in /llvm/trunk/lib/Target/X86: X86ISelLowering.cpp X86ISelLowering.h X86InstrFragmentsSIMD.td X86InstrSSE.td Message-ID: <20100901050825.7DBC82A6C12C@llvm.org> Author: bruno Date: Wed Sep 1 00:08:25 2010 New Revision: 112694 URL: http://llvm.org/viewvc/llvm-project?rev=112694&view=rev Log: Use movlps, movlpd, movss and movsd specific nodes instead of pattern matching with movlp pattern fragment Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.h llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=112694&r1=112693&r2=112694&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Sep 1 00:08:25 2010 @@ -2593,7 +2593,10 @@ case X86ISD::SHUFPD: case X86ISD::SHUFPS: case X86ISD::MOVLHPS: + case X86ISD::MOVLHPD: case X86ISD::MOVHLPS: + case X86ISD::MOVLPS: + case X86ISD::MOVLPD: case X86ISD::MOVSHDUP: case X86ISD::MOVSLDUP: case X86ISD::MOVSS: @@ -2648,6 +2651,8 @@ case X86ISD::MOVLHPS: case X86ISD::MOVLHPD: case X86ISD::MOVHLPS: + case X86ISD::MOVLPS: + case X86ISD::MOVLPD: case X86ISD::MOVSS: case X86ISD::MOVSD: case X86ISD::PUNPCKLDQ: @@ -3664,7 +3669,6 @@ SDValue V = SDValue(N, 0); EVT VT = V.getValueType(); unsigned Opcode = V.getOpcode(); - int NumElems = VT.getVectorNumElements(); // Recurse into ISD::VECTOR_SHUFFLE node to find scalars. if (const ShuffleVectorSDNode *SV = dyn_cast(N)) { @@ -3673,6 +3677,7 @@ if (Index < 0) return DAG.getUNDEF(VT.getVectorElementType()); + int NumElems = VT.getVectorNumElements(); SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1); return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG); } @@ -3698,8 +3703,9 @@ if (Opcode == ISD::BIT_CONVERT) { V = V.getOperand(0); EVT SrcVT = V.getValueType(); + unsigned NumElems = VT.getVectorNumElements(); - if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != (unsigned)NumElems) + if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems) return SDValue(); } @@ -5061,6 +5067,67 @@ return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG); } +static +SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) { + SDValue V1 = Op.getOperand(0); + SDValue V2 = Op.getOperand(1); + EVT VT = Op.getValueType(); + unsigned NumElems = VT.getVectorNumElements(); + + // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second + // operand of these instructions is only memory, so check if there's a + // potencial load folding here, otherwise use SHUFPS or MOVSD to match the + // same masks. + bool CanFoldLoad = false; + SDValue TmpV1 = V1; + SDValue TmpV2 = V2; + + // Trivial case, when V2 is a load. + if (TmpV2.getOpcode() == ISD::BIT_CONVERT) + TmpV2 = TmpV2.getOperand(0); + if (TmpV2.getOpcode() == ISD::SCALAR_TO_VECTOR) + TmpV2 = TmpV2.getOperand(0); + if (MayFoldLoad(TmpV2)) + CanFoldLoad = true; + + // When V1 is a load, it can be folded later into a store in isel, example: + // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1) + // turns into: + // (MOVLPSmr addr:$src1, VR128:$src2) + // So, recognize this potential and also use MOVLPS or MOVLPD + if (TmpV1.getOpcode() == ISD::BIT_CONVERT) + TmpV1 = TmpV1.getOperand(0); + if (MayFoldLoad(TmpV1)) + CanFoldLoad = true; + + if (CanFoldLoad) { + if (HasSSE2 && NumElems == 2) + return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG); + + if (NumElems == 4) + return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG); + } + + ShuffleVectorSDNode *SVOp = cast(Op); + // movl and movlp will both match v2i64, but v2i64 is never matched by + // movl earlier because we make it strict to avoid messing with the movlp load + // folding logic (see the code above getMOVLP call). Match it here then, + // this is horrible, but will stay like this until we move all shuffle + // matching to x86 specific nodes. Note that for the 1st condition all + // types are matched with movsd. + if ((HasSSE2 && NumElems == 2) || !X86::isMOVLMask(SVOp)) + return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); + else if (HasSSE2) + return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); + + + assert(VT != MVT::v4i32 && "unsupported shuffle type"); + + // Invert the operand order and use SHUFPS to match it. + return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V2, V1, + X86::getShuffleSHUFImmediate(SVOp), DAG); +} + SDValue X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { ShuffleVectorSDNode *SVOp = cast(Op); @@ -5182,7 +5249,7 @@ return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG); if (X86::isMOVLPMask(SVOp)) - return Op; + return getMOVLP(Op, dl, DAG, HasSSE2); } if (ShouldXformToMOVHLPS(SVOp) || @@ -8433,6 +8500,8 @@ case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD"; case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS"; case X86ISD::MOVHLPD: return "X86ISD::MOVHLPD"; + case X86ISD::MOVLPS: return "X86ISD::MOVLPS"; + case X86ISD::MOVLPD: return "X86ISD::MOVLPD"; case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP"; case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP"; case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP"; Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=112694&r1=112693&r2=112694&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Wed Sep 1 00:08:25 2010 @@ -269,6 +269,8 @@ MOVLHPD, MOVHLPS, MOVHLPD, + MOVLPS, + MOVLPD, MOVSD, MOVSS, UNPCKLPS, Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=112694&r1=112693&r2=112694&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Wed Sep 1 00:08:25 2010 @@ -134,9 +134,6 @@ def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisInt<3>]>; -def SDTShuff2OpLd : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>, - SDTCisPtrTy<2>]>; - def SDTShuff2OpLdI : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisPtrTy<1>, SDTCisInt<2>]>; @@ -161,14 +158,11 @@ def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>; def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>; - def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>; def X86Movhlpd : SDNode<"X86ISD::MOVHLPD", SDTShuff2Op>; -def X86MovlpsLd : SDNode<"X86ISD::MOVLPS", SDTShuff2OpLd, - [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; -def X86MovlpdLd : SDNode<"X86ISD::MOVLPD", SDTShuff2OpLd, - [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; +def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>; +def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>; def X86Unpcklps : SDNode<"X86ISD::UNPCKLPS", SDTShuff2Op>; def X86Unpcklpd : SDNode<"X86ISD::UNPCKLPD", SDTShuff2Op>; Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=112694&r1=112693&r2=112694&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Sep 1 00:08:25 2010 @@ -5840,9 +5840,9 @@ (MOVSDrr (v2f64 VR128:$src1), (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>; def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)), - (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>; + (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_sd))>; def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)), - (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>; + (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_sd))>; // Shuffle with MOVSHDUP def : Pat<(v4i32 (X86Movshdup VR128:$src)), @@ -5901,7 +5901,25 @@ def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))), (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>; -// Extra patterns to match stores +// Shuffle with MOVLPS +def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))), + (MOVLPSrm VR128:$src1, addr:$src2)>; +def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))), + (MOVLPSrm VR128:$src1, addr:$src2)>; +def : Pat<(X86Movlps VR128:$src1, + (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))), + (MOVLPSrm VR128:$src1, addr:$src2)>; + +// Shuffle with MOVLPD +def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))), + (MOVLPDrm VR128:$src1, addr:$src2)>; +def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))), + (MOVLPDrm VR128:$src1, addr:$src2)>; +def : Pat<(v2f64 (X86Movlpd VR128:$src1, + (scalar_to_vector (loadf64 addr:$src2)))), + (MOVLPDrm VR128:$src1, addr:$src2)>; + +// Extra patterns to match stores with MOVHPS/PD and MOVLPS/PD def : Pat<(store (f64 (vector_extract (v2f64 (X86Unpckhps VR128:$src, (undef))), (iPTR 0))),addr:$dst), (MOVHPSmr addr:$dst, VR128:$src)>; @@ -5909,3 +5927,13 @@ (v2f64 (X86Unpckhpd VR128:$src, (undef))), (iPTR 0))),addr:$dst), (MOVHPDmr addr:$dst, VR128:$src)>; +def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),addr:$src1), + (MOVLPSmr addr:$src1, VR128:$src2)>; +def : Pat<(store (v4i32 (X86Movlps + (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1), + (MOVLPSmr addr:$src1, VR128:$src2)>; + +def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),addr:$src1), + (MOVLPDmr addr:$src1, VR128:$src2)>; +def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),addr:$src1), + (MOVLPDmr addr:$src1, VR128:$src2)>; From sabre at nondot.org Wed Sep 1 00:10:14 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 01 Sep 2010 05:10:14 -0000 Subject: [llvm-commits] [llvm] r112695 - /llvm/trunk/test/Transforms/ScalarRepl/vector_promote.ll Message-ID: <20100901051014.718102A6C12C@llvm.org> Author: lattner Date: Wed Sep 1 00:10:14 2010 New Revision: 112695 URL: http://llvm.org/viewvc/llvm-project?rev=112695&view=rev Log: filecheckize Modified: llvm/trunk/test/Transforms/ScalarRepl/vector_promote.ll Modified: llvm/trunk/test/Transforms/ScalarRepl/vector_promote.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ScalarRepl/vector_promote.ll?rev=112695&r1=112694&r2=112695&view=diff ============================================================================== --- llvm/trunk/test/Transforms/ScalarRepl/vector_promote.ll (original) +++ llvm/trunk/test/Transforms/ScalarRepl/vector_promote.ll Wed Sep 1 00:10:14 2010 @@ -1,8 +1,7 @@ -; RUN: opt < %s -scalarrepl -S | not grep alloca -; RUN: opt < %s -scalarrepl -S | grep {load <4 x float>} +; RUN: opt < %s -scalarrepl -S | FileCheck %s target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -define void @test(<4 x float>* %F, float %f) { +define void @test1(<4 x float>* %F, float %f) { entry: %G = alloca <4 x float>, align 16 ; <<4 x float>*> [#uses=3] %tmp = load <4 x float>* %F ; <<4 x float>> [#uses=2] @@ -14,6 +13,11 @@ %tmp6 = fadd <4 x float> %tmp4, %tmp4 ; <<4 x float>> [#uses=1] store <4 x float> %tmp6, <4 x float>* %F ret void +; CHECK: @test1 +; CHECK-NOT: alloca +; CHECK: %tmp = load <4 x float>* %F +; CHECK: fadd <4 x float> %tmp, %tmp +; CHECK-NEXT: insertelement <4 x float> %tmp3, float %f, i32 0 } define void @test2(<4 x float>* %F, float %f) { @@ -28,6 +32,11 @@ %tmp6 = fadd <4 x float> %tmp4, %tmp4 ; <<4 x float>> [#uses=1] store <4 x float> %tmp6, <4 x float>* %F ret void +; CHECK: @test2 +; CHECK-NOT: alloca +; CHECK: %tmp = load <4 x float>* %F +; CHECK: fadd <4 x float> %tmp, %tmp +; CHECK-NEXT: insertelement <4 x float> %tmp3, float %f, i32 2 } define void @test3(<4 x float>* %F, float* %f) { @@ -40,6 +49,11 @@ %tmp.upgrd.4 = load float* %tmp.upgrd.3 ; [#uses=1] store float %tmp.upgrd.4, float* %f ret void +; CHECK: @test3 +; CHECK-NOT: alloca +; CHECK: %tmp = load <4 x float>* %F +; CHECK: fadd <4 x float> %tmp, %tmp +; CHECK-NEXT: extractelement <4 x float> %tmp3, i32 2 } define void @test4(<4 x float>* %F, float* %f) { @@ -52,6 +66,11 @@ %tmp.upgrd.6 = load float* %G.upgrd.5 ; [#uses=1] store float %tmp.upgrd.6, float* %f ret void +; CHECK: @test4 +; CHECK-NOT: alloca +; CHECK: %tmp = load <4 x float>* %F +; CHECK: fadd <4 x float> %tmp, %tmp +; CHECK-NEXT: extractelement <4 x float> %tmp3, i32 0 } define i32 @test5(float %X) { ;; should turn into bitcast. @@ -61,5 +80,8 @@ %a = bitcast float* %X1 to i32* %tmp = load i32* %a ret i32 %tmp +; CHECK: @test5 +; CHECK-NEXT: bitcast float %X to i32 +; CHECK-NEXT: ret i32 } From sabre at nondot.org Wed Sep 1 00:14:33 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 01 Sep 2010 05:14:33 -0000 Subject: [llvm-commits] [llvm] r112696 - in /llvm/trunk: lib/Transforms/Scalar/ScalarReplAggregates.cpp test/Transforms/ScalarRepl/vector_promote.ll Message-ID: <20100901051433.DD3B62A6C12C@llvm.org> Author: lattner Date: Wed Sep 1 00:14:33 2010 New Revision: 112696 URL: http://llvm.org/viewvc/llvm-project?rev=112696&view=rev Log: add a gross hack to work around a problem that Argiris reported on llvmdev: SRoA is introducing MMX datatypes like <1 x i64>, which then cause random problems because the X86 backend is producing mmx stuff without inserting proper emms calls. In the short term, force off MMX datatypes. In the long term, the X86 backend should not select generic vector types to MMX registers. This is being worked on, but won't be done in time for 2.8. rdar://8380055 Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp llvm/trunk/test/Transforms/ScalarRepl/vector_promote.ll Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=112696&r1=112695&r2=112696&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Wed Sep 1 00:14:33 2010 @@ -193,6 +193,22 @@ }; } // end anonymous namespace. + +/// IsVerbotenVectorType - Return true if this is a vector type ScalarRepl isn't +/// allowed to form. We do this to avoid MMX types, which is a complete hack, +/// but is required until the backend is fixed. +static bool IsVerbotenVectorType(const VectorType *VTy) { + // Reject all the MMX vector types. + switch (VTy->getNumElements()) { + default: return false; + case 1: return VTy->getElementType()->isIntegerTy(64); + case 2: return VTy->getElementType()->isIntegerTy(32); + case 4: return VTy->getElementType()->isIntegerTy(16); + case 8: return VTy->getElementType()->isIntegerTy(8); + } +} + + /// TryConvert - Analyze the specified alloca, and if it is safe to do so, /// rewrite it to be a new alloca which is mem2reg'able. This returns the new /// alloca if possible or null if not. @@ -209,7 +225,8 @@ // we just get a lot of insert/extracts. If at least one vector is // involved, then we probably really do have a union of vector/array. const Type *NewTy; - if (VectorTy && VectorTy->isVectorTy() && HadAVector) { + if (VectorTy && VectorTy->isVectorTy() && HadAVector && + !IsVerbotenVectorType(cast(VectorTy))) { DEBUG(dbgs() << "CONVERT TO VECTOR: " << *AI << "\n TYPE = " << *VectorTy << '\n'); NewTy = VectorTy; // Use the vector type. @@ -1662,6 +1679,12 @@ /// HasPadding - Return true if the specified type has any structure or /// alignment padding, false otherwise. static bool HasPadding(const Type *Ty, const TargetData &TD) { + if (const ArrayType *ATy = dyn_cast(Ty)) + return HasPadding(ATy->getElementType(), TD); + + if (const VectorType *VTy = dyn_cast(Ty)) + return HasPadding(VTy->getElementType(), TD); + if (const StructType *STy = dyn_cast(Ty)) { const StructLayout *SL = TD.getStructLayout(STy); unsigned PrevFieldBitOffset = 0; @@ -1691,12 +1714,8 @@ if (PrevFieldEnd < SL->getSizeInBits()) return true; } - - } else if (const ArrayType *ATy = dyn_cast(Ty)) { - return HasPadding(ATy->getElementType(), TD); - } else if (const VectorType *VTy = dyn_cast(Ty)) { - return HasPadding(VTy->getElementType(), TD); } + return TD.getTypeSizeInBits(Ty) != TD.getTypeAllocSizeInBits(Ty); } Modified: llvm/trunk/test/Transforms/ScalarRepl/vector_promote.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ScalarRepl/vector_promote.ll?rev=112696&r1=112695&r2=112696&view=diff ============================================================================== --- llvm/trunk/test/Transforms/ScalarRepl/vector_promote.ll (original) +++ llvm/trunk/test/Transforms/ScalarRepl/vector_promote.ll Wed Sep 1 00:14:33 2010 @@ -85,3 +85,17 @@ ; CHECK-NEXT: ret i32 } + +;; should not turn into <1 x i64> - It is a banned MMX datatype. +;; rdar://8380055 +define i64 @test6(<2 x float> %X) { + %X_addr = alloca <2 x float> + store <2 x float> %X, <2 x float>* %X_addr + %P = bitcast <2 x float>* %X_addr to i64* + %tmp = load i64* %P + ret i64 %tmp +; CHECK: @test6 +; CHECK-NEXT: bitcast <2 x float> %X to i64 +; CHECK-NEXT: ret i64 +} + From dalej at apple.com Wed Sep 1 00:19:06 2010 From: dalej at apple.com (Dale Johannesen) Date: Wed, 01 Sep 2010 05:19:06 -0000 Subject: [llvm-commits] [llvm] r112697 - /llvm/trunk/test/FrontendC/asm-reg-var-local.c Message-ID: <20100901051906.9FE5C2A6C12C@llvm.org> Author: johannes Date: Wed Sep 1 00:19:06 2010 New Revision: 112697 URL: http://llvm.org/viewvc/llvm-project?rev=112697&view=rev Log: Attempt to fix buildbot. Modified: llvm/trunk/test/FrontendC/asm-reg-var-local.c Modified: llvm/trunk/test/FrontendC/asm-reg-var-local.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/asm-reg-var-local.c?rev=112697&r1=112696&r2=112697&view=diff ============================================================================== --- llvm/trunk/test/FrontendC/asm-reg-var-local.c (original) +++ llvm/trunk/test/FrontendC/asm-reg-var-local.c Wed Sep 1 00:19:06 2010 @@ -1,7 +1,7 @@ // RUN: %llvmgcc %s -m64 -S -o - | FileCheck %s // Exercise various use cases for local asm "register variables". // XFAIL: * -// XTARGET: x86_64 +// XTARGET: x86_64,i686,i386 int foo() { // CHECK: %a = alloca i32 From baldrick at free.fr Wed Sep 1 04:26:00 2010 From: baldrick at free.fr (Duncan Sands) Date: Wed, 01 Sep 2010 09:26:00 -0000 Subject: [llvm-commits] [llvm] r112698 - /llvm/trunk/include/llvm/IntrinsicInst.h Message-ID: <20100901092600.4AF012A6C12C@llvm.org> Author: baldrick Date: Wed Sep 1 04:26:00 2010 New Revision: 112698 URL: http://llvm.org/viewvc/llvm-project?rev=112698&view=rev Log: Add convenience class for working with eh.exception calls. Modified: llvm/trunk/include/llvm/IntrinsicInst.h Modified: llvm/trunk/include/llvm/IntrinsicInst.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicInst.h?rev=112698&r1=112697&r2=112698&view=diff ============================================================================== --- llvm/trunk/include/llvm/IntrinsicInst.h (original) +++ llvm/trunk/include/llvm/IntrinsicInst.h Wed Sep 1 04:26:00 2010 @@ -269,6 +269,20 @@ } }; + /// EHExceptionInst - This represents the llvm.eh.exception instruction. + /// + class EHExceptionInst : public IntrinsicInst { + public: + // Methods for support type inquiry through isa, cast, and dyn_cast: + static inline bool classof(const EHExceptionInst *) { return true; } + static inline bool classof(const IntrinsicInst *I) { + return I->getIntrinsicID() == Intrinsic::eh_exception; + } + static inline bool classof(const Value *V) { + return isa(V) && classof(cast(V)); + } + }; + /// EHSelectorInst - This represents the llvm.eh.selector instruction. /// class EHSelectorInst : public IntrinsicInst { From geek4civic at gmail.com Wed Sep 1 04:44:49 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Wed, 1 Sep 2010 18:44:49 +0900 Subject: [llvm-commits] [www] r112658 - in /www/trunk: devmtg/index.html header.incl index.html In-Reply-To: <20100831222214.16D332A6C12D@llvm.org> References: <20100831222214.16D332A6C12D@llvm.org> Message-ID: Tanya, > +

      November 4, 2010

      Is the canonical host "llvm.org", not www.llvm.org? ...Takumi From baldrick at free.fr Wed Sep 1 05:29:33 2010 From: baldrick at free.fr (Duncan Sands) Date: Wed, 01 Sep 2010 10:29:33 -0000 Subject: [llvm-commits] [llvm] r112699 - in /llvm/trunk: include/llvm/Transforms/Utils/SSAUpdater.h lib/Transforms/Scalar/GVN.cpp lib/Transforms/Scalar/JumpThreading.cpp lib/Transforms/Scalar/LICM.cpp lib/Transforms/Scalar/LoopRotation.cpp lib/Transforms/Utils/LCSSA.cpp lib/Transforms/Utils/SSAUpdater.cpp Message-ID: <20100901102933.CE8872A6C12C@llvm.org> Author: baldrick Date: Wed Sep 1 05:29:33 2010 New Revision: 112699 URL: http://llvm.org/viewvc/llvm-project?rev=112699&view=rev Log: If PrototypeValue is erased in the middle of using the SSAUpdator then the SSAUpdator may access freed memory. Instead, simply pass in the type and name explicitly, which is all that was used anyway. Modified: llvm/trunk/include/llvm/Transforms/Utils/SSAUpdater.h llvm/trunk/lib/Transforms/Scalar/GVN.cpp llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp llvm/trunk/lib/Transforms/Scalar/LICM.cpp llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp llvm/trunk/lib/Transforms/Utils/LCSSA.cpp llvm/trunk/lib/Transforms/Utils/SSAUpdater.cpp Modified: llvm/trunk/include/llvm/Transforms/Utils/SSAUpdater.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/Utils/SSAUpdater.h?rev=112699&r1=112698&r2=112699&view=diff ============================================================================== --- llvm/trunk/include/llvm/Transforms/Utils/SSAUpdater.h (original) +++ llvm/trunk/include/llvm/Transforms/Utils/SSAUpdater.h Wed Sep 1 05:29:33 2010 @@ -36,9 +36,11 @@ //typedef DenseMap AvailableValsTy; void *AV; - /// PrototypeValue is an arbitrary representative value, which we derive names - /// and a type for PHI nodes. - Value *PrototypeValue; + /// ProtoType holds the type of the values being rewritten. + const Type *ProtoType; + + // PHI nodes are given a name based on ProtoName. + std::string ProtoName; /// InsertedPHIs - If this is non-null, the SSAUpdater adds all PHI nodes that /// it creates to the vector. @@ -51,8 +53,8 @@ ~SSAUpdater(); /// Initialize - Reset this object to get ready for a new set of SSA - /// updates. ProtoValue is the value used to name PHI nodes. - void Initialize(Value *ProtoValue); + /// updates with type 'Ty'. PHI nodes get a name based on 'Name'. + void Initialize(const Type *Ty, StringRef Name); /// AddAvailableValue - Indicate that a rewritten value is available at the /// end of the specified block with the specified value. Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=112699&r1=112698&r2=112699&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Wed Sep 1 05:29:33 2010 @@ -1310,7 +1310,7 @@ // Otherwise, we have to construct SSA form. SmallVector NewPHIs; SSAUpdater SSAUpdate(&NewPHIs); - SSAUpdate.Initialize(LI); + SSAUpdate.Initialize(LI->getType(), LI->getName()); const Type *LoadTy = LI->getType(); Modified: llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp?rev=112699&r1=112698&r2=112699&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Wed Sep 1 05:29:33 2010 @@ -1526,7 +1526,7 @@ // We found a use of I outside of BB. Rename all uses of I that are outside // its block to be uses of the appropriate PHI node etc. See ValuesInBlocks // with the two values we know. - SSAUpdate.Initialize(I); + SSAUpdate.Initialize(I->getType(), I->getName()); SSAUpdate.AddAvailableValue(BB, I); SSAUpdate.AddAvailableValue(NewBB, ValueMapping[I]); @@ -1681,7 +1681,7 @@ // We found a use of I outside of BB. Rename all uses of I that are outside // its block to be uses of the appropriate PHI node etc. See ValuesInBlocks // with the two values we know. - SSAUpdate.Initialize(I); + SSAUpdate.Initialize(I->getType(), I->getName()); SSAUpdate.AddAvailableValue(BB, I); SSAUpdate.AddAvailableValue(PredBB, ValueMapping[I]); Modified: llvm/trunk/lib/Transforms/Scalar/LICM.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LICM.cpp?rev=112699&r1=112698&r2=112699&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LICM.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LICM.cpp Wed Sep 1 05:29:33 2010 @@ -526,7 +526,7 @@ SSAUpdater SSA(&NewPHIs); if (!I.use_empty()) - SSA.Initialize(&I); + SSA.Initialize(I.getType(), I.getName()); // Insert a copy of the instruction in each exit block of the loop that is // dominated by the instruction. Each exit block is known to only be in the @@ -728,7 +728,7 @@ SomeValue = LoopUses[0]; else SomeValue = cast(LoopUses[0])->getOperand(0); - SSA.Initialize(SomeValue); + SSA.Initialize(SomeValue->getType(), SomeValue->getName()); // First step: bucket up uses of the pointers by the block they occur in. // This is important because we have to handle multiple defs/uses in a block Modified: llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp?rev=112699&r1=112698&r2=112699&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp Wed Sep 1 05:29:33 2010 @@ -221,7 +221,7 @@ // The value now exits in two versions: the initial value in the preheader // and the loop "next" value in the original header. - SSA.Initialize(OrigHeaderVal); + SSA.Initialize(OrigHeaderVal->getType(), OrigHeaderVal->getName()); SSA.AddAvailableValue(OrigHeader, OrigHeaderVal); SSA.AddAvailableValue(OrigPreHeader, OrigPreHeaderVal); Modified: llvm/trunk/lib/Transforms/Utils/LCSSA.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/LCSSA.cpp?rev=112699&r1=112698&r2=112699&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/LCSSA.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/LCSSA.cpp Wed Sep 1 05:29:33 2010 @@ -206,7 +206,7 @@ DomTreeNode *DomNode = DT->getNode(DomBB); SSAUpdater SSAUpdate; - SSAUpdate.Initialize(Inst); + SSAUpdate.Initialize(Inst->getType(), Inst->getName()); // Insert the LCSSA phi's into all of the exit blocks dominated by the // value, and add them to the Phi's map. Modified: llvm/trunk/lib/Transforms/Utils/SSAUpdater.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SSAUpdater.cpp?rev=112699&r1=112698&r2=112699&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SSAUpdater.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SSAUpdater.cpp Wed Sep 1 05:29:33 2010 @@ -29,20 +29,21 @@ } SSAUpdater::SSAUpdater(SmallVectorImpl *NewPHI) - : AV(0), PrototypeValue(0), InsertedPHIs(NewPHI) {} + : AV(0), ProtoType(0), ProtoName(), InsertedPHIs(NewPHI) {} SSAUpdater::~SSAUpdater() { delete &getAvailableVals(AV); } /// Initialize - Reset this object to get ready for a new set of SSA -/// updates. ProtoValue is the value used to name PHI nodes. -void SSAUpdater::Initialize(Value *ProtoValue) { +/// updates with type 'Ty'. PHI nodes get a name based on 'Name'. +void SSAUpdater::Initialize(const Type *Ty, StringRef Name) { if (AV == 0) AV = new AvailableValsTy(); else getAvailableVals(AV).clear(); - PrototypeValue = ProtoValue; + ProtoType = Ty; + ProtoName = Name; } /// HasValueForBlock - Return true if the SSAUpdater already has a value for @@ -54,8 +55,8 @@ /// AddAvailableValue - Indicate that a rewritten value is available in the /// specified block with the specified value. void SSAUpdater::AddAvailableValue(BasicBlock *BB, Value *V) { - assert(PrototypeValue != 0 && "Need to initialize SSAUpdater"); - assert(PrototypeValue->getType() == V->getType() && + assert(ProtoType != 0 && "Need to initialize SSAUpdater"); + assert(ProtoType == V->getType() && "All rewritten values must have the same type"); getAvailableVals(AV)[BB] = V; } @@ -148,7 +149,7 @@ // If there are no predecessors, just return undef. if (PredValues.empty()) - return UndefValue::get(PrototypeValue->getType()); + return UndefValue::get(ProtoType); // Otherwise, if all the merged values are the same, just use it. if (SingularValue != 0) @@ -168,9 +169,7 @@ } // Ok, we have no way out, insert a new one now. - PHINode *InsertedPHI = PHINode::Create(PrototypeValue->getType(), - PrototypeValue->getName(), - &BB->front()); + PHINode *InsertedPHI = PHINode::Create(ProtoType, ProtoName, &BB->front()); InsertedPHI->reserveOperandSpace(PredValues.size()); // Fill in all the predecessors of the PHI. @@ -282,15 +281,14 @@ /// GetUndefVal - Get an undefined value of the same type as the value /// being handled. static Value *GetUndefVal(BasicBlock *BB, SSAUpdater *Updater) { - return UndefValue::get(Updater->PrototypeValue->getType()); + return UndefValue::get(Updater->ProtoType); } /// CreateEmptyPHI - Create a new PHI instruction in the specified block. /// Reserve space for the operands but do not fill them in yet. static Value *CreateEmptyPHI(BasicBlock *BB, unsigned NumPreds, SSAUpdater *Updater) { - PHINode *PHI = PHINode::Create(Updater->PrototypeValue->getType(), - Updater->PrototypeValue->getName(), + PHINode *PHI = PHINode::Create(Updater->ProtoType, Updater->ProtoName, &BB->front()); PHI->reserveOperandSpace(NumPreds); return PHI; From baldrick at free.fr Wed Sep 1 08:07:11 2010 From: baldrick at free.fr (Duncan Sands) Date: Wed, 01 Sep 2010 13:07:11 -0000 Subject: [llvm-commits] [llvm] r112700 - /llvm/trunk/include/llvm/Support/Compiler.h Message-ID: <20100901130711.309B92A6C12C@llvm.org> Author: baldrick Date: Wed Sep 1 08:07:11 2010 New Revision: 112700 URL: http://llvm.org/viewvc/llvm-project?rev=112700&view=rev Log: Define LLVM_GLOBAL_VISIBILITY to be __declspec(dllexport) on windows systems. Modified: llvm/trunk/include/llvm/Support/Compiler.h Modified: llvm/trunk/include/llvm/Support/Compiler.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/Compiler.h?rev=112700&r1=112699&r2=112700&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/Compiler.h (original) +++ llvm/trunk/include/llvm/Support/Compiler.h Wed Sep 1 08:07:11 2010 @@ -24,7 +24,10 @@ /// into a shared library, then the class will be accessible from outside the /// the library. Can also be used to mark variables and functions, making them /// accessible from outside any shared library they are linked into. -#if (__GNUC__ >= 4) && !defined(__MINGW32__) && !defined(__CYGWIN__) +#if defined(__MINGW32__) || defined(__CYGWIN__) +#define LLVM_LIBRARY_VISIBILITY +#define LLVM_GLOBAL_VISIBILITY __declspec(dllexport) +#elif (__GNUC__ >= 4) #define LLVM_LIBRARY_VISIBILITY __attribute__ ((visibility("hidden"))) #define LLVM_GLOBAL_VISIBILITY __attribute__ ((visibility("default"))) #else From gohman at apple.com Wed Sep 1 09:00:35 2010 From: gohman at apple.com (Dan Gohman) Date: Wed, 01 Sep 2010 14:00:35 -0000 Subject: [llvm-commits] [llvm] r112701 - in /llvm/trunk/include/llvm/ADT: DenseMap.h DenseSet.h ValueMap.h Message-ID: <20100901140035.651522A6C12D@llvm.org> Author: djg Date: Wed Sep 1 09:00:35 2010 New Revision: 112701 URL: http://llvm.org/viewvc/llvm-project?rev=112701&view=rev Log: Make the iterator form of erase return void, since it always succeeds, and since this is what std::map and std::set do. Modified: llvm/trunk/include/llvm/ADT/DenseMap.h llvm/trunk/include/llvm/ADT/DenseSet.h llvm/trunk/include/llvm/ADT/ValueMap.h Modified: llvm/trunk/include/llvm/ADT/DenseMap.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/DenseMap.h?rev=112701&r1=112700&r2=112701&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/DenseMap.h (original) +++ llvm/trunk/include/llvm/ADT/DenseMap.h Wed Sep 1 09:00:35 2010 @@ -185,13 +185,12 @@ ++NumTombstones; return true; } - bool erase(iterator I) { + void erase(iterator I) { BucketT *TheBucket = &*I; TheBucket->second.~ValueT(); TheBucket->first = getTombstoneKey(); --NumEntries; ++NumTombstones; - return true; } void swap(DenseMap& RHS) { Modified: llvm/trunk/include/llvm/ADT/DenseSet.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/DenseSet.h?rev=112701&r1=112700&r2=112701&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/DenseSet.h (original) +++ llvm/trunk/include/llvm/ADT/DenseSet.h Wed Sep 1 09:00:35 2010 @@ -106,8 +106,8 @@ const_iterator end() const { return ConstIterator(TheMap.end()); } iterator find(const ValueT &V) { return Iterator(TheMap.find(V)); } - bool erase(Iterator I) { return TheMap.erase(I.I); } - bool erase(ConstIterator CI) { return TheMap.erase(CI.I); } + void erase(Iterator I) { return TheMap.erase(I.I); } + void erase(ConstIterator CI) { return TheMap.erase(CI.I); } std::pair insert(const ValueT &V) { return TheMap.insert(std::make_pair(V, 0)); Modified: llvm/trunk/include/llvm/ADT/ValueMap.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/ValueMap.h?rev=112701&r1=112700&r2=112701&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/ValueMap.h (original) +++ llvm/trunk/include/llvm/ADT/ValueMap.h Wed Sep 1 09:00:35 2010 @@ -149,7 +149,7 @@ bool erase(const KeyT &Val) { return Map.erase(Wrap(Val)); } - bool erase(iterator I) { + void erase(iterator I) { return Map.erase(I.base()); } From baldrick at free.fr Wed Sep 1 09:07:47 2010 From: baldrick at free.fr (Duncan Sands) Date: Wed, 01 Sep 2010 14:07:47 -0000 Subject: [llvm-commits] [llvm] r112702 - /llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp Message-ID: <20100901140747.44F3A2A6C12C@llvm.org> Author: baldrick Date: Wed Sep 1 09:07:47 2010 New Revision: 112702 URL: http://llvm.org/viewvc/llvm-project?rev=112702&view=rev Log: Use the SSAUpdator to turn calls to eh.exception that are not in a landing pad into uses of registers rather than loads from a stack slot. Doesn't touch the 'orrible hack code - Bill needs to persuade me harder :) Modified: llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp Modified: llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp?rev=112702&r1=112701&r2=112702&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp (original) +++ llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp Wed Sep 1 09:07:47 2010 @@ -25,12 +25,12 @@ #include "llvm/Support/CallSite.h" #include "llvm/Target/TargetLowering.h" #include "llvm/Transforms/Utils/BasicBlockUtils.h" +#include "llvm/Transforms/Utils/SSAUpdater.h" using namespace llvm; STATISTIC(NumLandingPadsSplit, "Number of landing pads split"); STATISTIC(NumUnwindsLowered, "Number of unwind instructions lowered"); STATISTIC(NumExceptionValuesMoved, "Number of eh.exception calls moved"); -STATISTIC(NumStackTempsIntroduced, "Number of stack temporaries introduced"); namespace { class DwarfEHPrepare : public FunctionPass { @@ -62,24 +62,11 @@ typedef SmallPtrSet BBSet; BBSet LandingPads; - // Stack temporary used to hold eh.exception values. - AllocaInst *ExceptionValueVar; - bool NormalizeLandingPads(); bool LowerUnwinds(); bool MoveExceptionValueCalls(); - bool FinishStackTemporaries(); Instruction *CreateExceptionValueCall(BasicBlock *BB); - Instruction *CreateValueLoad(BasicBlock *BB); - - /// CreateReadOfExceptionValue - Return the result of the eh.exception - /// intrinsic by calling the intrinsic if in a landing pad, or loading it - /// from the exception value variable otherwise. - Instruction *CreateReadOfExceptionValue(BasicBlock *BB) { - return LandingPads.count(BB) ? - CreateExceptionValueCall(BB) : CreateValueLoad(BB); - } /// CleanupSelectors - Any remaining eh.selector intrinsic calls which still /// use the "llvm.eh.catch.all.value" call need to convert to using its @@ -117,7 +104,7 @@ virtual bool runOnFunction(Function &Fn); - // getAnalysisUsage - We need dominance frontiers for memory promotion. + // getAnalysisUsage - We need the dominator tree for handling URoR. virtual void getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired(); AU.addPreserved(); @@ -517,7 +504,7 @@ // Create the call... CallInst *CI = CallInst::Create(RewindFunction, - CreateReadOfExceptionValue(TI->getParent()), + CreateExceptionValueCall(TI->getParent()), "", TI); CI->setCallingConv(TLI->getLibcallCallingConv(RTLIB::UNWIND_RESUME)); // ...followed by an UnreachableInst. @@ -533,9 +520,11 @@ } /// MoveExceptionValueCalls - Ensure that eh.exception is only ever called from -/// landing pads by replacing calls outside of landing pads with loads from a -/// stack temporary. Move eh.exception calls inside landing pads to the start -/// of the landing pad (optional, but may make things simpler for later passes). +/// landing pads by replacing calls outside of landing pads with direct use of +/// a register holding the appropriate value; this requires adding calls inside +/// all landing pads to initialize the register. Also, move eh.exception calls +/// inside landing pads to the start of the landing pad (optional, but may make +/// things simpler for later passes). bool DwarfEHPrepare::MoveExceptionValueCalls() { // If the eh.exception intrinsic is not declared in the module then there is // nothing to do. Speed up compilation by checking for this common case. @@ -545,49 +534,87 @@ bool Changed = false; - for (Function::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) { - for (BasicBlock::iterator II = BB->begin(), E = BB->end(); II != E;) - if (IntrinsicInst *CI = dyn_cast(II++)) - if (CI->getIntrinsicID() == Intrinsic::eh_exception) { - if (!CI->use_empty()) { - Value *ExceptionValue = CreateReadOfExceptionValue(BB); - if (CI == ExceptionValue) { - // The call was at the start of a landing pad - leave it alone. - assert(LandingPads.count(BB) && - "Created eh.exception call outside landing pad!"); - continue; - } - CI->replaceAllUsesWith(ExceptionValue); - } - CI->eraseFromParent(); - ++NumExceptionValuesMoved; - Changed = true; + // Move calls to eh.exception that are inside a landing pad to the start of + // the landing pad. + for (BBSet::const_iterator LI = LandingPads.begin(), LE = LandingPads.end(); + LI != LE; ++LI) { + BasicBlock *LP = *LI; + for (BasicBlock::iterator II = LP->getFirstNonPHIOrDbg(), IE = LP->end(); + II != IE;) + if (EHExceptionInst *EI = dyn_cast(II++)) { + // Found a call to eh.exception. + if (!EI->use_empty()) { + // If there is already a call to eh.exception at the start of the + // landing pad, then get hold of it; otherwise create such a call. + Value *CallAtStart = CreateExceptionValueCall(LP); + + // If the call was at the start of a landing pad then leave it alone. + if (EI == CallAtStart) + continue; + EI->replaceAllUsesWith(CallAtStart); } + EI->eraseFromParent(); + ++NumExceptionValuesMoved; + Changed = true; + } } - return Changed; -} + // Look for calls to eh.exception that are not in a landing pad. If one is + // found, then a register that holds the exception value will be created in + // each landing pad, and the SSAUpdater will be used to compute the values + // returned by eh.exception calls outside of landing pads. + SSAUpdater SSA; + + // Remember where we found the eh.exception call, to avoid rescanning earlier + // basic blocks which we already know contain no eh.exception calls. + bool FoundCallOutsideLandingPad = false; + Function::iterator BB = F->begin(); + for (Function::iterator BE = F->end(); BB != BE; ++BB) { + // Skip over landing pads. + if (LandingPads.count(BB)) + continue; -/// FinishStackTemporaries - If we introduced a stack variable to hold the -/// exception value then initialize it in each landing pad. -bool DwarfEHPrepare::FinishStackTemporaries() { - if (!ExceptionValueVar) - // Nothing to do. - return false; + for (BasicBlock::iterator II = BB->getFirstNonPHIOrDbg(), IE = BB->end(); + II != IE; ++II) + if (isa(II)) { + SSA.Initialize(II->getType(), II->getName()); + FoundCallOutsideLandingPad = true; + break; + } - bool Changed = false; + if (FoundCallOutsideLandingPad) + break; + } + + // If all calls to eh.exception are in landing pads then we are done. + if (!FoundCallOutsideLandingPad) + return Changed; - // Make sure that there is a store of the exception value at the start of - // each landing pad. + // Add a call to eh.exception at the start of each landing pad, and tell the + // SSAUpdater that this is the value produced by the landing pad. for (BBSet::iterator LI = LandingPads.begin(), LE = LandingPads.end(); - LI != LE; ++LI) { - Instruction *ExceptionValue = CreateReadOfExceptionValue(*LI); - Instruction *Store = new StoreInst(ExceptionValue, ExceptionValueVar); - Store->insertAfter(ExceptionValue); - Changed = true; + LI != LE; ++LI) + SSA.AddAvailableValue(*LI, CreateExceptionValueCall(*LI)); + + // Now turn all calls to eh.exception that are not in a landing pad into a use + // of the appropriate register. + for (Function::iterator BE = F->end(); BB != BE; ++BB) { + // Skip over landing pads. + if (LandingPads.count(BB)) + continue; + + for (BasicBlock::iterator II = BB->getFirstNonPHIOrDbg(), IE = BB->end(); + II != IE;) + if (EHExceptionInst *EI = dyn_cast(II++)) { + // Found a call to eh.exception, replace it with the value from any + // upstream landing pad(s). + EI->replaceAllUsesWith(SSA.GetValueAtEndOfBlock(BB)); + EI->eraseFromParent(); + ++NumExceptionValuesMoved; + } } - return Changed; + return true; } /// CreateExceptionValueCall - Insert a call to the eh.exception intrinsic at @@ -610,35 +637,11 @@ return CallInst::Create(ExceptionValueIntrinsic, "eh.value.call", Start); } -/// CreateValueLoad - Insert a load of the exception value stack variable -/// (creating it if necessary) at the start of the basic block (unless -/// there already is a load, in which case the existing load is returned). -Instruction *DwarfEHPrepare::CreateValueLoad(BasicBlock *BB) { - Instruction *Start = BB->getFirstNonPHIOrDbg(); - // Is this a load of the exception temporary? - if (ExceptionValueVar) - if (LoadInst* LI = dyn_cast(Start)) - if (LI->getPointerOperand() == ExceptionValueVar) - // Reuse the existing load. - return Start; - - // Create the temporary if we didn't already. - if (!ExceptionValueVar) { - ExceptionValueVar = new AllocaInst(PointerType::getUnqual( - Type::getInt8Ty(BB->getContext())), "eh.value", F->begin()->begin()); - ++NumStackTempsIntroduced; - } - - // Load the value. - return new LoadInst(ExceptionValueVar, "eh.value.load", Start); -} - bool DwarfEHPrepare::runOnFunction(Function &Fn) { bool Changed = false; // Initialize internal state. DT = &getAnalysis(); - ExceptionValueVar = 0; F = &Fn; // Ensure that only unwind edges end at landing pads (a landing pad is a @@ -653,11 +656,6 @@ // Move eh.exception calls to landing pads. Changed |= MoveExceptionValueCalls(); - // Initialize any stack temporaries we introduced. - Changed |= FinishStackTemporaries(); - - // TODO: Turn any stack temporaries into registers if possible. - Changed |= HandleURoRInvokes(); LandingPads.clear(); From bigcheesegs at gmail.com Wed Sep 1 09:09:36 2010 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Wed, 01 Sep 2010 14:09:36 -0000 Subject: [llvm-commits] [llvm] r112703 - /llvm/trunk/include/llvm/Support/COFF.h Message-ID: <20100901140937.006AD2A6C12C@llvm.org> Author: mspencer Date: Wed Sep 1 09:09:36 2010 New Revision: 112703 URL: http://llvm.org/viewvc/llvm-project?rev=112703&view=rev Log: COFF: Fix incorrect SCT_COMPLEX_TYPE_SHIFT. Add a few constants. Modified: llvm/trunk/include/llvm/Support/COFF.h Modified: llvm/trunk/include/llvm/Support/COFF.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/COFF.h?rev=112703&r1=112702&r2=112703&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/COFF.h (original) +++ llvm/trunk/include/llvm/Support/COFF.h Wed Sep 1 09:09:36 2010 @@ -72,6 +72,12 @@ SF_WeakReference = 0x01000000 }; + enum SymbolSectionNumber { + IMAGE_SYM_DEBUG = -2, + IMAGE_SYM_ABSOLUTE = -1, + IMAGE_SYM_UNDEFINED = 0 + }; + /// Storage class tells where and what the symbol represents enum SymbolStorageClass { IMAGE_SYM_CLASS_END_OF_FUNCTION = -1, ///< Physical end of function @@ -133,7 +139,7 @@ IMAGE_SYM_DTYPE_ARRAY = 3, ///< An array of base type. /// Type is formed as (base + (derived << SCT_COMPLEX_TYPE_SHIFT)) - SCT_COMPLEX_TYPE_SHIFT = 4 + SCT_COMPLEX_TYPE_SHIFT = 8 }; struct section { From bigcheesegs at gmail.com Wed Sep 1 09:15:31 2010 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Wed, 01 Sep 2010 14:15:31 -0000 Subject: [llvm-commits] [llvm] r112704 - in /llvm/trunk/test/MC/COFF: basic-coff.ll symbol-fragment-offset.ll Message-ID: <20100901141531.3BAFD2A6C12C@llvm.org> Author: mspencer Date: Wed Sep 1 09:15:31 2010 New Revision: 112704 URL: http://llvm.org/viewvc/llvm-project?rev=112704&view=rev Log: COFF: Update tests to reflect changes in last commit. Modified: llvm/trunk/test/MC/COFF/basic-coff.ll llvm/trunk/test/MC/COFF/symbol-fragment-offset.ll Modified: llvm/trunk/test/MC/COFF/basic-coff.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/COFF/basic-coff.ll?rev=112704&r1=112703&r2=112704&view=diff ============================================================================== --- llvm/trunk/test/MC/COFF/basic-coff.ll (original) +++ llvm/trunk/test/MC/COFF/basic-coff.ll Wed Sep 1 09:15:31 2010 @@ -106,8 +106,8 @@ ; CHECK: Name = _main ; CHECK: Value = 0 ; CHECK: SectionNumber = 1 -; CHECK: SimpleType = unknown (32) -; CHECK: ComplexType = IMAGE_SYM_DTYPE_NULL (0) +; CHECK: SimpleType = IMAGE_SYM_TYPE_NULL (0) +; CHECK: ComplexType = IMAGE_SYM_DTYPE_FUNCTION (2) ; CHECK: StorageClass = IMAGE_SYM_CLASS_EXTERNAL (2) ; CHECK: NumberOfAuxSymbols = 0 ; CHECK: AuxillaryData = Modified: llvm/trunk/test/MC/COFF/symbol-fragment-offset.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/COFF/symbol-fragment-offset.ll?rev=112704&r1=112703&r2=112704&view=diff ============================================================================== --- llvm/trunk/test/MC/COFF/symbol-fragment-offset.ll (original) +++ llvm/trunk/test/MC/COFF/symbol-fragment-offset.ll Wed Sep 1 09:15:31 2010 @@ -127,8 +127,8 @@ ; CHECK: Name = _main ; CHECK: Value = 0 ; CHECK: SectionNumber = 1 -; CHECK: SimpleType = unknown (32) -; CHECK: ComplexType = IMAGE_SYM_DTYPE_NULL (0) +; CHECK: SimpleType = IMAGE_SYM_TYPE_NULL (0) +; CHECK: ComplexType = IMAGE_SYM_DTYPE_FUNCTION (2) ; CHECK: StorageClass = IMAGE_SYM_CLASS_EXTERNAL (2) ; CHECK: NumberOfAuxSymbols = 0 ; CHECK: AuxillaryData = From gohman at apple.com Wed Sep 1 09:17:34 2010 From: gohman at apple.com (Dan Gohman) Date: Wed, 01 Sep 2010 14:17:34 -0000 Subject: [llvm-commits] [llvm] r112705 - in /llvm/trunk: include/llvm/System/Signals.h lib/System/Unix/Signals.inc lib/System/Win32/Signals.inc Message-ID: <20100901141734.9AFEC2A6C12C@llvm.org> Author: djg Date: Wed Sep 1 09:17:34 2010 New Revision: 112705 URL: http://llvm.org/viewvc/llvm-project?rev=112705&view=rev Log: Add an interface for unregistering a file from the FilesToRemove list. Modified: llvm/trunk/include/llvm/System/Signals.h llvm/trunk/lib/System/Unix/Signals.inc llvm/trunk/lib/System/Win32/Signals.inc Modified: llvm/trunk/include/llvm/System/Signals.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/System/Signals.h?rev=112705&r1=112704&r2=112705&view=diff ============================================================================== --- llvm/trunk/include/llvm/System/Signals.h (original) +++ llvm/trunk/include/llvm/System/Signals.h Wed Sep 1 09:17:34 2010 @@ -29,6 +29,10 @@ /// @brief Remove a file if a fatal signal occurs. bool RemoveFileOnSignal(const Path &Filename, std::string* ErrMsg = 0); + /// This function removes a file from the list of files to be removed on + /// signal delivery. + void DontRemoveFileOnSignal(const Path &Filename); + /// When an error signal (such as SIBABRT or SIGSEGV) is delivered to the /// process, print a stack trace and then exit. /// @brief Print a stack trace if a fatal signal occurs. Modified: llvm/trunk/lib/System/Unix/Signals.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Unix/Signals.inc?rev=112705&r1=112704&r2=112705&view=diff ============================================================================== --- llvm/trunk/lib/System/Unix/Signals.inc (original) +++ llvm/trunk/lib/System/Unix/Signals.inc Wed Sep 1 09:17:34 2010 @@ -182,6 +182,16 @@ return false; } +// DontRemoveFileOnSignal - The public API +void llvm::sys::DontRemoveFileOnSignal(const sys::Path &Filename) { + SignalsMutex.acquire(); + std::vector::reverse_iterator I = + std::find(FilesToRemove.rbegin(), FilesToRemove.rend(), Filename); + if (I != FilesToRemove.rend()) + FilesToRemove.erase(I.base()-1); + SignalsMutex.release(); +} + /// AddSignalHandler - Add a function to be called when a signal is delivered /// to the process. The handler can have a cookie passed to it to identify /// what instance of the handler it is. Modified: llvm/trunk/lib/System/Win32/Signals.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Win32/Signals.inc?rev=112705&r1=112704&r2=112705&view=diff ============================================================================== --- llvm/trunk/lib/System/Win32/Signals.inc (original) +++ llvm/trunk/lib/System/Win32/Signals.inc Wed Sep 1 09:17:34 2010 @@ -140,6 +140,20 @@ return false; } +// DontRemoveFileOnSignal - The public API +void sys::DontRemoveFileOnSignal(const sys::Path &Filename) { + if (FilesToRemove == NULL) + return; + + FilesToRemove->push_back(Filename); + std::vector::reverse_iterator I = + std::find(FilesToRemove->rbegin(), FilesToRemove->rend(), Filename); + if (I != FilesToRemove->rend()) + FilesToRemove->erase(I.base()-1); + + LeaveCriticalSection(&CriticalSection); +} + /// PrintStackTraceOnErrorSignal - When an error signal (such as SIBABRT or /// SIGSEGV) is delivered to the process, print a stack trace and then exit. void sys::PrintStackTraceOnErrorSignal() { From gohman at apple.com Wed Sep 1 09:20:41 2010 From: gohman at apple.com (Dan Gohman) Date: Wed, 01 Sep 2010 14:20:41 -0000 Subject: [llvm-commits] [llvm] r112706 - in /llvm/trunk: include/llvm/Support/ lib/Support/ tools/bugpoint/ tools/llc/ tools/llvm-as/ tools/llvm-dis/ tools/llvm-extract/ tools/llvm-ld/ tools/llvm-link/ tools/llvm-mc/ tools/lto/ tools/opt/ utils/FileUpdate/ utils/TableGen/ Message-ID: <20100901142041.DD2B52A6C12C@llvm.org> Author: djg Date: Wed Sep 1 09:20:41 2010 New Revision: 112706 URL: http://llvm.org/viewvc/llvm-project?rev=112706&view=rev Log: Make tool_output_file's raw_ostream instance a member variable instead of a base class. This makes it possible to unregister the file from FilesToRemove when the file is done. Also, this eliminates the need for formatted_tool_output_file. Modified: llvm/trunk/include/llvm/Support/FormattedStream.h llvm/trunk/include/llvm/Support/raw_ostream.h llvm/trunk/lib/Support/FormattedStream.cpp llvm/trunk/lib/Support/raw_ostream.cpp llvm/trunk/tools/bugpoint/ExtractFunction.cpp llvm/trunk/tools/bugpoint/OptimizerDriver.cpp llvm/trunk/tools/llc/llc.cpp llvm/trunk/tools/llvm-as/llvm-as.cpp llvm/trunk/tools/llvm-dis/llvm-dis.cpp llvm/trunk/tools/llvm-extract/llvm-extract.cpp llvm/trunk/tools/llvm-ld/llvm-ld.cpp llvm/trunk/tools/llvm-link/llvm-link.cpp llvm/trunk/tools/llvm-mc/llvm-mc.cpp llvm/trunk/tools/lto/LTOCodeGenerator.cpp llvm/trunk/tools/lto/LTOCodeGenerator.h llvm/trunk/tools/opt/GraphPrinters.cpp llvm/trunk/tools/opt/opt.cpp llvm/trunk/utils/FileUpdate/FileUpdate.cpp llvm/trunk/utils/TableGen/TableGen.cpp Modified: llvm/trunk/include/llvm/Support/FormattedStream.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/FormattedStream.h?rev=112706&r1=112705&r2=112706&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/FormattedStream.h (original) +++ llvm/trunk/include/llvm/Support/FormattedStream.h Wed Sep 1 09:20:41 2010 @@ -19,14 +19,10 @@ namespace llvm { - class formatted_tool_output_file; - /// formatted_raw_ostream - Formatted raw_fd_ostream to handle /// asm-specific constructs. /// class formatted_raw_ostream : public raw_ostream { - friend class formatted_tool_output_file; - public: /// DELETE_STREAM - Tell the destructor to delete the held stream. /// @@ -140,38 +136,6 @@ } }; - /// formatted_tool_output_file - This is a subclass of formatted_raw_ostream - /// for use when the underlying stream is a tool_output_file. It exposes - /// keep() and several other member functions. - class formatted_tool_output_file : public formatted_raw_ostream { - private: - tool_output_file &get_tool_output_file() const { - return *static_cast(TheStream); - } - - public: - formatted_tool_output_file(tool_output_file &Stream, bool Delete = false) - : formatted_raw_ostream(Stream, Delete) {} - - formatted_tool_output_file() {} - - ~formatted_tool_output_file(); - - void setStream(tool_output_file &Stream, bool Delete = false) { - return formatted_raw_ostream::setStream(Stream, Delete); - } - - void keep() { return get_tool_output_file().keep(); } - bool has_error() const { return get_tool_output_file().has_error(); } - void clear_error() { return get_tool_output_file().clear_error(); } - void close() { - // The inner stream is unbuffered; flush the outer stream's buffer. - flush(); - // The inner stream can close its file descriptor now. - return get_tool_output_file().close(); - } - }; - /// fouts() - This returns a reference to a formatted_raw_ostream for /// standard output. Use it like: fouts() << "foo" << "bar"; formatted_raw_ostream &fouts(); Modified: llvm/trunk/include/llvm/Support/raw_ostream.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/raw_ostream.h?rev=112706&r1=112705&r2=112706&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/raw_ostream.h (original) +++ llvm/trunk/include/llvm/Support/raw_ostream.h Wed Sep 1 09:20:41 2010 @@ -475,23 +475,43 @@ ~raw_null_ostream(); }; -/// tool_output_file - This class behaves like a raw_fd_ostream but adds a +/// tool_output_file - This class contains a raw_fd_ostream and adds a /// few extra features commonly needed for compiler-like tool output files: /// - The file is automatically deleted if the process is killed. /// - The file is automatically deleted when the tool_output_file /// object is destroyed unless the client calls keep(). -class tool_output_file : public raw_fd_ostream { - std::string Filename; - bool Keep; +class tool_output_file { + /// Installer - This class is declared before the raw_fd_ostream so that + /// it is constructed before the raw_fd_ostream is constructed and + /// destructed after the raw_fd_ostream is destructed. It installs + /// cleanups in its constructor and uninstalls them in its destructor. + class CleanupInstaller { + /// Filename - The name of the file. + std::string Filename; + public: + /// Keep - The flag which indicates whether we should not delete the file. + bool Keep; + + explicit CleanupInstaller(const char *filename); + ~CleanupInstaller(); + } Installer; + + /// OS - The contained stream. This is intentionally declared after + /// Installer. + raw_fd_ostream OS; + public: + /// tool_output_file - This constructor's arguments are passed to + /// to raw_fd_ostream's constructor. tool_output_file(const char *filename, std::string &ErrorInfo, unsigned Flags = 0); - ~tool_output_file(); + /// os - Return the contained raw_fd_ostream. + raw_fd_ostream &os() { return OS; } /// keep - Indicate that the tool's job wrt this output file has been /// successful and the file should not be deleted. - void keep() { Keep = true; } + void keep() { Installer.Keep = true; } }; } // end llvm namespace Modified: llvm/trunk/lib/Support/FormattedStream.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/FormattedStream.cpp?rev=112706&r1=112705&r2=112706&view=diff ============================================================================== --- llvm/trunk/lib/Support/FormattedStream.cpp (original) +++ llvm/trunk/lib/Support/FormattedStream.cpp Wed Sep 1 09:20:41 2010 @@ -98,6 +98,3 @@ static formatted_raw_ostream S(dbgs()); return S; } - -/// ~formatted_tool_output_file - Out-of-line destructor. -formatted_tool_output_file::~formatted_tool_output_file() {} Modified: llvm/trunk/lib/Support/raw_ostream.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/raw_ostream.cpp?rev=112706&r1=112705&r2=112706&view=diff ============================================================================== --- llvm/trunk/lib/Support/raw_ostream.cpp (original) +++ llvm/trunk/lib/Support/raw_ostream.cpp Wed Sep 1 09:20:41 2010 @@ -670,25 +670,29 @@ // tool_output_file //===----------------------------------------------------------------------===// -/// SetupRemoveOnSignal - This is a helper for tool_output_file's constructor -/// to allow the signal handlers to be installed before constructing the -/// base class raw_fd_ostream. -static const char *SetupRemoveOnSignal(const char *Filename) { +tool_output_file::CleanupInstaller::CleanupInstaller(const char *filename) + : Filename(filename), Keep(false) { // Arrange for the file to be deleted if the process is killed. - if (strcmp(Filename, "-") != 0) + if (Filename != "-") sys::RemoveFileOnSignal(sys::Path(Filename)); - return Filename; } -tool_output_file::tool_output_file(const char *filename, std::string &ErrorInfo, - unsigned Flags) - : raw_fd_ostream(SetupRemoveOnSignal(filename), ErrorInfo, Flags), - Filename(filename), - Keep(!ErrorInfo.empty() /* If open fails, no cleanup is needed. */) { -} - -tool_output_file::~tool_output_file() { +tool_output_file::CleanupInstaller::~CleanupInstaller() { // Delete the file if the client hasn't told us not to. if (!Keep && Filename != "-") sys::Path(Filename).eraseFromDisk(); + + // Ok, the file is successfully written and closed, or deleted. There's no + // further need to clean it up on signals. + if (Filename != "-") + sys::DontRemoveFileOnSignal(sys::Path(Filename)); +} + +tool_output_file::tool_output_file(const char *filename, std::string &ErrorInfo, + unsigned Flags) + : Installer(filename), + OS(filename, ErrorInfo, Flags) { + // If open fails, no cleanup is needed. + if (!ErrorInfo.empty()) + Installer.Keep = true; } Modified: llvm/trunk/tools/bugpoint/ExtractFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/bugpoint/ExtractFunction.cpp?rev=112706&r1=112705&r2=112706&view=diff ============================================================================== --- llvm/trunk/tools/bugpoint/ExtractFunction.cpp (original) +++ llvm/trunk/tools/bugpoint/ExtractFunction.cpp Wed Sep 1 09:20:41 2010 @@ -339,15 +339,15 @@ // If the BB doesn't have a name, give it one so we have something to key // off of. if (!BB->hasName()) BB->setName("tmpbb"); - BlocksToNotExtractFile << BB->getParent()->getNameStr() << " " - << BB->getName() << "\n"; + BlocksToNotExtractFile.os() << BB->getParent()->getNameStr() << " " + << BB->getName() << "\n"; } - BlocksToNotExtractFile.close(); - if (BlocksToNotExtractFile.has_error()) { + BlocksToNotExtractFile.os().close(); + if (BlocksToNotExtractFile.os().has_error()) { errs() << "Error writing list of blocks to not extract: " << ErrorInfo << "\n"; EmitProgressBitcode(M, "basicblockextractfail", true); - BlocksToNotExtractFile.clear_error(); + BlocksToNotExtractFile.os().clear_error(); return 0; } BlocksToNotExtractFile.keep(); Modified: llvm/trunk/tools/bugpoint/OptimizerDriver.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/bugpoint/OptimizerDriver.cpp?rev=112706&r1=112705&r2=112706&view=diff ============================================================================== --- llvm/trunk/tools/bugpoint/OptimizerDriver.cpp (original) +++ llvm/trunk/tools/bugpoint/OptimizerDriver.cpp Wed Sep 1 09:20:41 2010 @@ -58,14 +58,14 @@ tool_output_file Out(Filename.c_str(), ErrInfo, raw_fd_ostream::F_Binary); if (ErrInfo.empty()) { - WriteBitcodeToFile(M, Out); - Out.close(); - if (!Out.has_error()) { + WriteBitcodeToFile(M, Out.os()); + Out.os().close(); + if (!Out.os().has_error()) { Out.keep(); return false; } } - Out.clear_error(); + Out.os().clear_error(); return true; } @@ -140,11 +140,11 @@ errs() << "Error opening bitcode file: " << inputFilename.str() << "\n"; return 1; } - WriteBitcodeToFile(Program, InFile); - InFile.close(); - if (InFile.has_error()) { + WriteBitcodeToFile(Program, InFile.os()); + InFile.os().close(); + if (InFile.os().has_error()) { errs() << "Error writing bitcode file: " << inputFilename.str() << "\n"; - InFile.clear_error(); + InFile.os().clear_error(); return 1; } InFile.keep(); Modified: llvm/trunk/tools/llc/llc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llc/llc.cpp?rev=112706&r1=112705&r2=112706&view=diff ============================================================================== --- llvm/trunk/tools/llc/llc.cpp (original) +++ llvm/trunk/tools/llc/llc.cpp Wed Sep 1 09:20:41 2010 @@ -123,9 +123,9 @@ return outputFilename; } -static formatted_tool_output_file *GetOutputStream(const char *TargetName, - Triple::OSType OS, - const char *ProgName) { +static tool_output_file *GetOutputStream(const char *TargetName, + Triple::OSType OS, + const char *ProgName) { // If we don't yet have an output filename, make one. if (OutputFilename.empty()) { if (InputFilename == "-") @@ -183,11 +183,7 @@ return 0; } - formatted_tool_output_file *Out = - new formatted_tool_output_file(*FDOut, - formatted_raw_ostream::DELETE_STREAM); - - return Out; + return FDOut; } // main - Entry point for the llc compiler. @@ -278,7 +274,7 @@ TargetMachine &Target = *target.get(); // Figure out where we are going to send the output... - OwningPtr Out + OwningPtr Out (GetOutputStream(TheTarget->getName(), TheTriple.getOS(), argv[0])); if (!Out) return 1; @@ -314,15 +310,18 @@ Target.setMCRelaxAll(true); } - // Ask the target to add backend passes as necessary. - if (Target.addPassesToEmitFile(PM, *Out, FileType, OLvl, - NoVerify)) { - errs() << argv[0] << ": target does not support generation of this" - << " file type!\n"; - return 1; - } + { + formatted_raw_ostream FOS(Out->os()); - PM.run(mod); + // Ask the target to add backend passes as necessary. + if (Target.addPassesToEmitFile(PM, FOS, FileType, OLvl, NoVerify)) { + errs() << argv[0] << ": target does not support generation of this" + << " file type!\n"; + return 1; + } + + PM.run(mod); + } // Declare success. Out->keep(); Modified: llvm/trunk/tools/llvm-as/llvm-as.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-as/llvm-as.cpp?rev=112706&r1=112705&r2=112706&view=diff ============================================================================== --- llvm/trunk/tools/llvm-as/llvm-as.cpp (original) +++ llvm/trunk/tools/llvm-as/llvm-as.cpp Wed Sep 1 09:20:41 2010 @@ -77,8 +77,8 @@ exit(1); } - if (Force || !CheckBitcodeOutputToConsole(*Out, true)) - WriteBitcodeToFile(M, *Out); + if (Force || !CheckBitcodeOutputToConsole(Out->os(), true)) + WriteBitcodeToFile(M, Out->os()); // Declare success. Out->keep(); Modified: llvm/trunk/tools/llvm-dis/llvm-dis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-dis/llvm-dis.cpp?rev=112706&r1=112705&r2=112706&view=diff ============================================================================== --- llvm/trunk/tools/llvm-dis/llvm-dis.cpp (original) +++ llvm/trunk/tools/llvm-dis/llvm-dis.cpp Wed Sep 1 09:20:41 2010 @@ -98,7 +98,7 @@ // All that llvm-dis does is write the assembly to a file. if (!DontPrint) - *Out << *M; + Out->os() << *M; // Declare success. Out->keep(); Modified: llvm/trunk/tools/llvm-extract/llvm-extract.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-extract/llvm-extract.cpp?rev=112706&r1=112705&r2=112706&view=diff ============================================================================== --- llvm/trunk/tools/llvm-extract/llvm-extract.cpp (original) +++ llvm/trunk/tools/llvm-extract/llvm-extract.cpp Wed Sep 1 09:20:41 2010 @@ -134,9 +134,9 @@ } if (OutputAssembly) - Passes.add(createPrintModulePass(&Out)); - else if (Force || !CheckBitcodeOutputToConsole(Out, true)) - Passes.add(createBitcodeWriterPass(Out)); + Passes.add(createPrintModulePass(&Out.os())); + else if (Force || !CheckBitcodeOutputToConsole(Out.os(), true)) + Passes.add(createBitcodeWriterPass(Out.os())); Passes.run(*M.get()); Modified: llvm/trunk/tools/llvm-ld/llvm-ld.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-ld/llvm-ld.cpp?rev=112706&r1=112705&r2=112706&view=diff ============================================================================== --- llvm/trunk/tools/llvm-ld/llvm-ld.cpp (original) +++ llvm/trunk/tools/llvm-ld/llvm-ld.cpp Wed Sep 1 09:20:41 2010 @@ -244,7 +244,7 @@ } // Write it out - WriteBitcodeToFile(M, Out); + WriteBitcodeToFile(M, Out.os()); Out.keep(); } @@ -432,10 +432,10 @@ if (!ErrorInfo.empty()) PrintAndExit(ErrorInfo, M); - Out2 << "#!/bin/sh\n"; + Out2.os() << "#!/bin/sh\n"; // Allow user to setenv LLVMINTERP if lli is not in their PATH. - Out2 << "lli=${LLVMINTERP-lli}\n"; - Out2 << "exec $lli \\\n"; + Out2.os() << "lli=${LLVMINTERP-lli}\n"; + Out2.os() << "exec $lli \\\n"; // gcc accepts -l and implicitly searches /lib and /usr/lib. LibPaths.push_back("/lib"); LibPaths.push_back("/usr/lib"); @@ -466,9 +466,9 @@ if (FullLibraryPath.isEmpty()) FullLibraryPath = sys::Path::FindLibrary(*i); if (!FullLibraryPath.isEmpty()) - Out2 << " -load=" << FullLibraryPath.str() << " \\\n"; + Out2.os() << " -load=" << FullLibraryPath.str() << " \\\n"; } - Out2 << " " << BitcodeOutputFilename << " ${1+\"$@\"}\n"; + Out2.os() << " " << BitcodeOutputFilename << " ${1+\"$@\"}\n"; Out2.keep(); } Modified: llvm/trunk/tools/llvm-link/llvm-link.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-link/llvm-link.cpp?rev=112706&r1=112705&r2=112706&view=diff ============================================================================== --- llvm/trunk/tools/llvm-link/llvm-link.cpp (original) +++ llvm/trunk/tools/llvm-link/llvm-link.cpp Wed Sep 1 09:20:41 2010 @@ -130,9 +130,9 @@ if (Verbose) errs() << "Writing bitcode...\n"; if (OutputAssembly) { - Out << *Composite; - } else if (Force || !CheckBitcodeOutputToConsole(Out, true)) - WriteBitcodeToFile(Composite.get(), Out); + Out.os() << *Composite; + } else if (Force || !CheckBitcodeOutputToConsole(Out.os(), true)) + WriteBitcodeToFile(Composite.get(), Out.os()); // Declare success. Out.keep(); Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=112706&r1=112705&r2=112706&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original) +++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Wed Sep 1 09:20:41 2010 @@ -140,7 +140,7 @@ return 0; } -static formatted_tool_output_file *GetOutputStream() { +static tool_output_file *GetOutputStream() { if (OutputFilename == "") OutputFilename = "-"; @@ -152,9 +152,8 @@ delete Out; return 0; } - - return new formatted_tool_output_file(*Out, - formatted_raw_ostream::DELETE_STREAM); + + return Out; } static int AsLexInput(const char *ProgName) { @@ -189,7 +188,7 @@ AsmLexer Lexer(*MAI); Lexer.setBuffer(SrcMgr.getMemoryBuffer(0)); - OwningPtr Out(GetOutputStream()); + OwningPtr Out(GetOutputStream()); if (!Out) return 1; @@ -204,44 +203,44 @@ Error = true; // error already printed. break; case AsmToken::Identifier: - *Out << "identifier: " << Lexer.getTok().getString() << '\n'; + Out->os() << "identifier: " << Lexer.getTok().getString() << '\n'; break; case AsmToken::String: - *Out << "string: " << Lexer.getTok().getString() << '\n'; + Out->os() << "string: " << Lexer.getTok().getString() << '\n'; break; case AsmToken::Integer: - *Out << "int: " << Lexer.getTok().getString() << '\n'; + Out->os() << "int: " << Lexer.getTok().getString() << '\n'; break; - case AsmToken::Amp: *Out << "Amp\n"; break; - case AsmToken::AmpAmp: *Out << "AmpAmp\n"; break; - case AsmToken::Caret: *Out << "Caret\n"; break; - case AsmToken::Colon: *Out << "Colon\n"; break; - case AsmToken::Comma: *Out << "Comma\n"; break; - case AsmToken::Dollar: *Out << "Dollar\n"; break; - case AsmToken::EndOfStatement: *Out << "EndOfStatement\n"; break; - case AsmToken::Eof: *Out << "Eof\n"; break; - case AsmToken::Equal: *Out << "Equal\n"; break; - case AsmToken::EqualEqual: *Out << "EqualEqual\n"; break; - case AsmToken::Exclaim: *Out << "Exclaim\n"; break; - case AsmToken::ExclaimEqual: *Out << "ExclaimEqual\n"; break; - case AsmToken::Greater: *Out << "Greater\n"; break; - case AsmToken::GreaterEqual: *Out << "GreaterEqual\n"; break; - case AsmToken::GreaterGreater: *Out << "GreaterGreater\n"; break; - case AsmToken::LParen: *Out << "LParen\n"; break; - case AsmToken::Less: *Out << "Less\n"; break; - case AsmToken::LessEqual: *Out << "LessEqual\n"; break; - case AsmToken::LessGreater: *Out << "LessGreater\n"; break; - case AsmToken::LessLess: *Out << "LessLess\n"; break; - case AsmToken::Minus: *Out << "Minus\n"; break; - case AsmToken::Percent: *Out << "Percent\n"; break; - case AsmToken::Pipe: *Out << "Pipe\n"; break; - case AsmToken::PipePipe: *Out << "PipePipe\n"; break; - case AsmToken::Plus: *Out << "Plus\n"; break; - case AsmToken::RParen: *Out << "RParen\n"; break; - case AsmToken::Slash: *Out << "Slash\n"; break; - case AsmToken::Star: *Out << "Star\n"; break; - case AsmToken::Tilde: *Out << "Tilde\n"; break; + case AsmToken::Amp: Out->os() << "Amp\n"; break; + case AsmToken::AmpAmp: Out->os() << "AmpAmp\n"; break; + case AsmToken::Caret: Out->os() << "Caret\n"; break; + case AsmToken::Colon: Out->os() << "Colon\n"; break; + case AsmToken::Comma: Out->os() << "Comma\n"; break; + case AsmToken::Dollar: Out->os() << "Dollar\n"; break; + case AsmToken::EndOfStatement: Out->os() << "EndOfStatement\n"; break; + case AsmToken::Eof: Out->os() << "Eof\n"; break; + case AsmToken::Equal: Out->os() << "Equal\n"; break; + case AsmToken::EqualEqual: Out->os() << "EqualEqual\n"; break; + case AsmToken::Exclaim: Out->os() << "Exclaim\n"; break; + case AsmToken::ExclaimEqual: Out->os() << "ExclaimEqual\n"; break; + case AsmToken::Greater: Out->os() << "Greater\n"; break; + case AsmToken::GreaterEqual: Out->os() << "GreaterEqual\n"; break; + case AsmToken::GreaterGreater: Out->os() << "GreaterGreater\n"; break; + case AsmToken::LParen: Out->os() << "LParen\n"; break; + case AsmToken::Less: Out->os() << "Less\n"; break; + case AsmToken::LessEqual: Out->os() << "LessEqual\n"; break; + case AsmToken::LessGreater: Out->os() << "LessGreater\n"; break; + case AsmToken::LessLess: Out->os() << "LessLess\n"; break; + case AsmToken::Minus: Out->os() << "Minus\n"; break; + case AsmToken::Percent: Out->os() << "Percent\n"; break; + case AsmToken::Pipe: Out->os() << "Pipe\n"; break; + case AsmToken::PipePipe: Out->os() << "PipePipe\n"; break; + case AsmToken::Plus: Out->os() << "Plus\n"; break; + case AsmToken::RParen: Out->os() << "RParen\n"; break; + case AsmToken::Slash: Out->os() << "Slash\n"; break; + case AsmToken::Star: Out->os() << "Star\n"; break; + case AsmToken::Tilde: Out->os() << "Tilde\n"; break; } } @@ -291,10 +290,11 @@ return 1; } - OwningPtr Out(GetOutputStream()); + OwningPtr Out(GetOutputStream()); if (!Out) return 1; + formatted_raw_ostream FOS(Out->os()); OwningPtr Str; if (FileType == OFT_AssemblyFile) { @@ -303,7 +303,7 @@ MCCodeEmitter *CE = 0; if (ShowEncoding) CE = TheTarget->createCodeEmitter(*TM, Ctx); - Str.reset(createAsmStreamer(Ctx, *Out, + Str.reset(createAsmStreamer(Ctx, FOS, TM->getTargetData()->isLittleEndian(), /*asmverbose*/true, IP, CE, ShowInst)); } else if (FileType == OFT_Null) { @@ -313,7 +313,7 @@ MCCodeEmitter *CE = TheTarget->createCodeEmitter(*TM, Ctx); TargetAsmBackend *TAB = TheTarget->createAsmBackend(TripleName); Str.reset(TheTarget->createObjectStreamer(TripleName, Ctx, *TAB, - *Out, CE, RelaxAll)); + FOS, CE, RelaxAll)); } if (EnableLogging) { @@ -359,15 +359,15 @@ return 1; } - OwningPtr Out(GetOutputStream()); + OwningPtr Out(GetOutputStream()); if (!Out) return 1; int Res; if (Enhanced) - Res = Disassembler::disassembleEnhanced(TripleName, *Buffer, *Out); + Res = Disassembler::disassembleEnhanced(TripleName, *Buffer, Out->os()); else - Res = Disassembler::disassemble(*TheTarget, TripleName, *Buffer, *Out); + Res = Disassembler::disassemble(*TheTarget, TripleName, *Buffer, Out->os()); // Keep output if no errors. if (Res == 0) Out->keep(); Modified: llvm/trunk/tools/lto/LTOCodeGenerator.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOCodeGenerator.cpp?rev=112706&r1=112705&r2=112706&view=diff ============================================================================== --- llvm/trunk/tools/lto/LTOCodeGenerator.cpp (original) +++ llvm/trunk/tools/lto/LTOCodeGenerator.cpp Wed Sep 1 09:20:41 2010 @@ -164,13 +164,13 @@ } // write bitcode to it - WriteBitcodeToFile(_linker.getModule(), Out); - Out.close(); + WriteBitcodeToFile(_linker.getModule(), Out.os()); + Out.os().close(); - if (Out.has_error()) { + if (Out.os().has_error()) { errMsg = "could not write bitcode file: "; errMsg += path; - Out.clear_error(); + Out.os().clear_error(); return true; } @@ -190,14 +190,13 @@ // generate assembly code bool genResult = false; { - tool_output_file asmFD(uniqueAsmPath.c_str(), errMsg); - formatted_tool_output_file asmFile(asmFD); + tool_output_file asmFile(uniqueAsmPath.c_str(), errMsg); if (!errMsg.empty()) return NULL; - genResult = this->generateAssemblyCode(asmFile, errMsg); - asmFile.close(); - if (asmFile.has_error()) { - asmFile.clear_error(); + genResult = this->generateAssemblyCode(asmFile.os(), errMsg); + asmFile.os().close(); + if (asmFile.os().has_error()) { + asmFile.os().clear_error(); return NULL; } asmFile.keep(); @@ -368,7 +367,7 @@ } /// Optimize merged modules using various IPO passes -bool LTOCodeGenerator::generateAssemblyCode(formatted_raw_ostream& out, +bool LTOCodeGenerator::generateAssemblyCode(raw_ostream& out, std::string& errMsg) { if ( this->determineTarget(errMsg) ) @@ -403,7 +402,9 @@ codeGenPasses->add(new TargetData(*_target->getTargetData())); - if (_target->addPassesToEmitFile(*codeGenPasses, out, + formatted_raw_ostream Out(out); + + if (_target->addPassesToEmitFile(*codeGenPasses, Out, TargetMachine::CGFT_AssemblyFile, CodeGenOpt::Aggressive)) { errMsg = "target file type not supported"; Modified: llvm/trunk/tools/lto/LTOCodeGenerator.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOCodeGenerator.h?rev=112706&r1=112705&r2=112706&view=diff ============================================================================== --- llvm/trunk/tools/lto/LTOCodeGenerator.h (original) +++ llvm/trunk/tools/lto/LTOCodeGenerator.h Wed Sep 1 09:20:41 2010 @@ -45,7 +45,7 @@ const void* compile(size_t* length, std::string& errMsg); void setCodeGenDebugOptions(const char *opts); private: - bool generateAssemblyCode(llvm::formatted_raw_ostream& out, + bool generateAssemblyCode(llvm::raw_ostream& out, std::string& errMsg); bool assemble(const std::string& asmPath, const std::string& objPath, std::string& errMsg); Modified: llvm/trunk/tools/opt/GraphPrinters.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/opt/GraphPrinters.cpp?rev=112706&r1=112705&r2=112706&view=diff ============================================================================== --- llvm/trunk/tools/opt/GraphPrinters.cpp (original) +++ llvm/trunk/tools/opt/GraphPrinters.cpp Wed Sep 1 09:20:41 2010 @@ -31,16 +31,16 @@ tool_output_file F(Filename.c_str(), ErrInfo); if (ErrInfo.empty()) { - WriteGraph(F, GT); - F.close(); - if (!F.has_error()) { + WriteGraph(F.os(), GT); + F.os().close(); + if (!F.os().has_error()) { O << "\n"; F.keep(); return; } } - F.clear_error(); O << " error opening file for writing!\n"; + F.os().clear_error(); } Modified: llvm/trunk/tools/opt/opt.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/opt/opt.cpp?rev=112706&r1=112705&r2=112706&view=diff ============================================================================== --- llvm/trunk/tools/opt/opt.cpp (original) +++ llvm/trunk/tools/opt/opt.cpp Wed Sep 1 09:20:41 2010 @@ -359,6 +359,11 @@ int main(int argc, char **argv) { sys::PrintStackTraceOnErrorSignal(); llvm::PrettyStackTraceProgram X(argc, argv); + + if (AnalyzeOnly && NoOutput) { + errs() << argv[0] << ": analyze mode conflicts with no-output mode.\n"; + return 1; + } // Enable debug stream buffering. EnableDebugBuffering = true; @@ -408,7 +413,7 @@ // console, print out a warning message and refuse to do it. We don't // impress anyone by spewing tons of binary goo to a terminal. if (!Force && !NoOutput && !AnalyzeOnly && !OutputAssembly) - if (CheckBitcodeOutputToConsole(*Out, !Quiet)) + if (CheckBitcodeOutputToConsole(Out->os(), !Quiet)) NoOutput = true; // Create a PassManager to hold and optimize the collection of passes we are @@ -484,19 +489,19 @@ if (AnalyzeOnly) { switch (Kind) { case PT_BasicBlock: - Passes.add(new BasicBlockPassPrinter(PassInf, *Out)); + Passes.add(new BasicBlockPassPrinter(PassInf, Out->os())); break; case PT_Loop: - Passes.add(new LoopPassPrinter(PassInf, *Out)); + Passes.add(new LoopPassPrinter(PassInf, Out->os())); break; case PT_Function: - Passes.add(new FunctionPassPrinter(PassInf, *Out)); + Passes.add(new FunctionPassPrinter(PassInf, Out->os())); break; case PT_CallGraphSCC: - Passes.add(new CallGraphSCCPassPrinter(PassInf, *Out)); + Passes.add(new CallGraphSCCPassPrinter(PassInf, Out->os())); break; default: - Passes.add(new ModulePassPrinter(PassInf, *Out)); + Passes.add(new ModulePassPrinter(PassInf, Out->os())); break; } } @@ -536,9 +541,9 @@ // Write bitcode or assembly to the output as the last step... if (!NoOutput && !AnalyzeOnly) { if (OutputAssembly) - Passes.add(createPrintModulePass(Out.get())); + Passes.add(createPrintModulePass(&Out->os())); else - Passes.add(createBitcodeWriterPass(*Out)); + Passes.add(createBitcodeWriterPass(Out->os())); } // Now that we have all of the passes ready, run them. Modified: llvm/trunk/utils/FileUpdate/FileUpdate.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/FileUpdate/FileUpdate.cpp?rev=112706&r1=112705&r2=112706&view=diff ============================================================================== --- llvm/trunk/utils/FileUpdate/FileUpdate.cpp (original) +++ llvm/trunk/utils/FileUpdate/FileUpdate.cpp Wed Sep 1 09:20:41 2010 @@ -78,7 +78,7 @@ return 1; } - OutStream.write(In->getBufferStart(), In->getBufferSize()); + OutStream.os().write(In->getBufferStart(), In->getBufferSize()); // Declare success. OutStream.keep(); Modified: llvm/trunk/utils/TableGen/TableGen.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TableGen.cpp?rev=112706&r1=112705&r2=112706&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/TableGen.cpp (original) +++ llvm/trunk/utils/TableGen/TableGen.cpp Wed Sep 1 09:20:41 2010 @@ -226,109 +226,109 @@ try { switch (Action) { case PrintRecords: - Out << Records; // No argument, dump all contents + Out.os() << Records; // No argument, dump all contents break; case GenEmitter: - CodeEmitterGen(Records).run(Out); + CodeEmitterGen(Records).run(Out.os()); break; case GenRegisterEnums: - RegisterInfoEmitter(Records).runEnums(Out); + RegisterInfoEmitter(Records).runEnums(Out.os()); break; case GenRegister: - RegisterInfoEmitter(Records).run(Out); + RegisterInfoEmitter(Records).run(Out.os()); break; case GenRegisterHeader: - RegisterInfoEmitter(Records).runHeader(Out); + RegisterInfoEmitter(Records).runHeader(Out.os()); break; case GenInstrEnums: - InstrEnumEmitter(Records).run(Out); + InstrEnumEmitter(Records).run(Out.os()); break; case GenInstrs: - InstrInfoEmitter(Records).run(Out); + InstrInfoEmitter(Records).run(Out.os()); break; case GenCallingConv: - CallingConvEmitter(Records).run(Out); + CallingConvEmitter(Records).run(Out.os()); break; case GenAsmWriter: - AsmWriterEmitter(Records).run(Out); + AsmWriterEmitter(Records).run(Out.os()); break; case GenARMDecoder: - ARMDecoderEmitter(Records).run(Out); + ARMDecoderEmitter(Records).run(Out.os()); break; case GenAsmMatcher: - AsmMatcherEmitter(Records).run(Out); + AsmMatcherEmitter(Records).run(Out.os()); break; case GenClangAttrClasses: - ClangAttrClassEmitter(Records).run(Out); + ClangAttrClassEmitter(Records).run(Out.os()); break; case GenClangAttrImpl: - ClangAttrImplEmitter(Records).run(Out); + ClangAttrImplEmitter(Records).run(Out.os()); break; case GenClangAttrList: - ClangAttrListEmitter(Records).run(Out); + ClangAttrListEmitter(Records).run(Out.os()); break; case GenClangAttrPCHRead: - ClangAttrPCHReadEmitter(Records).run(Out); + ClangAttrPCHReadEmitter(Records).run(Out.os()); break; case GenClangAttrPCHWrite: - ClangAttrPCHWriteEmitter(Records).run(Out); + ClangAttrPCHWriteEmitter(Records).run(Out.os()); break; case GenClangDiagsDefs: - ClangDiagsDefsEmitter(Records, ClangComponent).run(Out); + ClangDiagsDefsEmitter(Records, ClangComponent).run(Out.os()); break; case GenClangDiagGroups: - ClangDiagGroupsEmitter(Records).run(Out); + ClangDiagGroupsEmitter(Records).run(Out.os()); break; case GenClangDeclNodes: - ClangASTNodesEmitter(Records, "Decl", "Decl").run(Out); - ClangDeclContextEmitter(Records).run(Out); + ClangASTNodesEmitter(Records, "Decl", "Decl").run(Out.os()); + ClangDeclContextEmitter(Records).run(Out.os()); break; case GenClangStmtNodes: - ClangASTNodesEmitter(Records, "Stmt", "").run(Out); + ClangASTNodesEmitter(Records, "Stmt", "").run(Out.os()); break; case GenDisassembler: - DisassemblerEmitter(Records).run(Out); + DisassemblerEmitter(Records).run(Out.os()); break; case GenOptParserDefs: - OptParserEmitter(Records, true).run(Out); + OptParserEmitter(Records, true).run(Out.os()); break; case GenOptParserImpl: - OptParserEmitter(Records, false).run(Out); + OptParserEmitter(Records, false).run(Out.os()); break; case GenDAGISel: - DAGISelEmitter(Records).run(Out); + DAGISelEmitter(Records).run(Out.os()); break; case GenFastISel: - FastISelEmitter(Records).run(Out); + FastISelEmitter(Records).run(Out.os()); break; case GenSubtarget: - SubtargetEmitter(Records).run(Out); + SubtargetEmitter(Records).run(Out.os()); break; case GenIntrinsic: - IntrinsicEmitter(Records).run(Out); + IntrinsicEmitter(Records).run(Out.os()); break; case GenTgtIntrinsic: - IntrinsicEmitter(Records, true).run(Out); + IntrinsicEmitter(Records, true).run(Out.os()); break; case GenLLVMCConf: - LLVMCConfigurationEmitter(Records).run(Out); + LLVMCConfigurationEmitter(Records).run(Out.os()); break; case GenEDInfo: - EDEmitter(Records).run(Out); + EDEmitter(Records).run(Out.os()); break; case GenArmNeon: - NeonEmitter(Records).run(Out); + NeonEmitter(Records).run(Out.os()); break; case GenArmNeonSema: - NeonEmitter(Records).runHeader(Out); + NeonEmitter(Records).runHeader(Out.os()); break; case PrintEnums: { std::vector Recs = Records.getAllDerivedDefinitions(Class); for (unsigned i = 0, e = Recs.size(); i != e; ++i) - Out << Recs[i]->getName() << ", "; - Out << "\n"; + Out.os() << Recs[i]->getName() << ", "; + Out.os() << "\n"; break; } default: From espindola at google.com Wed Sep 1 09:54:18 2010 From: espindola at google.com (Rafael Espindola) Date: Wed, 1 Sep 2010 10:54:18 -0400 Subject: [llvm-commits] [PATCH 0/5] ELF object support In-Reply-To: <20100813182949.GA3979@console-pimps.org> References: <20100813182949.GA3979@console-pimps.org> Message-ID: > ... I was planning on committing some ELF tests after the basic support > went in just because I haven't written them yet. I hadn't thought about > writing a dumping tool for ELF but I can certainly do that. Do we need a dedicated tool? If readelf works we might be able to live with it. The downside is that you would need an ELF host to run the tests, but we probably have enough ELF bots now. Cheers, -- Rafael ?vila de Esp?ndola From sabre at nondot.org Wed Sep 1 10:39:31 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 01 Sep 2010 15:39:31 -0000 Subject: [llvm-commits] [llvm] r112707 - /llvm/trunk/utils/TableGen/EDEmitter.cpp Message-ID: <20100901153931.C97982A6C12C@llvm.org> Author: lattner Date: Wed Sep 1 10:39:31 2010 New Revision: 112707 URL: http://llvm.org/viewvc/llvm-project?rev=112707&view=rev Log: remove dead code. Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=112707&r1=112706&r2=112707&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/EDEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/EDEmitter.cpp Wed Sep 1 10:39:31 2010 @@ -84,34 +84,6 @@ } }; - class StructEmitter { - private: - std::string Name; - typedef std::pair member; - std::vector< member > Members; - public: - StructEmitter(const char *N) : Name(N) { - } - void addMember(const char *t, const char *n) { - member m(t, n); - Members.push_back(m); - } - void emit(raw_ostream &o, unsigned int &i) { - o.indent(i) << "struct " << Name.c_str() << " {" << "\n"; - i += 2; - - unsigned int index = 0; - unsigned int numMembers = Members.size(); - for (index = 0; index < numMembers; ++index) { - o.indent(i) << Members[index].first << " "; - o.indent(i) << Members[index].second << ";" << "\n"; - } - - i -= 2; - o.indent(i) << "};" << "\n"; - } - }; - class ConstantEmitter { public: virtual ~ConstantEmitter() { } @@ -126,10 +98,6 @@ const char* String; }; public: - LiteralConstantEmitter(const char *string) : - IsNumber(false), - String(string) { - } LiteralConstantEmitter(int number = 0) : IsNumber(true), Number(number) { @@ -139,11 +107,6 @@ Number = 0; String = string; } - void set(int number) { - IsNumber = true; - String = NULL; - Number = number; - } bool is(const char *string) { return !strcmp(String, string); } From sabre at nondot.org Wed Sep 1 10:44:05 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 01 Sep 2010 15:44:05 -0000 Subject: [llvm-commits] [llvm] r112708 - /llvm/trunk/unittests/Support/ValueHandleTest.cpp Message-ID: <20100901154405.B15CD2A6C12C@llvm.org> Author: lattner Date: Wed Sep 1 10:44:05 2010 New Revision: 112708 URL: http://llvm.org/viewvc/llvm-project?rev=112708&view=rev Log: zap dead code. Modified: llvm/trunk/unittests/Support/ValueHandleTest.cpp Modified: llvm/trunk/unittests/Support/ValueHandleTest.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/Support/ValueHandleTest.cpp?rev=112708&r1=112707&r2=112708&view=diff ============================================================================== --- llvm/trunk/unittests/Support/ValueHandleTest.cpp (original) +++ llvm/trunk/unittests/Support/ValueHandleTest.cpp Wed Sep 1 10:44:05 2010 @@ -35,7 +35,6 @@ class ConcreteCallbackVH : public CallbackVH { public: - ConcreteCallbackVH() : CallbackVH() {} ConcreteCallbackVH(Value *V) : CallbackVH(V) {} }; From sabre at nondot.org Wed Sep 1 11:00:50 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 01 Sep 2010 16:00:50 -0000 Subject: [llvm-commits] [llvm] r112711 - in /llvm/trunk: lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td test/CodeGen/ARM/mvncc.ll test/CodeGen/Thumb2/thumb2-mvncc.ll Message-ID: <20100901160050.B0D962A6C12C@llvm.org> Author: lattner Date: Wed Sep 1 11:00:50 2010 New Revision: 112711 URL: http://llvm.org/viewvc/llvm-project?rev=112711&view=rev Log: temporarily revert r112664, it is causing a decoding conflict, and the testcases should be merged. Removed: llvm/trunk/test/CodeGen/ARM/mvncc.ll llvm/trunk/test/CodeGen/Thumb2/thumb2-mvncc.ll Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=112711&r1=112710&r2=112711&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Wed Sep 1 11:00:50 2010 @@ -180,9 +180,6 @@ SDNode *SelectARMCMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag); - SDNode *OptimizeCMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, - ARMCC::CondCodes CCVal, SDValue CCR, - SDValue InFlag, bool IsThumb2); SDNode *SelectConcatVector(SDNode *N); @@ -1644,92 +1641,6 @@ return 0; } -/// OptimizeCMOVSoImmOp - It's possible to save an instruction or two be -/// recognizing that the TST and AND instructions perform the same function -/// (they "and" the two values). See inside for more details. -SDNode *ARMDAGToDAGISel:: -OptimizeCMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, - ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag, - bool IsThumb2) { - // Convert: - // - // tst.w r0, #256 - // mvn r0, #25 - // it eq - // moveq r0, #0 - // - // into: - // - // ands.w r0, r0, #256 - // it ne - // mvnne.w r0, #25 - // - if (InFlag.getOpcode() != ARMISD::CMPZ || - InFlag.getOperand(0).getOpcode() != ISD::AND) - return 0; - - // The true value needs to be zero, as that's the result of the AND - // instruction. - ConstantSDNode *True = dyn_cast(TrueVal); - if (!True || True->getZExtValue() != 0) - return 0; - - // Bail if the false value isn't an immediate. - ConstantSDNode *False = dyn_cast(FalseVal); - if (!False) - return 0; - - bool UseMVN = false; - if ((IsThumb2 && !Pred_t2_so_imm(FalseVal.getNode())) || - (!IsThumb2 && !Pred_so_imm(FalseVal.getNode()))) { - // The false value isn't a proper immediate. Check to see if we can use the - // bitwise NOT version. - if ((IsThumb2 && ARM_AM::getT2SOImmVal(~False->getZExtValue()) != -1) || - (!IsThumb2 && ARM_AM::getSOImmVal(~False->getZExtValue()) != -1)) { - UseMVN = true; - FalseVal = CurDAG->getTargetConstant(~False->getZExtValue(), MVT::i32); - } else { - return 0; - } - } else { - FalseVal = CurDAG->getTargetConstant(False->getZExtValue(), MVT::i32); - } - - // A comparison against zero corresponds with the flag AND sets if the result - // is zero. - ConstantSDNode *CmpVal = dyn_cast(InFlag.getOperand(1)); - if (!CmpVal || CmpVal->getZExtValue() != 0) - return 0; - - ARMCC::CondCodes NegCC = ARMCC::getOppositeCondition(CCVal); - SDValue OrigAnd = InFlag.getOperand(0); - SDValue NewAnd = - CurDAG->getNode(ARMISD::AND, N->getDebugLoc(), - CurDAG->getVTList(OrigAnd.getValueType(), MVT::Flag), - OrigAnd->getOperand(0), OrigAnd->getOperand(1)); - - unsigned Opcode = !UseMVN ? - (IsThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi) : - (IsThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi); - - SDValue Ops[] = { - NewAnd.getValue(0), - FalseVal, - CurDAG->getTargetConstant(NegCC, MVT::i32), - CCR, NewAnd.getValue(1) - }; - SDNode *ResNode = CurDAG->SelectNodeTo(N, Opcode, MVT::i32, Ops, 5); - - // Manually run "Select" on the newly created "ARMISD::AND" node to make - // sure that it's converted properly. - SDNode *AndNode = Select(NewAnd.getNode()); - if (AndNode && NewAnd.getNode() != AndNode && - NewAnd.getNode()->getOpcode() != ISD::DELETED_NODE) - ReplaceUses(NewAnd.getNode(), AndNode); - - return ResNode; -} - SDNode *ARMDAGToDAGISel:: SelectT2CMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) { @@ -1738,10 +1649,6 @@ return 0; if (Pred_t2_so_imm(TrueVal.getNode())) { - SDNode *ResNode = OptimizeCMOVSoImmOp(N, FalseVal, TrueVal, CCVal, CCR, - InFlag, true); - if (ResNode) return ResNode; - SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32); SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32); SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag }; @@ -1759,10 +1666,6 @@ return 0; if (Pred_so_imm(TrueVal.getNode())) { - SDNode *ResNode = OptimizeCMOVSoImmOp(N, FalseVal, TrueVal, CCVal, CCR, - InFlag, false); - if (ResNode) return ResNode; - SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32); SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32); SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag }; Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=112711&r1=112710&r2=112711&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Sep 1 11:00:50 2010 @@ -2419,14 +2419,6 @@ RegConstraint<"$false = $dst">, UnaryDP { let Inst{25} = 1; } - -def MVNCCi : AI1<0b1111, (outs GPR:$dst), - (ins GPR:$false, so_imm:$true), DPFrm, IIC_iCMOVi, - "mvn", "\t$dst, $true", - [/*(set GPR:$dst, (ARMcmov GPR:$false,so_imm_not:$true,imm:$cc,CCR:$ccr))*/]>, - RegConstraint<"$false = $dst">, UnaryDP { - let Inst{25} = 0; -} } // neverHasSideEffects //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=112711&r1=112710&r2=112711&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Sep 1 11:00:50 2010 @@ -2195,18 +2195,6 @@ let Inst{15} = 0; } -def t2MVNCCi : T2I<(outs rGPR:$dst), (ins rGPR:$false, t2_so_imm:$true), - IIC_iCMOVi, "mvn", ".w\t$dst, $true", -[/*(set rGPR:$dst,(ARMcmov rGPR:$false,t2_so_imm_not:$true,imm:$cc,CCR:$ccr))*/]>, - RegConstraint<"$false = $dst"> { - let Inst{31-27} = 0b11110; - let Inst{25} = 0; - let Inst{24-21} = 0b0011; - let Inst{20} = 0; // The S bit. - let Inst{19-16} = 0b1111; // Rn - let Inst{15} = 0; -} - class T2I_movcc_sh opcod, dag oops, dag iops, InstrItinClass itin, string opc, string asm, list pattern> : T2I { Removed: llvm/trunk/test/CodeGen/ARM/mvncc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/mvncc.ll?rev=112710&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/mvncc.ll (original) +++ llvm/trunk/test/CodeGen/ARM/mvncc.ll (removed) @@ -1,12 +0,0 @@ -; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s - -define i32 @f1(i32 %t) nounwind { -; CHECK: f1 -; CHECK-NOT: tst -; CHECK: and -; CHECK: mvnne - %and = and i32 %t, 256 - %tobool = icmp eq i32 %and, 0 - %retval.0 = select i1 %tobool, i32 0, i32 -26 - ret i32 %retval.0 -} Removed: llvm/trunk/test/CodeGen/Thumb2/thumb2-mvncc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-mvncc.ll?rev=112710&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-mvncc.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-mvncc.ll (removed) @@ -1,13 +0,0 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s - -define i32 @f1(i32 %t) nounwind { -; CHECK: f1 -; CHECK-NOT: tst -; CHECK: ands -; CHECK: it ne -; CHECK: mvnne - %and = and i32 %t, 256 - %tobool = icmp eq i32 %and, 0 - %retval.0 = select i1 %tobool, i32 0, i32 -26 - ret i32 %retval.0 -} From sabre at nondot.org Wed Sep 1 11:04:34 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 01 Sep 2010 16:04:34 -0000 Subject: [llvm-commits] [llvm] r112712 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20100901160435.07A002A6C12C@llvm.org> Author: lattner Date: Wed Sep 1 11:04:34 2010 New Revision: 112712 URL: http://llvm.org/viewvc/llvm-project?rev=112712&view=rev Log: zap dead code. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=112712&r1=112711&r2=112712&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Sep 1 11:04:34 2010 @@ -167,8 +167,8 @@ }; - ARMOperand(KindTy K, SMLoc S, SMLoc E) - : Kind(K), StartLoc(S), EndLoc(E) {} + //ARMOperand(KindTy K, SMLoc S, SMLoc E) + // : Kind(K), StartLoc(S), EndLoc(E) {} ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() { Kind = o.Kind; From sabre at nondot.org Wed Sep 1 11:06:39 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 01 Sep 2010 16:06:39 -0000 Subject: [llvm-commits] [llvm] r112713 - /llvm/trunk/lib/Linker/LinkModules.cpp Message-ID: <20100901160639.4F13B2A6C12C@llvm.org> Author: lattner Date: Wed Sep 1 11:06:39 2010 New Revision: 112713 URL: http://llvm.org/viewvc/llvm-project?rev=112713&view=rev Log: dead code patrol Modified: llvm/trunk/lib/Linker/LinkModules.cpp Modified: llvm/trunk/lib/Linker/LinkModules.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Linker/LinkModules.cpp?rev=112713&r1=112712&r2=112713&view=diff ============================================================================== --- llvm/trunk/lib/Linker/LinkModules.cpp (original) +++ llvm/trunk/lib/Linker/LinkModules.cpp Wed Sep 1 11:06:39 2010 @@ -97,15 +97,6 @@ return 0; } - /// erase - Remove the specified type, returning true if it was in the set. - bool erase(const Type *Ty) { - if (!TheMap.erase(Ty)) - return false; - if (Ty->isAbstract()) - Ty->removeAbstractTypeUser(this); - return true; - } - /// insert - This returns true if the pointer was new to the set, false if it /// was already in the set. bool insert(const Type *Src, const Type *Dst) { From sabre at nondot.org Wed Sep 1 11:11:17 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 01 Sep 2010 16:11:17 -0000 Subject: [llvm-commits] [llvm] r112714 - in /llvm/trunk: Makefile.rules lib/CompilerDriver/Makefile Message-ID: <20100901161117.E26B42A6C12C@llvm.org> Author: lattner Date: Wed Sep 1 11:11:17 2010 New Revision: 112714 URL: http://llvm.org/viewvc/llvm-project?rev=112714&view=rev Log: have the makefiles check the llvm-config error code instead of charging on an producing weird link errors. Patch by Yuri Gribov! Modified: llvm/trunk/Makefile.rules llvm/trunk/lib/CompilerDriver/Makefile Modified: llvm/trunk/Makefile.rules URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=112714&r1=112713&r2=112714&view=diff ============================================================================== --- llvm/trunk/Makefile.rules (original) +++ llvm/trunk/Makefile.rules Wed Sep 1 11:11:17 2010 @@ -917,9 +917,20 @@ LLVMLibsOptions += -lLLVM-$(LLVMVersion) LLVMLibsPaths += $(SharedLibDir)/$(SharedPrefix)LLVM-$(LLVMVersion)$(SHLIBEXT) else -LLVMLibsOptions += $(shell $(LLVM_CONFIG) --libs $(LINK_COMPONENTS)) -LLVMLibsPaths += $(LLVM_CONFIG) \ - $(shell $(LLVM_CONFIG) --libfiles $(LINK_COMPONENTS)) + +ifndef NO_LLVM_CONFIG +LLVMConfigLibs := $(shell $(LLVM_CONFIG) --libs $(LINK_COMPONENTS) || echo Error) +ifeq ($(LLVMConfigLibs),Error) +$(error llvm-config --libs failed) +endif +LLVMLibsOptions += $(LLVMConfigLibs) +LLVMConfigLibfiles := $(shell $(LLVM_CONFIG) --libfiles $(LINK_COMPONENTS) || echo Error) +ifeq ($(LLVMConfigLibfiles),Error) +$(error llvm-config --libfiles failed) +endif +LLVMLibsPaths += $(LLVM_CONFIG) $(LLVMConfigLibfiles) +endif + endif endif endif Modified: llvm/trunk/lib/CompilerDriver/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CompilerDriver/Makefile?rev=112714&r1=112713&r2=112714&view=diff ============================================================================== --- llvm/trunk/lib/CompilerDriver/Makefile (original) +++ llvm/trunk/lib/CompilerDriver/Makefile Wed Sep 1 11:11:17 2010 @@ -10,9 +10,11 @@ LEVEL = ../.. # We don't want this library to appear in `llvm-config --libs` output, so its -# name doesn't start with "LLVM". +# name doesn't start with "LLVM" and NO_LLVM_CONFIG is set. LIBRARYNAME = CompilerDriver LINK_COMPONENTS = support system +NO_LLVM_CONFIG = 1 + include $(LEVEL)/Makefile.common From tonic at nondot.org Wed Sep 1 11:16:58 2010 From: tonic at nondot.org (Tanya Lattner) Date: Wed, 1 Sep 2010 09:16:58 -0700 Subject: [llvm-commits] [www] r112658 - in /www/trunk: devmtg/index.html header.incl index.html In-Reply-To: References: <20100831222214.16D332A6C12D@llvm.org> Message-ID: On Sep 1, 2010, at 2:44 AM, NAKAMURA Takumi wrote: > Tanya, > >> +

      November 4, 2010

      > > Is the canonical host "llvm.org", not www.llvm.org? > They are both A records, but I don't control the DNS record. If you are asking which is the one thats preferred, its llvm.org. I don't know why I used www :) -Tanya From clattner at apple.com Wed Sep 1 11:21:11 2010 From: clattner at apple.com (Chris Lattner) Date: Wed, 1 Sep 2010 09:21:11 -0700 Subject: [llvm-commits] [llvm] r112706 - in /llvm/trunk: include/llvm/Support/ lib/Support/ tools/bugpoint/ tools/llc/ tools/llvm-as/ tools/llvm-dis/ tools/llvm-extract/ tools/llvm-ld/ tools/llvm-link/ tools/llvm-mc/ tools/lto/ tools/opt/ utils/FileUpdate/ utils/TableGen/ In-Reply-To: <20100901142041.DD2B52A6C12C@llvm.org> References: <20100901142041.DD2B52A6C12C@llvm.org> Message-ID: <47E6780E-4387-4F92-BC36-53051E7F625C@apple.com> On Sep 1, 2010, at 7:20 AM, Dan Gohman wrote: > Author: djg > Date: Wed Sep 1 09:20:41 2010 > New Revision: 112706 > > URL: http://llvm.org/viewvc/llvm-project?rev=112706&view=rev > Log: > Make tool_output_file's raw_ostream instance a member variable instead > of a base class. > > This makes it possible to unregister the file from FilesToRemove when > the file is done. Also, this eliminates the need for > formatted_tool_output_file. Thanks Dan! As a follow-up, can you move tool_output_file out to its own header (not in raw_ostream.h)? -Chris From gohman at apple.com Wed Sep 1 12:16:16 2010 From: gohman at apple.com (Dan Gohman) Date: Wed, 1 Sep 2010 10:16:16 -0700 Subject: [llvm-commits] [llvm] r111665 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp test/Transforms/InstCombine/2010-08-19-StoreNarrowing.ll In-Reply-To: References: <20100820182443.4552E2A6C12E@llvm.org> <74D55FC8-5CD1-4F1D-8512-4C4BFC06AD4C@mac.com> Message-ID: On Aug 30, 2010, at 5:17 PM, Chris Lattner wrote: > > On Aug 30, 2010, at 4:47 PM, Owen Anderson wrote: > >> >> On Aug 30, 2010, at 2:26 PM, Chris Lattner wrote: >>> >>> >>>> + ConstantInt *CI1 =0, *CI2 = 0; >>>> + Value *Ld = 0; >>>> + if (getTargetData() && >>>> + match(SI.getValueOperand(), >>>> + m_And(m_Or(m_Value(Ld), m_ConstantInt(CI1)), m_ConstantInt(CI2))) && >>>> + isa(Ld) && >>>> + equivalentAddressValues(cast(Ld)->getPointerOperand(), Ptr)) { >>> >>> I don't see where you check to make sure you don't have something like: >>> >>> x = load P >>> store 123 -> Q ;; might alias P! >>> x' = stuff(x) >>> store x' -> P >>> >>> How do you know the loaded value hasn't been changed in memory? Also, you don't check for a volatile load here. >> >> Good catch. Is this even reasonably fixable within the context of instcombine? It looks like we'd want to use something like memdep to guarantee that there are no intervening writes to P. > > This is best done in dag combine, where the chains tell you this. Please revert your instcombine change. Hi Chris, is the memory dependence issue the only reason to prefer to use dagcombine here instead of instcombine? This can be solved in instcombine also using FindAvailableLoadedValue. Narrowing stores and eliminating loads can open up a variety of optimization opportunities. This suggests that instcombine is a better place for this optimization. Dan From echristo at apple.com Wed Sep 1 12:29:10 2010 From: echristo at apple.com (Eric Christopher) Date: Wed, 01 Sep 2010 17:29:10 -0000 Subject: [llvm-commits] [llvm] r112719 - in /llvm/trunk: include/llvm/Transforms/Utils/SSAUpdater.h lib/CodeGen/DwarfEHPrepare.cpp lib/Transforms/Scalar/GVN.cpp lib/Transforms/Scalar/JumpThreading.cpp lib/Transforms/Scalar/LICM.cpp lib/Transforms/Scalar/LoopRotation.cpp lib/Transforms/Utils/LCSSA.cpp lib/Transforms/Utils/SSAUpdater.cpp Message-ID: <20100901172910.55FF52A6C12C@llvm.org> Author: echristo Date: Wed Sep 1 12:29:10 2010 New Revision: 112719 URL: http://llvm.org/viewvc/llvm-project?rev=112719&view=rev Log: Speculatively revert 112699 and 112702, they seem to be causing self host errors on clang-x86-64. Modified: llvm/trunk/include/llvm/Transforms/Utils/SSAUpdater.h llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp llvm/trunk/lib/Transforms/Scalar/GVN.cpp llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp llvm/trunk/lib/Transforms/Scalar/LICM.cpp llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp llvm/trunk/lib/Transforms/Utils/LCSSA.cpp llvm/trunk/lib/Transforms/Utils/SSAUpdater.cpp Modified: llvm/trunk/include/llvm/Transforms/Utils/SSAUpdater.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/Utils/SSAUpdater.h?rev=112719&r1=112718&r2=112719&view=diff ============================================================================== --- llvm/trunk/include/llvm/Transforms/Utils/SSAUpdater.h (original) +++ llvm/trunk/include/llvm/Transforms/Utils/SSAUpdater.h Wed Sep 1 12:29:10 2010 @@ -36,11 +36,9 @@ //typedef DenseMap AvailableValsTy; void *AV; - /// ProtoType holds the type of the values being rewritten. - const Type *ProtoType; - - // PHI nodes are given a name based on ProtoName. - std::string ProtoName; + /// PrototypeValue is an arbitrary representative value, which we derive names + /// and a type for PHI nodes. + Value *PrototypeValue; /// InsertedPHIs - If this is non-null, the SSAUpdater adds all PHI nodes that /// it creates to the vector. @@ -53,8 +51,8 @@ ~SSAUpdater(); /// Initialize - Reset this object to get ready for a new set of SSA - /// updates with type 'Ty'. PHI nodes get a name based on 'Name'. - void Initialize(const Type *Ty, StringRef Name); + /// updates. ProtoValue is the value used to name PHI nodes. + void Initialize(Value *ProtoValue); /// AddAvailableValue - Indicate that a rewritten value is available at the /// end of the specified block with the specified value. Modified: llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp?rev=112719&r1=112718&r2=112719&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp (original) +++ llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp Wed Sep 1 12:29:10 2010 @@ -25,12 +25,12 @@ #include "llvm/Support/CallSite.h" #include "llvm/Target/TargetLowering.h" #include "llvm/Transforms/Utils/BasicBlockUtils.h" -#include "llvm/Transforms/Utils/SSAUpdater.h" using namespace llvm; STATISTIC(NumLandingPadsSplit, "Number of landing pads split"); STATISTIC(NumUnwindsLowered, "Number of unwind instructions lowered"); STATISTIC(NumExceptionValuesMoved, "Number of eh.exception calls moved"); +STATISTIC(NumStackTempsIntroduced, "Number of stack temporaries introduced"); namespace { class DwarfEHPrepare : public FunctionPass { @@ -62,11 +62,24 @@ typedef SmallPtrSet BBSet; BBSet LandingPads; + // Stack temporary used to hold eh.exception values. + AllocaInst *ExceptionValueVar; + bool NormalizeLandingPads(); bool LowerUnwinds(); bool MoveExceptionValueCalls(); + bool FinishStackTemporaries(); Instruction *CreateExceptionValueCall(BasicBlock *BB); + Instruction *CreateValueLoad(BasicBlock *BB); + + /// CreateReadOfExceptionValue - Return the result of the eh.exception + /// intrinsic by calling the intrinsic if in a landing pad, or loading it + /// from the exception value variable otherwise. + Instruction *CreateReadOfExceptionValue(BasicBlock *BB) { + return LandingPads.count(BB) ? + CreateExceptionValueCall(BB) : CreateValueLoad(BB); + } /// CleanupSelectors - Any remaining eh.selector intrinsic calls which still /// use the "llvm.eh.catch.all.value" call need to convert to using its @@ -104,7 +117,7 @@ virtual bool runOnFunction(Function &Fn); - // getAnalysisUsage - We need the dominator tree for handling URoR. + // getAnalysisUsage - We need dominance frontiers for memory promotion. virtual void getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired(); AU.addPreserved(); @@ -504,7 +517,7 @@ // Create the call... CallInst *CI = CallInst::Create(RewindFunction, - CreateExceptionValueCall(TI->getParent()), + CreateReadOfExceptionValue(TI->getParent()), "", TI); CI->setCallingConv(TLI->getLibcallCallingConv(RTLIB::UNWIND_RESUME)); // ...followed by an UnreachableInst. @@ -520,11 +533,9 @@ } /// MoveExceptionValueCalls - Ensure that eh.exception is only ever called from -/// landing pads by replacing calls outside of landing pads with direct use of -/// a register holding the appropriate value; this requires adding calls inside -/// all landing pads to initialize the register. Also, move eh.exception calls -/// inside landing pads to the start of the landing pad (optional, but may make -/// things simpler for later passes). +/// landing pads by replacing calls outside of landing pads with loads from a +/// stack temporary. Move eh.exception calls inside landing pads to the start +/// of the landing pad (optional, but may make things simpler for later passes). bool DwarfEHPrepare::MoveExceptionValueCalls() { // If the eh.exception intrinsic is not declared in the module then there is // nothing to do. Speed up compilation by checking for this common case. @@ -534,87 +545,49 @@ bool Changed = false; - // Move calls to eh.exception that are inside a landing pad to the start of - // the landing pad. - for (BBSet::const_iterator LI = LandingPads.begin(), LE = LandingPads.end(); - LI != LE; ++LI) { - BasicBlock *LP = *LI; - for (BasicBlock::iterator II = LP->getFirstNonPHIOrDbg(), IE = LP->end(); - II != IE;) - if (EHExceptionInst *EI = dyn_cast(II++)) { - // Found a call to eh.exception. - if (!EI->use_empty()) { - // If there is already a call to eh.exception at the start of the - // landing pad, then get hold of it; otherwise create such a call. - Value *CallAtStart = CreateExceptionValueCall(LP); - - // If the call was at the start of a landing pad then leave it alone. - if (EI == CallAtStart) - continue; - EI->replaceAllUsesWith(CallAtStart); + for (Function::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) { + for (BasicBlock::iterator II = BB->begin(), E = BB->end(); II != E;) + if (IntrinsicInst *CI = dyn_cast(II++)) + if (CI->getIntrinsicID() == Intrinsic::eh_exception) { + if (!CI->use_empty()) { + Value *ExceptionValue = CreateReadOfExceptionValue(BB); + if (CI == ExceptionValue) { + // The call was at the start of a landing pad - leave it alone. + assert(LandingPads.count(BB) && + "Created eh.exception call outside landing pad!"); + continue; + } + CI->replaceAllUsesWith(ExceptionValue); + } + CI->eraseFromParent(); + ++NumExceptionValuesMoved; + Changed = true; } - EI->eraseFromParent(); - ++NumExceptionValuesMoved; - Changed = true; - } } - // Look for calls to eh.exception that are not in a landing pad. If one is - // found, then a register that holds the exception value will be created in - // each landing pad, and the SSAUpdater will be used to compute the values - // returned by eh.exception calls outside of landing pads. - SSAUpdater SSA; - - // Remember where we found the eh.exception call, to avoid rescanning earlier - // basic blocks which we already know contain no eh.exception calls. - bool FoundCallOutsideLandingPad = false; - Function::iterator BB = F->begin(); - for (Function::iterator BE = F->end(); BB != BE; ++BB) { - // Skip over landing pads. - if (LandingPads.count(BB)) - continue; - - for (BasicBlock::iterator II = BB->getFirstNonPHIOrDbg(), IE = BB->end(); - II != IE; ++II) - if (isa(II)) { - SSA.Initialize(II->getType(), II->getName()); - FoundCallOutsideLandingPad = true; - break; - } + return Changed; +} - if (FoundCallOutsideLandingPad) - break; - } +/// FinishStackTemporaries - If we introduced a stack variable to hold the +/// exception value then initialize it in each landing pad. +bool DwarfEHPrepare::FinishStackTemporaries() { + if (!ExceptionValueVar) + // Nothing to do. + return false; - // If all calls to eh.exception are in landing pads then we are done. - if (!FoundCallOutsideLandingPad) - return Changed; + bool Changed = false; - // Add a call to eh.exception at the start of each landing pad, and tell the - // SSAUpdater that this is the value produced by the landing pad. + // Make sure that there is a store of the exception value at the start of + // each landing pad. for (BBSet::iterator LI = LandingPads.begin(), LE = LandingPads.end(); - LI != LE; ++LI) - SSA.AddAvailableValue(*LI, CreateExceptionValueCall(*LI)); - - // Now turn all calls to eh.exception that are not in a landing pad into a use - // of the appropriate register. - for (Function::iterator BE = F->end(); BB != BE; ++BB) { - // Skip over landing pads. - if (LandingPads.count(BB)) - continue; - - for (BasicBlock::iterator II = BB->getFirstNonPHIOrDbg(), IE = BB->end(); - II != IE;) - if (EHExceptionInst *EI = dyn_cast(II++)) { - // Found a call to eh.exception, replace it with the value from any - // upstream landing pad(s). - EI->replaceAllUsesWith(SSA.GetValueAtEndOfBlock(BB)); - EI->eraseFromParent(); - ++NumExceptionValuesMoved; - } + LI != LE; ++LI) { + Instruction *ExceptionValue = CreateReadOfExceptionValue(*LI); + Instruction *Store = new StoreInst(ExceptionValue, ExceptionValueVar); + Store->insertAfter(ExceptionValue); + Changed = true; } - return true; + return Changed; } /// CreateExceptionValueCall - Insert a call to the eh.exception intrinsic at @@ -637,11 +610,35 @@ return CallInst::Create(ExceptionValueIntrinsic, "eh.value.call", Start); } +/// CreateValueLoad - Insert a load of the exception value stack variable +/// (creating it if necessary) at the start of the basic block (unless +/// there already is a load, in which case the existing load is returned). +Instruction *DwarfEHPrepare::CreateValueLoad(BasicBlock *BB) { + Instruction *Start = BB->getFirstNonPHIOrDbg(); + // Is this a load of the exception temporary? + if (ExceptionValueVar) + if (LoadInst* LI = dyn_cast(Start)) + if (LI->getPointerOperand() == ExceptionValueVar) + // Reuse the existing load. + return Start; + + // Create the temporary if we didn't already. + if (!ExceptionValueVar) { + ExceptionValueVar = new AllocaInst(PointerType::getUnqual( + Type::getInt8Ty(BB->getContext())), "eh.value", F->begin()->begin()); + ++NumStackTempsIntroduced; + } + + // Load the value. + return new LoadInst(ExceptionValueVar, "eh.value.load", Start); +} + bool DwarfEHPrepare::runOnFunction(Function &Fn) { bool Changed = false; // Initialize internal state. DT = &getAnalysis(); + ExceptionValueVar = 0; F = &Fn; // Ensure that only unwind edges end at landing pads (a landing pad is a @@ -656,6 +653,11 @@ // Move eh.exception calls to landing pads. Changed |= MoveExceptionValueCalls(); + // Initialize any stack temporaries we introduced. + Changed |= FinishStackTemporaries(); + + // TODO: Turn any stack temporaries into registers if possible. + Changed |= HandleURoRInvokes(); LandingPads.clear(); Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=112719&r1=112718&r2=112719&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Wed Sep 1 12:29:10 2010 @@ -1310,7 +1310,7 @@ // Otherwise, we have to construct SSA form. SmallVector NewPHIs; SSAUpdater SSAUpdate(&NewPHIs); - SSAUpdate.Initialize(LI->getType(), LI->getName()); + SSAUpdate.Initialize(LI); const Type *LoadTy = LI->getType(); Modified: llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp?rev=112719&r1=112718&r2=112719&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Wed Sep 1 12:29:10 2010 @@ -1526,7 +1526,7 @@ // We found a use of I outside of BB. Rename all uses of I that are outside // its block to be uses of the appropriate PHI node etc. See ValuesInBlocks // with the two values we know. - SSAUpdate.Initialize(I->getType(), I->getName()); + SSAUpdate.Initialize(I); SSAUpdate.AddAvailableValue(BB, I); SSAUpdate.AddAvailableValue(NewBB, ValueMapping[I]); @@ -1681,7 +1681,7 @@ // We found a use of I outside of BB. Rename all uses of I that are outside // its block to be uses of the appropriate PHI node etc. See ValuesInBlocks // with the two values we know. - SSAUpdate.Initialize(I->getType(), I->getName()); + SSAUpdate.Initialize(I); SSAUpdate.AddAvailableValue(BB, I); SSAUpdate.AddAvailableValue(PredBB, ValueMapping[I]); Modified: llvm/trunk/lib/Transforms/Scalar/LICM.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LICM.cpp?rev=112719&r1=112718&r2=112719&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LICM.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LICM.cpp Wed Sep 1 12:29:10 2010 @@ -526,7 +526,7 @@ SSAUpdater SSA(&NewPHIs); if (!I.use_empty()) - SSA.Initialize(I.getType(), I.getName()); + SSA.Initialize(&I); // Insert a copy of the instruction in each exit block of the loop that is // dominated by the instruction. Each exit block is known to only be in the @@ -728,7 +728,7 @@ SomeValue = LoopUses[0]; else SomeValue = cast(LoopUses[0])->getOperand(0); - SSA.Initialize(SomeValue->getType(), SomeValue->getName()); + SSA.Initialize(SomeValue); // First step: bucket up uses of the pointers by the block they occur in. // This is important because we have to handle multiple defs/uses in a block Modified: llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp?rev=112719&r1=112718&r2=112719&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp Wed Sep 1 12:29:10 2010 @@ -221,7 +221,7 @@ // The value now exits in two versions: the initial value in the preheader // and the loop "next" value in the original header. - SSA.Initialize(OrigHeaderVal->getType(), OrigHeaderVal->getName()); + SSA.Initialize(OrigHeaderVal); SSA.AddAvailableValue(OrigHeader, OrigHeaderVal); SSA.AddAvailableValue(OrigPreHeader, OrigPreHeaderVal); Modified: llvm/trunk/lib/Transforms/Utils/LCSSA.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/LCSSA.cpp?rev=112719&r1=112718&r2=112719&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/LCSSA.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/LCSSA.cpp Wed Sep 1 12:29:10 2010 @@ -206,7 +206,7 @@ DomTreeNode *DomNode = DT->getNode(DomBB); SSAUpdater SSAUpdate; - SSAUpdate.Initialize(Inst->getType(), Inst->getName()); + SSAUpdate.Initialize(Inst); // Insert the LCSSA phi's into all of the exit blocks dominated by the // value, and add them to the Phi's map. Modified: llvm/trunk/lib/Transforms/Utils/SSAUpdater.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SSAUpdater.cpp?rev=112719&r1=112718&r2=112719&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SSAUpdater.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SSAUpdater.cpp Wed Sep 1 12:29:10 2010 @@ -29,21 +29,20 @@ } SSAUpdater::SSAUpdater(SmallVectorImpl *NewPHI) - : AV(0), ProtoType(0), ProtoName(), InsertedPHIs(NewPHI) {} + : AV(0), PrototypeValue(0), InsertedPHIs(NewPHI) {} SSAUpdater::~SSAUpdater() { delete &getAvailableVals(AV); } /// Initialize - Reset this object to get ready for a new set of SSA -/// updates with type 'Ty'. PHI nodes get a name based on 'Name'. -void SSAUpdater::Initialize(const Type *Ty, StringRef Name) { +/// updates. ProtoValue is the value used to name PHI nodes. +void SSAUpdater::Initialize(Value *ProtoValue) { if (AV == 0) AV = new AvailableValsTy(); else getAvailableVals(AV).clear(); - ProtoType = Ty; - ProtoName = Name; + PrototypeValue = ProtoValue; } /// HasValueForBlock - Return true if the SSAUpdater already has a value for @@ -55,8 +54,8 @@ /// AddAvailableValue - Indicate that a rewritten value is available in the /// specified block with the specified value. void SSAUpdater::AddAvailableValue(BasicBlock *BB, Value *V) { - assert(ProtoType != 0 && "Need to initialize SSAUpdater"); - assert(ProtoType == V->getType() && + assert(PrototypeValue != 0 && "Need to initialize SSAUpdater"); + assert(PrototypeValue->getType() == V->getType() && "All rewritten values must have the same type"); getAvailableVals(AV)[BB] = V; } @@ -149,7 +148,7 @@ // If there are no predecessors, just return undef. if (PredValues.empty()) - return UndefValue::get(ProtoType); + return UndefValue::get(PrototypeValue->getType()); // Otherwise, if all the merged values are the same, just use it. if (SingularValue != 0) @@ -169,7 +168,9 @@ } // Ok, we have no way out, insert a new one now. - PHINode *InsertedPHI = PHINode::Create(ProtoType, ProtoName, &BB->front()); + PHINode *InsertedPHI = PHINode::Create(PrototypeValue->getType(), + PrototypeValue->getName(), + &BB->front()); InsertedPHI->reserveOperandSpace(PredValues.size()); // Fill in all the predecessors of the PHI. @@ -281,14 +282,15 @@ /// GetUndefVal - Get an undefined value of the same type as the value /// being handled. static Value *GetUndefVal(BasicBlock *BB, SSAUpdater *Updater) { - return UndefValue::get(Updater->ProtoType); + return UndefValue::get(Updater->PrototypeValue->getType()); } /// CreateEmptyPHI - Create a new PHI instruction in the specified block. /// Reserve space for the operands but do not fill them in yet. static Value *CreateEmptyPHI(BasicBlock *BB, unsigned NumPreds, SSAUpdater *Updater) { - PHINode *PHI = PHINode::Create(Updater->ProtoType, Updater->ProtoName, + PHINode *PHI = PHINode::Create(Updater->PrototypeValue->getType(), + Updater->PrototypeValue->getName(), &BB->front()); PHI->reserveOperandSpace(NumPreds); return PHI; From echristo at apple.com Wed Sep 1 12:32:34 2010 From: echristo at apple.com (Eric Christopher) Date: Wed, 1 Sep 2010 10:32:34 -0700 Subject: [llvm-commits] [llvm] r112702 - /llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp In-Reply-To: <20100901140747.44F3A2A6C12C@llvm.org> References: <20100901140747.44F3A2A6C12C@llvm.org> Message-ID: <34CBA870-D2B9-48DD-8D62-F36A924F93A7@apple.com> Hi Duncan! On Sep 1, 2010, at 7:07 AM, Duncan Sands wrote: > Use the SSAUpdator to turn calls to eh.exception that are not in a > landing pad into uses of registers rather than loads from a stack > slot. Doesn't touch the 'orrible hack code - Bill needs to persuade > me harder :) As you saw last night this seems to cause a self-host failure on clang-x86_64-darwin. The failure mode isn't very exciting or illuminating: command timed out: 1200 seconds without output, killing pid 8844 process killed by signal 9 program finished with exit code -1 elapsedTime=1880.724556 I've speculatively reverted this and the EHPrepare patch that depended upon it. Thanks! -eric From geek4civic at gmail.com Wed Sep 1 13:01:21 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Thu, 2 Sep 2010 03:01:21 +0900 Subject: [llvm-commits] [PATCH] test/Transforms/TailDup/2008-06-11-AvoidDupLoopHeader.ll Message-ID: Hello, everyone. This test passes unexpectedly on bash-less environment. ; RUN: opt < %s -tailduplicate -taildup-threshold=3 -stats -disable-output | not grep tailduplicate The output of opt -stats must be sent to stderr. Confirmed on mingw, cygwin and centos5. good night...Takumi -------------- next part -------------- diff --git a/test/Transforms/TailDup/2008-06-11-AvoidDupLoopHeader.ll b/test/Transforms/TailDup/2008-06-11-AvoidDupLoopHeader.ll index 88a5656..03e99bc 100644 --- a/test/Transforms/TailDup/2008-06-11-AvoidDupLoopHeader.ll +++ b/test/Transforms/TailDup/2008-06-11-AvoidDupLoopHeader.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -tailduplicate -taildup-threshold=3 -stats -disable-output | not grep tailduplicate +; RUN: opt < %s -tailduplicate -taildup-threshold=3 -stats -disable-output |& not grep tailduplicate ; XFAIL: * define i32 @foo(i32 %l) nounwind { From echristo at apple.com Wed Sep 1 13:01:32 2010 From: echristo at apple.com (Eric Christopher) Date: Wed, 01 Sep 2010 18:01:32 -0000 Subject: [llvm-commits] [llvm] r112721 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20100901180132.4EEBB2A6C12C@llvm.org> Author: echristo Date: Wed Sep 1 13:01:32 2010 New Revision: 112721 URL: http://llvm.org/viewvc/llvm-project?rev=112721&view=rev Log: Add some more load types in. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=112721&r1=112720&r2=112721&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Wed Sep 1 13:01:32 2010 @@ -110,6 +110,7 @@ // Utility routines. private: bool isTypeLegal(const Type *Ty, EVT &VT); + bool isLoadTypeLegal(const Type *Ty, EVT &VT); bool ARMEmitLoad(EVT VT, unsigned &ResultReg, unsigned Reg, int Offset); bool ARMLoadAlloca(const Instruction *I); bool ARMComputeRegOffset(const Value *Obj, unsigned &Reg, int &Offset); @@ -317,12 +318,23 @@ // Only handle simple types. if (VT == MVT::Other || !VT.isSimple()) return false; - + // Handle all legal types, i.e. a register that will directly hold this // value. return TLI.isTypeLegal(VT); } +bool ARMFastISel::isLoadTypeLegal(const Type *Ty, EVT &VT) { + if (isTypeLegal(Ty, VT)) return true; + + // If this is a type than can be sign or zero-extended to a basic operation + // go ahead and accept it now. + if (VT == MVT::i8 || VT == MVT::i16) + return true; + + return false; +} + // Computes the Reg+Offset to get to an object. bool ARMFastISel::ARMComputeRegOffset(const Value *Obj, unsigned &Reg, int &Offset) { @@ -403,6 +415,14 @@ default: assert(false && "Trying to emit for an unhandled type!"); return false; + case MVT::i16: + Opc = isThumb ? ARM::tLDRH : ARM::LDRH; + VT = MVT::i32; + break; + case MVT::i8: + Opc = isThumb ? ARM::tLDRB : ARM::LDRB; + VT = MVT::i32; + break; case MVT::i32: Opc = isThumb ? ARM::tLDR : ARM::LDR; break; @@ -432,7 +452,7 @@ // Verify we have a legal type before going any further. EVT VT; - if (!isTypeLegal(I->getType(), VT)) + if (!isLoadTypeLegal(I->getType(), VT)) return false; // Our register and offset with innocuous defaults. From resistor at mac.com Wed Sep 1 13:27:22 2010 From: resistor at mac.com (Owen Anderson) Date: Wed, 01 Sep 2010 18:27:22 -0000 Subject: [llvm-commits] [llvm] r112722 - /llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Message-ID: <20100901182722.F2D4D2A6C12C@llvm.org> Author: resistor Date: Wed Sep 1 13:27:22 2010 New Revision: 112722 URL: http://llvm.org/viewvc/llvm-project?rev=112722&view=rev Log: JumpThreading keeps LazyValueInfo up to date, so we don't need to rerun it if we schedule another LVI-using pass afterwards. Modified: llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Modified: llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp?rev=112722&r1=112721&r2=112722&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Wed Sep 1 13:27:22 2010 @@ -100,8 +100,10 @@ bool runOnFunction(Function &F); virtual void getAnalysisUsage(AnalysisUsage &AU) const { - if (EnableLVI) + if (EnableLVI) { AU.addRequired(); + AU.addPreserved(); + } } void FindLoopHeaders(Function &F); From resistor at mac.com Wed Sep 1 13:30:15 2010 From: resistor at mac.com (Owen Anderson) Date: Wed, 01 Sep 2010 18:30:15 -0000 Subject: [llvm-commits] [llvm] r112723 - /llvm/trunk/include/llvm/Support/StandardPasses.h Message-ID: <20100901183015.9BAA42A6C12C@llvm.org> Author: resistor Date: Wed Sep 1 13:30:15 2010 New Revision: 112723 URL: http://llvm.org/viewvc/llvm-project?rev=112723&view=rev Log: Tentatively add correlated value propagation to the set of standard passes. Modified: llvm/trunk/include/llvm/Support/StandardPasses.h Modified: llvm/trunk/include/llvm/Support/StandardPasses.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/StandardPasses.h?rev=112723&r1=112722&r2=112723&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/StandardPasses.h (original) +++ llvm/trunk/include/llvm/Support/StandardPasses.h Wed Sep 1 13:30:15 2010 @@ -146,6 +146,7 @@ // opened up by them. PM->add(createInstructionCombiningPass()); PM->add(createJumpThreadingPass()); // Thread jumps + PM->add(createCorrelatedValuePropagationPass()); PM->add(createDeadStoreEliminationPass()); // Delete dead stores PM->add(createAggressiveDCEPass()); // Delete dead instructions PM->add(createCFGSimplificationPass()); // Merge & remove BBs From isanbard at gmail.com Wed Sep 1 13:32:56 2010 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 01 Sep 2010 18:32:56 -0000 Subject: [llvm-commits] [llvm] r112724 - /llvm/trunk/test/Transforms/TailDup/2008-06-11-AvoidDupLoopHeader.ll Message-ID: <20100901183256.4D1FC2A6C12C@llvm.org> Author: void Date: Wed Sep 1 13:32:56 2010 New Revision: 112724 URL: http://llvm.org/viewvc/llvm-project?rev=112724&view=rev Log: The output of opt -stats must be sent to stderr. Patch by NAKAMURA Takumi! Modified: llvm/trunk/test/Transforms/TailDup/2008-06-11-AvoidDupLoopHeader.ll Modified: llvm/trunk/test/Transforms/TailDup/2008-06-11-AvoidDupLoopHeader.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/TailDup/2008-06-11-AvoidDupLoopHeader.ll?rev=112724&r1=112723&r2=112724&view=diff ============================================================================== --- llvm/trunk/test/Transforms/TailDup/2008-06-11-AvoidDupLoopHeader.ll (original) +++ llvm/trunk/test/Transforms/TailDup/2008-06-11-AvoidDupLoopHeader.ll Wed Sep 1 13:32:56 2010 @@ -1,4 +1,4 @@ -; RUN: opt < %s -tailduplicate -taildup-threshold=3 -stats -disable-output | not grep tailduplicate +; RUN: opt < %s -tailduplicate -taildup-threshold=3 -stats -disable-output |& not grep tailduplicate ; XFAIL: * define i32 @foo(i32 %l) nounwind { From wendling at apple.com Wed Sep 1 13:33:49 2010 From: wendling at apple.com (Bill Wendling) Date: Wed, 1 Sep 2010 11:33:49 -0700 Subject: [llvm-commits] [PATCH] test/Transforms/TailDup/2008-06-11-AvoidDupLoopHeader.ll In-Reply-To: References: Message-ID: Applied in r112724. Thanks! -bw On Sep 1, 2010, at 11:01 AM, NAKAMURA Takumi wrote: > Hello, everyone. > > This test passes unexpectedly on bash-less environment. > > ; RUN: opt < %s -tailduplicate -taildup-threshold=3 -stats > -disable-output | not grep tailduplicate > > The output of opt -stats must be sent to stderr. > Confirmed on mingw, cygwin and centos5. > > > good night...Takumi > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From grosbach at apple.com Wed Sep 1 14:16:29 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 01 Sep 2010 19:16:29 -0000 Subject: [llvm-commits] [llvm] r112726 - /llvm/trunk/lib/CodeGen/RegAllocFast.cpp Message-ID: <20100901191629.6A9E42A6C12C@llvm.org> Author: grosbach Date: Wed Sep 1 14:16:29 2010 New Revision: 112726 URL: http://llvm.org/viewvc/llvm-project?rev=112726&view=rev Log: tidy up a few 80-column and trailing whitespace bits. Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=112726&r1=112725&r2=112726&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocFast.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp Wed Sep 1 14:16:29 2010 @@ -113,9 +113,9 @@ // Allocatable - vector of allocatable physical registers. BitVector Allocatable; - // SkippedInstrs - Descriptors of instructions whose clobber list was ignored - // because all registers were spilled. It is still necessary to mark all the - // clobbered registers as used by the function. + // SkippedInstrs - Descriptors of instructions whose clobber list was + // ignored because all registers were spilled. It is still necessary to + // mark all the clobbered registers as used by the function. SmallPtrSet SkippedInstrs; // isBulkSpilling - This flag is set when LiveRegMap will be cleared @@ -267,11 +267,11 @@ TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, SpillKill, FI, RC, TRI); ++NumStores; // Update statistics - // If this register is used by DBG_VALUE then insert new DBG_VALUE to + // If this register is used by DBG_VALUE then insert new DBG_VALUE to // identify spilled location as the place to find corresponding variable's // value. if (MachineInstr *DBG = LiveDbgValueMap.lookup(LRI->first)) { - const MDNode *MDPtr = + const MDNode *MDPtr = DBG->getOperand(DBG->getNumOperands()-1).getMetadata(); int64_t Offset = 0; if (DBG->getOperand(1).isImm()) @@ -284,7 +284,7 @@ } else DL = MI->getDebugLoc(); - if (MachineInstr *NewDV = + if (MachineInstr *NewDV = TII->emitFrameIndexDebugValue(*MF, FI, Offset, MDPtr, DL)) { MachineBasicBlock *MBB = DBG->getParent(); MBB->insert(MI, NewDV); @@ -796,16 +796,18 @@ else { int SS = StackSlotForVirtReg[Reg]; if (SS == -1) - MO.setReg(0); // We can't allocate a physreg for a DebugValue, sorry! + // We can't allocate a physreg for a DebugValue, sorry! + MO.setReg(0); else { // Modify DBG_VALUE now that the value is in a spill slot. int64_t Offset = MI->getOperand(1).getImm(); - const MDNode *MDPtr = + const MDNode *MDPtr = MI->getOperand(MI->getNumOperands()-1).getMetadata(); DebugLoc DL = MI->getDebugLoc(); - if (MachineInstr *NewDV = + if (MachineInstr *NewDV = TII->emitFrameIndexDebugValue(*MF, SS, Offset, MDPtr, DL)) { - DEBUG(dbgs() << "Modifying debug info due to spill:" << "\t" << *MI); + DEBUG(dbgs() << "Modifying debug info due to spill:" << + "\t" << *MI); MachineBasicBlock *MBB = MI->getParent(); MBB->insert(MBB->erase(MI), NewDV); // Scan NewDV operands from the beginning. @@ -813,7 +815,8 @@ ScanDbgValue = true; break; } else - MO.setReg(0); // We can't allocate a physreg for a DebugValue, sorry! + // We can't allocate a physreg for a DebugValue; sorry! + MO.setReg(0); } } } @@ -876,8 +879,8 @@ // operands. If there are also physical defs, these registers must avoid // both physical defs and uses, making them more constrained than normal // operands. - // Similarly, if there are multiple defs and tied operands, we must make sure - // the same register is allocated to uses and defs. + // Similarly, if there are multiple defs and tied operands, we must make + // sure the same register is allocated to uses and defs. // We didn't detect inline asm tied operands above, so just make this extra // pass for all inline asm. if (MI->isInlineAsm() || hasEarlyClobbers || hasPartialRedefs || @@ -928,9 +931,9 @@ unsigned DefOpEnd = MI->getNumOperands(); if (TID.isCall()) { // Spill all virtregs before a call. This serves two purposes: 1. If an - // exception is thrown, the landing pad is going to expect to find registers - // in their spill slots, and 2. we don't have to wade through all the - // operands on the call instruction. + // exception is thrown, the landing pad is going to expect to find + // registers in their spill slots, and 2. we don't have to wade through + // all the operands on the call instruction. DefOpEnd = VirtOpEnd; DEBUG(dbgs() << " Spilling remaining registers before call.\n"); spillAll(MI); From resistor at mac.com Wed Sep 1 14:20:46 2010 From: resistor at mac.com (Owen Anderson) Date: Wed, 01 Sep 2010 19:20:46 -0000 Subject: [llvm-commits] [llvm] r112727 - /llvm/trunk/include/llvm/Support/StandardPasses.h Message-ID: <20100901192046.E869F2A6C12C@llvm.org> Author: resistor Date: Wed Sep 1 14:20:46 2010 New Revision: 112727 URL: http://llvm.org/viewvc/llvm-project?rev=112727&view=rev Log: Disable CorrelatedValuePropagation while I track down selfhost failures. Modified: llvm/trunk/include/llvm/Support/StandardPasses.h Modified: llvm/trunk/include/llvm/Support/StandardPasses.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/StandardPasses.h?rev=112727&r1=112726&r2=112727&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/StandardPasses.h (original) +++ llvm/trunk/include/llvm/Support/StandardPasses.h Wed Sep 1 14:20:46 2010 @@ -146,7 +146,6 @@ // opened up by them. PM->add(createInstructionCombiningPass()); PM->add(createJumpThreadingPass()); // Thread jumps - PM->add(createCorrelatedValuePropagationPass()); PM->add(createDeadStoreEliminationPass()); // Delete dead stores PM->add(createAggressiveDCEPass()); // Delete dead instructions PM->add(createCFGSimplificationPass()); // Merge & remove BBs From grosbach at apple.com Wed Sep 1 14:28:42 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 01 Sep 2010 19:28:42 -0000 Subject: [llvm-commits] [llvm] r112728 - /llvm/trunk/lib/CodeGen/RegAllocFast.cpp Message-ID: <20100901192842.18C932A6C12C@llvm.org> Author: grosbach Date: Wed Sep 1 14:28:41 2010 New Revision: 112728 URL: http://llvm.org/viewvc/llvm-project?rev=112728&view=rev Log: The register allocator shouldn't consider allocating reserved registers. Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=112728&r1=112727&r2=112728&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocFast.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp Wed Sep 1 14:28:41 2010 @@ -113,6 +113,9 @@ // Allocatable - vector of allocatable physical registers. BitVector Allocatable; + // Reserved - vector of reserved physical registers. + BitVector Reserved; + // SkippedInstrs - Descriptors of instructions whose clobber list was // ignored because all registers were spilled. It is still necessary to // mark all the clobbered registers as used by the function. @@ -709,7 +712,7 @@ } // Restore UsedInInstr to a state usable for allocating normal virtual uses. - UsedInInstr.reset(); + UsedInInstr = Reserved; for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); if (!MO.isReg() || (MO.isDef() && !MO.isEarlyClobber())) continue; @@ -835,7 +838,7 @@ } // Track registers used by instruction. - UsedInInstr.reset(); + UsedInInstr = Reserved; // First scan. // Mark physreg uses and early clobbers as used. @@ -913,7 +916,7 @@ // Track registers defined by instruction - early clobbers and tied uses at // this point. - UsedInInstr.reset(); + UsedInInstr = Reserved; if (hasEarlyClobbers) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); @@ -1011,6 +1014,7 @@ UsedInInstr.resize(TRI->getNumRegs()); Allocatable = TRI->getAllocatableSet(*MF); + Reserved = TRI->getReservedRegs(*MF); // initialize the virtual->physical register map to have a 'null' // mapping for all virtual registers From clattner at apple.com Wed Sep 1 14:29:32 2010 From: clattner at apple.com (Chris Lattner) Date: Wed, 1 Sep 2010 12:29:32 -0700 Subject: [llvm-commits] [llvm] r111665 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp test/Transforms/InstCombine/2010-08-19-StoreNarrowing.ll In-Reply-To: References: <20100820182443.4552E2A6C12E@llvm.org> <74D55FC8-5CD1-4F1D-8512-4C4BFC06AD4C@mac.com> Message-ID: On Sep 1, 2010, at 10:16 AM, Dan Gohman wrote: >>> Good catch. Is this even reasonably fixable within the context of instcombine? It looks like we'd want to use something like memdep to guarantee that there are no intervening writes to P. >> >> This is best done in dag combine, where the chains tell you this. Please revert your instcombine change. > > Hi Chris, is the memory dependence issue the only reason to prefer to use > dagcombine here instead of instcombine? No, I also don't like that it narrows the load/store operations, which introduces type unsafety, and discourages GVN and other mid-level optimizations. > Narrowing stores and eliminating loads can open up a variety of optimization > opportunities. This suggests that instcombine is a better place for this > optimization. It discourages load GVN. -Chris From sabre at nondot.org Wed Sep 1 15:09:20 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 01 Sep 2010 20:09:20 -0000 Subject: [llvm-commits] [llvm] r112733 - in /llvm/trunk/docs/tutorial: LangImpl3.html LangImpl5.html LangImpl6.html LangImpl7.html Message-ID: <20100901200920.C6D252A6C12C@llvm.org> Author: lattner Date: Wed Sep 1 15:09:20 2010 New Revision: 112733 URL: http://llvm.org/viewvc/llvm-project?rev=112733&view=rev Log: update the tutorial to use CreateFAdd to create fp operations. Modified: llvm/trunk/docs/tutorial/LangImpl3.html llvm/trunk/docs/tutorial/LangImpl5.html llvm/trunk/docs/tutorial/LangImpl6.html llvm/trunk/docs/tutorial/LangImpl7.html Modified: llvm/trunk/docs/tutorial/LangImpl3.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/tutorial/LangImpl3.html?rev=112733&r1=112732&r2=112733&view=diff ============================================================================== --- llvm/trunk/docs/tutorial/LangImpl3.html (original) +++ llvm/trunk/docs/tutorial/LangImpl3.html Wed Sep 1 15:09:20 2010 @@ -222,7 +222,7 @@

      In the example above, the LLVM builder class is starting to show its value. IRBuilder knows where to insert the newly created instruction, all you have to -do is specify what instruction to create (e.g. with CreateAdd), which +do is specify what instruction to create (e.g. with CreateFAdd), which operands to use (L and R here) and optionally provide a name for the generated instruction.

      @@ -1054,9 +1054,9 @@ if (L == 0 || R == 0) return 0; switch (Op) { - case '+': return Builder.CreateAdd(L, R, "addtmp"); - case '-': return Builder.CreateSub(L, R, "subtmp"); - case '*': return Builder.CreateMul(L, R, "multmp"); + case '+': return Builder.CreateFAdd(L, R, "addtmp"); + case '-': return Builder.CreateFSub(L, R, "subtmp"); + case '*': return Builder.CreateFMul(L, R, "multmp"); case '<': L = Builder.CreateFCmpULT(L, R, "cmptmp"); // Convert bool 0/1 to double 0.0 or 1.0 Modified: llvm/trunk/docs/tutorial/LangImpl5.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/tutorial/LangImpl5.html?rev=112733&r1=112732&r2=112733&view=diff ============================================================================== --- llvm/trunk/docs/tutorial/LangImpl5.html (original) +++ llvm/trunk/docs/tutorial/LangImpl5.html Wed Sep 1 15:09:20 2010 @@ -800,7 +800,7 @@ StepVal = ConstantFP::get(getGlobalContext(), APFloat(1.0)); } - Value *NextVar = Builder.CreateAdd(Variable, StepVal, "nextvar"); + Value *NextVar = Builder.CreateFAdd(Variable, StepVal, "nextvar");
      @@ -1517,7 +1517,7 @@ StepVal = ConstantFP::get(getGlobalContext(), APFloat(1.0)); } - Value *NextVar = Builder.CreateAdd(Variable, StepVal, "nextvar"); + Value *NextVar = Builder.CreateFAdd(Variable, StepVal, "nextvar"); // Compute the end condition. Value *EndCond = End->Codegen(); Modified: llvm/trunk/docs/tutorial/LangImpl6.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/tutorial/LangImpl6.html?rev=112733&r1=112732&r2=112733&view=diff ============================================================================== --- llvm/trunk/docs/tutorial/LangImpl6.html (original) +++ llvm/trunk/docs/tutorial/LangImpl6.html Wed Sep 1 15:09:20 2010 @@ -1540,7 +1540,7 @@ StepVal = ConstantFP::get(getGlobalContext(), APFloat(1.0)); } - Value *NextVar = Builder.CreateAdd(Variable, StepVal, "nextvar"); + Value *NextVar = Builder.CreateFAdd(Variable, StepVal, "nextvar"); // Compute the end condition. Value *EndCond = End->Codegen(); Modified: llvm/trunk/docs/tutorial/LangImpl7.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/tutorial/LangImpl7.html?rev=112733&r1=112732&r2=112733&view=diff ============================================================================== --- llvm/trunk/docs/tutorial/LangImpl7.html (original) +++ llvm/trunk/docs/tutorial/LangImpl7.html Wed Sep 1 15:09:20 2010 @@ -480,7 +480,7 @@ // Reload, increment, and restore the alloca. This handles the case where // the body of the loop mutates the variable. Value *CurVar = Builder.CreateLoad(Alloca); - Value *NextVar = Builder.CreateAdd(CurVar, StepVal, "nextvar"); + Value *NextVar = Builder.CreateFAdd(CurVar, StepVal, "nextvar"); Builder.CreateStore(NextVar, Alloca); ... @@ -1833,7 +1833,7 @@ // Reload, increment, and restore the alloca. This handles the case where // the body of the loop mutates the variable. Value *CurVar = Builder.CreateLoad(Alloca, VarName.c_str()); - Value *NextVar = Builder.CreateAdd(CurVar, StepVal, "nextvar"); + Value *NextVar = Builder.CreateFAdd(CurVar, StepVal, "nextvar"); Builder.CreateStore(NextVar, Alloca); // Convert condition to a bool by comparing equal to 0.0. From echristo at apple.com Wed Sep 1 15:23:15 2010 From: echristo at apple.com (Eric Christopher) Date: Wed, 01 Sep 2010 20:23:15 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r112736 - /llvm-gcc-4.2/trunk/gcc/llvm-linker-hack.cpp Message-ID: <20100901202315.3D5B42A6C12C@llvm.org> Author: echristo Date: Wed Sep 1 15:23:15 2010 New Revision: 112736 URL: http://llvm.org/viewvc/llvm-project?rev=112736&view=rev Log: Add this to the linker hack! Modified: llvm-gcc-4.2/trunk/gcc/llvm-linker-hack.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-linker-hack.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-linker-hack.cpp?rev=112736&r1=112735&r2=112736&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-linker-hack.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-linker-hack.cpp Wed Sep 1 15:23:15 2010 @@ -90,6 +90,7 @@ llvm::createFunctionAttrsPass(); llvm::createPrintModulePass(0); llvm::createPromoteMemoryToRegisterPass(); + llvm::createCorrelatedValuePropagationPass(); llvm::Type::getInt8Ty(llvm::getGlobalContext()); From dalej at apple.com Wed Sep 1 16:03:03 2010 From: dalej at apple.com (Dale Johannesen) Date: Wed, 01 Sep 2010 21:03:03 -0000 Subject: [llvm-commits] [llvm] r112740 - /llvm/trunk/include/llvm/IntrinsicsX86.td Message-ID: <20100901210303.9D0602A6C12C@llvm.org> Author: johannes Date: Wed Sep 1 16:03:03 2010 New Revision: 112740 URL: http://llvm.org/viewvc/llvm-project?rev=112740&view=rev Log: Add a few more missing MMX operations. This should be it. Modified: llvm/trunk/include/llvm/IntrinsicsX86.td Modified: llvm/trunk/include/llvm/IntrinsicsX86.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsX86.td?rev=112740&r1=112739&r2=112740&view=diff ============================================================================== --- llvm/trunk/include/llvm/IntrinsicsX86.td (original) +++ llvm/trunk/include/llvm/IntrinsicsX86.td Wed Sep 1 16:03:03 2010 @@ -630,6 +630,9 @@ def int_x86_ssse3_pshuf_b_128 : GCCBuiltin<"__builtin_ia32_pshufb128">, Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>; + def int_x86_ssse3_pshuf_w : GCCBuiltin<"__builtin_ia32_pshufw">, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_i32_ty], + [IntrNoMem]>; } // Sign ops @@ -1567,12 +1570,20 @@ def int_x86_mmx_movnt_dq : GCCBuiltin<"__builtin_ia32_movntq">, Intrinsic<[], [llvm_ptr_ty, llvm_v1i64_ty], []>; - def int_x86_mmx_cvtsi32_MMX : GCCBuiltin<"__builtin_ia32_vec_init_v2si">, + def int_x86_mmx_palignr_b : GCCBuiltin<"__builtin_ia32_palignr">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, + llvm_v1i64_ty, llvm_i32_ty], [IntrNoMem]>; + + def int_x86_mmx_pextr_w : + Intrinsic<[llvm_i32_ty], [llvm_v1i64_ty, llvm_i32_ty], + [IntrNoMem]>; + + def int_x86_mmx_pinsr_w : + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, + llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; + + def int_x86_mmx_cvtsi32_si64 : GCCBuiltin<"__builtin_ia32_vec_init_v2si">, Intrinsic<[llvm_v1i64_ty], [llvm_i32_ty], [IntrNoMem]>; - def int_x86_mmx_cvtsi64_MMX : - Intrinsic<[llvm_v1i64_ty], [llvm_i64_ty], [IntrNoMem]>; - def int_x86_mmx_MMX_si32 : GCCBuiltin<"__builtin_ia32_vec_ext_v2si">, + def int_x86_mmx_cvtsi64_si32 : GCCBuiltin<"__builtin_ia32_vec_ext_v2si">, Intrinsic<[llvm_i32_ty], [llvm_v1i64_ty], [IntrNoMem]>; - def int_x86_mmx_MMX_si64 : - Intrinsic<[llvm_i64_ty], [llvm_v1i64_ty], [IntrNoMem]>; } From grosbach at apple.com Wed Sep 1 16:04:27 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 01 Sep 2010 21:04:27 -0000 Subject: [llvm-commits] [llvm] r112741 - /llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Message-ID: <20100901210427.9497B2A6C12C@llvm.org> Author: grosbach Date: Wed Sep 1 16:04:27 2010 New Revision: 112741 URL: http://llvm.org/viewvc/llvm-project?rev=112741&view=rev Log: The register allocator shouldn't consider allocating reserved registers. r112728 did this for fast regalloc. Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp?rev=112741&r1=112740&r2=112741&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Wed Sep 1 16:04:27 2010 @@ -125,6 +125,7 @@ const TargetRegisterInfo* tri_; const TargetInstrInfo* tii_; BitVector allocatableRegs_; + BitVector reservedRegs_; LiveIntervals* li_; LiveStacks* ls_; MachineLoopInfo *loopInfo; @@ -464,6 +465,7 @@ tri_ = tm_->getRegisterInfo(); tii_ = tm_->getInstrInfo(); allocatableRegs_ = tri_->getAllocatableSet(fn); + reservedRegs_ = tri_->getReservedRegs(fn); li_ = &getAnalysis(); ls_ = &getAnalysis(); loopInfo = &getAnalysis(); @@ -949,8 +951,14 @@ const TargetRegisterClass *RC = mri_->getRegClass(cur->reg); if (cur->empty()) { unsigned physReg = vrm_->getRegAllocPref(cur->reg); - if (!physReg) - physReg = *RC->allocation_order_begin(*mf_); + if (!physReg) { + TargetRegisterClass::iterator aoe = RC->allocation_order_end(*mf_); + TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_); + while (reservedRegs_.test(*i) && i != aoe) + ++i; + assert(i != aoe && "All registers reserved?!"); + physReg = *i; + } DEBUG(dbgs() << tri_->getName(physReg) << '\n'); // Note the register is not really in use. vrm_->assignVirt2Phys(cur->reg, physReg); @@ -1133,8 +1141,9 @@ e = RC->allocation_order_end(*mf_); i != e; ++i) { unsigned reg = *i; float regWeight = SpillWeights[reg]; - // Skip recently allocated registers. - if (minWeight > regWeight && !isRecentlyUsed(reg)) + // Skip recently allocated registers and reserved registers. + if (minWeight > regWeight && !isRecentlyUsed(reg) && + !reservedRegs_.test(reg)) Found = true; RegsWeights.push_back(std::make_pair(reg, regWeight)); } @@ -1144,6 +1153,8 @@ for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_), e = RC->allocation_order_end(*mf_); i != e; ++i) { unsigned reg = *i; + if (reservedRegs_.test(reg)) + continue; // No need to worry about if the alias register size < regsize of RC. // We are going to spill all registers that alias it anyway. for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as) @@ -1157,7 +1168,15 @@ minWeight = RegsWeights[0].second; if (minWeight == HUGE_VALF) { // All registers must have inf weight. Just grab one! - minReg = BestPhysReg ? BestPhysReg : *RC->allocation_order_begin(*mf_); + if (BestPhysReg == 0) { + TargetRegisterClass::iterator aoe = RC->allocation_order_end(*mf_); + TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_); + while (reservedRegs_.test(*i) && i != aoe) + ++i; + assert(i != aoe && "All registers reserved?!"); + minReg = *i; + } else + minReg = BestPhysReg; if (cur->weight == HUGE_VALF || li_->getApproximateInstructionCount(*cur) == 0) { // Spill a physical register around defs and uses. @@ -1414,6 +1433,9 @@ // Ignore "downgraded" registers. if (SkipDGRegs && DowngradedRegs.count(Reg)) continue; + // Skip reserved registers. + if (reservedRegs_.test(Reg)) + continue; // Skip recently allocated registers. if (isRegAvail(Reg) && !isRecentlyUsed(Reg)) { FreeReg = Reg; @@ -1442,6 +1464,9 @@ // Ignore "downgraded" registers. if (SkipDGRegs && DowngradedRegs.count(Reg)) continue; + // Skip reserved registers. + if (reservedRegs_.test(Reg)) + continue; if (isRegAvail(Reg) && Reg < inactiveCounts.size() && FreeRegInactiveCount < inactiveCounts[Reg] && !isRecentlyUsed(Reg)) { FreeReg = Reg; From stoklund at 2pi.dk Wed Sep 1 16:20:29 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 1 Sep 2010 14:20:29 -0700 Subject: [llvm-commits] [llvm] r112741 - /llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp In-Reply-To: <20100901210427.9497B2A6C12C@llvm.org> References: <20100901210427.9497B2A6C12C@llvm.org> Message-ID: <187300E7-5EFC-4C38-98CE-8DD6781C460C@2pi.dk> On Sep 1, 2010, at 2:04 PM, Jim Grosbach wrote: > + if (!physReg) { > + TargetRegisterClass::iterator aoe = RC->allocation_order_end(*mf_); > + TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_); > + while (reservedRegs_.test(*i) && i != aoe) > + ++i; > + assert(i != aoe && "All registers reserved?!"); > + physReg = *i; > + } Hi Jim, This bit should probably be a function since you're doing it twice. Also, make sure you can handle register classes with an empty allocation order. They shouldn't occur here, but its better to get the assert when they do. I would like to properly clean up the specification of allocation order, register classes, and reserved registers in the .td files, but for now allowing reserved registers in the allocation order is a good compromise. /jakob From grosbach at apple.com Wed Sep 1 16:23:35 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 1 Sep 2010 14:23:35 -0700 Subject: [llvm-commits] [llvm] r112741 - /llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp In-Reply-To: <187300E7-5EFC-4C38-98CE-8DD6781C460C@2pi.dk> References: <20100901210427.9497B2A6C12C@llvm.org> <187300E7-5EFC-4C38-98CE-8DD6781C460C@2pi.dk> Message-ID: <08D61044-BFFC-41A3-BF78-233CD4CBCBD6@apple.com> On Sep 1, 2010, at 2:20 PM, Jakob Stoklund Olesen wrote: > > On Sep 1, 2010, at 2:04 PM, Jim Grosbach wrote: > >> + if (!physReg) { >> + TargetRegisterClass::iterator aoe = RC->allocation_order_end(*mf_); >> + TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_); >> + while (reservedRegs_.test(*i) && i != aoe) >> + ++i; >> + assert(i != aoe && "All registers reserved?!"); >> + physReg = *i; >> + } > > Hi Jim, > > This bit should probably be a function since you're doing it twice. > > Also, make sure you can handle register classes with an empty allocation order. They shouldn't occur here, but its better to get the assert when they do. > Both excellent points. Will do. > I would like to properly clean up the specification of allocation order, register classes, and reserved registers in the .td files, but for now allowing reserved registers in the allocation order is a good compromise. Agreed. There's definitely lots of room for improvement in this area. Thanks for the review! -Jim From grosbach at apple.com Wed Sep 1 16:23:03 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 01 Sep 2010 21:23:03 -0000 Subject: [llvm-commits] [llvm] r112742 - /llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp Message-ID: <20100901212303.CDE9E2A6C12C@llvm.org> Author: grosbach Date: Wed Sep 1 16:23:03 2010 New Revision: 112742 URL: http://llvm.org/viewvc/llvm-project?rev=112742&view=rev Log: The register allocator shouldn't consider allocating reserved registers. PBQP version. Modified: llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp Modified: llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp?rev=112742&r1=112741&r2=112742&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp Wed Sep 1 16:23:03 2010 @@ -587,6 +587,8 @@ // Resize allowedSets container appropriately. allowedSets.resize(vregIntervalsToAlloc.size()); + BitVector ReservedRegs = tri->getReservedRegs(*mf); + // Iterate over virtual register intervals to compute allowed sets... for (unsigned node = 0; node < node2LI.size(); ++node) { @@ -595,8 +597,12 @@ const TargetRegisterClass *liRC = mri->getRegClass(li->reg); // Start by assuming all allocable registers in the class are allowed... - RegVector liAllowed(liRC->allocation_order_begin(*mf), - liRC->allocation_order_end(*mf)); + RegVector liAllowed; + TargetRegisterClass::iterator aob = liRC->allocation_order_begin(*mf); + TargetRegisterClass::iterator aoe = liRC->allocation_order_end(*mf); + for (TargetRegisterClass::iterator it = aob; it != aoe; ++it) + if (!ReservedRegs.test(*it)) + liAllowed.push_back(*it); // Eliminate the physical registers which overlap with this range, along // with all their aliases. From grosbach at apple.com Wed Sep 1 16:34:41 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 01 Sep 2010 21:34:41 -0000 Subject: [llvm-commits] [llvm] r112743 - /llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Message-ID: <20100901213441.7CDEC2A6C12C@llvm.org> Author: grosbach Date: Wed Sep 1 16:34:41 2010 New Revision: 112743 URL: http://llvm.org/viewvc/llvm-project?rev=112743&view=rev Log: cleanup per feedback. use a helper function for getting the first non-reserved physical register in a register class. Make sure to assert if the register class is empty. Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp?rev=112743&r1=112742&r2=112743&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Wed Sep 1 16:34:41 2010 @@ -336,6 +336,17 @@ SmallVector &inactiveCounts, bool SkipDGRegs); + /// getFirstNonReservedPhysReg - return the first non-reserved physical + /// register in the register class. + unsigned getFirstNonReservedPhysReg(const TargetRegisterClass *RC) { + TargetRegisterClass::iterator aoe = RC->allocation_order_end(*mf_); + TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_); + while (i != aoe && reservedRegs_.test(*i)) + ++i; + assert(i != aoe && "All registers reserved?!"); + return *i; + } + void ComputeRelatedRegClasses(); template @@ -951,14 +962,8 @@ const TargetRegisterClass *RC = mri_->getRegClass(cur->reg); if (cur->empty()) { unsigned physReg = vrm_->getRegAllocPref(cur->reg); - if (!physReg) { - TargetRegisterClass::iterator aoe = RC->allocation_order_end(*mf_); - TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_); - while (reservedRegs_.test(*i) && i != aoe) - ++i; - assert(i != aoe && "All registers reserved?!"); - physReg = *i; - } + if (!physReg) + physReg = getFirstNonReservedPhysReg(RC); DEBUG(dbgs() << tri_->getName(physReg) << '\n'); // Note the register is not really in use. vrm_->assignVirt2Phys(cur->reg, physReg); @@ -1168,15 +1173,7 @@ minWeight = RegsWeights[0].second; if (minWeight == HUGE_VALF) { // All registers must have inf weight. Just grab one! - if (BestPhysReg == 0) { - TargetRegisterClass::iterator aoe = RC->allocation_order_end(*mf_); - TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_); - while (reservedRegs_.test(*i) && i != aoe) - ++i; - assert(i != aoe && "All registers reserved?!"); - minReg = *i; - } else - minReg = BestPhysReg; + minReg = BestPhysReg ? BestPhysReg : getFirstNonReservedPhysReg(RC); if (cur->weight == HUGE_VALF || li_->getApproximateInstructionCount(*cur) == 0) { // Spill a physical register around defs and uses. From dalej at apple.com Wed Sep 1 16:36:44 2010 From: dalej at apple.com (Dale Johannesen) Date: Wed, 01 Sep 2010 21:36:44 -0000 Subject: [llvm-commits] [llvm] r112744 - /llvm/trunk/include/llvm/IntrinsicsX86.td Message-ID: <20100901213644.6A4312A6C12C@llvm.org> Author: johannes Date: Wed Sep 1 16:36:44 2010 New Revision: 112744 URL: http://llvm.org/viewvc/llvm-project?rev=112744&view=rev Log: Revert 112740, it broke some clang tests somehow... Modified: llvm/trunk/include/llvm/IntrinsicsX86.td Modified: llvm/trunk/include/llvm/IntrinsicsX86.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsX86.td?rev=112744&r1=112743&r2=112744&view=diff ============================================================================== --- llvm/trunk/include/llvm/IntrinsicsX86.td (original) +++ llvm/trunk/include/llvm/IntrinsicsX86.td Wed Sep 1 16:36:44 2010 @@ -630,9 +630,6 @@ def int_x86_ssse3_pshuf_b_128 : GCCBuiltin<"__builtin_ia32_pshufb128">, Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>; - def int_x86_ssse3_pshuf_w : GCCBuiltin<"__builtin_ia32_pshufw">, - Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_i32_ty], - [IntrNoMem]>; } // Sign ops @@ -1570,20 +1567,12 @@ def int_x86_mmx_movnt_dq : GCCBuiltin<"__builtin_ia32_movntq">, Intrinsic<[], [llvm_ptr_ty, llvm_v1i64_ty], []>; - def int_x86_mmx_palignr_b : GCCBuiltin<"__builtin_ia32_palignr">, - Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, - llvm_v1i64_ty, llvm_i32_ty], [IntrNoMem]>; - - def int_x86_mmx_pextr_w : - Intrinsic<[llvm_i32_ty], [llvm_v1i64_ty, llvm_i32_ty], - [IntrNoMem]>; - - def int_x86_mmx_pinsr_w : - Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, - llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; - - def int_x86_mmx_cvtsi32_si64 : GCCBuiltin<"__builtin_ia32_vec_init_v2si">, + def int_x86_mmx_cvtsi32_MMX : GCCBuiltin<"__builtin_ia32_vec_init_v2si">, Intrinsic<[llvm_v1i64_ty], [llvm_i32_ty], [IntrNoMem]>; - def int_x86_mmx_cvtsi64_si32 : GCCBuiltin<"__builtin_ia32_vec_ext_v2si">, + def int_x86_mmx_cvtsi64_MMX : + Intrinsic<[llvm_v1i64_ty], [llvm_i64_ty], [IntrNoMem]>; + def int_x86_mmx_MMX_si32 : GCCBuiltin<"__builtin_ia32_vec_ext_v2si">, Intrinsic<[llvm_i32_ty], [llvm_v1i64_ty], [IntrNoMem]>; + def int_x86_mmx_MMX_si64 : + Intrinsic<[llvm_i64_ty], [llvm_v1i64_ty], [IntrNoMem]>; } From wendling at apple.com Wed Sep 1 16:42:33 2010 From: wendling at apple.com (Bill Wendling) Date: Wed, 1 Sep 2010 14:42:33 -0700 Subject: [llvm-commits] [llvm] r112744 - /llvm/trunk/include/llvm/IntrinsicsX86.td In-Reply-To: <20100901213644.6A4312A6C12C@llvm.org> References: <20100901213644.6A4312A6C12C@llvm.org> Message-ID: <7DC28FC1-954A-4902-B173-692324DA5291@apple.com> I'll try your change with my clang changes to see if it helps? -bw On Sep 1, 2010, at 2:36 PM, Dale Johannesen wrote: > Author: johannes > Date: Wed Sep 1 16:36:44 2010 > New Revision: 112744 > > URL: http://llvm.org/viewvc/llvm-project?rev=112744&view=rev > Log: > Revert 112740, it broke some clang tests somehow... > > > Modified: > llvm/trunk/include/llvm/IntrinsicsX86.td > > Modified: llvm/trunk/include/llvm/IntrinsicsX86.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsX86.td?rev=112744&r1=112743&r2=112744&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/IntrinsicsX86.td (original) > +++ llvm/trunk/include/llvm/IntrinsicsX86.td Wed Sep 1 16:36:44 2010 > @@ -630,9 +630,6 @@ > def int_x86_ssse3_pshuf_b_128 : GCCBuiltin<"__builtin_ia32_pshufb128">, > Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, > llvm_v16i8_ty], [IntrNoMem]>; > - def int_x86_ssse3_pshuf_w : GCCBuiltin<"__builtin_ia32_pshufw">, > - Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_i32_ty], > - [IntrNoMem]>; > } > > // Sign ops > @@ -1570,20 +1567,12 @@ > def int_x86_mmx_movnt_dq : GCCBuiltin<"__builtin_ia32_movntq">, > Intrinsic<[], [llvm_ptr_ty, llvm_v1i64_ty], []>; > > - def int_x86_mmx_palignr_b : GCCBuiltin<"__builtin_ia32_palignr">, > - Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, > - llvm_v1i64_ty, llvm_i32_ty], [IntrNoMem]>; > - > - def int_x86_mmx_pextr_w : > - Intrinsic<[llvm_i32_ty], [llvm_v1i64_ty, llvm_i32_ty], > - [IntrNoMem]>; > - > - def int_x86_mmx_pinsr_w : > - Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, > - llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; > - > - def int_x86_mmx_cvtsi32_si64 : GCCBuiltin<"__builtin_ia32_vec_init_v2si">, > + def int_x86_mmx_cvtsi32_MMX : GCCBuiltin<"__builtin_ia32_vec_init_v2si">, > Intrinsic<[llvm_v1i64_ty], [llvm_i32_ty], [IntrNoMem]>; > - def int_x86_mmx_cvtsi64_si32 : GCCBuiltin<"__builtin_ia32_vec_ext_v2si">, > + def int_x86_mmx_cvtsi64_MMX : > + Intrinsic<[llvm_v1i64_ty], [llvm_i64_ty], [IntrNoMem]>; > + def int_x86_mmx_MMX_si32 : GCCBuiltin<"__builtin_ia32_vec_ext_v2si">, > Intrinsic<[llvm_i32_ty], [llvm_v1i64_ty], [IntrNoMem]>; > + def int_x86_mmx_MMX_si64 : > + Intrinsic<[llvm_i64_ty], [llvm_v1i64_ty], [IntrNoMem]>; > } > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From grosbach at apple.com Wed Sep 1 16:47:26 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 1 Sep 2010 14:47:26 -0700 Subject: [llvm-commits] [llvm] r112741 - /llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp In-Reply-To: <187300E7-5EFC-4C38-98CE-8DD6781C460C@2pi.dk> References: <20100901210427.9497B2A6C12C@llvm.org> <187300E7-5EFC-4C38-98CE-8DD6781C460C@2pi.dk> Message-ID: On Sep 1, 2010, at 2:20 PM, Jakob Stoklund Olesen wrote: > > On Sep 1, 2010, at 2:04 PM, Jim Grosbach wrote: > >> + if (!physReg) { >> + TargetRegisterClass::iterator aoe = RC->allocation_order_end(*mf_); >> + TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_); >> + while (reservedRegs_.test(*i) && i != aoe) >> + ++i; >> + assert(i != aoe && "All registers reserved?!"); >> + physReg = *i; >> + } > > Hi Jim, > > This bit should probably be a function since you're doing it twice. > > Also, make sure you can handle register classes with an empty allocation order. They shouldn't occur here, but its better to get the assert when they do. and done in r112743. From gohman at apple.com Wed Sep 1 16:46:45 2010 From: gohman at apple.com (Dan Gohman) Date: Wed, 01 Sep 2010 21:46:45 -0000 Subject: [llvm-commits] [llvm] r112745 - in /llvm/trunk: lib/Transforms/Scalar/LoopUnswitch.cpp test/Transforms/LoopUnswitch/infinite-loop.ll Message-ID: <20100901214645.5461B2A6C12C@llvm.org> Author: djg Date: Wed Sep 1 16:46:45 2010 New Revision: 112745 URL: http://llvm.org/viewvc/llvm-project?rev=112745&view=rev Log: Fix loop unswitching's assumption that a code path which either infinite loops or exits will eventually exit. This fixes PR5373. Added: llvm/trunk/test/Transforms/LoopUnswitch/infinite-loop.ll Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp?rev=112745&r1=112744&r2=112745&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp Wed Sep 1 16:46:45 2010 @@ -277,19 +277,18 @@ return Changed; } -/// isTrivialLoopExitBlock - Check to see if all paths from BB either: -/// 1. Exit the loop with no side effects. -/// 2. Branch to the latch block with no side-effects. +/// isTrivialLoopExitBlock - Check to see if all paths from BB exit the +/// loop with no side effects (including infinite loops). /// -/// If these conditions are true, we return true and set ExitBB to the block we +/// If true, we return true and set ExitBB to the block we /// exit through. /// static bool isTrivialLoopExitBlockHelper(Loop *L, BasicBlock *BB, BasicBlock *&ExitBB, std::set &Visited) { if (!Visited.insert(BB).second) { - // Already visited and Ok, end of recursion. - return true; + // Already visited. Without more analysis, this could indicate an infinte loop. + return false; } else if (!L->contains(BB)) { // Otherwise, this is a loop exit, this is fine so long as this is the // first exit. @@ -319,7 +318,7 @@ /// process. If so, return the block that is exited to, otherwise return null. static BasicBlock *isTrivialLoopExitBlock(Loop *L, BasicBlock *BB) { std::set Visited; - Visited.insert(L->getHeader()); // Branches to header are ok. + Visited.insert(L->getHeader()); // Branches to header make infinite loops. BasicBlock *ExitBB = 0; if (isTrivialLoopExitBlockHelper(L, BB, ExitBB, Visited)) return ExitBB; @@ -351,8 +350,8 @@ if (!BI->isConditional() || BI->getCondition() != Cond) return false; - // Check to see if a successor of the branch is guaranteed to go to the - // latch block or exit through a one exit block without having any + // Check to see if a successor of the branch is guaranteed to + // exit through a unique exit block without having any // side-effects. If so, determine the value of Cond that causes it to do // this. if ((LoopExitBB = isTrivialLoopExitBlock(currentLoop, Added: llvm/trunk/test/Transforms/LoopUnswitch/infinite-loop.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopUnswitch/infinite-loop.ll?rev=112745&view=auto ============================================================================== --- llvm/trunk/test/Transforms/LoopUnswitch/infinite-loop.ll (added) +++ llvm/trunk/test/Transforms/LoopUnswitch/infinite-loop.ll Wed Sep 1 16:46:45 2010 @@ -0,0 +1,53 @@ +; RUN: opt -loop-unswitch -disable-output -stats -info-output-file - < %s | FileCheck --check-prefix=STATS %s +; RUN: opt -loop-unswitch -simplifycfg -S < %s | FileCheck %s +; PR5373 + +; Loop unswitching shouldn't trivially unswitch the true case of condition %a +; in the code here because it leads to an infinite loop. While this doesn't +; contain any instructions with side effects, it's still a kind of side effect. +; It can trivially unswitch on the false cas of condition %a though. + +; STATS: 2 loop-unswitch - Number of branches unswitched +; STATS: 1 loop-unswitch - Number of unswitches that are trivial + +; CHECK: @func_16 +; CHECK-NEXT: entry: +; CHECK-NEXT: br i1 %a, label %entry.split, label %abort0.split + +; CHECK: entry.split: +; CHECK-NEXT: br i1 %b, label %cond.end.us, label %abort1 + +; CHECK: cond.end.us: +; CHECK-NEXT: br label %cond.end.us + +; CHECK: abort0.split: +; CHECK-NEXT: call void @end0() noreturn nounwind +; CHECK-NEXT: unreachable + +; CHECK: abort1: +; CHECK-NEXT: call void @end1() noreturn nounwind +; CHECK-NEXT: unreachable + +; CHECK: } + +define void @func_16(i1 %a, i1 %b) nounwind { +entry: + br label %for.body + +for.body: + br i1 %a, label %cond.end, label %abort0 + +cond.end: + br i1 %b, label %for.body, label %abort1 + +abort0: + call void @end0() noreturn nounwind + unreachable + +abort1: + call void @end1() noreturn nounwind + unreachable +} + +declare void @end0() noreturn +declare void @end1() noreturn From grosbach at apple.com Wed Sep 1 16:48:06 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 01 Sep 2010 21:48:06 -0000 Subject: [llvm-commits] [llvm] r112746 - /llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Message-ID: <20100901214806.ED6592A6C12C@llvm.org> Author: grosbach Date: Wed Sep 1 16:48:06 2010 New Revision: 112746 URL: http://llvm.org/viewvc/llvm-project?rev=112746&view=rev Log: tidy up trailing whitespace and an 80 column violation. Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp?rev=112746&r1=112745&r2=112746&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Wed Sep 1 16:48:06 2010 @@ -87,7 +87,7 @@ "to skip."), cl::init(0), cl::Hidden); - + struct RALinScan : public MachineFunctionPass { static char ID; RALinScan() : MachineFunctionPass(ID) { @@ -383,7 +383,7 @@ for (TargetRegisterClass::iterator I = (*RCI)->begin(), E = (*RCI)->end(); I != E; ++I) { HasAliases = HasAliases || *tri_->getAliasSet(*I) != 0; - + const TargetRegisterClass *&PRC = OneClassForEachPhysReg[*I]; if (PRC) { // Already processed this register. Just make sure we know that @@ -394,7 +394,7 @@ } } } - + // Second pass, now that we know conservatively what register classes each reg // belongs to, add info about aliases. We don't need to do this for targets // without register aliases. @@ -495,9 +495,9 @@ vrm_ = &getAnalysis(); if (!rewriter_.get()) rewriter_.reset(createVirtRegRewriter()); - + spiller_.reset(createSpiller(*this, *mf_, *vrm_)); - + initIntervalSets(); linearScan(); @@ -551,7 +551,7 @@ // linear scan algorithm DEBUG({ dbgs() << "********** LINEAR SCAN **********\n" - << "********** Function: " + << "********** Function: " << mf_->getFunction()->getName() << '\n'; printIntervals("fixed", fixed_.begin(), fixed_.end()); }); @@ -773,7 +773,8 @@ return IP.end(); } -static void RevertVectorIteratorsTo(RALinScan::IntervalPtrs &V, SlotIndex Point){ +static void RevertVectorIteratorsTo(RALinScan::IntervalPtrs &V, + SlotIndex Point){ for (unsigned i = 0, e = V.size(); i != e; ++i) { RALinScan::IntervalPtr &IP = V[i]; LiveInterval::iterator I = std::upper_bound(IP.first->begin(), @@ -845,7 +846,7 @@ dbgs() << tri_->getName(Candidates[i].first) << " "; dbgs() << "\n"; }); - + // Calculate the number of conflicts of each candidate. for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) { unsigned Reg = i->first->reg; @@ -1015,7 +1016,7 @@ assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Can only allocate virtual registers!"); const TargetRegisterClass *RegRC = mri_->getRegClass(Reg); - // If this is not in a related reg class to the register we're allocating, + // If this is not in a related reg class to the register we're allocating, // don't check it. if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader && cur->overlapsFrom(*i->first, i->second-1)) { @@ -1024,7 +1025,7 @@ SpillWeightsToAdd.push_back(std::make_pair(Reg, i->first->weight)); } } - + // Speculatively check to see if we can get a register right now. If not, // we know we won't be able to by adding more constraints. If so, we can // check to see if it is valid. Doing an exhaustive search of the fixed_ list @@ -1039,7 +1040,7 @@ SmallSet RegAliases; for (const unsigned *AS = tri_->getAliasSet(physReg); *AS; ++AS) RegAliases.insert(*AS); - + bool ConflictsWithFixed = false; for (unsigned i = 0, e = fixed_.size(); i != e; ++i) { IntervalPtr &IP = fixed_[i]; @@ -1059,7 +1060,7 @@ } } } - + // Okay, the register picked by our speculative getFreePhysReg call turned // out to be in use. Actually add all of the conflicting fixed registers to // regUse_ so we can do an accurate query. @@ -1071,7 +1072,7 @@ LiveInterval *I = IP.first; const TargetRegisterClass *RegRC = OneClassForEachPhysReg[I->reg]; - if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader && + if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader && I->endIndex() > StartPosition) { LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition); IP.second = II; @@ -1090,11 +1091,11 @@ physReg = getFreePhysReg(cur); } } - + // Restore the physical register tracker, removing information about the // future. restoreRegUses(); - + // If we find a free register, we are done: assign this virtual to // the free physical register and add this interval to the active // list. @@ -1109,7 +1110,7 @@ UpgradeRegister(physReg); if (LiveInterval *NextReloadLI = hasNextReloadInterval(cur)) { // "Downgrade" physReg to try to keep physReg from being allocated until - // the next reload from the same SS is allocated. + // the next reload from the same SS is allocated. mri_->setRegAllocationHint(NextReloadLI->reg, 0, physReg); DowngradeRegister(cur, physReg); } @@ -1122,7 +1123,7 @@ for (std::vector >::iterator I = SpillWeightsToAdd.begin(), E = SpillWeightsToAdd.end(); I != E; ++I) updateSpillWeights(SpillWeights, I->first, I->second, RC); - + // for each interval in active, update spill weights. for (IntervalPtrs::const_iterator i = active_.begin(), e = active_.end(); i != e; ++i) { @@ -1132,7 +1133,7 @@ reg = vrm_->getPhys(reg); updateSpillWeights(SpillWeights, reg, i->first->weight, RC); } - + DEBUG(dbgs() << "\tassigning stack slot at interval "<< *cur << ":\n"); // Find a register to spill. @@ -1152,7 +1153,7 @@ Found = true; RegsWeights.push_back(std::make_pair(reg, regWeight)); } - + // If we didn't find a register that is spillable, try aliases? if (!Found) { for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_), @@ -1281,7 +1282,7 @@ // The earliest start of a Spilled interval indicates up to where // in handled we need to roll back - assert(!spillIs.empty() && "No spill intervals?"); + assert(!spillIs.empty() && "No spill intervals?"); SlotIndex earliestStart = spillIs[0]->beginIndex(); // Spill live intervals of virtual regs mapped to the physical register we @@ -1484,17 +1485,17 @@ unsigned RALinScan::getFreePhysReg(LiveInterval *cur) { SmallVector inactiveCounts; unsigned MaxInactiveCount = 0; - + const TargetRegisterClass *RC = mri_->getRegClass(cur->reg); const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC); - + for (IntervalPtrs::iterator i = inactive_.begin(), e = inactive_.end(); i != e; ++i) { unsigned reg = i->first->reg; assert(TargetRegisterInfo::isVirtualRegister(reg) && "Can only allocate virtual registers!"); - // If this is not in a related reg class to the register we're allocating, + // If this is not in a related reg class to the register we're allocating, // don't check it. const TargetRegisterClass *RegRC = mri_->getRegClass(reg); if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader) { @@ -1511,7 +1512,7 @@ unsigned Preference = vrm_->getRegAllocPref(cur->reg); if (Preference) { DEBUG(dbgs() << "(preferred: " << tri_->getName(Preference) << ") "); - if (isRegAvail(Preference) && + if (isRegAvail(Preference) && RC->contains(Preference)) return Preference; } From dalej at apple.com Wed Sep 1 16:57:20 2010 From: dalej at apple.com (Dale Johannesen) Date: Wed, 01 Sep 2010 21:57:20 -0000 Subject: [llvm-commits] [llvm] r112748 - /llvm/trunk/test/FrontendC/misaligned-param.c Message-ID: <20100901215720.802A02A6C12C@llvm.org> Author: johannes Date: Wed Sep 1 16:57:20 2010 New Revision: 112748 URL: http://llvm.org/viewvc/llvm-project?rev=112748&view=rev Log: Apparently only Darwin passes long double misaligned. Compensate. Modified: llvm/trunk/test/FrontendC/misaligned-param.c Modified: llvm/trunk/test/FrontendC/misaligned-param.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/misaligned-param.c?rev=112748&r1=112747&r2=112748&view=diff ============================================================================== --- llvm/trunk/test/FrontendC/misaligned-param.c (original) +++ llvm/trunk/test/FrontendC/misaligned-param.c Wed Sep 1 16:57:20 2010 @@ -1,7 +1,7 @@ // RUN: %llvmgcc %s -m32 -S -o - | FileCheck %s // Misaligned parameter must be memcpy'd to correctly aligned temporary. // XFAIL: * -// XTARGET: i386,i686,x86_64 +// XTARGET: i386-apple-darwin,i686-apple-darwin,x86_64-apple-darwin struct s { int x; long double y; }; long double foo(struct s x, int i, struct s y) { From stoklund at 2pi.dk Wed Sep 1 17:15:35 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 01 Sep 2010 22:15:35 -0000 Subject: [llvm-commits] [llvm] r112751 - in /llvm/trunk: lib/CodeGen/SimpleRegisterCoalescing.cpp test/CodeGen/X86/2010-09-01-RemoveCopyByCommutingDef.ll Message-ID: <20100901221535.8BF742A6C12C@llvm.org> Author: stoklund Date: Wed Sep 1 17:15:35 2010 New Revision: 112751 URL: http://llvm.org/viewvc/llvm-project?rev=112751&view=rev Log: Teach RemoveCopyByCommutingDef to check all aliases, not just subregisters. This caused a miscompilation in WebKit where %RAX had conflicting defs when RemoveCopyByCommutingDef was commuting a %EAX use. Added: llvm/trunk/test/CodeGen/X86/2010-09-01-RemoveCopyByCommutingDef.ll Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=112751&r1=112750&r2=112751&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original) +++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Wed Sep 1 17:15:35 2010 @@ -389,16 +389,12 @@ if (HasOtherReachingDefs(IntA, IntB, AValNo, BValNo)) return false; - bool BHasSubRegs = false; - if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) - BHasSubRegs = *tri_->getSubRegisters(IntB.reg); - - // Abort if the subregisters of IntB.reg have values that are not simply the + // Abort if the aliases of IntB.reg have values that are not simply the // clobbers from the superreg. - if (BHasSubRegs) - for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) - if (li_->hasInterval(*SR) && - HasOtherReachingDefs(IntA, li_->getInterval(*SR), AValNo, 0)) + if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) + for (const unsigned *AS = tri_->getAliasSet(IntB.reg); *AS; ++AS) + if (li_->hasInterval(*AS) && + HasOtherReachingDefs(IntA, li_->getInterval(*AS), AValNo, 0)) return false; // If some of the uses of IntA.reg is already coalesced away, return false. @@ -415,6 +411,8 @@ return false; } + DEBUG(dbgs() << "\tRemoveCopyByCommutingDef: " << *DefMI); + // At this point we have decided that it is legal to do this // transformation. Start by commuting the instruction. MachineBasicBlock *MBB = DefMI->getParent(); @@ -478,7 +476,7 @@ if (UseMI->getOperand(0).getReg() != IntB.reg || UseMI->getOperand(0).getSubReg()) continue; - + // This copy will become a noop. If it's defining a new val#, // remove that val# as well. However this live range is being // extended to the end of the existing live range defined by the copy. @@ -503,13 +501,13 @@ // Remove val#'s defined by copies that will be coalesced away. for (unsigned i = 0, e = BDeadValNos.size(); i != e; ++i) { VNInfo *DeadVNI = BDeadValNos[i]; - if (BHasSubRegs) { - for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) { - if (!li_->hasInterval(*SR)) + if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) { + for (const unsigned *AS = tri_->getAliasSet(IntB.reg); *AS; ++AS) { + if (!li_->hasInterval(*AS)) continue; - LiveInterval &SRLI = li_->getInterval(*SR); - if (const LiveRange *SRLR = SRLI.getLiveRangeContaining(DeadVNI->def)) - SRLI.removeValNo(SRLR->valno); + LiveInterval &ASLI = li_->getInterval(*AS); + if (const LiveRange *ASLR = ASLI.getLiveRangeContaining(DeadVNI->def)) + ASLI.removeValNo(ASLR->valno); } } IntB.removeValNo(BDeadValNos[i]); Added: llvm/trunk/test/CodeGen/X86/2010-09-01-RemoveCopyByCommutingDef.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-09-01-RemoveCopyByCommutingDef.ll?rev=112751&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2010-09-01-RemoveCopyByCommutingDef.ll (added) +++ llvm/trunk/test/CodeGen/X86/2010-09-01-RemoveCopyByCommutingDef.ll Wed Sep 1 17:15:35 2010 @@ -0,0 +1,28 @@ +; RUN: llc < %s -verify-machineinstrs | FileCheck %s +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.0.0" + +; This test exercises the alias checking in SimpleRegisterCoalescing::RemoveCopyByCommutingDef. + +define void @f(i32* %w, i32* %h, i8* %_this, i8* %image) nounwind ssp { + %x1 = tail call i64 @g(i8* %_this, i8* %image) nounwind ; [#uses=3] + %tmp1 = trunc i64 %x1 to i32 ; [#uses=1] +; CHECK: movl (%r{{.*}}), % + %x4 = load i32* %h, align 4 ; [#uses=1] + +; The imull clobbers a 32-bit register. +; CHECK: imull %{{...}}, %e[[CLOBBER:..]] + %x5 = mul nsw i32 %x4, %tmp1 ; [#uses=1] + +; So we cannot use the corresponding 64-bit register anymore. +; CHECK-NOT: shrq $32, %r[[CLOBBER]] + %btmp3 = lshr i64 %x1, 32 ; [#uses=1] + %btmp4 = trunc i64 %btmp3 to i32 ; [#uses=1] + +; CHECK: idiv + %x6 = sdiv i32 %x5, %btmp4 ; [#uses=1] + store i32 %x6, i32* %w, align 4 + ret void +} + +declare i64 @g(i8*, i8*) From echristo at apple.com Wed Sep 1 17:16:27 2010 From: echristo at apple.com (Eric Christopher) Date: Wed, 01 Sep 2010 22:16:27 -0000 Subject: [llvm-commits] [llvm] r112752 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20100901221627.98A372A6C12C@llvm.org> Author: echristo Date: Wed Sep 1 17:16:27 2010 New Revision: 112752 URL: http://llvm.org/viewvc/llvm-project?rev=112752&view=rev Log: Some basic store support. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=112752&r1=112751&r2=112752&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Wed Sep 1 17:16:27 2010 @@ -106,6 +106,7 @@ // Instruction selection routines. virtual bool ARMSelectLoad(const Instruction *I); + virtual bool ARMSelectStore(const Instruction *I); // Utility routines. private: @@ -113,6 +114,7 @@ bool isLoadTypeLegal(const Type *Ty, EVT &VT); bool ARMEmitLoad(EVT VT, unsigned &ResultReg, unsigned Reg, int Offset); bool ARMLoadAlloca(const Instruction *I); + bool ARMStoreAlloca(const Instruction *I); bool ARMComputeRegOffset(const Value *Obj, unsigned &Reg, int &Offset); bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR); @@ -444,6 +446,43 @@ return true; } +bool ARMFastISel::ARMStoreAlloca(const Instruction *I) { + Value *Op1 = I->getOperand(1); + + // Verify it's an alloca. + if (const AllocaInst *AI = dyn_cast(Op1)) { + DenseMap::iterator SI = + FuncInfo.StaticAllocaMap.find(AI); + + if (SI != FuncInfo.StaticAllocaMap.end()) { + TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy()); + unsigned Reg = getRegForValue(I->getOperand(0)); + // Make sure we can get this into a register. + if (Reg == 0) return false; + TII.storeRegToStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt, + Reg, true /*isKill*/, SI->second, RC, + TM.getRegisterInfo()); + return true; + } + } + return false; +} + +bool ARMFastISel::ARMSelectStore(const Instruction *I) { + // If we're an alloca we know we have a frame index and can emit the store + // quickly. + if (ARMStoreAlloca(I)) + return true; + + // Yay type legalization + EVT VT; + if (!isLoadTypeLegal(I->getType(), VT)) + return false; + + return false; + +} + bool ARMFastISel::ARMSelectLoad(const Instruction *I) { // If we're an alloca we know we have a frame index and can emit the load // directly in short order. @@ -496,6 +535,8 @@ switch (I->getOpcode()) { case Instruction::Load: return ARMSelectLoad(I); + case Instruction::Store: + return ARMSelectStore(I); default: break; } return false; From bruno.cardoso at gmail.com Wed Sep 1 17:33:21 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Wed, 01 Sep 2010 22:33:21 -0000 Subject: [llvm-commits] [llvm] r112753 - in /llvm/trunk: lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/vec_shuffle-37.ll Message-ID: <20100901223321.2822F2A6C12C@llvm.org> Author: bruno Date: Wed Sep 1 17:33:20 2010 New Revision: 112753 URL: http://llvm.org/viewvc/llvm-project?rev=112753&view=rev Log: Using target specific nodes for shuffle nodes makes the mask check more strict, breaking some cases not checked in the testsuite, but also exposes some foldings not done before, as this example: movaps (%rdi), %xmm0 movaps (%rax), %xmm1 movaps %xmm0, %xmm2 movss %xmm1, %xmm2 shufps $36, %xmm2, %xmm0 now is generated as: movaps (%rdi), %xmm0 movaps %xmm0, %xmm1 movlps (%rax), %xmm1 shufps $36, %xmm1, %xmm0 Added: llvm/trunk/test/CodeGen/X86/vec_shuffle-37.ll Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=112753&r1=112752&r2=112753&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Sep 1 17:33:20 2010 @@ -5909,6 +5909,9 @@ def : Pat<(X86Movlps VR128:$src1, (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))), (MOVLPSrm VR128:$src1, addr:$src2)>; +def : Pat<(X86Movlps VR128:$src1, + (bc_v4i32 (v2i64 (load addr:$src2)))), + (MOVLPSrm VR128:$src1, addr:$src2)>; // Shuffle with MOVLPD def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))), Added: llvm/trunk/test/CodeGen/X86/vec_shuffle-37.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_shuffle-37.ll?rev=112753&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/vec_shuffle-37.ll (added) +++ llvm/trunk/test/CodeGen/X86/vec_shuffle-37.ll Wed Sep 1 17:33:20 2010 @@ -0,0 +1,14 @@ +; RUN: llc < %s -march=x86-64 | FileCheck %s + +define <4 x i32> @t00(<4 x i32>* %a0) nounwind ssp { +entry: +; CHECK: movaps (%rdi), %xmm0 +; CHECK-NEXT: movaps %xmm0, %xmm1 +; CHECK-NEXT: movlps (%rax), %xmm1 +; CHECK-NEXT: shufps $36, %xmm1, %xmm0 + %0 = load <4 x i32>* undef, align 16 + %1 = load <4 x i32>* %a0, align 16 + %2 = shufflevector <4 x i32> %1, <4 x i32> %0, <4 x i32> + ret <4 x i32> %2 +} + From dalej at apple.com Wed Sep 1 17:43:48 2010 From: dalej at apple.com (Dale Johannesen) Date: Wed, 01 Sep 2010 22:43:48 -0000 Subject: [llvm-commits] [llvm] r112754 - /llvm/trunk/include/llvm/IntrinsicsX86.td Message-ID: <20100901224348.909ED2A6C12C@llvm.org> Author: johannes Date: Wed Sep 1 17:43:48 2010 New Revision: 112754 URL: http://llvm.org/viewvc/llvm-project?rev=112754&view=rev Log: Recommit with changes. Comment out palignr for the moment, as there's a testcase that uses it and expects it to be subject to optimizations; we won't be doing that. Some adjustments based on feedback from Bill. Modified: llvm/trunk/include/llvm/IntrinsicsX86.td Modified: llvm/trunk/include/llvm/IntrinsicsX86.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsX86.td?rev=112754&r1=112753&r2=112754&view=diff ============================================================================== --- llvm/trunk/include/llvm/IntrinsicsX86.td (original) +++ llvm/trunk/include/llvm/IntrinsicsX86.td Wed Sep 1 17:43:48 2010 @@ -630,6 +630,9 @@ def int_x86_ssse3_pshuf_b_128 : GCCBuiltin<"__builtin_ia32_pshufb128">, Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>; + def int_x86_ssse3_pshuf_w : GCCBuiltin<"__builtin_ia32_pshufw">, + Intrinsic<[llvm_v4i16_ty], [llvm_v4i16_ty, llvm_i32_ty], + [IntrNoMem]>; } // Sign ops @@ -1567,12 +1570,20 @@ def int_x86_mmx_movnt_dq : GCCBuiltin<"__builtin_ia32_movntq">, Intrinsic<[], [llvm_ptr_ty, llvm_v1i64_ty], []>; - def int_x86_mmx_cvtsi32_MMX : GCCBuiltin<"__builtin_ia32_vec_init_v2si">, +// def int_x86_mmx_palignr_b : GCCBuiltin<"__builtin_ia32_palignr">, +// Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, +// llvm_v1i64_ty, llvm_i8_ty], [IntrNoMem]>; + + def int_x86_mmx_pextr_w : + Intrinsic<[llvm_i32_ty], [llvm_v1i64_ty, llvm_i32_ty], + [IntrNoMem]>; + + def int_x86_mmx_pinsr_w : + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, + llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; + + def int_x86_mmx_cvtsi32_si64 : Intrinsic<[llvm_v1i64_ty], [llvm_i32_ty], [IntrNoMem]>; - def int_x86_mmx_cvtsi64_MMX : - Intrinsic<[llvm_v1i64_ty], [llvm_i64_ty], [IntrNoMem]>; - def int_x86_mmx_MMX_si32 : GCCBuiltin<"__builtin_ia32_vec_ext_v2si">, + def int_x86_mmx_cvtsi64_si32 : Intrinsic<[llvm_i32_ty], [llvm_v1i64_ty], [IntrNoMem]>; - def int_x86_mmx_MMX_si64 : - Intrinsic<[llvm_i64_ty], [llvm_v1i64_ty], [IntrNoMem]>; } From grosbach at apple.com Wed Sep 1 17:48:34 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 01 Sep 2010 22:48:34 -0000 Subject: [llvm-commits] [llvm] r112756 - /llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Message-ID: <20100901224834.95EFC2A6C12C@llvm.org> Author: grosbach Date: Wed Sep 1 17:48:34 2010 New Revision: 112756 URL: http://llvm.org/viewvc/llvm-project?rev=112756&view=rev Log: Tweak to ignoring reserved regs. The allocator was occasionally still looking at them since they'd end up in the register weights list. Tell it to stop doing that. Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp?rev=112756&r1=112755&r2=112756&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Wed Sep 1 17:48:34 2010 @@ -1147,9 +1147,11 @@ e = RC->allocation_order_end(*mf_); i != e; ++i) { unsigned reg = *i; float regWeight = SpillWeights[reg]; + // Don't even consider reserved regs. + if (reservedRegs_.test(reg)) + continue; // Skip recently allocated registers and reserved registers. - if (minWeight > regWeight && !isRecentlyUsed(reg) && - !reservedRegs_.test(reg)) + if (minWeight > regWeight && !isRecentlyUsed(reg)) Found = true; RegsWeights.push_back(std::make_pair(reg, regWeight)); } From sabre at nondot.org Wed Sep 1 17:48:52 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 01 Sep 2010 22:48:52 -0000 Subject: [llvm-commits] [www-pubs] r112757 - /www-pubs/trunk/TEMPLATE-Paper.html Message-ID: <20100901224852.819DB2A6C12C@llvm.org> Author: lattner Date: Wed Sep 1 17:48:52 2010 New Revision: 112757 URL: http://llvm.org/viewvc/llvm-project?rev=112757&view=rev Log: add another template. Added: www-pubs/trunk/TEMPLATE-Paper.html Added: www-pubs/trunk/TEMPLATE-Paper.html URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/TEMPLATE-Paper.html?rev=112757&view=auto ============================================================================== --- www-pubs/trunk/TEMPLATE-Paper.html (added) +++ www-pubs/trunk/TEMPLATE-Paper.html Wed Sep 1 17:48:52 2010 @@ -0,0 +1,54 @@ + + + + + + TITLE + + + +
      + TITLE +
      +
      + AUTHOR +
      + +

      Abstract:

      +
      +

      +ABSTRACT +

      +
      + +

      Published:

      +
      + "TITLE"
      + AUTHOR
      +In Proceedings WHERE, +LOCATION, MONTH YEAR. +
      + +

      Download:

      +

      Paper:

      + + +

      BibTeX Entry:

      +
      +BIBTEX
+
      + + + +
      + Valid CSS! + Valid HTML 4.01! + + + From sabre at nondot.org Wed Sep 1 17:51:07 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 01 Sep 2010 22:51:07 -0000 Subject: [llvm-commits] [www-pubs] r112758 - in /www-pubs/trunk: 2010-09-HASKELLSYM-LLVM-GHC.html 2010-09-HASKELLSYM-LLVM-GHC.pdf pubs.js Message-ID: <20100901225107.7D3A02A6C12C@llvm.org> Author: lattner Date: Wed Sep 1 17:51:07 2010 New Revision: 112758 URL: http://llvm.org/viewvc/llvm-project?rev=112758&view=rev Log: add "An LLVM Backend for GHC" Added: www-pubs/trunk/2010-09-HASKELLSYM-LLVM-GHC.html www-pubs/trunk/2010-09-HASKELLSYM-LLVM-GHC.pdf (with props) Modified: www-pubs/trunk/pubs.js Added: www-pubs/trunk/2010-09-HASKELLSYM-LLVM-GHC.html URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/2010-09-HASKELLSYM-LLVM-GHC.html?rev=112758&view=auto ============================================================================== --- www-pubs/trunk/2010-09-HASKELLSYM-LLVM-GHC.html (added) +++ www-pubs/trunk/2010-09-HASKELLSYM-LLVM-GHC.html Wed Sep 1 17:51:07 2010 @@ -0,0 +1,58 @@ + + + + + + An LLVM Backend for GHC + + + +
      + An LLVM Backend for GHC +
      +
      + David A. Terei and Manuel M. T. Chakravarty +
      + +

      Abstract:

      +
      +

      +In the presence of ever-changing computer architectures, high-quality optimising +compiler backends are moving targets that require specialist knowledge and +sophisticated algorithms. In this paper, we explore a new backend for the +Glasgow Haskell Compiler (GHC) that leverages the Low Level Virtual Machine +(LLVM), a new breed of compiler written explicitly for use by other compiler +writers, not high-level programmers, that promises to enable outsourcing of +low-level and architecture-dependent aspects of code generation. We discuss the +conceptual challenges and our backend design. We also provide an extensive +quantitative evaluation of the performance of the backend and of the code it +produces. +

      +
      + +

      Published:

      +
      + "An LLVM Backend for GHC"
      + David A. Terei and Manuel M. T. Chakravarty
      +In Proceedings ACM SIGPLAN Haskell Symposium 2010, +Baltimore MD, United States, September 2010. +
      + +

      Download:

      +

      Paper:

      + + + + +
      + Valid CSS! + Valid HTML 4.01! + + + Added: www-pubs/trunk/2010-09-HASKELLSYM-LLVM-GHC.pdf URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/2010-09-HASKELLSYM-LLVM-GHC.pdf?rev=112758&view=auto ============================================================================== Binary file - no diff available. Propchange: www-pubs/trunk/2010-09-HASKELLSYM-LLVM-GHC.pdf ------------------------------------------------------------------------------ svn:mime-type = application/octet-stream Modified: www-pubs/trunk/pubs.js URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/pubs.js?rev=112758&r1=112757&r2=112758&view=diff ============================================================================== --- www-pubs/trunk/pubs.js (original) +++ www-pubs/trunk/pubs.js Wed Sep 1 17:51:07 2010 @@ -1,6 +1,13 @@ // The array should be sorted reverse-chronologically, and will be displayed on // the page in the order listed. var PUBS = [ + {url: "2010-09-HASKELLSYM-LLVM-GHC.html", + title: "An LLVM Backend for GHC", + published: "ACM SIGPLAN Haskell Symposium 2010", + location: "Baltimore, Maryland", + author: "David A. Terei and Manuel M. T. Chakravarty", + month: 9, + year: 2010}, {url: "2010-08-SBLP-SSI.html", title: "Efficient SSI Conversion", published: "Brazilian Symposium on Programming Languages 2010", From bruno.cardoso at gmail.com Wed Sep 1 17:59:03 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Wed, 01 Sep 2010 22:59:03 -0000 Subject: [llvm-commits] [llvm] r112760 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20100901225903.9AF172A6C12C@llvm.org> Author: bruno Date: Wed Sep 1 17:59:03 2010 New Revision: 112760 URL: http://llvm.org/viewvc/llvm-project?rev=112760&view=rev Log: Revert r112689, avoid those kind of checks cause they mess up with mmx Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=112760&r1=112759&r2=112760&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Sep 1 17:59:03 2010 @@ -5194,10 +5194,10 @@ unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp); - if (HasSSE2 && NumElems == 4) + if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32)) return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG); - if (HasSSE2 && NumElems == 2) + if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64)) return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V1, TargetMask, DAG); @@ -5226,10 +5226,10 @@ if (ISD::isBuildVectorAllZeros(V1.getNode())) return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); if (!isMMX && !X86::isMOVLPMask(SVOp)) { - if (HasSSE2 && NumElems == 2) + if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64)) return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); - if (NumElems == 4) + if (VT == MVT::v4i32 || VT == MVT::v4f32) return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); } } From sabre at nondot.org Wed Sep 1 18:09:28 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 01 Sep 2010 23:09:28 -0000 Subject: [llvm-commits] [llvm] r112763 - in /llvm/trunk: lib/Transforms/Scalar/ScalarReplAggregates.cpp test/Transforms/ScalarRepl/vector_promote.ll Message-ID: <20100901230928.185842A6C12C@llvm.org> Author: lattner Date: Wed Sep 1 18:09:27 2010 New Revision: 112763 URL: http://llvm.org/viewvc/llvm-project?rev=112763&view=rev Log: deepen my MMX/SRoA hack to avoid hurting non-x86 codegen. Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp llvm/trunk/test/Transforms/ScalarRepl/vector_promote.ll Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=112763&r1=112762&r2=112763&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Wed Sep 1 18:09:27 2010 @@ -28,6 +28,7 @@ #include "llvm/Instructions.h" #include "llvm/IntrinsicInst.h" #include "llvm/LLVMContext.h" +#include "llvm/Module.h" #include "llvm/Pass.h" #include "llvm/Analysis/Dominators.h" #include "llvm/Target/TargetData.h" @@ -197,7 +198,12 @@ /// IsVerbotenVectorType - Return true if this is a vector type ScalarRepl isn't /// allowed to form. We do this to avoid MMX types, which is a complete hack, /// but is required until the backend is fixed. -static bool IsVerbotenVectorType(const VectorType *VTy) { +static bool IsVerbotenVectorType(const VectorType *VTy, const Instruction *I) { + StringRef Triple(I->getParent()->getParent()->getParent()->getTargetTriple()); + if (!Triple.startswith("i386") && + !Triple.startswith("x86_64")) + return false; + // Reject all the MMX vector types. switch (VTy->getNumElements()) { default: return false; @@ -226,7 +232,7 @@ // involved, then we probably really do have a union of vector/array. const Type *NewTy; if (VectorTy && VectorTy->isVectorTy() && HadAVector && - !IsVerbotenVectorType(cast(VectorTy))) { + !IsVerbotenVectorType(cast(VectorTy), AI)) { DEBUG(dbgs() << "CONVERT TO VECTOR: " << *AI << "\n TYPE = " << *VectorTy << '\n'); NewTy = VectorTy; // Use the vector type. Modified: llvm/trunk/test/Transforms/ScalarRepl/vector_promote.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ScalarRepl/vector_promote.ll?rev=112763&r1=112762&r2=112763&view=diff ============================================================================== --- llvm/trunk/test/Transforms/ScalarRepl/vector_promote.ll (original) +++ llvm/trunk/test/Transforms/ScalarRepl/vector_promote.ll Wed Sep 1 18:09:27 2010 @@ -1,5 +1,6 @@ ; RUN: opt < %s -scalarrepl -S | FileCheck %s target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" +target triple = "x86_64-apple-darwin10.0.0" define void @test1(<4 x float>* %F, float %f) { entry: From sabre at nondot.org Wed Sep 1 18:27:10 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 01 Sep 2010 23:27:10 -0000 Subject: [llvm-commits] [www] r112765 - /www/trunk/devmtg/2010-11/index.html Message-ID: <20100901232710.D26D02A6C12C@llvm.org> Author: lattner Date: Wed Sep 1 18:27:10 2010 New Revision: 112765 URL: http://llvm.org/viewvc/llvm-project?rev=112765&view=rev Log: mention lldb as well as a bunch of other llvm subprojects. Modified: www/trunk/devmtg/2010-11/index.html Modified: www/trunk/devmtg/2010-11/index.html URL: http://llvm.org/viewvc/llvm-project/www/trunk/devmtg/2010-11/index.html?rev=112765&r1=112764&r2=112765&view=diff ============================================================================== --- www/trunk/devmtg/2010-11/index.html (original) +++ www/trunk/devmtg/2010-11/index.html Wed Sep 1 18:27:10 2010 @@ -24,17 +24,19 @@ p://google.com">Google, Adobe, Qualcomm Incorporated

      --> -

      The meeting serves as a forum for both LLVM -and Clang developers and users to get acquainted, lea -rn how LLVM is used, and +

      The meeting serves as a forum for LLVM, +Clang, LLDB and +other LLVM project developers and users to get acquainted, learn how LLVM is used, and exchange ideas about LLVM and its (potential) applications. More broadly, we believe the event will be of particular interest to the following people:

        -
      • Active LLVM and Clang developers and users.
        • -
      • Anyone interested in using LLVM or Clang.
        • +
      • Active developers of projects in the LLVM Umbrella +(LLVM core, Clang, LLDB, libc++, compiler_rt, klee, dragonegg, etc).
        • +
      • Anyone interested in using these as part of another project.
      • Compiler, programming language, and runtime enthusiasts.
        • -
      • Those interested in using compiler technology in novel and interesting ways.
        • +
      • Those interested in using compiler and toolchain technology in novel +and interesting ways.
      Registration & Logistics
      @@ -44,7 +46,8 @@
      Call for Speakers

      We are looking for speakers for this year's developers meeting! Specifically -we'd love talks on the LLVM or Clang core infrastructure or new uses of LLVM or Clang.

      +we'd love talks on the LLVM, Clang, LLDB, core infrastructure, new uses and +applications of LLVM components, etc.

      If you are interested in presenting at this year's LLVM Developers' Meeting, please submit your talk proposal to us by September 22, 2010 via the website.

      From gohman at apple.com Wed Sep 1 18:33:02 2010 From: gohman at apple.com (Dan Gohman) Date: Wed, 01 Sep 2010 23:33:02 -0000 Subject: [llvm-commits] [llvm] r112767 - /llvm/trunk/include/llvm/Support/SystemUtils.h Message-ID: <20100901233302.C41E52A6C12C@llvm.org> Author: djg Date: Wed Sep 1 18:33:02 2010 New Revision: 112767 URL: http://llvm.org/viewvc/llvm-project?rev=112767&view=rev Log: Reword this comment. Don't mention outs(), as that's not what this code is actually testing for. Modified: llvm/trunk/include/llvm/Support/SystemUtils.h Modified: llvm/trunk/include/llvm/Support/SystemUtils.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/SystemUtils.h?rev=112767&r1=112766&r2=112767&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/SystemUtils.h (original) +++ llvm/trunk/include/llvm/Support/SystemUtils.h Wed Sep 1 18:33:02 2010 @@ -21,10 +21,9 @@ class raw_ostream; namespace sys { class Path; } -/// Determine if the raw_ostream provided is connected to the outs() and -/// displayed or not (to a console window). If so, generate a warning message -/// advising against display of bitcode and return true. Otherwise just return -/// false +/// Determine if the raw_ostream provided is connected to a terminal. If so, +/// generate a warning message to errs() advising against display of bitcode +/// and return true. Otherwise just return false. /// @brief Check for output written to a console bool CheckBitcodeOutputToConsole( raw_ostream &stream_to_check, ///< The stream to be checked From sabre at nondot.org Wed Sep 1 18:38:48 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 01 Sep 2010 23:38:48 -0000 Subject: [llvm-commits] [www-pubs] r112771 - in /www-pubs/trunk: 2008-09-Lightspark.html 2008-09-Lightspark.pdf pubs.js Message-ID: <20100901233848.5E2842A6C12C@llvm.org> Author: lattner Date: Wed Sep 1 18:38:48 2010 New Revision: 112771 URL: http://llvm.org/viewvc/llvm-project?rev=112771&view=rev Log: add lightspark thesis, "An Efficient ActionScript 3.0 Just-In-Time Compiler Implementation" Added: www-pubs/trunk/2008-09-Lightspark.html www-pubs/trunk/2008-09-Lightspark.pdf (with props) Modified: www-pubs/trunk/pubs.js Added: www-pubs/trunk/2008-09-Lightspark.html URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/2008-09-Lightspark.html?rev=112771&view=auto ============================================================================== --- www-pubs/trunk/2008-09-Lightspark.html (added) +++ www-pubs/trunk/2008-09-Lightspark.html Wed Sep 1 18:38:48 2010 @@ -0,0 +1,41 @@ + + + + + + An Efficient ActionScript 3.0 Just-In-Time Compiler Implementation + + + +
      + An Efficient ActionScript 3.0 Just-In-Time Compiler Implementation +
      +
      + Alessandro Pignotti, B.S. Thesis +
      + + +

      Abstract:

      +
      +Adobe Flash: the current de facto standard for rich content web applications is +powered by an ECMAScript derived language called Action-Script. The bytecode +for the language is designed to run on a stack based virtual machine. We +introduce a Just in Time compiler and runtime en- vironment for such bytecode. +The LLVM framework is used to generate optimized native assembly from an +intermediate representation, generated from the bytecode while optimizing stack +traffic, local variable accesses and exploiting implicit type information. +
      + +

      Published:

      +
      + An Efficient ActionScript 3.0 Just-In-Time Compiler Implementation, + Alessandro Pignotti.
      + Bachelor Thesis, Universita degli Studi di Pisa, September 2008 +
      + +

      Download:

      + + + Added: www-pubs/trunk/2008-09-Lightspark.pdf URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/2008-09-Lightspark.pdf?rev=112771&view=auto ============================================================================== Binary file - no diff available. Propchange: www-pubs/trunk/2008-09-Lightspark.pdf ------------------------------------------------------------------------------ svn:mime-type = application/octet-stream Modified: www-pubs/trunk/pubs.js URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/pubs.js?rev=112771&r1=112770&r2=112771&view=diff ============================================================================== --- www-pubs/trunk/pubs.js (original) +++ www-pubs/trunk/pubs.js Wed Sep 1 18:38:48 2010 @@ -594,6 +594,13 @@ published: "Proc. International Conference on Principles and Practice of Programming In Java (PPPJ 2008)", month: 9, year: 2008}, + + {url: "2008-09-Lightspark.html", + title: "An Efficient ActionScript 3.0 Just-In-Time Compiler Implementation", + author: "Alessandro Pignotti", + published: "Bachelor Thesis, Universita degli Studi di Pisa", + month: 9, + year: 2008}, {url: '2008-08-RTCodegen.html', title: 'Run-Time Code Generation for Materials', From clattner at apple.com Wed Sep 1 18:43:24 2010 From: clattner at apple.com (Chris Lattner) Date: Wed, 1 Sep 2010 16:43:24 -0700 Subject: [llvm-commits] [PATCH] Bugpoint/Support: Fix llvm::FindExecutable not looking for files ending with .exe In-Reply-To: References: <4CAB5B77-B4EB-4E91-B861-D9DE27867AE7@apple.com> Message-ID: <3D2BD0D9-026E-4147-9E99-0F56FCB83E28@apple.com> Looks good to me, please commit! On Aug 31, 2010, at 2:05 PM, NAKAMURA Takumi wrote: > Michael, > > An refined patch is attached. Please take a look. > Confirmed on mingw, mingw-cross, f12 and centos5. > > - get rid of extra sys::Path variable FoundPath > - suppose value of FindProgramByName() must be valid when it is not empty > > > ...Takumi > From clattner at apple.com Wed Sep 1 18:44:21 2010 From: clattner at apple.com (Chris Lattner) Date: Wed, 1 Sep 2010 16:44:21 -0700 Subject: [llvm-commits] [PATCH] test/CodeGen/X86 patches for win32 In-Reply-To: References: Message-ID: <0C45983F-0D48-4990-8170-1E69E7CB2D41@apple.com> Looks good to me, please commit! On Aug 31, 2010, at 3:00 PM, NAKAMURA Takumi wrote: > Good morning. > > This patch is set of tweaks for win32 to test/CodeGen/X86 > Some issues are on win32. > > - EH is disabled by default. > - @main() with extra calling __main. > - stack allocatoin > > In fact, all tests in CodeGen/X86 pass on Cygwin, > but I am not sure my patch would be reasonable. > Please review it. > > > ...Takumi > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From bob.wilson at apple.com Wed Sep 1 18:46:59 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Wed, 01 Sep 2010 23:46:59 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r112772 - /llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp Message-ID: <20100901234659.2AD5A2A6C12C@llvm.org> Author: bwilson Date: Wed Sep 1 18:46:58 2010 New Revision: 112772 URL: http://llvm.org/viewvc/llvm-project?rev=112772&view=rev Log: Translate NEON vmull, vmlal, and vmlsl builtins to llvm multiply-add/sub with zext/sext operations, instead of to llvm intrinsics. Modified: llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp Modified: llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp?rev=112772&r1=112771&r2=112772&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp Wed Sep 1 18:46:58 2010 @@ -929,15 +929,17 @@ return UnexpectedError("%Hinvalid lane number", exp, Result); Ops[2] = BuildDupLane(Ops[2], LaneVal, NUnits, Builder); } - if (datatype == neon_datatype_signed) - intID = Intrinsic::arm_neon_vmlals; - else if (datatype == neon_datatype_unsigned) - intID = Intrinsic::arm_neon_vmlalu; - else + if (datatype == neon_datatype_signed) { + Ops[1] = Builder.CreateSExt(Ops[1], ResultType); + Ops[2] = Builder.CreateSExt(Ops[2], ResultType); + } else if (datatype == neon_datatype_unsigned) { + Ops[1] = Builder.CreateZExt(Ops[1], ResultType); + Ops[2] = Builder.CreateZExt(Ops[2], ResultType); + } else return BadImmediateError(exp, Result); - intFn = Intrinsic::getDeclaration(TheModule, intID, &ResultType, 1); - Result = Builder.CreateCall3(intFn, Ops[0], Ops[1], Ops[2]); + Ops[1] = Builder.CreateMul(Ops[1], Ops[2]); + Result = Builder.CreateAdd(Ops[0], Ops[1]); break; case NEON_BUILTIN_vmlsl_lane: @@ -952,15 +954,17 @@ return UnexpectedError("%Hinvalid lane number", exp, Result); Ops[2] = BuildDupLane(Ops[2], LaneVal, NUnits, Builder); } - if (datatype == neon_datatype_signed) - intID = Intrinsic::arm_neon_vmlsls; - else if (datatype == neon_datatype_unsigned) - intID = Intrinsic::arm_neon_vmlslu; - else + if (datatype == neon_datatype_signed) { + Ops[1] = Builder.CreateSExt(Ops[1], ResultType); + Ops[2] = Builder.CreateSExt(Ops[2], ResultType); + } else if (datatype == neon_datatype_unsigned) { + Ops[1] = Builder.CreateZExt(Ops[1], ResultType); + Ops[2] = Builder.CreateZExt(Ops[2], ResultType); + } else return BadImmediateError(exp, Result); - intFn = Intrinsic::getDeclaration(TheModule, intID, &ResultType, 1); - Result = Builder.CreateCall3(intFn, Ops[0], Ops[1], Ops[2]); + Ops[1] = Builder.CreateMul(Ops[1], Ops[2]); + Result = Builder.CreateSub(Ops[0], Ops[1]); break; case NEON_BUILTIN_vqdmulh_lane: @@ -1040,17 +1044,22 @@ return UnexpectedError("%Hinvalid lane number", exp, Result); Ops[1] = BuildDupLane(Ops[1], LaneVal, NUnits, Builder); } - if (datatype == neon_datatype_polynomial) + if (datatype == neon_datatype_polynomial) { intID = Intrinsic::arm_neon_vmullp; - else if (datatype == neon_datatype_signed) - intID = Intrinsic::arm_neon_vmulls; - else if (datatype == neon_datatype_unsigned) - intID = Intrinsic::arm_neon_vmullu; - else + intFn = Intrinsic::getDeclaration(TheModule, intID, &ResultType, 1); + Result = Builder.CreateCall2(intFn, Ops[0], Ops[1]); + break; + } + if (datatype == neon_datatype_signed) { + Ops[0] = Builder.CreateSExt(Ops[0], ResultType); + Ops[1] = Builder.CreateSExt(Ops[1], ResultType); + } else if (datatype == neon_datatype_unsigned) { + Ops[0] = Builder.CreateZExt(Ops[0], ResultType); + Ops[1] = Builder.CreateZExt(Ops[1], ResultType); + } else return BadImmediateError(exp, Result); - intFn = Intrinsic::getDeclaration(TheModule, intID, &ResultType, 1); - Result = Builder.CreateCall2(intFn, Ops[0], Ops[1]); + Result = Builder.CreateMul(Ops[0], Ops[1]); break; case NEON_BUILTIN_vqdmull_n: From bob.wilson at apple.com Wed Sep 1 18:50:19 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Wed, 01 Sep 2010 23:50:19 -0000 Subject: [llvm-commits] [llvm] r112773 - in /llvm/trunk: include/llvm/IntrinsicsARM.td lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMISelLowering.h lib/Target/ARM/ARMInstrNEON.td lib/VMCore/AutoUpgrade.cpp test/Bitcode/neon-intrinsics.ll test/Bitcode/neon-intrinsics.ll.bc test/CodeGen/ARM/vmla.ll test/CodeGen/ARM/vmls.ll test/CodeGen/ARM/vmul.ll Message-ID: <20100901235019.BAE602A6C12C@llvm.org> Author: bwilson Date: Wed Sep 1 18:50:19 2010 New Revision: 112773 URL: http://llvm.org/viewvc/llvm-project?rev=112773&view=rev Log: Remove NEON vmull, vmlal, and vmlsl intrinsics, replacing them with multiply, add, and subtract operations with zero-extended or sign-extended vectors. Update tests. Add auto-upgrade support for the old intrinsics. Modified: llvm/trunk/include/llvm/IntrinsicsARM.td llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.h llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/lib/VMCore/AutoUpgrade.cpp llvm/trunk/test/Bitcode/neon-intrinsics.ll llvm/trunk/test/Bitcode/neon-intrinsics.ll.bc llvm/trunk/test/CodeGen/ARM/vmla.ll llvm/trunk/test/CodeGen/ARM/vmls.ll llvm/trunk/test/CodeGen/ARM/vmul.ll Modified: llvm/trunk/include/llvm/IntrinsicsARM.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsARM.td?rev=112773&r1=112772&r2=112773&view=diff ============================================================================== --- llvm/trunk/include/llvm/IntrinsicsARM.td (original) +++ llvm/trunk/include/llvm/IntrinsicsARM.td Wed Sep 1 18:50:19 2010 @@ -129,16 +129,8 @@ def int_arm_neon_vmulp : Neon_2Arg_Intrinsic; def int_arm_neon_vqdmulh : Neon_2Arg_Intrinsic; def int_arm_neon_vqrdmulh : Neon_2Arg_Intrinsic; - def int_arm_neon_vmulls : Neon_2Arg_Long_Intrinsic; - def int_arm_neon_vmullu : Neon_2Arg_Long_Intrinsic; def int_arm_neon_vmullp : Neon_2Arg_Long_Intrinsic; def int_arm_neon_vqdmull : Neon_2Arg_Long_Intrinsic; - - // Vector Multiply and Accumulate/Subtract. - def int_arm_neon_vmlals : Neon_3Arg_Long_Intrinsic; - def int_arm_neon_vmlalu : Neon_3Arg_Long_Intrinsic; - def int_arm_neon_vmlsls : Neon_3Arg_Long_Intrinsic; - def int_arm_neon_vmlslu : Neon_3Arg_Long_Intrinsic; def int_arm_neon_vqdmlal : Neon_3Arg_Long_Intrinsic; def int_arm_neon_vqdmlsl : Neon_3Arg_Long_Intrinsic; @@ -302,7 +294,7 @@ def int_arm_neon_vcvtfxs2fp : Neon_CvtFxToFP_Intrinsic; def int_arm_neon_vcvtfxu2fp : Neon_CvtFxToFP_Intrinsic; -// Narrowing and Lengthening Vector Moves. +// Narrowing Saturating Vector Moves. def int_arm_neon_vqmovns : Neon_1Arg_Narrow_Intrinsic; def int_arm_neon_vqmovnu : Neon_1Arg_Narrow_Intrinsic; def int_arm_neon_vqmovnsu : Neon_1Arg_Narrow_Intrinsic; Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=112773&r1=112772&r2=112773&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Sep 1 18:50:19 2010 @@ -326,7 +326,10 @@ // Neon does not support some operations on v1i64 and v2i64 types. setOperationAction(ISD::MUL, MVT::v1i64, Expand); - setOperationAction(ISD::MUL, MVT::v2i64, Expand); + // Custom handling for some quad-vector types to detect VMULL. + setOperationAction(ISD::MUL, MVT::v8i16, Custom); + setOperationAction(ISD::MUL, MVT::v4i32, Custom); + setOperationAction(ISD::MUL, MVT::v2i64, Custom); setOperationAction(ISD::VSETCC, MVT::v1i64, Expand); setOperationAction(ISD::VSETCC, MVT::v2i64, Expand); @@ -684,6 +687,8 @@ case ARMISD::VZIP: return "ARMISD::VZIP"; case ARMISD::VUZP: return "ARMISD::VUZP"; case ARMISD::VTRN: return "ARMISD::VTRN"; + case ARMISD::VMULLs: return "ARMISD::VMULLs"; + case ARMISD::VMULLu: return "ARMISD::VMULLu"; case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR"; case ARMISD::FMAX: return "ARMISD::FMAX"; case ARMISD::FMIN: return "ARMISD::FMIN"; @@ -3751,6 +3756,51 @@ return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val); } +/// SkipExtension - For a node that is either a SIGN_EXTEND, ZERO_EXTEND, or +/// an extending load, return the unextended value. +static SDValue SkipExtension(SDNode *N, SelectionDAG &DAG) { + if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND) + return N->getOperand(0); + LoadSDNode *LD = cast(N); + return DAG.getLoad(LD->getMemoryVT(), N->getDebugLoc(), LD->getChain(), + LD->getBasePtr(), LD->getSrcValue(), + LD->getSrcValueOffset(), LD->isVolatile(), + LD->isNonTemporal(), LD->getAlignment()); +} + +static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) { + // Multiplications are only custom-lowered for 128-bit vectors so that + // VMULL can be detected. Otherwise v2i64 multiplications are not legal. + EVT VT = Op.getValueType(); + assert(VT.is128BitVector() && "unexpected type for custom-lowering ISD::MUL"); + SDNode *N0 = Op.getOperand(0).getNode(); + SDNode *N1 = Op.getOperand(1).getNode(); + unsigned NewOpc = 0; + if ((N0->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N0)) && + (N1->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N1))) { + NewOpc = ARMISD::VMULLs; + } else if ((N0->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N0)) && + (N1->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N1))) { + NewOpc = ARMISD::VMULLu; + } else if (VT.getSimpleVT().SimpleTy == MVT::v2i64) { + // Fall through to expand this. It is not legal. + return SDValue(); + } else { + // Other vector multiplications are legal. + return Op; + } + + // Legalize to a VMULL instruction. + DebugLoc DL = Op.getDebugLoc(); + SDValue Op0 = SkipExtension(N0, DAG); + SDValue Op1 = SkipExtension(N1, DAG); + + assert(Op0.getValueType().is64BitVector() && + Op1.getValueType().is64BitVector() && + "unexpected types for extended operands to VMULL"); + return DAG.getNode(NewOpc, DL, VT, Op0, Op1); +} + SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { switch (Op.getOpcode()) { default: llvm_unreachable("Don't know how to custom lower this!"); @@ -3792,6 +3842,7 @@ case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); + case ISD::MUL: return LowerMUL(Op, DAG); } return SDValue(); } Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=112773&r1=112772&r2=112773&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Wed Sep 1 18:50:19 2010 @@ -145,6 +145,10 @@ VUZP, // unzip (deinterleave) VTRN, // transpose + // Vector multiply long: + VMULLs, // ...signed + VMULLu, // ...unsigned + // Operands of the standard BUILD_VECTOR node are not legalized, which // is fine if BUILD_VECTORs are always lowered to shuffles or other // operations, but for ARM some BUILD_VECTORs are legal as-is and their Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=112773&r1=112772&r2=112773&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Wed Sep 1 18:50:19 2010 @@ -93,6 +93,11 @@ def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>; def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>; +def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>, + SDTCisSameAs<1, 2>]>; +def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>; +def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>; + def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>]>; def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>; @@ -1255,6 +1260,42 @@ [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2), (OpTy QPR:$src3))))]>; +// Long Multiply-Add/Sub operations. +class N3VLMulOp op21_20, bits<4> op11_8, bit op4, + InstrItinClass itin, string OpcodeStr, string Dt, + ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode> + : N3V; +class N3VLMulOpSL op21_20, bits<4> op11_8, + InstrItinClass itin, string OpcodeStr, string Dt, + ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode> + : N3V; +class N3VLMulOpSL16 op21_20, bits<4> op11_8, + InstrItinClass itin, string OpcodeStr, string Dt, + ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode> + : N3V; + + // Neon Long 3-argument intrinsic. The destination register is // a quad-register and is also used as the first source operand register. class N3VLInt3 op21_20, bits<4> op11_8, bit op4, @@ -1306,8 +1347,37 @@ // Long 3-register operations. class N3VL op21_20, bits<4> op11_8, bit op4, InstrItinClass itin, string OpcodeStr, string Dt, - ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp, - bit Commutable> + ValueType TyQ, ValueType TyD, SDNode OpNode, bit Commutable> + : N3V { + let isCommutable = Commutable; +} +class N3VLSL op21_20, bits<4> op11_8, + InstrItinClass itin, string OpcodeStr, string Dt, + ValueType TyQ, ValueType TyD, SDNode OpNode> + : N3V; +class N3VLSL16 op21_20, bits<4> op11_8, + InstrItinClass itin, string OpcodeStr, string Dt, + ValueType TyQ, ValueType TyD, SDNode OpNode> + : N3V; + +// Long 3-register operations with explicitly extended operands. +class N3VLExt op21_20, bits<4> op11_8, bit op4, + InstrItinClass itin, string OpcodeStr, string Dt, + ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp, + bit Commutable> : N3V op11_8, bit op4, InstrItinClass itin16, InstrItinClass itin32, string OpcodeStr, string Dt, - SDNode OpNode, SDNode ExtOp, bit Commutable = 0> { + SDNode OpNode, bit Commutable = 0> { + def v8i16 : N3VL; def v4i32 : N3VL; + v4i32, v4i16, OpNode, Commutable>; def v2i64 : N3VL; - def v8i16 : N3VL; + v2i64, v2i32, OpNode, Commutable>; +} + +multiclass N3VLSL_HS op11_8, + InstrItinClass itin, string OpcodeStr, string Dt, + SDNode OpNode> { + def v4i16 : N3VLSL16; + def v2i32 : N3VLSL; +} + +multiclass N3VLExt_QHS op11_8, bit op4, + InstrItinClass itin16, InstrItinClass itin32, + string OpcodeStr, string Dt, + SDNode OpNode, SDNode ExtOp, bit Commutable = 0> { + def v8i16 : N3VLExt; + def v4i32 : N3VLExt; + def v2i64 : N3VLExt; } // Neon Long 3-register vector intrinsics. @@ -1857,6 +1951,29 @@ } +// Neon Long Multiply-Op vector operations, +// element sizes of 8, 16 and 32 bits: +multiclass N3VLMulOp_QHS op11_8, bit op4, + InstrItinClass itin16, InstrItinClass itin32, + string OpcodeStr, string Dt, SDNode MulOp, + SDNode OpNode> { + def v8i16 : N3VLMulOp; + def v4i32 : N3VLMulOp; + def v2i64 : N3VLMulOp; +} + +multiclass N3VLMulOpSL_HS op11_8, string OpcodeStr, + string Dt, SDNode MulOp, SDNode OpNode> { + def v4i16 : N3VLMulOpSL16; + def v2i32 : N3VLMulOpSL; +} + + // Neon Long 3-argument intrinsics. // First with only element sizes of 16 and 32 bits: @@ -2130,10 +2247,10 @@ def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32", v4f32, v4f32, fadd, 1>; // VADDL : Vector Add Long (Q = D + D) -defm VADDLs : N3VL_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD, - "vaddl", "s", add, sext, 1>; -defm VADDLu : N3VL_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD, - "vaddl", "u", add, zext, 1>; +defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD, + "vaddl", "s", add, sext, 1>; +defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD, + "vaddl", "u", add, zext, 1>; // VADDW : Vector Add Wide (Q = Q + D) defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>; defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>; @@ -2247,16 +2364,14 @@ (SubReg_i32_lane imm:$lane)))>; // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D) -defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D, - "vmull", "s", int_arm_neon_vmulls, 1>; -defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D, - "vmull", "u", int_arm_neon_vmullu, 1>; +defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D, + "vmull", "s", NEONvmulls, 1>; +defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D, + "vmull", "u", NEONvmullu, 1>; def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8", v8i16, v8i8, int_arm_neon_vmullp, 1>; -defm VMULLsls : N3VLIntSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", - int_arm_neon_vmulls>; -defm VMULLslu : N3VLIntSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", - int_arm_neon_vmullu>; +defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", NEONvmulls>; +defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", NEONvmullu>; // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D) defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D, @@ -2306,13 +2421,13 @@ (SubReg_i32_lane imm:$lane)))>; // VMLAL : Vector Multiply Accumulate Long (Q += D * D) -defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D, - "vmlal", "s", int_arm_neon_vmlals>; -defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D, - "vmlal", "u", int_arm_neon_vmlalu>; +defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D, + "vmlal", "s", NEONvmulls, add>; +defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D, + "vmlal", "u", NEONvmullu, add>; -defm VMLALsls : N3VLInt3SL_HS<0, 0b0010, "vmlal", "s", int_arm_neon_vmlals>; -defm VMLALslu : N3VLInt3SL_HS<1, 0b0010, "vmlal", "u", int_arm_neon_vmlalu>; +defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>; +defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>; // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D) defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D, @@ -2358,13 +2473,13 @@ (SubReg_i32_lane imm:$lane)))>; // VMLSL : Vector Multiply Subtract Long (Q -= D * D) -defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D, - "vmlsl", "s", int_arm_neon_vmlsls>; -defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D, - "vmlsl", "u", int_arm_neon_vmlslu>; +defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D, + "vmlsl", "s", NEONvmulls, sub>; +defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D, + "vmlsl", "u", NEONvmullu, sub>; -defm VMLSLsls : N3VLInt3SL_HS<0, 0b0110, "vmlsl", "s", int_arm_neon_vmlsls>; -defm VMLSLslu : N3VLInt3SL_HS<1, 0b0110, "vmlsl", "u", int_arm_neon_vmlslu>; +defm VMLSLsls : N3VLMulOpSL_HS<0, 0b0110, "vmlsl", "s", NEONvmulls, sub>; +defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>; // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D) defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D, @@ -2381,10 +2496,10 @@ def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32", v4f32, v4f32, fsub, 0>; // VSUBL : Vector Subtract Long (Q = D - D) -defm VSUBLs : N3VL_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD, - "vsubl", "s", sub, sext, 0>; -defm VSUBLu : N3VL_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD, - "vsubl", "u", sub, zext, 0>; +defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD, + "vsubl", "s", sub, sext, 0>; +defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD, + "vsubl", "u", sub, zext, 0>; // VSUBW : Vector Subtract Wide (Q = Q - D) defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>; defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>; Modified: llvm/trunk/lib/VMCore/AutoUpgrade.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AutoUpgrade.cpp?rev=112773&r1=112772&r2=112773&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/AutoUpgrade.cpp (original) +++ llvm/trunk/lib/VMCore/AutoUpgrade.cpp Wed Sep 1 18:50:19 2010 @@ -90,6 +90,12 @@ (Name.compare(19, 2, "s.", 2) == 0 || Name.compare(19, 2, "u.", 2) == 0)) || + ((Name.compare(14, 5, "vmull", 5) == 0 || + Name.compare(14, 5, "vmlal", 5) == 0 || + Name.compare(14, 5, "vmlsl", 5) == 0) && + (Name.compare(19, 2, "s.", 2) == 0 || + Name.compare(19, 2, "u.", 2) == 0)) || + (Name.compare(14, 6, "vmovn.", 6) == 0)) { // Calls to these are transformed into IR without intrinsics. @@ -359,6 +365,32 @@ return Upgraded; } +/// ExtendNEONArgs - For NEON "long" and "wide" operations, where the results +/// have vector elements twice as big as one or both source operands, do the +/// sign- or zero-extension that used to be handled by intrinsics. The +/// extended values are returned via V0 and V1. +static void ExtendNEONArgs(CallInst *CI, Value *Arg0, Value *Arg1, + Value *&V0, Value *&V1) { + Function *F = CI->getCalledFunction(); + const std::string& Name = F->getName(); + bool isLong = (Name.at(18) == 'l'); + bool isSigned = (Name.at(19) == 's'); + + if (isSigned) { + if (isLong) + V0 = new SExtInst(Arg0, CI->getType(), "", CI); + else + V0 = Arg0; + V1 = new SExtInst(Arg1, CI->getType(), "", CI); + } else { + if (isLong) + V0 = new ZExtInst(Arg0, CI->getType(), "", CI); + else + V0 = Arg0; + V1 = new ZExtInst(Arg1, CI->getType(), "", CI); + } +} + // UpgradeIntrinsicCall - Upgrade a call to an old intrinsic to be a call the // upgraded intrinsic. All argument and return casting must be provided in // order to seamlessly integrate with existing context. @@ -376,33 +408,32 @@ // Upgrade ARM NEON intrinsics. if (Name.compare(5, 9, "arm.neon.", 9) == 0) { Instruction *NewI; + Value *V0, *V1; if (Name.compare(14, 7, "vmovls.", 7) == 0) { NewI = new SExtInst(CI->getArgOperand(0), CI->getType(), "upgraded." + CI->getName(), CI); } else if (Name.compare(14, 7, "vmovlu.", 7) == 0) { NewI = new ZExtInst(CI->getArgOperand(0), CI->getType(), "upgraded." + CI->getName(), CI); - - } else if (Name.compare(14, 4, "vadd", 4) == 0 || - Name.compare(14, 4, "vsub", 4) == 0) { - // Extend one (vaddw/vsubw) or both (vaddl/vsubl) operands. - Value *V0 = CI->getArgOperand(0); - Value *V1 = CI->getArgOperand(1); - if (Name.at(19) == 's') { - if (Name.at(18) == 'l') - V0 = new SExtInst(CI->getArgOperand(0), CI->getType(), "", CI); - V1 = new SExtInst(CI->getArgOperand(1), CI->getType(), "", CI); - } else { - assert(Name.at(19) == 'u' && "unexpected vadd/vsub intrinsic"); - if (Name.at(18) == 'l') - V0 = new ZExtInst(CI->getArgOperand(0), CI->getType(), "", CI); - V1 = new ZExtInst(CI->getArgOperand(1), CI->getType(), "", CI); - } - if (Name.compare(14, 4, "vadd", 4) == 0) - NewI = BinaryOperator::CreateAdd(V0, V1,"upgraded."+CI->getName(),CI); - else - NewI = BinaryOperator::CreateSub(V0, V1,"upgraded."+CI->getName(),CI); - + } else if (Name.compare(14, 4, "vadd", 4) == 0) { + ExtendNEONArgs(CI, CI->getArgOperand(0), CI->getArgOperand(1), V0, V1); + NewI = BinaryOperator::CreateAdd(V0, V1, "upgraded."+CI->getName(), CI); + } else if (Name.compare(14, 4, "vsub", 4) == 0) { + ExtendNEONArgs(CI, CI->getArgOperand(0), CI->getArgOperand(1), V0, V1); + NewI = BinaryOperator::CreateSub(V0, V1,"upgraded."+CI->getName(),CI); + } else if (Name.compare(14, 4, "vmul", 4) == 0) { + ExtendNEONArgs(CI, CI->getArgOperand(0), CI->getArgOperand(1), V0, V1); + NewI = BinaryOperator::CreateMul(V0, V1,"upgraded."+CI->getName(),CI); + } else if (Name.compare(14, 4, "vmla", 4) == 0) { + ExtendNEONArgs(CI, CI->getArgOperand(1), CI->getArgOperand(2), V0, V1); + Instruction *MulI = BinaryOperator::CreateMul(V0, V1, "", CI); + NewI = BinaryOperator::CreateAdd(CI->getArgOperand(0), MulI, + "upgraded."+CI->getName(), CI); + } else if (Name.compare(14, 4, "vmls", 4) == 0) { + ExtendNEONArgs(CI, CI->getArgOperand(1), CI->getArgOperand(2), V0, V1); + Instruction *MulI = BinaryOperator::CreateMul(V0, V1, "", CI); + NewI = BinaryOperator::CreateSub(CI->getArgOperand(0), MulI, + "upgraded."+CI->getName(), CI); } else if (Name.compare(14, 6, "vmovn.", 6) == 0) { NewI = new TruncInst(CI->getArgOperand(0), CI->getType(), "upgraded." + CI->getName(), CI); Modified: llvm/trunk/test/Bitcode/neon-intrinsics.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bitcode/neon-intrinsics.ll?rev=112773&r1=112772&r2=112773&view=diff ============================================================================== --- llvm/trunk/test/Bitcode/neon-intrinsics.ll (original) +++ llvm/trunk/test/Bitcode/neon-intrinsics.ll Wed Sep 1 18:50:19 2010 @@ -52,7 +52,7 @@ ; CHECK: zext <4 x i16> ; CHECK-NEXT: add <4 x i32> -; vsubl/vsubw should be auto-upgraded to sub with sext/zext +; vsubl/vsubw should be auto-upgraded to subtract with sext/zext ; CHECK: vsubls16 ; CHECK-NOT: arm.neon.vsubls.v4i32 @@ -76,6 +76,56 @@ ; CHECK: zext <4 x i16> ; CHECK-NEXT: sub <4 x i32> +; vmull should be auto-upgraded to multiply with sext/zext +; (but vmullp should remain an intrinsic) + +; CHECK: vmulls8 +; CHECK-NOT: arm.neon.vmulls.v8i16 +; CHECK: sext <8 x i8> +; CHECK-NEXT: sext <8 x i8> +; CHECK-NEXT: mul <8 x i16> + +; CHECK: vmullu16 +; CHECK-NOT: arm.neon.vmullu.v4i32 +; CHECK: zext <4 x i16> +; CHECK-NEXT: zext <4 x i16> +; CHECK-NEXT: mul <4 x i32> + +; CHECK: vmullp8 +; CHECK: arm.neon.vmullp.v8i16 + +; vmlal should be auto-upgraded to multiply/add with sext/zext + +; CHECK: vmlals32 +; CHECK-NOT: arm.neon.vmlals.v2i64 +; CHECK: sext <2 x i32> +; CHECK-NEXT: sext <2 x i32> +; CHECK-NEXT: mul <2 x i64> +; CHECK-NEXT: add <2 x i64> + +; CHECK: vmlalu8 +; CHECK-NOT: arm.neon.vmlalu.v8i16 +; CHECK: zext <8 x i8> +; CHECK-NEXT: zext <8 x i8> +; CHECK-NEXT: mul <8 x i16> +; CHECK-NEXT: add <8 x i16> + +; vmlsl should be auto-upgraded to multiply/sub with sext/zext + +; CHECK: vmlsls16 +; CHECK-NOT: arm.neon.vmlsls.v4i32 +; CHECK: sext <4 x i16> +; CHECK-NEXT: sext <4 x i16> +; CHECK-NEXT: mul <4 x i32> +; CHECK-NEXT: sub <4 x i32> + +; CHECK: vmlslu32 +; CHECK-NOT: arm.neon.vmlslu.v2i64 +; CHECK: zext <2 x i32> +; CHECK-NEXT: zext <2 x i32> +; CHECK-NEXT: mul <2 x i64> +; CHECK-NEXT: sub <2 x i64> + ; vmovn should be auto-upgraded to trunc ; CHECK: vmovni16 Modified: llvm/trunk/test/Bitcode/neon-intrinsics.ll.bc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bitcode/neon-intrinsics.ll.bc?rev=112773&r1=112772&r2=112773&view=diff ============================================================================== Binary files - no diff available. Modified: llvm/trunk/test/CodeGen/ARM/vmla.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vmla.ll?rev=112773&r1=112772&r2=112773&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vmla.ll (original) +++ llvm/trunk/test/CodeGen/ARM/vmla.ll Wed Sep 1 18:50:19 2010 @@ -94,8 +94,11 @@ %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i8>* %B %tmp3 = load <8 x i8>* %C - %tmp4 = call <8 x i16> @llvm.arm.neon.vmlals.v8i16(<8 x i16> %tmp1, <8 x i8> %tmp2, <8 x i8> %tmp3) - ret <8 x i16> %tmp4 + %tmp4 = sext <8 x i8> %tmp2 to <8 x i16> + %tmp5 = sext <8 x i8> %tmp3 to <8 x i16> + %tmp6 = mul <8 x i16> %tmp4, %tmp5 + %tmp7 = add <8 x i16> %tmp1, %tmp6 + ret <8 x i16> %tmp7 } define <4 x i32> @vmlals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { @@ -104,8 +107,11 @@ %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i16>* %B %tmp3 = load <4 x i16>* %C - %tmp4 = call <4 x i32> @llvm.arm.neon.vmlals.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2, <4 x i16> %tmp3) - ret <4 x i32> %tmp4 + %tmp4 = sext <4 x i16> %tmp2 to <4 x i32> + %tmp5 = sext <4 x i16> %tmp3 to <4 x i32> + %tmp6 = mul <4 x i32> %tmp4, %tmp5 + %tmp7 = add <4 x i32> %tmp1, %tmp6 + ret <4 x i32> %tmp7 } define <2 x i64> @vmlals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { @@ -114,8 +120,11 @@ %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i32>* %B %tmp3 = load <2 x i32>* %C - %tmp4 = call <2 x i64> @llvm.arm.neon.vmlals.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2, <2 x i32> %tmp3) - ret <2 x i64> %tmp4 + %tmp4 = sext <2 x i32> %tmp2 to <2 x i64> + %tmp5 = sext <2 x i32> %tmp3 to <2 x i64> + %tmp6 = mul <2 x i64> %tmp4, %tmp5 + %tmp7 = add <2 x i64> %tmp1, %tmp6 + ret <2 x i64> %tmp7 } define <8 x i16> @vmlalu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { @@ -124,8 +133,11 @@ %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i8>* %B %tmp3 = load <8 x i8>* %C - %tmp4 = call <8 x i16> @llvm.arm.neon.vmlalu.v8i16(<8 x i16> %tmp1, <8 x i8> %tmp2, <8 x i8> %tmp3) - ret <8 x i16> %tmp4 + %tmp4 = zext <8 x i8> %tmp2 to <8 x i16> + %tmp5 = zext <8 x i8> %tmp3 to <8 x i16> + %tmp6 = mul <8 x i16> %tmp4, %tmp5 + %tmp7 = add <8 x i16> %tmp1, %tmp6 + ret <8 x i16> %tmp7 } define <4 x i32> @vmlalu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { @@ -134,8 +146,11 @@ %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i16>* %B %tmp3 = load <4 x i16>* %C - %tmp4 = call <4 x i32> @llvm.arm.neon.vmlalu.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2, <4 x i16> %tmp3) - ret <4 x i32> %tmp4 + %tmp4 = zext <4 x i16> %tmp2 to <4 x i32> + %tmp5 = zext <4 x i16> %tmp3 to <4 x i32> + %tmp6 = mul <4 x i32> %tmp4, %tmp5 + %tmp7 = add <4 x i32> %tmp1, %tmp6 + ret <4 x i32> %tmp7 } define <2 x i64> @vmlalu32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { @@ -144,8 +159,11 @@ %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i32>* %B %tmp3 = load <2 x i32>* %C - %tmp4 = call <2 x i64> @llvm.arm.neon.vmlalu.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2, <2 x i32> %tmp3) - ret <2 x i64> %tmp4 + %tmp4 = zext <2 x i32> %tmp2 to <2 x i64> + %tmp5 = zext <2 x i32> %tmp3 to <2 x i64> + %tmp6 = mul <2 x i64> %tmp4, %tmp5 + %tmp7 = add <2 x i64> %tmp1, %tmp6 + ret <2 x i64> %tmp7 } define arm_aapcs_vfpcc <4 x i32> @test_vmlal_lanes16(<4 x i32> %arg0_int32x4_t, <4 x i16> %arg1_int16x4_t, <4 x i16> %arg2_int16x4_t) nounwind readnone { @@ -153,8 +171,11 @@ ; CHECK: test_vmlal_lanes16 ; CHECK: vmlal.s16 q0, d2, d3[1] %0 = shufflevector <4 x i16> %arg2_int16x4_t, <4 x i16> undef, <4 x i32> ; <<4 x i16>> [#uses=1] - %1 = tail call <4 x i32> @llvm.arm.neon.vmlals.v4i32(<4 x i32> %arg0_int32x4_t, <4 x i16> %arg1_int16x4_t, <4 x i16> %0) ; <<4 x i32>> [#uses=1] - ret <4 x i32> %1 + %1 = sext <4 x i16> %arg1_int16x4_t to <4 x i32> + %2 = sext <4 x i16> %0 to <4 x i32> + %3 = mul <4 x i32> %1, %2 + %4 = add <4 x i32> %arg0_int32x4_t, %3 + ret <4 x i32> %4 } define arm_aapcs_vfpcc <2 x i64> @test_vmlal_lanes32(<2 x i64> %arg0_int64x2_t, <2 x i32> %arg1_int32x2_t, <2 x i32> %arg2_int32x2_t) nounwind readnone { @@ -162,8 +183,11 @@ ; CHECK: test_vmlal_lanes32 ; CHECK: vmlal.s32 q0, d2, d3[1] %0 = shufflevector <2 x i32> %arg2_int32x2_t, <2 x i32> undef, <2 x i32> ; <<2 x i32>> [#uses=1] - %1 = tail call <2 x i64> @llvm.arm.neon.vmlals.v2i64(<2 x i64> %arg0_int64x2_t, <2 x i32> %arg1_int32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1] - ret <2 x i64> %1 + %1 = sext <2 x i32> %arg1_int32x2_t to <2 x i64> + %2 = sext <2 x i32> %0 to <2 x i64> + %3 = mul <2 x i64> %1, %2 + %4 = add <2 x i64> %arg0_int64x2_t, %3 + ret <2 x i64> %4 } define arm_aapcs_vfpcc <4 x i32> @test_vmlal_laneu16(<4 x i32> %arg0_uint32x4_t, <4 x i16> %arg1_uint16x4_t, <4 x i16> %arg2_uint16x4_t) nounwind readnone { @@ -171,8 +195,11 @@ ; CHECK: test_vmlal_laneu16 ; CHECK: vmlal.u16 q0, d2, d3[1] %0 = shufflevector <4 x i16> %arg2_uint16x4_t, <4 x i16> undef, <4 x i32> ; <<4 x i16>> [#uses=1] - %1 = tail call <4 x i32> @llvm.arm.neon.vmlalu.v4i32(<4 x i32> %arg0_uint32x4_t, <4 x i16> %arg1_uint16x4_t, <4 x i16> %0) ; <<4 x i32>> [#uses=1] - ret <4 x i32> %1 + %1 = zext <4 x i16> %arg1_uint16x4_t to <4 x i32> + %2 = zext <4 x i16> %0 to <4 x i32> + %3 = mul <4 x i32> %1, %2 + %4 = add <4 x i32> %arg0_uint32x4_t, %3 + ret <4 x i32> %4 } define arm_aapcs_vfpcc <2 x i64> @test_vmlal_laneu32(<2 x i64> %arg0_uint64x2_t, <2 x i32> %arg1_uint32x2_t, <2 x i32> %arg2_uint32x2_t) nounwind readnone { @@ -180,14 +207,9 @@ ; CHECK: test_vmlal_laneu32 ; CHECK: vmlal.u32 q0, d2, d3[1] %0 = shufflevector <2 x i32> %arg2_uint32x2_t, <2 x i32> undef, <2 x i32> ; <<2 x i32>> [#uses=1] - %1 = tail call <2 x i64> @llvm.arm.neon.vmlalu.v2i64(<2 x i64> %arg0_uint64x2_t, <2 x i32> %arg1_uint32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1] - ret <2 x i64> %1 + %1 = zext <2 x i32> %arg1_uint32x2_t to <2 x i64> + %2 = zext <2 x i32> %0 to <2 x i64> + %3 = mul <2 x i64> %1, %2 + %4 = add <2 x i64> %arg0_uint64x2_t, %3 + ret <2 x i64> %4 } - -declare <8 x i16> @llvm.arm.neon.vmlals.v8i16(<8 x i16>, <8 x i8>, <8 x i8>) nounwind readnone -declare <4 x i32> @llvm.arm.neon.vmlals.v4i32(<4 x i32>, <4 x i16>, <4 x i16>) nounwind readnone -declare <2 x i64> @llvm.arm.neon.vmlals.v2i64(<2 x i64>, <2 x i32>, <2 x i32>) nounwind readnone - -declare <8 x i16> @llvm.arm.neon.vmlalu.v8i16(<8 x i16>, <8 x i8>, <8 x i8>) nounwind readnone -declare <4 x i32> @llvm.arm.neon.vmlalu.v4i32(<4 x i32>, <4 x i16>, <4 x i16>) nounwind readnone -declare <2 x i64> @llvm.arm.neon.vmlalu.v2i64(<2 x i64>, <2 x i32>, <2 x i32>) nounwind readnone Modified: llvm/trunk/test/CodeGen/ARM/vmls.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vmls.ll?rev=112773&r1=112772&r2=112773&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vmls.ll (original) +++ llvm/trunk/test/CodeGen/ARM/vmls.ll Wed Sep 1 18:50:19 2010 @@ -94,8 +94,11 @@ %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i8>* %B %tmp3 = load <8 x i8>* %C - %tmp4 = call <8 x i16> @llvm.arm.neon.vmlsls.v8i16(<8 x i16> %tmp1, <8 x i8> %tmp2, <8 x i8> %tmp3) - ret <8 x i16> %tmp4 + %tmp4 = sext <8 x i8> %tmp2 to <8 x i16> + %tmp5 = sext <8 x i8> %tmp3 to <8 x i16> + %tmp6 = mul <8 x i16> %tmp4, %tmp5 + %tmp7 = sub <8 x i16> %tmp1, %tmp6 + ret <8 x i16> %tmp7 } define <4 x i32> @vmlsls16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { @@ -104,8 +107,11 @@ %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i16>* %B %tmp3 = load <4 x i16>* %C - %tmp4 = call <4 x i32> @llvm.arm.neon.vmlsls.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2, <4 x i16> %tmp3) - ret <4 x i32> %tmp4 + %tmp4 = sext <4 x i16> %tmp2 to <4 x i32> + %tmp5 = sext <4 x i16> %tmp3 to <4 x i32> + %tmp6 = mul <4 x i32> %tmp4, %tmp5 + %tmp7 = sub <4 x i32> %tmp1, %tmp6 + ret <4 x i32> %tmp7 } define <2 x i64> @vmlsls32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { @@ -114,8 +120,11 @@ %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i32>* %B %tmp3 = load <2 x i32>* %C - %tmp4 = call <2 x i64> @llvm.arm.neon.vmlsls.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2, <2 x i32> %tmp3) - ret <2 x i64> %tmp4 + %tmp4 = sext <2 x i32> %tmp2 to <2 x i64> + %tmp5 = sext <2 x i32> %tmp3 to <2 x i64> + %tmp6 = mul <2 x i64> %tmp4, %tmp5 + %tmp7 = sub <2 x i64> %tmp1, %tmp6 + ret <2 x i64> %tmp7 } define <8 x i16> @vmlslu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { @@ -124,8 +133,11 @@ %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i8>* %B %tmp3 = load <8 x i8>* %C - %tmp4 = call <8 x i16> @llvm.arm.neon.vmlslu.v8i16(<8 x i16> %tmp1, <8 x i8> %tmp2, <8 x i8> %tmp3) - ret <8 x i16> %tmp4 + %tmp4 = zext <8 x i8> %tmp2 to <8 x i16> + %tmp5 = zext <8 x i8> %tmp3 to <8 x i16> + %tmp6 = mul <8 x i16> %tmp4, %tmp5 + %tmp7 = sub <8 x i16> %tmp1, %tmp6 + ret <8 x i16> %tmp7 } define <4 x i32> @vmlslu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { @@ -134,8 +146,11 @@ %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i16>* %B %tmp3 = load <4 x i16>* %C - %tmp4 = call <4 x i32> @llvm.arm.neon.vmlslu.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2, <4 x i16> %tmp3) - ret <4 x i32> %tmp4 + %tmp4 = zext <4 x i16> %tmp2 to <4 x i32> + %tmp5 = zext <4 x i16> %tmp3 to <4 x i32> + %tmp6 = mul <4 x i32> %tmp4, %tmp5 + %tmp7 = sub <4 x i32> %tmp1, %tmp6 + ret <4 x i32> %tmp7 } define <2 x i64> @vmlslu32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { @@ -144,8 +159,11 @@ %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i32>* %B %tmp3 = load <2 x i32>* %C - %tmp4 = call <2 x i64> @llvm.arm.neon.vmlslu.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2, <2 x i32> %tmp3) - ret <2 x i64> %tmp4 + %tmp4 = zext <2 x i32> %tmp2 to <2 x i64> + %tmp5 = zext <2 x i32> %tmp3 to <2 x i64> + %tmp6 = mul <2 x i64> %tmp4, %tmp5 + %tmp7 = sub <2 x i64> %tmp1, %tmp6 + ret <2 x i64> %tmp7 } define arm_aapcs_vfpcc <4 x i32> @test_vmlsl_lanes16(<4 x i32> %arg0_int32x4_t, <4 x i16> %arg1_int16x4_t, <4 x i16> %arg2_int16x4_t) nounwind readnone { @@ -153,8 +171,11 @@ ; CHECK: test_vmlsl_lanes16 ; CHECK: vmlsl.s16 q0, d2, d3[1] %0 = shufflevector <4 x i16> %arg2_int16x4_t, <4 x i16> undef, <4 x i32> ; <<4 x i16>> [#uses=1] - %1 = tail call <4 x i32> @llvm.arm.neon.vmlsls.v4i32(<4 x i32> %arg0_int32x4_t, <4 x i16> %arg1_int16x4_t, <4 x i16> %0) ; <<4 x i32>> [#uses=1] - ret <4 x i32> %1 + %1 = sext <4 x i16> %arg1_int16x4_t to <4 x i32> + %2 = sext <4 x i16> %0 to <4 x i32> + %3 = mul <4 x i32> %1, %2 + %4 = sub <4 x i32> %arg0_int32x4_t, %3 + ret <4 x i32> %4 } define arm_aapcs_vfpcc <2 x i64> @test_vmlsl_lanes32(<2 x i64> %arg0_int64x2_t, <2 x i32> %arg1_int32x2_t, <2 x i32> %arg2_int32x2_t) nounwind readnone { @@ -162,8 +183,11 @@ ; CHECK: test_vmlsl_lanes32 ; CHECK: vmlsl.s32 q0, d2, d3[1] %0 = shufflevector <2 x i32> %arg2_int32x2_t, <2 x i32> undef, <2 x i32> ; <<2 x i32>> [#uses=1] - %1 = tail call <2 x i64> @llvm.arm.neon.vmlsls.v2i64(<2 x i64> %arg0_int64x2_t, <2 x i32> %arg1_int32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1] - ret <2 x i64> %1 + %1 = sext <2 x i32> %arg1_int32x2_t to <2 x i64> + %2 = sext <2 x i32> %0 to <2 x i64> + %3 = mul <2 x i64> %1, %2 + %4 = sub <2 x i64> %arg0_int64x2_t, %3 + ret <2 x i64> %4 } define arm_aapcs_vfpcc <4 x i32> @test_vmlsl_laneu16(<4 x i32> %arg0_uint32x4_t, <4 x i16> %arg1_uint16x4_t, <4 x i16> %arg2_uint16x4_t) nounwind readnone { @@ -171,8 +195,11 @@ ; CHECK: test_vmlsl_laneu16 ; CHECK: vmlsl.u16 q0, d2, d3[1] %0 = shufflevector <4 x i16> %arg2_uint16x4_t, <4 x i16> undef, <4 x i32> ; <<4 x i16>> [#uses=1] - %1 = tail call <4 x i32> @llvm.arm.neon.vmlslu.v4i32(<4 x i32> %arg0_uint32x4_t, <4 x i16> %arg1_uint16x4_t, <4 x i16> %0) ; <<4 x i32>> [#uses=1] - ret <4 x i32> %1 + %1 = zext <4 x i16> %arg1_uint16x4_t to <4 x i32> + %2 = zext <4 x i16> %0 to <4 x i32> + %3 = mul <4 x i32> %1, %2 + %4 = sub <4 x i32> %arg0_uint32x4_t, %3 + ret <4 x i32> %4 } define arm_aapcs_vfpcc <2 x i64> @test_vmlsl_laneu32(<2 x i64> %arg0_uint64x2_t, <2 x i32> %arg1_uint32x2_t, <2 x i32> %arg2_uint32x2_t) nounwind readnone { @@ -180,14 +207,9 @@ ; CHECK: test_vmlsl_laneu32 ; CHECK: vmlsl.u32 q0, d2, d3[1] %0 = shufflevector <2 x i32> %arg2_uint32x2_t, <2 x i32> undef, <2 x i32> ; <<2 x i32>> [#uses=1] - %1 = tail call <2 x i64> @llvm.arm.neon.vmlslu.v2i64(<2 x i64> %arg0_uint64x2_t, <2 x i32> %arg1_uint32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1] - ret <2 x i64> %1 + %1 = zext <2 x i32> %arg1_uint32x2_t to <2 x i64> + %2 = zext <2 x i32> %0 to <2 x i64> + %3 = mul <2 x i64> %1, %2 + %4 = sub <2 x i64> %arg0_uint64x2_t, %3 + ret <2 x i64> %4 } - -declare <8 x i16> @llvm.arm.neon.vmlsls.v8i16(<8 x i16>, <8 x i8>, <8 x i8>) nounwind readnone -declare <4 x i32> @llvm.arm.neon.vmlsls.v4i32(<4 x i32>, <4 x i16>, <4 x i16>) nounwind readnone -declare <2 x i64> @llvm.arm.neon.vmlsls.v2i64(<2 x i64>, <2 x i32>, <2 x i32>) nounwind readnone - -declare <8 x i16> @llvm.arm.neon.vmlslu.v8i16(<8 x i16>, <8 x i8>, <8 x i8>) nounwind readnone -declare <4 x i32> @llvm.arm.neon.vmlslu.v4i32(<4 x i32>, <4 x i16>, <4 x i16>) nounwind readnone -declare <2 x i64> @llvm.arm.neon.vmlslu.v2i64(<2 x i64>, <2 x i32>, <2 x i32>) nounwind readnone Modified: llvm/trunk/test/CodeGen/ARM/vmul.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vmul.ll?rev=112773&r1=112772&r2=112773&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vmul.ll (original) +++ llvm/trunk/test/CodeGen/ARM/vmul.ll Wed Sep 1 18:50:19 2010 @@ -152,8 +152,10 @@ ;CHECK: vmull.s8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B - %tmp3 = call <8 x i16> @llvm.arm.neon.vmulls.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2) - ret <8 x i16> %tmp3 + %tmp3 = sext <8 x i8> %tmp1 to <8 x i16> + %tmp4 = sext <8 x i8> %tmp2 to <8 x i16> + %tmp5 = mul <8 x i16> %tmp3, %tmp4 + ret <8 x i16> %tmp5 } define <4 x i32> @vmulls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { @@ -161,8 +163,10 @@ ;CHECK: vmull.s16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B - %tmp3 = call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2) - ret <4 x i32> %tmp3 + %tmp3 = sext <4 x i16> %tmp1 to <4 x i32> + %tmp4 = sext <4 x i16> %tmp2 to <4 x i32> + %tmp5 = mul <4 x i32> %tmp3, %tmp4 + ret <4 x i32> %tmp5 } define <2 x i64> @vmulls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { @@ -170,8 +174,10 @@ ;CHECK: vmull.s32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B - %tmp3 = call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2) - ret <2 x i64> %tmp3 + %tmp3 = sext <2 x i32> %tmp1 to <2 x i64> + %tmp4 = sext <2 x i32> %tmp2 to <2 x i64> + %tmp5 = mul <2 x i64> %tmp3, %tmp4 + ret <2 x i64> %tmp5 } define <8 x i16> @vmullu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { @@ -179,8 +185,10 @@ ;CHECK: vmull.u8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B - %tmp3 = call <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2) - ret <8 x i16> %tmp3 + %tmp3 = zext <8 x i8> %tmp1 to <8 x i16> + %tmp4 = zext <8 x i8> %tmp2 to <8 x i16> + %tmp5 = mul <8 x i16> %tmp3, %tmp4 + ret <8 x i16> %tmp5 } define <4 x i32> @vmullu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { @@ -188,8 +196,10 @@ ;CHECK: vmull.u16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B - %tmp3 = call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2) - ret <4 x i32> %tmp3 + %tmp3 = zext <4 x i16> %tmp1 to <4 x i32> + %tmp4 = zext <4 x i16> %tmp2 to <4 x i32> + %tmp5 = mul <4 x i32> %tmp3, %tmp4 + ret <4 x i32> %tmp5 } define <2 x i64> @vmullu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { @@ -197,8 +207,10 @@ ;CHECK: vmull.u32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B - %tmp3 = call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2) - ret <2 x i64> %tmp3 + %tmp3 = zext <2 x i32> %tmp1 to <2 x i64> + %tmp4 = zext <2 x i32> %tmp2 to <2 x i64> + %tmp5 = mul <2 x i64> %tmp3, %tmp4 + ret <2 x i64> %tmp5 } define <8 x i16> @vmullp8(<8 x i8>* %A, <8 x i8>* %B) nounwind { @@ -215,8 +227,10 @@ ; CHECK: test_vmull_lanes16 ; CHECK: vmull.s16 q0, d0, d1[1] %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <4 x i32> ; <<4 x i16>> [#uses=1] - %1 = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %arg0_int16x4_t, <4 x i16> %0) ; <<4 x i32>> [#uses=1] - ret <4 x i32> %1 + %1 = sext <4 x i16> %arg0_int16x4_t to <4 x i32> + %2 = sext <4 x i16> %0 to <4 x i32> + %3 = mul <4 x i32> %1, %2 + ret <4 x i32> %3 } define arm_aapcs_vfpcc <2 x i64> @test_vmull_lanes32(<2 x i32> %arg0_int32x2_t, <2 x i32> %arg1_int32x2_t) nounwind readnone { @@ -224,8 +238,10 @@ ; CHECK: test_vmull_lanes32 ; CHECK: vmull.s32 q0, d0, d1[1] %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <2 x i32> ; <<2 x i32>> [#uses=1] - %1 = tail call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32> %arg0_int32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1] - ret <2 x i64> %1 + %1 = sext <2 x i32> %arg0_int32x2_t to <2 x i64> + %2 = sext <2 x i32> %0 to <2 x i64> + %3 = mul <2 x i64> %1, %2 + ret <2 x i64> %3 } define arm_aapcs_vfpcc <4 x i32> @test_vmull_laneu16(<4 x i16> %arg0_uint16x4_t, <4 x i16> %arg1_uint16x4_t) nounwind readnone { @@ -233,8 +249,10 @@ ; CHECK: test_vmull_laneu16 ; CHECK: vmull.u16 q0, d0, d1[1] %0 = shufflevector <4 x i16> %arg1_uint16x4_t, <4 x i16> undef, <4 x i32> ; <<4 x i16>> [#uses=1] - %1 = tail call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> %arg0_uint16x4_t, <4 x i16> %0) ; <<4 x i32>> [#uses=1] - ret <4 x i32> %1 + %1 = zext <4 x i16> %arg0_uint16x4_t to <4 x i32> + %2 = zext <4 x i16> %0 to <4 x i32> + %3 = mul <4 x i32> %1, %2 + ret <4 x i32> %3 } define arm_aapcs_vfpcc <2 x i64> @test_vmull_laneu32(<2 x i32> %arg0_uint32x2_t, <2 x i32> %arg1_uint32x2_t) nounwind readnone { @@ -242,16 +260,10 @@ ; CHECK: test_vmull_laneu32 ; CHECK: vmull.u32 q0, d0, d1[1] %0 = shufflevector <2 x i32> %arg1_uint32x2_t, <2 x i32> undef, <2 x i32> ; <<2 x i32>> [#uses=1] - %1 = tail call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32> %arg0_uint32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1] - ret <2 x i64> %1 + %1 = zext <2 x i32> %arg0_uint32x2_t to <2 x i64> + %2 = zext <2 x i32> %0 to <2 x i64> + %3 = mul <2 x i64> %1, %2 + ret <2 x i64> %3 } -declare <8 x i16> @llvm.arm.neon.vmulls.v8i16(<8 x i8>, <8 x i8>) nounwind readnone -declare <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16>, <4 x i16>) nounwind readnone -declare <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32>, <2 x i32>) nounwind readnone - -declare <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8>, <8 x i8>) nounwind readnone -declare <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone -declare <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32>, <2 x i32>) nounwind readnone - declare <8 x i16> @llvm.arm.neon.vmullp.v8i16(<8 x i8>, <8 x i8>) nounwind readnone From grosbach at apple.com Wed Sep 1 18:50:23 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 01 Sep 2010 23:50:23 -0000 Subject: [llvm-commits] [llvm] r112774 - /llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td Message-ID: <20100901235023.AC0EB2A6C12D@llvm.org> Author: grosbach Date: Wed Sep 1 18:50:23 2010 New Revision: 112774 URL: http://llvm.org/viewvc/llvm-project?rev=112774&view=rev Log: Simplify the tGPR register class now that the register allocators know not to try to allocate reserved registers. Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td?rev=112774&r1=112773&r2=112774&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td Wed Sep 1 18:50:23 2010 @@ -425,32 +425,7 @@ // Thumb registers are R0-R7 normally. Some instructions can still use // the general GPR register class above (MOV, e.g.) -def tGPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6, R7]> { - let MethodProtos = [{ - iterator allocation_order_begin(const MachineFunction &MF) const; - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - static const unsigned THUMB_tGPR_AO[] = { - ARM::R0, ARM::R1, ARM::R2, ARM::R3, - ARM::R4, ARM::R5, ARM::R6, ARM::R7 }; - - // FP is R7, only low registers available. - tGPRClass::iterator - tGPRClass::allocation_order_begin(const MachineFunction &MF) const { - return THUMB_tGPR_AO; - } - - tGPRClass::iterator - tGPRClass::allocation_order_end(const MachineFunction &MF) const { - const TargetMachine &TM = MF.getTarget(); - const TargetRegisterInfo *RI = TM.getRegisterInfo(); - tGPRClass::iterator I = - THUMB_tGPR_AO + (sizeof(THUMB_tGPR_AO)/sizeof(unsigned)); - return RI->hasFP(MF) ? I-1 : I; - } - }]; -} +def tGPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6, R7]> {} // For tail calls, we can't use callee-saved registers, as they are restored // to the saved value before the tail call, which would clobber a call address. From sabre at nondot.org Wed Sep 1 18:53:43 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 01 Sep 2010 23:53:43 -0000 Subject: [llvm-commits] [www-pubs] r112775 - in /www-pubs/trunk: 2010-06-ISCA-Relax.html 2010-06-ISCA-Relax.pdf pubs.js Message-ID: <20100901235344.16E1A2A6C12C@llvm.org> Author: lattner Date: Wed Sep 1 18:53:43 2010 New Revision: 112775 URL: http://llvm.org/viewvc/llvm-project?rev=112775&view=rev Log: add "Relax: An Architectural Framework for Software Recovery of Hardware Faults" from ISCA'10 Added: www-pubs/trunk/2010-06-ISCA-Relax.html www-pubs/trunk/2010-06-ISCA-Relax.pdf (with props) Modified: www-pubs/trunk/pubs.js Added: www-pubs/trunk/2010-06-ISCA-Relax.html URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/2010-06-ISCA-Relax.html?rev=112775&view=auto ============================================================================== --- www-pubs/trunk/2010-06-ISCA-Relax.html (added) +++ www-pubs/trunk/2010-06-ISCA-Relax.html Wed Sep 1 18:53:43 2010 @@ -0,0 +1,70 @@ + + + + + + Relax: An Architectural Framework for Software Recovery of Hardware Faults + + + +
      + Relax: An Architectural Framework for Software Recovery of Hardware Faults +
      +
      + M. de Kruijf, S. Nomura, and K.Sankaralingam +
      + +

      Abstract:

      +
      +

      +As technology scales ever further, device unreliability is creating excessive +complexity for hardware to maintain the illusion of perfect operation. In this +paper, we consider whether exposing hardware fault information to software and +allowing software to control fault recovery simplifies hardware design and helps +technology scaling.

      + +

      The combination of emerging applications and emerging many-core architectures +makes software recovery a viable alternative to hardware-based fault recovery. +Emerging applications tend to have few I/O and memory side-effects, which limits +the amount of information that needs checkpointing, and they allow discarding +individual sub-computations with small qualitative impact. Software recovery can +harness these properties in ways that hardware recovery cannot.

      + +

      +We describe Relax, an architectural framework for software recovery of hardware +faults. Relax includes three core components: (1) an ISA extension that allows +software to mark regions of code for software recovery, (2) a hardware +organization that simplifies reliability considerations and provides energy +efficiency with hardware recovery support removed, and (3) software support for +compilers and programmers to utilize the Relax ISA. Applying Relax to counter +the effects of process variation, our results show a 20% energy efficiency +improvement for PARSEC applications with only minimal source code changes and +simpler hardware. +

      +
      + +

      Published:

      +
      + "Relax: An Architectural Framework for Software Recovery of Hardware Faults"
      + M. de Kruijf, S. Nomura, and K.Sankaralingam
      +In Proceedings of ISCA '10: International Symposium on Computer Architecture, +June 2010. +
      + +

      Download:

      +

      Paper:

      + + + +
      + Valid CSS! + Valid HTML 4.01! + + + Added: www-pubs/trunk/2010-06-ISCA-Relax.pdf URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/2010-06-ISCA-Relax.pdf?rev=112775&view=auto ============================================================================== Binary file - no diff available. Propchange: www-pubs/trunk/2010-06-ISCA-Relax.pdf ------------------------------------------------------------------------------ svn:mime-type = application/octet-stream Modified: www-pubs/trunk/pubs.js URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/pubs.js?rev=112775&r1=112774&r2=112775&view=diff ============================================================================== --- www-pubs/trunk/pubs.js (original) +++ www-pubs/trunk/pubs.js Wed Sep 1 18:53:43 2010 @@ -15,6 +15,12 @@ author: "André Tavares, Fernando Magno Pereira, Mariza Bigonha and Roberto Bigonha", month: 9, year: 2010}, + {url: "2010-06-ISCA-Relax.html", + title: "Relax: An Architectural Framework for Software Recovery of Hardware Faults", + published: "ISCA '10: International Symposium on Computer Architecture", + author: "M. de Kruijf, S. Nomura, and K.Sankaralingam", + month: 6, + year: 2010}, {url: "2010-06-ISMM-CETS.html", title: "CETS: Compiler Enforced Temporal Safety for C", published: "International Conference on Memory Management 2010", From sabre at nondot.org Wed Sep 1 18:57:35 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 01 Sep 2010 23:57:35 -0000 Subject: [llvm-commits] [www-pubs] r112778 - in /www-pubs/trunk: 2010-06-06-Clang-LLVM.html 2010-06-06-Clang-LLVM.pdf pubs.js Message-ID: <20100901235735.C66592A6C12C@llvm.org> Author: lattner Date: Wed Sep 1 18:57:35 2010 New Revision: 112778 URL: http://llvm.org/viewvc/llvm-project?rev=112778&view=rev Log: add the "Clang/LLVM Maturity Report" Added: www-pubs/trunk/2010-06-06-Clang-LLVM.html www-pubs/trunk/2010-06-06-Clang-LLVM.pdf (with props) Modified: www-pubs/trunk/pubs.js Added: www-pubs/trunk/2010-06-06-Clang-LLVM.html URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/2010-06-06-Clang-LLVM.html?rev=112778&view=auto ============================================================================== --- www-pubs/trunk/2010-06-06-Clang-LLVM.html (added) +++ www-pubs/trunk/2010-06-06-Clang-LLVM.html Wed Sep 1 18:57:35 2010 @@ -0,0 +1,51 @@ + + + + + + Clang/LLVM Maturity Report +</head> +<body> + +<div class="pub_title"> + Clang/LLVM Maturity Report +</div> +<div class="pub_author"> + <a href="mailto:kamikaze at bsdforen.de">Dominic Fandrey</a> +</div> + + +<h2>Abstract:</h2> +<blockquote> +This report describes the current maturity state of the Clang/LLVM C/C++ +compiler. The main focus is on compile time and memory consumption compared +to GCC 4.2, the version used by the FreeBSD operating system project to avoid +the integration of GPLv3 code. +</blockquote> + +<h2>Published:</h2> +<blockquote> + Clang/LLVM Maturity Report, Dominic Fandrey<br> + <i>Proceedings of the Summer 2010 Research Seminar</i>, Computer Science Dept., University of Applied Sciences Karlsruhe, June 2010. +</blockquote> + +<h2>Download:</h2> +<ul> + <li><a href="2010-06-06-Clang-LLVM.pdf">Clang/LLVM Maturity Report</a> (PDF)</li> +</ul> + +<h2>BibTeX Entry:</h2> +<pre> + @Proceedings{Fandrey, + author = {Dominic Fandrey}, + title = "{Clang/LLVM Maturity Report}", + school = "{Computer Science Dept., University of Applied Sciences Karlsruhe}", + year = {2010}, + address = {Moltkestr. 30, 76133 Karlsruhe - Germany}, + month = {June}, + note = {{\em See {\tt http://www.iwi.hs-karlsruhe.de}.}} + } +</pre> + +</body> +</html> Added: www-pubs/trunk/2010-06-06-Clang-LLVM.pdf URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/2010-06-06-Clang-LLVM.pdf?rev=112778&view=auto ============================================================================== Binary file - no diff available. Propchange: www-pubs/trunk/2010-06-06-Clang-LLVM.pdf ------------------------------------------------------------------------------ svn:mime-type = application/octet-stream Modified: www-pubs/trunk/pubs.js URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/pubs.js?rev=112778&r1=112777&r2=112778&view=diff ============================================================================== --- www-pubs/trunk/pubs.js (original) +++ www-pubs/trunk/pubs.js Wed Sep 1 18:57:35 2010 @@ -27,6 +27,13 @@ author: "Santosh Nagarakatte, Jianzhou Zhao, Milo M K Martin and Steve Zdancewic", month: 6, year: 2010}, + + {url: "2010-06-06-Clang-LLVM.html", + title: "Clang/LLVM Maturity Report", + published: "Proceedings of the Summer 2010 Research Seminar", + author: "Dominic Fandrey", + month: 6, + year: 2010}, {url: "2010-05-Oakland-HyperSafe.html", title: "HyperSafe: A Lightweight Approach to Provide Lifetime Hypervisor Control-Flow Integrity", published: "IEEE Symposium on Security & Privacy 2010", From grosbach at apple.com Wed Sep 1 19:02:27 2010 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 02 Sep 2010 00:02:27 -0000 Subject: [llvm-commits] [llvm] r112779 - /llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td Message-ID: <20100902000227.0B18D2A6C12C@llvm.org> Author: grosbach Date: Wed Sep 1 19:02:26 2010 New Revision: 112779 URL: http://llvm.org/viewvc/llvm-project?rev=112779&view=rev Log: trivial cleanup Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td?rev=112779&r1=112778&r2=112779&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td Wed Sep 1 19:02:26 2010 @@ -475,10 +475,8 @@ const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>(); GPRClass::iterator I; - if (Subtarget.isThumb1Only()) { - I = THUMB_GPR_AO_TC + (sizeof(THUMB_GPR_AO_TC)/sizeof(unsigned)); - return I; - } + if (Subtarget.isThumb1Only()) + return THUMB_GPR_AO_TC + (sizeof(THUMB_GPR_AO_TC)/sizeof(unsigned)); if (Subtarget.isTargetDarwin()) { if (Subtarget.isR9Reserved()) From sabre at nondot.org Wed Sep 1 19:09:17 2010 From: sabre at nondot.org (Chris Lattner) Date: Thu, 02 Sep 2010 00:09:17 -0000 Subject: [llvm-commits] [llvm] r112781 - /llvm/trunk/docs/DeveloperPolicy.html Message-ID: <20100902000917.817722A6C12C@llvm.org> Author: lattner Date: Wed Sep 1 19:09:17 2010 New Revision: 112781 URL: http://llvm.org/viewvc/llvm-project?rev=112781&view=rev Log: updates to make it clear that this applies to clang and other llvm subprojects. Modified: llvm/trunk/docs/DeveloperPolicy.html Modified: llvm/trunk/docs/DeveloperPolicy.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/DeveloperPolicy.html?rev=112781&r1=112780&r2=112781&view=diff ============================================================================== --- llvm/trunk/docs/DeveloperPolicy.html (original) +++ llvm/trunk/docs/DeveloperPolicy.html Wed Sep 1 19:09:17 2010 @@ -43,7 +43,8 @@ is to eliminate miscommunication, rework, and confusion that might arise from the distributed nature of LLVM's development. By stating the policy in clear terms, we hope each developer can know ahead of time what to expect when - making LLVM contributions.</p> + making LLVM contributions. This policy covers all llvm.org subprojects, + including Clang, LLDB, etc.</p> <p>This policy is also designed to accomplish the following objectives:</p> <ol> @@ -77,17 +78,28 @@ <!-- _______________________________________________________________________ --> <div class="doc_subsection"> <a name="informed">Stay Informed</a> </div> <div class="doc_text"> -<p>Developers should stay informed by reading at least the - <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev">llvmdev</a> email - list. If you are doing anything more than just casual work on LLVM, it is - suggested that you also subscribe to the - <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits">llvm-commits</a> - list and pay attention to changes being made by others.</p> +<p>Developers should stay informed by reading at least the "dev" mailing list + for the projects you are interested in, such as + <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev">llvmdev</a> for + LLVM, <a href="http://lists.cs.uiuc.edu/mailman/listinfo/cfe-dev">cfe-dev</a> + for Clang, or <a + href="http://lists.cs.uiuc.edu/mailman/listinfo/lldb-dev">lldb-dev</a> + for LLDB. If you are doing anything more than just casual work on LLVM, it + is suggested that you also subscribe to the "commits" mailing list for the + subproject you're interested in, such as + <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits">llvm-commits</a>, + <a href="http://lists.cs.uiuc.edu/mailman/listinfo/cfe-commits">cfe-commits</a>, + or <a href="http://lists.cs.uiuc.edu/mailman/listinfo/lldb-commits">lldb-commits</a>. + Reading the "commits" list and paying attention to changes being made by + others is a good way to see what other people are interested in and watching + the flow of the project as a whole.</p> <p>We recommend that active developers register an email account with <a href="http://llvm.org/bugs/">LLVM Bugzilla</a> and preferably subscribe to the <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmbugs">llvm-bugs</a> - email list to keep track of bugs and enhancements occurring in LLVM.</p> + email list to keep track of bugs and enhancements occurring in LLVM. We + really appreciate people who are proactive at catching incoming bugs in their + components and dealing with them promptly.</p> </div> <!-- _______________________________________________________________________ --> @@ -234,8 +246,9 @@ them short.</li> </ol> -<p>Note that llvm/test is designed for regression and small feature tests - only. More extensive test cases (e.g., entire applications, benchmarks, etc) +<p>Note that llvm/test and clang/test are designed for regression and small + feature tests only. More extensive test cases (e.g., entire applications, + benchmarks, etc) should be added to the <tt>llvm-test</tt> test suite. The llvm-test suite is for coverage (correctness, performance, etc) testing, not feature or regression testing.</p> @@ -258,7 +271,7 @@ testcase</a> so we know if the fix/feature ever regresses in the future.</li> - <li>Code must pass the dejagnu (<tt>llvm/test</tt>) test suite.</li> + <li>Code must pass the <tt>llvm/test</tt> test suite.</li> <li>The code must not cause regressions on a reasonable subset of llvm-test, where "reasonable" depends on the contributor's judgement and the scope of From nlewycky at google.com Wed Sep 1 19:09:56 2010 From: nlewycky at google.com (Nick Lewycky) Date: Wed, 1 Sep 2010 17:09:56 -0700 Subject: [llvm-commits] [llvm] r112773 - in /llvm/trunk: include/llvm/IntrinsicsARM.td lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMISelLowering.h lib/Target/ARM/ARMInstrNEON.td lib/VMCore/AutoUpgrade.cpp test/Bitcode/neon-intrinsics.ll test/Bitco Message-ID: <AANLkTikd7SCPgXnhrL-U_B5jswK0SGBNNWUga_4SCH17@mail.gmail.com> On 1 September 2010 16:50, Bob Wilson <bob.wilson at apple.com> wrote: > Author: bwilson > Date: Wed Sep 1 18:50:19 2010 > New Revision: 112773 > > URL: http://llvm.org/viewvc/llvm-project?rev=112773&view=rev > Log: > Remove NEON vmull, vmlal, and vmlsl intrinsics, replacing them with > multiply, > add, and subtract operations with zero-extended or sign-extended vectors. > Update tests. Add auto-upgrade support for the old intrinsics. > Fantastic! Thanks Bob! Nick > Modified: > llvm/trunk/include/llvm/IntrinsicsARM.td > llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp > llvm/trunk/lib/Target/ARM/ARMISelLowering.h > llvm/trunk/lib/Target/ARM/ARMInstrNEON.td > llvm/trunk/lib/VMCore/AutoUpgrade.cpp > llvm/trunk/test/Bitcode/neon-intrinsics.ll > llvm/trunk/test/Bitcode/neon-intrinsics.ll.bc > llvm/trunk/test/CodeGen/ARM/vmla.ll > llvm/trunk/test/CodeGen/ARM/vmls.ll > llvm/trunk/test/CodeGen/ARM/vmul.ll > > Modified: llvm/trunk/include/llvm/IntrinsicsARM.td > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsARM.td?rev=112773&r1=112772&r2=112773&view=diff > > ============================================================================== > --- llvm/trunk/include/llvm/IntrinsicsARM.td (original) > +++ llvm/trunk/include/llvm/IntrinsicsARM.td Wed Sep 1 18:50:19 2010 > @@ -129,16 +129,8 @@ > def int_arm_neon_vmulp : Neon_2Arg_Intrinsic; > def int_arm_neon_vqdmulh : Neon_2Arg_Intrinsic; > def int_arm_neon_vqrdmulh : Neon_2Arg_Intrinsic; > - def int_arm_neon_vmulls : Neon_2Arg_Long_Intrinsic; > - def int_arm_neon_vmullu : Neon_2Arg_Long_Intrinsic; > def int_arm_neon_vmullp : Neon_2Arg_Long_Intrinsic; > def int_arm_neon_vqdmull : Neon_2Arg_Long_Intrinsic; > - > - // Vector Multiply and Accumulate/Subtract. > - def int_arm_neon_vmlals : Neon_3Arg_Long_Intrinsic; > - def int_arm_neon_vmlalu : Neon_3Arg_Long_Intrinsic; > - def int_arm_neon_vmlsls : Neon_3Arg_Long_Intrinsic; > - def int_arm_neon_vmlslu : Neon_3Arg_Long_Intrinsic; > def int_arm_neon_vqdmlal : Neon_3Arg_Long_Intrinsic; > def int_arm_neon_vqdmlsl : Neon_3Arg_Long_Intrinsic; > > @@ -302,7 +294,7 @@ > def int_arm_neon_vcvtfxs2fp : Neon_CvtFxToFP_Intrinsic; > def int_arm_neon_vcvtfxu2fp : Neon_CvtFxToFP_Intrinsic; > > -// Narrowing and Lengthening Vector Moves. > +// Narrowing Saturating Vector Moves. > def int_arm_neon_vqmovns : Neon_1Arg_Narrow_Intrinsic; > def int_arm_neon_vqmovnu : Neon_1Arg_Narrow_Intrinsic; > def int_arm_neon_vqmovnsu : Neon_1Arg_Narrow_Intrinsic; > > Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=112773&r1=112772&r2=112773&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Sep 1 18:50:19 2010 > @@ -326,7 +326,10 @@ > > // Neon does not support some operations on v1i64 and v2i64 types. > setOperationAction(ISD::MUL, MVT::v1i64, Expand); > - setOperationAction(ISD::MUL, MVT::v2i64, Expand); > + // Custom handling for some quad-vector types to detect VMULL. > + setOperationAction(ISD::MUL, MVT::v8i16, Custom); > + setOperationAction(ISD::MUL, MVT::v4i32, Custom); > + setOperationAction(ISD::MUL, MVT::v2i64, Custom); > setOperationAction(ISD::VSETCC, MVT::v1i64, Expand); > setOperationAction(ISD::VSETCC, MVT::v2i64, Expand); > > @@ -684,6 +687,8 @@ > case ARMISD::VZIP: return "ARMISD::VZIP"; > case ARMISD::VUZP: return "ARMISD::VUZP"; > case ARMISD::VTRN: return "ARMISD::VTRN"; > + case ARMISD::VMULLs: return "ARMISD::VMULLs"; > + case ARMISD::VMULLu: return "ARMISD::VMULLu"; > case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR"; > case ARMISD::FMAX: return "ARMISD::FMAX"; > case ARMISD::FMIN: return "ARMISD::FMIN"; > @@ -3751,6 +3756,51 @@ > return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val); > } > > +/// SkipExtension - For a node that is either a SIGN_EXTEND, ZERO_EXTEND, > or > +/// an extending load, return the unextended value. > +static SDValue SkipExtension(SDNode *N, SelectionDAG &DAG) { > + if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == > ISD::ZERO_EXTEND) > + return N->getOperand(0); > + LoadSDNode *LD = cast<LoadSDNode>(N); > + return DAG.getLoad(LD->getMemoryVT(), N->getDebugLoc(), LD->getChain(), > + LD->getBasePtr(), LD->getSrcValue(), > + LD->getSrcValueOffset(), LD->isVolatile(), > + LD->isNonTemporal(), LD->getAlignment()); > +} > + > +static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) { > + // Multiplications are only custom-lowered for 128-bit vectors so that > + // VMULL can be detected. Otherwise v2i64 multiplications are not > legal. > + EVT VT = Op.getValueType(); > + assert(VT.is128BitVector() && "unexpected type for custom-lowering > ISD::MUL"); > + SDNode *N0 = Op.getOperand(0).getNode(); > + SDNode *N1 = Op.getOperand(1).getNode(); > + unsigned NewOpc = 0; > + if ((N0->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N0)) && > + (N1->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N1))) { > + NewOpc = ARMISD::VMULLs; > + } else if ((N0->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N0)) > && > + (N1->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N1))) > { > + NewOpc = ARMISD::VMULLu; > + } else if (VT.getSimpleVT().SimpleTy == MVT::v2i64) { > + // Fall through to expand this. It is not legal. > + return SDValue(); > + } else { > + // Other vector multiplications are legal. > + return Op; > + } > + > + // Legalize to a VMULL instruction. > + DebugLoc DL = Op.getDebugLoc(); > + SDValue Op0 = SkipExtension(N0, DAG); > + SDValue Op1 = SkipExtension(N1, DAG); > + > + assert(Op0.getValueType().is64BitVector() && > + Op1.getValueType().is64BitVector() && > + "unexpected types for extended operands to VMULL"); > + return DAG.getNode(NewOpc, DL, VT, Op0, Op1); > +} > + > SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) > const { > switch (Op.getOpcode()) { > default: llvm_unreachable("Don't know how to custom lower this!"); > @@ -3792,6 +3842,7 @@ > case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); > case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); > case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); > + case ISD::MUL: return LowerMUL(Op, DAG); > } > return SDValue(); > } > > Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=112773&r1=112772&r2=112773&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original) > +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Wed Sep 1 18:50:19 2010 > @@ -145,6 +145,10 @@ > VUZP, // unzip (deinterleave) > VTRN, // transpose > > + // Vector multiply long: > + VMULLs, // ...signed > + VMULLu, // ...unsigned > + > // Operands of the standard BUILD_VECTOR node are not legalized, > which > // is fine if BUILD_VECTORs are always lowered to shuffles or other > // operations, but for ARM some BUILD_VECTORs are legal as-is and > their > > Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=112773&r1=112772&r2=112773&view=diff > > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) > +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Wed Sep 1 18:50:19 2010 > @@ -93,6 +93,11 @@ > def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>; > def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>; > > +def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>, > + SDTCisSameAs<1, 2>]>; > +def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>; > +def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>; > + > def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, > 1>, > SDTCisSameAs<0, 2>]>; > def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>; > @@ -1255,6 +1260,42 @@ > [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), > (OpTy QPR:$src2), (OpTy > QPR:$src3))))]>; > > +// Long Multiply-Add/Sub operations. > +class N3VLMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit > op4, > + InstrItinClass itin, string OpcodeStr, string Dt, > + ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode> > + : N3V<op24, op23, op21_20, op11_8, 0, op4, > + (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), N3RegFrm, > itin, > + OpcodeStr, Dt, "$dst, $src2, $src3", "$src1 = $dst", > + [(set QPR:$dst, (OpNode (TyQ QPR:$src1), > + (TyQ (MulOp (TyD DPR:$src2), > + (TyD DPR:$src3)))))]>; > +class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8, > + InstrItinClass itin, string OpcodeStr, string Dt, > + ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode > OpNode> > + : N3V<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$dst), > + (ins QPR:$src1, DPR:$src2, DPR_VFP2:$src3, nohash_imm:$lane), > + NVMulSLFrm, itin, > + OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst", > + [(set QPR:$dst, > + (OpNode (TyQ QPR:$src1), > + (TyQ (MulOp (TyD DPR:$src2), > + (TyD (NEONvduplane (TyD DPR_VFP2:$src3), > + imm:$lane))))))]>; > +class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8, > + InstrItinClass itin, string OpcodeStr, string Dt, > + ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode > OpNode> > + : N3V<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$dst), > + (ins QPR:$src1, DPR:$src2, DPR_8:$src3, nohash_imm:$lane), > + NVMulSLFrm, itin, > + OpcodeStr, Dt, "$dst, $src2, $src3[$lane]", "$src1 = $dst", > + [(set QPR:$dst, > + (OpNode (TyQ QPR:$src1), > + (TyQ (MulOp (TyD DPR:$src2), > + (TyD (NEONvduplane (TyD DPR_8:$src3), > + imm:$lane))))))]>; > + > + > // Neon Long 3-argument intrinsic. The destination register is > // a quad-register and is also used as the first source operand register. > class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit > op4, > @@ -1306,8 +1347,37 @@ > // Long 3-register operations. > class N3VL<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, > InstrItinClass itin, string OpcodeStr, string Dt, > - ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp, > - bit Commutable> > + ValueType TyQ, ValueType TyD, SDNode OpNode, bit Commutable> > + : N3V<op24, op23, op21_20, op11_8, 0, op4, > + (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin, > + OpcodeStr, Dt, "$dst, $src1, $src2", "", > + [(set QPR:$dst, (TyQ (OpNode (TyD DPR:$src1), (TyD DPR:$src2))))]> > { > + let isCommutable = Commutable; > +} > +class N3VLSL<bit op24, bits<2> op21_20, bits<4> op11_8, > + InstrItinClass itin, string OpcodeStr, string Dt, > + ValueType TyQ, ValueType TyD, SDNode OpNode> > + : N3V<op24, 1, op21_20, op11_8, 1, 0, > + (outs QPR:$dst), (ins DPR:$src1, DPR_VFP2:$src2, > nohash_imm:$lane), > + NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "", > + [(set QPR:$dst, > + (TyQ (OpNode (TyD DPR:$src1), > + (TyD (NEONvduplane (TyD > DPR_VFP2:$src2),imm:$lane)))))]>; > +class N3VLSL16<bit op24, bits<2> op21_20, bits<4> op11_8, > + InstrItinClass itin, string OpcodeStr, string Dt, > + ValueType TyQ, ValueType TyD, SDNode OpNode> > + : N3V<op24, 1, op21_20, op11_8, 1, 0, > + (outs QPR:$dst), (ins DPR:$src1, DPR_8:$src2, nohash_imm:$lane), > + NVMulSLFrm, itin, OpcodeStr, Dt, "$dst, $src1, $src2[$lane]", "", > + [(set QPR:$dst, > + (TyQ (OpNode (TyD DPR:$src1), > + (TyD (NEONvduplane (TyD DPR_8:$src2), > imm:$lane)))))]>; > + > +// Long 3-register operations with explicitly extended operands. > +class N3VLExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit > op4, > + InstrItinClass itin, string OpcodeStr, string Dt, > + ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp, > + bit Commutable> > : N3V<op24, op23, op21_20, op11_8, 0, op4, > (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), N3RegFrm, itin, > OpcodeStr, Dt, "$dst, $src1, $src2", "", > @@ -1729,16 +1799,40 @@ > multiclass N3VL_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, > InstrItinClass itin16, InstrItinClass itin32, > string OpcodeStr, string Dt, > - SDNode OpNode, SDNode ExtOp, bit Commutable = 0> { > + SDNode OpNode, bit Commutable = 0> { > + def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16, > + OpcodeStr, !strconcat(Dt, "8"), > + v8i16, v8i8, OpNode, Commutable>; > def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16, > OpcodeStr, !strconcat(Dt, "16"), > - v4i32, v4i16, OpNode, ExtOp, Commutable>; > + v4i32, v4i16, OpNode, Commutable>; > def v2i64 : N3VL<op24, op23, 0b10, op11_8, op4, itin32, > OpcodeStr, !strconcat(Dt, "32"), > - v2i64, v2i32, OpNode, ExtOp, Commutable>; > - def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16, > - OpcodeStr, !strconcat(Dt, "8"), > - v8i16, v8i8, OpNode, ExtOp, Commutable>; > + v2i64, v2i32, OpNode, Commutable>; > +} > + > +multiclass N3VLSL_HS<bit op24, bits<4> op11_8, > + InstrItinClass itin, string OpcodeStr, string Dt, > + SDNode OpNode> { > + def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr, > + !strconcat(Dt, "16"), v4i32, v4i16, OpNode>; > + def v2i32 : N3VLSL<op24, 0b10, op11_8, itin, OpcodeStr, > + !strconcat(Dt, "32"), v2i64, v2i32, OpNode>; > +} > + > +multiclass N3VLExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, > + InstrItinClass itin16, InstrItinClass itin32, > + string OpcodeStr, string Dt, > + SDNode OpNode, SDNode ExtOp, bit Commutable = 0> { > + def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16, > + OpcodeStr, !strconcat(Dt, "8"), > + v8i16, v8i8, OpNode, ExtOp, Commutable>; > + def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16, > + OpcodeStr, !strconcat(Dt, "16"), > + v4i32, v4i16, OpNode, ExtOp, Commutable>; > + def v2i64 : N3VLExt<op24, op23, 0b10, op11_8, op4, itin32, > + OpcodeStr, !strconcat(Dt, "32"), > + v2i64, v2i32, OpNode, ExtOp, Commutable>; > } > > // Neon Long 3-register vector intrinsics. > @@ -1857,6 +1951,29 @@ > } > > > +// Neon Long Multiply-Op vector operations, > +// element sizes of 8, 16 and 32 bits: > +multiclass N3VLMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, > + InstrItinClass itin16, InstrItinClass itin32, > + string OpcodeStr, string Dt, SDNode MulOp, > + SDNode OpNode> { > + def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr, > + !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>; > + def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr, > + !strconcat(Dt, "16"), v4i32, v4i16, MulOp, > OpNode>; > + def v2i64 : N3VLMulOp<op24, op23, 0b10, op11_8, op4, itin32, OpcodeStr, > + !strconcat(Dt, "32"), v2i64, v2i32, MulOp, > OpNode>; > +} > + > +multiclass N3VLMulOpSL_HS<bit op24, bits<4> op11_8, string OpcodeStr, > + string Dt, SDNode MulOp, SDNode OpNode> { > + def v4i16 : N3VLMulOpSL16<op24, 0b01, op11_8, IIC_VMACi16D, OpcodeStr, > + !strconcat(Dt,"16"), v4i32, v4i16, MulOp, > OpNode>; > + def v2i32 : N3VLMulOpSL<op24, 0b10, op11_8, IIC_VMACi32D, OpcodeStr, > + !strconcat(Dt, "32"), v2i64, v2i32, MulOp, > OpNode>; > +} > + > + > // Neon Long 3-argument intrinsics. > > // First with only element sizes of 16 and 32 bits: > @@ -2130,10 +2247,10 @@ > def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32", > v4f32, v4f32, fadd, 1>; > // VADDL : Vector Add Long (Q = D + D) > -defm VADDLs : N3VL_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD, > - "vaddl", "s", add, sext, 1>; > -defm VADDLu : N3VL_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD, > - "vaddl", "u", add, zext, 1>; > +defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD, > + "vaddl", "s", add, sext, 1>; > +defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD, > + "vaddl", "u", add, zext, 1>; > // VADDW : Vector Add Wide (Q = Q + D) > defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>; > defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>; > @@ -2247,16 +2364,14 @@ > (SubReg_i32_lane imm:$lane)))>; > > // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D) > -defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D, > - "vmull", "s", int_arm_neon_vmulls, 1>; > -defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D, > - "vmull", "u", int_arm_neon_vmullu, 1>; > +defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D, > + "vmull", "s", NEONvmulls, 1>; > +defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D, > + "vmull", "u", NEONvmullu, 1>; > def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", > "p8", > v8i16, v8i8, int_arm_neon_vmullp, 1>; > -defm VMULLsls : N3VLIntSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", > - int_arm_neon_vmulls>; > -defm VMULLslu : N3VLIntSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", > - int_arm_neon_vmullu>; > +defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", > NEONvmulls>; > +defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", > NEONvmullu>; > > // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D) > defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D, > @@ -2306,13 +2421,13 @@ > (SubReg_i32_lane imm:$lane)))>; > > // VMLAL : Vector Multiply Accumulate Long (Q += D * D) > -defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D, > - "vmlal", "s", int_arm_neon_vmlals>; > -defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D, > - "vmlal", "u", int_arm_neon_vmlalu>; > +defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D, > + "vmlal", "s", NEONvmulls, add>; > +defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D, > + "vmlal", "u", NEONvmullu, add>; > > -defm VMLALsls : N3VLInt3SL_HS<0, 0b0010, "vmlal", "s", > int_arm_neon_vmlals>; > -defm VMLALslu : N3VLInt3SL_HS<1, 0b0010, "vmlal", "u", > int_arm_neon_vmlalu>; > +defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>; > +defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>; > > // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += > D * D) > defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D, > @@ -2358,13 +2473,13 @@ > (SubReg_i32_lane imm:$lane)))>; > > // VMLSL : Vector Multiply Subtract Long (Q -= D * D) > -defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D, > - "vmlsl", "s", int_arm_neon_vmlsls>; > -defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D, > - "vmlsl", "u", int_arm_neon_vmlslu>; > +defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D, > + "vmlsl", "s", NEONvmulls, sub>; > +defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D, > + "vmlsl", "u", NEONvmullu, sub>; > > -defm VMLSLsls : N3VLInt3SL_HS<0, 0b0110, "vmlsl", "s", > int_arm_neon_vmlsls>; > -defm VMLSLslu : N3VLInt3SL_HS<1, 0b0110, "vmlsl", "u", > int_arm_neon_vmlslu>; > +defm VMLSLsls : N3VLMulOpSL_HS<0, 0b0110, "vmlsl", "s", NEONvmulls, sub>; > +defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>; > > // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D > * D) > defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D, > @@ -2381,10 +2496,10 @@ > def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32", > v4f32, v4f32, fsub, 0>; > // VSUBL : Vector Subtract Long (Q = D - D) > -defm VSUBLs : N3VL_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD, > - "vsubl", "s", sub, sext, 0>; > -defm VSUBLu : N3VL_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD, > - "vsubl", "u", sub, zext, 0>; > +defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD, > + "vsubl", "s", sub, sext, 0>; > +defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD, > + "vsubl", "u", sub, zext, 0>; > // VSUBW : Vector Subtract Wide (Q = Q - D) > defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>; > defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>; > > Modified: llvm/trunk/lib/VMCore/AutoUpgrade.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AutoUpgrade.cpp?rev=112773&r1=112772&r2=112773&view=diff > > ============================================================================== > --- llvm/trunk/lib/VMCore/AutoUpgrade.cpp (original) > +++ llvm/trunk/lib/VMCore/AutoUpgrade.cpp Wed Sep 1 18:50:19 2010 > @@ -90,6 +90,12 @@ > (Name.compare(19, 2, "s.", 2) == 0 || > Name.compare(19, 2, "u.", 2) == 0)) || > > + ((Name.compare(14, 5, "vmull", 5) == 0 || > + Name.compare(14, 5, "vmlal", 5) == 0 || > + Name.compare(14, 5, "vmlsl", 5) == 0) && > + (Name.compare(19, 2, "s.", 2) == 0 || > + Name.compare(19, 2, "u.", 2) == 0)) || > + > (Name.compare(14, 6, "vmovn.", 6) == 0)) { > > // Calls to these are transformed into IR without intrinsics. > @@ -359,6 +365,32 @@ > return Upgraded; > } > > +/// ExtendNEONArgs - For NEON "long" and "wide" operations, where the > results > +/// have vector elements twice as big as one or both source operands, do > the > +/// sign- or zero-extension that used to be handled by intrinsics. The > +/// extended values are returned via V0 and V1. > +static void ExtendNEONArgs(CallInst *CI, Value *Arg0, Value *Arg1, > + Value *&V0, Value *&V1) { > + Function *F = CI->getCalledFunction(); > + const std::string& Name = F->getName(); > + bool isLong = (Name.at(18) == 'l'); > + bool isSigned = (Name.at(19) == 's'); > + > + if (isSigned) { > + if (isLong) > + V0 = new SExtInst(Arg0, CI->getType(), "", CI); > + else > + V0 = Arg0; > + V1 = new SExtInst(Arg1, CI->getType(), "", CI); > + } else { > + if (isLong) > + V0 = new ZExtInst(Arg0, CI->getType(), "", CI); > + else > + V0 = Arg0; > + V1 = new ZExtInst(Arg1, CI->getType(), "", CI); > + } > +} > + > // UpgradeIntrinsicCall - Upgrade a call to an old intrinsic to be a call > the > // upgraded intrinsic. All argument and return casting must be provided in > // order to seamlessly integrate with existing context. > @@ -376,33 +408,32 @@ > // Upgrade ARM NEON intrinsics. > if (Name.compare(5, 9, "arm.neon.", 9) == 0) { > Instruction *NewI; > + Value *V0, *V1; > if (Name.compare(14, 7, "vmovls.", 7) == 0) { > NewI = new SExtInst(CI->getArgOperand(0), CI->getType(), > "upgraded." + CI->getName(), CI); > } else if (Name.compare(14, 7, "vmovlu.", 7) == 0) { > NewI = new ZExtInst(CI->getArgOperand(0), CI->getType(), > "upgraded." + CI->getName(), CI); > - > - } else if (Name.compare(14, 4, "vadd", 4) == 0 || > - Name.compare(14, 4, "vsub", 4) == 0) { > - // Extend one (vaddw/vsubw) or both (vaddl/vsubl) operands. > - Value *V0 = CI->getArgOperand(0); > - Value *V1 = CI->getArgOperand(1); > - if (Name.at(19) == 's') { > - if (Name.at(18) == 'l') > - V0 = new SExtInst(CI->getArgOperand(0), CI->getType(), "", > CI); > - V1 = new SExtInst(CI->getArgOperand(1), CI->getType(), "", CI); > - } else { > - assert(Name.at(19) == 'u' && "unexpected vadd/vsub intrinsic"); > - if (Name.at(18) == 'l') > - V0 = new ZExtInst(CI->getArgOperand(0), CI->getType(), "", > CI); > - V1 = new ZExtInst(CI->getArgOperand(1), CI->getType(), "", CI); > - } > - if (Name.compare(14, 4, "vadd", 4) == 0) > - NewI = BinaryOperator::CreateAdd(V0, > V1,"upgraded."+CI->getName(),CI); > - else > - NewI = BinaryOperator::CreateSub(V0, > V1,"upgraded."+CI->getName(),CI); > - > + } else if (Name.compare(14, 4, "vadd", 4) == 0) { > + ExtendNEONArgs(CI, CI->getArgOperand(0), CI->getArgOperand(1), V0, > V1); > + NewI = BinaryOperator::CreateAdd(V0, V1, > "upgraded."+CI->getName(), CI); > + } else if (Name.compare(14, 4, "vsub", 4) == 0) { > + ExtendNEONArgs(CI, CI->getArgOperand(0), CI->getArgOperand(1), V0, > V1); > + NewI = BinaryOperator::CreateSub(V0, > V1,"upgraded."+CI->getName(),CI); > + } else if (Name.compare(14, 4, "vmul", 4) == 0) { > + ExtendNEONArgs(CI, CI->getArgOperand(0), CI->getArgOperand(1), V0, > V1); > + NewI = BinaryOperator::CreateMul(V0, > V1,"upgraded."+CI->getName(),CI); > + } else if (Name.compare(14, 4, "vmla", 4) == 0) { > + ExtendNEONArgs(CI, CI->getArgOperand(1), CI->getArgOperand(2), V0, > V1); > + Instruction *MulI = BinaryOperator::CreateMul(V0, V1, "", CI); > + NewI = BinaryOperator::CreateAdd(CI->getArgOperand(0), MulI, > + "upgraded."+CI->getName(), CI); > + } else if (Name.compare(14, 4, "vmls", 4) == 0) { > + ExtendNEONArgs(CI, CI->getArgOperand(1), CI->getArgOperand(2), V0, > V1); > + Instruction *MulI = BinaryOperator::CreateMul(V0, V1, "", CI); > + NewI = BinaryOperator::CreateSub(CI->getArgOperand(0), MulI, > + "upgraded."+CI->getName(), CI); > } else if (Name.compare(14, 6, "vmovn.", 6) == 0) { > NewI = new TruncInst(CI->getArgOperand(0), CI->getType(), > "upgraded." + CI->getName(), CI); > > Modified: llvm/trunk/test/Bitcode/neon-intrinsics.ll > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bitcode/neon-intrinsics.ll?rev=112773&r1=112772&r2=112773&view=diff > > ============================================================================== > --- llvm/trunk/test/Bitcode/neon-intrinsics.ll (original) > +++ llvm/trunk/test/Bitcode/neon-intrinsics.ll Wed Sep 1 18:50:19 2010 > @@ -52,7 +52,7 @@ > ; CHECK: zext <4 x i16> > ; CHECK-NEXT: add <4 x i32> > > -; vsubl/vsubw should be auto-upgraded to sub with sext/zext > +; vsubl/vsubw should be auto-upgraded to subtract with sext/zext > > ; CHECK: vsubls16 > ; CHECK-NOT: arm.neon.vsubls.v4i32 > @@ -76,6 +76,56 @@ > ; CHECK: zext <4 x i16> > ; CHECK-NEXT: sub <4 x i32> > > +; vmull should be auto-upgraded to multiply with sext/zext > +; (but vmullp should remain an intrinsic) > + > +; CHECK: vmulls8 > +; CHECK-NOT: arm.neon.vmulls.v8i16 > +; CHECK: sext <8 x i8> > +; CHECK-NEXT: sext <8 x i8> > +; CHECK-NEXT: mul <8 x i16> > + > +; CHECK: vmullu16 > +; CHECK-NOT: arm.neon.vmullu.v4i32 > +; CHECK: zext <4 x i16> > +; CHECK-NEXT: zext <4 x i16> > +; CHECK-NEXT: mul <4 x i32> > + > +; CHECK: vmullp8 > +; CHECK: arm.neon.vmullp.v8i16 > + > +; vmlal should be auto-upgraded to multiply/add with sext/zext > + > +; CHECK: vmlals32 > +; CHECK-NOT: arm.neon.vmlals.v2i64 > +; CHECK: sext <2 x i32> > +; CHECK-NEXT: sext <2 x i32> > +; CHECK-NEXT: mul <2 x i64> > +; CHECK-NEXT: add <2 x i64> > + > +; CHECK: vmlalu8 > +; CHECK-NOT: arm.neon.vmlalu.v8i16 > +; CHECK: zext <8 x i8> > +; CHECK-NEXT: zext <8 x i8> > +; CHECK-NEXT: mul <8 x i16> > +; CHECK-NEXT: add <8 x i16> > + > +; vmlsl should be auto-upgraded to multiply/sub with sext/zext > + > +; CHECK: vmlsls16 > +; CHECK-NOT: arm.neon.vmlsls.v4i32 > +; CHECK: sext <4 x i16> > +; CHECK-NEXT: sext <4 x i16> > +; CHECK-NEXT: mul <4 x i32> > +; CHECK-NEXT: sub <4 x i32> > + > +; CHECK: vmlslu32 > +; CHECK-NOT: arm.neon.vmlslu.v2i64 > +; CHECK: zext <2 x i32> > +; CHECK-NEXT: zext <2 x i32> > +; CHECK-NEXT: mul <2 x i64> > +; CHECK-NEXT: sub <2 x i64> > + > ; vmovn should be auto-upgraded to trunc > > ; CHECK: vmovni16 > > Modified: llvm/trunk/test/Bitcode/neon-intrinsics.ll.bc > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bitcode/neon-intrinsics.ll.bc?rev=112773&r1=112772&r2=112773&view=diff > > ============================================================================== > Binary files - no diff available. > > Modified: llvm/trunk/test/CodeGen/ARM/vmla.ll > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vmla.ll?rev=112773&r1=112772&r2=112773&view=diff > > ============================================================================== > --- llvm/trunk/test/CodeGen/ARM/vmla.ll (original) > +++ llvm/trunk/test/CodeGen/ARM/vmla.ll Wed Sep 1 18:50:19 2010 > @@ -94,8 +94,11 @@ > %tmp1 = load <8 x i16>* %A > %tmp2 = load <8 x i8>* %B > %tmp3 = load <8 x i8>* %C > - %tmp4 = call <8 x i16> @llvm.arm.neon.vmlals.v8i16(<8 x i16> %tmp1, > <8 x i8> %tmp2, <8 x i8> %tmp3) > - ret <8 x i16> %tmp4 > + %tmp4 = sext <8 x i8> %tmp2 to <8 x i16> > + %tmp5 = sext <8 x i8> %tmp3 to <8 x i16> > + %tmp6 = mul <8 x i16> %tmp4, %tmp5 > + %tmp7 = add <8 x i16> %tmp1, %tmp6 > + ret <8 x i16> %tmp7 > } > > define <4 x i32> @vmlals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) > nounwind { > @@ -104,8 +107,11 @@ > %tmp1 = load <4 x i32>* %A > %tmp2 = load <4 x i16>* %B > %tmp3 = load <4 x i16>* %C > - %tmp4 = call <4 x i32> @llvm.arm.neon.vmlals.v4i32(<4 x i32> %tmp1, > <4 x i16> %tmp2, <4 x i16> %tmp3) > - ret <4 x i32> %tmp4 > + %tmp4 = sext <4 x i16> %tmp2 to <4 x i32> > + %tmp5 = sext <4 x i16> %tmp3 to <4 x i32> > + %tmp6 = mul <4 x i32> %tmp4, %tmp5 > + %tmp7 = add <4 x i32> %tmp1, %tmp6 > + ret <4 x i32> %tmp7 > } > > define <2 x i64> @vmlals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) > nounwind { > @@ -114,8 +120,11 @@ > %tmp1 = load <2 x i64>* %A > %tmp2 = load <2 x i32>* %B > %tmp3 = load <2 x i32>* %C > - %tmp4 = call <2 x i64> @llvm.arm.neon.vmlals.v2i64(<2 x i64> %tmp1, > <2 x i32> %tmp2, <2 x i32> %tmp3) > - ret <2 x i64> %tmp4 > + %tmp4 = sext <2 x i32> %tmp2 to <2 x i64> > + %tmp5 = sext <2 x i32> %tmp3 to <2 x i64> > + %tmp6 = mul <2 x i64> %tmp4, %tmp5 > + %tmp7 = add <2 x i64> %tmp1, %tmp6 > + ret <2 x i64> %tmp7 > } > > define <8 x i16> @vmlalu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) > nounwind { > @@ -124,8 +133,11 @@ > %tmp1 = load <8 x i16>* %A > %tmp2 = load <8 x i8>* %B > %tmp3 = load <8 x i8>* %C > - %tmp4 = call <8 x i16> @llvm.arm.neon.vmlalu.v8i16(<8 x i16> %tmp1, > <8 x i8> %tmp2, <8 x i8> %tmp3) > - ret <8 x i16> %tmp4 > + %tmp4 = zext <8 x i8> %tmp2 to <8 x i16> > + %tmp5 = zext <8 x i8> %tmp3 to <8 x i16> > + %tmp6 = mul <8 x i16> %tmp4, %tmp5 > + %tmp7 = add <8 x i16> %tmp1, %tmp6 > + ret <8 x i16> %tmp7 > } > > define <4 x i32> @vmlalu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) > nounwind { > @@ -134,8 +146,11 @@ > %tmp1 = load <4 x i32>* %A > %tmp2 = load <4 x i16>* %B > %tmp3 = load <4 x i16>* %C > - %tmp4 = call <4 x i32> @llvm.arm.neon.vmlalu.v4i32(<4 x i32> %tmp1, > <4 x i16> %tmp2, <4 x i16> %tmp3) > - ret <4 x i32> %tmp4 > + %tmp4 = zext <4 x i16> %tmp2 to <4 x i32> > + %tmp5 = zext <4 x i16> %tmp3 to <4 x i32> > + %tmp6 = mul <4 x i32> %tmp4, %tmp5 > + %tmp7 = add <4 x i32> %tmp1, %tmp6 > + ret <4 x i32> %tmp7 > } > > define <2 x i64> @vmlalu32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) > nounwind { > @@ -144,8 +159,11 @@ > %tmp1 = load <2 x i64>* %A > %tmp2 = load <2 x i32>* %B > %tmp3 = load <2 x i32>* %C > - %tmp4 = call <2 x i64> @llvm.arm.neon.vmlalu.v2i64(<2 x i64> %tmp1, > <2 x i32> %tmp2, <2 x i32> %tmp3) > - ret <2 x i64> %tmp4 > + %tmp4 = zext <2 x i32> %tmp2 to <2 x i64> > + %tmp5 = zext <2 x i32> %tmp3 to <2 x i64> > + %tmp6 = mul <2 x i64> %tmp4, %tmp5 > + %tmp7 = add <2 x i64> %tmp1, %tmp6 > + ret <2 x i64> %tmp7 > } > > define arm_aapcs_vfpcc <4 x i32> @test_vmlal_lanes16(<4 x i32> > %arg0_int32x4_t, <4 x i16> %arg1_int16x4_t, <4 x i16> %arg2_int16x4_t) > nounwind readnone { > @@ -153,8 +171,11 @@ > ; CHECK: test_vmlal_lanes16 > ; CHECK: vmlal.s16 q0, d2, d3[1] > %0 = shufflevector <4 x i16> %arg2_int16x4_t, <4 x i16> undef, <4 x i32> > <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1] > - %1 = tail call <4 x i32> @llvm.arm.neon.vmlals.v4i32(<4 x i32> > %arg0_int32x4_t, <4 x i16> %arg1_int16x4_t, <4 x i16> %0) ; <<4 x i32>> > [#uses=1] > - ret <4 x i32> %1 > + %1 = sext <4 x i16> %arg1_int16x4_t to <4 x i32> > + %2 = sext <4 x i16> %0 to <4 x i32> > + %3 = mul <4 x i32> %1, %2 > + %4 = add <4 x i32> %arg0_int32x4_t, %3 > + ret <4 x i32> %4 > } > > define arm_aapcs_vfpcc <2 x i64> @test_vmlal_lanes32(<2 x i64> > %arg0_int64x2_t, <2 x i32> %arg1_int32x2_t, <2 x i32> %arg2_int32x2_t) > nounwind readnone { > @@ -162,8 +183,11 @@ > ; CHECK: test_vmlal_lanes32 > ; CHECK: vmlal.s32 q0, d2, d3[1] > %0 = shufflevector <2 x i32> %arg2_int32x2_t, <2 x i32> undef, <2 x i32> > <i32 1, i32 1> ; <<2 x i32>> [#uses=1] > - %1 = tail call <2 x i64> @llvm.arm.neon.vmlals.v2i64(<2 x i64> > %arg0_int64x2_t, <2 x i32> %arg1_int32x2_t, <2 x i32> %0) ; <<2 x i64>> > [#uses=1] > - ret <2 x i64> %1 > + %1 = sext <2 x i32> %arg1_int32x2_t to <2 x i64> > + %2 = sext <2 x i32> %0 to <2 x i64> > + %3 = mul <2 x i64> %1, %2 > + %4 = add <2 x i64> %arg0_int64x2_t, %3 > + ret <2 x i64> %4 > } > > define arm_aapcs_vfpcc <4 x i32> @test_vmlal_laneu16(<4 x i32> > %arg0_uint32x4_t, <4 x i16> %arg1_uint16x4_t, <4 x i16> %arg2_uint16x4_t) > nounwind readnone { > @@ -171,8 +195,11 @@ > ; CHECK: test_vmlal_laneu16 > ; CHECK: vmlal.u16 q0, d2, d3[1] > %0 = shufflevector <4 x i16> %arg2_uint16x4_t, <4 x i16> undef, <4 x i32> > <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1] > - %1 = tail call <4 x i32> @llvm.arm.neon.vmlalu.v4i32(<4 x i32> > %arg0_uint32x4_t, <4 x i16> %arg1_uint16x4_t, <4 x i16> %0) ; <<4 x i32>> > [#uses=1] > - ret <4 x i32> %1 > + %1 = zext <4 x i16> %arg1_uint16x4_t to <4 x i32> > + %2 = zext <4 x i16> %0 to <4 x i32> > + %3 = mul <4 x i32> %1, %2 > + %4 = add <4 x i32> %arg0_uint32x4_t, %3 > + ret <4 x i32> %4 > } > > define arm_aapcs_vfpcc <2 x i64> @test_vmlal_laneu32(<2 x i64> > %arg0_uint64x2_t, <2 x i32> %arg1_uint32x2_t, <2 x i32> %arg2_uint32x2_t) > nounwind readnone { > @@ -180,14 +207,9 @@ > ; CHECK: test_vmlal_laneu32 > ; CHECK: vmlal.u32 q0, d2, d3[1] > %0 = shufflevector <2 x i32> %arg2_uint32x2_t, <2 x i32> undef, <2 x i32> > <i32 1, i32 1> ; <<2 x i32>> [#uses=1] > - %1 = tail call <2 x i64> @llvm.arm.neon.vmlalu.v2i64(<2 x i64> > %arg0_uint64x2_t, <2 x i32> %arg1_uint32x2_t, <2 x i32> %0) ; <<2 x i64>> > [#uses=1] > - ret <2 x i64> %1 > + %1 = zext <2 x i32> %arg1_uint32x2_t to <2 x i64> > + %2 = zext <2 x i32> %0 to <2 x i64> > + %3 = mul <2 x i64> %1, %2 > + %4 = add <2 x i64> %arg0_uint64x2_t, %3 > + ret <2 x i64> %4 > } > - > -declare <8 x i16> @llvm.arm.neon.vmlals.v8i16(<8 x i16>, <8 x i8>, <8 x > i8>) nounwind readnone > -declare <4 x i32> @llvm.arm.neon.vmlals.v4i32(<4 x i32>, <4 x i16>, <4 x > i16>) nounwind readnone > -declare <2 x i64> @llvm.arm.neon.vmlals.v2i64(<2 x i64>, <2 x i32>, <2 x > i32>) nounwind readnone > - > -declare <8 x i16> @llvm.arm.neon.vmlalu.v8i16(<8 x i16>, <8 x i8>, <8 x > i8>) nounwind readnone > -declare <4 x i32> @llvm.arm.neon.vmlalu.v4i32(<4 x i32>, <4 x i16>, <4 x > i16>) nounwind readnone > -declare <2 x i64> @llvm.arm.neon.vmlalu.v2i64(<2 x i64>, <2 x i32>, <2 x > i32>) nounwind readnone > > Modified: llvm/trunk/test/CodeGen/ARM/vmls.ll > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vmls.ll?rev=112773&r1=112772&r2=112773&view=diff > > ============================================================================== > --- llvm/trunk/test/CodeGen/ARM/vmls.ll (original) > +++ llvm/trunk/test/CodeGen/ARM/vmls.ll Wed Sep 1 18:50:19 2010 > @@ -94,8 +94,11 @@ > %tmp1 = load <8 x i16>* %A > %tmp2 = load <8 x i8>* %B > %tmp3 = load <8 x i8>* %C > - %tmp4 = call <8 x i16> @llvm.arm.neon.vmlsls.v8i16(<8 x i16> %tmp1, > <8 x i8> %tmp2, <8 x i8> %tmp3) > - ret <8 x i16> %tmp4 > + %tmp4 = sext <8 x i8> %tmp2 to <8 x i16> > + %tmp5 = sext <8 x i8> %tmp3 to <8 x i16> > + %tmp6 = mul <8 x i16> %tmp4, %tmp5 > + %tmp7 = sub <8 x i16> %tmp1, %tmp6 > + ret <8 x i16> %tmp7 > } > > define <4 x i32> @vmlsls16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) > nounwind { > @@ -104,8 +107,11 @@ > %tmp1 = load <4 x i32>* %A > %tmp2 = load <4 x i16>* %B > %tmp3 = load <4 x i16>* %C > - %tmp4 = call <4 x i32> @llvm.arm.neon.vmlsls.v4i32(<4 x i32> %tmp1, > <4 x i16> %tmp2, <4 x i16> %tmp3) > - ret <4 x i32> %tmp4 > + %tmp4 = sext <4 x i16> %tmp2 to <4 x i32> > + %tmp5 = sext <4 x i16> %tmp3 to <4 x i32> > + %tmp6 = mul <4 x i32> %tmp4, %tmp5 > + %tmp7 = sub <4 x i32> %tmp1, %tmp6 > + ret <4 x i32> %tmp7 > } > > define <2 x i64> @vmlsls32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) > nounwind { > @@ -114,8 +120,11 @@ > %tmp1 = load <2 x i64>* %A > %tmp2 = load <2 x i32>* %B > %tmp3 = load <2 x i32>* %C > - %tmp4 = call <2 x i64> @llvm.arm.neon.vmlsls.v2i64(<2 x i64> %tmp1, > <2 x i32> %tmp2, <2 x i32> %tmp3) > - ret <2 x i64> %tmp4 > + %tmp4 = sext <2 x i32> %tmp2 to <2 x i64> > + %tmp5 = sext <2 x i32> %tmp3 to <2 x i64> > + %tmp6 = mul <2 x i64> %tmp4, %tmp5 > + %tmp7 = sub <2 x i64> %tmp1, %tmp6 > + ret <2 x i64> %tmp7 > } > > define <8 x i16> @vmlslu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) > nounwind { > @@ -124,8 +133,11 @@ > %tmp1 = load <8 x i16>* %A > %tmp2 = load <8 x i8>* %B > %tmp3 = load <8 x i8>* %C > - %tmp4 = call <8 x i16> @llvm.arm.neon.vmlslu.v8i16(<8 x i16> %tmp1, > <8 x i8> %tmp2, <8 x i8> %tmp3) > - ret <8 x i16> %tmp4 > + %tmp4 = zext <8 x i8> %tmp2 to <8 x i16> > + %tmp5 = zext <8 x i8> %tmp3 to <8 x i16> > + %tmp6 = mul <8 x i16> %tmp4, %tmp5 > + %tmp7 = sub <8 x i16> %tmp1, %tmp6 > + ret <8 x i16> %tmp7 > } > > define <4 x i32> @vmlslu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) > nounwind { > @@ -134,8 +146,11 @@ > %tmp1 = load <4 x i32>* %A > %tmp2 = load <4 x i16>* %B > %tmp3 = load <4 x i16>* %C > - %tmp4 = call <4 x i32> @llvm.arm.neon.vmlslu.v4i32(<4 x i32> %tmp1, > <4 x i16> %tmp2, <4 x i16> %tmp3) > - ret <4 x i32> %tmp4 > + %tmp4 = zext <4 x i16> %tmp2 to <4 x i32> > + %tmp5 = zext <4 x i16> %tmp3 to <4 x i32> > + %tmp6 = mul <4 x i32> %tmp4, %tmp5 > + %tmp7 = sub <4 x i32> %tmp1, %tmp6 > + ret <4 x i32> %tmp7 > } > > define <2 x i64> @vmlslu32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) > nounwind { > @@ -144,8 +159,11 @@ > %tmp1 = load <2 x i64>* %A > %tmp2 = load <2 x i32>* %B > %tmp3 = load <2 x i32>* %C > - %tmp4 = call <2 x i64> @llvm.arm.neon.vmlslu.v2i64(<2 x i64> %tmp1, > <2 x i32> %tmp2, <2 x i32> %tmp3) > - ret <2 x i64> %tmp4 > + %tmp4 = zext <2 x i32> %tmp2 to <2 x i64> > + %tmp5 = zext <2 x i32> %tmp3 to <2 x i64> > + %tmp6 = mul <2 x i64> %tmp4, %tmp5 > + %tmp7 = sub <2 x i64> %tmp1, %tmp6 > + ret <2 x i64> %tmp7 > } > > define arm_aapcs_vfpcc <4 x i32> @test_vmlsl_lanes16(<4 x i32> > %arg0_int32x4_t, <4 x i16> %arg1_int16x4_t, <4 x i16> %arg2_int16x4_t) > nounwind readnone { > @@ -153,8 +171,11 @@ > ; CHECK: test_vmlsl_lanes16 > ; CHECK: vmlsl.s16 q0, d2, d3[1] > %0 = shufflevector <4 x i16> %arg2_int16x4_t, <4 x i16> undef, <4 x i32> > <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1] > - %1 = tail call <4 x i32> @llvm.arm.neon.vmlsls.v4i32(<4 x i32> > %arg0_int32x4_t, <4 x i16> %arg1_int16x4_t, <4 x i16> %0) ; <<4 x i32>> > [#uses=1] > - ret <4 x i32> %1 > + %1 = sext <4 x i16> %arg1_int16x4_t to <4 x i32> > + %2 = sext <4 x i16> %0 to <4 x i32> > + %3 = mul <4 x i32> %1, %2 > + %4 = sub <4 x i32> %arg0_int32x4_t, %3 > + ret <4 x i32> %4 > } > > define arm_aapcs_vfpcc <2 x i64> @test_vmlsl_lanes32(<2 x i64> > %arg0_int64x2_t, <2 x i32> %arg1_int32x2_t, <2 x i32> %arg2_int32x2_t) > nounwind readnone { > @@ -162,8 +183,11 @@ > ; CHECK: test_vmlsl_lanes32 > ; CHECK: vmlsl.s32 q0, d2, d3[1] > %0 = shufflevector <2 x i32> %arg2_int32x2_t, <2 x i32> undef, <2 x i32> > <i32 1, i32 1> ; <<2 x i32>> [#uses=1] > - %1 = tail call <2 x i64> @llvm.arm.neon.vmlsls.v2i64(<2 x i64> > %arg0_int64x2_t, <2 x i32> %arg1_int32x2_t, <2 x i32> %0) ; <<2 x i64>> > [#uses=1] > - ret <2 x i64> %1 > + %1 = sext <2 x i32> %arg1_int32x2_t to <2 x i64> > + %2 = sext <2 x i32> %0 to <2 x i64> > + %3 = mul <2 x i64> %1, %2 > + %4 = sub <2 x i64> %arg0_int64x2_t, %3 > + ret <2 x i64> %4 > } > > define arm_aapcs_vfpcc <4 x i32> @test_vmlsl_laneu16(<4 x i32> > %arg0_uint32x4_t, <4 x i16> %arg1_uint16x4_t, <4 x i16> %arg2_uint16x4_t) > nounwind readnone { > @@ -171,8 +195,11 @@ > ; CHECK: test_vmlsl_laneu16 > ; CHECK: vmlsl.u16 q0, d2, d3[1] > %0 = shufflevector <4 x i16> %arg2_uint16x4_t, <4 x i16> undef, <4 x i32> > <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1] > - %1 = tail call <4 x i32> @llvm.arm.neon.vmlslu.v4i32(<4 x i32> > %arg0_uint32x4_t, <4 x i16> %arg1_uint16x4_t, <4 x i16> %0) ; <<4 x i32>> > [#uses=1] > - ret <4 x i32> %1 > + %1 = zext <4 x i16> %arg1_uint16x4_t to <4 x i32> > + %2 = zext <4 x i16> %0 to <4 x i32> > + %3 = mul <4 x i32> %1, %2 > + %4 = sub <4 x i32> %arg0_uint32x4_t, %3 > + ret <4 x i32> %4 > } > > define arm_aapcs_vfpcc <2 x i64> @test_vmlsl_laneu32(<2 x i64> > %arg0_uint64x2_t, <2 x i32> %arg1_uint32x2_t, <2 x i32> %arg2_uint32x2_t) > nounwind readnone { > @@ -180,14 +207,9 @@ > ; CHECK: test_vmlsl_laneu32 > ; CHECK: vmlsl.u32 q0, d2, d3[1] > %0 = shufflevector <2 x i32> %arg2_uint32x2_t, <2 x i32> undef, <2 x i32> > <i32 1, i32 1> ; <<2 x i32>> [#uses=1] > - %1 = tail call <2 x i64> @llvm.arm.neon.vmlslu.v2i64(<2 x i64> > %arg0_uint64x2_t, <2 x i32> %arg1_uint32x2_t, <2 x i32> %0) ; <<2 x i64>> > [#uses=1] > - ret <2 x i64> %1 > + %1 = zext <2 x i32> %arg1_uint32x2_t to <2 x i64> > + %2 = zext <2 x i32> %0 to <2 x i64> > + %3 = mul <2 x i64> %1, %2 > + %4 = sub <2 x i64> %arg0_uint64x2_t, %3 > + ret <2 x i64> %4 > } > - > -declare <8 x i16> @llvm.arm.neon.vmlsls.v8i16(<8 x i16>, <8 x i8>, <8 x > i8>) nounwind readnone > -declare <4 x i32> @llvm.arm.neon.vmlsls.v4i32(<4 x i32>, <4 x i16>, <4 x > i16>) nounwind readnone > -declare <2 x i64> @llvm.arm.neon.vmlsls.v2i64(<2 x i64>, <2 x i32>, <2 x > i32>) nounwind readnone > - > -declare <8 x i16> @llvm.arm.neon.vmlslu.v8i16(<8 x i16>, <8 x i8>, <8 x > i8>) nounwind readnone > -declare <4 x i32> @llvm.arm.neon.vmlslu.v4i32(<4 x i32>, <4 x i16>, <4 x > i16>) nounwind readnone > -declare <2 x i64> @llvm.arm.neon.vmlslu.v2i64(<2 x i64>, <2 x i32>, <2 x > i32>) nounwind readnone > > Modified: llvm/trunk/test/CodeGen/ARM/vmul.ll > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vmul.ll?rev=112773&r1=112772&r2=112773&view=diff > > ============================================================================== > --- llvm/trunk/test/CodeGen/ARM/vmul.ll (original) > +++ llvm/trunk/test/CodeGen/ARM/vmul.ll Wed Sep 1 18:50:19 2010 > @@ -152,8 +152,10 @@ > ;CHECK: vmull.s8 > %tmp1 = load <8 x i8>* %A > %tmp2 = load <8 x i8>* %B > - %tmp3 = call <8 x i16> @llvm.arm.neon.vmulls.v8i16(<8 x i8> %tmp1, > <8 x i8> %tmp2) > - ret <8 x i16> %tmp3 > + %tmp3 = sext <8 x i8> %tmp1 to <8 x i16> > + %tmp4 = sext <8 x i8> %tmp2 to <8 x i16> > + %tmp5 = mul <8 x i16> %tmp3, %tmp4 > + ret <8 x i16> %tmp5 > } > > define <4 x i32> @vmulls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { > @@ -161,8 +163,10 @@ > ;CHECK: vmull.s16 > %tmp1 = load <4 x i16>* %A > %tmp2 = load <4 x i16>* %B > - %tmp3 = call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %tmp1, > <4 x i16> %tmp2) > - ret <4 x i32> %tmp3 > + %tmp3 = sext <4 x i16> %tmp1 to <4 x i32> > + %tmp4 = sext <4 x i16> %tmp2 to <4 x i32> > + %tmp5 = mul <4 x i32> %tmp3, %tmp4 > + ret <4 x i32> %tmp5 > } > > define <2 x i64> @vmulls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { > @@ -170,8 +174,10 @@ > ;CHECK: vmull.s32 > %tmp1 = load <2 x i32>* %A > %tmp2 = load <2 x i32>* %B > - %tmp3 = call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32> %tmp1, > <2 x i32> %tmp2) > - ret <2 x i64> %tmp3 > + %tmp3 = sext <2 x i32> %tmp1 to <2 x i64> > + %tmp4 = sext <2 x i32> %tmp2 to <2 x i64> > + %tmp5 = mul <2 x i64> %tmp3, %tmp4 > + ret <2 x i64> %tmp5 > } > > define <8 x i16> @vmullu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { > @@ -179,8 +185,10 @@ > ;CHECK: vmull.u8 > %tmp1 = load <8 x i8>* %A > %tmp2 = load <8 x i8>* %B > - %tmp3 = call <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8> %tmp1, > <8 x i8> %tmp2) > - ret <8 x i16> %tmp3 > + %tmp3 = zext <8 x i8> %tmp1 to <8 x i16> > + %tmp4 = zext <8 x i8> %tmp2 to <8 x i16> > + %tmp5 = mul <8 x i16> %tmp3, %tmp4 > + ret <8 x i16> %tmp5 > } > > define <4 x i32> @vmullu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { > @@ -188,8 +196,10 @@ > ;CHECK: vmull.u16 > %tmp1 = load <4 x i16>* %A > %tmp2 = load <4 x i16>* %B > - %tmp3 = call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> %tmp1, > <4 x i16> %tmp2) > - ret <4 x i32> %tmp3 > + %tmp3 = zext <4 x i16> %tmp1 to <4 x i32> > + %tmp4 = zext <4 x i16> %tmp2 to <4 x i32> > + %tmp5 = mul <4 x i32> %tmp3, %tmp4 > + ret <4 x i32> %tmp5 > } > > define <2 x i64> @vmullu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { > @@ -197,8 +207,10 @@ > ;CHECK: vmull.u32 > %tmp1 = load <2 x i32>* %A > %tmp2 = load <2 x i32>* %B > - %tmp3 = call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32> %tmp1, > <2 x i32> %tmp2) > - ret <2 x i64> %tmp3 > + %tmp3 = zext <2 x i32> %tmp1 to <2 x i64> > + %tmp4 = zext <2 x i32> %tmp2 to <2 x i64> > + %tmp5 = mul <2 x i64> %tmp3, %tmp4 > + ret <2 x i64> %tmp5 > } > > define <8 x i16> @vmullp8(<8 x i8>* %A, <8 x i8>* %B) nounwind { > @@ -215,8 +227,10 @@ > ; CHECK: test_vmull_lanes16 > ; CHECK: vmull.s16 q0, d0, d1[1] > %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <4 x i32> > <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1] > - %1 = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> > %arg0_int16x4_t, <4 x i16> %0) ; <<4 x i32>> [#uses=1] > - ret <4 x i32> %1 > + %1 = sext <4 x i16> %arg0_int16x4_t to <4 x i32> > + %2 = sext <4 x i16> %0 to <4 x i32> > + %3 = mul <4 x i32> %1, %2 > + ret <4 x i32> %3 > } > > define arm_aapcs_vfpcc <2 x i64> @test_vmull_lanes32(<2 x i32> > %arg0_int32x2_t, <2 x i32> %arg1_int32x2_t) nounwind readnone { > @@ -224,8 +238,10 @@ > ; CHECK: test_vmull_lanes32 > ; CHECK: vmull.s32 q0, d0, d1[1] > %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <2 x i32> > <i32 1, i32 1> ; <<2 x i32>> [#uses=1] > - %1 = tail call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32> > %arg0_int32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1] > - ret <2 x i64> %1 > + %1 = sext <2 x i32> %arg0_int32x2_t to <2 x i64> > + %2 = sext <2 x i32> %0 to <2 x i64> > + %3 = mul <2 x i64> %1, %2 > + ret <2 x i64> %3 > } > > define arm_aapcs_vfpcc <4 x i32> @test_vmull_laneu16(<4 x i16> > %arg0_uint16x4_t, <4 x i16> %arg1_uint16x4_t) nounwind readnone { > @@ -233,8 +249,10 @@ > ; CHECK: test_vmull_laneu16 > ; CHECK: vmull.u16 q0, d0, d1[1] > %0 = shufflevector <4 x i16> %arg1_uint16x4_t, <4 x i16> undef, <4 x i32> > <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1] > - %1 = tail call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> > %arg0_uint16x4_t, <4 x i16> %0) ; <<4 x i32>> [#uses=1] > - ret <4 x i32> %1 > + %1 = zext <4 x i16> %arg0_uint16x4_t to <4 x i32> > + %2 = zext <4 x i16> %0 to <4 x i32> > + %3 = mul <4 x i32> %1, %2 > + ret <4 x i32> %3 > } > > define arm_aapcs_vfpcc <2 x i64> @test_vmull_laneu32(<2 x i32> > %arg0_uint32x2_t, <2 x i32> %arg1_uint32x2_t) nounwind readnone { > @@ -242,16 +260,10 @@ > ; CHECK: test_vmull_laneu32 > ; CHECK: vmull.u32 q0, d0, d1[1] > %0 = shufflevector <2 x i32> %arg1_uint32x2_t, <2 x i32> undef, <2 x i32> > <i32 1, i32 1> ; <<2 x i32>> [#uses=1] > - %1 = tail call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32> > %arg0_uint32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1] > - ret <2 x i64> %1 > + %1 = zext <2 x i32> %arg0_uint32x2_t to <2 x i64> > + %2 = zext <2 x i32> %0 to <2 x i64> > + %3 = mul <2 x i64> %1, %2 > + ret <2 x i64> %3 > } > > -declare <8 x i16> @llvm.arm.neon.vmulls.v8i16(<8 x i8>, <8 x i8>) nounwind > readnone > -declare <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16>, <4 x i16>) > nounwind readnone > -declare <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32>, <2 x i32>) > nounwind readnone > - > -declare <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8>, <8 x i8>) nounwind > readnone > -declare <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16>, <4 x i16>) > nounwind readnone > -declare <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32>, <2 x i32>) > nounwind readnone > - > declare <8 x i16> @llvm.arm.neon.vmullp.v8i16(<8 x i8>, <8 x i8>) > nounwind readnone > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100901/20aa2b6b/attachment.html From sabre at nondot.org Wed Sep 1 19:21:16 2010 From: sabre at nondot.org (Chris Lattner) Date: Thu, 02 Sep 2010 00:21:16 -0000 Subject: [llvm-commits] [www] r112783 - /www/trunk/ProjectsWithLLVM/index.html Message-ID: <20100902002116.DCE9F2A6C12C@llvm.org> Author: lattner Date: Wed Sep 1 19:21:16 2010 New Revision: 112783 URL: http://llvm.org/viewvc/llvm-project?rev=112783&view=rev Log: add 'crack' from Shannon Weyrick Modified: www/trunk/ProjectsWithLLVM/index.html Modified: www/trunk/ProjectsWithLLVM/index.html URL: http://llvm.org/viewvc/llvm-project/www/trunk/ProjectsWithLLVM/index.html?rev=112783&r1=112782&r2=112783&view=diff ============================================================================== --- www/trunk/ProjectsWithLLVM/index.html (original) +++ www/trunk/ProjectsWithLLVM/index.html Wed Sep 1 19:21:16 2010 @@ -35,6 +35,7 @@ <div class="www_text"> <ul> +<li><a href="#crack">The Crack Programming Language</a></li> <li><a href="#rubinius">Rubinius: a Ruby implementation</a></li> <li><a href="#unladenswallow">Unladen Swallow: an optimization branch of CPython</a></li> @@ -69,6 +70,21 @@ <!--=========================================================================--> <div class="www_subsection"> + <a name="crack">The Crack Programming Language</a><br> +</div> +<!--=========================================================================--> + +<div class="www_text"> +<p><a href="http://code.google.com/p/crack-language/">Crack</a> aims to provide +the ease of development of a scripting language with the performance of a +compiled language. The language derives concepts from C++, Java and Python, +incorporating object-oriented programming, operator overloading and strong +typing.</p> +</div> + + +<!--=========================================================================--> +<div class="www_subsection"> <a name="rubinius">Rubinius</a><br> </div> <!--=========================================================================--> From grosbach at apple.com Wed Sep 1 19:51:37 2010 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 02 Sep 2010 00:51:37 -0000 Subject: [llvm-commits] [llvm] r112787 - /llvm/trunk/lib/CodeGen/RegisterScavenging.cpp Message-ID: <20100902005137.8C19A2A6C12C@llvm.org> Author: grosbach Date: Wed Sep 1 19:51:37 2010 New Revision: 112787 URL: http://llvm.org/viewvc/llvm-project?rev=112787&view=rev Log: Add a bit of debug output for register scavenging Modified: llvm/trunk/lib/CodeGen/RegisterScavenging.cpp Modified: llvm/trunk/lib/CodeGen/RegisterScavenging.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterScavenging.cpp?rev=112787&r1=112786&r2=112787&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegisterScavenging.cpp (original) +++ llvm/trunk/lib/CodeGen/RegisterScavenging.cpp Wed Sep 1 19:51:37 2010 @@ -21,7 +21,9 @@ #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" @@ -237,8 +239,11 @@ unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const { for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I != E; ++I) - if (!isAliasUsed(*I)) + if (!isAliasUsed(*I)) { + DEBUG(dbgs() << "Scavenger found unused reg: " << TRI->getName(*I) << + "\n"); return *I; + } return 0; } @@ -349,8 +354,10 @@ unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI); // If we found an unused register there is no reason to spill it. - if (!isAliasUsed(SReg)) + if (!isAliasUsed(SReg)) { + DEBUG(dbgs() << "Scavenged register: " << TRI->getName(SReg) << "\n"); return SReg; + } assert(ScavengedReg == 0 && "Scavenger slot is live, unable to scavenge another register!"); @@ -380,5 +387,8 @@ // ScavengedReg = SReg; ScavengedRC = RC; + DEBUG(dbgs() << "Scavenged register (with spill): " << TRI->getName(SReg) << + "\n"); + return SReg; } From echristo at apple.com Wed Sep 1 19:53:56 2010 From: echristo at apple.com (Eric Christopher) Date: Thu, 02 Sep 2010 00:53:56 -0000 Subject: [llvm-commits] [llvm] r112788 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20100902005357.092972A6C12C@llvm.org> Author: echristo Date: Wed Sep 1 19:53:56 2010 New Revision: 112788 URL: http://llvm.org/viewvc/llvm-project?rev=112788&view=rev Log: Rework arm fast-isel load and store handling. Move offset computation into the "address selection" routine and handle constant materialization for stores. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=112788&r1=112787&r2=112788&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Wed Sep 1 19:53:56 2010 @@ -113,9 +113,11 @@ bool isTypeLegal(const Type *Ty, EVT &VT); bool isLoadTypeLegal(const Type *Ty, EVT &VT); bool ARMEmitLoad(EVT VT, unsigned &ResultReg, unsigned Reg, int Offset); + bool ARMEmitStore(EVT VT, unsigned SrcReg, unsigned Reg, int Offset); bool ARMLoadAlloca(const Instruction *I); - bool ARMStoreAlloca(const Instruction *I); + bool ARMStoreAlloca(const Instruction *I, unsigned SrcReg); bool ARMComputeRegOffset(const Value *Obj, unsigned &Reg, int &Offset); + bool ARMMaterializeConstant(const ConstantInt *Val, unsigned &Reg); bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR); const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB); @@ -381,7 +383,31 @@ // Try to get this in a register if nothing else has worked. Reg = getRegForValue(Obj); - return Reg != 0; + if (Reg == 0) return false; + + // Since the offset may be too large for the load instruction + // get the reg+offset into a register. + // TODO: Verify the additions work, otherwise we'll need to add the + // offset instead of 0 to the instructions and do all sorts of operand + // munging. + // TODO: Optimize this somewhat. + if (Offset != 0) { + ARMCC::CondCodes Pred = ARMCC::AL; + unsigned PredReg = 0; + + if (!AFI->isThumbFunction()) + emitARMRegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL, + Reg, Reg, Offset, Pred, PredReg, + static_cast<const ARMBaseInstrInfo&>(TII)); + else { + assert(AFI->isThumb2Function()); + emitT2RegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL, + Reg, Reg, Offset, Pred, PredReg, + static_cast<const ARMBaseInstrInfo&>(TII)); + } + } + + return true; } bool ARMFastISel::ARMLoadAlloca(const Instruction *I) { @@ -446,7 +472,31 @@ return true; } -bool ARMFastISel::ARMStoreAlloca(const Instruction *I) { +bool ARMFastISel::ARMMaterializeConstant(const ConstantInt *CI, unsigned &Reg) { + unsigned Opc; + bool Signed = true; + bool isThumb = AFI->isThumbFunction(); + EVT VT = TLI.getValueType(CI->getType(), true); + + switch (VT.getSimpleVT().SimpleTy) { + default: return false; + case MVT::i1: Signed = false; // FALLTHROUGH to handle as i8. + case MVT::i8: + case MVT::i16: + case MVT::i32: + Opc = isThumb ? ARM::t2MOVi32imm : ARM::MOVi32imm; break; + } + + Reg = createResultReg(TLI.getRegClassFor(VT)); + AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), + Reg) + .addImm(Signed ? (uint64_t) CI->getSExtValue() : + CI->getZExtValue())); + + return true; +} + +bool ARMFastISel::ARMStoreAlloca(const Instruction *I, unsigned SrcReg) { Value *Op1 = I->getOperand(1); // Verify it's an alloca. @@ -456,11 +506,9 @@ if (SI != FuncInfo.StaticAllocaMap.end()) { TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy()); - unsigned Reg = getRegForValue(I->getOperand(0)); - // Make sure we can get this into a register. - if (Reg == 0) return false; + assert(SrcReg != 0 && "Nothing to store!"); TII.storeRegToStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt, - Reg, true /*isKill*/, SI->second, RC, + SrcReg, true /*isKill*/, SI->second, RC, TM.getRegisterInfo()); return true; } @@ -468,17 +516,73 @@ return false; } +bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, + unsigned DstReg, int Offset) { + bool isThumb = AFI->isThumbFunction(); + + unsigned StrOpc; + switch (VT.getSimpleVT().SimpleTy) { + default: return false; + case MVT::i1: + case MVT::i8: StrOpc = isThumb ? ARM::tSTRB : ARM::STRB; break; + case MVT::i16: StrOpc = isThumb ? ARM::tSTRH : ARM::STRH; break; + case MVT::i32: StrOpc = isThumb ? ARM::tSTR : ARM::STR; break; + } + + if (isThumb) + AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, + TII.get(StrOpc), SrcReg) + .addReg(DstReg).addImm(Offset).addReg(0)); + else + AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, + TII.get(StrOpc), SrcReg) + .addReg(DstReg).addReg(0).addImm(Offset)); + + return true; +} + bool ARMFastISel::ARMSelectStore(const Instruction *I) { + Value *Op0 = I->getOperand(0); + unsigned SrcReg = 0; + + // Yay type legalization + EVT VT; + if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT)) + return false; + + // First see if we're a constant that we want to store, we'll need to + // materialize that into a register. + // Handle 'null' like i32/i64 0. + if (isa<ConstantPointerNull>(Op0)) + Op0 = Constant::getNullValue(TD.getIntPtrType(Op0->getContext())); + + // If this is a store of a simple constant, materialize the constant into + // a register then emit the store into the location. + if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op0)) + if (!ARMMaterializeConstant(CI, SrcReg)) + return false; + + // If Reg is still 0, try to get the value into a register. + if (SrcReg == 0) + SrcReg = getRegForValue(Op0); + if (SrcReg == 0) + return false; + // If we're an alloca we know we have a frame index and can emit the store // quickly. - if (ARMStoreAlloca(I)) + if (ARMStoreAlloca(I, SrcReg)) return true; - // Yay type legalization - EVT VT; - if (!isLoadTypeLegal(I->getType(), VT)) + // Our register and offset with innocuous defaults. + unsigned Reg = 0; + int Offset = 0; + + // See if we can handle this as Reg + Offset + if (!ARMComputeRegOffset(I->getOperand(1), Reg, Offset)) return false; + if (!ARMEmitStore(VT, SrcReg, Reg, Offset /* 0 */)) return false; + return false; } @@ -501,28 +605,9 @@ // See if we can handle this as Reg + Offset if (!ARMComputeRegOffset(I->getOperand(0), Reg, Offset)) return false; - - // Since the offset may be too large for the load instruction - // get the reg+offset into a register. - // TODO: Optimize this somewhat. - ARMCC::CondCodes Pred = ARMCC::AL; - unsigned PredReg = 0; - - if (!AFI->isThumbFunction()) - emitARMRegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL, - Reg, Reg, Offset, Pred, PredReg, - static_cast<const ARMBaseInstrInfo&>(TII)); - else { - assert(AFI->isThumb2Function()); - emitT2RegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL, - Reg, Reg, Offset, Pred, PredReg, - static_cast<const ARMBaseInstrInfo&>(TII)); - } unsigned ResultReg; - // TODO: Verify the additions above work, otherwise we'll need to add the - // offset instead of 0 and do all sorts of operand munging. - if (!ARMEmitLoad(VT, ResultReg, Reg, 0)) return false; + if (!ARMEmitLoad(VT, ResultReg, Reg, Offset /* 0 */)) return false; UpdateValueMap(I, ResultReg); return true; From grosbach at apple.com Wed Sep 1 20:02:07 2010 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 02 Sep 2010 01:02:07 -0000 Subject: [llvm-commits] [llvm] r112790 - /llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Message-ID: <20100902010207.234F72A6C12C@llvm.org> Author: grosbach Date: Wed Sep 1 20:02:06 2010 New Revision: 112790 URL: http://llvm.org/viewvc/llvm-project?rev=112790&view=rev Log: Remove trailing whitespace Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=112790&r1=112789&r2=112790&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Wed Sep 1 20:02:06 2010 @@ -90,9 +90,9 @@ virtual const char *getPassName() const { return "ARM Assembly Printer"; } - + void printInstructionThroughMCStreamer(const MachineInstr *MI); - + void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O, const char *Modifier = 0); @@ -204,7 +204,7 @@ virtual void EmitInstruction(const MachineInstr *MI); bool runOnMachineFunction(MachineFunction &F); - + virtual void EmitConstantPool() {} // we emit constant pools customly! virtual void EmitFunctionEntryLabel(); void EmitStartOfAsmFile(Module &M); @@ -242,7 +242,7 @@ EmitMachineConstantPoolValue(MCPV, OS); OutStreamer.EmitRawText(OS.str()); } - + void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV, raw_ostream &O) { switch (TM.getTargetData()->getTypeAllocSize(MCPV->getType())) { @@ -268,7 +268,7 @@ // FIXME: Remove this when Darwin transition to @GOT like syntax. MCSymbol *Sym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr"); O << *Sym; - + MachineModuleInfoMachO &MMIMachO = MMI->getObjFileInfo<MachineModuleInfoMachO>(); MachineModuleInfoImpl::StubValueTy &StubSym = @@ -312,7 +312,7 @@ OutStreamer.EmitRawText(OS.str()); } } - + OutStreamer.EmitLabel(CurrentFnSym); } @@ -392,7 +392,7 @@ case MachineOperand::MO_ExternalSymbol: { bool isCallOp = Modifier && !strcmp(Modifier, "call"); O << *GetExternalSymbolSymbol(MO.getSymbolName()); - + if (isCallOp && Subtarget->isTargetELF() && TM.getRelocationModel() == Reloc::PIC_) O << "(PLT)"; @@ -963,7 +963,7 @@ const MachineOperand &MO1 = MI->getOperand(OpNum); const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id - + unsigned JTI = MO1.getIndex(); MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm()); // Can't use EmitLabel until instprinter happens, label comes out in the wrong @@ -1005,9 +1005,9 @@ const MachineOperand &MO1 = MI->getOperand(OpNum); const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id unsigned JTI = MO1.getIndex(); - + MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm()); - + // Can't use EmitLabel until instprinter happens, label comes out in the wrong // order. O << "\n" << *JTISymbol << ":\n"; @@ -1027,7 +1027,7 @@ O << MAI->getData8bitsDirective(); else if (HalfWordOffset) O << MAI->getData16bitsDirective(); - + if (ByteOffset || HalfWordOffset) O << '(' << *MBB->getSymbol() << "-" << *JTISymbol << ")/2"; else @@ -1133,10 +1133,10 @@ printInstructionThroughMCStreamer(MI); return; } - + if (MI->getOpcode() == ARM::CONSTPOOL_ENTRY) EmitAlignment(2); - + SmallString<128> Str; raw_svector_ostream OS(Str); if (MI->getOpcode() == ARM::DBG_VALUE) { @@ -1159,7 +1159,7 @@ printInstruction(MI, OS); OutStreamer.EmitRawText(OS.str()); - + // Make sure the instruction that follows TBB is 2-byte aligned. // FIXME: Constant island pass should insert an "ALIGN" instruction instead. if (MI->getOpcode() == ARM::t2TBB) @@ -1176,7 +1176,7 @@ // avoid out-of-range branches that are due a fundamental limitation of // the way symbol offsets are encoded with the current Darwin ARM // relocations. - const TargetLoweringObjectFileMachO &TLOFMacho = + const TargetLoweringObjectFileMachO &TLOFMacho = static_cast<const TargetLoweringObjectFileMachO &>( getObjFileLowering()); OutStreamer.SwitchSection(TLOFMacho.getTextSection()); @@ -1226,7 +1226,7 @@ OutStreamer.EmitRawText("\t.eabi_attribute " + Twine(ARMBuildAttrs::ABI_FP_exceptions) + ", 1"); } - + if (NoInfsFPMath && NoNaNsFPMath) OutStreamer.EmitRawText("\t.eabi_attribute " + Twine(ARMBuildAttrs::ABI_FP_number_model)+ ", 1"); @@ -1333,7 +1333,7 @@ // LPC0: // add r0, pc, r0 // This adds the address of LPC0 to r0. - + // Emit the label. // FIXME: MOVE TO SHARED PLACE. unsigned Id = (unsigned)MI->getOperand(2).getImm(); @@ -1341,8 +1341,8 @@ MCSymbol *Label =OutContext.GetOrCreateSymbol(Twine(Prefix) + "PC" + Twine(getFunctionNumber()) + "_" + Twine(Id)); OutStreamer.EmitLabel(Label); - - + + // Form and emit tha dd. MCInst AddInst; AddInst.setOpcode(ARM::ADDrr); @@ -1368,7 +1368,7 @@ EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal); else EmitGlobalConstant(MCPE.Val.ConstVal); - + return; } case ARM::MOVi2pieces: { // FIXME: Remove asmstring from td file. @@ -1378,13 +1378,13 @@ unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal); unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal); - + { MCInst TmpInst; TmpInst.setOpcode(ARM::MOVi); TmpInst.addOperand(MCOperand::CreateReg(DstReg)); TmpInst.addOperand(MCOperand::CreateImm(SOImmValV1)); - + // Predicate. TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm())); TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg())); @@ -1402,11 +1402,11 @@ // Predicate. TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm())); TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg())); - + TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out OutStreamer.EmitInstruction(TmpInst); } - return; + return; } case ARM::MOVi32imm: { // FIXME: Remove asmstring from td file. // This is a hack that lowers as a two instruction sequence. @@ -1437,32 +1437,32 @@ TmpInst.setOpcode(ARM::MOVi16); TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg TmpInst.addOperand(V1); // lower16(imm) - + // Predicate. TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm())); TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg())); - + OutStreamer.EmitInstruction(TmpInst); } - + { MCInst TmpInst; TmpInst.setOpcode(ARM::MOVTi16); TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // srcreg TmpInst.addOperand(V2); // upper16(imm) - + // Predicate. TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm())); TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg())); - + OutStreamer.EmitInstruction(TmpInst); } - + return; } } - + MCInst TmpInst; MCInstLowering.Lower(MI, TmpInst); OutStreamer.EmitInstruction(TmpInst); From echristo at apple.com Wed Sep 1 20:39:14 2010 From: echristo at apple.com (Eric Christopher) Date: Thu, 02 Sep 2010 01:39:14 -0000 Subject: [llvm-commits] [llvm] r112793 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20100902013914.8C4392A6C12C@llvm.org> Author: echristo Date: Wed Sep 1 20:39:14 2010 New Revision: 112793 URL: http://llvm.org/viewvc/llvm-project?rev=112793&view=rev Log: One definition of isThumb is plenty, thanks. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=112793&r1=112792&r2=112793&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Wed Sep 1 20:39:14 2010 @@ -59,6 +59,9 @@ const TargetLowering &TLI; const ARMFunctionInfo *AFI; + // Convenience variable to avoid checking all the time. + bool isThumb; + public: explicit ARMFastISel(FunctionLoweringInfo &funcInfo) : FastISel(funcInfo), @@ -67,6 +70,7 @@ TLI(*TM.getTargetLowering()) { Subtarget = &TM.getSubtarget<ARMSubtarget>(); AFI = funcInfo.MF->getInfo<ARMFunctionInfo>(); + isThumb = AFI->isThumbFunction(); } // Code from FastISel.cpp. @@ -395,7 +399,7 @@ ARMCC::CondCodes Pred = ARMCC::AL; unsigned PredReg = 0; - if (!AFI->isThumbFunction()) + if (!isThumb) emitARMRegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL, Reg, Reg, Offset, Pred, PredReg, static_cast<const ARMBaseInstrInfo&>(TII)); @@ -435,8 +439,6 @@ unsigned Reg, int Offset) { assert(VT.isSimple() && "Non-simple types are invalid here!"); - - bool isThumb = AFI->isThumbFunction(); unsigned Opc; switch (VT.getSimpleVT().SimpleTy) { @@ -475,7 +477,6 @@ bool ARMFastISel::ARMMaterializeConstant(const ConstantInt *CI, unsigned &Reg) { unsigned Opc; bool Signed = true; - bool isThumb = AFI->isThumbFunction(); EVT VT = TLI.getValueType(CI->getType(), true); switch (VT.getSimpleVT().SimpleTy) { @@ -518,8 +519,6 @@ bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, unsigned DstReg, int Offset) { - bool isThumb = AFI->isThumbFunction(); - unsigned StrOpc; switch (VT.getSimpleVT().SimpleTy) { default: return false; @@ -615,7 +614,7 @@ bool ARMFastISel::TargetSelectInstruction(const Instruction *I) { // No Thumb-1 for now. - if (AFI->isThumbFunction() && !AFI->isThumb2Function()) return false; + if (isThumb && !AFI->isThumb2Function()) return false; switch (I->getOpcode()) { case Instruction::Load: From echristo at apple.com Wed Sep 1 20:48:11 2010 From: echristo at apple.com (Eric Christopher) Date: Thu, 02 Sep 2010 01:48:11 -0000 Subject: [llvm-commits] [llvm] r112795 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20100902014811.5F8072A6C12C@llvm.org> Author: echristo Date: Wed Sep 1 20:48:11 2010 New Revision: 112795 URL: http://llvm.org/viewvc/llvm-project?rev=112795&view=rev Log: This should be TargetMaterializeConstant instead. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=112795&r1=112794&r2=112795&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Wed Sep 1 20:48:11 2010 @@ -105,6 +105,7 @@ // Backend specific FastISel code. virtual bool TargetSelectInstruction(const Instruction *I); + virtual unsigned TargetMaterializeConstant(const Constant *C); #include "ARMGenFastISel.inc" @@ -321,6 +322,31 @@ return ResultReg; } +unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) { + const ConstantInt *CI = dyn_cast<ConstantInt>(C); + if (!CI) return 0; + + unsigned Opc; + bool Signed = true; + EVT VT = TLI.getValueType(CI->getType(), true); + + switch (VT.getSimpleVT().SimpleTy) { + default: return 0; + case MVT::i1: Signed = false; // FALLTHROUGH to handle as i8. + case MVT::i8: + case MVT::i16: + case MVT::i32: + Opc = isThumb ? ARM::t2MOVi32imm : ARM::MOVi32imm; break; + } + + unsigned Reg = createResultReg(TLI.getRegClassFor(VT)); + AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), + Reg) + .addImm(Signed ? (uint64_t) CI->getSExtValue() : + CI->getZExtValue())); + return Reg; +} + bool ARMFastISel::isTypeLegal(const Type *Ty, EVT &VT) { VT = TLI.getValueType(Ty, true); @@ -474,29 +500,6 @@ return true; } -bool ARMFastISel::ARMMaterializeConstant(const ConstantInt *CI, unsigned &Reg) { - unsigned Opc; - bool Signed = true; - EVT VT = TLI.getValueType(CI->getType(), true); - - switch (VT.getSimpleVT().SimpleTy) { - default: return false; - case MVT::i1: Signed = false; // FALLTHROUGH to handle as i8. - case MVT::i8: - case MVT::i16: - case MVT::i32: - Opc = isThumb ? ARM::t2MOVi32imm : ARM::MOVi32imm; break; - } - - Reg = createResultReg(TLI.getRegClassFor(VT)); - AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), - Reg) - .addImm(Signed ? (uint64_t) CI->getSExtValue() : - CI->getZExtValue())); - - return true; -} - bool ARMFastISel::ARMStoreAlloca(const Instruction *I, unsigned SrcReg) { Value *Op1 = I->getOperand(1); @@ -548,22 +551,9 @@ EVT VT; if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT)) return false; - - // First see if we're a constant that we want to store, we'll need to - // materialize that into a register. - // Handle 'null' like i32/i64 0. - if (isa<ConstantPointerNull>(Op0)) - Op0 = Constant::getNullValue(TD.getIntPtrType(Op0->getContext())); - - // If this is a store of a simple constant, materialize the constant into - // a register then emit the store into the location. - if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op0)) - if (!ARMMaterializeConstant(CI, SrcReg)) - return false; - // If Reg is still 0, try to get the value into a register. - if (SrcReg == 0) - SrcReg = getRegForValue(Op0); + // Get the value to be stored into a register. + SrcReg = getRegForValue(Op0); if (SrcReg == 0) return false; From echristo at apple.com Wed Sep 1 21:30:46 2010 From: echristo at apple.com (Eric Christopher) Date: Thu, 02 Sep 2010 02:30:46 -0000 Subject: [llvm-commits] [llvm] r112798 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20100902023046.8C4DC2A6C12C@llvm.org> Author: echristo Date: Wed Sep 1 21:30:46 2010 New Revision: 112798 URL: http://llvm.org/viewvc/llvm-project?rev=112798&view=rev Log: Clang's -ccc-host-triple was ignoring the arch specifier on my triple, I don't need to implement this quite yet - and not for ConstantInt anyhow. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=112798&r1=112797&r2=112798&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Wed Sep 1 21:30:46 2010 @@ -323,28 +323,9 @@ } unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) { - const ConstantInt *CI = dyn_cast<ConstantInt>(C); - if (!CI) return 0; - - unsigned Opc; - bool Signed = true; - EVT VT = TLI.getValueType(CI->getType(), true); - - switch (VT.getSimpleVT().SimpleTy) { - default: return 0; - case MVT::i1: Signed = false; // FALLTHROUGH to handle as i8. - case MVT::i8: - case MVT::i16: - case MVT::i32: - Opc = isThumb ? ARM::t2MOVi32imm : ARM::MOVi32imm; break; - } - - unsigned Reg = createResultReg(TLI.getRegClassFor(VT)); - AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), - Reg) - .addImm(Signed ? (uint64_t) CI->getSExtValue() : - CI->getZExtValue())); - return Reg; + // TODO: Implement this for floating point constants and integer constants + // if we care about non-v6 architectures. + return 0; } bool ARMFastISel::isTypeLegal(const Type *Ty, EVT &VT) { From bruno.cardoso at gmail.com Wed Sep 1 21:35:52 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Thu, 02 Sep 2010 02:35:52 -0000 Subject: [llvm-commits] [llvm] r112799 - in /llvm/trunk/lib/Target/X86: X86ISelLowering.cpp X86InstrSSE.td Message-ID: <20100902023552.390CD2A6C12C@llvm.org> Author: bruno Date: Wed Sep 1 21:35:51 2010 New Revision: 112799 URL: http://llvm.org/viewvc/llvm-project?rev=112799&view=rev Log: become more strict about when it's safe to use X86ISD::MOVLPS Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=112799&r1=112798&r2=112799&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Sep 1 21:35:51 2010 @@ -5082,10 +5082,10 @@ SDValue TmpV1 = V1; SDValue TmpV2 = V2; - // Trivial case, when V2 is a load. - if (TmpV2.getOpcode() == ISD::BIT_CONVERT) + // Trivial case, when V2 comes from a load. + if (TmpV2.hasOneUse() && TmpV2.getOpcode() == ISD::BIT_CONVERT) TmpV2 = TmpV2.getOperand(0); - if (TmpV2.getOpcode() == ISD::SCALAR_TO_VECTOR) + if (TmpV2.hasOneUse() && TmpV2.getOpcode() == ISD::SCALAR_TO_VECTOR) TmpV2 = TmpV2.getOperand(0); if (MayFoldLoad(TmpV2)) CanFoldLoad = true; @@ -5095,9 +5095,9 @@ // turns into: // (MOVLPSmr addr:$src1, VR128:$src2) // So, recognize this potential and also use MOVLPS or MOVLPD - if (TmpV1.getOpcode() == ISD::BIT_CONVERT) + if (TmpV1.hasOneUse() && TmpV1.getOpcode() == ISD::BIT_CONVERT) TmpV1 = TmpV1.getOperand(0); - if (MayFoldLoad(TmpV1)) + if (MayFoldLoad(TmpV1) && MayFoldIntoStore(Op)) CanFoldLoad = true; if (CanFoldLoad) { Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=112799&r1=112798&r2=112799&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Sep 1 21:35:51 2010 @@ -5829,6 +5829,13 @@ def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)), (MOVSSrr (v4f32 VR128:$src1), (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>; +// FIXME: Instead of a X86Movss there should be a X86Movlps here, the problem +// is during lowering, where it's not possible to recognize the load fold cause +// it has two uses through a bitcast. One use disappears at isel time and the +// fold opportunity reappears. +def : Pat<(X86Movss VR128:$src1, + (bc_v4i32 (v2i64 (load addr:$src2)))), + (MOVLPSrm VR128:$src1, addr:$src2)>; // Shuffle with MOVSD def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))), @@ -5909,9 +5916,6 @@ def : Pat<(X86Movlps VR128:$src1, (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))), (MOVLPSrm VR128:$src1, addr:$src2)>; -def : Pat<(X86Movlps VR128:$src1, - (bc_v4i32 (v2i64 (load addr:$src2)))), - (MOVLPSrm VR128:$src1, addr:$src2)>; // Shuffle with MOVLPD def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))), From geek4civic at gmail.com Wed Sep 1 22:45:52 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Thu, 02 Sep 2010 03:45:52 -0000 Subject: [llvm-commits] [llvm] r112801 - /llvm/trunk/test/CodeGen/X86/twoaddr-coalesce.ll Message-ID: <20100902034552.0ACD32A6C12C@llvm.org> Author: chapuni Date: Wed Sep 1 22:45:51 2010 New Revision: 112801 URL: http://llvm.org/viewvc/llvm-project?rev=112801&view=rev Log: test/twoaddr-coalesce: Do not use @main. Win32 codegen emits implicit invoking __main into, to fail. Modified: llvm/trunk/test/CodeGen/X86/twoaddr-coalesce.ll Modified: llvm/trunk/test/CodeGen/X86/twoaddr-coalesce.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/twoaddr-coalesce.ll?rev=112801&r1=112800&r2=112801&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/twoaddr-coalesce.ll (original) +++ llvm/trunk/test/CodeGen/X86/twoaddr-coalesce.ll Wed Sep 1 22:45:51 2010 @@ -3,7 +3,7 @@ @"\01LC" = internal constant [4 x i8] c"%d\0A\00" ; <[4 x i8]*> [#uses=1] -define i32 @main() nounwind { +define i32 @foo() nounwind { bb1.thread: br label %bb1 From geek4civic at gmail.com Wed Sep 1 22:45:58 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Thu, 02 Sep 2010 03:45:58 -0000 Subject: [llvm-commits] [llvm] r112802 - /llvm/trunk/test/CodeGen/X86/loop-strength-reduce4.ll Message-ID: <20100902034558.9EF6E2A6C12D@llvm.org> Author: chapuni Date: Wed Sep 1 22:45:58 2010 New Revision: 112802 URL: http://llvm.org/viewvc/llvm-project?rev=112802&view=rev Log: test/loop-strength-reduce4: Add explicit triplet for Win32 host. Modified: llvm/trunk/test/CodeGen/X86/loop-strength-reduce4.ll Modified: llvm/trunk/test/CodeGen/X86/loop-strength-reduce4.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/loop-strength-reduce4.ll?rev=112802&r1=112801&r2=112802&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/loop-strength-reduce4.ll (original) +++ llvm/trunk/test/CodeGen/X86/loop-strength-reduce4.ll Wed Sep 1 22:45:58 2010 @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=x86 -relocation-model=static -mtriple=i686-apple-darwin | FileCheck %s -check-prefix=STATIC -; RUN: llc < %s -march=x86 -relocation-model=pic | FileCheck %s -check-prefix=PIC +; RUN: llc < %s -mtriple=i686-apple-darwin -relocation-model=static | FileCheck %s -check-prefix=STATIC +; RUN: llc < %s -mtriple=i686-apple-darwin -relocation-model=pic | FileCheck %s -check-prefix=PIC ; By starting the IV at -64 instead of 0, a cmp is eliminated, ; as the flags from the add can be used directly. From geek4civic at gmail.com Wed Sep 1 22:46:04 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Thu, 02 Sep 2010 03:46:04 -0000 Subject: [llvm-commits] [llvm] r112803 - /llvm/trunk/lib/Support/SystemUtils.cpp Message-ID: <20100902034604.74E4E2A6C12C@llvm.org> Author: chapuni Date: Wed Sep 1 22:46:04 2010 New Revision: 112803 URL: http://llvm.org/viewvc/llvm-project?rev=112803&view=rev Log: llvm::FindExecutable(): Retrieve the name with suffix.exe, if available. bugpoint uses it. Modified: llvm/trunk/lib/Support/SystemUtils.cpp Modified: llvm/trunk/lib/Support/SystemUtils.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/SystemUtils.cpp?rev=112803&r1=112802&r2=112803&view=diff ============================================================================== --- llvm/trunk/lib/Support/SystemUtils.cpp (original) +++ llvm/trunk/lib/Support/SystemUtils.cpp Wed Sep 1 22:46:04 2010 @@ -49,6 +49,10 @@ Result.appendComponent(ExeName); if (Result.canExecute()) return Result; + // Expect to retrieve the pathname with suffix .exe. + Result = sys::Program::FindProgramByName(Result.str()); + if (!Result.empty()) + return Result; } return sys::Path(); From geek4civic at gmail.com Wed Sep 1 22:48:36 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Thu, 2 Sep 2010 12:48:36 +0900 Subject: [llvm-commits] [PATCH] Bugpoint/Support: Fix llvm::FindExecutable not looking for files ending with .exe In-Reply-To: <3D2BD0D9-026E-4147-9E99-0F56FCB83E28@apple.com> References: <AANLkTim8d2gyytoiWkjd9otSG8dYvNqYc-EShtFCggms@mail.gmail.com> <4CAB5B77-B4EB-4E91-B861-D9DE27867AE7@apple.com> <AANLkTim7nnkqgtFk8hwaEzDbe_0g62NvOFK8r6b0zcdQ@mail.gmail.com> <AANLkTineuN6hA_5V=xEy8--OmzRFQdsEuf8tBR0zud93@mail.gmail.com> <AANLkTimt-gX0a2CYUZrHH7DwAA2-yBL-v-zK29dN+bhK@mail.gmail.com> <3D2BD0D9-026E-4147-9E99-0F56FCB83E28@apple.com> Message-ID: <AANLkTinY-=L=MFMN0jr4KaNrV+dHcp6vpfhWaJmCz60N@mail.gmail.com> Commited in r112803...Takumi 2010/9/2 Chris Lattner <clattner at apple.com>: > Looks good to me, please commit! > > On Aug 31, 2010, at 2:05 PM, NAKAMURA Takumi wrote: > >> Michael, >> >> An refined patch is attached. Please take a look. >> Confirmed on mingw, mingw-cross, f12 and centos5. >> >> ?- get rid of extra sys::Path variable FoundPath >> ?- suppose value of FindProgramByName() must be valid when it is not empty >> >> >> ...Takumi >> <r81568-2-FindExecutable-retrieve-exe.diff.txt> > > From geek4civic at gmail.com Wed Sep 1 22:54:28 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Thu, 2 Sep 2010 12:54:28 +0900 Subject: [llvm-commits] [PATCH] test/CodeGen/X86 patches for win32 In-Reply-To: <0C45983F-0D48-4990-8170-1E69E7CB2D41@apple.com> References: <AANLkTikXM+t=fPa0g5-qyfLm80OYPF_hNnWxmFBeaVCJ@mail.gmail.com> <0C45983F-0D48-4990-8170-1E69E7CB2D41@apple.com> Message-ID: <AANLkTinyHisOgj7xfMDzjgod+5_Sk2b9ObqgEdWU1Dmr@mail.gmail.com> Committed in r112801 and r112802 partially. (w/o XFAIL) Anton told me on the IRC, sometimes it would be not good idea to mark XFAIL to CodeGen tests. I will wait for Anton's comment, please. Thank you, ...Takumi 2010/9/2 Chris Lattner <clattner at apple.com>: > Looks good to me, please commit! > > On Aug 31, 2010, at 3:00 PM, NAKAMURA Takumi wrote: > >> Good morning. >> >> This patch is set of tweaks for win32 to test/CodeGen/X86 >> Some issues are on win32. >> >> ?- EH is disabled by default. >> ?- @main() with extra calling __main. >> ?- stack allocatoin >> >> In fact, all tests in CodeGen/X86 pass on Cygwin, >> but I am not sure my patch would be reasonable. >> Please review it. >> >> >> ...Takumi >> <test-CodeGen-win32.diff.txt>_______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > From bruno.cardoso at gmail.com Wed Sep 1 22:57:58 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Thu, 02 Sep 2010 03:57:58 -0000 Subject: [llvm-commits] [llvm] r112804 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20100902035758.84EBB2A6C12C@llvm.org> Author: bruno Date: Wed Sep 1 22:57:58 2010 New Revision: 112804 URL: http://llvm.org/viewvc/llvm-project?rev=112804&view=rev Log: Remove checking for isUNPCKL_v_undef_Mask, the specific node is already emitted for it Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=112804&r1=112803&r2=112804&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Sep 1 22:57:58 2010 @@ -5290,8 +5290,7 @@ return getMOVL(DAG, dl, VT, V2, V1); } - if (X86::isUNPCKL_v_undef_Mask(SVOp) || - X86::isUNPCKH_v_undef_Mask(SVOp) || + if (X86::isUNPCKH_v_undef_Mask(SVOp) || X86::isUNPCKLMask(SVOp) || X86::isUNPCKHMask(SVOp)) return Op; @@ -5316,8 +5315,7 @@ // FIXME: this seems wrong. SDValue NewOp = CommuteVectorShuffle(SVOp, DAG); ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp); - if (X86::isUNPCKL_v_undef_Mask(NewSVOp) || - X86::isUNPCKH_v_undef_Mask(NewSVOp) || + if (X86::isUNPCKH_v_undef_Mask(NewSVOp) || X86::isUNPCKLMask(NewSVOp) || X86::isUNPCKHMask(NewSVOp)) return NewOp; From anton at korobeynikov.info Wed Sep 1 23:04:21 2010 From: anton at korobeynikov.info (Anton Korobeynikov) Date: Thu, 2 Sep 2010 08:04:21 +0400 Subject: [llvm-commits] [PATCH] test/CodeGen/X86 patches for win32 In-Reply-To: <AANLkTinyHisOgj7xfMDzjgod+5_Sk2b9ObqgEdWU1Dmr@mail.gmail.com> References: <AANLkTikXM+t=fPa0g5-qyfLm80OYPF_hNnWxmFBeaVCJ@mail.gmail.com> <0C45983F-0D48-4990-8170-1E69E7CB2D41@apple.com> <AANLkTinyHisOgj7xfMDzjgod+5_Sk2b9ObqgEdWU1Dmr@mail.gmail.com> Message-ID: <AANLkTinvAtnY=68abyFuxt6qAgAJU1CzYpRwbkM7XaFq@mail.gmail.com> > Anton told me on the IRC, > sometimes it would be not good idea to mark XFAIL to CodeGen tests. > I will wait for Anton's comment, please. As I said, please do not XFAIL the tests. Add explicit target triplets. Please fix the stuff for: test/CodeGen/X86/2009-03-13-PHIElimBug.ll test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll test/CodeGen/X86/dyn-stackalloc.ll Also, it's not obvious why you need to change test/CodeGen/X86/twoaddr-coalesce.ll -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From bruno.cardoso at gmail.com Wed Sep 1 23:20:26 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Thu, 02 Sep 2010 04:20:26 -0000 Subject: [llvm-commits] [llvm] r112805 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20100902042026.D6F112A6C12C@llvm.org> Author: bruno Date: Wed Sep 1 23:20:26 2010 New Revision: 112805 URL: http://llvm.org/viewvc/llvm-project?rev=112805&view=rev Log: Move condition out to prepare for more matching Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=112805&r1=112804&r2=112805&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Sep 1 23:20:26 2010 @@ -5181,6 +5181,11 @@ } } + if (OptForSize) { // NOTE: isPSHUFDMask can also match this mask... + if (HasSSE2 && X86::isUNPCKL_v_undef_Mask(SVOp) && VT == MVT::v4i32) + return getTargetShuffleNode(X86ISD::PUNPCKLDQ, dl, VT, V1, V1, DAG); + } + if (X86::isPSHUFDMask(SVOp)) { // The actual implementation will match the mask in the if above and then // during isel it can match several different instructions, not only pshufd @@ -5188,10 +5193,6 @@ if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64))) return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG); - if (OptForSize && HasSSE2 && X86::isUNPCKL_v_undef_Mask(SVOp) && - VT == MVT::v4i32) - return getTargetShuffleNode(X86ISD::PUNPCKLDQ, dl, VT, V1, V1, DAG); - unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp); if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32)) From bruno.cardoso at gmail.com Thu Sep 2 00:23:12 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Thu, 02 Sep 2010 05:23:12 -0000 Subject: [llvm-commits] [llvm] r112806 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20100902052312.C98992A6C12C@llvm.org> Author: bruno Date: Thu Sep 2 00:23:12 2010 New Revision: 112806 URL: http://llvm.org/viewvc/llvm-project?rev=112806&view=rev Log: Replace unpckl_undef and unpckh_undef matching with target specific opcodes Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=112806&r1=112805&r2=112806&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Sep 2 00:23:12 2010 @@ -2601,7 +2601,14 @@ case X86ISD::MOVSLDUP: case X86ISD::MOVSS: case X86ISD::MOVSD: + case X86ISD::UNPCKLPS: + case X86ISD::PUNPCKLWD: + case X86ISD::PUNPCKLBW: case X86ISD::PUNPCKLDQ: + case X86ISD::UNPCKHPS: + case X86ISD::PUNPCKHWD: + case X86ISD::PUNPCKHBW: + case X86ISD::PUNPCKHDQ: return true; } return false; @@ -2655,7 +2662,14 @@ case X86ISD::MOVLPD: case X86ISD::MOVSS: case X86ISD::MOVSD: + case X86ISD::UNPCKLPS: + case X86ISD::PUNPCKLWD: + case X86ISD::PUNPCKLBW: case X86ISD::PUNPCKLDQ: + case X86ISD::UNPCKHPS: + case X86ISD::PUNPCKHWD: + case X86ISD::PUNPCKHBW: + case X86ISD::PUNPCKHDQ: return DAG.getNode(Opc, dl, VT, V1, V2); } return SDValue(); @@ -5181,11 +5195,32 @@ } } - if (OptForSize) { // NOTE: isPSHUFDMask can also match this mask... - if (HasSSE2 && X86::isUNPCKL_v_undef_Mask(SVOp) && VT == MVT::v4i32) + if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp)) { + // NOTE: isPSHUFDMask can also match this mask, if speed is more + // important than size here, this will be matched by pshufd + if (VT == MVT::v4f32) + return getTargetShuffleNode(X86ISD::UNPCKLPS, dl, VT, V1, V1, DAG); + if (HasSSE2 && VT == MVT::v16i8) + return getTargetShuffleNode(X86ISD::PUNPCKLBW, dl, VT, V1, V1, DAG); + if (HasSSE2 && VT == MVT::v8i16) + return getTargetShuffleNode(X86ISD::PUNPCKLWD, dl, VT, V1, V1, DAG); + if (HasSSE2 && VT == MVT::v4i32) return getTargetShuffleNode(X86ISD::PUNPCKLDQ, dl, VT, V1, V1, DAG); } + if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp)) { + // NOTE: isPSHUFDMask can also match this mask, if speed is more + // important than size here, this will be matched by pshufd + if (VT == MVT::v4f32) + return getTargetShuffleNode(X86ISD::UNPCKHPS, dl, VT, V1, V1, DAG); + if (HasSSE2 && VT == MVT::v16i8) + return getTargetShuffleNode(X86ISD::PUNPCKHBW, dl, VT, V1, V1, DAG); + if (HasSSE2 && VT == MVT::v8i16) + return getTargetShuffleNode(X86ISD::PUNPCKHWD, dl, VT, V1, V1, DAG); + if (HasSSE2 && VT == MVT::v4i32) + return getTargetShuffleNode(X86ISD::PUNPCKHDQ, dl, VT, V1, V1, DAG); + } + if (X86::isPSHUFDMask(SVOp)) { // The actual implementation will match the mask in the if above and then // during isel it can match several different instructions, not only pshufd @@ -5291,8 +5326,7 @@ return getMOVL(DAG, dl, VT, V2, V1); } - if (X86::isUNPCKH_v_undef_Mask(SVOp) || - X86::isUNPCKLMask(SVOp) || + if (X86::isUNPCKLMask(SVOp) || X86::isUNPCKHMask(SVOp)) return Op; @@ -5316,8 +5350,7 @@ // FIXME: this seems wrong. SDValue NewOp = CommuteVectorShuffle(SVOp, DAG); ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp); - if (X86::isUNPCKH_v_undef_Mask(NewSVOp) || - X86::isUNPCKLMask(NewSVOp) || + if (X86::isUNPCKLMask(NewSVOp) || X86::isUNPCKHMask(NewSVOp)) return NewOp; } From kuwerty at gmail.com Thu Sep 2 00:05:49 2010 From: kuwerty at gmail.com (Krister Wombell) Date: Thu, 2 Sep 2010 13:05:49 +0800 Subject: [llvm-commits] [PATCH] fix debug_ranges for ELF targets In-Reply-To: <AANLkTin8LAJAQtV8VFWBbX=-E51BDTDuKU=E5es-gKBW@mail.gmail.com> References: <AANLkTin8LAJAQtV8VFWBbX=-E51BDTDuKU=E5es-gKBW@mail.gmail.com> Message-ID: <AANLkTimeYVh0bxF2CpznS-P81ZJsLT0Qn=ZfA-uVLR-E@mail.gmail.com> As requested: new patch that uses an MAI query to implement either the previous behaviour on Darwin or the new expression structure for ELF. Krister On Thu, Aug 26, 2010 at 1:26 PM, Krister Wombell <kuwerty at gmail.com> wrote: > Some (all binutils?) based ELF assemblers treat expressions like: > > (.Ldebug_ranges + 48) - .Ldebug_ranges > > as a constant and won't emit a relocation. When the debug_ranges sections > are finally linked then DIE's that have a reference to an offset in the > debug_ranges section won't be correct (they'll all point to the first > compilation unit encountered by the linker). gdb doesn't like this. > > This form of expression is emitted by > AsmPrinter::EmitLabelOffsetDifference. It'd be difficult to encode this form > of expression in ELF and because the only caller of this function actually > called it with the same symbol for the Lo and Hi args it can be represented > as 'label + offset' instead. Replaced the entire function with something > called EmitLabelPlusOffset. > > Ran make in tests directory, no unexpected failures. > > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100902/d8f6d77f/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: debug_ranges.patch Type: text/x-patch Size: 5173 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100902/d8f6d77f/attachment.bin From lhames at gmail.com Thu Sep 2 00:37:52 2010 From: lhames at gmail.com (Lang Hames) Date: Thu, 02 Sep 2010 05:37:52 -0000 Subject: [llvm-commits] [llvm] r112807 - in /llvm/trunk/lib/CodeGen/PBQP: HeuristicBase.h HeuristicSolver.h Solution.h Message-ID: <20100902053752.DB87C2A6C12C@llvm.org> Author: lhames Date: Thu Sep 2 00:37:52 2010 New Revision: 112807 URL: http://llvm.org/viewvc/llvm-project?rev=112807&view=rev Log: Added counters for PBQP reduction rules. Modified: llvm/trunk/lib/CodeGen/PBQP/HeuristicBase.h llvm/trunk/lib/CodeGen/PBQP/HeuristicSolver.h llvm/trunk/lib/CodeGen/PBQP/Solution.h Modified: llvm/trunk/lib/CodeGen/PBQP/HeuristicBase.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PBQP/HeuristicBase.h?rev=112807&r1=112806&r2=112807&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PBQP/HeuristicBase.h (original) +++ llvm/trunk/lib/CodeGen/PBQP/HeuristicBase.h Thu Sep 2 00:37:52 2010 @@ -174,8 +174,11 @@ while (!finished) { if (!optimalReduce()) - if (!impl().heuristicReduce()) + if (impl().heuristicReduce()) { + getSolver().recordRN(); + } else { finished = true; + } } } Modified: llvm/trunk/lib/CodeGen/PBQP/HeuristicSolver.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PBQP/HeuristicSolver.h?rev=112807&r1=112806&r2=112807&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PBQP/HeuristicSolver.h (original) +++ llvm/trunk/lib/CodeGen/PBQP/HeuristicSolver.h Thu Sep 2 00:37:52 2010 @@ -226,6 +226,8 @@ // Nothing to do. Just push the node onto the reduction stack. pushToStack(nItr); + + s.recordR0(); } /// \brief Apply rule R1. @@ -274,6 +276,7 @@ assert(nd.getSolverDegree() == 0 && "Degree 1 with edge removed should be 0."); pushToStack(xnItr); + s.recordR1(); } /// \brief Apply rule R2. @@ -378,8 +381,14 @@ removeSolverEdge(zxeItr); pushToStack(xnItr); + s.recordR2(); } + /// \brief Record an application of the RN rule. + /// + /// For use by the HeuristicBase. + void recordRN() { s.recordRN(); } + private: NodeData& getSolverNodeData(Graph::NodeItr nItr) { Modified: llvm/trunk/lib/CodeGen/PBQP/Solution.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PBQP/Solution.h?rev=112807&r1=112806&r2=112807&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PBQP/Solution.h (original) +++ llvm/trunk/lib/CodeGen/PBQP/Solution.h Thu Sep 2 00:37:52 2010 @@ -26,15 +26,46 @@ /// To get the selection for each node in the problem use the getSelection method. class Solution { private: + typedef std::map<Graph::NodeItr, unsigned, NodeItrComparator> SelectionsMap; SelectionsMap selections; + unsigned r0Reductions, r1Reductions, r2Reductions, rNReductions; + public: /// \brief Number of nodes for which selections have been made. /// @return Number of nodes for which selections have been made. unsigned numNodes() const { return selections.size(); } + /// \brief Records a reduction via the R0 rule. Should be called from the + /// solver only. + void recordR0() { ++r0Reductions; } + + /// \brief Returns the number of R0 reductions applied to solve the problem. + unsigned numR0Reductions() const { return r0Reductions; } + + /// \brief Records a reduction via the R1 rule. Should be called from the + /// solver only. + void recordR1() { ++r1Reductions; } + + /// \brief Returns the number of R1 reductions applied to solve the problem. + unsigned numR1Reductions() const { return r1Reductions; } + + /// \brief Records a reduction via the R2 rule. Should be called from the + /// solver only. + void recordR2() { ++r2Reductions; } + + /// \brief Returns the number of R2 reductions applied to solve the problem. + unsigned numR2Reductions() const { return r2Reductions; } + + /// \brief Records a reduction via the RN rule. Should be called from the + /// solver only. + void recordRN() { ++ rNReductions; } + + /// \brief Returns the number of RN reductions applied to solve the problem. + unsigned numRNReductions() const { return rNReductions; } + /// \brief Set the selection for a given node. /// @param nItr Node iterator. /// @param selection Selection for nItr. From nicholas at mxc.ca Thu Sep 2 00:44:31 2010 From: nicholas at mxc.ca (Nick Lewycky) Date: Thu, 02 Sep 2010 05:44:31 -0000 Subject: [llvm-commits] [llvm] r112808 - /llvm/trunk/tools/gold/gold-plugin.cpp Message-ID: <20100902054431.42ED92A6C12C@llvm.org> Author: nicholas Date: Thu Sep 2 00:44:31 2010 New Revision: 112808 URL: http://llvm.org/viewvc/llvm-project?rev=112808&view=rev Log: Fix compile errors. Modified: llvm/trunk/tools/gold/gold-plugin.cpp Modified: llvm/trunk/tools/gold/gold-plugin.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/gold/gold-plugin.cpp?rev=112808&r1=112807&r2=112808&view=diff ============================================================================== --- llvm/trunk/tools/gold/gold-plugin.cpp (original) +++ llvm/trunk/tools/gold/gold-plugin.cpp Thu Sep 2 00:44:31 2010 @@ -460,12 +460,12 @@ return LDPS_ERR; } - objFile.write(buffer, bufsize); - objFile.close(); - if (objFile.has_error()) { + objFile.os().write(buffer, bufsize); + objFile.os().close(); + if (objFile.os().has_error()) { (*message)(LDPL_ERROR, "Error writing output file '%s'", uniqueObjPath.c_str()); - objFile.clear_error(); + objFile.os().clear_error(); return LDPS_ERR; } objFile.keep(); From chandlerc at gmail.com Thu Sep 2 02:08:06 2010 From: chandlerc at gmail.com (Chandler Carruth) Date: Thu, 02 Sep 2010 07:08:06 -0000 Subject: [llvm-commits] [llvm] r112809 - /llvm/trunk/lib/CodeGen/PBQP/HeuristicBase.h Message-ID: <20100902070806.0D5922A6C12C@llvm.org> Author: chandlerc Date: Thu Sep 2 02:08:05 2010 New Revision: 112809 URL: http://llvm.org/viewvc/llvm-project?rev=112809&view=rev Log: Silence an ambiguous else warning from GCC. Modified: llvm/trunk/lib/CodeGen/PBQP/HeuristicBase.h Modified: llvm/trunk/lib/CodeGen/PBQP/HeuristicBase.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PBQP/HeuristicBase.h?rev=112809&r1=112808&r2=112809&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PBQP/HeuristicBase.h (original) +++ llvm/trunk/lib/CodeGen/PBQP/HeuristicBase.h Thu Sep 2 02:08:05 2010 @@ -173,12 +173,13 @@ bool finished = false; while (!finished) { - if (!optimalReduce()) + if (!optimalReduce()) { if (impl().heuristicReduce()) { getSolver().recordRN(); } else { finished = true; } + } } } From lhames at gmail.com Thu Sep 2 02:39:56 2010 From: lhames at gmail.com (Lang Hames) Date: Thu, 2 Sep 2010 17:39:56 +1000 Subject: [llvm-commits] [llvm] r112809 - /llvm/trunk/lib/CodeGen/PBQP/HeuristicBase.h In-Reply-To: <20100902070806.0D5922A6C12C@llvm.org> References: <20100902070806.0D5922A6C12C@llvm.org> Message-ID: <AANLkTinf0eGHMnE5QGL+m1KS6k4ZroEEAywNxD3X9rp3@mail.gmail.com> Oops. Cheers for that! - Lang. On Thu, Sep 2, 2010 at 5:08 PM, Chandler Carruth <chandlerc at gmail.com>wrote: > Author: chandlerc > Date: Thu Sep 2 02:08:05 2010 > New Revision: 112809 > > URL: http://llvm.org/viewvc/llvm-project?rev=112809&view=rev > Log: > Silence an ambiguous else warning from GCC. > > Modified: > llvm/trunk/lib/CodeGen/PBQP/HeuristicBase.h > > Modified: llvm/trunk/lib/CodeGen/PBQP/HeuristicBase.h > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PBQP/HeuristicBase.h?rev=112809&r1=112808&r2=112809&view=diff > > ============================================================================== > --- llvm/trunk/lib/CodeGen/PBQP/HeuristicBase.h (original) > +++ llvm/trunk/lib/CodeGen/PBQP/HeuristicBase.h Thu Sep 2 02:08:05 2010 > @@ -173,12 +173,13 @@ > bool finished = false; > > while (!finished) { > - if (!optimalReduce()) > + if (!optimalReduce()) { > if (impl().heuristicReduce()) { > getSolver().recordRN(); > } else { > finished = true; > } > + } > } > } > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100902/17d9b077/attachment.html From baldrick at free.fr Thu Sep 2 03:14:03 2010 From: baldrick at free.fr (Duncan Sands) Date: Thu, 02 Sep 2010 08:14:03 -0000 Subject: [llvm-commits] [llvm] r112810 - in /llvm/trunk: include/llvm/Transforms/Utils/SSAUpdater.h lib/Transforms/Scalar/GVN.cpp lib/Transforms/Scalar/JumpThreading.cpp lib/Transforms/Scalar/LICM.cpp lib/Transforms/Scalar/LoopRotation.cpp lib/Transforms/Utils/LCSSA.cpp lib/Transforms/Utils/SSAUpdater.cpp Message-ID: <20100902081403.AA8672A6C12D@llvm.org> Author: baldrick Date: Thu Sep 2 03:14:03 2010 New Revision: 112810 URL: http://llvm.org/viewvc/llvm-project?rev=112810&view=rev Log: Reapply commit 112699, speculatively reverted by echristo, since I'm sure it is harmless. Original commit message: If PrototypeValue is erased in the middle of using the SSAUpdator then the SSAUpdator may access freed memory. Instead, simply pass in the type and name explicitly, which is all that was used anyway. Modified: llvm/trunk/include/llvm/Transforms/Utils/SSAUpdater.h llvm/trunk/lib/Transforms/Scalar/GVN.cpp llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp llvm/trunk/lib/Transforms/Scalar/LICM.cpp llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp llvm/trunk/lib/Transforms/Utils/LCSSA.cpp llvm/trunk/lib/Transforms/Utils/SSAUpdater.cpp Modified: llvm/trunk/include/llvm/Transforms/Utils/SSAUpdater.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/Utils/SSAUpdater.h?rev=112810&r1=112809&r2=112810&view=diff ============================================================================== --- llvm/trunk/include/llvm/Transforms/Utils/SSAUpdater.h (original) +++ llvm/trunk/include/llvm/Transforms/Utils/SSAUpdater.h Thu Sep 2 03:14:03 2010 @@ -36,9 +36,11 @@ //typedef DenseMap<BasicBlock*, Value*> AvailableValsTy; void *AV; - /// PrototypeValue is an arbitrary representative value, which we derive names - /// and a type for PHI nodes. - Value *PrototypeValue; + /// ProtoType holds the type of the values being rewritten. + const Type *ProtoType; + + // PHI nodes are given a name based on ProtoName. + std::string ProtoName; /// InsertedPHIs - If this is non-null, the SSAUpdater adds all PHI nodes that /// it creates to the vector. @@ -51,8 +53,8 @@ ~SSAUpdater(); /// Initialize - Reset this object to get ready for a new set of SSA - /// updates. ProtoValue is the value used to name PHI nodes. - void Initialize(Value *ProtoValue); + /// updates with type 'Ty'. PHI nodes get a name based on 'Name'. + void Initialize(const Type *Ty, StringRef Name); /// AddAvailableValue - Indicate that a rewritten value is available at the /// end of the specified block with the specified value. Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=112810&r1=112809&r2=112810&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Thu Sep 2 03:14:03 2010 @@ -1310,7 +1310,7 @@ // Otherwise, we have to construct SSA form. SmallVector<PHINode*, 8> NewPHIs; SSAUpdater SSAUpdate(&NewPHIs); - SSAUpdate.Initialize(LI); + SSAUpdate.Initialize(LI->getType(), LI->getName()); const Type *LoadTy = LI->getType(); Modified: llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp?rev=112810&r1=112809&r2=112810&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Thu Sep 2 03:14:03 2010 @@ -1528,7 +1528,7 @@ // We found a use of I outside of BB. Rename all uses of I that are outside // its block to be uses of the appropriate PHI node etc. See ValuesInBlocks // with the two values we know. - SSAUpdate.Initialize(I); + SSAUpdate.Initialize(I->getType(), I->getName()); SSAUpdate.AddAvailableValue(BB, I); SSAUpdate.AddAvailableValue(NewBB, ValueMapping[I]); @@ -1683,7 +1683,7 @@ // We found a use of I outside of BB. Rename all uses of I that are outside // its block to be uses of the appropriate PHI node etc. See ValuesInBlocks // with the two values we know. - SSAUpdate.Initialize(I); + SSAUpdate.Initialize(I->getType(), I->getName()); SSAUpdate.AddAvailableValue(BB, I); SSAUpdate.AddAvailableValue(PredBB, ValueMapping[I]); Modified: llvm/trunk/lib/Transforms/Scalar/LICM.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LICM.cpp?rev=112810&r1=112809&r2=112810&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LICM.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LICM.cpp Thu Sep 2 03:14:03 2010 @@ -526,7 +526,7 @@ SSAUpdater SSA(&NewPHIs); if (!I.use_empty()) - SSA.Initialize(&I); + SSA.Initialize(I.getType(), I.getName()); // Insert a copy of the instruction in each exit block of the loop that is // dominated by the instruction. Each exit block is known to only be in the @@ -728,7 +728,7 @@ SomeValue = LoopUses[0]; else SomeValue = cast<StoreInst>(LoopUses[0])->getOperand(0); - SSA.Initialize(SomeValue); + SSA.Initialize(SomeValue->getType(), SomeValue->getName()); // First step: bucket up uses of the pointers by the block they occur in. // This is important because we have to handle multiple defs/uses in a block Modified: llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp?rev=112810&r1=112809&r2=112810&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp Thu Sep 2 03:14:03 2010 @@ -221,7 +221,7 @@ // The value now exits in two versions: the initial value in the preheader // and the loop "next" value in the original header. - SSA.Initialize(OrigHeaderVal); + SSA.Initialize(OrigHeaderVal->getType(), OrigHeaderVal->getName()); SSA.AddAvailableValue(OrigHeader, OrigHeaderVal); SSA.AddAvailableValue(OrigPreHeader, OrigPreHeaderVal); Modified: llvm/trunk/lib/Transforms/Utils/LCSSA.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/LCSSA.cpp?rev=112810&r1=112809&r2=112810&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/LCSSA.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/LCSSA.cpp Thu Sep 2 03:14:03 2010 @@ -206,7 +206,7 @@ DomTreeNode *DomNode = DT->getNode(DomBB); SSAUpdater SSAUpdate; - SSAUpdate.Initialize(Inst); + SSAUpdate.Initialize(Inst->getType(), Inst->getName()); // Insert the LCSSA phi's into all of the exit blocks dominated by the // value, and add them to the Phi's map. Modified: llvm/trunk/lib/Transforms/Utils/SSAUpdater.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SSAUpdater.cpp?rev=112810&r1=112809&r2=112810&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SSAUpdater.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SSAUpdater.cpp Thu Sep 2 03:14:03 2010 @@ -29,20 +29,21 @@ } SSAUpdater::SSAUpdater(SmallVectorImpl<PHINode*> *NewPHI) - : AV(0), PrototypeValue(0), InsertedPHIs(NewPHI) {} + : AV(0), ProtoType(0), ProtoName(), InsertedPHIs(NewPHI) {} SSAUpdater::~SSAUpdater() { delete &getAvailableVals(AV); } /// Initialize - Reset this object to get ready for a new set of SSA -/// updates. ProtoValue is the value used to name PHI nodes. -void SSAUpdater::Initialize(Value *ProtoValue) { +/// updates with type 'Ty'. PHI nodes get a name based on 'Name'. +void SSAUpdater::Initialize(const Type *Ty, StringRef Name) { if (AV == 0) AV = new AvailableValsTy(); else getAvailableVals(AV).clear(); - PrototypeValue = ProtoValue; + ProtoType = Ty; + ProtoName = Name; } /// HasValueForBlock - Return true if the SSAUpdater already has a value for @@ -54,8 +55,8 @@ /// AddAvailableValue - Indicate that a rewritten value is available in the /// specified block with the specified value. void SSAUpdater::AddAvailableValue(BasicBlock *BB, Value *V) { - assert(PrototypeValue != 0 && "Need to initialize SSAUpdater"); - assert(PrototypeValue->getType() == V->getType() && + assert(ProtoType != 0 && "Need to initialize SSAUpdater"); + assert(ProtoType == V->getType() && "All rewritten values must have the same type"); getAvailableVals(AV)[BB] = V; } @@ -148,7 +149,7 @@ // If there are no predecessors, just return undef. if (PredValues.empty()) - return UndefValue::get(PrototypeValue->getType()); + return UndefValue::get(ProtoType); // Otherwise, if all the merged values are the same, just use it. if (SingularValue != 0) @@ -168,9 +169,7 @@ } // Ok, we have no way out, insert a new one now. - PHINode *InsertedPHI = PHINode::Create(PrototypeValue->getType(), - PrototypeValue->getName(), - &BB->front()); + PHINode *InsertedPHI = PHINode::Create(ProtoType, ProtoName, &BB->front()); InsertedPHI->reserveOperandSpace(PredValues.size()); // Fill in all the predecessors of the PHI. @@ -282,15 +281,14 @@ /// GetUndefVal - Get an undefined value of the same type as the value /// being handled. static Value *GetUndefVal(BasicBlock *BB, SSAUpdater *Updater) { - return UndefValue::get(Updater->PrototypeValue->getType()); + return UndefValue::get(Updater->ProtoType); } /// CreateEmptyPHI - Create a new PHI instruction in the specified block. /// Reserve space for the operands but do not fill them in yet. static Value *CreateEmptyPHI(BasicBlock *BB, unsigned NumPreds, SSAUpdater *Updater) { - PHINode *PHI = PHINode::Create(Updater->PrototypeValue->getType(), - Updater->PrototypeValue->getName(), + PHINode *PHI = PHINode::Create(Updater->ProtoType, Updater->ProtoName, &BB->front()); PHI->reserveOperandSpace(NumPreds); return PHI; From baldrick at free.fr Thu Sep 2 03:20:44 2010 From: baldrick at free.fr (Duncan Sands) Date: Thu, 02 Sep 2010 10:20:44 +0200 Subject: [llvm-commits] [llvm] r112719 - in /llvm/trunk: include/llvm/Transforms/Utils/SSAUpdater.h lib/CodeGen/DwarfEHPrepare.cpp lib/Transforms/Scalar/GVN.cpp lib/Transforms/Scalar/JumpThreading.cpp lib/Transforms/Scalar/LICM.cpp lib/Transforms/Scalar/LoopRotation.cpp lib/Transforms/Utils/LCSSA.cpp lib/Transforms/Utils/SSAUpdater.cpp In-Reply-To: <20100901172910.55FF52A6C12C@llvm.org> References: <20100901172910.55FF52A6C12C@llvm.org> Message-ID: <4C7F5E5C.6060805@free.fr> Hi Eric, > Speculatively revert 112699 and 112702, they seem to be causing > self host errors on clang-x86-64. I've reapplied 112699 since it should be harmless. Once the dust settles I will probably reapply 112702 since I didn't yet spot anything wrong with it. Ciao, Duncan. From lhames at gmail.com Thu Sep 2 03:27:00 2010 From: lhames at gmail.com (Lang Hames) Date: Thu, 02 Sep 2010 08:27:00 -0000 Subject: [llvm-commits] [llvm] r112811 - in /llvm/trunk/lib/CodeGen: RegAllocPBQP.cpp RenderMachineFunction.cpp RenderMachineFunction.h Message-ID: <20100902082700.5DF532A6C12C@llvm.org> Author: lhames Date: Thu Sep 2 03:27:00 2010 New Revision: 112811 URL: http://llvm.org/viewvc/llvm-project?rev=112811&view=rev Log: Added support for register allocators to record which intervals are spill intervals, and where the uses and defs of the original intervals were in the original code. Spill intervals can be hidden using the "-rmf-intervals=virt-nospills*" option. Modified: llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp llvm/trunk/lib/CodeGen/RenderMachineFunction.cpp llvm/trunk/lib/CodeGen/RenderMachineFunction.h Modified: llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp?rev=112811&r1=112810&r2=112811&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp Thu Sep 2 03:27:00 2010 @@ -140,6 +140,7 @@ const TargetInstrInfo *tii; const MachineLoopInfo *loopInfo; MachineRegisterInfo *mri; + RenderMachineFunction *rmf; LiveIntervals *lis; LiveStacks *lss; @@ -761,9 +762,11 @@ const LiveInterval *spillInterval = node2LI[node]; double oldSpillWeight = spillInterval->weight; SmallVector<LiveInterval*, 8> spillIs; + rmf->rememberUseDefs(spillInterval); std::vector<LiveInterval*> newSpills = lis->addIntervalsForSpills(*spillInterval, spillIs, loopInfo, *vrm); addStackInterval(spillInterval, mri); + rmf->rememberSpills(spillInterval, newSpills); (void) oldSpillWeight; DEBUG(dbgs() << "VREG " << virtReg << " -> SPILLED (Cost: " @@ -871,7 +874,7 @@ lis = &getAnalysis<LiveIntervals>(); lss = &getAnalysis<LiveStacks>(); loopInfo = &getAnalysis<MachineLoopInfo>(); - RenderMachineFunction *rmf = &getAnalysis<RenderMachineFunction>(); + rmf = &getAnalysis<RenderMachineFunction>(); vrm = &getAnalysis<VirtRegMap>(); Modified: llvm/trunk/lib/CodeGen/RenderMachineFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RenderMachineFunction.cpp?rev=112811&r1=112810&r2=112811&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RenderMachineFunction.cpp (original) +++ llvm/trunk/lib/CodeGen/RenderMachineFunction.cpp Thu Sep 2 03:27:00 2010 @@ -57,6 +57,11 @@ cl::init(""), cl::Hidden); static cl::opt<bool> +filterEmpty("rmf-filter-empty-intervals", + cl::desc("Don't display empty intervals."), + cl::init(true), cl::Hidden); + +static cl::opt<bool> showEmptyIndexes("rmf-empty-indexes", cl::desc("Render indexes not associated with instructions or " "MBB starts."), @@ -150,10 +155,14 @@ const std::string &intervalRangeStr) { if (intervalRangeStr == "*") { intervalTypesToRender |= All; + } else if (intervalRangeStr == "virt-nospills*") { + intervalTypesToRender |= VirtNoSpills; + } else if (intervalRangeStr == "spills*") { + intervalTypesToRender |= VirtSpills; } else if (intervalRangeStr == "virt*") { - intervalTypesToRender |= VirtPlusExplicit; + intervalTypesToRender |= AllVirt; } else if (intervalRangeStr == "phys*") { - intervalTypesToRender |= PhysPlusExplicit; + intervalTypesToRender |= AllPhys; } else { std::istringstream iss(intervalRangeStr); unsigned reg1, reg2; @@ -179,10 +188,12 @@ void MFRenderingOptions::setup(MachineFunction *mf, const TargetRegisterInfo *tri, - LiveIntervals *lis) { + LiveIntervals *lis, + const RenderMachineFunction *rmf) { this->mf = mf; this->tri = tri; this->lis = lis; + this->rmf = rmf; clear(); } @@ -252,12 +263,19 @@ if (intervalTypesToRender != ExplicitOnly) { for (LiveIntervals::iterator liItr = lis->begin(), liEnd = lis->end(); liItr != liEnd; ++liItr) { + LiveInterval *li = liItr->second; - if ((TargetRegisterInfo::isPhysicalRegister(liItr->first) && - (intervalTypesToRender & PhysPlusExplicit)) || - (TargetRegisterInfo::isVirtualRegister(liItr->first) && - (intervalTypesToRender & VirtPlusExplicit))) { - intervalSet.insert(liItr->second); + if (filterEmpty && li->empty()) + continue; + + if ((TargetRegisterInfo::isPhysicalRegister(li->reg) && + (intervalTypesToRender & AllPhys))) { + intervalSet.insert(li); + } else if (TargetRegisterInfo::isVirtualRegister(li->reg)) { + if (((intervalTypesToRender & VirtNoSpills) && !rmf->isSpill(li)) || + ((intervalTypesToRender & VirtSpills) && rmf->isSpill(li))) { + intervalSet.insert(li); + } } } } @@ -542,7 +560,26 @@ SlotIndex i) const { const MachineInstr *mi = sis->getInstructionFromIndex(i); + // For uses/defs recorded use/def indexes override current liveness and + // instruction operands (Only for the interval which records the indexes). + if (i.isUse() || i.isDef()) { + UseDefs::const_iterator udItr = useDefs.find(li); + if (udItr != useDefs.end()) { + const SlotSet &slotSet = udItr->second; + if (slotSet.count(i)) { + if (i.isUse()) { + return Used; + } + // else + return Defined; + } + } + } + + // If the slot is a load/store, or there's no info in the use/def set then + // use liveness and instruction operand info. if (li->liveAt(i)) { + if (mi == 0) { if (vrm == 0 || (vrm->getStackSlot(li->reg) == VirtRegMap::NO_STACK_SLOT)) { @@ -880,6 +917,7 @@ } bool RenderMachineFunction::runOnMachineFunction(MachineFunction &fn) { + mf = &fn; mri = &mf->getRegInfo(); tri = mf->getTarget().getRegisterInfo(); @@ -887,7 +925,10 @@ sis = &getAnalysis<SlotIndexes>(); trei.setup(mf, mri, tri, lis); - ro.setup(mf, tri, lis); + ro.setup(mf, tri, lis, this); + spillIntervals.clear(); + spillFor.clear(); + useDefs.clear(); fqn = mf->getFunction()->getParent()->getModuleIdentifier() + "." + mf->getFunction()->getName().str(); @@ -898,6 +939,50 @@ void RenderMachineFunction::releaseMemory() { trei.clear(); ro.clear(); + spillIntervals.clear(); + spillFor.clear(); + useDefs.clear(); + } + + void RenderMachineFunction::rememberUseDefs(const LiveInterval *li) { + + if (!ro.shouldRenderCurrentMachineFunction()) + return; + + for (MachineRegisterInfo::reg_iterator rItr = mri->reg_begin(li->reg), + rEnd = mri->reg_end(); + rItr != rEnd; ++rItr) { + const MachineInstr *mi = &*rItr; + if (mi->readsRegister(li->reg)) { + useDefs[li].insert(lis->getInstructionIndex(mi).getUseIndex()); + } + if (mi->definesRegister(li->reg)) { + useDefs[li].insert(lis->getInstructionIndex(mi).getDefIndex()); + } + } + } + + void RenderMachineFunction::rememberSpills( + const LiveInterval *li, + const std::vector<LiveInterval*> &spills) { + + if (!ro.shouldRenderCurrentMachineFunction()) + return; + + for (std::vector<LiveInterval*>::const_iterator siItr = spills.begin(), + siEnd = spills.end(); + siItr != siEnd; ++siItr) { + const LiveInterval *spill = *siItr; + spillIntervals[li].insert(spill); + spillFor[spill] = li; + } + } + + bool RenderMachineFunction::isSpill(const LiveInterval *li) const { + SpillForMap::const_iterator sfItr = spillFor.find(li); + if (sfItr == spillFor.end()) + return false; + return true; } void RenderMachineFunction::renderMachineFunction( Modified: llvm/trunk/lib/CodeGen/RenderMachineFunction.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RenderMachineFunction.h?rev=112811&r1=112810&r2=112811&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RenderMachineFunction.h (original) +++ llvm/trunk/lib/CodeGen/RenderMachineFunction.h Thu Sep 2 03:27:00 2010 @@ -28,77 +28,12 @@ class LiveIntervals; class MachineInstr; class MachineRegisterInfo; + class RenderMachineFunction; class TargetRegisterClass; class TargetRegisterInfo; class VirtRegMap; class raw_ostream; - /// \brief Provide extra information about the physical and virtual registers - /// in the function being compiled. - class TargetRegisterExtraInfo { - public: - TargetRegisterExtraInfo(); - - /// \brief Set up TargetRegisterExtraInfo with pointers to necessary - /// sources of information. - void setup(MachineFunction *mf, MachineRegisterInfo *mri, - const TargetRegisterInfo *tri, LiveIntervals *lis); - - /// \brief Recompute tables for changed function. - void reset(); - - /// \brief Free all tables in TargetRegisterExtraInfo. - void clear(); - - /// \brief Maximum number of registers from trc which alias reg. - unsigned getWorst(unsigned reg, const TargetRegisterClass *trc) const; - - /// \brief Returns the number of allocable registers in trc. - unsigned getCapacity(const TargetRegisterClass *trc) const; - - /// \brief Return the number of registers of class trc that may be - /// needed at slot i. - unsigned getPressureAtSlot(const TargetRegisterClass *trc, - SlotIndex i) const; - - /// \brief Return true if the number of registers of type trc that may be - /// needed at slot i is greater than the capacity of trc. - bool classOverCapacityAtSlot(const TargetRegisterClass *trc, - SlotIndex i) const; - - private: - - MachineFunction *mf; - MachineRegisterInfo *mri; - const TargetRegisterInfo *tri; - LiveIntervals *lis; - - typedef std::map<const TargetRegisterClass*, unsigned> WorstMapLine; - typedef std::map<const TargetRegisterClass*, WorstMapLine> VRWorstMap; - VRWorstMap vrWorst; - - typedef std::map<unsigned, WorstMapLine> PRWorstMap; - PRWorstMap prWorst; - - typedef std::map<const TargetRegisterClass*, unsigned> CapacityMap; - CapacityMap capacityMap; - - typedef std::map<const TargetRegisterClass*, unsigned> PressureMapLine; - typedef std::map<SlotIndex, PressureMapLine> PressureMap; - PressureMap pressureMap; - - bool mapsPopulated; - - /// \brief Initialise the 'worst' table. - void initWorst(); - - /// \brief Initialise the 'capacity' table. - void initCapacity(); - - /// \brief Initialise/Reset the 'pressure' and live states tables. - void resetPressureAndLiveStates(); - }; - /// \brief Helper class to process rendering options. Tries to be as lazy as /// possible. class MFRenderingOptions { @@ -125,7 +60,7 @@ /// Initialise the rendering options. void setup(MachineFunction *mf, const TargetRegisterInfo *tri, - LiveIntervals *lis); + LiveIntervals *lis, const RenderMachineFunction *rmf); /// Clear translations of options to the current function. void clear(); @@ -160,9 +95,11 @@ static std::set<std::pair<unsigned, unsigned> > intervalNumsToRender; typedef enum { ExplicitOnly = 0, - VirtPlusExplicit = 1, - PhysPlusExplicit = 2, - All = 3 } + AllPhys = 1, + VirtNoSpills = 2, + VirtSpills = 4, + AllVirt = 6, + All = 7 } IntervalTypesToRender; static unsigned intervalTypesToRender; @@ -180,6 +117,7 @@ MachineFunction *mf; const TargetRegisterInfo *tri; LiveIntervals *lis; + const RenderMachineFunction *rmf; mutable bool regClassesTranslatedToCurrentFunction; mutable RegClassSet regClassSet; @@ -192,6 +130,72 @@ void translateIntervalNumbersToCurrentFunction() const; }; + /// \brief Provide extra information about the physical and virtual registers + /// in the function being compiled. + class TargetRegisterExtraInfo { + public: + TargetRegisterExtraInfo(); + + /// \brief Set up TargetRegisterExtraInfo with pointers to necessary + /// sources of information. + void setup(MachineFunction *mf, MachineRegisterInfo *mri, + const TargetRegisterInfo *tri, LiveIntervals *lis); + + /// \brief Recompute tables for changed function. + void reset(); + + /// \brief Free all tables in TargetRegisterExtraInfo. + void clear(); + + /// \brief Maximum number of registers from trc which alias reg. + unsigned getWorst(unsigned reg, const TargetRegisterClass *trc) const; + + /// \brief Returns the number of allocable registers in trc. + unsigned getCapacity(const TargetRegisterClass *trc) const; + + /// \brief Return the number of registers of class trc that may be + /// needed at slot i. + unsigned getPressureAtSlot(const TargetRegisterClass *trc, + SlotIndex i) const; + + /// \brief Return true if the number of registers of type trc that may be + /// needed at slot i is greater than the capacity of trc. + bool classOverCapacityAtSlot(const TargetRegisterClass *trc, + SlotIndex i) const; + + private: + + MachineFunction *mf; + MachineRegisterInfo *mri; + const TargetRegisterInfo *tri; + LiveIntervals *lis; + + typedef std::map<const TargetRegisterClass*, unsigned> WorstMapLine; + typedef std::map<const TargetRegisterClass*, WorstMapLine> VRWorstMap; + VRWorstMap vrWorst; + + typedef std::map<unsigned, WorstMapLine> PRWorstMap; + PRWorstMap prWorst; + + typedef std::map<const TargetRegisterClass*, unsigned> CapacityMap; + CapacityMap capacityMap; + + typedef std::map<const TargetRegisterClass*, unsigned> PressureMapLine; + typedef std::map<SlotIndex, PressureMapLine> PressureMap; + PressureMap pressureMap; + + bool mapsPopulated; + + /// \brief Initialise the 'worst' table. + void initWorst(); + + /// \brief Initialise the 'capacity' table. + void initCapacity(); + + /// \brief Initialise/Reset the 'pressure' and live states tables. + void resetPressureAndLiveStates(); + }; + /// \brief Render MachineFunction objects and related information to a HTML /// page. class RenderMachineFunction : public MachineFunctionPass { @@ -206,6 +210,13 @@ virtual void releaseMemory(); + void rememberUseDefs(const LiveInterval *li); + + void rememberSpills(const LiveInterval *li, + const std::vector<LiveInterval*> &spills); + + bool isSpill(const LiveInterval *li) const; + /// \brief Render this machine function to HTML. /// /// @param renderContextStr This parameter will be included in the top of @@ -225,10 +236,8 @@ private: class Spacer; - friend raw_ostream& operator<<(raw_ostream &os, const Spacer &s); - std::string fqn; MachineFunction *mf; @@ -241,6 +250,8 @@ TargetRegisterExtraInfo trei; MFRenderingOptions ro; + + // Utilities. typedef enum { Dead, Defined, Used, AliveReg, AliveStack } LiveState; LiveState getLiveStateAt(const LiveInterval *li, SlotIndex i) const; @@ -249,6 +260,17 @@ PressureState getPressureStateAt(const TargetRegisterClass *trc, SlotIndex i) const; + typedef std::map<const LiveInterval*, std::set<const LiveInterval*> > + SpillIntervals; + SpillIntervals spillIntervals; + + typedef std::map<const LiveInterval*, const LiveInterval*> SpillForMap; + SpillForMap spillFor; + + typedef std::set<SlotIndex> SlotSet; + typedef std::map<const LiveInterval*, SlotSet> UseDefs; + UseDefs useDefs; + // ---------- Rendering methods ---------- /// For inserting spaces when pretty printing. From echristo at apple.com Thu Sep 2 03:50:47 2010 From: echristo at apple.com (Eric Christopher) Date: Thu, 2 Sep 2010 01:50:47 -0700 Subject: [llvm-commits] [llvm] r112810 - in /llvm/trunk: include/llvm/Transforms/Utils/SSAUpdater.h lib/Transforms/Scalar/GVN.cpp lib/Transforms/Scalar/JumpThreading.cpp lib/Transforms/Scalar/LICM.cpp lib/Transforms/Scalar/LoopRotation.cpp lib/Transforms/Utils/LCSSA.cpp lib/Transforms/Utils/SSAUpdater.cpp In-Reply-To: <20100902081403.AA8672A6C12D@llvm.org> References: <20100902081403.AA8672A6C12D@llvm.org> Message-ID: <E75E12F3-4A60-4DAB-83CE-5A3B05A899B2@apple.com> On Sep 2, 2010, at 1:14 AM, Duncan Sands wrote: > Reapply commit 112699, speculatively reverted by echristo, since > I'm sure it is harmless. Original commit message: > If PrototypeValue is erased in the middle of using the SSAUpdator > then the SSAUpdator may access freed memory. Instead, simply pass > in the type and name explicitly, which is all that was used anyway. Yeah, I meant to reapply, there's some random miscompilation causing failures. *sigh* -eric From baldrick at free.fr Thu Sep 2 03:52:23 2010 From: baldrick at free.fr (Duncan Sands) Date: Thu, 02 Sep 2010 08:52:23 -0000 Subject: [llvm-commits] [llvm] r112812 - in /llvm/trunk: lib/VMCore/AsmWriter.cpp test/Transforms/IndVarSimplify/2003-12-10-IndVarDeadCode.ll Message-ID: <20100902085223.466DD2A6C12C@llvm.org> Author: baldrick Date: Thu Sep 2 03:52:23 2010 New Revision: 112812 URL: http://llvm.org/viewvc/llvm-project?rev=112812&view=rev Log: Print the number of uses of a function in the .ll since it can be informative and there seems to be no reason not to. Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp llvm/trunk/test/Transforms/IndVarSimplify/2003-12-10-IndVarDeadCode.ll Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=112812&r1=112811&r2=112812&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/AsmWriter.cpp (original) +++ llvm/trunk/lib/VMCore/AsmWriter.cpp Thu Sep 2 03:52:23 2010 @@ -1635,9 +1635,9 @@ if (F->hasGC()) Out << " gc \"" << F->getGC() << '"'; if (F->isDeclaration()) { - Out << "\n"; + Out << " ; [#uses=" << F->getNumUses() << "]\n"; // Output # uses } else { - Out << " {"; + Out << " { ; [#uses=" << F->getNumUses() << ']'; // Output # uses // Output all of its basic blocks... for the function for (Function::const_iterator I = F->begin(), E = F->end(); I != E; ++I) Modified: llvm/trunk/test/Transforms/IndVarSimplify/2003-12-10-IndVarDeadCode.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/2003-12-10-IndVarDeadCode.ll?rev=112812&r1=112811&r2=112812&view=diff ============================================================================== --- llvm/trunk/test/Transforms/IndVarSimplify/2003-12-10-IndVarDeadCode.ll (original) +++ llvm/trunk/test/Transforms/IndVarSimplify/2003-12-10-IndVarDeadCode.ll Thu Sep 2 03:52:23 2010 @@ -1,8 +1,7 @@ ; The induction variable canonicalization pass shouldn't leave dead ; instructions laying around! ; -; RUN: opt < %s -indvars -S | \ -; RUN: not grep {#uses=0} +; RUN: opt < %s -indvars -S | grep {#uses=0} | count 1 define i32 @mul(i32 %x, i32 %y) { entry: From nunoplopes at sapo.pt Thu Sep 2 05:51:27 2010 From: nunoplopes at sapo.pt (Nuno Lopes) Date: Thu, 02 Sep 2010 10:51:27 -0000 Subject: [llvm-commits] [www-pubs] r112817 - /www-pubs/trunk/2010-06-06-Clang-LLVM.html Message-ID: <20100902105127.92FAD2A6C12C@llvm.org> Author: nlopes Date: Thu Sep 2 05:51:27 2010 New Revision: 112817 URL: http://llvm.org/viewvc/llvm-project?rev=112817&view=rev Log: fix html Modified: www-pubs/trunk/2010-06-06-Clang-LLVM.html Modified: www-pubs/trunk/2010-06-06-Clang-LLVM.html URL: http://llvm.org/viewvc/llvm-project/www-pubs/trunk/2010-06-06-Clang-LLVM.html?rev=112817&r1=112816&r2=112817&view=diff ============================================================================== --- www-pubs/trunk/2010-06-06-Clang-LLVM.html (original) +++ www-pubs/trunk/2010-06-06-Clang-LLVM.html Thu Sep 2 05:51:27 2010 @@ -3,7 +3,7 @@ <head> <meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /> <link rel="stylesheet" href="../llvm.css" type="text/css" media="screen" /> - <title>Clang/LLVM Maturity Report + <title>Clang/LLVM Maturity Report From geek4civic at gmail.com Thu Sep 2 08:04:36 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Thu, 2 Sep 2010 22:04:36 +0900 Subject: [llvm-commits] [PATCH] test/CodeGen/X86 patches for win32 In-Reply-To: References: <0C45983F-0D48-4990-8170-1E69E7CB2D41@apple.com> Message-ID: Anton, Thank you comments. I understand, "Tests should be funcionality test, not environment test." > test/CodeGen/X86/2009-03-13-PHIElimBug.ll > test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll > test/CodeGen/X86/dyn-stackalloc.ll I will commit 3 of them tonight, with -mtriple=(i686|x86_64)-linux > Also, it's not obvious why you need to change > test/CodeGen/X86/twoaddr-coalesce.ll I thought this test would not require to be @main. In fact, (a part) difference among @foo(-) and @main(+) is below on cygwin and mingw; -_foo: +_main: # BB#0: + pushl %ebp + movl %esp, %ebp pushl %ebx - subl $8, %esp + subl $12, %esp + call ___main With -mtriple=i686-linux, they are almost same. ps. Thanks to Duncan, to give me several advices about triplet on the irc today. Sleepy Thursday...Takumi From foldr at codedgers.com Thu Sep 2 09:06:21 2010 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Thu, 02 Sep 2010 14:06:21 -0000 Subject: [llvm-commits] [llvm] r112818 - /llvm/trunk/tools/llvmc/src/Base.td.in Message-ID: <20100902140621.C6D822A6C12C@llvm.org> Author: foldr Date: Thu Sep 2 09:06:21 2010 New Revision: 112818 URL: http://llvm.org/viewvc/llvm-project?rev=112818&view=rev Log: llvmc: .dylib support. Modified: llvm/trunk/tools/llvmc/src/Base.td.in Modified: llvm/trunk/tools/llvmc/src/Base.td.in URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvmc/src/Base.td.in?rev=112818&r1=112817&r2=112818&view=diff ============================================================================== --- llvm/trunk/tools/llvmc/src/Base.td.in (original) +++ llvm/trunk/tools/llvmc/src/Base.td.in Thu Sep 2 09:06:21 2010 @@ -262,7 +262,7 @@ // Base class for linkers class llvm_gcc_based_linker : Tool< -[(in_language ["object-code", "static-library"]), +[(in_language ["object-code", "static-library", "dynamic-library"]), (out_language "executable"), (output_suffix "out"), (command cmd_prefix), @@ -321,6 +321,7 @@ (lang_to_suffixes "llvm-bitcode", "bc"), (lang_to_suffixes "object-code", ["o", "*empty*"]), (lang_to_suffixes "static-library", ["a", "lib"]), + (lang_to_suffixes "dynamic-library", ["so", "dylib", "dll"]), (lang_to_suffixes "executable", ["out"]) ]>; From baldrick at free.fr Thu Sep 2 10:43:20 2010 From: baldrick at free.fr (Duncan Sands) Date: Thu, 02 Sep 2010 15:43:20 -0000 Subject: [llvm-commits] [zorg] r112822 - /zorg/trunk/buildbot/osuosl/master/config/slaves.py Message-ID: <20100902154320.688262A6C12C@llvm.org> Author: baldrick Date: Thu Sep 2 10:43:20 2010 New Revision: 112822 URL: http://llvm.org/viewvc/llvm-project?rev=112822&view=rev Log: Place comments before the create_slave line. Modified: zorg/trunk/buildbot/osuosl/master/config/slaves.py Modified: zorg/trunk/buildbot/osuosl/master/config/slaves.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/slaves.py?rev=112822&r1=112821&r2=112822&view=diff ============================================================================== --- zorg/trunk/buildbot/osuosl/master/config/slaves.py (original) +++ zorg/trunk/buildbot/osuosl/master/config/slaves.py Thu Sep 2 10:43:20 2010 @@ -53,35 +53,65 @@ create_slave("adobe1", properties={'jobs' : 2}, max_builds=1), # GCC Farm Slaves - create_slave("baldrick10", properties={'jobs' : 12}, max_builds=1), # gcc10 2TB 2x12x1.5 GHz 2x Opteron Magny-Cours / 64 GB RAM / Supermicro AS-1022G-BTF - create_slave("baldrick11", properties={'jobs' : 2}, max_builds=1), # gcc11 580G 2x 2x2.0 GHz Opteron 2212 / 4GB RAM / Dell SC1345 - create_slave("baldrick12", properties={'jobs' : 2}, max_builds=1), # gcc12 580G 2x 2x2.0 GHz Opteron 2212 / 4GB RAM / Dell SC1345 - create_slave("baldrick13", properties={'jobs' : 2}, max_builds=1), # gcc13 580G 2x2x2.0 GHz Opteron 2212 / 4GB RAM / Dell SC1345 - create_slave("baldrick14", properties={'jobs' : 4}, max_builds=1), # gcc14 750G 2x4x3.0 GHz Xeon X5450 / 16GB RAM / Dell Poweredge 1950 - create_slave("baldrick15", properties={'jobs' : 1}, max_builds=1), # gcc15 160G 1x2x2.8 GHz Xeon dual core "paxville" / 1 GB RAM / Dell SC1425 - create_slave("baldrick16", properties={'jobs' : 4}, max_builds=1), # gcc16 580G 2x4x2.2 GHz Opteron 8354 "Barcelona B3" / 16 GB RAM - create_slave("baldrick17", properties={'jobs' : 4}, max_builds=1), # gcc17 580G 2x4x2.2 GHz Opteron 8354 "Barcelona B3" / 16 GB RAM - create_slave("baldrick35", properties={'jobs' : 1}, max_builds=1), # gcc35 19035 1TB 0.8 GHz Freescale i.MX515 (ARM Cortex-A8) / 512 MB RAM / Efika MX Client Dev Board - create_slave("baldrick38", properties={'jobs' : 1}, max_builds=1), # gcc38 19038 1TB 3.2 GHz Sony Playstation 3 / Cell / SPE - create_slave("baldrick40", properties={'jobs' : 1}, max_builds=1), # gcc40 9090 160G 1.8 GHz PowerPC 970 G5 / 512 MB RAM / PowerMac G5 - create_slave("baldrick42", properties={'jobs' : 1}, max_builds=1), # gcc42 9092 160G 0.8 GHz MIPS Loongson 2F / 1 GB RAM / Lemote Fuloong 6004 Linux mini PC - create_slave("baldrick43", properties={'jobs' : 1}, max_builds=1), # gcc43 9093 60G 1.4 GHz Powerpc G4 7447A / 1GB RAM / Apple Mac Mini - create_slave("baldrick50", properties={'jobs' : 1}, max_builds=1), # gcc50 9080 250G 0.6 GHz ARM XScale-80219 / 512 MB RAM / Thecus N2100 NAS - create_slave("baldrick51", properties={'jobs' : 1}, max_builds=1), # gcc51 9081 60G 0.8 GHz MIPS Loongson 2F / 1 GB RAM / Lemote YeeLoong 8089 notebook - create_slave("baldrick52", properties={'jobs' : 1}, max_builds=1), # gcc52 9082 1TB 0.8 GHz MIPS Loongson 2F / 512 MB RAM / Gdium Liberty 1000 notebook Mandriva 2009.1 - create_slave("baldrick53", properties={'jobs' : 1}, max_builds=1), # gcc53 9083 80G 2x1.25 GHz PowerPC 7455 G4 / 1.5 GB RAM / PowerMac G4 dual processor - create_slave("baldrick54", properties={'jobs' : 1}, max_builds=1), # gcc54 9084 36G 0.5 GHz TI UltraSparc IIe (Hummingbird) / 1.5 GB RAM / Sun Netra T1 200 / Debian sparc64 - create_slave("baldrick55", properties={'jobs' : 1}, max_builds=1), # gcc55 9085 250G 1.2 GHz ARM Feroceon 88FR131 (kirkwood) / 512 MB RAM / Marvell SheevaPlug - create_slave("baldrick56", properties={'jobs' : 1}, max_builds=1), # gcc56 9086 320G 1.2 GHz ARM Feroceon 88FR131 (kirkwood) / 512 MB RAM / Marvell SheevaPlug - create_slave("baldrick57", properties={'jobs' : 1}, max_builds=1), # gcc57 9087 320G 1.2 GHz ARM Feroceon 88FR131 (kirkwood) / 512 MB RAM / Marvell SheevaPlug - create_slave("baldrick60", properties={'jobs' : 1}, max_builds=1), # gcc60 9200 72G 2x1.3 GHz Madison / 6 GB RAM / HP zx6000 - create_slave("baldrick61", properties={'jobs' : 1}, max_builds=1), # gcc61 9201 36G 2x0.55 GHz PA8600 / 3.5 GB RAM / HP 9000/785/J6000 - create_slave("baldrick62", properties={'jobs' : 3}, max_builds=1), # gcc62 9202 36G 6x0.4GHz TI UltraSparc II (BlackBird) / 5 GB RAM / Sun Enterprise 4500 / Debian sparc64 - create_slave("baldrick63", properties={'jobs' : 16}, max_builds=1), # gcc63 9203 72G 8x4x1GHz UltraSparc T1 (Niagara) 1 GHz 8 core 32 threads / 8 GB RAM / Sun Fire T1000 / Debian sparc64 - create_slave("baldrick64", properties={'jobs' : 1}, max_builds=1), # gcc64 9204 72G 1x1GHz UltraSPARC-IIIi / 1 GB RAM / Sun V210 / OpenBSD 4.6 sparc64 - create_slave("baldrick101", properties={'jobs' : 1}, max_builds=1), # gcc101 1TB 2x2.6 GHz Opteron 252 / 1GB RAM running FreeBSD 8 x86_64 - create_slave("baldrick200", properties={'jobs' : 2}, max_builds=1), # gcc200 8010 80G 4x0.4GHz TI UltraSparc II (BlackBird) / 4 GB RAM / Sun E250 / Gentoo sparc64 - create_slave("baldrick201", properties={'jobs' : 2}, max_builds=1), # gcc201 8011 80G 4x0.4GHz TI UltraSparc II (BlackBird) / 4 GB RAM / Sun E250 / Gentoo sparc64 + + # gcc10 2TB 2x12x1.5 GHz 2x Opteron Magny-Cours / 64 GB RAM / Supermicro AS-1022G-BTF + create_slave("baldrick10", properties={'jobs' : 12}, max_builds=1), + # gcc11 580G 2x 2x2.0 GHz Opteron 2212 / 4GB RAM / Dell SC1345 + create_slave("baldrick11", properties={'jobs' : 2}, max_builds=1), + # gcc12 580G 2x 2x2.0 GHz Opteron 2212 / 4GB RAM / Dell SC1345 + create_slave("baldrick12", properties={'jobs' : 2}, max_builds=1), + # gcc13 580G 2x2x2.0 GHz Opteron 2212 / 4GB RAM / Dell SC1345 + create_slave("baldrick13", properties={'jobs' : 2}, max_builds=1), + # gcc14 750G 2x4x3.0 GHz Xeon X5450 / 16GB RAM / Dell Poweredge 1950 + create_slave("baldrick14", properties={'jobs' : 4}, max_builds=1), + # gcc15 160G 1x2x2.8 GHz Xeon dual core "paxville" / 1 GB RAM / Dell SC1425 + create_slave("baldrick15", properties={'jobs' : 1}, max_builds=1), + # gcc16 580G 2x4x2.2 GHz Opteron 8354 "Barcelona B3" / 16 GB RAM + create_slave("baldrick16", properties={'jobs' : 4}, max_builds=1), + # gcc17 580G 2x4x2.2 GHz Opteron 8354 "Barcelona B3" / 16 GB RAM + create_slave("baldrick17", properties={'jobs' : 4}, max_builds=1), + # gcc35 19035 1TB 0.8 GHz Freescale i.MX515 (ARM Cortex-A8) / 512 MB RAM / Efika MX Client Dev Board + create_slave("baldrick35", properties={'jobs' : 1}, max_builds=1), + # gcc38 19038 1TB 3.2 GHz Sony Playstation 3 / Cell / SPE + create_slave("baldrick38", properties={'jobs' : 1}, max_builds=1), + # gcc40 9090 160G 1.8 GHz PowerPC 970 G5 / 512 MB RAM / PowerMac G5 + create_slave("baldrick40", properties={'jobs' : 1}, max_builds=1), + # gcc42 9092 160G 0.8 GHz MIPS Loongson 2F / 1 GB RAM / Lemote Fuloong 6004 Linux mini PC + create_slave("baldrick42", properties={'jobs' : 1}, max_builds=1), + # gcc43 9093 60G 1.4 GHz Powerpc G4 7447A / 1GB RAM / Apple Mac Mini + create_slave("baldrick43", properties={'jobs' : 1}, max_builds=1), + # gcc50 9080 250G 0.6 GHz ARM XScale-80219 / 512 MB RAM / Thecus N2100 NAS + create_slave("baldrick50", properties={'jobs' : 1}, max_builds=1), + # gcc51 9081 60G 0.8 GHz MIPS Loongson 2F / 1 GB RAM / Lemote YeeLoong 8089 notebook + create_slave("baldrick51", properties={'jobs' : 1}, max_builds=1), + # gcc52 9082 1TB 0.8 GHz MIPS Loongson 2F / 512 MB RAM / Gdium Liberty 1000 notebook Mandriva 2009.1 + create_slave("baldrick52", properties={'jobs' : 1}, max_builds=1), + # gcc53 9083 80G 2x1.25 GHz PowerPC 7455 G4 / 1.5 GB RAM / PowerMac G4 dual processor + create_slave("baldrick53", properties={'jobs' : 1}, max_builds=1), + # gcc54 9084 36G 0.5 GHz TI UltraSparc IIe (Hummingbird) / 1.5 GB RAM / Sun Netra T1 200 / Debian sparc64 + create_slave("baldrick54", properties={'jobs' : 1}, max_builds=1), + # gcc55 9085 250G 1.2 GHz ARM Feroceon 88FR131 (kirkwood) / 512 MB RAM / Marvell SheevaPlug + create_slave("baldrick55", properties={'jobs' : 1}, max_builds=1), + # gcc56 9086 320G 1.2 GHz ARM Feroceon 88FR131 (kirkwood) / 512 MB RAM / Marvell SheevaPlug + create_slave("baldrick56", properties={'jobs' : 1}, max_builds=1), + # gcc57 9087 320G 1.2 GHz ARM Feroceon 88FR131 (kirkwood) / 512 MB RAM / Marvell SheevaPlug + create_slave("baldrick57", properties={'jobs' : 1}, max_builds=1), + # gcc60 9200 72G 2x1.3 GHz Madison / 6 GB RAM / HP zx6000 + create_slave("baldrick60", properties={'jobs' : 1}, max_builds=1), + # gcc61 9201 36G 2x0.55 GHz PA8600 / 3.5 GB RAM / HP 9000/785/J6000 + create_slave("baldrick61", properties={'jobs' : 1}, max_builds=1), + # gcc62 9202 36G 6x0.4GHz TI UltraSparc II (BlackBird) / 5 GB RAM / Sun Enterprise 4500 / Debian sparc64 + create_slave("baldrick62", properties={'jobs' : 3}, max_builds=1), + # gcc63 9203 72G 8x4x1GHz UltraSparc T1 (Niagara) 1 GHz 8 core 32 threads / 8 GB RAM / Sun Fire T1000 / Debian sparc64 + create_slave("baldrick63", properties={'jobs' : 16}, max_builds=1), + # gcc64 9204 72G 1x1GHz UltraSPARC-IIIi / 1 GB RAM / Sun V210 / OpenBSD 4.6 sparc64 + create_slave("baldrick64", properties={'jobs' : 1}, max_builds=1), + # gcc101 1TB 2x2.6 GHz Opteron 252 / 1GB RAM running FreeBSD 8 x86_64 + create_slave("baldrick101", properties={'jobs' : 1}, max_builds=1), + # gcc200 8010 80G 4x0.4GHz TI UltraSparc II (BlackBird) / 4 GB RAM / Sun E250 / Gentoo sparc64 + create_slave("baldrick200", properties={'jobs' : 2}, max_builds=1), + # gcc201 8011 80G 4x0.4GHz TI UltraSparc II (BlackBird) / 4 GB RAM / Sun E250 / Gentoo sparc64 + create_slave("baldrick201", properties={'jobs' : 2}, max_builds=1), # Debian x86_64, 2 x 6-core Opteron 2.6 GHz create_slave("osu7", properties={'jobs' : 6}, max_builds=4), From baldrick at free.fr Thu Sep 2 10:55:13 2010 From: baldrick at free.fr (Duncan Sands) Date: Thu, 02 Sep 2010 15:55:13 -0000 Subject: [llvm-commits] [zorg] r112823 - in /zorg/trunk/buildbot/osuosl/master/config: builders.py slaves.py Message-ID: <20100902155513.369D72A6C12C@llvm.org> Author: baldrick Date: Thu Sep 2 10:55:13 2010 New Revision: 112823 URL: http://llvm.org/viewvc/llvm-project?rev=112823&view=rev Log: Rename the baldrickXYZ buildslaves to gccXYZ, i.e. the name of the gcc compile farm machine it runs on. Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py zorg/trunk/buildbot/osuosl/master/config/slaves.py Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=112823&r1=112822&r2=112823&view=diff ============================================================================== --- zorg/trunk/buildbot/osuosl/master/config/builders.py (original) +++ zorg/trunk/buildbot/osuosl/master/config/builders.py Thu Sep 2 10:55:13 2010 @@ -190,7 +190,7 @@ def _get_dragonegg_builders(): return [ {'name' : 'dragonegg-i386-linux', - 'slavenames' : ['baldrick16'], + 'slavenames' : ['gcc16'], 'builddir' : 'dragonegg-i386-linux', 'factory' : ScriptedBuilder.getScriptedBuildFactory( source_code = [SVN(name='svn-llvm', @@ -205,7 +205,7 @@ 'category' : 'dragonegg'}, {'name' : 'dragonegg-x86_64-linux', - 'slavenames' : ['baldrick17'], + 'slavenames' : ['gcc17'], 'builddir' : 'dragonegg-x86_64-linux', 'factory' : ScriptedBuilder.getScriptedBuildFactory( source_code = [SVN(name='svn-llvm', Modified: zorg/trunk/buildbot/osuosl/master/config/slaves.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/slaves.py?rev=112823&r1=112822&r2=112823&view=diff ============================================================================== --- zorg/trunk/buildbot/osuosl/master/config/slaves.py (original) +++ zorg/trunk/buildbot/osuosl/master/config/slaves.py Thu Sep 2 10:55:13 2010 @@ -54,64 +54,64 @@ # GCC Farm Slaves - # gcc10 2TB 2x12x1.5 GHz 2x Opteron Magny-Cours / 64 GB RAM / Supermicro AS-1022G-BTF - create_slave("baldrick10", properties={'jobs' : 12}, max_builds=1), - # gcc11 580G 2x 2x2.0 GHz Opteron 2212 / 4GB RAM / Dell SC1345 - create_slave("baldrick11", properties={'jobs' : 2}, max_builds=1), - # gcc12 580G 2x 2x2.0 GHz Opteron 2212 / 4GB RAM / Dell SC1345 - create_slave("baldrick12", properties={'jobs' : 2}, max_builds=1), - # gcc13 580G 2x2x2.0 GHz Opteron 2212 / 4GB RAM / Dell SC1345 - create_slave("baldrick13", properties={'jobs' : 2}, max_builds=1), - # gcc14 750G 2x4x3.0 GHz Xeon X5450 / 16GB RAM / Dell Poweredge 1950 - create_slave("baldrick14", properties={'jobs' : 4}, max_builds=1), - # gcc15 160G 1x2x2.8 GHz Xeon dual core "paxville" / 1 GB RAM / Dell SC1425 - create_slave("baldrick15", properties={'jobs' : 1}, max_builds=1), - # gcc16 580G 2x4x2.2 GHz Opteron 8354 "Barcelona B3" / 16 GB RAM - create_slave("baldrick16", properties={'jobs' : 4}, max_builds=1), - # gcc17 580G 2x4x2.2 GHz Opteron 8354 "Barcelona B3" / 16 GB RAM - create_slave("baldrick17", properties={'jobs' : 4}, max_builds=1), - # gcc35 19035 1TB 0.8 GHz Freescale i.MX515 (ARM Cortex-A8) / 512 MB RAM / Efika MX Client Dev Board - create_slave("baldrick35", properties={'jobs' : 1}, max_builds=1), - # gcc38 19038 1TB 3.2 GHz Sony Playstation 3 / Cell / SPE - create_slave("baldrick38", properties={'jobs' : 1}, max_builds=1), - # gcc40 9090 160G 1.8 GHz PowerPC 970 G5 / 512 MB RAM / PowerMac G5 - create_slave("baldrick40", properties={'jobs' : 1}, max_builds=1), - # gcc42 9092 160G 0.8 GHz MIPS Loongson 2F / 1 GB RAM / Lemote Fuloong 6004 Linux mini PC - create_slave("baldrick42", properties={'jobs' : 1}, max_builds=1), - # gcc43 9093 60G 1.4 GHz Powerpc G4 7447A / 1GB RAM / Apple Mac Mini - create_slave("baldrick43", properties={'jobs' : 1}, max_builds=1), - # gcc50 9080 250G 0.6 GHz ARM XScale-80219 / 512 MB RAM / Thecus N2100 NAS - create_slave("baldrick50", properties={'jobs' : 1}, max_builds=1), - # gcc51 9081 60G 0.8 GHz MIPS Loongson 2F / 1 GB RAM / Lemote YeeLoong 8089 notebook - create_slave("baldrick51", properties={'jobs' : 1}, max_builds=1), - # gcc52 9082 1TB 0.8 GHz MIPS Loongson 2F / 512 MB RAM / Gdium Liberty 1000 notebook Mandriva 2009.1 - create_slave("baldrick52", properties={'jobs' : 1}, max_builds=1), - # gcc53 9083 80G 2x1.25 GHz PowerPC 7455 G4 / 1.5 GB RAM / PowerMac G4 dual processor - create_slave("baldrick53", properties={'jobs' : 1}, max_builds=1), - # gcc54 9084 36G 0.5 GHz TI UltraSparc IIe (Hummingbird) / 1.5 GB RAM / Sun Netra T1 200 / Debian sparc64 - create_slave("baldrick54", properties={'jobs' : 1}, max_builds=1), - # gcc55 9085 250G 1.2 GHz ARM Feroceon 88FR131 (kirkwood) / 512 MB RAM / Marvell SheevaPlug - create_slave("baldrick55", properties={'jobs' : 1}, max_builds=1), - # gcc56 9086 320G 1.2 GHz ARM Feroceon 88FR131 (kirkwood) / 512 MB RAM / Marvell SheevaPlug - create_slave("baldrick56", properties={'jobs' : 1}, max_builds=1), - # gcc57 9087 320G 1.2 GHz ARM Feroceon 88FR131 (kirkwood) / 512 MB RAM / Marvell SheevaPlug - create_slave("baldrick57", properties={'jobs' : 1}, max_builds=1), - # gcc60 9200 72G 2x1.3 GHz Madison / 6 GB RAM / HP zx6000 - create_slave("baldrick60", properties={'jobs' : 1}, max_builds=1), - # gcc61 9201 36G 2x0.55 GHz PA8600 / 3.5 GB RAM / HP 9000/785/J6000 - create_slave("baldrick61", properties={'jobs' : 1}, max_builds=1), - # gcc62 9202 36G 6x0.4GHz TI UltraSparc II (BlackBird) / 5 GB RAM / Sun Enterprise 4500 / Debian sparc64 - create_slave("baldrick62", properties={'jobs' : 3}, max_builds=1), - # gcc63 9203 72G 8x4x1GHz UltraSparc T1 (Niagara) 1 GHz 8 core 32 threads / 8 GB RAM / Sun Fire T1000 / Debian sparc64 - create_slave("baldrick63", properties={'jobs' : 16}, max_builds=1), - # gcc64 9204 72G 1x1GHz UltraSPARC-IIIi / 1 GB RAM / Sun V210 / OpenBSD 4.6 sparc64 - create_slave("baldrick64", properties={'jobs' : 1}, max_builds=1), - # gcc101 1TB 2x2.6 GHz Opteron 252 / 1GB RAM running FreeBSD 8 x86_64 - create_slave("baldrick101", properties={'jobs' : 1}, max_builds=1), - # gcc200 8010 80G 4x0.4GHz TI UltraSparc II (BlackBird) / 4 GB RAM / Sun E250 / Gentoo sparc64 - create_slave("baldrick200", properties={'jobs' : 2}, max_builds=1), - # gcc201 8011 80G 4x0.4GHz TI UltraSparc II (BlackBird) / 4 GB RAM / Sun E250 / Gentoo sparc64 - create_slave("baldrick201", properties={'jobs' : 2}, max_builds=1), + # 2TB 2x12x1.5 GHz 2x Opteron Magny-Cours / 64 GB RAM / Supermicro AS-1022G-BTF + create_slave("gcc10", properties={'jobs' : 12}, max_builds=1), + # 580G 2x 2x2.0 GHz Opteron 2212 / 4GB RAM / Dell SC1345 + create_slave("gcc11", properties={'jobs' : 2}, max_builds=1), + # 580G 2x 2x2.0 GHz Opteron 2212 / 4GB RAM / Dell SC1345 + create_slave("gcc12", properties={'jobs' : 2}, max_builds=1), + # 580G 2x2x2.0 GHz Opteron 2212 / 4GB RAM / Dell SC1345 + create_slave("gcc13", properties={'jobs' : 2}, max_builds=1), + # 750G 2x4x3.0 GHz Xeon X5450 / 16GB RAM / Dell Poweredge 1950 + create_slave("gcc14", properties={'jobs' : 4}, max_builds=1), + # 160G 1x2x2.8 GHz Xeon dual core "paxville" / 1 GB RAM / Dell SC1425 + create_slave("gcc15", properties={'jobs' : 1}, max_builds=1), + # 580G 2x4x2.2 GHz Opteron 8354 "Barcelona B3" / 16 GB RAM + create_slave("gcc16", properties={'jobs' : 4}, max_builds=1), + # 580G 2x4x2.2 GHz Opteron 8354 "Barcelona B3" / 16 GB RAM + create_slave("gcc17", properties={'jobs' : 4}, max_builds=1), + # 1TB 0.8 GHz Freescale i.MX515 (ARM Cortex-A8) / 512 MB RAM / Efika MX Client Dev Board + create_slave("gcc35", properties={'jobs' : 1}, max_builds=1), + # 1TB 3.2 GHz Sony Playstation 3 / Cell / SPE + create_slave("gcc38", properties={'jobs' : 1}, max_builds=1), + # 160G 1.8 GHz PowerPC 970 G5 / 512 MB RAM / PowerMac G5 + create_slave("gcc40", properties={'jobs' : 1}, max_builds=1), + # 160G 0.8 GHz MIPS Loongson 2F / 1 GB RAM / Lemote Fuloong 6004 Linux mini PC + create_slave("gcc42", properties={'jobs' : 1}, max_builds=1), + # 60G 1.4 GHz Powerpc G4 7447A / 1GB RAM / Apple Mac Mini + create_slave("gcc43", properties={'jobs' : 1}, max_builds=1), + # 250G 0.6 GHz ARM XScale-80219 / 512 MB RAM / Thecus N2100 NAS + create_slave("gcc50", properties={'jobs' : 1}, max_builds=1), + # 60G 0.8 GHz MIPS Loongson 2F / 1 GB RAM / Lemote YeeLoong 8089 notebook + create_slave("gcc51", properties={'jobs' : 1}, max_builds=1), + # 1TB 0.8 GHz MIPS Loongson 2F / 512 MB RAM / Gdium Liberty 1000 notebook Mandriva 2009.1 + create_slave("gcc52", properties={'jobs' : 1}, max_builds=1), + # 80G 2x1.25 GHz PowerPC 7455 G4 / 1.5 GB RAM / PowerMac G4 dual processor + create_slave("gcc53", properties={'jobs' : 1}, max_builds=1), + # 36G 0.5 GHz TI UltraSparc IIe (Hummingbird) / 1.5 GB RAM / Sun Netra T1 200 / Debian sparc64 + create_slave("gcc54", properties={'jobs' : 1}, max_builds=1), + # 250G 1.2 GHz ARM Feroceon 88FR131 (kirkwood) / 512 MB RAM / Marvell SheevaPlug + create_slave("gcc55", properties={'jobs' : 1}, max_builds=1), + # 320G 1.2 GHz ARM Feroceon 88FR131 (kirkwood) / 512 MB RAM / Marvell SheevaPlug + create_slave("gcc56", properties={'jobs' : 1}, max_builds=1), + # 320G 1.2 GHz ARM Feroceon 88FR131 (kirkwood) / 512 MB RAM / Marvell SheevaPlug + create_slave("gcc57", properties={'jobs' : 1}, max_builds=1), + # 72G 2x1.3 GHz Madison / 6 GB RAM / HP zx6000 + create_slave("gcc60", properties={'jobs' : 1}, max_builds=1), + # 36G 2x0.55 GHz PA8600 / 3.5 GB RAM / HP 9000/785/J6000 + create_slave("gcc61", properties={'jobs' : 1}, max_builds=1), + # 36G 6x0.4GHz TI UltraSparc II (BlackBird) / 5 GB RAM / Sun Enterprise 4500 / Debian sparc64 + create_slave("gcc62", properties={'jobs' : 3}, max_builds=1), + # 72G 8x4x1GHz UltraSparc T1 (Niagara) 1 GHz 8 core 32 threads / 8 GB RAM / Sun Fire T1000 / Debian sparc64 + create_slave("gcc63", properties={'jobs' : 16}, max_builds=1), + # 72G 1x1GHz UltraSPARC-IIIi / 1 GB RAM / Sun V210 / OpenBSD 4.6 sparc64 + create_slave("gcc64", properties={'jobs' : 1}, max_builds=1), + # 1TB 2x2.6 GHz Opteron 252 / 1GB RAM running FreeBSD 8 x86_64 + create_slave("gcc101", properties={'jobs' : 1}, max_builds=1), + # 80G 4x0.4GHz TI UltraSparc II (BlackBird) / 4 GB RAM / Sun E250 / Gentoo sparc64 + create_slave("gcc200", properties={'jobs' : 2}, max_builds=1), + # 80G 4x0.4GHz TI UltraSparc II (BlackBird) / 4 GB RAM / Sun E250 / Gentoo sparc64 + create_slave("gcc201", properties={'jobs' : 2}, max_builds=1), # Debian x86_64, 2 x 6-core Opteron 2.6 GHz create_slave("osu7", properties={'jobs' : 6}, max_builds=4), From Mike.Gist at imgtec.com Thu Sep 2 10:12:07 2010 From: Mike.Gist at imgtec.com (Mike Gist) Date: Thu, 2 Sep 2010 16:12:07 +0100 Subject: [llvm-commits] [PATCH] Fix cmake build without native target selected In-Reply-To: <98860CD172CEBA47AC403E1E6D93F842104762@klmail.kl.imgtec.org> Message-ID: <98860CD172CEBA47AC403E1E6D93F842104763@klmail.kl.imgtec.org> Hi, The cmake (+ MSVC) build is broken if you don't select your native target. e.g. 'cmake -D LLVM_TARGETS_TO_BUILD="MyNonNativeTarget" .' This is because cmake currently sets the LLVM_NATIVE_* definitions regardless of whether the native target is selected (causing build errors). The attached patch fixes this problem by only setting them when the native target is selected, which is consistent with the behaviour of configure. Regards, Mike -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100902/0b7f97a7/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: config-ix.patch Type: application/octet-stream Size: 983 bytes Desc: config-ix.patch Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100902/0b7f97a7/attachment.obj From bob.wilson at apple.com Thu Sep 2 11:00:54 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Thu, 02 Sep 2010 16:00:54 -0000 Subject: [llvm-commits] [llvm] r112825 - in /llvm/trunk: lib/Target/ARM/ARMExpandPseudoInsts.cpp lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/ARM/ARMInstrNEON.td lib/Target/ARM/NEONPreAllocPass.cpp test/CodeGen/ARM/reg_sequence.ll Message-ID: <20100902160054.C5A8F2A6C12C@llvm.org> Author: bwilson Date: Thu Sep 2 11:00:54 2010 New Revision: 112825 URL: http://llvm.org/viewvc/llvm-project?rev=112825&view=rev Log: Convert VLD1 and VLD2 instructions to use pseudo-instructions until after regalloc. Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp llvm/trunk/test/CodeGen/ARM/reg_sequence.ll Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=112825&r1=112824&r2=112825&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Thu Sep 2 11:00:54 2010 @@ -48,6 +48,8 @@ void TransferImpOps(MachineInstr &OldMI, MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI); bool ExpandMBB(MachineBasicBlock &MBB); + void ExpandVLD(MachineBasicBlock::iterator &MBBI, unsigned Opc, + bool hasWriteBack, NEONRegSpacing RegSpc, unsigned NumRegs); void ExpandVST(MachineBasicBlock::iterator &MBBI, unsigned Opc, bool hasWriteBack, NEONRegSpacing RegSpc, unsigned NumRegs); }; @@ -72,6 +74,66 @@ } } +/// ExpandVLD - +/// +void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI, + unsigned Opc, bool hasWriteBack, + NEONRegSpacing RegSpc, unsigned NumRegs) { + MachineInstr &MI = *MBBI; + MachineBasicBlock &MBB = *MI.getParent(); + + MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)); + unsigned OpIdx = 0; + + bool DstIsDead = MI.getOperand(OpIdx).isDead(); + unsigned DstReg = MI.getOperand(OpIdx++).getReg(); + unsigned D0, D1, D2, D3; + if (RegSpc == SingleSpc) { + D0 = TRI->getSubReg(DstReg, ARM::dsub_0); + D1 = TRI->getSubReg(DstReg, ARM::dsub_1); + D2 = TRI->getSubReg(DstReg, ARM::dsub_2); + D3 = TRI->getSubReg(DstReg, ARM::dsub_3); + } else if (RegSpc == EvenDblSpc) { + D0 = TRI->getSubReg(DstReg, ARM::dsub_0); + D1 = TRI->getSubReg(DstReg, ARM::dsub_2); + D2 = TRI->getSubReg(DstReg, ARM::dsub_4); + D3 = TRI->getSubReg(DstReg, ARM::dsub_6); + } else { + assert(RegSpc == OddDblSpc && "unknown register spacing for VLD"); + D0 = TRI->getSubReg(DstReg, ARM::dsub_1); + D1 = TRI->getSubReg(DstReg, ARM::dsub_3); + D2 = TRI->getSubReg(DstReg, ARM::dsub_5); + D3 = TRI->getSubReg(DstReg, ARM::dsub_7); + } + MIB.addReg(D0).addReg(D1); + if (NumRegs > 2) + MIB.addReg(D2); + if (NumRegs > 3) + MIB.addReg(D3); + + if (hasWriteBack) { + bool WBIsDead = MI.getOperand(OpIdx).isDead(); + unsigned WBReg = MI.getOperand(OpIdx++).getReg(); + MIB.addReg(WBReg, getDefRegState(true) | getDeadRegState(WBIsDead)); + } + // Copy the addrmode6 operands. + bool AddrIsKill = MI.getOperand(OpIdx).isKill(); + MIB.addReg(MI.getOperand(OpIdx++).getReg(), getKillRegState(AddrIsKill)); + MIB.addImm(MI.getOperand(OpIdx++).getImm()); + if (hasWriteBack) { + // Copy the am6offset operand. + bool OffsetIsKill = MI.getOperand(OpIdx).isKill(); + MIB.addReg(MI.getOperand(OpIdx++).getReg(), getKillRegState(OffsetIsKill)); + } + + MIB = AddDefaultPred(MIB); + TransferImpOps(MI, MIB, MIB); + // Add an implicit def for the super-reg. + MIB.addReg(DstReg, (getDefRegState(true) | getDeadRegState(DstIsDead) | + getImplRegState(true))); + MI.eraseFromParent(); +} + /// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register /// operands to real VST instructions with D register operands. void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI, @@ -232,6 +294,58 @@ MI.eraseFromParent(); } + case ARM::VLD1q8Pseudo: + ExpandVLD(MBBI, ARM::VLD1q8, false, SingleSpc, 2); break; + case ARM::VLD1q16Pseudo: + ExpandVLD(MBBI, ARM::VLD1q16, false, SingleSpc, 2); break; + case ARM::VLD1q32Pseudo: + ExpandVLD(MBBI, ARM::VLD1q32, false, SingleSpc, 2); break; + case ARM::VLD1q64Pseudo: + ExpandVLD(MBBI, ARM::VLD1q64, false, SingleSpc, 2); break; + case ARM::VLD1q8Pseudo_UPD: + ExpandVLD(MBBI, ARM::VLD1q8, true, SingleSpc, 2); break; + case ARM::VLD1q16Pseudo_UPD: + ExpandVLD(MBBI, ARM::VLD1q16, true, SingleSpc, 2); break; + case ARM::VLD1q32Pseudo_UPD: + ExpandVLD(MBBI, ARM::VLD1q32, true, SingleSpc, 2); break; + case ARM::VLD1q64Pseudo_UPD: + ExpandVLD(MBBI, ARM::VLD1q64, true, SingleSpc, 2); break; + + case ARM::VLD2d8Pseudo: + ExpandVLD(MBBI, ARM::VLD2d8, false, SingleSpc, 2); break; + case ARM::VLD2d16Pseudo: + ExpandVLD(MBBI, ARM::VLD2d16, false, SingleSpc, 2); break; + case ARM::VLD2d32Pseudo: + ExpandVLD(MBBI, ARM::VLD2d32, false, SingleSpc, 2); break; + case ARM::VLD2q8Pseudo: + ExpandVLD(MBBI, ARM::VLD2q8, false, SingleSpc, 4); break; + case ARM::VLD2q16Pseudo: + ExpandVLD(MBBI, ARM::VLD2q16, false, SingleSpc, 4); break; + case ARM::VLD2q32Pseudo: + ExpandVLD(MBBI, ARM::VLD2q32, false, SingleSpc, 4); break; + case ARM::VLD2d8Pseudo_UPD: + ExpandVLD(MBBI, ARM::VLD2d8, true, SingleSpc, 2); break; + case ARM::VLD2d16Pseudo_UPD: + ExpandVLD(MBBI, ARM::VLD2d16, true, SingleSpc, 2); break; + case ARM::VLD2d32Pseudo_UPD: + ExpandVLD(MBBI, ARM::VLD2d32, true, SingleSpc, 2); break; + case ARM::VLD2q8Pseudo_UPD: + ExpandVLD(MBBI, ARM::VLD2q8, true, SingleSpc, 4); break; + case ARM::VLD2q16Pseudo_UPD: + ExpandVLD(MBBI, ARM::VLD2q16, true, SingleSpc, 4); break; + case ARM::VLD2q32Pseudo_UPD: + ExpandVLD(MBBI, ARM::VLD2q32, true, SingleSpc, 4); break; + + case ARM::VLD1d64TPseudo: + ExpandVLD(MBBI, ARM::VLD1d64T, false, SingleSpc, 3); break; + case ARM::VLD1d64TPseudo_UPD: + ExpandVLD(MBBI, ARM::VLD1d64T, true, SingleSpc, 3); break; + + case ARM::VLD1d64QPseudo: + ExpandVLD(MBBI, ARM::VLD1d64Q, false, SingleSpc, 4); break; + case ARM::VLD1d64QPseudo_UPD: + ExpandVLD(MBBI, ARM::VLD1d64Q, true, SingleSpc, 4); break; + case ARM::VST1q8Pseudo: ExpandVST(MBBI, ARM::VST1q8, false, SingleSpc, 2); break; case ARM::VST1q16Pseudo: Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=112825&r1=112824&r2=112825&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Thu Sep 2 11:00:54 2010 @@ -1116,35 +1116,44 @@ if (is64BitVector) { unsigned Opc = DOpcodes[OpcodeIndex]; const SDValue Ops[] = { MemAddr, Align, Pred, Reg0, Chain }; - std::vector ResTys(NumVecs, VT); - ResTys.push_back(MVT::Other); - SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 5); - if (NumVecs < 2) + SDNode *VLd; + if (NumVecs <= 2) { + EVT ResTy; + if (NumVecs == 1) + ResTy = VT; + else + ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, NumVecs); + VLd = CurDAG->getMachineNode(Opc, dl, ResTy, MVT::Other, Ops, 5); + } else { + std::vector ResTys(NumVecs, VT); + ResTys.push_back(MVT::Other); + VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 5); + } + if (NumVecs == 1) return VLd; - SDValue RegSeq; - SDValue V0 = SDValue(VLd, 0); - SDValue V1 = SDValue(VLd, 1); - - // Form a REG_SEQUENCE to force register allocation. - if (NumVecs == 2) - RegSeq = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0); + SDValue SuperReg; + if (NumVecs <= 2) + SuperReg = SDValue(VLd, 0); else { + SDValue V0 = SDValue(VLd, 0); + SDValue V1 = SDValue(VLd, 1); + // Form a REG_SEQUENCE to force register allocation. SDValue V2 = SDValue(VLd, 2); // If it's a vld3, form a quad D-register but discard the last part. SDValue V3 = (NumVecs == 3) ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0) : SDValue(VLd, 3); - RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0); + SuperReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0); } assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering"); for (unsigned Vec = 0; Vec < NumVecs; ++Vec) { SDValue D = CurDAG->getTargetExtractSubreg(ARM::dsub_0+Vec, - dl, VT, RegSeq); + dl, VT, SuperReg); ReplaceUses(SDValue(N, Vec), D); } - ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, NumVecs)); + ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, NumVecs <= 2 ? 1 : NumVecs)); return NULL; } @@ -1154,24 +1163,25 @@ // loading pairs of D regs. unsigned Opc = QOpcodes0[OpcodeIndex]; const SDValue Ops[] = { MemAddr, Align, Pred, Reg0, Chain }; - std::vector ResTys(2 * NumVecs, RegVT); - ResTys.push_back(MVT::Other); - SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 5); - Chain = SDValue(VLd, 2 * NumVecs); + + EVT ResTy; + if (NumVecs == 1) + ResTy = VT; + else + ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, 2 * NumVecs); + SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTy, MVT::Other, Ops, 5); // Combine the even and odd subregs to produce the result. - if (NumVecs == 1) { - SDNode *Q = PairDRegs(VT, SDValue(VLd, 0), SDValue(VLd, 1)); - ReplaceUses(SDValue(N, 0), SDValue(Q, 0)); - } else { - SDValue QQ = SDValue(QuadDRegs(MVT::v4i64, - SDValue(VLd, 0), SDValue(VLd, 1), - SDValue(VLd, 2), SDValue(VLd, 3)), 0); - SDValue Q0 = CurDAG->getTargetExtractSubreg(ARM::qsub_0, dl, VT, QQ); - SDValue Q1 = CurDAG->getTargetExtractSubreg(ARM::qsub_1, dl, VT, QQ); - ReplaceUses(SDValue(N, 0), Q0); - ReplaceUses(SDValue(N, 1), Q1); - } + if (NumVecs == 1) + return VLd; + + SDValue QQ = SDValue(VLd, 0); + Chain = SDValue(VLd, 1); + + SDValue Q0 = CurDAG->getTargetExtractSubreg(ARM::qsub_0, dl, VT, QQ); + SDValue Q1 = CurDAG->getTargetExtractSubreg(ARM::qsub_1, dl, VT, QQ); + ReplaceUses(SDValue(N, 0), Q0); + ReplaceUses(SDValue(N, 1), Q1); } else { // Otherwise, quad registers are loaded with two separate instructions, // where one loads the even registers and the other loads the odd registers. @@ -2142,15 +2152,16 @@ case Intrinsic::arm_neon_vld1: { unsigned DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16, ARM::VLD1d32, ARM::VLD1d64 }; - unsigned QOpcodes[] = { ARM::VLD1q8, ARM::VLD1q16, - ARM::VLD1q32, ARM::VLD1q64 }; + unsigned QOpcodes[] = { ARM::VLD1q8Pseudo, ARM::VLD1q16Pseudo, + ARM::VLD1q32Pseudo, ARM::VLD1q64Pseudo }; return SelectVLD(N, 1, DOpcodes, QOpcodes, 0); } case Intrinsic::arm_neon_vld2: { - unsigned DOpcodes[] = { ARM::VLD2d8, ARM::VLD2d16, - ARM::VLD2d32, ARM::VLD1q64 }; - unsigned QOpcodes[] = { ARM::VLD2q8, ARM::VLD2q16, ARM::VLD2q32 }; + unsigned DOpcodes[] = { ARM::VLD2d8Pseudo, ARM::VLD2d16Pseudo, + ARM::VLD2d32Pseudo, ARM::VLD1q64Pseudo }; + unsigned QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo, + ARM::VLD2q32Pseudo }; return SelectVLD(N, 2, DOpcodes, QOpcodes, 0); } Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=112825&r1=112824&r2=112825&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Thu Sep 2 11:00:54 2010 @@ -167,6 +167,21 @@ let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in { +// Classes for VLD* pseudo-instructions with multi-register operands. +// These are expanded to real instructions after register allocation. +class VLDQPseudo + : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), IIC_VST, "">; +class VLDQWBPseudo + : PseudoNLdSt<(outs QPR:$dst, GPR:$wb), + (ins addrmode6:$addr, am6offset:$offset), IIC_VST, + "$addr.addr = $wb">; +class VLDQQPseudo + : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), IIC_VST, "">; +class VLDQQWBPseudo + : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb), + (ins addrmode6:$addr, am6offset:$offset), IIC_VST, + "$addr.addr = $wb">; + // VLD1 : Vector Load (multiple single elements) class VLD1D op7_4, string Dt> : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst), @@ -187,6 +202,11 @@ def VLD1q32 : VLD1Q<0b1000, "32">; def VLD1q64 : VLD1Q<0b1100, "64">; +def VLD1q8Pseudo : VLDQPseudo; +def VLD1q16Pseudo : VLDQPseudo; +def VLD1q32Pseudo : VLDQPseudo; +def VLD1q64Pseudo : VLDQPseudo; + // ...with address register writeback: class VLD1DWB op7_4, string Dt> : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$dst, GPR:$wb), @@ -209,6 +229,11 @@ def VLD1q32_UPD : VLD1QWB<0b1000, "32">; def VLD1q64_UPD : VLD1QWB<0b1100, "64">; +def VLD1q8Pseudo_UPD : VLDQWBPseudo; +def VLD1q16Pseudo_UPD : VLDQWBPseudo; +def VLD1q32Pseudo_UPD : VLDQWBPseudo; +def VLD1q64Pseudo_UPD : VLDQWBPseudo; + // ...with 3 registers (some of these are only for the disassembler): class VLD1D3 op7_4, string Dt> : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3), @@ -229,6 +254,9 @@ def VLD1d32T_UPD : VLD1D3WB<0b1000, "32">; def VLD1d64T_UPD : VLD1D3WB<0b1100, "64">; +def VLD1d64TPseudo : VLDQQPseudo; +def VLD1d64TPseudo_UPD : VLDQQWBPseudo; + // ...with 4 registers (some of these are only for the disassembler): class VLD1D4 op7_4, string Dt> : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4), @@ -251,6 +279,9 @@ def VLD1d32Q_UPD : VLD1D4WB<0b1000, "32">; def VLD1d64Q_UPD : VLD1D4WB<0b1100, "64">; +def VLD1d64QPseudo : VLDQQPseudo; +def VLD1d64QPseudo_UPD : VLDQQWBPseudo; + // VLD2 : Vector Load (multiple 2-element structures) class VLD2D op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2), @@ -270,6 +301,14 @@ def VLD2q16 : VLD2Q<0b0100, "16">; def VLD2q32 : VLD2Q<0b1000, "32">; +def VLD2d8Pseudo : VLDQPseudo; +def VLD2d16Pseudo : VLDQPseudo; +def VLD2d32Pseudo : VLDQPseudo; + +def VLD2q8Pseudo : VLDQQPseudo; +def VLD2q16Pseudo : VLDQQPseudo; +def VLD2q32Pseudo : VLDQQPseudo; + // ...with address register writeback: class VLD2DWB op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$dst1, DPR:$dst2, GPR:$wb), @@ -291,6 +330,14 @@ def VLD2q16_UPD : VLD2QWB<0b0100, "16">; def VLD2q32_UPD : VLD2QWB<0b1000, "32">; +def VLD2d8Pseudo_UPD : VLDQWBPseudo; +def VLD2d16Pseudo_UPD : VLDQWBPseudo; +def VLD2d32Pseudo_UPD : VLDQWBPseudo; + +def VLD2q8Pseudo_UPD : VLDQQWBPseudo; +def VLD2q16Pseudo_UPD : VLDQQWBPseudo; +def VLD2q32Pseudo_UPD : VLDQQWBPseudo; + // ...with double-spaced registers (for disassembly only): def VLD2b8 : VLD2D<0b1001, 0b0000, "8">; def VLD2b16 : VLD2D<0b1001, 0b0100, "16">; @@ -531,10 +578,10 @@ def VST1q32 : VST1Q<0b1000, "32">; def VST1q64 : VST1Q<0b1100, "64">; -def VST1q8Pseudo : VSTQPseudo; -def VST1q16Pseudo : VSTQPseudo; -def VST1q32Pseudo : VSTQPseudo; -def VST1q64Pseudo : VSTQPseudo; +def VST1q8Pseudo : VSTQPseudo; +def VST1q16Pseudo : VSTQPseudo; +def VST1q32Pseudo : VSTQPseudo; +def VST1q64Pseudo : VSTQPseudo; // ...with address register writeback: class VST1DWB op7_4, string Dt> Modified: llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp?rev=112825&r1=112824&r2=112825&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp (original) +++ llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp Thu Sep 2 11:00:54 2010 @@ -51,13 +51,6 @@ default: break; - case ARM::VLD1q8: - case ARM::VLD1q16: - case ARM::VLD1q32: - case ARM::VLD1q64: - case ARM::VLD2d8: - case ARM::VLD2d16: - case ARM::VLD2d32: case ARM::VLD2LNd8: case ARM::VLD2LNd16: case ARM::VLD2LNd32: @@ -65,13 +58,6 @@ NumRegs = 2; return true; - case ARM::VLD2q8: - case ARM::VLD2q16: - case ARM::VLD2q32: - FirstOpnd = 0; - NumRegs = 4; - return true; - case ARM::VLD2LNq16: case ARM::VLD2LNq32: FirstOpnd = 0; Modified: llvm/trunk/test/CodeGen/ARM/reg_sequence.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/reg_sequence.ll?rev=112825&r1=112824&r2=112825&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/reg_sequence.ll (original) +++ llvm/trunk/test/CodeGen/ARM/reg_sequence.ll Thu Sep 2 11:00:54 2010 @@ -45,10 +45,10 @@ entry: ; CHECK: t2: ; CHECK: vld1.16 -; CHECK: vmul.i16 ; CHECK-NOT: vmov ; CHECK: vld1.16 ; CHECK: vmul.i16 +; CHECK: vmul.i16 ; CHECK-NOT: vmov ; CHECK: vst1.16 ; CHECK: vst1.16 From bob.wilson at apple.com Thu Sep 2 11:17:29 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Thu, 02 Sep 2010 16:17:29 -0000 Subject: [llvm-commits] [llvm] r112826 - /llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Message-ID: <20100902161729.2CF802A6C12C@llvm.org> Author: bwilson Date: Thu Sep 2 11:17:29 2010 New Revision: 112826 URL: http://llvm.org/viewvc/llvm-project?rev=112826&view=rev Log: Fill in a missing comment. Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=112826&r1=112825&r2=112826&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Thu Sep 2 11:17:29 2010 @@ -74,8 +74,8 @@ } } -/// ExpandVLD - -/// +/// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register +/// operands to real VLD instructions with D register operands. void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI, unsigned Opc, bool hasWriteBack, NEONRegSpacing RegSpc, unsigned NumRegs) { From grosbach at apple.com Thu Sep 2 11:31:21 2010 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 02 Sep 2010 16:31:21 -0000 Subject: [llvm-commits] [llvm] r112828 - /llvm/trunk/lib/Target/TargetRegisterInfo.cpp Message-ID: <20100902163121.B38292A6C12C@llvm.org> Author: grosbach Date: Thu Sep 2 11:31:21 2010 New Revision: 112828 URL: http://llvm.org/viewvc/llvm-project?rev=112828&view=rev Log: Mask out reserved registers when constructing the set of allocatable regs. Modified: llvm/trunk/lib/Target/TargetRegisterInfo.cpp Modified: llvm/trunk/lib/Target/TargetRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetRegisterInfo.cpp?rev=112828&r1=112827&r2=112828&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/TargetRegisterInfo.cpp Thu Sep 2 11:31:21 2010 @@ -80,6 +80,11 @@ for (TargetRegisterInfo::regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I) getAllocatableSetForRC(MF, *I, Allocatable); + + // Mask out the reserved registers + BitVector Reserved = getReservedRegs(MF); + Allocatable ^= Reserved & Allocatable; + return Allocatable; } From gohman at apple.com Thu Sep 2 11:43:59 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 2 Sep 2010 09:43:59 -0700 Subject: [llvm-commits] [llvm] r112812 - in /llvm/trunk: lib/VMCore/AsmWriter.cpp test/Transforms/IndVarSimplify/2003-12-10-IndVarDeadCode.ll In-Reply-To: <20100902085223.466DD2A6C12C@llvm.org> References: <20100902085223.466DD2A6C12C@llvm.org> Message-ID: <4C105032-4407-482D-8246-67444396F6B2@apple.com> On Sep 2, 2010, at 1:52 AM, Duncan Sands wrote: > Author: baldrick > Date: Thu Sep 2 03:52:23 2010 > New Revision: 112812 > > URL: http://llvm.org/viewvc/llvm-project?rev=112812&view=rev > Log: > Print the number of uses of a function in the .ll since it can be informative > and there seems to be no reason not to. Hi Duncan, IMHO, the AsmPrinter should just print the IR. It shouldn't be doing extra unnecessary analysis (especially not when the analysis has quadratic worst-case complexity :-}). There has been a fair amount of confusion from newcomers about whether these numbers are an explicit part of the IR; they aren't. Also, in the case of functions with external linkage, the use count is more misleading than useful, because such functions may have any number of users outside their module. And, the first line of function definitions is already a pretty crowded place, and it's liable to become more crowded in the future. I've actually been considering removing use count printing altogether, possibly adding an AsmAnnotationWriter for printing use counts as an option when the information is actually desired. Another possibility is to suppress use counts for single-use instructions and global values with external linkage. This would reduce the clutter while still preserving the information that is useful. Dan From dpatel at apple.com Thu Sep 2 11:43:44 2010 From: dpatel at apple.com (Devang Patel) Date: Thu, 02 Sep 2010 16:43:44 -0000 Subject: [llvm-commits] [llvm] r112830 - in /llvm/trunk: include/llvm/CodeGen/AsmPrinter.h include/llvm/MC/MCAsmInfo.h lib/CodeGen/AsmPrinter/AsmPrinter.cpp lib/CodeGen/AsmPrinter/DwarfDebug.cpp lib/MC/MCAsmInfo.cpp lib/MC/MCAsmInfoDarwin.cpp Message-ID: <20100902164344.D7E792A6C12C@llvm.org> Author: dpatel Date: Thu Sep 2 11:43:44 2010 New Revision: 112830 URL: http://llvm.org/viewvc/llvm-project?rev=112830&view=rev Log: Fix .debug_range for linux. Patch by Krister Wombell. Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h llvm/trunk/include/llvm/MC/MCAsmInfo.h llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp llvm/trunk/lib/MC/MCAsmInfo.cpp llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/AsmPrinter.h?rev=112830&r1=112829&r2=112830&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/AsmPrinter.h (original) +++ llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Thu Sep 2 11:43:44 2010 @@ -328,6 +328,12 @@ void EmitLabelOffsetDifference(const MCSymbol *Hi, uint64_t Offset, const MCSymbol *Lo, unsigned Size) const; + /// EmitLabelPlusOffset - Emit something like ".long Label+Offset" + /// where the size in bytes of the directive is specified by Size and Label + /// specifies the label. This implicitly uses .set if it is available. + void EmitLabelPlusOffset(const MCSymbol *Label, uint64_t Offset, + unsigned Size) const; + //===------------------------------------------------------------------===// // Dwarf Emission Helper Routines //===------------------------------------------------------------------===// Modified: llvm/trunk/include/llvm/MC/MCAsmInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAsmInfo.h?rev=112830&r1=112829&r2=112830&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCAsmInfo.h (original) +++ llvm/trunk/include/llvm/MC/MCAsmInfo.h Thu Sep 2 11:43:44 2010 @@ -259,6 +259,10 @@ /// absolute label instead of offset. bool DwarfUsesAbsoluteLabelForStmtList; // Defaults to true; + // DwarfUsesLabelOffsetDifference - True if Dwarf2 output can + // use EmitLabelOffsetDifference. + bool DwarfUsesLabelOffsetForRanges; + //===--- CBE Asm Translation Table -----------------------------------===// const char *const *AsmTransCBE; // Defaults to empty @@ -424,6 +428,9 @@ bool doesDwarfUsesAbsoluteLabelForStmtList() const { return DwarfUsesAbsoluteLabelForStmtList; } + bool doesDwarfUsesLabelOffsetForRanges() const { + return DwarfUsesLabelOffsetForRanges; + } const char *const *getAsmCBE() const { return AsmTransCBE; } Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=112830&r1=112829&r2=112830&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Thu Sep 2 11:43:44 2010 @@ -1218,6 +1218,29 @@ OutStreamer.EmitSymbolValue(SetLabel, 4, 0/*AddrSpace*/); } } + +/// EmitLabelPlusOffset - Emit something like ".long Label+Offset" +/// where the size in bytes of the directive is specified by Size and Label +/// specifies the label. This implicitly uses .set if it is available. +void AsmPrinter::EmitLabelPlusOffset(const MCSymbol *Label, uint64_t Offset, + unsigned Size) + const { + + // Emit Label+Offset + const MCExpr *Plus = + MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(Label, OutContext), + MCConstantExpr::Create(Offset, OutContext), + OutContext); + + if (!MAI->hasSetDirective()) + OutStreamer.EmitValue(Plus, 4, 0/*AddrSpace*/); + else { + // Otherwise, emit with .set (aka assignment). + MCSymbol *SetLabel = GetTempSymbol("set", SetCounter++); + OutStreamer.EmitAssignment(SetLabel, Plus); + OutStreamer.EmitSymbolValue(SetLabel, 4, 0/*AddrSpace*/); + } +} //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=112830&r1=112829&r2=112830&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Thu Sep 2 11:43:44 2010 @@ -3130,10 +3130,17 @@ case dwarf::DW_AT_ranges: { // DW_AT_range Value encodes offset in debug_range section. DIEInteger *V = cast(Values[i]); - Asm->EmitLabelOffsetDifference(DwarfDebugRangeSectionSym, - V->getValue(), - DwarfDebugRangeSectionSym, - 4); + + if (Asm->MAI->doesDwarfUsesLabelOffsetForRanges()) { + Asm->EmitLabelPlusOffset(DwarfDebugRangeSectionSym, + V->getValue(), + 4); + } else { + Asm->EmitLabelOffsetDifference(DwarfDebugRangeSectionSym, + V->getValue(), + DwarfDebugRangeSectionSym, + 4); + } break; } case dwarf::DW_AT_location: { Modified: llvm/trunk/lib/MC/MCAsmInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmInfo.cpp?rev=112830&r1=112829&r2=112830&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAsmInfo.cpp (original) +++ llvm/trunk/lib/MC/MCAsmInfo.cpp Thu Sep 2 11:43:44 2010 @@ -70,6 +70,7 @@ DwarfUsesInlineInfoSection = false; DwarfUsesAbsoluteLabelForStmtList = true; DwarfSectionOffsetDirective = 0; + DwarfUsesLabelOffsetForRanges = true; HasMicrosoftFastStdCallMangling = false; AsmTransCBE = 0; Modified: llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp?rev=112830&r1=112829&r2=112830&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp (original) +++ llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp Thu Sep 2 11:43:44 2010 @@ -46,5 +46,6 @@ HasNoDeadStrip = true; DwarfUsesAbsoluteLabelForStmtList = false; + DwarfUsesLabelOffsetForRanges = false; } From dpatel at apple.com Thu Sep 2 11:45:13 2010 From: dpatel at apple.com (Devang Patel) Date: Thu, 2 Sep 2010 09:45:13 -0700 Subject: [llvm-commits] [PATCH] fix debug_ranges for ELF targets In-Reply-To: References: Message-ID: <464874E9-EBA3-4441-BE92-41A58F6A95EC@apple.com> On Sep 1, 2010, at 10:05 PM, Krister Wombell wrote: > As requested: new patch that uses an MAI query to implement either the previous behaviour on Darwin or the new expression structure for ELF. Looks good. I applied the patch r112830. > > Krister > > On Thu, Aug 26, 2010 at 1:26 PM, Krister Wombell wrote: > Some (all binutils?) based ELF assemblers treat expressions like: > > (.Ldebug_ranges + 48) - .Ldebug_ranges > > as a constant and won't emit a relocation. When the debug_ranges sections are finally linked then DIE's that have a reference to an offset in the debug_ranges section won't be correct (they'll all point to the first compilation unit encountered by the linker). gdb doesn't like this. > > This form of expression is emitted by AsmPrinter::EmitLabelOffsetDifference. It'd be difficult to encode this form of expression in ELF and because the only caller of this function actually called it with the same symbol for the Lo and Hi args it can be represented as 'label + offset' instead. Replaced the entire function with something called EmitLabelPlusOffset. > > Ran make in tests directory, no unexpected failures. > > > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100902/503896d8/attachment.html From gohman at apple.com Thu Sep 2 11:46:46 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 2 Sep 2010 09:46:46 -0700 Subject: [llvm-commits] [llvm] r112808 - /llvm/trunk/tools/gold/gold-plugin.cpp In-Reply-To: <20100902054431.42ED92A6C12C@llvm.org> References: <20100902054431.42ED92A6C12C@llvm.org> Message-ID: <873495F9-CDA0-4569-95A7-EEE1AA86022B@apple.com> On Sep 1, 2010, at 10:44 PM, Nick Lewycky wrote: > > Fix compile errors. Thanks, sorry for the breakage. Dan From gohman at apple.com Thu Sep 2 11:52:35 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 2 Sep 2010 09:52:35 -0700 Subject: [llvm-commits] [llvm] r112803 - /llvm/trunk/lib/Support/SystemUtils.cpp In-Reply-To: <20100902034604.74E4E2A6C12C@llvm.org> References: <20100902034604.74E4E2A6C12C@llvm.org> Message-ID: <98A02388-43C9-4CD4-AC80-26861E6FA462@apple.com> On Sep 1, 2010, at 8:46 PM, NAKAMURA Takumi wrote: > Author: chapuni > Date: Wed Sep 1 22:46:04 2010 > New Revision: 112803 > > URL: http://llvm.org/viewvc/llvm-project?rev=112803&view=rev > Log: > llvm::FindExecutable(): Retrieve the name with suffix.exe, if available. > > bugpoint uses it. > > Modified: > llvm/trunk/lib/Support/SystemUtils.cpp > > Modified: llvm/trunk/lib/Support/SystemUtils.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/SystemUtils.cpp?rev=112803&r1=112802&r2=112803&view=diff > ============================================================================== > --- llvm/trunk/lib/Support/SystemUtils.cpp (original) > +++ llvm/trunk/lib/Support/SystemUtils.cpp Wed Sep 1 22:46:04 2010 > @@ -49,6 +49,10 @@ > Result.appendComponent(ExeName); > if (Result.canExecute()) > return Result; > + // Expect to retrieve the pathname with suffix .exe. > + Result = sys::Program::FindProgramByName(Result.str()); > + if (!Result.empty()) > + return Result; > } Hello, This changes the semantics of llvm::FindExecutable, which didn't previously look through PATH. I think searching PATH is subtle and dangerous here, because it's not uncommon to have older versions of LLVM tools installed somewhere, and it can be very confusing and frustrating to figure out what's going on when the system is silently falling back to some older program that it happened to be able to find. Is it possible to explicitly add the suffix before the canExecute() test? Dan From dpatel at apple.com Thu Sep 2 11:54:20 2010 From: dpatel at apple.com (Devang Patel) Date: Thu, 2 Sep 2010 09:54:20 -0700 Subject: [llvm-commits] [llvm] r112812 - in /llvm/trunk: lib/VMCore/AsmWriter.cpp test/Transforms/IndVarSimplify/2003-12-10-IndVarDeadCode.ll In-Reply-To: <4C105032-4407-482D-8246-67444396F6B2@apple.com> References: <20100902085223.466DD2A6C12C@llvm.org> <4C105032-4407-482D-8246-67444396F6B2@apple.com> Message-ID: <72F64DB6-7F1F-4A38-B1CA-48A9ADF2B1F4@apple.com> On Sep 2, 2010, at 9:43 AM, Dan Gohman wrote: > Also, in the case of functions with external linkage, the use count > is more misleading than useful, because such functions may have > any number of users outside their module. It would be useful to print use count for functions with internal linkage, at least. > And, the first line of function definitions is already a pretty > crowded place, and it's liable to become more crowded in the future. > > I've actually been considering removing use count printing altogether, Please do not. I use it. > possibly adding an AsmAnnotationWriter for printing use counts as an > option when the information is actually desired. If you want to omit undesired info in your eyes then I'd prefer that you add a option to omit #use count (say -fast-asmwriter :). > > Another possibility is to suppress use counts for single-use > instructions and global values with external linkage. This would > reduce the clutter while still preserving the information that > is useful. That'd be very confusing for instructions. I'll have to guess whether this is single-use instruction or missing use count. It'd be convenient to say "[#uses=unknown]" for global values with external linkage. - Devang From clattner at apple.com Thu Sep 2 12:00:34 2010 From: clattner at apple.com (Chris Lattner) Date: Thu, 2 Sep 2010 10:00:34 -0700 Subject: [llvm-commits] [llvm] r112812 - in /llvm/trunk: lib/VMCore/AsmWriter.cpp test/Transforms/IndVarSimplify/2003-12-10-IndVarDeadCode.ll In-Reply-To: <4C105032-4407-482D-8246-67444396F6B2@apple.com> References: <20100902085223.466DD2A6C12C@llvm.org> <4C105032-4407-482D-8246-67444396F6B2@apple.com> Message-ID: <6AA4D843-C94D-4614-AF59-D34CD911DF7A@apple.com> On Sep 2, 2010, at 9:43 AM, Dan Gohman wrote: > > On Sep 2, 2010, at 1:52 AM, Duncan Sands wrote: > >> Author: baldrick >> Date: Thu Sep 2 03:52:23 2010 >> New Revision: 112812 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=112812&view=rev >> Log: >> Print the number of uses of a function in the .ll since it can be informative >> and there seems to be no reason not to. > > Hi Duncan, > > IMHO, the AsmPrinter should just print the IR. It shouldn't be doing > extra unnecessary analysis (especially not when the analysis has > quadratic worst-case complexity :-}). There has been a fair amount of > confusion from newcomers about whether these numbers are an explicit > part of the IR; they aren't. I agree, to me, this is just clutter. > Another possibility is to suppress use counts for single-use > instructions This sounds like a great idea! -Chris From clattner at apple.com Thu Sep 2 12:02:30 2010 From: clattner at apple.com (Chris Lattner) Date: Thu, 2 Sep 2010 10:02:30 -0700 Subject: [llvm-commits] [llvm] r112830 - in /llvm/trunk: include/llvm/CodeGen/AsmPrinter.h include/llvm/MC/MCAsmInfo.h lib/CodeGen/AsmPrinter/AsmPrinter.cpp lib/CodeGen/AsmPrinter/DwarfDebug.cpp lib/MC/MCAsmInfo.cpp lib/MC/MCAsmInfoDarwin.cpp In-Reply-To: <20100902164344.D7E792A6C12C@llvm.org> References: <20100902164344.D7E792A6C12C@llvm.org> Message-ID: <92C63B71-AC1B-4D4B-970F-9BDA19905361@apple.com> On Sep 2, 2010, at 9:43 AM, Devang Patel wrote: > Author: dpatel > Date: Thu Sep 2 11:43:44 2010 > New Revision: 112830 > > URL: http://llvm.org/viewvc/llvm-project?rev=112830&view=rev > Log: > Fix .debug_range for linux. Patch by Krister Wombell. Thanks Devang, FWIW, I don't think it ever makes sense to use .set here. You can't get an absolute number with LFoo+42, only LFoo-LBar -Chris > > Modified: > llvm/trunk/include/llvm/CodeGen/AsmPrinter.h > llvm/trunk/include/llvm/MC/MCAsmInfo.h > llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp > llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp > llvm/trunk/lib/MC/MCAsmInfo.cpp > llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp > > Modified: llvm/trunk/include/llvm/CodeGen/AsmPrinter.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/AsmPrinter.h?rev=112830&r1=112829&r2=112830&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/CodeGen/AsmPrinter.h (original) > +++ llvm/trunk/include/llvm/CodeGen/AsmPrinter.h Thu Sep 2 11:43:44 2010 > @@ -328,6 +328,12 @@ > void EmitLabelOffsetDifference(const MCSymbol *Hi, uint64_t Offset, > const MCSymbol *Lo, unsigned Size) const; > > + /// EmitLabelPlusOffset - Emit something like ".long Label+Offset" > + /// where the size in bytes of the directive is specified by Size and Label > + /// specifies the label. This implicitly uses .set if it is available. > + void EmitLabelPlusOffset(const MCSymbol *Label, uint64_t Offset, > + unsigned Size) const; > + > //===------------------------------------------------------------------===// > // Dwarf Emission Helper Routines > //===------------------------------------------------------------------===// > > Modified: llvm/trunk/include/llvm/MC/MCAsmInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAsmInfo.h?rev=112830&r1=112829&r2=112830&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/MC/MCAsmInfo.h (original) > +++ llvm/trunk/include/llvm/MC/MCAsmInfo.h Thu Sep 2 11:43:44 2010 > @@ -259,6 +259,10 @@ > /// absolute label instead of offset. > bool DwarfUsesAbsoluteLabelForStmtList; // Defaults to true; > > + // DwarfUsesLabelOffsetDifference - True if Dwarf2 output can > + // use EmitLabelOffsetDifference. > + bool DwarfUsesLabelOffsetForRanges; > + > //===--- CBE Asm Translation Table -----------------------------------===// > > const char *const *AsmTransCBE; // Defaults to empty > @@ -424,6 +428,9 @@ > bool doesDwarfUsesAbsoluteLabelForStmtList() const { > return DwarfUsesAbsoluteLabelForStmtList; > } > + bool doesDwarfUsesLabelOffsetForRanges() const { > + return DwarfUsesLabelOffsetForRanges; > + } > const char *const *getAsmCBE() const { > return AsmTransCBE; > } > > Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=112830&r1=112829&r2=112830&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original) > +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Thu Sep 2 11:43:44 2010 > @@ -1218,6 +1218,29 @@ > OutStreamer.EmitSymbolValue(SetLabel, 4, 0/*AddrSpace*/); > } > } > + > +/// EmitLabelPlusOffset - Emit something like ".long Label+Offset" > +/// where the size in bytes of the directive is specified by Size and Label > +/// specifies the label. This implicitly uses .set if it is available. > +void AsmPrinter::EmitLabelPlusOffset(const MCSymbol *Label, uint64_t Offset, > + unsigned Size) > + const { > + > + // Emit Label+Offset > + const MCExpr *Plus = > + MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(Label, OutContext), > + MCConstantExpr::Create(Offset, OutContext), > + OutContext); > + > + if (!MAI->hasSetDirective()) > + OutStreamer.EmitValue(Plus, 4, 0/*AddrSpace*/); > + else { > + // Otherwise, emit with .set (aka assignment). > + MCSymbol *SetLabel = GetTempSymbol("set", SetCounter++); > + OutStreamer.EmitAssignment(SetLabel, Plus); > + OutStreamer.EmitSymbolValue(SetLabel, 4, 0/*AddrSpace*/); > + } > +} > > > //===----------------------------------------------------------------------===// > > Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=112830&r1=112829&r2=112830&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) > +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Thu Sep 2 11:43:44 2010 > @@ -3130,10 +3130,17 @@ > case dwarf::DW_AT_ranges: { > // DW_AT_range Value encodes offset in debug_range section. > DIEInteger *V = cast(Values[i]); > - Asm->EmitLabelOffsetDifference(DwarfDebugRangeSectionSym, > - V->getValue(), > - DwarfDebugRangeSectionSym, > - 4); > + > + if (Asm->MAI->doesDwarfUsesLabelOffsetForRanges()) { > + Asm->EmitLabelPlusOffset(DwarfDebugRangeSectionSym, > + V->getValue(), > + 4); > + } else { > + Asm->EmitLabelOffsetDifference(DwarfDebugRangeSectionSym, > + V->getValue(), > + DwarfDebugRangeSectionSym, > + 4); > + } > break; > } > case dwarf::DW_AT_location: { > > Modified: llvm/trunk/lib/MC/MCAsmInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmInfo.cpp?rev=112830&r1=112829&r2=112830&view=diff > ============================================================================== > --- llvm/trunk/lib/MC/MCAsmInfo.cpp (original) > +++ llvm/trunk/lib/MC/MCAsmInfo.cpp Thu Sep 2 11:43:44 2010 > @@ -70,6 +70,7 @@ > DwarfUsesInlineInfoSection = false; > DwarfUsesAbsoluteLabelForStmtList = true; > DwarfSectionOffsetDirective = 0; > + DwarfUsesLabelOffsetForRanges = true; > HasMicrosoftFastStdCallMangling = false; > > AsmTransCBE = 0; > > Modified: llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp?rev=112830&r1=112829&r2=112830&view=diff > ============================================================================== > --- llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp (original) > +++ llvm/trunk/lib/MC/MCAsmInfoDarwin.cpp Thu Sep 2 11:43:44 2010 > @@ -46,5 +46,6 @@ > HasNoDeadStrip = true; > > DwarfUsesAbsoluteLabelForStmtList = false; > + DwarfUsesLabelOffsetForRanges = false; > } > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From daniel at zuster.org Thu Sep 2 12:09:09 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 02 Sep 2010 17:09:09 -0000 Subject: [llvm-commits] [test-suite] r112831 - /test-suite/trunk/External/SPEC/CINT2006/464.h264ref/Makefile Message-ID: <20100902170909.0DA612A6C12C@llvm.org> Author: ddunbar Date: Thu Sep 2 12:09:08 2010 New Revision: 112831 URL: http://llvm.org/viewvc/llvm-project?rev=112831&view=rev Log: Bump 464.h264ref timeout, we are pushing the boundary on -O0 builds. Modified: test-suite/trunk/External/SPEC/CINT2006/464.h264ref/Makefile Modified: test-suite/trunk/External/SPEC/CINT2006/464.h264ref/Makefile URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/External/SPEC/CINT2006/464.h264ref/Makefile?rev=112831&r1=112830&r2=112831&view=diff ============================================================================== --- test-suite/trunk/External/SPEC/CINT2006/464.h264ref/Makefile (original) +++ test-suite/trunk/External/SPEC/CINT2006/464.h264ref/Makefile Thu Sep 2 12:09:08 2010 @@ -8,6 +8,9 @@ include ../../Makefile.spec2006 +# This test can take more than the default 500s timeout at -O0. +RUNTIMELIMIT:=750 + ifeq ($(RUN_TYPE),test) RUN_OPTIONS := -d foreman_test_encoder_baseline.cfg STDOUT_FILENAME := foreman_test_baseline_encodelog.out From grosbach at apple.com Thu Sep 2 12:12:55 2010 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 02 Sep 2010 17:12:55 -0000 Subject: [llvm-commits] [llvm] r112832 - in /llvm/trunk/lib/CodeGen: AggressiveAntiDepBreaker.cpp CriticalAntiDepBreaker.cpp Message-ID: <20100902171256.00FFF2A6C12C@llvm.org> Author: grosbach Date: Thu Sep 2 12:12:55 2010 New Revision: 112832 URL: http://llvm.org/viewvc/llvm-project?rev=112832&view=rev Log: Anti-dependency breaking needs to be careful not to use reserved regs Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp?rev=112832&r1=112831&r2=112832&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp (original) +++ llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp Thu Sep 2 12:12:55 2010 @@ -654,6 +654,8 @@ if (R == RB) R = RE; --R; const unsigned NewSuperReg = *R; + // Don't consider non-allocatable registers + if (!AllocatableSet.test(NewSuperReg)) continue; // Don't replace a register with itself. if (NewSuperReg == SuperReg) continue; Modified: llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp?rev=112832&r1=112831&r2=112832&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp (original) +++ llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp Thu Sep 2 12:12:55 2010 @@ -330,6 +330,8 @@ for (TargetRegisterClass::iterator R = RC->allocation_order_begin(MF), RE = RC->allocation_order_end(MF); R != RE; ++R) { unsigned NewReg = *R; + // Don't consider non-allocatable registers + if (!AllocatableSet.test(NewReg)) continue; // Don't replace a register with itself. if (NewReg == AntiDepReg) continue; // Don't replace a register with one that was recently used to repair From baldrick at free.fr Thu Sep 2 12:14:41 2010 From: baldrick at free.fr (Duncan Sands) Date: Thu, 02 Sep 2010 19:14:41 +0200 Subject: [llvm-commits] [llvm-gcc-4.2] r112531 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp In-Reply-To: <142A2E95-68A6-44CE-A3A7-7D43C228DEB1@apple.com> References: <20100830214050.BD6D92A6C12C@llvm.org> <4C7CA267.7030907@free.fr> <142A2E95-68A6-44CE-A3A7-7D43C228DEB1@apple.com> Message-ID: <4C7FDB81.9020105@free.fr> >> which gcc testcase are you referring to? > > gcc.c-torture/execute/builtin-bitops-1.c Thanks Stuart - this also crashes dragonegg :( Ciao, Duncan. From benny.kra at googlemail.com Thu Sep 2 12:18:33 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Thu, 02 Sep 2010 17:18:33 -0000 Subject: [llvm-commits] [llvm] r112834 - /llvm/trunk/lib/MC/MCELFStreamer.cpp Message-ID: <20100902171833.28D4C2A6C12C@llvm.org> Author: d0k Date: Thu Sep 2 12:18:32 2010 New Revision: 112834 URL: http://llvm.org/viewvc/llvm-project?rev=112834&view=rev Log: Allow MCSA_WeakRef in ELF. Patch by Roman Divacky. Modified: llvm/trunk/lib/MC/MCELFStreamer.cpp Modified: llvm/trunk/lib/MC/MCELFStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCELFStreamer.cpp?rev=112834&r1=112833&r2=112834&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCELFStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCELFStreamer.cpp Thu Sep 2 12:18:32 2010 @@ -177,7 +177,6 @@ case MCSA_Reference: case MCSA_NoDeadStrip: case MCSA_PrivateExtern: - case MCSA_WeakReference: case MCSA_WeakDefinition: case MCSA_WeakDefAutoPrivate: case MCSA_Invalid: @@ -191,6 +190,7 @@ SD.setExternal(true); break; + case MCSA_WeakReference: case MCSA_Weak: SD.setFlags(SD.getFlags() | ELF_STB_Weak); break; From gohman at apple.com Thu Sep 2 12:35:11 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 02 Sep 2010 17:35:11 -0000 Subject: [llvm-commits] [llvm] r112836 - /llvm/trunk/include/llvm/System/Path.h Message-ID: <20100902173511.246AE2A6C12C@llvm.org> Author: djg Date: Thu Sep 2 12:35:10 2010 New Revision: 112836 URL: http://llvm.org/viewvc/llvm-project?rev=112836&view=rev Log: Add a comment. Modified: llvm/trunk/include/llvm/System/Path.h Modified: llvm/trunk/include/llvm/System/Path.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/System/Path.h?rev=112836&r1=112835&r2=112836&view=diff ============================================================================== --- llvm/trunk/include/llvm/System/Path.h (original) +++ llvm/trunk/include/llvm/System/Path.h Thu Sep 2 12:35:10 2010 @@ -164,6 +164,7 @@ /// GetMainExecutable - Return the path to the main executable, given the /// value of argv[0] from program startup and the address of main itself. + /// In extremis, this function may fail and return an empty path. static Path GetMainExecutable(const char *argv0, void *MainAddr); /// This is one of the very few ways in which a path can be constructed From stoklund at 2pi.dk Thu Sep 2 12:53:49 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 2 Sep 2010 10:53:49 -0700 Subject: [llvm-commits] [llvm] r112825 - in /llvm/trunk: lib/Target/ARM/ARMExpandPseudoInsts.cpp lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/ARM/ARMInstrNEON.td lib/Target/ARM/NEONPreAllocPass.cpp test/CodeGen/ARM/reg_sequence.ll In-Reply-To: <20100902160054.C5A8F2A6C12C@llvm.org> References: <20100902160054.C5A8F2A6C12C@llvm.org> Message-ID: <92CB5159-37F6-4D6E-9523-53BF295C7FAB@2pi.dk> Hi Bob, On Sep 2, 2010, at 9:00 AM, Bob Wilson wrote: > + MIB.addReg(D0).addReg(D1); > + if (NumRegs > 2) > + MIB.addReg(D2); > + if (NumRegs > 3) > + MIB.addReg(D3); I think you need to add flags here. [...] > + // Add an implicit def for the super-reg. > + MIB.addReg(DstReg, (getDefRegState(true) | getDeadRegState(DstIsDead) | > + getImplRegState(true))); Just like you did here. (Also note that getDefRegState(true) | getImplRegState(true) can be spelled as RegState::ImplicitDefine) This part is tricky, but a sub-register takes precedence over a super-register , so the sub-register is resurrected. See the bottom of RegScavenger::forward(): // Commit the changes. setUnused(KillRegs); setUnused(DeadRegs); setUsed(DefRegs); Same here: void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) { BBInfo &MInfo = MBBInfoMap[MI->getParent()]; set_union(MInfo.regsKilled, regsKilled); set_subtract(regsLive, regsKilled); regsKilled.clear(); set_subtract(regsLive, regsDead); regsDead.clear(); set_union(regsLive, regsDefined); regsDefined.clear(); } In other words, overrides and This instruction: %D0, %D1 = VLD ..., %Q0 Leaves %Q0 dead while subregs %D0 and D1 are live. You want: %D0, %D1 = VLD ..., %Q0 To avoid any zombies. Alternatively, you can use MachineInstr::addRegister{Defined,Dead}(%Q0, TRI, true) which should take care of this, including adding dead flags to the subreg operands. /jakob From stoklund at 2pi.dk Thu Sep 2 13:02:42 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 2 Sep 2010 11:02:42 -0700 Subject: [llvm-commits] [llvm] r112828 - /llvm/trunk/lib/Target/TargetRegisterInfo.cpp In-Reply-To: <20100902163121.B38292A6C12C@llvm.org> References: <20100902163121.B38292A6C12C@llvm.org> Message-ID: On Sep 2, 2010, at 9:31 AM, Jim Grosbach wrote: > Author: grosbach > Date: Thu Sep 2 11:31:21 2010 > New Revision: 112828 > > URL: http://llvm.org/viewvc/llvm-project?rev=112828&view=rev > Log: > Mask out reserved registers when constructing the set of allocatable regs. > > Modified: > llvm/trunk/lib/Target/TargetRegisterInfo.cpp > > Modified: llvm/trunk/lib/Target/TargetRegisterInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetRegisterInfo.cpp?rev=112828&r1=112827&r2=112828&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/TargetRegisterInfo.cpp (original) > +++ llvm/trunk/lib/Target/TargetRegisterInfo.cpp Thu Sep 2 11:31:21 2010 > @@ -80,6 +80,11 @@ > for (TargetRegisterInfo::regclass_iterator I = regclass_begin(), > E = regclass_end(); I != E; ++I) > getAllocatableSetForRC(MF, *I, Allocatable); > + > + // Mask out the reserved registers > + BitVector Reserved = getReservedRegs(MF); > + Allocatable ^= Reserved & Allocatable; > + > return Allocatable; > } Jim, I think you should include the case where RC is non-NULL as well. It is used by AggressiveAntiDepBreaker and SimpleRegisterCoalescing. /jakob From grosbach at apple.com Thu Sep 2 13:14:29 2010 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 02 Sep 2010 18:14:29 -0000 Subject: [llvm-commits] [llvm] r112841 - in /llvm/trunk: lib/Target/ARM/ARMRegisterInfo.td test/CodeGen/ARM/lsr-on-unrolled-loops.ll test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll test/CodeGen/Thumb2/ldr-str-imm12.ll test/CodeGen/Thumb2/lsr-deficiency.ll Message-ID: <20100902181430.083712A6C12C@llvm.org> Author: grosbach Date: Thu Sep 2 13:14:29 2010 New Revision: 112841 URL: http://llvm.org/viewvc/llvm-project?rev=112841&view=rev Log: Now that register allocation properly considers reserved regs, simplify the ARM register class allocation order functions to take advantage of that. Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td llvm/trunk/test/CodeGen/ARM/lsr-on-unrolled-loops.ll llvm/trunk/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll llvm/trunk/test/CodeGen/Thumb2/ldr-str-imm12.ll llvm/trunk/test/CodeGen/Thumb2/lsr-deficiency.ll Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td?rev=112841&r1=112840&r2=112841&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td Thu Sep 2 13:14:29 2010 @@ -220,41 +220,11 @@ iterator allocation_order_end(const MachineFunction &MF) const; }]; let MethodBodies = [{ - // FP is R11, R9 is available. - static const unsigned ARM_GPR_AO_1[] = { + static const unsigned ARM_GPR_AO[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R12,ARM::LR, ARM::R4, ARM::R5, ARM::R6, ARM::R7, - ARM::R8, ARM::R9, ARM::R10, - ARM::R11 }; - // FP is R11, R9 is not available. - static const unsigned ARM_GPR_AO_2[] = { - ARM::R0, ARM::R1, ARM::R2, ARM::R3, - ARM::R12,ARM::LR, - ARM::R4, ARM::R5, ARM::R6, ARM::R7, - ARM::R8, ARM::R10, - ARM::R11 }; - // FP is R7, R9 is available as non-callee-saved register. - // This is used by Darwin. - static const unsigned ARM_GPR_AO_3[] = { - ARM::R0, ARM::R1, ARM::R2, ARM::R3, - ARM::R9, ARM::R12,ARM::LR, - ARM::R4, ARM::R5, ARM::R6, - ARM::R8, ARM::R10,ARM::R11,ARM::R7 }; - // FP is R7, R9 is not available. - static const unsigned ARM_GPR_AO_4[] = { - ARM::R0, ARM::R1, ARM::R2, ARM::R3, - ARM::R12,ARM::LR, - ARM::R4, ARM::R5, ARM::R6, - ARM::R8, ARM::R10,ARM::R11, - ARM::R7 }; - // FP is R7, R9 is available as callee-saved register. - // This is used by non-Darwin platform in Thumb mode. - static const unsigned ARM_GPR_AO_5[] = { - ARM::R0, ARM::R1, ARM::R2, ARM::R3, - ARM::R12,ARM::LR, - ARM::R4, ARM::R5, ARM::R6, - ARM::R8, ARM::R9, ARM::R10,ARM::R11,ARM::R7 }; + ARM::R8, ARM::R9, ARM::R10, ARM::R11 }; // For Thumb1 mode, we don't want to allocate hi regs at all, as we // don't know how to spill them. If we make our prologue/epilogue code @@ -270,48 +240,16 @@ const ARMSubtarget &Subtarget = TM.getSubtarget(); if (Subtarget.isThumb1Only()) return THUMB_GPR_AO; - if (Subtarget.isTargetDarwin()) { - if (Subtarget.isR9Reserved()) - return ARM_GPR_AO_4; - else - return ARM_GPR_AO_3; - } else { - if (Subtarget.isR9Reserved()) - return ARM_GPR_AO_2; - else if (Subtarget.isThumb()) - return ARM_GPR_AO_5; - else - return ARM_GPR_AO_1; - } + return ARM_GPR_AO; } GPRClass::iterator GPRClass::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetRegisterInfo *RI = TM.getRegisterInfo(); const ARMSubtarget &Subtarget = TM.getSubtarget(); - GPRClass::iterator I; - - if (Subtarget.isThumb1Only()) { - I = THUMB_GPR_AO + (sizeof(THUMB_GPR_AO)/sizeof(unsigned)); - return RI->hasFP(MF) ? I-1 : I; - } - - if (Subtarget.isTargetDarwin()) { - if (Subtarget.isR9Reserved()) - I = ARM_GPR_AO_4 + (sizeof(ARM_GPR_AO_4)/sizeof(unsigned)); - else - I = ARM_GPR_AO_3 + (sizeof(ARM_GPR_AO_3)/sizeof(unsigned)); - } else { - if (Subtarget.isR9Reserved()) - I = ARM_GPR_AO_2 + (sizeof(ARM_GPR_AO_2)/sizeof(unsigned)); - else if (Subtarget.isThumb()) - I = ARM_GPR_AO_5 + (sizeof(ARM_GPR_AO_5)/sizeof(unsigned)); - else - I = ARM_GPR_AO_1 + (sizeof(ARM_GPR_AO_1)/sizeof(unsigned)); - } - - return RI->hasFP(MF) ? I-1 : I; + if (Subtarget.isThumb1Only()) + return THUMB_GPR_AO + (sizeof(THUMB_GPR_AO)/sizeof(unsigned)); + return ARM_GPR_AO + (sizeof(ARM_GPR_AO)/sizeof(unsigned)); } }]; } @@ -327,47 +265,18 @@ iterator allocation_order_end(const MachineFunction &MF) const; }]; let MethodBodies = [{ - // FP is R11, R9 is available. - static const unsigned ARM_rGPRAO_1[] = { + static const unsigned ARM_rGPR_AO[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R12,ARM::LR, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11 }; - // FP is R11, R9 is not available. - static const unsigned ARM_rGPRAO_2[] = { - ARM::R0, ARM::R1, ARM::R2, ARM::R3, - ARM::R12,ARM::LR, - ARM::R4, ARM::R5, ARM::R6, ARM::R7, - ARM::R8, ARM::R10, - ARM::R11 }; - // FP is R7, R9 is available as non-callee-saved register. - // This is used by Darwin. - static const unsigned ARM_rGPRAO_3[] = { - ARM::R0, ARM::R1, ARM::R2, ARM::R3, - ARM::R9, ARM::R12,ARM::LR, - ARM::R4, ARM::R5, ARM::R6, - ARM::R8, ARM::R10,ARM::R11,ARM::R7 }; - // FP is R7, R9 is not available. - static const unsigned ARM_rGPRAO_4[] = { - ARM::R0, ARM::R1, ARM::R2, ARM::R3, - ARM::R12,ARM::LR, - ARM::R4, ARM::R5, ARM::R6, - ARM::R8, ARM::R10,ARM::R11, - ARM::R7 }; - // FP is R7, R9 is available as callee-saved register. - // This is used by non-Darwin platform in Thumb mode. - static const unsigned ARM_rGPRAO_5[] = { - ARM::R0, ARM::R1, ARM::R2, ARM::R3, - ARM::R12,ARM::LR, - ARM::R4, ARM::R5, ARM::R6, - ARM::R8, ARM::R9, ARM::R10,ARM::R11,ARM::R7 }; // For Thumb1 mode, we don't want to allocate hi regs at all, as we // don't know how to spill them. If we make our prologue/epilogue code // smarter at some point, we can go back to using the above allocation // orders for the Thumb1 instructions that know how to use hi regs. - static const unsigned THUMB_rGPRAO[] = { + static const unsigned THUMB_rGPR_AO[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7 }; @@ -376,49 +285,18 @@ const TargetMachine &TM = MF.getTarget(); const ARMSubtarget &Subtarget = TM.getSubtarget(); if (Subtarget.isThumb1Only()) - return THUMB_rGPRAO; - if (Subtarget.isTargetDarwin()) { - if (Subtarget.isR9Reserved()) - return ARM_rGPRAO_4; - else - return ARM_rGPRAO_3; - } else { - if (Subtarget.isR9Reserved()) - return ARM_rGPRAO_2; - else if (Subtarget.isThumb()) - return ARM_rGPRAO_5; - else - return ARM_rGPRAO_1; - } + return THUMB_rGPR_AO; + return ARM_rGPR_AO; } rGPRClass::iterator rGPRClass::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetRegisterInfo *RI = TM.getRegisterInfo(); const ARMSubtarget &Subtarget = TM.getSubtarget(); - GPRClass::iterator I; - - if (Subtarget.isThumb1Only()) { - I = THUMB_rGPRAO + (sizeof(THUMB_rGPRAO)/sizeof(unsigned)); - return RI->hasFP(MF) ? I-1 : I; - } - - if (Subtarget.isTargetDarwin()) { - if (Subtarget.isR9Reserved()) - I = ARM_rGPRAO_4 + (sizeof(ARM_rGPRAO_4)/sizeof(unsigned)); - else - I = ARM_rGPRAO_3 + (sizeof(ARM_rGPRAO_3)/sizeof(unsigned)); - } else { - if (Subtarget.isR9Reserved()) - I = ARM_rGPRAO_2 + (sizeof(ARM_rGPRAO_2)/sizeof(unsigned)); - else if (Subtarget.isThumb()) - I = ARM_rGPRAO_5 + (sizeof(ARM_rGPRAO_5)/sizeof(unsigned)); - else - I = ARM_rGPRAO_1 + (sizeof(ARM_rGPRAO_1)/sizeof(unsigned)); - } - return RI->hasFP(MF) ? I-1 : I; + if (Subtarget.isThumb1Only()) + return THUMB_rGPR_AO + (sizeof(THUMB_rGPR_AO)/sizeof(unsigned)); + return ARM_rGPR_AO + (sizeof(ARM_rGPR_AO)/sizeof(unsigned)); } }]; } @@ -459,34 +337,20 @@ const ARMSubtarget &Subtarget = TM.getSubtarget(); if (Subtarget.isThumb1Only()) return THUMB_GPR_AO_TC; - if (Subtarget.isTargetDarwin()) { - if (Subtarget.isR9Reserved()) - return ARM_GPR_NOR9_TC; - else - return ARM_GPR_R9_TC; - } else - // R9 is either callee-saved or reserved; can't use it. - return ARM_GPR_NOR9_TC; + return Subtarget.isTargetDarwin() ? ARM_GPR_R9_TC : ARM_GPR_NOR9_TC; } tcGPRClass::iterator tcGPRClass::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); const ARMSubtarget &Subtarget = TM.getSubtarget(); - GPRClass::iterator I; if (Subtarget.isThumb1Only()) return THUMB_GPR_AO_TC + (sizeof(THUMB_GPR_AO_TC)/sizeof(unsigned)); - if (Subtarget.isTargetDarwin()) { - if (Subtarget.isR9Reserved()) - I = ARM_GPR_NOR9_TC + (sizeof(ARM_GPR_NOR9_TC)/sizeof(unsigned)); - else - I = ARM_GPR_R9_TC + (sizeof(ARM_GPR_R9_TC)/sizeof(unsigned)); - } else - // R9 is either callee-saved or reserved; can't use it. - I = ARM_GPR_NOR9_TC + (sizeof(ARM_GPR_NOR9_TC)/sizeof(unsigned)); - return I; + return Subtarget.isTargetDarwin() ? + ARM_GPR_R9_TC + (sizeof(ARM_GPR_R9_TC)/sizeof(unsigned)) : + ARM_GPR_NOR9_TC + (sizeof(ARM_GPR_NOR9_TC)/sizeof(unsigned)); } }]; } Modified: llvm/trunk/test/CodeGen/ARM/lsr-on-unrolled-loops.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/lsr-on-unrolled-loops.ll?rev=112841&r1=112840&r2=112841&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/lsr-on-unrolled-loops.ll (original) +++ llvm/trunk/test/CodeGen/ARM/lsr-on-unrolled-loops.ll Thu Sep 2 13:14:29 2010 @@ -628,7 +628,7 @@ ; CHECK: @ %bb24 ; CHECK-NEXT: @ in Loop: Header=BB1_1 Depth=1 -; CHECK-NEXT: sub{{.*}} [[REGISTER:r[0-9]+]], #1 +; CHECK-NEXT: sub{{.*}} [[REGISTER:(r[0-9]+)|(lr)]], #1 ; CHECK-NEXT: bne.w %92 = icmp eq i32 %tmp81, %indvar78 ; [#uses=1] Modified: llvm/trunk/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll?rev=112841&r1=112840&r2=112841&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll Thu Sep 2 13:14:29 2010 @@ -11,8 +11,8 @@ define weak arm_aapcs_vfpcc i32 @_ZNKSs7compareERKSs(%"struct.std::basic_string,std::allocator >"* %this, %"struct.std::basic_string,std::allocator >"* %__str) { ; CHECK: _ZNKSs7compareERKSs: ; CHECK: it eq -; CHECK-NEXT: subeq.w r0, r6, r8 -; CHECK-NEXT: ldmia.w sp!, {r4, r5, r6, r8, r9, pc} +; CHECK-NEXT: subeq r0, r6, r7 +; CHECK-NEXT: ldmia.w sp!, {r4, r5, r6, r7, r8, pc} entry: %0 = tail call arm_aapcs_vfpcc i32 @_ZNKSs4sizeEv(%"struct.std::basic_string,std::allocator >"* %this) ; [#uses=3] %1 = tail call arm_aapcs_vfpcc i32 @_ZNKSs4sizeEv(%"struct.std::basic_string,std::allocator >"* %__str) ; [#uses=3] Modified: llvm/trunk/test/CodeGen/Thumb2/ldr-str-imm12.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/ldr-str-imm12.ll?rev=112841&r1=112840&r2=112841&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/ldr-str-imm12.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/ldr-str-imm12.ll Thu Sep 2 13:14:29 2010 @@ -22,7 +22,7 @@ define %union.rec* @Manifest(%union.rec* %x, %union.rec* %env, %struct.STYLE* %style, %union.rec** %bthr, %union.rec** %fthr, %union.rec** %target, %union.rec** %crs, i32 %ok, i32 %need_expand, %union.rec** %enclose, i32 %fcr) nounwind { entry: -; CHECK: ldr.w r9, [r7, #28] +; CHECK: ldr.w {{(r[0-9])|(lr)}}, [r7, #28] %xgaps.i = alloca [32 x %union.rec*], align 4 ; <[32 x %union.rec*]*> [#uses=0] %ycomp.i = alloca [32 x %union.rec*], align 4 ; <[32 x %union.rec*]*> [#uses=0] br label %bb20 @@ -46,9 +46,9 @@ bb420: ; preds = %bb20, %bb20 ; CHECK: bb420 -; CHECK: str r{{[0-7]}}, [sp] -; CHECK: str r{{[0-7]}}, [sp, #4] -; CHECK: str r{{[0-7]}}, [sp, #8] +; CHECK: str{{(.w)?}} r{{[0-9]+}}, [sp] +; CHECK: str{{(.w)?}} r{{[0-9]+}}, [sp, #4] +; CHECK: str{{(.w)?}} r{{[0-9]+}}, [sp, #8] ; CHECK: str{{(.w)?}} r{{[0-9]+}}, [sp, #24] store %union.rec* null, %union.rec** @zz_hold, align 4 store %union.rec* null, %union.rec** @zz_res, align 4 Modified: llvm/trunk/test/CodeGen/Thumb2/lsr-deficiency.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/lsr-deficiency.ll?rev=112841&r1=112840&r2=112841&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/lsr-deficiency.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/lsr-deficiency.ll Thu Sep 2 13:14:29 2010 @@ -21,8 +21,8 @@ bb: ; preds = %bb, %entry ; CHECK: LBB0_1: ; CHECK: cmp r2, #0 -; CHECK: sub.w r9, r2, #1 -; CHECK: mov r2, r9 +; CHECK: sub{{(.w)?}} [[REGISTER:(r[0-9]+)|(lr)]], r2, #1 +; CHECK: mov r2, [[REGISTER]] %0 = phi i32 [ %.pre, %entry ], [ %3, %bb ] ; [#uses=1] %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; [#uses=2] From grosbach at apple.com Thu Sep 2 13:18:52 2010 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 02 Sep 2010 18:18:52 -0000 Subject: [llvm-commits] [llvm] r112842 - /llvm/trunk/lib/Target/TargetRegisterInfo.cpp Message-ID: <20100902181852.482BA2A6C12C@llvm.org> Author: grosbach Date: Thu Sep 2 13:18:52 2010 New Revision: 112842 URL: http://llvm.org/viewvc/llvm-project?rev=112842&view=rev Log: handle case where a register class is specified Modified: llvm/trunk/lib/Target/TargetRegisterInfo.cpp Modified: llvm/trunk/lib/Target/TargetRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetRegisterInfo.cpp?rev=112842&r1=112841&r2=112842&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/TargetRegisterInfo.cpp Thu Sep 2 13:18:52 2010 @@ -74,12 +74,11 @@ BitVector Allocatable(NumRegs); if (RC) { getAllocatableSetForRC(MF, RC, Allocatable); - return Allocatable; - } - - for (TargetRegisterInfo::regclass_iterator I = regclass_begin(), + } else { + for (TargetRegisterInfo::regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I) - getAllocatableSetForRC(MF, *I, Allocatable); + getAllocatableSetForRC(MF, *I, Allocatable); + } // Mask out the reserved registers BitVector Reserved = getReservedRegs(MF); From grosbach at apple.com Thu Sep 2 13:19:58 2010 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 2 Sep 2010 11:19:58 -0700 Subject: [llvm-commits] [llvm] r112828 - /llvm/trunk/lib/Target/TargetRegisterInfo.cpp In-Reply-To: References: <20100902163121.B38292A6C12C@llvm.org> Message-ID: <94CFB921-BA22-42D6-9AB6-4BC2BB8715C0@apple.com> Quite right. r112842. On Sep 2, 2010, at 11:02 AM, Jakob Stoklund Olesen wrote: > > On Sep 2, 2010, at 9:31 AM, Jim Grosbach wrote: > >> Author: grosbach >> Date: Thu Sep 2 11:31:21 2010 >> New Revision: 112828 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=112828&view=rev >> Log: >> Mask out reserved registers when constructing the set of allocatable regs. >> >> Modified: >> llvm/trunk/lib/Target/TargetRegisterInfo.cpp >> >> Modified: llvm/trunk/lib/Target/TargetRegisterInfo.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetRegisterInfo.cpp?rev=112828&r1=112827&r2=112828&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/TargetRegisterInfo.cpp (original) >> +++ llvm/trunk/lib/Target/TargetRegisterInfo.cpp Thu Sep 2 11:31:21 2010 >> @@ -80,6 +80,11 @@ >> for (TargetRegisterInfo::regclass_iterator I = regclass_begin(), >> E = regclass_end(); I != E; ++I) >> getAllocatableSetForRC(MF, *I, Allocatable); >> + >> + // Mask out the reserved registers >> + BitVector Reserved = getReservedRegs(MF); >> + Allocatable ^= Reserved & Allocatable; >> + >> return Allocatable; >> } > > Jim, > > I think you should include the case where RC is non-NULL as well. It is used by AggressiveAntiDepBreaker and SimpleRegisterCoalescing. > > /jakob > From resistor at mac.com Thu Sep 2 13:23:58 2010 From: resistor at mac.com (Owen Anderson) Date: Thu, 02 Sep 2010 18:23:58 -0000 Subject: [llvm-commits] [llvm] r112843 - in /llvm/trunk: lib/Analysis/LazyValueInfo.cpp test/Transforms/CorrelatedValuePropagation/2010-09-02-Trunc.ll Message-ID: <20100902182358.DA0F82A6C12C@llvm.org> Author: resistor Date: Thu Sep 2 13:23:58 2010 New Revision: 112843 URL: http://llvm.org/viewvc/llvm-project?rev=112843&view=rev Log: Fix a bug in LazyValueInfo that CorrelatedValuePropagation exposed: In the LVI lattice, undef and the full set ConstantRange should not be treated as equivalent. Added: llvm/trunk/test/Transforms/CorrelatedValuePropagation/2010-09-02-Trunc.ll Modified: llvm/trunk/lib/Analysis/LazyValueInfo.cpp Modified: llvm/trunk/lib/Analysis/LazyValueInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/LazyValueInfo.cpp?rev=112843&r1=112842&r2=112843&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/LazyValueInfo.cpp (original) +++ llvm/trunk/lib/Analysis/LazyValueInfo.cpp Thu Sep 2 13:23:58 2010 @@ -173,10 +173,6 @@ assert(isUndefined()); if (NewR.isEmptySet()) return markOverdefined(); - else if (NewR.isFullSet()) { - Tag = undefined; - return true; - } Tag = constantrange; Range = NewR; Added: llvm/trunk/test/Transforms/CorrelatedValuePropagation/2010-09-02-Trunc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/CorrelatedValuePropagation/2010-09-02-Trunc.ll?rev=112843&view=auto ============================================================================== --- llvm/trunk/test/Transforms/CorrelatedValuePropagation/2010-09-02-Trunc.ll (added) +++ llvm/trunk/test/Transforms/CorrelatedValuePropagation/2010-09-02-Trunc.ll Thu Sep 2 13:23:58 2010 @@ -0,0 +1,25 @@ +; RUN: opt -S < %s -correlated-propagation | FileCheck %s + +; CHECK: @check +define i16 @test(i32 %a, i1 %b) { +entry: + %c = icmp eq i32 %a, 0 + br i1 %c, label %left, label %right + +right: + %d = trunc i32 %a to i1 + br label %merge + +left: + br i1 %b, label %merge, label %other + +other: + ret i16 23 + +merge: + %f = phi i1 [%b, %left], [%d, %right] +; CHECK: select i1 %f, i16 1, i16 0 + %h = select i1 %f, i16 1, i16 0 +; CHECK: ret i16 %h + ret i16 %h +} \ No newline at end of file From gohman at apple.com Thu Sep 2 13:24:46 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 02 Sep 2010 18:24:46 -0000 Subject: [llvm-commits] [llvm] r112844 - /llvm/trunk/lib/System/Unix/Path.inc Message-ID: <20100902182446.5AC072A6C12C@llvm.org> Author: djg Date: Thu Sep 2 13:24:46 2010 New Revision: 112844 URL: http://llvm.org/viewvc/llvm-project?rev=112844&view=rev Log: Apply a patch from Kees van Reeuwijk to add support for Minix. Minix apparently doesn't like double-slash separators, and there's no apparent need for them here. Modified: llvm/trunk/lib/System/Unix/Path.inc Modified: llvm/trunk/lib/System/Unix/Path.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Unix/Path.inc?rev=112844&r1=112843&r2=112844&view=diff ============================================================================== --- llvm/trunk/lib/System/Unix/Path.inc (original) +++ llvm/trunk/lib/System/Unix/Path.inc Thu Sep 2 13:24:46 2010 @@ -282,14 +282,14 @@ return Path(pathname); } -#if defined(__FreeBSD__) || defined (__NetBSD__) +#if defined(__FreeBSD__) || defined (__NetBSD__) || defined(__minix) static int test_dir(char buf[PATH_MAX], char ret[PATH_MAX], const char *dir, const char *bin) { struct stat sb; - snprintf(buf, PATH_MAX, "%s//%s", dir, bin); + snprintf(buf, PATH_MAX, "%s/%s", dir, bin); if (realpath(buf, ret) == NULL) return (1); if (stat(buf, &sb) != 0) @@ -350,7 +350,7 @@ if (realpath(exe_path, link_path)) return Path(std::string(link_path)); } -#elif defined(__FreeBSD__) || defined (__NetBSD__) +#elif defined(__FreeBSD__) || defined (__NetBSD__) || defined(__minix) char exe_path[PATH_MAX]; if (getprogpath(exe_path, argv0) != NULL) From stoklund at 2pi.dk Thu Sep 2 13:28:22 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 2 Sep 2010 11:28:22 -0700 Subject: [llvm-commits] [llvm] r112841 - in /llvm/trunk: lib/Target/ARM/ARMRegisterInfo.td test/CodeGen/ARM/lsr-on-unrolled-loops.ll test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll test/CodeGen/Thumb2/ldr-str-imm12.ll test/CodeGen/Thumb2/lsr-deficiency.ll In-Reply-To: <20100902181430.083712A6C12C@llvm.org> References: <20100902181430.083712A6C12C@llvm.org> Message-ID: <9F327C4D-3600-459C-AB1A-5574BC647617@2pi.dk> On Sep 2, 2010, at 11:14 AM, Jim Grosbach wrote: > Author: grosbach > Date: Thu Sep 2 13:14:29 2010 > New Revision: 112841 > > URL: http://llvm.org/viewvc/llvm-project?rev=112841&view=rev > Log: > Now that register allocation properly considers reserved regs, simplify the > ARM register class allocation order functions to take advantage of that. Yay for minusses! But shouldn't register allocation be unaffected? > Modified: > llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td > llvm/trunk/test/CodeGen/ARM/lsr-on-unrolled-loops.ll > llvm/trunk/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll > llvm/trunk/test/CodeGen/Thumb2/ldr-str-imm12.ll > llvm/trunk/test/CodeGen/Thumb2/lsr-deficiency.ll From grosbach at apple.com Thu Sep 2 13:29:04 2010 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 02 Sep 2010 18:29:04 -0000 Subject: [llvm-commits] [llvm] r112845 - /llvm/trunk/lib/CodeGen/RegisterScavenging.cpp Message-ID: <20100902182904.62E942A6C12C@llvm.org> Author: grosbach Date: Thu Sep 2 13:29:04 2010 New Revision: 112845 URL: http://llvm.org/viewvc/llvm-project?rev=112845&view=rev Log: The scavenger should just use getAllocatableSet() rather than reinventing it locally. Modified: llvm/trunk/lib/CodeGen/RegisterScavenging.cpp Modified: llvm/trunk/lib/CodeGen/RegisterScavenging.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterScavenging.cpp?rev=112845&r1=112844&r2=112845&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegisterScavenging.cpp (original) +++ llvm/trunk/lib/CodeGen/RegisterScavenging.cpp Thu Sep 2 13:29:04 2010 @@ -228,14 +228,6 @@ used = ~RegsAvailable & ~ReservedRegs; } -/// CreateRegClassMask - Set the bits that represent the registers in the -/// TargetRegisterClass. -static void CreateRegClassMask(const TargetRegisterClass *RC, BitVector &Mask) { - for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I != E; - ++I) - Mask.set(*I); -} - unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const { for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I != E; ++I) @@ -330,11 +322,9 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC, MachineBasicBlock::iterator I, int SPAdj) { - // Mask off the registers which are not in the TargetRegisterClass. - BitVector Candidates(NumPhysRegs, false); - CreateRegClassMask(RC, Candidates); - // Do not include reserved registers. - Candidates ^= ReservedRegs & Candidates; + // Consider all allocatable registers in the register class initially + BitVector Candidates = + TRI->getAllocatableSet(*I->getParent()->getParent(), RC); // Exclude all the registers being used by the instruction. for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) { From echristo at apple.com Thu Sep 2 13:30:05 2010 From: echristo at apple.com (Eric Christopher) Date: Thu, 2 Sep 2010 11:30:05 -0700 Subject: [llvm-commits] [llvm] r112719 - in /llvm/trunk: include/llvm/Transforms/Utils/SSAUpdater.h lib/CodeGen/DwarfEHPrepare.cpp lib/Transforms/Scalar/GVN.cpp lib/Transforms/Scalar/JumpThreading.cpp lib/Transforms/Scalar/LICM.cpp lib/Transforms/Scalar/LoopRotation.cpp lib/Transforms/Utils/LCSSA.cpp lib/Transforms/Utils/SSAUpdater.cpp In-Reply-To: <4C7F5E5C.6060805@free.fr> References: <20100901172910.55FF52A6C12C@llvm.org> <4C7F5E5C.6060805@free.fr> Message-ID: <99AD106D-5C79-40E2-B693-E810CCAE20F3@apple.com> On Sep 2, 2010, at 1:20 AM, Duncan Sands wrote: > Hi Eric, > >> Speculatively revert 112699 and 112702, they seem to be causing >> self host errors on clang-x86-64. > > I've reapplied 112699 since it should be harmless. Once the dust settles I > will probably reapply 112702 since I didn't yet spot anything wrong with it. Yeah, I think you're good. Thanks for the patience! -eric From grosbach at apple.com Thu Sep 2 13:33:11 2010 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 2 Sep 2010 11:33:11 -0700 Subject: [llvm-commits] [llvm] r112841 - in /llvm/trunk: lib/Target/ARM/ARMRegisterInfo.td test/CodeGen/ARM/lsr-on-unrolled-loops.ll test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll test/CodeGen/Thumb2/ldr-str-imm12.ll test/CodeGen/Thumb2/lsr-deficiency.ll In-Reply-To: <9F327C4D-3600-459C-AB1A-5574BC647617@2pi.dk> References: <20100902181430.083712A6C12C@llvm.org> <9F327C4D-3600-459C-AB1A-5574BC647617@2pi.dk> Message-ID: <39D9994E-4D97-4E2B-9EC1-8ADB6E712ED6@apple.com> On Sep 2, 2010, at 11:28 AM, Jakob Stoklund Olesen wrote: > > On Sep 2, 2010, at 11:14 AM, Jim Grosbach wrote: > >> Author: grosbach >> Date: Thu Sep 2 13:14:29 2010 >> New Revision: 112841 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=112841&view=rev >> Log: >> Now that register allocation properly considers reserved regs, simplify the >> ARM register class allocation order functions to take advantage of that. > > Yay for minusses! Absolutely! diffstat says: 5 files changed, 26 insertions(+), 162 deletions(-) Gotta love it. > > But shouldn't register allocation be unaffected? > The old allocation orders did things like putting R7/R11 (frame pointer) at the end of the order artificially so they could manipulate the end() iterator easily. That's no longer necessary, and as a result, there are some changes to which registers get allocated here and there. >> Modified: >> llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td >> llvm/trunk/test/CodeGen/ARM/lsr-on-unrolled-loops.ll >> llvm/trunk/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll >> llvm/trunk/test/CodeGen/Thumb2/ldr-str-imm12.ll >> llvm/trunk/test/CodeGen/Thumb2/lsr-deficiency.ll > > From bruno.cardoso at gmail.com Thu Sep 2 13:40:13 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Thu, 02 Sep 2010 18:40:13 -0000 Subject: [llvm-commits] [llvm] r112846 - in /llvm/trunk/lib/Target/X86: AsmPrinter/X86InstComments.cpp X86ShuffleDecode.h Message-ID: <20100902184013.B785C2A6C12C@llvm.org> Author: bruno Date: Thu Sep 2 13:40:13 2010 New Revision: 112846 URL: http://llvm.org/viewvc/llvm-project?rev=112846&view=rev Log: Move x86 specific shuffle mask decoding to its own header, it's also going to be used elsewhere. Also trim trailing whitespaces Added: llvm/trunk/lib/Target/X86/X86ShuffleDecode.h Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86InstComments.cpp Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86InstComments.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86InstComments.cpp?rev=112846&r1=112845&r2=112846&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmPrinter/X86InstComments.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86InstComments.cpp Thu Sep 2 13:40:13 2010 @@ -16,137 +16,13 @@ #include "X86GenInstrNames.inc" #include "llvm/MC/MCInst.h" #include "llvm/Support/raw_ostream.h" +#include "../X86ShuffleDecode.h" using namespace llvm; //===----------------------------------------------------------------------===// -// Vector Mask Decoding -//===----------------------------------------------------------------------===// - -enum { - SM_SentinelZero = ~0U -}; - -static void DecodeINSERTPSMask(unsigned Imm, - SmallVectorImpl &ShuffleMask) { - // Defaults the copying the dest value. - ShuffleMask.push_back(0); - ShuffleMask.push_back(1); - ShuffleMask.push_back(2); - ShuffleMask.push_back(3); - - // Decode the immediate. - unsigned ZMask = Imm & 15; - unsigned CountD = (Imm >> 4) & 3; - unsigned CountS = (Imm >> 6) & 3; - - // CountS selects which input element to use. - unsigned InVal = 4+CountS; - // CountD specifies which element of destination to update. - ShuffleMask[CountD] = InVal; - // ZMask zaps values, potentially overriding the CountD elt. - if (ZMask & 1) ShuffleMask[0] = SM_SentinelZero; - if (ZMask & 2) ShuffleMask[1] = SM_SentinelZero; - if (ZMask & 4) ShuffleMask[2] = SM_SentinelZero; - if (ZMask & 8) ShuffleMask[3] = SM_SentinelZero; -} - -static void DecodeMOVHLPSMask(SmallVectorImpl &ShuffleMask) { - ShuffleMask.push_back(3); - ShuffleMask.push_back(1); -} - -static void DecodeMOVLHPSMask(SmallVectorImpl &ShuffleMask) { - ShuffleMask.push_back(0); - ShuffleMask.push_back(2); -} - -static void DecodePSHUFMask(unsigned NElts, unsigned Imm, - SmallVectorImpl &ShuffleMask) { - for (unsigned i = 0; i != NElts; ++i) { - ShuffleMask.push_back(Imm % NElts); - Imm /= NElts; - } -} - -static void DecodePSHUFHWMask(unsigned Imm, - SmallVectorImpl &ShuffleMask) { - ShuffleMask.push_back(0); - ShuffleMask.push_back(1); - ShuffleMask.push_back(2); - ShuffleMask.push_back(3); - for (unsigned i = 0; i != 4; ++i) { - ShuffleMask.push_back(4+(Imm & 3)); - Imm >>= 2; - } -} - -static void DecodePSHUFLWMask(unsigned Imm, - SmallVectorImpl &ShuffleMask) { - for (unsigned i = 0; i != 4; ++i) { - ShuffleMask.push_back((Imm & 3)); - Imm >>= 2; - } - ShuffleMask.push_back(4); - ShuffleMask.push_back(5); - ShuffleMask.push_back(6); - ShuffleMask.push_back(7); -} - -static void DecodePUNPCKLMask(unsigned NElts, - SmallVectorImpl &ShuffleMask) { - for (unsigned i = 0; i != NElts/2; ++i) { - ShuffleMask.push_back(i); - ShuffleMask.push_back(i+NElts); - } -} - -static void DecodePUNPCKHMask(unsigned NElts, - SmallVectorImpl &ShuffleMask) { - for (unsigned i = 0; i != NElts/2; ++i) { - ShuffleMask.push_back(i+NElts/2); - ShuffleMask.push_back(i+NElts+NElts/2); - } -} - -static void DecodeSHUFPSMask(unsigned NElts, unsigned Imm, - SmallVectorImpl &ShuffleMask) { - // Part that reads from dest. - for (unsigned i = 0; i != NElts/2; ++i) { - ShuffleMask.push_back(Imm % NElts); - Imm /= NElts; - } - // Part that reads from src. - for (unsigned i = 0; i != NElts/2; ++i) { - ShuffleMask.push_back(Imm % NElts + NElts); - Imm /= NElts; - } -} - -static void DecodeUNPCKHPMask(unsigned NElts, - SmallVectorImpl &ShuffleMask) { - for (unsigned i = 0; i != NElts/2; ++i) { - ShuffleMask.push_back(i+NElts/2); // Reads from dest - ShuffleMask.push_back(i+NElts+NElts/2); // Reads from src - } -} - - -/// DecodeUNPCKLPMask - This decodes the shuffle masks for unpcklps/unpcklpd -/// etc. NElts indicates the number of elements in the vector allowing it to -/// handle different datatypes and vector widths. -static void DecodeUNPCKLPMask(unsigned NElts, - SmallVectorImpl &ShuffleMask) { - for (unsigned i = 0; i != NElts/2; ++i) { - ShuffleMask.push_back(i); // Reads from dest - ShuffleMask.push_back(i+NElts); // Reads from src - } -} - -//===----------------------------------------------------------------------===// // Top Level Entrypoint //===----------------------------------------------------------------------===// - /// EmitAnyX86InstComments - This function decodes x86 instructions and prints /// newline terminated strings to the specified string if desired. This /// information is shown in disassembly dumps when verbose assembly is enabled. @@ -155,26 +31,26 @@ // If this is a shuffle operation, the switch should fill in this state. SmallVector ShuffleMask; const char *DestName = 0, *Src1Name = 0, *Src2Name = 0; - + switch (MI->getOpcode()) { case X86::INSERTPSrr: Src1Name = getRegName(MI->getOperand(1).getReg()); Src2Name = getRegName(MI->getOperand(2).getReg()); DecodeINSERTPSMask(MI->getOperand(3).getImm(), ShuffleMask); break; - + case X86::MOVLHPSrr: Src2Name = getRegName(MI->getOperand(2).getReg()); Src1Name = getRegName(MI->getOperand(0).getReg()); DecodeMOVLHPSMask(ShuffleMask); break; - + case X86::MOVHLPSrr: Src2Name = getRegName(MI->getOperand(2).getReg()); Src1Name = getRegName(MI->getOperand(0).getReg()); DecodeMOVHLPSMask(ShuffleMask); break; - + case X86::PSHUFDri: Src1Name = getRegName(MI->getOperand(1).getReg()); // FALL THROUGH. @@ -183,7 +59,7 @@ DecodePSHUFMask(4, MI->getOperand(MI->getNumOperands()-1).getImm(), ShuffleMask); break; - + case X86::PSHUFHWri: Src1Name = getRegName(MI->getOperand(1).getReg()); // FALL THROUGH. @@ -200,7 +76,7 @@ DecodePSHUFLWMask(MI->getOperand(MI->getNumOperands()-1).getImm(), ShuffleMask); break; - + case X86::PUNPCKHBWrr: Src2Name = getRegName(MI->getOperand(2).getReg()); // FALL THROUGH. @@ -229,7 +105,7 @@ Src1Name = getRegName(MI->getOperand(0).getReg()); DecodePUNPCKHMask(2, ShuffleMask); break; - + case X86::PUNPCKLBWrr: Src2Name = getRegName(MI->getOperand(2).getReg()); // FALL THROUGH. @@ -258,13 +134,13 @@ Src1Name = getRegName(MI->getOperand(0).getReg()); DecodePUNPCKLMask(2, ShuffleMask); break; - + case X86::SHUFPDrri: DecodeSHUFPSMask(2, MI->getOperand(3).getImm(), ShuffleMask); Src1Name = getRegName(MI->getOperand(0).getReg()); Src2Name = getRegName(MI->getOperand(2).getReg()); break; - + case X86::SHUFPSrri: Src2Name = getRegName(MI->getOperand(2).getReg()); // FALL THROUGH. @@ -272,7 +148,7 @@ DecodeSHUFPSMask(4, MI->getOperand(3).getImm(), ShuffleMask); Src1Name = getRegName(MI->getOperand(0).getReg()); break; - + case X86::UNPCKLPDrr: Src2Name = getRegName(MI->getOperand(2).getReg()); // FALL THROUGH. @@ -303,12 +179,12 @@ break; } - + // If this was a shuffle operation, print the shuffle mask. if (!ShuffleMask.empty()) { if (DestName == 0) DestName = Src1Name; OS << (DestName ? DestName : "mem") << " = "; - + // If the two sources are the same, canonicalize the input elements to be // from the first src so that we get larger element spans. if (Src1Name == Src2Name) { @@ -318,7 +194,7 @@ ShuffleMask[i] -= e; } } - + // The shuffle mask specifies which elements of the src1/src2 fill in the // destination, with a few sentinel values. Loop through and print them // out. @@ -329,7 +205,7 @@ OS << "zero"; continue; } - + // Otherwise, it must come from src1 or src2. Print the span of elements // that comes from this src. bool isSrc1 = ShuffleMask[i] < ShuffleMask.size(); @@ -352,5 +228,5 @@ //MI->print(OS, 0); OS << "\n"; } - + } Added: llvm/trunk/lib/Target/X86/X86ShuffleDecode.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ShuffleDecode.h?rev=112846&view=auto ============================================================================== --- llvm/trunk/lib/Target/X86/X86ShuffleDecode.h (added) +++ llvm/trunk/lib/Target/X86/X86ShuffleDecode.h Thu Sep 2 13:40:13 2010 @@ -0,0 +1,145 @@ +//===-- X86ShuffleDecode.h - X86 shuffle decode logic ---------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// Define several functions to decode x86 specific shuffle semantics into a +// generic vector mask. +// +//===----------------------------------------------------------------------===// + +#ifndef X86_SHUFFLE_DECODE_H +#define X86_SHUFFLE_DECODE_H + +#include "llvm/ADT/SmallVector.h" +using namespace llvm; + +//===----------------------------------------------------------------------===// +// Vector Mask Decoding +//===----------------------------------------------------------------------===// + +enum { + SM_SentinelZero = ~0U +}; + +static void DecodeINSERTPSMask(unsigned Imm, + SmallVectorImpl &ShuffleMask) { + // Defaults the copying the dest value. + ShuffleMask.push_back(0); + ShuffleMask.push_back(1); + ShuffleMask.push_back(2); + ShuffleMask.push_back(3); + + // Decode the immediate. + unsigned ZMask = Imm & 15; + unsigned CountD = (Imm >> 4) & 3; + unsigned CountS = (Imm >> 6) & 3; + + // CountS selects which input element to use. + unsigned InVal = 4+CountS; + // CountD specifies which element of destination to update. + ShuffleMask[CountD] = InVal; + // ZMask zaps values, potentially overriding the CountD elt. + if (ZMask & 1) ShuffleMask[0] = SM_SentinelZero; + if (ZMask & 2) ShuffleMask[1] = SM_SentinelZero; + if (ZMask & 4) ShuffleMask[2] = SM_SentinelZero; + if (ZMask & 8) ShuffleMask[3] = SM_SentinelZero; +} + +static void DecodeMOVHLPSMask(SmallVectorImpl &ShuffleMask) { + ShuffleMask.push_back(3); + ShuffleMask.push_back(1); +} + +static void DecodeMOVLHPSMask(SmallVectorImpl &ShuffleMask) { + ShuffleMask.push_back(0); + ShuffleMask.push_back(2); +} + +static void DecodePSHUFMask(unsigned NElts, unsigned Imm, + SmallVectorImpl &ShuffleMask) { + for (unsigned i = 0; i != NElts; ++i) { + ShuffleMask.push_back(Imm % NElts); + Imm /= NElts; + } +} + +static void DecodePSHUFHWMask(unsigned Imm, + SmallVectorImpl &ShuffleMask) { + ShuffleMask.push_back(0); + ShuffleMask.push_back(1); + ShuffleMask.push_back(2); + ShuffleMask.push_back(3); + for (unsigned i = 0; i != 4; ++i) { + ShuffleMask.push_back(4+(Imm & 3)); + Imm >>= 2; + } +} + +static void DecodePSHUFLWMask(unsigned Imm, + SmallVectorImpl &ShuffleMask) { + for (unsigned i = 0; i != 4; ++i) { + ShuffleMask.push_back((Imm & 3)); + Imm >>= 2; + } + ShuffleMask.push_back(4); + ShuffleMask.push_back(5); + ShuffleMask.push_back(6); + ShuffleMask.push_back(7); +} + +static void DecodePUNPCKLMask(unsigned NElts, + SmallVectorImpl &ShuffleMask) { + for (unsigned i = 0; i != NElts/2; ++i) { + ShuffleMask.push_back(i); + ShuffleMask.push_back(i+NElts); + } +} + +static void DecodePUNPCKHMask(unsigned NElts, + SmallVectorImpl &ShuffleMask) { + for (unsigned i = 0; i != NElts/2; ++i) { + ShuffleMask.push_back(i+NElts/2); + ShuffleMask.push_back(i+NElts+NElts/2); + } +} + +static void DecodeSHUFPSMask(unsigned NElts, unsigned Imm, + SmallVectorImpl &ShuffleMask) { + // Part that reads from dest. + for (unsigned i = 0; i != NElts/2; ++i) { + ShuffleMask.push_back(Imm % NElts); + Imm /= NElts; + } + // Part that reads from src. + for (unsigned i = 0; i != NElts/2; ++i) { + ShuffleMask.push_back(Imm % NElts + NElts); + Imm /= NElts; + } +} + +static void DecodeUNPCKHPMask(unsigned NElts, + SmallVectorImpl &ShuffleMask) { + for (unsigned i = 0; i != NElts/2; ++i) { + ShuffleMask.push_back(i+NElts/2); // Reads from dest + ShuffleMask.push_back(i+NElts+NElts/2); // Reads from src + } +} + + +/// DecodeUNPCKLPMask - This decodes the shuffle masks for unpcklps/unpcklpd +/// etc. NElts indicates the number of elements in the vector allowing it to +/// handle different datatypes and vector widths. +static void DecodeUNPCKLPMask(unsigned NElts, + SmallVectorImpl &ShuffleMask) { + for (unsigned i = 0; i != NElts/2; ++i) { + ShuffleMask.push_back(i); // Reads from dest + ShuffleMask.push_back(i+NElts); // Reads from src + } +} + +#endif From stoklund at 2pi.dk Thu Sep 2 13:41:10 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 2 Sep 2010 11:41:10 -0700 Subject: [llvm-commits] [llvm] r112841 - in /llvm/trunk: lib/Target/ARM/ARMRegisterInfo.td test/CodeGen/ARM/lsr-on-unrolled-loops.ll test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll test/CodeGen/Thumb2/ldr-str-imm12.ll test/CodeGen/Thumb2/lsr-deficiency.ll In-Reply-To: <39D9994E-4D97-4E2B-9EC1-8ADB6E712ED6@apple.com> References: <20100902181430.083712A6C12C@llvm.org> <9F327C4D-3600-459C-AB1A-5574BC647617@2pi.dk> <39D9994E-4D97-4E2B-9EC1-8ADB6E712ED6@apple.com> Message-ID: On Sep 2, 2010, at 11:33 AM, Jim Grosbach wrote: > > On Sep 2, 2010, at 11:28 AM, Jakob Stoklund Olesen wrote: > >> But shouldn't register allocation be unaffected? >> > > The old allocation orders did things like putting R7/R11 (frame pointer) at the end of the order artificially so they could manipulate the end() iterator easily. That's no longer necessary, and as a result, there are some changes to which registers get allocated here and there. Ah, that makes sense. Only the beginning of the allocation order matters. Once you start using CSRs, the order is not important. From grosbach at apple.com Thu Sep 2 13:44:51 2010 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 02 Sep 2010 18:44:51 -0000 Subject: [llvm-commits] [llvm] r112847 - /llvm/trunk/lib/Target/TargetRegisterInfo.cpp Message-ID: <20100902184452.077032A6C12C@llvm.org> Author: grosbach Date: Thu Sep 2 13:44:51 2010 New Revision: 112847 URL: http://llvm.org/viewvc/llvm-project?rev=112847&view=rev Log: remove trailing whitespace Modified: llvm/trunk/lib/Target/TargetRegisterInfo.cpp Modified: llvm/trunk/lib/Target/TargetRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetRegisterInfo.cpp?rev=112847&r1=112846&r2=112847&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/TargetRegisterInfo.cpp Thu Sep 2 13:44:51 2010 @@ -63,7 +63,7 @@ /// getAllocatableSetForRC - Toggle the bits that represent allocatable /// registers for the specific register class. static void getAllocatableSetForRC(const MachineFunction &MF, - const TargetRegisterClass *RC, BitVector &R){ + const TargetRegisterClass *RC, BitVector &R){ for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF), E = RC->allocation_order_end(MF); I != E; ++I) R.set(*I); From benny.kra at googlemail.com Thu Sep 2 13:53:37 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Thu, 02 Sep 2010 18:53:37 -0000 Subject: [llvm-commits] [llvm] r112849 - in /llvm/trunk: include/llvm/MC/MCStreamer.h lib/MC/MCAsmStreamer.cpp lib/MC/MCNullStreamer.cpp lib/MC/MCObjectStreamer.cpp lib/MC/MCParser/ELFAsmParser.cpp lib/MC/MCStreamer.cpp test/MC/AsmParser/ELF/directive_previous.s Message-ID: <20100902185337.5E8BF2A6C12C@llvm.org> Author: d0k Date: Thu Sep 2 13:53:37 2010 New Revision: 112849 URL: http://llvm.org/viewvc/llvm-project?rev=112849&view=rev Log: Add AsmParser support for the ELF .previous directive. Patch by Roman Divacky. Added: llvm/trunk/test/MC/AsmParser/ELF/directive_previous.s Modified: llvm/trunk/include/llvm/MC/MCStreamer.h llvm/trunk/lib/MC/MCAsmStreamer.cpp llvm/trunk/lib/MC/MCNullStreamer.cpp llvm/trunk/lib/MC/MCObjectStreamer.cpp llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp llvm/trunk/lib/MC/MCStreamer.cpp Modified: llvm/trunk/include/llvm/MC/MCStreamer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCStreamer.h?rev=112849&r1=112848&r2=112849&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCStreamer.h (original) +++ llvm/trunk/include/llvm/MC/MCStreamer.h Thu Sep 2 13:53:37 2010 @@ -54,6 +54,10 @@ /// kept up to date by SwitchSection. const MCSection *CurSection; + /// PrevSection - This is the previous section code is being emitted to, it is + /// kept up to date by SwitchSection. + const MCSection *PrevSection; + public: virtual ~MCStreamer(); @@ -96,6 +100,10 @@ /// emitting code to. const MCSection *getCurrentSection() const { return CurSection; } + /// getPreviousSection - Return the previous section that the streamer is + /// emitting code to. + const MCSection *getPreviousSection() const { return PrevSection; } + /// SwitchSection - Set the current section where code is being emitted to /// @p Section. This is required to update CurSection. /// Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=112849&r1=112848&r2=112849&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Thu Sep 2 13:53:37 2010 @@ -217,6 +217,7 @@ void MCAsmStreamer::SwitchSection(const MCSection *Section) { assert(Section && "Cannot switch to a null section!"); if (Section != CurSection) { + PrevSection = CurSection; CurSection = Section; Section->PrintSwitchToSection(MAI, OS); } Modified: llvm/trunk/lib/MC/MCNullStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCNullStreamer.cpp?rev=112849&r1=112848&r2=112849&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCNullStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCNullStreamer.cpp Thu Sep 2 13:53:37 2010 @@ -26,6 +26,7 @@ /// @{ virtual void SwitchSection(const MCSection *Section) { + PrevSection = CurSection; CurSection = Section; } Modified: llvm/trunk/lib/MC/MCObjectStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCObjectStreamer.cpp?rev=112849&r1=112848&r2=112849&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCObjectStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCObjectStreamer.cpp Thu Sep 2 13:53:37 2010 @@ -77,6 +77,7 @@ // If already in this section, then this is a noop. if (Section == CurSection) return; + PrevSection = CurSection; CurSection = Section; CurSectionData = &getAssembler().getOrCreateSectionData(*Section); } Modified: llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp?rev=112849&r1=112848&r2=112849&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp Thu Sep 2 13:53:37 2010 @@ -50,6 +50,7 @@ AddDirectiveHandler<&ELFAsmParser::ParseDirectiveSize>(".size"); AddDirectiveHandler<&ELFAsmParser::ParseDirectiveLEB128>(".sleb128"); AddDirectiveHandler<&ELFAsmParser::ParseDirectiveLEB128>(".uleb128"); + AddDirectiveHandler<&ELFAsmParser::ParseDirectivePrevious>(".previous"); } bool ParseSectionDirectiveData(StringRef, SMLoc) { @@ -111,6 +112,7 @@ bool ParseDirectiveLEB128(StringRef, SMLoc); bool ParseDirectiveSection(StringRef, SMLoc); bool ParseDirectiveSize(StringRef, SMLoc); + bool ParseDirectivePrevious(StringRef, SMLoc); }; } @@ -272,6 +274,14 @@ return TokError("LEB128 not supported yet"); } +bool ELFAsmParser::ParseDirectivePrevious(StringRef DirName, SMLoc) { + const MCSection *PreviousSection = getStreamer().getPreviousSection(); + if (PreviousSection != NULL) + getStreamer().SwitchSection(PreviousSection); + + return false; +} + namespace llvm { MCAsmParserExtension *createELFAsmParser() { Modified: llvm/trunk/lib/MC/MCStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCStreamer.cpp?rev=112849&r1=112848&r2=112849&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCStreamer.cpp Thu Sep 2 13:53:37 2010 @@ -15,7 +15,8 @@ #include using namespace llvm; -MCStreamer::MCStreamer(MCContext &Ctx) : Context(Ctx), CurSection(0) { +MCStreamer::MCStreamer(MCContext &Ctx) : Context(Ctx), CurSection(0), + PrevSection(0) { } MCStreamer::~MCStreamer() { Added: llvm/trunk/test/MC/AsmParser/ELF/directive_previous.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/ELF/directive_previous.s?rev=112849&view=auto ============================================================================== --- llvm/trunk/test/MC/AsmParser/ELF/directive_previous.s (added) +++ llvm/trunk/test/MC/AsmParser/ELF/directive_previous.s Thu Sep 2 13:53:37 2010 @@ -0,0 +1,13 @@ +# RUN: llvm-mc -triple i386-pc-linux-gnu %s | FileCheck %s + +.bss +# CHECK: .bss + +.text +# CHECK: .text + +.previous +# CHECK: .bss + +.previous +# CHECK: .text From resistor at mac.com Thu Sep 2 14:52:06 2010 From: resistor at mac.com (Owen Anderson) Date: Thu, 02 Sep 2010 19:52:06 -0000 Subject: [llvm-commits] [llvm] r112851 - /llvm/trunk/test/Transforms/CorrelatedValuePropagation/2010-09-02-Trunc.ll Message-ID: <20100902195206.917D92A6C12C@llvm.org> Author: resistor Date: Thu Sep 2 14:52:06 2010 New Revision: 112851 URL: http://llvm.org/viewvc/llvm-project?rev=112851&view=rev Log: Fix typo. I accidentally edited the wrong file before my last commit. Modified: llvm/trunk/test/Transforms/CorrelatedValuePropagation/2010-09-02-Trunc.ll Modified: llvm/trunk/test/Transforms/CorrelatedValuePropagation/2010-09-02-Trunc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/CorrelatedValuePropagation/2010-09-02-Trunc.ll?rev=112851&r1=112850&r2=112851&view=diff ============================================================================== --- llvm/trunk/test/Transforms/CorrelatedValuePropagation/2010-09-02-Trunc.ll (original) +++ llvm/trunk/test/Transforms/CorrelatedValuePropagation/2010-09-02-Trunc.ll Thu Sep 2 14:52:06 2010 @@ -1,6 +1,6 @@ ; RUN: opt -S < %s -correlated-propagation | FileCheck %s -; CHECK: @check +; CHECK: @test define i16 @test(i32 %a, i1 %b) { entry: %c = icmp eq i32 %a, 0 From grosbach at apple.com Thu Sep 2 14:52:39 2010 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 02 Sep 2010 19:52:39 -0000 Subject: [llvm-commits] [llvm] r112852 - /llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Message-ID: <20100902195239.481CA2A6C12C@llvm.org> Author: grosbach Date: Thu Sep 2 14:52:39 2010 New Revision: 112852 URL: http://llvm.org/viewvc/llvm-project?rev=112852&view=rev Log: trailing whitespace Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=112852&r1=112851&r2=112852&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Thu Sep 2 14:52:39 2010 @@ -641,19 +641,19 @@ unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) || F->hasFnAttr(Attribute::StackAlignment)); - + // FIXME: Currently we don't support stack realignment for functions with // variable-sized allocas. // FIXME: It's more complicated than this... if (0 && requiresRealignment && MFI->hasVarSizedObjects()) report_fatal_error( "Stack realignment in presense of dynamic allocas is not supported"); - + // FIXME: This probably isn't the right place for this. if (0 && requiresRealignment && AFI->isThumb1OnlyFunction()) report_fatal_error( "Stack realignment in thumb1 functions is not supported"); - + return requiresRealignment && canRealignStack(MF); } @@ -984,7 +984,7 @@ return ARM::LR; } -unsigned +unsigned ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const { if (hasFP(MF)) return FramePtr; @@ -1980,7 +1980,7 @@ // Jump to label or value in register. if (RetOpcode == ARM::TCRETURNdi) { - BuildMI(MBB, MBBI, dl, + BuildMI(MBB, MBBI, dl, TII.get(STI.isThumb() ? ARM::TAILJMPdt : ARM::TAILJMPd)). addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), JumpTarget.getTargetFlags()); @@ -1995,7 +1995,7 @@ } else if (RetOpcode == ARM::TCRETURNriND) { BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPrND)). addReg(JumpTarget.getReg(), RegState::Kill); - } + } MachineInstr *NewMI = prior(MBBI); for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i) From deeppatel1987 at gmail.com Thu Sep 2 15:19:24 2010 From: deeppatel1987 at gmail.com (Sandeep Patel) Date: Thu, 02 Sep 2010 20:19:24 -0000 Subject: [llvm-commits] [llvm] r112853 - /llvm/trunk/test/CodeGen/ARM/fnmuls.ll Message-ID: <20100902201924.2E6882A6C12C@llvm.org> Author: sandeep Date: Thu Sep 2 15:19:24 2010 New Revision: 112853 URL: http://llvm.org/viewvc/llvm-project?rev=112853&view=rev Log: Fix an unnecessary XFAIL Modified: llvm/trunk/test/CodeGen/ARM/fnmuls.ll Modified: llvm/trunk/test/CodeGen/ARM/fnmuls.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fnmuls.ll?rev=112853&r1=112852&r2=112853&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fnmuls.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fnmuls.ll Thu Sep 2 15:19:24 2010 @@ -1,20 +1,18 @@ -; XFAIL: * ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -define float @test1(float %a, float %b) nounwind { -; CHECK: fnmscs s2, s1, s0 +define arm_aapcs_vfpcc float @test1(float %a, float %b) nounwind { +; CHECK: vnmul.f32 s0, s0, s1 entry: %0 = fmul float %a, %b %1 = fsub float -0.0, %0 ret float %1 } -define float @test2(float %a, float %b) nounwind { -; CHECK: fnmscs s2, s1, s0 +define arm_aapcs_vfpcc float @test2(float %a, float %b) nounwind { +; CHECK: vnmul.f32 s0, s0, s1 entry: %0 = fmul float %a, %b %1 = fmul float -1.0, %0 From dpatel at apple.com Thu Sep 2 16:02:27 2010 From: dpatel at apple.com (Devang Patel) Date: Thu, 02 Sep 2010 21:02:27 -0000 Subject: [llvm-commits] [llvm] r112858 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Message-ID: <20100902210227.CA5352A6C12C@llvm.org> Author: dpatel Date: Thu Sep 2 16:02:27 2010 New Revision: 112858 URL: http://llvm.org/viewvc/llvm-project?rev=112858&view=rev Log: Tidy up. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=112858&r1=112857&r2=112858&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Thu Sep 2 16:02:27 2010 @@ -4064,19 +4064,10 @@ } case Intrinsic::dbg_declare: { const DbgDeclareInst &DI = cast(I); - if (!DIVariable(DI.getVariable()).Verify()) - return 0; - MDNode *Variable = DI.getVariable(); - // Parameters are handled specially. - bool isParameter = - DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable; const Value *Address = DI.getAddress(); - if (!Address) + if (!Address || !DIVariable(DI.getVariable()).Verify()) return 0; - if (const BitCastInst *BCI = dyn_cast(Address)) - Address = BCI->getOperand(0); - const AllocaInst *AI = dyn_cast(Address); // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder // but do not always have a corresponding SDNode built. The SDNodeOrder @@ -4089,6 +4080,13 @@ N = UnusedArgNodeMap[Address]; SDDbgValue *SDV; if (N.getNode()) { + // Parameters are handled specially. + bool isParameter = + DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable; + if (const BitCastInst *BCI = dyn_cast(Address)) + Address = BCI->getOperand(0); + const AllocaInst *AI = dyn_cast(Address); + if (isParameter && !AI) { FrameIndexSDNode *FINode = dyn_cast(N.getNode()); if (FINode) @@ -4113,7 +4111,7 @@ if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) { SDV = DAG.getDbgValue(Variable, UndefValue::get(Address->getType()), 0, dl, SDNodeOrder); - DAG.AddDbgValue(SDV, 0, isParameter); + DAG.AddDbgValue(SDV, 0, false); } } return 0; From gohman at apple.com Thu Sep 2 16:18:42 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 02 Sep 2010 21:18:42 -0000 Subject: [llvm-commits] [llvm] r112861 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp lib/Target/X86/README.txt test/CodeGen/X86/narrow_op-2.ll test/CodeGen/X86/store-narrow.ll Message-ID: <20100902211842.A3BFF2A6C12C@llvm.org> Author: djg Date: Thu Sep 2 16:18:42 2010 New Revision: 112861 URL: http://llvm.org/viewvc/llvm-project?rev=112861&view=rev Log: Don't narrow the load and store in a load+twiddle+store sequence unless there are clearly no stores between the load and the store. This fixes this miscompile reported as PR7833. This breaks the test/CodeGen/X86/narrow_op-2.ll optimization, which is safe, but awkward to prove safe. Move it to X86's README.txt. Removed: llvm/trunk/test/CodeGen/X86/narrow_op-2.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp llvm/trunk/lib/Target/X86/README.txt llvm/trunk/test/CodeGen/X86/store-narrow.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=112861&r1=112860&r2=112861&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Sep 2 16:18:42 2010 @@ -5798,7 +5798,8 @@ return SDValue(); SDValue N0 = Value.getOperand(0); - if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse()) { + if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && + Chain == SDValue(N0.getNode(), 1)) { LoadSDNode *LD = cast(N0); if (LD->getBasePtr() != Ptr) return SDValue(); Modified: llvm/trunk/lib/Target/X86/README.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/README.txt?rev=112861&r1=112860&r2=112861&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/README.txt (original) +++ llvm/trunk/lib/Target/X86/README.txt Thu Sep 2 16:18:42 2010 @@ -1915,3 +1915,48 @@ It should be possible to eliminate the sign extensions. //===---------------------------------------------------------------------===// + +LLVM misses a load+store narrowing opportunity in this code: + +%struct.bf = type { i64, i16, i16, i32 } + + at bfi = external global %struct.bf* ; <%struct.bf**> [#uses=2] + +define void @t1() nounwind ssp { +entry: + %0 = load %struct.bf** @bfi, align 8 ; <%struct.bf*> [#uses=1] + %1 = getelementptr %struct.bf* %0, i64 0, i32 1 ; [#uses=1] + %2 = bitcast i16* %1 to i32* ; [#uses=2] + %3 = load i32* %2, align 1 ; [#uses=1] + %4 = and i32 %3, -65537 ; [#uses=1] + store i32 %4, i32* %2, align 1 + %5 = load %struct.bf** @bfi, align 8 ; <%struct.bf*> [#uses=1] + %6 = getelementptr %struct.bf* %5, i64 0, i32 1 ; [#uses=1] + %7 = bitcast i16* %6 to i32* ; [#uses=2] + %8 = load i32* %7, align 1 ; [#uses=1] + %9 = and i32 %8, -131073 ; [#uses=1] + store i32 %9, i32* %7, align 1 + ret void +} + +LLVM currently emits this: + + movq bfi(%rip), %rax + andl $-65537, 8(%rax) + movq bfi(%rip), %rax + andl $-131073, 8(%rax) + ret + +It could narrow the loads and stores to emit this: + + movq bfi(%rip), %rax + andb $-2, 10(%rax) + movq bfi(%rip), %rax + andb $-3, 10(%rax) + ret + +The trouble is that there is a TokenFactor between the store and the +load, making it non-trivial to determine if there's anything between +the load and the store which would prohibit narrowing. + +//===---------------------------------------------------------------------===// Removed: llvm/trunk/test/CodeGen/X86/narrow_op-2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/narrow_op-2.ll?rev=112860&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/narrow_op-2.ll (original) +++ llvm/trunk/test/CodeGen/X86/narrow_op-2.ll (removed) @@ -1,25 +0,0 @@ -; RUN: llc < %s -march=x86-64 | FileCheck %s - - %struct.bf = type { i64, i16, i16, i32 } - at bfi = external global %struct.bf* - -define void @t1() nounwind ssp { -entry: - -; CHECK: andb $-2, 10( -; CHECK: andb $-3, 10( - - %0 = load %struct.bf** @bfi, align 8 - %1 = getelementptr %struct.bf* %0, i64 0, i32 1 - %2 = bitcast i16* %1 to i32* - %3 = load i32* %2, align 1 - %4 = and i32 %3, -65537 - store i32 %4, i32* %2, align 1 - %5 = load %struct.bf** @bfi, align 8 - %6 = getelementptr %struct.bf* %5, i64 0, i32 1 - %7 = bitcast i16* %6 to i32* - %8 = load i32* %7, align 1 - %9 = and i32 %8, -131073 - store i32 %9, i32* %7, align 1 - ret void -} Modified: llvm/trunk/test/CodeGen/X86/store-narrow.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/store-narrow.ll?rev=112861&r1=112860&r2=112861&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/store-narrow.ll (original) +++ llvm/trunk/test/CodeGen/X86/store-narrow.ll Thu Sep 2 16:18:42 2010 @@ -1,6 +1,6 @@ ; rdar://7860110 -; RUN: llc < %s | FileCheck %s -check-prefix=X64 -; RUN: llc -march=x86 < %s | FileCheck %s -check-prefix=X32 +; RUN: llc -asm-verbose=false < %s | FileCheck %s -check-prefix=X64 +; RUN: llc -march=x86 -asm-verbose=false < %s | FileCheck %s -check-prefix=X32 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-apple-darwin10.2" @@ -125,3 +125,30 @@ ; X32: movb %cl, 5(%{{.*}}) } +; PR7833 + + at g_16 = internal global i32 -1 + +; X64: test8: +; X64-NEXT: movl _g_16(%rip), %eax +; X64-NEXT: movl $0, _g_16(%rip) +; X64-NEXT: orl $1, %eax +; X64-NEXT: movl %eax, _g_16(%rip) +; X64-NEXT: ret +define void @test8() nounwind { + %tmp = load i32* @g_16 + store i32 0, i32* @g_16 + %or = or i32 %tmp, 1 + store i32 %or, i32* @g_16 + ret void +} + +; X64: test9: +; X64-NEXT: orb $1, _g_16(%rip) +; X64-NEXT: ret +define void @test9() nounwind { + %tmp = load i32* @g_16 + %or = or i32 %tmp, 1 + store i32 %or, i32* @g_16 + ret void +} From dpatel at apple.com Thu Sep 2 16:29:42 2010 From: dpatel at apple.com (Devang Patel) Date: Thu, 02 Sep 2010 21:29:42 -0000 Subject: [llvm-commits] [llvm] r112864 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Message-ID: <20100902212942.ACEA62A6C12C@llvm.org> Author: dpatel Date: Thu Sep 2 16:29:42 2010 New Revision: 112864 URL: http://llvm.org/viewvc/llvm-project?rev=112864&view=rev Log: Detect undef value early and save unnecessary NodeMap query. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=112864&r1=112863&r2=112864&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Thu Sep 2 16:29:42 2010 @@ -4074,6 +4074,17 @@ // absolute, but not relative, values are different depending on whether // debug info exists. ++SDNodeOrder; + + // Check if address has undef value. + if (isa(Address) || + (Address->use_empty() && !isa(Address))) { + SDDbgValue*SDV = + DAG.getDbgValue(Variable, UndefValue::get(Address->getType()), + 0, dl, SDNodeOrder); + DAG.AddDbgValue(SDV, 0, false); + return 0; + } + SDValue &N = NodeMap[Address]; if (!N.getNode() && isa(Address)) // Check unused arguments map. From bruno.cardoso at gmail.com Thu Sep 2 16:51:11 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Thu, 02 Sep 2010 21:51:11 -0000 Subject: [llvm-commits] [llvm] r112869 - in /llvm/trunk/lib/Target/X86: AsmPrinter/X86InstComments.cpp X86ShuffleDecode.h Message-ID: <20100902215111.DEB032A6C12C@llvm.org> Author: bruno Date: Thu Sep 2 16:51:11 2010 New Revision: 112869 URL: http://llvm.org/viewvc/llvm-project?rev=112869&view=rev Log: Move decoding of insertps back to avoid unused warnings in x86 isel lowering, and fix movlhps/movhlps to decode 4 elements shuffles Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86InstComments.cpp llvm/trunk/lib/Target/X86/X86ShuffleDecode.h Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86InstComments.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86InstComments.cpp?rev=112869&r1=112868&r2=112869&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmPrinter/X86InstComments.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86InstComments.cpp Thu Sep 2 16:51:11 2010 @@ -20,6 +20,34 @@ using namespace llvm; //===----------------------------------------------------------------------===// +// Vector Mask Decoding for non-shuffles +//===----------------------------------------------------------------------===// + +static void DecodeINSERTPSMask(unsigned Imm, + SmallVectorImpl &ShuffleMask) { + // Defaults the copying the dest value. + ShuffleMask.push_back(0); + ShuffleMask.push_back(1); + ShuffleMask.push_back(2); + ShuffleMask.push_back(3); + + // Decode the immediate. + unsigned ZMask = Imm & 15; + unsigned CountD = (Imm >> 4) & 3; + unsigned CountS = (Imm >> 6) & 3; + + // CountS selects which input element to use. + unsigned InVal = 4+CountS; + // CountD specifies which element of destination to update. + ShuffleMask[CountD] = InVal; + // ZMask zaps values, potentially overriding the CountD elt. + if (ZMask & 1) ShuffleMask[0] = SM_SentinelZero; + if (ZMask & 2) ShuffleMask[1] = SM_SentinelZero; + if (ZMask & 4) ShuffleMask[2] = SM_SentinelZero; + if (ZMask & 8) ShuffleMask[3] = SM_SentinelZero; +} + +//===----------------------------------------------------------------------===// // Top Level Entrypoint //===----------------------------------------------------------------------===// @@ -42,13 +70,13 @@ case X86::MOVLHPSrr: Src2Name = getRegName(MI->getOperand(2).getReg()); Src1Name = getRegName(MI->getOperand(0).getReg()); - DecodeMOVLHPSMask(ShuffleMask); + DecodeMOVLHPSMask(2, ShuffleMask); break; case X86::MOVHLPSrr: Src2Name = getRegName(MI->getOperand(2).getReg()); Src1Name = getRegName(MI->getOperand(0).getReg()); - DecodeMOVHLPSMask(ShuffleMask); + DecodeMOVHLPSMask(2, ShuffleMask); break; case X86::PSHUFDri: Modified: llvm/trunk/lib/Target/X86/X86ShuffleDecode.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ShuffleDecode.h?rev=112869&r1=112868&r2=112869&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ShuffleDecode.h (original) +++ llvm/trunk/lib/Target/X86/X86ShuffleDecode.h Thu Sep 2 16:51:11 2010 @@ -26,38 +26,24 @@ SM_SentinelZero = ~0U }; -static void DecodeINSERTPSMask(unsigned Imm, - SmallVectorImpl &ShuffleMask) { - // Defaults the copying the dest value. - ShuffleMask.push_back(0); - ShuffleMask.push_back(1); - ShuffleMask.push_back(2); - ShuffleMask.push_back(3); +// <3,1> or <6,7,2,3> +static void DecodeMOVHLPSMask(unsigned NElts, + SmallVectorImpl &ShuffleMask) { + for (unsigned i = NElts/2; i != NElts; ++i) + ShuffleMask.push_back(NElts+i); - // Decode the immediate. - unsigned ZMask = Imm & 15; - unsigned CountD = (Imm >> 4) & 3; - unsigned CountS = (Imm >> 6) & 3; - - // CountS selects which input element to use. - unsigned InVal = 4+CountS; - // CountD specifies which element of destination to update. - ShuffleMask[CountD] = InVal; - // ZMask zaps values, potentially overriding the CountD elt. - if (ZMask & 1) ShuffleMask[0] = SM_SentinelZero; - if (ZMask & 2) ShuffleMask[1] = SM_SentinelZero; - if (ZMask & 4) ShuffleMask[2] = SM_SentinelZero; - if (ZMask & 8) ShuffleMask[3] = SM_SentinelZero; + for (unsigned i = NElts/2; i != NElts; ++i) + ShuffleMask.push_back(i); } -static void DecodeMOVHLPSMask(SmallVectorImpl &ShuffleMask) { - ShuffleMask.push_back(3); - ShuffleMask.push_back(1); -} +// <0,2> or <0,1,4,5> +static void DecodeMOVLHPSMask(unsigned NElts, + SmallVectorImpl &ShuffleMask) { + for (unsigned i = 0; i != NElts/2; ++i) + ShuffleMask.push_back(i); -static void DecodeMOVLHPSMask(SmallVectorImpl &ShuffleMask) { - ShuffleMask.push_back(0); - ShuffleMask.push_back(2); + for (unsigned i = 0; i != NElts/2; ++i) + ShuffleMask.push_back(NElts+i); } static void DecodePSHUFMask(unsigned NElts, unsigned Imm, From rjmccall at apple.com Thu Sep 2 16:55:04 2010 From: rjmccall at apple.com (John McCall) Date: Thu, 02 Sep 2010 21:55:04 -0000 Subject: [llvm-commits] [llvm] r112870 - in /llvm/trunk: include/llvm/ADT/SmallVector.h lib/Support/SmallVector.cpp Message-ID: <20100902215504.280632A6C12C@llvm.org> Author: rjmccall Date: Thu Sep 2 16:55:03 2010 New Revision: 112870 URL: http://llvm.org/viewvc/llvm-project?rev=112870&view=rev Log: After some discussion with djg, teach SmallVector to grow from a zero capacity and remove the workaround in SmallVector. There are some theoretical benefits to a N->2N+1 growth policy anyway. Modified: llvm/trunk/include/llvm/ADT/SmallVector.h llvm/trunk/lib/Support/SmallVector.cpp Modified: llvm/trunk/include/llvm/ADT/SmallVector.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/SmallVector.h?rev=112870&r1=112869&r2=112870&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/SmallVector.h (original) +++ llvm/trunk/include/llvm/ADT/SmallVector.h Thu Sep 2 16:55:03 2010 @@ -206,7 +206,7 @@ void SmallVectorTemplateBase::grow(size_t MinSize) { size_t CurCapacity = this->capacity(); size_t CurSize = this->size(); - size_t NewCapacity = 2*CurCapacity; + size_t NewCapacity = 2*CurCapacity + 1; // Always grow, even from zero. if (NewCapacity < MinSize) NewCapacity = MinSize; T *NewElts = static_cast(malloc(NewCapacity*sizeof(T))); @@ -712,38 +712,27 @@ /// members are required. template class SmallVector : public SmallVectorImpl { - // SmallVector doesn't like growing from zero capacity. As a - // temporary workaround, avoid changing the growth algorithm by - // forcing capacity to be at least 1 in the constructors. - public: - SmallVector() : SmallVectorImpl(0) { - this->reserve(1); // workaround - } + SmallVector() : SmallVectorImpl(0) {} explicit SmallVector(unsigned Size, const T &Value = T()) : SmallVectorImpl(0) { - this->reserve(Size ? Size : 1); // workaround + this->reserve(Size); while (Size--) this->push_back(Value); } template SmallVector(ItTy S, ItTy E) : SmallVectorImpl(0) { - if (S == E) this->reserve(1); // workaround this->append(S, E); } SmallVector(const SmallVector &RHS) : SmallVectorImpl(0) { - if (!RHS.empty()) - SmallVectorImpl::operator=(RHS); - else - this->reserve(1); // workaround + SmallVectorImpl::operator=(RHS); } - const SmallVector &operator=(const SmallVector &RHS) { - SmallVectorImpl::operator=(RHS); - return *this; + SmallVector &operator=(const SmallVectorImpl &RHS) { + return SmallVectorImpl::operator=(RHS); } }; Modified: llvm/trunk/lib/Support/SmallVector.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/SmallVector.cpp?rev=112870&r1=112869&r2=112870&view=diff ============================================================================== --- llvm/trunk/lib/Support/SmallVector.cpp (original) +++ llvm/trunk/lib/Support/SmallVector.cpp Thu Sep 2 16:55:03 2010 @@ -18,7 +18,7 @@ /// on POD-like datatypes and is out of line to reduce code duplication. void SmallVectorBase::grow_pod(size_t MinSizeInBytes, size_t TSize) { size_t CurSizeBytes = size_in_bytes(); - size_t NewCapacityInBytes = 2 * capacity_in_bytes(); + size_t NewCapacityInBytes = 2 * capacity_in_bytes() + TSize; // Always grow. if (NewCapacityInBytes < MinSizeInBytes) NewCapacityInBytes = MinSizeInBytes; From clattner at apple.com Thu Sep 2 17:01:49 2010 From: clattner at apple.com (Chris Lattner) Date: Thu, 2 Sep 2010 15:01:49 -0700 Subject: [llvm-commits] [llvm] r112869 - in /llvm/trunk/lib/Target/X86: AsmPrinter/X86InstComments.cpp X86ShuffleDecode.h In-Reply-To: <20100902215111.DEB032A6C12C@llvm.org> References: <20100902215111.DEB032A6C12C@llvm.org> Message-ID: <2DDB83ED-B312-4D89-A108-059419D39EF7@apple.com> On Sep 2, 2010, at 2:51 PM, Bruno Cardoso Lopes wrote: > Author: bruno > Date: Thu Sep 2 16:51:11 2010 > New Revision: 112869 > > URL: http://llvm.org/viewvc/llvm-project?rev=112869&view=rev > Log: > Move decoding of insertps back to avoid unused warnings in x86 isel lowering, and fix movlhps/movhlps to decode 4 elements shuffles What warning? If it is about unused functions, just mark the function 'static inline'. -Chris From bruno.cardoso at gmail.com Thu Sep 2 17:07:10 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Thu, 2 Sep 2010 15:07:10 -0700 Subject: [llvm-commits] [llvm] r112869 - in /llvm/trunk/lib/Target/X86: AsmPrinter/X86InstComments.cpp X86ShuffleDecode.h In-Reply-To: <2DDB83ED-B312-4D89-A108-059419D39EF7@apple.com> References: <20100902215111.DEB032A6C12C@llvm.org> <2DDB83ED-B312-4D89-A108-059419D39EF7@apple.com> Message-ID: On Thu, Sep 2, 2010 at 3:01 PM, Chris Lattner wrote: > > On Sep 2, 2010, at 2:51 PM, Bruno Cardoso Lopes wrote: > >> Author: bruno >> Date: Thu Sep ?2 16:51:11 2010 >> New Revision: 112869 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=112869&view=rev >> Log: >> Move decoding of insertps back to avoid unused warnings in x86 isel lowering, and fix movlhps/movhlps to decode 4 elements shuffles > > What warning? ?If it is about unused functions, just mark the function 'static inline'. A warning at the code I'm going to check-in, in X86ISelLowering, all functions are going to be used but the insertps, which is not a shuffle. -- Bruno Cardoso Lopes http://www.brunocardoso.cc From gohman at apple.com Thu Sep 2 17:14:51 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 02 Sep 2010 22:14:51 -0000 Subject: [llvm-commits] [llvm] r112874 - in /llvm/trunk/include/llvm: Bitcode/Archive.h Linker.h Support/TypeBuilder.h System/Memory.h System/Process.h System/Program.h Message-ID: <20100902221451.765F92A6C12C@llvm.org> Author: djg Date: Thu Sep 2 17:14:51 2010 New Revision: 112874 URL: http://llvm.org/viewvc/llvm-project?rev=112874&view=rev Log: Remove obsolete comments about throwing exceptions. Modified: llvm/trunk/include/llvm/Bitcode/Archive.h llvm/trunk/include/llvm/Linker.h llvm/trunk/include/llvm/Support/TypeBuilder.h llvm/trunk/include/llvm/System/Memory.h llvm/trunk/include/llvm/System/Process.h llvm/trunk/include/llvm/System/Program.h Modified: llvm/trunk/include/llvm/Bitcode/Archive.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Bitcode/Archive.h?rev=112874&r1=112873&r2=112874&view=diff ============================================================================== --- llvm/trunk/include/llvm/Bitcode/Archive.h (original) +++ llvm/trunk/include/llvm/Bitcode/Archive.h Thu Sep 2 17:14:51 2010 @@ -297,7 +297,7 @@ /// its symbol table without reading in any of the archive's members. This /// reduces both I/O and cpu time in opening the archive if it is to be used /// solely for symbol lookup (e.g. during linking). The \p Filename must - /// exist and be an archive file or an exception will be thrown. This form + /// exist and be an archive file or an error will be returned. This form /// of opening the archive is intended for read-only operations that need to /// locate members via the symbol table for link editing. Since the archve /// members are not read by this method, the archive will appear empty upon @@ -306,8 +306,7 @@ /// if this form of opening the archive is used that only the symbol table /// lookup methods (getSymbolTable, findModuleDefiningSymbol, and /// findModulesDefiningSymbols) be used. - /// @throws std::string if an error occurs opening the file - /// @returns an Archive* that represents the archive file. + /// @returns an Archive* that represents the archive file, or null on error. /// @brief Open an existing archive and load its symbols. static Archive* OpenAndLoadSymbols( const sys::Path& Filename, ///< Name of the archive file to open @@ -319,7 +318,6 @@ /// closes files. It does nothing with the archive file on disk. If you /// haven't used the writeToDisk method by the time the destructor is /// called, all changes to the archive will be lost. - /// @throws std::string if an error occurs /// @brief Destruct in-memory archive ~Archive(); Modified: llvm/trunk/include/llvm/Linker.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Linker.h?rev=112874&r1=112873&r2=112874&view=diff ============================================================================== --- llvm/trunk/include/llvm/Linker.h (original) +++ llvm/trunk/include/llvm/Linker.h Thu Sep 2 17:14:51 2010 @@ -158,7 +158,6 @@ /// @returns true if an error occurred, false otherwise /// @see LinkItemKind /// @see getLastError - /// @throws nothing bool LinkInItems ( const ItemList& Items, ///< Set of libraries/files to link in ItemList& NativeItems ///< Output list of native files/libs Modified: llvm/trunk/include/llvm/Support/TypeBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/TypeBuilder.h?rev=112874&r1=112873&r2=112874&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/TypeBuilder.h (original) +++ llvm/trunk/include/llvm/Support/TypeBuilder.h Thu Sep 2 17:14:51 2010 @@ -73,7 +73,7 @@ /// /// TypeBuilder cannot handle recursive types or types you only know at runtime. /// If you try to give it a recursive type, it will deadlock, infinitely -/// recurse, or throw a recursive_init exception. +/// recurse, or do something similarly undesirable. template class TypeBuilder {}; // Types for use with cross-compilable TypeBuilders. These correspond Modified: llvm/trunk/include/llvm/System/Memory.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/System/Memory.h?rev=112874&r1=112873&r2=112874&view=diff ============================================================================== --- llvm/trunk/include/llvm/System/Memory.h (original) +++ llvm/trunk/include/llvm/System/Memory.h Thu Sep 2 17:14:51 2010 @@ -63,7 +63,6 @@ /// /// On success, this returns false, otherwise it returns true and fills /// in *ErrMsg. - /// @throws std::string if an error occurred. /// @brief Release Read/Write/Execute memory. static bool ReleaseRWX(MemoryBlock &block, std::string *ErrMsg = 0); Modified: llvm/trunk/include/llvm/System/Process.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/System/Process.h?rev=112874&r1=112873&r2=112874&view=diff ============================================================================== --- llvm/trunk/include/llvm/System/Process.h (original) +++ llvm/trunk/include/llvm/System/Process.h Thu Sep 2 17:14:51 2010 @@ -30,7 +30,6 @@ /// This static function will return the operating system's virtual memory /// page size. /// @returns The number of bytes in a virtual memory page. - /// @throws nothing /// @brief Get the virtual memory page size static unsigned GetPageSize(); @@ -38,7 +37,6 @@ /// by the process. This only counts the memory allocated via the malloc, /// calloc and realloc functions and includes any "free" holes in the /// allocated space. - /// @throws nothing /// @brief Return process memory usage. static size_t GetMallocUsage(); Modified: llvm/trunk/include/llvm/System/Program.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/System/Program.h?rev=112874&r1=112873&r2=112874&view=diff ============================================================================== --- llvm/trunk/include/llvm/System/Program.h (original) +++ llvm/trunk/include/llvm/System/Program.h Thu Sep 2 17:14:51 2010 @@ -116,7 +116,6 @@ /// locations to search (e.g. the PATH on Unix). /// @returns A Path object initialized to the path of the program or a /// Path object that is empty (invalid) if the program could not be found. - /// @throws nothing /// @brief Construct a Program by finding it by name. static Path FindProgramByName(const std::string& name); @@ -129,7 +128,6 @@ /// A convenience function equivalent to Program prg; prg.Execute(..); /// prg.Wait(..); - /// @throws nothing /// @see Execute, Wait static int ExecuteAndWait(const Path& path, const char** args, @@ -140,7 +138,6 @@ std::string* ErrMsg = 0); /// A convenience function equivalent to Program prg; prg.Execute(..); - /// @throws nothing /// @see Execute static void ExecuteNoWait(const Path& path, const char** args, From asl at math.spbu.ru Thu Sep 2 17:16:28 2010 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Thu, 02 Sep 2010 22:16:28 -0000 Subject: [llvm-commits] [llvm] r112875 - in /llvm/trunk/lib/Target/X86: X86ISelLowering.cpp X86RegisterInfo.cpp Message-ID: <20100902221628.C38BA2A6C12C@llvm.org> Author: asl Date: Thu Sep 2 17:16:28 2010 New Revision: 112875 URL: http://llvm.org/viewvc/llvm-project?rev=112875&view=rev Log: Properly allocate win64 shadow reg area. Patch by Jan Sjodin! Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=112875&r1=112874&r2=112875&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Sep 2 17:16:28 2010 @@ -1616,6 +1616,11 @@ SmallVector ArgLocs; CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs, *DAG.getContext()); + + // Allocate shadow area for Win64 + if (IsWin64) + CCInfo.AllocateStack(32, 8); + CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv)); unsigned LastVal = ~0U; @@ -1842,8 +1847,7 @@ DebugLoc dl, SelectionDAG &DAG, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const { - const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0); - unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset(); + unsigned LocMemOffset = VA.getLocMemOffset(); SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); if (Flags.isByVal()) { @@ -1926,6 +1930,11 @@ SmallVector ArgLocs; CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs, *DAG.getContext()); + + // Allocate shadow area for Win64 + if (Subtarget->isTargetWin64()) + CCInfo.AllocateStack(32, 8); + CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv)); // Get a count of how many bytes are to be pushed on the stack. Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=112875&r1=112874&r2=112875&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Thu Sep 2 17:16:28 2010 @@ -945,11 +945,6 @@ if (HasFP) MinSize += SlotSize; StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0); MFI->setStackSize(StackSize); - } else if (Subtarget->isTargetWin64()) { - // We need to always allocate 32 bytes as register spill area. - // FIXME: We might reuse these 32 bytes for leaf functions. - StackSize += 32; - MFI->setStackSize(StackSize); } // Insert stack pointer adjustment for later moving of return addr. Only From resistor at mac.com Thu Sep 2 17:16:52 2010 From: resistor at mac.com (Owen Anderson) Date: Thu, 02 Sep 2010 22:16:52 -0000 Subject: [llvm-commits] [llvm] r112876 - /llvm/trunk/lib/Analysis/LazyValueInfo.cpp Message-ID: <20100902221652.3D10D2A6C12C@llvm.org> Author: resistor Date: Thu Sep 2 17:16:52 2010 New Revision: 112876 URL: http://llvm.org/viewvc/llvm-project?rev=112876&view=rev Log: Remove incorrect and poorly tested code for trying to reason about values on default edges of switches. Just return the conservatively correct answer. Modified: llvm/trunk/lib/Analysis/LazyValueInfo.cpp Modified: llvm/trunk/lib/Analysis/LazyValueInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/LazyValueInfo.cpp?rev=112876&r1=112875&r2=112876&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/LazyValueInfo.cpp (original) +++ llvm/trunk/lib/Analysis/LazyValueInfo.cpp Thu Sep 2 17:16:52 2010 @@ -670,25 +670,11 @@ // If the edge was formed by a switch on the value, then we may know exactly // what it is. if (SwitchInst *SI = dyn_cast(BBFrom->getTerminator())) { - // If BBTo is the default destination of the switch, we know that it - // doesn't have the same value as any of the cases. if (SI->getCondition() == Val) { + // We don't know anything in the default case. if (SI->getDefaultDest() == BBTo) { - const IntegerType *IT = cast(Val->getType()); - ConstantRange CR(IT->getBitWidth()); - - for (unsigned i = 1, e = SI->getNumSuccessors(); i != e; ++i) { - const APInt CaseVal = SI->getCaseValue(i)->getValue(); - ConstantRange CaseRange(CaseVal, CaseVal+1); - CaseRange = CaseRange.inverse(); - CR = CR.intersectWith(CaseRange); - } - LVILatticeVal Result; - if (CR.isFullSet() || CR.isEmptySet()) - Result.markOverdefined(); - else - Result.markConstantRange(CR); + Result.markOverdefined(); return Result; } From sabre at nondot.org Thu Sep 2 17:19:10 2010 From: sabre at nondot.org (Chris Lattner) Date: Thu, 02 Sep 2010 22:19:10 -0000 Subject: [llvm-commits] [llvm] r112878 - in /llvm/trunk: lib/Transforms/Scalar/LICM.cpp test/Transforms/LICM/scalar_promote.ll Message-ID: <20100902221910.7DE9A2A6C12C@llvm.org> Author: lattner Date: Thu Sep 2 17:19:10 2010 New Revision: 112878 URL: http://llvm.org/viewvc/llvm-project?rev=112878&view=rev Log: fix more AST updating bugs, correcting miscompilation in PR8041 Modified: llvm/trunk/lib/Transforms/Scalar/LICM.cpp llvm/trunk/test/Transforms/LICM/scalar_promote.ll Modified: llvm/trunk/lib/Transforms/Scalar/LICM.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LICM.cpp?rev=112878&r1=112877&r2=112878&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LICM.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LICM.cpp Thu Sep 2 17:19:10 2010 @@ -583,7 +583,7 @@ // Update CurAST for NewPHIs if I had pointer type. if (I.getType()->isPointerTy()) for (unsigned i = 0, e = NewPHIs.size(); i != e; ++i) - CurAST->copyValue(NewPHIs[i], &I); + CurAST->copyValue(&I, NewPHIs[i]); // Finally, remove the instruction from CurAST. It is no longer in the loop. CurAST->deleteValue(&I); @@ -843,7 +843,9 @@ // inserting PHI nodes as necessary. for (unsigned i = 0, e = LiveInLoads.size(); i != e; ++i) { LoadInst *ALoad = LiveInLoads[i]; - ALoad->replaceAllUsesWith(SSA.GetValueInMiddleOfBlock(ALoad->getParent())); + Value *NewVal = SSA.GetValueInMiddleOfBlock(ALoad->getParent()); + ALoad->replaceAllUsesWith(NewVal); + CurAST->copyValue(ALoad, NewVal); } // Now that everything is rewritten, delete the old instructions from the body Modified: llvm/trunk/test/Transforms/LICM/scalar_promote.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LICM/scalar_promote.ll?rev=112878&r1=112877&r2=112878&view=diff ============================================================================== --- llvm/trunk/test/Transforms/LICM/scalar_promote.ll (original) +++ llvm/trunk/test/Transforms/LICM/scalar_promote.ll Thu Sep 2 17:19:10 2010 @@ -71,3 +71,50 @@ ret void } +; PR8041 +define void @test4(i8* %x, i8 %n) { +; CHECK: @test4 + %handle1 = alloca i8* + %handle2 = alloca i8* + store i8* %x, i8** %handle1 + br label %loop + +loop: + %tmp = getelementptr i8* %x, i64 8 + store i8* %tmp, i8** %handle2 + br label %subloop + +subloop: + %count = phi i8 [ 0, %loop ], [ %nextcount, %subloop ] + %offsetx2 = load i8** %handle2 + store i8 %n, i8* %offsetx2 + %newoffsetx2 = getelementptr i8* %offsetx2, i64 -1 + store i8* %newoffsetx2, i8** %handle2 + %nextcount = add i8 %count, 1 + %innerexitcond = icmp sge i8 %nextcount, 8 + br i1 %innerexitcond, label %innerexit, label %subloop + +; Should have promoted 'handle2' accesses. +; CHECK: subloop: +; CHECK-NEXT: phi i8* [ +; CHECK-NEXT: %count = phi i8 [ +; CHECK-NEXT: store i8 %n +; CHECK-NOT: store +; CHECK: br i1 + +innerexit: + %offsetx1 = load i8** %handle1 + %val = load i8* %offsetx1 + %cond = icmp eq i8 %val, %n + br i1 %cond, label %exit, label %loop + +; Should not have promoted offsetx1 loads. +; CHECK: innerexit: +; CHECK: %val = load i8* %offsetx1 +; CHECK: %cond = icmp eq i8 %val, %n +; CHECK: br i1 %cond, label %exit, label %loop + +exit: + ret void +} + From clattner at apple.com Thu Sep 2 17:22:28 2010 From: clattner at apple.com (Chris Lattner) Date: Thu, 2 Sep 2010 15:22:28 -0700 Subject: [llvm-commits] [llvm] r112869 - in /llvm/trunk/lib/Target/X86: AsmPrinter/X86InstComments.cpp X86ShuffleDecode.h In-Reply-To: References: <20100902215111.DEB032A6C12C@llvm.org> <2DDB83ED-B312-4D89-A108-059419D39EF7@apple.com> Message-ID: On Sep 2, 2010, at 3:07 PM, Bruno Cardoso Lopes wrote: > On Thu, Sep 2, 2010 at 3:01 PM, Chris Lattner wrote: >> >> On Sep 2, 2010, at 2:51 PM, Bruno Cardoso Lopes wrote: >> >>> Author: bruno >>> Date: Thu Sep 2 16:51:11 2010 >>> New Revision: 112869 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=112869&view=rev >>> Log: >>> Move decoding of insertps back to avoid unused warnings in x86 isel lowering, and fix movlhps/movhlps to decode 4 elements shuffles >> >> What warning? If it is about unused functions, just mark the function 'static inline'. > > A warning at the code I'm going to check-in, in X86ISelLowering, all > functions are going to be used but the insertps, which is not a > shuffle. If you mark them all 'inline' that warning will go away. insertps is a (funny) shuffle :), it would be nice to keep everything together in the header. -Chris From isanbard at gmail.com Thu Sep 2 17:26:36 2010 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 02 Sep 2010 22:26:36 -0000 Subject: [llvm-commits] [llvm] r112881 - /llvm/trunk/include/llvm/IntrinsicsX86.td Message-ID: <20100902222636.1333F2A6C12C@llvm.org> Author: void Date: Thu Sep 2 17:26:35 2010 New Revision: 112881 URL: http://llvm.org/viewvc/llvm-project?rev=112881&view=rev Log: - Change __builtin_ia32_palignr intrinsic type to match the pattern in clang. - Add patterns to match the following MMX builtins: * __builtin_ia32_vec_init_v8qi * __builtin_ia32_vec_init_v4hi * __builtin_ia32_vec_init_v2si * __builtin_ia32_vec_ext_v2si These builtins do not correspond to a single MMX instruction. They will have to be lowered -- most likely in the back-end. Modified: llvm/trunk/include/llvm/IntrinsicsX86.td Modified: llvm/trunk/include/llvm/IntrinsicsX86.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsX86.td?rev=112881&r1=112880&r2=112881&view=diff ============================================================================== --- llvm/trunk/include/llvm/IntrinsicsX86.td (original) +++ llvm/trunk/include/llvm/IntrinsicsX86.td Thu Sep 2 17:26:35 2010 @@ -1570,9 +1570,9 @@ def int_x86_mmx_movnt_dq : GCCBuiltin<"__builtin_ia32_movntq">, Intrinsic<[], [llvm_ptr_ty, llvm_v1i64_ty], []>; -// def int_x86_mmx_palignr_b : GCCBuiltin<"__builtin_ia32_palignr">, -// Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, -// llvm_v1i64_ty, llvm_i8_ty], [IntrNoMem]>; +// def int_x86_mmx_palignr_b : GCCBuiltin<"__builtin_ia32_palignr">, +// Intrinsic<[llvm_v8i8_ty], [llvm_8i8_ty, +// llvm_v8i8_ty, llvm_i8_ty], [IntrNoMem]>; def int_x86_mmx_pextr_w : Intrinsic<[llvm_i32_ty], [llvm_v1i64_ty, llvm_i32_ty], @@ -1583,7 +1583,26 @@ llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; def int_x86_mmx_cvtsi32_si64 : - Intrinsic<[llvm_v1i64_ty], [llvm_i32_ty], [IntrNoMem]>; + Intrinsic<[llvm_v1i64_ty], [llvm_i32_ty], [IntrNoMem]>; def int_x86_mmx_cvtsi64_si32 : - Intrinsic<[llvm_i32_ty], [llvm_v1i64_ty], [IntrNoMem]>; + Intrinsic<[llvm_i32_ty], [llvm_v1i64_ty], [IntrNoMem]>; + + def int_x86_mmx_vec_init_b : GCCBuiltin<"__builtin_ia32_vec_init_v8qi">, + Intrinsic<[llvm_v8i8_ty], + [llvm_i8_ty, llvm_i8_ty, llvm_i8_ty, llvm_i8_ty, + llvm_i8_ty, llvm_i8_ty, llvm_i8_ty, llvm_i8_ty], + [IntrNoMem]>; + def int_x86_mmx_vec_init_w : GCCBuiltin<"__builtin_ia32_vec_init_v4hi">, + Intrinsic<[llvm_v4i16_ty], + [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_i16_ty], + [IntrNoMem]>; + def int_x86_mmx_vec_init_d : GCCBuiltin<"__builtin_ia32_vec_init_v2si">, + Intrinsic<[llvm_v2i32_ty], + [llvm_i32_ty, llvm_i32_ty], + [IntrNoMem]>; + + def int_x86_mmx_vec_ext_d : GCCBuiltin<"__builtin_ia32_vec_ext_v2si">, + Intrinsic<[llvm_v2i32_ty], + [llvm_v2i32_ty, llvm_i32_ty], + [IntrNoMem]>; } From grosbach at apple.com Thu Sep 2 17:29:02 2010 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 02 Sep 2010 22:29:02 -0000 Subject: [llvm-commits] [llvm] r112883 - in /llvm/trunk: lib/Target/ARM/ARMBaseRegisterInfo.cpp lib/Target/ARM/ARMBaseRegisterInfo.h lib/Target/ARM/Thumb1RegisterInfo.cpp test/CodeGen/Thumb/dyn-stackalloc.ll test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll Message-ID: <20100902222902.13F3C2A6C12C@llvm.org> Author: grosbach Date: Thu Sep 2 17:29:01 2010 New Revision: 112883 URL: http://llvm.org/viewvc/llvm-project?rev=112883&view=rev Log: For ARM stack frames that utilize variable sized objects and have either large local stack areas or require dynamic stack realignment, allocate a base register via which to access the local frame. This allows efficient access to frame indices not accessible via the FP (either due to being out of range or due to dynamic realignment) or the SP (due to variable sized object allocation). In particular, this greatly improves efficiency of access to spill slots in Thumb functions which contain VLAs. rdar://7352504 rdar://8374540 rdar://8355680 Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp llvm/trunk/test/CodeGen/Thumb/dyn-stackalloc.ll llvm/trunk/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=112883&r1=112882&r2=112883&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Thu Sep 2 17:29:01 2010 @@ -50,6 +50,10 @@ using namespace llvm; +static cl::opt +EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true), + cl::desc("Enable use of a base pointer for complex stack frames")); + unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum, bool *isSPVFP) { if (isSPVFP) @@ -146,7 +150,8 @@ const ARMSubtarget &sti) : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), TII(tii), STI(sti), - FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) { + FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11), + BasePtr(ARM::R6) { } const unsigned* @@ -182,6 +187,8 @@ Reserved.set(ARM::FPSCR); if (hasFP(MF)) Reserved.set(FramePtr); + if (hasBasePointer(MF)) + Reserved.set(BasePtr); // Some targets reserve R9. if (STI.isR9Reserved()) Reserved.set(ARM::R9); @@ -195,6 +202,10 @@ case ARM::SP: case ARM::PC: return true; + case ARM::R6: + if (hasBasePointer(MF)) + return true; + break; case ARM::R7: case ARM::R11: if (FramePtr == Reg && hasFP(MF)) @@ -625,35 +636,49 @@ MFI->isFrameAddressTaken()); } -bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const { +bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); const ARMFunctionInfo *AFI = MF.getInfo(); - return (RealignStack && - !AFI->isThumb1OnlyFunction() && - !MFI->hasVarSizedObjects()); + + if (!EnableBasePointer) + return false; + + if (needsStackRealignment(MF) && MFI->hasVarSizedObjects()) + return true; + + // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited + // negative range for ldr/str (255), and thumb1 is positive offsets only. + // It's going to be better to use the SP or Base Pointer instead. When there + // are variable sized objects, we can't reference off of the SP, so we + // reserve a Base Pointer. + if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) { + // Conservatively estimate whether the negative offset from the frame + // pointer will be sufficient to reach. If a function has a smallish + // frame, it's less likely to have lots of spills and callee saved + // space, so it's all more likely to be within range of the frame pointer. + // If it's wrong, the scavenger will still enable access to work, it just + // won't be optimal. + if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128) + return false; + return true; + } + + return false; +} + +bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const { + const ARMFunctionInfo *AFI = MF.getInfo(); + return (RealignStack && !AFI->isThumb1OnlyFunction()); } bool ARMBaseRegisterInfo:: needsStackRealignment(const MachineFunction &MF) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); const Function *F = MF.getFunction(); - const ARMFunctionInfo *AFI = MF.getInfo(); unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) || F->hasFnAttr(Attribute::StackAlignment)); - // FIXME: Currently we don't support stack realignment for functions with - // variable-sized allocas. - // FIXME: It's more complicated than this... - if (0 && requiresRealignment && MFI->hasVarSizedObjects()) - report_fatal_error( - "Stack realignment in presense of dynamic allocas is not supported"); - - // FIXME: This probably isn't the right place for this. - if (0 && requiresRealignment && AFI->isThumb1OnlyFunction()) - report_fatal_error( - "Stack realignment in thumb1 functions is not supported"); - return requiresRealignment && canRealignStack(MF); } @@ -776,6 +801,10 @@ if (AFI->isThumb1OnlyFunction() && AFI->getVarArgsRegSaveSize() > 0) MF.getRegInfo().setPhysRegUsed(ARM::LR); + // Spill the BasePtr if it's used. + if (hasBasePointer(MF)) + MF.getRegInfo().setPhysRegUsed(BasePtr); + // Don't spill FP if the frame can be eliminated. This is determined // by scanning the callee-save registers to see if any is used. const unsigned *CSRegs = getCalleeSavedRegs(); @@ -1022,13 +1051,14 @@ return Offset - AFI->getDPRCalleeSavedAreaOffset(); // When dynamically realigning the stack, use the frame pointer for - // parameters, and the stack pointer for locals. + // parameters, and the stack/base pointer for locals. if (needsStackRealignment(MF)) { assert (hasFP(MF) && "dynamic stack realignment without a FP!"); if (isFixed) { FrameReg = getFrameRegister(MF); Offset = FPOffset; - } + } else if (MFI->hasVarSizedObjects()) + FrameReg = BasePtr; return Offset; } @@ -1036,9 +1066,13 @@ if (hasFP(MF) && AFI->hasStackFrame()) { // Use frame pointer to reference fixed objects. Use it for locals if // there are VLAs (and thus the SP isn't reliable as a base). - if (isFixed || MFI->hasVarSizedObjects()) { + if (isFixed || (MFI->hasVarSizedObjects() && !hasBasePointer(MF))) { FrameReg = getFrameRegister(MF); Offset = FPOffset; + } else if (MFI->hasVarSizedObjects()) { + assert(hasBasePointer(MF) && "missing base pointer!"); + // Use the base register since we have it. + FrameReg = BasePtr; } else if (AFI->isThumb2Function()) { // In Thumb2 mode, the negative offset is very limited. Try to avoid // out of range references. @@ -1052,6 +1086,9 @@ Offset = FPOffset; } } + // Use the base pointer if we have one. + if (hasBasePointer(MF)) + FrameReg = BasePtr; return Offset; } @@ -1089,7 +1126,8 @@ case ARM::R5: return ARM::R4; case ARM::R7: - return isReservedReg(MF, ARM::R7) ? 0 : ARM::R6; + return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6)) + ? 0 : ARM::R6; case ARM::R9: return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8; case ARM::R11: @@ -1178,7 +1216,8 @@ case ARM::R4: return ARM::R5; case ARM::R6: - return isReservedReg(MF, ARM::R7) ? 0 : ARM::R7; + return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6)) + ? 0 : ARM::R7; case ARM::R8: return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9; case ARM::R10: @@ -1878,6 +1917,20 @@ AFI->setShouldRestoreSPFromFP(true); } + // If we need a base pointer, set it up here. It's whatever the value + // of the stack pointer is at this point. Any variable size objects + // will be allocated after this, so we can still use the base pointer + // to reference locals. + if (hasBasePointer(MF)) { + if (isARM) + BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), BasePtr) + .addReg(ARM::SP) + .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); + else + BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), BasePtr) + .addReg(ARM::SP); + } + // If the frame has variable sized objects then the epilogue must restore // the sp from fp. if (!AFI->shouldRestoreSPFromFP() && MFI->hasVarSizedObjects()) Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h?rev=112883&r1=112882&r2=112883&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h Thu Sep 2 17:29:01 2010 @@ -52,6 +52,11 @@ /// FramePtr - ARM physical register used as frame ptr. unsigned FramePtr; + /// BasePtr - ARM physical register used as a base ptr in complex stack + /// frames. I.e., when we need a 3rd base, not just SP and FP, due to + /// variable size stack objects. + unsigned BasePtr; + // Can be only subclassed. explicit ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI); @@ -102,6 +107,7 @@ MachineFunction &MF) const; bool hasFP(const MachineFunction &MF) const; + bool hasBasePointer(const MachineFunction &MF) const; bool canRealignStack(const MachineFunction &MF) const; bool needsStackRealignment(const MachineFunction &MF) const; Modified: llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp?rev=112883&r1=112882&r2=112883&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp Thu Sep 2 17:29:01 2010 @@ -604,9 +604,12 @@ else if (MF.getFrameInfo()->hasVarSizedObjects()) { assert(SPAdj == 0 && hasFP(MF) && "Unexpected"); // There are alloca()'s in this function, must reference off the frame - // pointer instead. - FrameReg = getFrameRegister(MF); - Offset -= AFI->getFramePtrSpillOffset(); + // pointer or base pointer instead. + if (!hasBasePointer(MF)) { + FrameReg = getFrameRegister(MF); + Offset -= AFI->getFramePtrSpillOffset(); + } else + FrameReg = BasePtr; } // Special handling of dbg_value instructions. @@ -787,6 +790,13 @@ AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); AFI->setDPRCalleeSavedAreaSize(DPRCSSize); + + // If we need a base pointer, set it up here. It's whatever the value + // of the stack pointer is at this point. Any variable size objects + // will be allocated after this, so we can still use the base pointer + // to reference locals. + if (hasBasePointer(MF)) + BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), BasePtr).addReg(ARM::SP); } static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) { Modified: llvm/trunk/test/CodeGen/Thumb/dyn-stackalloc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/dyn-stackalloc.ll?rev=112883&r1=112882&r2=112883&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/dyn-stackalloc.ll (original) +++ llvm/trunk/test/CodeGen/Thumb/dyn-stackalloc.ll Thu Sep 2 17:29:01 2010 @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=thumb | not grep {ldr sp} ; RUN: llc < %s -mtriple=thumb-apple-darwin | \ ; RUN: not grep {sub.*r7} -; RUN: llc < %s -march=thumb | grep 4294967280 +; RUN: llc < %s -march=thumb | grep {mov.*r6, sp} %struct.state = type { i32, %struct.info*, float**, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64, i64, i64, i64, i64, i64, i8* } %struct.info = type { i32, i32, i32, i32, i32, i32, i32, i8* } Modified: llvm/trunk/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll?rev=112883&r1=112882&r2=112883&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll Thu Sep 2 17:29:01 2010 @@ -7,19 +7,12 @@ define void @t() nounwind ssp { entry: ; CHECK: t: -; CHECK: push {r4, r7} -; CHECK: mov r0, sp -; CHECK: add r7, sp, #4 -; CHECK: bic r0, r0, #7 + %size = mul i32 8, 2 ; CHECK: subs r0, #16 ; CHECK: mov sp, r0 -; CHECK: mov r0, sp -; CHECK: bic r0, r0, #7 + %vla_a = alloca i8, i32 %size, align 8 ; CHECK: subs r0, #16 ; CHECK: mov sp, r0 - - %size = mul i32 8, 2 - %vla_a = alloca i8, i32 %size, align 8 %vla_b = alloca i8, i32 %size, align 8 unreachable } From echristo at apple.com Thu Sep 2 17:30:22 2010 From: echristo at apple.com (Eric Christopher) Date: Thu, 2 Sep 2010 15:30:22 -0700 Subject: [llvm-commits] [llvm] r112881 - /llvm/trunk/include/llvm/IntrinsicsX86.td In-Reply-To: <20100902222636.1333F2A6C12C@llvm.org> References: <20100902222636.1333F2A6C12C@llvm.org> Message-ID: On Sep 2, 2010, at 3:26 PM, Bill Wendling wrote: > -// def int_x86_mmx_palignr_b : GCCBuiltin<"__builtin_ia32_palignr">, > -// Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, > -// llvm_v1i64_ty, llvm_i8_ty], [IntrNoMem]>; > +// def int_x86_mmx_palignr_b : GCCBuiltin<"__builtin_ia32_palignr">, > +// Intrinsic<[llvm_v8i8_ty], [llvm_8i8_ty, > +// llvm_v8i8_ty, llvm_i8_ty], [IntrNoMem]>; This will, if it's ever re-enabled, likely not match the one coming from llvm-gcc. -eric From isanbard at gmail.com Thu Sep 2 17:31:35 2010 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 2 Sep 2010 15:31:35 -0700 Subject: [llvm-commits] [llvm] r112881 - /llvm/trunk/include/llvm/IntrinsicsX86.td In-Reply-To: References: <20100902222636.1333F2A6C12C@llvm.org> Message-ID: <5A66D3AE-02E5-4E88-8EC6-DCB74A5B8D86@gmail.com> On Sep 2, 2010, at 3:30 PM, Eric Christopher wrote: > On Sep 2, 2010, at 3:26 PM, Bill Wendling wrote: > >> -// def int_x86_mmx_palignr_b : GCCBuiltin<"__builtin_ia32_palignr">, >> -// Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, >> -// llvm_v1i64_ty, llvm_i8_ty], [IntrNoMem]>; >> +// def int_x86_mmx_palignr_b : GCCBuiltin<"__builtin_ia32_palignr">, >> +// Intrinsic<[llvm_v8i8_ty], [llvm_8i8_ty, >> +// llvm_v8i8_ty, llvm_i8_ty], [IntrNoMem]>; > > This will, if it's ever re-enabled, likely not match the one coming from llvm-gcc. > The one from llvm-gcc was changed awhile ago from "long long" to "v1di". I think the original was correct, but clang doesn't seem to agree... Eh...I'll change it back. -bw From asl at math.spbu.ru Thu Sep 2 17:31:32 2010 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Thu, 02 Sep 2010 22:31:32 -0000 Subject: [llvm-commits] [llvm] r112885 - in /llvm/trunk/lib/Target/X86: X86ISelLowering.cpp X86RegisterInfo.cpp Message-ID: <20100902223132.78D7C2A6C12C@llvm.org> Author: asl Date: Thu Sep 2 17:31:32 2010 New Revision: 112885 URL: http://llvm.org/viewvc/llvm-project?rev=112885&view=rev Log: Revert win64 changes. They seem to be incomplete Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=112885&r1=112884&r2=112885&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Sep 2 17:31:32 2010 @@ -1616,11 +1616,6 @@ SmallVector ArgLocs; CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs, *DAG.getContext()); - - // Allocate shadow area for Win64 - if (IsWin64) - CCInfo.AllocateStack(32, 8); - CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv)); unsigned LastVal = ~0U; @@ -1847,7 +1842,8 @@ DebugLoc dl, SelectionDAG &DAG, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const { - unsigned LocMemOffset = VA.getLocMemOffset(); + const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0); + unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset(); SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); if (Flags.isByVal()) { @@ -1930,11 +1926,6 @@ SmallVector ArgLocs; CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs, *DAG.getContext()); - - // Allocate shadow area for Win64 - if (Subtarget->isTargetWin64()) - CCInfo.AllocateStack(32, 8); - CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv)); // Get a count of how many bytes are to be pushed on the stack. Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=112885&r1=112884&r2=112885&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Thu Sep 2 17:31:32 2010 @@ -945,6 +945,11 @@ if (HasFP) MinSize += SlotSize; StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0); MFI->setStackSize(StackSize); + } else if (Subtarget->isTargetWin64()) { + // We need to always allocate 32 bytes as register spill area. + // FIXME: We might reuse these 32 bytes for leaf functions. + StackSize += 32; + MFI->setStackSize(StackSize); } // Insert stack pointer adjustment for later moving of return addr. Only From isanbard at gmail.com Thu Sep 2 17:31:53 2010 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 02 Sep 2010 22:31:53 -0000 Subject: [llvm-commits] [llvm] r112886 - /llvm/trunk/include/llvm/IntrinsicsX86.td Message-ID: <20100902223153.AD5C22A6C12C@llvm.org> Author: void Date: Thu Sep 2 17:31:53 2010 New Revision: 112886 URL: http://llvm.org/viewvc/llvm-project?rev=112886&view=rev Log: Revert int_x86_mmx_palignr_b intrinsic to match llvm-gcc's version. Modified: llvm/trunk/include/llvm/IntrinsicsX86.td Modified: llvm/trunk/include/llvm/IntrinsicsX86.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsX86.td?rev=112886&r1=112885&r2=112886&view=diff ============================================================================== --- llvm/trunk/include/llvm/IntrinsicsX86.td (original) +++ llvm/trunk/include/llvm/IntrinsicsX86.td Thu Sep 2 17:31:53 2010 @@ -1571,8 +1571,8 @@ Intrinsic<[], [llvm_ptr_ty, llvm_v1i64_ty], []>; // def int_x86_mmx_palignr_b : GCCBuiltin<"__builtin_ia32_palignr">, -// Intrinsic<[llvm_v8i8_ty], [llvm_8i8_ty, -// llvm_v8i8_ty, llvm_i8_ty], [IntrNoMem]>; +// Intrinsic<[llvm_v1i64_ty], [llvm_1i64_ty, +// llvm_v1i64_ty, llvm_i8_ty], [IntrNoMem]>; def int_x86_mmx_pextr_w : Intrinsic<[llvm_i32_ty], [llvm_v1i64_ty, llvm_i32_ty], From sabre at nondot.org Thu Sep 2 17:32:02 2010 From: sabre at nondot.org (Chris Lattner) Date: Thu, 02 Sep 2010 22:32:02 -0000 Subject: [llvm-commits] [llvm] r112887 - in /llvm/trunk/test/Integer: a15.ll a15.ll.out a17.ll a17.ll.out a31.ll a31.ll.out a33.ll a33.ll.out a63.ll a63.ll.out a7.ll a7.ll.out a9.ll a9.ll.out Message-ID: <20100902223202.7A0AE2A6C12C@llvm.org> Author: lattner Date: Thu Sep 2 17:32:02 2010 New Revision: 112887 URL: http://llvm.org/viewvc/llvm-project?rev=112887&view=rev Log: we are past the point where these tests are useful. Removed: llvm/trunk/test/Integer/a15.ll llvm/trunk/test/Integer/a15.ll.out llvm/trunk/test/Integer/a17.ll llvm/trunk/test/Integer/a17.ll.out llvm/trunk/test/Integer/a31.ll llvm/trunk/test/Integer/a31.ll.out llvm/trunk/test/Integer/a33.ll llvm/trunk/test/Integer/a33.ll.out llvm/trunk/test/Integer/a63.ll llvm/trunk/test/Integer/a63.ll.out llvm/trunk/test/Integer/a7.ll llvm/trunk/test/Integer/a7.ll.out llvm/trunk/test/Integer/a9.ll llvm/trunk/test/Integer/a9.ll.out Removed: llvm/trunk/test/Integer/a15.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Integer/a15.ll?rev=112886&view=auto ============================================================================== --- llvm/trunk/test/Integer/a15.ll (original) +++ llvm/trunk/test/Integer/a15.ll (removed) @@ -1,27 +0,0 @@ -; RUN: llvm-as %s -o - | llvm-dis > %t.ll -; RUN: diff %t.ll %s.out - -; test 15 bits -; - at b = constant i15 add(i15 32767, i15 1) - at c = constant i15 add(i15 32767, i15 32767) - at d = constant i15 add(i15 32760, i15 8) - at e = constant i15 sub(i15 0 , i15 1) - at f = constant i15 sub(i15 0 , i15 32767) - at g = constant i15 sub(i15 2 , i15 32767) - - at h = constant i15 shl(i15 1 , i15 15) - at i = constant i15 shl(i15 1 , i15 14) - at j = constant i15 lshr(i15 32767 , i15 14) - at l = constant i15 ashr(i15 32767 , i15 14) - - at n = constant i15 mul(i15 32767, i15 2) - at q = constant i15 mul(i15 -16383,i15 -3) - at r = constant i15 sdiv(i15 -1, i15 16383) - at s = constant i15 udiv(i15 -1, i15 16383) - at t = constant i15 srem(i15 1, i15 32766) - at u = constant i15 urem(i15 32767,i15 -1) - at o = constant i15 trunc( i16 32768 to i15 ) - at p = constant i15 trunc( i16 32767 to i15 ) - at v = constant i15 srem(i15 -1, i15 768) - Removed: llvm/trunk/test/Integer/a15.ll.out URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Integer/a15.ll.out?rev=112886&view=auto ============================================================================== --- llvm/trunk/test/Integer/a15.ll.out (original) +++ llvm/trunk/test/Integer/a15.ll.out (removed) @@ -1,21 +0,0 @@ -; ModuleID = '' - - at b = constant i15 0 ; [#uses=0] - at c = constant i15 -2 ; [#uses=0] - at d = constant i15 0 ; [#uses=0] - at e = constant i15 -1 ; [#uses=0] - at f = constant i15 1 ; [#uses=0] - at g = constant i15 3 ; [#uses=0] - at h = constant i15 undef ; [#uses=0] - at i = constant i15 -16384 ; [#uses=0] - at j = constant i15 1 ; [#uses=0] - at l = constant i15 -1 ; [#uses=0] - at n = constant i15 -2 ; [#uses=0] - at q = constant i15 16381 ; [#uses=0] - at r = constant i15 0 ; [#uses=0] - at s = constant i15 2 ; [#uses=0] - at t = constant i15 1 ; [#uses=0] - at u = constant i15 0 ; [#uses=0] - at o = constant i15 0 ; [#uses=0] - at p = constant i15 -1 ; [#uses=0] - at v = constant i15 -1 ; [#uses=0] Removed: llvm/trunk/test/Integer/a17.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Integer/a17.ll?rev=112886&view=auto ============================================================================== --- llvm/trunk/test/Integer/a17.ll (original) +++ llvm/trunk/test/Integer/a17.ll (removed) @@ -1,25 +0,0 @@ -; RUN: llvm-as %s -o - | llvm-dis > %t.ll -; RUN: diff %t.ll %s.out - -; test 17 bits -; - at b = constant i17 add(i17 131071, i17 1) - at c = constant i17 add(i17 131071, i17 131071) - at d = constant i17 add(i17 131064, i17 8) - at e = constant i17 sub(i17 0 , i17 1) - at f = constant i17 sub(i17 0 , i17 131071) - at g = constant i17 sub(i17 2 , i17 131071) - - at h = constant i17 shl(i17 1 , i17 17) - at i = constant i17 shl(i17 1 , i17 16) - at j = constant i17 lshr(i17 131071 , i17 16) - at l = constant i17 ashr(i17 131071 , i17 16) - - at n = constant i17 mul(i17 131071, i17 2) - at q = constant i17 sdiv(i17 -1, i17 65535) - at r = constant i17 udiv(i17 -1, i17 65535) - at s = constant i17 srem(i17 1, i17 131070) - at t = constant i17 urem(i17 131071,i17 -1) - at o = constant i17 trunc( i18 131072 to i17 ) - at p = constant i17 trunc( i18 131071 to i17 ) - at v = constant i17 srem(i17 -1, i17 15) Removed: llvm/trunk/test/Integer/a17.ll.out URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Integer/a17.ll.out?rev=112886&view=auto ============================================================================== --- llvm/trunk/test/Integer/a17.ll.out (original) +++ llvm/trunk/test/Integer/a17.ll.out (removed) @@ -1,20 +0,0 @@ -; ModuleID = '' - - at b = constant i17 0 ; [#uses=0] - at c = constant i17 -2 ; [#uses=0] - at d = constant i17 0 ; [#uses=0] - at e = constant i17 -1 ; [#uses=0] - at f = constant i17 1 ; [#uses=0] - at g = constant i17 3 ; [#uses=0] - at h = constant i17 undef ; [#uses=0] - at i = constant i17 -65536 ; [#uses=0] - at j = constant i17 1 ; [#uses=0] - at l = constant i17 -1 ; [#uses=0] - at n = constant i17 -2 ; [#uses=0] - at q = constant i17 0 ; [#uses=0] - at r = constant i17 2 ; [#uses=0] - at s = constant i17 1 ; [#uses=0] - at t = constant i17 0 ; [#uses=0] - at o = constant i17 0 ; [#uses=0] - at p = constant i17 -1 ; [#uses=0] - at v = constant i17 -1 ; [#uses=0] Removed: llvm/trunk/test/Integer/a31.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Integer/a31.ll?rev=112886&view=auto ============================================================================== --- llvm/trunk/test/Integer/a31.ll (original) +++ llvm/trunk/test/Integer/a31.ll (removed) @@ -1,25 +0,0 @@ -; RUN: llvm-as %s -o - | llvm-dis > %t.ll -; RUN: diff %t.ll %s.out - -; test 31 bits -; - at b = constant i31 add(i31 2147483647, i31 1) - at c = constant i31 add(i31 2147483647, i31 2147483647) - at d = constant i31 add(i31 2147483640, i31 8) - at e = constant i31 sub(i31 0 , i31 1) - at f = constant i31 sub(i31 0 , i31 2147483647) - at g = constant i31 sub(i31 2 , i31 2147483647) - - at h = constant i31 shl(i31 1 , i31 31) - at i = constant i31 shl(i31 1 , i31 30) - at j = constant i31 lshr(i31 2147483647 , i31 30) - at l = constant i31 ashr(i31 2147483647 , i31 30) - - at n = constant i31 mul(i31 2147483647, i31 2) - at q = constant i31 sdiv(i31 -1, i31 1073741823) - at r = constant i31 udiv(i31 -1, i31 1073741823) - at s = constant i31 srem(i31 1, i31 2147483646) - at t = constant i31 urem(i31 2147483647,i31 -1) - at o = constant i31 trunc( i32 2147483648 to i31 ) - at p = constant i31 trunc( i32 2147483647 to i31 ) - at u = constant i31 srem(i31 -3, i31 17) Removed: llvm/trunk/test/Integer/a31.ll.out URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Integer/a31.ll.out?rev=112886&view=auto ============================================================================== --- llvm/trunk/test/Integer/a31.ll.out (original) +++ llvm/trunk/test/Integer/a31.ll.out (removed) @@ -1,20 +0,0 @@ -; ModuleID = '' - - at b = constant i31 0 ; [#uses=0] - at c = constant i31 -2 ; [#uses=0] - at d = constant i31 0 ; [#uses=0] - at e = constant i31 -1 ; [#uses=0] - at f = constant i31 1 ; [#uses=0] - at g = constant i31 3 ; [#uses=0] - at h = constant i31 undef ; [#uses=0] - at i = constant i31 -1073741824 ; [#uses=0] - at j = constant i31 1 ; [#uses=0] - at l = constant i31 -1 ; [#uses=0] - at n = constant i31 -2 ; [#uses=0] - at q = constant i31 0 ; [#uses=0] - at r = constant i31 2 ; [#uses=0] - at s = constant i31 1 ; [#uses=0] - at t = constant i31 0 ; [#uses=0] - at o = constant i31 0 ; [#uses=0] - at p = constant i31 -1 ; [#uses=0] - at u = constant i31 -3 ; [#uses=0] Removed: llvm/trunk/test/Integer/a33.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Integer/a33.ll?rev=112886&view=auto ============================================================================== --- llvm/trunk/test/Integer/a33.ll (original) +++ llvm/trunk/test/Integer/a33.ll (removed) @@ -1,26 +0,0 @@ -; RUN: llvm-as %s -o - | llvm-dis > %t.ll -; RUN: diff %t.ll %s.out - -; test 33 bits -; - at b = constant i33 add(i33 8589934591, i33 1) - at c = constant i33 add(i33 8589934591, i33 8589934591) - at d = constant i33 add(i33 8589934584, i33 8) - at e = constant i33 sub(i33 0 , i33 1) - at f = constant i33 sub(i33 0 , i33 8589934591) - at g = constant i33 sub(i33 2 , i33 8589934591) - - at h = constant i33 shl(i33 1 , i33 33) - at i = constant i33 shl(i33 1 , i33 32) - at j = constant i33 lshr(i33 8589934591 , i33 32) - at l = constant i33 ashr(i33 8589934591 , i33 32) - - at n = constant i33 mul(i33 8589934591, i33 2) - at q = constant i33 sdiv(i33 -1, i33 4294967295) - at r = constant i33 udiv(i33 -1, i33 4294967295) - at s = constant i33 srem(i33 1, i33 8589934590) - at t = constant i33 urem(i33 8589934591,i33 -1) - at o = constant i33 trunc( i34 8589934592 to i33 ) - at p = constant i33 trunc( i34 8589934591 to i33 ) - at u = constant i33 srem(i33 -1, i33 17) - Removed: llvm/trunk/test/Integer/a33.ll.out URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Integer/a33.ll.out?rev=112886&view=auto ============================================================================== --- llvm/trunk/test/Integer/a33.ll.out (original) +++ llvm/trunk/test/Integer/a33.ll.out (removed) @@ -1,20 +0,0 @@ -; ModuleID = '' - - at b = constant i33 0 ; [#uses=0] - at c = constant i33 -2 ; [#uses=0] - at d = constant i33 0 ; [#uses=0] - at e = constant i33 -1 ; [#uses=0] - at f = constant i33 1 ; [#uses=0] - at g = constant i33 3 ; [#uses=0] - at h = constant i33 undef ; [#uses=0] - at i = constant i33 -4294967296 ; [#uses=0] - at j = constant i33 1 ; [#uses=0] - at l = constant i33 -1 ; [#uses=0] - at n = constant i33 -2 ; [#uses=0] - at q = constant i33 0 ; [#uses=0] - at r = constant i33 2 ; [#uses=0] - at s = constant i33 1 ; [#uses=0] - at t = constant i33 0 ; [#uses=0] - at o = constant i33 0 ; [#uses=0] - at p = constant i33 -1 ; [#uses=0] - at u = constant i33 -1 ; [#uses=0] Removed: llvm/trunk/test/Integer/a63.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Integer/a63.ll?rev=112886&view=auto ============================================================================== --- llvm/trunk/test/Integer/a63.ll (original) +++ llvm/trunk/test/Integer/a63.ll (removed) @@ -1,25 +0,0 @@ -; RUN: llvm-as %s -o - | llvm-dis > %t.ll -; RUN: diff %t.ll %s.out - -; test 63 bits -; - at b = constant i63 add(i63 9223372036854775807, i63 1) - at c = constant i63 add(i63 9223372036854775807, i63 9223372036854775807) - at d = constant i63 add(i63 9223372036854775800, i63 8) - at e = constant i63 sub(i63 0 , i63 1) - at f = constant i63 sub(i63 0 , i63 9223372036854775807) - at g = constant i63 sub(i63 2 , i63 9223372036854775807) - - at h = constant i63 shl(i63 1 , i63 63) - at i = constant i63 shl(i63 1 , i63 62) - at j = constant i63 lshr(i63 9223372036854775807 , i63 62) - at l = constant i63 ashr(i63 9223372036854775807 , i63 62) - - at n = constant i63 mul(i63 9223372036854775807, i63 2) - at q = constant i63 sdiv(i63 -1, i63 4611686018427387903) - at u = constant i63 sdiv(i63 -1, i63 1) - at r = constant i63 udiv(i63 -1, i63 4611686018427387903) - at s = constant i63 srem(i63 3, i63 9223372036854775806) - at t = constant i63 urem(i63 9223372036854775807,i63 -1) - at o = constant i63 trunc( i64 9223372036854775808 to i63 ) - at p = constant i63 trunc( i64 9223372036854775807 to i63 ) Removed: llvm/trunk/test/Integer/a63.ll.out URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Integer/a63.ll.out?rev=112886&view=auto ============================================================================== --- llvm/trunk/test/Integer/a63.ll.out (original) +++ llvm/trunk/test/Integer/a63.ll.out (removed) @@ -1,20 +0,0 @@ -; ModuleID = '' - - at b = constant i63 0 ; [#uses=0] - at c = constant i63 -2 ; [#uses=0] - at d = constant i63 0 ; [#uses=0] - at e = constant i63 -1 ; [#uses=0] - at f = constant i63 1 ; [#uses=0] - at g = constant i63 3 ; [#uses=0] - at h = constant i63 undef ; [#uses=0] - at i = constant i63 -4611686018427387904 ; [#uses=0] - at j = constant i63 1 ; [#uses=0] - at l = constant i63 -1 ; [#uses=0] - at n = constant i63 -2 ; [#uses=0] - at q = constant i63 0 ; [#uses=0] - at u = constant i63 -1 ; [#uses=0] - at r = constant i63 2 ; [#uses=0] - at s = constant i63 1 ; [#uses=0] - at t = constant i63 0 ; [#uses=0] - at o = constant i63 0 ; [#uses=0] - at p = constant i63 -1 ; [#uses=0] Removed: llvm/trunk/test/Integer/a7.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Integer/a7.ll?rev=112886&view=auto ============================================================================== --- llvm/trunk/test/Integer/a7.ll (original) +++ llvm/trunk/test/Integer/a7.ll (removed) @@ -1,31 +0,0 @@ -; RUN: llvm-as %s -o - | llvm-dis > %t.ll -; RUN: diff %t.ll %s.out - -; test 7 bits -; - at b = constant i7 add(i7 127, i7 1) - at q = constant i7 add(i7 -64, i7 -1) - at c = constant i7 add(i7 127, i7 127) - at d = constant i7 add(i7 120, i7 8) - at e = constant i7 sub(i7 0 , i7 1) - at f = constant i7 sub(i7 0 , i7 127) - at g = constant i7 sub(i7 2 , i7 127) - at r = constant i7 sub(i7 -3, i7 120) - at s = constant i7 sub(i7 -3, i7 -8) - - at h = constant i7 shl(i7 1 , i7 7) - at i = constant i7 shl(i7 1 , i7 6) - at j = constant i7 lshr(i7 127 , i7 6) - at l = constant i7 ashr(i7 127 , i7 6) - at m2= constant i7 ashr(i7 -1 , i7 3) - - at n = constant i7 mul(i7 127, i7 2) - at t = constant i7 mul(i7 -63, i7 -2) - at u = constant i7 mul(i7 -32, i7 2) - at v = constant i7 sdiv(i7 -1, i7 63) - at w = constant i7 udiv(i7 -1, i7 63) - at x = constant i7 srem(i7 1 , i7 126) - at y = constant i7 urem(i7 127, i7 -1) - at o = constant i7 trunc( i8 128 to i7 ) - at p = constant i7 trunc( i8 255 to i7 ) - Removed: llvm/trunk/test/Integer/a7.ll.out URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Integer/a7.ll.out?rev=112886&view=auto ============================================================================== --- llvm/trunk/test/Integer/a7.ll.out (original) +++ llvm/trunk/test/Integer/a7.ll.out (removed) @@ -1,25 +0,0 @@ -; ModuleID = '' - - at b = constant i7 0 ; [#uses=0] - at q = constant i7 63 ; [#uses=0] - at c = constant i7 -2 ; [#uses=0] - at d = constant i7 0 ; [#uses=0] - at e = constant i7 -1 ; [#uses=0] - at f = constant i7 1 ; [#uses=0] - at g = constant i7 3 ; [#uses=0] - at r = constant i7 5 ; [#uses=0] - at s = constant i7 5 ; [#uses=0] - at h = constant i7 undef ; [#uses=0] - at i = constant i7 -64 ; [#uses=0] - at j = constant i7 1 ; [#uses=0] - at l = constant i7 -1 ; [#uses=0] - at m2 = constant i7 -1 ; [#uses=0] - at n = constant i7 -2 ; [#uses=0] - at t = constant i7 -2 ; [#uses=0] - at u = constant i7 -64 ; [#uses=0] - at v = constant i7 0 ; [#uses=0] - at w = constant i7 2 ; [#uses=0] - at x = constant i7 1 ; [#uses=0] - at y = constant i7 0 ; [#uses=0] - at o = constant i7 0 ; [#uses=0] - at p = constant i7 -1 ; [#uses=0] Removed: llvm/trunk/test/Integer/a9.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Integer/a9.ll?rev=112886&view=auto ============================================================================== --- llvm/trunk/test/Integer/a9.ll (original) +++ llvm/trunk/test/Integer/a9.ll (removed) @@ -1,25 +0,0 @@ -; RUN: llvm-as %s -o - | llvm-dis > %t.ll -; RUN: diff %t.ll %s.out - -; test 9 bits -; - at b = constant i9 add(i9 511, i9 1) - at c = constant i9 add(i9 511, i9 511) - at d = constant i9 add(i9 504, i9 8) - at e = constant i9 sub(i9 0 , i9 1) - at f = constant i9 sub(i9 0 , i9 511) - at g = constant i9 sub(i9 2 , i9 511) - - at h = constant i9 shl(i9 1 , i9 9) - at i = constant i9 shl(i9 1 , i9 8) - at j = constant i9 lshr(i9 511 , i9 8) - at l = constant i9 ashr(i9 511 , i9 8) - - at n = constant i9 mul(i9 511, i9 2) - at q = constant i9 sdiv(i9 511, i9 2) - at r = constant i9 udiv(i9 511, i9 2) - at s = constant i9 urem(i9 511, i9 -1) - at t = constant i9 srem(i9 1, i9 510) - at o = constant i9 trunc( i10 512 to i9 ) - at p = constant i9 trunc( i10 511 to i9 ) - Removed: llvm/trunk/test/Integer/a9.ll.out URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Integer/a9.ll.out?rev=112886&view=auto ============================================================================== --- llvm/trunk/test/Integer/a9.ll.out (original) +++ llvm/trunk/test/Integer/a9.ll.out (removed) @@ -1,19 +0,0 @@ -; ModuleID = '' - - at b = constant i9 0 ; [#uses=0] - at c = constant i9 -2 ; [#uses=0] - at d = constant i9 0 ; [#uses=0] - at e = constant i9 -1 ; [#uses=0] - at f = constant i9 1 ; [#uses=0] - at g = constant i9 3 ; [#uses=0] - at h = constant i9 undef ; [#uses=0] - at i = constant i9 -256 ; [#uses=0] - at j = constant i9 1 ; [#uses=0] - at l = constant i9 -1 ; [#uses=0] - at n = constant i9 -2 ; [#uses=0] - at q = constant i9 0 ; [#uses=0] - at r = constant i9 255 ; [#uses=0] - at s = constant i9 0 ; [#uses=0] - at t = constant i9 1 ; [#uses=0] - at o = constant i9 0 ; [#uses=0] - at p = constant i9 -1 ; [#uses=0] From gohman at apple.com Thu Sep 2 17:32:38 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 02 Sep 2010 22:32:38 -0000 Subject: [llvm-commits] [llvm] r112888 - /llvm/trunk/lib/Support/SystemUtils.cpp Message-ID: <20100902223238.3DFB62A6C12C@llvm.org> Author: djg Date: Thu Sep 2 17:32:38 2010 New Revision: 112888 URL: http://llvm.org/viewvc/llvm-project?rev=112888&view=rev Log: Use the FindProgramByName fallback only with known absolute paths. I wasn't able to convince myself that all GetMainExecutable implementations always return absolute paths; this prevents unexpected behavior in case they ever don't. Modified: llvm/trunk/lib/Support/SystemUtils.cpp Modified: llvm/trunk/lib/Support/SystemUtils.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/SystemUtils.cpp?rev=112888&r1=112887&r2=112888&view=diff ============================================================================== --- llvm/trunk/lib/Support/SystemUtils.cpp (original) +++ llvm/trunk/lib/Support/SystemUtils.cpp Thu Sep 2 17:32:38 2010 @@ -49,10 +49,16 @@ Result.appendComponent(ExeName); if (Result.canExecute()) return Result; - // Expect to retrieve the pathname with suffix .exe. - Result = sys::Program::FindProgramByName(Result.str()); - if (!Result.empty()) - return Result; + // If the path is absolute (and it usually is), call FindProgramByName to + // allow it to try platform-specific logic, such as appending a .exe suffix + // on Windows. Don't do this if we somehow have a relative path, because + // we don't want to go searching the PATH and accidentally find an unrelated + // version of the program. + if (Result.isAbsolute()) { + Result = sys::Program::FindProgramByName(Result.str()); + if (!Result.empty()) + return Result; + } } return sys::Path(); From bruno.cardoso at gmail.com Thu Sep 2 17:35:58 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Thu, 2 Sep 2010 15:35:58 -0700 Subject: [llvm-commits] [llvm] r112869 - in /llvm/trunk/lib/Target/X86: AsmPrinter/X86InstComments.cpp X86ShuffleDecode.h In-Reply-To: References: <20100902215111.DEB032A6C12C@llvm.org> <2DDB83ED-B312-4D89-A108-059419D39EF7@apple.com> Message-ID: On Thu, Sep 2, 2010 at 3:22 PM, Chris Lattner wrote: > > On Sep 2, 2010, at 3:07 PM, Bruno Cardoso Lopes wrote: > >> On Thu, Sep 2, 2010 at 3:01 PM, Chris Lattner wrote: >>> >>> On Sep 2, 2010, at 2:51 PM, Bruno Cardoso Lopes wrote: >>> >>>> Author: bruno >>>> Date: Thu Sep ?2 16:51:11 2010 >>>> New Revision: 112869 >>>> >>>> URL: http://llvm.org/viewvc/llvm-project?rev=112869&view=rev >>>> Log: >>>> Move decoding of insertps back to avoid unused warnings in x86 isel lowering, and fix movlhps/movhlps to decode 4 elements shuffles >>> >>> What warning? ?If it is about unused functions, just mark the function 'static inline'. >> >> A warning at the code I'm going to check-in, in X86ISelLowering, all >> functions are going to be used but the insertps, which is not a >> shuffle. > > If you mark them all 'inline' that warning will go away. ?insertps is a (funny) shuffle :), it would be nice to keep everything together in the header. > > -Chris Yep! :) -- Bruno Cardoso Lopes http://www.brunocardoso.cc From sabre at nondot.org Thu Sep 2 17:35:33 2010 From: sabre at nondot.org (Chris Lattner) Date: Thu, 02 Sep 2010 22:35:33 -0000 Subject: [llvm-commits] [llvm] r112889 - in /llvm/trunk/test: Analysis/BasicAA/args-rets-allocas-loads.ll Analysis/ScalarEvolution/avoid-smax-1.ll Assembler/getelementptr.ll Transforms/ConstProp/constant-expr.ll Message-ID: <20100902223533.9FB632A6C12C@llvm.org> Author: lattner Date: Thu Sep 2 17:35:33 2010 New Revision: 112889 URL: http://llvm.org/viewvc/llvm-project?rev=112889&view=rev Log: remove some noise from tests. Modified: llvm/trunk/test/Analysis/BasicAA/args-rets-allocas-loads.ll llvm/trunk/test/Analysis/ScalarEvolution/avoid-smax-1.ll llvm/trunk/test/Assembler/getelementptr.ll llvm/trunk/test/Transforms/ConstProp/constant-expr.ll Modified: llvm/trunk/test/Analysis/BasicAA/args-rets-allocas-loads.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/BasicAA/args-rets-allocas-loads.ll?rev=112889&r1=112888&r2=112889&view=diff ============================================================================== --- llvm/trunk/test/Analysis/BasicAA/args-rets-allocas-loads.ll (original) +++ llvm/trunk/test/Analysis/BasicAA/args-rets-allocas-loads.ll Thu Sep 2 17:35:33 2010 @@ -168,70 +168,70 @@ ; CHECK: NoAlias: double* %noalias_ret_a1, double* %normal_ret_a0 ; CHECK: NoAlias: double* %noalias_ret_a1, double* %normal_ret_a1 ; CHECK: NoAlias: double* %noalias_ret_a0, double* %noalias_ret_a1 -; CHECK: Both ModRef: Ptr: double* %arg_a0 <-> %normal_ret_a0 = call double* @normal_returner() ; [#uses=1] -; CHECK: Both ModRef: Ptr: double* %arg_a1 <-> %normal_ret_a0 = call double* @normal_returner() ; [#uses=1] -; CHECK: NoModRef: Ptr: double* %noalias_arg_a0 <-> %normal_ret_a0 = call double* @normal_returner() ; [#uses=1] -; CHECK: NoModRef: Ptr: double* %noalias_arg_a1 <-> %normal_ret_a0 = call double* @normal_returner() ; [#uses=1] -; CHECK: Both ModRef: Ptr: double** %indirect_a0 <-> %normal_ret_a0 = call double* @normal_returner() ; [#uses=1] -; CHECK: Both ModRef: Ptr: double** %indirect_a1 <-> %normal_ret_a0 = call double* @normal_returner() ; [#uses=1] -; CHECK: Both ModRef: Ptr: double* %loaded_a0 <-> %normal_ret_a0 = call double* @normal_returner() ; [#uses=1] -; CHECK: Both ModRef: Ptr: double* %loaded_a1 <-> %normal_ret_a0 = call double* @normal_returner() ; [#uses=1] -; CHECK: Both ModRef: Ptr: double* %escape_alloca_a0 <-> %normal_ret_a0 = call double* @normal_returner() ; [#uses=1] -; CHECK: Both ModRef: Ptr: double* %escape_alloca_a1 <-> %normal_ret_a0 = call double* @normal_returner() ; [#uses=1] -; CHECK: NoModRef: Ptr: double* %noescape_alloca_a0 <-> %normal_ret_a0 = call double* @normal_returner() ; [#uses=1] -; CHECK: NoModRef: Ptr: double* %noescape_alloca_a1 <-> %normal_ret_a0 = call double* @normal_returner() ; [#uses=1] -; CHECK: Both ModRef: Ptr: double* %normal_ret_a0 <-> %normal_ret_a0 = call double* @normal_returner() ; [#uses=1] -; CHECK: Both ModRef: Ptr: double* %normal_ret_a1 <-> %normal_ret_a0 = call double* @normal_returner() ; [#uses=1] -; CHECK: NoModRef: Ptr: double* %noalias_ret_a0 <-> %normal_ret_a0 = call double* @normal_returner() ; [#uses=1] -; CHECK: NoModRef: Ptr: double* %noalias_ret_a1 <-> %normal_ret_a0 = call double* @normal_returner() ; [#uses=1] -; CHECK: Both ModRef: Ptr: double* %arg_a0 <-> %normal_ret_a1 = call double* @normal_returner() ; [#uses=1] -; CHECK: Both ModRef: Ptr: double* %arg_a1 <-> %normal_ret_a1 = call double* @normal_returner() ; [#uses=1] -; CHECK: NoModRef: Ptr: double* %noalias_arg_a0 <-> %normal_ret_a1 = call double* @normal_returner() ; [#uses=1] -; CHECK: NoModRef: Ptr: double* %noalias_arg_a1 <-> %normal_ret_a1 = call double* @normal_returner() ; [#uses=1] -; CHECK: Both ModRef: Ptr: double** %indirect_a0 <-> %normal_ret_a1 = call double* @normal_returner() ; [#uses=1] -; CHECK: Both ModRef: Ptr: double** %indirect_a1 <-> %normal_ret_a1 = call double* @normal_returner() ; [#uses=1] -; CHECK: Both ModRef: Ptr: double* %loaded_a0 <-> %normal_ret_a1 = call double* @normal_returner() ; [#uses=1] -; CHECK: Both ModRef: Ptr: double* %loaded_a1 <-> %normal_ret_a1 = call double* @normal_returner() ; [#uses=1] -; CHECK: Both ModRef: Ptr: double* %escape_alloca_a0 <-> %normal_ret_a1 = call double* @normal_returner() ; [#uses=1] -; CHECK: Both ModRef: Ptr: double* %escape_alloca_a1 <-> %normal_ret_a1 = call double* @normal_returner() ; [#uses=1] -; CHECK: NoModRef: Ptr: double* %noescape_alloca_a0 <-> %normal_ret_a1 = call double* @normal_returner() ; [#uses=1] -; CHECK: NoModRef: Ptr: double* %noescape_alloca_a1 <-> %normal_ret_a1 = call double* @normal_returner() ; [#uses=1] -; CHECK: Both ModRef: Ptr: double* %normal_ret_a0 <-> %normal_ret_a1 = call double* @normal_returner() ; [#uses=1] -; CHECK: Both ModRef: Ptr: double* %normal_ret_a1 <-> %normal_ret_a1 = call double* @normal_returner() ; [#uses=1] -; CHECK: NoModRef: Ptr: double* %noalias_ret_a0 <-> %normal_ret_a1 = call double* @normal_returner() ; [#uses=1] -; CHECK: NoModRef: Ptr: double* %noalias_ret_a1 <-> %normal_ret_a1 = call double* @normal_returner() ; [#uses=1] -; CHECK: Both ModRef: Ptr: double* %arg_a0 <-> %noalias_ret_a0 = call double* @noalias_returner() ; [#uses=1] -; CHECK: Both ModRef: Ptr: double* %arg_a1 <-> %noalias_ret_a0 = call double* @noalias_returner() ; [#uses=1] -; CHECK: NoModRef: Ptr: double* %noalias_arg_a0 <-> %noalias_ret_a0 = call double* @noalias_returner() ; [#uses=1] -; CHECK: NoModRef: Ptr: double* %noalias_arg_a1 <-> %noalias_ret_a0 = call double* @noalias_returner() ; [#uses=1] -; CHECK: Both ModRef: Ptr: double** %indirect_a0 <-> %noalias_ret_a0 = call double* @noalias_returner() ; [#uses=1] -; CHECK: Both ModRef: Ptr: double** %indirect_a1 <-> %noalias_ret_a0 = call double* @noalias_returner() ; [#uses=1] -; CHECK: Both ModRef: Ptr: double* %loaded_a0 <-> %noalias_ret_a0 = call double* @noalias_returner() ; [#uses=1] -; CHECK: Both ModRef: Ptr: double* %loaded_a1 <-> %noalias_ret_a0 = call double* @noalias_returner() ; [#uses=1] -; CHECK: Both ModRef: Ptr: double* %escape_alloca_a0 <-> %noalias_ret_a0 = call double* @noalias_returner() ; [#uses=1] -; CHECK: Both ModRef: Ptr: double* %escape_alloca_a1 <-> %noalias_ret_a0 = call double* @noalias_returner() ; [#uses=1] -; CHECK: NoModRef: Ptr: double* %noescape_alloca_a0 <-> %noalias_ret_a0 = call double* @noalias_returner() ; [#uses=1] -; CHECK: NoModRef: Ptr: double* %noescape_alloca_a1 <-> %noalias_ret_a0 = call double* @noalias_returner() ; [#uses=1] -; CHECK: Both ModRef: Ptr: double* %normal_ret_a0 <-> %noalias_ret_a0 = call double* @noalias_returner() ; [#uses=1] -; CHECK: Both ModRef: Ptr: double* %normal_ret_a1 <-> %noalias_ret_a0 = call double* @noalias_returner() ; [#uses=1] -; CHECK: Both ModRef: Ptr: double* %noalias_ret_a0 <-> %noalias_ret_a0 = call double* @noalias_returner() ; [#uses=1] -; CHECK: NoModRef: Ptr: double* %noalias_ret_a1 <-> %noalias_ret_a0 = call double* @noalias_returner() ; [#uses=1] -; CHECK: Both ModRef: Ptr: double* %arg_a0 <-> %noalias_ret_a1 = call double* @noalias_returner() ; [#uses=1] -; CHECK: Both ModRef: Ptr: double* %arg_a1 <-> %noalias_ret_a1 = call double* @noalias_returner() ; [#uses=1] -; CHECK: NoModRef: Ptr: double* %noalias_arg_a0 <-> %noalias_ret_a1 = call double* @noalias_returner() ; [#uses=1] -; CHECK: NoModRef: Ptr: double* %noalias_arg_a1 <-> %noalias_ret_a1 = call double* @noalias_returner() ; [#uses=1] -; CHECK: Both ModRef: Ptr: double** %indirect_a0 <-> %noalias_ret_a1 = call double* @noalias_returner() ; [#uses=1] -; CHECK: Both ModRef: Ptr: double** %indirect_a1 <-> %noalias_ret_a1 = call double* @noalias_returner() ; [#uses=1] -; CHECK: Both ModRef: Ptr: double* %loaded_a0 <-> %noalias_ret_a1 = call double* @noalias_returner() ; [#uses=1] -; CHECK: Both ModRef: Ptr: double* %loaded_a1 <-> %noalias_ret_a1 = call double* @noalias_returner() ; [#uses=1] -; CHECK: Both ModRef: Ptr: double* %escape_alloca_a0 <-> %noalias_ret_a1 = call double* @noalias_returner() ; [#uses=1] -; CHECK: Both ModRef: Ptr: double* %escape_alloca_a1 <-> %noalias_ret_a1 = call double* @noalias_returner() ; [#uses=1] -; CHECK: NoModRef: Ptr: double* %noescape_alloca_a0 <-> %noalias_ret_a1 = call double* @noalias_returner() ; [#uses=1] -; CHECK: NoModRef: Ptr: double* %noescape_alloca_a1 <-> %noalias_ret_a1 = call double* @noalias_returner() ; [#uses=1] -; CHECK: Both ModRef: Ptr: double* %normal_ret_a0 <-> %noalias_ret_a1 = call double* @noalias_returner() ; [#uses=1] -; CHECK: Both ModRef: Ptr: double* %normal_ret_a1 <-> %noalias_ret_a1 = call double* @noalias_returner() ; [#uses=1] -; CHECK: NoModRef: Ptr: double* %noalias_ret_a0 <-> %noalias_ret_a1 = call double* @noalias_returner() ; [#uses=1] -; CHECK: Both ModRef: Ptr: double* %noalias_ret_a1 <-> %noalias_ret_a1 = call double* @noalias_returner() ; [#uses=1] +; CHECK: Both ModRef: Ptr: double* %arg_a0 <-> %normal_ret_a0 = call double* @normal_returner() +; CHECK: Both ModRef: Ptr: double* %arg_a1 <-> %normal_ret_a0 = call double* @normal_returner() +; CHECK: NoModRef: Ptr: double* %noalias_arg_a0 <-> %normal_ret_a0 = call double* @normal_returner() +; CHECK: NoModRef: Ptr: double* %noalias_arg_a1 <-> %normal_ret_a0 = call double* @normal_returner() +; CHECK: Both ModRef: Ptr: double** %indirect_a0 <-> %normal_ret_a0 = call double* @normal_returner() +; CHECK: Both ModRef: Ptr: double** %indirect_a1 <-> %normal_ret_a0 = call double* @normal_returner() +; CHECK: Both ModRef: Ptr: double* %loaded_a0 <-> %normal_ret_a0 = call double* @normal_returner() +; CHECK: Both ModRef: Ptr: double* %loaded_a1 <-> %normal_ret_a0 = call double* @normal_returner() +; CHECK: Both ModRef: Ptr: double* %escape_alloca_a0 <-> %normal_ret_a0 = call double* @normal_returner() +; CHECK: Both ModRef: Ptr: double* %escape_alloca_a1 <-> %normal_ret_a0 = call double* @normal_returner() +; CHECK: NoModRef: Ptr: double* %noescape_alloca_a0 <-> %normal_ret_a0 = call double* @normal_returner() +; CHECK: NoModRef: Ptr: double* %noescape_alloca_a1 <-> %normal_ret_a0 = call double* @normal_returner() +; CHECK: Both ModRef: Ptr: double* %normal_ret_a0 <-> %normal_ret_a0 = call double* @normal_returner() +; CHECK: Both ModRef: Ptr: double* %normal_ret_a1 <-> %normal_ret_a0 = call double* @normal_returner() +; CHECK: NoModRef: Ptr: double* %noalias_ret_a0 <-> %normal_ret_a0 = call double* @normal_returner() +; CHECK: NoModRef: Ptr: double* %noalias_ret_a1 <-> %normal_ret_a0 = call double* @normal_returner() +; CHECK: Both ModRef: Ptr: double* %arg_a0 <-> %normal_ret_a1 = call double* @normal_returner() +; CHECK: Both ModRef: Ptr: double* %arg_a1 <-> %normal_ret_a1 = call double* @normal_returner() +; CHECK: NoModRef: Ptr: double* %noalias_arg_a0 <-> %normal_ret_a1 = call double* @normal_returner() +; CHECK: NoModRef: Ptr: double* %noalias_arg_a1 <-> %normal_ret_a1 = call double* @normal_returner() +; CHECK: Both ModRef: Ptr: double** %indirect_a0 <-> %normal_ret_a1 = call double* @normal_returner() +; CHECK: Both ModRef: Ptr: double** %indirect_a1 <-> %normal_ret_a1 = call double* @normal_returner() +; CHECK: Both ModRef: Ptr: double* %loaded_a0 <-> %normal_ret_a1 = call double* @normal_returner() +; CHECK: Both ModRef: Ptr: double* %loaded_a1 <-> %normal_ret_a1 = call double* @normal_returner() +; CHECK: Both ModRef: Ptr: double* %escape_alloca_a0 <-> %normal_ret_a1 = call double* @normal_returner() +; CHECK: Both ModRef: Ptr: double* %escape_alloca_a1 <-> %normal_ret_a1 = call double* @normal_returner() +; CHECK: NoModRef: Ptr: double* %noescape_alloca_a0 <-> %normal_ret_a1 = call double* @normal_returner() +; CHECK: NoModRef: Ptr: double* %noescape_alloca_a1 <-> %normal_ret_a1 = call double* @normal_returner() +; CHECK: Both ModRef: Ptr: double* %normal_ret_a0 <-> %normal_ret_a1 = call double* @normal_returner() +; CHECK: Both ModRef: Ptr: double* %normal_ret_a1 <-> %normal_ret_a1 = call double* @normal_returner() +; CHECK: NoModRef: Ptr: double* %noalias_ret_a0 <-> %normal_ret_a1 = call double* @normal_returner() +; CHECK: NoModRef: Ptr: double* %noalias_ret_a1 <-> %normal_ret_a1 = call double* @normal_returner() +; CHECK: Both ModRef: Ptr: double* %arg_a0 <-> %noalias_ret_a0 = call double* @noalias_returner() +; CHECK: Both ModRef: Ptr: double* %arg_a1 <-> %noalias_ret_a0 = call double* @noalias_returner() +; CHECK: NoModRef: Ptr: double* %noalias_arg_a0 <-> %noalias_ret_a0 = call double* @noalias_returner() +; CHECK: NoModRef: Ptr: double* %noalias_arg_a1 <-> %noalias_ret_a0 = call double* @noalias_returner() +; CHECK: Both ModRef: Ptr: double** %indirect_a0 <-> %noalias_ret_a0 = call double* @noalias_returner() +; CHECK: Both ModRef: Ptr: double** %indirect_a1 <-> %noalias_ret_a0 = call double* @noalias_returner() +; CHECK: Both ModRef: Ptr: double* %loaded_a0 <-> %noalias_ret_a0 = call double* @noalias_returner() +; CHECK: Both ModRef: Ptr: double* %loaded_a1 <-> %noalias_ret_a0 = call double* @noalias_returner() +; CHECK: Both ModRef: Ptr: double* %escape_alloca_a0 <-> %noalias_ret_a0 = call double* @noalias_returner() +; CHECK: Both ModRef: Ptr: double* %escape_alloca_a1 <-> %noalias_ret_a0 = call double* @noalias_returner() +; CHECK: NoModRef: Ptr: double* %noescape_alloca_a0 <-> %noalias_ret_a0 = call double* @noalias_returner() +; CHECK: NoModRef: Ptr: double* %noescape_alloca_a1 <-> %noalias_ret_a0 = call double* @noalias_returner() +; CHECK: Both ModRef: Ptr: double* %normal_ret_a0 <-> %noalias_ret_a0 = call double* @noalias_returner() +; CHECK: Both ModRef: Ptr: double* %normal_ret_a1 <-> %noalias_ret_a0 = call double* @noalias_returner() +; CHECK: Both ModRef: Ptr: double* %noalias_ret_a0 <-> %noalias_ret_a0 = call double* @noalias_returner() +; CHECK: NoModRef: Ptr: double* %noalias_ret_a1 <-> %noalias_ret_a0 = call double* @noalias_returner() +; CHECK: Both ModRef: Ptr: double* %arg_a0 <-> %noalias_ret_a1 = call double* @noalias_returner() +; CHECK: Both ModRef: Ptr: double* %arg_a1 <-> %noalias_ret_a1 = call double* @noalias_returner() +; CHECK: NoModRef: Ptr: double* %noalias_arg_a0 <-> %noalias_ret_a1 = call double* @noalias_returner() +; CHECK: NoModRef: Ptr: double* %noalias_arg_a1 <-> %noalias_ret_a1 = call double* @noalias_returner() +; CHECK: Both ModRef: Ptr: double** %indirect_a0 <-> %noalias_ret_a1 = call double* @noalias_returner() +; CHECK: Both ModRef: Ptr: double** %indirect_a1 <-> %noalias_ret_a1 = call double* @noalias_returner() +; CHECK: Both ModRef: Ptr: double* %loaded_a0 <-> %noalias_ret_a1 = call double* @noalias_returner() +; CHECK: Both ModRef: Ptr: double* %loaded_a1 <-> %noalias_ret_a1 = call double* @noalias_returner() +; CHECK: Both ModRef: Ptr: double* %escape_alloca_a0 <-> %noalias_ret_a1 = call double* @noalias_returner() +; CHECK: Both ModRef: Ptr: double* %escape_alloca_a1 <-> %noalias_ret_a1 = call double* @noalias_returner() +; CHECK: NoModRef: Ptr: double* %noescape_alloca_a0 <-> %noalias_ret_a1 = call double* @noalias_returner() +; CHECK: NoModRef: Ptr: double* %noescape_alloca_a1 <-> %noalias_ret_a1 = call double* @noalias_returner() +; CHECK: Both ModRef: Ptr: double* %normal_ret_a0 <-> %noalias_ret_a1 = call double* @noalias_returner() +; CHECK: Both ModRef: Ptr: double* %normal_ret_a1 <-> %noalias_ret_a1 = call double* @noalias_returner() +; CHECK: NoModRef: Ptr: double* %noalias_ret_a0 <-> %noalias_ret_a1 = call double* @noalias_returner() +; CHECK: Both ModRef: Ptr: double* %noalias_ret_a1 <-> %noalias_ret_a1 = call double* @noalias_returner() ; CHECK: Both ModRef: Ptr: double* %arg_a0 <-> call void @callee(double* %escape_alloca_a0) ; CHECK: Both ModRef: Ptr: double* %arg_a1 <-> call void @callee(double* %escape_alloca_a0) ; CHECK: NoModRef: Ptr: double* %noalias_arg_a0 <-> call void @callee(double* %escape_alloca_a0) Modified: llvm/trunk/test/Analysis/ScalarEvolution/avoid-smax-1.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/ScalarEvolution/avoid-smax-1.ll?rev=112889&r1=112888&r2=112889&view=diff ============================================================================== --- llvm/trunk/test/Analysis/ScalarEvolution/avoid-smax-1.ll (original) +++ llvm/trunk/test/Analysis/ScalarEvolution/avoid-smax-1.ll Thu Sep 2 17:35:33 2010 @@ -1,6 +1,6 @@ ; RUN: opt < %s -indvars -S > %t ; RUN: grep select %t | count 2 -; RUN: grep {icmp ne i32.\* %w } %t +; RUN: grep {icmp ne i32.\* } %t ; Indvars should be able to insert a canonical induction variable ; for the bb6 loop without using a maximum calculation (icmp, select) Modified: llvm/trunk/test/Assembler/getelementptr.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Assembler/getelementptr.ll?rev=112889&r1=112888&r2=112889&view=diff ============================================================================== --- llvm/trunk/test/Assembler/getelementptr.ll (original) +++ llvm/trunk/test/Assembler/getelementptr.ll Thu Sep 2 17:35:33 2010 @@ -3,9 +3,9 @@ ; Verify that over-indexed getelementptrs are folded. @A = external global [2 x [3 x [5 x [7 x i32]]]] @B = global i32* getelementptr ([2 x [3 x [5 x [7 x i32]]]]* @A, i64 0, i64 0, i64 2, i64 1, i64 7523) -; CHECK: @B = global i32* getelementptr ([2 x [3 x [5 x [7 x i32]]]]* @A, i64 36, i64 0, i64 1, i64 0, i64 5) ; [#uses=0] +; CHECK: @B = global i32* getelementptr ([2 x [3 x [5 x [7 x i32]]]]* @A, i64 36, i64 0, i64 1, i64 0, i64 5) @C = global i32* getelementptr ([2 x [3 x [5 x [7 x i32]]]]* @A, i64 3, i64 2, i64 0, i64 0, i64 7523) -; CHECK: @C = global i32* getelementptr ([2 x [3 x [5 x [7 x i32]]]]* @A, i64 39, i64 1, i64 1, i64 4, i64 5) ; [#uses=0] +; CHECK: @C = global i32* getelementptr ([2 x [3 x [5 x [7 x i32]]]]* @A, i64 39, i64 1, i64 1, i64 4, i64 5) ;; Verify that i16 indices work. @x = external global {i32, i32} Modified: llvm/trunk/test/Transforms/ConstProp/constant-expr.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ConstProp/constant-expr.ll?rev=112889&r1=112888&r2=112889&view=diff ============================================================================== --- llvm/trunk/test/Transforms/ConstProp/constant-expr.ll (original) +++ llvm/trunk/test/Transforms/ConstProp/constant-expr.ll Thu Sep 2 17:35:33 2010 @@ -16,9 +16,9 @@ @E = global i1 udiv (i1 icmp ult (i8* @X, i8* @Y), i1 icmp ult (i8* @X, i8* @Z)) ; CHECK: @E = global i1 icmp ult (i8* @X, i8* @Y) @F = global i1 srem (i1 icmp ult (i8* @X, i8* @Y), i1 icmp ult (i8* @X, i8* @Z)) -; CHECK: @F = global i1 false ; [#uses=0] +; CHECK: @F = global i1 false @G = global i1 urem (i1 icmp ult (i8* @X, i8* @Y), i1 icmp ult (i8* @X, i8* @Z)) -; CHECK: @G = global i1 false ; [#uses=0] +; CHECK: @G = global i1 false @H = global i1 icmp ule (i32* bitcast (i8* @X to i32*), i32* bitcast (i8* @Y to i32*)) ; CHECK: @H = global i1 icmp ule (i8* @X, i8* @Y) From sabre at nondot.org Thu Sep 2 17:38:57 2010 From: sabre at nondot.org (Chris Lattner) Date: Thu, 02 Sep 2010 22:38:57 -0000 Subject: [llvm-commits] [llvm] r112892 - in /llvm/trunk/test/Transforms: GlobalOpt/2008-07-17-addrspace.ll IPConstantProp/2009-09-24-byval-ptr.ll IndVarSimplify/2003-12-10-IndVarDeadCode.ll InstCombine/urem-simplify-bug.ll Message-ID: <20100902223857.266D22A6C12C@llvm.org> Author: lattner Date: Thu Sep 2 17:38:56 2010 New Revision: 112892 URL: http://llvm.org/viewvc/llvm-project?rev=112892&view=rev Log: more test cleanup Removed: llvm/trunk/test/Transforms/IndVarSimplify/2003-12-10-IndVarDeadCode.ll Modified: llvm/trunk/test/Transforms/GlobalOpt/2008-07-17-addrspace.ll llvm/trunk/test/Transforms/IPConstantProp/2009-09-24-byval-ptr.ll llvm/trunk/test/Transforms/InstCombine/urem-simplify-bug.ll Modified: llvm/trunk/test/Transforms/GlobalOpt/2008-07-17-addrspace.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GlobalOpt/2008-07-17-addrspace.ll?rev=112892&r1=112891&r2=112892&view=diff ============================================================================== --- llvm/trunk/test/Transforms/GlobalOpt/2008-07-17-addrspace.ll (original) +++ llvm/trunk/test/Transforms/GlobalOpt/2008-07-17-addrspace.ll Thu Sep 2 17:38:56 2010 @@ -4,7 +4,7 @@ ; RUN: opt < %s -globalopt -S > %t ; Check that the new global values still have their address space -; RUN: cat %t | grep global.*addrspace +; RUN: cat %t | grep addrspace.*global @struct = internal addrspace(1) global { i32, i32 } zeroinitializer @array = internal addrspace(1) global [ 2 x i32 ] zeroinitializer Modified: llvm/trunk/test/Transforms/IPConstantProp/2009-09-24-byval-ptr.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IPConstantProp/2009-09-24-byval-ptr.ll?rev=112892&r1=112891&r2=112892&view=diff ============================================================================== --- llvm/trunk/test/Transforms/IPConstantProp/2009-09-24-byval-ptr.ll (original) +++ llvm/trunk/test/Transforms/IPConstantProp/2009-09-24-byval-ptr.ll Thu Sep 2 17:38:56 2010 @@ -21,10 +21,10 @@ entry: %0 = getelementptr %struct.MYstr* %u, i32 0, i32 1 ; [#uses=1] %1 = load i32* %0 -; CHECK: load i32* getelementptr inbounds (%struct.MYstr* @mystr, i32 0, i32 1) ; [#uses=1] +; CHECK: load i32* getelementptr inbounds (%struct.MYstr* @mystr, i32 0, i32 1) %2 = getelementptr %struct.MYstr* %u, i32 0, i32 0 ; [#uses=1] %3 = load i8* %2 -; CHECK: load i8* getelementptr inbounds (%struct.MYstr* @mystr, i32 0, i32 0) ; [#uses=1] +; CHECK: load i8* getelementptr inbounds (%struct.MYstr* @mystr, i32 0, i32 0) %4 = zext i8 %3 to i32 %5 = add i32 %4, %1 ret i32 %5 Removed: llvm/trunk/test/Transforms/IndVarSimplify/2003-12-10-IndVarDeadCode.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/2003-12-10-IndVarDeadCode.ll?rev=112891&view=auto ============================================================================== --- llvm/trunk/test/Transforms/IndVarSimplify/2003-12-10-IndVarDeadCode.ll (original) +++ llvm/trunk/test/Transforms/IndVarSimplify/2003-12-10-IndVarDeadCode.ll (removed) @@ -1,24 +0,0 @@ -; The induction variable canonicalization pass shouldn't leave dead -; instructions laying around! -; -; RUN: opt < %s -indvars -S | grep {#uses=0} | count 1 - -define i32 @mul(i32 %x, i32 %y) { -entry: - br label %tailrecurse - -tailrecurse: ; preds = %endif, %entry - %accumulator.tr = phi i32 [ %x, %entry ], [ %tmp.9, %endif ] ; [#uses=2] - %y.tr = phi i32 [ %y, %entry ], [ %tmp.8, %endif ] ; [#uses=2] - %tmp.1 = icmp eq i32 %y.tr, 0 ; [#uses=1] - br i1 %tmp.1, label %return, label %endif - -endif: ; preds = %tailrecurse - %tmp.8 = add i32 %y.tr, -1 ; [#uses=1] - %tmp.9 = add i32 %accumulator.tr, %x ; [#uses=1] - br label %tailrecurse - -return: ; preds = %tailrecurse - ret i32 %accumulator.tr -} - Modified: llvm/trunk/test/Transforms/InstCombine/urem-simplify-bug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/urem-simplify-bug.ll?rev=112892&r1=112891&r2=112892&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/urem-simplify-bug.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/urem-simplify-bug.ll Thu Sep 2 17:38:56 2010 @@ -1,4 +1,4 @@ -; RUN: opt < %s -instcombine -S | grep {= or i32 %x, -5 } +; RUN: opt < %s -instcombine -S | grep {= or i32 %x, -5} @.str = internal constant [5 x i8] c"foo\0A\00" ; <[5 x i8]*> [#uses=1] @.str1 = internal constant [5 x i8] c"bar\0A\00" ; <[5 x i8]*> [#uses=1] From grosbach at apple.com Thu Sep 2 17:39:36 2010 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 02 Sep 2010 22:39:36 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r112893 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Message-ID: <20100902223936.E24C02A6C12C@llvm.org> Author: grosbach Date: Thu Sep 2 17:39:36 2010 New Revision: 112893 URL: http://llvm.org/viewvc/llvm-project?rev=112893&view=rev Log: turn off VLA+dynamic realignment diagnostic for ARM since it's now supported there. Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=112893&r1=112892&r2=112893&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Thu Sep 2 17:39:36 2010 @@ -851,6 +851,9 @@ } UniquedValues.clear(); +#if !defined(TARGET_ARM) + // ARM supports VLAs + dynamic realignment. Others don't. + // If we've seen a vla in this function and we'll possibly need to // either dynamically realign or this is greater than the maximum stack // alignment, output a warning. This is here so we don't warn every time @@ -859,6 +862,7 @@ GreatestAlignment > TheTarget->getFrameInfo()->getStackAlignment()) warning (0, "alignment for %q+D conflicts with a dynamically realigned " "stack", SeenVLA); +#endif return Fn; } From sabre at nondot.org Thu Sep 2 17:41:24 2010 From: sabre at nondot.org (Chris Lattner) Date: Thu, 02 Sep 2010 22:41:24 -0000 Subject: [llvm-commits] [llvm] r112894 - /llvm/trunk/lib/VMCore/AsmWriter.cpp Message-ID: <20100902224124.DD7752A6C12C@llvm.org> Author: lattner Date: Thu Sep 2 17:41:24 2010 New Revision: 112894 URL: http://llvm.org/viewvc/llvm-project?rev=112894&view=rev Log: Remove #uses comments from functions: they we're padded out to column 50 and were potentially confusing for externally visible functions. going further, remove the " [#uses=3]" comments entirely. They add a lot of noise, confuse people about what the IR is, and don't add any particular value. When the types are long it makes it really really hard to read IR. If someone is interested in this sort of thing, the right way to do this is to implement an AsmAnnotationWriter that produces the same output, and add a flag to llvm-dis (only) to produce this output. Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=112894&r1=112893&r2=112894&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/AsmWriter.cpp (original) +++ llvm/trunk/lib/VMCore/AsmWriter.cpp Thu Sep 2 17:41:24 2010 @@ -1635,11 +1635,10 @@ if (F->hasGC()) Out << " gc \"" << F->getGC() << '"'; if (F->isDeclaration()) { - Out << " ; [#uses=" << F->getNumUses() << "]\n"; // Output # uses + Out << '\n'; } else { - Out << " { ; [#uses=" << F->getNumUses() << ']'; // Output # uses - - // Output all of its basic blocks... for the function + Out << " {"; + // Output all of the function's basic blocks. for (Function::const_iterator I = F->begin(), E = F->end(); I != E; ++I) printBasicBlock(I); @@ -1688,7 +1687,7 @@ Out.PadToColumn(50); Out << "; Error: Block without parent!"; } else if (BB != &BB->getParent()->getEntryBlock()) { // Not the entry block? - // Output predecessors for the block... + // Output predecessors for the block. Out.PadToColumn(50); Out << ";"; const_pred_iterator PI = pred_begin(BB), PE = pred_end(BB); @@ -1726,13 +1725,6 @@ AnnotationWriter->printInfoComment(V, Out); return; } - - if (V.getType()->isVoidTy()) return; - - Out.PadToColumn(50); - Out << "; <"; - TypePrinter.print(V.getType(), Out); - Out << "> [#uses=" << V.getNumUses() << ']'; // Output # uses } // This member is called for each Instruction in a function.. From anton at korobeynikov.info Thu Sep 2 17:42:39 2010 From: anton at korobeynikov.info (Anton Korobeynikov) Date: Fri, 3 Sep 2010 02:42:39 +0400 Subject: [llvm-commits] Issue with Win64 local area stack offset In-Reply-To: <832540.73670.qm@web55606.mail.re4.yahoo.com> References: <489333.28347.qm@web55604.mail.re4.yahoo.com> <832540.73670.qm@web55606.mail.re4.yahoo.com> Message-ID: Hello, Jan > Any comments about the revised patch? Ok for someone to commit? The patch is invalid. First of all, make sure it does not break "make check". Right now it does and one of the failed tests clearly indicates the problem - the shadow space is allocated in the wrong place and calls might clobber spills of the callee which will be really hard to find in real-world apps. -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From sabre at nondot.org Thu Sep 2 17:42:07 2010 From: sabre at nondot.org (Chris Lattner) Date: Thu, 02 Sep 2010 22:42:07 -0000 Subject: [llvm-commits] [llvm] r112895 - /llvm/trunk/lib/VMCore/AsmWriter.cpp Message-ID: <20100902224207.A5E732A6C12C@llvm.org> Author: lattner Date: Thu Sep 2 17:42:07 2010 New Revision: 112895 URL: http://llvm.org/viewvc/llvm-project?rev=112895&view=rev Log: revert patch, need to update clang tests too Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=112895&r1=112894&r2=112895&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/AsmWriter.cpp (original) +++ llvm/trunk/lib/VMCore/AsmWriter.cpp Thu Sep 2 17:42:07 2010 @@ -1635,10 +1635,11 @@ if (F->hasGC()) Out << " gc \"" << F->getGC() << '"'; if (F->isDeclaration()) { - Out << '\n'; + Out << " ; [#uses=" << F->getNumUses() << "]\n"; // Output # uses } else { - Out << " {"; - // Output all of the function's basic blocks. + Out << " { ; [#uses=" << F->getNumUses() << ']'; // Output # uses + + // Output all of its basic blocks... for the function for (Function::const_iterator I = F->begin(), E = F->end(); I != E; ++I) printBasicBlock(I); @@ -1687,7 +1688,7 @@ Out.PadToColumn(50); Out << "; Error: Block without parent!"; } else if (BB != &BB->getParent()->getEntryBlock()) { // Not the entry block? - // Output predecessors for the block. + // Output predecessors for the block... Out.PadToColumn(50); Out << ";"; const_pred_iterator PI = pred_begin(BB), PE = pred_end(BB); @@ -1725,6 +1726,13 @@ AnnotationWriter->printInfoComment(V, Out); return; } + + if (V.getType()->isVoidTy()) return; + + Out.PadToColumn(50); + Out << "; <"; + TypePrinter.print(V.getType(), Out); + Out << "> [#uses=" << V.getNumUses() << ']'; // Output # uses } // This member is called for each Instruction in a function.. From bruno.cardoso at gmail.com Thu Sep 2 17:43:39 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Thu, 02 Sep 2010 22:43:39 -0000 Subject: [llvm-commits] [llvm] r112896 - in /llvm/trunk/lib/Target/X86: AsmPrinter/X86InstComments.cpp X86ShuffleDecode.h Message-ID: <20100902224339.517B92A6C12C@llvm.org> Author: bruno Date: Thu Sep 2 17:43:39 2010 New Revision: 112896 URL: http://llvm.org/viewvc/llvm-project?rev=112896&view=rev Log: Move insertps mask decoding to header file Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86InstComments.cpp llvm/trunk/lib/Target/X86/X86ShuffleDecode.h Modified: llvm/trunk/lib/Target/X86/AsmPrinter/X86InstComments.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/X86InstComments.cpp?rev=112896&r1=112895&r2=112896&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmPrinter/X86InstComments.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmPrinter/X86InstComments.cpp Thu Sep 2 17:43:39 2010 @@ -20,34 +20,6 @@ using namespace llvm; //===----------------------------------------------------------------------===// -// Vector Mask Decoding for non-shuffles -//===----------------------------------------------------------------------===// - -static void DecodeINSERTPSMask(unsigned Imm, - SmallVectorImpl &ShuffleMask) { - // Defaults the copying the dest value. - ShuffleMask.push_back(0); - ShuffleMask.push_back(1); - ShuffleMask.push_back(2); - ShuffleMask.push_back(3); - - // Decode the immediate. - unsigned ZMask = Imm & 15; - unsigned CountD = (Imm >> 4) & 3; - unsigned CountS = (Imm >> 6) & 3; - - // CountS selects which input element to use. - unsigned InVal = 4+CountS; - // CountD specifies which element of destination to update. - ShuffleMask[CountD] = InVal; - // ZMask zaps values, potentially overriding the CountD elt. - if (ZMask & 1) ShuffleMask[0] = SM_SentinelZero; - if (ZMask & 2) ShuffleMask[1] = SM_SentinelZero; - if (ZMask & 4) ShuffleMask[2] = SM_SentinelZero; - if (ZMask & 8) ShuffleMask[3] = SM_SentinelZero; -} - -//===----------------------------------------------------------------------===// // Top Level Entrypoint //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/X86/X86ShuffleDecode.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ShuffleDecode.h?rev=112896&r1=112895&r2=112896&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ShuffleDecode.h (original) +++ llvm/trunk/lib/Target/X86/X86ShuffleDecode.h Thu Sep 2 17:43:39 2010 @@ -26,6 +26,30 @@ SM_SentinelZero = ~0U }; +static inline +void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl &ShuffleMask) { + // Defaults the copying the dest value. + ShuffleMask.push_back(0); + ShuffleMask.push_back(1); + ShuffleMask.push_back(2); + ShuffleMask.push_back(3); + + // Decode the immediate. + unsigned ZMask = Imm & 15; + unsigned CountD = (Imm >> 4) & 3; + unsigned CountS = (Imm >> 6) & 3; + + // CountS selects which input element to use. + unsigned InVal = 4+CountS; + // CountD specifies which element of destination to update. + ShuffleMask[CountD] = InVal; + // ZMask zaps values, potentially overriding the CountD elt. + if (ZMask & 1) ShuffleMask[0] = SM_SentinelZero; + if (ZMask & 2) ShuffleMask[1] = SM_SentinelZero; + if (ZMask & 4) ShuffleMask[2] = SM_SentinelZero; + if (ZMask & 8) ShuffleMask[3] = SM_SentinelZero; +} + // <3,1> or <6,7,2,3> static void DecodeMOVHLPSMask(unsigned NElts, SmallVectorImpl &ShuffleMask) { From dalej at apple.com Thu Sep 2 17:45:18 2010 From: dalej at apple.com (Dale Johannesen) Date: Thu, 2 Sep 2010 15:45:18 -0700 Subject: [llvm-commits] [llvm] r112881 - /llvm/trunk/include/llvm/IntrinsicsX86.td In-Reply-To: <5A66D3AE-02E5-4E88-8EC6-DCB74A5B8D86@gmail.com> References: <20100902222636.1333F2A6C12C@llvm.org> <5A66D3AE-02E5-4E88-8EC6-DCB74A5B8D86@gmail.com> Message-ID: On Sep 2, 2010, at 3:31 PMPDT, Bill Wendling wrote: > On Sep 2, 2010, at 3:30 PM, Eric Christopher wrote: > >> On Sep 2, 2010, at 3:26 PM, Bill Wendling wrote: >> >>> -// def int_x86_mmx_palignr_b : >>> GCCBuiltin<"__builtin_ia32_palignr">, >>> -// Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, >>> -// llvm_v1i64_ty, llvm_i8_ty], [IntrNoMem]>; >>> +// def int_x86_mmx_palignr_b : >>> GCCBuiltin<"__builtin_ia32_palignr">, >>> +// Intrinsic<[llvm_v8i8_ty], [llvm_8i8_ty, >>> +// llvm_v8i8_ty, llvm_i8_ty], >>> [IntrNoMem]>; >> >> This will, if it's ever re-enabled, likely not match the one coming >> from llvm-gcc. >> > The one from llvm-gcc was changed awhile ago from "long long" to > "v1di". I think the original was correct, but clang doesn't seem to > agree... Eh...I'll change it back. llvm-gcc isn't currently producing an intrinsic for palignr because there isn't one. I believe v8i8 corresponds best to what the instruction does, fwiw, but really in intrinsics "correct" is what we define it to be. No rush on palignr, that needs some work in the BE before I can turn it on. From echristo at apple.com Thu Sep 2 17:46:56 2010 From: echristo at apple.com (Eric Christopher) Date: Thu, 2 Sep 2010 15:46:56 -0700 Subject: [llvm-commits] [llvm] r112881 - /llvm/trunk/include/llvm/IntrinsicsX86.td In-Reply-To: References: <20100902222636.1333F2A6C12C@llvm.org> <5A66D3AE-02E5-4E88-8EC6-DCB74A5B8D86@gmail.com> Message-ID: <0CBFDC72-A7F7-4D49-8EFC-4956511F4E34@apple.com> On Sep 2, 2010, at 3:45 PM, Dale Johannesen wrote: > > On Sep 2, 2010, at 3:31 PMPDT, Bill Wendling wrote: > >> On Sep 2, 2010, at 3:30 PM, Eric Christopher wrote: >> >>> On Sep 2, 2010, at 3:26 PM, Bill Wendling wrote: >>> >>>> -// def int_x86_mmx_palignr_b : GCCBuiltin<"__builtin_ia32_palignr">, >>>> -// Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, >>>> -// llvm_v1i64_ty, llvm_i8_ty], [IntrNoMem]>; >>>> +// def int_x86_mmx_palignr_b : GCCBuiltin<"__builtin_ia32_palignr">, >>>> +// Intrinsic<[llvm_v8i8_ty], [llvm_8i8_ty, >>>> +// llvm_v8i8_ty, llvm_i8_ty], [IntrNoMem]>; >>> >>> This will, if it's ever re-enabled, likely not match the one coming from llvm-gcc. >>> >> The one from llvm-gcc was changed awhile ago from "long long" to "v1di". I think the original was correct, but clang doesn't seem to agree... Eh...I'll change it back. > > llvm-gcc isn't currently producing an intrinsic for palignr because there isn't one. I believe v8i8 corresponds best to what the instruction does, fwiw, but really in intrinsics "correct" is what we define it to be. > > No rush on palignr, that needs some work in the BE before I can turn it on. > It was at one point. I didn't keep up with what happened here over the last day or so, been too busy watching things break. What happened with palignr? -eric From sabre at nondot.org Thu Sep 2 17:52:10 2010 From: sabre at nondot.org (Chris Lattner) Date: Thu, 02 Sep 2010 22:52:10 -0000 Subject: [llvm-commits] [llvm] r112899 - /llvm/trunk/lib/VMCore/AsmWriter.cpp Message-ID: <20100902225210.40BDA2A6C12C@llvm.org> Author: lattner Date: Thu Sep 2 17:52:10 2010 New Revision: 112899 URL: http://llvm.org/viewvc/llvm-project?rev=112899&view=rev Log: reapply 112894: Remove #uses comments from functions: they we're padded out to column 50 and were potentially confusing for externally visible functions. going further, remove the " [#uses=3]" comments entirely. They add a lot of noise, confuse people about what the IR is, and don't add any particular value. When the types are long it makes it really really hard to read IR. If someone is interested in this sort of thing, the right way to do this is to implement an AsmAnnotationWriter that produces the same output, and add a flag to llvm-dis (only) to produce this output. Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=112899&r1=112898&r2=112899&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/AsmWriter.cpp (original) +++ llvm/trunk/lib/VMCore/AsmWriter.cpp Thu Sep 2 17:52:10 2010 @@ -1635,11 +1635,10 @@ if (F->hasGC()) Out << " gc \"" << F->getGC() << '"'; if (F->isDeclaration()) { - Out << " ; [#uses=" << F->getNumUses() << "]\n"; // Output # uses + Out << '\n'; } else { - Out << " { ; [#uses=" << F->getNumUses() << ']'; // Output # uses - - // Output all of its basic blocks... for the function + Out << " {"; + // Output all of the function's basic blocks. for (Function::const_iterator I = F->begin(), E = F->end(); I != E; ++I) printBasicBlock(I); @@ -1688,7 +1687,7 @@ Out.PadToColumn(50); Out << "; Error: Block without parent!"; } else if (BB != &BB->getParent()->getEntryBlock()) { // Not the entry block? - // Output predecessors for the block... + // Output predecessors for the block. Out.PadToColumn(50); Out << ";"; const_pred_iterator PI = pred_begin(BB), PE = pred_end(BB); @@ -1726,13 +1725,6 @@ AnnotationWriter->printInfoComment(V, Out); return; } - - if (V.getType()->isVoidTy()) return; - - Out.PadToColumn(50); - Out << "; <"; - TypePrinter.print(V.getType(), Out); - Out << "> [#uses=" << V.getNumUses() << ']'; // Output # uses } // This member is called for each Instruction in a function.. From dpatel at apple.com Thu Sep 2 18:01:10 2010 From: dpatel at apple.com (Devang Patel) Date: Thu, 02 Sep 2010 23:01:10 -0000 Subject: [llvm-commits] [llvm] r112900 - /llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Message-ID: <20100902230110.2E5F02A6C12C@llvm.org> Author: dpatel Date: Thu Sep 2 18:01:10 2010 New Revision: 112900 URL: http://llvm.org/viewvc/llvm-project?rev=112900&view=rev Log: There is no need to use .set here. Thanks Chris! Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=112900&r1=112899&r2=112900&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Thu Sep 2 18:01:10 2010 @@ -1232,14 +1232,7 @@ MCConstantExpr::Create(Offset, OutContext), OutContext); - if (!MAI->hasSetDirective()) - OutStreamer.EmitValue(Plus, 4, 0/*AddrSpace*/); - else { - // Otherwise, emit with .set (aka assignment). - MCSymbol *SetLabel = GetTempSymbol("set", SetCounter++); - OutStreamer.EmitAssignment(SetLabel, Plus); - OutStreamer.EmitSymbolValue(SetLabel, 4, 0/*AddrSpace*/); - } + OutStreamer.EmitValue(Plus, 4, 0/*AddrSpace*/); } From sabre at nondot.org Thu Sep 2 18:03:10 2010 From: sabre at nondot.org (Chris Lattner) Date: Thu, 02 Sep 2010 23:03:10 -0000 Subject: [llvm-commits] [llvm] r112901 - /llvm/trunk/lib/Analysis/IVUsers.cpp Message-ID: <20100902230310.8EDAE2A6C12C@llvm.org> Author: lattner Date: Thu Sep 2 18:03:10 2010 New Revision: 112901 URL: http://llvm.org/viewvc/llvm-project?rev=112901&view=rev Log: stop forcing a noop AssemblyAnnotationWriter to silence #uses comments, these don't happen anymore. Modified: llvm/trunk/lib/Analysis/IVUsers.cpp Modified: llvm/trunk/lib/Analysis/IVUsers.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/IVUsers.cpp?rev=112901&r1=112900&r2=112901&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/IVUsers.cpp (original) +++ llvm/trunk/lib/Analysis/IVUsers.cpp Thu Sep 2 18:03:10 2010 @@ -21,7 +21,6 @@ #include "llvm/Analysis/Dominators.h" #include "llvm/Analysis/LoopPass.h" #include "llvm/Analysis/ScalarEvolutionExpressions.h" -#include "llvm/Assembly/AsmAnnotationWriter.h" #include "llvm/ADT/STLExtras.h" #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" @@ -179,9 +178,6 @@ } OS << ":\n"; - // Use a default AssemblyAnnotationWriter to suppress the default info - // comments, which aren't relevant here. - AssemblyAnnotationWriter Annotator; for (ilist::const_iterator UI = IVUses.begin(), E = IVUses.end(); UI != E; ++UI) { OS << " "; @@ -195,7 +191,7 @@ OS << ")"; } OS << " in "; - UI->getUser()->print(OS, &Annotator); + UI->getUser()->print(OS); OS << '\n'; } } From asl at math.spbu.ru Thu Sep 2 18:03:46 2010 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Thu, 02 Sep 2010 23:03:46 -0000 Subject: [llvm-commits] [llvm] r112902 - in /llvm/trunk: lib/Target/X86/X86RegisterInfo.cpp lib/Target/X86/X86Subtarget.h test/CodeGen/X86/win_chkstk.ll Message-ID: <20100902230346.342902A6C12C@llvm.org> Author: asl Date: Thu Sep 2 18:03:46 2010 New Revision: 112902 URL: http://llvm.org/viewvc/llvm-project?rev=112902&view=rev Log: Properly emit __chkstk call instead of __alloca on non-mingw windows targets. Patch by Cameron Esfahani! Added: llvm/trunk/test/CodeGen/X86/win_chkstk.ll Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp llvm/trunk/lib/Target/X86/X86Subtarget.h Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=112902&r1=112901&r2=112902&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Thu Sep 2 18:03:46 2010 @@ -764,7 +764,7 @@ } } -/// mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator. +/// mergeSPUpdatesDown - Merge two stack-manipulating instructions lower iterator. static void mergeSPUpdatesDown(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, @@ -1087,7 +1087,17 @@ DL = MBB.findDebugLoc(MBBI); // Adjust stack pointer: ESP -= numbytes. - if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) { + + // Windows and cygwin/mingw require a prologue helper routine when allocating + // more than 4K bytes on the stack. Windows uses __chkstk and cygwin/mingw + // uses __alloca. __alloca and the 32-bit version of __chkstk will probe + // the stack and adjust the stack pointer in one go. The 64-bit version + // of __chkstk is only responsible for probing the stack. The 64-bit + // prologue is responsible for adjusting the stack pointer. Touching the + // stack at 4K increments is necessary to ensure that the guard pages used + // by the OS virtual memory manager are allocated in correct sequence. + if (NumBytes >= 4096 && + (Subtarget->isTargetCygMing() || Subtarget->isTargetWin32())) { // Check, whether EAX is livein for this function. bool isEAXAlive = false; for (MachineRegisterInfo::livein_iterator @@ -1098,15 +1108,14 @@ Reg == X86::AH || Reg == X86::AL); } - // Function prologue calls _alloca to probe the stack when allocating more - // than 4k bytes in one go. Touching the stack at 4K increments is necessary - // to ensure that the guard pages used by the OS virtual memory manager are - // allocated in correct sequence. + + const char *StackProbeSymbol = + Subtarget->isTargetWindows() ? "_chkstk" : "_alloca"; if (!isEAXAlive) { BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX) .addImm(NumBytes); BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32)) - .addExternalSymbol("_alloca") + .addExternalSymbol(StackProbeSymbol) .addReg(StackPtr, RegState::Define | RegState::Implicit) .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); } else { @@ -1119,7 +1128,7 @@ BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX) .addImm(NumBytes - 4); BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32)) - .addExternalSymbol("_alloca") + .addExternalSymbol(StackProbeSymbol) .addReg(StackPtr, RegState::Define | RegState::Implicit) .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=112902&r1=112901&r2=112902&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Subtarget.h (original) +++ llvm/trunk/lib/Target/X86/X86Subtarget.h Thu Sep 2 18:03:46 2010 @@ -186,6 +186,10 @@ return Is64Bit && (isTargetMingw() || isTargetWindows()); } + bool isTargetWin32() const { + return !Is64Bit && (isTargetMingw() || isTargetWindows()); + } + std::string getDataLayout() const { const char *p; if (is64Bit()) Added: llvm/trunk/test/CodeGen/X86/win_chkstk.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/win_chkstk.ll?rev=112902&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/win_chkstk.ll (added) +++ llvm/trunk/test/CodeGen/X86/win_chkstk.ll Thu Sep 2 18:03:46 2010 @@ -0,0 +1,45 @@ +; RUN: llc < %s -mtriple=i686-pc-win32 | FileCheck %s -check-prefix=WIN_X32 +; RUN: llc < %s -mtriple=i686-pc-mingw32 | FileCheck %s -check-prefix=MINGW_X32 +; RUN: llc < %s -mtriple=x86_64-pc-mingw32 | FileCheck %s -check-prefix=MINGW_X64 +; RUN: llc < %s -mtriple=i386-pc-linux | FileCheck %s -check-prefix=LINUX + +; Windows and mingw require a prologue helper routine if more than 4096 bytes area +; allocated on the stack. Windows uses __chkstk and mingw uses __alloca. __alloca +; and the 32-bit version of __chkstk will probe the stack and adjust the stack pointer. +; The 64-bit version of __chkstk is only responsible for probing the stack. The 64-bit +; prologue is responsible for adjusting the stack pointer. + +; Stack allocation >= 4096 bytes will require call to __chkstk in the Windows ABI. +define i32 @main4k() nounwind { +entry: +; WIN_X32: call __chkstk +; WIN_X64: call __chkstk +; MINGW_X32: call __alloca +; MINGW_X64: call _alloca +; LINUX-NOT: call __chkstk + %array4096 = alloca [4096 x i8], align 16 ; <[4096 x i8]*> [#uses=0] + ret i32 0 +} + +; Make sure we don't call __chkstk or __alloca when we have less than a 4096 stack +; allocation. +define i32 @main128() nounwind { +entry: +; WIN_X32: # BB#0: +; WIN_X32-NOT: call __chkstk +; WIN_X32: ret + +; WIN_X64: # BB#0: +; WIN_X64-NOT: call __chkstk +; WIN_X64: ret + +; MINGW_X64: # BB#0: +; MINGW_X64-NOT: call _alloca +; MINGW_X64: ret + +; LINUX: # BB#0: +; LINUX-NOT: call __chkstk +; LINUX: ret + %array128 = alloca [128 x i8], align 16 ; <[128 x i8]*> [#uses=0] + ret i32 0 +} From sabre at nondot.org Thu Sep 2 18:07:12 2010 From: sabre at nondot.org (Chris Lattner) Date: Thu, 02 Sep 2010 23:07:12 -0000 Subject: [llvm-commits] [llvm] r112903 - in /llvm/trunk: include/llvm/Assembly/AsmAnnotationWriter.h tools/llvm-prof/llvm-prof.cpp Message-ID: <20100902230712.458C82A6C12C@llvm.org> Author: lattner Date: Thu Sep 2 18:07:12 2010 New Revision: 112903 URL: http://llvm.org/viewvc/llvm-project?rev=112903&view=rev Log: AsmPrinter has a formatted stream, pass it down through AsmAnnotationWriter Modified: llvm/trunk/include/llvm/Assembly/AsmAnnotationWriter.h llvm/trunk/tools/llvm-prof/llvm-prof.cpp Modified: llvm/trunk/include/llvm/Assembly/AsmAnnotationWriter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Assembly/AsmAnnotationWriter.h?rev=112903&r1=112902&r2=112903&view=diff ============================================================================== --- llvm/trunk/include/llvm/Assembly/AsmAnnotationWriter.h (original) +++ llvm/trunk/include/llvm/Assembly/AsmAnnotationWriter.h Thu Sep 2 18:07:12 2010 @@ -32,21 +32,26 @@ /// emitFunctionAnnot - This may be implemented to emit a string right before /// the start of a function. - virtual void emitFunctionAnnot(const Function *F, raw_ostream &OS) {} + virtual void emitFunctionAnnot(const Function *F, + formatted_raw_ostream &OS) {} /// emitBasicBlockStartAnnot - This may be implemented to emit a string right - /// after the basic block label, but before the first instruction in the block. - virtual void emitBasicBlockStartAnnot(const BasicBlock *BB, raw_ostream &OS){ + /// after the basic block label, but before the first instruction in the + /// block. + virtual void emitBasicBlockStartAnnot(const BasicBlock *BB, + formatted_raw_ostream &OS){ } /// emitBasicBlockEndAnnot - This may be implemented to emit a string right /// after the basic block. - virtual void emitBasicBlockEndAnnot(const BasicBlock *BB, raw_ostream &OS){ + virtual void emitBasicBlockEndAnnot(const BasicBlock *BB, + formatted_raw_ostream &OS){ } /// emitInstructionAnnot - This may be implemented to emit a string right /// before an instruction is emitted. - virtual void emitInstructionAnnot(const Instruction *I, raw_ostream &OS) {} + virtual void emitInstructionAnnot(const Instruction *I, + formatted_raw_ostream &OS) {} /// printInfoComment - This may be implemented to emit a comment to the /// right of an instruction or global value. Modified: llvm/trunk/tools/llvm-prof/llvm-prof.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-prof/llvm-prof.cpp?rev=112903&r1=112902&r2=112903&view=diff ============================================================================== --- llvm/trunk/tools/llvm-prof/llvm-prof.cpp (original) +++ llvm/trunk/tools/llvm-prof/llvm-prof.cpp Thu Sep 2 18:07:12 2010 @@ -23,6 +23,7 @@ #include "llvm/Analysis/Passes.h" #include "llvm/Bitcode/ReaderWriter.h" #include "llvm/Support/CommandLine.h" +#include "llvm/Support/FormattedStream.h" #include "llvm/Support/ManagedStatic.h" #include "llvm/Support/MemoryBuffer.h" #include "llvm/Support/PrettyStackTrace.h" @@ -75,9 +76,10 @@ class ProfileAnnotator : public AssemblyAnnotationWriter { ProfileInfo &PI; public: - ProfileAnnotator(ProfileInfo& pi) : PI(pi) {} + ProfileAnnotator(ProfileInfo &pi) : PI(pi) {} - virtual void emitFunctionAnnot(const Function *F, raw_ostream &OS) { + virtual void emitFunctionAnnot(const Function *F, + formatted_raw_ostream &OS) { double w = PI.getExecutionCount(F); if (w != ProfileInfo::MissingValue) { OS << ";;; %" << F->getName() << " called "<<(unsigned)w @@ -85,7 +87,7 @@ } } virtual void emitBasicBlockStartAnnot(const BasicBlock *BB, - raw_ostream &OS) { + formatted_raw_ostream &OS) { double w = PI.getExecutionCount(BB); if (w != ProfileInfo::MissingValue) { if (w != 0) { @@ -96,7 +98,8 @@ } } - virtual void emitBasicBlockEndAnnot(const BasicBlock *BB, raw_ostream &OS) { + virtual void emitBasicBlockEndAnnot(const BasicBlock *BB, + formatted_raw_ostream &OS) { // Figure out how many times each successor executed. std::vector > SuccCounts; From sabre at nondot.org Thu Sep 2 18:09:43 2010 From: sabre at nondot.org (Chris Lattner) Date: Thu, 02 Sep 2010 23:09:43 -0000 Subject: [llvm-commits] [llvm] r112904 - in /llvm/trunk: include/llvm/Assembly/AsmAnnotationWriter.h include/llvm/Assembly/AssemblyAnnotationWriter.h lib/VMCore/AsmWriter.cpp tools/llvm-prof/llvm-prof.cpp Message-ID: <20100902230943.124E92A6C12C@llvm.org> Author: lattner Date: Thu Sep 2 18:09:42 2010 New Revision: 112904 URL: http://llvm.org/viewvc/llvm-project?rev=112904&view=rev Log: lets get crazy and name the header file the exact class name, not a scrunched version of it. Added: llvm/trunk/include/llvm/Assembly/AssemblyAnnotationWriter.h - copied, changed from r112903, llvm/trunk/include/llvm/Assembly/AsmAnnotationWriter.h Removed: llvm/trunk/include/llvm/Assembly/AsmAnnotationWriter.h Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp llvm/trunk/tools/llvm-prof/llvm-prof.cpp Removed: llvm/trunk/include/llvm/Assembly/AsmAnnotationWriter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Assembly/AsmAnnotationWriter.h?rev=112903&view=auto ============================================================================== --- llvm/trunk/include/llvm/Assembly/AsmAnnotationWriter.h (original) +++ llvm/trunk/include/llvm/Assembly/AsmAnnotationWriter.h (removed) @@ -1,63 +0,0 @@ -//===-- AsmAnnotationWriter.h - Itf for annotation .ll files - --*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// Clients of the assembly writer can use this interface to add their own -// special-purpose annotations to LLVM assembly language printouts. Note that -// the assembly parser won't be able to parse these, in general, so -// implementations are advised to print stuff as LLVM comments. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_ASSEMBLY_ASMANNOTATIONWRITER_H -#define LLVM_ASSEMBLY_ASMANNOTATIONWRITER_H - -namespace llvm { - -class Function; -class BasicBlock; -class Instruction; -class raw_ostream; -class formatted_raw_ostream; - -class AssemblyAnnotationWriter { -public: - - virtual ~AssemblyAnnotationWriter(); - - /// emitFunctionAnnot - This may be implemented to emit a string right before - /// the start of a function. - virtual void emitFunctionAnnot(const Function *F, - formatted_raw_ostream &OS) {} - - /// emitBasicBlockStartAnnot - This may be implemented to emit a string right - /// after the basic block label, but before the first instruction in the - /// block. - virtual void emitBasicBlockStartAnnot(const BasicBlock *BB, - formatted_raw_ostream &OS){ - } - - /// emitBasicBlockEndAnnot - This may be implemented to emit a string right - /// after the basic block. - virtual void emitBasicBlockEndAnnot(const BasicBlock *BB, - formatted_raw_ostream &OS){ - } - - /// emitInstructionAnnot - This may be implemented to emit a string right - /// before an instruction is emitted. - virtual void emitInstructionAnnot(const Instruction *I, - formatted_raw_ostream &OS) {} - - /// printInfoComment - This may be implemented to emit a comment to the - /// right of an instruction or global value. - virtual void printInfoComment(const Value &V, formatted_raw_ostream &OS) {} -}; - -} // End llvm namespace - -#endif Copied: llvm/trunk/include/llvm/Assembly/AssemblyAnnotationWriter.h (from r112903, llvm/trunk/include/llvm/Assembly/AsmAnnotationWriter.h) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Assembly/AssemblyAnnotationWriter.h?p2=llvm/trunk/include/llvm/Assembly/AssemblyAnnotationWriter.h&p1=llvm/trunk/include/llvm/Assembly/AsmAnnotationWriter.h&r1=112903&r2=112904&rev=112904&view=diff ============================================================================== --- llvm/trunk/include/llvm/Assembly/AsmAnnotationWriter.h (original) +++ llvm/trunk/include/llvm/Assembly/AssemblyAnnotationWriter.h Thu Sep 2 18:09:42 2010 @@ -1,4 +1,4 @@ -//===-- AsmAnnotationWriter.h - Itf for annotation .ll files - --*- C++ -*-===// +//===-- AssemblyAnnotationWriter.h - Annotation .ll files -------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -39,13 +39,13 @@ /// after the basic block label, but before the first instruction in the /// block. virtual void emitBasicBlockStartAnnot(const BasicBlock *BB, - formatted_raw_ostream &OS){ + formatted_raw_ostream &OS) { } /// emitBasicBlockEndAnnot - This may be implemented to emit a string right /// after the basic block. virtual void emitBasicBlockEndAnnot(const BasicBlock *BB, - formatted_raw_ostream &OS){ + formatted_raw_ostream &OS) { } /// emitInstructionAnnot - This may be implemented to emit a string right Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=112904&r1=112903&r2=112904&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/AsmWriter.cpp (original) +++ llvm/trunk/lib/VMCore/AsmWriter.cpp Thu Sep 2 18:09:42 2010 @@ -16,7 +16,7 @@ #include "llvm/Assembly/Writer.h" #include "llvm/Assembly/PrintModulePass.h" -#include "llvm/Assembly/AsmAnnotationWriter.h" +#include "llvm/Assembly/AssemblyAnnotationWriter.h" #include "llvm/LLVMContext.h" #include "llvm/CallingConv.h" #include "llvm/Constants.h" Modified: llvm/trunk/tools/llvm-prof/llvm-prof.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-prof/llvm-prof.cpp?rev=112904&r1=112903&r2=112904&view=diff ============================================================================== --- llvm/trunk/tools/llvm-prof/llvm-prof.cpp (original) +++ llvm/trunk/tools/llvm-prof/llvm-prof.cpp Thu Sep 2 18:09:42 2010 @@ -17,7 +17,7 @@ #include "llvm/LLVMContext.h" #include "llvm/Module.h" #include "llvm/PassManager.h" -#include "llvm/Assembly/AsmAnnotationWriter.h" +#include "llvm/Assembly/AssemblyAnnotationWriter.h" #include "llvm/Analysis/ProfileInfo.h" #include "llvm/Analysis/ProfileInfoLoader.h" #include "llvm/Analysis/Passes.h" From asl at math.spbu.ru Thu Sep 2 18:13:49 2010 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Fri, 3 Sep 2010 03:13:49 +0400 Subject: [llvm-commits] [PATCH] Win64 var arg support In-Reply-To: References: Message-ID: Hello, Cameron > Here's the corresponding llvm changes to support the Win64 ABI version of var args. ?With a test case! This hunk seems to be unrelated to the patch and in wrong in general: - (Subtarget.isTargetWin64() ? -40 : - (Subtarget.is64Bit() ? -8 : -4))), + (Subtarget.is64Bit() ? -8 : -4)), Why do you need it? -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From sabre at nondot.org Thu Sep 2 18:21:44 2010 From: sabre at nondot.org (Chris Lattner) Date: Thu, 02 Sep 2010 23:21:44 -0000 Subject: [llvm-commits] [llvm] r112906 - in /llvm/trunk: test/Assembler/comment.ll tools/llvm-dis/llvm-dis.cpp Message-ID: <20100902232144.74D222A6C12C@llvm.org> Author: lattner Date: Thu Sep 2 18:21:44 2010 New Revision: 112906 URL: http://llvm.org/viewvc/llvm-project?rev=112906&view=rev Log: add a new "llvm-dis -show-annotations" option, which causes it to print #uses comments, with a testcase. Added: llvm/trunk/test/Assembler/comment.ll Modified: llvm/trunk/tools/llvm-dis/llvm-dis.cpp Added: llvm/trunk/test/Assembler/comment.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Assembler/comment.ll?rev=112906&view=auto ============================================================================== --- llvm/trunk/test/Assembler/comment.ll (added) +++ llvm/trunk/test/Assembler/comment.ll Thu Sep 2 18:21:44 2010 @@ -0,0 +1,20 @@ +; RUN: llvm-as < %s | llvm-dis -show-annotations | FileCheck -check-prefix=ANNOT %s +; RUN: llvm-as < %s | llvm-dis | FileCheck -check-prefix=BARE %s + +; The bare version of this file should not have any #uses lines. +; BARE: @B = +; BARE-NOT: #uses +; BARE: } + + at B = external global i32 +; ANNOT: @B = external global i32 ; [#uses=0] + +define <4 x i1> @foo(<4 x float> %a, <4 x float> %b) nounwind { +entry: + %cmp = fcmp olt <4 x float> %a, %b ; [#uses=1] + ret <4 x i1> %cmp +} + +; ANNOT: %cmp = fcmp olt <4 x float> %a, %b ; [#uses=1] + + Modified: llvm/trunk/tools/llvm-dis/llvm-dis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-dis/llvm-dis.cpp?rev=112906&r1=112905&r2=112906&view=diff ============================================================================== --- llvm/trunk/tools/llvm-dis/llvm-dis.cpp (original) +++ llvm/trunk/tools/llvm-dis/llvm-dis.cpp Thu Sep 2 18:21:44 2010 @@ -18,8 +18,11 @@ #include "llvm/LLVMContext.h" #include "llvm/Module.h" +#include "llvm/Type.h" #include "llvm/Bitcode/ReaderWriter.h" +#include "llvm/Assembly/AssemblyAnnotationWriter.h" #include "llvm/Support/CommandLine.h" +#include "llvm/Support/FormattedStream.h" #include "llvm/Support/ManagedStatic.h" #include "llvm/Support/MemoryBuffer.h" #include "llvm/Support/PrettyStackTrace.h" @@ -40,6 +43,29 @@ static cl::opt DontPrint("disable-output", cl::desc("Don't output the .ll file"), cl::Hidden); +static cl::opt +ShowAnnotations("show-annotations", + cl::desc("Add informational comments to the .ll file")); + +namespace { + +class CommentWriter : public AssemblyAnnotationWriter { +public: + void emitFunctionAnnot(const Function *F, + formatted_raw_ostream &OS) { + OS << "; [#uses=" << F->getNumUses() << ']'; // Output # uses + OS << '\n'; + } + void printInfoComment(const Value &V, formatted_raw_ostream &OS) { + if (V.getType()->isVoidTy()) return; + + OS.PadToColumn(50); + OS << "; [#uses=" << V.getNumUses() << ']'; // Output # uses + } +}; + +} // end anon namespace + int main(int argc, char **argv) { // Print a stack trace if we signal out. sys::PrintStackTraceOnErrorSignal(); @@ -96,9 +122,13 @@ return 1; } + OwningPtr Annotator; + if (ShowAnnotations) + Annotator.reset(new CommentWriter()); + // All that llvm-dis does is write the assembly to a file. if (!DontPrint) - Out->os() << *M; + M->print(Out->os(), Annotator.get()); // Declare success. Out->keep(); From sabre at nondot.org Thu Sep 2 18:22:50 2010 From: sabre at nondot.org (Chris Lattner) Date: Thu, 02 Sep 2010 23:22:50 -0000 Subject: [llvm-commits] [llvm] r112907 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <20100902232250.B574E2A6C12C@llvm.org> Author: lattner Date: Thu Sep 2 18:22:50 2010 New Revision: 112907 URL: http://llvm.org/viewvc/llvm-project?rev=112907&view=rev Log: this is a release note worthy change. Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=112907&r1=112906&r2=112907&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Thu Sep 2 18:22:50 2010 @@ -494,6 +494,8 @@ from the previous release.

        +
      • .ll file doesn't produce #uses comments anymore, to get them, run a .bc file + through "llvm-dis --show-annotations".
      • MSIL Backend removed.
      • ABCD and SSI passes removed.
      • 'Union' LLVM IR feature removed.
        • From sabre at nondot.org Thu Sep 2 18:32:56 2010 From: sabre at nondot.org (Chris Lattner) Date: Thu, 02 Sep 2010 23:32:56 -0000 Subject: [llvm-commits] [llvm] r112910 - /llvm/trunk/test/FrontendC/2010-07-14-ref-off-end.c Message-ID: <20100902233256.20E6C2A6C12C@llvm.org> Author: lattner Date: Thu Sep 2 18:32:55 2010 New Revision: 112910 URL: http://llvm.org/viewvc/llvm-project?rev=112910&view=rev Log: update one more test Modified: llvm/trunk/test/FrontendC/2010-07-14-ref-off-end.c Modified: llvm/trunk/test/FrontendC/2010-07-14-ref-off-end.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/2010-07-14-ref-off-end.c?rev=112910&r1=112909&r2=112910&view=diff ============================================================================== --- llvm/trunk/test/FrontendC/2010-07-14-ref-off-end.c (original) +++ llvm/trunk/test/FrontendC/2010-07-14-ref-off-end.c Thu Sep 2 18:32:55 2010 @@ -17,8 +17,8 @@ } main() { -// CHECK: getelementptr inbounds %struct.T* %t, i32 0, i32 0 ; [#uses=2] -// CHECK: getelementptr inbounds %struct.T* %t, i32 0, i32 0 ; [#uses=2] +// CHECK: getelementptr inbounds %struct.T* %t, i32 0, i32 0 +// CHECK: getelementptr inbounds %struct.T* %t, i32 0, i32 0 struct T t; t.i=0xff; t.c=0xffff11; From daniel at zuster.org Thu Sep 2 18:35:04 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 02 Sep 2010 23:35:04 -0000 Subject: [llvm-commits] [test-suite] r112911 - in /test-suite/trunk/SingleSource/UnitTests/ObjC: bitfield-access.m bitfield-access.reference_output Message-ID: <20100902233504.CC35F2A6C12C@llvm.org> Author: ddunbar Date: Thu Sep 2 18:35:04 2010 New Revision: 112911 URL: http://llvm.org/viewvc/llvm-project?rev=112911&view=rev Log: Add a test case that Objective-C bitfield access doesn't reach past end of structure. Added: test-suite/trunk/SingleSource/UnitTests/ObjC/bitfield-access.m test-suite/trunk/SingleSource/UnitTests/ObjC/bitfield-access.reference_output Added: test-suite/trunk/SingleSource/UnitTests/ObjC/bitfield-access.m URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/ObjC/bitfield-access.m?rev=112911&view=auto ============================================================================== --- test-suite/trunk/SingleSource/UnitTests/ObjC/bitfield-access.m (added) +++ test-suite/trunk/SingleSource/UnitTests/ObjC/bitfield-access.m Thu Sep 2 18:35:04 2010 @@ -0,0 +1,27 @@ +#include +#include +#include + + at interface I0 { + at public + unsigned a:15; + unsigned b: 9; +} + at end + + at implementation I0 + at end + +void f0(I0 *s) { + s->b = 1; +} + +int main() { + char *p = valloc(4096*2); + mprotect(p+4096, 4096, 0); + I0 *s = (I0 *)(p+4096-4); + + f0(s); + + return 0; +} Added: test-suite/trunk/SingleSource/UnitTests/ObjC/bitfield-access.reference_output URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/ObjC/bitfield-access.reference_output?rev=112911&view=auto ============================================================================== --- test-suite/trunk/SingleSource/UnitTests/ObjC/bitfield-access.reference_output (added) +++ test-suite/trunk/SingleSource/UnitTests/ObjC/bitfield-access.reference_output Thu Sep 2 18:35:04 2010 @@ -0,0 +1 @@ +exit 0 From echristo at apple.com Thu Sep 2 18:43:26 2010 From: echristo at apple.com (Eric Christopher) Date: Thu, 02 Sep 2010 23:43:26 -0000 Subject: [llvm-commits] [llvm] r112912 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20100902234326.468FC2A6C12C@llvm.org> Author: echristo Date: Thu Sep 2 18:43:26 2010 New Revision: 112912 URL: http://llvm.org/viewvc/llvm-project?rev=112912&view=rev Log: Add basic support for materializing constants (including fp) and stores. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=112912&r1=112911&r2=112912&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Thu Sep 2 18:43:26 2010 @@ -323,9 +323,37 @@ } unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) { - // TODO: Implement this for floating point constants and integer constants - // if we care about non-v6 architectures. - return 0; + EVT VT = TLI.getValueType(C->getType(), true); + + // Only handle simple types. + if (!VT.isSimple()) return 0; + + // TODO: This should be safe for fp because they're just bits from the + // Constant. + // TODO: Theoretically we could materialize fp constants with instructions + // from VFP3. + + // MachineConstantPool wants an explicit alignment. + unsigned Align = TD.getPrefTypeAlignment(C->getType()); + if (Align == 0) { + // TODO: Figure out if this is correct. + Align = TD.getTypeAllocSize(C->getType()); + } + unsigned Idx = MCP.getConstantPoolIndex(C, Align); + + unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); + // Different addressing modes between ARM/Thumb2 for constant pool loads. + if (isThumb) + AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, + TII.get(ARM::t2LDRpci)) + .addReg(DestReg).addConstantPoolIndex(Idx)); + else + AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, + TII.get(ARM::LDRcp)) + .addReg(DestReg).addConstantPoolIndex(Idx) + .addReg(0).addImm(0)); + + return DestReg; } bool ARMFastISel::isTypeLegal(const Type *Ty, EVT &VT) { @@ -510,6 +538,14 @@ case MVT::i8: StrOpc = isThumb ? ARM::tSTRB : ARM::STRB; break; case MVT::i16: StrOpc = isThumb ? ARM::tSTRH : ARM::STRH; break; case MVT::i32: StrOpc = isThumb ? ARM::tSTR : ARM::STR; break; + case MVT::f32: + if (!Subtarget->hasVFP2()) return false; + StrOpc = ARM::VSTRS; + break; + case MVT::f64: + if (!Subtarget->hasVFP2()) return false; + StrOpc = ARM::VSTRD; + break; } if (isThumb) @@ -583,6 +619,7 @@ return true; } +// TODO: SoftFP support. bool ARMFastISel::TargetSelectInstruction(const Instruction *I) { // No Thumb-1 for now. if (isThumb && !AFI->isThumb2Function()) return false; From stoklund at 2pi.dk Thu Sep 2 19:35:13 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Fri, 03 Sep 2010 00:35:13 -0000 Subject: [llvm-commits] [llvm] r112919 - /llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Message-ID: <20100903003513.65AAE2A6C12C@llvm.org> Author: stoklund Date: Thu Sep 2 19:35:13 2010 New Revision: 112919 URL: http://llvm.org/viewvc/llvm-project?rev=112919&view=rev Log: Remove Predicate_* calls from Mips Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=112919&r1=112918&r2=112919&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Thu Sep 2 19:35:13 2010 @@ -184,8 +184,9 @@ if (!Subtarget.isMips1() || NVT != MVT::f64) return NULL; - if (!Predicate_unindexedload(N) || - !Predicate_load(N)) + LoadSDNode *LN = cast(N); + if (LN->getExtensionType() != ISD::NON_EXTLOAD || + LN->getAddressingMode() != ISD::UNINDEXED) return NULL; SDValue Chain = N->getOperand(0); From stoklund at 2pi.dk Thu Sep 2 19:35:16 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Fri, 03 Sep 2010 00:35:16 -0000 Subject: [llvm-commits] [llvm] r112920 - in /llvm/trunk/lib/Target: MBlaze/MBlazeISelDAGToDAG.cpp XCore/XCoreISelDAGToDAG.cpp XCore/XCoreInstrInfo.td Message-ID: <20100903003516.49E5D2A6C12D@llvm.org> Author: stoklund Date: Thu Sep 2 19:35:16 2010 New Revision: 112920 URL: http://llvm.org/viewvc/llvm-project?rev=112920&view=rev Log: Remove Predicate_* calls from MBlaze and XCore Modified: llvm/trunk/lib/Target/MBlaze/MBlazeISelDAGToDAG.cpp llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td Modified: llvm/trunk/lib/Target/MBlaze/MBlazeISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeISelDAGToDAG.cpp?rev=112920&r1=112919&r2=112920&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeISelDAGToDAG.cpp Thu Sep 2 19:35:16 2010 @@ -219,7 +219,7 @@ // Operand is a result from an ADD. if (Addr.getOpcode() == ISD::ADD) { if (ConstantSDNode *CN = dyn_cast(Addr.getOperand(1))) { - if (Predicate_immSExt16(CN)) { + if (isUInt<16>(CN->getZExtValue())) { // If the first operand is a FI, get the TargetFI Node if (FrameIndexSDNode *FIN = dyn_cast Modified: llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp?rev=112920&r1=112919&r2=112920&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp Thu Sep 2 19:35:16 2010 @@ -56,6 +56,17 @@ return CurDAG->getTargetConstant(Imm, MVT::i32); } + inline bool immMskBitp(SDNode *inN) const { + ConstantSDNode *N = cast(inN); + uint32_t value = (uint32_t)N->getZExtValue(); + if (!isMask_32(value)) { + return false; + } + int msksize = 32 - CountLeadingZeros_32(value); + return (msksize >= 1 && msksize <= 8) || + msksize == 16 || msksize == 24 || msksize == 32; + } + // Complex Pattern Selectors. bool SelectADDRspii(SDNode *Op, SDValue Addr, SDValue &Base, SDValue &Offset); @@ -151,17 +162,15 @@ switch (N->getOpcode()) { default: break; case ISD::Constant: { - if (Predicate_immMskBitp(N)) { + uint64_t Val = cast(N)->getZExtValue(); + if (immMskBitp(N)) { // Transformation function: get the size of a mask - int64_t MaskVal = cast(N)->getZExtValue(); - assert(isMask_32(MaskVal)); // Look for the first non-zero bit - SDValue MskSize = getI32Imm(32 - CountLeadingZeros_32(MaskVal)); + SDValue MskSize = getI32Imm(32 - CountLeadingZeros_32(Val)); return CurDAG->getMachineNode(XCore::MKMSK_rus, dl, MVT::i32, MskSize); } - else if (! Predicate_immU16(N)) { - unsigned Val = cast(N)->getZExtValue(); + else if (!isUInt<16>(Val)) { SDValue CPIdx = CurDAG->getTargetConstantPool(ConstantInt::get( Type::getInt32Ty(*CurDAG->getContext()), Val), Modified: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td?rev=112920&r1=112919&r2=112920&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td (original) +++ llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td Thu Sep 2 19:35:16 2010 @@ -140,17 +140,7 @@ return (uint32_t)N->getZExtValue() < (1 << 20); }]>; -def immMskBitp : PatLeaf<(imm), [{ - uint32_t value = (uint32_t)N->getZExtValue(); - if (!isMask_32(value)) { - return false; - } - int msksize = 32 - CountLeadingZeros_32(value); - return (msksize >= 1 && msksize <= 8) - || msksize == 16 - || msksize == 24 - || msksize == 32; -}]>; +def immMskBitp : PatLeaf<(imm), [{ return immMskBitp(N); }]>; def immBitp : PatLeaf<(imm), [{ uint32_t value = (uint32_t)N->getZExtValue(); From stoklund at 2pi.dk Thu Sep 2 19:35:18 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Fri, 03 Sep 2010 00:35:18 -0000 Subject: [llvm-commits] [llvm] r112921 - in /llvm/trunk/lib/Target/X86: X86ISelDAGToDAG.cpp X86Instr64bit.td X86InstrInfo.td Message-ID: <20100903003519.0EF822A6C12E@llvm.org> Author: stoklund Date: Thu Sep 2 19:35:18 2010 New Revision: 112921 URL: http://llvm.org/viewvc/llvm-project?rev=112921&view=rev Log: Don't call Predicate_* from X86 target. Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp llvm/trunk/lib/Target/X86/X86Instr64bit.td llvm/trunk/lib/Target/X86/X86InstrInfo.td Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=112921&r1=112920&r2=112921&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Thu Sep 2 19:35:18 2010 @@ -171,6 +171,17 @@ virtual void PreprocessISelDAG(); + inline bool immSext8(SDNode *N) const { + return isInt<8>(cast(N)->getSExtValue()); + } + + // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit + // sign extended field. + inline bool i64immSExt32(SDNode *N) const { + uint64_t v = cast(N)->getZExtValue(); + return (int64_t)v == (int32_t)v; + } + // Include the pieces autogenerated from the target description. #include "X86GenDAGISel.inc" @@ -1396,7 +1407,7 @@ Opc = X86::LOCK_DEC16m; else if (isSub) { if (isCN) { - if (Predicate_immSext8(Val.getNode())) + if (immSext8(Val.getNode())) Opc = X86::LOCK_SUB16mi8; else Opc = X86::LOCK_SUB16mi; @@ -1404,7 +1415,7 @@ Opc = X86::LOCK_SUB16mr; } else { if (isCN) { - if (Predicate_immSext8(Val.getNode())) + if (immSext8(Val.getNode())) Opc = X86::LOCK_ADD16mi8; else Opc = X86::LOCK_ADD16mi; @@ -1419,7 +1430,7 @@ Opc = X86::LOCK_DEC32m; else if (isSub) { if (isCN) { - if (Predicate_immSext8(Val.getNode())) + if (immSext8(Val.getNode())) Opc = X86::LOCK_SUB32mi8; else Opc = X86::LOCK_SUB32mi; @@ -1427,7 +1438,7 @@ Opc = X86::LOCK_SUB32mr; } else { if (isCN) { - if (Predicate_immSext8(Val.getNode())) + if (immSext8(Val.getNode())) Opc = X86::LOCK_ADD32mi8; else Opc = X86::LOCK_ADD32mi; @@ -1443,17 +1454,17 @@ else if (isSub) { Opc = X86::LOCK_SUB64mr; if (isCN) { - if (Predicate_immSext8(Val.getNode())) + if (immSext8(Val.getNode())) Opc = X86::LOCK_SUB64mi8; - else if (Predicate_i64immSExt32(Val.getNode())) + else if (i64immSExt32(Val.getNode())) Opc = X86::LOCK_SUB64mi32; } } else { Opc = X86::LOCK_ADD64mr; if (isCN) { - if (Predicate_immSext8(Val.getNode())) + if (immSext8(Val.getNode())) Opc = X86::LOCK_ADD64mi8; - else if (Predicate_i64immSExt32(Val.getNode())) + else if (i64immSExt32(Val.getNode())) Opc = X86::LOCK_ADD64mi32; } } Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=112921&r1=112920&r2=112921&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original) +++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Thu Sep 2 19:35:18 2010 @@ -73,11 +73,7 @@ return getI32Imm((unsigned)N->getZExtValue()); }]>; -def i64immSExt32 : PatLeaf<(i64 imm), [{ - // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit - // sign extended field. - return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue(); -}]>; +def i64immSExt32 : PatLeaf<(i64 imm), [{ return i64immSExt32(N); }]>; def i64immZExt32 : PatLeaf<(i64 imm), [{ Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=112921&r1=112920&r2=112921&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Thu Sep 2 19:35:18 2010 @@ -414,9 +414,7 @@ def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE def X86_COND_S : PatLeaf<(i8 15)>; -def immSext8 : PatLeaf<(imm), [{ - return N->getSExtValue() == (int8_t)N->getSExtValue(); -}]>; +def immSext8 : PatLeaf<(imm), [{ return immSext8(N); }]>; def i16immSExt8 : PatLeaf<(i16 immSext8)>; def i32immSExt8 : PatLeaf<(i32 immSext8)>; From echristo at apple.com Thu Sep 2 19:35:48 2010 From: echristo at apple.com (Eric Christopher) Date: Fri, 03 Sep 2010 00:35:48 -0000 Subject: [llvm-commits] [llvm] r112923 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20100903003548.187322A6C12C@llvm.org> Author: echristo Date: Thu Sep 2 19:35:47 2010 New Revision: 112923 URL: http://llvm.org/viewvc/llvm-project?rev=112923&view=rev Log: Simple branch instruction support. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=112923&r1=112922&r2=112923&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Thu Sep 2 19:35:47 2010 @@ -112,6 +112,7 @@ // Instruction selection routines. virtual bool ARMSelectLoad(const Instruction *I); virtual bool ARMSelectStore(const Instruction *I); + virtual bool ARMSelectBranch(const Instruction *I); // Utility routines. private: @@ -619,6 +620,26 @@ return true; } +bool ARMFastISel::ARMSelectBranch(const Instruction *I) { + const BranchInst *BI = cast(I); + MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)]; + MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)]; + + // Simple branch support. + unsigned CondReg = getRegForValue(BI->getCondition()); + if (CondReg == 0) return false; + + unsigned CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr; + unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc; + AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc)) + .addReg(CondReg).addReg(CondReg)); + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc)) + .addMBB(TBB).addImm(ARMCC::NE).addReg(ARM::CPSR); + FastEmitBranch(FBB, DL); + FuncInfo.MBB->addSuccessor(TBB); + return true; +} + // TODO: SoftFP support. bool ARMFastISel::TargetSelectInstruction(const Instruction *I) { // No Thumb-1 for now. @@ -629,6 +650,8 @@ return ARMSelectLoad(I); case Instruction::Store: return ARMSelectStore(I); + case Instruction::Br: + return ARMSelectBranch(I); default: break; } return false; From bruno.cardoso at gmail.com Thu Sep 2 19:38:05 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Thu, 2 Sep 2010 17:38:05 -0700 Subject: [llvm-commits] [llvm] r112919 - /llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp In-Reply-To: <20100903003513.65AAE2A6C12C@llvm.org> References: <20100903003513.65AAE2A6C12C@llvm.org> Message-ID: Thanks Jakob! :) On Thu, Sep 2, 2010 at 5:35 PM, Jakob Stoklund Olesen wrote: > Author: stoklund > Date: Thu Sep ?2 19:35:13 2010 > New Revision: 112919 > > URL: http://llvm.org/viewvc/llvm-project?rev=112919&view=rev > Log: > Remove Predicate_* calls from Mips > > Modified: > ? ?llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp > > Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=112919&r1=112918&r2=112919&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original) > +++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Thu Sep ?2 19:35:13 2010 > @@ -184,8 +184,9 @@ > ? if (!Subtarget.isMips1() || NVT != MVT::f64) > ? ? return NULL; > > - ?if (!Predicate_unindexedload(N) || > - ? ? ?!Predicate_load(N)) > + ?LoadSDNode *LN = cast(N); > + ?if (LN->getExtensionType() != ISD::NON_EXTLOAD || > + ? ? ?LN->getAddressingMode() != ISD::UNINDEXED) > ? ? return NULL; > > ? SDValue Chain = N->getOperand(0); > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -- Bruno Cardoso Lopes http://www.brunocardoso.cc From stoklund at 2pi.dk Thu Sep 2 19:39:50 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Fri, 03 Sep 2010 00:39:50 -0000 Subject: [llvm-commits] [llvm] r112924 - in /llvm/trunk/utils/TableGen: DAGISelEmitter.cpp DAGISelEmitter.h Message-ID: <20100903003950.BD1402A6C12C@llvm.org> Author: stoklund Date: Thu Sep 2 19:39:50 2010 New Revision: 112924 URL: http://llvm.org/viewvc/llvm-project?rev=112924&view=rev Log: Stop emitting predicate functions. They are no longer used. Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp llvm/trunk/utils/TableGen/DAGISelEmitter.h Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=112924&r1=112923&r2=112924&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Thu Sep 2 19:39:50 2010 @@ -57,51 +57,6 @@ return Cost; } -//===----------------------------------------------------------------------===// -// Predicate emitter implementation. -// - -void DAGISelEmitter::EmitPredicateFunctions(raw_ostream &OS) { - OS << "\n// Predicate functions.\n"; - - // Walk the pattern fragments, adding them to a map, which sorts them by - // name. - typedef std::map > PFsByNameTy; - PFsByNameTy PFsByName; - - for (CodeGenDAGPatterns::pf_iterator I = CGP.pf_begin(), E = CGP.pf_end(); - I != E; ++I) - PFsByName.insert(std::make_pair(I->first->getName(), *I)); - - - for (PFsByNameTy::iterator I = PFsByName.begin(), E = PFsByName.end(); - I != E; ++I) { - Record *PatFragRecord = I->second.first;// Record that derives from PatFrag. - TreePattern *P = I->second.second; - - // If there is a code init for this fragment, emit the predicate code. - std::string Code = PatFragRecord->getValueAsCode("Predicate"); - if (Code.empty()) continue; - - if (P->getOnlyTree()->isLeaf()) - OS << "inline bool Predicate_" << PatFragRecord->getName() - << "(SDNode *N) const {\n"; - else { - std::string ClassName = - CGP.getSDNodeInfo(P->getOnlyTree()->getOperator()).getSDClassName(); - const char *C2 = ClassName == "SDNode" ? "N" : "inN"; - - OS << "inline bool Predicate_" << PatFragRecord->getName() - << "(SDNode *" << C2 << ") const {\n"; - if (ClassName != "SDNode") - OS << " " << ClassName << " *N = cast<" << ClassName << ">(inN);\n"; - } - OS << Code << "\n}\n"; - } - - OS << "\n\n"; -} - namespace { // PatternSortingPredicate - return true if we prefer to match LHS before RHS. // In particular, we want to match maximal patterns first and lowest cost within @@ -168,9 +123,6 @@ errs() << "\n"; }); - // FIXME: These are being used by hand written code, gross. - EmitPredicateFunctions(OS); - // Add all the patterns to a temporary list so we can sort them. std::vector Patterns; for (CodeGenDAGPatterns::ptm_iterator I = CGP.ptm_begin(), E = CGP.ptm_end(); Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.h?rev=112924&r1=112923&r2=112924&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/DAGISelEmitter.h (original) +++ llvm/trunk/utils/TableGen/DAGISelEmitter.h Thu Sep 2 19:39:50 2010 @@ -31,8 +31,6 @@ // run - Output the isel, returning true on failure. void run(raw_ostream &OS); -private: - void EmitPredicateFunctions(raw_ostream &OS); }; } // End llvm namespace From stoklund at 2pi.dk Thu Sep 2 19:47:26 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 2 Sep 2010 17:47:26 -0700 Subject: [llvm-commits] [llvm] r112899 - /llvm/trunk/lib/VMCore/AsmWriter.cpp In-Reply-To: <20100902225210.40BDA2A6C12C@llvm.org> References: <20100902225210.40BDA2A6C12C@llvm.org> Message-ID: On Sep 2, 2010, at 3:52 PM, Chris Lattner wrote: > going further, remove the " [#uses=3]" comments entirely. They > add a lot of noise, confuse people about what the IR is, and don't add > any particular value. When the types are long it makes it really really > hard to read IR. Nice! This cleans up .ll files pretty well. There are still predicate comments on each basic block, but they are often useful. From bruno.cardoso at gmail.com Thu Sep 2 20:24:00 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Fri, 03 Sep 2010 01:24:00 -0000 Subject: [llvm-commits] [llvm] r112934 - in /llvm/trunk/lib/Target/X86: X86ISelLowering.cpp X86InstrSSE.td Message-ID: <20100903012400.DD2A52A6C12C@llvm.org> Author: bruno Date: Thu Sep 2 20:24:00 2010 New Revision: 112934 URL: http://llvm.org/viewvc/llvm-project?rev=112934&view=rev Log: - Use specific nodes to match unpckl masks. - Teach getShuffleScalarElt how to handle more target specific nodes, so the DAGCombine can make use of it. - Add another hack to avoid the node update problem during legalization. More description on the comments Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=112934&r1=112933&r2=112934&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Sep 2 20:24:00 2010 @@ -15,6 +15,7 @@ #define DEBUG_TYPE "x86-isel" #include "X86.h" #include "X86InstrBuilder.h" +#include "X86ShuffleDecode.h" #include "X86ISelLowering.h" #include "X86TargetMachine.h" #include "X86TargetObjectFile.h" @@ -2602,9 +2603,11 @@ case X86ISD::MOVSS: case X86ISD::MOVSD: case X86ISD::UNPCKLPS: + case X86ISD::UNPCKLPD: case X86ISD::PUNPCKLWD: case X86ISD::PUNPCKLBW: case X86ISD::PUNPCKLDQ: + case X86ISD::PUNPCKLQDQ: case X86ISD::UNPCKHPS: case X86ISD::PUNPCKHWD: case X86ISD::PUNPCKHBW: @@ -2663,9 +2666,11 @@ case X86ISD::MOVSS: case X86ISD::MOVSD: case X86ISD::UNPCKLPS: + case X86ISD::UNPCKLPD: case X86ISD::PUNPCKLWD: case X86ISD::PUNPCKLBW: case X86ISD::PUNPCKLDQ: + case X86ISD::PUNPCKLQDQ: case X86ISD::UNPCKHPS: case X86ISD::PUNPCKHWD: case X86ISD::PUNPCKHBW: @@ -3698,7 +3703,60 @@ // Recurse into target specific vector shuffles to find scalars. if (isTargetShuffle(Opcode)) { + int NumElems = VT.getVectorNumElements(); + SmallVector ShuffleMask; + SDValue ImmN; + switch(Opcode) { + case X86ISD::SHUFPS: + case X86ISD::SHUFPD: + ImmN = N->getOperand(N->getNumOperands()-1); + DecodeSHUFPSMask(NumElems, + cast(ImmN)->getZExtValue(), + ShuffleMask); + break; + case X86ISD::PUNPCKHBW: + case X86ISD::PUNPCKHWD: + case X86ISD::PUNPCKHDQ: + case X86ISD::PUNPCKHQDQ: + DecodePUNPCKHMask(NumElems, ShuffleMask); + break; + case X86ISD::UNPCKHPS: + case X86ISD::UNPCKHPD: + DecodeUNPCKHPMask(NumElems, ShuffleMask); + break; + case X86ISD::PUNPCKLBW: + case X86ISD::PUNPCKLWD: + case X86ISD::PUNPCKLDQ: + case X86ISD::PUNPCKLQDQ: + DecodePUNPCKLMask(NumElems, ShuffleMask); + break; + case X86ISD::UNPCKLPS: + case X86ISD::UNPCKLPD: + DecodeUNPCKLPMask(NumElems, ShuffleMask); + break; + case X86ISD::MOVHLPS: + DecodeMOVHLPSMask(NumElems, ShuffleMask); + break; + case X86ISD::MOVLHPS: + DecodeMOVLHPSMask(NumElems, ShuffleMask); + break; + case X86ISD::PSHUFD: + ImmN = N->getOperand(N->getNumOperands()-1); + DecodePSHUFMask(NumElems, + cast(ImmN)->getZExtValue(), + ShuffleMask); + break; + case X86ISD::PSHUFHW: + ImmN = N->getOperand(N->getNumOperands()-1); + DecodePSHUFHWMask(cast(ImmN)->getZExtValue(), + ShuffleMask); + break; + case X86ISD::PSHUFLW: + ImmN = N->getOperand(N->getNumOperands()-1); + DecodePSHUFLWMask(cast(ImmN)->getZExtValue(), + ShuffleMask); + break; case X86ISD::MOVSS: case X86ISD::MOVSD: { // The index 0 always comes from the first element of the second source, @@ -3711,6 +3769,13 @@ assert("not implemented for target shuffle node"); return SDValue(); } + + Index = ShuffleMask[Index]; + if (Index < 0) + return DAG.getUNDEF(VT.getVectorElementType()); + + SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); + return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG); } // Actual nodes that may contain scalar elements @@ -5049,6 +5114,16 @@ return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); } +static bool MayFoldVectorLoad(SDValue V) { + if (V.hasOneUse() && V.getOpcode() == ISD::BIT_CONVERT) + V = V.getOperand(0); + if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) + V = V.getOperand(0); + if (MayFoldLoad(V)) + return true; + return false; +} + static SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) { @@ -5093,15 +5168,9 @@ // potencial load folding here, otherwise use SHUFPS or MOVSD to match the // same masks. bool CanFoldLoad = false; - SDValue TmpV1 = V1; - SDValue TmpV2 = V2; // Trivial case, when V2 comes from a load. - if (TmpV2.hasOneUse() && TmpV2.getOpcode() == ISD::BIT_CONVERT) - TmpV2 = TmpV2.getOperand(0); - if (TmpV2.hasOneUse() && TmpV2.getOpcode() == ISD::SCALAR_TO_VECTOR) - TmpV2 = TmpV2.getOperand(0); - if (MayFoldLoad(TmpV2)) + if (MayFoldVectorLoad(V2)) CanFoldLoad = true; // When V1 is a load, it can be folded later into a store in isel, example: @@ -5109,9 +5178,7 @@ // turns into: // (MOVLPSmr addr:$src1, VR128:$src2) // So, recognize this potential and also use MOVLPS or MOVLPD - if (TmpV1.hasOneUse() && TmpV1.getOpcode() == ISD::BIT_CONVERT) - TmpV1 = TmpV1.getOperand(0); - if (MayFoldLoad(TmpV1) && MayFoldIntoStore(Op)) + if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op)) CanFoldLoad = true; if (CanFoldLoad) { @@ -5142,6 +5209,20 @@ X86::getShuffleSHUFImmediate(SVOp), DAG); } +static unsigned getUNPCKLOpcode(EVT VT) { + switch(VT.getSimpleVT().SimpleTy) { + case MVT::v4i32: return X86ISD::PUNPCKLDQ; + case MVT::v2i64: return X86ISD::PUNPCKLQDQ; + case MVT::v4f32: return X86ISD::UNPCKLPS; + case MVT::v2f64: return X86ISD::UNPCKLPD; + case MVT::v16i8: return X86ISD::PUNPCKLBW; + case MVT::v8i16: return X86ISD::PUNPCKLWD; + default: + llvm_unreachable("Unknow type for unpckl"); + } + return 0; +} + SDValue X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { ShuffleVectorSDNode *SVOp = cast(Op); @@ -5272,7 +5353,8 @@ // FIXME: fold these into legal mask. if (!isMMX) { - if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp)) + if (X86::isMOVLHPSMask(SVOp) && + (!X86::isUNPCKLMask(SVOp) || MayFoldVectorLoad(V2))) return getMOVLowToHigh(Op, dl, DAG, HasSSE2); if (X86::isMOVHLPSMask(SVOp)) @@ -5326,8 +5408,11 @@ return getMOVL(DAG, dl, VT, V2, V1); } - if (X86::isUNPCKLMask(SVOp) || - X86::isUNPCKHMask(SVOp)) + if (X86::isUNPCKLMask(SVOp)) + return (isMMX) ? + Op : getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V2, DAG); + + if (X86::isUNPCKHMask(SVOp)) return Op; if (V2IsSplat) { @@ -5350,8 +5435,12 @@ // FIXME: this seems wrong. SDValue NewOp = CommuteVectorShuffle(SVOp, DAG); ShuffleVectorSDNode *NewSVOp = cast(NewOp); - if (X86::isUNPCKLMask(NewSVOp) || - X86::isUNPCKHMask(NewSVOp)) + + if (X86::isUNPCKLMask(NewSVOp)) + return (isMMX) ? + Op : getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V2, V1, DAG); + + if (X86::isUNPCKHMask(NewSVOp)) return NewOp; } @@ -10621,7 +10710,6 @@ SelectionDAG &DAG = DCI.DAG; switch (N->getOpcode()) { default: break; - case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this); case ISD::EXTRACT_VECTOR_ELT: return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this); case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget); @@ -10638,6 +10726,28 @@ case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG); + case X86ISD::SHUFPS: // Handle all target specific shuffles + case X86ISD::SHUFPD: + case X86ISD::PUNPCKHBW: + case X86ISD::PUNPCKHWD: + case X86ISD::PUNPCKHDQ: + case X86ISD::PUNPCKHQDQ: + case X86ISD::UNPCKHPS: + case X86ISD::UNPCKHPD: + case X86ISD::PUNPCKLBW: + case X86ISD::PUNPCKLWD: + case X86ISD::PUNPCKLDQ: + case X86ISD::PUNPCKLQDQ: + case X86ISD::UNPCKLPS: + case X86ISD::UNPCKLPD: + case X86ISD::MOVHLPS: + case X86ISD::MOVLHPS: + case X86ISD::PSHUFD: + case X86ISD::PSHUFHW: + case X86ISD::PSHUFLW: + case X86ISD::MOVSS: + case X86ISD::MOVSD: + case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this); } return SDValue(); Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=112934&r1=112933&r2=112934&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Sep 2 20:24:00 2010 @@ -5819,6 +5819,13 @@ def : Pat<(v2f64 (X86Movlhpd VR128:$src1, (scalar_to_vector (loadf64 addr:$src2)))), (MOVHPDrm VR128:$src1, addr:$src2)>; +// FIXME: Instead of X86Unpcklpd, there should be a X86Movlhpd here, the problem +// is during lowering, where it's not possible to recognize the load fold cause +// it has two uses through a bitcast. One use disappears at isel time and the +// fold opportunity reappears. +def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, + (scalar_to_vector (loadf64 addr:$src2)))), + (MOVHPDrm VR128:$src1, addr:$src2)>; // Shuffle with MOVSS def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))), From bruno.cardoso at gmail.com Thu Sep 2 20:28:51 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Fri, 03 Sep 2010 01:28:51 -0000 Subject: [llvm-commits] [llvm] r112938 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20100903012851.62A9D2A6C12C@llvm.org> Author: bruno Date: Thu Sep 2 20:28:51 2010 New Revision: 112938 URL: http://llvm.org/viewvc/llvm-project?rev=112938&view=rev Log: Fix comment Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=112938&r1=112937&r2=112938&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Sep 2 20:28:51 2010 @@ -9787,9 +9787,9 @@ return EltsFromConsecutiveLoads(VT, Elts, dl, DAG); } -/// PerformShuffleCombine - Detect vector gather/scatter index generation -/// and convert it from being a bunch of shuffles and extracts to a simple -/// store and scalar loads to extract the elements. +/// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index +/// generation and convert it from being a bunch of shuffles and extracts +/// to a simple store and scalar loads to extract the elements. static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG, const TargetLowering &TLI) { SDValue InputVector = N->getOperand(0); From bob.wilson at apple.com Thu Sep 2 20:32:05 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Fri, 03 Sep 2010 01:32:05 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r112940 - /llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp Message-ID: <20100903013205.6EE132A6C12C@llvm.org> Author: bwilson Date: Thu Sep 2 20:32:05 2010 New Revision: 112940 URL: http://llvm.org/viewvc/llvm-project?rev=112940&view=rev Log: Translate NEON vabdl, vaba, and vabal builtins to be implemented using the vabd intrinsic combined with zext and add operations. Modified: llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp Modified: llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp?rev=112940&r1=112939&r2=112940&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp Thu Sep 2 20:32:05 2010 @@ -1412,41 +1412,53 @@ Result = Builder.CreateCall2(intFn, Ops[0], Ops[1]); break; - case NEON_BUILTIN_vabdl: + case NEON_BUILTIN_vabdl: { if (datatype == neon_datatype_signed) - intID = Intrinsic::arm_neon_vabdls; + intID = Intrinsic::arm_neon_vabds; else if (datatype == neon_datatype_unsigned) - intID = Intrinsic::arm_neon_vabdlu; + intID = Intrinsic::arm_neon_vabdu; else return BadImmediateError(exp, Result); - intFn = Intrinsic::getDeclaration(TheModule, intID, &ResultType, 1); - Result = Builder.CreateCall2(intFn, Ops[0], Ops[1]); + const VectorType *VTy = dyn_cast(ResultType); + assert(VTy && "expected a vector type for vabdl result"); + const llvm::Type *DTy = VectorType::getTruncatedElementVectorType(VTy); + intFn = Intrinsic::getDeclaration(TheModule, intID, &DTy, 1); + Ops[0] = Builder.CreateCall2(intFn, Ops[0], Ops[1]); + Result = Builder.CreateZExt(Ops[0], ResultType); break; + } case NEON_BUILTIN_vaba: if (datatype == neon_datatype_signed) - intID = Intrinsic::arm_neon_vabas; + intID = Intrinsic::arm_neon_vabds; else if (datatype == neon_datatype_unsigned) - intID = Intrinsic::arm_neon_vabau; + intID = Intrinsic::arm_neon_vabdu; else return BadImmediateError(exp, Result); intFn = Intrinsic::getDeclaration(TheModule, intID, &ResultType, 1); - Result = Builder.CreateCall3(intFn, Ops[0], Ops[1], Ops[2]); + Ops[1] = Builder.CreateCall2(intFn, Ops[1], Ops[2]); + Result = Builder.CreateAdd(Ops[0], Ops[1]); break; - case NEON_BUILTIN_vabal: + case NEON_BUILTIN_vabal: { if (datatype == neon_datatype_signed) - intID = Intrinsic::arm_neon_vabals; + intID = Intrinsic::arm_neon_vabds; else if (datatype == neon_datatype_unsigned) - intID = Intrinsic::arm_neon_vabalu; + intID = Intrinsic::arm_neon_vabdu; else return BadImmediateError(exp, Result); - intFn = Intrinsic::getDeclaration(TheModule, intID, &ResultType, 1); - Result = Builder.CreateCall3(intFn, Ops[0], Ops[1], Ops[2]); + const VectorType *VTy = dyn_cast(ResultType); + assert(VTy && "expected a vector type for vabal result"); + const llvm::Type *DTy = VectorType::getTruncatedElementVectorType(VTy); + intFn = Intrinsic::getDeclaration(TheModule, intID, &DTy, 1); + Ops[1] = Builder.CreateCall2(intFn, Ops[1], Ops[2]); + Ops[1] = Builder.CreateZExt(Ops[1], ResultType); + Result = Builder.CreateAdd(Ops[0], Ops[1]); break; + } case NEON_BUILTIN_vmax: if (datatype == neon_datatype_float || From bob.wilson at apple.com Thu Sep 2 20:35:08 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Fri, 03 Sep 2010 01:35:08 -0000 Subject: [llvm-commits] [llvm] r112941 - in /llvm/trunk: include/llvm/IntrinsicsARM.td lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMInstrNEON.td lib/VMCore/AutoUpgrade.cpp test/Bitcode/neon-intrinsics.ll test/Bitcode/neon-intrinsics.ll.bc test/CodeGen/ARM/vaba.ll test/CodeGen/ARM/vabd.ll Message-ID: <20100903013508.EC7E22A6C12C@llvm.org> Author: bwilson Date: Thu Sep 2 20:35:08 2010 New Revision: 112941 URL: http://llvm.org/viewvc/llvm-project?rev=112941&view=rev Log: Replace NEON vabdl, vaba, and vabal intrinsics with combinations of the vabd intrinsic and add and/or zext operations. In the case of vaba, this also avoids the need for a DAG combine pattern to combine vabd with add. Update tests. Auto-upgrade the old intrinsics. Modified: llvm/trunk/include/llvm/IntrinsicsARM.td llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/lib/VMCore/AutoUpgrade.cpp llvm/trunk/test/Bitcode/neon-intrinsics.ll llvm/trunk/test/Bitcode/neon-intrinsics.ll.bc llvm/trunk/test/CodeGen/ARM/vaba.ll llvm/trunk/test/CodeGen/ARM/vabd.ll Modified: llvm/trunk/include/llvm/IntrinsicsARM.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsARM.td?rev=112941&r1=112940&r2=112941&view=diff ============================================================================== --- llvm/trunk/include/llvm/IntrinsicsARM.td (original) +++ llvm/trunk/include/llvm/IntrinsicsARM.td Thu Sep 2 20:35:08 2010 @@ -176,14 +176,6 @@ // Vector Absolute Differences. def int_arm_neon_vabds : Neon_2Arg_Intrinsic; def int_arm_neon_vabdu : Neon_2Arg_Intrinsic; -def int_arm_neon_vabdls : Neon_2Arg_Long_Intrinsic; -def int_arm_neon_vabdlu : Neon_2Arg_Long_Intrinsic; - -// Vector Absolute Difference and Accumulate. -def int_arm_neon_vabas : Neon_3Arg_Intrinsic; -def int_arm_neon_vabau : Neon_3Arg_Intrinsic; -def int_arm_neon_vabals : Neon_3Arg_Long_Intrinsic; -def int_arm_neon_vabalu : Neon_3Arg_Long_Intrinsic; // Vector Pairwise Add. def int_arm_neon_vpadd : Neon_2Arg_Intrinsic; Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=112941&r1=112940&r2=112941&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Sep 2 20:35:08 2010 @@ -4293,28 +4293,11 @@ /// operands. static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI) { - SelectionDAG &DAG = DCI.DAG; - // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) { SDValue Result = combineSelectAndUse(N, N0, N1, DCI); if (Result.getNode()) return Result; } - - // fold (add (arm_neon_vabd a, b) c) -> (arm_neon_vaba c, a, b) - EVT VT = N->getValueType(0); - if (N0.getOpcode() == ISD::INTRINSIC_WO_CHAIN && VT.isInteger()) { - unsigned IntNo = cast(N0.getOperand(0))->getZExtValue(); - if (IntNo == Intrinsic::arm_neon_vabds) - return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(), VT, - DAG.getConstant(Intrinsic::arm_neon_vabas, MVT::i32), - N1, N0.getOperand(1), N0.getOperand(2)); - if (IntNo == Intrinsic::arm_neon_vabdu) - return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(), VT, - DAG.getConstant(Intrinsic::arm_neon_vabau, MVT::i32), - N1, N0.getOperand(1), N0.getOperand(2)); - } - return SDValue(); } Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=112941&r1=112940&r2=112941&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Thu Sep 2 20:35:08 2010 @@ -1288,6 +1288,24 @@ (ResTy (NEONvduplane (OpTy DPR_8:$src3), imm:$lane)))))))]>; +// Neon Intrinsic-Op instructions (VABA): double- and quad-register. +class N3VDIntOp op21_20, bits<4> op11_8, bit op4, + InstrItinClass itin, string OpcodeStr, string Dt, + ValueType Ty, Intrinsic IntOp, SDNode OpNode> + : N3V; +class N3VQIntOp op21_20, bits<4> op11_8, bit op4, + InstrItinClass itin, string OpcodeStr, string Dt, + ValueType Ty, Intrinsic IntOp, SDNode OpNode> + : N3V; + // Neon 3-argument intrinsics, both double- and quad-register. // The destination register is also used as the first source operand register. class N3VDInt3 op21_20, bits<4> op11_8, bit op4, @@ -1342,6 +1360,17 @@ (TyD (NEONvduplane (TyD DPR_8:$src3), imm:$lane))))))]>; +// Long Intrinsic-Op vector operations with explicit extend (VABAL). +class N3VLIntExtOp op21_20, bits<4> op11_8, bit op4, + InstrItinClass itin, string OpcodeStr, string Dt, + ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp, + SDNode OpNode> + : N3V; // Neon Long 3-argument intrinsic. The destination register is // a quad-register and is also used as the first source operand register. @@ -1433,6 +1462,19 @@ let isCommutable = Commutable; } +// Long 3-register intrinsics with explicit extend (VABDL). +class N3VLIntExt op21_20, bits<4> op11_8, bit op4, + InstrItinClass itin, string OpcodeStr, string Dt, + ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp, + bit Commutable> + : N3V { + let isCommutable = Commutable; +} + // Long 3-register intrinsics. class N3VLInt op21_20, bits<4> op11_8, bit op4, InstrItinClass itin, string OpcodeStr, string Dt, @@ -1918,6 +1960,21 @@ v8i16, v8i8, IntOp, Commutable>; } +// ....with explicit extend (VABDL). +multiclass N3VLIntExt_QHS op11_8, bit op4, + InstrItinClass itin, string OpcodeStr, string Dt, + Intrinsic IntOp, SDNode ExtOp, bit Commutable = 0> { + def v8i16 : N3VLIntExt; + def v4i32 : N3VLIntExt; + def v2i64 : N3VLIntExt; +} + // Neon Wide 3-register vector intrinsics, // source operand element sizes of 8, 16 and 32 bits: @@ -1975,6 +2032,29 @@ mul, ShOp>; } +// Neon Intrinsic-Op vector operations, +// element sizes of 8, 16 and 32 bits: +multiclass N3VIntOp_QHS op11_8, bit op4, + InstrItinClass itinD, InstrItinClass itinQ, + string OpcodeStr, string Dt, Intrinsic IntOp, + SDNode OpNode> { + // 64-bit vector types. + def v8i8 : N3VDIntOp; + def v4i16 : N3VDIntOp; + def v2i32 : N3VDIntOp; + + // 128-bit vector types. + def v16i8 : N3VQIntOp; + def v8i16 : N3VQIntOp; + def v4i32 : N3VQIntOp; +} + // Neon 3-argument intrinsics, // element sizes of 8, 16 and 32 bits: multiclass N3VInt3_QHS op11_8, bit op4, @@ -2050,6 +2130,21 @@ OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>; } +// ....with explicit extend (VABAL). +multiclass N3VLIntExtOp_QHS op11_8, bit op4, + InstrItinClass itin, string OpcodeStr, string Dt, + Intrinsic IntOp, SDNode ExtOp, SDNode OpNode> { + def v8i16 : N3VLIntExtOp; + def v4i32 : N3VLIntExtOp; + def v2i64 : N3VLIntExtOp; +} + // Neon 2-register vector intrinsics, // element sizes of 8, 16 and 32 bits: @@ -2765,32 +2860,32 @@ // VABD : Vector Absolute Difference defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q, - "vabd", "s", int_arm_neon_vabds, 0>; + "vabd", "s", int_arm_neon_vabds, 1>; defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q, - "vabd", "u", int_arm_neon_vabdu, 0>; + "vabd", "u", int_arm_neon_vabdu, 1>; def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND, - "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 0>; + "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>; def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ, - "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 0>; + "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>; // VABDL : Vector Absolute Difference Long (Q = | D - D |) -defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, IIC_VSUBi4Q, IIC_VSUBi4Q, - "vabdl", "s", int_arm_neon_vabdls, 0>; -defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, IIC_VSUBi4Q, IIC_VSUBi4Q, - "vabdl", "u", int_arm_neon_vabdlu, 0>; +defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q, + "vabdl", "s", int_arm_neon_vabds, zext, 1>; +defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q, + "vabdl", "u", int_arm_neon_vabdu, zext, 1>; // VABA : Vector Absolute Difference and Accumulate -defm VABAs : N3VInt3_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ, - "vaba", "s", int_arm_neon_vabas>; -defm VABAu : N3VInt3_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ, - "vaba", "u", int_arm_neon_vabau>; +defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ, + "vaba", "s", int_arm_neon_vabds, add>; +defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ, + "vaba", "u", int_arm_neon_vabdu, add>; // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |) -defm VABALs : N3VLInt3_QHS<0,1,0b0101,0, IIC_VABAD, IIC_VABAD, - "vabal", "s", int_arm_neon_vabals>; -defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, IIC_VABAD, IIC_VABAD, - "vabal", "u", int_arm_neon_vabalu>; +defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD, + "vabal", "s", int_arm_neon_vabds, zext, add>; +defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD, + "vabal", "u", int_arm_neon_vabdu, zext, add>; // Vector Maximum and Minimum. Modified: llvm/trunk/lib/VMCore/AutoUpgrade.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AutoUpgrade.cpp?rev=112941&r1=112940&r2=112941&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/AutoUpgrade.cpp (original) +++ llvm/trunk/lib/VMCore/AutoUpgrade.cpp Thu Sep 2 20:35:08 2010 @@ -81,21 +81,21 @@ } else if (Name.compare(5, 9, "arm.neon.", 9) == 0) { if (((Name.compare(14, 5, "vmovl", 5) == 0 || Name.compare(14, 5, "vaddl", 5) == 0 || - Name.compare(14, 5, "vsubl", 5) == 0) && - (Name.compare(19, 2, "s.", 2) == 0 || - Name.compare(19, 2, "u.", 2) == 0)) || - - ((Name.compare(14, 5, "vaddw", 5) == 0 || - Name.compare(14, 5, "vsubw", 5) == 0) && - (Name.compare(19, 2, "s.", 2) == 0 || - Name.compare(19, 2, "u.", 2) == 0)) || - - ((Name.compare(14, 5, "vmull", 5) == 0 || + Name.compare(14, 5, "vsubl", 5) == 0 || + Name.compare(14, 5, "vaddw", 5) == 0 || + Name.compare(14, 5, "vsubw", 5) == 0 || + Name.compare(14, 5, "vmull", 5) == 0 || Name.compare(14, 5, "vmlal", 5) == 0 || - Name.compare(14, 5, "vmlsl", 5) == 0) && + Name.compare(14, 5, "vmlsl", 5) == 0 || + Name.compare(14, 5, "vabdl", 5) == 0 || + Name.compare(14, 5, "vabal", 5) == 0) && (Name.compare(19, 2, "s.", 2) == 0 || Name.compare(19, 2, "u.", 2) == 0)) || + (Name.compare(14, 4, "vaba", 4) == 0 && + (Name.compare(18, 2, "s.", 2) == 0 || + Name.compare(18, 2, "u.", 2) == 0)) || + (Name.compare(14, 6, "vmovn.", 6) == 0)) { // Calls to these are transformed into IR without intrinsics. @@ -391,6 +391,35 @@ } } +/// CallVABD - As part of expanding a call to one of the old NEON vabdl, vaba, +/// or vabal intrinsics, construct a call to a vabd intrinsic. Examine the +/// name of the old intrinsic to determine whether to use a signed or unsigned +/// vabd intrinsic. Get the type from the old call instruction, adjusted for +/// half-size vector elements if the old intrinsic was vabdl or vabal. +static Instruction *CallVABD(CallInst *CI, Value *Arg0, Value *Arg1) { + Function *F = CI->getCalledFunction(); + const std::string& Name = F->getName(); + bool isLong = (Name.at(18) == 'l'); + bool isSigned = (Name.at(isLong ? 19 : 18) == 's'); + + Intrinsic::ID intID; + if (isSigned) + intID = Intrinsic::arm_neon_vabds; + else + intID = Intrinsic::arm_neon_vabdu; + + const Type *Ty = CI->getType(); + if (isLong) + Ty = VectorType::getTruncatedElementVectorType(cast(Ty)); + + Function *VABD = Intrinsic::getDeclaration(F->getParent(), intID, &Ty, 1); + Value *Operands[2]; + Operands[0] = Arg0; + Operands[1] = Arg1; + return CallInst::Create(VABD, Operands, Operands+2, + "upgraded."+CI->getName(), CI); +} + // UpgradeIntrinsicCall - Upgrade a call to an old intrinsic to be a call the // upgraded intrinsic. All argument and return casting must be provided in // order to seamlessly integrate with existing context. @@ -434,6 +463,15 @@ Instruction *MulI = BinaryOperator::CreateMul(V0, V1, "", CI); NewI = BinaryOperator::CreateSub(CI->getArgOperand(0), MulI, "upgraded."+CI->getName(), CI); + } else if (Name.compare(14, 4, "vabd", 4) == 0) { + NewI = CallVABD(CI, CI->getArgOperand(0), CI->getArgOperand(1)); + NewI = new ZExtInst(NewI, CI->getType(), "upgraded."+CI->getName(), CI); + } else if (Name.compare(14, 4, "vaba", 4) == 0) { + NewI = CallVABD(CI, CI->getArgOperand(1), CI->getArgOperand(2)); + if (Name.at(18) == 'l') + NewI = new ZExtInst(NewI, CI->getType(), "", CI); + NewI = BinaryOperator::CreateAdd(CI->getArgOperand(0), NewI, + "upgraded."+CI->getName(), CI); } else if (Name.compare(14, 6, "vmovn.", 6) == 0) { NewI = new TruncInst(CI->getArgOperand(0), CI->getType(), "upgraded." + CI->getName(), CI); @@ -675,7 +713,7 @@ } switch (NewFn->getIntrinsicID()) { - default: llvm_unreachable("Unknown function for CallInst upgrade."); + default: llvm_unreachable("Unknown function for CallInst upgrade."); case Intrinsic::arm_neon_vld1: case Intrinsic::arm_neon_vld2: case Intrinsic::arm_neon_vld3: Modified: llvm/trunk/test/Bitcode/neon-intrinsics.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bitcode/neon-intrinsics.ll?rev=112941&r1=112940&r2=112941&view=diff ============================================================================== --- llvm/trunk/test/Bitcode/neon-intrinsics.ll (original) +++ llvm/trunk/test/Bitcode/neon-intrinsics.ll Thu Sep 2 20:35:08 2010 @@ -126,6 +126,44 @@ ; CHECK-NEXT: mul <2 x i64> ; CHECK-NEXT: sub <2 x i64> +; vaba should be auto-upgraded to vabd + add + +; CHECK: vabas32 +; CHECK-NOT: arm.neon.vabas.v2i32 +; CHECK: arm.neon.vabds.v2i32 +; CHECK-NEXT: add <2 x i32> + +; CHECK: vabaQu8 +; CHECK-NOT: arm.neon.vabau.v16i8 +; CHECK: arm.neon.vabdu.v16i8 +; CHECK-NEXT: add <16 x i8> + +; vabal should be auto-upgraded to vabd with zext + add + +; CHECK: vabals16 +; CHECK-NOT: arm.neon.vabals.v4i32 +; CHECK: arm.neon.vabds.v4i16 +; CHECK-NEXT: zext <4 x i16> +; CHECK-NEXT: add <4 x i32> + +; CHECK: vabalu32 +; CHECK-NOT: arm.neon.vabalu.v2i64 +; CHECK: arm.neon.vabdu.v2i32 +; CHECK-NEXT: zext <2 x i32> +; CHECK-NEXT: add <2 x i64> + +; vabdl should be auto-upgraded to vabd with zext + +; CHECK: vabdls8 +; CHECK-NOT: arm.neon.vabdls.v8i16 +; CHECK: arm.neon.vabds.v8i8 +; CHECK-NEXT: zext <8 x i8> + +; CHECK: vabdlu16 +; CHECK-NOT: arm.neon.vabdlu.v4i32 +; CHECK: arm.neon.vabdu.v4i16 +; CHECK-NEXT: zext <4 x i16> + ; vmovn should be auto-upgraded to trunc ; CHECK: vmovni16 Modified: llvm/trunk/test/Bitcode/neon-intrinsics.ll.bc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bitcode/neon-intrinsics.ll.bc?rev=112941&r1=112940&r2=112941&view=diff ============================================================================== Binary files - no diff available. Modified: llvm/trunk/test/CodeGen/ARM/vaba.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vaba.ll?rev=112941&r1=112940&r2=112941&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vaba.ll (original) +++ llvm/trunk/test/CodeGen/ARM/vaba.ll Thu Sep 2 20:35:08 2010 @@ -6,8 +6,9 @@ %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B %tmp3 = load <8 x i8>* %C - %tmp4 = call <8 x i8> @llvm.arm.neon.vabas.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i8> %tmp3) - ret <8 x i8> %tmp4 + %tmp4 = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %tmp2, <8 x i8> %tmp3) + %tmp5 = add <8 x i8> %tmp1, %tmp4 + ret <8 x i8> %tmp5 } define <4 x i16> @vabas16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { @@ -16,8 +17,9 @@ %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B %tmp3 = load <4 x i16>* %C - %tmp4 = call <4 x i16> @llvm.arm.neon.vabas.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i16> %tmp3) - ret <4 x i16> %tmp4 + %tmp4 = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %tmp2, <4 x i16> %tmp3) + %tmp5 = add <4 x i16> %tmp1, %tmp4 + ret <4 x i16> %tmp5 } define <2 x i32> @vabas32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { @@ -26,8 +28,9 @@ %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B %tmp3 = load <2 x i32>* %C - %tmp4 = call <2 x i32> @llvm.arm.neon.vabas.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> %tmp3) - ret <2 x i32> %tmp4 + %tmp4 = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %tmp2, <2 x i32> %tmp3) + %tmp5 = add <2 x i32> %tmp1, %tmp4 + ret <2 x i32> %tmp5 } define <8 x i8> @vabau8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { @@ -36,8 +39,9 @@ %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B %tmp3 = load <8 x i8>* %C - %tmp4 = call <8 x i8> @llvm.arm.neon.vabau.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i8> %tmp3) - ret <8 x i8> %tmp4 + %tmp4 = call <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8> %tmp2, <8 x i8> %tmp3) + %tmp5 = add <8 x i8> %tmp1, %tmp4 + ret <8 x i8> %tmp5 } define <4 x i16> @vabau16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { @@ -46,8 +50,9 @@ %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B %tmp3 = load <4 x i16>* %C - %tmp4 = call <4 x i16> @llvm.arm.neon.vabau.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i16> %tmp3) - ret <4 x i16> %tmp4 + %tmp4 = call <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16> %tmp2, <4 x i16> %tmp3) + %tmp5 = add <4 x i16> %tmp1, %tmp4 + ret <4 x i16> %tmp5 } define <2 x i32> @vabau32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { @@ -56,8 +61,9 @@ %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B %tmp3 = load <2 x i32>* %C - %tmp4 = call <2 x i32> @llvm.arm.neon.vabau.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> %tmp3) - ret <2 x i32> %tmp4 + %tmp4 = call <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32> %tmp2, <2 x i32> %tmp3) + %tmp5 = add <2 x i32> %tmp1, %tmp4 + ret <2 x i32> %tmp5 } define <16 x i8> @vabaQs8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind { @@ -66,8 +72,9 @@ %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B %tmp3 = load <16 x i8>* %C - %tmp4 = call <16 x i8> @llvm.arm.neon.vabas.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i8> %tmp3) - ret <16 x i8> %tmp4 + %tmp4 = call <16 x i8> @llvm.arm.neon.vabds.v16i8(<16 x i8> %tmp2, <16 x i8> %tmp3) + %tmp5 = add <16 x i8> %tmp1, %tmp4 + ret <16 x i8> %tmp5 } define <8 x i16> @vabaQs16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind { @@ -76,8 +83,9 @@ %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B %tmp3 = load <8 x i16>* %C - %tmp4 = call <8 x i16> @llvm.arm.neon.vabas.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i16> %tmp3) - ret <8 x i16> %tmp4 + %tmp4 = call <8 x i16> @llvm.arm.neon.vabds.v8i16(<8 x i16> %tmp2, <8 x i16> %tmp3) + %tmp5 = add <8 x i16> %tmp1, %tmp4 + ret <8 x i16> %tmp5 } define <4 x i32> @vabaQs32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind { @@ -86,8 +94,9 @@ %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B %tmp3 = load <4 x i32>* %C - %tmp4 = call <4 x i32> @llvm.arm.neon.vabas.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> %tmp3) - ret <4 x i32> %tmp4 + %tmp4 = call <4 x i32> @llvm.arm.neon.vabds.v4i32(<4 x i32> %tmp2, <4 x i32> %tmp3) + %tmp5 = add <4 x i32> %tmp1, %tmp4 + ret <4 x i32> %tmp5 } define <16 x i8> @vabaQu8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind { @@ -96,8 +105,9 @@ %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B %tmp3 = load <16 x i8>* %C - %tmp4 = call <16 x i8> @llvm.arm.neon.vabau.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i8> %tmp3) - ret <16 x i8> %tmp4 + %tmp4 = call <16 x i8> @llvm.arm.neon.vabdu.v16i8(<16 x i8> %tmp2, <16 x i8> %tmp3) + %tmp5 = add <16 x i8> %tmp1, %tmp4 + ret <16 x i8> %tmp5 } define <8 x i16> @vabaQu16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind { @@ -106,8 +116,9 @@ %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B %tmp3 = load <8 x i16>* %C - %tmp4 = call <8 x i16> @llvm.arm.neon.vabau.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i16> %tmp3) - ret <8 x i16> %tmp4 + %tmp4 = call <8 x i16> @llvm.arm.neon.vabdu.v8i16(<8 x i16> %tmp2, <8 x i16> %tmp3) + %tmp5 = add <8 x i16> %tmp1, %tmp4 + ret <8 x i16> %tmp5 } define <4 x i32> @vabaQu32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind { @@ -116,25 +127,26 @@ %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B %tmp3 = load <4 x i32>* %C - %tmp4 = call <4 x i32> @llvm.arm.neon.vabau.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> %tmp3) - ret <4 x i32> %tmp4 + %tmp4 = call <4 x i32> @llvm.arm.neon.vabdu.v4i32(<4 x i32> %tmp2, <4 x i32> %tmp3) + %tmp5 = add <4 x i32> %tmp1, %tmp4 + ret <4 x i32> %tmp5 } -declare <8 x i8> @llvm.arm.neon.vabas.v8i8(<8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone -declare <4 x i16> @llvm.arm.neon.vabas.v4i16(<4 x i16>, <4 x i16>, <4 x i16>) nounwind readnone -declare <2 x i32> @llvm.arm.neon.vabas.v2i32(<2 x i32>, <2 x i32>, <2 x i32>) nounwind readnone - -declare <8 x i8> @llvm.arm.neon.vabau.v8i8(<8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone -declare <4 x i16> @llvm.arm.neon.vabau.v4i16(<4 x i16>, <4 x i16>, <4 x i16>) nounwind readnone -declare <2 x i32> @llvm.arm.neon.vabau.v2i32(<2 x i32>, <2 x i32>, <2 x i32>) nounwind readnone +declare <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32>, <2 x i32>) nounwind readnone -declare <16 x i8> @llvm.arm.neon.vabas.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone -declare <8 x i16> @llvm.arm.neon.vabas.v8i16(<8 x i16>, <8 x i16>, <8 x i16>) nounwind readnone -declare <4 x i32> @llvm.arm.neon.vabas.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) nounwind readnone +declare <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone -declare <16 x i8> @llvm.arm.neon.vabau.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone -declare <8 x i16> @llvm.arm.neon.vabau.v8i16(<8 x i16>, <8 x i16>, <8 x i16>) nounwind readnone -declare <4 x i32> @llvm.arm.neon.vabau.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) nounwind readnone +declare <16 x i8> @llvm.arm.neon.vabds.v16i8(<16 x i8>, <16 x i8>) nounwind readnone +declare <8 x i16> @llvm.arm.neon.vabds.v8i16(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vabds.v4i32(<4 x i32>, <4 x i32>) nounwind readnone + +declare <16 x i8> @llvm.arm.neon.vabdu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone +declare <8 x i16> @llvm.arm.neon.vabdu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vabdu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone define <8 x i16> @vabals8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { ;CHECK: vabals8: @@ -142,8 +154,10 @@ %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i8>* %B %tmp3 = load <8 x i8>* %C - %tmp4 = call <8 x i16> @llvm.arm.neon.vabals.v8i16(<8 x i16> %tmp1, <8 x i8> %tmp2, <8 x i8> %tmp3) - ret <8 x i16> %tmp4 + %tmp4 = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %tmp2, <8 x i8> %tmp3) + %tmp5 = zext <8 x i8> %tmp4 to <8 x i16> + %tmp6 = add <8 x i16> %tmp1, %tmp5 + ret <8 x i16> %tmp6 } define <4 x i32> @vabals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { @@ -152,8 +166,10 @@ %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i16>* %B %tmp3 = load <4 x i16>* %C - %tmp4 = call <4 x i32> @llvm.arm.neon.vabals.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2, <4 x i16> %tmp3) - ret <4 x i32> %tmp4 + %tmp4 = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %tmp2, <4 x i16> %tmp3) + %tmp5 = zext <4 x i16> %tmp4 to <4 x i32> + %tmp6 = add <4 x i32> %tmp1, %tmp5 + ret <4 x i32> %tmp6 } define <2 x i64> @vabals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { @@ -162,8 +178,10 @@ %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i32>* %B %tmp3 = load <2 x i32>* %C - %tmp4 = call <2 x i64> @llvm.arm.neon.vabals.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2, <2 x i32> %tmp3) - ret <2 x i64> %tmp4 + %tmp4 = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %tmp2, <2 x i32> %tmp3) + %tmp5 = zext <2 x i32> %tmp4 to <2 x i64> + %tmp6 = add <2 x i64> %tmp1, %tmp5 + ret <2 x i64> %tmp6 } define <8 x i16> @vabalu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { @@ -172,8 +190,10 @@ %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i8>* %B %tmp3 = load <8 x i8>* %C - %tmp4 = call <8 x i16> @llvm.arm.neon.vabalu.v8i16(<8 x i16> %tmp1, <8 x i8> %tmp2, <8 x i8> %tmp3) - ret <8 x i16> %tmp4 + %tmp4 = call <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8> %tmp2, <8 x i8> %tmp3) + %tmp5 = zext <8 x i8> %tmp4 to <8 x i16> + %tmp6 = add <8 x i16> %tmp1, %tmp5 + ret <8 x i16> %tmp6 } define <4 x i32> @vabalu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { @@ -182,8 +202,10 @@ %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i16>* %B %tmp3 = load <4 x i16>* %C - %tmp4 = call <4 x i32> @llvm.arm.neon.vabalu.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2, <4 x i16> %tmp3) - ret <4 x i32> %tmp4 + %tmp4 = call <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16> %tmp2, <4 x i16> %tmp3) + %tmp5 = zext <4 x i16> %tmp4 to <4 x i32> + %tmp6 = add <4 x i32> %tmp1, %tmp5 + ret <4 x i32> %tmp6 } define <2 x i64> @vabalu32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { @@ -192,38 +214,8 @@ %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i32>* %B %tmp3 = load <2 x i32>* %C - %tmp4 = call <2 x i64> @llvm.arm.neon.vabalu.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2, <2 x i32> %tmp3) - ret <2 x i64> %tmp4 -} - -declare <8 x i16> @llvm.arm.neon.vabals.v8i16(<8 x i16>, <8 x i8>, <8 x i8>) nounwind readnone -declare <4 x i32> @llvm.arm.neon.vabals.v4i32(<4 x i32>, <4 x i16>, <4 x i16>) nounwind readnone -declare <2 x i64> @llvm.arm.neon.vabals.v2i64(<2 x i64>, <2 x i32>, <2 x i32>) nounwind readnone - -declare <8 x i16> @llvm.arm.neon.vabalu.v8i16(<8 x i16>, <8 x i8>, <8 x i8>) nounwind readnone -declare <4 x i32> @llvm.arm.neon.vabalu.v4i32(<4 x i32>, <4 x i16>, <4 x i16>) nounwind readnone -declare <2 x i64> @llvm.arm.neon.vabalu.v2i64(<2 x i64>, <2 x i32>, <2 x i32>) nounwind readnone - -define <8 x i8> @vabd_combine_s8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vabd_combine_s8: -;CHECK: vaba.s8 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B - %tmp3 = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) - %tmp4 = add <8 x i8> %tmp2, %tmp3 - ret <8 x i8> %tmp4 + %tmp4 = call <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32> %tmp2, <2 x i32> %tmp3) + %tmp5 = zext <2 x i32> %tmp4 to <2 x i64> + %tmp6 = add <2 x i64> %tmp1, %tmp5 + ret <2 x i64> %tmp6 } - -define <4 x i16> @vabd_combine_u16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vabd_combine_u16: -;CHECK: vaba.u16 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B - %tmp3 = call <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) - %tmp4 = add <4 x i16> %tmp3, %tmp1 - ret <4 x i16> %tmp4 -} - -declare <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8>, <8 x i8>) nounwind readnone -declare <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone - Modified: llvm/trunk/test/CodeGen/ARM/vabd.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vabd.ll?rev=112941&r1=112940&r2=112941&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vabd.ll (original) +++ llvm/trunk/test/CodeGen/ARM/vabd.ll Thu Sep 2 20:35:08 2010 @@ -151,8 +151,9 @@ ;CHECK: vabdl.s8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B - %tmp3 = call <8 x i16> @llvm.arm.neon.vabdls.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2) - ret <8 x i16> %tmp3 + %tmp3 = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) + %tmp4 = zext <8 x i8> %tmp3 to <8 x i16> + ret <8 x i16> %tmp4 } define <4 x i32> @vabdls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { @@ -160,8 +161,9 @@ ;CHECK: vabdl.s16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B - %tmp3 = call <4 x i32> @llvm.arm.neon.vabdls.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2) - ret <4 x i32> %tmp3 + %tmp3 = call <4 x i16> @llvm.arm.neon.vabds.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) + %tmp4 = zext <4 x i16> %tmp3 to <4 x i32> + ret <4 x i32> %tmp4 } define <2 x i64> @vabdls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { @@ -169,8 +171,9 @@ ;CHECK: vabdl.s32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B - %tmp3 = call <2 x i64> @llvm.arm.neon.vabdls.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2) - ret <2 x i64> %tmp3 + %tmp3 = call <2 x i32> @llvm.arm.neon.vabds.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) + %tmp4 = zext <2 x i32> %tmp3 to <2 x i64> + ret <2 x i64> %tmp4 } define <8 x i16> @vabdlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { @@ -178,8 +181,9 @@ ;CHECK: vabdl.u8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B - %tmp3 = call <8 x i16> @llvm.arm.neon.vabdlu.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2) - ret <8 x i16> %tmp3 + %tmp3 = call <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) + %tmp4 = zext <8 x i8> %tmp3 to <8 x i16> + ret <8 x i16> %tmp4 } define <4 x i32> @vabdlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { @@ -187,8 +191,9 @@ ;CHECK: vabdl.u16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B - %tmp3 = call <4 x i32> @llvm.arm.neon.vabdlu.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2) - ret <4 x i32> %tmp3 + %tmp3 = call <4 x i16> @llvm.arm.neon.vabdu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) + %tmp4 = zext <4 x i16> %tmp3 to <4 x i32> + ret <4 x i32> %tmp4 } define <2 x i64> @vabdlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { @@ -196,14 +201,7 @@ ;CHECK: vabdl.u32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B - %tmp3 = call <2 x i64> @llvm.arm.neon.vabdlu.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2) - ret <2 x i64> %tmp3 + %tmp3 = call <2 x i32> @llvm.arm.neon.vabdu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) + %tmp4 = zext <2 x i32> %tmp3 to <2 x i64> + ret <2 x i64> %tmp4 } - -declare <8 x i16> @llvm.arm.neon.vabdls.v8i16(<8 x i8>, <8 x i8>) nounwind readnone -declare <4 x i32> @llvm.arm.neon.vabdls.v4i32(<4 x i16>, <4 x i16>) nounwind readnone -declare <2 x i64> @llvm.arm.neon.vabdls.v2i64(<2 x i32>, <2 x i32>) nounwind readnone - -declare <8 x i16> @llvm.arm.neon.vabdlu.v8i16(<8 x i8>, <8 x i8>) nounwind readnone -declare <4 x i32> @llvm.arm.neon.vabdlu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone -declare <2 x i64> @llvm.arm.neon.vabdlu.v2i64(<2 x i32>, <2 x i32>) nounwind readnone From bruno.cardoso at gmail.com Thu Sep 2 20:39:08 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Fri, 03 Sep 2010 01:39:08 -0000 Subject: [llvm-commits] [llvm] r112942 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20100903013908.A24BE2A6C12C@llvm.org> Author: bruno Date: Thu Sep 2 20:39:08 2010 New Revision: 112942 URL: http://llvm.org/viewvc/llvm-project?rev=112942&view=rev Log: Use punpckh and unpckh family of nodes instead of using unpckh mask pattern fragment Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=112942&r1=112941&r2=112942&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Sep 2 20:39:08 2010 @@ -2609,9 +2609,11 @@ case X86ISD::PUNPCKLDQ: case X86ISD::PUNPCKLQDQ: case X86ISD::UNPCKHPS: + case X86ISD::UNPCKHPD: case X86ISD::PUNPCKHWD: case X86ISD::PUNPCKHBW: case X86ISD::PUNPCKHDQ: + case X86ISD::PUNPCKHQDQ: return true; } return false; @@ -2672,9 +2674,11 @@ case X86ISD::PUNPCKLDQ: case X86ISD::PUNPCKLQDQ: case X86ISD::UNPCKHPS: + case X86ISD::UNPCKHPD: case X86ISD::PUNPCKHWD: case X86ISD::PUNPCKHBW: case X86ISD::PUNPCKHDQ: + case X86ISD::PUNPCKHQDQ: return DAG.getNode(Opc, dl, VT, V1, V2); } return SDValue(); @@ -5223,6 +5227,20 @@ return 0; } +static unsigned getUNPCKHOpcode(EVT VT) { + switch(VT.getSimpleVT().SimpleTy) { + case MVT::v4i32: return X86ISD::PUNPCKHDQ; + case MVT::v2i64: return X86ISD::PUNPCKHQDQ; + case MVT::v4f32: return X86ISD::UNPCKHPS; + case MVT::v2f64: return X86ISD::UNPCKHPD; + case MVT::v16i8: return X86ISD::PUNPCKHBW; + case MVT::v8i16: return X86ISD::PUNPCKHWD; + default: + llvm_unreachable("Unknow type for unpckh"); + } + return 0; +} + SDValue X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { ShuffleVectorSDNode *SVOp = cast(Op); @@ -5413,7 +5431,8 @@ Op : getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V2, DAG); if (X86::isUNPCKHMask(SVOp)) - return Op; + return (isMMX) ? + Op : getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V2, DAG); if (V2IsSplat) { // Normalize mask so all entries that point to V2 points to its first @@ -5438,10 +5457,11 @@ if (X86::isUNPCKLMask(NewSVOp)) return (isMMX) ? - Op : getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V2, V1, DAG); + NewOp : getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V2, V1, DAG); if (X86::isUNPCKHMask(NewSVOp)) - return NewOp; + return (isMMX) ? + NewOp : getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V2, V1, DAG); } // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle. From bruno.cardoso at gmail.com Thu Sep 2 21:08:46 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Fri, 03 Sep 2010 02:08:46 -0000 Subject: [llvm-commits] [llvm] r112944 - in /llvm/trunk: lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/avx-intrinsics-x86.ll Message-ID: <20100903020846.3EC122A6C12C@llvm.org> Author: bruno Date: Thu Sep 2 21:08:45 2010 New Revision: 112944 URL: http://llvm.org/viewvc/llvm-project?rev=112944&view=rev Log: AVX doesn't support mm operations neither its instrinsics. The AVX versions of PALIGN and PABS* should only exist for 128-bit. Remove the unnecessary stuff. Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=112944&r1=112943&r2=112944&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Sep 2 21:08:45 2010 @@ -3532,10 +3532,9 @@ // SSSE3 - Packed Absolute Instructions //===---------------------------------------------------------------------===// -/// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}. -multiclass SS3I_unop_rm_int opc, string OpcodeStr, - PatFrag mem_frag64, PatFrag mem_frag128, - Intrinsic IntId64, Intrinsic IntId128> { +/// SS3I_unop_rm_int_mm - Simple SSSE3 unary whose type can be v*{i8,i16,i32}. +multiclass SS3I_unop_rm_int_mm opc, string OpcodeStr, + PatFrag mem_frag64, Intrinsic IntId64> { def rr64 : SS38I; @@ -3544,7 +3543,11 @@ !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [(set VR64:$dst, (IntId64 (bitconvert (mem_frag64 addr:$src))))]>; +} +/// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}. +multiclass SS3I_unop_rm_int opc, string OpcodeStr, + PatFrag mem_frag128, Intrinsic IntId128> { def rr128 : SS38I, VEX; - defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", memopv4i16, memopv8i16, - int_x86_ssse3_pabs_w, + defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", memopv8i16, int_x86_ssse3_pabs_w_128>, VEX; - defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", memopv2i32, memopv4i32, - int_x86_ssse3_pabs_d, + defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", memopv4i32, int_x86_ssse3_pabs_d_128>, VEX; } -defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", memopv8i8, memopv16i8, - int_x86_ssse3_pabs_b, - int_x86_ssse3_pabs_b_128>; -defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", memopv4i16, memopv8i16, - int_x86_ssse3_pabs_w, - int_x86_ssse3_pabs_w_128>; -defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", memopv2i32, memopv4i32, - int_x86_ssse3_pabs_d, - int_x86_ssse3_pabs_d_128>; +defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", memopv16i8, + int_x86_ssse3_pabs_b_128>, + SS3I_unop_rm_int_mm<0x1C, "pabsb", memopv8i8, + int_x86_ssse3_pabs_b>; + +defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", memopv8i16, + int_x86_ssse3_pabs_w_128>, + SS3I_unop_rm_int_mm<0x1D, "pabsw", memopv4i16, + int_x86_ssse3_pabs_w>; + +defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", memopv4i32, + int_x86_ssse3_pabs_d_128>, + SS3I_unop_rm_int_mm<0x1E, "pabsd", memopv2i32, + int_x86_ssse3_pabs_d>; //===---------------------------------------------------------------------===// // SSSE3 - Packed Binary Operator Instructions @@ -3716,22 +3721,16 @@ // SSSE3 - Packed Align Instruction Patterns //===---------------------------------------------------------------------===// -multiclass sse3_palign { +multiclass ssse3_palign_mm { def R64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2, i8imm:$src3), - !if(Is2Addr, - !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), - !strconcat(asm, - "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")), - []>; + !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>; def R64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2, i8imm:$src3), - !if(Is2Addr, - !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), - !strconcat(asm, - "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")), - []>; + !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>; +} +multiclass ssse3_palign { def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3), !if(Is2Addr, @@ -3749,9 +3748,10 @@ } let isAsmParserOnly = 1, Predicates = [HasAVX] in - defm VPALIGN : sse3_palign<"vpalignr", 0>, VEX_4V; + defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V; let Constraints = "$src1 = $dst" in - defm PALIGN : sse3_palign<"palignr">; + defm PALIGN : ssse3_palign<"palignr">, + ssse3_palign_mm<"palignr">; let AddedComplexity = 5 in { Modified: llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll?rev=112944&r1=112943&r2=112944&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll (original) +++ llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll Thu Sep 2 21:08:45 2010 @@ -1715,14 +1715,6 @@ declare i32 @llvm.x86.sse.ucomineq.ss(<4 x float>, <4 x float>) nounwind readnone -define <8 x i8> @test_x86_ssse3_pabs_b(<8 x i8> %a0) { - ; CHECK: vpabsb - %res = call <8 x i8> @llvm.x86.ssse3.pabs.b(<8 x i8> %a0) ; <<8 x i8>> [#uses=1] - ret <8 x i8> %res -} -declare <8 x i8> @llvm.x86.ssse3.pabs.b(<8 x i8>) nounwind readnone - - define <16 x i8> @test_x86_ssse3_pabs_b_128(<16 x i8> %a0) { ; CHECK: vpabsb %res = call <16 x i8> @llvm.x86.ssse3.pabs.b.128(<16 x i8> %a0) ; <<16 x i8>> [#uses=1] @@ -1731,14 +1723,6 @@ declare <16 x i8> @llvm.x86.ssse3.pabs.b.128(<16 x i8>) nounwind readnone -define <2 x i32> @test_x86_ssse3_pabs_d(<2 x i32> %a0) { - ; CHECK: vpabsd - %res = call <2 x i32> @llvm.x86.ssse3.pabs.d(<2 x i32> %a0) ; <<2 x i32>> [#uses=1] - ret <2 x i32> %res -} -declare <2 x i32> @llvm.x86.ssse3.pabs.d(<2 x i32>) nounwind readnone - - define <4 x i32> @test_x86_ssse3_pabs_d_128(<4 x i32> %a0) { ; CHECK: vpabsd %res = call <4 x i32> @llvm.x86.ssse3.pabs.d.128(<4 x i32> %a0) ; <<4 x i32>> [#uses=1] @@ -1747,14 +1731,6 @@ declare <4 x i32> @llvm.x86.ssse3.pabs.d.128(<4 x i32>) nounwind readnone -define <4 x i16> @test_x86_ssse3_pabs_w(<4 x i16> %a0) { - ; CHECK: vpabsw - %res = call <4 x i16> @llvm.x86.ssse3.pabs.w(<4 x i16> %a0) ; <<4 x i16>> [#uses=1] - ret <4 x i16> %res -} -declare <4 x i16> @llvm.x86.ssse3.pabs.w(<4 x i16>) nounwind readnone - - define <8 x i16> @test_x86_ssse3_pabs_w_128(<8 x i16> %a0) { ; CHECK: vpabsw %res = call <8 x i16> @llvm.x86.ssse3.pabs.w.128(<8 x i16> %a0) ; <<8 x i16>> [#uses=1] From ofv at wanadoo.es Thu Sep 2 21:22:23 2010 From: ofv at wanadoo.es (Oscar Fuentes) Date: Fri, 03 Sep 2010 02:22:23 -0000 Subject: [llvm-commits] [llvm] r112946 - /llvm/trunk/cmake/config-ix.cmake Message-ID: <20100903022223.880362A6C12C@llvm.org> Author: ofv Date: Thu Sep 2 21:22:23 2010 New Revision: 112946 URL: http://llvm.org/viewvc/llvm-project?rev=112946&view=rev Log: Fix cmake build without native target selected. The cmake (+ MSVC) build is broken if you don't select your native target. e.g. 'cmake -D LLVM_TARGETS_TO_BUILD="MyNonNativeTarget" .' This is because cmake currently sets the LLVM_NATIVE_* definitions regardless of whether the native target is selected (causing build errors). Patch by Mike Gist! Modified: llvm/trunk/cmake/config-ix.cmake Modified: llvm/trunk/cmake/config-ix.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/config-ix.cmake?rev=112946&r1=112945&r2=112946&view=diff ============================================================================== --- llvm/trunk/cmake/config-ix.cmake (original) +++ llvm/trunk/cmake/config-ix.cmake Thu Sep 2 21:22:23 2010 @@ -207,9 +207,6 @@ endif () if (LLVM_NATIVE_ARCH) - set(LLVM_NATIVE_TARGET LLVMInitialize${LLVM_NATIVE_ARCH}Target) - set(LLVM_NATIVE_TARGETINFO LLVMInitialize${LLVM_NATIVE_ARCH}TargetInfo) - set(LLVM_NATIVE_ASMPRINTER LLVMInitialize${LLVM_NATIVE_ARCH}AsmPrinter) list(FIND LLVM_TARGETS_TO_BUILD ${LLVM_NATIVE_ARCH} NATIVE_ARCH_IDX) if (NATIVE_ARCH_IDX EQUAL -1) message(STATUS @@ -217,6 +214,9 @@ set(LLVM_NATIVE_ARCH) else () message(STATUS "Native target architecture is ${LLVM_NATIVE_ARCH}") + set(LLVM_NATIVE_TARGET LLVMInitialize${LLVM_NATIVE_ARCH}Target) + set(LLVM_NATIVE_TARGETINFO LLVMInitialize${LLVM_NATIVE_ARCH}TargetInfo) + set(LLVM_NATIVE_ASMPRINTER LLVMInitialize${LLVM_NATIVE_ARCH}AsmPrinter) endif () endif() From ofv at wanadoo.es Thu Sep 2 21:24:14 2010 From: ofv at wanadoo.es (=?utf-8?Q?=C3=93scar_Fuentes?=) Date: Fri, 03 Sep 2010 04:24:14 +0200 Subject: [llvm-commits] [PATCH] Fix cmake build without native target selected References: <98860CD172CEBA47AC403E1E6D93F842104762@klmail.kl.imgtec.org> <98860CD172CEBA47AC403E1E6D93F842104763@klmail.kl.imgtec.org> Message-ID: <87sk1rsgxd.fsf@telefonica.net> "Mike Gist" writes: [snip] > The attached patch fixes this problem by only setting them when the > native target is selected, which is consistent with the behaviour of > configure. Applied. Thanks! From grosbach at apple.com Thu Sep 2 21:32:11 2010 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 2 Sep 2010 19:32:11 -0700 Subject: [llvm-commits] [llvm] r112924 - in /llvm/trunk/utils/TableGen: DAGISelEmitter.cpp DAGISelEmitter.h In-Reply-To: <20100903003950.BD1402A6C12C@llvm.org> References: <20100903003950.BD1402A6C12C@llvm.org> Message-ID: <45D4C9B3-3260-4EE1-97C1-656E76597220@apple.com> Woot! Very nice. On Sep 2, 2010, at 5:39 PM, Jakob Stoklund Olesen wrote: > Author: stoklund > Date: Thu Sep 2 19:39:50 2010 > New Revision: 112924 > > URL: http://llvm.org/viewvc/llvm-project?rev=112924&view=rev > Log: > Stop emitting predicate functions. They are no longer used. > > Modified: > llvm/trunk/utils/TableGen/DAGISelEmitter.cpp > llvm/trunk/utils/TableGen/DAGISelEmitter.h > > Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.cpp?rev=112924&r1=112923&r2=112924&view=diff > ============================================================================== > --- llvm/trunk/utils/TableGen/DAGISelEmitter.cpp (original) > +++ llvm/trunk/utils/TableGen/DAGISelEmitter.cpp Thu Sep 2 19:39:50 2010 > @@ -57,51 +57,6 @@ > return Cost; > } > > -//===----------------------------------------------------------------------===// > -// Predicate emitter implementation. > -// > - > -void DAGISelEmitter::EmitPredicateFunctions(raw_ostream &OS) { > - OS << "\n// Predicate functions.\n"; > - > - // Walk the pattern fragments, adding them to a map, which sorts them by > - // name. > - typedef std::map > PFsByNameTy; > - PFsByNameTy PFsByName; > - > - for (CodeGenDAGPatterns::pf_iterator I = CGP.pf_begin(), E = CGP.pf_end(); > - I != E; ++I) > - PFsByName.insert(std::make_pair(I->first->getName(), *I)); > - > - > - for (PFsByNameTy::iterator I = PFsByName.begin(), E = PFsByName.end(); > - I != E; ++I) { > - Record *PatFragRecord = I->second.first;// Record that derives from PatFrag. > - TreePattern *P = I->second.second; > - > - // If there is a code init for this fragment, emit the predicate code. > - std::string Code = PatFragRecord->getValueAsCode("Predicate"); > - if (Code.empty()) continue; > - > - if (P->getOnlyTree()->isLeaf()) > - OS << "inline bool Predicate_" << PatFragRecord->getName() > - << "(SDNode *N) const {\n"; > - else { > - std::string ClassName = > - CGP.getSDNodeInfo(P->getOnlyTree()->getOperator()).getSDClassName(); > - const char *C2 = ClassName == "SDNode" ? "N" : "inN"; > - > - OS << "inline bool Predicate_" << PatFragRecord->getName() > - << "(SDNode *" << C2 << ") const {\n"; > - if (ClassName != "SDNode") > - OS << " " << ClassName << " *N = cast<" << ClassName << ">(inN);\n"; > - } > - OS << Code << "\n}\n"; > - } > - > - OS << "\n\n"; > -} > - > namespace { > // PatternSortingPredicate - return true if we prefer to match LHS before RHS. > // In particular, we want to match maximal patterns first and lowest cost within > @@ -168,9 +123,6 @@ > errs() << "\n"; > }); > > - // FIXME: These are being used by hand written code, gross. > - EmitPredicateFunctions(OS); > - > // Add all the patterns to a temporary list so we can sort them. > std::vector Patterns; > for (CodeGenDAGPatterns::ptm_iterator I = CGP.ptm_begin(), E = CGP.ptm_end(); > > Modified: llvm/trunk/utils/TableGen/DAGISelEmitter.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelEmitter.h?rev=112924&r1=112923&r2=112924&view=diff > ============================================================================== > --- llvm/trunk/utils/TableGen/DAGISelEmitter.h (original) > +++ llvm/trunk/utils/TableGen/DAGISelEmitter.h Thu Sep 2 19:39:50 2010 > @@ -31,8 +31,6 @@ > > // run - Output the isel, returning true on failure. > void run(raw_ostream &OS); > -private: > - void EmitPredicateFunctions(raw_ostream &OS); > }; > > } // End llvm namespace > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From geek4civic at gmail.com Thu Sep 2 22:12:24 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Fri, 3 Sep 2010 12:12:24 +0900 Subject: [llvm-commits] [llvm] r112888 - /llvm/trunk/lib/Support/SystemUtils.cpp In-Reply-To: <20100902223238.3DFB62A6C12C@llvm.org> References: <20100902223238.3DFB62A6C12C@llvm.org> Message-ID: Dan, Thank you! 2010/9/3 Dan Gohman : > + ? ?// If the path is absolute (and it usually is), call FindProgramByName to > + ? ?// allow it to try platform-specific logic, such as appending a .exe suffix > + ? ?// on Windows. Don't do this if we somehow have a relative path, because > + ? ?// we don't want to go searching the PATH and accidentally find an unrelated > + ? ?// version of the program. cool! ...Takumi From geek4civic at gmail.com Thu Sep 2 22:24:08 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Fri, 03 Sep 2010 03:24:08 -0000 Subject: [llvm-commits] [llvm] r112947 - in /llvm/trunk/test/CodeGen/X86: 2009-03-13-PHIElimBug.ll 2009-03-16-PHIElimInLPad.ll dyn-stackalloc.ll Message-ID: <20100903032408.F000E2A6C12C@llvm.org> Author: chapuni Date: Thu Sep 2 22:24:08 2010 New Revision: 112947 URL: http://llvm.org/viewvc/llvm-project?rev=112947&view=rev Log: test/CodeGen/X86: Add explicit -mtriple=(i686|x86_64)-linux for Win32 host. Modified: llvm/trunk/test/CodeGen/X86/2009-03-13-PHIElimBug.ll llvm/trunk/test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll llvm/trunk/test/CodeGen/X86/dyn-stackalloc.ll Modified: llvm/trunk/test/CodeGen/X86/2009-03-13-PHIElimBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-03-13-PHIElimBug.ll?rev=112947&r1=112946&r2=112947&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2009-03-13-PHIElimBug.ll (original) +++ llvm/trunk/test/CodeGen/X86/2009-03-13-PHIElimBug.ll Thu Sep 2 22:24:08 2010 @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 | FileCheck %s +; RUN: llc < %s -mtriple=i686-linux | FileCheck %s ; Check the register copy comes after the call to f and before the call to g ; PR3784 Modified: llvm/trunk/test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll?rev=112947&r1=112946&r2=112947&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll (original) +++ llvm/trunk/test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll Thu Sep 2 22:24:08 2010 @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -asm-verbose | FileCheck %s +; RUN: llc < %s -mtriple=i686-linux -asm-verbose | FileCheck %s ; Check that register copies in the landing pad come after the EH_LABEL declare i32 @f() Modified: llvm/trunk/test/CodeGen/X86/dyn-stackalloc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dyn-stackalloc.ll?rev=112947&r1=112946&r2=112947&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/dyn-stackalloc.ll (original) +++ llvm/trunk/test/CodeGen/X86/dyn-stackalloc.ll Thu Sep 2 22:24:08 2010 @@ -1,6 +1,6 @@ -; RUN: llc < %s -march=x86 | not egrep {\\\$4294967289|-7} -; RUN: llc < %s -march=x86 | egrep {\\\$4294967280|-16} -; RUN: llc < %s -march=x86-64 | grep {\\-16} +; RUN: llc < %s -mtriple=i686-linux | not egrep {\\\$4294967289|-7} +; RUN: llc < %s -mtriple=i686-linux | egrep {\\\$4294967280|-16} +; RUN: llc < %s -mtriple=x86_64-linux | grep {\\-16} define void @t() nounwind { A: From geek4civic at gmail.com Thu Sep 2 22:27:36 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Fri, 3 Sep 2010 12:27:36 +0900 Subject: [llvm-commits] [PATCH] test/CodeGen/X86 patches for win32 In-Reply-To: References: <0C45983F-0D48-4990-8170-1E69E7CB2D41@apple.com> Message-ID: Commited in r112947. This also fixes PR6892. http://llvm.org/bugs/show_bug.cgi?id=6892 X86 test failures on Cygwin 1.7 ...Takumi 2010/9/2 NAKAMURA Takumi : > Anton, > > Thank you comments. I understand, > "Tests should be funcionality test, not environment test." > >> test/CodeGen/X86/2009-03-13-PHIElimBug.ll >> test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll >> test/CodeGen/X86/dyn-stackalloc.ll > > I will commit 3 of them tonight, with -mtriple=(i686|x86_64)-linux > >> Also, it's not obvious why you need to change >> test/CodeGen/X86/twoaddr-coalesce.ll > > I thought this test would not require to be @main. > > In fact, (a part) difference among @foo(-) and @main(+) is below on > cygwin and mingw; > > -_foo: > +_main: > ?# BB#0: > + ? ? ? pushl ? %ebp > + ? ? ? movl ? ?%esp, %ebp > ? ? ? ?pushl ? %ebx > - ? ? ? subl ? ?$8, %esp > + ? ? ? subl ? ?$12, %esp > + ? ? ? call ? ?___main > > With -mtriple=i686-linux, they are almost same. > > ps. Thanks to Duncan, to give me several advices about triplet on the irc today. > > > Sleepy Thursday...Takumi > From dirty at apple.com Thu Sep 2 22:42:31 2010 From: dirty at apple.com (Cameron Esfahani) Date: Thu, 2 Sep 2010 20:42:31 -0700 Subject: [llvm-commits] [PATCH] Win64 var arg support In-Reply-To: References: Message-ID: This is required for the var arg support. Without this change, there's no way to know how far the home register space allocated by the caller is from the top of the stack. Any fixed object created via MFI is put at it's offset after the frame info stuff is calculated. So, if you wanted to put something into the caller's frame, it's pretty difficult. On Sep 2, 2010, at 4:13 PM, Anton Korobeynikov wrote: > Hello, Cameron > >> Here's the corresponding llvm changes to support the Win64 ABI version of var args. With a test case! > This hunk seems to be unrelated to the patch and in wrong in general: > - (Subtarget.isTargetWin64() ? -40 : > - (Subtarget.is64Bit() ? -8 : -4))), > + (Subtarget.is64Bit() ? -8 : -4)), > Why do you need it? > > -- > With best regards, Anton Korobeynikov > Faculty of Mathematics and Mechanics, Saint Petersburg State University Cameron Esfahani dirty at apple.com "You only live once, and the way I live, once is enough" Frank Sinatra From sabre at nondot.org Thu Sep 2 23:01:35 2010 From: sabre at nondot.org (Chris Lattner) Date: Thu, 2 Sep 2010 21:01:35 -0700 Subject: [llvm-commits] [llvm] r112899 - /llvm/trunk/lib/VMCore/AsmWriter.cpp In-Reply-To: References: <20100902225210.40BDA2A6C12C@llvm.org> Message-ID: On Sep 2, 2010, at 5:47 PM, Jakob Stoklund Olesen wrote: > > On Sep 2, 2010, at 3:52 PM, Chris Lattner wrote: > >> going further, remove the " [#uses=3]" comments entirely. They >> add a lot of noise, confuse people about what the IR is, and don't add >> any particular value. When the types are long it makes it really really >> hard to read IR. > > Nice! This cleans up .ll files pretty well. > > There are still predicate comments on each basic block, but they are often useful. Yeah, I think the predecessor info is still useful, -Chris From resistor at mac.com Thu Sep 2 23:16:29 2010 From: resistor at mac.com (Owen Anderson) Date: Fri, 03 Sep 2010 04:16:29 -0000 Subject: [llvm-commits] [llvm] r112948 - /llvm/trunk/include/llvm/Support/StandardPasses.h Message-ID: <20100903041629.2381B2A6C12C@llvm.org> Author: resistor Date: Thu Sep 2 23:16:28 2010 New Revision: 112948 URL: http://llvm.org/viewvc/llvm-project?rev=112948&view=rev Log: Re-enable CorrelatedValuePropagation. I've tested nightly tests, llvm-gcc bootstrap, and clang self-host. Modified: llvm/trunk/include/llvm/Support/StandardPasses.h Modified: llvm/trunk/include/llvm/Support/StandardPasses.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/StandardPasses.h?rev=112948&r1=112947&r2=112948&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/StandardPasses.h (original) +++ llvm/trunk/include/llvm/Support/StandardPasses.h Thu Sep 2 23:16:28 2010 @@ -122,6 +122,7 @@ PM->add(createSimplifyLibCallsPass()); // Library Call Optimizations PM->add(createInstructionCombiningPass()); // Cleanup for scalarrepl. PM->add(createJumpThreadingPass()); // Thread jumps. + PM->add(createCorrelatedValuePropagationPass()); // Propagate conditionals PM->add(createCFGSimplificationPass()); // Merge & remove BBs PM->add(createInstructionCombiningPass()); // Combine silly seq's @@ -146,6 +147,7 @@ // opened up by them. PM->add(createInstructionCombiningPass()); PM->add(createJumpThreadingPass()); // Thread jumps + PM->add(createCorrelatedValuePropagationPass()); PM->add(createDeadStoreEliminationPass()); // Delete dead stores PM->add(createAggressiveDCEPass()); // Delete dead instructions PM->add(createCFGSimplificationPass()); // Merge & remove BBs From asl at math.spbu.ru Fri Sep 3 00:38:01 2010 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Fri, 3 Sep 2010 09:38:01 +0400 Subject: [llvm-commits] [PATCH] Win64 var arg support In-Reply-To: References: Message-ID: Hello, Cameron On Fri, Sep 3, 2010 at 07:42, Cameron Esfahani wrote: > This is required for the var arg support. ?Without this change, there's no way to know how far the home register space allocated by the caller is from the top of the stack. ?Any fixed object created via MFI is put at it's offset after the frame info stuff is calculated. ?So, if you wanted to put something into the caller's frame, it's pretty difficult. Ok. However, this way you break everything passed normal way. Make sure that "make check" passes with your patch. Right now it doesn't. -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From baldrick at free.fr Fri Sep 3 03:31:49 2010 From: baldrick at free.fr (Duncan Sands) Date: Fri, 03 Sep 2010 08:31:49 -0000 Subject: [llvm-commits] [llvm] r112952 - /llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp Message-ID: <20100903083149.1A3A42A6C12E@llvm.org> Author: baldrick Date: Fri Sep 3 03:31:48 2010 New Revision: 112952 URL: http://llvm.org/viewvc/llvm-project?rev=112952&view=rev Log: Reapply commit 112702 which was speculatively reverted by echristo. Original commit message: Use the SSAUpdator to turn calls to eh.exception that are not in a landing pad into uses of registers rather than loads from a stack slot. Doesn't touch the 'orrible hack code - Bill needs to persuade me harder :) Modified: llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp Modified: llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp?rev=112952&r1=112951&r2=112952&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp (original) +++ llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp Fri Sep 3 03:31:48 2010 @@ -25,12 +25,12 @@ #include "llvm/Support/CallSite.h" #include "llvm/Target/TargetLowering.h" #include "llvm/Transforms/Utils/BasicBlockUtils.h" +#include "llvm/Transforms/Utils/SSAUpdater.h" using namespace llvm; STATISTIC(NumLandingPadsSplit, "Number of landing pads split"); STATISTIC(NumUnwindsLowered, "Number of unwind instructions lowered"); STATISTIC(NumExceptionValuesMoved, "Number of eh.exception calls moved"); -STATISTIC(NumStackTempsIntroduced, "Number of stack temporaries introduced"); namespace { class DwarfEHPrepare : public FunctionPass { @@ -62,24 +62,11 @@ typedef SmallPtrSet BBSet; BBSet LandingPads; - // Stack temporary used to hold eh.exception values. - AllocaInst *ExceptionValueVar; - bool NormalizeLandingPads(); bool LowerUnwinds(); bool MoveExceptionValueCalls(); - bool FinishStackTemporaries(); Instruction *CreateExceptionValueCall(BasicBlock *BB); - Instruction *CreateValueLoad(BasicBlock *BB); - - /// CreateReadOfExceptionValue - Return the result of the eh.exception - /// intrinsic by calling the intrinsic if in a landing pad, or loading it - /// from the exception value variable otherwise. - Instruction *CreateReadOfExceptionValue(BasicBlock *BB) { - return LandingPads.count(BB) ? - CreateExceptionValueCall(BB) : CreateValueLoad(BB); - } /// CleanupSelectors - Any remaining eh.selector intrinsic calls which still /// use the "llvm.eh.catch.all.value" call need to convert to using its @@ -117,7 +104,7 @@ virtual bool runOnFunction(Function &Fn); - // getAnalysisUsage - We need dominance frontiers for memory promotion. + // getAnalysisUsage - We need the dominator tree for handling URoR. virtual void getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired(); AU.addPreserved(); @@ -517,7 +504,7 @@ // Create the call... CallInst *CI = CallInst::Create(RewindFunction, - CreateReadOfExceptionValue(TI->getParent()), + CreateExceptionValueCall(TI->getParent()), "", TI); CI->setCallingConv(TLI->getLibcallCallingConv(RTLIB::UNWIND_RESUME)); // ...followed by an UnreachableInst. @@ -533,9 +520,11 @@ } /// MoveExceptionValueCalls - Ensure that eh.exception is only ever called from -/// landing pads by replacing calls outside of landing pads with loads from a -/// stack temporary. Move eh.exception calls inside landing pads to the start -/// of the landing pad (optional, but may make things simpler for later passes). +/// landing pads by replacing calls outside of landing pads with direct use of +/// a register holding the appropriate value; this requires adding calls inside +/// all landing pads to initialize the register. Also, move eh.exception calls +/// inside landing pads to the start of the landing pad (optional, but may make +/// things simpler for later passes). bool DwarfEHPrepare::MoveExceptionValueCalls() { // If the eh.exception intrinsic is not declared in the module then there is // nothing to do. Speed up compilation by checking for this common case. @@ -545,49 +534,87 @@ bool Changed = false; - for (Function::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) { - for (BasicBlock::iterator II = BB->begin(), E = BB->end(); II != E;) - if (IntrinsicInst *CI = dyn_cast(II++)) - if (CI->getIntrinsicID() == Intrinsic::eh_exception) { - if (!CI->use_empty()) { - Value *ExceptionValue = CreateReadOfExceptionValue(BB); - if (CI == ExceptionValue) { - // The call was at the start of a landing pad - leave it alone. - assert(LandingPads.count(BB) && - "Created eh.exception call outside landing pad!"); - continue; - } - CI->replaceAllUsesWith(ExceptionValue); - } - CI->eraseFromParent(); - ++NumExceptionValuesMoved; - Changed = true; + // Move calls to eh.exception that are inside a landing pad to the start of + // the landing pad. + for (BBSet::const_iterator LI = LandingPads.begin(), LE = LandingPads.end(); + LI != LE; ++LI) { + BasicBlock *LP = *LI; + for (BasicBlock::iterator II = LP->getFirstNonPHIOrDbg(), IE = LP->end(); + II != IE;) + if (EHExceptionInst *EI = dyn_cast(II++)) { + // Found a call to eh.exception. + if (!EI->use_empty()) { + // If there is already a call to eh.exception at the start of the + // landing pad, then get hold of it; otherwise create such a call. + Value *CallAtStart = CreateExceptionValueCall(LP); + + // If the call was at the start of a landing pad then leave it alone. + if (EI == CallAtStart) + continue; + EI->replaceAllUsesWith(CallAtStart); } + EI->eraseFromParent(); + ++NumExceptionValuesMoved; + Changed = true; + } } - return Changed; -} + // Look for calls to eh.exception that are not in a landing pad. If one is + // found, then a register that holds the exception value will be created in + // each landing pad, and the SSAUpdater will be used to compute the values + // returned by eh.exception calls outside of landing pads. + SSAUpdater SSA; + + // Remember where we found the eh.exception call, to avoid rescanning earlier + // basic blocks which we already know contain no eh.exception calls. + bool FoundCallOutsideLandingPad = false; + Function::iterator BB = F->begin(); + for (Function::iterator BE = F->end(); BB != BE; ++BB) { + // Skip over landing pads. + if (LandingPads.count(BB)) + continue; -/// FinishStackTemporaries - If we introduced a stack variable to hold the -/// exception value then initialize it in each landing pad. -bool DwarfEHPrepare::FinishStackTemporaries() { - if (!ExceptionValueVar) - // Nothing to do. - return false; + for (BasicBlock::iterator II = BB->getFirstNonPHIOrDbg(), IE = BB->end(); + II != IE; ++II) + if (isa(II)) { + SSA.Initialize(II->getType(), II->getName()); + FoundCallOutsideLandingPad = true; + break; + } - bool Changed = false; + if (FoundCallOutsideLandingPad) + break; + } + + // If all calls to eh.exception are in landing pads then we are done. + if (!FoundCallOutsideLandingPad) + return Changed; - // Make sure that there is a store of the exception value at the start of - // each landing pad. + // Add a call to eh.exception at the start of each landing pad, and tell the + // SSAUpdater that this is the value produced by the landing pad. for (BBSet::iterator LI = LandingPads.begin(), LE = LandingPads.end(); - LI != LE; ++LI) { - Instruction *ExceptionValue = CreateReadOfExceptionValue(*LI); - Instruction *Store = new StoreInst(ExceptionValue, ExceptionValueVar); - Store->insertAfter(ExceptionValue); - Changed = true; + LI != LE; ++LI) + SSA.AddAvailableValue(*LI, CreateExceptionValueCall(*LI)); + + // Now turn all calls to eh.exception that are not in a landing pad into a use + // of the appropriate register. + for (Function::iterator BE = F->end(); BB != BE; ++BB) { + // Skip over landing pads. + if (LandingPads.count(BB)) + continue; + + for (BasicBlock::iterator II = BB->getFirstNonPHIOrDbg(), IE = BB->end(); + II != IE;) + if (EHExceptionInst *EI = dyn_cast(II++)) { + // Found a call to eh.exception, replace it with the value from any + // upstream landing pad(s). + EI->replaceAllUsesWith(SSA.GetValueAtEndOfBlock(BB)); + EI->eraseFromParent(); + ++NumExceptionValuesMoved; + } } - return Changed; + return true; } /// CreateExceptionValueCall - Insert a call to the eh.exception intrinsic at @@ -610,35 +637,11 @@ return CallInst::Create(ExceptionValueIntrinsic, "eh.value.call", Start); } -/// CreateValueLoad - Insert a load of the exception value stack variable -/// (creating it if necessary) at the start of the basic block (unless -/// there already is a load, in which case the existing load is returned). -Instruction *DwarfEHPrepare::CreateValueLoad(BasicBlock *BB) { - Instruction *Start = BB->getFirstNonPHIOrDbg(); - // Is this a load of the exception temporary? - if (ExceptionValueVar) - if (LoadInst* LI = dyn_cast(Start)) - if (LI->getPointerOperand() == ExceptionValueVar) - // Reuse the existing load. - return Start; - - // Create the temporary if we didn't already. - if (!ExceptionValueVar) { - ExceptionValueVar = new AllocaInst(PointerType::getUnqual( - Type::getInt8Ty(BB->getContext())), "eh.value", F->begin()->begin()); - ++NumStackTempsIntroduced; - } - - // Load the value. - return new LoadInst(ExceptionValueVar, "eh.value.load", Start); -} - bool DwarfEHPrepare::runOnFunction(Function &Fn) { bool Changed = false; // Initialize internal state. DT = &getAnalysis(); - ExceptionValueVar = 0; F = &Fn; // Ensure that only unwind edges end at landing pads (a landing pad is a @@ -653,11 +656,6 @@ // Move eh.exception calls to landing pads. Changed |= MoveExceptionValueCalls(); - // Initialize any stack temporaries we introduced. - Changed |= FinishStackTemporaries(); - - // TODO: Turn any stack temporaries into registers if possible. - Changed |= HandleURoRInvokes(); LandingPads.clear(); From foldr at codedgers.com Fri Sep 3 04:57:52 2010 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Fri, 03 Sep 2010 09:57:52 -0000 Subject: [llvm-commits] [llvm] r112954 - /llvm/trunk/Makefile.rules Message-ID: <20100903095752.47CD52A6C12E@llvm.org> Author: foldr Date: Fri Sep 3 04:57:52 2010 New Revision: 112954 URL: http://llvm.org/viewvc/llvm-project?rev=112954&view=rev Log: Rules for win32 ld shouldn't fire when cross-compiling. Modified: llvm/trunk/Makefile.rules Modified: llvm/trunk/Makefile.rules URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=112954&r1=112953&r2=112954&view=diff ============================================================================== --- llvm/trunk/Makefile.rules (original) +++ llvm/trunk/Makefile.rules Fri Sep 3 04:57:52 2010 @@ -972,7 +972,14 @@ endif # GNU ld Win32 accepts .DEF files that contain "DATA" entries. +# This doesn't work when cross-compiling, though. ifeq ($(HOST_OS), $(filter $(HOST_OS), Cygwin MingW)) +ifneq ($(LLVM_CROSS_COMPILING),1) +HAVE_WIN32_GNU_LD=1 +endif +endif + +ifeq ($(HAVE_WIN32_GNU_LD),1) NativeExportsFile := $(ObjDir)/$(notdir $(EXPORTED_SYMBOL_FILE:.exports=.def)) # LLVMLibsOptions is invalidated at processing tools/llvm-shlib. From baldrick at free.fr Fri Sep 3 05:33:17 2010 From: baldrick at free.fr (Duncan Sands) Date: Fri, 03 Sep 2010 12:33:17 +0200 Subject: [llvm-commits] [llvm] r112810 - in /llvm/trunk: include/llvm/Transforms/Utils/SSAUpdater.h lib/Transforms/Scalar/GVN.cpp lib/Transforms/Scalar/JumpThreading.cpp lib/Transforms/Scalar/LICM.cpp lib/Transforms/Scalar/LoopRotation.cpp lib/Transforms/Utils/LCSSA.cpp lib/Transforms/Utils/SSAUpdater.cpp In-Reply-To: References: <20100902081403.AA8672A6C12D@llvm.org> Message-ID: <4C80CEED.90101@free.fr> > Yeah, I meant to reapply, there's some random miscompilation causing failures. I've now reapplied the DwarfEHPrepare changes too. Ciao, Duncan. From benny.kra at googlemail.com Fri Sep 3 07:13:18 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Fri, 03 Sep 2010 12:13:18 -0000 Subject: [llvm-commits] [llvm] r112955 - in /llvm/trunk/lib/Target/CellSPU: SPUISelDAGToDAG.cpp SPUOperands.td Message-ID: <20100903121318.F0EB72A6C12E@llvm.org> Author: d0k Date: Fri Sep 3 07:13:18 2010 New Revision: 112955 URL: http://llvm.org/viewvc/llvm-project?rev=112955&view=rev Log: Zap dead code. Modified: llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp llvm/trunk/lib/Target/CellSPU/SPUOperands.td Modified: llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp?rev=112955&r1=112954&r2=112955&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp Fri Sep 3 07:13:18 2010 @@ -41,13 +41,6 @@ namespace { //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates bool - isI64IntS10Immediate(ConstantSDNode *CN) - { - return isInt<10>(CN->getSExtValue()); - } - - //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates - bool isI32IntS10Immediate(ConstantSDNode *CN) { return isInt<10>(CN->getSExtValue()); Modified: llvm/trunk/lib/Target/CellSPU/SPUOperands.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUOperands.td?rev=112955&r1=112954&r2=112955&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUOperands.td (original) +++ llvm/trunk/lib/Target/CellSPU/SPUOperands.td Fri Sep 3 07:13:18 2010 @@ -98,12 +98,6 @@ return (N->getZExtValue() <= 0xff); }]>; -// i64ImmSExt10 predicate - True if the i64 immediate fits in a 10-bit sign -// extended field. Used by RI10Form instructions like 'ldq'. -def i64ImmSExt10 : PatLeaf<(imm), [{ - return isI64IntS10Immediate(N); -}]>; - // i32ImmSExt10 predicate - True if the i32 immediate fits in a 10-bit sign // extended field. Used by RI10Form instructions like 'ldq'. def i32ImmSExt10 : PatLeaf<(imm), [{ From geek4civic at gmail.com Fri Sep 3 09:38:58 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Fri, 3 Sep 2010 23:38:58 +0900 Subject: [llvm-commits] [llvm] r112954 - /llvm/trunk/Makefile.rules In-Reply-To: <20100903095752.47CD52A6C12E@llvm.org> References: <20100903095752.47CD52A6C12E@llvm.org> Message-ID: Mikhail, Is it not GNU ld. what you use for cross build.? Please tell me, version of gcc driver and binutils you are using. We might need to let autoconf determine something. FYI, I got failed with your patch at ENABLE_SHARED=1 on mingw-cross fedora12 ppc. I had succeeded w/o the patch. $ i686-pc-mingw32-g++ --version i686-pc-mingw32-g++ (GCC) 4.4.1 20090902 (Fedora MinGW 4.4.1-3.fc12) $ i686-pc-mingw32-ld --version GNU ld (Linux/GNU Binutils) 2.19.51.0.14.20090722 ...Takumi From grosser at fim.uni-passau.de Fri Sep 3 09:53:52 2010 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Fri, 3 Sep 2010 16:53:52 +0200 Subject: [llvm-commits] [PATCH 0/3] PassManager fixes and improvements Message-ID: <1283525635-16182-1-git-send-email-grosser@fim.uni-passau.de> While working on http://llvm.org/bugs/show_bug.cgi?id=8037 I found two inconsistencies in the PassPrinter passes. I solved them and took the chance to give the PassPrinter passes more meaningful names. Furthermore I fixed the bug. OK to commit? Cheers Tobi Tobias Grosser (3): Include original pass name in the PassPrinter's name. Execute all Pass Printers even if -quiet is set. Implement requiredTransitive lib/VMCore/PassManager.cpp | 14 ++++ .../2010-09-03-RequiredTransitive.ll | 24 ++++++ tools/opt/opt.cpp | 81 +++++++++++++------- 3 files changed, 90 insertions(+), 29 deletions(-) create mode 100644 test/Analysis/ScalarEvolution/2010-09-03-RequiredTransitive.ll From grosser at fim.uni-passau.de Fri Sep 3 09:53:53 2010 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Fri, 3 Sep 2010 16:53:53 +0200 Subject: [llvm-commits] [PATCH 1/3] Include original pass name in the PassPrinter's name. In-Reply-To: <1283525635-16182-1-git-send-email-grosser@fim.uni-passau.de> References: <1283525635-16182-1-git-send-email-grosser@fim.uni-passau.de> Message-ID: <1283525635-16182-2-git-send-email-grosser@fim.uni-passau.de> --- tools/opt/opt.cpp | 46 ++++++++++++++++++++++++++++++++++++---------- 1 files changed, 36 insertions(+), 10 deletions(-) diff --git a/tools/opt/opt.cpp b/tools/opt/opt.cpp index d837185..ce92ec1 100644 --- a/tools/opt/opt.cpp +++ b/tools/opt/opt.cpp @@ -139,8 +139,13 @@ struct CallGraphSCCPassPrinter : public CallGraphSCCPass { static char ID; const PassInfo *PassToPrint; raw_ostream &Out; + std::string PassName; + CallGraphSCCPassPrinter(const PassInfo *PI, raw_ostream &out) : - CallGraphSCCPass(ID), PassToPrint(PI), Out(out) {} + CallGraphSCCPass(ID), PassToPrint(PI), Out(out) { + std::string PassToPrintName = PassToPrint->getPassName(); + PassName = "CallGraphSCCPass Printer: " + PassToPrintName; + } virtual bool runOnSCC(CallGraphSCC &SCC) { if (!Quiet) { @@ -157,7 +162,7 @@ struct CallGraphSCCPassPrinter : public CallGraphSCCPass { return false; } - virtual const char *getPassName() const { return "'Pass' Printer"; } + virtual const char *getPassName() const { return PassName.c_str(); } virtual void getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequiredID(PassToPrint->getTypeInfo()); @@ -171,8 +176,13 @@ struct ModulePassPrinter : public ModulePass { static char ID; const PassInfo *PassToPrint; raw_ostream &Out; + std::string PassName; + ModulePassPrinter(const PassInfo *PI, raw_ostream &out) - : ModulePass(ID), PassToPrint(PI), Out(out) {} + : ModulePass(ID), PassToPrint(PI), Out(out) { + std::string PassToPrintName = PassToPrint->getPassName(); + PassName = "ModulePass Printer: " + PassToPrintName; + } virtual bool runOnModule(Module &M) { if (!Quiet) { @@ -184,7 +194,7 @@ struct ModulePassPrinter : public ModulePass { return false; } - virtual const char *getPassName() const { return "'Pass' Printer"; } + virtual const char *getPassName() const { return PassName.c_str(); } virtual void getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequiredID(PassToPrint->getTypeInfo()); @@ -197,8 +207,13 @@ struct FunctionPassPrinter : public FunctionPass { const PassInfo *PassToPrint; raw_ostream &Out; static char ID; + std::string PassName; + FunctionPassPrinter(const PassInfo *PI, raw_ostream &out) - : FunctionPass(ID), PassToPrint(PI), Out(out) {} + : FunctionPass(ID), PassToPrint(PI), Out(out) { + std::string PassToPrintName = PassToPrint->getPassName(); + PassName = "FunctionPass Printer: " + PassToPrintName; + } virtual bool runOnFunction(Function &F) { if (!Quiet) { @@ -211,7 +226,7 @@ struct FunctionPassPrinter : public FunctionPass { return false; } - virtual const char *getPassName() const { return "FunctionPass Printer"; } + virtual const char *getPassName() const { return PassName.c_str(); } virtual void getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequiredID(PassToPrint->getTypeInfo()); @@ -225,8 +240,14 @@ struct LoopPassPrinter : public LoopPass { static char ID; const PassInfo *PassToPrint; raw_ostream &Out; + std::string PassName; + LoopPassPrinter(const PassInfo *PI, raw_ostream &out) : - LoopPass(ID), PassToPrint(PI), Out(out) {} + LoopPass(ID), PassToPrint(PI), Out(out) { + std::string PassToPrintName = PassToPrint->getPassName(); + PassName = "LoopPass Printer: " + PassToPrintName; + } + virtual bool runOnLoop(Loop *L, LPPassManager &LPM) { if (!Quiet) { @@ -238,7 +259,7 @@ struct LoopPassPrinter : public LoopPass { return false; } - virtual const char *getPassName() const { return "'Pass' Printer"; } + virtual const char *getPassName() const { return PassName.c_str(); } virtual void getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequiredID(PassToPrint->getTypeInfo()); @@ -252,8 +273,13 @@ struct BasicBlockPassPrinter : public BasicBlockPass { const PassInfo *PassToPrint; raw_ostream &Out; static char ID; + std::string PassName; + BasicBlockPassPrinter(const PassInfo *PI, raw_ostream &out) - : BasicBlockPass(ID), PassToPrint(PI), Out(out) {} + : BasicBlockPass(ID), PassToPrint(PI), Out(out) { + std::string PassToPrintName = PassToPrint->getPassName(); + PassName = "BasicBlockPass Printer: " + PassToPrintName; + } virtual bool runOnBasicBlock(BasicBlock &BB) { if (!Quiet) { @@ -267,7 +293,7 @@ struct BasicBlockPassPrinter : public BasicBlockPass { return false; } - virtual const char *getPassName() const { return "BasicBlockPass Printer"; } + virtual const char *getPassName() const { return PassName.c_str(); } virtual void getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequiredID(PassToPrint->getTypeInfo()); -- 1.7.1 From grosser at fim.uni-passau.de Fri Sep 3 09:53:54 2010 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Fri, 3 Sep 2010 16:53:54 +0200 Subject: [llvm-commits] [PATCH 2/3] Execute all Pass Printers even if -quiet is set. In-Reply-To: <1283525635-16182-2-git-send-email-grosser@fim.uni-passau.de> References: <1283525635-16182-1-git-send-email-grosser@fim.uni-passau.de> <1283525635-16182-2-git-send-email-grosser@fim.uni-passau.de> Message-ID: <1283525635-16182-3-git-send-email-grosser@fim.uni-passau.de> Follow the same logic in the LoopPass, ModulePass and CallGraphSCCPass printers, as it was already used in the BasicBlockPass and FunctionPass printers. This is more consistent. The other option would have been to completely disable dumping the analysis information. However, as this information is the only information printed if the -analysis flag is set, calling opt would not do anything at all. --- tools/opt/opt.cpp | 35 ++++++++++++++++------------------- 1 files changed, 16 insertions(+), 19 deletions(-) diff --git a/tools/opt/opt.cpp b/tools/opt/opt.cpp index ce92ec1..56460d1 100644 --- a/tools/opt/opt.cpp +++ b/tools/opt/opt.cpp @@ -148,17 +148,16 @@ struct CallGraphSCCPassPrinter : public CallGraphSCCPass { } virtual bool runOnSCC(CallGraphSCC &SCC) { - if (!Quiet) { + if (!Quiet) Out << "Printing analysis '" << PassToPrint->getPassName() << "':\n"; - for (CallGraphSCC::iterator I = SCC.begin(), E = SCC.end(); I != E; ++I) { - Function *F = (*I)->getFunction(); - if (F) - getAnalysisID(PassToPrint->getTypeInfo()).print(Out, - F->getParent()); - } - } // Get and print pass... + for (CallGraphSCC::iterator I = SCC.begin(), E = SCC.end(); I != E; ++I) { + Function *F = (*I)->getFunction(); + if (F) + getAnalysisID(PassToPrint->getTypeInfo()).print(Out, + F->getParent()); + } return false; } @@ -185,12 +184,11 @@ struct ModulePassPrinter : public ModulePass { } virtual bool runOnModule(Module &M) { - if (!Quiet) { + if (!Quiet) Out << "Printing analysis '" << PassToPrint->getPassName() << "':\n"; - getAnalysisID(PassToPrint->getTypeInfo()).print(Out, &M); - } // Get and print pass... + getAnalysisID(PassToPrint->getTypeInfo()).print(Out, &M); return false; } @@ -216,10 +214,10 @@ struct FunctionPassPrinter : public FunctionPass { } virtual bool runOnFunction(Function &F) { - if (!Quiet) { + if (!Quiet) Out << "Printing analysis '" << PassToPrint->getPassName() << "' for function '" << F.getName() << "':\n"; - } + // Get and print pass... getAnalysisID(PassToPrint->getTypeInfo()).print(Out, F.getParent()); @@ -250,12 +248,12 @@ struct LoopPassPrinter : public LoopPass { virtual bool runOnLoop(Loop *L, LPPassManager &LPM) { - if (!Quiet) { + if (!Quiet) Out << "Printing analysis '" << PassToPrint->getPassName() << "':\n"; - getAnalysisID(PassToPrint->getTypeInfo()).print(Out, - L->getHeader()->getParent()->getParent()); - } + // Get and print pass... + getAnalysisID(PassToPrint->getTypeInfo()).print(Out, + L->getHeader()->getParent()->getParent()); return false; } @@ -282,10 +280,9 @@ struct BasicBlockPassPrinter : public BasicBlockPass { } virtual bool runOnBasicBlock(BasicBlock &BB) { - if (!Quiet) { + if (!Quiet) Out << "Printing Analysis info for BasicBlock '" << BB.getName() << "': Pass " << PassToPrint->getPassName() << ":\n"; - } // Get and print pass... getAnalysisID(PassToPrint->getTypeInfo()).print(Out, -- 1.7.1 From grosser at fim.uni-passau.de Fri Sep 3 09:53:55 2010 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Fri, 3 Sep 2010 16:53:55 +0200 Subject: [llvm-commits] [PATCH 3/3] Implement requiredTransitive In-Reply-To: <1283525635-16182-3-git-send-email-grosser@fim.uni-passau.de> References: <1283525635-16182-1-git-send-email-grosser@fim.uni-passau.de> <1283525635-16182-2-git-send-email-grosser@fim.uni-passau.de> <1283525635-16182-3-git-send-email-grosser@fim.uni-passau.de> Message-ID: <1283525635-16182-4-git-send-email-grosser@fim.uni-passau.de> The PassManager did not implement the transitivity of requiredTransitive. We just did not notice. --- lib/VMCore/PassManager.cpp | 14 +++++++++++ .../2010-09-03-RequiredTransitive.ll | 24 ++++++++++++++++++++ 2 files changed, 38 insertions(+), 0 deletions(-) create mode 100644 test/Analysis/ScalarEvolution/2010-09-03-RequiredTransitive.ll diff --git a/lib/VMCore/PassManager.cpp b/lib/VMCore/PassManager.cpp index ab4d4e5..2a491d0 100644 --- a/lib/VMCore/PassManager.cpp +++ b/lib/VMCore/PassManager.cpp @@ -507,6 +507,20 @@ void PMTopLevelManager::setLastUser(SmallVector &AnalysisPasses, if (P == AP) continue; + // Update the last users of passes that are required transitive by AP. + AnalysisUsage *AnUsage = findAnalysisUsage(AP); + const AnalysisUsage::VectorType &IDs = AnUsage->getRequiredTransitiveSet(); + SmallVector LastUses; + for (AnalysisUsage::VectorType::const_iterator I = IDs.begin(), + E = IDs.end(); I != E; ++I) { + if (Pass *AnalysisPass = findAnalysisPass(*I)) + LastUses.push_back(AnalysisPass); + else + llvm_unreachable("There is a problem"); + } + + setLastUser(LastUses, P); + // If AP is the last user of other passes then make P last user of // such passes. for (DenseMap::iterator LUI = LastUser.begin(), diff --git a/test/Analysis/ScalarEvolution/2010-09-03-RequiredTransitive.ll b/test/Analysis/ScalarEvolution/2010-09-03-RequiredTransitive.ll new file mode 100644 index 0000000..88f1338 --- /dev/null +++ b/test/Analysis/ScalarEvolution/2010-09-03-RequiredTransitive.ll @@ -0,0 +1,24 @@ +; RUN: opt -indvars -scalar-evolution -disable-output -analyze +; This test checks if the SCEV analysis is printed out at all. +; It failed once as the RequiredTransitive option was not implemented +; correctly. + +define i32 @main() nounwind { +entry: + br label %for.cond + +for.cond: ; preds = %for.inc, %entry + %indvar1 = phi i64 [ %indvar.next2, %for.inc ], [ 0, %entry ] ; [#uses=3] + %exitcond = icmp ne i64 %indvar1, 1024 ; [#uses=1] + br i1 %exitcond, label %for.body, label %for.end + +for.body: ; preds = %for.cond + br label %for.inc + +for.inc: ; preds = %for.body + %indvar.next2 = add i64 %indvar1, 1 ; [#uses=1] + br label %for.cond + +for.end: ; preds = %for.cond + ret i32 0 +} -- 1.7.1 From foldr at codedgers.com Fri Sep 3 10:01:53 2010 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Fri, 3 Sep 2010 17:01:53 +0200 Subject: [llvm-commits] [llvm] r112954 - /llvm/trunk/Makefile.rules In-Reply-To: References: <20100903095752.47CD52A6C12E@llvm.org> Message-ID: <20100903150153.GA2440@localhost.localdomain> Hi, On Fri, Sep 03, 2010 at 11:38:58PM +0900, NAKAMURA Takumi wrote: > Mikhail, > > Is it not GNU ld. what you use for cross build.? > Please tell me, version of gcc driver and binutils you are using. > We might need to let autoconf determine something. These are the versions I'm using: $ ./cross2/bin/i386-mingw32-llvm-gcc --version i386-mingw32-llvm-gcc (GCC) 4.2.1 (Based on Apple Inc. build 5658) (LLVM build) Copyright (C) 2007 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. $ ./cross2/bin/i386-mingw32-ld --version GNU ld (GNU Binutils) 2.20.1.20100303 Copyright 2009 Free Software Foundation, Inc. This program is free software; you may redistribute it under the terms of the GNU General Public License version 3 or (at your option) a later version. This program has absolutely no warranty. Maybe there's some configure argument that I should be providing when building binutils? That's what I'm doing now: $ TARGET=i386-mingw32 $ ~/src/binutils-2.20.1/configure --target=$TARGET --prefix=$PREFIX --disable-nls --disable-werror -- () ascii ribbon campaign - against html e-mail /\ www.asciiribbon.org - against proprietary attachments From foldr at codedgers.com Fri Sep 3 10:19:33 2010 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Fri, 3 Sep 2010 17:19:33 +0200 Subject: [llvm-commits] [llvm] r112954 - /llvm/trunk/Makefile.rules In-Reply-To: References: <20100903095752.47CD52A6C12E@llvm.org> Message-ID: <20100903151933.GA2839@localhost.localdomain> Hi, On Fri, Sep 03, 2010 at 11:38:58PM +0900, NAKAMURA Takumi wrote: > Mikhail, > > Is it not GNU ld. what you use for cross build.? > Please tell me, version of gcc driver and binutils you are using. > We might need to let autoconf determine something. BTW, ld was complaining about syntax error in 'exported_symbols.lst' which it interpreted as a linker script. Maybe the problem here is the wrong file extension (.lst instead of .def) ? -- () ascii ribbon campaign - against html e-mail /\ www.asciiribbon.org - against proprietary attachments From daniel at zuster.org Fri Sep 3 10:26:42 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Fri, 03 Sep 2010 15:26:42 -0000 Subject: [llvm-commits] [llvm] r112962 - in /llvm/trunk: lib/Target/ARM/ARMBaseRegisterInfo.cpp lib/Target/ARM/ARMBaseRegisterInfo.h lib/Target/ARM/Thumb1RegisterInfo.cpp test/CodeGen/Thumb/dyn-stackalloc.ll test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll Message-ID: <20100903152642.8C68D2A6C12E@llvm.org> Author: ddunbar Date: Fri Sep 3 10:26:42 2010 New Revision: 112962 URL: http://llvm.org/viewvc/llvm-project?rev=112962&view=rev Log: Revert "For ARM stack frames that utilize variable sized objects and have either", it is breaking oggenc with Clang for ARMv6. This reverts commit 8d6e29cfda270be483abf638850311670829ee65. Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp llvm/trunk/test/CodeGen/Thumb/dyn-stackalloc.ll llvm/trunk/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=112962&r1=112961&r2=112962&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Fri Sep 3 10:26:42 2010 @@ -50,10 +50,6 @@ using namespace llvm; -static cl::opt -EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true), - cl::desc("Enable use of a base pointer for complex stack frames")); - unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum, bool *isSPVFP) { if (isSPVFP) @@ -150,8 +146,7 @@ const ARMSubtarget &sti) : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), TII(tii), STI(sti), - FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11), - BasePtr(ARM::R6) { + FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) { } const unsigned* @@ -187,8 +182,6 @@ Reserved.set(ARM::FPSCR); if (hasFP(MF)) Reserved.set(FramePtr); - if (hasBasePointer(MF)) - Reserved.set(BasePtr); // Some targets reserve R9. if (STI.isR9Reserved()) Reserved.set(ARM::R9); @@ -202,10 +195,6 @@ case ARM::SP: case ARM::PC: return true; - case ARM::R6: - if (hasBasePointer(MF)) - return true; - break; case ARM::R7: case ARM::R11: if (FramePtr == Reg && hasFP(MF)) @@ -636,49 +625,35 @@ MFI->isFrameAddressTaken()); } -bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const { - const MachineFrameInfo *MFI = MF.getFrameInfo(); - const ARMFunctionInfo *AFI = MF.getInfo(); - - if (!EnableBasePointer) - return false; - - if (needsStackRealignment(MF) && MFI->hasVarSizedObjects()) - return true; - - // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited - // negative range for ldr/str (255), and thumb1 is positive offsets only. - // It's going to be better to use the SP or Base Pointer instead. When there - // are variable sized objects, we can't reference off of the SP, so we - // reserve a Base Pointer. - if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) { - // Conservatively estimate whether the negative offset from the frame - // pointer will be sufficient to reach. If a function has a smallish - // frame, it's less likely to have lots of spills and callee saved - // space, so it's all more likely to be within range of the frame pointer. - // If it's wrong, the scavenger will still enable access to work, it just - // won't be optimal. - if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128) - return false; - return true; - } - - return false; -} - bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const { + const MachineFrameInfo *MFI = MF.getFrameInfo(); const ARMFunctionInfo *AFI = MF.getInfo(); - return (RealignStack && !AFI->isThumb1OnlyFunction()); + return (RealignStack && + !AFI->isThumb1OnlyFunction() && + !MFI->hasVarSizedObjects()); } bool ARMBaseRegisterInfo:: needsStackRealignment(const MachineFunction &MF) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); const Function *F = MF.getFunction(); + const ARMFunctionInfo *AFI = MF.getInfo(); unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) || F->hasFnAttr(Attribute::StackAlignment)); + // FIXME: Currently we don't support stack realignment for functions with + // variable-sized allocas. + // FIXME: It's more complicated than this... + if (0 && requiresRealignment && MFI->hasVarSizedObjects()) + report_fatal_error( + "Stack realignment in presense of dynamic allocas is not supported"); + + // FIXME: This probably isn't the right place for this. + if (0 && requiresRealignment && AFI->isThumb1OnlyFunction()) + report_fatal_error( + "Stack realignment in thumb1 functions is not supported"); + return requiresRealignment && canRealignStack(MF); } @@ -801,10 +776,6 @@ if (AFI->isThumb1OnlyFunction() && AFI->getVarArgsRegSaveSize() > 0) MF.getRegInfo().setPhysRegUsed(ARM::LR); - // Spill the BasePtr if it's used. - if (hasBasePointer(MF)) - MF.getRegInfo().setPhysRegUsed(BasePtr); - // Don't spill FP if the frame can be eliminated. This is determined // by scanning the callee-save registers to see if any is used. const unsigned *CSRegs = getCalleeSavedRegs(); @@ -1051,14 +1022,13 @@ return Offset - AFI->getDPRCalleeSavedAreaOffset(); // When dynamically realigning the stack, use the frame pointer for - // parameters, and the stack/base pointer for locals. + // parameters, and the stack pointer for locals. if (needsStackRealignment(MF)) { assert (hasFP(MF) && "dynamic stack realignment without a FP!"); if (isFixed) { FrameReg = getFrameRegister(MF); Offset = FPOffset; - } else if (MFI->hasVarSizedObjects()) - FrameReg = BasePtr; + } return Offset; } @@ -1066,13 +1036,9 @@ if (hasFP(MF) && AFI->hasStackFrame()) { // Use frame pointer to reference fixed objects. Use it for locals if // there are VLAs (and thus the SP isn't reliable as a base). - if (isFixed || (MFI->hasVarSizedObjects() && !hasBasePointer(MF))) { + if (isFixed || MFI->hasVarSizedObjects()) { FrameReg = getFrameRegister(MF); Offset = FPOffset; - } else if (MFI->hasVarSizedObjects()) { - assert(hasBasePointer(MF) && "missing base pointer!"); - // Use the base register since we have it. - FrameReg = BasePtr; } else if (AFI->isThumb2Function()) { // In Thumb2 mode, the negative offset is very limited. Try to avoid // out of range references. @@ -1086,9 +1052,6 @@ Offset = FPOffset; } } - // Use the base pointer if we have one. - if (hasBasePointer(MF)) - FrameReg = BasePtr; return Offset; } @@ -1126,8 +1089,7 @@ case ARM::R5: return ARM::R4; case ARM::R7: - return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6)) - ? 0 : ARM::R6; + return isReservedReg(MF, ARM::R7) ? 0 : ARM::R6; case ARM::R9: return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8; case ARM::R11: @@ -1216,8 +1178,7 @@ case ARM::R4: return ARM::R5; case ARM::R6: - return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6)) - ? 0 : ARM::R7; + return isReservedReg(MF, ARM::R7) ? 0 : ARM::R7; case ARM::R8: return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9; case ARM::R10: @@ -1917,20 +1878,6 @@ AFI->setShouldRestoreSPFromFP(true); } - // If we need a base pointer, set it up here. It's whatever the value - // of the stack pointer is at this point. Any variable size objects - // will be allocated after this, so we can still use the base pointer - // to reference locals. - if (hasBasePointer(MF)) { - if (isARM) - BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), BasePtr) - .addReg(ARM::SP) - .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); - else - BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), BasePtr) - .addReg(ARM::SP); - } - // If the frame has variable sized objects then the epilogue must restore // the sp from fp. if (!AFI->shouldRestoreSPFromFP() && MFI->hasVarSizedObjects()) Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h?rev=112962&r1=112961&r2=112962&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h Fri Sep 3 10:26:42 2010 @@ -52,11 +52,6 @@ /// FramePtr - ARM physical register used as frame ptr. unsigned FramePtr; - /// BasePtr - ARM physical register used as a base ptr in complex stack - /// frames. I.e., when we need a 3rd base, not just SP and FP, due to - /// variable size stack objects. - unsigned BasePtr; - // Can be only subclassed. explicit ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI); @@ -107,7 +102,6 @@ MachineFunction &MF) const; bool hasFP(const MachineFunction &MF) const; - bool hasBasePointer(const MachineFunction &MF) const; bool canRealignStack(const MachineFunction &MF) const; bool needsStackRealignment(const MachineFunction &MF) const; Modified: llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp?rev=112962&r1=112961&r2=112962&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp Fri Sep 3 10:26:42 2010 @@ -604,12 +604,9 @@ else if (MF.getFrameInfo()->hasVarSizedObjects()) { assert(SPAdj == 0 && hasFP(MF) && "Unexpected"); // There are alloca()'s in this function, must reference off the frame - // pointer or base pointer instead. - if (!hasBasePointer(MF)) { - FrameReg = getFrameRegister(MF); - Offset -= AFI->getFramePtrSpillOffset(); - } else - FrameReg = BasePtr; + // pointer instead. + FrameReg = getFrameRegister(MF); + Offset -= AFI->getFramePtrSpillOffset(); } // Special handling of dbg_value instructions. @@ -790,13 +787,6 @@ AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); AFI->setDPRCalleeSavedAreaSize(DPRCSSize); - - // If we need a base pointer, set it up here. It's whatever the value - // of the stack pointer is at this point. Any variable size objects - // will be allocated after this, so we can still use the base pointer - // to reference locals. - if (hasBasePointer(MF)) - BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), BasePtr).addReg(ARM::SP); } static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) { Modified: llvm/trunk/test/CodeGen/Thumb/dyn-stackalloc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/dyn-stackalloc.ll?rev=112962&r1=112961&r2=112962&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/dyn-stackalloc.ll (original) +++ llvm/trunk/test/CodeGen/Thumb/dyn-stackalloc.ll Fri Sep 3 10:26:42 2010 @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=thumb | not grep {ldr sp} ; RUN: llc < %s -mtriple=thumb-apple-darwin | \ ; RUN: not grep {sub.*r7} -; RUN: llc < %s -march=thumb | grep {mov.*r6, sp} +; RUN: llc < %s -march=thumb | grep 4294967280 %struct.state = type { i32, %struct.info*, float**, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64, i64, i64, i64, i64, i64, i8* } %struct.info = type { i32, i32, i32, i32, i32, i32, i32, i8* } Modified: llvm/trunk/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll?rev=112962&r1=112961&r2=112962&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll Fri Sep 3 10:26:42 2010 @@ -7,12 +7,19 @@ define void @t() nounwind ssp { entry: ; CHECK: t: - %size = mul i32 8, 2 +; CHECK: push {r4, r7} +; CHECK: mov r0, sp +; CHECK: add r7, sp, #4 +; CHECK: bic r0, r0, #7 ; CHECK: subs r0, #16 ; CHECK: mov sp, r0 - %vla_a = alloca i8, i32 %size, align 8 +; CHECK: mov r0, sp +; CHECK: bic r0, r0, #7 ; CHECK: subs r0, #16 ; CHECK: mov sp, r0 + + %size = mul i32 8, 2 + %vla_a = alloca i8, i32 %size, align 8 %vla_b = alloca i8, i32 %size, align 8 unreachable } From foldr at codedgers.com Fri Sep 3 10:42:38 2010 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Fri, 03 Sep 2010 15:42:38 -0000 Subject: [llvm-commits] [llvm] r112963 - /llvm/trunk/Makefile.rules Message-ID: <20100903154238.6CBEC2A6C12E@llvm.org> Author: foldr Date: Fri Sep 3 10:42:38 2010 New Revision: 112963 URL: http://llvm.org/viewvc/llvm-project?rev=112963&view=rev Log: Revert "Rules for win32 ld shouldn't fire when cross-compiling." This reverts commit 012b374e5b46fe93a8fdf605f5929fa8239e0960. Modified: llvm/trunk/Makefile.rules Modified: llvm/trunk/Makefile.rules URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=112963&r1=112962&r2=112963&view=diff ============================================================================== --- llvm/trunk/Makefile.rules (original) +++ llvm/trunk/Makefile.rules Fri Sep 3 10:42:38 2010 @@ -972,14 +972,7 @@ endif # GNU ld Win32 accepts .DEF files that contain "DATA" entries. -# This doesn't work when cross-compiling, though. ifeq ($(HOST_OS), $(filter $(HOST_OS), Cygwin MingW)) -ifneq ($(LLVM_CROSS_COMPILING),1) -HAVE_WIN32_GNU_LD=1 -endif -endif - -ifeq ($(HAVE_WIN32_GNU_LD),1) NativeExportsFile := $(ObjDir)/$(notdir $(EXPORTED_SYMBOL_FILE:.exports=.def)) # LLVMLibsOptions is invalidated at processing tools/llvm-shlib. From foldr at codedgers.com Fri Sep 3 10:42:45 2010 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Fri, 03 Sep 2010 15:42:45 -0000 Subject: [llvm-commits] [llvm] r112964 - in /llvm/trunk/runtime/libprofile: Makefile exported_symbols.lst libprofile.exports Message-ID: <20100903154245.99F2D2A6C12F@llvm.org> Author: foldr Date: Fri Sep 3 10:42:45 2010 New Revision: 112964 URL: http://llvm.org/viewvc/llvm-project?rev=112964&view=rev Log: Rename 'libprofile/exported_symbols.lst' to 'libprofile/libprofile.exports'. Makefile.rules assumes that all EXPORTED_SYMBOL_FILEs have the .exports extension. Added: llvm/trunk/runtime/libprofile/libprofile.exports - copied, changed from r112963, llvm/trunk/runtime/libprofile/exported_symbols.lst Removed: llvm/trunk/runtime/libprofile/exported_symbols.lst Modified: llvm/trunk/runtime/libprofile/Makefile Modified: llvm/trunk/runtime/libprofile/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/runtime/libprofile/Makefile?rev=112964&r1=112963&r2=112964&view=diff ============================================================================== --- llvm/trunk/runtime/libprofile/Makefile (original) +++ llvm/trunk/runtime/libprofile/Makefile Fri Sep 3 10:42:45 2010 @@ -1,10 +1,10 @@ ##===- runtime/libprofile/Makefile -------------------------*- Makefile -*-===## -# +# # The LLVM Compiler Infrastructure # # This file is distributed under the University of Illinois Open Source # License. See LICENSE.TXT for details. -# +# ##===----------------------------------------------------------------------===## LEVEL = ../.. @@ -16,7 +16,7 @@ SHARED_LIBRARY = 1 LOADABLE_MODULE = 1 LIBRARYNAME = profile_rt -EXTRA_DIST = exported_symbols.lst -EXPORTED_SYMBOL_FILE = $(PROJ_SRC_DIR)/exported_symbols.lst +EXTRA_DIST = libprofile.exports +EXPORTED_SYMBOL_FILE = $(PROJ_SRC_DIR)/libprofile.exports include $(LEVEL)/Makefile.common Removed: llvm/trunk/runtime/libprofile/exported_symbols.lst URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/runtime/libprofile/exported_symbols.lst?rev=112963&view=auto ============================================================================== --- llvm/trunk/runtime/libprofile/exported_symbols.lst (original) +++ llvm/trunk/runtime/libprofile/exported_symbols.lst (removed) @@ -1,4 +0,0 @@ -llvm_start_edge_profiling -llvm_start_opt_edge_profiling -llvm_start_basic_block_tracing -llvm_trace_basic_block Copied: llvm/trunk/runtime/libprofile/libprofile.exports (from r112963, llvm/trunk/runtime/libprofile/exported_symbols.lst) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/runtime/libprofile/libprofile.exports?p2=llvm/trunk/runtime/libprofile/libprofile.exports&p1=llvm/trunk/runtime/libprofile/exported_symbols.lst&r1=112963&r2=112964&rev=112964&view=diff ============================================================================== (empty) From foldr at codedgers.com Fri Sep 3 10:45:32 2010 From: foldr at codedgers.com (Mikhail Glushenkov) Date: Fri, 3 Sep 2010 17:45:32 +0200 Subject: [llvm-commits] [llvm] r112954 - /llvm/trunk/Makefile.rules In-Reply-To: <20100903151933.GA2839@localhost.localdomain> References: <20100903095752.47CD52A6C12E@llvm.org> <20100903151933.GA2839@localhost.localdomain> Message-ID: <20100903154532.GA4712@localhost.localdomain> Hi, On Fri, Sep 03, 2010 at 05:19:33PM +0200, Mikhail Glushenkov wrote: > > BTW, ld was complaining about syntax error in 'exported_symbols.lst' which it > interpreted as a linker script. Maybe the problem here is the wrong file > extension (.lst instead of .def) ? Indeed, this was the case. Proper fix committed in r112964. -- () ascii ribbon campaign - against html e-mail /\ www.asciiribbon.org - against proprietary attachments From geek4civic at gmail.com Fri Sep 3 10:48:30 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Sat, 4 Sep 2010 00:48:30 +0900 Subject: [llvm-commits] [llvm] r112954 - /llvm/trunk/Makefile.rules In-Reply-To: <20100903150153.GA2440@localhost.localdomain> References: <20100903095752.47CD52A6C12E@llvm.org> <20100903150153.GA2440@localhost.localdomain> Message-ID: Mikhail, Thank for me to give your informations! 2010/9/4 Mikhail Glushenkov : > $ TARGET=i386-mingw32 > $ ~/src/binutils-2.20.1/configure --target=$TARGET --prefix=$PREFIX --disable-nls > --disable-werror Would you like to confirm and show command line with make VERBOSE=1 ? I supposed "cross build" might be "canadian cross". I specify; $ /path/to/configure --host=i686-pc-mingw32 --enable-optimized=yes --enable-shared=(yes|no) configure: WARNING: If you wanted to set the --build type, don't use --host. If a cross compiler is detected then cross compile mode will be used. checking build system type... (cached) powerpc64-unknown-linux-gnu checking host system type... (cached) i686-pc-mingw32 checking target system type... (cached) i686-pc-mingw32 checking type of operating system we're going to host on... (cached) MingW checking type of operating system we're going to target... (cached) MingW checking target architecture... (cached) x86 (snip) ...Takumi From geek4civic at gmail.com Fri Sep 3 10:54:59 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Sat, 4 Sep 2010 00:54:59 +0900 Subject: [llvm-commits] [llvm] r112964 - in /llvm/trunk/runtime/libprofile: Makefile exported_symbols.lst libprofile.exports In-Reply-To: <20100903154245.99F2D2A6C12F@llvm.org> References: <20100903154245.99F2D2A6C12F@llvm.org> Message-ID: Mikhail, > Rename 'libprofile/exported_symbols.lst' to 'libprofile/libprofile.exports'. It is the thing I wanted to propose commit, spasibo. I would commit one when I found how to check profile_rt.dll. (one is in my local repo) ...Takumi 2010/9/4 Mikhail Glushenkov : > Author: foldr > Date: Fri Sep ?3 10:42:45 2010 > New Revision: 112964 > > URL: http://llvm.org/viewvc/llvm-project?rev=112964&view=rev > Log: > Rename 'libprofile/exported_symbols.lst' to 'libprofile/libprofile.exports'. > > Makefile.rules assumes that all EXPORTED_SYMBOL_FILEs have the .exports > extension. > > Added: > ? ?llvm/trunk/runtime/libprofile/libprofile.exports > ? ? ?- copied, changed from r112963, llvm/trunk/runtime/libprofile/exported_symbols.lst > Removed: > ? ?llvm/trunk/runtime/libprofile/exported_symbols.lst > Modified: > ? ?llvm/trunk/runtime/libprofile/Makefile > > Modified: llvm/trunk/runtime/libprofile/Makefile > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/runtime/libprofile/Makefile?rev=112964&r1=112963&r2=112964&view=diff > ============================================================================== > --- llvm/trunk/runtime/libprofile/Makefile (original) > +++ llvm/trunk/runtime/libprofile/Makefile Fri Sep ?3 10:42:45 2010 > @@ -1,10 +1,10 @@ > ?##===- runtime/libprofile/Makefile -------------------------*- Makefile -*-===## > -# > +# > ?# ? ? ? ? ? ? ? ? ? ? The LLVM Compiler Infrastructure > ?# > ?# This file is distributed under the University of Illinois Open Source > ?# License. See LICENSE.TXT for details. > -# > +# > ?##===----------------------------------------------------------------------===## > > ?LEVEL = ../.. > @@ -16,7 +16,7 @@ > ?SHARED_LIBRARY = 1 > ?LOADABLE_MODULE = 1 > ?LIBRARYNAME = profile_rt > -EXTRA_DIST = exported_symbols.lst > -EXPORTED_SYMBOL_FILE = $(PROJ_SRC_DIR)/exported_symbols.lst > +EXTRA_DIST = libprofile.exports > +EXPORTED_SYMBOL_FILE = $(PROJ_SRC_DIR)/libprofile.exports > > ?include $(LEVEL)/Makefile.common > > Removed: llvm/trunk/runtime/libprofile/exported_symbols.lst > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/runtime/libprofile/exported_symbols.lst?rev=112963&view=auto > ============================================================================== > --- llvm/trunk/runtime/libprofile/exported_symbols.lst (original) > +++ llvm/trunk/runtime/libprofile/exported_symbols.lst (removed) > @@ -1,4 +0,0 @@ > -llvm_start_edge_profiling > -llvm_start_opt_edge_profiling > -llvm_start_basic_block_tracing > -llvm_trace_basic_block > > Copied: llvm/trunk/runtime/libprofile/libprofile.exports (from r112963, llvm/trunk/runtime/libprofile/exported_symbols.lst) > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/runtime/libprofile/libprofile.exports?p2=llvm/trunk/runtime/libprofile/libprofile.exports&p1=llvm/trunk/runtime/libprofile/exported_symbols.lst&r1=112963&r2=112964&rev=112964&view=diff > ============================================================================== > ? ?(empty) > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From resistor at mac.com Fri Sep 3 11:58:26 2010 From: resistor at mac.com (Owen Anderson) Date: Fri, 03 Sep 2010 16:58:26 -0000 Subject: [llvm-commits] [llvm] r112971 - /llvm/trunk/test/Transforms/CorrelatedValuePropagation/basic.ll Message-ID: <20100903165826.174C42A6C12C@llvm.org> Author: resistor Date: Fri Sep 3 11:58:25 2010 New Revision: 112971 URL: http://llvm.org/viewvc/llvm-project?rev=112971&view=rev Log: Add PR number to test. Modified: llvm/trunk/test/Transforms/CorrelatedValuePropagation/basic.ll Modified: llvm/trunk/test/Transforms/CorrelatedValuePropagation/basic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/CorrelatedValuePropagation/basic.ll?rev=112971&r1=112970&r2=112971&view=diff ============================================================================== --- llvm/trunk/test/Transforms/CorrelatedValuePropagation/basic.ll (original) +++ llvm/trunk/test/Transforms/CorrelatedValuePropagation/basic.ll Fri Sep 3 11:58:25 2010 @@ -16,6 +16,7 @@ ret i32 10 } +; PR4420 declare i1 @ext() ; CHECK: @test2 define i1 @test2() { From gohman at apple.com Fri Sep 3 12:29:33 2010 From: gohman at apple.com (Dan Gohman) Date: Fri, 03 Sep 2010 17:29:33 -0000 Subject: [llvm-commits] [llvm] r112976 - /llvm/trunk/Makefile.rules Message-ID: <20100903172933.45D6E2A6C12C@llvm.org> Author: djg Date: Fri Sep 3 12:29:33 2010 New Revision: 112976 URL: http://llvm.org/viewvc/llvm-project?rev=112976&view=rev Log: Fix Windows stuff to follow the existing source organization. Modified: llvm/trunk/Makefile.rules Modified: llvm/trunk/Makefile.rules URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=112976&r1=112975&r2=112976&view=diff ============================================================================== --- llvm/trunk/Makefile.rules (original) +++ llvm/trunk/Makefile.rules Fri Sep 3 12:29:33 2010 @@ -961,23 +961,9 @@ clean-local:: -$(Verb) $(RM) -f $(NativeExportsFile) else -NativeExportsFile := $(EXPORTED_SYMBOL_FILE) -endif -endif - -# Now add the linker command-line options to use the native export file. - -ifeq ($(HOST_OS),Darwin) -LLVMLibsOptions += -Wl,-exported_symbols_list,$(NativeExportsFile) -endif - -# GNU ld Win32 accepts .DEF files that contain "DATA" entries. ifeq ($(HOST_OS), $(filter $(HOST_OS), Cygwin MingW)) +# GNU ld Win32 accepts .DEF files that contain "DATA" entries. NativeExportsFile := $(ObjDir)/$(notdir $(EXPORTED_SYMBOL_FILE:.exports=.def)) - -# LLVMLibsOptions is invalidated at processing tools/llvm-shlib. -SharedLinkOptions += $(NativeExportsFile) - $(NativeExportsFile): $(EXPORTED_SYMBOL_FILE) $(ObjDir)/.dir $(Echo) Generating $(notdir $@) $(Verb) $(ECHO) "EXPORTS" > $@ @@ -985,12 +971,28 @@ clean-local:: -$(Verb) $(RM) -f $(NativeExportsFile) else +# Default behavior: just use the exports file verbatim. +NativeExportsFile := $(EXPORTED_SYMBOL_FILE) +endif +endif +endif + +# Now add the linker command-line options to use the native export file. + +# Darwin +ifeq ($(HOST_OS),Darwin) +LLVMLibsOptions += -Wl,-exported_symbols_list,$(NativeExportsFile) +endif # gold, bfd ld, etc. ifeq ($(HAVE_LINK_VERSION_SCRIPT),1) LLVMLibsOptions += -Wl,--version-script,$(NativeExportsFile) endif +# Windows +ifeq ($(HOST_OS), $(filter $(HOST_OS), Cygwin MingW)) +# LLVMLibsOptions is invalidated at processing tools/llvm-shlib. +SharedLinkOptions += $(NativeExportsFile) endif endif From gohman at apple.com Fri Sep 3 13:06:11 2010 From: gohman at apple.com (Dan Gohman) Date: Fri, 03 Sep 2010 18:06:11 -0000 Subject: [llvm-commits] [llvm] r112982 - /llvm/trunk/utils/vim/vimrc Message-ID: <20100903180611.9385A2A6C12C@llvm.org> Author: djg Date: Fri Sep 3 13:06:11 2010 New Revision: 112982 URL: http://llvm.org/viewvc/llvm-project?rev=112982&view=rev Log: Remove a TODO comment; this is now filed in bugzilla (PR8005). Modified: llvm/trunk/utils/vim/vimrc Modified: llvm/trunk/utils/vim/vimrc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/vim/vimrc?rev=112982&r1=112981&r2=112982&view=diff ============================================================================== --- llvm/trunk/utils/vim/vimrc (original) +++ llvm/trunk/utils/vim/vimrc Fri Sep 3 13:06:11 2010 @@ -94,10 +94,6 @@ " Clang code-completion support. This is highly experimental! -" TODO: code-completing on -" cast_cast< -" turns up some peculiarities -- "asm("? - " A path to a clang executable. let g:clang_path = "clang++" From bob.wilson at apple.com Fri Sep 3 13:16:02 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Fri, 03 Sep 2010 18:16:02 -0000 Subject: [llvm-commits] [llvm] r112983 - in /llvm/trunk/lib/Target/ARM: ARMExpandPseudoInsts.cpp ARMISelDAGToDAG.cpp ARMInstrNEON.td NEONPreAllocPass.cpp Message-ID: <20100903181602.C949B2A6C12C@llvm.org> Author: bwilson Date: Fri Sep 3 13:16:02 2010 New Revision: 112983 URL: http://llvm.org/viewvc/llvm-project?rev=112983&view=rev Log: Finish converting the rest of the NEON VLD instructions to use pseudo- instructions prior to regalloc. Since it's getting a little close to the 2.8 branch deadline, I'll have to leave the rest of the instructions handled by the NEONPreAllocPass for now, but I didn't want to leave half of the VLD instructions converted and the other half not. Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=112983&r1=112982&r2=112983&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Fri Sep 3 13:16:02 2010 @@ -105,16 +105,17 @@ D2 = TRI->getSubReg(DstReg, ARM::dsub_5); D3 = TRI->getSubReg(DstReg, ARM::dsub_7); } - MIB.addReg(D0).addReg(D1); + MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)) + .addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); if (NumRegs > 2) - MIB.addReg(D2); + MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); if (NumRegs > 3) - MIB.addReg(D3); + MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); if (hasWriteBack) { bool WBIsDead = MI.getOperand(OpIdx).isDead(); unsigned WBReg = MI.getOperand(OpIdx++).getReg(); - MIB.addReg(WBReg, getDefRegState(true) | getDeadRegState(WBIsDead)); + MIB.addReg(WBReg, RegState::Define | getDeadRegState(WBIsDead)); } // Copy the addrmode6 operands. bool AddrIsKill = MI.getOperand(OpIdx).isKill(); @@ -128,9 +129,12 @@ MIB = AddDefaultPred(MIB); TransferImpOps(MI, MIB, MIB); - // Add an implicit def for the super-reg. - MIB.addReg(DstReg, (getDefRegState(true) | getDeadRegState(DstIsDead) | - getImplRegState(true))); + // For an instruction writing the odd subregs, add an implicit use of the + // super-register because the even subregs were loaded separately. + if (RegSpc == OddDblSpc) + MIB.addReg(DstReg, RegState::Implicit); + // Add an implicit def for the super-register. + MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); MI.eraseFromParent(); } @@ -147,7 +151,7 @@ if (hasWriteBack) { bool DstIsDead = MI.getOperand(OpIdx).isDead(); unsigned DstReg = MI.getOperand(OpIdx++).getReg(); - MIB.addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead)); + MIB.addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)); } // Copy the addrmode6 operands. bool AddrIsKill = MI.getOperand(OpIdx).isKill(); @@ -336,15 +340,63 @@ case ARM::VLD2q32Pseudo_UPD: ExpandVLD(MBBI, ARM::VLD2q32, true, SingleSpc, 4); break; + case ARM::VLD3d8Pseudo: + ExpandVLD(MBBI, ARM::VLD3d8, false, SingleSpc, 3); break; + case ARM::VLD3d16Pseudo: + ExpandVLD(MBBI, ARM::VLD3d16, false, SingleSpc, 3); break; + case ARM::VLD3d32Pseudo: + ExpandVLD(MBBI, ARM::VLD3d32, false, SingleSpc, 3); break; case ARM::VLD1d64TPseudo: ExpandVLD(MBBI, ARM::VLD1d64T, false, SingleSpc, 3); break; + case ARM::VLD3d8Pseudo_UPD: + ExpandVLD(MBBI, ARM::VLD3d8_UPD, true, SingleSpc, 3); break; + case ARM::VLD3d16Pseudo_UPD: + ExpandVLD(MBBI, ARM::VLD3d16_UPD, true, SingleSpc, 3); break; + case ARM::VLD3d32Pseudo_UPD: + ExpandVLD(MBBI, ARM::VLD3d32_UPD, true, SingleSpc, 3); break; case ARM::VLD1d64TPseudo_UPD: - ExpandVLD(MBBI, ARM::VLD1d64T, true, SingleSpc, 3); break; - + ExpandVLD(MBBI, ARM::VLD1d64T_UPD, true, SingleSpc, 3); break; + case ARM::VLD3q8Pseudo_UPD: + ExpandVLD(MBBI, ARM::VLD3q8_UPD, true, EvenDblSpc, 3); break; + case ARM::VLD3q16Pseudo_UPD: + ExpandVLD(MBBI, ARM::VLD3q16_UPD, true, EvenDblSpc, 3); break; + case ARM::VLD3q32Pseudo_UPD: + ExpandVLD(MBBI, ARM::VLD3q32_UPD, true, EvenDblSpc, 3); break; + case ARM::VLD3q8oddPseudo_UPD: + ExpandVLD(MBBI, ARM::VLD3q8_UPD, true, OddDblSpc, 3); break; + case ARM::VLD3q16oddPseudo_UPD: + ExpandVLD(MBBI, ARM::VLD3q16_UPD, true, OddDblSpc, 3); break; + case ARM::VLD3q32oddPseudo_UPD: + ExpandVLD(MBBI, ARM::VLD3q32_UPD, true, OddDblSpc, 3); break; + + case ARM::VLD4d8Pseudo: + ExpandVLD(MBBI, ARM::VLD4d8, false, SingleSpc, 4); break; + case ARM::VLD4d16Pseudo: + ExpandVLD(MBBI, ARM::VLD4d16, false, SingleSpc, 4); break; + case ARM::VLD4d32Pseudo: + ExpandVLD(MBBI, ARM::VLD4d32, false, SingleSpc, 4); break; case ARM::VLD1d64QPseudo: ExpandVLD(MBBI, ARM::VLD1d64Q, false, SingleSpc, 4); break; + case ARM::VLD4d8Pseudo_UPD: + ExpandVLD(MBBI, ARM::VLD4d8_UPD, true, SingleSpc, 4); break; + case ARM::VLD4d16Pseudo_UPD: + ExpandVLD(MBBI, ARM::VLD4d16_UPD, true, SingleSpc, 4); break; + case ARM::VLD4d32Pseudo_UPD: + ExpandVLD(MBBI, ARM::VLD4d32_UPD, true, SingleSpc, 4); break; case ARM::VLD1d64QPseudo_UPD: - ExpandVLD(MBBI, ARM::VLD1d64Q, true, SingleSpc, 4); break; + ExpandVLD(MBBI, ARM::VLD1d64Q_UPD, true, SingleSpc, 4); break; + case ARM::VLD4q8Pseudo_UPD: + ExpandVLD(MBBI, ARM::VLD4q8_UPD, true, EvenDblSpc, 4); break; + case ARM::VLD4q16Pseudo_UPD: + ExpandVLD(MBBI, ARM::VLD4q16_UPD, true, EvenDblSpc, 4); break; + case ARM::VLD4q32Pseudo_UPD: + ExpandVLD(MBBI, ARM::VLD4q32_UPD, true, EvenDblSpc, 4); break; + case ARM::VLD4q8oddPseudo_UPD: + ExpandVLD(MBBI, ARM::VLD4q8_UPD, true, OddDblSpc, 4); break; + case ARM::VLD4q16oddPseudo_UPD: + ExpandVLD(MBBI, ARM::VLD4q16_UPD, true, OddDblSpc, 4); break; + case ARM::VLD4q32oddPseudo_UPD: + ExpandVLD(MBBI, ARM::VLD4q32_UPD, true, OddDblSpc, 4); break; case ARM::VST1q8Pseudo: ExpandVST(MBBI, ARM::VST1q8, false, SingleSpc, 2); break; Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=112983&r1=112982&r2=112983&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Fri Sep 3 13:16:02 2010 @@ -1111,120 +1111,79 @@ break; } + EVT ResTy; + if (NumVecs == 1) + ResTy = VT; + else { + unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs; + if (!is64BitVector) + ResTyElts *= 2; + ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts); + } + SDValue Pred = getAL(CurDAG); SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); + SDValue SuperReg; if (is64BitVector) { unsigned Opc = DOpcodes[OpcodeIndex]; const SDValue Ops[] = { MemAddr, Align, Pred, Reg0, Chain }; - SDNode *VLd; - if (NumVecs <= 2) { - EVT ResTy; - if (NumVecs == 1) - ResTy = VT; - else - ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, NumVecs); - VLd = CurDAG->getMachineNode(Opc, dl, ResTy, MVT::Other, Ops, 5); - } else { - std::vector ResTys(NumVecs, VT); - ResTys.push_back(MVT::Other); - VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 5); - } + SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTy, MVT::Other, Ops, 5); if (NumVecs == 1) return VLd; - SDValue SuperReg; - if (NumVecs <= 2) - SuperReg = SDValue(VLd, 0); - else { - SDValue V0 = SDValue(VLd, 0); - SDValue V1 = SDValue(VLd, 1); - // Form a REG_SEQUENCE to force register allocation. - SDValue V2 = SDValue(VLd, 2); - // If it's a vld3, form a quad D-register but discard the last part. - SDValue V3 = (NumVecs == 3) - ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0) - : SDValue(VLd, 3); - SuperReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0); - } - + SuperReg = SDValue(VLd, 0); assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering"); for (unsigned Vec = 0; Vec < NumVecs; ++Vec) { SDValue D = CurDAG->getTargetExtractSubreg(ARM::dsub_0+Vec, dl, VT, SuperReg); ReplaceUses(SDValue(N, Vec), D); } - ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, NumVecs <= 2 ? 1 : NumVecs)); + ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1)); return NULL; } - EVT RegVT = GetNEONSubregVT(VT); if (NumVecs <= 2) { // Quad registers are directly supported for VLD1 and VLD2, // loading pairs of D regs. unsigned Opc = QOpcodes0[OpcodeIndex]; const SDValue Ops[] = { MemAddr, Align, Pred, Reg0, Chain }; - - EVT ResTy; - if (NumVecs == 1) - ResTy = VT; - else - ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, 2 * NumVecs); SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTy, MVT::Other, Ops, 5); - - // Combine the even and odd subregs to produce the result. if (NumVecs == 1) return VLd; - SDValue QQ = SDValue(VLd, 0); + SuperReg = SDValue(VLd, 0); Chain = SDValue(VLd, 1); - SDValue Q0 = CurDAG->getTargetExtractSubreg(ARM::qsub_0, dl, VT, QQ); - SDValue Q1 = CurDAG->getTargetExtractSubreg(ARM::qsub_1, dl, VT, QQ); - ReplaceUses(SDValue(N, 0), Q0); - ReplaceUses(SDValue(N, 1), Q1); } else { // Otherwise, quad registers are loaded with two separate instructions, // where one loads the even registers and the other loads the odd registers. - - std::vector ResTys(NumVecs, RegVT); - ResTys.push_back(MemAddr.getValueType()); - ResTys.push_back(MVT::Other); + EVT AddrTy = MemAddr.getValueType(); // Load the even subregs. unsigned Opc = QOpcodes0[OpcodeIndex]; - const SDValue OpsA[] = { MemAddr, Align, Reg0, Pred, Reg0, Chain }; - SDNode *VLdA = CurDAG->getMachineNode(Opc, dl, ResTys, OpsA, 6); - Chain = SDValue(VLdA, NumVecs+1); + SDValue ImplDef = + SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0); + const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain }; + SDNode *VLdA = + CurDAG->getMachineNode(Opc, dl, ResTy, AddrTy, MVT::Other, OpsA, 7); + Chain = SDValue(VLdA, 2); // Load the odd subregs. Opc = QOpcodes1[OpcodeIndex]; - const SDValue OpsB[] = { SDValue(VLdA, NumVecs), - Align, Reg0, Pred, Reg0, Chain }; - SDNode *VLdB = CurDAG->getMachineNode(Opc, dl, ResTys, OpsB, 6); - Chain = SDValue(VLdB, NumVecs+1); - - SDValue V0 = SDValue(VLdA, 0); - SDValue V1 = SDValue(VLdB, 0); - SDValue V2 = SDValue(VLdA, 1); - SDValue V3 = SDValue(VLdB, 1); - SDValue V4 = SDValue(VLdA, 2); - SDValue V5 = SDValue(VLdB, 2); - SDValue V6 = (NumVecs == 3) - ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,RegVT), 0) - : SDValue(VLdA, 3); - SDValue V7 = (NumVecs == 3) - ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,RegVT), 0) - : SDValue(VLdB, 3); - SDValue RegSeq = SDValue(OctoDRegs(MVT::v8i64, V0, V1, V2, V3, - V4, V5, V6, V7), 0); + const SDValue OpsB[] = { SDValue(VLdA, 1), Align, Reg0, SDValue(VLdA, 0), + Pred, Reg0, Chain }; + SDNode *VLdB = + CurDAG->getMachineNode(Opc, dl, ResTy, AddrTy, MVT::Other, OpsB, 7); + SuperReg = SDValue(VLdB, 0); + Chain = SDValue(VLdB, 2); + } - // Extract out the 3 / 4 Q registers. - assert(ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering"); - for (unsigned Vec = 0; Vec < NumVecs; ++Vec) { - SDValue Q = CurDAG->getTargetExtractSubreg(ARM::qsub_0+Vec, - dl, VT, RegSeq); - ReplaceUses(SDValue(N, Vec), Q); - } + // Extract out the Q registers. + assert(ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering"); + for (unsigned Vec = 0; Vec < NumVecs; ++Vec) { + SDValue Q = CurDAG->getTargetExtractSubreg(ARM::qsub_0+Vec, + dl, VT, SuperReg); + ReplaceUses(SDValue(N, Vec), Q); } ReplaceUses(SDValue(N, NumVecs), Chain); return NULL; @@ -2166,26 +2125,26 @@ } case Intrinsic::arm_neon_vld3: { - unsigned DOpcodes[] = { ARM::VLD3d8, ARM::VLD3d16, - ARM::VLD3d32, ARM::VLD1d64T }; - unsigned QOpcodes0[] = { ARM::VLD3q8_UPD, - ARM::VLD3q16_UPD, - ARM::VLD3q32_UPD }; - unsigned QOpcodes1[] = { ARM::VLD3q8odd_UPD, - ARM::VLD3q16odd_UPD, - ARM::VLD3q32odd_UPD }; + unsigned DOpcodes[] = { ARM::VLD3d8Pseudo, ARM::VLD3d16Pseudo, + ARM::VLD3d32Pseudo, ARM::VLD1d64TPseudo }; + unsigned QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD, + ARM::VLD3q16Pseudo_UPD, + ARM::VLD3q32Pseudo_UPD }; + unsigned QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD, + ARM::VLD3q16oddPseudo_UPD, + ARM::VLD3q32oddPseudo_UPD }; return SelectVLD(N, 3, DOpcodes, QOpcodes0, QOpcodes1); } case Intrinsic::arm_neon_vld4: { - unsigned DOpcodes[] = { ARM::VLD4d8, ARM::VLD4d16, - ARM::VLD4d32, ARM::VLD1d64Q }; - unsigned QOpcodes0[] = { ARM::VLD4q8_UPD, - ARM::VLD4q16_UPD, - ARM::VLD4q32_UPD }; - unsigned QOpcodes1[] = { ARM::VLD4q8odd_UPD, - ARM::VLD4q16odd_UPD, - ARM::VLD4q32odd_UPD }; + unsigned DOpcodes[] = { ARM::VLD4d8Pseudo, ARM::VLD4d16Pseudo, + ARM::VLD4d32Pseudo, ARM::VLD1d64QPseudo }; + unsigned QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD, + ARM::VLD4q16Pseudo_UPD, + ARM::VLD4q32Pseudo_UPD }; + unsigned QOpcodes1[] = { ARM::VLD4q8oddPseudo_UPD, + ARM::VLD4q16oddPseudo_UPD, + ARM::VLD4q32oddPseudo_UPD }; return SelectVLD(N, 4, DOpcodes, QOpcodes0, QOpcodes1); } Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=112983&r1=112982&r2=112983&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Fri Sep 3 13:16:02 2010 @@ -181,6 +181,10 @@ : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb), (ins addrmode6:$addr, am6offset:$offset), IIC_VST, "$addr.addr = $wb">; +class VLDQQQQWBPseudo + : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb), + (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), IIC_VST, + "$addr.addr = $wb, $src = $dst">; // VLD1 : Vector Load (multiple single elements) class VLD1D op7_4, string Dt> @@ -356,6 +360,10 @@ def VLD3d16 : VLD3D<0b0100, 0b0100, "16">; def VLD3d32 : VLD3D<0b0100, 0b1000, "32">; +def VLD3d8Pseudo : VLDQQPseudo; +def VLD3d16Pseudo : VLDQQPseudo; +def VLD3d32Pseudo : VLDQQPseudo; + // ...with address register writeback: class VLD3DWB op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b10, op11_8, op7_4, @@ -368,6 +376,10 @@ def VLD3d16_UPD : VLD3DWB<0b0100, 0b0100, "16">; def VLD3d32_UPD : VLD3DWB<0b0100, 0b1000, "32">; +def VLD3d8Pseudo_UPD : VLDQQWBPseudo; +def VLD3d16Pseudo_UPD : VLDQQWBPseudo; +def VLD3d32Pseudo_UPD : VLDQQWBPseudo; + // ...with double-spaced registers (non-updating versions for disassembly only): def VLD3q8 : VLD3D<0b0101, 0b0000, "8">; def VLD3q16 : VLD3D<0b0101, 0b0100, "16">; @@ -376,10 +388,14 @@ def VLD3q16_UPD : VLD3DWB<0b0101, 0b0100, "16">; def VLD3q32_UPD : VLD3DWB<0b0101, 0b1000, "32">; +def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo; +def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo; +def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo; + // ...alternate versions to be allocated odd register numbers: -def VLD3q8odd_UPD : VLD3DWB<0b0101, 0b0000, "8">; -def VLD3q16odd_UPD : VLD3DWB<0b0101, 0b0100, "16">; -def VLD3q32odd_UPD : VLD3DWB<0b0101, 0b1000, "32">; +def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo; +def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo; +def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo; // VLD4 : Vector Load (multiple 4-element structures) class VLD4D op11_8, bits<4> op7_4, string Dt> @@ -392,6 +408,10 @@ def VLD4d16 : VLD4D<0b0000, 0b0100, "16">; def VLD4d32 : VLD4D<0b0000, 0b1000, "32">; +def VLD4d8Pseudo : VLDQQPseudo; +def VLD4d16Pseudo : VLDQQPseudo; +def VLD4d32Pseudo : VLDQQPseudo; + // ...with address register writeback: class VLD4DWB op11_8, bits<4> op7_4, string Dt> : NLdSt<0, 0b10, op11_8, op7_4, @@ -404,6 +424,10 @@ def VLD4d16_UPD : VLD4DWB<0b0000, 0b0100, "16">; def VLD4d32_UPD : VLD4DWB<0b0000, 0b1000, "32">; +def VLD4d8Pseudo_UPD : VLDQQWBPseudo; +def VLD4d16Pseudo_UPD : VLDQQWBPseudo; +def VLD4d32Pseudo_UPD : VLDQQWBPseudo; + // ...with double-spaced registers (non-updating versions for disassembly only): def VLD4q8 : VLD4D<0b0001, 0b0000, "8">; def VLD4q16 : VLD4D<0b0001, 0b0100, "16">; @@ -412,10 +436,14 @@ def VLD4q16_UPD : VLD4DWB<0b0001, 0b0100, "16">; def VLD4q32_UPD : VLD4DWB<0b0001, 0b1000, "32">; +def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo; +def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo; +def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo; + // ...alternate versions to be allocated odd register numbers: -def VLD4q8odd_UPD : VLD4DWB<0b0001, 0b0000, "8">; -def VLD4q16odd_UPD : VLD4DWB<0b0001, 0b0100, "16">; -def VLD4q32odd_UPD : VLD4DWB<0b0001, 0b1000, "32">; +def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo; +def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo; +def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo; // VLD1LN : Vector Load (single element to one lane) // FIXME: Not yet implemented. Modified: llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp?rev=112983&r1=112982&r2=112983&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp (original) +++ llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp Fri Sep 3 13:16:02 2010 @@ -74,10 +74,6 @@ Stride = 2; return true; - case ARM::VLD3d8: - case ARM::VLD3d16: - case ARM::VLD3d32: - case ARM::VLD1d64T: case ARM::VLD3LNd8: case ARM::VLD3LNd16: case ARM::VLD3LNd32: @@ -85,24 +81,6 @@ NumRegs = 3; return true; - case ARM::VLD3q8_UPD: - case ARM::VLD3q16_UPD: - case ARM::VLD3q32_UPD: - FirstOpnd = 0; - NumRegs = 3; - Offset = 0; - Stride = 2; - return true; - - case ARM::VLD3q8odd_UPD: - case ARM::VLD3q16odd_UPD: - case ARM::VLD3q32odd_UPD: - FirstOpnd = 0; - NumRegs = 3; - Offset = 1; - Stride = 2; - return true; - case ARM::VLD3LNq16: case ARM::VLD3LNq32: FirstOpnd = 0; @@ -119,10 +97,6 @@ Stride = 2; return true; - case ARM::VLD4d8: - case ARM::VLD4d16: - case ARM::VLD4d32: - case ARM::VLD1d64Q: case ARM::VLD4LNd8: case ARM::VLD4LNd16: case ARM::VLD4LNd32: @@ -130,24 +104,6 @@ NumRegs = 4; return true; - case ARM::VLD4q8_UPD: - case ARM::VLD4q16_UPD: - case ARM::VLD4q32_UPD: - FirstOpnd = 0; - NumRegs = 4; - Offset = 0; - Stride = 2; - return true; - - case ARM::VLD4q8odd_UPD: - case ARM::VLD4q16odd_UPD: - case ARM::VLD4q32odd_UPD: - FirstOpnd = 0; - NumRegs = 4; - Offset = 1; - Stride = 2; - return true; - case ARM::VLD4LNq16: case ARM::VLD4LNq32: FirstOpnd = 0; From grosbach at apple.com Fri Sep 3 13:17:16 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 03 Sep 2010 18:17:16 -0000 Subject: [llvm-commits] [llvm] r112984 - /llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h Message-ID: <20100903181716.E6A842A6C12C@llvm.org> Author: grosbach Date: Fri Sep 3 13:17:16 2010 New Revision: 112984 URL: http://llvm.org/viewvc/llvm-project?rev=112984&view=rev Log: Add 'const' to getter function. Modified: llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h Modified: llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h?rev=112984&r1=112983&r2=112984&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h Fri Sep 3 13:17:16 2010 @@ -305,7 +305,7 @@ /// getLocalFrameMaxAlign - Return the required alignment of the local /// object blob. - unsigned getLocalFrameMaxAlign() { return LocalFrameMaxAlign; } + unsigned getLocalFrameMaxAlign() const { return LocalFrameMaxAlign; } /// getUseLocalStackAllocationBlock - Get whether the local allocation blob /// should be allocated together or let PEI allocate the locals in it From grosbach at apple.com Fri Sep 3 13:28:19 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 03 Sep 2010 18:28:19 -0000 Subject: [llvm-commits] [llvm] r112986 - /llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Message-ID: <20100903182819.EE0E02A6C12C@llvm.org> Author: grosbach Date: Fri Sep 3 13:28:19 2010 New Revision: 112986 URL: http://llvm.org/viewvc/llvm-project?rev=112986&view=rev Log: Check the local frame alignment for determining whether dynamic stack alignment should be performed. Otherwise dynamic realignment may trigger when the register allocator has already used the frame pointer as a general purpose register. That is, we need to make sure that the list of reserved registers doesn't change after register allocation. Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=112986&r1=112985&r2=112986&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Fri Sep 3 13:28:19 2010 @@ -639,7 +639,7 @@ const Function *F = MF.getFunction(); const ARMFunctionInfo *AFI = MF.getInfo(); unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); - bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) || + bool requiresRealignment = ((MFI->getLocalFrameMaxAlign() > StackAlign) || F->hasFnAttr(Attribute::StackAlignment)); // FIXME: Currently we don't support stack realignment for functions with From resistor at mac.com Fri Sep 3 13:33:09 2010 From: resistor at mac.com (Owen Anderson) Date: Fri, 03 Sep 2010 18:33:09 -0000 Subject: [llvm-commits] [llvm] r112987 - /llvm/trunk/test/Transforms/InstCombine/phi.ll Message-ID: <20100903183309.1A7862A6C12C@llvm.org> Author: resistor Date: Fri Sep 3 13:33:08 2010 New Revision: 112987 URL: http://llvm.org/viewvc/llvm-project?rev=112987&view=rev Log: Add a test for PR4413, which was apparently fixed at some point in the past. Modified: llvm/trunk/test/Transforms/InstCombine/phi.ll Modified: llvm/trunk/test/Transforms/InstCombine/phi.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/phi.ll?rev=112987&r1=112986&r2=112987&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/phi.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/phi.ll Fri Sep 3 13:33:08 2010 @@ -402,3 +402,24 @@ store i32 %tmp5, i32* %res br label %if.end } + +; PR4413 +declare i32 @ext() +; CHECK: @test17 +define i32 @test17(i1 %a) { +entry: + br i1 %a, label %bb1, label %bb2 + +bb1: ; preds = %entry + %0 = tail call i32 @ext() ; [#uses=1] + br label %bb2 + +bb2: ; preds = %bb1, %entry + %cond = phi i1 [ true, %bb1 ], [ false, %entry ] ; [#uses=1] +; CHECK-NOT: %val = phi i32 [ %0, %bb1 ], [ 0, %entry ] + %val = phi i32 [ %0, %bb1 ], [ 0, %entry ] ; [#uses=1] + %res = select i1 %cond, i32 %val, i32 0 ; [#uses=1] +; CHECK: ret i32 %cond + ret i32 %res +} + From stoklund at 2pi.dk Fri Sep 3 13:36:56 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Fri, 03 Sep 2010 18:36:56 -0000 Subject: [llvm-commits] [llvm] r112988 - /llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp Message-ID: <20100903183656.8531A2A6C12C@llvm.org> Author: stoklund Date: Fri Sep 3 13:36:56 2010 New Revision: 112988 URL: http://llvm.org/viewvc/llvm-project?rev=112988&view=rev Log: VirtRegRewriter checks for early clobbers before it reuses an available stack slot. Teach it to also check for early clobbered aliases, and early clobber operands following the current operand. This fixes the miscompilation in PR8044 where EC registers eax and ecx were being used for inputs. Modified: llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp Modified: llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp?rev=112988&r1=112987&r2=112988&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp (original) +++ llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp Fri Sep 3 13:36:56 2010 @@ -2027,14 +2027,16 @@ CanReuse = !ReusedOperands.isClobbered(PhysReg) && Spills.canClobberPhysReg(PhysReg); } - // If this is an asm, and PhysReg is used elsewhere as an earlyclobber - // operand, we can't also use it as an input. (Outputs always come - // before inputs, so we can stop looking at i.) + // If this is an asm, and a PhysReg alias is used elsewhere as an + // earlyclobber operand, we can't also use it as an input. if (MI.isInlineAsm()) { - for (unsigned k=0; kregsOverlap(MOk.getReg(), PhysReg)) { CanReuse = false; + DEBUG(dbgs() << "Not reusing physreg " << TRI->getName(PhysReg) + << " for vreg" << VirtReg << ": " << MOk << '\n'); break; } } From isanbard at gmail.com Fri Sep 3 13:41:21 2010 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 03 Sep 2010 18:41:21 -0000 Subject: [llvm-commits] [llvm] r112991 - /llvm/trunk/tools/llvm-diff/DifferenceEngine.h Message-ID: <20100903184121.28CBC2A6C12C@llvm.org> Author: void Date: Fri Sep 3 13:41:20 2010 New Revision: 112991 URL: http://llvm.org/viewvc/llvm-project?rev=112991&view=rev Log: Quiesce warning about non-virtual d'tor in virtual class. Modified: llvm/trunk/tools/llvm-diff/DifferenceEngine.h Modified: llvm/trunk/tools/llvm-diff/DifferenceEngine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-diff/DifferenceEngine.h?rev=112991&r1=112990&r2=112991&view=diff ============================================================================== --- llvm/trunk/tools/llvm-diff/DifferenceEngine.h (original) +++ llvm/trunk/tools/llvm-diff/DifferenceEngine.h Fri Sep 3 13:41:20 2010 @@ -118,7 +118,7 @@ virtual void logd(const DiffLogBuilder &Log) = 0; protected: - ~Consumer() {} + virtual ~Consumer() {} }; /// A RAII object for recording the current context. @@ -141,7 +141,7 @@ virtual bool operator()(Value *L, Value *R) = 0; protected: - ~Oracle() {} + virtual ~Oracle() {} }; DifferenceEngine(LLVMContext &context, Consumer &consumer) From grosbach at apple.com Fri Sep 3 13:37:12 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 03 Sep 2010 18:37:12 -0000 Subject: [llvm-commits] [llvm] r112989 - in /llvm/trunk: lib/Target/ARM/ARMBaseRegisterInfo.cpp lib/Target/ARM/ARMBaseRegisterInfo.h lib/Target/ARM/Thumb1RegisterInfo.cpp test/CodeGen/Thumb/dyn-stackalloc.ll test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll Message-ID: <20100903183712.A178D2A6C12C@llvm.org> Author: grosbach Date: Fri Sep 3 13:37:12 2010 New Revision: 112989 URL: http://llvm.org/viewvc/llvm-project?rev=112989&view=rev Log: Re-apply r112883: "For ARM stack frames that utilize variable sized objects and have either large local stack areas or require dynamic stack realignment, allocate a base register via which to access the local frame. This allows efficient access to frame indices not accessible via the FP (either due to being out of range or due to dynamic realignment) or the SP (due to variable sized object allocation). In particular, this greatly improves efficiency of access to spill slots in Thumb functions which contain VLAs." r112986 fixed a latent bug exposed by the above. Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp llvm/trunk/test/CodeGen/Thumb/dyn-stackalloc.ll llvm/trunk/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=112989&r1=112988&r2=112989&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Fri Sep 3 13:37:12 2010 @@ -50,6 +50,10 @@ using namespace llvm; +static cl::opt +EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true), + cl::desc("Enable use of a base pointer for complex stack frames")); + unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum, bool *isSPVFP) { if (isSPVFP) @@ -146,7 +150,8 @@ const ARMSubtarget &sti) : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), TII(tii), STI(sti), - FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) { + FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11), + BasePtr(ARM::R6) { } const unsigned* @@ -182,6 +187,8 @@ Reserved.set(ARM::FPSCR); if (hasFP(MF)) Reserved.set(FramePtr); + if (hasBasePointer(MF)) + Reserved.set(BasePtr); // Some targets reserve R9. if (STI.isR9Reserved()) Reserved.set(ARM::R9); @@ -195,6 +202,10 @@ case ARM::SP: case ARM::PC: return true; + case ARM::R6: + if (hasBasePointer(MF)) + return true; + break; case ARM::R7: case ARM::R11: if (FramePtr == Reg && hasFP(MF)) @@ -625,35 +636,49 @@ MFI->isFrameAddressTaken()); } -bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const { +bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); const ARMFunctionInfo *AFI = MF.getInfo(); - return (RealignStack && - !AFI->isThumb1OnlyFunction() && - !MFI->hasVarSizedObjects()); + + if (!EnableBasePointer) + return false; + + if (needsStackRealignment(MF) && MFI->hasVarSizedObjects()) + return true; + + // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited + // negative range for ldr/str (255), and thumb1 is positive offsets only. + // It's going to be better to use the SP or Base Pointer instead. When there + // are variable sized objects, we can't reference off of the SP, so we + // reserve a Base Pointer. + if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) { + // Conservatively estimate whether the negative offset from the frame + // pointer will be sufficient to reach. If a function has a smallish + // frame, it's less likely to have lots of spills and callee saved + // space, so it's all more likely to be within range of the frame pointer. + // If it's wrong, the scavenger will still enable access to work, it just + // won't be optimal. + if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128) + return false; + return true; + } + + return false; +} + +bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const { + const ARMFunctionInfo *AFI = MF.getInfo(); + return (RealignStack && !AFI->isThumb1OnlyFunction()); } bool ARMBaseRegisterInfo:: needsStackRealignment(const MachineFunction &MF) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); const Function *F = MF.getFunction(); - const ARMFunctionInfo *AFI = MF.getInfo(); unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); bool requiresRealignment = ((MFI->getLocalFrameMaxAlign() > StackAlign) || F->hasFnAttr(Attribute::StackAlignment)); - // FIXME: Currently we don't support stack realignment for functions with - // variable-sized allocas. - // FIXME: It's more complicated than this... - if (0 && requiresRealignment && MFI->hasVarSizedObjects()) - report_fatal_error( - "Stack realignment in presense of dynamic allocas is not supported"); - - // FIXME: This probably isn't the right place for this. - if (0 && requiresRealignment && AFI->isThumb1OnlyFunction()) - report_fatal_error( - "Stack realignment in thumb1 functions is not supported"); - return requiresRealignment && canRealignStack(MF); } @@ -776,6 +801,10 @@ if (AFI->isThumb1OnlyFunction() && AFI->getVarArgsRegSaveSize() > 0) MF.getRegInfo().setPhysRegUsed(ARM::LR); + // Spill the BasePtr if it's used. + if (hasBasePointer(MF)) + MF.getRegInfo().setPhysRegUsed(BasePtr); + // Don't spill FP if the frame can be eliminated. This is determined // by scanning the callee-save registers to see if any is used. const unsigned *CSRegs = getCalleeSavedRegs(); @@ -1022,13 +1051,14 @@ return Offset - AFI->getDPRCalleeSavedAreaOffset(); // When dynamically realigning the stack, use the frame pointer for - // parameters, and the stack pointer for locals. + // parameters, and the stack/base pointer for locals. if (needsStackRealignment(MF)) { assert (hasFP(MF) && "dynamic stack realignment without a FP!"); if (isFixed) { FrameReg = getFrameRegister(MF); Offset = FPOffset; - } + } else if (MFI->hasVarSizedObjects()) + FrameReg = BasePtr; return Offset; } @@ -1036,9 +1066,13 @@ if (hasFP(MF) && AFI->hasStackFrame()) { // Use frame pointer to reference fixed objects. Use it for locals if // there are VLAs (and thus the SP isn't reliable as a base). - if (isFixed || MFI->hasVarSizedObjects()) { + if (isFixed || (MFI->hasVarSizedObjects() && !hasBasePointer(MF))) { FrameReg = getFrameRegister(MF); Offset = FPOffset; + } else if (MFI->hasVarSizedObjects()) { + assert(hasBasePointer(MF) && "missing base pointer!"); + // Use the base register since we have it. + FrameReg = BasePtr; } else if (AFI->isThumb2Function()) { // In Thumb2 mode, the negative offset is very limited. Try to avoid // out of range references. @@ -1052,6 +1086,9 @@ Offset = FPOffset; } } + // Use the base pointer if we have one. + if (hasBasePointer(MF)) + FrameReg = BasePtr; return Offset; } @@ -1089,7 +1126,8 @@ case ARM::R5: return ARM::R4; case ARM::R7: - return isReservedReg(MF, ARM::R7) ? 0 : ARM::R6; + return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6)) + ? 0 : ARM::R6; case ARM::R9: return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8; case ARM::R11: @@ -1178,7 +1216,8 @@ case ARM::R4: return ARM::R5; case ARM::R6: - return isReservedReg(MF, ARM::R7) ? 0 : ARM::R7; + return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6)) + ? 0 : ARM::R7; case ARM::R8: return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9; case ARM::R10: @@ -1878,6 +1917,20 @@ AFI->setShouldRestoreSPFromFP(true); } + // If we need a base pointer, set it up here. It's whatever the value + // of the stack pointer is at this point. Any variable size objects + // will be allocated after this, so we can still use the base pointer + // to reference locals. + if (hasBasePointer(MF)) { + if (isARM) + BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), BasePtr) + .addReg(ARM::SP) + .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); + else + BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), BasePtr) + .addReg(ARM::SP); + } + // If the frame has variable sized objects then the epilogue must restore // the sp from fp. if (!AFI->shouldRestoreSPFromFP() && MFI->hasVarSizedObjects()) Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h?rev=112989&r1=112988&r2=112989&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h Fri Sep 3 13:37:12 2010 @@ -52,6 +52,11 @@ /// FramePtr - ARM physical register used as frame ptr. unsigned FramePtr; + /// BasePtr - ARM physical register used as a base ptr in complex stack + /// frames. I.e., when we need a 3rd base, not just SP and FP, due to + /// variable size stack objects. + unsigned BasePtr; + // Can be only subclassed. explicit ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI); @@ -102,6 +107,7 @@ MachineFunction &MF) const; bool hasFP(const MachineFunction &MF) const; + bool hasBasePointer(const MachineFunction &MF) const; bool canRealignStack(const MachineFunction &MF) const; bool needsStackRealignment(const MachineFunction &MF) const; Modified: llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp?rev=112989&r1=112988&r2=112989&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp Fri Sep 3 13:37:12 2010 @@ -604,9 +604,12 @@ else if (MF.getFrameInfo()->hasVarSizedObjects()) { assert(SPAdj == 0 && hasFP(MF) && "Unexpected"); // There are alloca()'s in this function, must reference off the frame - // pointer instead. - FrameReg = getFrameRegister(MF); - Offset -= AFI->getFramePtrSpillOffset(); + // pointer or base pointer instead. + if (!hasBasePointer(MF)) { + FrameReg = getFrameRegister(MF); + Offset -= AFI->getFramePtrSpillOffset(); + } else + FrameReg = BasePtr; } // Special handling of dbg_value instructions. @@ -787,6 +790,13 @@ AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); AFI->setDPRCalleeSavedAreaSize(DPRCSSize); + + // If we need a base pointer, set it up here. It's whatever the value + // of the stack pointer is at this point. Any variable size objects + // will be allocated after this, so we can still use the base pointer + // to reference locals. + if (hasBasePointer(MF)) + BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), BasePtr).addReg(ARM::SP); } static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) { Modified: llvm/trunk/test/CodeGen/Thumb/dyn-stackalloc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/dyn-stackalloc.ll?rev=112989&r1=112988&r2=112989&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/dyn-stackalloc.ll (original) +++ llvm/trunk/test/CodeGen/Thumb/dyn-stackalloc.ll Fri Sep 3 13:37:12 2010 @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=thumb | not grep {ldr sp} ; RUN: llc < %s -mtriple=thumb-apple-darwin | \ ; RUN: not grep {sub.*r7} -; RUN: llc < %s -march=thumb | grep 4294967280 +; RUN: llc < %s -march=thumb | grep {mov.*r6, sp} %struct.state = type { i32, %struct.info*, float**, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64, i64, i64, i64, i64, i64, i8* } %struct.info = type { i32, i32, i32, i32, i32, i32, i32, i8* } Modified: llvm/trunk/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll?rev=112989&r1=112988&r2=112989&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll Fri Sep 3 13:37:12 2010 @@ -7,19 +7,12 @@ define void @t() nounwind ssp { entry: ; CHECK: t: -; CHECK: push {r4, r7} -; CHECK: mov r0, sp -; CHECK: add r7, sp, #4 -; CHECK: bic r0, r0, #7 + %size = mul i32 8, 2 ; CHECK: subs r0, #16 ; CHECK: mov sp, r0 -; CHECK: mov r0, sp -; CHECK: bic r0, r0, #7 + %vla_a = alloca i8, i32 %size, align 8 ; CHECK: subs r0, #16 ; CHECK: mov sp, r0 - - %size = mul i32 8, 2 - %vla_a = alloca i8, i32 %size, align 8 %vla_b = alloca i8, i32 %size, align 8 unreachable } From resistor at mac.com Fri Sep 3 14:08:37 2010 From: resistor at mac.com (Owen Anderson) Date: Fri, 03 Sep 2010 19:08:37 -0000 Subject: [llvm-commits] [llvm] r112994 - in /llvm/trunk: lib/Analysis/LazyValueInfo.cpp lib/Transforms/Scalar/CorrelatedValuePropagation.cpp test/Transforms/CorrelatedValuePropagation/basic.ll Message-ID: <20100903190837.375F92A6C12C@llvm.org> Author: resistor Date: Fri Sep 3 14:08:37 2010 New Revision: 112994 URL: http://llvm.org/viewvc/llvm-project?rev=112994&view=rev Log: Add support for simplifying a load from a computed value to a load from a global when it is provable that they're equivalent. This fixes PR4855. Modified: llvm/trunk/lib/Analysis/LazyValueInfo.cpp llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp llvm/trunk/test/Transforms/CorrelatedValuePropagation/basic.ll Modified: llvm/trunk/lib/Analysis/LazyValueInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/LazyValueInfo.cpp?rev=112994&r1=112993&r2=112994&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/LazyValueInfo.cpp (original) +++ llvm/trunk/lib/Analysis/LazyValueInfo.cpp Fri Sep 3 14:08:37 2010 @@ -452,14 +452,15 @@ // If this is a pointer, and there's a load from that pointer in this BB, // then we know that the pointer can't be NULL. + bool NotNull = false; if (Val->getType()->isPointerTy()) { - const PointerType *PTy = cast(Val->getType()); for (BasicBlock::iterator BI = BB->begin(), BE = BB->end();BI != BE;++BI){ LoadInst *L = dyn_cast(BI); if (L && L->getPointerAddressSpace() == 0 && L->getPointerOperand()->getUnderlyingObject() == Val->getUnderlyingObject()) { - return LVILatticeVal::getNot(ConstantPointerNull::get(PTy)); + NotNull = true; + break; } } } @@ -475,11 +476,19 @@ if (Result.isOverdefined()) { DEBUG(dbgs() << " compute BB '" << BB->getName() << "' - overdefined because of pred.\n"); + // If we previously determined that this is a pointer that can't be null + // then return that rather than giving up entirely. + if (NotNull) { + const PointerType *PTy = cast(Val->getType()); + Result = LVILatticeVal::getNot(ConstantPointerNull::get(PTy)); + } + return Result; } ++NumPreds; } + // If this is the entry block, we must be asking about an argument. The // value is overdefined. if (NumPreds == 0 && BB == &BB->getParent()->front()) { Modified: llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp?rev=112994&r1=112993&r2=112994&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp Fri Sep 3 14:08:37 2010 @@ -21,8 +21,9 @@ #include "llvm/ADT/Statistic.h" using namespace llvm; -STATISTIC(NumPhis, "Number of phis propagated"); -STATISTIC(NumSelects, "Number of selects propagated"); +STATISTIC(NumPhis, "Number of phis propagated"); +STATISTIC(NumSelects, "Number of selects propagated"); +STATISTIC(NumMemAccess, "Number of memory access targets propagated"); namespace { class CorrelatedValuePropagation : public FunctionPass { @@ -30,6 +31,7 @@ bool processSelect(SelectInst *SI); bool processPHI(PHINode *P); + bool processMemAccess(Instruction *I); public: static char ID; @@ -54,6 +56,7 @@ bool CorrelatedValuePropagation::processSelect(SelectInst *S) { if (S->getType()->isVectorTy()) return false; + if (isa(S->getOperand(0))) return false; Constant *C = LVI->getConstant(S->getOperand(0), S->getParent()); if (!C) return false; @@ -97,6 +100,23 @@ return Changed; } +bool CorrelatedValuePropagation::processMemAccess(Instruction *I) { + Value *Pointer = 0; + if (LoadInst *L = dyn_cast(I)) + Pointer = L->getPointerOperand(); + else + Pointer = cast(I)->getPointerOperand(); + + if (isa(Pointer)) return false; + + Constant *C = LVI->getConstant(Pointer, I->getParent()); + if (!C) return false; + + ++NumMemAccess; + I->replaceUsesOfWith(Pointer, C); + return true; +} + bool CorrelatedValuePropagation::runOnFunction(Function &F) { LVI = &getAnalysis(); @@ -106,10 +126,18 @@ bool BBChanged = false; for (BasicBlock::iterator BI = FI->begin(), BE = FI->end(); BI != BE; ) { Instruction *II = BI++; - if (SelectInst *SI = dyn_cast(II)) - BBChanged |= processSelect(SI); - else if (PHINode *P = dyn_cast(II)) - BBChanged |= processPHI(P); + switch (II->getOpcode()) { + case Instruction::Select: + BBChanged |= processSelect(cast(II)); + break; + case Instruction::PHI: + BBChanged |= processPHI(cast(II)); + break; + case Instruction::Load: + case Instruction::Store: + BBChanged |= processMemAccess(II); + break; + } } // Propagating correlated values might leave cruft around. Modified: llvm/trunk/test/Transforms/CorrelatedValuePropagation/basic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/CorrelatedValuePropagation/basic.ll?rev=112994&r1=112993&r2=112994&view=diff ============================================================================== --- llvm/trunk/test/Transforms/CorrelatedValuePropagation/basic.ll (original) +++ llvm/trunk/test/Transforms/CorrelatedValuePropagation/basic.ll Fri Sep 3 14:08:37 2010 @@ -39,3 +39,21 @@ ; CHECK: ret i1 %res ret i1 %res } + +; PR4855 + at gv = internal constant i8 7 +; CHECK: @test3 +define i8 @test3(i8* %a) nounwind { +entry: + %cond = icmp eq i8* %a, @gv + br i1 %cond, label %bb2, label %bb + +bb: ; preds = %entry + ret i8 0 + +bb2: ; preds = %entry +; CHECK-NOT: load i8* %a + %should_be_const = load i8* %a +; CHECK: ret i8 7 + ret i8 %should_be_const +} \ No newline at end of file From isanbard at gmail.com Fri Sep 3 14:09:46 2010 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 03 Sep 2010 19:09:46 -0000 Subject: [llvm-commits] [llvm] r112995 - /llvm/trunk/lib/MC/MCMachOStreamer.cpp Message-ID: <20100903190947.04AE12A6C12C@llvm.org> Author: void Date: Fri Sep 3 14:09:46 2010 New Revision: 112995 URL: http://llvm.org/viewvc/llvm-project?rev=112995&view=rev Log: Get rid of "passing signed into unsigned parameter" warning on PPC. Modified: llvm/trunk/lib/MC/MCMachOStreamer.cpp Modified: llvm/trunk/lib/MC/MCMachOStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCMachOStreamer.cpp?rev=112995&r1=112994&r2=112995&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCMachOStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCMachOStreamer.cpp Fri Sep 3 14:09:46 2010 @@ -548,7 +548,7 @@ // Minimum line offset in a special line info. opcode. This value // was chosen to give a reasonable range of values. */ // DWARF2_LINE_BASE - EmitIntValue(-5, 1); + EmitIntValue(uint64_t(-5), 1); // Range of line offsets in a special line info. opcode. // DWARF2_LINE_RANGE EmitIntValue(14, 1); From bob.wilson at apple.com Fri Sep 3 14:20:37 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Fri, 03 Sep 2010 19:20:37 -0000 Subject: [llvm-commits] [llvm] r112997 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <20100903192037.E5A382A6C12C@llvm.org> Author: bwilson Date: Fri Sep 3 14:20:37 2010 New Revision: 112997 URL: http://llvm.org/viewvc/llvm-project?rev=112997&view=rev Log: Add a missing check when legalizing a vector extending load. This doesn't solve the root problem, but it corrects the bug in the code I added to support legalizing in the case where the non-extended type is also legal. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=112997&r1=112996&r2=112997&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Sep 3 14:20:37 2010 @@ -1313,9 +1313,7 @@ } break; case TargetLowering::Expand: - if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT)) { - // FIXME: If SrcVT isn't legal, then this introduces an illegal - // type. + if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && isTypeLegal(SrcVT)) { SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(), LD->getSrcValueOffset(), LD->isVolatile(), LD->isNonTemporal(), @@ -1335,6 +1333,10 @@ Tmp2 = LegalizeOp(Load.getValue(1)); break; } + // FIXME: This does not work for vectors on most targets. Sign- and + // zero-extend operations are currently folded into extending loads, + // whether they are legal or not, and then we end up here without any + // support for legalizing them. assert(ExtType != ISD::EXTLOAD && "EXTLOAD should always be supported!"); // Turn the unsupported load into an EXTLOAD followed by an explicit From daniel at zuster.org Fri Sep 3 14:38:06 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Fri, 03 Sep 2010 19:38:06 -0000 Subject: [llvm-commits] [llvm] r112998 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20100903193806.2AB142A6C12C@llvm.org> Author: ddunbar Date: Fri Sep 3 14:38:05 2010 New Revision: 112998 URL: http://llvm.org/viewvc/llvm-project?rev=112998&view=rev Log: Revert r112942, "Use punpckh and unpckh family of nodes instead of using unpckh mask pattern fragment", which depends on r112934, which introduced some infinite loop and select failures. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=112998&r1=112997&r2=112998&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Sep 3 14:38:05 2010 @@ -2609,11 +2609,9 @@ case X86ISD::PUNPCKLDQ: case X86ISD::PUNPCKLQDQ: case X86ISD::UNPCKHPS: - case X86ISD::UNPCKHPD: case X86ISD::PUNPCKHWD: case X86ISD::PUNPCKHBW: case X86ISD::PUNPCKHDQ: - case X86ISD::PUNPCKHQDQ: return true; } return false; @@ -2674,11 +2672,9 @@ case X86ISD::PUNPCKLDQ: case X86ISD::PUNPCKLQDQ: case X86ISD::UNPCKHPS: - case X86ISD::UNPCKHPD: case X86ISD::PUNPCKHWD: case X86ISD::PUNPCKHBW: case X86ISD::PUNPCKHDQ: - case X86ISD::PUNPCKHQDQ: return DAG.getNode(Opc, dl, VT, V1, V2); } return SDValue(); @@ -5227,20 +5223,6 @@ return 0; } -static unsigned getUNPCKHOpcode(EVT VT) { - switch(VT.getSimpleVT().SimpleTy) { - case MVT::v4i32: return X86ISD::PUNPCKHDQ; - case MVT::v2i64: return X86ISD::PUNPCKHQDQ; - case MVT::v4f32: return X86ISD::UNPCKHPS; - case MVT::v2f64: return X86ISD::UNPCKHPD; - case MVT::v16i8: return X86ISD::PUNPCKHBW; - case MVT::v8i16: return X86ISD::PUNPCKHWD; - default: - llvm_unreachable("Unknow type for unpckh"); - } - return 0; -} - SDValue X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { ShuffleVectorSDNode *SVOp = cast(Op); @@ -5431,8 +5413,7 @@ Op : getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V2, DAG); if (X86::isUNPCKHMask(SVOp)) - return (isMMX) ? - Op : getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V2, DAG); + return Op; if (V2IsSplat) { // Normalize mask so all entries that point to V2 points to its first @@ -5457,11 +5438,10 @@ if (X86::isUNPCKLMask(NewSVOp)) return (isMMX) ? - NewOp : getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V2, V1, DAG); + Op : getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V2, V1, DAG); if (X86::isUNPCKHMask(NewSVOp)) - return (isMMX) ? - NewOp : getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V2, V1, DAG); + return NewOp; } // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle. From daniel at zuster.org Fri Sep 3 14:38:08 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Fri, 03 Sep 2010 19:38:08 -0000 Subject: [llvm-commits] [llvm] r112999 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20100903193808.D71D62A6C12D@llvm.org> Author: ddunbar Date: Fri Sep 3 14:38:08 2010 New Revision: 112999 URL: http://llvm.org/viewvc/llvm-project?rev=112999&view=rev Log: Revert r112938 "Fix comment", which depends on r112934, which introduced some infinite loop and select failures. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=112999&r1=112998&r2=112999&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Sep 3 14:38:08 2010 @@ -9787,9 +9787,9 @@ return EltsFromConsecutiveLoads(VT, Elts, dl, DAG); } -/// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index -/// generation and convert it from being a bunch of shuffles and extracts -/// to a simple store and scalar loads to extract the elements. +/// PerformShuffleCombine - Detect vector gather/scatter index generation +/// and convert it from being a bunch of shuffles and extracts to a simple +/// store and scalar loads to extract the elements. static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG, const TargetLowering &TLI) { SDValue InputVector = N->getOperand(0); From daniel at zuster.org Fri Sep 3 14:38:11 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Fri, 03 Sep 2010 19:38:11 -0000 Subject: [llvm-commits] [llvm] r113000 - in /llvm/trunk/lib/Target/X86: X86ISelLowering.cpp X86InstrSSE.td Message-ID: <20100903193811.CD9C52A6C12E@llvm.org> Author: ddunbar Date: Fri Sep 3 14:38:11 2010 New Revision: 113000 URL: http://llvm.org/viewvc/llvm-project?rev=113000&view=rev Log: Revert r112934, "- Use specific nodes to match unpckl masks.", which introduced some infinite loop and select failures. - Apologies for eager reverting, but its branch day. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=113000&r1=112999&r2=113000&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Sep 3 14:38:11 2010 @@ -15,7 +15,6 @@ #define DEBUG_TYPE "x86-isel" #include "X86.h" #include "X86InstrBuilder.h" -#include "X86ShuffleDecode.h" #include "X86ISelLowering.h" #include "X86TargetMachine.h" #include "X86TargetObjectFile.h" @@ -2603,11 +2602,9 @@ case X86ISD::MOVSS: case X86ISD::MOVSD: case X86ISD::UNPCKLPS: - case X86ISD::UNPCKLPD: case X86ISD::PUNPCKLWD: case X86ISD::PUNPCKLBW: case X86ISD::PUNPCKLDQ: - case X86ISD::PUNPCKLQDQ: case X86ISD::UNPCKHPS: case X86ISD::PUNPCKHWD: case X86ISD::PUNPCKHBW: @@ -2666,11 +2663,9 @@ case X86ISD::MOVSS: case X86ISD::MOVSD: case X86ISD::UNPCKLPS: - case X86ISD::UNPCKLPD: case X86ISD::PUNPCKLWD: case X86ISD::PUNPCKLBW: case X86ISD::PUNPCKLDQ: - case X86ISD::PUNPCKLQDQ: case X86ISD::UNPCKHPS: case X86ISD::PUNPCKHWD: case X86ISD::PUNPCKHBW: @@ -3703,60 +3698,7 @@ // Recurse into target specific vector shuffles to find scalars. if (isTargetShuffle(Opcode)) { - int NumElems = VT.getVectorNumElements(); - SmallVector ShuffleMask; - SDValue ImmN; - switch(Opcode) { - case X86ISD::SHUFPS: - case X86ISD::SHUFPD: - ImmN = N->getOperand(N->getNumOperands()-1); - DecodeSHUFPSMask(NumElems, - cast(ImmN)->getZExtValue(), - ShuffleMask); - break; - case X86ISD::PUNPCKHBW: - case X86ISD::PUNPCKHWD: - case X86ISD::PUNPCKHDQ: - case X86ISD::PUNPCKHQDQ: - DecodePUNPCKHMask(NumElems, ShuffleMask); - break; - case X86ISD::UNPCKHPS: - case X86ISD::UNPCKHPD: - DecodeUNPCKHPMask(NumElems, ShuffleMask); - break; - case X86ISD::PUNPCKLBW: - case X86ISD::PUNPCKLWD: - case X86ISD::PUNPCKLDQ: - case X86ISD::PUNPCKLQDQ: - DecodePUNPCKLMask(NumElems, ShuffleMask); - break; - case X86ISD::UNPCKLPS: - case X86ISD::UNPCKLPD: - DecodeUNPCKLPMask(NumElems, ShuffleMask); - break; - case X86ISD::MOVHLPS: - DecodeMOVHLPSMask(NumElems, ShuffleMask); - break; - case X86ISD::MOVLHPS: - DecodeMOVLHPSMask(NumElems, ShuffleMask); - break; - case X86ISD::PSHUFD: - ImmN = N->getOperand(N->getNumOperands()-1); - DecodePSHUFMask(NumElems, - cast(ImmN)->getZExtValue(), - ShuffleMask); - break; - case X86ISD::PSHUFHW: - ImmN = N->getOperand(N->getNumOperands()-1); - DecodePSHUFHWMask(cast(ImmN)->getZExtValue(), - ShuffleMask); - break; - case X86ISD::PSHUFLW: - ImmN = N->getOperand(N->getNumOperands()-1); - DecodePSHUFLWMask(cast(ImmN)->getZExtValue(), - ShuffleMask); - break; case X86ISD::MOVSS: case X86ISD::MOVSD: { // The index 0 always comes from the first element of the second source, @@ -3769,13 +3711,6 @@ assert("not implemented for target shuffle node"); return SDValue(); } - - Index = ShuffleMask[Index]; - if (Index < 0) - return DAG.getUNDEF(VT.getVectorElementType()); - - SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); - return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG); } // Actual nodes that may contain scalar elements @@ -5114,16 +5049,6 @@ return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); } -static bool MayFoldVectorLoad(SDValue V) { - if (V.hasOneUse() && V.getOpcode() == ISD::BIT_CONVERT) - V = V.getOperand(0); - if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) - V = V.getOperand(0); - if (MayFoldLoad(V)) - return true; - return false; -} - static SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) { @@ -5168,9 +5093,15 @@ // potencial load folding here, otherwise use SHUFPS or MOVSD to match the // same masks. bool CanFoldLoad = false; + SDValue TmpV1 = V1; + SDValue TmpV2 = V2; // Trivial case, when V2 comes from a load. - if (MayFoldVectorLoad(V2)) + if (TmpV2.hasOneUse() && TmpV2.getOpcode() == ISD::BIT_CONVERT) + TmpV2 = TmpV2.getOperand(0); + if (TmpV2.hasOneUse() && TmpV2.getOpcode() == ISD::SCALAR_TO_VECTOR) + TmpV2 = TmpV2.getOperand(0); + if (MayFoldLoad(TmpV2)) CanFoldLoad = true; // When V1 is a load, it can be folded later into a store in isel, example: @@ -5178,7 +5109,9 @@ // turns into: // (MOVLPSmr addr:$src1, VR128:$src2) // So, recognize this potential and also use MOVLPS or MOVLPD - if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op)) + if (TmpV1.hasOneUse() && TmpV1.getOpcode() == ISD::BIT_CONVERT) + TmpV1 = TmpV1.getOperand(0); + if (MayFoldLoad(TmpV1) && MayFoldIntoStore(Op)) CanFoldLoad = true; if (CanFoldLoad) { @@ -5209,20 +5142,6 @@ X86::getShuffleSHUFImmediate(SVOp), DAG); } -static unsigned getUNPCKLOpcode(EVT VT) { - switch(VT.getSimpleVT().SimpleTy) { - case MVT::v4i32: return X86ISD::PUNPCKLDQ; - case MVT::v2i64: return X86ISD::PUNPCKLQDQ; - case MVT::v4f32: return X86ISD::UNPCKLPS; - case MVT::v2f64: return X86ISD::UNPCKLPD; - case MVT::v16i8: return X86ISD::PUNPCKLBW; - case MVT::v8i16: return X86ISD::PUNPCKLWD; - default: - llvm_unreachable("Unknow type for unpckl"); - } - return 0; -} - SDValue X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { ShuffleVectorSDNode *SVOp = cast(Op); @@ -5353,8 +5272,7 @@ // FIXME: fold these into legal mask. if (!isMMX) { - if (X86::isMOVLHPSMask(SVOp) && - (!X86::isUNPCKLMask(SVOp) || MayFoldVectorLoad(V2))) + if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp)) return getMOVLowToHigh(Op, dl, DAG, HasSSE2); if (X86::isMOVHLPSMask(SVOp)) @@ -5408,11 +5326,8 @@ return getMOVL(DAG, dl, VT, V2, V1); } - if (X86::isUNPCKLMask(SVOp)) - return (isMMX) ? - Op : getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V2, DAG); - - if (X86::isUNPCKHMask(SVOp)) + if (X86::isUNPCKLMask(SVOp) || + X86::isUNPCKHMask(SVOp)) return Op; if (V2IsSplat) { @@ -5435,12 +5350,8 @@ // FIXME: this seems wrong. SDValue NewOp = CommuteVectorShuffle(SVOp, DAG); ShuffleVectorSDNode *NewSVOp = cast(NewOp); - - if (X86::isUNPCKLMask(NewSVOp)) - return (isMMX) ? - Op : getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V2, V1, DAG); - - if (X86::isUNPCKHMask(NewSVOp)) + if (X86::isUNPCKLMask(NewSVOp) || + X86::isUNPCKHMask(NewSVOp)) return NewOp; } @@ -10710,6 +10621,7 @@ SelectionDAG &DAG = DCI.DAG; switch (N->getOpcode()) { default: break; + case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this); case ISD::EXTRACT_VECTOR_ELT: return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this); case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget); @@ -10726,28 +10638,6 @@ case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG); - case X86ISD::SHUFPS: // Handle all target specific shuffles - case X86ISD::SHUFPD: - case X86ISD::PUNPCKHBW: - case X86ISD::PUNPCKHWD: - case X86ISD::PUNPCKHDQ: - case X86ISD::PUNPCKHQDQ: - case X86ISD::UNPCKHPS: - case X86ISD::UNPCKHPD: - case X86ISD::PUNPCKLBW: - case X86ISD::PUNPCKLWD: - case X86ISD::PUNPCKLDQ: - case X86ISD::PUNPCKLQDQ: - case X86ISD::UNPCKLPS: - case X86ISD::UNPCKLPD: - case X86ISD::MOVHLPS: - case X86ISD::MOVLHPS: - case X86ISD::PSHUFD: - case X86ISD::PSHUFHW: - case X86ISD::PSHUFLW: - case X86ISD::MOVSS: - case X86ISD::MOVSD: - case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this); } return SDValue(); Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=113000&r1=112999&r2=113000&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Fri Sep 3 14:38:11 2010 @@ -5819,13 +5819,6 @@ def : Pat<(v2f64 (X86Movlhpd VR128:$src1, (scalar_to_vector (loadf64 addr:$src2)))), (MOVHPDrm VR128:$src1, addr:$src2)>; -// FIXME: Instead of X86Unpcklpd, there should be a X86Movlhpd here, the problem -// is during lowering, where it's not possible to recognize the load fold cause -// it has two uses through a bitcast. One use disappears at isel time and the -// fold opportunity reappears. -def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, - (scalar_to_vector (loadf64 addr:$src2)))), - (MOVHPDrm VR128:$src1, addr:$src2)>; // Shuffle with MOVSS def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))), From bruno.cardoso at gmail.com Fri Sep 3 14:55:05 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Fri, 03 Sep 2010 19:55:05 -0000 Subject: [llvm-commits] [llvm] r113006 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20100903195506.0AEED2A6C12C@llvm.org> Author: bruno Date: Fri Sep 3 14:55:05 2010 New Revision: 113006 URL: http://llvm.org/viewvc/llvm-project?rev=113006&view=rev Log: Reapply Fix comment Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=113006&r1=113005&r2=113006&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Sep 3 14:55:05 2010 @@ -9698,9 +9698,9 @@ return EltsFromConsecutiveLoads(VT, Elts, dl, DAG); } -/// PerformShuffleCombine - Detect vector gather/scatter index generation -/// and convert it from being a bunch of shuffles and extracts to a simple -/// store and scalar loads to extract the elements. +/// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index +/// generation and convert it from being a bunch of shuffles and extracts +/// to a simple store and scalar loads to extract the elements. static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG, const TargetLowering &TLI) { SDValue InputVector = N->getOperand(0); From bruno.cardoso at gmail.com Fri Sep 3 15:10:35 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Fri, 03 Sep 2010 20:10:35 -0000 Subject: [llvm-commits] [llvm] r113007 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20100903201035.67E452A6C12C@llvm.org> Author: bruno Date: Fri Sep 3 15:10:35 2010 New Revision: 113007 URL: http://llvm.org/viewvc/llvm-project?rev=113007&view=rev Log: Reapply piecies of r112942 and r112934 which don't do functional changes Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=113007&r1=113006&r2=113007&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Sep 3 15:10:35 2010 @@ -2602,13 +2602,17 @@ case X86ISD::MOVSS: case X86ISD::MOVSD: case X86ISD::UNPCKLPS: + case X86ISD::UNPCKLPD: case X86ISD::PUNPCKLWD: case X86ISD::PUNPCKLBW: case X86ISD::PUNPCKLDQ: + case X86ISD::PUNPCKLQDQ: case X86ISD::UNPCKHPS: + case X86ISD::UNPCKHPD: case X86ISD::PUNPCKHWD: case X86ISD::PUNPCKHBW: case X86ISD::PUNPCKHDQ: + case X86ISD::PUNPCKHQDQ: return true; } return false; @@ -2663,13 +2667,17 @@ case X86ISD::MOVSS: case X86ISD::MOVSD: case X86ISD::UNPCKLPS: + case X86ISD::UNPCKLPD: case X86ISD::PUNPCKLWD: case X86ISD::PUNPCKLBW: case X86ISD::PUNPCKLDQ: + case X86ISD::PUNPCKLQDQ: case X86ISD::UNPCKHPS: + case X86ISD::UNPCKHPD: case X86ISD::PUNPCKHWD: case X86ISD::PUNPCKHBW: case X86ISD::PUNPCKHDQ: + case X86ISD::PUNPCKHQDQ: return DAG.getNode(Opc, dl, VT, V1, V2); } return SDValue(); @@ -5142,6 +5150,34 @@ X86::getShuffleSHUFImmediate(SVOp), DAG); } +static inline unsigned getUNPCKLOpcode(EVT VT) { + switch(VT.getSimpleVT().SimpleTy) { + case MVT::v4i32: return X86ISD::PUNPCKLDQ; + case MVT::v2i64: return X86ISD::PUNPCKLQDQ; + case MVT::v4f32: return X86ISD::UNPCKLPS; + case MVT::v2f64: return X86ISD::UNPCKLPD; + case MVT::v16i8: return X86ISD::PUNPCKLBW; + case MVT::v8i16: return X86ISD::PUNPCKLWD; + default: + llvm_unreachable("Unknow type for unpckl"); + } + return 0; +} + +static inline unsigned getUNPCKHOpcode(EVT VT) { + switch(VT.getSimpleVT().SimpleTy) { + case MVT::v4i32: return X86ISD::PUNPCKHDQ; + case MVT::v2i64: return X86ISD::PUNPCKHQDQ; + case MVT::v4f32: return X86ISD::UNPCKHPS; + case MVT::v2f64: return X86ISD::UNPCKHPD; + case MVT::v16i8: return X86ISD::PUNPCKHBW; + case MVT::v8i16: return X86ISD::PUNPCKHWD; + default: + llvm_unreachable("Unknow type for unpckh"); + } + return 0; +} + SDValue X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { ShuffleVectorSDNode *SVOp = cast(Op); From bruno.cardoso at gmail.com Fri Sep 3 15:20:02 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Fri, 03 Sep 2010 20:20:02 -0000 Subject: [llvm-commits] [llvm] r113008 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20100903202003.0D6F52A6C12C@llvm.org> Author: bruno Date: Fri Sep 3 15:20:02 2010 New Revision: 113008 URL: http://llvm.org/viewvc/llvm-project?rev=113008&view=rev Log: Reintroduce a simple function refactoring done in r112934, also without any functionality changes Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=113008&r1=113007&r2=113008&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Sep 3 15:20:02 2010 @@ -5057,6 +5057,16 @@ return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); } +static bool MayFoldVectorLoad(SDValue V) { + if (V.hasOneUse() && V.getOpcode() == ISD::BIT_CONVERT) + V = V.getOperand(0); + if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) + V = V.getOperand(0); + if (MayFoldLoad(V)) + return true; + return false; +} + static SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) { @@ -5101,15 +5111,9 @@ // potencial load folding here, otherwise use SHUFPS or MOVSD to match the // same masks. bool CanFoldLoad = false; - SDValue TmpV1 = V1; - SDValue TmpV2 = V2; // Trivial case, when V2 comes from a load. - if (TmpV2.hasOneUse() && TmpV2.getOpcode() == ISD::BIT_CONVERT) - TmpV2 = TmpV2.getOperand(0); - if (TmpV2.hasOneUse() && TmpV2.getOpcode() == ISD::SCALAR_TO_VECTOR) - TmpV2 = TmpV2.getOperand(0); - if (MayFoldLoad(TmpV2)) + if (MayFoldVectorLoad(V2)) CanFoldLoad = true; // When V1 is a load, it can be folded later into a store in isel, example: @@ -5117,9 +5121,7 @@ // turns into: // (MOVLPSmr addr:$src1, VR128:$src2) // So, recognize this potential and also use MOVLPS or MOVLPD - if (TmpV1.hasOneUse() && TmpV1.getOpcode() == ISD::BIT_CONVERT) - TmpV1 = TmpV1.getOperand(0); - if (MayFoldLoad(TmpV1) && MayFoldIntoStore(Op)) + if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op)) CanFoldLoad = true; if (CanFoldLoad) { From bruno.cardoso at gmail.com Fri Sep 3 15:44:26 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Fri, 03 Sep 2010 20:44:26 -0000 Subject: [llvm-commits] [llvm] r113009 - /llvm/trunk/lib/Target/X86/X86InstrSSE.td Message-ID: <20100903204427.0DB182A6C12C@llvm.org> Author: bruno Date: Fri Sep 3 15:44:26 2010 New Revision: 113009 URL: http://llvm.org/viewvc/llvm-project?rev=113009&view=rev Log: Reapply last harmless part of r112934, the pattern fragment to match X86Unpcklpd Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=113009&r1=113008&r2=113009&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Fri Sep 3 15:44:26 2010 @@ -5819,6 +5819,13 @@ def : Pat<(v2f64 (X86Movlhpd VR128:$src1, (scalar_to_vector (loadf64 addr:$src2)))), (MOVHPDrm VR128:$src1, addr:$src2)>; +// FIXME: Instead of X86Unpcklpd, there should be a X86Movlhpd here, the problem +// is during lowering, where it's not possible to recognize the load fold cause +// it has two uses through a bitcast. One use disappears at isel time and the +// fold opportunity reappears. +def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, + (scalar_to_vector (loadf64 addr:$src2)))), + (MOVHPDrm VR128:$src1, addr:$src2)>; // Shuffle with MOVSS def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))), From greened at obbligato.org Fri Sep 3 16:00:49 2010 From: greened at obbligato.org (David Greene) Date: Fri, 03 Sep 2010 21:00:49 -0000 Subject: [llvm-commits] [llvm] r113010 - in /llvm/trunk: test/TableGen/FieldAccess.td test/TableGen/ListManip.td utils/TableGen/Record.cpp utils/TableGen/Record.h Message-ID: <20100903210049.C70622A6C12C@llvm.org> Author: greened Date: Fri Sep 3 16:00:49 2010 New Revision: 113010 URL: http://llvm.org/viewvc/llvm-project?rev=113010&view=rev Log: Generalize getFieldType to work on all TypedInits. Add a couple of testcases from Amaury Pouly. Added: llvm/trunk/test/TableGen/FieldAccess.td llvm/trunk/test/TableGen/ListManip.td Modified: llvm/trunk/utils/TableGen/Record.cpp llvm/trunk/utils/TableGen/Record.h Added: llvm/trunk/test/TableGen/FieldAccess.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/TableGen/FieldAccess.td?rev=113010&view=auto ============================================================================== --- llvm/trunk/test/TableGen/FieldAccess.td (added) +++ llvm/trunk/test/TableGen/FieldAccess.td Fri Sep 3 16:00:49 2010 @@ -0,0 +1,14 @@ +// RUN: tblgen %s +class Bla +{ + string blu = t; +} + +class Bli +{ + Bla bla = t; +} + +def a : Bli>; +def b : Bla(a.bla).blu>; // works +def c : Bla; // doesn't work: Cannot access field 'blu' of value 'a.bla' Added: llvm/trunk/test/TableGen/ListManip.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/TableGen/ListManip.td?rev=113010&view=auto ============================================================================== --- llvm/trunk/test/TableGen/ListManip.td (added) +++ llvm/trunk/test/TableGen/ListManip.td Fri Sep 3 16:00:49 2010 @@ -0,0 +1,10 @@ +// RUN: tblgen %s +class Bli +{ + string t = _t; +} + +class Bla _bli> +: Bli +{ +} Modified: llvm/trunk/utils/TableGen/Record.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/Record.cpp?rev=113010&r1=113009&r2=113010&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/Record.cpp (original) +++ llvm/trunk/utils/TableGen/Record.cpp Fri Sep 3 16:00:49 2010 @@ -628,23 +628,6 @@ return Result + "(" + LHS->getAsString() + ")"; } -RecTy *UnOpInit::getFieldType(const std::string &FieldName) const { - switch (getOpcode()) { - default: assert(0 && "Unknown unop"); - case CAST: { - RecordRecTy *RecordType = dynamic_cast(getType()); - if (RecordType) { - RecordVal *Field = RecordType->getRecord()->getValue(FieldName); - if (Field) { - return Field->getType(); - } - } - break; - } - } - return 0; -} - Init *BinOpInit::Fold(Record *CurRec, MultiClass *CurMultiClass) { switch (getOpcode()) { default: assert(0 && "Unknown binop"); @@ -1046,6 +1029,17 @@ + RHS->getAsString() + ")"; } +RecTy *TypedInit::getFieldType(const std::string &FieldName) const { + RecordRecTy *RecordType = dynamic_cast(getType()); + if (RecordType) { + RecordVal *Field = RecordType->getRecord()->getValue(FieldName); + if (Field) { + return Field->getType(); + } + } + return 0; +} + Init *TypedInit::convertInitializerBitRange(const std::vector &Bits) { BitsRecTy *T = dynamic_cast(getType()); if (T == 0) return 0; // Cannot subscript a non-bits variable... Modified: llvm/trunk/utils/TableGen/Record.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/Record.h?rev=113010&r1=113009&r2=113010&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/Record.h (original) +++ llvm/trunk/utils/TableGen/Record.h Fri Sep 3 16:00:49 2010 @@ -535,6 +535,12 @@ virtual Init *convertInitializerBitRange(const std::vector &Bits); virtual Init *convertInitListSlice(const std::vector &Elements); + /// getFieldType - This method is used to implement the FieldInit class. + /// Implementors of this method should return the type of the named field if + /// they are of record type. + /// + virtual RecTy *getFieldType(const std::string &FieldName) const; + /// resolveBitReference - This method is used to implement /// VarBitInit::resolveReferences. If the bit is able to be resolved, we /// simply return the resolved value, otherwise we return null. @@ -835,12 +841,6 @@ virtual Init *resolveReferences(Record &R, const RecordVal *RV); - /// getFieldType - This method is used to implement the FieldInit class. - /// Implementors of this method should return the type of the named field if - /// they are of record type. - /// - virtual RecTy *getFieldType(const std::string &FieldName) const; - virtual std::string getAsString() const; }; From dalej at apple.com Fri Sep 3 16:23:00 2010 From: dalej at apple.com (Dale Johannesen) Date: Fri, 03 Sep 2010 21:23:00 -0000 Subject: [llvm-commits] [llvm] r113014 - in /llvm/trunk: lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/avx-intrinsics-x86.ll Message-ID: <20100903212300.7B5702A6C12C@llvm.org> Author: johannes Date: Fri Sep 3 16:23:00 2010 New Revision: 113014 URL: http://llvm.org/viewvc/llvm-project?rev=113014&view=rev Log: Remove the rest of the nonexistent 64-bit AVX instructions. Bruno, please review. Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=113014&r1=113013&r2=113014&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Fri Sep 3 16:23:00 2010 @@ -3592,26 +3592,9 @@ /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}. multiclass SS3I_binop_rm_int opc, string OpcodeStr, - PatFrag mem_frag64, PatFrag mem_frag128, - Intrinsic IntId64, Intrinsic IntId128, + PatFrag mem_frag128, Intrinsic IntId128, bit Is2Addr = 1> { let isCommutable = 1 in - def rr64 : SS38I; - def rm64 : SS38I; - - let isCommutable = 1 in def rr128 : SS38I, OpSize; } +multiclass SS3I_binop_rm_int_mm opc, string OpcodeStr, + PatFrag mem_frag64, Intrinsic IntId64> { + let isCommutable = 1 in + def rr64 : SS38I; + def rm64 : SS38I; +} let isAsmParserOnly = 1, Predicates = [HasAVX] in { let isCommutable = 0 in { - defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw", memopv4i16, memopv8i16, - int_x86_ssse3_phadd_w, + defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw", memopv8i16, int_x86_ssse3_phadd_w_128, 0>, VEX_4V; - defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd", memopv2i32, memopv4i32, - int_x86_ssse3_phadd_d, + defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd", memopv4i32, int_x86_ssse3_phadd_d_128, 0>, VEX_4V; - defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw", memopv4i16, memopv8i16, - int_x86_ssse3_phadd_sw, + defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw", memopv8i16, int_x86_ssse3_phadd_sw_128, 0>, VEX_4V; - defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw", memopv4i16, memopv8i16, - int_x86_ssse3_phsub_w, + defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw", memopv8i16, int_x86_ssse3_phsub_w_128, 0>, VEX_4V; - defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd", memopv2i32, memopv4i32, - int_x86_ssse3_phsub_d, + defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd", memopv4i32, int_x86_ssse3_phsub_d_128, 0>, VEX_4V; - defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw", memopv4i16, memopv8i16, - int_x86_ssse3_phsub_sw, + defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw", memopv8i16, int_x86_ssse3_phsub_sw_128, 0>, VEX_4V; - defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", memopv8i8, memopv16i8, - int_x86_ssse3_pmadd_ub_sw, + defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", memopv16i8, int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V; - defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb", memopv8i8, memopv16i8, - int_x86_ssse3_pshuf_b, + defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb", memopv16i8, int_x86_ssse3_pshuf_b_128, 0>, VEX_4V; - defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb", memopv8i8, memopv16i8, - int_x86_ssse3_psign_b, + defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb", memopv16i8, int_x86_ssse3_psign_b_128, 0>, VEX_4V; - defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw", memopv4i16, memopv8i16, - int_x86_ssse3_psign_w, + defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw", memopv8i16, int_x86_ssse3_psign_w_128, 0>, VEX_4V; - defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd", memopv2i32, memopv4i32, - int_x86_ssse3_psign_d, + defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd", memopv4i32, int_x86_ssse3_psign_d_128, 0>, VEX_4V; } -defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv4i16, memopv8i16, - int_x86_ssse3_pmul_hr_sw, +defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv8i16, int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V; } // None of these have i8 immediate fields. let ImmT = NoImm, Constraints = "$src1 = $dst" in { let isCommutable = 0 in { - defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw", memopv4i16, memopv8i16, - int_x86_ssse3_phadd_w, - int_x86_ssse3_phadd_w_128>; - defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd", memopv2i32, memopv4i32, - int_x86_ssse3_phadd_d, - int_x86_ssse3_phadd_d_128>; - defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", memopv4i16, memopv8i16, - int_x86_ssse3_phadd_sw, - int_x86_ssse3_phadd_sw_128>; - defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw", memopv4i16, memopv8i16, - int_x86_ssse3_phsub_w, - int_x86_ssse3_phsub_w_128>; - defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd", memopv2i32, memopv4i32, - int_x86_ssse3_phsub_d, - int_x86_ssse3_phsub_d_128>; - defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", memopv4i16, memopv8i16, - int_x86_ssse3_phsub_sw, - int_x86_ssse3_phsub_sw_128>; - defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv8i8, memopv16i8, - int_x86_ssse3_pmadd_ub_sw, - int_x86_ssse3_pmadd_ub_sw_128>; - defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", memopv8i8, memopv16i8, - int_x86_ssse3_pshuf_b, - int_x86_ssse3_pshuf_b_128>; - defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", memopv8i8, memopv16i8, - int_x86_ssse3_psign_b, - int_x86_ssse3_psign_b_128>; - defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", memopv4i16, memopv8i16, - int_x86_ssse3_psign_w, - int_x86_ssse3_psign_w_128>; - defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", memopv2i32, memopv4i32, - int_x86_ssse3_psign_d, - int_x86_ssse3_psign_d_128>; -} -defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv4i16, memopv8i16, - int_x86_ssse3_pmul_hr_sw, - int_x86_ssse3_pmul_hr_sw_128>; + defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw", memopv8i16, + int_x86_ssse3_phadd_w_128>, + SS3I_binop_rm_int_mm<0x01, "phaddw", memopv4i16, + int_x86_ssse3_phadd_w>; + defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd", memopv4i32, + int_x86_ssse3_phadd_d_128>, + SS3I_binop_rm_int_mm<0x02, "phaddd", memopv2i32, + int_x86_ssse3_phadd_d>; + defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", memopv8i16, + int_x86_ssse3_phadd_sw_128>, + SS3I_binop_rm_int_mm<0x03, "phaddsw", memopv4i16, + int_x86_ssse3_phadd_sw>; + defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw", memopv8i16, + int_x86_ssse3_phsub_w_128>, + SS3I_binop_rm_int_mm<0x05, "phsubw", memopv4i16, + int_x86_ssse3_phsub_w>; + defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd", memopv4i32, + int_x86_ssse3_phsub_d_128>, + SS3I_binop_rm_int_mm<0x06, "phsubd", memopv2i32, + int_x86_ssse3_phsub_d>; + defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", memopv8i16, + int_x86_ssse3_phsub_sw_128>, + SS3I_binop_rm_int_mm<0x07, "phsubsw", memopv4i16, + int_x86_ssse3_phsub_sw>; + defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv16i8, + int_x86_ssse3_pmadd_ub_sw_128>, + SS3I_binop_rm_int_mm<0x04, "pmaddubsw", memopv8i8, + int_x86_ssse3_pmadd_ub_sw>; + defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", memopv8i8, + int_x86_ssse3_pshuf_b_128>, + SS3I_binop_rm_int_mm<0x00, "pshufb", memopv8i8, + int_x86_ssse3_pshuf_b>; + defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", memopv16i8, + int_x86_ssse3_psign_b_128>, + SS3I_binop_rm_int_mm<0x08, "psignb", memopv8i8, + int_x86_ssse3_psign_b>; + defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", memopv8i16, + int_x86_ssse3_psign_w_128>, + SS3I_binop_rm_int_mm<0x09, "psignw", memopv4i16, + int_x86_ssse3_psign_w>; + defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", memopv4i32, + int_x86_ssse3_psign_d_128>, + SS3I_binop_rm_int_mm<0x0A, "psignd", memopv2i32, + int_x86_ssse3_psign_d>; +} +defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv8i16, + int_x86_ssse3_pmul_hr_sw_128>, + SS3I_binop_rm_int_mm<0x0B, "pmulhrsw", memopv4i16, + int_x86_ssse3_pmul_hr_sw>; } def : Pat<(X86pshufb VR128:$src, VR128:$mask), Modified: llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll?rev=113014&r1=113013&r2=113014&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll (original) +++ llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll Fri Sep 3 16:23:00 2010 @@ -1739,14 +1739,6 @@ declare <8 x i16> @llvm.x86.ssse3.pabs.w.128(<8 x i16>) nounwind readnone -define <2 x i32> @test_x86_ssse3_phadd_d(<2 x i32> %a0, <2 x i32> %a1) { - ; CHECK: vphaddd - %res = call <2 x i32> @llvm.x86.ssse3.phadd.d(<2 x i32> %a0, <2 x i32> %a1) ; <<2 x i32>> [#uses=1] - ret <2 x i32> %res -} -declare <2 x i32> @llvm.x86.ssse3.phadd.d(<2 x i32>, <2 x i32>) nounwind readnone - - define <4 x i32> @test_x86_ssse3_phadd_d_128(<4 x i32> %a0, <4 x i32> %a1) { ; CHECK: vphaddd %res = call <4 x i32> @llvm.x86.ssse3.phadd.d.128(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1] @@ -1755,14 +1747,6 @@ declare <4 x i32> @llvm.x86.ssse3.phadd.d.128(<4 x i32>, <4 x i32>) nounwind readnone -define <4 x i16> @test_x86_ssse3_phadd_sw(<4 x i16> %a0, <4 x i16> %a1) { - ; CHECK: vphaddsw - %res = call <4 x i16> @llvm.x86.ssse3.phadd.sw(<4 x i16> %a0, <4 x i16> %a1) ; <<4 x i16>> [#uses=1] - ret <4 x i16> %res -} -declare <4 x i16> @llvm.x86.ssse3.phadd.sw(<4 x i16>, <4 x i16>) nounwind readnone - - define <4 x i32> @test_x86_ssse3_phadd_sw_128(<4 x i32> %a0, <4 x i32> %a1) { ; CHECK: vphaddsw %res = call <4 x i32> @llvm.x86.ssse3.phadd.sw.128(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1] @@ -1771,14 +1755,6 @@ declare <4 x i32> @llvm.x86.ssse3.phadd.sw.128(<4 x i32>, <4 x i32>) nounwind readnone -define <4 x i16> @test_x86_ssse3_phadd_w(<4 x i16> %a0, <4 x i16> %a1) { - ; CHECK: vphaddw - %res = call <4 x i16> @llvm.x86.ssse3.phadd.w(<4 x i16> %a0, <4 x i16> %a1) ; <<4 x i16>> [#uses=1] - ret <4 x i16> %res -} -declare <4 x i16> @llvm.x86.ssse3.phadd.w(<4 x i16>, <4 x i16>) nounwind readnone - - define <8 x i16> @test_x86_ssse3_phadd_w_128(<8 x i16> %a0, <8 x i16> %a1) { ; CHECK: vphaddw %res = call <8 x i16> @llvm.x86.ssse3.phadd.w.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1] @@ -1787,14 +1763,6 @@ declare <8 x i16> @llvm.x86.ssse3.phadd.w.128(<8 x i16>, <8 x i16>) nounwind readnone -define <2 x i32> @test_x86_ssse3_phsub_d(<2 x i32> %a0, <2 x i32> %a1) { - ; CHECK: vphsubd - %res = call <2 x i32> @llvm.x86.ssse3.phsub.d(<2 x i32> %a0, <2 x i32> %a1) ; <<2 x i32>> [#uses=1] - ret <2 x i32> %res -} -declare <2 x i32> @llvm.x86.ssse3.phsub.d(<2 x i32>, <2 x i32>) nounwind readnone - - define <4 x i32> @test_x86_ssse3_phsub_d_128(<4 x i32> %a0, <4 x i32> %a1) { ; CHECK: vphsubd %res = call <4 x i32> @llvm.x86.ssse3.phsub.d.128(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1] @@ -1803,14 +1771,6 @@ declare <4 x i32> @llvm.x86.ssse3.phsub.d.128(<4 x i32>, <4 x i32>) nounwind readnone -define <4 x i16> @test_x86_ssse3_phsub_sw(<4 x i16> %a0, <4 x i16> %a1) { - ; CHECK: vphsubsw - %res = call <4 x i16> @llvm.x86.ssse3.phsub.sw(<4 x i16> %a0, <4 x i16> %a1) ; <<4 x i16>> [#uses=1] - ret <4 x i16> %res -} -declare <4 x i16> @llvm.x86.ssse3.phsub.sw(<4 x i16>, <4 x i16>) nounwind readnone - - define <8 x i16> @test_x86_ssse3_phsub_sw_128(<8 x i16> %a0, <8 x i16> %a1) { ; CHECK: vphsubsw %res = call <8 x i16> @llvm.x86.ssse3.phsub.sw.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1] @@ -1819,14 +1779,6 @@ declare <8 x i16> @llvm.x86.ssse3.phsub.sw.128(<8 x i16>, <8 x i16>) nounwind readnone -define <4 x i16> @test_x86_ssse3_phsub_w(<4 x i16> %a0, <4 x i16> %a1) { - ; CHECK: vphsubw - %res = call <4 x i16> @llvm.x86.ssse3.phsub.w(<4 x i16> %a0, <4 x i16> %a1) ; <<4 x i16>> [#uses=1] - ret <4 x i16> %res -} -declare <4 x i16> @llvm.x86.ssse3.phsub.w(<4 x i16>, <4 x i16>) nounwind readnone - - define <8 x i16> @test_x86_ssse3_phsub_w_128(<8 x i16> %a0, <8 x i16> %a1) { ; CHECK: vphsubw %res = call <8 x i16> @llvm.x86.ssse3.phsub.w.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1] @@ -1835,14 +1787,6 @@ declare <8 x i16> @llvm.x86.ssse3.phsub.w.128(<8 x i16>, <8 x i16>) nounwind readnone -define <4 x i16> @test_x86_ssse3_pmadd_ub_sw(<4 x i16> %a0, <4 x i16> %a1) { - ; CHECK: vpmaddubsw - %res = call <4 x i16> @llvm.x86.ssse3.pmadd.ub.sw(<4 x i16> %a0, <4 x i16> %a1) ; <<4 x i16>> [#uses=1] - ret <4 x i16> %res -} -declare <4 x i16> @llvm.x86.ssse3.pmadd.ub.sw(<4 x i16>, <4 x i16>) nounwind readnone - - define <8 x i16> @test_x86_ssse3_pmadd_ub_sw_128(<8 x i16> %a0, <8 x i16> %a1) { ; CHECK: vpmaddubsw %res = call <8 x i16> @llvm.x86.ssse3.pmadd.ub.sw.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1] @@ -1851,14 +1795,6 @@ declare <8 x i16> @llvm.x86.ssse3.pmadd.ub.sw.128(<8 x i16>, <8 x i16>) nounwind readnone -define <4 x i16> @test_x86_ssse3_pmul_hr_sw(<4 x i16> %a0, <4 x i16> %a1) { - ; CHECK: vpmulhrsw - %res = call <4 x i16> @llvm.x86.ssse3.pmul.hr.sw(<4 x i16> %a0, <4 x i16> %a1) ; <<4 x i16>> [#uses=1] - ret <4 x i16> %res -} -declare <4 x i16> @llvm.x86.ssse3.pmul.hr.sw(<4 x i16>, <4 x i16>) nounwind readnone - - define <8 x i16> @test_x86_ssse3_pmul_hr_sw_128(<8 x i16> %a0, <8 x i16> %a1) { ; CHECK: vpmulhrsw %res = call <8 x i16> @llvm.x86.ssse3.pmul.hr.sw.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1] @@ -1867,14 +1803,6 @@ declare <8 x i16> @llvm.x86.ssse3.pmul.hr.sw.128(<8 x i16>, <8 x i16>) nounwind readnone -define <8 x i8> @test_x86_ssse3_pshuf_b(<8 x i8> %a0, <8 x i8> %a1) { - ; CHECK: vpshufb - %res = call <8 x i8> @llvm.x86.ssse3.pshuf.b(<8 x i8> %a0, <8 x i8> %a1) ; <<8 x i8>> [#uses=1] - ret <8 x i8> %res -} -declare <8 x i8> @llvm.x86.ssse3.pshuf.b(<8 x i8>, <8 x i8>) nounwind readnone - - define <16 x i8> @test_x86_ssse3_pshuf_b_128(<16 x i8> %a0, <16 x i8> %a1) { ; CHECK: vpshufb %res = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1] @@ -1883,14 +1811,6 @@ declare <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8>, <16 x i8>) nounwind readnone -define <8 x i8> @test_x86_ssse3_psign_b(<8 x i8> %a0, <8 x i8> %a1) { - ; CHECK: vpsignb - %res = call <8 x i8> @llvm.x86.ssse3.psign.b(<8 x i8> %a0, <8 x i8> %a1) ; <<8 x i8>> [#uses=1] - ret <8 x i8> %res -} -declare <8 x i8> @llvm.x86.ssse3.psign.b(<8 x i8>, <8 x i8>) nounwind readnone - - define <16 x i8> @test_x86_ssse3_psign_b_128(<16 x i8> %a0, <16 x i8> %a1) { ; CHECK: vpsignb %res = call <16 x i8> @llvm.x86.ssse3.psign.b.128(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1] @@ -1899,14 +1819,6 @@ declare <16 x i8> @llvm.x86.ssse3.psign.b.128(<16 x i8>, <16 x i8>) nounwind readnone -define <2 x i32> @test_x86_ssse3_psign_d(<2 x i32> %a0, <2 x i32> %a1) { - ; CHECK: vpsignd - %res = call <2 x i32> @llvm.x86.ssse3.psign.d(<2 x i32> %a0, <2 x i32> %a1) ; <<2 x i32>> [#uses=1] - ret <2 x i32> %res -} -declare <2 x i32> @llvm.x86.ssse3.psign.d(<2 x i32>, <2 x i32>) nounwind readnone - - define <4 x i32> @test_x86_ssse3_psign_d_128(<4 x i32> %a0, <4 x i32> %a1) { ; CHECK: vpsignd %res = call <4 x i32> @llvm.x86.ssse3.psign.d.128(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1] @@ -1915,14 +1827,6 @@ declare <4 x i32> @llvm.x86.ssse3.psign.d.128(<4 x i32>, <4 x i32>) nounwind readnone -define <4 x i16> @test_x86_ssse3_psign_w(<4 x i16> %a0, <4 x i16> %a1) { - ; CHECK: vpsignw - %res = call <4 x i16> @llvm.x86.ssse3.psign.w(<4 x i16> %a0, <4 x i16> %a1) ; <<4 x i16>> [#uses=1] - ret <4 x i16> %res -} -declare <4 x i16> @llvm.x86.ssse3.psign.w(<4 x i16>, <4 x i16>) nounwind readnone - - define <8 x i16> @test_x86_ssse3_psign_w_128(<8 x i16> %a0, <8 x i16> %a1) { ; CHECK: vpsignw %res = call <8 x i16> @llvm.x86.ssse3.psign.w.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1] From grosbach at apple.com Fri Sep 3 16:45:15 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 03 Sep 2010 21:45:15 -0000 Subject: [llvm-commits] [llvm] r113016 - /llvm/trunk/lib/CodeGen/RegAllocFast.cpp Message-ID: <20100903214516.08C592A6C12C@llvm.org> Author: grosbach Date: Fri Sep 3 16:45:15 2010 New Revision: 113016 URL: http://llvm.org/viewvc/llvm-project?rev=113016&view=rev Log: previous patch was a little too tricky for its own good. Don't try to overload UserInInstr. Explicitly check Allocatable. The early exit in the condition will mean the performance impact of the extra test should be minimal. Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=113016&r1=113015&r2=113016&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocFast.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp Fri Sep 3 16:45:15 2010 @@ -113,9 +113,6 @@ // Allocatable - vector of allocatable physical registers. BitVector Allocatable; - // Reserved - vector of reserved physical registers. - BitVector Reserved; - // SkippedInstrs - Descriptors of instructions whose clobber list was // ignored because all registers were spilled. It is still necessary to // mark all the clobbered registers as used by the function. @@ -501,7 +498,8 @@ // First try to find a completely free register. for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) { unsigned PhysReg = *I; - if (PhysRegState[PhysReg] == regFree && !UsedInInstr.test(PhysReg)) + if (PhysRegState[PhysReg] == regFree && !UsedInInstr.test(PhysReg) && + Allocatable.test(PhysReg)) return assignVirtToPhysReg(LRE, PhysReg); } @@ -510,6 +508,8 @@ unsigned BestReg = 0, BestCost = spillImpossible; for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) { + if (!Allocatable.test(*I)) + continue; unsigned Cost = calcSpillCost(*I); // Cost is 0 when all aliases are already disabled. if (Cost == 0) @@ -712,7 +712,7 @@ } // Restore UsedInInstr to a state usable for allocating normal virtual uses. - UsedInInstr = Reserved; + UsedInInstr.reset(); for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); if (!MO.isReg() || (MO.isDef() && !MO.isEarlyClobber())) continue; @@ -838,7 +838,7 @@ } // Track registers used by instruction. - UsedInInstr = Reserved; + UsedInInstr.reset(); // First scan. // Mark physreg uses and early clobbers as used. @@ -916,7 +916,7 @@ // Track registers defined by instruction - early clobbers and tied uses at // this point. - UsedInInstr = Reserved; + UsedInInstr.reset(); if (hasEarlyClobbers) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); @@ -1014,7 +1014,6 @@ UsedInInstr.resize(TRI->getNumRegs()); Allocatable = TRI->getAllocatableSet(*MF); - Reserved = TRI->getReservedRegs(*MF); // initialize the virtual->physical register map to have a 'null' // mapping for all virtual registers From dalej at apple.com Fri Sep 3 17:04:13 2010 From: dalej at apple.com (Dale Johannesen) Date: Fri, 3 Sep 2010 15:04:13 -0700 Subject: [llvm-commits] [llvm] r113016 - /llvm/trunk/lib/CodeGen/RegAllocFast.cpp In-Reply-To: <20100903214516.08C592A6C12C@llvm.org> References: <20100903214516.08C592A6C12C@llvm.org> Message-ID: Jim believes this will fix the PPC buildbot. I've started a run, ETA around 5 PM (Pacific). On Sep 3, 2010, at 2:45 PMPDT, Jim Grosbach wrote: > Author: grosbach > Date: Fri Sep 3 16:45:15 2010 > New Revision: 113016 > > URL: http://llvm.org/viewvc/llvm-project?rev=113016&view=rev > Log: > previous patch was a little too tricky for its own good. Don't try to > overload UserInInstr. Explicitly check Allocatable. The early exit > in the > condition will mean the performance impact of the extra test should be > minimal. > > Modified: > llvm/trunk/lib/CodeGen/RegAllocFast.cpp > > Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=113016&r1=113015&r2=113016&view=diff > = > = > = > = > = > = > = > = > ====================================================================== > --- llvm/trunk/lib/CodeGen/RegAllocFast.cpp (original) > +++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp Fri Sep 3 16:45:15 2010 > @@ -113,9 +113,6 @@ > // Allocatable - vector of allocatable physical registers. > BitVector Allocatable; > > - // Reserved - vector of reserved physical registers. > - BitVector Reserved; > - > // SkippedInstrs - Descriptors of instructions whose clobber > list was > // ignored because all registers were spilled. It is still > necessary to > // mark all the clobbered registers as used by the function. > @@ -501,7 +498,8 @@ > // First try to find a completely free register. > for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) { > unsigned PhysReg = *I; > - if (PhysRegState[PhysReg] == regFree && ! > UsedInInstr.test(PhysReg)) > + if (PhysRegState[PhysReg] == regFree && ! > UsedInInstr.test(PhysReg) && > + Allocatable.test(PhysReg)) > return assignVirtToPhysReg(LRE, PhysReg); > } > > @@ -510,6 +508,8 @@ > > unsigned BestReg = 0, BestCost = spillImpossible; > for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) { > + if (!Allocatable.test(*I)) > + continue; > unsigned Cost = calcSpillCost(*I); > // Cost is 0 when all aliases are already disabled. > if (Cost == 0) > @@ -712,7 +712,7 @@ > } > > // Restore UsedInInstr to a state usable for allocating normal > virtual uses. > - UsedInInstr = Reserved; > + UsedInInstr.reset(); > for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { > MachineOperand &MO = MI->getOperand(i); > if (!MO.isReg() || (MO.isDef() && !MO.isEarlyClobber())) continue; > @@ -838,7 +838,7 @@ > } > > // Track registers used by instruction. > - UsedInInstr = Reserved; > + UsedInInstr.reset(); > > // First scan. > // Mark physreg uses and early clobbers as used. > @@ -916,7 +916,7 @@ > > // Track registers defined by instruction - early clobbers and > tied uses at > // this point. > - UsedInInstr = Reserved; > + UsedInInstr.reset(); > if (hasEarlyClobbers) { > for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { > MachineOperand &MO = MI->getOperand(i); > @@ -1014,7 +1014,6 @@ > > UsedInInstr.resize(TRI->getNumRegs()); > Allocatable = TRI->getAllocatableSet(*MF); > - Reserved = TRI->getReservedRegs(*MF); > > // initialize the virtual->physical register map to have a 'null' > // mapping for all virtual registers > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From bruno.cardoso at gmail.com Fri Sep 3 17:09:41 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Fri, 03 Sep 2010 22:09:41 -0000 Subject: [llvm-commits] [llvm] r113020 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20100903220942.042162A6C12C@llvm.org> Author: bruno Date: Fri Sep 3 17:09:41 2010 New Revision: 113020 URL: http://llvm.org/viewvc/llvm-project?rev=113020&view=rev Log: Reapply considered harmfull part of rr112934 and r112942. "Use target specific nodes instead of relying in unpckl and unpckh pattern fragments during isel time. Also place a depth limit in getShuffleScalarElt. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=113020&r1=113019&r2=113020&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Sep 3 17:09:41 2010 @@ -16,6 +16,7 @@ #include "X86.h" #include "X86InstrBuilder.h" #include "X86ISelLowering.h" +#include "X86ShuffleDecode.h" #include "X86TargetMachine.h" #include "X86TargetObjectFile.h" #include "llvm/CallingConv.h" @@ -3687,7 +3688,11 @@ /// getShuffleScalarElt - Returns the scalar element that will make up the ith /// element of the result of the vector shuffle. -SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG) { +SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG, + unsigned Depth) { + if (Depth == 6) + return SDValue(); // Limit search depth. + SDValue V = SDValue(N, 0); EVT VT = V.getValueType(); unsigned Opcode = V.getOpcode(); @@ -3701,24 +3706,86 @@ int NumElems = VT.getVectorNumElements(); SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1); - return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG); + return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1); } // Recurse into target specific vector shuffles to find scalars. if (isTargetShuffle(Opcode)) { + int NumElems = VT.getVectorNumElements(); + SmallVector ShuffleMask; + SDValue ImmN; + switch(Opcode) { + case X86ISD::SHUFPS: + case X86ISD::SHUFPD: + ImmN = N->getOperand(N->getNumOperands()-1); + DecodeSHUFPSMask(NumElems, + cast(ImmN)->getZExtValue(), + ShuffleMask); + break; + case X86ISD::PUNPCKHBW: + case X86ISD::PUNPCKHWD: + case X86ISD::PUNPCKHDQ: + case X86ISD::PUNPCKHQDQ: + DecodePUNPCKHMask(NumElems, ShuffleMask); + break; + case X86ISD::UNPCKHPS: + case X86ISD::UNPCKHPD: + DecodeUNPCKHPMask(NumElems, ShuffleMask); + break; + case X86ISD::PUNPCKLBW: + case X86ISD::PUNPCKLWD: + case X86ISD::PUNPCKLDQ: + case X86ISD::PUNPCKLQDQ: + DecodePUNPCKLMask(NumElems, ShuffleMask); + break; + case X86ISD::UNPCKLPS: + case X86ISD::UNPCKLPD: + DecodeUNPCKLPMask(NumElems, ShuffleMask); + break; + case X86ISD::MOVHLPS: + DecodeMOVHLPSMask(NumElems, ShuffleMask); + break; + case X86ISD::MOVLHPS: + DecodeMOVLHPSMask(NumElems, ShuffleMask); + break; + case X86ISD::PSHUFD: + ImmN = N->getOperand(N->getNumOperands()-1); + DecodePSHUFMask(NumElems, + cast(ImmN)->getZExtValue(), + ShuffleMask); + break; + case X86ISD::PSHUFHW: + ImmN = N->getOperand(N->getNumOperands()-1); + DecodePSHUFHWMask(cast(ImmN)->getZExtValue(), + ShuffleMask); + break; + case X86ISD::PSHUFLW: + ImmN = N->getOperand(N->getNumOperands()-1); + DecodePSHUFLWMask(cast(ImmN)->getZExtValue(), + ShuffleMask); + break; case X86ISD::MOVSS: case X86ISD::MOVSD: { // The index 0 always comes from the first element of the second source, // this is why MOVSS and MOVSD are used in the first place. The other // elements come from the other positions of the first source vector. unsigned OpNum = (Index == 0) ? 1 : 0; - return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG); + return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG, + Depth+1); } default: assert("not implemented for target shuffle node"); return SDValue(); } + + Index = ShuffleMask[Index]; + if (Index < 0) + return DAG.getUNDEF(VT.getVectorElementType()); + + SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); + return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, + Depth+1); } // Actual nodes that may contain scalar elements @@ -3751,7 +3818,7 @@ while (i < NumElems) { unsigned Index = ZerosFromLeft ? i : NumElems-i-1; - SDValue Elt = getShuffleScalarElt(N, Index, DAG); + SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0); if (!(Elt.getNode() && (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt)))) break; @@ -5364,9 +5431,13 @@ return getMOVL(DAG, dl, VT, V2, V1); } - if (X86::isUNPCKLMask(SVOp) || - X86::isUNPCKHMask(SVOp)) - return Op; + if (X86::isUNPCKLMask(SVOp)) + return (isMMX) ? + Op : getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V2, DAG); + + if (X86::isUNPCKHMask(SVOp)) + return (isMMX) ? + Op : getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V2, DAG); if (V2IsSplat) { // Normalize mask so all entries that point to V2 points to its first @@ -5388,9 +5459,14 @@ // FIXME: this seems wrong. SDValue NewOp = CommuteVectorShuffle(SVOp, DAG); ShuffleVectorSDNode *NewSVOp = cast(NewOp); - if (X86::isUNPCKLMask(NewSVOp) || - X86::isUNPCKHMask(NewSVOp)) - return NewOp; + + if (X86::isUNPCKLMask(NewSVOp)) + return (isMMX) ? + NewOp : getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V2, V1, DAG); + + if (X86::isUNPCKHMask(NewSVOp)) + return (isMMX) ? + NewOp : getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V2, V1, DAG); } // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle. @@ -9731,7 +9807,7 @@ SmallVector Elts; for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) - Elts.push_back(getShuffleScalarElt(N, i, DAG)); + Elts.push_back(getShuffleScalarElt(N, i, DAG, 0)); return EltsFromConsecutiveLoads(VT, Elts, dl, DAG); } @@ -10659,7 +10735,6 @@ SelectionDAG &DAG = DCI.DAG; switch (N->getOpcode()) { default: break; - case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this); case ISD::EXTRACT_VECTOR_ELT: return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this); case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget); @@ -10676,6 +10751,28 @@ case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG); + case X86ISD::SHUFPS: // Handle all target specific shuffles + case X86ISD::SHUFPD: + case X86ISD::PUNPCKHBW: + case X86ISD::PUNPCKHWD: + case X86ISD::PUNPCKHDQ: + case X86ISD::PUNPCKHQDQ: + case X86ISD::UNPCKHPS: + case X86ISD::UNPCKHPD: + case X86ISD::PUNPCKLBW: + case X86ISD::PUNPCKLWD: + case X86ISD::PUNPCKLDQ: + case X86ISD::PUNPCKLQDQ: + case X86ISD::UNPCKLPS: + case X86ISD::UNPCKLPD: + case X86ISD::MOVHLPS: + case X86ISD::MOVLHPS: + case X86ISD::PSHUFD: + case X86ISD::PSHUFHW: + case X86ISD::PSHUFLW: + case X86ISD::MOVSS: + case X86ISD::MOVSD: + case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this); } return SDValue(); From bruno.cardoso at gmail.com Fri Sep 3 17:11:16 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Fri, 3 Sep 2010 15:11:16 -0700 Subject: [llvm-commits] [llvm] r113014 - in /llvm/trunk: lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/avx-intrinsics-x86.ll In-Reply-To: <20100903212300.7B5702A6C12C@llvm.org> References: <20100903212300.7B5702A6C12C@llvm.org> Message-ID: Nice! Also thanks for pointing this out! :) On Fri, Sep 3, 2010 at 2:23 PM, Dale Johannesen wrote: > Author: johannes > Date: Fri Sep ?3 16:23:00 2010 > New Revision: 113014 > > URL: http://llvm.org/viewvc/llvm-project?rev=113014&view=rev > Log: > Remove the rest of the nonexistent 64-bit AVX instructions. > Bruno, please review. > > > Modified: > ? ?llvm/trunk/lib/Target/X86/X86InstrSSE.td > ? ?llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll > > Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=113014&r1=113013&r2=113014&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) > +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Fri Sep ?3 16:23:00 2010 > @@ -3592,26 +3592,9 @@ > > ?/// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}. > ?multiclass SS3I_binop_rm_int opc, string OpcodeStr, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? PatFrag mem_frag64, PatFrag mem_frag128, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? Intrinsic IntId64, Intrinsic IntId128, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? PatFrag mem_frag128, Intrinsic IntId128, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bit Is2Addr = 1> { > ? let isCommutable = 1 in > - ?def rr64 : SS38I - ? ? ? (ins VR64:$src1, VR64:$src2), > - ? ? ? !if(Is2Addr, > - ? ? ? ? !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), > - ? ? ? ? !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")), > - ? ? ? [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]>; > - ?def rm64 : SS38I - ? ? ? (ins VR64:$src1, i64mem:$src2), > - ? ? ? !if(Is2Addr, > - ? ? ? ? !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), > - ? ? ? ? !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")), > - ? ? ? [(set VR64:$dst, > - ? ? ? ? (IntId64 VR64:$src1, > - ? ? ? ? ?(bitconvert (memopv8i8 addr:$src2))))]>; > - > - ?let isCommutable = 1 in > ? def rr128 : SS38I ? ? ? ?(ins VR128:$src1, VR128:$src2), > ? ? ? ?!if(Is2Addr, > @@ -3628,88 +3611,102 @@ > ? ? ? ? ?(IntId128 VR128:$src1, > ? ? ? ? ? (bitconvert (memopv16i8 addr:$src2))))]>, OpSize; > ?} > +multiclass SS3I_binop_rm_int_mm opc, string OpcodeStr, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? PatFrag mem_frag64, Intrinsic IntId64> { > + ?let isCommutable = 1 in > + ?def rr64 : SS38I + ? ? ? (ins VR64:$src1, VR64:$src2), > + ? ? ? ?!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), > + ? ? ? [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]>; > + ?def rm64 : SS38I + ? ? ? (ins VR64:$src1, i64mem:$src2), > + ? ? ? ?!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), > + ? ? ? [(set VR64:$dst, > + ? ? ? ? (IntId64 VR64:$src1, > + ? ? ? ? ?(bitconvert (memopv8i8 addr:$src2))))]>; > +} > > ?let isAsmParserOnly = 1, Predicates = [HasAVX] in { > ?let isCommutable = 0 in { > - ?defm VPHADDW ? ?: SS3I_binop_rm_int<0x01, "vphaddw", memopv4i16, memopv8i16, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?int_x86_ssse3_phadd_w, > + ?defm VPHADDW ? ?: SS3I_binop_rm_int<0x01, "vphaddw", memopv8i16, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_phadd_w_128, 0>, VEX_4V; > - ?defm VPHADDD ? ?: SS3I_binop_rm_int<0x02, "vphaddd", memopv2i32, memopv4i32, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?int_x86_ssse3_phadd_d, > + ?defm VPHADDD ? ?: SS3I_binop_rm_int<0x02, "vphaddd", memopv4i32, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_phadd_d_128, 0>, VEX_4V; > - ?defm VPHADDSW ? : SS3I_binop_rm_int<0x03, "vphaddsw", memopv4i16, memopv8i16, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?int_x86_ssse3_phadd_sw, > + ?defm VPHADDSW ? : SS3I_binop_rm_int<0x03, "vphaddsw", memopv8i16, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_phadd_sw_128, 0>, VEX_4V; > - ?defm VPHSUBW ? ?: SS3I_binop_rm_int<0x05, "vphsubw", memopv4i16, memopv8i16, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?int_x86_ssse3_phsub_w, > + ?defm VPHSUBW ? ?: SS3I_binop_rm_int<0x05, "vphsubw", memopv8i16, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_phsub_w_128, 0>, VEX_4V; > - ?defm VPHSUBD ? ?: SS3I_binop_rm_int<0x06, "vphsubd", memopv2i32, memopv4i32, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?int_x86_ssse3_phsub_d, > + ?defm VPHSUBD ? ?: SS3I_binop_rm_int<0x06, "vphsubd", memopv4i32, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_phsub_d_128, 0>, VEX_4V; > - ?defm VPHSUBSW ? : SS3I_binop_rm_int<0x07, "vphsubsw", memopv4i16, memopv8i16, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?int_x86_ssse3_phsub_sw, > + ?defm VPHSUBSW ? : SS3I_binop_rm_int<0x07, "vphsubsw", memopv8i16, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_phsub_sw_128, 0>, VEX_4V; > - ?defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", memopv8i8, memopv16i8, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?int_x86_ssse3_pmadd_ub_sw, > + ?defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", memopv16i8, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V; > - ?defm VPSHUFB ? ?: SS3I_binop_rm_int<0x00, "vpshufb", memopv8i8, memopv16i8, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?int_x86_ssse3_pshuf_b, > + ?defm VPSHUFB ? ?: SS3I_binop_rm_int<0x00, "vpshufb", memopv16i8, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_pshuf_b_128, 0>, VEX_4V; > - ?defm VPSIGNB ? ?: SS3I_binop_rm_int<0x08, "vpsignb", memopv8i8, memopv16i8, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?int_x86_ssse3_psign_b, > + ?defm VPSIGNB ? ?: SS3I_binop_rm_int<0x08, "vpsignb", memopv16i8, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_psign_b_128, 0>, VEX_4V; > - ?defm VPSIGNW ? ?: SS3I_binop_rm_int<0x09, "vpsignw", memopv4i16, memopv8i16, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?int_x86_ssse3_psign_w, > + ?defm VPSIGNW ? ?: SS3I_binop_rm_int<0x09, "vpsignw", memopv8i16, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_psign_w_128, 0>, VEX_4V; > - ?defm VPSIGND ? ?: SS3I_binop_rm_int<0x0A, "vpsignd", memopv2i32, memopv4i32, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?int_x86_ssse3_psign_d, > + ?defm VPSIGND ? ?: SS3I_binop_rm_int<0x0A, "vpsignd", memopv4i32, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_psign_d_128, 0>, VEX_4V; > ?} > -defm VPMULHRSW ? ?: SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv4i16, memopv8i16, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?int_x86_ssse3_pmul_hr_sw, > +defm VPMULHRSW ? ?: SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv8i16, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V; > ?} > > ?// None of these have i8 immediate fields. > ?let ImmT = NoImm, Constraints = "$src1 = $dst" in { > ?let isCommutable = 0 in { > - ?defm PHADDW ? ?: SS3I_binop_rm_int<0x01, "phaddw", memopv4i16, memopv8i16, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_phadd_w, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_phadd_w_128>; > - ?defm PHADDD ? ?: SS3I_binop_rm_int<0x02, "phaddd", memopv2i32, memopv4i32, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_phadd_d, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_phadd_d_128>; > - ?defm PHADDSW ? : SS3I_binop_rm_int<0x03, "phaddsw", memopv4i16, memopv8i16, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_phadd_sw, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_phadd_sw_128>; > - ?defm PHSUBW ? ?: SS3I_binop_rm_int<0x05, "phsubw", memopv4i16, memopv8i16, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_phsub_w, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_phsub_w_128>; > - ?defm PHSUBD ? ?: SS3I_binop_rm_int<0x06, "phsubd", memopv2i32, memopv4i32, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_phsub_d, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_phsub_d_128>; > - ?defm PHSUBSW ? : SS3I_binop_rm_int<0x07, "phsubsw", memopv4i16, memopv8i16, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_phsub_sw, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_phsub_sw_128>; > - ?defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv8i8, memopv16i8, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_pmadd_ub_sw, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_pmadd_ub_sw_128>; > - ?defm PSHUFB ? ?: SS3I_binop_rm_int<0x00, "pshufb", memopv8i8, memopv16i8, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_pshuf_b, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_pshuf_b_128>; > - ?defm PSIGNB ? ?: SS3I_binop_rm_int<0x08, "psignb", memopv8i8, memopv16i8, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_psign_b, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_psign_b_128>; > - ?defm PSIGNW ? ?: SS3I_binop_rm_int<0x09, "psignw", memopv4i16, memopv8i16, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_psign_w, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_psign_w_128>; > - ?defm PSIGND ? ?: SS3I_binop_rm_int<0x0A, "psignd", memopv2i32, memopv4i32, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_psign_d, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_psign_d_128>; > -} > -defm PMULHRSW ? ?: SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv4i16, memopv8i16, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_pmul_hr_sw, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_pmul_hr_sw_128>; > + ?defm PHADDW ? ?: SS3I_binop_rm_int<0x01, "phaddw", memopv8i16, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_phadd_w_128>, > + ? ? ? ? ? ? ? ? ? SS3I_binop_rm_int_mm<0x01, "phaddw", memopv4i16, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_phadd_w>; > + ?defm PHADDD ? ?: SS3I_binop_rm_int<0x02, "phaddd", memopv4i32, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_phadd_d_128>, > + ? ? ? ? ? ? ? ? ? SS3I_binop_rm_int_mm<0x02, "phaddd", memopv2i32, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_phadd_d>; > + ?defm PHADDSW ? : SS3I_binop_rm_int<0x03, "phaddsw", memopv8i16, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_phadd_sw_128>, > + ? ? ? ? ? ? ? ? ? SS3I_binop_rm_int_mm<0x03, "phaddsw", memopv4i16, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_phadd_sw>; > + ?defm PHSUBW ? ?: SS3I_binop_rm_int<0x05, "phsubw", memopv8i16, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_phsub_w_128>, > + ? ? ? ? ? ? ? ? ? ?SS3I_binop_rm_int_mm<0x05, "phsubw", memopv4i16, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_phsub_w>; > + ?defm PHSUBD ? ?: SS3I_binop_rm_int<0x06, "phsubd", memopv4i32, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_phsub_d_128>, > + ? ? ? ? ? ? ? ? ? SS3I_binop_rm_int_mm<0x06, "phsubd", memopv2i32, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_phsub_d>; > + ?defm PHSUBSW ? : SS3I_binop_rm_int<0x07, "phsubsw", memopv8i16, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_phsub_sw_128>, > + ? ? ? ? ? ? ? ? ? SS3I_binop_rm_int_mm<0x07, "phsubsw", memopv4i16, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_phsub_sw>; > + ?defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv16i8, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_pmadd_ub_sw_128>, > + ? ? ? ? ? ? ? ? ? SS3I_binop_rm_int_mm<0x04, "pmaddubsw", memopv8i8, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_pmadd_ub_sw>; > + ?defm PSHUFB ? ?: SS3I_binop_rm_int<0x00, "pshufb", memopv8i8, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_pshuf_b_128>, > + ? ? ? ? ? ? ? ? ? SS3I_binop_rm_int_mm<0x00, "pshufb", memopv8i8, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_pshuf_b>; > + ?defm PSIGNB ? ?: SS3I_binop_rm_int<0x08, "psignb", memopv16i8, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_psign_b_128>, > + ? ? ? ? ? ? ? ? ? SS3I_binop_rm_int_mm<0x08, "psignb", memopv8i8, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_psign_b>; > + ?defm PSIGNW ? ?: SS3I_binop_rm_int<0x09, "psignw", memopv8i16, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_psign_w_128>, > + ? ? ? ? ? ? ? ? ? SS3I_binop_rm_int_mm<0x09, "psignw", memopv4i16, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_psign_w>; > + ?defm PSIGND ? ?: SS3I_binop_rm_int<0x0A, "psignd", memopv4i32, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_psign_d_128>, > + ? ? ? ? ? ? ? ? ? SS3I_binop_rm_int_mm<0x0A, "psignd", memopv2i32, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_psign_d>; > +} > +defm PMULHRSW ? ?: SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv8i16, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_pmul_hr_sw_128>, > + ? ? ? ? ? ? ? ? ? SS3I_binop_rm_int_mm<0x0B, "pmulhrsw", memopv4i16, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int_x86_ssse3_pmul_hr_sw>; > ?} > > ?def : Pat<(X86pshufb VR128:$src, VR128:$mask), > > Modified: llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll?rev=113014&r1=113013&r2=113014&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll (original) > +++ llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll Fri Sep ?3 16:23:00 2010 > @@ -1739,14 +1739,6 @@ > ?declare <8 x i16> @llvm.x86.ssse3.pabs.w.128(<8 x i16>) nounwind readnone > > > -define <2 x i32> @test_x86_ssse3_phadd_d(<2 x i32> %a0, <2 x i32> %a1) { > - ?; CHECK: vphaddd > - ?%res = call <2 x i32> @llvm.x86.ssse3.phadd.d(<2 x i32> %a0, <2 x i32> %a1) ; <<2 x i32>> [#uses=1] > - ?ret <2 x i32> %res > -} > -declare <2 x i32> @llvm.x86.ssse3.phadd.d(<2 x i32>, <2 x i32>) nounwind readnone > - > - > ?define <4 x i32> @test_x86_ssse3_phadd_d_128(<4 x i32> %a0, <4 x i32> %a1) { > ? ; CHECK: vphaddd > ? %res = call <4 x i32> @llvm.x86.ssse3.phadd.d.128(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1] > @@ -1755,14 +1747,6 @@ > ?declare <4 x i32> @llvm.x86.ssse3.phadd.d.128(<4 x i32>, <4 x i32>) nounwind readnone > > > -define <4 x i16> @test_x86_ssse3_phadd_sw(<4 x i16> %a0, <4 x i16> %a1) { > - ?; CHECK: vphaddsw > - ?%res = call <4 x i16> @llvm.x86.ssse3.phadd.sw(<4 x i16> %a0, <4 x i16> %a1) ; <<4 x i16>> [#uses=1] > - ?ret <4 x i16> %res > -} > -declare <4 x i16> @llvm.x86.ssse3.phadd.sw(<4 x i16>, <4 x i16>) nounwind readnone > - > - > ?define <4 x i32> @test_x86_ssse3_phadd_sw_128(<4 x i32> %a0, <4 x i32> %a1) { > ? ; CHECK: vphaddsw > ? %res = call <4 x i32> @llvm.x86.ssse3.phadd.sw.128(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1] > @@ -1771,14 +1755,6 @@ > ?declare <4 x i32> @llvm.x86.ssse3.phadd.sw.128(<4 x i32>, <4 x i32>) nounwind readnone > > > -define <4 x i16> @test_x86_ssse3_phadd_w(<4 x i16> %a0, <4 x i16> %a1) { > - ?; CHECK: vphaddw > - ?%res = call <4 x i16> @llvm.x86.ssse3.phadd.w(<4 x i16> %a0, <4 x i16> %a1) ; <<4 x i16>> [#uses=1] > - ?ret <4 x i16> %res > -} > -declare <4 x i16> @llvm.x86.ssse3.phadd.w(<4 x i16>, <4 x i16>) nounwind readnone > - > - > ?define <8 x i16> @test_x86_ssse3_phadd_w_128(<8 x i16> %a0, <8 x i16> %a1) { > ? ; CHECK: vphaddw > ? %res = call <8 x i16> @llvm.x86.ssse3.phadd.w.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1] > @@ -1787,14 +1763,6 @@ > ?declare <8 x i16> @llvm.x86.ssse3.phadd.w.128(<8 x i16>, <8 x i16>) nounwind readnone > > > -define <2 x i32> @test_x86_ssse3_phsub_d(<2 x i32> %a0, <2 x i32> %a1) { > - ?; CHECK: vphsubd > - ?%res = call <2 x i32> @llvm.x86.ssse3.phsub.d(<2 x i32> %a0, <2 x i32> %a1) ; <<2 x i32>> [#uses=1] > - ?ret <2 x i32> %res > -} > -declare <2 x i32> @llvm.x86.ssse3.phsub.d(<2 x i32>, <2 x i32>) nounwind readnone > - > - > ?define <4 x i32> @test_x86_ssse3_phsub_d_128(<4 x i32> %a0, <4 x i32> %a1) { > ? ; CHECK: vphsubd > ? %res = call <4 x i32> @llvm.x86.ssse3.phsub.d.128(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1] > @@ -1803,14 +1771,6 @@ > ?declare <4 x i32> @llvm.x86.ssse3.phsub.d.128(<4 x i32>, <4 x i32>) nounwind readnone > > > -define <4 x i16> @test_x86_ssse3_phsub_sw(<4 x i16> %a0, <4 x i16> %a1) { > - ?; CHECK: vphsubsw > - ?%res = call <4 x i16> @llvm.x86.ssse3.phsub.sw(<4 x i16> %a0, <4 x i16> %a1) ; <<4 x i16>> [#uses=1] > - ?ret <4 x i16> %res > -} > -declare <4 x i16> @llvm.x86.ssse3.phsub.sw(<4 x i16>, <4 x i16>) nounwind readnone > - > - > ?define <8 x i16> @test_x86_ssse3_phsub_sw_128(<8 x i16> %a0, <8 x i16> %a1) { > ? ; CHECK: vphsubsw > ? %res = call <8 x i16> @llvm.x86.ssse3.phsub.sw.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1] > @@ -1819,14 +1779,6 @@ > ?declare <8 x i16> @llvm.x86.ssse3.phsub.sw.128(<8 x i16>, <8 x i16>) nounwind readnone > > > -define <4 x i16> @test_x86_ssse3_phsub_w(<4 x i16> %a0, <4 x i16> %a1) { > - ?; CHECK: vphsubw > - ?%res = call <4 x i16> @llvm.x86.ssse3.phsub.w(<4 x i16> %a0, <4 x i16> %a1) ; <<4 x i16>> [#uses=1] > - ?ret <4 x i16> %res > -} > -declare <4 x i16> @llvm.x86.ssse3.phsub.w(<4 x i16>, <4 x i16>) nounwind readnone > - > - > ?define <8 x i16> @test_x86_ssse3_phsub_w_128(<8 x i16> %a0, <8 x i16> %a1) { > ? ; CHECK: vphsubw > ? %res = call <8 x i16> @llvm.x86.ssse3.phsub.w.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1] > @@ -1835,14 +1787,6 @@ > ?declare <8 x i16> @llvm.x86.ssse3.phsub.w.128(<8 x i16>, <8 x i16>) nounwind readnone > > > -define <4 x i16> @test_x86_ssse3_pmadd_ub_sw(<4 x i16> %a0, <4 x i16> %a1) { > - ?; CHECK: vpmaddubsw > - ?%res = call <4 x i16> @llvm.x86.ssse3.pmadd.ub.sw(<4 x i16> %a0, <4 x i16> %a1) ; <<4 x i16>> [#uses=1] > - ?ret <4 x i16> %res > -} > -declare <4 x i16> @llvm.x86.ssse3.pmadd.ub.sw(<4 x i16>, <4 x i16>) nounwind readnone > - > - > ?define <8 x i16> @test_x86_ssse3_pmadd_ub_sw_128(<8 x i16> %a0, <8 x i16> %a1) { > ? ; CHECK: vpmaddubsw > ? %res = call <8 x i16> @llvm.x86.ssse3.pmadd.ub.sw.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1] > @@ -1851,14 +1795,6 @@ > ?declare <8 x i16> @llvm.x86.ssse3.pmadd.ub.sw.128(<8 x i16>, <8 x i16>) nounwind readnone > > > -define <4 x i16> @test_x86_ssse3_pmul_hr_sw(<4 x i16> %a0, <4 x i16> %a1) { > - ?; CHECK: vpmulhrsw > - ?%res = call <4 x i16> @llvm.x86.ssse3.pmul.hr.sw(<4 x i16> %a0, <4 x i16> %a1) ; <<4 x i16>> [#uses=1] > - ?ret <4 x i16> %res > -} > -declare <4 x i16> @llvm.x86.ssse3.pmul.hr.sw(<4 x i16>, <4 x i16>) nounwind readnone > - > - > ?define <8 x i16> @test_x86_ssse3_pmul_hr_sw_128(<8 x i16> %a0, <8 x i16> %a1) { > ? ; CHECK: vpmulhrsw > ? %res = call <8 x i16> @llvm.x86.ssse3.pmul.hr.sw.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1] > @@ -1867,14 +1803,6 @@ > ?declare <8 x i16> @llvm.x86.ssse3.pmul.hr.sw.128(<8 x i16>, <8 x i16>) nounwind readnone > > > -define <8 x i8> @test_x86_ssse3_pshuf_b(<8 x i8> %a0, <8 x i8> %a1) { > - ?; CHECK: vpshufb > - ?%res = call <8 x i8> @llvm.x86.ssse3.pshuf.b(<8 x i8> %a0, <8 x i8> %a1) ; <<8 x i8>> [#uses=1] > - ?ret <8 x i8> %res > -} > -declare <8 x i8> @llvm.x86.ssse3.pshuf.b(<8 x i8>, <8 x i8>) nounwind readnone > - > - > ?define <16 x i8> @test_x86_ssse3_pshuf_b_128(<16 x i8> %a0, <16 x i8> %a1) { > ? ; CHECK: vpshufb > ? %res = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1] > @@ -1883,14 +1811,6 @@ > ?declare <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8>, <16 x i8>) nounwind readnone > > > -define <8 x i8> @test_x86_ssse3_psign_b(<8 x i8> %a0, <8 x i8> %a1) { > - ?; CHECK: vpsignb > - ?%res = call <8 x i8> @llvm.x86.ssse3.psign.b(<8 x i8> %a0, <8 x i8> %a1) ; <<8 x i8>> [#uses=1] > - ?ret <8 x i8> %res > -} > -declare <8 x i8> @llvm.x86.ssse3.psign.b(<8 x i8>, <8 x i8>) nounwind readnone > - > - > ?define <16 x i8> @test_x86_ssse3_psign_b_128(<16 x i8> %a0, <16 x i8> %a1) { > ? ; CHECK: vpsignb > ? %res = call <16 x i8> @llvm.x86.ssse3.psign.b.128(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1] > @@ -1899,14 +1819,6 @@ > ?declare <16 x i8> @llvm.x86.ssse3.psign.b.128(<16 x i8>, <16 x i8>) nounwind readnone > > > -define <2 x i32> @test_x86_ssse3_psign_d(<2 x i32> %a0, <2 x i32> %a1) { > - ?; CHECK: vpsignd > - ?%res = call <2 x i32> @llvm.x86.ssse3.psign.d(<2 x i32> %a0, <2 x i32> %a1) ; <<2 x i32>> [#uses=1] > - ?ret <2 x i32> %res > -} > -declare <2 x i32> @llvm.x86.ssse3.psign.d(<2 x i32>, <2 x i32>) nounwind readnone > - > - > ?define <4 x i32> @test_x86_ssse3_psign_d_128(<4 x i32> %a0, <4 x i32> %a1) { > ? ; CHECK: vpsignd > ? %res = call <4 x i32> @llvm.x86.ssse3.psign.d.128(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1] > @@ -1915,14 +1827,6 @@ > ?declare <4 x i32> @llvm.x86.ssse3.psign.d.128(<4 x i32>, <4 x i32>) nounwind readnone > > > -define <4 x i16> @test_x86_ssse3_psign_w(<4 x i16> %a0, <4 x i16> %a1) { > - ?; CHECK: vpsignw > - ?%res = call <4 x i16> @llvm.x86.ssse3.psign.w(<4 x i16> %a0, <4 x i16> %a1) ; <<4 x i16>> [#uses=1] > - ?ret <4 x i16> %res > -} > -declare <4 x i16> @llvm.x86.ssse3.psign.w(<4 x i16>, <4 x i16>) nounwind readnone > - > - > ?define <8 x i16> @test_x86_ssse3_psign_w_128(<8 x i16> %a0, <8 x i16> %a1) { > ? ; CHECK: vpsignw > ? %res = call <8 x i16> @llvm.x86.ssse3.psign.w.128(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1] > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -- Bruno Cardoso Lopes http://www.brunocardoso.cc From gohman at apple.com Fri Sep 3 17:12:56 2010 From: gohman at apple.com (Dan Gohman) Date: Fri, 03 Sep 2010 22:12:56 -0000 Subject: [llvm-commits] [llvm] r113021 - /llvm/trunk/lib/Analysis/ScalarEvolutionNormalization.cpp Message-ID: <20100903221256.C189E2A6C12C@llvm.org> Author: djg Date: Fri Sep 3 17:12:56 2010 New Revision: 113021 URL: http://llvm.org/viewvc/llvm-project?rev=113021&view=rev Log: Disable the asserts that check that normalization is perfectly invertible. ScalarEvolution's folding routines don't always succeed in canonicalizing equal expressions to a single canonical form, and this can cause these asserts to fail, even though there's no actual correctness problem. This fixes PR8066. Modified: llvm/trunk/lib/Analysis/ScalarEvolutionNormalization.cpp Modified: llvm/trunk/lib/Analysis/ScalarEvolutionNormalization.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolutionNormalization.cpp?rev=113021&r1=113020&r2=113021&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolutionNormalization.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolutionNormalization.cpp Fri Sep 3 17:12:56 2010 @@ -108,7 +108,11 @@ Result = SE.getMinusSCEV(Result, TransformedStep); Loops.insert(L); } -#ifdef XDEBUG +#if 0 + // This assert is conceptually correct, but ScalarEvolution currently + // sometimes fails to canonicalize two equal SCEVs to exactly the same + // form. It's possibly a pessimization when this happens, but it isn't a + // correctness problem, so disable this assert for now. assert(S == TransformForPostIncUse(Denormalize, Result, User, OperandValToReplace, Loops, SE, DT) && @@ -122,7 +126,8 @@ User, OperandValToReplace, Loops, SE, DT); Result = SE.getMinusSCEV(Result, TransformedStep); } -#ifdef XDEBUG +#if 0 + // See the comment on the assert above. assert(S == TransformForPostIncUse(Denormalize, Result, User, OperandValToReplace, Loops, SE, DT) && From jan_sjodin at yahoo.com Fri Sep 3 17:28:49 2010 From: jan_sjodin at yahoo.com (Jan Sjodin) Date: Fri, 3 Sep 2010 15:28:49 -0700 (PDT) Subject: [llvm-commits] Issue with Win64 local area stack offset In-Reply-To: References: <489333.28347.qm@web55604.mail.re4.yahoo.com> <832540.73670.qm@web55606.mail.re4.yahoo.com> Message-ID: <921691.29161.qm@web55608.mail.re4.yahoo.com> I see, that is unfortunate. I will take a look at why this happens. Right now I believe this is because the patch is incomplete and there is some interaction with the callee code that is not taken into consideration. The shadow area should still be allocated before the return address on the stack. - Jan ----- Original Message ---- > From: Anton Korobeynikov > To: Jan Sjodin > Cc: llvm-commits at cs.uiuc.edu > Sent: Fri, September 3, 2010 6:42:39 AM > Subject: Re: [llvm-commits] Issue with Win64 local area stack offset > > Hello, Jan > > > Any comments about the revised patch? Ok for someone to commit? > The patch is invalid. First of all, make sure it does not break "make check". > Right now it does and one of the failed tests clearly indicates the > problem - the shadow space is allocated in the wrong place and calls > might clobber spills of the callee which will be really hard to find > in real-world apps. > > -- > With best regards, Anton Korobeynikov > Faculty of Mathematics and Mechanics, Saint Petersburg State University > From jan_sjodin at yahoo.com Fri Sep 3 17:34:11 2010 From: jan_sjodin at yahoo.com (Jan Sjodin) Date: Fri, 3 Sep 2010 15:34:11 -0700 (PDT) Subject: [llvm-commits] [PATCH] Win64 var arg support In-Reply-To: References: Message-ID: <257699.86359.qm@web55607.mail.re4.yahoo.com> I believe once my patch about the calling convention is fixed this should be okay. The Win64 patch I'm working on is making the same change. Regards, Jan ----- Original Message ---- > From: Anton Korobeynikov > To: Cameron Esfahani > Cc: llvm-commits at cs.uiuc.edu > Sent: Fri, September 3, 2010 1:38:01 PM > Subject: Re: [llvm-commits] [PATCH] Win64 var arg support > > Hello, Cameron > > On Fri, Sep 3, 2010 at 07:42, Cameron Esfahani wrote: > > This is required for the var arg support. ?Without this change, there's no >way to know how far the home register space allocated by the caller is from the >top of the stack. ?Any fixed object created via MFI is put at it's offset after >the frame info stuff is calculated. ?So, if you wanted to put something into the >caller's frame, it's pretty difficult. > Ok. However, this way you break everything passed normal way. Make > sure that "make check" passes with your patch. Right now it doesn't. > > -- > With best regards, Anton Korobeynikov > Faculty of Mathematics and Mechanics, Saint Petersburg State University > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From stoklund at 2pi.dk Fri Sep 3 17:38:43 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Fri, 3 Sep 2010 15:38:43 -0700 Subject: [llvm-commits] [llvm] r112983 - in /llvm/trunk/lib/Target/ARM: ARMExpandPseudoInsts.cpp ARMISelDAGToDAG.cpp ARMInstrNEON.td NEONPreAllocPass.cpp In-Reply-To: <20100903181602.C949B2A6C12C@llvm.org> References: <20100903181602.C949B2A6C12C@llvm.org> Message-ID: On Sep 3, 2010, at 11:16 AM, Bob Wilson wrote: > Author: bwilson > Date: Fri Sep 3 13:16:02 2010 > New Revision: 112983 > > URL: http://llvm.org/viewvc/llvm-project?rev=112983&view=rev > Log: > Finish converting the rest of the NEON VLD instructions to use pseudo- > instructions prior to regalloc. Since it's getting a little close to > the 2.8 branch deadline, I'll have to leave the rest of the instructions > handled by the NEONPreAllocPass for now, but I didn't want to leave half > of the VLD instructions converted and the other half not. > > Modified: > llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp > llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp > llvm/trunk/lib/Target/ARM/ARMInstrNEON.td > llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp > > Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=112983&r1=112982&r2=112983&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Fri Sep 3 13:16:02 2010 > @@ -105,16 +105,17 @@ > D2 = TRI->getSubReg(DstReg, ARM::dsub_5); > D3 = TRI->getSubReg(DstReg, ARM::dsub_7); > } > - MIB.addReg(D0).addReg(D1); > + MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)) > + .addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); > if (NumRegs > 2) > - MIB.addReg(D2); > + MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); > if (NumRegs > 3) > - MIB.addReg(D3); > + MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); Thanks! > - MIB.addReg(WBReg, getDefRegState(true) | getDeadRegState(WBIsDead)); > + MIB.addReg(WBReg, RegState::Define | getDeadRegState(WBIsDead)); Right. I think using the enums directly is fine. The functions were added as helpers when your bit is variable like here. Not in this patch, but related: // Copy the addrmode6 operands. bool AddrIsKill = MI.getOperand(OpIdx).isKill(); MIB.addReg(MI.getOperand(OpIdx++).getReg(), getKillRegState(AddrIsKill)); MIB.addImm(MI.getOperand(OpIdx++).getImm()); Is easier like this: MIB.addOperand(MI.getOperand(OpIdx++)); MIB.addOperand(MI.getOperand(OpIdx++)); > } > // Copy the addrmode6 operands. > bool AddrIsKill = MI.getOperand(OpIdx).isKill(); > @@ -128,9 +129,12 @@ > > MIB = AddDefaultPred(MIB); > TransferImpOps(MI, MIB, MIB); > - // Add an implicit def for the super-reg. > - MIB.addReg(DstReg, (getDefRegState(true) | getDeadRegState(DstIsDead) | > - getImplRegState(true))); > + // For an instruction writing the odd subregs, add an implicit use of the > + // super-register because the even subregs were loaded separately. > + if (RegSpc == OddDblSpc) > + MIB.addReg(DstReg, RegState::Implicit); This part is weird. Is OddDblSpc guaranteed to have DstReg live in? In that case, would there already be a DstReg operand on MI that gets transferred by TransferImpOps()? The end result should be: %D0, %D2, ... = VLD ..., %QQQQ0 %D1, %D3, ... = VLD ..., %QQQQ0, %QQQQ0 > + // Add an implicit def for the super-register. > + MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); This is correct, but since TransferImpOps() has added arbitrary imp-ops to your new instruction, it would be better to call addRegisterDefined() / addRegisterDead(). That handles existing operands, and it will even flip the bit on subregs if you pass in a TRI. You could argue that we are missing a MachineInstr::addRegisterUsed() function to complete the quartet. /jakob From echristo at apple.com Fri Sep 3 17:46:31 2010 From: echristo at apple.com (Eric Christopher) Date: Fri, 03 Sep 2010 22:46:31 -0000 Subject: [llvm-commits] [llvm] r113024 - /llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Message-ID: <20100903224631.E93D32A6C12C@llvm.org> Author: echristo Date: Fri Sep 3 17:46:31 2010 New Revision: 113024 URL: http://llvm.org/viewvc/llvm-project?rev=113024&view=rev Log: Reapply this increase to the number of virtual registers. All of the various breakages appear to be dealt with. Patch by Pekka J??skel?inen. Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=113024&r1=113023&r2=113024&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Fri Sep 3 17:46:31 2010 @@ -301,7 +301,7 @@ /// considered to be a 'virtual' register, which is part of the SSA /// namespace. This must be the same for all targets, which means that each /// target is limited to this fixed number of registers. - FirstVirtualRegister = 1024 + FirstVirtualRegister = 16384 }; /// isPhysicalRegister - Return true if the specified register number is in From resistor at mac.com Fri Sep 3 17:47:08 2010 From: resistor at mac.com (Owen Anderson) Date: Fri, 03 Sep 2010 22:47:08 -0000 Subject: [llvm-commits] [llvm] r113025 - in /llvm/trunk: lib/Transforms/Scalar/CorrelatedValuePropagation.cpp test/Transforms/CorrelatedValuePropagation/basic.ll Message-ID: <20100903224708.AC8B42A6C12C@llvm.org> Author: resistor Date: Fri Sep 3 17:47:08 2010 New Revision: 113025 URL: http://llvm.org/viewvc/llvm-project?rev=113025&view=rev Log: Propagate non-local comparisons. Fixes PR1757. Modified: llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp llvm/trunk/test/Transforms/CorrelatedValuePropagation/basic.ll Modified: llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp?rev=113025&r1=113024&r2=113025&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp Fri Sep 3 17:47:08 2010 @@ -17,6 +17,7 @@ #include "llvm/Instructions.h" #include "llvm/Pass.h" #include "llvm/Analysis/LazyValueInfo.h" +#include "llvm/Support/CFG.h" #include "llvm/Transforms/Utils/Local.h" #include "llvm/ADT/Statistic.h" using namespace llvm; @@ -24,6 +25,7 @@ STATISTIC(NumPhis, "Number of phis propagated"); STATISTIC(NumSelects, "Number of selects propagated"); STATISTIC(NumMemAccess, "Number of memory access targets propagated"); +STATISTIC(NumCmps, "Number of comparisons propagated"); namespace { class CorrelatedValuePropagation : public FunctionPass { @@ -32,6 +34,7 @@ bool processSelect(SelectInst *SI); bool processPHI(PHINode *P); bool processMemAccess(Instruction *I); + bool processCmp(CmpInst *C); public: static char ID; @@ -117,6 +120,47 @@ return true; } +/// processCmp - If the value of this comparison could be determined locally, +/// constant propagation would already have figured it out. Instead, walk +/// the predecessors and statically evaluate the comparison based on information +/// available on that edge. If a given static evaluation is true on ALL +/// incoming edges, then it's true universally and we can simplify the compare. +bool CorrelatedValuePropagation::processCmp(CmpInst *C) { + Value *Op0 = C->getOperand(0); + if (isa(Op0) && + cast(Op0)->getParent() == C->getParent()) + return false; + + Constant *Op1 = dyn_cast(C->getOperand(1)); + if (!Op1) return false; + + pred_iterator PI = pred_begin(C->getParent()), PE = pred_end(C->getParent()); + if (PI == PE) return false; + + LazyValueInfo::Tristate Result = LVI->getPredicateOnEdge(C->getPredicate(), + C->getOperand(0), Op1, *PI, C->getParent()); + if (Result == LazyValueInfo::Unknown) return false; + + ++PI; + while (PI != PE) { + LazyValueInfo::Tristate Res = LVI->getPredicateOnEdge(C->getPredicate(), + C->getOperand(0), Op1, *PI, C->getParent()); + if (Res != Result) return false; + ++PI; + } + + ++NumCmps; + + if (Result == LazyValueInfo::True) + C->replaceAllUsesWith(ConstantInt::getTrue(C->getContext())); + else + C->replaceAllUsesWith(ConstantInt::getFalse(C->getContext())); + + C->eraseFromParent(); + + return true; +} + bool CorrelatedValuePropagation::runOnFunction(Function &F) { LVI = &getAnalysis(); @@ -133,6 +177,10 @@ case Instruction::PHI: BBChanged |= processPHI(cast(II)); break; + case Instruction::ICmp: + case Instruction::FCmp: + BBChanged |= processCmp(cast(II)); + break; case Instruction::Load: case Instruction::Store: BBChanged |= processMemAccess(II); Modified: llvm/trunk/test/Transforms/CorrelatedValuePropagation/basic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/CorrelatedValuePropagation/basic.ll?rev=113025&r1=113024&r2=113025&view=diff ============================================================================== --- llvm/trunk/test/Transforms/CorrelatedValuePropagation/basic.ll (original) +++ llvm/trunk/test/Transforms/CorrelatedValuePropagation/basic.ll Fri Sep 3 17:47:08 2010 @@ -56,4 +56,28 @@ %should_be_const = load i8* %a ; CHECK: ret i8 7 ret i8 %should_be_const +} + +; PR1757 +; CHECK: @test4 +define i32 @test4(i32) { +EntryBlock: +; CHECK: icmp sgt i32 %0, 2 + %.demorgan = icmp sgt i32 %0, 2 + br i1 %.demorgan, label %GreaterThanTwo, label %LessThanOrEqualToTwo + +GreaterThanTwo: +; CHECK-NOT: icmp eq i32 %0, 2 + icmp eq i32 %0, 2 +; CHECK: br i1 false + br i1 %1, label %Impossible, label %NotTwoAndGreaterThanTwo + +NotTwoAndGreaterThanTwo: + ret i32 2 + +Impossible: + ret i32 1 + +LessThanOrEqualToTwo: + ret i32 0 } \ No newline at end of file From bruno.cardoso at gmail.com Fri Sep 3 18:24:07 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Fri, 03 Sep 2010 23:24:07 -0000 Subject: [llvm-commits] [llvm] r113031 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20100903232407.239222A6C12C@llvm.org> Author: bruno Date: Fri Sep 3 18:24:06 2010 New Revision: 113031 URL: http://llvm.org/viewvc/llvm-project?rev=113031&view=rev Log: Inline isShuffleMaskLegal into LowerVECTOR_SHUFFLE, so we can start checking each standalone condition and decide whether emit target specific nodes or remove the condition if it's already matched before. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=113031&r1=113030&r2=113031&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Sep 3 18:24:06 2010 @@ -5475,10 +5475,29 @@ if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp)) return CommuteVectorShuffle(SVOp, DAG); - // Check for legal shuffle and return? - SmallVector PermMask; - SVOp->getMask(PermMask); - if (isShuffleMaskLegal(PermMask, VT)) + // The checks below are all present in isShuffleMaskLegal, but they are + // inlined here right now to enable us to directly emit target specific + // nodes, and remove one by one until they don't return Op anymore. + SmallVector M; + SVOp->getMask(M); + + // Very little shuffling can be done for 64-bit vectors right now. + if (VT.getSizeInBits() == 64) + return isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ? Op : SDValue(); + + // FIXME: pshufb, blends, shifts. + if (VT.getVectorNumElements() == 2 || + ShuffleVectorSDNode::isSplatMask(&M[0], VT) || + isMOVLMask(M, VT) || + isSHUFPMask(M, VT) || + isPSHUFDMask(M, VT) || + isPSHUFHWMask(M, VT) || + isPSHUFLWMask(M, VT) || + isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) || + isUNPCKLMask(M, VT) || + isUNPCKHMask(M, VT) || + isUNPCKL_v_undef_Mask(M, VT) || + isUNPCKH_v_undef_Mask(M, VT)) return Op; // Handle v8i16 specifically since SSE can do byte extraction and insertion. From bruno.cardoso at gmail.com Fri Sep 3 18:31:50 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Fri, 03 Sep 2010 23:31:50 -0000 Subject: [llvm-commits] [llvm] r113034 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20100903233150.895C92A6C12C@llvm.org> Author: bruno Date: Fri Sep 3 18:31:50 2010 New Revision: 113034 URL: http://llvm.org/viewvc/llvm-project?rev=113034&view=rev Log: Remove check for unpckl mask Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=113034&r1=113033&r2=113034&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Sep 3 18:31:50 2010 @@ -5494,7 +5494,6 @@ isPSHUFHWMask(M, VT) || isPSHUFLWMask(M, VT) || isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) || - isUNPCKLMask(M, VT) || isUNPCKHMask(M, VT) || isUNPCKL_v_undef_Mask(M, VT) || isUNPCKH_v_undef_Mask(M, VT)) From bruno.cardoso at gmail.com Fri Sep 3 18:32:47 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Fri, 03 Sep 2010 23:32:47 -0000 Subject: [llvm-commits] [llvm] r113035 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20100903233247.A3DB62A6C12C@llvm.org> Author: bruno Date: Fri Sep 3 18:32:47 2010 New Revision: 113035 URL: http://llvm.org/viewvc/llvm-project?rev=113035&view=rev Log: Remove check for unpckh mask Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=113035&r1=113034&r2=113035&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Sep 3 18:32:47 2010 @@ -5494,7 +5494,6 @@ isPSHUFHWMask(M, VT) || isPSHUFLWMask(M, VT) || isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) || - isUNPCKHMask(M, VT) || isUNPCKL_v_undef_Mask(M, VT) || isUNPCKH_v_undef_Mask(M, VT)) return Op; From grosbach at apple.com Fri Sep 3 19:11:59 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 3 Sep 2010 17:11:59 -0700 Subject: [llvm-commits] [llvm] r113016 - /llvm/trunk/lib/CodeGen/RegAllocFast.cpp In-Reply-To: References: <20100903214516.08C592A6C12C@llvm.org> Message-ID: Houston, we have lift-off. (Sep 03 14:53) rev=[113016] success #3868: build successful On Sep 3, 2010, at 3:04 PM, Dale Johannesen wrote: > Jim believes this will fix the PPC buildbot. I've started a run, ETA around 5 PM (Pacific). > > On Sep 3, 2010, at 2:45 PMPDT, Jim Grosbach wrote: > >> Author: grosbach >> Date: Fri Sep 3 16:45:15 2010 >> New Revision: 113016 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=113016&view=rev >> Log: >> previous patch was a little too tricky for its own good. Don't try to >> overload UserInInstr. Explicitly check Allocatable. The early exit in the >> condition will mean the performance impact of the extra test should be >> minimal. >> >> Modified: >> llvm/trunk/lib/CodeGen/RegAllocFast.cpp >> >> Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=113016&r1=113015&r2=113016&view=diff >> ============================================================================== >> --- llvm/trunk/lib/CodeGen/RegAllocFast.cpp (original) >> +++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp Fri Sep 3 16:45:15 2010 >> @@ -113,9 +113,6 @@ >> // Allocatable - vector of allocatable physical registers. >> BitVector Allocatable; >> >> - // Reserved - vector of reserved physical registers. >> - BitVector Reserved; >> - >> // SkippedInstrs - Descriptors of instructions whose clobber list was >> // ignored because all registers were spilled. It is still necessary to >> // mark all the clobbered registers as used by the function. >> @@ -501,7 +498,8 @@ >> // First try to find a completely free register. >> for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) { >> unsigned PhysReg = *I; >> - if (PhysRegState[PhysReg] == regFree && !UsedInInstr.test(PhysReg)) >> + if (PhysRegState[PhysReg] == regFree && !UsedInInstr.test(PhysReg) && >> + Allocatable.test(PhysReg)) >> return assignVirtToPhysReg(LRE, PhysReg); >> } >> >> @@ -510,6 +508,8 @@ >> >> unsigned BestReg = 0, BestCost = spillImpossible; >> for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) { >> + if (!Allocatable.test(*I)) >> + continue; >> unsigned Cost = calcSpillCost(*I); >> // Cost is 0 when all aliases are already disabled. >> if (Cost == 0) >> @@ -712,7 +712,7 @@ >> } >> >> // Restore UsedInInstr to a state usable for allocating normal virtual uses. >> - UsedInInstr = Reserved; >> + UsedInInstr.reset(); >> for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { >> MachineOperand &MO = MI->getOperand(i); >> if (!MO.isReg() || (MO.isDef() && !MO.isEarlyClobber())) continue; >> @@ -838,7 +838,7 @@ >> } >> >> // Track registers used by instruction. >> - UsedInInstr = Reserved; >> + UsedInInstr.reset(); >> >> // First scan. >> // Mark physreg uses and early clobbers as used. >> @@ -916,7 +916,7 @@ >> >> // Track registers defined by instruction - early clobbers and tied uses at >> // this point. >> - UsedInInstr = Reserved; >> + UsedInInstr.reset(); >> if (hasEarlyClobbers) { >> for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { >> MachineOperand &MO = MI->getOperand(i); >> @@ -1014,7 +1014,6 @@ >> >> UsedInInstr.resize(TRI->getNumRegs()); >> Allocatable = TRI->getAllocatableSet(*MF); >> - Reserved = TRI->getReservedRegs(*MF); >> >> // initialize the virtual->physical register map to have a 'null' >> // mapping for all virtual registers >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100903/854b4552/attachment.html From sabre at nondot.org Fri Sep 3 19:12:30 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 04 Sep 2010 00:12:30 -0000 Subject: [llvm-commits] [llvm] r113042 - in /llvm/trunk: lib/Transforms/Scalar/LICM.cpp test/Transforms/LICM/crash.ll Message-ID: <20100904001230.C51AB2A6C12C@llvm.org> Author: lattner Date: Fri Sep 3 19:12:30 2010 New Revision: 113042 URL: http://llvm.org/viewvc/llvm-project?rev=113042&view=rev Log: fix a bug in my licm rewrite when a load from the promoted memory location is being re-stored to the memory location. We would get a dangling pointer from the SSAUpdate data structure and miss a use. This fixes PR8068 Added: llvm/trunk/test/Transforms/LICM/crash.ll Modified: llvm/trunk/lib/Transforms/Scalar/LICM.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LICM.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LICM.cpp?rev=113042&r1=113041&r2=113042&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LICM.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LICM.cpp Fri Sep 3 19:12:30 2010 @@ -743,6 +743,7 @@ // Okay, now we can iterate over all the blocks in the loop with uses, // processing them. Keep track of which loads are loading a live-in value. SmallVector LiveInLoads; + DenseMap ReplacedLoads; for (unsigned LoopUse = 0, e = LoopUses.size(); LoopUse != e; ++LoopUse) { Instruction *User = LoopUses[LoopUse]; @@ -792,15 +793,17 @@ Value *StoredValue = 0; for (BasicBlock::iterator II = BB->begin(), E = BB->end(); II != E; ++II) { if (LoadInst *L = dyn_cast(II)) { - // If this is a load to an unrelated pointer, ignore it. + // If this is a load from an unrelated pointer, ignore it. if (!PointerMustAliases.count(L->getOperand(0))) continue; // If we haven't seen a store yet, this is a live in use, otherwise // use the stored value. - if (StoredValue) + if (StoredValue) { L->replaceAllUsesWith(StoredValue); - else + ReplacedLoads[L] = StoredValue; + } else { LiveInLoads.push_back(L); + } continue; } @@ -846,12 +849,35 @@ Value *NewVal = SSA.GetValueInMiddleOfBlock(ALoad->getParent()); ALoad->replaceAllUsesWith(NewVal); CurAST->copyValue(ALoad, NewVal); + ReplacedLoads[ALoad] = NewVal; } // Now that everything is rewritten, delete the old instructions from the body // of the loop. They should all be dead now. for (unsigned i = 0, e = LoopUses.size(); i != e; ++i) { Instruction *User = LoopUses[i]; + + // If this is a load that still has uses, then the load must have been added + // as a live value in the SSAUpdate data structure for a block (e.g. because + // the loaded value was stored later). In this case, we need to recursively + // propagate the updates until we get to the real value. + if (!User->use_empty()) { + Value *NewVal = ReplacedLoads[User]; + assert(NewVal && "not a replaced load?"); + + // Propagate down to the ultimate replacee. The intermediately loads + // could theoretically already have been deleted, so we don't want to + // dereference the Value*'s. + DenseMap::iterator RLI = ReplacedLoads.find(NewVal); + while (RLI != ReplacedLoads.end()) { + NewVal = RLI->second; + RLI = ReplacedLoads.find(NewVal); + } + + User->replaceAllUsesWith(NewVal); + CurAST->copyValue(User, NewVal); + } + CurAST->deleteValue(User); User->eraseFromParent(); } Added: llvm/trunk/test/Transforms/LICM/crash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LICM/crash.ll?rev=113042&view=auto ============================================================================== --- llvm/trunk/test/Transforms/LICM/crash.ll (added) +++ llvm/trunk/test/Transforms/LICM/crash.ll Fri Sep 3 19:12:30 2010 @@ -0,0 +1,27 @@ +; RUN: opt -licm %s -disable-output + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.0.0" + + +; PR8068 + at g_12 = external global i8, align 1 +define void @test1() nounwind ssp { +entry: + br label %for.body + +for.body: ; preds = %for.cond, %bb.nph + store i8 0, i8* @g_12, align 1 + %tmp6 = load i8* @g_12, align 1 + br label %for.cond + +for.cond: ; preds = %for.body + store i8 %tmp6, i8* @g_12, align 1 + br i1 false, label %for.cond.for.end10_crit_edge, label %for.body + +for.cond.for.end10_crit_edge: ; preds = %for.cond + br label %for.end10 + +for.end10: ; preds = %for.cond.for.end10_crit_edge, %entry + ret void +} From bruno.cardoso at gmail.com Fri Sep 3 19:39:43 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Sat, 04 Sep 2010 00:39:43 -0000 Subject: [llvm-commits] [llvm] r113043 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20100904003943.B5BAE2A6C12C@llvm.org> Author: bruno Date: Fri Sep 3 19:39:43 2010 New Revision: 113043 URL: http://llvm.org/viewvc/llvm-project?rev=113043&view=rev Log: Refactor some code and remove the extra checks for unpckl_undef and unpckh_undef Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=113043&r1=113042&r2=113043&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Sep 3 19:39:43 2010 @@ -5300,31 +5300,14 @@ } } - if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp)) { - // NOTE: isPSHUFDMask can also match this mask, if speed is more - // important than size here, this will be matched by pshufd - if (VT == MVT::v4f32) - return getTargetShuffleNode(X86ISD::UNPCKLPS, dl, VT, V1, V1, DAG); - if (HasSSE2 && VT == MVT::v16i8) - return getTargetShuffleNode(X86ISD::PUNPCKLBW, dl, VT, V1, V1, DAG); - if (HasSSE2 && VT == MVT::v8i16) - return getTargetShuffleNode(X86ISD::PUNPCKLWD, dl, VT, V1, V1, DAG); - if (HasSSE2 && VT == MVT::v4i32) - return getTargetShuffleNode(X86ISD::PUNPCKLDQ, dl, VT, V1, V1, DAG); - } - - if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp)) { - // NOTE: isPSHUFDMask can also match this mask, if speed is more - // important than size here, this will be matched by pshufd - if (VT == MVT::v4f32) - return getTargetShuffleNode(X86ISD::UNPCKHPS, dl, VT, V1, V1, DAG); - if (HasSSE2 && VT == MVT::v16i8) - return getTargetShuffleNode(X86ISD::PUNPCKHBW, dl, VT, V1, V1, DAG); - if (HasSSE2 && VT == MVT::v8i16) - return getTargetShuffleNode(X86ISD::PUNPCKHWD, dl, VT, V1, V1, DAG); - if (HasSSE2 && VT == MVT::v4i32) - return getTargetShuffleNode(X86ISD::PUNPCKHDQ, dl, VT, V1, V1, DAG); - } + // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and + // unpckh_undef). Only use pshufd if speed is more important than size. + if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp)) + if (VT != MVT::v2i64 && VT != MVT::v2f64) + return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG); + if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp)) + if (VT != MVT::v2i64 && VT != MVT::v2f64) + return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG); if (X86::isPSHUFDMask(SVOp)) { // The actual implementation will match the mask in the if above and then @@ -5475,6 +5458,15 @@ if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp)) return CommuteVectorShuffle(SVOp, DAG); + // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and + // unpckh_undef). Only use pshufd if speed is more important than size. + if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp)) + if (VT != MVT::v2i64 && VT != MVT::v2f64) + return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG); + if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp)) + if (VT != MVT::v2i64 && VT != MVT::v2f64) + return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG); + // The checks below are all present in isShuffleMaskLegal, but they are // inlined here right now to enable us to directly emit target specific // nodes, and remove one by one until they don't return Op anymore. @@ -5493,11 +5485,16 @@ isPSHUFDMask(M, VT) || isPSHUFHWMask(M, VT) || isPSHUFLWMask(M, VT) || - isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) || - isUNPCKL_v_undef_Mask(M, VT) || - isUNPCKH_v_undef_Mask(M, VT)) + isPALIGNRMask(M, VT, Subtarget->hasSSSE3())) return Op; + if (X86::isUNPCKL_v_undef_Mask(SVOp)) + if (VT != MVT::v2i64 && VT != MVT::v2f64) + return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG); + if (X86::isUNPCKH_v_undef_Mask(SVOp)) + if (VT != MVT::v2i64 && VT != MVT::v2f64) + return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG); + // Handle v8i16 specifically since SSE can do byte extraction and insertion. if (VT == MVT::v8i16) { SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG); From bruno.cardoso at gmail.com Fri Sep 3 19:43:12 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Sat, 04 Sep 2010 00:43:12 -0000 Subject: [llvm-commits] [llvm] r113044 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20100904004312.B60162A6C12C@llvm.org> Author: bruno Date: Fri Sep 3 19:43:12 2010 New Revision: 113044 URL: http://llvm.org/viewvc/llvm-project?rev=113044&view=rev Log: Remove a duplicated but useless check that i've inserted in the previous commit. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=113044&r1=113043&r2=113044&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Sep 3 19:43:12 2010 @@ -5458,15 +5458,6 @@ if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp)) return CommuteVectorShuffle(SVOp, DAG); - // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and - // unpckh_undef). Only use pshufd if speed is more important than size. - if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp)) - if (VT != MVT::v2i64 && VT != MVT::v2f64) - return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG); - if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp)) - if (VT != MVT::v2i64 && VT != MVT::v2f64) - return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG); - // The checks below are all present in isShuffleMaskLegal, but they are // inlined here right now to enable us to directly emit target specific // nodes, and remove one by one until they don't return Op anymore. From bruno.cardoso at gmail.com Fri Sep 3 19:46:16 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Sat, 04 Sep 2010 00:46:16 -0000 Subject: [llvm-commits] [llvm] r113045 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20100904004616.A71EB2A6C12C@llvm.org> Author: bruno Date: Fri Sep 3 19:46:16 2010 New Revision: 113045 URL: http://llvm.org/viewvc/llvm-project?rev=113045&view=rev Log: One more check from the original isShuffleMaskLegal goes away Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=113045&r1=113044&r2=113045&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Sep 3 19:46:16 2010 @@ -5473,7 +5473,6 @@ ShuffleVectorSDNode::isSplatMask(&M[0], VT) || isMOVLMask(M, VT) || isSHUFPMask(M, VT) || - isPSHUFDMask(M, VT) || isPSHUFHWMask(M, VT) || isPSHUFLWMask(M, VT) || isPALIGNRMask(M, VT, Subtarget->hasSSSE3())) From bruno.cardoso at gmail.com Fri Sep 3 19:50:09 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Sat, 04 Sep 2010 00:50:09 -0000 Subject: [llvm-commits] [llvm] r113047 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20100904005009.1D8142A6C12C@llvm.org> Author: bruno Date: Fri Sep 3 19:50:08 2010 New Revision: 113047 URL: http://llvm.org/viewvc/llvm-project?rev=113047&view=rev Log: Previous isMOVLMask matching already emits targets nodes, remove check Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=113047&r1=113046&r2=113047&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Sep 3 19:50:08 2010 @@ -5471,7 +5471,6 @@ // FIXME: pshufb, blends, shifts. if (VT.getVectorNumElements() == 2 || ShuffleVectorSDNode::isSplatMask(&M[0], VT) || - isMOVLMask(M, VT) || isSHUFPMask(M, VT) || isPSHUFHWMask(M, VT) || isPSHUFLWMask(M, VT) || From bruno.cardoso at gmail.com Fri Sep 3 20:22:57 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Sat, 04 Sep 2010 01:22:57 -0000 Subject: [llvm-commits] [llvm] r113048 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20100904012257.95FEF2A6C12C@llvm.org> Author: bruno Date: Fri Sep 3 20:22:57 2010 New Revision: 113048 URL: http://llvm.org/viewvc/llvm-project?rev=113048&view=rev Log: Emit target specific nodes for isSHUFPMask Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=113048&r1=113047&r2=113048&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Sep 3 20:22:57 2010 @@ -5471,12 +5471,21 @@ // FIXME: pshufb, blends, shifts. if (VT.getVectorNumElements() == 2 || ShuffleVectorSDNode::isSplatMask(&M[0], VT) || - isSHUFPMask(M, VT) || isPSHUFHWMask(M, VT) || isPSHUFLWMask(M, VT) || isPALIGNRMask(M, VT, Subtarget->hasSSSE3())) return Op; + if (isSHUFPMask(M, VT)) { + unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp); + if (VT == MVT::v4f32 || VT == MVT::v4i32) + return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V2, + TargetMask, DAG); + if (VT == MVT::v2f64 || VT == MVT::v2i64) + return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V2, + TargetMask, DAG); + } + if (X86::isUNPCKL_v_undef_Mask(SVOp)) if (VT != MVT::v2i64 && VT != MVT::v2f64) return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG); From bruno.cardoso at gmail.com Fri Sep 3 20:36:46 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Sat, 04 Sep 2010 01:36:46 -0000 Subject: [llvm-commits] [llvm] r113050 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20100904013646.2346B2A6C12C@llvm.org> Author: bruno Date: Fri Sep 3 20:36:45 2010 New Revision: 113050 URL: http://llvm.org/viewvc/llvm-project?rev=113050&view=rev Log: Emit target specific nodes for isPSHUFHWMask and isPSHUFLWMask Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=113050&r1=113049&r2=113050&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Sep 3 20:36:45 2010 @@ -5471,11 +5471,19 @@ // FIXME: pshufb, blends, shifts. if (VT.getVectorNumElements() == 2 || ShuffleVectorSDNode::isSplatMask(&M[0], VT) || - isPSHUFHWMask(M, VT) || - isPSHUFLWMask(M, VT) || isPALIGNRMask(M, VT, Subtarget->hasSSSE3())) return Op; + if (isPSHUFHWMask(M, VT)) + return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1, + X86::getShufflePSHUFHWImmediate(SVOp), + DAG); + + if (isPSHUFLWMask(M, VT)) + return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1, + X86::getShufflePSHUFLWImmediate(SVOp), + DAG); + if (isSHUFPMask(M, VT)) { unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp); if (VT == MVT::v4f32 || VT == MVT::v4i32) From isanbard at gmail.com Fri Sep 3 21:00:34 2010 From: isanbard at gmail.com (Bill Wendling) Date: Sat, 04 Sep 2010 02:00:34 -0000 Subject: [llvm-commits] [test-suite] r113054 - /test-suite/branches/release_28/ Message-ID: <20100904020034.2F7362A6C12C@llvm.org> Author: void Date: Fri Sep 3 21:00:34 2010 New Revision: 113054 URL: http://llvm.org/viewvc/llvm-project?rev=113054&view=rev Log: Creating release_28 branch from test-suite trunk. Added: test-suite/branches/release_28/ - copied from r113053, test-suite/trunk/ From bruno.cardoso at gmail.com Fri Sep 3 21:02:14 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Sat, 04 Sep 2010 02:02:14 -0000 Subject: [llvm-commits] [llvm] r113055 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20100904020214.A4C6C2A6C12C@llvm.org> Author: bruno Date: Fri Sep 3 21:02:14 2010 New Revision: 113055 URL: http://llvm.org/viewvc/llvm-project?rev=113055&view=rev Log: Emit target specific nodes to handle splats starting at zero indicies Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=113055&r1=113054&r2=113055&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Sep 3 21:02:14 2010 @@ -5470,10 +5470,17 @@ // FIXME: pshufb, blends, shifts. if (VT.getVectorNumElements() == 2 || - ShuffleVectorSDNode::isSplatMask(&M[0], VT) || isPALIGNRMask(M, VT, Subtarget->hasSSSE3())) return Op; + if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) && + SVOp->getSplatIndex() == 0 && V2IsUndef) { + if (VT == MVT::v2f64) + return getTargetShuffleNode(X86ISD::UNPCKLPD, dl, VT, V1, V1, DAG); + if (VT == MVT::v2i64) + return getTargetShuffleNode(X86ISD::PUNPCKLQDQ, dl, VT, V1, V1, DAG); + } + if (isPSHUFHWMask(M, VT)) return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1, X86::getShufflePSHUFHWImmediate(SVOp), From bruno.cardoso at gmail.com Fri Sep 3 21:36:07 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Sat, 04 Sep 2010 02:36:07 -0000 Subject: [llvm-commits] [llvm] r113056 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20100904023607.4F2512A6C12C@llvm.org> Author: bruno Date: Fri Sep 3 21:36:07 2010 New Revision: 113056 URL: http://llvm.org/viewvc/llvm-project?rev=113056&view=rev Log: Emit target specific nodes to handle palignr. Do not touch it for MMX versions yet. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=113056&r1=113055&r2=113056&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Sep 3 21:36:07 2010 @@ -2592,6 +2592,7 @@ case X86ISD::PSHUFHW: case X86ISD::PSHUFLW: case X86ISD::SHUFPD: + case X86ISD::PALIGN: case X86ISD::SHUFPS: case X86ISD::MOVLHPS: case X86ISD::MOVLHPD: @@ -2648,6 +2649,7 @@ SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) { switch(Opc) { default: llvm_unreachable("Unknown x86 shuffle node"); + case X86ISD::PALIGN: case X86ISD::SHUFPD: case X86ISD::SHUFPS: return DAG.getNode(Opc, dl, VT, V1, V2, @@ -5262,6 +5264,7 @@ bool V2IsSplat = false; bool HasSSE2 = Subtarget->hasSSE2() || Subtarget->hasAVX(); bool HasSSE3 = Subtarget->hasSSE3() || Subtarget->hasAVX(); + bool HasSSSE3 = Subtarget->hasSSSE3() || Subtarget->hasAVX(); MachineFunction &MF = DAG.getMachineFunction(); bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize); @@ -5469,10 +5472,14 @@ return isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ? Op : SDValue(); // FIXME: pshufb, blends, shifts. - if (VT.getVectorNumElements() == 2 || - isPALIGNRMask(M, VT, Subtarget->hasSSSE3())) + if (VT.getVectorNumElements() == 2) return Op; + if (isPALIGNRMask(M, VT, HasSSSE3)) + return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2, + X86::getShufflePALIGNRImmediate(SVOp), + DAG); + if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) && SVOp->getSplatIndex() == 0 && V2IsUndef) { if (VT == MVT::v2f64) @@ -10780,6 +10787,7 @@ case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG); case X86ISD::SHUFPS: // Handle all target specific shuffles case X86ISD::SHUFPD: + case X86ISD::PALIGN: case X86ISD::PUNPCKHBW: case X86ISD::PUNPCKHWD: case X86ISD::PUNPCKHDQ: From gohman at apple.com Fri Sep 3 21:42:48 2010 From: gohman at apple.com (Dan Gohman) Date: Sat, 04 Sep 2010 02:42:48 -0000 Subject: [llvm-commits] [llvm] r113057 - in /llvm/trunk: lib/Transforms/Utils/LoopSimplify.cpp test/Transforms/LoopSimplify/preserve-scev.ll Message-ID: <20100904024248.7509A2A6C12C@llvm.org> Author: djg Date: Fri Sep 3 21:42:48 2010 New Revision: 113057 URL: http://llvm.org/viewvc/llvm-project?rev=113057&view=rev Log: Fix LoopSimplify to notify ScalarEvolution when splitting a loop backedge into an inner loop, as the new loop iteration may differ substantially. This fixes PR8078. Added: llvm/trunk/test/Transforms/LoopSimplify/preserve-scev.ll Modified: llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp Modified: llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp?rev=113057&r1=113056&r2=113057&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp Fri Sep 3 21:42:48 2010 @@ -46,6 +46,7 @@ #include "llvm/LLVMContext.h" #include "llvm/Type.h" #include "llvm/Analysis/AliasAnalysis.h" +#include "llvm/Analysis/ScalarEvolution.h" #include "llvm/Analysis/Dominators.h" #include "llvm/Analysis/LoopPass.h" #include "llvm/Transforms/Utils/BasicBlockUtils.h" @@ -71,6 +72,7 @@ AliasAnalysis *AA; LoopInfo *LI; DominatorTree *DT; + ScalarEvolution *SE; Loop *L; virtual bool runOnLoop(Loop *L, LPPassManager &LPM); @@ -83,7 +85,7 @@ AU.addPreserved(); AU.addPreserved(); - AU.addPreserved("scalar-evolution"); + AU.addPreserved(); AU.addPreservedID(BreakCriticalEdgesID); // No critical edges added. AU.addPreserved(); AU.addPreservedID(LCSSAID); @@ -121,6 +123,7 @@ LI = &getAnalysis(); AA = getAnalysisIfAvailable(); DT = &getAnalysis(); + SE = getAnalysisIfAvailable(); Changed |= ProcessLoop(L, LPM); @@ -532,6 +535,12 @@ DEBUG(dbgs() << "LoopSimplify: Splitting out a new outer loop\n"); + // If ScalarEvolution is around and knows anything about values in + // this loop, tell it to forget them, because we're about to + // substantially change it. + if (SE) + SE->forgetLoop(L); + BasicBlock *Header = L->getHeader(); BasicBlock *NewBB = SplitBlockPredecessors(Header, &OuterLoopPreds[0], OuterLoopPreds.size(), Added: llvm/trunk/test/Transforms/LoopSimplify/preserve-scev.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopSimplify/preserve-scev.ll?rev=113057&view=auto ============================================================================== --- llvm/trunk/test/Transforms/LoopSimplify/preserve-scev.ll (added) +++ llvm/trunk/test/Transforms/LoopSimplify/preserve-scev.ll Fri Sep 3 21:42:48 2010 @@ -0,0 +1,50 @@ +; RUN: opt -S < %s -indvars | opt -analyze -iv-users | grep {%cmp = icmp slt i32} | grep {= \{%\\.ph,+,1\}<%for.cond>} +; PR8079 + +; LoopSimplify should invalidate indvars when splitting out the +; inner loop. + + at maxStat = external global i32 + +define i32 @test() nounwind { +entry: + br label %for.cond + +for.cond: ; preds = %if.then5, %if.end, %entry + %cuts.1 = phi i32 [ 0, %entry ], [ %inc, %if.then5 ], [ %cuts.1, %if.end ] + %0 = phi i32 [ 0, %entry ], [ %add, %if.end ], [ %add, %if.then5 ] + %add = add i32 %0, 1 + %cmp = icmp slt i32 %0, 1 + %tmp1 = load i32* @maxStat, align 4 + br i1 %cmp, label %for.body, label %for.cond14.preheader + +for.cond14.preheader: ; preds = %for.cond + %cmp1726 = icmp sgt i32 %tmp1, 0 + br i1 %cmp1726, label %for.body18, label %return + +for.body: ; preds = %for.cond + %cmp2 = icmp sgt i32 %tmp1, 100 + br i1 %cmp2, label %return, label %if.end + +if.end: ; preds = %for.body + %cmp4 = icmp sgt i32 %tmp1, -1 + br i1 %cmp4, label %if.then5, label %for.cond + +if.then5: ; preds = %if.end + call void @foo() nounwind + %inc = add i32 %cuts.1, 1 + br label %for.cond + +for.body18: ; preds = %for.body18, %for.cond14.preheader + %i13.027 = phi i32 [ %1, %for.body18 ], [ 0, %for.cond14.preheader ] + call void @foo() nounwind + %1 = add nsw i32 %i13.027, 1 + %tmp16 = load i32* @maxStat, align 4 + %cmp17 = icmp slt i32 %1, %tmp16 + br i1 %cmp17, label %for.body18, label %return + +return: ; preds = %for.body18, %for.body, %for.cond14.preheader + ret i32 0 +} + +declare void @foo() nounwind From bruno.cardoso at gmail.com Fri Sep 3 21:50:13 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Sat, 04 Sep 2010 02:50:13 -0000 Subject: [llvm-commits] [llvm] r113058 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20100904025013.E40E42A6C12C@llvm.org> Author: bruno Date: Fri Sep 3 21:50:13 2010 New Revision: 113058 URL: http://llvm.org/viewvc/llvm-project?rev=113058&view=rev Log: make explicit that we not handle several mmx shuffles Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=113058&r1=113057&r2=113058&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Sep 3 21:50:13 2010 @@ -5467,19 +5467,19 @@ SmallVector M; SVOp->getMask(M); - // Very little shuffling can be done for 64-bit vectors right now. + if (isPALIGNRMask(M, VT, HasSSSE3)) + return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2, + X86::getShufflePALIGNRImmediate(SVOp), + DAG); + + // MMX shuffles not already handled must be expanded. if (VT.getSizeInBits() == 64) - return isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ? Op : SDValue(); + return SDValue(); // FIXME: pshufb, blends, shifts. if (VT.getVectorNumElements() == 2) return Op; - if (isPALIGNRMask(M, VT, HasSSSE3)) - return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2, - X86::getShufflePALIGNRImmediate(SVOp), - DAG); - if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) && SVOp->getSplatIndex() == 0 && V2IsUndef) { if (VT == MVT::v2f64) From bruno.cardoso at gmail.com Fri Sep 3 21:58:56 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Sat, 04 Sep 2010 02:58:56 -0000 Subject: [llvm-commits] [llvm] r113059 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20100904025856.9D9D12A6C12C@llvm.org> Author: bruno Date: Fri Sep 3 21:58:56 2010 New Revision: 113059 URL: http://llvm.org/viewvc/llvm-project?rev=113059&view=rev Log: Remove the last bit of isShuffleMaskLegal checks and improve the comment regarding mmx shuffles Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=113059&r1=113058&r2=113059&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Sep 3 21:58:56 2010 @@ -5472,14 +5472,12 @@ X86::getShufflePALIGNRImmediate(SVOp), DAG); - // MMX shuffles not already handled must be expanded. + // Only a few shuffle masks are handled for 64-bit vectors (MMX), and + // 64-bit vectors which made to this point can't be handled, they are + // expanded. if (VT.getSizeInBits() == 64) return SDValue(); - // FIXME: pshufb, blends, shifts. - if (VT.getVectorNumElements() == 2) - return Op; - if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) && SVOp->getSplatIndex() == 0 && V2IsUndef) { if (VT == MVT::v2f64) From isanbard at gmail.com Fri Sep 3 22:40:32 2010 From: isanbard at gmail.com (Bill Wendling) Date: Sat, 04 Sep 2010 03:40:32 -0000 Subject: [llvm-commits] [test-suite] r113062 - /test-suite/tags/RELEASE_28/ Message-ID: <20100904034032.EB82E2A6C12C@llvm.org> Author: void Date: Fri Sep 3 22:40:32 2010 New Revision: 113062 URL: http://llvm.org/viewvc/llvm-project?rev=113062&view=rev Log: Create RELEASE_28 tag directory. Added: test-suite/tags/RELEASE_28/ From isanbard at gmail.com Fri Sep 3 22:41:37 2010 From: isanbard at gmail.com (Bill Wendling) Date: Sat, 04 Sep 2010 03:41:37 -0000 Subject: [llvm-commits] [test-suite] r113066 - /test-suite/tags/RELEASE_28/rc0/ Message-ID: <20100904034137.25AB52A6C12C@llvm.org> Author: void Date: Fri Sep 3 22:41:36 2010 New Revision: 113066 URL: http://llvm.org/viewvc/llvm-project?rev=113066&view=rev Log: Create rc0 from release_28 branch. Added: test-suite/tags/RELEASE_28/rc0/ - copied from r113065, test-suite/branches/release_28/ From echristo at apple.com Sat Sep 4 02:44:28 2010 From: echristo at apple.com (Eric Christopher) Date: Sat, 4 Sep 2010 00:44:28 -0700 Subject: [llvm-commits] [llvm] r113056 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp In-Reply-To: <20100904023607.4F2512A6C12C@llvm.org> References: <20100904023607.4F2512A6C12C@llvm.org> Message-ID: <07D973DD-C3FE-409A-97B1-968516F75AFF@apple.com> On Sep 3, 2010, at 7:36 PM, Bruno Cardoso Lopes wrote: > bool HasSSE2 = Subtarget->hasSSE2() || Subtarget->hasAVX(); > bool HasSSE3 = Subtarget->hasSSE3() || Subtarget->hasAVX(); > + bool HasSSSE3 = Subtarget->hasSSSE3() || Subtarget->hasAVX(); I understand it's probably just a side effect, but "HasSSE2" = "HasSSE2 or this other thing" reads somewhat oddly :) -eric From echristo at apple.com Sat Sep 4 02:45:42 2010 From: echristo at apple.com (Eric Christopher) Date: Sat, 4 Sep 2010 00:45:42 -0700 Subject: [llvm-commits] [llvm] r113059 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp In-Reply-To: <20100904025856.9D9D12A6C12C@llvm.org> References: <20100904025856.9D9D12A6C12C@llvm.org> Message-ID: On Sep 3, 2010, at 7:58 PM, Bruno Cardoso Lopes wrote: > Remove the last bit of isShuffleMaskLegal checks and improve the comment regarding mmx shuffles Nice set of cleanups, thanks! -eric From bruno.cardoso at gmail.com Sat Sep 4 04:45:24 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Sat, 4 Sep 2010 02:45:24 -0700 Subject: [llvm-commits] [llvm] r113056 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp In-Reply-To: <07D973DD-C3FE-409A-97B1-968516F75AFF@apple.com> References: <20100904023607.4F2512A6C12C@llvm.org> <07D973DD-C3FE-409A-97B1-968516F75AFF@apple.com> Message-ID: On Sat, Sep 4, 2010 at 12:44 AM, Eric Christopher wrote: > > On Sep 3, 2010, at 7:36 PM, Bruno Cardoso Lopes wrote: > >> ? bool HasSSE2 = Subtarget->hasSSE2() || Subtarget->hasAVX(); >> ? bool HasSSE3 = Subtarget->hasSSE3() || Subtarget->hasAVX(); >> + ?bool HasSSSE3 = Subtarget->hasSSSE3() || Subtarget->hasAVX(); > > I understand it's probably just a side effect, but > > "HasSSE2" = "HasSSE2 or this other thing" > > reads somewhat oddly :) Yep, we need to incorporate somehow the AVX with SSE levels, but in a way that we can select the disjoint set of them - selecting only AVX stuff when AVX is turned on (since AVX contains a version of all 128-bit SSE instructions). We try to emulate that right now during isel by defining: def HasSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">; There's a FIXME there explaining why! Anyway, better approaches are always welcome! :) -- Bruno Cardoso Lopes http://www.brunocardoso.cc From baldrick at free.fr Sat Sep 4 10:05:31 2010 From: baldrick at free.fr (Duncan Sands) Date: Sat, 04 Sep 2010 15:05:31 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r113070 - /llvm-gcc-4.2/trunk/libada/Makefile.in Message-ID: <20100904150532.03F142A6C12C@llvm.org> Author: baldrick Date: Sat Sep 4 10:05:31 2010 New Revision: 113070 URL: http://llvm.org/viewvc/llvm-project?rev=113070&view=rev Log: Temporary workaround for PR8051, which breaks the Ada front-end build. Modified: llvm-gcc-4.2/trunk/libada/Makefile.in Modified: llvm-gcc-4.2/trunk/libada/Makefile.in URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/libada/Makefile.in?rev=113070&r1=113069&r2=113070&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/libada/Makefile.in (original) +++ llvm-gcc-4.2/trunk/libada/Makefile.in Sat Sep 4 10:05:31 2010 @@ -55,7 +55,8 @@ include $(GCC_DIR)/libada-mk TARGET_LIBGCC2_CFLAGS= -GNATLIBCFLAGS= -g -O2 +# LLVM LOCAL pass -disable-physical-join as a temporary workaround for PR8051 +GNATLIBCFLAGS= -g -O2 -mllvm -disable-physical-join # Get target-specific overrides for TARGET_LIBGCC2_CFLAGS # and possibly GNATLIBCFLAGS. Currently this uses files # in gcc/config. The 'subst' call is used to rerelativize them From sabre at nondot.org Sat Sep 4 12:45:58 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 04 Sep 2010 17:45:58 -0000 Subject: [llvm-commits] [llvm] r113071 - /llvm/trunk/utils/TableGen/DAGISelMatcherGen.cpp Message-ID: <20100904174558.66D732A6C12C@llvm.org> Author: lattner Date: Sat Sep 4 12:45:58 2010 New Revision: 113071 URL: http://llvm.org/viewvc/llvm-project?rev=113071&view=rev Log: zap dead code. Modified: llvm/trunk/utils/TableGen/DAGISelMatcherGen.cpp Modified: llvm/trunk/utils/TableGen/DAGISelMatcherGen.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelMatcherGen.cpp?rev=113071&r1=113070&r2=113071&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/DAGISelMatcherGen.cpp (original) +++ llvm/trunk/utils/TableGen/DAGISelMatcherGen.cpp Sat Sep 4 12:45:58 2010 @@ -102,7 +102,6 @@ void EmitResultCode(); Matcher *GetMatcher() const { return TheMatcher; } - Matcher *GetCurPredicate() const { return CurPredicate; } private: void AddMatcher(Matcher *NewNode); void InferPossibleTypes(); From sabre at nondot.org Sat Sep 4 13:02:47 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 04 Sep 2010 18:02:47 -0000 Subject: [llvm-commits] [llvm] r113072 - /llvm/trunk/lib/Target/MBlaze/MBlazeISelDAGToDAG.cpp Message-ID: <20100904180247.CA36F2A6C12C@llvm.org> Author: lattner Date: Sat Sep 4 13:02:47 2010 New Revision: 113072 URL: http://llvm.org/viewvc/llvm-project?rev=113072&view=rev Log: remove dead code, mblaze uses SelectAddrRegImm/SelectAddrRegReg, not SelectAddr Modified: llvm/trunk/lib/Target/MBlaze/MBlazeISelDAGToDAG.cpp Modified: llvm/trunk/lib/Target/MBlaze/MBlazeISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeISelDAGToDAG.cpp?rev=113072&r1=113071&r2=113072&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeISelDAGToDAG.cpp Sat Sep 4 13:02:47 2010 @@ -81,10 +81,6 @@ SDNode *getGlobalBaseReg(); SDNode *Select(SDNode *N); - // Complex Pattern. - bool SelectAddr(SDNode *Op, SDValue N, - SDValue &Base, SDValue &Offset); - // Address Selection bool SelectAddrRegReg(SDNode *Op, SDValue N, SDValue &Base, SDValue &Index); bool SelectAddrRegImm(SDNode *Op, SDValue N, SDValue &Disp, SDValue &Base); @@ -190,56 +186,6 @@ return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode(); } -/// ComplexPattern used on MBlazeInstrInfo -/// Used on MBlaze Load/Store instructions -bool MBlazeDAGToDAGISel:: -SelectAddr(SDNode *Op, SDValue Addr, SDValue &Offset, SDValue &Base) { - // if Address is FI, get the TargetFrameIndex. - if (FrameIndexSDNode *FIN = dyn_cast(Addr)) { - Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); - Offset = CurDAG->getTargetConstant(0, MVT::i32); - return true; - } - - // on PIC code Load GA - if (TM.getRelocationModel() == Reloc::PIC_) { - if ((Addr.getOpcode() == ISD::TargetGlobalAddress) || - (Addr.getOpcode() == ISD::TargetConstantPool) || - (Addr.getOpcode() == ISD::TargetJumpTable)){ - Base = CurDAG->getRegister(MBlaze::R15, MVT::i32); - Offset = Addr; - return true; - } - } else { - if ((Addr.getOpcode() == ISD::TargetExternalSymbol || - Addr.getOpcode() == ISD::TargetGlobalAddress)) - return false; - } - - // Operand is a result from an ADD. - if (Addr.getOpcode() == ISD::ADD) { - if (ConstantSDNode *CN = dyn_cast(Addr.getOperand(1))) { - if (isUInt<16>(CN->getZExtValue())) { - - // If the first operand is a FI, get the TargetFI Node - if (FrameIndexSDNode *FIN = dyn_cast - (Addr.getOperand(0))) { - Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); - } else { - Base = Addr.getOperand(0); - } - - Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32); - return true; - } - } - } - - Base = Addr; - Offset = CurDAG->getTargetConstant(0, MVT::i32); - return true; -} - /// Select instructions not customized! Used for /// expanded, promoted and normal instructions SDNode* MBlazeDAGToDAGISel::Select(SDNode *Node) { From sabre at nondot.org Sat Sep 4 13:12:00 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 04 Sep 2010 18:12:00 -0000 Subject: [llvm-commits] [llvm] r113073 - in /llvm/trunk/lib: Analysis/ Bitcode/Reader/ CodeGen/ Target/ARM/ Target/Alpha/ Target/CellSPU/ Target/CellSPU/AsmPrinter/ Target/MSP430/ Target/PowerPC/ Target/PowerPC/AsmPrinter/ Target/SystemZ/ Target/X86/ Transforms/Scalar/ Message-ID: <20100904181200.D5E3E2A6C12C@llvm.org> Author: lattner Date: Sat Sep 4 13:12:00 2010 New Revision: 113073 URL: http://llvm.org/viewvc/llvm-project?rev=113073&view=rev Log: zap dead code. Modified: llvm/trunk/lib/Analysis/CFGPrinter.cpp llvm/trunk/lib/Analysis/LazyValueInfo.cpp llvm/trunk/lib/Analysis/Lint.cpp llvm/trunk/lib/Analysis/LoopPass.cpp llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp llvm/trunk/lib/CodeGen/GCMetadata.cpp llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp llvm/trunk/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp llvm/trunk/lib/Transforms/Scalar/GVN.cpp Modified: llvm/trunk/lib/Analysis/CFGPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/CFGPrinter.cpp?rev=113073&r1=113072&r2=113073&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/CFGPrinter.cpp (original) +++ llvm/trunk/lib/Analysis/CFGPrinter.cpp Sat Sep 4 13:12:00 2010 @@ -69,7 +69,6 @@ struct CFGPrinter : public FunctionPass { static char ID; // Pass identification, replacement for typeid CFGPrinter() : FunctionPass(ID) {} - explicit CFGPrinter(char &pid) : FunctionPass(pid) {} virtual bool runOnFunction(Function &F) { std::string Filename = "cfg." + F.getNameStr() + ".dot"; @@ -102,7 +101,6 @@ struct CFGOnlyPrinter : public FunctionPass { static char ID; // Pass identification, replacement for typeid CFGOnlyPrinter() : FunctionPass(ID) {} - explicit CFGOnlyPrinter(char &pid) : FunctionPass(pid) {} virtual bool runOnFunction(Function &F) { std::string Filename = "cfg." + F.getNameStr() + ".dot"; errs() << "Writing '" << Filename << "'..."; Modified: llvm/trunk/lib/Analysis/LazyValueInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/LazyValueInfo.cpp?rev=113073&r1=113072&r2=113073&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/LazyValueInfo.cpp (original) +++ llvm/trunk/lib/Analysis/LazyValueInfo.cpp Sat Sep 4 13:12:00 2010 @@ -293,10 +293,6 @@ void allUsesReplacedWith(Value* V) { deleted(); } - - LVIValueHandle &operator=(Value *V) { - return *this = LVIValueHandle(V, Parent); - } }; /// ValueCache - This is all of the cached information for all values, Modified: llvm/trunk/lib/Analysis/Lint.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/Lint.cpp?rev=113073&r1=113072&r2=113073&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/Lint.cpp (original) +++ llvm/trunk/lib/Analysis/Lint.cpp Sat Sep 4 13:12:00 2010 @@ -129,12 +129,6 @@ } } - void WriteType(const Type *T) { - if (!T) return; - MessagesStr << ' '; - WriteTypeSymbolic(MessagesStr, T, Mod); - } - // CheckFailed - A check failed, so print out the condition and the message // that failed. This provides a nice place to put a breakpoint if you want // to see why something is not correct. @@ -147,22 +141,6 @@ WriteValue(V3); WriteValue(V4); } - - void CheckFailed(const Twine &Message, const Value *V1, - const Type *T2, const Value *V3 = 0) { - MessagesStr << Message.str() << "\n"; - WriteValue(V1); - WriteType(T2); - WriteValue(V3); - } - - void CheckFailed(const Twine &Message, const Type *T1, - const Type *T2 = 0, const Type *T3 = 0) { - MessagesStr << Message.str() << "\n"; - WriteType(T1); - WriteType(T2); - WriteType(T3); - } }; } Modified: llvm/trunk/lib/Analysis/LoopPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/LoopPass.cpp?rev=113073&r1=113072&r2=113073&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/LoopPass.cpp (original) +++ llvm/trunk/lib/Analysis/LoopPass.cpp Sat Sep 4 13:12:00 2010 @@ -30,7 +30,6 @@ public: static char ID; - PrintLoopPass() : LoopPass(ID), Out(dbgs()) {} PrintLoopPass(const std::string &B, raw_ostream &o) : LoopPass(ID), Banner(B), Out(o) {} Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp?rev=113073&r1=113072&r2=113073&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp (original) +++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp Sat Sep 4 13:12:00 2010 @@ -136,7 +136,6 @@ /// @brief A class for maintaining the slot number definition /// as a placeholder for the actual definition for forward constants defs. class ConstantPlaceHolder : public ConstantExpr { - ConstantPlaceHolder(); // DO NOT IMPLEMENT void operator=(const ConstantPlaceHolder &); // DO NOT IMPLEMENT public: // allocate space for exactly one operand @@ -149,7 +148,7 @@ } /// @brief Methods to support type inquiry through isa, cast, and dyn_cast. - static inline bool classof(const ConstantPlaceHolder *) { return true; } + //static inline bool classof(const ConstantPlaceHolder *) { return true; } static bool classof(const Value *V) { return isa(V) && cast(V)->getOpcode() == Instruction::UserOp1; Modified: llvm/trunk/lib/CodeGen/GCMetadata.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GCMetadata.cpp?rev=113073&r1=113072&r2=113073&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/GCMetadata.cpp (original) +++ llvm/trunk/lib/CodeGen/GCMetadata.cpp Sat Sep 4 13:12:00 2010 @@ -30,7 +30,6 @@ raw_ostream &OS; public: - Printer() : FunctionPass(ID), OS(errs()) {} explicit Printer(raw_ostream &OS) : FunctionPass(ID), OS(OS) {} Modified: llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp?rev=113073&r1=113072&r2=113073&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineModuleInfo.cpp Sat Sep 4 13:12:00 2010 @@ -562,20 +562,3 @@ // in the zero index. return 0; } - -namespace { - /// VariableDebugSorter - Comparison to sort the VariableDbgInfo map - /// by source location, to avoid depending on the arbitrary order that - /// instruction selection visits variables in. - struct VariableDebugSorter { - bool operator()(const MachineModuleInfo::VariableDbgInfoMapTy::value_type &A, - const MachineModuleInfo::VariableDbgInfoMapTy::value_type &B) - const { - if (A.second.second.getLine() != B.second.second.getLine()) - return A.second.second.getLine() < B.second.second.getLine(); - if (A.second.second.getCol() != B.second.second.getCol()) - return A.second.second.getCol() < B.second.second.getCol(); - return false; - } - }; -} Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=113073&r1=113072&r2=113073&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Sat Sep 4 13:12:00 2010 @@ -160,10 +160,6 @@ /// zero. unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO, unsigned Reloc); - unsigned getMovi32Value(const MachineInstr &MI, unsigned OpIdx, - unsigned Reloc) { - return getMovi32Value(MI, MI.getOperand(OpIdx), Reloc); - } /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. /// Modified: llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp?rev=113073&r1=113072&r2=113073&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaISelDAGToDAG.cpp Sat Sep 4 13:12:00 2010 @@ -130,19 +130,6 @@ return (x - y) == r; } - static bool isFPZ(SDValue N) { - ConstantFPSDNode *CN = dyn_cast(N); - return (CN && (CN->getValueAPF().isZero())); - } - static bool isFPZn(SDValue N) { - ConstantFPSDNode *CN = dyn_cast(N); - return (CN && CN->getValueAPF().isNegZero()); - } - static bool isFPZp(SDValue N) { - ConstantFPSDNode *CN = dyn_cast(N); - return (CN && CN->getValueAPF().isPosZero()); - } - public: explicit AlphaDAGToDAGISel(AlphaTargetMachine &TM) : SelectionDAGISel(TM) Modified: llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp?rev=113073&r1=113072&r2=113073&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp Sat Sep 4 13:12:00 2010 @@ -46,10 +46,6 @@ return "STI CBEA SPU Assembly Printer"; } - SPUTargetMachine &getTM() { - return static_cast(TM); - } - /// printInstruction - This method is automatically generated by tablegen /// from the instruction set description. void printInstruction(const MachineInstr *MI, raw_ostream &OS); @@ -64,15 +60,6 @@ } void printOp(const MachineOperand &MO, raw_ostream &OS); - /// printRegister - Print register according to target requirements. - /// - void printRegister(const MachineOperand &MO, bool R0AsZero, raw_ostream &O){ - unsigned RegNo = MO.getReg(); - assert(TargetRegisterInfo::isPhysicalRegister(RegNo) && - "Not physreg??"); - O << getRegisterName(RegNo); - } - void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { const MachineOperand &MO = MI->getOperand(OpNo); if (MO.isReg()) { @@ -93,17 +80,6 @@ void - printS7ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) - { - int value = MI->getOperand(OpNo).getImm(); - value = (value << (32 - 7)) >> (32 - 7); - - assert((value >= -(1 << 8) && value <= (1 << 7) - 1) - && "Invalid s7 argument"); - O << value; - } - - void printU7ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { unsigned int value = MI->getOperand(OpNo).getImm(); @@ -134,12 +110,6 @@ } void - printU32ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) - { - O << (unsigned)MI->getOperand(OpNo).getImm(); - } - - void printMemRegReg(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { // When used as the base register, r0 reads constant zero rather than // the value contained in the register. For this reason, the darwin @@ -221,13 +191,6 @@ printOp(MI->getOperand(OpNo), O); } - void printHBROperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { - // HBR operands are generated in front of branches, hence, the - // program counter plus the target. - O << ".+"; - printOp(MI->getOperand(OpNo), O); - } - void printSymbolHi(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { if (MI->getOperand(OpNo).isImm()) { printS16ImmOperand(MI, OpNo, O); Modified: llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp?rev=113073&r1=113072&r2=113073&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp Sat Sep 4 13:12:00 2010 @@ -221,16 +221,10 @@ return CurDAG->getTargetConstant(Imm, MVT::i32); } - /// getI64Imm - Return a target constant with the specified value, of type - /// i64. - inline SDValue getI64Imm(uint64_t Imm) { - return CurDAG->getTargetConstant(Imm, MVT::i64); - } - /// getSmallIPtrImm - Return a target constant of pointer type. inline SDValue getSmallIPtrImm(unsigned Imm) { return CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy()); - } + } SDNode *emitBuildVector(SDNode *bvNode) { EVT vecVT = bvNode->getValueType(0); Modified: llvm/trunk/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp?rev=113073&r1=113072&r2=113073&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp Sat Sep 4 13:12:00 2010 @@ -60,15 +60,6 @@ return GV != 0 || CP != 0 || ES != 0 || JT != -1; } - bool hasBaseReg() const { - return Base.Reg.getNode() != 0; - } - - void setBaseReg(SDValue Reg) { - BaseType = RegBase; - Base.Reg = Reg; - } - void dump() { errs() << "MSP430ISelAddressMode " << this << '\n'; if (BaseType == RegBase && Base.Reg.getNode() != 0) { Modified: llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp?rev=113073&r1=113072&r2=113073&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp Sat Sep 4 13:12:00 2010 @@ -67,10 +67,6 @@ return "PowerPC Assembly Printer"; } - PPCTargetMachine &getTM() { - return static_cast(TM); - } - unsigned enumRegToMachineReg(unsigned enumReg) { switch (enumReg) { default: llvm_unreachable("Unhandled register!"); Modified: llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp?rev=113073&r1=113072&r2=113073&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp Sat Sep 4 13:12:00 2010 @@ -67,10 +67,6 @@ /// emitBasicBlock - emits the given MachineBasicBlock to memory /// void emitBasicBlock(MachineBasicBlock &MBB); - - /// getValueBit - return the particular bit of Val - /// - unsigned getValueBit(int64_t Val, unsigned bit) { return (Val >> bit) & 1; } }; } Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=113073&r1=113072&r2=113073&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Sat Sep 4 13:12:00 2010 @@ -152,9 +152,6 @@ return false; } - SDValue BuildSDIVSequence(SDNode *N); - SDValue BuildUDIVSequence(SDNode *N); - void InsertVRSaveCode(MachineFunction &MF); virtual const char *getPassName() const { Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp?rev=113073&r1=113072&r2=113073&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp Sat Sep 4 13:12:00 2010 @@ -142,8 +142,6 @@ bool MatchAddress(SDValue N, SystemZRRIAddressMode &AM, bool is12Bit, unsigned Depth = 0); bool MatchAddressBase(SDValue N, SystemZRRIAddressMode &AM); - bool MatchAddressRI(SDValue N, SystemZRRIAddressMode &AM, - bool is12Bit); }; } // end anonymous namespace Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=113073&r1=113072&r2=113073&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Sat Sep 4 13:12:00 2010 @@ -264,12 +264,6 @@ return CurDAG->getTargetConstant(Imm, MVT::i8); } - /// getI16Imm - Return a target constant with the specified value, of type - /// i16. - inline SDValue getI16Imm(unsigned Imm) { - return CurDAG->getTargetConstant(Imm, MVT::i16); - } - /// getI32Imm - Return a target constant with the specified value, of type /// i32. inline SDValue getI32Imm(unsigned Imm) { Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=113073&r1=113072&r2=113073&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Sat Sep 4 13:12:00 2010 @@ -140,9 +140,9 @@ } } - bool operator!=(const Expression &other) const { + /*bool operator!=(const Expression &other) const { return !(*this == other); - } + }*/ }; class ValueTable { @@ -176,7 +176,6 @@ void add(Value *V, uint32_t num); void clear(); void erase(Value *v); - unsigned size(); void setAliasAnalysis(AliasAnalysis* A) { AA = A; } AliasAnalysis *getAliasAnalysis() const { return AA; } void setMemDep(MemoryDependenceAnalysis* M) { MD = M; } From sabre at nondot.org Sat Sep 4 13:17:16 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 04 Sep 2010 18:17:16 -0000 Subject: [llvm-commits] [llvm] r113075 - /llvm/trunk/utils/unittest/googletest/gtest.cc Message-ID: <20100904181716.DD8B02A6C12C@llvm.org> Author: lattner Date: Sat Sep 4 13:17:16 2010 New Revision: 113075 URL: http://llvm.org/viewvc/llvm-project?rev=113075&view=rev Log: delete dead code. Modified: llvm/trunk/utils/unittest/googletest/gtest.cc Modified: llvm/trunk/utils/unittest/googletest/gtest.cc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/unittest/googletest/gtest.cc?rev=113075&r1=113074&r2=113075&view=diff ============================================================================== --- llvm/trunk/utils/unittest/googletest/gtest.cc (original) +++ llvm/trunk/utils/unittest/googletest/gtest.cc Sat Sep 4 13:17:16 2010 @@ -2224,35 +2224,6 @@ return impl_->result()->increment_death_test_count(); } -namespace { - -// A predicate that checks the test name of a TestInfo against a known -// value. -// -// This is used for implementation of the TestCase class only. We put -// it in the anonymous namespace to prevent polluting the outer -// namespace. -// -// TestNameIs is copyable. -class TestNameIs { - public: - // Constructor. - // - // TestNameIs has NO default constructor. - explicit TestNameIs(const char* name) - : name_(name) {} - - // Returns true iff the test name of test_info matches name_. - bool operator()(const TestInfo * test_info) const { - return test_info && internal::String(test_info->name()).Compare(name_) == 0; - } - - private: - internal::String name_; -}; - -} // namespace - namespace internal { // This method expands all parameterized tests registered with macros TEST_P From sabre at nondot.org Sat Sep 4 13:19:16 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 04 Sep 2010 18:19:16 -0000 Subject: [llvm-commits] [llvm] r113077 - /llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp Message-ID: <20100904181916.E16EC2A6C12C@llvm.org> Author: lattner Date: Sat Sep 4 13:19:16 2010 New Revision: 113077 URL: http://llvm.org/viewvc/llvm-project?rev=113077&view=rev Log: dead method. Modified: llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp Modified: llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp?rev=113077&r1=113076&r2=113077&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp (original) +++ llvm/trunk/lib/Analysis/IPA/CallGraphSCCPass.cpp Sat Sep 4 13:19:16 2010 @@ -582,7 +582,6 @@ public: static char ID; - PrintCallGraphPass() : CallGraphSCCPass(ID), Out(dbgs()) {} PrintCallGraphPass(const std::string &B, raw_ostream &o) : CallGraphSCCPass(ID), Banner(B), Out(o) {} From sabre at nondot.org Sat Sep 4 13:45:03 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 04 Sep 2010 18:45:03 -0000 Subject: [llvm-commits] [llvm] r113078 - /llvm/trunk/include/llvm/ADT/StringMap.h Message-ID: <20100904184503.136A32A6C12C@llvm.org> Author: lattner Date: Sat Sep 4 13:45:02 2010 New Revision: 113078 URL: http://llvm.org/viewvc/llvm-project?rev=113078&view=rev Log: fix this to work with allocators that have reference type with compilers that diagnose invalid references to references. Modified: llvm/trunk/include/llvm/ADT/StringMap.h Modified: llvm/trunk/include/llvm/ADT/StringMap.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/StringMap.h?rev=113078&r1=113077&r2=113078&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/StringMap.h (original) +++ llvm/trunk/include/llvm/ADT/StringMap.h Sat Sep 4 13:45:02 2010 @@ -242,6 +242,9 @@ }; +template struct ReferenceAdder { typedef T& result; }; +template struct ReferenceAdder { typedef T result; }; + /// StringMap - This is an unconventional map that is specialized for handling /// keys that are "strings", which are basically ranges of bytes. This does some /// funky memory allocation and hashing things to make it extremely efficient, @@ -269,9 +272,10 @@ clear(); } - - AllocatorTy &getAllocator() { return Allocator; } - const AllocatorTy &getAllocator() const { return Allocator; } + typedef typename ReferenceAdder::result AllocatorRefTy; + typedef typename ReferenceAdder::result AllocatorCRefTy; + AllocatorRefTy getAllocator() { return Allocator; } + AllocatorCRefTy getAllocator() const { return Allocator; } typedef const char* key_type; typedef ValueTy mapped_type; From aggarwa4 at illinois.edu Sat Sep 4 15:55:42 2010 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Sat, 04 Sep 2010 20:55:42 -0000 Subject: [llvm-commits] [poolalloc] r113083 - /poolalloc/trunk/lib/DSA/DSTest.cpp Message-ID: <20100904205542.435062A6C12C@llvm.org> Author: aggarwa4 Date: Sat Sep 4 15:55:42 2010 New Revision: 113083 URL: http://llvm.org/viewvc/llvm-project?rev=113083&view=rev Log: Added check for types Modified: poolalloc/trunk/lib/DSA/DSTest.cpp Modified: poolalloc/trunk/lib/DSA/DSTest.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DSTest.cpp?rev=113083&r1=113082&r2=113083&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/DSTest.cpp (original) +++ poolalloc/trunk/lib/DSA/DSTest.cpp Sat Sep 4 15:55:42 2010 @@ -59,6 +59,9 @@ // For each value, verify they have (or don't have) the specified flags cl::list VerifyFlags("verify-flags", cl::CommaSeparated, cl::ReallyHidden); + // For each value, verify that type is as given + cl::list CheckType("check-type", + cl::CommaSeparated, cl::ReallyHidden); } /// NodeValue -- represents a particular node in a DSGraph @@ -278,7 +281,7 @@ ee = N->type_end(); ii != ee; ++ii) { if (!firstType) O << " "; firstType = false; - O << ii->first << ": "; + O << ii->first << ":"; if (ii->second) { bool first = true; for (svset::const_iterator ni = ii->second->begin(), @@ -295,7 +298,7 @@ O << "VOID"; if (N->isArrayNode()) - O << " array"; + O << "Array"; } static std::string getFlags(DSNode *N) { @@ -436,6 +439,35 @@ return false; } +/// checkTypes -- Verify type for the given nodes. +/// Returns true iff the user specified anything for this option +/// + +static bool checkTypes(llvm::raw_ostream &O, const Module *M, const DataStructures *DS) { + + // Verify all nodes listed in "CheckType" have the same Type + cl::list::iterator I = CheckType.begin(), + E = CheckType.end(); + // If the user specified that a set of values should be in the same node... + if (I != E) { + // last value is type string + std::string typeRef = *(--E); + //typeRef = typeRef.substr(1, typeRef.length()-2); + // Iterate through the remaining to verify they're the same node. + for(; I != E; ++I) { + NodeValue NV(*I, M, DS); + std::string *type = new std::string(); + llvm::raw_string_ostream *test= new llvm::raw_string_ostream(*type); + + printTypesForNode(*test, NV); + + assert(test->str()==typeRef && "Types don't match!"); + } + return true; + } + return false; +} + /// VerifyFlags -- Verify flag properties for the given nodes. /// This is a common enough testing process that this was added to make it simpler. /// Returns true iff the user specified anything for this option. @@ -510,6 +542,7 @@ tested |= checkIfNodesAreSame(O,M,this); tested |= checkIfNodesAreNotSame(O,M,this); tested |= verifyFlags(O,M,this); + tested |= checkTypes(O,M,this); return tested; } From stoklund at 2pi.dk Sat Sep 4 16:09:33 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Sat, 04 Sep 2010 21:09:33 -0000 Subject: [llvm-commits] [llvm] r113084 - in /llvm/trunk: include/llvm/CodeGen/LiveInterval.h lib/CodeGen/LiveInterval.cpp Message-ID: <20100904210933.6FE8A2A6C12C@llvm.org> Author: stoklund Date: Sat Sep 4 16:09:33 2010 New Revision: 113084 URL: http://llvm.org/viewvc/llvm-project?rev=113084&view=rev Log: Remove dead code. Clobber ranges are no longer used when joining physical registers. Instead, all aliases are checked for interference. Modified: llvm/trunk/include/llvm/CodeGen/LiveInterval.h llvm/trunk/lib/CodeGen/LiveInterval.cpp Modified: llvm/trunk/include/llvm/CodeGen/LiveInterval.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveInterval.h?rev=113084&r1=113083&r2=113084&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/LiveInterval.h (original) +++ llvm/trunk/include/llvm/CodeGen/LiveInterval.h Sat Sep 4 16:09:33 2010 @@ -358,21 +358,6 @@ /// cause merging of V1/V2 values numbers and compaction of the value space. VNInfo* MergeValueNumberInto(VNInfo *V1, VNInfo *V2); - /// MergeInClobberRanges - For any live ranges that are not defined in the - /// current interval, but are defined in the Clobbers interval, mark them - /// used with an unknown definition value. Caller must pass in reference to - /// VNInfoAllocator since it will create a new val#. - void MergeInClobberRanges(LiveIntervals &li_, - const LiveInterval &Clobbers, - VNInfo::Allocator &VNInfoAllocator); - - /// MergeInClobberRange - Same as MergeInClobberRanges except it merge in a - /// single LiveRange only. - void MergeInClobberRange(LiveIntervals &li_, - SlotIndex Start, - SlotIndex End, - VNInfo::Allocator &VNInfoAllocator); - /// MergeValueInAsValue - Merge all of the live ranges of a specific val# /// in RHS into this live interval as the specified value number. /// The LiveRanges in RHS are allowed to overlap with LiveRanges in the Modified: llvm/trunk/lib/CodeGen/LiveInterval.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveInterval.cpp?rev=113084&r1=113083&r2=113084&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveInterval.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveInterval.cpp Sat Sep 4 16:09:33 2010 @@ -616,103 +616,6 @@ } -/// MergeInClobberRanges - For any live ranges that are not defined in the -/// current interval, but are defined in the Clobbers interval, mark them -/// used with an unknown definition value. -void LiveInterval::MergeInClobberRanges(LiveIntervals &li_, - const LiveInterval &Clobbers, - VNInfo::Allocator &VNInfoAllocator) { - if (Clobbers.empty()) return; - - DenseMap ValNoMaps; - VNInfo *UnusedValNo = 0; - iterator IP = begin(); - for (const_iterator I = Clobbers.begin(), E = Clobbers.end(); I != E; ++I) { - // For every val# in the Clobbers interval, create a new "unknown" val#. - VNInfo *ClobberValNo = 0; - DenseMap::iterator VI = ValNoMaps.find(I->valno); - if (VI != ValNoMaps.end()) - ClobberValNo = VI->second; - else if (UnusedValNo) - ClobberValNo = UnusedValNo; - else { - UnusedValNo = ClobberValNo = - getNextValue(li_.getInvalidIndex(), 0, false, VNInfoAllocator); - ValNoMaps.insert(std::make_pair(I->valno, ClobberValNo)); - } - - bool Done = false; - SlotIndex Start = I->start, End = I->end; - // If a clobber range starts before an existing range and ends after - // it, the clobber range will need to be split into multiple ranges. - // Loop until the entire clobber range is handled. - while (!Done) { - Done = true; - IP = std::upper_bound(IP, end(), Start); - SlotIndex SubRangeStart = Start; - SlotIndex SubRangeEnd = End; - - // If the start of this range overlaps with an existing liverange, trim it. - if (IP != begin() && IP[-1].end > SubRangeStart) { - SubRangeStart = IP[-1].end; - // Trimmed away the whole range? - if (SubRangeStart >= SubRangeEnd) continue; - } - // If the end of this range overlaps with an existing liverange, trim it. - if (IP != end() && SubRangeEnd > IP->start) { - // If the clobber live range extends beyond the existing live range, - // it'll need at least another live range, so set the flag to keep - // iterating. - if (SubRangeEnd > IP->end) { - Start = IP->end; - Done = false; - } - SubRangeEnd = IP->start; - // If this trimmed away the whole range, ignore it. - if (SubRangeStart == SubRangeEnd) continue; - } - - // Insert the clobber interval. - IP = addRangeFrom(LiveRange(SubRangeStart, SubRangeEnd, ClobberValNo), - IP); - UnusedValNo = 0; - } - } - - if (UnusedValNo) { - // Delete the last unused val#. - valnos.pop_back(); - } -} - -void LiveInterval::MergeInClobberRange(LiveIntervals &li_, - SlotIndex Start, - SlotIndex End, - VNInfo::Allocator &VNInfoAllocator) { - // Find a value # to use for the clobber ranges. If there is already a value# - // for unknown values, use it. - VNInfo *ClobberValNo = - getNextValue(li_.getInvalidIndex(), 0, false, VNInfoAllocator); - - iterator IP = begin(); - IP = std::upper_bound(IP, end(), Start); - - // If the start of this range overlaps with an existing liverange, trim it. - if (IP != begin() && IP[-1].end > Start) { - Start = IP[-1].end; - // Trimmed away the whole range? - if (Start >= End) return; - } - // If the end of this range overlaps with an existing liverange, trim it. - if (IP != end() && End > IP->start) { - End = IP->start; - // If this trimmed away the whole range, ignore it. - if (Start == End) return; - } - - // Insert the clobber interval. - addRangeFrom(LiveRange(Start, End, ClobberValNo), IP); -} /// MergeValueNumberInto - This method is called when two value nubmers /// are found to be equivalent. This eliminates V1, replacing all From espindola at google.com Sat Sep 4 20:17:09 2010 From: espindola at google.com (Rafael Espindola) Date: Sat, 4 Sep 2010 21:17:09 -0400 Subject: [llvm-commits] [llvm-gcc-4.2] r112522 - /llvm-gcc-4.2/trunk/gcc/gcc.c In-Reply-To: <4C7CA1D9.7000307@free.fr> References: <20100830205259.4311B2A6C12C@llvm.org> <4C7CA1D9.7000307@free.fr> Message-ID: > how is this issue handled in gcc mainline? I don't think it is handled at all. > Ciao, > > Duncan. Cheers, -- Rafael ?vila de Esp?ndola From geek4civic at gmail.com Sat Sep 4 20:57:44 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Sun, 5 Sep 2010 10:57:44 +0900 Subject: [llvm-commits] [llvm] r112976 - /llvm/trunk/Makefile.rules In-Reply-To: <20100903172933.45D6E2A6C12C@llvm.org> References: <20100903172933.45D6E2A6C12C@llvm.org> Message-ID: Dan, A bad news, it broke mingw's enable_shared. HAVE_LINK_VERSION_SCRIPT is set on mingw by autoconf, regadless of functionality of it. Also RPATH, RDYNAMIC are set. They are accepted but ignored by GNU ld win32. To reorder "if (HAVE_LINK_VERSION_SCRIPT) clause and if (cyginw || mingw) clause", it would be resolved. Thank you, ...Takumi 2010/9/4 Dan Gohman : > Author: djg > Date: Fri Sep ?3 12:29:33 2010 > New Revision: 112976 > > URL: http://llvm.org/viewvc/llvm-project?rev=112976&view=rev > Log: > Fix Windows stuff to follow the existing source organization. > > Modified: > ? ?llvm/trunk/Makefile.rules > > Modified: llvm/trunk/Makefile.rules > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=112976&r1=112975&r2=112976&view=diff > ============================================================================== > --- llvm/trunk/Makefile.rules (original) > +++ llvm/trunk/Makefile.rules Fri Sep ?3 12:29:33 2010 > @@ -961,23 +961,9 @@ > ?clean-local:: > ? ? ? ?-$(Verb) $(RM) -f $(NativeExportsFile) > ?else > -NativeExportsFile := $(EXPORTED_SYMBOL_FILE) > -endif > -endif > - > -# Now add the linker command-line options to use the native export file. > - > -ifeq ($(HOST_OS),Darwin) > -LLVMLibsOptions += -Wl,-exported_symbols_list,$(NativeExportsFile) > -endif > - > -# GNU ld Win32 accepts .DEF files that contain "DATA" entries. > ?ifeq ($(HOST_OS), $(filter $(HOST_OS), Cygwin MingW)) > +# GNU ld Win32 accepts .DEF files that contain "DATA" entries. > ?NativeExportsFile := $(ObjDir)/$(notdir $(EXPORTED_SYMBOL_FILE:.exports=.def)) > - > -# LLVMLibsOptions is invalidated at processing tools/llvm-shlib. > -SharedLinkOptions += $(NativeExportsFile) > - > ?$(NativeExportsFile): $(EXPORTED_SYMBOL_FILE) $(ObjDir)/.dir > ? ? ? ?$(Echo) Generating $(notdir $@) > ? ? ? ?$(Verb) $(ECHO) "EXPORTS" > $@ > @@ -985,12 +971,28 @@ > ?clean-local:: > ? ? ? ?-$(Verb) $(RM) -f $(NativeExportsFile) > ?else > +# Default behavior: just use the exports file verbatim. > +NativeExportsFile := $(EXPORTED_SYMBOL_FILE) > +endif > +endif > +endif > + > +# Now add the linker command-line options to use the native export file. > + > +# Darwin > +ifeq ($(HOST_OS),Darwin) > +LLVMLibsOptions += -Wl,-exported_symbols_list,$(NativeExportsFile) > +endif > > ?# gold, bfd ld, etc. > ?ifeq ($(HAVE_LINK_VERSION_SCRIPT),1) > ?LLVMLibsOptions += -Wl,--version-script,$(NativeExportsFile) > ?endif > > +# Windows > +ifeq ($(HOST_OS), $(filter $(HOST_OS), Cygwin MingW)) > +# LLVMLibsOptions is invalidated at processing tools/llvm-shlib. > +SharedLinkOptions += $(NativeExportsFile) > ?endif > > ?endif > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From sabre at nondot.org Sat Sep 4 21:18:34 2010 From: sabre at nondot.org (Chris Lattner) Date: Sun, 05 Sep 2010 02:18:34 -0000 Subject: [llvm-commits] [llvm] r113102 - in /llvm/trunk: include/llvm/CodeGen/FastISel.h include/llvm/CodeGen/SelectionDAGISel.h lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp lib/Target/X86/X86FastISel.cpp lib/Target/X86/X86InstrBuilder.h lib/Target/X86/X86InstrInfo.h test/CodeGen/X86/fast-isel-mem.ll Message-ID: <20100905021834.7FD542A6C12C@llvm.org> Author: lattner Date: Sat Sep 4 21:18:34 2010 New Revision: 113102 URL: http://llvm.org/viewvc/llvm-project?rev=113102&view=rev Log: implement rdar://6653118 - fastisel should fold loads where possible. Since mem2reg isn't run at -O0, we get a ton of reloads from the stack, for example, before, this code: int foo(int x, int y, int z) { return x+y+z; } used to compile into: _foo: ## @foo subq $12, %rsp movl %edi, 8(%rsp) movl %esi, 4(%rsp) movl %edx, (%rsp) movl 8(%rsp), %edx movl 4(%rsp), %esi addl %edx, %esi movl (%rsp), %edx addl %esi, %edx movl %edx, %eax addq $12, %rsp ret Now we produce: _foo: ## @foo subq $12, %rsp movl %edi, 8(%rsp) movl %esi, 4(%rsp) movl %edx, (%rsp) movl 8(%rsp), %edx addl 4(%rsp), %edx ## Folded load addl (%rsp), %edx ## Folded load movl %edx, %eax addq $12, %rsp ret Fewer instructions and less register use = faster compiles. Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp llvm/trunk/lib/Target/X86/X86FastISel.cpp llvm/trunk/lib/Target/X86/X86InstrBuilder.h llvm/trunk/lib/Target/X86/X86InstrInfo.h llvm/trunk/test/CodeGen/X86/fast-isel-mem.ll Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FastISel.h?rev=113102&r1=113101&r2=113102&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/FastISel.h (original) +++ llvm/trunk/include/llvm/CodeGen/FastISel.h Sat Sep 4 21:18:34 2010 @@ -39,6 +39,7 @@ class TargetMachine; class TargetRegisterClass; class TargetRegisterInfo; +class LoadInst; /// FastISel - This is a fast-path instruction selection class that /// generates poor code and doesn't support illegal types or non-trivial @@ -102,7 +103,16 @@ /// index value. std::pair getRegForGEPIndex(const Value *V); - /// recomputeInsertPt - Reset InsertPt to prepare for insterting instructions + /// TryToFoldLoad - The specified machine instr operand is a vreg, and that + /// vreg is being provided by the specified load instruction. If possible, + /// try to fold the load as an operand to the instruction, returning true if + /// possible. + virtual bool TryToFoldLoad(MachineInstr * /*MI*/, unsigned /*OpNo*/, + const LoadInst * /*LI*/) { + return false; + } + + /// recomputeInsertPt - Reset InsertPt to prepare for inserting instructions /// into the current block. void recomputeInsertPt(); Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h?rev=113102&r1=113101&r2=113102&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAGISel.h Sat Sep 4 21:18:34 2010 @@ -34,6 +34,7 @@ class ScheduleHazardRecognizer; class GCFunctionInfo; class ScheduleDAGSDNodes; + class LoadInst; /// SelectionDAGISel - This is the common base class used for SelectionDAG-based /// pattern-matching instruction selectors. @@ -282,6 +283,7 @@ void PrepareEHLandingPad(); void SelectAllBasicBlocks(const Function &Fn); + bool TryToFoldFastISelLoad(const LoadInst *LI, FastISel *FastIS); void FinishBasicBlock(); void SelectBasicBlock(BasicBlock::const_iterator Begin, Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=113102&r1=113101&r2=113102&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sat Sep 4 21:18:34 2010 @@ -661,6 +661,43 @@ } } + + + +bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI, + FastISel *FastIS) { + // Don't try to fold volatile loads. Target has to deal with alignment + // constraints. + if (LI->isVolatile()) return false; + + // Figure out which vreg this is going into. + unsigned LoadReg = FastIS->getRegForValue(LI); + assert(LoadReg && "Load isn't already assigned a vreg? "); + + // Check to see what the uses of this vreg are. If it has no uses, or more + // than one use (at the machine instr level) then we can't fold it. + MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg); + if (RI == RegInfo->reg_end()) + return false; + + // See if there is exactly one use of the vreg. If there are multiple uses, + // then the instruction got lowered to multiple machine instructions or the + // use of the loaded value ended up being multiple operands of the result, in + // either case, we can't fold this. + MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI; + if (PostRI != RegInfo->reg_end()) + return false; + + assert(RI.getOperand().isUse() && + "The only use of the vreg must be a use, we haven't emitted the def!"); + + // Ask the target to try folding the load. + return FastIS->TryToFoldLoad(&*RI, RI.getOperandNo(), LI); +} + + + + void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { // Initialize the Fast-ISel state, if needed. FastISel *FastIS = 0; @@ -723,8 +760,21 @@ FastIS->recomputeInsertPt(); // Try to select the instruction with FastISel. - if (FastIS->SelectInstruction(Inst)) + if (FastIS->SelectInstruction(Inst)) { + // If fast isel succeeded, check to see if there is a single-use + // non-volatile load right before the selected instruction, and see if + // the load is used by the instruction. If so, try to fold it. + const Instruction *BeforeInst = 0; + if (Inst != Begin) + BeforeInst = llvm::prior(llvm::prior(BI)); + if (BeforeInst && isa(BeforeInst) && + BeforeInst->hasOneUse() && *BeforeInst->use_begin() == Inst && + TryToFoldFastISelLoad(cast(BeforeInst), FastIS)) { + // If we succeeded, don't re-select the load. + --BI; + } continue; + } // Then handle certain instructions as single-LLVM-Instruction blocks. if (isa(Inst)) { Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=113102&r1=113101&r2=113102&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Sat Sep 4 21:18:34 2010 @@ -63,6 +63,13 @@ virtual bool TargetSelectInstruction(const Instruction *I); + /// TryToFoldLoad - The specified machine instr operand is a vreg, and that + /// vreg is being provided by the specified load instruction. If possible, + /// try to fold the load as an operand to the instruction, returning true if + /// possible. + virtual bool TryToFoldLoad(MachineInstr *MI, unsigned OpNo, + const LoadInst *LI); + #include "X86GenFastISel.inc" private: @@ -1941,6 +1948,34 @@ return ResultReg; } +/// TryToFoldLoad - The specified machine instr operand is a vreg, and that +/// vreg is being provided by the specified load instruction. If possible, +/// try to fold the load as an operand to the instruction, returning true if +/// possible. +bool X86FastISel::TryToFoldLoad(MachineInstr *MI, unsigned OpNo, + const LoadInst *LI) { + X86AddressMode AM; + if (!X86SelectAddress(LI->getOperand(0), AM)) + return false; + + X86InstrInfo &XII = (X86InstrInfo&)TII; + + unsigned Size = TD.getTypeAllocSize(LI->getType()); + unsigned Alignment = LI->getAlignment(); + + SmallVector AddrOps; + AM.getFullAddress(AddrOps); + + MachineInstr *Result = + XII.foldMemoryOperandImpl(*FuncInfo.MF, MI, OpNo, AddrOps, Size, Alignment); + if (Result == 0) return false; + + MI->getParent()->insert(MI, Result); + MI->eraseFromParent(); + return true; +} + + namespace llvm { llvm::FastISel *X86::createFastISel(FunctionLoweringInfo &funcInfo) { return new X86FastISel(funcInfo); Modified: llvm/trunk/lib/Target/X86/X86InstrBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrBuilder.h?rev=113102&r1=113101&r2=113102&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrBuilder.h (original) +++ llvm/trunk/lib/Target/X86/X86InstrBuilder.h Sat Sep 4 21:18:34 2010 @@ -56,6 +56,31 @@ : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(0), GVOpFlags(0) { Base.Reg = 0; } + + + void getFullAddress(SmallVectorImpl &MO) { + assert(Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8); + + if (BaseType == X86AddressMode::RegBase) + MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false, + false, false, false, 0, false)); + else { + assert(BaseType == X86AddressMode::FrameIndexBase); + MO.push_back(MachineOperand::CreateFI(Base.FrameIndex)); + } + + MO.push_back(MachineOperand::CreateImm(Scale)); + MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, + false, false, false, 0, false)); + + if (GV) + MO.push_back(MachineOperand::CreateGA(GV, Disp, GVOpFlags)); + else + MO.push_back(MachineOperand::CreateImm(Disp)); + + MO.push_back(MachineOperand::CreateReg(0, false, false, + false, false, false, 0, false)); + } }; /// addDirectMem - This function is used to add a direct memory reference to the @@ -101,10 +126,11 @@ if (AM.BaseType == X86AddressMode::RegBase) MIB.addReg(AM.Base.Reg); - else if (AM.BaseType == X86AddressMode::FrameIndexBase) + else { + assert(AM.BaseType == X86AddressMode::FrameIndexBase); MIB.addFrameIndex(AM.Base.FrameIndex); - else - assert (0); + } + MIB.addImm(AM.Scale).addReg(AM.IndexReg); if (AM.GV) MIB.addGlobalAddress(AM.GV, AM.Disp, AM.GVOpFlags); Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=113102&r1=113101&r2=113102&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Sat Sep 4 21:18:34 2010 @@ -845,18 +845,18 @@ /// SetSSEDomain - Set the SSEDomain of MI. void SetSSEDomain(MachineInstr *MI, unsigned Domain) const; + MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, + MachineInstr* MI, + unsigned OpNum, + const SmallVectorImpl &MOs, + unsigned Size, unsigned Alignment) const; + private: MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc, MachineFunction::iterator &MFI, MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const; - MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, - MachineInstr* MI, - unsigned OpNum, - const SmallVectorImpl &MOs, - unsigned Size, unsigned Alignment) const; - /// isFrameOperand - Return true and the FrameIndex if the specified /// operand and follow operands form a reference to the stack frame. bool isFrameOperand(const MachineInstr *MI, unsigned int Op, Modified: llvm/trunk/test/CodeGen/X86/fast-isel-mem.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-mem.ll?rev=113102&r1=113101&r2=113102&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/fast-isel-mem.ll (original) +++ llvm/trunk/test/CodeGen/X86/fast-isel-mem.ll Sat Sep 4 21:18:34 2010 @@ -1,10 +1,8 @@ -; RUN: llc < %s -fast-isel -mtriple=i386-apple-darwin | \ -; RUN: grep lazy_ptr, | count 2 -; RUN: llc < %s -fast-isel -march=x86 -relocation-model=static | \ -; RUN: grep lea +; RUN: llc < %s -fast-isel -mtriple=i386-apple-darwin | FileCheck %s @src = external global i32 +; rdar://6653118 define i32 @loadgv() nounwind { entry: %0 = load i32* @src, align 4 @@ -12,6 +10,14 @@ %2 = add i32 %0, %1 store i32 %2, i32* @src ret i32 %2 +; This should fold one of the loads into the add. +; CHECK: loadgv: +; CHECK: movl L_src$non_lazy_ptr, %ecx +; CHECK: movl (%ecx), %eax +; CHECK: addl (%ecx), %eax +; CHECK: movl %eax, (%ecx) +; CHECK: ret + } %stuff = type { i32 (...)** } @@ -21,4 +27,8 @@ entry: store i32 (...)** getelementptr ([4 x i32 (...)*]* @LotsStuff, i32 0, i32 2), i32 (...)*** null, align 4 ret void +; CHECK: _t: +; CHECK: movl $0, %eax +; CHECK: movl L_LotsStuff$non_lazy_ptr, %ecx + } From nicholas at mxc.ca Sun Sep 5 03:22:49 2010 From: nicholas at mxc.ca (Nick Lewycky) Date: Sun, 05 Sep 2010 08:22:49 -0000 Subject: [llvm-commits] [llvm] r113104 - /llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp Message-ID: <20100905082250.05F6A2A6C12C@llvm.org> Author: nicholas Date: Sun Sep 5 03:22:49 2010 New Revision: 113104 URL: http://llvm.org/viewvc/llvm-project?rev=113104&view=rev Log: Fix many bugs when merging weak-strong and weak-weak pairs. We now merge all strong functions first to make sure they're the canonical definitions and then do a second pass looking only for weak functions. Modified: llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp Modified: llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp?rev=113104&r1=113103&r2=113104&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp Sun Sep 5 03:22:49 2010 @@ -69,32 +69,79 @@ STATISTIC(NumFunctionsMerged, "Number of functions merged"); namespace { - /// MergeFunctions finds functions which will generate identical machine code, - /// by considering all pointer types to be equivalent. Once identified, - /// MergeFunctions will fold them by replacing a call to one to a call to a - /// bitcast of the other. - /// - class MergeFunctions : public ModulePass { - public: - static char ID; - MergeFunctions() : ModulePass(ID) {} - - bool runOnModule(Module &M); - - private: - /// MergeTwoFunctions - Merge two equivalent functions. Upon completion, G - /// may be deleted, or may be converted into a thunk. In either case, it - /// should never be visited again. - void MergeTwoFunctions(Function *F, Function *G) const; - - /// WriteThunk - Replace G with a simple tail call to bitcast(F). Also - /// replace direct uses of G with bitcast(F). - void WriteThunk(Function *F, Function *G) const; - TargetData *TD; - }; +static unsigned ProfileFunction(const Function *F) { + const FunctionType *FTy = F->getFunctionType(); + + FoldingSetNodeID ID; + ID.AddInteger(F->size()); + ID.AddInteger(F->getCallingConv()); + ID.AddBoolean(F->hasGC()); + ID.AddBoolean(FTy->isVarArg()); + ID.AddInteger(FTy->getReturnType()->getTypeID()); + for (unsigned i = 0, e = FTy->getNumParams(); i != e; ++i) + ID.AddInteger(FTy->getParamType(i)->getTypeID()); + return ID.ComputeHash(); } +class ComparableFunction { +public: + ComparableFunction(Function *Func, TargetData *TD) + : Func(Func), Hash(ProfileFunction(Func)), TD(TD) {} + + AssertingVH const Func; + const unsigned Hash; + TargetData * const TD; +}; + +struct MergeFunctionsEqualityInfo { + static ComparableFunction *getEmptyKey() { + return reinterpret_cast(0); + } + static ComparableFunction *getTombstoneKey() { + return reinterpret_cast(-1); + } + static unsigned getHashValue(const ComparableFunction *CF) { + return CF->Hash; + } + static bool isEqual(const ComparableFunction *LHS, + const ComparableFunction *RHS); +}; + +/// MergeFunctions finds functions which will generate identical machine code, +/// by considering all pointer types to be equivalent. Once identified, +/// MergeFunctions will fold them by replacing a call to one to a call to a +/// bitcast of the other. +/// +class MergeFunctions : public ModulePass { +public: + static char ID; + MergeFunctions() : ModulePass(ID) {} + + bool runOnModule(Module &M); + +private: + typedef DenseSet FnSetType; + + + /// Insert a ComparableFunction into the FnSet, or merge it away if it's + /// equal to one that's already present. + bool Insert(FnSetType &FnSet, ComparableFunction *NewF); + + /// MergeTwoFunctions - Merge two equivalent functions. Upon completion, G + /// may be deleted, or may be converted into a thunk. In either case, it + /// should never be visited again. + void MergeTwoFunctions(Function *F, Function *G) const; + + /// WriteThunk - Replace G with a simple tail call to bitcast(F). Also + /// replace direct uses of G with bitcast(F). Deletes G. + void WriteThunk(Function *F, Function *G) const; + + TargetData *TD; +}; + +} // end anonymous namespace + char MergeFunctions::ID = 0; INITIALIZE_PASS(MergeFunctions, "mergefunc", "Merge Functions", false, false); @@ -475,7 +522,7 @@ } /// WriteThunk - Replace G with a simple tail call to bitcast(F). Also replace -/// direct uses of G with bitcast(F). +/// direct uses of G with bitcast(F). Deletes G. void MergeFunctions::WriteThunk(Function *F, Function *G) const { if (!G->mayBeOverridden()) { // Redirect direct callers of G to F. @@ -553,100 +600,138 @@ ++NumFunctionsMerged; } -static unsigned ProfileFunction(const Function *F) { - const FunctionType *FTy = F->getFunctionType(); +// Insert - Insert a ComparableFunction into the FnSet, or merge it away if +// equal to one that's already inserted. +bool MergeFunctions::Insert(FnSetType &FnSet, ComparableFunction *NewF) { + std::pair Result = FnSet.insert(NewF); + if (Result.second) + return false; - FoldingSetNodeID ID; - ID.AddInteger(F->size()); - ID.AddInteger(F->getCallingConv()); - ID.AddBoolean(F->hasGC()); - ID.AddBoolean(FTy->isVarArg()); - ID.AddInteger(FTy->getReturnType()->getTypeID()); - for (unsigned i = 0, e = FTy->getNumParams(); i != e; ++i) - ID.AddInteger(FTy->getParamType(i)->getTypeID()); - return ID.ComputeHash(); -} + ComparableFunction *OldF = *Result.first; + assert(OldF && "Expected a hash collision"); -class ComparableFunction { -public: - ComparableFunction(Function *Func, TargetData *TD) - : Func(Func), Hash(ProfileFunction(Func)), TD(TD) {} + // Never thunk a strong function to a weak function. + assert(!OldF->Func->isWeakForLinker() || NewF->Func->isWeakForLinker()); - AssertingVH const Func; - const unsigned Hash; - TargetData * const TD; -}; + DEBUG(dbgs() << " " << OldF->Func->getName() << " == " + << NewF->Func->getName() << '\n'); -struct MergeFunctionsEqualityInfo { - static ComparableFunction *getEmptyKey() { - return reinterpret_cast(0); - } - static ComparableFunction *getTombstoneKey() { - return reinterpret_cast(-1); - } - static unsigned getHashValue(const ComparableFunction *CF) { - return CF->Hash; - } - static bool isEqual(const ComparableFunction *LHS, - const ComparableFunction *RHS) { - if (LHS == RHS) - return true; - if (LHS == getEmptyKey() || LHS == getTombstoneKey() || - RHS == getEmptyKey() || RHS == getTombstoneKey()) - return false; - assert(LHS->TD == RHS->TD && "Comparing functions for different targets"); - return FunctionComparator(LHS->TD, LHS->Func, RHS->Func).Compare(); + Function *DeleteF = NewF->Func; + delete NewF; + MergeTwoFunctions(OldF->Func, DeleteF); + return true; +} + +// IsThunk - This method determines whether or not a given Function is a thunk\// like the ones emitted by this pass and therefore not subject to further +// merging. +static bool IsThunk(const Function *F) { + // The safe direction to fail is to return true. In that case, the function + // will be removed from merging analysis. If we failed to including functions + // then we may try to merge unmergable thing (ie., identical weak functions) + // which will push us into an infinite loop. + + if (F->size() != 1) + return false; + + const BasicBlock *BB = &F->front(); + // A thunk is: + // bitcast-inst* + // optional-reg tail call @thunkee(args...*) + // ret void|optional-reg + // where the args are in the same order as the arguments. + + // Verify that the sequence of bitcast-inst's are all casts of arguments and + // that there aren't any extras (ie. no repeated casts). + int LastArgNo = -1; + BasicBlock::const_iterator I = BB->begin(); + while (const BitCastInst *BCI = dyn_cast(I)) { + const Argument *A = dyn_cast(BCI->getOperand(0)); + if (!A) return false; + if ((int)A->getArgNo() >= LastArgNo) return false; + LastArgNo = A->getArgNo(); + ++I; + } + + // Verify that the call instruction has the same arguments as this function + // and that they're all either the incoming argument or a cast of the right + // argument. + const CallInst *CI = dyn_cast(I++); + if (!CI || !CI->isTailCall() || + CI->getNumArgOperands() != F->arg_size()) return false; + + for (unsigned i = 0, e = CI->getNumArgOperands(); i != e; ++i) { + const Value *V = CI->getArgOperand(i); + const Argument *A = dyn_cast(V); + if (!A) { + const BitCastInst *BCI = dyn_cast(V); + if (!BCI) return false; + A = cast(BCI->getOperand(0)); + } + if (A->getArgNo() != i) return false; } -}; -bool MergeFunctions::runOnModule(Module &M) { - typedef DenseSet FnSetType; + // Verify that the terminator is a ret void (if we're void) or a ret of the + // call's return, or a ret of a bitcast of the call's return. + const Value *RetOp = CI; + if (const BitCastInst *BCI = dyn_cast(I)) { + ++I; + if (BCI->getOperand(0) != CI) return false; + RetOp = BCI; + } + const ReturnInst *RI = dyn_cast(I); + if (!RI) return false; + if (RI->getNumOperands() == 0) + return CI->getType()->isVoidTy(); + return RI->getReturnValue() == CI; +} +bool MergeFunctions::runOnModule(Module &M) { bool Changed = false; TD = getAnalysisIfAvailable(); - std::vector Funcs; - for (Module::iterator F = M.begin(), E = M.end(); F != E; ++F) { - if (!F->isDeclaration() && !F->hasAvailableExternallyLinkage()) - Funcs.push_back(F); - } - bool LocalChanged; do { + DEBUG(dbgs() << "size: " << M.size() << '\n'); LocalChanged = false; - FnSetType FnSet; - for (unsigned i = 0, e = Funcs.size(); i != e;) { - Function *F = Funcs[i]; - ComparableFunction *NewF = new ComparableFunction(F, TD); - std::pair Result = FnSet.insert(NewF); - if (!Result.second) { - ComparableFunction *&OldF = *Result.first; - assert(OldF && "Expected a hash collision"); - - // NewF will be deleted in favour of OldF unless NewF is strong and - // OldF is weak in which case swap them to keep the strong definition. - - if (OldF->Func->isWeakForLinker() && !NewF->Func->isWeakForLinker()) - std::swap(OldF, NewF); - - DEBUG(dbgs() << " " << OldF->Func->getName() << " == " - << NewF->Func->getName() << '\n'); - - Funcs.erase(Funcs.begin() + i); - --e; - - Function *DeleteF = NewF->Func; - delete NewF; - MergeTwoFunctions(OldF->Func, DeleteF); - LocalChanged = true; - Changed = true; - } else { - ++i; + + // Insert only strong functions and merge them. Strong function merging + // always deletes one of them. + for (Module::iterator I = M.begin(), E = M.end(); I != E;) { + Function *F = I++; + if (!F->isDeclaration() && !F->hasAvailableExternallyLinkage() && + !F->isWeakForLinker() && !IsThunk(F)) { + ComparableFunction *CF = new ComparableFunction(F, TD); + LocalChanged |= Insert(FnSet, CF); + } + } + + // Insert only weak functions and merge them. By doing these second we + // create thunks to the strong function when possible. When two weak + // functions are identical, we create a new strong function with two weak + // weak thunks to it which are identical but not mergable. + for (Module::iterator I = M.begin(), E = M.end(); I != E;) { + Function *F = I++; + if (!F->isDeclaration() && !F->hasAvailableExternallyLinkage() && + F->isWeakForLinker() && !IsThunk(F)) { + ComparableFunction *CF = new ComparableFunction(F, TD); + LocalChanged |= Insert(FnSet, CF); } } DeleteContainerPointers(FnSet); + Changed |= LocalChanged; } while (LocalChanged); return Changed; } + +bool MergeFunctionsEqualityInfo::isEqual(const ComparableFunction *LHS, + const ComparableFunction *RHS) { + if (LHS == RHS) + return true; + if (LHS == getEmptyKey() || LHS == getTombstoneKey() || + RHS == getEmptyKey() || RHS == getTombstoneKey()) + return false; + assert(LHS->TD == RHS->TD && "Comparing functions for different targets"); + return FunctionComparator(LHS->TD, LHS->Func, RHS->Func).Compare(); +} From nicholas at mxc.ca Sun Sep 5 04:00:32 2010 From: nicholas at mxc.ca (Nick Lewycky) Date: Sun, 05 Sep 2010 09:00:32 -0000 Subject: [llvm-commits] [llvm] r113105 - /llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp Message-ID: <20100905090032.6F8642A6C12D@llvm.org> Author: nicholas Date: Sun Sep 5 04:00:32 2010 New Revision: 113105 URL: http://llvm.org/viewvc/llvm-project?rev=113105&view=rev Log: Switch FnSet to containing the ComparableFunction instead of a pointer to one. This reduces malloc traffic (yay!) and removes MergeFunctionsEqualityInfo. Modified: llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp Modified: llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp?rev=113105&r1=113104&r2=113105&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp Sun Sep 5 04:00:32 2010 @@ -86,28 +86,58 @@ class ComparableFunction { public: + static const ComparableFunction EmptyKey; + static const ComparableFunction TombstoneKey; + ComparableFunction(Function *Func, TargetData *TD) : Func(Func), Hash(ProfileFunction(Func)), TD(TD) {} - AssertingVH const Func; - const unsigned Hash; - TargetData * const TD; -}; - -struct MergeFunctionsEqualityInfo { - static ComparableFunction *getEmptyKey() { - return reinterpret_cast(0); - } - static ComparableFunction *getTombstoneKey() { - return reinterpret_cast(-1); + Function *getFunc() const { return Func; } + unsigned getHash() const { return Hash; } + TargetData *getTD() const { return TD; } + + // Drops AssertingVH reference to the function. Outside of debug mode, this + // does nothing. + void release() { + assert(Func && + "Attempted to release function twice, or release empty/tombstone!"); + Func = NULL; } - static unsigned getHashValue(const ComparableFunction *CF) { - return CF->Hash; - } - static bool isEqual(const ComparableFunction *LHS, - const ComparableFunction *RHS); + +private: + explicit ComparableFunction(unsigned Hash) + : Func(NULL), Hash(Hash), TD(NULL) {} + + AssertingVH Func; + unsigned Hash; + TargetData *TD; }; +const ComparableFunction ComparableFunction::EmptyKey = ComparableFunction(0); +const ComparableFunction ComparableFunction::TombstoneKey = + ComparableFunction(1); + +} // anonymous namespace + +namespace llvm { + template <> + struct DenseMapInfo { + static ComparableFunction getEmptyKey() { + return ComparableFunction::EmptyKey; + } + static ComparableFunction getTombstoneKey() { + return ComparableFunction::TombstoneKey; + } + static unsigned getHashValue(const ComparableFunction &CF) { + return CF.getHash(); + } + static bool isEqual(const ComparableFunction &LHS, + const ComparableFunction &RHS); + }; +} + +namespace { + /// MergeFunctions finds functions which will generate identical machine code, /// by considering all pointer types to be equivalent. Once identified, /// MergeFunctions will fold them by replacing a call to one to a call to a @@ -121,12 +151,12 @@ bool runOnModule(Module &M); private: - typedef DenseSet FnSetType; + typedef DenseSet FnSetType; /// Insert a ComparableFunction into the FnSet, or merge it away if it's /// equal to one that's already present. - bool Insert(FnSetType &FnSet, ComparableFunction *NewF); + bool Insert(FnSetType &FnSet, ComparableFunction &NewF); /// MergeTwoFunctions - Merge two equivalent functions. Upon completion, G /// may be deleted, or may be converted into a thunk. In either case, it @@ -602,23 +632,23 @@ // Insert - Insert a ComparableFunction into the FnSet, or merge it away if // equal to one that's already inserted. -bool MergeFunctions::Insert(FnSetType &FnSet, ComparableFunction *NewF) { +bool MergeFunctions::Insert(FnSetType &FnSet, ComparableFunction &NewF) { std::pair Result = FnSet.insert(NewF); if (Result.second) return false; - ComparableFunction *OldF = *Result.first; - assert(OldF && "Expected a hash collision"); + const ComparableFunction &OldF = *Result.first; // Never thunk a strong function to a weak function. - assert(!OldF->Func->isWeakForLinker() || NewF->Func->isWeakForLinker()); + assert(!OldF.getFunc()->isWeakForLinker() || + NewF.getFunc()->isWeakForLinker()); - DEBUG(dbgs() << " " << OldF->Func->getName() << " == " - << NewF->Func->getName() << '\n'); + DEBUG(dbgs() << " " << OldF.getFunc()->getName() << " == " + << NewF.getFunc()->getName() << '\n'); - Function *DeleteF = NewF->Func; - delete NewF; - MergeTwoFunctions(OldF->Func, DeleteF); + Function *DeleteF = NewF.getFunc(); + NewF.release(); + MergeTwoFunctions(OldF.getFunc(), DeleteF); return true; } @@ -701,7 +731,7 @@ Function *F = I++; if (!F->isDeclaration() && !F->hasAvailableExternallyLinkage() && !F->isWeakForLinker() && !IsThunk(F)) { - ComparableFunction *CF = new ComparableFunction(F, TD); + ComparableFunction CF = ComparableFunction(F, TD); LocalChanged |= Insert(FnSet, CF); } } @@ -714,24 +744,25 @@ Function *F = I++; if (!F->isDeclaration() && !F->hasAvailableExternallyLinkage() && F->isWeakForLinker() && !IsThunk(F)) { - ComparableFunction *CF = new ComparableFunction(F, TD); + ComparableFunction CF = ComparableFunction(F, TD); LocalChanged |= Insert(FnSet, CF); } } - DeleteContainerPointers(FnSet); Changed |= LocalChanged; } while (LocalChanged); return Changed; } -bool MergeFunctionsEqualityInfo::isEqual(const ComparableFunction *LHS, - const ComparableFunction *RHS) { - if (LHS == RHS) +bool DenseMapInfo::isEqual(const ComparableFunction &LHS, + const ComparableFunction &RHS) { + if (LHS.getFunc() == RHS.getFunc() && + LHS.getHash() == RHS.getHash()) return true; - if (LHS == getEmptyKey() || LHS == getTombstoneKey() || - RHS == getEmptyKey() || RHS == getTombstoneKey()) + if (!LHS.getFunc() || !RHS.getFunc()) return false; - assert(LHS->TD == RHS->TD && "Comparing functions for different targets"); - return FunctionComparator(LHS->TD, LHS->Func, RHS->Func).Compare(); + assert(LHS.getTD() == RHS.getTD() && + "Comparing functions for different targets"); + return FunctionComparator(LHS.getTD(), + LHS.getFunc(), RHS.getFunc()).Compare(); } From nicholas at mxc.ca Sun Sep 5 04:11:38 2010 From: nicholas at mxc.ca (Nick Lewycky) Date: Sun, 05 Sep 2010 09:11:38 -0000 Subject: [llvm-commits] [llvm] r113106 - /llvm/trunk/lib/Transforms/IPO/ExtractGV.cpp Message-ID: <20100905091138.BC0492A6C12C@llvm.org> Author: nicholas Date: Sun Sep 5 04:11:38 2010 New Revision: 113106 URL: http://llvm.org/viewvc/llvm-project?rev=113106&view=rev Log: Fix warning reported by MSVC++ builder. Modified: llvm/trunk/lib/Transforms/IPO/ExtractGV.cpp Modified: llvm/trunk/lib/Transforms/IPO/ExtractGV.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/ExtractGV.cpp?rev=113106&r1=113105&r2=113106&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/ExtractGV.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/ExtractGV.cpp Sun Sep 5 04:11:38 2010 @@ -55,7 +55,7 @@ if (I->hasLocalLinkage()) I->setVisibility(GlobalValue::HiddenVisibility); I->setLinkage(GlobalValue::ExternalLinkage); - if (deleteStuff == Named.count(I)) + if (deleteStuff == (bool)Named.count(I)) I->setInitializer(0); } @@ -65,7 +65,7 @@ if (I->hasLocalLinkage()) I->setVisibility(GlobalValue::HiddenVisibility); I->setLinkage(GlobalValue::ExternalLinkage); - if (deleteStuff == Named.count(I)) + if (deleteStuff == (bool)Named.count(I)) I->deleteBody(); } From baldrick at free.fr Sun Sep 5 08:25:32 2010 From: baldrick at free.fr (Duncan Sands) Date: Sun, 05 Sep 2010 13:25:32 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r113107 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Message-ID: <20100905132532.D7DE92A6C12C@llvm.org> Author: baldrick Date: Sun Sep 5 08:25:32 2010 New Revision: 113107 URL: http://llvm.org/viewvc/llvm-project?rev=113107&view=rev Log: Commit 106612 (stuart) broke the Ada front-end build. The problem is that the Ada f-e likes to mark fields as bitfields whether they are really bitfields or not. In Ada a bitfield can be of any type (including struct and array types), while commit 106612 only works properly for bitfields of scalar type. When building the Ada f-e, the only non-scalar bitfields are actually bogus bitfields - i.e. those that don't need to be handled as bitfields at all. Thus the build can be fixed by using the isBitfield predicate which only returns true for non-bogus bitfields. Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=113107&r1=113106&r2=113107&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Sun Sep 5 08:25:32 2010 @@ -8480,7 +8480,7 @@ // Zero-sized bitfields upset the type converter. If it's not a // bit-field, or it is a bit-field but it has a non-zero precision // type, go ahead and convert it. - if (!DECL_BIT_FIELD_TYPE(Field) || TYPE_PRECISION(TREE_TYPE(Field))) + if (!isBitfield(Field) || TYPE_PRECISION(TREE_TYPE(Field))) Val = Convert(FieldValue); // Decode the field's value. if (DECL_SIZE(Field)) { From lhames at gmail.com Sun Sep 5 08:42:32 2010 From: lhames at gmail.com (Lang Hames) Date: Sun, 05 Sep 2010 13:42:32 -0000 Subject: [llvm-commits] [llvm] r113108 - /llvm/trunk/lib/CodeGen/PBQP/Solution.h Message-ID: <20100905134232.DA3392A6C12C@llvm.org> Author: lhames Date: Sun Sep 5 08:42:32 2010 New Revision: 113108 URL: http://llvm.org/viewvc/llvm-project?rev=113108&view=rev Log: Added initialisers for reduction rule counters. Modified: llvm/trunk/lib/CodeGen/PBQP/Solution.h Modified: llvm/trunk/lib/CodeGen/PBQP/Solution.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PBQP/Solution.h?rev=113108&r1=113107&r2=113108&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PBQP/Solution.h (original) +++ llvm/trunk/lib/CodeGen/PBQP/Solution.h Sun Sep 5 08:42:32 2010 @@ -34,6 +34,10 @@ public: + /// \brief Initialise an empty solution. + Solution() + : r0Reductions(0), r1Reductions(0), r2Reductions(0), rNReductions(0) {} + /// \brief Number of nodes for which selections have been made. /// @return Number of nodes for which selections have been made. unsigned numNodes() const { return selections.size(); } From sabre at nondot.org Sun Sep 5 12:20:46 2010 From: sabre at nondot.org (Chris Lattner) Date: Sun, 05 Sep 2010 17:20:46 -0000 Subject: [llvm-commits] [llvm] r113109 - in /llvm/trunk: lib/Analysis/ValueTracking.cpp test/Transforms/GlobalOpt/crash.ll Message-ID: <20100905172046.846022A6C12C@llvm.org> Author: lattner Date: Sun Sep 5 12:20:46 2010 New Revision: 113109 URL: http://llvm.org/viewvc/llvm-project?rev=113109&view=rev Log: fix PR8063, a crash in globalopt in the malloc analysis code. Modified: llvm/trunk/lib/Analysis/ValueTracking.cpp llvm/trunk/test/Transforms/GlobalOpt/crash.ll Modified: llvm/trunk/lib/Analysis/ValueTracking.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ValueTracking.cpp?rev=113109&r1=113108&r2=113109&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ValueTracking.cpp (original) +++ llvm/trunk/lib/Analysis/ValueTracking.cpp Sun Sep 5 12:20:46 2010 @@ -880,19 +880,20 @@ } Value *Mul0 = NULL; - Value *Mul1 = NULL; - bool M0 = ComputeMultiple(Op0, Base, Mul0, - LookThroughSExt, Depth+1); - bool M1 = ComputeMultiple(Op1, Base, Mul1, - LookThroughSExt, Depth+1); - - if (M0) { - if (isa(Op1) && isa(Mul0)) { - // V == Base * (Mul0 * Op1), so return (Mul0 * Op1) - Multiple = ConstantExpr::getMul(cast(Mul0), - cast(Op1)); - return true; - } + if (ComputeMultiple(Op0, Base, Mul0, LookThroughSExt, Depth+1)) { + if (Constant *Op1C = dyn_cast(Op1)) + if (Constant *MulC = dyn_cast(Mul0)) { + if (Op1C->getType()->getPrimitiveSizeInBits() < + MulC->getType()->getPrimitiveSizeInBits()) + Op1C = ConstantExpr::getZExt(Op1C, MulC->getType()); + if (Op1C->getType()->getPrimitiveSizeInBits() > + MulC->getType()->getPrimitiveSizeInBits()) + MulC = ConstantExpr::getZExt(MulC, Op1C->getType()); + + // V == Base * (Mul0 * Op1), so return (Mul0 * Op1) + Multiple = ConstantExpr::getMul(MulC, Op1C); + return true; + } if (ConstantInt *Mul0CI = dyn_cast(Mul0)) if (Mul0CI->getValue() == 1) { @@ -902,13 +903,21 @@ } } - if (M1) { - if (isa(Op0) && isa(Mul1)) { - // V == Base * (Mul1 * Op0), so return (Mul1 * Op0) - Multiple = ConstantExpr::getMul(cast(Mul1), - cast(Op0)); - return true; - } + Value *Mul1 = NULL; + if (ComputeMultiple(Op1, Base, Mul1, LookThroughSExt, Depth+1)) { + if (Constant *Op0C = dyn_cast(Op0)) + if (Constant *MulC = dyn_cast(Mul1)) { + if (Op0C->getType()->getPrimitiveSizeInBits() < + MulC->getType()->getPrimitiveSizeInBits()) + Op0C = ConstantExpr::getZExt(Op0C, MulC->getType()); + if (Op0C->getType()->getPrimitiveSizeInBits() > + MulC->getType()->getPrimitiveSizeInBits()) + MulC = ConstantExpr::getZExt(MulC, Op0C->getType()); + + // V == Base * (Mul1 * Op0), so return (Mul1 * Op0) + Multiple = ConstantExpr::getMul(MulC, Op0C); + return true; + } if (ConstantInt *Mul1CI = dyn_cast(Mul1)) if (Mul1CI->getValue() == 1) { Modified: llvm/trunk/test/Transforms/GlobalOpt/crash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GlobalOpt/crash.ll?rev=113109&r1=113108&r2=113109&view=diff ============================================================================== --- llvm/trunk/test/Transforms/GlobalOpt/crash.ll (original) +++ llvm/trunk/test/Transforms/GlobalOpt/crash.ll Sun Sep 5 12:20:46 2010 @@ -40,3 +40,18 @@ } declare noalias i8* @malloc(i64) nounwind + + +; PR8063 + at permute_bitrev.bitrev = internal global i32* null, align 8 +define void @permute_bitrev() nounwind { +entry: + %tmp = load i32** @permute_bitrev.bitrev, align 8 + %conv = sext i32 0 to i64 + %mul = mul i64 %conv, 4 + %call = call i8* @malloc(i64 %mul) + %0 = bitcast i8* %call to i32* + store i32* %0, i32** @permute_bitrev.bitrev, align 8 + ret void +} + From sabre at nondot.org Sun Sep 5 15:03:10 2010 From: sabre at nondot.org (Chris Lattner) Date: Sun, 05 Sep 2010 20:03:10 -0000 Subject: [llvm-commits] [llvm] r113113 - /llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Message-ID: <20100905200310.2857D2A6C12C@llvm.org> Author: lattner Date: Sun Sep 5 15:03:09 2010 New Revision: 113113 URL: http://llvm.org/viewvc/llvm-project?rev=113113&view=rev Log: eliminate some non-obvious casts. UndefValue isa Constant. Modified: llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Modified: llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp?rev=113113&r1=113112&r2=113113&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Sun Sep 5 15:03:09 2010 @@ -443,8 +443,8 @@ // Try to use constant folding to simplify the binary operator. for (unsigned i = 0, e = LHSVals.size(); i != e; ++i) { - Constant *V = LHSVals[i].first ? LHSVals[i].first : - cast(UndefValue::get(BO->getType())); + Constant *V = LHSVals[i].first; + if (V == 0) V = UndefValue::get(BO->getType()); Constant *Folded = ConstantExpr::get(BO->getOpcode(), V, CI); PushConstantIntOrUndef(Result, Folded, LHSVals[i].second); @@ -518,8 +518,8 @@ ComputeValueKnownInPredecessors(I->getOperand(0), BB, LHSVals); for (unsigned i = 0, e = LHSVals.size(); i != e; ++i) { - Constant *V = LHSVals[i].first ? LHSVals[i].first : - cast(UndefValue::get(CmpConst->getType())); + Constant *V = LHSVals[i].first; + if (V == 0) V = UndefValue::get(CmpConst->getType()); Constant *Folded = ConstantExpr::getCompare(Cmp->getPredicate(), V, CmpConst); PushConstantIntOrUndef(Result, Folded, LHSVals[i].second); From sabre at nondot.org Sun Sep 5 15:10:47 2010 From: sabre at nondot.org (Chris Lattner) Date: Sun, 05 Sep 2010 20:10:47 -0000 Subject: [llvm-commits] [llvm] r113114 - in /llvm/trunk/lib/Transforms/Scalar: JumpThreading.cpp LowerAtomic.cpp Message-ID: <20100905201047.BBB2A2A6C12C@llvm.org> Author: lattner Date: Sun Sep 5 15:10:47 2010 New Revision: 113114 URL: http://llvm.org/viewvc/llvm-project?rev=113114&view=rev Log: Change lower atomic pass to use IntrinsicInst to simplify it a bit. Modified: llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp llvm/trunk/lib/Transforms/Scalar/LowerAtomic.cpp Modified: llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp?rev=113114&r1=113113&r2=113114&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Sun Sep 5 15:10:47 2010 @@ -726,10 +726,9 @@ if (Baseline != LazyValueInfo::Unknown) { // Check that all remaining incoming values match the first one. while (++PI != PE) { - LazyValueInfo::Tristate Ret = LVI->getPredicateOnEdge( - CondCmp->getPredicate(), - CondCmp->getOperand(0), - CondConst, *PI, BB); + LazyValueInfo::Tristate Ret = + LVI->getPredicateOnEdge(CondCmp->getPredicate(), + CondCmp->getOperand(0), CondConst, *PI, BB); if (Ret != Baseline) break; } Modified: llvm/trunk/lib/Transforms/Scalar/LowerAtomic.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LowerAtomic.cpp?rev=113114&r1=113113&r2=113114&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LowerAtomic.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LowerAtomic.cpp Sun Sep 5 15:10:47 2010 @@ -18,22 +18,15 @@ #include "llvm/Function.h" #include "llvm/Instruction.h" #include "llvm/Instructions.h" +#include "llvm/IntrinsicInst.h" #include "llvm/Intrinsics.h" #include "llvm/Pass.h" #include "llvm/Support/IRBuilder.h" - using namespace llvm; -namespace { - -bool LowerAtomicIntrinsic(CallInst *CI) { - IRBuilder<> Builder(CI->getParent(), CI); - - Function *Callee = CI->getCalledFunction(); - if (!Callee) - return false; - - unsigned IID = Callee->getIntrinsicID(); +static bool LowerAtomicIntrinsic(IntrinsicInst *II) { + IRBuilder<> Builder(II->getParent(), II); + unsigned IID = II->getIntrinsicID(); switch (IID) { case Intrinsic::memory_barrier: break; @@ -48,8 +41,8 @@ case Intrinsic::atomic_load_min: case Intrinsic::atomic_load_umax: case Intrinsic::atomic_load_umin: { - Value *Ptr = CI->getArgOperand(0); - Value *Delta = CI->getArgOperand(1); + Value *Ptr = II->getArgOperand(0); + Value *Delta = II->getArgOperand(1); LoadInst *Orig = Builder.CreateLoad(Ptr); Value *Res = NULL; @@ -96,32 +89,32 @@ } Builder.CreateStore(Res, Ptr); - CI->replaceAllUsesWith(Orig); + II->replaceAllUsesWith(Orig); break; } case Intrinsic::atomic_swap: { - Value *Ptr = CI->getArgOperand(0); - Value *Val = CI->getArgOperand(1); + Value *Ptr = II->getArgOperand(0); + Value *Val = II->getArgOperand(1); LoadInst *Orig = Builder.CreateLoad(Ptr); Builder.CreateStore(Val, Ptr); - CI->replaceAllUsesWith(Orig); + II->replaceAllUsesWith(Orig); break; } case Intrinsic::atomic_cmp_swap: { - Value *Ptr = CI->getArgOperand(0); - Value *Cmp = CI->getArgOperand(1); - Value *Val = CI->getArgOperand(2); + Value *Ptr = II->getArgOperand(0); + Value *Cmp = II->getArgOperand(1); + Value *Val = II->getArgOperand(2); LoadInst *Orig = Builder.CreateLoad(Ptr); Value *Equal = Builder.CreateICmpEQ(Orig, Cmp); Value *Res = Builder.CreateSelect(Equal, Val, Orig); Builder.CreateStore(Res, Ptr); - CI->replaceAllUsesWith(Orig); + II->replaceAllUsesWith(Orig); break; } @@ -129,28 +122,25 @@ return false; } - assert(CI->use_empty() && + assert(II->use_empty() && "Lowering should have eliminated any uses of the intrinsic call!"); - CI->eraseFromParent(); + II->eraseFromParent(); return true; } -struct LowerAtomic : public BasicBlockPass { - static char ID; - LowerAtomic() : BasicBlockPass(ID) {} - bool runOnBasicBlock(BasicBlock &BB) { - bool Changed = false; - for (BasicBlock::iterator DI = BB.begin(), DE = BB.end(); DI != DE; ) { - Instruction *Inst = DI++; - if (CallInst *CI = dyn_cast(Inst)) - Changed |= LowerAtomicIntrinsic(CI); +namespace { + struct LowerAtomic : public BasicBlockPass { + static char ID; + LowerAtomic() : BasicBlockPass(ID) {} + bool runOnBasicBlock(BasicBlock &BB) { + bool Changed = false; + for (BasicBlock::iterator DI = BB.begin(), DE = BB.end(); DI != DE; ) + if (IntrinsicInst *II = dyn_cast(DI++)) + Changed |= LowerAtomicIntrinsic(II); + return Changed; } - return Changed; - } - -}; - + }; } char LowerAtomic::ID = 0; From sabre at nondot.org Sun Sep 5 15:13:07 2010 From: sabre at nondot.org (Chris Lattner) Date: Sun, 05 Sep 2010 20:13:07 -0000 Subject: [llvm-commits] [llvm] r113115 - /llvm/trunk/lib/Transforms/Scalar/LowerAtomic.cpp Message-ID: <20100905201307.983A62A6C12C@llvm.org> Author: lattner Date: Sun Sep 5 15:13:07 2010 New Revision: 113115 URL: http://llvm.org/viewvc/llvm-project?rev=113115&view=rev Log: more cleanups Modified: llvm/trunk/lib/Transforms/Scalar/LowerAtomic.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LowerAtomic.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LowerAtomic.cpp?rev=113115&r1=113114&r2=113115&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LowerAtomic.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LowerAtomic.cpp Sun Sep 5 15:13:07 2010 @@ -14,12 +14,8 @@ #define DEBUG_TYPE "loweratomic" #include "llvm/Transforms/Scalar.h" -#include "llvm/BasicBlock.h" #include "llvm/Function.h" -#include "llvm/Instruction.h" -#include "llvm/Instructions.h" #include "llvm/IntrinsicInst.h" -#include "llvm/Intrinsics.h" #include "llvm/Pass.h" #include "llvm/Support/IRBuilder.h" using namespace llvm; @@ -41,51 +37,46 @@ case Intrinsic::atomic_load_min: case Intrinsic::atomic_load_umax: case Intrinsic::atomic_load_umin: { - Value *Ptr = II->getArgOperand(0); - Value *Delta = II->getArgOperand(1); + Value *Ptr = II->getArgOperand(0), *Delta = II->getArgOperand(1); LoadInst *Orig = Builder.CreateLoad(Ptr); Value *Res = NULL; switch (IID) { - default: assert(0 && "Unrecognized atomic modify operation"); - case Intrinsic::atomic_load_add: - Res = Builder.CreateAdd(Orig, Delta); - break; - case Intrinsic::atomic_load_sub: - Res = Builder.CreateSub(Orig, Delta); - break; - case Intrinsic::atomic_load_and: - Res = Builder.CreateAnd(Orig, Delta); - break; - case Intrinsic::atomic_load_nand: - Res = Builder.CreateNot(Builder.CreateAnd(Orig, Delta)); - break; - case Intrinsic::atomic_load_or: - Res = Builder.CreateOr(Orig, Delta); - break; - case Intrinsic::atomic_load_xor: - Res = Builder.CreateXor(Orig, Delta); - break; - case Intrinsic::atomic_load_max: - Res = Builder.CreateSelect(Builder.CreateICmpSLT(Orig, Delta), - Delta, - Orig); - break; - case Intrinsic::atomic_load_min: - Res = Builder.CreateSelect(Builder.CreateICmpSLT(Orig, Delta), - Orig, - Delta); - break; - case Intrinsic::atomic_load_umax: - Res = Builder.CreateSelect(Builder.CreateICmpULT(Orig, Delta), - Delta, - Orig); - break; - case Intrinsic::atomic_load_umin: - Res = Builder.CreateSelect(Builder.CreateICmpULT(Orig, Delta), - Orig, - Delta); - break; + default: assert(0 && "Unrecognized atomic modify operation"); + case Intrinsic::atomic_load_add: + Res = Builder.CreateAdd(Orig, Delta); + break; + case Intrinsic::atomic_load_sub: + Res = Builder.CreateSub(Orig, Delta); + break; + case Intrinsic::atomic_load_and: + Res = Builder.CreateAnd(Orig, Delta); + break; + case Intrinsic::atomic_load_nand: + Res = Builder.CreateNot(Builder.CreateAnd(Orig, Delta)); + break; + case Intrinsic::atomic_load_or: + Res = Builder.CreateOr(Orig, Delta); + break; + case Intrinsic::atomic_load_xor: + Res = Builder.CreateXor(Orig, Delta); + break; + case Intrinsic::atomic_load_max: + Res = Builder.CreateSelect(Builder.CreateICmpSLT(Orig, Delta), + Delta, Orig); + break; + case Intrinsic::atomic_load_min: + Res = Builder.CreateSelect(Builder.CreateICmpSLT(Orig, Delta), + Orig, Delta); + break; + case Intrinsic::atomic_load_umax: + Res = Builder.CreateSelect(Builder.CreateICmpULT(Orig, Delta), + Delta, Orig); + break; + case Intrinsic::atomic_load_umin: + Res = Builder.CreateSelect(Builder.CreateICmpULT(Orig, Delta), + Orig, Delta); + break; } Builder.CreateStore(Res, Ptr); @@ -94,26 +85,21 @@ } case Intrinsic::atomic_swap: { - Value *Ptr = II->getArgOperand(0); - Value *Val = II->getArgOperand(1); - + Value *Ptr = II->getArgOperand(0), *Val = II->getArgOperand(1); LoadInst *Orig = Builder.CreateLoad(Ptr); Builder.CreateStore(Val, Ptr); - II->replaceAllUsesWith(Orig); break; } case Intrinsic::atomic_cmp_swap: { - Value *Ptr = II->getArgOperand(0); - Value *Cmp = II->getArgOperand(1); + Value *Ptr = II->getArgOperand(0), *Cmp = II->getArgOperand(1); Value *Val = II->getArgOperand(2); LoadInst *Orig = Builder.CreateLoad(Ptr); Value *Equal = Builder.CreateICmpEQ(Orig, Cmp); Value *Res = Builder.CreateSelect(Equal, Val, Orig); Builder.CreateStore(Res, Ptr); - II->replaceAllUsesWith(Orig); break; } From clattner at apple.com Sun Sep 5 15:16:25 2010 From: clattner at apple.com (Chris Lattner) Date: Sun, 5 Sep 2010 13:16:25 -0700 Subject: [llvm-commits] [PATCH] Phi node folding improvements In-Reply-To: <20100730201530.GA1396@pcc.me.uk> References: <20100730201530.GA1396@pcc.me.uk> Message-ID: <043636EC-FCA5-4AB2-AA18-1AA510C4412F@apple.com> On Jul 30, 2010, at 1:15 PM, Peter Collingbourne wrote: > Hi, > > The attached patches improve the flexibility of the phi node folding > mechanism by assigning a cost to each non-trapping instruction and > allowing the user to specify a maximum cost threshold. By increasing > the threshold the user can apply phi node folding to more complex > expressions. > > I developed this patch as part of my work with the Klee symbolic > virtual machine, which can handle symbolic expressions containing > selects more efficiently than branches conditional on symbolic > expressions. However I imagine it could also provide an advantage on > architectures with relatively expensive branch operations (I haven't > done any experiments to determine if this is the case though). > > The patches should not contain any changes to default functionality, > except for adding more instructions to the list of "cheap" (folded > by default) instructions. Hi Peter, Sorry for the delay on this. The first patch certainly looks ok, but we need testcases for each of these changes. -Chris -------------- next part -------------- A non-text attachment was scrubbed... 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Name: 0003-Expose-phi-node-folding-cost-threshold-as-command-li.patch Type: text/x-diff Size: 1618 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100905/5a0a3d69/attachment-0002.bin From sabre at nondot.org Sun Sep 5 15:22:09 2010 From: sabre at nondot.org (Chris Lattner) Date: Sun, 05 Sep 2010 20:22:09 -0000 Subject: [llvm-commits] [llvm] r113116 - /llvm/trunk/lib/Target/X86/README-SSE.txt Message-ID: <20100905202209.57A792A6C12C@llvm.org> Author: lattner Date: Sun Sep 5 15:22:09 2010 New Revision: 113116 URL: http://llvm.org/viewvc/llvm-project?rev=113116&view=rev Log: update this. Modified: llvm/trunk/lib/Target/X86/README-SSE.txt Modified: llvm/trunk/lib/Target/X86/README-SSE.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/README-SSE.txt?rev=113116&r1=113115&r2=113116&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/README-SSE.txt (original) +++ llvm/trunk/lib/Target/X86/README-SSE.txt Sun Sep 5 15:22:09 2010 @@ -20,7 +20,28 @@ //===---------------------------------------------------------------------===// SSE has instructions for doing operations on complex numbers, we should pattern -match them. Compiling this: +match them. For example, this should turn into a horizontal add: + +typedef float __attribute__((vector_size(16))) v4f32; +float f32(v4f32 A) { + return A[0]+A[1]+A[2]+A[3]; +} + +Instead we get this: + +_f32: ## @f32 + pshufd $1, %xmm0, %xmm1 ## xmm1 = xmm0[1,0,0,0] + addss %xmm0, %xmm1 + pshufd $3, %xmm0, %xmm2 ## xmm2 = xmm0[3,0,0,0] + movhlps %xmm0, %xmm0 ## xmm0 = xmm0[1,1] + movaps %xmm0, %xmm3 + addss %xmm1, %xmm3 + movdqa %xmm2, %xmm0 + addss %xmm3, %xmm0 + ret + +Also, there are cases where some simple local SLP would improve codegen a bit. +compiling this: _Complex float f32(_Complex float A, _Complex float B) { return A+B; @@ -28,19 +49,17 @@ into: -_f32: +_f32: ## @f32 movdqa %xmm0, %xmm2 addss %xmm1, %xmm2 - pshufd $16, %xmm2, %xmm2 - pshufd $1, %xmm1, %xmm1 - pshufd $1, %xmm0, %xmm0 - addss %xmm1, %xmm0 - pshufd $16, %xmm0, %xmm1 - movdqa %xmm2, %xmm0 - unpcklps %xmm1, %xmm0 + pshufd $1, %xmm1, %xmm1 ## xmm1 = xmm1[1,0,0,0] + pshufd $1, %xmm0, %xmm3 ## xmm3 = xmm0[1,0,0,0] + addss %xmm1, %xmm3 + movaps %xmm2, %xmm0 + unpcklps %xmm3, %xmm0 ## xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1] ret -seems silly. +seems silly when it could just be one addps. //===---------------------------------------------------------------------===// From sabre at nondot.org Sun Sep 5 15:33:40 2010 From: sabre at nondot.org (Chris Lattner) Date: Sun, 05 Sep 2010 20:33:40 -0000 Subject: [llvm-commits] [llvm] r113117 - /llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Message-ID: <20100905203340.B1BE32A6C12C@llvm.org> Author: lattner Date: Sun Sep 5 15:33:40 2010 New Revision: 113117 URL: http://llvm.org/viewvc/llvm-project?rev=113117&view=rev Log: add a comment about where this should eventually move. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=113117&r1=113116&r2=113117&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Sun Sep 5 15:33:40 2010 @@ -327,6 +327,13 @@ // Handle thread local data for mach-o which requires us to output an // additional structure of data and mangle the original symbol so that we // can reference it later. + // + // TODO: This should become an "emit thread local global" method on TLOF. + // All of this macho specific stuff should be sunk down into TLOFMachO and + // stuff like "TLSExtraDataSection" should no longer be part of the parent + // TLOF class. This will also make it more obvious that stuff like + // MCStreamer::EmitTBSSSymbol is macho specific and only called from macho + // specific code. if (GVKind.isThreadLocal() && MAI->hasMachoTBSSDirective()) { // Emit the .tbss symbol MCSymbol *MangSym = From sabre at nondot.org Sun Sep 5 15:49:45 2010 From: sabre at nondot.org (Chris Lattner) Date: Sun, 05 Sep 2010 20:49:45 -0000 Subject: [llvm-commits] [llvm] r113118 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <20100905204945.B78FC2A6C12C@llvm.org> Author: lattner Date: Sun Sep 5 15:49:45 2010 New Revision: 113118 URL: http://llvm.org/viewvc/llvm-project?rev=113118&view=rev Log: some random notes. Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=113118&r1=113117&r2=113118&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Sun Sep 5 15:49:45 2010 @@ -295,7 +295,10 @@

        LLVM 2.8 includes several major new capabilities:

          -
        • .
          • +
        • atomic lowering pass.
          • +
        • RegionInfo pass: opt -regions analyze" or "opt -view-regions". +
          • +
        • ARMGlobalMerge:
        From clattner at apple.com Sun Sep 5 16:19:19 2010 From: clattner at apple.com (Chris Lattner) Date: Sun, 5 Sep 2010 14:19:19 -0700 Subject: [llvm-commits] [llvm] r109359 - in /llvm/trunk: include/llvm/Target/TargetLowering.h lib/Target/ARM/ARM.h lib/Target/ARM/ARMGlobalMerge.cpp lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMISelLowering.h lib/Target/ARM/ARMTargetMachine.cpp lib/Target/ARM/ARMTargetMachine.h In-Reply-To: <20100724215209.2D6D52A6C12E@llvm.org> References: <20100724215209.2D6D52A6C12E@llvm.org> Message-ID: On Jul 24, 2010, at 2:52 PM, Anton Korobeynikov wrote: > URL: http://llvm.org/viewvc/llvm-project?rev=109359&view=rev > Log: > Hook in GlobalMerge pass Hey Anton, Sorry for the delay reviewing this. My general thought on this is that it should be a target-independent pass. PowerPC would certainly benefit from this as well, probably x86 in PIC mode as well, among others. Can this be generalized to support other targets? Also, you added no regression tests for this. Please fix this, this is a major new feature, and we want to make sure it is not broken in the future. > +++ llvm/trunk/include/llvm/Target/TargetLowering.h Sat Jul 24 16:52:08 2010 > @@ -792,6 +792,12 @@ > return false; > } > > + /// getMaximalGlobalOffset - Returns the maximal possible offset which can be > + /// used for loads / stores from the global. > + virtual unsigned getMaximalGlobalOffset() const { > + return 0; > + } If this stays an ARM-specific pass, there is no reason to have this as a target hook. If the hook stays, please improve the comment to better describe what this means and what is says. Could you just use the existing hooks that LSR uses to determine reg+imm offsets? The "offset from a global" depends on the type being accessed and many other things, so it isn't clear how to define this hook. Using the existing LSR hooks seems beneficial because if you end up turning [reg1+reg2] into tmp = reg1+imm [tmp+reg2] addressing, you actually don't save a register. I understand that you're not modeling this yet, but in any case, fewer hooks is better. -Chris From sabre at nondot.org Sun Sep 5 16:18:45 2010 From: sabre at nondot.org (Chris Lattner) Date: Sun, 05 Sep 2010 21:18:45 -0000 Subject: [llvm-commits] [llvm] r113119 - /llvm/trunk/lib/Target/ARM/ARMGlobalMerge.cpp Message-ID: <20100905211845.692E32A6C12C@llvm.org> Author: lattner Date: Sun Sep 5 16:18:45 2010 New Revision: 113119 URL: http://llvm.org/viewvc/llvm-project?rev=113119&view=rev Log: cleanups. Modified: llvm/trunk/lib/Target/ARM/ARMGlobalMerge.cpp Modified: llvm/trunk/lib/Target/ARM/ARMGlobalMerge.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMGlobalMerge.cpp?rev=113119&r1=113118&r2=113119&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMGlobalMerge.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMGlobalMerge.cpp Sun Sep 5 16:18:45 2010 @@ -67,7 +67,7 @@ using namespace llvm; namespace { - class LLVM_LIBRARY_VISIBILITY ARMGlobalMerge : public FunctionPass { + class ARMGlobalMerge : public FunctionPass { /// TLI - Keep a pointer of a TargetLowering to consult for determining /// target type sizes. const TargetLowering *TLI; @@ -81,7 +81,7 @@ : FunctionPass(ID), TLI(tli) {} virtual bool doInitialization(Module &M); - virtual bool runOnFunction(Function& F); + virtual bool runOnFunction(Function &F); const char *getPassName() const { return "Merge internal globals"; @@ -95,13 +95,11 @@ struct GlobalCmp { const TargetData *TD; - GlobalCmp(const TargetData *td): - TD(td) { } + GlobalCmp(const TargetData *td) : TD(td) { } - bool operator() (const GlobalVariable* GV1, - const GlobalVariable* GV2) { - const Type* Ty1 = cast(GV1->getType())->getElementType(); - const Type* Ty2 = cast(GV2->getType())->getElementType(); + bool operator()(const GlobalVariable *GV1, const GlobalVariable *GV2) { + const Type *Ty1 = cast(GV1->getType())->getElementType(); + const Type *Ty2 = cast(GV2->getType())->getElementType(); return (TD->getTypeAllocSize(Ty1) < TD->getTypeAllocSize(Ty2)); } @@ -131,26 +129,23 @@ std::vector Tys; std::vector Inits; for (j = i; MergedSize < MaxOffset && j != e; ++j) { - const Type* Ty = Globals[j]->getType()->getElementType(); + const Type *Ty = Globals[j]->getType()->getElementType(); Tys.push_back(Ty); Inits.push_back(Globals[j]->getInitializer()); MergedSize += TD->getTypeAllocSize(Ty); } - StructType* MergedTy = StructType::get(M.getContext(), Tys); - Constant* MergedInit = ConstantStruct::get(MergedTy, Inits); - GlobalVariable* MergedGV = new GlobalVariable(M, MergedTy, isConst, + StructType *MergedTy = StructType::get(M.getContext(), Tys); + Constant *MergedInit = ConstantStruct::get(MergedTy, Inits); + GlobalVariable *MergedGV = new GlobalVariable(M, MergedTy, isConst, GlobalValue::InternalLinkage, MergedInit, "merged"); for (size_t k = i; k < j; ++k) { - SmallVector Idx; - Idx.push_back(ConstantInt::get(Int32Ty, 0)); - Idx.push_back(ConstantInt::get(Int32Ty, k-i)); - - Constant* GEP = - ConstantExpr::getInBoundsGetElementPtr(MergedGV, - &Idx[0], Idx.size()); - + Constant *Idx[2] = { + ConstantInt::get(Int32Ty, 0), + ConstantInt::get(Int32Ty, k-i) + }; + Constant *GEP = ConstantExpr::getInBoundsGetElementPtr(MergedGV, Idx, 2); Globals[k]->replaceAllUsesWith(GEP); Globals[k]->eraseFromParent(); } @@ -161,7 +156,7 @@ } -bool ARMGlobalMerge::doInitialization(Module& M) { +bool ARMGlobalMerge::doInitialization(Module &M) { SmallVector Globals, ConstGlobals; const TargetData *TD = TLI->getTargetData(); unsigned MaxOffset = TLI->getMaximalGlobalOffset(); @@ -203,7 +198,7 @@ return Changed; } -bool ARMGlobalMerge::runOnFunction(Function& F) { +bool ARMGlobalMerge::runOnFunction(Function &F) { return false; } From clattner at apple.com Sun Sep 5 16:22:02 2010 From: clattner at apple.com (Chris Lattner) Date: Sun, 5 Sep 2010 14:22:02 -0700 Subject: [llvm-commits] [patch][Target/PTX] Create PTX backend In-Reply-To: References: Message-ID: <3169B6A7-65A6-4742-AA1F-E28618D1F764@apple.com> On Aug 27, 2010, at 12:01 AM, Che-Liang Chiou wrote: > SVN revision: r112257 > > re-generate patch against svn head. This conflicts in the autoconf stuff, but otherwise looks good to me. Please regenerate and ask someone to apply for you, thanks! -Chris > > On Wed, Aug 11, 2010 at 11:10 AM, Che-Liang Chiou wrote: >> SVN revision: 110776 >> >> This patch is a part of upstream work of a PTX backend using LLVM code >> generator. >> >> Change list summary: >> - Add an empty backend that is merely compilable >> - Add PTX entry to autoconf/configure.ac and include/llvm/ADT/Triple.h >> >> Outcome: >> $ ./configure --enable-targets=ptx >> $ make >> $ llc -version | grep ptx >> ptx - PTX >> >> Misc: >> - Diff of auto-generated files are put in a separated patch >> - The autotool version on my machine is newer than >> autoconf/AutoGegen.sh requires, so the diff of auto-gen'd files might >> be differ with that on your machine >> >> Cheers, >> Che-Liang >> > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From sabre at nondot.org Sun Sep 5 16:25:44 2010 From: sabre at nondot.org (Chris Lattner) Date: Sun, 05 Sep 2010 21:25:44 -0000 Subject: [llvm-commits] [llvm] r113120 - /llvm/trunk/tools/llvm-diff/llvm-diff.cpp Message-ID: <20100905212544.273982A6C12C@llvm.org> Author: lattner Date: Sun Sep 5 16:25:43 2010 New Revision: 113120 URL: http://llvm.org/viewvc/llvm-project?rev=113120&view=rev Log: cleanups: mark stuff static, only tagdecls should be in anon namespaces. Modified: llvm/trunk/tools/llvm-diff/llvm-diff.cpp Modified: llvm/trunk/tools/llvm-diff/llvm-diff.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-diff/llvm-diff.cpp?rev=113120&r1=113119&r2=113120&view=diff ============================================================================== --- llvm/trunk/tools/llvm-diff/llvm-diff.cpp (original) +++ llvm/trunk/tools/llvm-diff/llvm-diff.cpp Sun Sep 5 16:25:43 2010 @@ -63,18 +63,19 @@ } namespace { -struct DiffContext { - DiffContext(Value *L, Value *R) - : L(L), R(R), Differences(false), IsFunction(isa(L)) {} - Value *L; - Value *R; - bool Differences; - bool IsFunction; - DenseMap LNumbering; - DenseMap RNumbering; -}; + struct DiffContext { + DiffContext(Value *L, Value *R) + : L(L), R(R), Differences(false), IsFunction(isa(L)) {} + Value *L; + Value *R; + bool Differences; + bool IsFunction; + DenseMap LNumbering; + DenseMap RNumbering; + }; +} -void ComputeNumbering(Function *F, DenseMap &Numbering) { +static void ComputeNumbering(Function *F, DenseMap &Numbering){ unsigned IN = 0; // Arguments get the first numbers. @@ -98,6 +99,7 @@ assert(!Numbering.empty() && "asked for numbering but numbering was no-op"); } +namespace { class DiffConsumer : public DifferenceEngine::Consumer { private: raw_ostream &out; @@ -273,7 +275,7 @@ } }; -} +} // end anonymous namespace static void diffGlobal(DifferenceEngine &Engine, Module *L, Module *R, StringRef Name) { @@ -292,14 +294,14 @@ errs() << "No function named @" << Name << " in right module\n"; } -cl::opt LeftFilename(cl::Positional, - cl::desc(""), - cl::Required); -cl::opt RightFilename(cl::Positional, - cl::desc(""), - cl::Required); -cl::list GlobalsToCompare(cl::Positional, - cl::desc("")); +static cl::opt LeftFilename(cl::Positional, + cl::desc(""), + cl::Required); +static cl::opt RightFilename(cl::Positional, + cl::desc(""), + cl::Required); +static cl::list GlobalsToCompare(cl::Positional, + cl::desc("")); int main(int argc, char **argv) { cl::ParseCommandLineOptions(argc, argv); From clattner at apple.com Sun Sep 5 16:27:02 2010 From: clattner at apple.com (Chris Lattner) Date: Sun, 5 Sep 2010 14:27:02 -0700 Subject: [llvm-commits] [llvm] r109739 - in /llvm/trunk/tools/llvm-diff: ./ CMakeLists.txt DifferenceEngine.cpp DifferenceEngine.h Makefile llvm-diff.cpp In-Reply-To: <20100729075327.507082A6C12D@llvm.org> References: <20100729075327.507082A6C12D@llvm.org> Message-ID: <0BCA2D6B-4927-4EFC-B77F-1A33DD2BC7AA@apple.com> On Jul 29, 2010, at 12:53 AM, John McCall wrote: > Author: rjmccall > Date: Thu Jul 29 02:53:27 2010 > New Revision: 109739 > > URL: http://llvm.org/viewvc/llvm-project?rev=109739&view=rev > Log: > Add the llvm-diff tool, which performs a relatively naive structural > diff of a function. There's a lot of cruft in the current version, and > it's pretty far from perfect, but it's usable. > > Currently only capable of comparing functions. Currently ignores metadata. > Currently ignores most attributes of functions and instructions. > > Patches welcome. Very cool John. Does this actually work? What are its advantages over diff? Please add a couple of simple tests to llvm/test, and a man page in llvm/docs/CommandGuide/. A demo of how it works would be nice too :). It doesn't matter much to me, but the large methods in DiffConsumer should probably be moved out of line so that it is easier to understand the class. -Chris From asl at math.spbu.ru Sun Sep 5 16:58:18 2010 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Mon, 6 Sep 2010 01:58:18 +0400 Subject: [llvm-commits] [llvm] r109359 - in /llvm/trunk: include/llvm/Target/TargetLowering.h lib/Target/ARM/ARM.h lib/Target/ARM/ARMGlobalMerge.cpp lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMISelLowering.h lib/Target/ARM/ARMTargetMachine.cpp li Message-ID: Hi, Chris > Sorry for the delay reviewing this. ?My general thought on this is that it should be a target-independent pass. ?PowerPC would certainly benefit from this as well, probably x86 in PIC mode as well, among others. ?Can this be generalized to support other targets? Yes, surely. > Also, you added no regression tests for this. ?Please fix this, this is a major new feature, and we want to make sure it is not broken in the future. Ok, will add. > Could you just use the existing hooks that LSR uses to determine reg+imm offsets? ?The "offset from a global" depends on the type being accessed and many other things, so it isn't clear how to define this hook. ?Using the existing LSR hooks seems beneficial because if you end up turning [reg1+reg2] into tmp = reg1+imm [tmp+reg2] addressing, you actually don't save a register. ?I understand that you're not modeling this yet, but in any case, fewer hooks is better. Do you mean TLI::isLegalAddressingMode() ? If yes, then it's too inflexible, it allows only simple value types and will return nothing on e.g. array of structs. -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From clattner at apple.com Sun Sep 5 17:09:25 2010 From: clattner at apple.com (Chris Lattner) Date: Sun, 5 Sep 2010 15:09:25 -0700 Subject: [llvm-commits] InitializeNativeAsmPrinter implementation In-Reply-To: <318832.28864.qm@web55601.mail.re4.yahoo.com> References: <318832.28864.qm@web55601.mail.re4.yahoo.com> Message-ID: <8888711F-1CCE-4D57-8B1D-95D9F9DADDA7@apple.com> On Jul 22, 2010, at 8:50 AM, Jan Sjodin wrote: > This patch is to prepare for MCJIT. I had to normalized the names for > the initializers to have "Target" in the name to be able to use the > LLVM_NATIVE_ARCH in the macros. Hi Jan, This patch applies but doesn't build correctly: In file included from EDDisassembler.cpp:37: /Volumes/Data/Users/sabre/llvm/include/llvm/Target/TargetSelect.h:123:5: error: use of undeclared identifier 'LLVMInitializeX86AsmPrinter'; did you mean 'LLVMInitializeX86TargetAsmPrinter'? LLVM_NATIVE_ASMPRINTER(); ^~~~~~~~~~~~~~~~~~~~~~ Can you update it for mainline? -Chris From clattner at apple.com Sun Sep 5 17:12:26 2010 From: clattner at apple.com (Chris Lattner) Date: Sun, 5 Sep 2010 15:12:26 -0700 Subject: [llvm-commits] [PATCH 1/3] Include original pass name in the PassPrinter's name. In-Reply-To: <1283525635-16182-2-git-send-email-grosser@fim.uni-passau.de> References: <1283525635-16182-1-git-send-email-grosser@fim.uni-passau.de> <1283525635-16182-2-git-send-email-grosser@fim.uni-passau.de> Message-ID: <46480460-80CC-4B34-8C0A-8E4169781204@apple.com> On Sep 3, 2010, at 7:53 AM, Tobias Grosser wrote: > --- > tools/opt/opt.cpp | 46 ++++++++++++++++++++++++++++++++++++---------- > 1 files changed, 36 insertions(+), 10 deletions(-) Looks fine to me, please commit. Also, please send patches as non-inline attachments for easier review+application. -Chris > > diff --git a/tools/opt/opt.cpp b/tools/opt/opt.cpp > index d837185..ce92ec1 100644 > --- a/tools/opt/opt.cpp > +++ b/tools/opt/opt.cpp > @@ -139,8 +139,13 @@ struct CallGraphSCCPassPrinter : public CallGraphSCCPass { > static char ID; > const PassInfo *PassToPrint; > raw_ostream &Out; > + std::string PassName; > + > CallGraphSCCPassPrinter(const PassInfo *PI, raw_ostream &out) : > - CallGraphSCCPass(ID), PassToPrint(PI), Out(out) {} > + CallGraphSCCPass(ID), PassToPrint(PI), Out(out) { > + std::string PassToPrintName = PassToPrint->getPassName(); > + PassName = "CallGraphSCCPass Printer: " + PassToPrintName; > + } > > virtual bool runOnSCC(CallGraphSCC &SCC) { > if (!Quiet) { > @@ -157,7 +162,7 @@ struct CallGraphSCCPassPrinter : public CallGraphSCCPass { > return false; > } > > - virtual const char *getPassName() const { return "'Pass' Printer"; } > + virtual const char *getPassName() const { return PassName.c_str(); } > > virtual void getAnalysisUsage(AnalysisUsage &AU) const { > AU.addRequiredID(PassToPrint->getTypeInfo()); > @@ -171,8 +176,13 @@ struct ModulePassPrinter : public ModulePass { > static char ID; > const PassInfo *PassToPrint; > raw_ostream &Out; > + std::string PassName; > + > ModulePassPrinter(const PassInfo *PI, raw_ostream &out) > - : ModulePass(ID), PassToPrint(PI), Out(out) {} > + : ModulePass(ID), PassToPrint(PI), Out(out) { > + std::string PassToPrintName = PassToPrint->getPassName(); > + PassName = "ModulePass Printer: " + PassToPrintName; > + } > > virtual bool runOnModule(Module &M) { > if (!Quiet) { > @@ -184,7 +194,7 @@ struct ModulePassPrinter : public ModulePass { > return false; > } > > - virtual const char *getPassName() const { return "'Pass' Printer"; } > + virtual const char *getPassName() const { return PassName.c_str(); } > > virtual void getAnalysisUsage(AnalysisUsage &AU) const { > AU.addRequiredID(PassToPrint->getTypeInfo()); > @@ -197,8 +207,13 @@ struct FunctionPassPrinter : public FunctionPass { > const PassInfo *PassToPrint; > raw_ostream &Out; > static char ID; > + std::string PassName; > + > FunctionPassPrinter(const PassInfo *PI, raw_ostream &out) > - : FunctionPass(ID), PassToPrint(PI), Out(out) {} > + : FunctionPass(ID), PassToPrint(PI), Out(out) { > + std::string PassToPrintName = PassToPrint->getPassName(); > + PassName = "FunctionPass Printer: " + PassToPrintName; > + } > > virtual bool runOnFunction(Function &F) { > if (!Quiet) { > @@ -211,7 +226,7 @@ struct FunctionPassPrinter : public FunctionPass { > return false; > } > > - virtual const char *getPassName() const { return "FunctionPass Printer"; } > + virtual const char *getPassName() const { return PassName.c_str(); } > > virtual void getAnalysisUsage(AnalysisUsage &AU) const { > AU.addRequiredID(PassToPrint->getTypeInfo()); > @@ -225,8 +240,14 @@ struct LoopPassPrinter : public LoopPass { > static char ID; > const PassInfo *PassToPrint; > raw_ostream &Out; > + std::string PassName; > + > LoopPassPrinter(const PassInfo *PI, raw_ostream &out) : > - LoopPass(ID), PassToPrint(PI), Out(out) {} > + LoopPass(ID), PassToPrint(PI), Out(out) { > + std::string PassToPrintName = PassToPrint->getPassName(); > + PassName = "LoopPass Printer: " + PassToPrintName; > + } > + > > virtual bool runOnLoop(Loop *L, LPPassManager &LPM) { > if (!Quiet) { > @@ -238,7 +259,7 @@ struct LoopPassPrinter : public LoopPass { > return false; > } > > - virtual const char *getPassName() const { return "'Pass' Printer"; } > + virtual const char *getPassName() const { return PassName.c_str(); } > > virtual void getAnalysisUsage(AnalysisUsage &AU) const { > AU.addRequiredID(PassToPrint->getTypeInfo()); > @@ -252,8 +273,13 @@ struct BasicBlockPassPrinter : public BasicBlockPass { > const PassInfo *PassToPrint; > raw_ostream &Out; > static char ID; > + std::string PassName; > + > BasicBlockPassPrinter(const PassInfo *PI, raw_ostream &out) > - : BasicBlockPass(ID), PassToPrint(PI), Out(out) {} > + : BasicBlockPass(ID), PassToPrint(PI), Out(out) { > + std::string PassToPrintName = PassToPrint->getPassName(); > + PassName = "BasicBlockPass Printer: " + PassToPrintName; > + } > > virtual bool runOnBasicBlock(BasicBlock &BB) { > if (!Quiet) { > @@ -267,7 +293,7 @@ struct BasicBlockPassPrinter : public BasicBlockPass { > return false; > } > > - virtual const char *getPassName() const { return "BasicBlockPass Printer"; } > + virtual const char *getPassName() const { return PassName.c_str(); } > > virtual void getAnalysisUsage(AnalysisUsage &AU) const { > AU.addRequiredID(PassToPrint->getTypeInfo()); > -- > 1.7.1 > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From clattner at apple.com Sun Sep 5 17:13:00 2010 From: clattner at apple.com (Chris Lattner) Date: Sun, 5 Sep 2010 15:13:00 -0700 Subject: [llvm-commits] [PATCH 2/3] Execute all Pass Printers even if -quiet is set. In-Reply-To: <1283525635-16182-3-git-send-email-grosser@fim.uni-passau.de> References: <1283525635-16182-1-git-send-email-grosser@fim.uni-passau.de> <1283525635-16182-2-git-send-email-grosser@fim.uni-passau.de> <1283525635-16182-3-git-send-email-grosser@fim.uni-passau.de> Message-ID: <970DD0A0-68DA-461A-957B-BC17686D6087@apple.com> On Sep 3, 2010, at 7:53 AM, Tobias Grosser wrote: > Follow the same logic in the LoopPass, ModulePass and CallGraphSCCPass printers, > as it was already used in the BasicBlockPass and FunctionPass printers. This is > more consistent. > > The other option would have been to completely disable dumping the analysis > information. However, as this information is the only information printed if the > -analysis flag is set, calling opt would not do anything at all. Makes sense, please apply. -Chris From xerxes at zafena.se Sun Sep 5 17:34:48 2010 From: xerxes at zafena.se (Xerxes Ranby) Date: Mon, 06 Sep 2010 00:34:48 +0200 Subject: [llvm-commits] InitializeNativeAsmPrinter implementation In-Reply-To: <8888711F-1CCE-4D57-8B1D-95D9F9DADDA7@apple.com> References: <318832.28864.qm@web55601.mail.re4.yahoo.com> <8888711F-1CCE-4D57-8B1D-95D9F9DADDA7@apple.com> Message-ID: <4C841B08.706@zafena.se> Chris Lattner wrote: > On Jul 22, 2010, at 8:50 AM, Jan Sjodin wrote: > > >> This patch is to prepare for MCJIT. I had to normalized the names for >> the initializers to have "Target" in the name to be able to use the >> LLVM_NATIVE_ARCH in the macros. >> > > Hi Jan, > > This patch applies but doesn't build correctly: > > In file included from EDDisassembler.cpp:37: > /Volumes/Data/Users/sabre/llvm/include/llvm/Target/TargetSelect.h:123:5: error: > use of undeclared identifier 'LLVMInitializeX86AsmPrinter'; did you mean > 'LLVMInitializeX86TargetAsmPrinter'? > LLVM_NATIVE_ASMPRINTER(); > ^~~~~~~~~~~~~~~~~~~~~~ > > > Can you update it for mainline? > > -Chris > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > Jans patch have already got merged into trunk on the on 1st of August. http://llvm.org/viewvc/llvm-project?view=rev&revision=109996 It is quite odd that this old patch did apply a second time since the TargetSelect file have evolved quite much since back then. The InitializeNativeTargetAsmPrinter() are part of the branched LLVM 2.8 API. Nothing to worry about. Cheers, and have a great day! Xerxes From clattner at apple.com Sun Sep 5 17:39:02 2010 From: clattner at apple.com (Chris Lattner) Date: Sun, 5 Sep 2010 15:39:02 -0700 Subject: [llvm-commits] [llvm] r108885 - /llvm/trunk/include/llvm/PassRegistry.h In-Reply-To: <20100720185326.119772A6C12C@llvm.org> References: <20100720185326.119772A6C12C@llvm.org> Message-ID: <4425F656-CC04-4638-9641-9DFF5DE60F89@apple.com> On Jul 20, 2010, at 11:53 AM, Owen Anderson wrote: > Added: > llvm/trunk/include/llvm/PassRegistry.h Thanks for working on this Owen, some comments: > +// > +// This file defines PassRegistry, a class that is used in the initialization > +// and registration of passes. At initialization, passes are registered with "initialization" of what? Please mention app startup time or some other time. > +// the PassRegistry, which is later provided to the PassManager for dependency > +// resolution and similar tasks. > +#include "llvm/PassSupport.h" > +#include "llvm/ADT/StringMap.h" > +#include "llvm/System/DataTypes.h" > +#include "llvm/System/Mutex.h" > +#include > +#include > + > +using namespace llvm; > + > +namespace llvm { > + > +class PassRegistry { > + /// Guards the contents of this class. > + mutable sys::SmartMutex Lock; Why? I don't see why this needs to be locked at all. > + > + /// PassInfoMap - Keep track of the PassInfo object for each registered pass. > + typedef std::map MapType; > + MapType PassInfoMap; Please use a DenseMap for this. > + typedef StringMap StringMapType; > + StringMapType PassInfoStringMap; > + > + /// AnalysisGroupInfo - Keep track of information for each analysis group. > + struct AnalysisGroupInfo { > + std::set Implementations; > + }; Please use a SmallPtrSet > + std::map AnalysisGroupInfoMap; Please use the pimpl idiom to avoid having the this (and AnalysisGroupInfo) exposed in the header, eliminating some #includes. > + > +public: > + static PassRegistry *getPassRegistry(); > + > + const PassInfo *getPassInfo(intptr_t TI) const; > + const PassInfo *getPassInfo(StringRef Arg) const; > + > + void registerPass(const PassInfo &PI); > + void unregisterPass(const PassInfo &PI); > + > + /// Analysis Group Mechanisms. > + void registerAnalysisGroup(PassInfo *InterfaceInfo, > + const PassInfo *ImplementationInfo, > + bool isDefault); > + > + void enumerateWith(PassRegistrationListener *L); > +}; Doxygen comments please! This is a public interface and it's extremely unclear what all this stuff does, please document it. -Chris > + > +} > + > +#endif > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From clattner at apple.com Sun Sep 5 17:40:22 2010 From: clattner at apple.com (Chris Lattner) Date: Sun, 5 Sep 2010 15:40:22 -0700 Subject: [llvm-commits] [llvm] r108888 - in /llvm/trunk: include/llvm/PassRegistry.h lib/VMCore/PassRegistry.cpp In-Reply-To: <20100720192355.489052A6C12C@llvm.org> References: <20100720192355.489052A6C12C@llvm.org> Message-ID: On Jul 20, 2010, at 12:23 PM, Owen Anderson wrote: > URL: http://llvm.org/viewvc/llvm-project?rev=108888&view=rev > Log: > I just fail with SVN today. That may be, but this is a useless commit message. even if you fail or reapply a previous patch, your commit message should be descriptive. > +++ llvm/trunk/lib/VMCore/PassRegistry.cpp Tue Jul 20 14:23:55 2010 > @@ -0,0 +1,72 @@ > +//===- PassRegistry.cpp - Pass Registration Implementation ----------------===// > +// > +// The LLVM Compiler Infrastructure > +// > +// This file is distributed under the University of Illinois Open Source > +// License. See LICENSE.TXT for details. > +// > +//===----------------------------------------------------------------------===// > +// > +// This file implements the PassRegistry, with which passes are registered on > +// initialization, and supports the PassManager in dependency resolution. > +// > +//===----------------------------------------------------------------------===// > + > +#include "llvm/PassRegistry.h" > +#include "llvm/System/Mutex.h" Mutex.h is a redundant #include, but beyond that, none of these should be locked anyway. -Chris From clattner at apple.com Sun Sep 5 17:43:51 2010 From: clattner at apple.com (Chris Lattner) Date: Sun, 5 Sep 2010 15:43:51 -0700 Subject: [llvm-commits] [llvm] r108932 - in /llvm/trunk: include/llvm/PassRegistry.h lib/VMCore/Pass.cpp lib/VMCore/PassRegistry.cpp In-Reply-To: <20100720212224.6252B2A6C12C@llvm.org> References: <20100720212224.6252B2A6C12C@llvm.org> Message-ID: <9F11D537-80DA-4F24-B064-B3051462C7D0@apple.com> On Jul 20, 2010, at 2:22 PM, Owen Anderson wrote: > Author: resistor > Date: Tue Jul 20 16:22:24 2010 > New Revision: 108932 > > URL: http://llvm.org/viewvc/llvm-project?rev=108932&view=rev > Log: > Move more functionality from Pass.cpp to PassRegistry.cpp. This global will go away eventually, but for now we still need it around. > Ok. > +namespace { Please only use namespaces for classes. For globals and functions, just use 'static' like the coding standards say: http://llvm.org/docs/CodingStandards.html#micro_anonns > + > +// FIXME: We use ManagedCleanup to erase the pass registrar on shutdown. > +// Unfortunately, passes are registered with static ctors, and having > +// llvm_shutdown clear this map prevents successful ressurection after > +// llvm_shutdown is run. Ideally we should find a solution so that we don't > +// leak the map, AND can still resurrect after shutdown. > +void cleanupPassRegistry(void*) { > + if (PassRegistryObj) { > + delete PassRegistryObj; > + PassRegistryObj = 0; > + } > +} > +ManagedCleanup<&cleanupPassRegistry> registryCleanup ATTRIBUTE_USED; You shouldn't need the ATTRIBUTE_USED. > + > +} This FIXME still exists on mainline and seems pretty serious, what's your plan for fixing this? -Chris From sabre at nondot.org Sun Sep 5 17:43:56 2010 From: sabre at nondot.org (Chris Lattner) Date: Sun, 05 Sep 2010 22:43:56 -0000 Subject: [llvm-commits] [llvm] r113121 - /llvm/trunk/include/llvm/PassRegistry.h Message-ID: <20100905224356.763CC2A6C12C@llvm.org> Author: lattner Date: Sun Sep 5 17:43:56 2010 New Revision: 113121 URL: http://llvm.org/viewvc/llvm-project?rev=113121&view=rev Log: fix inconsistent formatting. Modified: llvm/trunk/include/llvm/PassRegistry.h Modified: llvm/trunk/include/llvm/PassRegistry.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/PassRegistry.h?rev=113121&r1=113120&r2=113121&view=diff ============================================================================== --- llvm/trunk/include/llvm/PassRegistry.h (original) +++ llvm/trunk/include/llvm/PassRegistry.h Sun Sep 5 17:43:56 2010 @@ -62,7 +62,7 @@ PassInfo& Registeree, bool isDefault); void enumerateWith(PassRegistrationListener *L); - void addRegistrationListener(PassRegistrationListener* L); + void addRegistrationListener(PassRegistrationListener *L); void removeRegistrationListener(PassRegistrationListener *L); }; From resistor at mac.com Sun Sep 5 17:47:43 2010 From: resistor at mac.com (Owen Anderson) Date: Sun, 05 Sep 2010 15:47:43 -0700 Subject: [llvm-commits] [llvm] r108932 - in /llvm/trunk: include/llvm/PassRegistry.h lib/VMCore/Pass.cpp lib/VMCore/PassRegistry.cpp In-Reply-To: <9F11D537-80DA-4F24-B064-B3051462C7D0@apple.com> References: <20100720212224.6252B2A6C12C@llvm.org> <9F11D537-80DA-4F24-B064-B3051462C7D0@apple.com> Message-ID: <85090547-8683-4536-8735-188BFA234216@mac.com> On Sep 5, 2010, at 3:43 PM, Chris Lattner wrote: > This FIXME still exists on mainline and seems pretty serious, what's your plan for fixing this? It's also not new. The same problem existed before, I just tried to explain it a bit better now. That said, since the eventual goal is to get rid of the static initializers as the means of registering classes, the long-term solution will be to have an InitializeLLVMPasses() method (or something similar) that takes a PassRegistry and registers all the core passes with it. Then, if you later destruct that PassRegistry and create a new one, you can just call InitializeLLVMPasses() on it, in turn, and you will have successfully resurrected the registration. --Owen From sabre at nondot.org Sun Sep 5 17:51:11 2010 From: sabre at nondot.org (Chris Lattner) Date: Sun, 05 Sep 2010 22:51:11 -0000 Subject: [llvm-commits] [llvm] r113122 - in /llvm/trunk/lib/Target/ARM: ARMISelDAGToDAG.cpp ARMInstrThumb2.td Message-ID: <20100905225111.2F92C2A6C12C@llvm.org> Author: lattner Date: Sun Sep 5 17:51:11 2010 New Revision: 113122 URL: http://llvm.org/viewvc/llvm-project?rev=113122&view=rev Log: remove some dead code. t2addrmode_imm8s4 is never used in a pattern, so there is no need to define a matching function. Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=113122&r1=113121&r2=113122&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Sun Sep 5 17:51:11 2010 @@ -113,8 +113,6 @@ SDValue &OffImm); bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N, SDValue &OffImm); - bool SelectT2AddrModeImm8s4(SDNode *Op, SDValue N, SDValue &Base, - SDValue &OffImm); bool SelectT2AddrModeSoReg(SDNode *Op, SDValue N, SDValue &Base, SDValue &OffReg, SDValue &ShImm); @@ -797,34 +795,6 @@ return false; } -bool ARMDAGToDAGISel::SelectT2AddrModeImm8s4(SDNode *Op, SDValue N, - SDValue &Base, SDValue &OffImm) { - if (N.getOpcode() == ISD::ADD) { - if (ConstantSDNode *RHS = dyn_cast(N.getOperand(1))) { - int RHSC = (int)RHS->getZExtValue(); - // 8 bits. - if (((RHSC & 0x3) == 0) && - ((RHSC >= 0 && RHSC < 0x400) || (RHSC < 0 && RHSC > -0x400))) { - Base = N.getOperand(0); - OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32); - return true; - } - } - } else if (N.getOpcode() == ISD::SUB) { - if (ConstantSDNode *RHS = dyn_cast(N.getOperand(1))) { - int RHSC = (int)RHS->getZExtValue(); - // 8 bits. - if (((RHSC & 0x3) == 0) && (RHSC >= 0 && RHSC < 0x400)) { - Base = N.getOperand(0); - OffImm = CurDAG->getTargetConstant(-RHSC, MVT::i32); - return true; - } - } - } - - return false; -} - bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDNode *Op, SDValue N, SDValue &Base, SDValue &OffReg, SDValue &ShImm) { Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=113122&r1=113121&r2=113122&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Sun Sep 5 17:51:11 2010 @@ -145,8 +145,7 @@ } // t2addrmode_imm8s4 := reg +/- (imm8 << 2) -def t2addrmode_imm8s4 : Operand, - ComplexPattern { +def t2addrmode_imm8s4 : Operand { let PrintMethod = "printT2AddrModeImm8s4Operand"; let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); } From sabre at nondot.org Sun Sep 5 18:09:31 2010 From: sabre at nondot.org (Chris Lattner) Date: Sun, 05 Sep 2010 23:09:31 -0000 Subject: [llvm-commits] [llvm] r113123 - /llvm/trunk/examples/Fibonacci/fibonacci.cpp Message-ID: <20100905230931.181F92A6C12C@llvm.org> Author: lattner Date: Sun Sep 5 18:09:30 2010 New Revision: 113123 URL: http://llvm.org/viewvc/llvm-project?rev=113123&view=rev Log: fit in 80 columns and don't crash on exit, fixes PR8080 Modified: llvm/trunk/examples/Fibonacci/fibonacci.cpp Modified: llvm/trunk/examples/Fibonacci/fibonacci.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/Fibonacci/fibonacci.cpp?rev=113123&r1=113122&r2=113123&view=diff ============================================================================== --- llvm/trunk/examples/Fibonacci/fibonacci.cpp (original) +++ llvm/trunk/examples/Fibonacci/fibonacci.cpp Sun Sep 5 18:09:30 2010 @@ -96,17 +96,22 @@ LLVMContext Context; // Create some module to put our function into it. - Module *M = new Module("test", Context); + OwningPtr M(new Module("test", Context)); // We are about to create the "fib" function: - Function *FibF = CreateFibFunction(M, Context); + Function *FibF = CreateFibFunction(M.get(), Context); // Now we going to create JIT std::string errStr; - ExecutionEngine *EE = EngineBuilder(M).setErrorStr(&errStr).setEngineKind(EngineKind::JIT).create(); + ExecutionEngine *EE = + EngineBuilder(M.get()) + .setErrorStr(&errStr) + .setEngineKind(EngineKind::JIT) + .create(); if (!EE) { - errs() << argv[0] << ": Failed to construct ExecutionEngine: " << errStr << "\n"; + errs() << argv[0] << ": Failed to construct ExecutionEngine: " << errStr + << "\n"; return 1; } @@ -127,5 +132,6 @@ // import result of execution outs() << "Result: " << GV.IntVal << "\n"; + return 0; } From clattner at apple.com Sun Sep 5 18:15:02 2010 From: clattner at apple.com (Chris Lattner) Date: Sun, 5 Sep 2010 16:15:02 -0700 Subject: [llvm-commits] [llvm] r108932 - in /llvm/trunk: include/llvm/PassRegistry.h lib/VMCore/Pass.cpp lib/VMCore/PassRegistry.cpp In-Reply-To: <85090547-8683-4536-8735-188BFA234216@mac.com> References: <20100720212224.6252B2A6C12C@llvm.org> <9F11D537-80DA-4F24-B064-B3051462C7D0@apple.com> <85090547-8683-4536-8735-188BFA234216@mac.com> Message-ID: On Sep 5, 2010, at 3:47 PM, Owen Anderson wrote: > > On Sep 5, 2010, at 3:43 PM, Chris Lattner wrote: >> This FIXME still exists on mainline and seems pretty serious, what's your plan for fixing this? > > It's also not new. The same problem existed before, I just tried to explain it a bit better now. Ok, please remove the UNUSED at least. > That said, since the eventual goal is to get rid of the static initializers as the means of registering classes, the long-term solution will be to have an InitializeLLVMPasses() method (or something similar) that takes a PassRegistry and registers all the core passes with it. Then, if you later destruct that PassRegistry and create a new one, you can just call InitializeLLVMPasses() on it, in turn, and you will have successfully resurrected the registration. Sounds good, do you plan to do this in the nearish future? -Chris From sabre at nondot.org Sun Sep 5 20:05:37 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 06 Sep 2010 01:05:37 -0000 Subject: [llvm-commits] [llvm] r113133 - in /llvm/trunk: include/llvm/Analysis/LoopInfo.h lib/Analysis/LoopInfo.cpp lib/Transforms/Scalar/LICM.cpp Message-ID: <20100906010538.00F262A6C12C@llvm.org> Author: lattner Date: Sun Sep 5 20:05:37 2010 New Revision: 113133 URL: http://llvm.org/viewvc/llvm-project?rev=113133&view=rev Log: pull a simple method out of LICM into a new Loop::hasLoopInvariantOperands method. Remove a useless and confusing Loop::isLoopInvariant(Instruction) method, which didn't do what you thought it did. No functionality change. Modified: llvm/trunk/include/llvm/Analysis/LoopInfo.h llvm/trunk/lib/Analysis/LoopInfo.cpp llvm/trunk/lib/Transforms/Scalar/LICM.cpp Modified: llvm/trunk/include/llvm/Analysis/LoopInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/LoopInfo.h?rev=113133&r1=113132&r2=113133&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/LoopInfo.h (original) +++ llvm/trunk/include/llvm/Analysis/LoopInfo.h Sun Sep 5 20:05:37 2010 @@ -523,10 +523,9 @@ /// bool isLoopInvariant(Value *V) const; - /// isLoopInvariant - Return true if the specified instruction is - /// loop-invariant. - /// - bool isLoopInvariant(Instruction *I) const; + /// hasLoopInvariantOperands - Return true if all the operands of the + /// specified instruction are loop invariant. + bool hasLoopInvariantOperands(Instruction *I) const; /// makeLoopInvariant - If the given value is an instruction inside of the /// loop and it can be hoisted, do so to make it trivially loop-invariant. Modified: llvm/trunk/lib/Analysis/LoopInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/LoopInfo.cpp?rev=113133&r1=113132&r2=113133&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/LoopInfo.cpp (original) +++ llvm/trunk/lib/Analysis/LoopInfo.cpp Sun Sep 5 20:05:37 2010 @@ -48,15 +48,18 @@ /// bool Loop::isLoopInvariant(Value *V) const { if (Instruction *I = dyn_cast(V)) - return isLoopInvariant(I); + return !contains(I); return true; // All non-instructions are loop invariant } -/// isLoopInvariant - Return true if the specified instruction is -/// loop-invariant. -/// -bool Loop::isLoopInvariant(Instruction *I) const { - return !contains(I); +/// hasLoopInvariantOperands - Return true if all the operands of the +/// specified instruction are loop invariant. +bool Loop::hasLoopInvariantOperands(Instruction *I) const { + for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) + if (!isLoopInvariant(I->getOperand(i))) + return false; + + return true; } /// makeLoopInvariant - If the given value is an instruciton inside of the @@ -105,6 +108,7 @@ for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) if (!makeLoopInvariant(I->getOperand(i), Changed, InsertPt)) return false; + // Hoist. I->moveBefore(InsertPt); Changed = true; Modified: llvm/trunk/lib/Transforms/Scalar/LICM.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LICM.cpp?rev=113133&r1=113132&r2=113133&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LICM.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LICM.cpp Sun Sep 5 20:05:37 2010 @@ -193,7 +193,6 @@ } bool canSinkOrHoistInst(Instruction &I); - bool isLoopInvariantInst(Instruction &I); bool isNotUsedInLoop(Instruction &I); void PromoteAliasSet(AliasSet &AS); @@ -369,7 +368,7 @@ // if all of the operands of the instruction are loop invariant and if it // is safe to hoist the instruction. // - if (isLoopInvariantInst(I) && canSinkOrHoistInst(I) && + if (CurLoop->hasLoopInvariantOperands(&I) && canSinkOrHoistInst(I) && isSafeToExecuteUnconditionally(I)) hoist(I); } @@ -452,20 +451,6 @@ } -/// isLoopInvariantInst - Return true if all operands of this instruction are -/// loop invariant. We also filter out non-hoistable instructions here just for -/// efficiency. -/// -bool LICM::isLoopInvariantInst(Instruction &I) { - // The instruction is loop invariant if all of its operands are loop-invariant - for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) - if (!CurLoop->isLoopInvariant(I.getOperand(i))) - return false; - - // If we got this far, the instruction is loop invariant! - return true; -} - /// sink - When an instruction is found to only be used outside of the loop, /// this function moves it to the exit blocks and patches up SSA form as needed. /// This method is guaranteed to remove the original instruction from its From sabre at nondot.org Sun Sep 5 20:10:22 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 06 Sep 2010 01:10:22 -0000 Subject: [llvm-commits] [llvm] r113134 - in /llvm/trunk: lib/Transforms/Scalar/LoopRotation.cpp test/Transforms/LoopRotate/basic.ll Message-ID: <20100906011022.9D73F2A6C12C@llvm.org> Author: lattner Date: Sun Sep 5 20:10:22 2010 New Revision: 113134 URL: http://llvm.org/viewvc/llvm-project?rev=113134&view=rev Log: Teach loop rotate to hoist trivially invariant instructions in the duplicated block instead of duplicating them. Duplicating them into the end of the loop and the preheader means that we got a phi node in the header of the loop, which prevented LICM from hoisting them. GVN would usually come around later and merge the duplicated instructions so we'd get reasonable output... except that anything dependent on the shoulda-been-hoisted value can't be hoisted. In PR5319 (which this fixes), a memory value didn't get promoted. Added: llvm/trunk/test/Transforms/LoopRotate/basic.ll Modified: llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp?rev=113134&r1=113133&r2=113134&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp Sun Sep 5 20:10:22 2010 @@ -143,11 +143,11 @@ // FIXME: Use common api to estimate size. for (BasicBlock::const_iterator OI = OrigHeader->begin(), OE = OrigHeader->end(); OI != OE; ++OI) { - if (isa(OI)) - continue; // PHI nodes don't count. - if (isa(OI)) - continue; // Debug intrinsics don't count as size. - ++Size; + if (isa(OI)) + continue; // PHI nodes don't count. + if (isa(OI)) + continue; // Debug intrinsics don't count as size. + ++Size; } if (Size > MAX_HEADER_SIZE) @@ -187,13 +187,30 @@ for (; PHINode *PN = dyn_cast(I); ++I) ValueMap[PN] = PN->getIncomingValue(PN->getBasicBlockIndex(OrigPreHeader)); - // For the rest of the instructions, create a clone in the OldPreHeader. + // For the rest of the instructions, either hoist to the OrigPreheader if + // possible or create a clone in the OldPreHeader if not. TerminatorInst *LoopEntryBranch = OrigPreHeader->getTerminator(); - for (; I != E; ++I) { - Instruction *C = I->clone(); - C->setName(I->getName()); + while (I != E) { + Instruction *Inst = I++; + + // If the instruction's operands are invariant and it doesn't read or write + // memory, then it is safe to hoist. Doing this doesn't change the order of + // execution in the preheader, but does prevent the instruction from + // executing in each iteration of the loop. This means it is safe to hoist + // something that might trap, but isn't safe to hoist something that reads + // memory (without proving that the loop doesn't write). + if (L->hasLoopInvariantOperands(Inst) && + !Inst->mayReadFromMemory() && !Inst->mayWriteToMemory() && + !isa(Inst)) { + Inst->moveBefore(LoopEntryBranch); + continue; + } + + // Otherwise, create a duplicate of the instruction. + Instruction *C = Inst->clone(); + C->setName(Inst->getName()); C->insertBefore(LoopEntryBranch); - ValueMap[I] = C; + ValueMap[Inst] = C; } // Along with all the other instructions, we just cloned OrigHeader's Added: llvm/trunk/test/Transforms/LoopRotate/basic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopRotate/basic.ll?rev=113134&view=auto ============================================================================== --- llvm/trunk/test/Transforms/LoopRotate/basic.ll (added) +++ llvm/trunk/test/Transforms/LoopRotate/basic.ll Sun Sep 5 20:10:22 2010 @@ -0,0 +1,35 @@ +; RUN: opt -S -loop-rotate %s | FileCheck %s +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.0.0" + +; PR5319 - The "arrayidx" gep should be hoisted, not duplicated. We should +; end up with one phi node. +define void @test1() nounwind ssp { +; CHECK: @test1 +entry: + %array = alloca [20 x i32], align 16 + br label %for.cond + +for.cond: ; preds = %for.body, %entry + %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %cmp = icmp slt i32 %i.0, 100 + %arrayidx = getelementptr inbounds [20 x i32]* %array, i64 0, i64 0 + br i1 %cmp, label %for.body, label %for.end + +; CHECK: for.body: +; CHECK-NEXT: phi i32 [ 0 +; CHECK-NEXT: store i32 0 + +for.body: ; preds = %for.cond + store i32 0, i32* %arrayidx, align 16 + %inc = add nsw i32 %i.0, 1 + br label %for.cond + +for.end: ; preds = %for.cond + %arrayidx.lcssa = phi i32* [ %arrayidx, %for.cond ] + call void @g(i32* %arrayidx.lcssa) nounwind + ret void +} + +declare void @g(i32*) + From sabre at nondot.org Sun Sep 5 20:26:29 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 06 Sep 2010 01:26:29 -0000 Subject: [llvm-commits] [llvm] r113135 - /llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Message-ID: <20100906012629.AEDF72A6C12C@llvm.org> Author: lattner Date: Sun Sep 5 20:26:29 2010 New Revision: 113135 URL: http://llvm.org/viewvc/llvm-project?rev=113135&view=rev Log: speed up -gvn 3.4% on the testcase in PR7023 Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp?rev=113135&r1=113134&r2=113135&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Sun Sep 5 20:26:29 2010 @@ -176,7 +176,7 @@ if (IntrinsicInst *II = dyn_cast(Inst)) { // Debug intrinsics don't cause dependences. - if (isa(Inst)) continue; + if (isa(II)) continue; // If we pass an invariant-end marker, then we've just entered an // invariant region and can start ignoring dependencies. From sabre at nondot.org Sun Sep 5 20:44:44 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 06 Sep 2010 01:44:44 -0000 Subject: [llvm-commits] [llvm] r113136 - /llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp Message-ID: <20100906014444.7DB752A6C12C@llvm.org> Author: lattner Date: Sun Sep 5 20:44:44 2010 New Revision: 113136 URL: http://llvm.org/viewvc/llvm-project?rev=113136&view=rev Log: slightly improve the runtime and code size of the Intrinsics info table by not comparing the "llvm." prefix in the memcmp, and not storing it in the string literal. Modified: llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp Modified: llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp?rev=113136&r1=113135&r2=113136&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp Sun Sep 5 20:44:44 2010 @@ -99,33 +99,35 @@ // Build a function name -> intrinsic name mapping. std::map IntMapping; for (unsigned i = 0, e = Ints.size(); i != e; ++i) - IntMapping[Ints[i].Name] = i; + IntMapping[Ints[i].Name.substr(5)] = i; OS << "// Function name -> enum value recognizer code.\n"; OS << "#ifdef GET_FUNCTION_RECOGNIZER\n"; - OS << " switch (Name[5]) {\n"; + OS << " Name += 5; Len -= 5; // Skip over 'llvm.'\n"; + OS << " switch (*Name) { // Dispatch on first letter.\n"; OS << " default:\n"; // Emit the intrinsics in sorted order. char LastChar = 0; for (std::map::iterator I = IntMapping.begin(), E = IntMapping.end(); I != E; ++I) { - if (I->first[5] != LastChar) { - LastChar = I->first[5]; + if (I->first[0] != LastChar) { + LastChar = I->first[0]; OS << " break;\n"; OS << " case '" << LastChar << "':\n"; } // For overloaded intrinsics, only the prefix needs to match - if (Ints[I->second].isOverloaded) - OS << " if (Len > " << I->first.size() - << " && !memcmp(Name, \"" << I->first << ".\", " - << (I->first.size() + 1) << ")) return " << TargetPrefix << "Intrinsic::" + std::string TheStr = I->first; + if (Ints[I->second].isOverloaded) { + TheStr += '.'; // Require "bswap." instead of bswap. + OS << " if (Len > " << I->first.size(); + } else { + OS << " if (Len == " << I->first.size(); + } + + OS << " && !memcmp(Name, \"" << TheStr << "\", " + << TheStr.size() << ")) return " << TargetPrefix << "Intrinsic::" << Ints[I->second].EnumName << ";\n"; - else - OS << " if (Len == " << I->first.size() - << " && !memcmp(Name, \"" << I->first << "\", " - << I->first.size() << ")) return " << TargetPrefix << "Intrinsic::" - << Ints[I->second].EnumName << ";\n"; } OS << " }\n"; OS << "#endif\n\n"; From sabre at nondot.org Sun Sep 5 21:01:51 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 06 Sep 2010 02:01:51 -0000 Subject: [llvm-commits] [llvm] r113137 - in /llvm/trunk/utils/TableGen: AsmMatcherEmitter.cpp StringMatcher.cpp StringMatcher.h Message-ID: <20100906020151.828602A6C12C@llvm.org> Author: lattner Date: Sun Sep 5 21:01:51 2010 New Revision: 113137 URL: http://llvm.org/viewvc/llvm-project?rev=113137&view=rev Log: factor the snazzy string matcher code that Daniel hates out of AsmMatcherEmitter.cpp into its own class. Added: llvm/trunk/utils/TableGen/StringMatcher.cpp llvm/trunk/utils/TableGen/StringMatcher.h Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=113137&r1=113136&r2=113137&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Sun Sep 5 21:01:51 2010 @@ -76,6 +76,7 @@ #include "AsmMatcherEmitter.h" #include "CodeGenTarget.h" #include "Record.h" +#include "StringMatcher.h" #include "llvm/ADT/OwningPtr.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/STLExtras.h" @@ -1397,133 +1398,6 @@ OS << "}\n\n"; } -typedef std::pair StringPair; - -/// FindFirstNonCommonLetter - Find the first character in the keys of the -/// string pairs that is not shared across the whole set of strings. All -/// strings are assumed to have the same length. -static unsigned -FindFirstNonCommonLetter(const std::vector &Matches) { - assert(!Matches.empty()); - for (unsigned i = 0, e = Matches[0]->first.size(); i != e; ++i) { - // Check to see if letter i is the same across the set. - char Letter = Matches[0]->first[i]; - - for (unsigned str = 0, e = Matches.size(); str != e; ++str) - if (Matches[str]->first[i] != Letter) - return i; - } - - return Matches[0]->first.size(); -} - -/// EmitStringMatcherForChar - Given a set of strings that are known to be the -/// same length and whose characters leading up to CharNo are the same, emit -/// code to verify that CharNo and later are the same. -/// -/// \return - True if control can leave the emitted code fragment. -static bool EmitStringMatcherForChar(const std::string &StrVariableName, - const std::vector &Matches, - unsigned CharNo, unsigned IndentCount, - raw_ostream &OS) { - assert(!Matches.empty() && "Must have at least one string to match!"); - std::string Indent(IndentCount*2+4, ' '); - - // If we have verified that the entire string matches, we're done: output the - // matching code. - if (CharNo == Matches[0]->first.size()) { - assert(Matches.size() == 1 && "Had duplicate keys to match on"); - - // FIXME: If Matches[0].first has embeded \n, this will be bad. - OS << Indent << Matches[0]->second << "\t // \"" << Matches[0]->first - << "\"\n"; - return false; - } - - // Bucket the matches by the character we are comparing. - std::map > MatchesByLetter; - - for (unsigned i = 0, e = Matches.size(); i != e; ++i) - MatchesByLetter[Matches[i]->first[CharNo]].push_back(Matches[i]); - - - // If we have exactly one bucket to match, see how many characters are common - // across the whole set and match all of them at once. - if (MatchesByLetter.size() == 1) { - unsigned FirstNonCommonLetter = FindFirstNonCommonLetter(Matches); - unsigned NumChars = FirstNonCommonLetter-CharNo; - - // Emit code to break out if the prefix doesn't match. - if (NumChars == 1) { - // Do the comparison with if (Str[1] != 'f') - // FIXME: Need to escape general characters. - OS << Indent << "if (" << StrVariableName << "[" << CharNo << "] != '" - << Matches[0]->first[CharNo] << "')\n"; - OS << Indent << " break;\n"; - } else { - // Do the comparison with if (Str.substr(1,3) != "foo"). - // FIXME: Need to escape general strings. - OS << Indent << "if (" << StrVariableName << ".substr(" << CharNo << "," - << NumChars << ") != \""; - OS << Matches[0]->first.substr(CharNo, NumChars) << "\")\n"; - OS << Indent << " break;\n"; - } - - return EmitStringMatcherForChar(StrVariableName, Matches, - FirstNonCommonLetter, IndentCount, OS); - } - - // Otherwise, we have multiple possible things, emit a switch on the - // character. - OS << Indent << "switch (" << StrVariableName << "[" << CharNo << "]) {\n"; - OS << Indent << "default: break;\n"; - - for (std::map >::iterator LI = - MatchesByLetter.begin(), E = MatchesByLetter.end(); LI != E; ++LI) { - // TODO: escape hard stuff (like \n) if we ever care about it. - OS << Indent << "case '" << LI->first << "':\t // " - << LI->second.size() << " strings to match.\n"; - if (EmitStringMatcherForChar(StrVariableName, LI->second, CharNo+1, - IndentCount+1, OS)) - OS << Indent << " break;\n"; - } - - OS << Indent << "}\n"; - return true; -} - - -/// EmitStringMatcher - Given a list of strings and code to execute when they -/// match, output a simple switch tree to classify the input string. -/// -/// If a match is found, the code in Vals[i].second is executed; control must -/// not exit this code fragment. If nothing matches, execution falls through. -/// -/// \param StrVariableName - The name of the variable to test. -static void EmitStringMatcher(const std::string &StrVariableName, - const std::vector &Matches, - raw_ostream &OS) { - // First level categorization: group strings by length. - std::map > MatchesByLength; - - for (unsigned i = 0, e = Matches.size(); i != e; ++i) - MatchesByLength[Matches[i].first.size()].push_back(&Matches[i]); - - // Output a switch statement on length and categorize the elements within each - // bin. - OS << " switch (" << StrVariableName << ".size()) {\n"; - OS << " default: break;\n"; - - for (std::map >::iterator LI = - MatchesByLength.begin(), E = MatchesByLength.end(); LI != E; ++LI) { - OS << " case " << LI->first << ":\t // " << LI->second.size() - << " strings to match.\n"; - if (EmitStringMatcherForChar(StrVariableName, LI->second, 0, 0, OS)) - OS << " break;\n"; - } - - OS << " }\n"; -} /// EmitMatchTokenString - Emit the function to match a token string to the @@ -1532,18 +1406,19 @@ std::vector &Infos, raw_ostream &OS) { // Construct the match list. - std::vector Matches; + std::vector Matches; for (std::vector::iterator it = Infos.begin(), ie = Infos.end(); it != ie; ++it) { ClassInfo &CI = **it; if (CI.Kind == ClassInfo::Token) - Matches.push_back(StringPair(CI.ValueName, "return " + CI.Name + ";")); + Matches.push_back(StringMatcher::StringPair(CI.ValueName, + "return " + CI.Name + ";")); } OS << "static MatchClassKind MatchTokenString(StringRef Name) {\n"; - EmitStringMatcher("Name", Matches, OS); + StringMatcher("Name", Matches, OS).Emit(); OS << " return InvalidMatchClass;\n"; OS << "}\n\n"; @@ -1554,19 +1429,20 @@ static void EmitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser, raw_ostream &OS) { // Construct the match list. - std::vector Matches; + std::vector Matches; for (unsigned i = 0, e = Target.getRegisters().size(); i != e; ++i) { const CodeGenRegister &Reg = Target.getRegisters()[i]; if (Reg.TheDef->getValueAsString("AsmName").empty()) continue; - Matches.push_back(StringPair(Reg.TheDef->getValueAsString("AsmName"), - "return " + utostr(i + 1) + ";")); + Matches.push_back(StringMatcher::StringPair( + Reg.TheDef->getValueAsString("AsmName"), + "return " + utostr(i + 1) + ";")); } OS << "static unsigned MatchRegisterName(StringRef Name) {\n"; - EmitStringMatcher("Name", Matches, OS); + StringMatcher("Name", Matches, OS).Emit(); OS << " return 0;\n"; OS << "}\n\n"; Added: llvm/trunk/utils/TableGen/StringMatcher.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/StringMatcher.cpp?rev=113137&view=auto ============================================================================== --- llvm/trunk/utils/TableGen/StringMatcher.cpp (added) +++ llvm/trunk/utils/TableGen/StringMatcher.cpp Sun Sep 5 21:01:51 2010 @@ -0,0 +1,134 @@ +//===- StringMatcher.cpp - Generate a matcher for input strings -----------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements the StringMatcher class. +// +//===----------------------------------------------------------------------===// + +#include "StringMatcher.h" +#include "llvm/Support/raw_ostream.h" +#include +using namespace llvm; + +/// FindFirstNonCommonLetter - Find the first character in the keys of the +/// string pairs that is not shared across the whole set of strings. All +/// strings are assumed to have the same length. +static unsigned +FindFirstNonCommonLetter(const std::vector &Matches) { + assert(!Matches.empty()); + for (unsigned i = 0, e = Matches[0]->first.size(); i != e; ++i) { + // Check to see if letter i is the same across the set. + char Letter = Matches[0]->first[i]; + + for (unsigned str = 0, e = Matches.size(); str != e; ++str) + if (Matches[str]->first[i] != Letter) + return i; + } + + return Matches[0]->first.size(); +} + +/// EmitStringMatcherForChar - Given a set of strings that are known to be the +/// same length and whose characters leading up to CharNo are the same, emit +/// code to verify that CharNo and later are the same. +/// +/// \return - True if control can leave the emitted code fragment. +bool StringMatcher:: +EmitStringMatcherForChar(const std::vector &Matches, + unsigned CharNo, unsigned IndentCount) const { + assert(!Matches.empty() && "Must have at least one string to match!"); + std::string Indent(IndentCount*2+4, ' '); + + // If we have verified that the entire string matches, we're done: output the + // matching code. + if (CharNo == Matches[0]->first.size()) { + assert(Matches.size() == 1 && "Had duplicate keys to match on"); + + // FIXME: If Matches[0].first has embeded \n, this will be bad. + OS << Indent << Matches[0]->second << "\t // \"" << Matches[0]->first + << "\"\n"; + return false; + } + + // Bucket the matches by the character we are comparing. + std::map > MatchesByLetter; + + for (unsigned i = 0, e = Matches.size(); i != e; ++i) + MatchesByLetter[Matches[i]->first[CharNo]].push_back(Matches[i]); + + + // If we have exactly one bucket to match, see how many characters are common + // across the whole set and match all of them at once. + if (MatchesByLetter.size() == 1) { + unsigned FirstNonCommonLetter = FindFirstNonCommonLetter(Matches); + unsigned NumChars = FirstNonCommonLetter-CharNo; + + // Emit code to break out if the prefix doesn't match. + if (NumChars == 1) { + // Do the comparison with if (Str[1] != 'f') + // FIXME: Need to escape general characters. + OS << Indent << "if (" << StrVariableName << "[" << CharNo << "] != '" + << Matches[0]->first[CharNo] << "')\n"; + OS << Indent << " break;\n"; + } else { + // Do the comparison with if (Str.substr(1,3) != "foo"). + // FIXME: Need to escape general strings. + OS << Indent << "if (" << StrVariableName << ".substr(" << CharNo << "," + << NumChars << ") != \""; + OS << Matches[0]->first.substr(CharNo, NumChars) << "\")\n"; + OS << Indent << " break;\n"; + } + + return EmitStringMatcherForChar(Matches, FirstNonCommonLetter, IndentCount); + } + + // Otherwise, we have multiple possible things, emit a switch on the + // character. + OS << Indent << "switch (" << StrVariableName << "[" << CharNo << "]) {\n"; + OS << Indent << "default: break;\n"; + + for (std::map >::iterator LI = + MatchesByLetter.begin(), E = MatchesByLetter.end(); LI != E; ++LI) { + // TODO: escape hard stuff (like \n) if we ever care about it. + OS << Indent << "case '" << LI->first << "':\t // " + << LI->second.size() << " strings to match.\n"; + if (EmitStringMatcherForChar(LI->second, CharNo+1, IndentCount+1)) + OS << Indent << " break;\n"; + } + + OS << Indent << "}\n"; + return true; +} + + +/// Emit - Top level entry point. +/// +void StringMatcher::Emit() const { + // First level categorization: group strings by length. + std::map > MatchesByLength; + + for (unsigned i = 0, e = Matches.size(); i != e; ++i) + MatchesByLength[Matches[i].first.size()].push_back(&Matches[i]); + + // Output a switch statement on length and categorize the elements within each + // bin. + OS << " switch (" << StrVariableName << ".size()) {\n"; + OS << " default: break;\n"; + + for (std::map >::iterator LI = + MatchesByLength.begin(), E = MatchesByLength.end(); LI != E; ++LI) { + OS << " case " << LI->first << ":\t // " << LI->second.size() + << " strings to match.\n"; + if (EmitStringMatcherForChar(LI->second, 0, 0)) + OS << " break;\n"; + } + + OS << " }\n"; +} Added: llvm/trunk/utils/TableGen/StringMatcher.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/StringMatcher.h?rev=113137&view=auto ============================================================================== --- llvm/trunk/utils/TableGen/StringMatcher.h (added) +++ llvm/trunk/utils/TableGen/StringMatcher.h Sun Sep 5 21:01:51 2010 @@ -0,0 +1,54 @@ +//===- StringMatcher.h - Generate a matcher for input strings ---*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements the StringMatcher class. +// +//===----------------------------------------------------------------------===// + +#ifndef STRINGMATCHER_H +#define STRINGMATCHER_H + +#include +#include +#include +#include "llvm/ADT/StringRef.h" + +namespace llvm { + class raw_ostream; + +/// StringMatcher - Given a list of strings and code to execute when they match, +/// output a simple switch tree to classify the input string. +/// +/// If a match is found, the code in Vals[i].second is executed; control must +/// not exit this code fragment. If nothing matches, execution falls through. +/// +class StringMatcher { +public: + typedef std::pair StringPair; +private: + StringRef StrVariableName; + const std::vector &Matches; + raw_ostream &OS; + +public: + StringMatcher(StringRef strVariableName, + const std::vector &matches, raw_ostream &os) + : StrVariableName(strVariableName), Matches(matches), OS(os) {} + + void Emit() const; + + +private: + bool EmitStringMatcherForChar(const std::vector &Matches, + unsigned CharNo, unsigned IndentCount) const; +}; + +} // end llvm namespace. + +#endif From pichet2000 at gmail.com Sun Sep 5 21:58:08 2010 From: pichet2000 at gmail.com (Francois Pichet) Date: Sun, 5 Sep 2010 22:58:08 -0400 Subject: [llvm-commits] [llvm] r113137 - in /llvm/trunk/utils/TableGen: AsmMatcherEmitter.cpp StringMatcher.cpp StringMatcher.h In-Reply-To: <20100906020151.828602A6C12C@llvm.org> References: <20100906020151.828602A6C12C@llvm.org> Message-ID: This break the CMake build.. new files not in CMakeLists.txt On Sun, Sep 5, 2010 at 10:01 PM, Chris Lattner wrote: > Author: lattner > Date: Sun Sep ?5 21:01:51 2010 > New Revision: 113137 > > URL: http://llvm.org/viewvc/llvm-project?rev=113137&view=rev > Log: > factor the snazzy string matcher code that Daniel hates > out of AsmMatcherEmitter.cpp into its own class. > > Added: > ? ?llvm/trunk/utils/TableGen/StringMatcher.cpp > ? ?llvm/trunk/utils/TableGen/StringMatcher.h > Modified: > ? ?llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp > From sabre at nondot.org Sun Sep 5 21:58:25 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 06 Sep 2010 02:58:25 -0000 Subject: [llvm-commits] [llvm] r113139 - /llvm/trunk/utils/TableGen/CMakeLists.txt Message-ID: <20100906025825.594CA2A6C12C@llvm.org> Author: lattner Date: Sun Sep 5 21:58:25 2010 New Revision: 113139 URL: http://llvm.org/viewvc/llvm-project?rev=113139&view=rev Log: update cmake Modified: llvm/trunk/utils/TableGen/CMakeLists.txt Modified: llvm/trunk/utils/TableGen/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CMakeLists.txt?rev=113139&r1=113138&r2=113139&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CMakeLists.txt (original) +++ llvm/trunk/utils/TableGen/CMakeLists.txt Sun Sep 5 21:58:25 2010 @@ -27,6 +27,7 @@ OptParserEmitter.cpp Record.cpp RegisterInfoEmitter.cpp + StringMatcher.cpp SubtargetEmitter.cpp TGLexer.cpp TGParser.cpp From sabre at nondot.org Sun Sep 5 21:59:17 2010 From: sabre at nondot.org (Chris Lattner) Date: Sun, 5 Sep 2010 19:59:17 -0700 Subject: [llvm-commits] [llvm] r113137 - in /llvm/trunk/utils/TableGen: AsmMatcherEmitter.cpp StringMatcher.cpp StringMatcher.h In-Reply-To: References: <20100906020151.828602A6C12C@llvm.org> Message-ID: <80A86ACA-6DD0-49C4-88D3-A2C3BDCE5970@nondot.org> fixed thanks. -Chris On Sep 5, 2010, at 7:58 PM, Francois Pichet wrote: > This break the CMake build.. new files not in CMakeLists.txt > > On Sun, Sep 5, 2010 at 10:01 PM, Chris Lattner wrote: >> Author: lattner >> Date: Sun Sep 5 21:01:51 2010 >> New Revision: 113137 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=113137&view=rev >> Log: >> factor the snazzy string matcher code that Daniel hates >> out of AsmMatcherEmitter.cpp into its own class. >> >> Added: >> llvm/trunk/utils/TableGen/StringMatcher.cpp >> llvm/trunk/utils/TableGen/StringMatcher.h >> Modified: >> llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp >> From sabre at nondot.org Sun Sep 5 22:11:10 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 06 Sep 2010 03:11:10 -0000 Subject: [llvm-commits] [llvm] r113140 - /llvm/trunk/utils/TableGen/StringMatcher.cpp Message-ID: <20100906031110.BF0DF2A6C12C@llvm.org> Author: lattner Date: Sun Sep 5 22:11:10 2010 New Revision: 113140 URL: http://llvm.org/viewvc/llvm-project?rev=113140&view=rev Log: fix a critical bug where the generated table would say "1 strings to match" in a comment, which isn't gramatic. Modified: llvm/trunk/utils/TableGen/StringMatcher.cpp Modified: llvm/trunk/utils/TableGen/StringMatcher.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/StringMatcher.cpp?rev=113140&r1=113139&r2=113140&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/StringMatcher.cpp (original) +++ llvm/trunk/utils/TableGen/StringMatcher.cpp Sun Sep 5 22:11:10 2010 @@ -98,7 +98,9 @@ MatchesByLetter.begin(), E = MatchesByLetter.end(); LI != E; ++LI) { // TODO: escape hard stuff (like \n) if we ever care about it. OS << Indent << "case '" << LI->first << "':\t // " - << LI->second.size() << " strings to match.\n"; + << LI->second.size() << " string"; + if (LI->second.size() != 1) OS << 's'; + OS << " to match.\n"; if (EmitStringMatcherForChar(LI->second, CharNo+1, IndentCount+1)) OS << Indent << " break;\n"; } From sabre at nondot.org Sun Sep 5 22:12:27 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 06 Sep 2010 03:12:27 -0000 Subject: [llvm-commits] [llvm] r113141 - /llvm/trunk/utils/TableGen/StringMatcher.cpp Message-ID: <20100906031227.DC0F12A6C12C@llvm.org> Author: lattner Date: Sun Sep 5 22:12:27 2010 New Revision: 113141 URL: http://llvm.org/viewvc/llvm-project?rev=113141&view=rev Log: same bug, another place. Modified: llvm/trunk/utils/TableGen/StringMatcher.cpp Modified: llvm/trunk/utils/TableGen/StringMatcher.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/StringMatcher.cpp?rev=113141&r1=113140&r2=113141&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/StringMatcher.cpp (original) +++ llvm/trunk/utils/TableGen/StringMatcher.cpp Sun Sep 5 22:12:27 2010 @@ -127,7 +127,7 @@ for (std::map >::iterator LI = MatchesByLength.begin(), E = MatchesByLength.end(); LI != E; ++LI) { OS << " case " << LI->first << ":\t // " << LI->second.size() - << " strings to match.\n"; + << " string" << (LI->second.size() == 1 ? "" : "s") << " to match.\n"; if (EmitStringMatcherForChar(LI->second, 0, 0)) OS << " break;\n"; } From sabre at nondot.org Sun Sep 5 22:14:45 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 06 Sep 2010 03:14:45 -0000 Subject: [llvm-commits] [llvm] r113142 - /llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp Message-ID: <20100906031445.62A7C2A6C12C@llvm.org> Author: lattner Date: Sun Sep 5 22:14:45 2010 New Revision: 113142 URL: http://llvm.org/viewvc/llvm-project?rev=113142&view=rev Log: emit the __builtin -> intrinsic map with StringMatcher instead of a copy of a close relative of it. Modified: llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp Modified: llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp?rev=113142&r1=113141&r2=113142&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp Sun Sep 5 22:14:45 2010 @@ -14,6 +14,7 @@ #include "CodeGenTarget.h" #include "IntrinsicEmitter.h" #include "Record.h" +#include "StringMatcher.h" #include "llvm/ADT/StringExtras.h" #include using namespace llvm; @@ -586,112 +587,22 @@ OS << "#endif\n\n"; } -/// EmitBuiltinComparisons - Emit comparisons to determine whether the specified -/// sorted range of builtin names is equal to the current builtin. This breaks -/// it down into a simple tree. -/// -/// At this point, we know that all the builtins in the range have the same name -/// for the first 'CharStart' characters. Only the end of the name needs to be -/// discriminated. -typedef std::map::const_iterator StrMapIterator; -static void EmitBuiltinComparisons(StrMapIterator Start, StrMapIterator End, - unsigned CharStart, unsigned Indent, - std::string TargetPrefix, raw_ostream &OS) { - if (Start == End) return; // empty range. - - // Determine what, if anything, is the same about all these strings. - std::string CommonString = Start->first; - unsigned NumInRange = 0; - for (StrMapIterator I = Start; I != End; ++I, ++NumInRange) { - // Find the first character that doesn't match. - const std::string &ThisStr = I->first; - unsigned NonMatchChar = CharStart; - while (NonMatchChar < CommonString.size() && - NonMatchChar < ThisStr.size() && - CommonString[NonMatchChar] == ThisStr[NonMatchChar]) - ++NonMatchChar; - // Truncate off pieces that don't match. - CommonString.resize(NonMatchChar); - } - - // Just compare the rest of the string. - if (NumInRange == 1) { - if (CharStart != CommonString.size()) { - OS << std::string(Indent*2, ' ') << "if (!memcmp(BuiltinName"; - if (CharStart) OS << "+" << CharStart; - OS << ", \"" << (CommonString.c_str()+CharStart) << "\", "; - OS << CommonString.size() - CharStart << "))\n"; - ++Indent; - } - OS << std::string(Indent*2, ' ') << "IntrinsicID = " << TargetPrefix - << "Intrinsic::"; - OS << Start->second << ";\n"; - return; - } - - // At this point, we potentially have a common prefix for these builtins, emit - // a check for this common prefix. - if (CommonString.size() != CharStart) { - OS << std::string(Indent*2, ' ') << "if (!memcmp(BuiltinName"; - if (CharStart) OS << "+" << CharStart; - OS << ", \"" << (CommonString.c_str()+CharStart) << "\", "; - OS << CommonString.size()-CharStart << ")) {\n"; - - EmitBuiltinComparisons(Start, End, CommonString.size(), Indent+1, - TargetPrefix, OS); - OS << std::string(Indent*2, ' ') << "}\n"; - return; - } - - // Output a switch on the character that differs across the set. - OS << std::string(Indent*2, ' ') << "switch (BuiltinName[" << CharStart - << "]) {"; - if (CharStart) - OS << " // \"" << std::string(Start->first.begin(), - Start->first.begin()+CharStart) << "\""; - OS << "\n"; - - for (StrMapIterator I = Start; I != End; ) { - char ThisChar = I->first[CharStart]; - OS << std::string(Indent*2, ' ') << "case '" << ThisChar << "':\n"; - // Figure out the range that has this common character. - StrMapIterator NextChar = I; - for (++NextChar; NextChar != End && NextChar->first[CharStart] == ThisChar; - ++NextChar) - /*empty*/; - EmitBuiltinComparisons(I, NextChar, CharStart+1, Indent+1, TargetPrefix,OS); - OS << std::string(Indent*2, ' ') << " break;\n"; - I = NextChar; - } - OS << std::string(Indent*2, ' ') << "}\n"; -} - /// EmitTargetBuiltins - All of the builtins in the specified map are for the /// same target, and we already checked it. static void EmitTargetBuiltins(const std::map &BIM, const std::string &TargetPrefix, raw_ostream &OS) { - // Rearrange the builtins by length. - std::vector > BuiltinsByLen; - BuiltinsByLen.reserve(100); - - for (StrMapIterator I = BIM.begin(), E = BIM.end(); I != E; ++I) { - if (I->first.size() >= BuiltinsByLen.size()) - BuiltinsByLen.resize(I->first.size()+1); - BuiltinsByLen[I->first.size()].insert(*I); - } - - // Now that we have all the builtins by their length, emit a switch stmt. - OS << " switch (strlen(BuiltinName)) {\n"; - OS << " default: break;\n"; - for (unsigned i = 0, e = BuiltinsByLen.size(); i != e; ++i) { - if (BuiltinsByLen[i].empty()) continue; - OS << " case " << i << ":\n"; - EmitBuiltinComparisons(BuiltinsByLen[i].begin(), BuiltinsByLen[i].end(), - 0, 3, TargetPrefix, OS); - OS << " break;\n"; + + std::vector Results; + + for (std::map::const_iterator I = BIM.begin(), + E = BIM.end(); I != E; ++I) { + std::string ResultCode = + "return " + TargetPrefix + "Intrinsic::" + I->second + ";"; + Results.push_back(StringMatcher::StringPair(I->first, ResultCode)); } - OS << " }\n"; + + StringMatcher("BuiltinName", Results, OS).Emit(); } @@ -721,24 +632,20 @@ if (TargetOnly) { OS << "static " << TargetPrefix << "Intrinsic::ID " << "getIntrinsicForGCCBuiltin(const char " - << "*TargetPrefix, const char *BuiltinName) {\n"; - OS << " " << TargetPrefix << "Intrinsic::ID IntrinsicID = "; + << "*TargetPrefixStr, const char *BuiltinNameStr) {\n"; } else { OS << "Intrinsic::ID Intrinsic::getIntrinsicForGCCBuiltin(const char " - << "*TargetPrefix, const char *BuiltinName) {\n"; - OS << " Intrinsic::ID IntrinsicID = "; + << "*TargetPrefixStr, const char *BuiltinNameStr) {\n"; } - if (TargetOnly) - OS << "(" << TargetPrefix<< "Intrinsic::ID)"; - - OS << "Intrinsic::not_intrinsic;\n"; + OS << " StringRef BuiltinName(BuiltinNameStr);\n"; + OS << " StringRef TargetPrefix(TargetPrefixStr);\n\n"; // Note: this could emit significantly better code if we cared. for (BIMTy::iterator I = BuiltinMap.begin(), E = BuiltinMap.end();I != E;++I){ OS << " "; if (!I->first.empty()) - OS << "if (!strcmp(TargetPrefix, \"" << I->first << "\")) "; + OS << "if (TargetPrefix == \"" << I->first << "\") "; else OS << "/* Target Independent Builtins */ "; OS << "{\n"; @@ -747,7 +654,10 @@ EmitTargetBuiltins(I->second, TargetPrefix, OS); OS << " }\n"; } - OS << " return IntrinsicID;\n"; + OS << " return "; + if (!TargetPrefix.empty()) + OS << "(" << TargetPrefix << "Intrinsic::ID)"; + OS << "Intrinsic::not_intrinsic;\n"; OS << "}\n"; OS << "#endif\n\n"; } From sabre at nondot.org Sun Sep 5 22:50:59 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 06 Sep 2010 03:50:59 -0000 Subject: [llvm-commits] [llvm] r113143 - in /llvm/trunk/utils/TableGen: StringMatcher.cpp StringMatcher.h Message-ID: <20100906035059.A5E342A6C12C@llvm.org> Author: lattner Date: Sun Sep 5 22:50:59 2010 New Revision: 113143 URL: http://llvm.org/viewvc/llvm-project?rev=113143&view=rev Log: allow specifying an indentation level for the string matcher. Modified: llvm/trunk/utils/TableGen/StringMatcher.cpp llvm/trunk/utils/TableGen/StringMatcher.h Modified: llvm/trunk/utils/TableGen/StringMatcher.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/StringMatcher.cpp?rev=113143&r1=113142&r2=113143&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/StringMatcher.cpp (original) +++ llvm/trunk/utils/TableGen/StringMatcher.cpp Sun Sep 5 22:50:59 2010 @@ -112,7 +112,10 @@ /// Emit - Top level entry point. /// -void StringMatcher::Emit() const { +void StringMatcher::Emit(unsigned Indent) const { + // If nothing to match, just fall through. + if (Matches.empty()) return; + // First level categorization: group strings by length. std::map > MatchesByLength; @@ -121,16 +124,17 @@ // Output a switch statement on length and categorize the elements within each // bin. - OS << " switch (" << StrVariableName << ".size()) {\n"; - OS << " default: break;\n"; + OS.indent(Indent*2+2) << "switch (" << StrVariableName << ".size()) {\n"; + OS.indent(Indent*2+2) << "default: break;\n"; for (std::map >::iterator LI = MatchesByLength.begin(), E = MatchesByLength.end(); LI != E; ++LI) { - OS << " case " << LI->first << ":\t // " << LI->second.size() + OS.indent(Indent*2+2) << "case " << LI->first << ":\t // " + << LI->second.size() << " string" << (LI->second.size() == 1 ? "" : "s") << " to match.\n"; - if (EmitStringMatcherForChar(LI->second, 0, 0)) - OS << " break;\n"; + if (EmitStringMatcherForChar(LI->second, 0, Indent)) + OS.indent(Indent*2+4) << "break;\n"; } - OS << " }\n"; + OS.indent(Indent*2+2) << "}\n"; } Modified: llvm/trunk/utils/TableGen/StringMatcher.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/StringMatcher.h?rev=113143&r1=113142&r2=113143&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/StringMatcher.h (original) +++ llvm/trunk/utils/TableGen/StringMatcher.h Sun Sep 5 22:50:59 2010 @@ -41,7 +41,7 @@ const std::vector &matches, raw_ostream &os) : StrVariableName(strVariableName), Matches(matches), OS(os) {} - void Emit() const; + void Emit(unsigned Indent = 0) const; private: From sabre at nondot.org Sun Sep 5 22:58:04 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 06 Sep 2010 03:58:04 -0000 Subject: [llvm-commits] [llvm] r113144 - /llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Message-ID: <20100906035804.E16442A6C12C@llvm.org> Author: lattner Date: Sun Sep 5 22:58:04 2010 New Revision: 113144 URL: http://llvm.org/viewvc/llvm-project?rev=113144&view=rev Log: cleanup some of the lifetime/invariant marker stuff, add a big fixme. Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp?rev=113144&r1=113143&r2=113144&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Sun Sep 5 22:58:04 2010 @@ -175,7 +175,7 @@ } if (IntrinsicInst *II = dyn_cast(Inst)) { - // Debug intrinsics don't cause dependences. + // Debug intrinsics don't (and can't) cause dependences. if (isa(II)) continue; // If we pass an invariant-end marker, then we've just entered an @@ -185,25 +185,30 @@ // pointer, not on query pointers that are indexed off of them. It'd // be nice to handle that at some point. AliasAnalysis::AliasResult R = AA->alias(II->getArgOperand(2), MemPtr); - if (R == AliasAnalysis::MustAlias) { + if (R == AliasAnalysis::MustAlias) InvariantTag = II->getArgOperand(0); - continue; - } - + + continue; + } + // If we reach a lifetime begin or end marker, then the query ends here // because the value is undefined. - } else if (II->getIntrinsicID() == Intrinsic::lifetime_start) { + if (II->getIntrinsicID() == Intrinsic::lifetime_start) { // FIXME: This only considers queries directly on the invariant-tagged // pointer, not on query pointers that are indexed off of them. It'd // be nice to handle that at some point. AliasAnalysis::AliasResult R = AA->alias(II->getArgOperand(1), MemPtr); if (R == AliasAnalysis::MustAlias) return MemDepResult::getDef(II); + continue; } } // If we're querying on a load and we're in an invariant region, we're done // at this point. Nothing a load depends on can live in an invariant region. + // + // FIXME: this will prevent us from returning load/load must-aliases, so GVN + // won't remove redundant loads. if (isLoad && InvariantTag) continue; // Values depend on loads if the pointers are must aliased. This means that From sabre at nondot.org Sun Sep 5 22:58:45 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 06 Sep 2010 03:58:45 -0000 Subject: [llvm-commits] [llvm] r113145 - in /llvm/trunk/utils/TableGen: IntrinsicEmitter.cpp StringMatcher.cpp Message-ID: <20100906035845.5AC0F2A6C12C@llvm.org> Author: lattner Date: Sun Sep 5 22:58:45 2010