From sabre at nondot.org Mon Sep 6 00:11:24 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 06 Sep 2010 05:11:24 -0000 Subject: [llvm-commits] [llvm] r113146 - in /llvm/trunk: lib/Transforms/Scalar/LICM.cpp test/Transforms/LICM/crash.ll Message-ID: <20100906051125.0C9CD2A6C12C@llvm.org> Author: lattner Date: Mon Sep 6 00:11:24 2010 New Revision: 113146 URL: http://llvm.org/viewvc/llvm-project?rev=113146&view=rev Log: fix PR8067, an over-aggressive assertion in LICM. Modified: llvm/trunk/lib/Transforms/Scalar/LICM.cpp llvm/trunk/test/Transforms/LICM/crash.ll Modified: llvm/trunk/lib/Transforms/Scalar/LICM.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LICM.cpp?rev=113146&r1=113145&r2=113146&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LICM.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LICM.cpp Mon Sep 6 00:11:24 2010 @@ -681,10 +681,10 @@ // it. if (isa(Use)) assert(!cast(Use)->isVolatile() && "AST broken"); - else if (isa(Use)) - assert(!cast(Use)->isVolatile() && - Use->getOperand(0) != ASIV && "AST broken"); - else + else if (isa(Use)) { + assert(!cast(Use)->isVolatile() && "AST broken"); + if (Use->getOperand(0) == ASIV) return; + } else return; // Not a load or store. if (!GuaranteedToExecute) Modified: llvm/trunk/test/Transforms/LICM/crash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LICM/crash.ll?rev=113146&r1=113145&r2=113146&view=diff ============================================================================== --- llvm/trunk/test/Transforms/LICM/crash.ll (original) +++ llvm/trunk/test/Transforms/LICM/crash.ll Mon Sep 6 00:11:24 2010 @@ -25,3 +25,17 @@ for.end10: ; preds = %for.cond.for.end10_crit_edge, %entry ret void } + +; PR8067 + at g_8 = external global i32, align 4 + +define void @test2() noreturn nounwind ssp { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + %tmp7 = load i32* @g_8, align 4 + store i32* @g_8, i32** undef, align 16 + store i32 undef, i32* @g_8, align 4 + br label %for.body +} From sabre at nondot.org Mon Sep 6 00:19:45 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 06 Sep 2010 05:19:45 -0000 Subject: [llvm-commits] [llvm] r113147 - /llvm/trunk/lib/System/Host.cpp Message-ID: <20100906051945.085082A6C12C@llvm.org> Author: lattner Date: Mon Sep 6 00:19:44 2010 New Revision: 113147 URL: http://llvm.org/viewvc/llvm-project?rev=113147&view=rev Log: compute the HasSSE3 bit correctly, patch by Nikolai Saoukh. Modified: llvm/trunk/lib/System/Host.cpp Modified: llvm/trunk/lib/System/Host.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Host.cpp?rev=113147&r1=113146&r2=113147&view=diff ============================================================================== --- llvm/trunk/lib/System/Host.cpp (original) +++ llvm/trunk/lib/System/Host.cpp Mon Sep 6 00:19:44 2010 @@ -92,7 +92,8 @@ return true; } -static void DetectX86FamilyModel(unsigned EAX, unsigned &Family, unsigned &Model) { +static void DetectX86FamilyModel(unsigned EAX, unsigned &Family, + unsigned &Model) { Family = (EAX >> 8) & 0xf; // Bits 8 - 11 Model = (EAX >> 4) & 0xf; // Bits 4 - 7 if (Family == 6 || Family == 0xf) { @@ -112,9 +113,9 @@ unsigned Model = 0; DetectX86FamilyModel(EAX, Family, Model); + bool HasSSE3 = (ECX & 0x1); GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); bool Em64T = (EDX >> 29) & 0x1; - bool HasSSE3 = (ECX & 0x1); union { unsigned u[3]; @@ -277,14 +278,12 @@ default: return "athlon"; } case 15: - if (HasSSE3) { + if (HasSSE3) return "k8-sse3"; - } else { - switch (Model) { - case 1: return "opteron"; - case 5: return "athlon-fx"; // also opteron - default: return "athlon64"; - } + switch (Model) { + case 1: return "opteron"; + case 5: return "athlon-fx"; // also opteron + default: return "athlon64"; } case 16: return "amdfam10"; From clchiou at gmail.com Mon Sep 6 04:28:14 2010 From: clchiou at gmail.com (Che-Liang Chiou) Date: Mon, 6 Sep 2010 17:28:14 +0800 Subject: [llvm-commits] [patch][Target/PTX] Create PTX backend In-Reply-To: <3169B6A7-65A6-4742-AA1F-E28618D1F764@apple.com> References: <3169B6A7-65A6-4742-AA1F-E28618D1F764@apple.com> Message-ID: Hi David, I regenerate against latest revision 113149. Would you review and apply it if possible? Thank you very much. Regards, Che-Liang On Mon, Sep 6, 2010 at 5:22 AM, Chris Lattner wrote: > On Aug 27, 2010, at 12:01 AM, Che-Liang Chiou wrote: > >> SVN revision: r112257 >> >> re-generate patch against svn head. > > This conflicts in the autoconf stuff, but otherwise looks good to me. ?Please regenerate and ask someone to apply for you, thanks! > > -Chris > >> >> On Wed, Aug 11, 2010 at 11:10 AM, Che-Liang Chiou wrote: >>> SVN revision: 110776 >>> >>> This patch is a part of upstream work of a PTX backend using LLVM code >>> generator. >>> >>> Change list summary: >>> - Add an empty backend that is merely compilable >>> - Add PTX entry to autoconf/configure.ac and include/llvm/ADT/Triple.h >>> >>> Outcome: >>> $ ./configure --enable-targets=ptx >>> $ make >>> $ llc -version | grep ptx >>> ? ?ptx ? - PTX >>> >>> Misc: >>> - Diff of auto-generated files are put in a separated patch >>> - The autotool version on my machine is newer than >>> autoconf/AutoGegen.sh requires, so the diff of auto-gen'd files might >>> be differ with that on your machine >>> >>> Cheers, >>> Che-Liang >>> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > -------------- next part -------------- A non-text attachment was scrubbed... Name: r113149-add-ptx-backend.patch Type: text/x-patch Size: 13930 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100906/00c31e0d/attachment.bin From kuwerty at gmail.com Mon Sep 6 04:48:06 2010 From: kuwerty at gmail.com (Krister Wombell) Date: Mon, 6 Sep 2010 17:48:06 +0800 Subject: [llvm-commits] [PATCH] ELF file alignments Message-ID: The ELF spec says: All data structures that the object file format defines follow the > "natural'' size and alignment guidelines for the relevant class. If > necessary, data structures contain explicit padding to ensure 4-byte > alignment for 4-byte objects, to force structure sizes to a multiple of 4, > and so on. Data also have suitable alignment from the beginning of the file. > Thus, for example, a structure containing an Elf32_Addr member will be > aligned on a 4-byte boundary within the file. > 1. ELFObjectWriter doesn't write the following objects with correct file alignment: symtab, relocation sections, section headers. It probably goes unnoticed because most CPUs support unaligned memory accesses and get to the data without a problem plus linkers tend to fix things up too. CPUs without unaligned accesses don't fare as well. 2. gas goes a step further than the rules above and ensures that even in relocatable output that a section's file offset is also a multiple of the section alignment. This behaviour falls out of the patch as well. Krister -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100906/85d01d24/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: elf_alignment.patch Type: text/x-patch Size: 2976 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100906/85d01d24/attachment.bin From geek4civic at gmail.com Mon Sep 6 09:03:32 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Mon, 6 Sep 2010 23:03:32 +0900 Subject: [llvm-commits] [PATCH] GNU ld win32 should not accept version script Message-ID: Good evening. GNU ld win32 accepts RPATH(-Wl,-R), RDYNAMIC(-Wl,-export-dynamic) and HAVE_LINK_VERSION_SCRIPT(-Wl,--version-script) but they are simply ignored. Autoconf detects them above. At first, I made a patch to suppress detecting HAVE_LINK_VERSION_SCRIPT on cygwin and mingw. Confirmed on Cygwin, mingw, mingw-cross-f12 and ppc-f12. It works better with Dan's patch r112976. I will make patches for RPATH and RDYNAMIC soon. Although I can commit configure.ac, I don't have proper version of autotools. Would anyone please like to generate and commit them for me? ...Takumi -------------- next part -------------- diff --git a/autoconf/configure.ac b/autoconf/configure.ac index e8020e4..bd97961 100644 --- a/autoconf/configure.ac +++ b/autoconf/configure.ac @@ -1020,20 +1020,22 @@ AC_PATH_PROGS(GAS, [gas as]) dnl Get the version of the linker in use. AC_LINK_GET_VERSION +dnl Check for libtool and the library that has dlopen function (which must come +dnl before the AC_PROG_LIBTOOL check in order to enable dlopening libraries with +dnl libtool). +AC_LIBTOOL_DLOPEN +AC_LIB_LTDL + dnl Determine whether the linker supports the -R option. AC_LINK_USE_R dnl Determine whether the linker supports the -export-dynamic option. AC_LINK_EXPORT_DYNAMIC -dnl Determine whether the linker supports the --version-script option. -AC_LINK_VERSION_SCRIPT - -dnl Check for libtool and the library that has dlopen function (which must come -dnl before the AC_PROG_LIBTOOL check in order to enable dlopening libraries with -dnl libtool). -AC_LIBTOOL_DLOPEN -AC_LIB_LTDL +if test "$dynamic_linker" != "Win32 ld.exe" ; then + dnl Determine whether the linker supports the --version-script option. + AC_LINK_VERSION_SCRIPT +fi if test "$WITH_LLVMGCCDIR" = "default" ; then LLVMGCC="llvm-gcc${EXEEXT}" From geek4civic at gmail.com Mon Sep 6 09:22:36 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Mon, 6 Sep 2010 23:22:36 +0900 Subject: [llvm-commits] [PATCH] Target/ARM build failure on Cygwin-1.5 Message-ID: Hello, Cygwin-1.5 has uint32_t as "unsigned long", and fails to build by type mismatch. I wonder which would be better to fix, Session::ITState or setSlice(). ...Takumi -------------- next part -------------- diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.h b/lib/Target/ARM/Disassembler/ARMDisassembler.h index 0a74a38..8c94e4f 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.h +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.h @@ -66,7 +66,7 @@ public: private: unsigned ITCounter; // Possible values: 0, 1, 2, 3, 4. - unsigned ITState; // A2.5.2 Consists of IT[7:5] and IT[4:0] initially. + uint32_t ITState; // A2.5.2 Consists of IT[7:5] and IT[4:0] initially. }; /// ThumbDisassembler - Thumb disassembler for all ARM platforms. From benny.kra at googlemail.com Mon Sep 6 11:11:52 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Mon, 06 Sep 2010 16:11:52 -0000 Subject: [llvm-commits] [llvm] r113155 - /llvm/trunk/lib/MC/ELFObjectWriter.cpp Message-ID: <20100906161152.880C22A6C12C@llvm.org> Author: d0k Date: Mon Sep 6 11:11:52 2010 New Revision: 113155 URL: http://llvm.org/viewvc/llvm-project?rev=113155&view=rev Log: MCELF: Align symtab, relocation sections and section headers properly. Patch by Krister Wombell. Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=113155&r1=113154&r2=113155&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Mon Sep 6 11:11:52 2010 @@ -103,9 +103,6 @@ raw_ostream &OS; - // This holds the current offset into the object file. - size_t FileOff; - unsigned Is64Bit : 1; bool HasRelocationAddend; @@ -120,7 +117,7 @@ public: ELFObjectWriterImpl(ELFObjectWriter *_Writer, bool _Is64Bit, bool _HasRelAddend) - : Writer(_Writer), OS(Writer->getStream()), FileOff(0), + : Writer(_Writer), OS(Writer->getStream()), Is64Bit(_Is64Bit), HasRelocationAddend(_HasRelAddend) { } @@ -702,7 +699,7 @@ false, EntrySize); MCSectionData &RelaSD = Asm.getOrCreateSectionData(*RelaSection); - RelaSD.setAlignment(1); + RelaSD.setAlignment(Is64Bit ? 8 : 4); MCDataFragment *F = new MCDataFragment(&RelaSD); @@ -832,21 +829,28 @@ // Add 1 for the null section. unsigned NumSections = Asm.size() + 1; - - uint64_t SectionDataSize = 0; + uint64_t NaturalAlignment = Is64Bit ? 8 : 4; + uint64_t HeaderSize = Is64Bit ? sizeof(ELF::Elf64_Ehdr) : sizeof(ELF::Elf32_Ehdr); + uint64_t FileOff = HeaderSize; for (MCAssembler::const_iterator it = Asm.begin(), ie = Asm.end(); it != ie; ++it) { const MCSectionData &SD = *it; + FileOff = RoundUpToAlignment(FileOff, SD.getAlignment()); + // Get the size of the section in the output file (including padding). uint64_t Size = Layout.getSectionFileSize(&SD); - SectionDataSize += Size; + + FileOff += Size; } + FileOff = RoundUpToAlignment(FileOff, NaturalAlignment); + // Write out the ELF header ... - WriteHeader(SectionDataSize, NumSections); - FileOff = Is64Bit ? sizeof(ELF::Elf64_Ehdr) : sizeof(ELF::Elf32_Ehdr); + WriteHeader(FileOff - HeaderSize, NumSections); + + FileOff = HeaderSize; // ... then all of the sections ... DenseMap SectionOffsetMap; @@ -856,17 +860,25 @@ unsigned Index = 1; for (MCAssembler::const_iterator it = Asm.begin(), ie = Asm.end(); it != ie; ++it) { + const MCSectionData &SD = *it; + + uint64_t Padding = OffsetToAlignment(FileOff, SD.getAlignment()); + WriteZeros(Padding); + FileOff += Padding; + // Remember the offset into the file for this section. SectionOffsetMap[&it->getSection()] = FileOff; - SectionIndexMap[&it->getSection()] = Index++; - const MCSectionData &SD = *it; FileOff += Layout.getSectionFileSize(&SD); Asm.WriteSectionData(it, Layout, Writer); } + uint64_t Padding = OffsetToAlignment(FileOff, NaturalAlignment); + WriteZeros(Padding); + FileOff += Padding; + // ... and then the section header table. // Should we align the section header table? // From benny.kra at googlemail.com Mon Sep 6 11:13:35 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Mon, 6 Sep 2010 18:13:35 +0200 Subject: [llvm-commits] [PATCH] ELF file alignments In-Reply-To: References: Message-ID: <3A165A00-39D8-4E23-ACC9-363AAB4DCCB0@gmail.com> On 06.09.2010, at 11:48, Krister Wombell wrote: > The ELF spec says: > > All data structures that the object file format defines follow the >> "natural'' size and alignment guidelines for the relevant class. If >> necessary, data structures contain explicit padding to ensure 4-byte >> alignment for 4-byte objects, to force structure sizes to a multiple of 4, >> and so on. Data also have suitable alignment from the beginning of the file. >> Thus, for example, a structure containing an Elf32_Addr member will be >> aligned on a 4-byte boundary within the file. >> > > 1. ELFObjectWriter doesn't write the following objects with correct file > alignment: symtab, relocation sections, section headers. It probably goes > unnoticed because most CPUs support unaligned memory accesses and get to the > data without a problem plus linkers tend to fix things up too. CPUs without > unaligned accesses don't fare as well. > > 2. gas goes a step further than the rules above and ensures that even in > relocatable output that a section's file offset is also a multiple of the > section alignment. This behaviour falls out of the patch as well. > > Krister Thanks, the patch looks great. Applied in r113155. From clattner at apple.com Mon Sep 6 12:55:52 2010 From: clattner at apple.com (Chris Lattner) Date: Mon, 6 Sep 2010 10:55:52 -0700 Subject: [llvm-commits] [PATCH] Target/ARM build failure on Cygwin-1.5 In-Reply-To: References: Message-ID: On Sep 6, 2010, at 7:22 AM, NAKAMURA Takumi wrote: > Hello, > > Cygwin-1.5 has uint32_t as "unsigned long", and fails to build by type mismatch. > I wonder which would be better to fix, Session::ITState or setSlice(). It's better to fix the other place. What error were you getting? -Chris From sabre at nondot.org Mon Sep 6 13:32:06 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 06 Sep 2010 18:32:06 -0000 Subject: [llvm-commits] [llvm] r113157 - /llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Message-ID: <20100906183206.79A682A6C12C@llvm.org> Author: lattner Date: Mon Sep 6 13:32:06 2010 New Revision: 113157 URL: http://llvm.org/viewvc/llvm-project?rev=113157&view=rev Log: random cleanups Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=113157&r1=113156&r2=113157&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Mon Sep 6 13:32:06 2010 @@ -623,14 +623,14 @@ if (Is64Bit) { if (Name == "popfl") return Error(NameLoc, "popfl cannot be encoded in 64-bit mode"); - else if (Name == "pushfl") + if (Name == "pushfl") return Error(NameLoc, "pushfl cannot be encoded in 64-bit mode"); - else if (Name == "pusha") + if (Name == "pusha") return Error(NameLoc, "pusha cannot be encoded in 64-bit mode"); } else { if (Name == "popfq") return Error(NameLoc, "popfq cannot be encoded in 32-bit mode"); - else if (Name == "pushfq") + if (Name == "pushfq") return Error(NameLoc, "pushfq cannot be encoded in 32-bit mode"); } @@ -778,6 +778,8 @@ if (ExtraImmOp) Operands.push_back(X86Operand::CreateImm(ExtraImmOp, NameLoc, NameLoc)); + + // This does the actual operand parsing. if (getLexer().isNot(AsmToken::EndOfStatement)) { // Parse '*' modifier. @@ -807,12 +809,13 @@ // FIXME: Hack to handle recognizing s{hr,ar,hl}? $1. if ((Name.startswith("shr") || Name.startswith("sar") || Name.startswith("shl")) && - Operands.size() == 3 && - static_cast(Operands[1])->isImm() && - isa(static_cast(Operands[1])->getImm()) && - cast(static_cast(Operands[1])->getImm())->getValue() == 1) { - delete Operands[1]; - Operands.erase(Operands.begin() + 1); + Operands.size() == 3) { + X86Operand *Op1 = static_cast(Operands[1]); + if (Op1->isImm() && isa(Op1->getImm()) && + cast(Op1->getImm())->getValue() == 1) { + delete Operands[1]; + Operands.erase(Operands.begin() + 1); + } } // FIXME: Hack to handle "f{mul*,add*,sub*,div*} $op, st(0)" the same as From rdivacky at freebsd.org Mon Sep 6 13:43:14 2010 From: rdivacky at freebsd.org (Roman Divacky) Date: Mon, 06 Sep 2010 18:43:14 -0000 Subject: [llvm-commits] [llvm] r113158 - /llvm/trunk/lib/Target/X86/X86InstrInfo.td Message-ID: <20100906184314.5445E2A6C12C@llvm.org> Author: rdivacky Date: Mon Sep 6 13:43:14 2010 New Revision: 113158 URL: http://llvm.org/viewvc/llvm-project?rev=113158&view=rev Log: Redefine LOOP* instructions from I to Ii8PCRel as they take an i8 argument. Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=113158&r1=113157&r2=113158&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon Sep 6 13:43:14 2010 @@ -694,9 +694,9 @@ // Loop instructions -def LOOP : I<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", []>; -def LOOPE : I<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", []>; -def LOOPNE : I<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", []>; +def LOOP : Ii8PCRel<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", []>; +def LOOPE : Ii8PCRel<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", []>; +def LOOPNE : Ii8PCRel<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", []>; //===----------------------------------------------------------------------===// // Call Instructions... From echristo at apple.com Mon Sep 6 13:47:00 2010 From: echristo at apple.com (Eric Christopher) Date: Mon, 06 Sep 2010 18:47:00 -0000 Subject: [llvm-commits] [llvm] r113159 - /llvm/trunk/autoconf/configure.ac Message-ID: <20100906184700.558862A6C12C@llvm.org> Author: echristo Date: Mon Sep 6 13:47:00 2010 New Revision: 113159 URL: http://llvm.org/viewvc/llvm-project?rev=113159&view=rev Log: Update to 2.9 post-2.8 branch. Modified: llvm/trunk/autoconf/configure.ac Modified: llvm/trunk/autoconf/configure.ac URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=113159&r1=113158&r2=113159&view=diff ============================================================================== --- llvm/trunk/autoconf/configure.ac (original) +++ llvm/trunk/autoconf/configure.ac Mon Sep 6 13:47:00 2010 @@ -31,7 +31,7 @@ dnl===-----------------------------------------------------------------------=== dnl Initialize autoconf and define the package name, version number and dnl email address for reporting bugs. -AC_INIT([[llvm]],[[2.8svn]],[llvmbugs at cs.uiuc.edu]) +AC_INIT([[llvm]],[[2.9svn]],[llvmbugs at cs.uiuc.edu]) dnl Provide a copyright substitution and ensure the copyright notice is included dnl in the output of --version option of the generated configure script. From echristo at apple.com Mon Sep 6 13:47:10 2010 From: echristo at apple.com (Eric Christopher) Date: Mon, 06 Sep 2010 18:47:10 -0000 Subject: [llvm-commits] [llvm] r113160 - /llvm/trunk/configure Message-ID: <20100906184710.BED0E2A6C12C@llvm.org> Author: echristo Date: Mon Sep 6 13:47:10 2010 New Revision: 113160 URL: http://llvm.org/viewvc/llvm-project?rev=113160&view=rev Log: Regenerate. Modified: llvm/trunk/configure Modified: llvm/trunk/configure URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=113160&r1=113159&r2=113160&view=diff ============================================================================== --- llvm/trunk/configure (original) +++ llvm/trunk/configure Mon Sep 6 13:47:10 2010 @@ -1,6 +1,6 @@ #! /bin/sh # Guess values for system-dependent variables and create Makefiles. -# Generated by GNU Autoconf 2.60 for llvm 2.8svn. +# Generated by GNU Autoconf 2.60 for llvm 2.9svn. # # Report bugs to . # @@ -561,8 +561,8 @@ # Identity of this package. PACKAGE_NAME='llvm' PACKAGE_TARNAME='-llvm-' -PACKAGE_VERSION='2.8svn' -PACKAGE_STRING='llvm 2.8svn' +PACKAGE_VERSION='2.9svn' +PACKAGE_STRING='llvm 2.9svn' PACKAGE_BUGREPORT='llvmbugs at cs.uiuc.edu' ac_unique_file="lib/VMCore/Module.cpp" @@ -1318,7 +1318,7 @@ # Omit some internal or obsolete options to make the list less imposing. # This message is too long to be a string in the A/UX 3.1 sh. cat <<_ACEOF -\`configure' configures llvm 2.8svn to adapt to many kinds of systems. +\`configure' configures llvm 2.9svn to adapt to many kinds of systems. Usage: $0 [OPTION]... [VAR=VALUE]... @@ -1384,7 +1384,7 @@ if test -n "$ac_init_help"; then case $ac_init_help in - short | recursive ) echo "Configuration of llvm 2.8svn:";; + short | recursive ) echo "Configuration of llvm 2.9svn:";; esac cat <<\_ACEOF @@ -1533,7 +1533,7 @@ test -n "$ac_init_help" && exit $ac_status if $ac_init_version; then cat <<\_ACEOF -llvm configure 2.8svn +llvm configure 2.9svn generated by GNU Autoconf 2.60 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, @@ -1549,7 +1549,7 @@ This file contains any messages produced by compilers while running configure, to aid debugging if configure makes a mistake. -It was created by llvm $as_me 2.8svn, which was +It was created by llvm $as_me 2.9svn, which was generated by GNU Autoconf 2.60. Invocation command line was $ $0 $@ @@ -21045,7 +21045,7 @@ # report actual input values of CONFIG_FILES etc. instead of their # values after options handling. ac_log=" -This file was extended by llvm $as_me 2.8svn, which was +This file was extended by llvm $as_me 2.9svn, which was generated by GNU Autoconf 2.60. Invocation command line was CONFIG_FILES = $CONFIG_FILES @@ -21098,7 +21098,7 @@ _ACEOF cat >>$CONFIG_STATUS <<_ACEOF ac_cs_version="\\ -llvm config.status 2.8svn +llvm config.status 2.9svn configured by $0, generated by GNU Autoconf 2.60, with options \\"`echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`\\" From sabre at nondot.org Mon Sep 6 14:11:01 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 06 Sep 2010 19:11:01 -0000 Subject: [llvm-commits] [llvm] r113163 - in /llvm/trunk: lib/Target/ARM/AsmParser/ARMAsmParser.cpp lib/Target/X86/AsmParser/X86AsmLexer.cpp lib/Target/X86/AsmParser/X86AsmParser.cpp utils/TableGen/AsmMatcherEmitter.cpp Message-ID: <20100906191101.8B6FD2A6C12D@llvm.org> Author: lattner Date: Mon Sep 6 14:11:01 2010 New Revision: 113163 URL: http://llvm.org/viewvc/llvm-project?rev=113163&view=rev Log: have AsmMatcherEmitter.cpp produce the hunk of code that gets included into the middle of the class, and rework how the different sections of the generated file are conditionally included for simplicity. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/lib/Target/X86/AsmParser/X86AsmLexer.cpp llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=113163&r1=113162&r2=113163&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Sep 6 14:11:01 2010 @@ -95,11 +95,8 @@ /// @name Auto-generated Match Functions /// { - unsigned ComputeAvailableFeatures(const ARMSubtarget *Subtarget) const; - - bool MatchInstructionImpl(const SmallVectorImpl - &Operands, - MCInst &Inst); +#define GET_ASSEMBLER_HEADER +#include "ARMGenAsmMatcher.inc" /// } @@ -869,4 +866,6 @@ LLVMInitializeARMAsmLexer(); } +#define GET_REGISTER_MATCHER +#define GET_MATCHER_IMPLEMENTATION #include "ARMGenAsmMatcher.inc" Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmLexer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmLexer.cpp?rev=113163&r1=113162&r2=113163&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmLexer.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmLexer.cpp Mon Sep 6 14:11:01 2010 @@ -65,9 +65,10 @@ } }; -} +} // end anonymous namespace -static unsigned MatchRegisterName(StringRef Name); +#define GET_REGISTER_MATCHER +#include "X86GenAsmMatcher.inc" AsmToken X86AsmLexer::LexTokenATT() { AsmToken lexedToken = lexDefinite(); @@ -162,7 +163,3 @@ RegisterAsmLexer X(TheX86_32Target); RegisterAsmLexer Y(TheX86_64Target); } - -#define REGISTERS_ONLY -#include "X86GenAsmMatcher.inc" -#undef REGISTERS_ONLY Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=113163&r1=113162&r2=113163&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Mon Sep 6 14:11:01 2010 @@ -56,12 +56,10 @@ /// @name Auto-generated Matcher Functions /// { - - unsigned ComputeAvailableFeatures(const X86Subtarget *Subtarget) const; - - bool MatchInstructionImpl( - const SmallVectorImpl &Operands, MCInst &Inst); - + +#define GET_ASSEMBLER_HEADER +#include "X86GenAsmMatcher.inc" + /// } public: @@ -882,9 +880,6 @@ MCInst &Inst) { assert(!Operands.empty() && "Unexpect empty operand list!"); - X86Operand *Op = static_cast(Operands[0]); - assert(Op->isToken() && "Leading operand should always be a mnemonic!"); - // First, try a direct match. if (!MatchInstructionImpl(Operands, Inst)) return false; @@ -894,6 +889,9 @@ // type. However, that requires substantially more matcher support than the // following hack. + X86Operand *Op = static_cast(Operands[0]); + assert(Op->isToken() && "Leading operand should always be a mnemonic!"); + // Change the operand to point to a temporary token. StringRef Base = Op->getToken(); SmallString<16> Tmp; @@ -966,4 +964,6 @@ LLVMInitializeX86AsmLexer(); } +#define GET_REGISTER_MATCHER +#define GET_MATCHER_IMPLEMENTATION #include "X86GenAsmMatcher.inc" Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=113163&r1=113162&r2=113163&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Mon Sep 6 14:11:01 2010 @@ -1541,13 +1541,32 @@ EmitSourceFileHeader("Assembly Matcher Source Fragment", OS); + // Information for the class declaration. + OS << "\n#ifdef GET_ASSEMBLER_HEADER\n"; + OS << "#undef GET_ASSEMBLER_HEADER\n"; + OS << " unsigned ComputeAvailableFeatures(const " << + Target.getName() << "Subtarget *Subtarget) const;\n"; + OS << "bool MatchInstructionImpl(const SmallVectorImpl" + << " &Operands, MCInst &Inst);\n\n"; + OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n"; + + + + + OS << "\n#ifdef GET_REGISTER_MATCHER\n"; + OS << "#undef GET_REGISTER_MATCHER\n\n"; + // Emit the subtarget feature enumeration. EmitSubtargetFeatureFlagEnumeration(Target, Info, OS); // Emit the function to match a register name to number. EmitMatchRegisterName(Target, AsmParser, OS); + + OS << "#endif // GET_REGISTER_MATCHER\n\n"; - OS << "#ifndef REGISTERS_ONLY\n\n"; + + OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n"; + OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n"; // Generate the unified function to convert operands into an MCInst. EmitConvertToMCInst(Target, Info.Instructions, OS); @@ -1658,16 +1677,17 @@ << "; it != ie; ++it) {\n"; // Emit check that the required features are available. - OS << " if ((AvailableFeatures & it->RequiredFeatures) " - << "!= it->RequiredFeatures)\n"; - OS << " continue;\n"; - + OS << " if ((AvailableFeatures & it->RequiredFeatures) " + << "!= it->RequiredFeatures)\n"; + OS << " continue;\n"; + // Emit check that the subclasses match. for (unsigned i = 0; i != MaxNumOperands; ++i) { OS << " if (!IsSubclass(Classes[" << i << "], it->Classes[" << i << "]))\n"; OS << " continue;\n"; } + OS << "\n"; OS << " ConvertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n"; @@ -1683,5 +1703,5 @@ OS << " return true;\n"; OS << "}\n\n"; - OS << "#endif // REGISTERS_ONLY\n"; + OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n"; } From sabre at nondot.org Mon Sep 6 14:14:40 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 06 Sep 2010 19:14:40 -0000 Subject: [llvm-commits] [llvm] r113164 - /llvm/trunk/docs/ReleaseNotes.html Message-ID: <20100906191440.C80BA2A6C12C@llvm.org> Author: lattner Date: Mon Sep 6 14:14:40 2010 New Revision: 113164 URL: http://llvm.org/viewvc/llvm-project?rev=113164&view=rev Log: add note Modified: llvm/trunk/docs/ReleaseNotes.html Modified: llvm/trunk/docs/ReleaseNotes.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=113164&r1=113163&r2=113164&view=diff ============================================================================== --- llvm/trunk/docs/ReleaseNotes.html (original) +++ llvm/trunk/docs/ReleaseNotes.html Mon Sep 6 14:14:40 2010 @@ -299,6 +299,7 @@
  • RegionInfo pass: opt -regions analyze" or "opt -view-regions".
  • ARMGlobalMerge:
  • +
  • llvm-diff
  • From sabre at nondot.org Mon Sep 6 14:22:17 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 06 Sep 2010 19:22:17 -0000 Subject: [llvm-commits] [llvm] r113165 - in /llvm/trunk: lib/Target/ARM/AsmParser/ARMAsmParser.cpp lib/Target/X86/AsmParser/X86AsmParser.cpp utils/TableGen/AsmMatcherEmitter.cpp Message-ID: <20100906192217.E752B2A6C12C@llvm.org> Author: lattner Date: Mon Sep 6 14:22:17 2010 New Revision: 113165 URL: http://llvm.org/viewvc/llvm-project?rev=113165&view=rev Log: change MatchInstructionImpl to return an enum instead of bool. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=113165&r1=113164&r2=113165&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Sep 6 14:22:17 2010 @@ -83,7 +83,7 @@ bool MatchInstruction(SMLoc IDLoc, const SmallVectorImpl &Operands, MCInst &Inst) { - if (!MatchInstructionImpl(Operands, Inst)) + if (MatchInstructionImpl(Operands, Inst) == Match_Success) return false; // FIXME: We should give nicer diagnostics about the exact failure. Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=113165&r1=113164&r2=113165&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Mon Sep 6 14:22:17 2010 @@ -881,7 +881,7 @@ assert(!Operands.empty() && "Unexpect empty operand list!"); // First, try a direct match. - if (!MatchInstructionImpl(Operands, Inst)) + if (MatchInstructionImpl(Operands, Inst) == Match_Success) return false; // FIXME: Ideally, we would only attempt suffix matches for things which are @@ -901,13 +901,13 @@ // Check for the various suffix matches. Tmp[Base.size()] = 'b'; - bool MatchB = MatchInstructionImpl(Operands, Inst); + bool MatchB = MatchInstructionImpl(Operands, Inst) != Match_Success; Tmp[Base.size()] = 'w'; - bool MatchW = MatchInstructionImpl(Operands, Inst); + bool MatchW = MatchInstructionImpl(Operands, Inst) != Match_Success; Tmp[Base.size()] = 'l'; - bool MatchL = MatchInstructionImpl(Operands, Inst); + bool MatchL = MatchInstructionImpl(Operands, Inst) != Match_Success; Tmp[Base.size()] = 'q'; - bool MatchQ = MatchInstructionImpl(Operands, Inst); + bool MatchQ = MatchInstructionImpl(Operands, Inst) != Match_Success; // Restore the old token. Op->setTokenValue(Base); Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=113165&r1=113164&r2=113165&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Mon Sep 6 14:22:17 2010 @@ -1544,9 +1544,14 @@ // Information for the class declaration. OS << "\n#ifdef GET_ASSEMBLER_HEADER\n"; OS << "#undef GET_ASSEMBLER_HEADER\n"; + OS << " // This should be included into the middle of the declaration of \n"; + OS << " // your subclasses implementation of TargetAsmParser.\n"; OS << " unsigned ComputeAvailableFeatures(const " << Target.getName() << "Subtarget *Subtarget) const;\n"; - OS << "bool MatchInstructionImpl(const SmallVectorImpl" + OS << " enum MatchResultTy {\n"; + OS << " Match_Success, Match_Fail\n"; + OS << " };\n"; + OS << " MatchResultTy MatchInstructionImpl(const SmallVectorImpl" << " &Operands, MCInst &Inst);\n\n"; OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n"; @@ -1594,7 +1599,8 @@ it != ie; ++it) MaxNumOperands = std::max(MaxNumOperands, (*it)->Operands.size()); - OS << "bool " << Target.getName() << ClassName << "::\n" + OS << Target.getName() << ClassName << "::MatchResultTy " + << Target.getName() << ClassName << "::\n" << "MatchInstructionImpl(const SmallVectorImpl" << " &Operands,\n"; OS << " MCInst &Inst) {\n"; @@ -1653,7 +1659,7 @@ // Emit code to compute the class list for this operand vector. OS << " // Eliminate obvious mismatches.\n"; OS << " if (Operands.size() > " << MaxNumOperands << ")\n"; - OS << " return true;\n\n"; + OS << " return Match_Fail;\n\n"; OS << " // Compute the class list for this operand vector.\n"; OS << " MatchClassKind Classes[" << MaxNumOperands << "];\n"; @@ -1662,7 +1668,7 @@ OS << " // Check for invalid operands before matching.\n"; OS << " if (Classes[i] == InvalidMatchClass)\n"; - OS << " return true;\n"; + OS << " return Match_Fail;\n"; OS << " }\n\n"; OS << " // Mark unused classes.\n"; @@ -1697,10 +1703,10 @@ if (!InsnCleanupFn.empty()) OS << " " << InsnCleanupFn << "(Inst);\n"; - OS << " return false;\n"; + OS << " return Match_Success;\n"; OS << " }\n\n"; - OS << " return true;\n"; + OS << " return Match_Fail;\n"; OS << "}\n\n"; OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n"; From sabre at nondot.org Mon Sep 6 15:08:02 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 06 Sep 2010 20:08:02 -0000 Subject: [llvm-commits] [llvm] r113166 - in /llvm/trunk: lib/Target/X86/AsmParser/X86AsmParser.cpp utils/TableGen/AsmMatcherEmitter.cpp Message-ID: <20100906200802.A4F482A6C12C@llvm.org> Author: lattner Date: Mon Sep 6 15:08:02 2010 New Revision: 113166 URL: http://llvm.org/viewvc/llvm-project?rev=113166&view=rev Log: have tblgen detect when an instruction would have matched, but failed because a subtarget feature was not enabled. Use this to remove a bunch of hacks from the X86AsmParser for rejecting things like popfl in 64-bit mode. Previously these hacks weren't needed, but were important to get a message better than "invalid instruction" when used in the wrong mode. This also fixes bugs where pushal would not be rejected correctly in 32-bit mode (just pusha). Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=113166&r1=113165&r2=113166&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Mon Sep 6 15:08:02 2010 @@ -615,28 +615,13 @@ bool X86ATTAsmParser:: ParseInstruction(StringRef Name, SMLoc NameLoc, SmallVectorImpl &Operands) { - // The various flavors of pushf and popf use Requires and - // Requires, but the assembler doesn't yet implement that. - // For now, just do a manual check to prevent silent misencoding. - if (Is64Bit) { - if (Name == "popfl") - return Error(NameLoc, "popfl cannot be encoded in 64-bit mode"); - if (Name == "pushfl") - return Error(NameLoc, "pushfl cannot be encoded in 64-bit mode"); - if (Name == "pusha") - return Error(NameLoc, "pusha cannot be encoded in 64-bit mode"); - } else { - if (Name == "popfq") - return Error(NameLoc, "popfq cannot be encoded in 32-bit mode"); - if (Name == "pushfq") - return Error(NameLoc, "pushfq cannot be encoded in 32-bit mode"); - } // The "Jump if rCX Zero" form jcxz is not allowed in 64-bit mode and // the form jrcxz is not allowed in 32-bit mode. if (Is64Bit) { - if (Name == "jcxz") - return Error(NameLoc, "jcxz cannot be encoded in 64-bit mode"); + // FIXME: We can do jcxz/jecxz, we just don't have the encoding right yet. + if (Name == "jcxz" || Name == "jecxz") + return Error(NameLoc, Name + " cannot be encoded in 64-bit mode"); } else { if (Name == "jrcxz") return Error(NameLoc, "jrcxz cannot be encoded in 32-bit mode"); @@ -881,8 +866,15 @@ assert(!Operands.empty() && "Unexpect empty operand list!"); // First, try a direct match. - if (MatchInstructionImpl(Operands, Inst) == Match_Success) + switch (MatchInstructionImpl(Operands, Inst)) { + case Match_Success: return false; + case Match_MissingFeature: + Error(IDLoc, "instruction requires a CPU feature not currently enabled"); + return true; + default: + break; + } // FIXME: Ideally, we would only attempt suffix matches for things which are // valid prefixes, and we could just infer the right unambiguous @@ -901,13 +893,13 @@ // Check for the various suffix matches. Tmp[Base.size()] = 'b'; - bool MatchB = MatchInstructionImpl(Operands, Inst) != Match_Success; + MatchResultTy MatchB = MatchInstructionImpl(Operands, Inst); Tmp[Base.size()] = 'w'; - bool MatchW = MatchInstructionImpl(Operands, Inst) != Match_Success; + MatchResultTy MatchW = MatchInstructionImpl(Operands, Inst); Tmp[Base.size()] = 'l'; - bool MatchL = MatchInstructionImpl(Operands, Inst) != Match_Success; + MatchResultTy MatchL = MatchInstructionImpl(Operands, Inst); Tmp[Base.size()] = 'q'; - bool MatchQ = MatchInstructionImpl(Operands, Inst) != Match_Success; + MatchResultTy MatchQ = MatchInstructionImpl(Operands, Inst); // Restore the old token. Op->setTokenValue(Base); @@ -915,23 +907,26 @@ // If exactly one matched, then we treat that as a successful match (and the // instruction will already have been filled in correctly, since the failing // matches won't have modified it). - if (MatchB + MatchW + MatchL + MatchQ == 3) + unsigned NumSuccessfulMatches = + (MatchB == Match_Success) + (MatchW == Match_Success) + + (MatchL == Match_Success) + (MatchQ == Match_Success); + if (NumSuccessfulMatches == 1) return false; - // Otherwise, the match failed. + // Otherwise, the match failed, try to produce a decent error message. // If we had multiple suffix matches, then identify this as an ambiguous // match. - if (MatchB + MatchW + MatchL + MatchQ != 4) { + if (NumSuccessfulMatches > 1) { char MatchChars[4]; unsigned NumMatches = 0; - if (!MatchB) + if (MatchB == Match_Success) MatchChars[NumMatches++] = 'b'; - if (!MatchW) + if (MatchW == Match_Success) MatchChars[NumMatches++] = 'w'; - if (!MatchL) + if (MatchL == Match_Success) MatchChars[NumMatches++] = 'l'; - if (!MatchQ) + if (MatchQ == Match_Success) MatchChars[NumMatches++] = 'q'; SmallString<126> Msg; @@ -946,11 +941,26 @@ } OS << ")"; Error(IDLoc, OS.str()); - } else { - // FIXME: We should give nicer diagnostics about the exact failure. - Error(IDLoc, "unrecognized instruction"); + return true; } - + + unsigned NumMatchFailures = + (MatchB == Match_Fail) + (MatchW == Match_Fail) + + (MatchL == Match_Fail) + (MatchQ == Match_Fail); + + + // If one instruction matched with a missing feature, report this as a + // missing feature. + if ((MatchB == Match_MissingFeature) + (MatchW == Match_MissingFeature) + + (MatchL == Match_MissingFeature) + (MatchQ == Match_MissingFeature) == 1&& + NumMatchFailures == 3) { + Error(IDLoc, "instruction requires a CPU feature not currently enabled"); + return true; + } + + // If all of these were an outright failure, report it in a useless way. + // FIXME: We should give nicer diagnostics about the exact failure. + Error(IDLoc, "unrecognized instruction"); return true; } Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=113166&r1=113165&r2=113166&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Mon Sep 6 15:08:02 2010 @@ -1549,7 +1549,7 @@ OS << " unsigned ComputeAvailableFeatures(const " << Target.getName() << "Subtarget *Subtarget) const;\n"; OS << " enum MatchResultTy {\n"; - OS << " Match_Success, Match_Fail\n"; + OS << " Match_Success, Match_Fail, Match_MissingFeature\n"; OS << " };\n"; OS << " MatchResultTy MatchInstructionImpl(const SmallVectorImpl" << " &Operands, MCInst &Inst);\n\n"; @@ -1678,21 +1678,24 @@ // Emit code to search the table. OS << " // Search the table.\n"; + OS << " bool HadMatchOtherThanFeatures = false;\n"; OS << " for (const MatchEntry *it = MatchTable, " << "*ie = MatchTable + " << Info.Instructions.size() << "; it != ie; ++it) {\n"; - // Emit check that the required features are available. - OS << " if ((AvailableFeatures & it->RequiredFeatures) " - << "!= it->RequiredFeatures)\n"; - OS << " continue;\n"; - // Emit check that the subclasses match. for (unsigned i = 0; i != MaxNumOperands; ++i) { OS << " if (!IsSubclass(Classes[" << i << "], it->Classes[" << i << "]))\n"; OS << " continue;\n"; } + + // Emit check that the required features are available. + OS << " if ((AvailableFeatures & it->RequiredFeatures) " + << "!= it->RequiredFeatures) {\n"; + OS << " HadMatchOtherThanFeatures = true;\n"; + OS << " continue;\n"; + OS << " }\n"; OS << "\n"; OS << " ConvertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n"; @@ -1706,6 +1709,8 @@ OS << " return Match_Success;\n"; OS << " }\n\n"; + OS << " // Okay, we had no match. Try to return a useful error code.\n"; + OS << " if (HadMatchOtherThanFeatures) return Match_MissingFeature;\n"; OS << " return Match_Fail;\n"; OS << "}\n\n"; From sabre at nondot.org Mon Sep 6 15:10:12 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 06 Sep 2010 20:10:12 -0000 Subject: [llvm-commits] [llvm] r113167 - /llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Message-ID: <20100906201012.93D9E2A6C12C@llvm.org> Author: lattner Date: Mon Sep 6 15:10:12 2010 New Revision: 113167 URL: http://llvm.org/viewvc/llvm-project?rev=113167&view=rev Log: simplify the hacks around jrcxz. Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=113167&r1=113166&r2=113167&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Mon Sep 6 15:10:12 2010 @@ -622,9 +622,6 @@ // FIXME: We can do jcxz/jecxz, we just don't have the encoding right yet. if (Name == "jcxz" || Name == "jecxz") return Error(NameLoc, Name + " cannot be encoded in 64-bit mode"); - } else { - if (Name == "jrcxz") - return Error(NameLoc, "jrcxz cannot be encoded in 32-bit mode"); } // FIXME: Hack to recognize "sal..." and "rep..." for now. We need a way to @@ -652,7 +649,7 @@ // jecxz requires an AdSize prefix but jecxz does not have a prefix in // 32-bit mode. .Case("jecxz", "jcxz") - .Case("jrcxz", "jcxz") + .Case("jrcxz", Is64Bit ? "jcxz" : "jrcxz") .Case("jna", "jbe") .Case("jnae", "jb") .Case("jnb", "jae") From sabre at nondot.org Mon Sep 6 15:21:47 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 06 Sep 2010 20:21:47 -0000 Subject: [llvm-commits] [llvm] r113168 - /llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Message-ID: <20100906202147.45CAE2A6C12C@llvm.org> Author: lattner Date: Mon Sep 6 15:21:47 2010 New Revision: 113168 URL: http://llvm.org/viewvc/llvm-project?rev=113168&view=rev Log: The "ambiguous instructions" check only produces anything with -debug, so only do the N^2 loop with debug mode. Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=113168&r1=113167&r2=113168&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Mon Sep 6 15:21:47 2010 @@ -1513,29 +1513,30 @@ }); // Check for ambiguous instructions. - unsigned NumAmbiguous = 0; - for (unsigned i = 0, e = Info.Instructions.size(); i != e; ++i) { - for (unsigned j = i + 1; j != e; ++j) { - InstructionInfo &A = *Info.Instructions[i]; - InstructionInfo &B = *Info.Instructions[j]; - - if (A.CouldMatchAmiguouslyWith(B)) { - DEBUG_WITH_TYPE("ambiguous_instrs", { - errs() << "warning: ambiguous instruction match:\n"; - A.dump(); - errs() << "\nis incomparable with:\n"; - B.dump(); - errs() << "\n\n"; - }); - ++NumAmbiguous; + DEBUG(unsigned NumAmbiguous = 0; + for (unsigned i = 0, e = Info.Instructions.size(); i != e; ++i) { + for (unsigned j = i + 1; j != e; ++j) { + InstructionInfo &A = *Info.Instructions[i]; + InstructionInfo &B = *Info.Instructions[j]; + + if (A.CouldMatchAmiguouslyWith(B)) { + DEBUG_WITH_TYPE("ambiguous_instrs", { + errs() << "warning: ambiguous instruction match:\n"; + A.dump(); + errs() << "\nis incomparable with:\n"; + B.dump(); + errs() << "\n\n"; + }); + ++NumAmbiguous; + } } } - } - if (NumAmbiguous) - DEBUG_WITH_TYPE("ambiguous_instrs", { - errs() << "warning: " << NumAmbiguous - << " ambiguous instructions!\n"; - }); + if (NumAmbiguous) + DEBUG_WITH_TYPE("ambiguous_instrs", { + errs() << "warning: " << NumAmbiguous + << " ambiguous instructions!\n"; + }); + ); // Write the output. From sabre at nondot.org Mon Sep 6 16:01:37 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 06 Sep 2010 21:01:37 -0000 Subject: [llvm-commits] [llvm] r113169 - /llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Message-ID: <20100906210137.AD2F32A6C12C@llvm.org> Author: lattner Date: Mon Sep 6 16:01:37 2010 New Revision: 113169 URL: http://llvm.org/viewvc/llvm-project?rev=113169&view=rev Log: special case the mnemonic operand of the instruction in the generated matcher, emiting it as a column in the MatchEntry table instead of forcing it to go through classification and everything else. Making it be classified caused tblgen to produce a ton of one-off classes for each mneumonic. This should reduce the size of the generated matcher significantly while paving the way for future improvements. Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=113169&r1=113168&r2=113169&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Mon Sep 6 16:01:37 2010 @@ -468,6 +468,10 @@ /// operator< - Compare two instructions. bool operator<(const InstructionInfo &RHS) const { + // The primary comparator is the instruction mnemonic. + if (Tokens[0] != RHS.Tokens[0]) + return Tokens[0] < RHS.Tokens[0]; + if (Operands.size() != RHS.Operands.size()) return Operands.size() < RHS.Operands.size(); @@ -991,8 +995,16 @@ for (std::vector::iterator it = Instructions.begin(), ie = Instructions.end(); it != ie; ++it) { InstructionInfo *II = *it; - - for (unsigned i = 0, e = II->Tokens.size(); i != e; ++i) { + + // The first token of the instruction is the mnemonic, which must be a + // simple string. + assert(!II->Tokens.empty() && "Instruction has no tokens?"); + StringRef Mnemonic = II->Tokens[0]; + assert(Mnemonic[0] != '$' && + (RegisterPrefix.empty() || !Mnemonic.startswith(RegisterPrefix))); + + // Parse the tokens after the mnemonic. + for (unsigned i = 1, e = II->Tokens.size(); i != e; ++i) { StringRef Token = II->Tokens[i]; // Check for singleton registers. @@ -1221,7 +1233,7 @@ CvtOS << " ((" << TargetOperandClass << "*)Operands[" << MIOperandList[i].second - << "])->" << Op.Class->RenderMethod + << "+1])->" << Op.Class->RenderMethod << "(Inst, " << Op.OperandInfo->MINumOperands << ");\n"; CurIndex += Op.OperandInfo->MINumOperands; } @@ -1618,6 +1630,7 @@ // following the mnemonic. OS << " static const struct MatchEntry {\n"; OS << " unsigned Opcode;\n"; + OS << " const char *Mnemonic;\n"; OS << " ConversionKind ConvertFn;\n"; OS << " MatchClassKind Classes[" << MaxNumOperands << "];\n"; OS << " unsigned RequiredFeatures;\n"; @@ -1629,6 +1642,7 @@ InstructionInfo &II = **it; OS << " { " << Target.getName() << "::" << II.InstrName + << ", \"" << II.Tokens[0] << "\"" << ", " << II.ConversionFnKind << ", { "; for (unsigned i = 0, e = II.Operands.size(); i != e; ++i) { InstructionInfo::Operand &Op = II.Operands[i]; @@ -1659,24 +1673,28 @@ // Emit code to compute the class list for this operand vector. OS << " // Eliminate obvious mismatches.\n"; - OS << " if (Operands.size() > " << MaxNumOperands << ")\n"; + OS << " if (Operands.size() > " << MaxNumOperands << "+1)\n"; OS << " return Match_Fail;\n\n"; OS << " // Compute the class list for this operand vector.\n"; OS << " MatchClassKind Classes[" << MaxNumOperands << "];\n"; - OS << " for (unsigned i = 0, e = Operands.size(); i != e; ++i) {\n"; - OS << " Classes[i] = ClassifyOperand(Operands[i]);\n\n"; + OS << " for (unsigned i = 1, e = Operands.size(); i != e; ++i) {\n"; + OS << " Classes[i-1] = ClassifyOperand(Operands[i]);\n\n"; OS << " // Check for invalid operands before matching.\n"; - OS << " if (Classes[i] == InvalidMatchClass)\n"; + OS << " if (Classes[i-1] == InvalidMatchClass)\n"; OS << " return Match_Fail;\n"; OS << " }\n\n"; OS << " // Mark unused classes.\n"; - OS << " for (unsigned i = Operands.size(), e = " << MaxNumOperands << "; " + OS << " for (unsigned i = Operands.size()-1, e = " << MaxNumOperands << "; " << "i != e; ++i)\n"; OS << " Classes[i] = InvalidMatchClass;\n\n"; + OS << " // Get the instruction mneumonic, which is the first token.\n"; + OS << " StringRef Mnemonic = ((" << Target.getName() + << "Operand*)Operands[0])->getToken();\n\n"; + // Emit code to search the table. OS << " // Search the table.\n"; OS << " bool HadMatchOtherThanFeatures = false;\n"; @@ -1684,6 +1702,9 @@ << "*ie = MatchTable + " << Info.Instructions.size() << "; it != ie; ++it) {\n"; + OS << " // Instruction mneumonic must match.\n"; + OS << " if (Mnemonic != it->Mnemonic) continue;"; + // Emit check that the subclasses match. for (unsigned i = 0; i != MaxNumOperands; ++i) { OS << " if (!IsSubclass(Classes[" From sabre at nondot.org Mon Sep 6 16:08:38 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 06 Sep 2010 21:08:38 -0000 Subject: [llvm-commits] [llvm] r113170 - /llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Message-ID: <20100906210839.05AA52A6C12C@llvm.org> Author: lattner Date: Mon Sep 6 16:08:38 2010 New Revision: 113170 URL: http://llvm.org/viewvc/llvm-project?rev=113170&view=rev Log: emit the match table at global scope instead of within the MatchInstructionImpl. This makes it easier to read/understand MatchInstructionImpl. Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=113170&r1=113169&r2=113170&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Mon Sep 6 16:08:38 2010 @@ -1604,20 +1604,14 @@ // Emit the available features compute function. EmitComputeAvailableFeatures(Target, Info, OS); - // Finally, build the match function. size_t MaxNumOperands = 0; for (std::vector::const_iterator it = Info.Instructions.begin(), ie = Info.Instructions.end(); it != ie; ++it) MaxNumOperands = std::max(MaxNumOperands, (*it)->Operands.size()); - - OS << Target.getName() << ClassName << "::MatchResultTy " - << Target.getName() << ClassName << "::\n" - << "MatchInstructionImpl(const SmallVectorImpl" - << " &Operands,\n"; - OS << " MCInst &Inst) {\n"; - + + // Emit the static match table; unused classes get initalized to 0 which is // guaranteed to be InvalidMatchClass. // @@ -1628,22 +1622,27 @@ // order the match kinds appropriately (putting mnemonics last), then we // should only end up using a few bits for each class, especially the ones // following the mnemonic. - OS << " static const struct MatchEntry {\n"; + OS << "namespace {\n"; + OS << " struct MatchEntry {\n"; OS << " unsigned Opcode;\n"; OS << " const char *Mnemonic;\n"; OS << " ConversionKind ConvertFn;\n"; OS << " MatchClassKind Classes[" << MaxNumOperands << "];\n"; OS << " unsigned RequiredFeatures;\n"; - OS << " } MatchTable[" << Info.Instructions.size() << "] = {\n"; - + OS << " };\n"; + OS << "} // end anonymous namespace.\n\n"; + + OS << "static const MatchEntry MatchTable[" + << Info.Instructions.size() << "] = {\n"; + for (std::vector::const_iterator it = - Info.Instructions.begin(), ie = Info.Instructions.end(); + Info.Instructions.begin(), ie = Info.Instructions.end(); it != ie; ++it) { InstructionInfo &II = **it; - - OS << " { " << Target.getName() << "::" << II.InstrName - << ", \"" << II.Tokens[0] << "\"" - << ", " << II.ConversionFnKind << ", { "; + + OS << " { " << Target.getName() << "::" << II.InstrName + << ", \"" << II.Tokens[0] << "\"" + << ", " << II.ConversionFnKind << ", { "; for (unsigned i = 0, e = II.Operands.size(); i != e; ++i) { InstructionInfo::Operand &Op = II.Operands[i]; @@ -1651,7 +1650,7 @@ OS << Op.Class->Name; } OS << " }, "; - + // Write the required features mask. if (!II.RequiredFeatures.empty()) { for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) { @@ -1660,12 +1659,18 @@ } } else OS << "0"; - + OS << "},\n"; } + + OS << "};\n\n"; - OS << " };\n\n"; - + // Finally, build the match function. + OS << Target.getName() << ClassName << "::MatchResultTy " + << Target.getName() << ClassName << "::\n" + << "MatchInstructionImpl(const SmallVectorImpl" + << " &Operands,\n"; + OS << " MCInst &Inst) {\n"; // Emit code to get the available features. OS << " // Get the current feature set.\n"; From sabre at nondot.org Mon Sep 6 16:22:45 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 06 Sep 2010 21:22:45 -0000 Subject: [llvm-commits] [llvm] r113171 - /llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Message-ID: <20100906212245.DE99B2A6C12C@llvm.org> Author: lattner Date: Mon Sep 6 16:22:45 2010 New Revision: 113171 URL: http://llvm.org/viewvc/llvm-project?rev=113171&view=rev Log: now that the opcode is trivially exposed, start matching instructions by doing a binary search over the mnemonic instead of doing a linear search through all possible instructions. This implements rdar://7785064 Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=113171&r1=113170&r2=113171&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Mon Sep 6 16:22:45 2010 @@ -1629,7 +1629,18 @@ OS << " ConversionKind ConvertFn;\n"; OS << " MatchClassKind Classes[" << MaxNumOperands << "];\n"; OS << " unsigned RequiredFeatures;\n"; + OS << " };\n\n"; + + OS << "// Predicate for searching for an opcode.\n"; + OS << " struct LessOpcode {\n"; + OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n"; + OS << " return StringRef(LHS.Mnemonic) < RHS;\n"; + OS << " }\n"; + OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n"; + OS << " return LHS < StringRef(RHS.Mnemonic);\n"; + OS << " }\n"; OS << " };\n"; + OS << "} // end anonymous namespace.\n\n"; OS << "static const MatchEntry MatchTable[" @@ -1699,16 +1710,21 @@ OS << " // Get the instruction mneumonic, which is the first token.\n"; OS << " StringRef Mnemonic = ((" << Target.getName() << "Operand*)Operands[0])->getToken();\n\n"; - + + OS << " bool HadMatchOtherThanFeatures = false;\n\n"; + // Emit code to search the table. OS << " // Search the table.\n"; - OS << " bool HadMatchOtherThanFeatures = false;\n"; - OS << " for (const MatchEntry *it = MatchTable, " - << "*ie = MatchTable + " << Info.Instructions.size() - << "; it != ie; ++it) {\n"; + OS << " std::pair MnemonicRange =\n"; + OS << " std::equal_range(MatchTable, MatchTable+" + << Info.Instructions.size() << ", Mnemonic, LessOpcode());\n\n"; + + OS << " for (const MatchEntry *it = MnemonicRange.first, " + << "*ie = MnemonicRange.second;\n" + OS << " it != ie; ++it) {\n"; OS << " // Instruction mneumonic must match.\n"; - OS << " if (Mnemonic != it->Mnemonic) continue;"; + OS << " if (Mnemonic != it->Mnemonic) continue;\n"; // Emit check that the subclasses match. for (unsigned i = 0; i != MaxNumOperands; ++i) { From sabre at nondot.org Mon Sep 6 16:23:43 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 06 Sep 2010 21:23:43 -0000 Subject: [llvm-commits] [llvm] r113172 - /llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Message-ID: <20100906212343.97EC82A6C12C@llvm.org> Author: lattner Date: Mon Sep 6 16:23:43 2010 New Revision: 113172 URL: http://llvm.org/viewvc/llvm-project?rev=113172&view=rev Log: ; Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=113172&r1=113171&r2=113172&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Mon Sep 6 16:23:43 2010 @@ -1720,7 +1720,7 @@ << Info.Instructions.size() << ", Mnemonic, LessOpcode());\n\n"; OS << " for (const MatchEntry *it = MnemonicRange.first, " - << "*ie = MnemonicRange.second;\n" + << "*ie = MnemonicRange.second;\n"; OS << " it != ie; ++it) {\n"; OS << " // Instruction mneumonic must match.\n"; From sabre at nondot.org Mon Sep 6 16:25:43 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 06 Sep 2010 21:25:43 -0000 Subject: [llvm-commits] [llvm] r113173 - /llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Message-ID: <20100906212543.4F7702A6C12C@llvm.org> Author: lattner Date: Mon Sep 6 16:25:43 2010 New Revision: 113173 URL: http://llvm.org/viewvc/llvm-project?rev=113173&view=rev Log: this if can now be an assert. Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=113173&r1=113172&r2=113173&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Mon Sep 6 16:25:43 2010 @@ -1723,8 +1723,8 @@ << "*ie = MnemonicRange.second;\n"; OS << " it != ie; ++it) {\n"; - OS << " // Instruction mneumonic must match.\n"; - OS << " if (Mnemonic != it->Mnemonic) continue;\n"; + OS << " // equal_range guarantees that instruction mneumonic matches.\n"; + OS << " assert(Mnemonic == it->Mnemonic);\n"; // Emit check that the subclasses match. for (unsigned i = 0; i != MaxNumOperands; ++i) { From sabre at nondot.org Mon Sep 6 16:28:52 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 06 Sep 2010 21:28:52 -0000 Subject: [llvm-commits] [llvm] r113174 - /llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Message-ID: <20100906212852.BFFF02A6C12C@llvm.org> Author: lattner Date: Mon Sep 6 16:28:52 2010 New Revision: 113174 URL: http://llvm.org/viewvc/llvm-project?rev=113174&view=rev Log: simplify DEBUG_WITH_TYPE usage Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=113174&r1=113173&r2=113174&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Mon Sep 6 16:28:52 2010 @@ -1525,30 +1525,27 @@ }); // Check for ambiguous instructions. - DEBUG(unsigned NumAmbiguous = 0; + DEBUG_WITH_TYPE("ambiguous_instrs", { + unsigned NumAmbiguous = 0; for (unsigned i = 0, e = Info.Instructions.size(); i != e; ++i) { for (unsigned j = i + 1; j != e; ++j) { InstructionInfo &A = *Info.Instructions[i]; InstructionInfo &B = *Info.Instructions[j]; if (A.CouldMatchAmiguouslyWith(B)) { - DEBUG_WITH_TYPE("ambiguous_instrs", { - errs() << "warning: ambiguous instruction match:\n"; - A.dump(); - errs() << "\nis incomparable with:\n"; - B.dump(); - errs() << "\n\n"; - }); + errs() << "warning: ambiguous instruction match:\n"; + A.dump(); + errs() << "\nis incomparable with:\n"; + B.dump(); + errs() << "\n\n"; ++NumAmbiguous; } } } if (NumAmbiguous) - DEBUG_WITH_TYPE("ambiguous_instrs", { - errs() << "warning: " << NumAmbiguous - << " ambiguous instructions!\n"; - }); - ); + errs() << "warning: " << NumAmbiguous + << " ambiguous instructions!\n"; + }); // Write the output. From wendling at apple.com Mon Sep 6 16:50:44 2010 From: wendling at apple.com (Bill Wendling) Date: Mon, 6 Sep 2010 14:50:44 -0700 Subject: [llvm-commits] [llvm] r113160 - /llvm/trunk/configure In-Reply-To: <20100906184710.BED0E2A6C12C@llvm.org> References: <20100906184710.BED0E2A6C12C@llvm.org> Message-ID: <21009003-C21C-4C05-992C-9CC50C2683A6@apple.com> Thanks Eric. :) -bw On Sep 6, 2010, at 11:47 AM, Eric Christopher wrote: > Author: echristo > Date: Mon Sep 6 13:47:10 2010 > New Revision: 113160 > > URL: http://llvm.org/viewvc/llvm-project?rev=113160&view=rev > Log: > Regenerate. > > Modified: > llvm/trunk/configure > > Modified: llvm/trunk/configure > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=113160&r1=113159&r2=113160&view=diff > ============================================================================== > --- llvm/trunk/configure (original) > +++ llvm/trunk/configure Mon Sep 6 13:47:10 2010 > @@ -1,6 +1,6 @@ > #! /bin/sh > # Guess values for system-dependent variables and create Makefiles. > -# Generated by GNU Autoconf 2.60 for llvm 2.8svn. > +# Generated by GNU Autoconf 2.60 for llvm 2.9svn. > # From sabre at nondot.org Mon Sep 6 16:54:15 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 06 Sep 2010 21:54:15 -0000 Subject: [llvm-commits] [llvm] r113176 - in /llvm/trunk: lib/Target/X86/AsmParser/X86AsmParser.cpp utils/TableGen/AsmMatcherEmitter.cpp Message-ID: <20100906215415.6F1032A6C12C@llvm.org> Author: lattner Date: Mon Sep 6 16:54:15 2010 New Revision: 113176 URL: http://llvm.org/viewvc/llvm-project?rev=113176&view=rev Log: Now that we know if we had a total fail on the instruction mnemonic, give a more detailed error. Before: t.s:11:4: error: unrecognized instruction addl $1, $1 ^ t.s:12:4: error: unrecognized instruction f2efqefa $1 ^ After: t.s:11:4: error: invalid operand for instruction addl $1, $1 ^ t.s:12:4: error: invalid instruction mnemonic 'f2efqefa' f2efqefa $1 ^ This fixes rdar://8017912 - llvm-mc says "unrecognized instruction" when it means "invalid operands" Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=113176&r1=113175&r2=113176&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Mon Sep 6 16:54:15 2010 @@ -862,6 +862,8 @@ MCInst &Inst) { assert(!Operands.empty() && "Unexpect empty operand list!"); + bool WasOriginallyInvalidOperand = false; + // First, try a direct match. switch (MatchInstructionImpl(Operands, Inst)) { case Match_Success: @@ -869,7 +871,10 @@ case Match_MissingFeature: Error(IDLoc, "instruction requires a CPU feature not currently enabled"); return true; - default: + case Match_InvalidOperand: + WasOriginallyInvalidOperand = true; + break; + case Match_MnemonicFail: break; } @@ -941,23 +946,38 @@ return true; } - unsigned NumMatchFailures = - (MatchB == Match_Fail) + (MatchW == Match_Fail) + - (MatchL == Match_Fail) + (MatchQ == Match_Fail); + // Okay, we know that none of the variants matched successfully. + // If all of the instructions reported an invalid mnemonic, then the original + // mnemonic was invalid. + if ((MatchB == Match_MnemonicFail) && (MatchW == Match_MnemonicFail) && + (MatchL == Match_MnemonicFail) && (MatchQ == Match_MnemonicFail)) { + if (WasOriginallyInvalidOperand) + Error(IDLoc, "invalid operand for instruction"); + else + Error(IDLoc, "invalid instruction mnemonic '" + Base + "'"); + return true; + } // If one instruction matched with a missing feature, report this as a // missing feature. if ((MatchB == Match_MissingFeature) + (MatchW == Match_MissingFeature) + - (MatchL == Match_MissingFeature) + (MatchQ == Match_MissingFeature) == 1&& - NumMatchFailures == 3) { + (MatchL == Match_MissingFeature) + (MatchQ == Match_MissingFeature) == 1){ Error(IDLoc, "instruction requires a CPU feature not currently enabled"); return true; } + // If one instruction matched with an invalid operand, report this as an + // operand failure. + if ((MatchB == Match_InvalidOperand) + (MatchW == Match_InvalidOperand) + + (MatchL == Match_InvalidOperand) + (MatchQ == Match_InvalidOperand) == 1){ + Error(IDLoc, "invalid operand for instruction"); + return true; + } + // If all of these were an outright failure, report it in a useless way. // FIXME: We should give nicer diagnostics about the exact failure. - Error(IDLoc, "unrecognized instruction"); + Error(IDLoc, "unknown use of instruction mnemonic without a size suffix"); return true; } Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=113176&r1=113175&r2=113176&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Mon Sep 6 16:54:15 2010 @@ -1559,7 +1559,8 @@ OS << " unsigned ComputeAvailableFeatures(const " << Target.getName() << "Subtarget *Subtarget) const;\n"; OS << " enum MatchResultTy {\n"; - OS << " Match_Success, Match_Fail, Match_MissingFeature\n"; + OS << " Match_Success, Match_MnemonicFail, Match_InvalidOperand,\n"; + OS << " Match_MissingFeature\n"; OS << " };\n"; OS << " MatchResultTy MatchInstructionImpl(const SmallVectorImpl" << " &Operands, MCInst &Inst);\n\n"; @@ -1687,7 +1688,7 @@ // Emit code to compute the class list for this operand vector. OS << " // Eliminate obvious mismatches.\n"; OS << " if (Operands.size() > " << MaxNumOperands << "+1)\n"; - OS << " return Match_Fail;\n\n"; + OS << " return Match_InvalidOperand;\n\n"; OS << " // Compute the class list for this operand vector.\n"; OS << " MatchClassKind Classes[" << MaxNumOperands << "];\n"; @@ -1696,7 +1697,7 @@ OS << " // Check for invalid operands before matching.\n"; OS << " if (Classes[i-1] == InvalidMatchClass)\n"; - OS << " return Match_Fail;\n"; + OS << " return Match_InvalidOperand;\n"; OS << " }\n\n"; OS << " // Mark unused classes.\n"; @@ -1716,6 +1717,10 @@ OS << " std::equal_range(MatchTable, MatchTable+" << Info.Instructions.size() << ", Mnemonic, LessOpcode());\n\n"; + OS << " // Return a more specific error code if no mnemonics match.\n"; + OS << " if (MnemonicRange.first == MnemonicRange.second)\n"; + OS << " return Match_MnemonicFail;\n\n"; + OS << " for (const MatchEntry *it = MnemonicRange.first, " << "*ie = MnemonicRange.second;\n"; OS << " it != ie; ++it) {\n"; @@ -1751,7 +1756,7 @@ OS << " // Okay, we had no match. Try to return a useful error code.\n"; OS << " if (HadMatchOtherThanFeatures) return Match_MissingFeature;\n"; - OS << " return Match_Fail;\n"; + OS << " return Match_InvalidOperand;\n"; OS << "}\n\n"; OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n"; From sabre at nondot.org Mon Sep 6 17:11:18 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 06 Sep 2010 22:11:18 -0000 Subject: [llvm-commits] [llvm] r113178 - in /llvm/trunk: lib/Target/ARM/AsmParser/ARMAsmParser.cpp lib/Target/X86/AsmParser/X86AsmParser.cpp utils/TableGen/AsmMatcherEmitter.cpp Message-ID: <20100906221118.82BF92A6C12C@llvm.org> Author: lattner Date: Mon Sep 6 17:11:18 2010 New Revision: 113178 URL: http://llvm.org/viewvc/llvm-project?rev=113178&view=rev Log: in the case where an instruction only has one implementation of a mneumonic, report operand errors with better location info. For example, we now report: t.s:6:14: error: invalid operand for instruction cwtl $1 ^ but we fail for common cases like: t.s:11:4: error: invalid operand for instruction addl $1, $1 ^ because we don't know if this is supposed to be the reg/imm or imm/reg form. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=113178&r1=113177&r2=113178&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Sep 6 17:11:18 2010 @@ -83,7 +83,8 @@ bool MatchInstruction(SMLoc IDLoc, const SmallVectorImpl &Operands, MCInst &Inst) { - if (MatchInstructionImpl(Operands, Inst) == Match_Success) + unsigned ErrorInfo; + if (MatchInstructionImpl(Operands, Inst, ErrorInfo) == Match_Success) return false; // FIXME: We should give nicer diagnostics about the exact failure. Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=113178&r1=113177&r2=113178&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Mon Sep 6 17:11:18 2010 @@ -863,9 +863,10 @@ assert(!Operands.empty() && "Unexpect empty operand list!"); bool WasOriginallyInvalidOperand = false; + unsigned OrigErrorInfo; // First, try a direct match. - switch (MatchInstructionImpl(Operands, Inst)) { + switch (MatchInstructionImpl(Operands, Inst, OrigErrorInfo)) { case Match_Success: return false; case Match_MissingFeature: @@ -895,13 +896,14 @@ // Check for the various suffix matches. Tmp[Base.size()] = 'b'; - MatchResultTy MatchB = MatchInstructionImpl(Operands, Inst); + unsigned BErrorInfo, WErrorInfo, LErrorInfo, QErrorInfo; + MatchResultTy MatchB = MatchInstructionImpl(Operands, Inst, BErrorInfo); Tmp[Base.size()] = 'w'; - MatchResultTy MatchW = MatchInstructionImpl(Operands, Inst); + MatchResultTy MatchW = MatchInstructionImpl(Operands, Inst, WErrorInfo); Tmp[Base.size()] = 'l'; - MatchResultTy MatchL = MatchInstructionImpl(Operands, Inst); + MatchResultTy MatchL = MatchInstructionImpl(Operands, Inst, LErrorInfo); Tmp[Base.size()] = 'q'; - MatchResultTy MatchQ = MatchInstructionImpl(Operands, Inst); + MatchResultTy MatchQ = MatchInstructionImpl(Operands, Inst, QErrorInfo); // Restore the old token. Op->setTokenValue(Base); @@ -952,10 +954,19 @@ // mnemonic was invalid. if ((MatchB == Match_MnemonicFail) && (MatchW == Match_MnemonicFail) && (MatchL == Match_MnemonicFail) && (MatchQ == Match_MnemonicFail)) { - if (WasOriginallyInvalidOperand) - Error(IDLoc, "invalid operand for instruction"); - else + if (!WasOriginallyInvalidOperand) { Error(IDLoc, "invalid instruction mnemonic '" + Base + "'"); + return true; + } + + // Recover location info for the operand if we know which was the problem. + SMLoc ErrorLoc = IDLoc; + if (OrigErrorInfo != ~0U) { + ErrorLoc = ((X86Operand*)Operands[OrigErrorInfo])->getStartLoc(); + if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; + } + + Error(ErrorLoc, "invalid operand for instruction"); return true; } Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=113178&r1=113177&r2=113178&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Mon Sep 6 17:11:18 2010 @@ -1563,7 +1563,7 @@ OS << " Match_MissingFeature\n"; OS << " };\n"; OS << " MatchResultTy MatchInstructionImpl(const SmallVectorImpl" - << " &Operands, MCInst &Inst);\n\n"; + << " &Operands, MCInst &Inst, unsigned &ErrorInfo);\n\n"; OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n"; @@ -1679,16 +1679,19 @@ << Target.getName() << ClassName << "::\n" << "MatchInstructionImpl(const SmallVectorImpl" << " &Operands,\n"; - OS << " MCInst &Inst) {\n"; + OS << " MCInst &Inst, unsigned &ErrorInfo) {\n"; // Emit code to get the available features. OS << " // Get the current feature set.\n"; OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n"; + OS << " ErrorInfo = 0;\n"; // Emit code to compute the class list for this operand vector. OS << " // Eliminate obvious mismatches.\n"; - OS << " if (Operands.size() > " << MaxNumOperands << "+1)\n"; - OS << " return Match_InvalidOperand;\n\n"; + OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n"; + OS << " ErrorInfo = " << (MaxNumOperands+1) << ";\n"; + OS << " return Match_InvalidOperand;\n"; + OS << " }\n\n"; OS << " // Compute the class list for this operand vector.\n"; OS << " MatchClassKind Classes[" << MaxNumOperands << "];\n"; @@ -1696,8 +1699,10 @@ OS << " Classes[i-1] = ClassifyOperand(Operands[i]);\n\n"; OS << " // Check for invalid operands before matching.\n"; - OS << " if (Classes[i-1] == InvalidMatchClass)\n"; + OS << " if (Classes[i-1] == InvalidMatchClass) {\n"; + OS << " ErrorInfo = i;\n"; OS << " return Match_InvalidOperand;\n"; + OS << " }\n"; OS << " }\n\n"; OS << " // Mark unused classes.\n"; @@ -1729,11 +1734,22 @@ OS << " assert(Mnemonic == it->Mnemonic);\n"; // Emit check that the subclasses match. - for (unsigned i = 0; i != MaxNumOperands; ++i) { - OS << " if (!IsSubclass(Classes[" - << i << "], it->Classes[" << i << "]))\n"; - OS << " continue;\n"; - } + OS << " bool OperandsValid = true;\n"; + OS << " for (unsigned i = 0; i != " << MaxNumOperands << "; ++i) {\n"; + OS << " if (IsSubclass(Classes[i], it->Classes[i]))\n"; + OS << " continue;\n"; + OS << " // If there is only one instruction with this opcode, report\n"; + OS << " // this as an operand error with location info.\n"; + OS << " if (MnemonicRange.first+1 == ie) {\n"; + OS << " ErrorInfo = i+1;\n"; + OS << " return Match_InvalidOperand;\n"; + OS << " }\n"; + OS << " // Otherwise, just reject this instance of the mnemonic.\n"; + OS << " OperandsValid = false;\n"; + OS << " break;\n"; + OS << " }\n\n"; + + OS << " if (!OperandsValid) continue;\n"; // Emit check that the required features are available. OS << " if ((AvailableFeatures & it->RequiredFeatures) " @@ -1756,6 +1772,7 @@ OS << " // Okay, we had no match. Try to return a useful error code.\n"; OS << " if (HadMatchOtherThanFeatures) return Match_MissingFeature;\n"; + OS << " ErrorInfo = ~0U;\n"; OS << " return Match_InvalidOperand;\n"; OS << "}\n\n"; From sabre at nondot.org Mon Sep 6 18:29:05 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 06 Sep 2010 23:29:05 -0000 Subject: [llvm-commits] [llvm] r113182 - in /llvm/trunk: lib/Target/X86/X86InstrInfo.td test/MC/AsmParser/X86/x86_instructions.s Message-ID: <20100906232905.91B322A6C12C@llvm.org> Author: lattner Date: Mon Sep 6 18:29:05 2010 New Revision: 113182 URL: http://llvm.org/viewvc/llvm-project?rev=113182&view=rev Log: fix the operand constraints of the immediate form of in/out, allowing unsigned 8-bit operands. This fixes rdar://8208481 Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=113182&r1=113181&r2=113182&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon Sep 6 18:29:05 2010 @@ -978,13 +978,13 @@ "in{l}\t{%dx, %eax|%EAX, %DX}", []>; let Defs = [AL] in -def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port), +def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i8imm:$port), "in{b}\t{$port, %al|%AL, $port}", []>; let Defs = [AX] in -def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port), +def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port), "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize; let Defs = [EAX] in -def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port), +def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port), "in{l}\t{$port, %eax|%EAX, $port}", []>; let Uses = [DX, AL] in @@ -998,13 +998,13 @@ "out{l}\t{%eax, %dx|%DX, %EAX}", []>; let Uses = [AL] in -def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port), +def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i8imm:$port), "out{b}\t{%al, $port|$port, %AL}", []>; let Uses = [AX] in -def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port), +def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port), "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize; let Uses = [EAX] in -def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port), +def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port), "out{l}\t{%eax, $port|$port, %EAX}", []>; def IN8 : I<0x6C, RawFrm, (outs), (ins), Modified: llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s?rev=113182&r1=113181&r2=113182&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s Mon Sep 6 18:29:05 2010 @@ -164,3 +164,12 @@ // CHECK: imull %ecx, %eax imull %ecx, %eax + + +// rdar://8208481 +// CHECK: outb %al, $161 +outb %al, $161 +// CHECK: outw %ax, $128 +outw %ax, $128 +// CHECK: inb $161, %al +inb $161, %al From sabre at nondot.org Mon Sep 6 18:37:39 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 06 Sep 2010 23:37:39 -0000 Subject: [llvm-commits] [llvm] r113183 - /llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Message-ID: <20100906233739.BAC532A6C12C@llvm.org> Author: lattner Date: Mon Sep 6 18:37:39 2010 New Revision: 113183 URL: http://llvm.org/viewvc/llvm-project?rev=113183&view=rev Log: generalize my previous operand loc info hack. If the same operand is busted for all variants, report it as the location. This allows us to get the operand right for bugs like: t.s:3:12: error: invalid operand for instruction outb %al, %gs ^ Even though there are reg/imm and reg/reg forms of this instruction. Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=113183&r1=113182&r2=113183&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Mon Sep 6 18:37:39 2010 @@ -1684,7 +1684,6 @@ // Emit code to get the available features. OS << " // Get the current feature set.\n"; OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n"; - OS << " ErrorInfo = 0;\n"; // Emit code to compute the class list for this operand vector. OS << " // Eliminate obvious mismatches.\n"; @@ -1714,7 +1713,11 @@ OS << " StringRef Mnemonic = ((" << Target.getName() << "Operand*)Operands[0])->getToken();\n\n"; + OS << " // Some state to try to produce better error messages.\n"; OS << " bool HadMatchOtherThanFeatures = false;\n\n"; + OS << " // Set ErrorInfo to the operand that mismatches if it is \n"; + OS << " // wrong for all instances of the instruction.\n"; + OS << " ErrorInfo = ~0U;\n"; // Emit code to search the table. OS << " // Search the table.\n"; @@ -1738,12 +1741,12 @@ OS << " for (unsigned i = 0; i != " << MaxNumOperands << "; ++i) {\n"; OS << " if (IsSubclass(Classes[i], it->Classes[i]))\n"; OS << " continue;\n"; - OS << " // If there is only one instruction with this opcode, report\n"; - OS << " // this as an operand error with location info.\n"; - OS << " if (MnemonicRange.first+1 == ie) {\n"; + OS << " // If this operand is broken for all of the instances of this\n"; + OS << " // mnemonic, keep track of it so we can report loc info.\n"; + OS << " if (it == MnemonicRange.first || ErrorInfo == i+1)\n"; OS << " ErrorInfo = i+1;\n"; - OS << " return Match_InvalidOperand;\n"; - OS << " }\n"; + OS << " else\n"; + OS << " ErrorInfo = ~0U;"; OS << " // Otherwise, just reject this instance of the mnemonic.\n"; OS << " OperandsValid = false;\n"; OS << " break;\n"; @@ -1772,7 +1775,6 @@ OS << " // Okay, we had no match. Try to return a useful error code.\n"; OS << " if (HadMatchOtherThanFeatures) return Match_MissingFeature;\n"; - OS << " ErrorInfo = ~0U;\n"; OS << " return Match_InvalidOperand;\n"; OS << "}\n\n"; From sabre at nondot.org Mon Sep 6 18:40:57 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 06 Sep 2010 23:40:57 -0000 Subject: [llvm-commits] [llvm] r113184 - in /llvm/trunk: lib/Target/X86/AsmParser/X86AsmParser.cpp test/MC/AsmParser/X86/x86_instructions.s Message-ID: <20100906234057.19C0C2A6C12C@llvm.org> Author: lattner Date: Mon Sep 6 18:40:56 2010 New Revision: 113184 URL: http://llvm.org/viewvc/llvm-project?rev=113184&view=rev Log: fix rdar://8017621 - llvm-mc can't guess encoding for "push $(1000)" Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=113184&r1=113183&r2=113184&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Mon Sep 6 18:40:56 2010 @@ -636,6 +636,7 @@ .Case("repe", "rep") .Case("repz", "rep") .Case("repnz", "repne") + .Case("push", Is64Bit ? "pushq" : "pushl") .Case("pushf", Is64Bit ? "pushfq" : "pushfl") .Case("popf", Is64Bit ? "popfq" : "popfl") .Case("retl", Is64Bit ? "retl" : "ret") Modified: llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s?rev=113184&r1=113183&r2=113184&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s Mon Sep 6 18:40:56 2010 @@ -173,3 +173,8 @@ outw %ax, $128 // CHECK: inb $161, %al inb $161, %al + +// rdar://8017621 +// CHECK: pushq $1 +push $1 + From sabre at nondot.org Mon Sep 6 18:51:44 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 06 Sep 2010 23:51:44 -0000 Subject: [llvm-commits] [llvm] r113186 - in /llvm/trunk: lib/Target/X86/AsmParser/X86AsmParser.cpp test/MC/AsmParser/X86/x86_instructions.s Message-ID: <20100906235144.DA84B2A6C12C@llvm.org> Author: lattner Date: Mon Sep 6 18:51:44 2010 New Revision: 113186 URL: http://llvm.org/viewvc/llvm-project?rev=113186&view=rev Log: "sldt " is ambiguous in 64-bit mode, but should always be disambiguated as sldtw. sldtw and sldtq with a mem operands have the same effect, but sldtw is more compact. Force it to sldtw, resolving rdar://8017530 Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=113186&r1=113185&r2=113186&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Mon Sep 6 18:51:44 2010 @@ -819,6 +819,13 @@ Operands.push_back(X86Operand::CreateReg(Op->getReg(), Op->getStartLoc(), Op->getEndLoc())); } + + // 'sldt ' can be encoded with either sldtw or sldtq with the same + // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity + // errors, since its encoding is the most compact. + if (Name == "sldt" && Operands.size() == 2 && + static_cast(Operands[1])->isMem()) + Operands[0] = X86Operand::CreateToken("sldtw", NameLoc); return false; } Modified: llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s?rev=113186&r1=113185&r2=113186&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s Mon Sep 6 18:51:44 2010 @@ -178,3 +178,6 @@ // CHECK: pushq $1 push $1 +// rdar://8017530 +// CHECK: sldtw 4 +sldt 4 From nicholas at mxc.ca Mon Sep 6 18:52:49 2010 From: nicholas at mxc.ca (Nick Lewycky) Date: Mon, 06 Sep 2010 23:52:49 -0000 Subject: [llvm-commits] [llvm] r113187 - in /llvm/trunk: include/llvm/Support/ConstantRange.h lib/Support/ConstantRange.cpp unittests/Support/ConstantRangeTest.cpp Message-ID: <20100906235249.B27172A6C12C@llvm.org> Author: nicholas Date: Mon Sep 6 18:52:49 2010 New Revision: 113187 URL: http://llvm.org/viewvc/llvm-project?rev=113187&view=rev Log: Add a new isSignWrappedSet() method to ConstantRange. Fix zeroExtend and signExtend to support empty sets, and to return the smallest possible result set which contains the extension of each element in their inputs. For example zext i8 [100, 10) to i16 is now [0, 256), not i16 [100, 10) which contains 63446 members. Modified: llvm/trunk/include/llvm/Support/ConstantRange.h llvm/trunk/lib/Support/ConstantRange.cpp llvm/trunk/unittests/Support/ConstantRangeTest.cpp Modified: llvm/trunk/include/llvm/Support/ConstantRange.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ConstantRange.h?rev=113187&r1=113186&r2=113187&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/ConstantRange.h (original) +++ llvm/trunk/include/llvm/Support/ConstantRange.h Mon Sep 6 18:52:49 2010 @@ -92,6 +92,11 @@ /// bool isWrappedSet() const; + /// isSignWrappedSet - Return true if this set wraps around the INT_MIN of + /// its bitwidth, for example: i8 [120, 140). + /// + bool isSignWrappedSet() const; + /// contains - Return true if the specified value is in the set. /// bool contains(const APInt &Val) const; Modified: llvm/trunk/lib/Support/ConstantRange.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/ConstantRange.cpp?rev=113187&r1=113186&r2=113187&view=diff ============================================================================== --- llvm/trunk/lib/Support/ConstantRange.cpp (original) +++ llvm/trunk/lib/Support/ConstantRange.cpp Mon Sep 6 18:52:49 2010 @@ -115,6 +115,14 @@ return Lower.ugt(Upper); } +/// isSignWrappedSet - Return true if this set wraps around the INT_MIN of +/// its bitwidth, for example: i8 [120, 140). +/// +bool ConstantRange::isSignWrappedSet() const { + return contains(APInt::getSignedMaxValue(getBitWidth())) && + contains(APInt::getSignedMinValue(getBitWidth())); +} + /// getSetSize - Return the number of elements in this set. /// APInt ConstantRange::getSetSize() const { @@ -408,10 +416,12 @@ /// correspond to the possible range of values as if the source range had been /// zero extended. ConstantRange ConstantRange::zeroExtend(uint32_t DstTySize) const { + if (isEmptySet()) return ConstantRange(DstTySize, /*isFullSet=*/false); + unsigned SrcTySize = getBitWidth(); assert(SrcTySize < DstTySize && "Not a value extension"); - if (isFullSet()) - // Change a source full set into [0, 1 << 8*numbytes) + if (isFullSet() || isWrappedSet()) + // Change into [0, 1 << src bit width) return ConstantRange(APInt(DstTySize,0), APInt(DstTySize,1).shl(SrcTySize)); APInt L = Lower; L.zext(DstTySize); @@ -424,9 +434,11 @@ /// correspond to the possible range of values as if the source range had been /// sign extended. ConstantRange ConstantRange::signExtend(uint32_t DstTySize) const { + if (isEmptySet()) return ConstantRange(DstTySize, /*isFullSet=*/false); + unsigned SrcTySize = getBitWidth(); assert(SrcTySize < DstTySize && "Not a value extension"); - if (isFullSet()) { + if (isFullSet() || isSignWrappedSet()) { return ConstantRange(APInt::getHighBitsSet(DstTySize,DstTySize-SrcTySize+1), APInt::getLowBitsSet(DstTySize, SrcTySize-1) + 1); } Modified: llvm/trunk/unittests/Support/ConstantRangeTest.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/Support/ConstantRangeTest.cpp?rev=113187&r1=113186&r2=113187&view=diff ============================================================================== --- llvm/trunk/unittests/Support/ConstantRangeTest.cpp (original) +++ llvm/trunk/unittests/Support/ConstantRangeTest.cpp Mon Sep 6 18:52:49 2010 @@ -146,6 +146,22 @@ APInt(4, 7)); } +TEST_F(ConstantRangeTest, SignWrapped) { + EXPECT_TRUE(Full.isSignWrappedSet()); + EXPECT_FALSE(Empty.isSignWrappedSet()); + EXPECT_FALSE(One.isSignWrappedSet()); + EXPECT_FALSE(Some.isSignWrappedSet()); + EXPECT_TRUE(Wrap.isSignWrappedSet()); + + EXPECT_FALSE(ConstantRange(APInt(8, 127), APInt(8, 128)).isSignWrappedSet()); + EXPECT_TRUE(ConstantRange(APInt(8, 127), APInt(8, 129)).isSignWrappedSet()); + EXPECT_FALSE(ConstantRange(APInt(8, 128), APInt(8, 129)).isSignWrappedSet()); + EXPECT_TRUE(ConstantRange(APInt(8, 10), APInt(8, 9)).isSignWrappedSet()); + EXPECT_TRUE(ConstantRange(APInt(8, 10), APInt(8, 250)).isSignWrappedSet()); + EXPECT_FALSE(ConstantRange(APInt(8, 250), APInt(8, 10)).isSignWrappedSet()); + EXPECT_FALSE(ConstantRange(APInt(8, 250), APInt(8, 251)).isSignWrappedSet()); +} + TEST_F(ConstantRangeTest, Trunc) { ConstantRange TFull = Full.truncate(10); ConstantRange TEmpty = Empty.truncate(10); @@ -171,8 +187,7 @@ APInt(One.getUpper()).zext(20))); EXPECT_EQ(ZSome, ConstantRange(APInt(Some.getLower()).zext(20), APInt(Some.getUpper()).zext(20))); - EXPECT_EQ(ZWrap, ConstantRange(APInt(Wrap.getLower()).zext(20), - APInt(Wrap.getUpper()).zext(20))); + EXPECT_EQ(ZWrap, ConstantRange(APInt(20, 0), APInt(20, 0x10000))); } TEST_F(ConstantRangeTest, SExt) { @@ -188,8 +203,11 @@ APInt(One.getUpper()).sext(20))); EXPECT_EQ(SSome, ConstantRange(APInt(Some.getLower()).sext(20), APInt(Some.getUpper()).sext(20))); - EXPECT_EQ(SWrap, ConstantRange(APInt(Wrap.getLower()).sext(20), - APInt(Wrap.getUpper()).sext(20))); + EXPECT_EQ(SWrap, ConstantRange(APInt(20, (uint64_t)INT16_MIN, true), + APInt(20, INT16_MAX + 1, true))); + + EXPECT_EQ(ConstantRange(APInt(8, 120), APInt(8, 140)).signExtend(16), + ConstantRange(APInt(16, -128), APInt(16, 128))); } TEST_F(ConstantRangeTest, IntersectWith) { From sabre at nondot.org Mon Sep 6 18:57:25 2010 From: sabre at nondot.org (Chris Lattner) Date: Mon, 06 Sep 2010 23:57:25 -0000 Subject: [llvm-commits] [llvm] r113188 - /llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Message-ID: <20100906235725.232AC2A6C12C@llvm.org> Author: lattner Date: Mon Sep 6 18:57:24 2010 New Revision: 113188 URL: http://llvm.org/viewvc/llvm-project?rev=113188&view=rev Log: remove duplicated entry Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=113188&r1=113187&r2=113188&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Mon Sep 6 18:57:24 2010 @@ -663,7 +663,6 @@ .Case("jpe", "jp") .Case("jpo", "jnp") .Case("cmovcl", "cmovbl") - .Case("cmovcl", "cmovbl") .Case("cmovnal", "cmovbel") .Case("cmovnbl", "cmovael") .Case("cmovnbel", "cmoval") From sabre at nondot.org Mon Sep 6 19:05:45 2010 From: sabre at nondot.org (Chris Lattner) Date: Tue, 07 Sep 2010 00:05:45 -0000 Subject: [llvm-commits] [llvm] r113189 - in /llvm/trunk: lib/Target/X86/AsmParser/X86AsmParser.cpp test/MC/AsmParser/X86/x86_instructions.s Message-ID: <20100907000545.7FB032A6C12C@llvm.org> Author: lattner Date: Mon Sep 6 19:05:45 2010 New Revision: 113189 URL: http://llvm.org/viewvc/llvm-project?rev=113189&view=rev Log: add missing cmov aliases, this resolves rdar://8208499 Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=113189&r1=113188&r2=113189&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Mon Sep 6 19:05:45 2010 @@ -662,19 +662,33 @@ .Case("jnle", "jg") .Case("jpe", "jp") .Case("jpo", "jnp") - .Case("cmovcl", "cmovbl") - .Case("cmovnal", "cmovbel") - .Case("cmovnbl", "cmovael") - .Case("cmovnbel", "cmoval") - .Case("cmovncl", "cmovael") - .Case("cmovngl", "cmovlel") - .Case("cmovnl", "cmovgel") - .Case("cmovngl", "cmovlel") - .Case("cmovngel", "cmovll") - .Case("cmovnll", "cmovgel") - .Case("cmovnlel", "cmovgl") - .Case("cmovnzl", "cmovnel") - .Case("cmovzl", "cmovel") + // Condition code aliases for 16-bit, 32-bit, 64-bit and unspec operands. + .Case("cmovcw", "cmovbw") .Case("cmovcl", "cmovbl") + .Case("cmovcq", "cmovbq") .Case("cmovc", "cmovb") + .Case("cmovnaw", "cmovbew").Case("cmovnal", "cmovbel") + .Case("cmovnaq", "cmovbeq").Case("cmovna", "cmovbe") + .Case("cmovnbw", "cmovaew").Case("cmovnbl", "cmovael") + .Case("cmovnbq", "cmovaeq").Case("cmovnb", "cmovae") + .Case("cmovnbew","cmovaw") .Case("cmovnbel","cmoval") + .Case("cmovnbeq","cmovaq") .Case("cmovnbe", "cmova") + .Case("cmovncw", "cmovaew").Case("cmovncl", "cmovael") + .Case("cmovncq", "cmovaeq").Case("cmovnc", "cmovae") + .Case("cmovngw", "cmovlew").Case("cmovngl", "cmovlel") + .Case("cmovngq", "cmovleq").Case("cmovng", "cmovle") + .Case("cmovnw", "cmovgew").Case("cmovnl", "cmovgel") + .Case("cmovnq", "cmovgeq").Case("cmovn", "cmovge") + .Case("cmovngw", "cmovlew").Case("cmovngl", "cmovlel") + .Case("cmovngq", "cmovleq").Case("cmovng", "cmovle") + .Case("cmovngew","cmovlw") .Case("cmovngel","cmovll") + .Case("cmovngeq","cmovlq") .Case("cmovnge", "cmovl") + .Case("cmovnlw", "cmovgew").Case("cmovnll", "cmovgel") + .Case("cmovnlq", "cmovgeq").Case("cmovnl", "cmovge") + .Case("cmovnlew","cmovgw") .Case("cmovnlel","cmovgl") + .Case("cmovnleq","cmovgq") .Case("cmovnle", "cmovg") + .Case("cmovnzw", "cmovnew").Case("cmovnzl", "cmovnel") + .Case("cmovnzq", "cmovneq").Case("cmovnz", "cmovne") + .Case("cmovzw", "cmovew") .Case("cmovzl", "cmovel") + .Case("cmovzq", "cmoveq") .Case("cmovz", "cmove") .Case("fwait", "wait") .Case("movzx", "movzb") .Default(Name); Modified: llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s?rev=113189&r1=113188&r2=113189&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s Mon Sep 6 19:05:45 2010 @@ -181,3 +181,10 @@ // rdar://8017530 // CHECK: sldtw 4 sldt 4 + +// rdar://8208499 +// CHECK: cmovnew %bx, %ax +cmovnz %bx, %ax +// CHECK: cmovneq %rbx, %rax +cmovnzq %rbx, %rax + From geek4civic at gmail.com Mon Sep 6 19:52:06 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Tue, 7 Sep 2010 09:52:06 +0900 Subject: [llvm-commits] [PATCH] Target/ARM build failure on Cygwin-1.5 In-Reply-To: References: Message-ID: Hi, Chris, I got erros below; lib/Target/ARM/Disassembler/ARMDisassembler.cpp: In member function `void llvm::Session::UpdateIT()': lib/Target/ARM/Disassembler/ARMDisassembler.cpp:559: error: invalid initialization of reference of type 'uint32_t&' from expression of type 'unsigned int' lib/Target/ARM/Disassembler/ARMDisassemblerCore.h:130: error: in passing argument 1 of `void llvm::setSlice(uint32_t&, unsigned int, unsigned int, uint32_t)' $ gcc --version gcc (GCC) 3.4.4 (cygming special, gdc 0.12, using dmd 0.125) I thought it would not be good idea to fix setSlice(). ...Takumi 2010/9/7 Chris Lattner : > > On Sep 6, 2010, at 7:22 AM, NAKAMURA Takumi wrote: > >> Hello, >> >> Cygwin-1.5 has uint32_t as "unsigned long", and fails to build by type mismatch. >> I wonder which would be better to fix, Session::ITState or setSlice(). > > It's better to fix the other place. What error were you getting? > > -Chris From nicholas at mxc.ca Mon Sep 6 20:42:10 2010 From: nicholas at mxc.ca (Nick Lewycky) Date: Tue, 07 Sep 2010 01:42:10 -0000 Subject: [llvm-commits] [llvm] r113190 - /llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp Message-ID: <20100907014210.938ED2A6C12C@llvm.org> Author: nicholas Date: Mon Sep 6 20:42:10 2010 New Revision: 113190 URL: http://llvm.org/viewvc/llvm-project?rev=113190&view=rev Log: Fix major bug in thunk detection. Also verify the calling convention. Switch from isWeakForLinker to mayBeOverridden which is more accurate. Add more statistics and debugging info. Add comments. Move static function outside anonymous namespace. Modified: llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp Modified: llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp?rev=113190&r1=113189&r2=113190&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp (original) +++ llvm/trunk/lib/Transforms/IPO/MergeFunctions.cpp Mon Sep 6 20:42:10 2010 @@ -67,9 +67,12 @@ using namespace llvm; STATISTIC(NumFunctionsMerged, "Number of functions merged"); +STATISTIC(NumThunksWritten, "Number of thunks generated"); +STATISTIC(NumDoubleWeak, "Number of new functions created"); -namespace { - +/// ProfileFunction - Creates a hash-code for the function which is the same +/// for any two functions that will compare equal, without looking at the +/// instructions inside the function. static unsigned ProfileFunction(const Function *F) { const FunctionType *FTy = F->getFunctionType(); @@ -84,6 +87,8 @@ return ID.ComputeHash(); } +namespace { + class ComparableFunction { public: static const ComparableFunction EmptyKey; @@ -117,7 +122,7 @@ const ComparableFunction ComparableFunction::TombstoneKey = ComparableFunction(1); -} // anonymous namespace +} namespace llvm { template <> @@ -508,14 +513,14 @@ return false; assert(F1->arg_size() == F2->arg_size() && - "Identical functions have a different number of args."); + "Identically typed functions have different numbers of args!"); // Visit the arguments so that they get enumerated in the order they're // passed in. for (Function::const_arg_iterator f1i = F1->arg_begin(), f2i = F2->arg_begin(), f1e = F1->arg_end(); f1i != f1e; ++f1i, ++f2i) { if (!Enumerate(f1i, f2i)) - llvm_unreachable("Arguments repeat"); + llvm_unreachable("Arguments repeat!"); } // We do a CFG-ordered walk since the actual ordering of the blocks in the @@ -567,7 +572,7 @@ } } - // If G was internal then we may have replaced all uses if G with F. If so, + // If G was internal then we may have replaced all uses of G with F. If so, // stop here and delete G. There's no need for a thunk. if (G->hasLocalLinkage() && G->use_empty()) { G->eraseFromParent(); @@ -601,13 +606,16 @@ NewG->takeName(G); G->replaceAllUsesWith(NewG); G->eraseFromParent(); + + DEBUG(dbgs() << "WriteThunk: " << NewG->getName() << '\n'); + ++NumThunksWritten; } /// MergeTwoFunctions - Merge two equivalent functions. Upon completion, /// Function G is deleted. void MergeFunctions::MergeTwoFunctions(Function *F, Function *G) const { - if (F->isWeakForLinker()) { - assert(G->isWeakForLinker()); + if (F->mayBeOverridden()) { + assert(G->mayBeOverridden()); // Make them both thunks to the same internal function. Function *H = Function::Create(F->getFunctionType(), F->getLinkage(), "", @@ -623,6 +631,8 @@ F->setAlignment(MaxAlignment); F->setLinkage(GlobalValue::InternalLinkage); + + ++NumDoubleWeak; } else { WriteThunk(F, G); } @@ -640,8 +650,8 @@ const ComparableFunction &OldF = *Result.first; // Never thunk a strong function to a weak function. - assert(!OldF.getFunc()->isWeakForLinker() || - NewF.getFunc()->isWeakForLinker()); + assert(!OldF.getFunc()->mayBeOverridden() || + NewF.getFunc()->mayBeOverridden()); DEBUG(dbgs() << " " << OldF.getFunc()->getName() << " == " << NewF.getFunc()->getName() << '\n'); @@ -660,8 +670,7 @@ // then we may try to merge unmergable thing (ie., identical weak functions) // which will push us into an infinite loop. - if (F->size() != 1) - return false; + assert(!F->isDeclaration() && "Expected a function definition."); const BasicBlock *BB = &F->front(); // A thunk is: @@ -670,6 +679,10 @@ // ret void|optional-reg // where the args are in the same order as the arguments. + // Put this at the top since it triggers most often. + const ReturnInst *RI = dyn_cast(BB->getTerminator()); + if (!RI) return false; + // Verify that the sequence of bitcast-inst's are all casts of arguments and // that there aren't any extras (ie. no repeated casts). int LastArgNo = -1; @@ -677,18 +690,22 @@ while (const BitCastInst *BCI = dyn_cast(I)) { const Argument *A = dyn_cast(BCI->getOperand(0)); if (!A) return false; - if ((int)A->getArgNo() >= LastArgNo) return false; + if ((int)A->getArgNo() <= LastArgNo) return false; LastArgNo = A->getArgNo(); ++I; } + // Verify that we have a direct tail call and that the calling conventions + // and number of arguments match. + const CallInst *CI = dyn_cast(I++); + if (!CI || !CI->isTailCall() || !CI->getCalledFunction() || + CI->getCallingConv() != CI->getCalledFunction()->getCallingConv() || + CI->getNumArgOperands() != F->arg_size()) + return false; + // Verify that the call instruction has the same arguments as this function // and that they're all either the incoming argument or a cast of the right // argument. - const CallInst *CI = dyn_cast(I++); - if (!CI || !CI->isTailCall() || - CI->getNumArgOperands() != F->arg_size()) return false; - for (unsigned i = 0, e = CI->getNumArgOperands(); i != e; ++i) { const Value *V = CI->getArgOperand(i); const Argument *A = dyn_cast(V); @@ -708,8 +725,7 @@ if (BCI->getOperand(0) != CI) return false; RetOp = BCI; } - const ReturnInst *RI = dyn_cast(I); - if (!RI) return false; + if (RI != I) return false; if (RI->getNumOperands() == 0) return CI->getType()->isVoidTy(); return RI->getReturnValue() == CI; @@ -721,7 +737,7 @@ bool LocalChanged; do { - DEBUG(dbgs() << "size: " << M.size() << '\n'); + DEBUG(dbgs() << "size of module: " << M.size() << '\n'); LocalChanged = false; FnSetType FnSet; @@ -730,7 +746,7 @@ for (Module::iterator I = M.begin(), E = M.end(); I != E;) { Function *F = I++; if (!F->isDeclaration() && !F->hasAvailableExternallyLinkage() && - !F->isWeakForLinker() && !IsThunk(F)) { + !F->mayBeOverridden() && !IsThunk(F)) { ComparableFunction CF = ComparableFunction(F, TD); LocalChanged |= Insert(FnSet, CF); } @@ -743,11 +759,12 @@ for (Module::iterator I = M.begin(), E = M.end(); I != E;) { Function *F = I++; if (!F->isDeclaration() && !F->hasAvailableExternallyLinkage() && - F->isWeakForLinker() && !IsThunk(F)) { + F->mayBeOverridden() && !IsThunk(F)) { ComparableFunction CF = ComparableFunction(F, TD); LocalChanged |= Insert(FnSet, CF); } } + DEBUG(dbgs() << "size of FnSet: " << FnSet.size() << '\n'); Changed |= LocalChanged; } while (LocalChanged); From isanbard at gmail.com Mon Sep 6 21:15:01 2010 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 07 Sep 2010 02:15:01 -0000 Subject: [llvm-commits] [test-suite] r113194 - /test-suite/tags/RELEASE_28/rc1/ Message-ID: <20100907021501.CFD2F2A6C12D@llvm.org> Author: void Date: Mon Sep 6 21:15:01 2010 New Revision: 113194 URL: http://llvm.org/viewvc/llvm-project?rev=113194&view=rev Log: Creating release candidate 1 from 2.8 release branch. Added: test-suite/tags/RELEASE_28/rc1/ - copied from r113193, test-suite/branches/release_28/ From nicholas at mxc.ca Tue Sep 7 00:39:02 2010 From: nicholas at mxc.ca (Nick Lewycky) Date: Tue, 07 Sep 2010 05:39:02 -0000 Subject: [llvm-commits] [llvm] r113196 - in /llvm/trunk: include/llvm/Support/ConstantRange.h lib/Analysis/LazyValueInfo.cpp lib/Support/ConstantRange.cpp Message-ID: <20100907053902.9AFF12A6C12C@llvm.org> Author: nicholas Date: Tue Sep 7 00:39:02 2010 New Revision: 113196 URL: http://llvm.org/viewvc/llvm-project?rev=113196&view=rev Log: Add completely hokey binary-and and binary-or operations to ConstantRange and teach LazyValueInfo to use them. Modified: llvm/trunk/include/llvm/Support/ConstantRange.h llvm/trunk/lib/Analysis/LazyValueInfo.cpp llvm/trunk/lib/Support/ConstantRange.cpp Modified: llvm/trunk/include/llvm/Support/ConstantRange.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ConstantRange.h?rev=113196&r1=113195&r2=113196&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/ConstantRange.h (original) +++ llvm/trunk/include/llvm/Support/ConstantRange.h Tue Sep 7 00:39:02 2010 @@ -224,6 +224,14 @@ /// \p Other. ConstantRange udiv(const ConstantRange &Other) const; + /// binaryAnd - return a new range representing the possible values resulting + /// from a binary-and of a value in this range by a value in \p Other. + ConstantRange binaryAnd(const ConstantRange &Other) const; + + /// binaryOr - return a new range representing the possible values resulting + /// from a binary-or of a value in this range by a value in \p Other. + ConstantRange binaryOr(const ConstantRange &Other) const; + /// shl - Return a new range representing the possible values resulting /// from a left shift of a value in this range by a value in \p Other. /// TODO: This isn't fully implemented yet. Modified: llvm/trunk/lib/Analysis/LazyValueInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/LazyValueInfo.cpp?rev=113196&r1=113195&r2=113196&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/LazyValueInfo.cpp (original) +++ llvm/trunk/lib/Analysis/LazyValueInfo.cpp Tue Sep 7 00:39:02 2010 @@ -602,6 +602,12 @@ case Instruction::BitCast: Result.markConstantRange(LHSRange); break; + case Instruction::And: + Result.markConstantRange(LHSRange.binaryAnd(RHSRange)); + break; + case Instruction::Or: + Result.markConstantRange(LHSRange.binaryOr(RHSRange)); + break; // Unhandled instructions are overdefined. default: Modified: llvm/trunk/lib/Support/ConstantRange.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/ConstantRange.cpp?rev=113196&r1=113195&r2=113196&view=diff ============================================================================== --- llvm/trunk/lib/Support/ConstantRange.cpp (original) +++ llvm/trunk/lib/Support/ConstantRange.cpp Tue Sep 7 00:39:02 2010 @@ -608,6 +608,32 @@ } ConstantRange +ConstantRange::binaryAnd(const ConstantRange &Other) const { + if (isEmptySet() || Other.isEmptySet()) + return ConstantRange(getBitWidth(), /*isFullSet=*/false); + + // TODO: replace this with something less conservative + + APInt umin = APIntOps::umin(Other.getUnsignedMax(), getUnsignedMax()); + if (umin.isAllOnesValue()) + return ConstantRange(getBitWidth(), /*isFullSet=*/true); + return ConstantRange(APInt::getNullValue(getBitWidth()), umin + 1); +} + +ConstantRange +ConstantRange::binaryOr(const ConstantRange &Other) const { + if (isEmptySet() || Other.isEmptySet()) + return ConstantRange(getBitWidth(), /*isFullSet=*/false); + + // TODO: replace this with something less conservative + + APInt umax = APIntOps::umax(getUnsignedMin(), Other.getUnsignedMin()); + if (umax.isMinValue()) + return ConstantRange(getBitWidth(), /*isFullSet=*/true); + return ConstantRange(umax, APInt::getNullValue(getBitWidth())); +} + +ConstantRange ConstantRange::shl(const ConstantRange &Other) const { if (isEmptySet() || Other.isEmptySet()) return ConstantRange(getBitWidth(), /*isFullSet=*/false); From ggreif at gmail.com Tue Sep 7 01:06:07 2010 From: ggreif at gmail.com (Gabor Greif) Date: Tue, 07 Sep 2010 06:06:07 -0000 Subject: [llvm-commits] [llvm] r113197 - /llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Message-ID: <20100907060607.24ACB2A6C12C@llvm.org> Author: ggreif Date: Tue Sep 7 01:06:06 2010 New Revision: 113197 URL: http://llvm.org/viewvc/llvm-project?rev=113197&view=rev Log: fix comment typos Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=113197&r1=113196&r2=113197&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Tue Sep 7 01:06:06 2010 @@ -1709,7 +1709,7 @@ << "i != e; ++i)\n"; OS << " Classes[i] = InvalidMatchClass;\n\n"; - OS << " // Get the instruction mneumonic, which is the first token.\n"; + OS << " // Get the instruction mnemonic, which is the first token.\n"; OS << " StringRef Mnemonic = ((" << Target.getName() << "Operand*)Operands[0])->getToken();\n\n"; @@ -1733,7 +1733,7 @@ << "*ie = MnemonicRange.second;\n"; OS << " it != ie; ++it) {\n"; - OS << " // equal_range guarantees that instruction mneumonic matches.\n"; + OS << " // equal_range guarantees that instruction mnemonic matches.\n"; OS << " assert(Mnemonic == it->Mnemonic);\n"; // Emit check that the subclasses match. From sabre at nondot.org Tue Sep 7 01:10:48 2010 From: sabre at nondot.org (Chris Lattner) Date: Tue, 07 Sep 2010 06:10:48 -0000 Subject: [llvm-commits] [llvm] r113198 - /llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Message-ID: <20100907061048.E81F32A6C12C@llvm.org> Author: lattner Date: Tue Sep 7 01:10:48 2010 New Revision: 113198 URL: http://llvm.org/viewvc/llvm-project?rev=113198&view=rev Log: attempt to appease msvc Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=113198&r1=113197&r2=113198&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Tue Sep 7 01:10:48 2010 @@ -1637,6 +1637,9 @@ OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n"; OS << " return LHS < StringRef(RHS.Mnemonic);\n"; OS << " }\n"; + OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n"; + OS << " return StringRef(LHS.Mnemonic) < StringRef(RHS.Mnemonic);\n"; + OS << " }\n"; OS << " };\n"; OS << "} // end anonymous namespace.\n\n"; From benny.kra at googlemail.com Tue Sep 7 09:40:59 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Tue, 07 Sep 2010 14:40:59 -0000 Subject: [llvm-commits] [llvm] r113200 - /llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Message-ID: <20100907144059.193D72A6C12C@llvm.org> Author: d0k Date: Tue Sep 7 09:40:58 2010 New Revision: 113200 URL: http://llvm.org/viewvc/llvm-project?rev=113200&view=rev Log: Don't leak the old operand when transforming "sldt" into "sldtw". Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=113200&r1=113199&r2=113200&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Tue Sep 7 09:40:58 2010 @@ -837,8 +837,10 @@ // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity // errors, since its encoding is the most compact. if (Name == "sldt" && Operands.size() == 2 && - static_cast(Operands[1])->isMem()) + static_cast(Operands[1])->isMem()) { + delete Operands[0]; Operands[0] = X86Operand::CreateToken("sldtw", NameLoc); + } return false; } From clattner at apple.com Tue Sep 7 10:38:13 2010 From: clattner at apple.com (Chris Lattner) Date: Tue, 7 Sep 2010 08:38:13 -0700 Subject: [llvm-commits] [llvm] r113200 - /llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp In-Reply-To: <20100907144059.193D72A6C12C@llvm.org> References: <20100907144059.193D72A6C12C@llvm.org> Message-ID: On Sep 7, 2010, at 7:40 AM, Benjamin Kramer wrote: > Author: d0k > Date: Tue Sep 7 09:40:58 2010 > New Revision: 113200 > > URL: http://llvm.org/viewvc/llvm-project?rev=113200&view=rev > Log: > Don't leak the old operand when transforming "sldt" into "sldtw". Oops, thanks! -Chris > > Modified: > llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp > > Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=113200&r1=113199&r2=113200&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) > +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Tue Sep 7 09:40:58 2010 > @@ -837,8 +837,10 @@ > // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity > // errors, since its encoding is the most compact. > if (Name == "sldt" && Operands.size() == 2 && > - static_cast(Operands[1])->isMem()) > + static_cast(Operands[1])->isMem()) { > + delete Operands[0]; > Operands[0] = X86Operand::CreateToken("sldtw", NameLoc); > + } > > return false; > } > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dpatel at apple.com Tue Sep 7 11:40:54 2010 From: dpatel at apple.com (Devang Patel) Date: Tue, 07 Sep 2010 16:40:54 -0000 Subject: [llvm-commits] [llvm] r113208 - /llvm/trunk/test/CodeGen/X86/dbg-declare.ll Message-ID: <20100907164054.253352A6C12E@llvm.org> Author: dpatel Date: Tue Sep 7 11:40:53 2010 New Revision: 113208 URL: http://llvm.org/viewvc/llvm-project?rev=113208&view=rev Log: Add a test case to check handling of dbg-declare by fast-isel. Added: llvm/trunk/test/CodeGen/X86/dbg-declare.ll Added: llvm/trunk/test/CodeGen/X86/dbg-declare.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-declare.ll?rev=113208&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/dbg-declare.ll (added) +++ llvm/trunk/test/CodeGen/X86/dbg-declare.ll Tue Sep 7 11:40:53 2010 @@ -0,0 +1,243 @@ +; This test case checks handling of llvm.dbg.declare intrinsic during fast-isel. +; RUN: llc --disable-fp-elim -O0 %s -o %t.s +; RUN: %compile_c %t.s -o %t.o +; RUN: %link %t.o -o %t.exe +; RUN: echo {break f1\n break f2 \n break f3 \n break f5 \n break f9 \n run \n p i \n c \n p i\n c \n p i\n c \n p i\n c \n p i.x} > %t.in +; RUN: gdb -q -batch -n -x %t.in %t.exe > %t.out +; RUN: grep "1 = 42" %t.out +; RUN: grep "2 = 43" %t.out +; RUN: grep "3 = 44" %t.out +; RUN: grep "4 = 46" %t.out +; RUN: grep "5 = 51" %t.out + +target triple = "x86_64-apple-darwin" +%struct.XYZ = type { i32, i32, i32, i32, i32 } + +; Check handling of llvm.dbg.declare for an argument referred through alloca, where +; alloca dominates llvm.dbg.declare +define i32 @f1(i32 %i) nounwind ssp { +entry: + %i.addr = alloca i32, align 4 + store i32 %i, i32* %i.addr, align 4 + call void @llvm.dbg.declare(metadata !{i32* %i.addr}, metadata !16), !dbg !17 + %tmp = load i32* %i.addr, align 4, !dbg !18 + ret i32 %tmp, !dbg !18 +} + +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + +; Check handling of llvm.dbg.declare for an argument referred through alloca, where +; llvm.dbg.declare dominates alloca. +define i32 @f2(i32 %i) nounwind ssp { +entry: + call void @llvm.dbg.declare(metadata !{i32* %i.addr}, metadata !20), !dbg !21 + %i.addr = alloca i32, align 4 + store i32 %i, i32* %i.addr, align 4 + %tmp = load i32* %i.addr, align 4, !dbg !22 + ret i32 %tmp, !dbg !22 +} + +; Check handling of an argument referred directly by llvm.dbg.declare where at least +; one argument use dominates llvm.dbg.declare. +define i32 @f3(i32 %i) nounwind ssp { +entry: + %i.addr = alloca i32, align 4 + store i32 %i, i32* %i.addr, align 4 + call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !24), !dbg !25 + %tmp = load i32* %i.addr, align 4, !dbg !26 + ret i32 %tmp, !dbg !26 +} + +; Check handling of an argument referred directly by llvm.dbg.declare where +; llvm.dbg.declare dominates all uses of argument. +define i32 @f4(i32 %i) nounwind ssp { +entry: + call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !28), !dbg !29 + ret i32 %i, !dbg !30 +} + +; Check handling of an argument referred directly by llvm.dbg.declare where +; llvm.dbg.declare dominates all uses of argument in separate basic block. +define i32 @f5(i32 %i) nounwind ssp { +entry: + call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !32), !dbg !33 + br label %bbr +bbr: + ret i32 %i, !dbg !34 +} + +; Check handling of an argument referred directly by llvm.dbg.declare where +; argument is not used. +define i32 @f6(i32 %i) nounwind ssp { +entry: + call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !36), !dbg !37 + ret i32 1, !dbg !38 +} + +; Check handling of an byval argument referred directly by llvm.dbg.declare where +; argument is not used. +define i32 @f7(%struct.XYZ* byval %i) nounwind ssp { +entry: + call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !40), !dbg !48 + ret i32 1, !dbg !49 +} + +; Check handling of an byval argument referred directly by llvm.dbg.declare where +; argument use dominates llvm.dbg.declare. +define i32 @f8(%struct.XYZ* byval %i) nounwind ssp { +entry: + %tmp = getelementptr inbounds %struct.XYZ* %i, i32 0, i32 1, !dbg !53 + %tmp1 = load i32* %tmp, align 4, !dbg !53 + call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !51), !dbg !52 + ret i32 %tmp1, !dbg !53 +} + +; Check handling of an byval argument referred directly by llvm.dbg.declare where +; llvm.dbg.declare dominates all uses of argument. +define i32 @f9(%struct.XYZ* byval %i) nounwind ssp { +entry: + call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !55), !dbg !56 + %tmp = getelementptr inbounds %struct.XYZ* %i, i32 0, i32 2, !dbg !57 + %tmp1 = load i32* %tmp, align 4, !dbg !57 + ret i32 %tmp1, !dbg !57 +} + +; Check handling of an byval argument referred directly by llvm.dbg.declare where +; llvm.dbg.declare dominates all uses of argument in separate basic block. +define i32 @f10(%struct.XYZ* byval %i) nounwind ssp { +entry: + call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !59), !dbg !60 + br label %bbr +bbr: + %tmp = getelementptr inbounds %struct.XYZ* %i, i32 0, i32 3, !dbg !61 + %tmp1 = load i32* %tmp, align 4, !dbg !61 + ret i32 %tmp1, !dbg !61 +} + +define i32 @main() nounwind ssp { +entry: + %retval = alloca i32, align 4 + %abc = alloca %struct.XYZ, align 4 + %agg.tmp = alloca %struct.XYZ, align 4 + %agg.tmp13 = alloca %struct.XYZ, align 4 + %agg.tmp17 = alloca %struct.XYZ, align 4 + %agg.tmp21 = alloca %struct.XYZ, align 4 + store i32 0, i32* %retval + %call = call i32 @f1(i32 42), !dbg !63 + %call1 = call i32 @f2(i32 43), !dbg !65 + %call2 = call i32 @f3(i32 44), !dbg !66 + %call3 = call i32 @f4(i32 45), !dbg !67 + %call4 = call i32 @f5(i32 46), !dbg !68 + %call5 = call i32 @f6(i32 47), !dbg !69 + call void @llvm.dbg.declare(metadata !{%struct.XYZ* %abc}, metadata !70), !dbg !71 + %tmp = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 0, !dbg !72 + store i32 51, i32* %tmp, align 4, !dbg !72 + %tmp6 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 1, !dbg !72 + store i32 52, i32* %tmp6, align 4, !dbg !72 + %tmp7 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 2, !dbg !72 + store i32 53, i32* %tmp7, align 4, !dbg !72 + %tmp8 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 3, !dbg !72 + store i32 54, i32* %tmp8, align 4, !dbg !72 + %tmp9 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 4, !dbg !72 + store i32 55, i32* %tmp9, align 4, !dbg !72 + %tmp10 = bitcast %struct.XYZ* %agg.tmp to i8*, !dbg !73 + %tmp11 = bitcast %struct.XYZ* %abc to i8*, !dbg !73 + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp10, i8* %tmp11, i64 20, i32 4, i1 false), !dbg !73 + %call12 = call i32 @f7(%struct.XYZ* byval %agg.tmp), !dbg !73 + %tmp14 = bitcast %struct.XYZ* %agg.tmp13 to i8*, !dbg !74 + %tmp15 = bitcast %struct.XYZ* %abc to i8*, !dbg !74 + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp14, i8* %tmp15, i64 20, i32 4, i1 false), !dbg !74 + %call16 = call i32 @f8(%struct.XYZ* byval %agg.tmp13), !dbg !74 + %tmp18 = bitcast %struct.XYZ* %agg.tmp17 to i8*, !dbg !75 + %tmp19 = bitcast %struct.XYZ* %abc to i8*, !dbg !75 + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp18, i8* %tmp19, i64 20, i32 4, i1 false), !dbg !75 + %call20 = call i32 @f9(%struct.XYZ* byval %agg.tmp17), !dbg !75 + %tmp22 = bitcast %struct.XYZ* %agg.tmp21 to i8*, !dbg !76 + %tmp23 = bitcast %struct.XYZ* %abc to i8*, !dbg !76 + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp22, i8* %tmp23, i64 20, i32 4, i1 false), !dbg !76 + %call24 = call i32 @f10(%struct.XYZ* byval %agg.tmp21), !dbg !76 + ret i32 0, !dbg !77 +} + +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind + +!llvm.dbg.sp = !{!0, !6, !7, !8, !9, !10, !11, !12, !13, !14, !15} + +!0 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f1", metadata !"f1", metadata !"f1", metadata !1, i32 11, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f1} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 524329, metadata !"/Users/manav/dbg_info_bugs/fastisel_arg.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 524305, i32 0, i32 12, metadata !"/Users/manav/dbg_info_bugs/fastisel_arg.c", metadata !"/private/tmp", metadata !"clang version 2.8 (trunk 112967)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{metadata !5} +!5 = metadata !{i32 524324, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f2", metadata !"f2", metadata !"f2", metadata !1, i32 12, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f2} ; [ DW_TAG_subprogram ] +!7 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f3", metadata !"f3", metadata !"f3", metadata !1, i32 13, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f3} ; [ DW_TAG_subprogram ] +!8 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f4", metadata !"f4", metadata !"f4", metadata !1, i32 14, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f4} ; [ DW_TAG_subprogram ] +!9 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f5", metadata !"f5", metadata !"f5", metadata !1, i32 15, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f5} ; [ DW_TAG_subprogram ] +!10 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f6", metadata !"f6", metadata !"f6", metadata !1, i32 16, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f6} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f7", metadata !"f7", metadata !"f7", metadata !1, i32 17, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f7} ; [ DW_TAG_subprogram ] +!12 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f8", metadata !"f8", metadata !"f8", metadata !1, i32 18, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f8} ; [ DW_TAG_subprogram ] +!13 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f9", metadata !"f9", metadata !"f9", metadata !1, i32 19, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f9} ; [ DW_TAG_subprogram ] +!14 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f10", metadata !"f10", metadata !"f10", metadata !1, i32 20, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f10} ; [ DW_TAG_subprogram ] +!15 = metadata !{i32 524334, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"main", metadata !1, i32 23, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @main} ; [ DW_TAG_subprogram ] +!16 = metadata !{i32 524545, metadata !0, metadata !"i", metadata !1, i32 11, metadata !5} ; [ DW_TAG_arg_variable ] +!17 = metadata !{i32 11, i32 12, metadata !0, null} +!18 = metadata !{i32 11, i32 17, metadata !19, null} +!19 = metadata !{i32 524299, metadata !0, i32 11, i32 15, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] +!20 = metadata !{i32 524545, metadata !6, metadata !"i", metadata !1, i32 12, metadata !5} ; [ DW_TAG_arg_variable ] +!21 = metadata !{i32 12, i32 12, metadata !6, null} +!22 = metadata !{i32 12, i32 17, metadata !23, null} +!23 = metadata !{i32 524299, metadata !6, i32 12, i32 15, metadata !1, i32 1} ; [ DW_TAG_lexical_block ] +!24 = metadata !{i32 524545, metadata !7, metadata !"i", metadata !1, i32 13, metadata !5} ; [ DW_TAG_arg_variable ] +!25 = metadata !{i32 13, i32 12, metadata !7, null} +!26 = metadata !{i32 13, i32 17, metadata !27, null} +!27 = metadata !{i32 524299, metadata !7, i32 13, i32 15, metadata !1, i32 2} ; [ DW_TAG_lexical_block ] +!28 = metadata !{i32 524545, metadata !8, metadata !"i", metadata !1, i32 14, metadata !5} ; [ DW_TAG_arg_variable ] +!29 = metadata !{i32 14, i32 12, metadata !8, null} +!30 = metadata !{i32 14, i32 17, metadata !31, null} +!31 = metadata !{i32 524299, metadata !8, i32 14, i32 15, metadata !1, i32 3} ; [ DW_TAG_lexical_block ] +!32 = metadata !{i32 524545, metadata !9, metadata !"i", metadata !1, i32 15, metadata !5} ; [ DW_TAG_arg_variable ] +!33 = metadata !{i32 15, i32 12, metadata !9, null} +!34 = metadata !{i32 15, i32 17, metadata !35, null} +!35 = metadata !{i32 524299, metadata !9, i32 15, i32 15, metadata !1, i32 4} ; [ DW_TAG_lexical_block ] +!36 = metadata !{i32 524545, metadata !10, metadata !"i", metadata !1, i32 16, metadata !5} ; [ DW_TAG_arg_variable ] +!37 = metadata !{i32 16, i32 12, metadata !10, null} +!38 = metadata !{i32 16, i32 17, metadata !39, null} +!39 = metadata !{i32 524299, metadata !10, i32 16, i32 15, metadata !1, i32 5} ; [ DW_TAG_lexical_block ] +!40 = metadata !{i32 524545, metadata !11, metadata !"i", metadata !1, i32 17, metadata !41} ; [ DW_TAG_arg_variable ] +!41 = metadata !{i32 524307, metadata !1, metadata !"XYZ", metadata !1, i32 2, i64 160, i64 32, i64 0, i32 0, null, metadata !42, i32 0, null} ; [ DW_TAG_structure_type ] +!42 = metadata !{metadata !43, metadata !44, metadata !45, metadata !46, metadata !47} +!43 = metadata !{i32 524301, metadata !1, metadata !"x", metadata !1, i32 3, i64 32, i64 32, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] +!44 = metadata !{i32 524301, metadata !1, metadata !"y", metadata !1, i32 4, i64 32, i64 32, i64 32, i32 0, metadata !5} ; [ DW_TAG_member ] +!45 = metadata !{i32 524301, metadata !1, metadata !"z", metadata !1, i32 5, i64 32, i64 32, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] +!46 = metadata !{i32 524301, metadata !1, metadata !"a", metadata !1, i32 6, i64 32, i64 32, i64 96, i32 0, metadata !5} ; [ DW_TAG_member ] +!47 = metadata !{i32 524301, metadata !1, metadata !"b", metadata !1, i32 7, i64 32, i64 32, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] +!48 = metadata !{i32 17, i32 19, metadata !11, null} +!49 = metadata !{i32 17, i32 24, metadata !50, null} +!50 = metadata !{i32 524299, metadata !11, i32 17, i32 22, metadata !1, i32 6} ; [ DW_TAG_lexical_block ] +!51 = metadata !{i32 524545, metadata !12, metadata !"i", metadata !1, i32 18, metadata !41} ; [ DW_TAG_arg_variable ] +!52 = metadata !{i32 18, i32 19, metadata !12, null} +!53 = metadata !{i32 18, i32 24, metadata !54, null} +!54 = metadata !{i32 524299, metadata !12, i32 18, i32 22, metadata !1, i32 7} ; [ DW_TAG_lexical_block ] +!55 = metadata !{i32 524545, metadata !13, metadata !"i", metadata !1, i32 19, metadata !41} ; [ DW_TAG_arg_variable ] +!56 = metadata !{i32 19, i32 19, metadata !13, null} +!57 = metadata !{i32 19, i32 24, metadata !58, null} +!58 = metadata !{i32 524299, metadata !13, i32 19, i32 22, metadata !1, i32 8} ; [ DW_TAG_lexical_block ] +!59 = metadata !{i32 524545, metadata !14, metadata !"i", metadata !1, i32 20, metadata !41} ; [ DW_TAG_arg_variable ] +!60 = metadata !{i32 20, i32 20, metadata !14, null} +!61 = metadata !{i32 20, i32 25, metadata !62, null} +!62 = metadata !{i32 524299, metadata !14, i32 20, i32 23, metadata !1, i32 9} ; [ DW_TAG_lexical_block ] +!63 = metadata !{i32 24, i32 3, metadata !64, null} +!64 = metadata !{i32 524299, metadata !15, i32 23, i32 12, metadata !1, i32 10} ; [ DW_TAG_lexical_block ] +!65 = metadata !{i32 25, i32 3, metadata !64, null} +!66 = metadata !{i32 26, i32 3, metadata !64, null} +!67 = metadata !{i32 27, i32 3, metadata !64, null} +!68 = metadata !{i32 28, i32 3, metadata !64, null} +!69 = metadata !{i32 29, i32 3, metadata !64, null} +!70 = metadata !{i32 524544, metadata !64, metadata !"abc", metadata !1, i32 30, metadata !41} ; [ DW_TAG_auto_variable ] +!71 = metadata !{i32 30, i32 14, metadata !64, null} +!72 = metadata !{i32 30, i32 17, metadata !64, null} +!73 = metadata !{i32 31, i32 3, metadata !64, null} +!74 = metadata !{i32 32, i32 3, metadata !64, null} +!75 = metadata !{i32 33, i32 3, metadata !64, null} +!76 = metadata !{i32 34, i32 3, metadata !64, null} +!77 = metadata !{i32 36, i32 3, metadata !64, null} From wdietz2 at illinois.edu Tue Sep 7 11:39:40 2010 From: wdietz2 at illinois.edu (Will Dietz) Date: Tue, 07 Sep 2010 16:39:40 -0000 Subject: [llvm-commits] [poolalloc] r113207 - in /poolalloc/trunk/test/dsa/var_arg: basic_32.ll basic_64.ll Message-ID: <20100907163940.623D92A6C12D@llvm.org> Author: wdietz2 Date: Tue Sep 7 11:39:40 2010 New Revision: 113207 URL: http://llvm.org/viewvc/llvm-project?rev=113207&view=rev Log: Convert var_args lit tests to new 'check-type' format Modified: poolalloc/trunk/test/dsa/var_arg/basic_32.ll poolalloc/trunk/test/dsa/var_arg/basic_64.ll Modified: poolalloc/trunk/test/dsa/var_arg/basic_32.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/var_arg/basic_32.ll?rev=113207&r1=113206&r2=113207&view=diff ============================================================================== --- poolalloc/trunk/test/dsa/var_arg/basic_32.ll (original) +++ poolalloc/trunk/test/dsa/var_arg/basic_32.ll Tue Sep 7 11:39:40 2010 @@ -12,11 +12,9 @@ ; Don't propagate the VAStart flag to children... ;RUN: dsaopt %s -dsa-local -analyze -verify-flags "get:ap:0-V" ; On 32-bit, VAStart node should point to an array of the arguments -;RUN: dsaopt %s -dsa-local -analyze -print-only-types \ -;RUN: -print-node-for-value "get:ap:0" | grep -i array | grep -i folded | grep -i void +;RUN: dsaopt %s -dsa-local -analyze -check-type "get:ap:0,FoldedVOIDArray" ; And the argument node should be of the proper type (in this case an i32) -;RUN: dsaopt %s -dsa-local -analyze -print-only-types \ -;RUN: -print-node-for-value "get:ap:0:0" | grep {^0: i32$} +;RUN: dsaopt %s -dsa-local -analyze -check-type "get:ap:0:0,0:i32" ; The argument should be ref'd, but not mod'd ;RUN: dsaopt %s -dsa-local -analyze --verify-flags "get:ap:0:0+R-M" Modified: poolalloc/trunk/test/dsa/var_arg/basic_64.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/var_arg/basic_64.ll?rev=113207&r1=113206&r2=113207&view=diff ============================================================================== --- poolalloc/trunk/test/dsa/var_arg/basic_64.ll (original) +++ poolalloc/trunk/test/dsa/var_arg/basic_64.ll Tue Sep 7 11:39:40 2010 @@ -13,15 +13,13 @@ ;RUN: dsaopt %s -dsa-local -analyze -verify-flags "get:ap:8-V" ;RUN: dsaopt %s -dsa-local -analyze -verify-flags "get:ap:16-V" ; On 64-bit, VAStart node should be a struct pointing to an array of the arguments -;RUN: dsaopt %s -dsa-local -analyze -print-only-types \ -;RUN: -print-node-for-value "get:ap:8" | grep -i array | grep -i folded | grep -i void +;RUN: dsaopt %s -dsa-local -analyze -check-type "get:ap:8,FoldedVOIDArray" ; Both offsets 8 and 16 point to the array as a simplification. ; Verify that these are indeed the same node. ;RUN: dsaopt %s -dsa-local -analyze -check-same-node \ ;RUN: "get:ap:8,get:ap:16" ; And the argument node should be of the proper type (in this case an i32) -;RUN: dsaopt %s -dsa-local -analyze -print-only-types \ -;RUN: -print-node-for-value "get:ap:8:0" | grep {^0: i32$} +;RUN: dsaopt %s -dsa-local -analyze -check-type "get:ap:8:0,0:i32" ; The argument should be ref'd, but not mod'd ;RUN: dsaopt %s -dsa-local -analyze --verify-flags "get:ap:8:0+R-M" From dpatel at apple.com Tue Sep 7 11:56:35 2010 From: dpatel at apple.com (Devang Patel) Date: Tue, 07 Sep 2010 16:56:35 -0000 Subject: [llvm-commits] [llvm] r113209 - /llvm/trunk/test/CodeGen/X86/dbg-declare2.ll Message-ID: <20100907165635.6F0A32A6C12C@llvm.org> Author: dpatel Date: Tue Sep 7 11:56:35 2010 New Revision: 113209 URL: http://llvm.org/viewvc/llvm-project?rev=113209&view=rev Log: Add a test case to check handling of dbg-declare by selection DAG builder. Added: llvm/trunk/test/CodeGen/X86/dbg-declare2.ll Added: llvm/trunk/test/CodeGen/X86/dbg-declare2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-declare2.ll?rev=113209&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/dbg-declare2.ll (added) +++ llvm/trunk/test/CodeGen/X86/dbg-declare2.ll Tue Sep 7 11:56:35 2010 @@ -0,0 +1,244 @@ +; This test case checks handling of llvm.dbg.declare intrinsic during isel. +; RUN: llc --disable-fp-elim -O0 -fast-isel=false %s -o %t.s +; RUN: %compile_c %t.s -o %t.o +; RUN: %link %t.o -o %t.exe +; RUN: echo {break f1\n break f2 \n break f7 \n break f8 \n break f9 \n break f10 \n run \n p i\n c \n p i\n c \n p i.x\n c \n p i.x\n c \n p i.x \n c \n p i.x \n} > %t.in +; RUN: gdb -q -batch -n -x %t.in %t.exe > %t.out +; RUN: grep "1 = 42" %t.out +; RUN: grep "2 = 43" %t.out +; RUN: grep "3 = 51" %t.out +; RUN: grep "4 = 51" %t.out +; RUN: grep "5 = 51" %t.out +; RUN: grep "6 = 51" %t.out + +target triple = "x86_64-apple-darwin" +%struct.XYZ = type { i32, i32, i32, i32, i32 } + +; Check handling of llvm.dbg.declare for an argument referred through alloca, where +; alloca dominates llvm.dbg.declare +define i32 @f1(i32 %i) nounwind ssp { +entry: + %i.addr = alloca i32, align 4 + store i32 %i, i32* %i.addr, align 4 + call void @llvm.dbg.declare(metadata !{i32* %i.addr}, metadata !16), !dbg !17 + %tmp = load i32* %i.addr, align 4, !dbg !18 + ret i32 %tmp, !dbg !18 +} + +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + +; Check handling of llvm.dbg.declare for an argument referred through alloca, where +; llvm.dbg.declare dominates alloca. +define i32 @f2(i32 %i) nounwind ssp { +entry: + call void @llvm.dbg.declare(metadata !{i32* %i.addr}, metadata !20), !dbg !21 + %i.addr = alloca i32, align 4 + store i32 %i, i32* %i.addr, align 4 + %tmp = load i32* %i.addr, align 4, !dbg !22 + ret i32 %tmp, !dbg !22 +} + +; Check handling of an argument referred directly by llvm.dbg.declare where at least +; one argument use dominates llvm.dbg.declare. +define i32 @f3(i32 %i) nounwind ssp { +entry: + %i.addr = alloca i32, align 4 + store i32 %i, i32* %i.addr, align 4 + call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !24), !dbg !25 + %tmp = load i32* %i.addr, align 4, !dbg !26 + ret i32 %tmp, !dbg !26 +} + +; Check handling of an argument referred directly by llvm.dbg.declare where +; llvm.dbg.declare dominates all uses of argument. +define i32 @f4(i32 %i) nounwind ssp { +entry: + call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !28), !dbg !29 + ret i32 %i, !dbg !30 +} + +; Check handling of an argument referred directly by llvm.dbg.declare where +; llvm.dbg.declare dominates all uses of argument in separate basic block. +define i32 @f5(i32 %i) nounwind ssp { +entry: + call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !32), !dbg !33 + br label %bbr +bbr: + ret i32 %i, !dbg !34 +} + +; Check handling of an argument referred directly by llvm.dbg.declare where +; argument is not used. +define i32 @f6(i32 %i) nounwind ssp { +entry: + call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !36), !dbg !37 + ret i32 1, !dbg !38 +} + +; Check handling of an byval argument referred directly by llvm.dbg.declare where +; argument is not used. +define i32 @f7(%struct.XYZ* byval %i) nounwind ssp { +entry: + call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !40), !dbg !48 + ret i32 1, !dbg !49 +} + +; Check handling of an byval argument referred directly by llvm.dbg.declare where +; argument use dominates llvm.dbg.declare. +define i32 @f8(%struct.XYZ* byval %i) nounwind ssp { +entry: + %tmp = getelementptr inbounds %struct.XYZ* %i, i32 0, i32 1, !dbg !53 + %tmp1 = load i32* %tmp, align 4, !dbg !53 + call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !51), !dbg !52 + ret i32 %tmp1, !dbg !53 +} + +; Check handling of an byval argument referred directly by llvm.dbg.declare where +; llvm.dbg.declare dominates all uses of argument. +define i32 @f9(%struct.XYZ* byval %i) nounwind ssp { +entry: + call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !55), !dbg !56 + %tmp = getelementptr inbounds %struct.XYZ* %i, i32 0, i32 2, !dbg !57 + %tmp1 = load i32* %tmp, align 4, !dbg !57 + ret i32 %tmp1, !dbg !57 +} + +; Check handling of an byval argument referred directly by llvm.dbg.declare where +; llvm.dbg.declare dominates all uses of argument in separate basic block. +define i32 @f10(%struct.XYZ* byval %i) nounwind ssp { +entry: + call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !59), !dbg !60 + br label %bbr +bbr: + %tmp = getelementptr inbounds %struct.XYZ* %i, i32 0, i32 3, !dbg !61 + %tmp1 = load i32* %tmp, align 4, !dbg !61 + ret i32 %tmp1, !dbg !61 +} + +define i32 @main() nounwind ssp { +entry: + %retval = alloca i32, align 4 + %abc = alloca %struct.XYZ, align 4 + %agg.tmp = alloca %struct.XYZ, align 4 + %agg.tmp13 = alloca %struct.XYZ, align 4 + %agg.tmp17 = alloca %struct.XYZ, align 4 + %agg.tmp21 = alloca %struct.XYZ, align 4 + store i32 0, i32* %retval + %call = call i32 @f1(i32 42), !dbg !63 + %call1 = call i32 @f2(i32 43), !dbg !65 + %call2 = call i32 @f3(i32 44), !dbg !66 + %call3 = call i32 @f4(i32 45), !dbg !67 + %call4 = call i32 @f5(i32 46), !dbg !68 + %call5 = call i32 @f6(i32 47), !dbg !69 + call void @llvm.dbg.declare(metadata !{%struct.XYZ* %abc}, metadata !70), !dbg !71 + %tmp = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 0, !dbg !72 + store i32 51, i32* %tmp, align 4, !dbg !72 + %tmp6 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 1, !dbg !72 + store i32 52, i32* %tmp6, align 4, !dbg !72 + %tmp7 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 2, !dbg !72 + store i32 53, i32* %tmp7, align 4, !dbg !72 + %tmp8 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 3, !dbg !72 + store i32 54, i32* %tmp8, align 4, !dbg !72 + %tmp9 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 4, !dbg !72 + store i32 55, i32* %tmp9, align 4, !dbg !72 + %tmp10 = bitcast %struct.XYZ* %agg.tmp to i8*, !dbg !73 + %tmp11 = bitcast %struct.XYZ* %abc to i8*, !dbg !73 + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp10, i8* %tmp11, i64 20, i32 4, i1 false), !dbg !73 + %call12 = call i32 @f7(%struct.XYZ* byval %agg.tmp), !dbg !73 + %tmp14 = bitcast %struct.XYZ* %agg.tmp13 to i8*, !dbg !74 + %tmp15 = bitcast %struct.XYZ* %abc to i8*, !dbg !74 + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp14, i8* %tmp15, i64 20, i32 4, i1 false), !dbg !74 + %call16 = call i32 @f8(%struct.XYZ* byval %agg.tmp13), !dbg !74 + %tmp18 = bitcast %struct.XYZ* %agg.tmp17 to i8*, !dbg !75 + %tmp19 = bitcast %struct.XYZ* %abc to i8*, !dbg !75 + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp18, i8* %tmp19, i64 20, i32 4, i1 false), !dbg !75 + %call20 = call i32 @f9(%struct.XYZ* byval %agg.tmp17), !dbg !75 + %tmp22 = bitcast %struct.XYZ* %agg.tmp21 to i8*, !dbg !76 + %tmp23 = bitcast %struct.XYZ* %abc to i8*, !dbg !76 + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp22, i8* %tmp23, i64 20, i32 4, i1 false), !dbg !76 + %call24 = call i32 @f10(%struct.XYZ* byval %agg.tmp21), !dbg !76 + ret i32 0, !dbg !77 +} + +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind + +!llvm.dbg.sp = !{!0, !6, !7, !8, !9, !10, !11, !12, !13, !14, !15} + +!0 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f1", metadata !"f1", metadata !"f1", metadata !1, i32 11, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f1} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 524329, metadata !"/Users/manav/dbg_info_bugs/fastisel_arg.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 524305, i32 0, i32 12, metadata !"/Users/manav/dbg_info_bugs/fastisel_arg.c", metadata !"/private/tmp", metadata !"clang version 2.8 (trunk 112967)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{metadata !5} +!5 = metadata !{i32 524324, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f2", metadata !"f2", metadata !"f2", metadata !1, i32 12, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f2} ; [ DW_TAG_subprogram ] +!7 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f3", metadata !"f3", metadata !"f3", metadata !1, i32 13, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f3} ; [ DW_TAG_subprogram ] +!8 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f4", metadata !"f4", metadata !"f4", metadata !1, i32 14, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f4} ; [ DW_TAG_subprogram ] +!9 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f5", metadata !"f5", metadata !"f5", metadata !1, i32 15, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f5} ; [ DW_TAG_subprogram ] +!10 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f6", metadata !"f6", metadata !"f6", metadata !1, i32 16, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f6} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f7", metadata !"f7", metadata !"f7", metadata !1, i32 17, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f7} ; [ DW_TAG_subprogram ] +!12 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f8", metadata !"f8", metadata !"f8", metadata !1, i32 18, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f8} ; [ DW_TAG_subprogram ] +!13 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f9", metadata !"f9", metadata !"f9", metadata !1, i32 19, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f9} ; [ DW_TAG_subprogram ] +!14 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f10", metadata !"f10", metadata !"f10", metadata !1, i32 20, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f10} ; [ DW_TAG_subprogram ] +!15 = metadata !{i32 524334, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"main", metadata !1, i32 23, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @main} ; [ DW_TAG_subprogram ] +!16 = metadata !{i32 524545, metadata !0, metadata !"i", metadata !1, i32 11, metadata !5} ; [ DW_TAG_arg_variable ] +!17 = metadata !{i32 11, i32 12, metadata !0, null} +!18 = metadata !{i32 11, i32 17, metadata !19, null} +!19 = metadata !{i32 524299, metadata !0, i32 11, i32 15, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] +!20 = metadata !{i32 524545, metadata !6, metadata !"i", metadata !1, i32 12, metadata !5} ; [ DW_TAG_arg_variable ] +!21 = metadata !{i32 12, i32 12, metadata !6, null} +!22 = metadata !{i32 12, i32 17, metadata !23, null} +!23 = metadata !{i32 524299, metadata !6, i32 12, i32 15, metadata !1, i32 1} ; [ DW_TAG_lexical_block ] +!24 = metadata !{i32 524545, metadata !7, metadata !"i", metadata !1, i32 13, metadata !5} ; [ DW_TAG_arg_variable ] +!25 = metadata !{i32 13, i32 12, metadata !7, null} +!26 = metadata !{i32 13, i32 17, metadata !27, null} +!27 = metadata !{i32 524299, metadata !7, i32 13, i32 15, metadata !1, i32 2} ; [ DW_TAG_lexical_block ] +!28 = metadata !{i32 524545, metadata !8, metadata !"i", metadata !1, i32 14, metadata !5} ; [ DW_TAG_arg_variable ] +!29 = metadata !{i32 14, i32 12, metadata !8, null} +!30 = metadata !{i32 14, i32 17, metadata !31, null} +!31 = metadata !{i32 524299, metadata !8, i32 14, i32 15, metadata !1, i32 3} ; [ DW_TAG_lexical_block ] +!32 = metadata !{i32 524545, metadata !9, metadata !"i", metadata !1, i32 15, metadata !5} ; [ DW_TAG_arg_variable ] +!33 = metadata !{i32 15, i32 12, metadata !9, null} +!34 = metadata !{i32 15, i32 17, metadata !35, null} +!35 = metadata !{i32 524299, metadata !9, i32 15, i32 15, metadata !1, i32 4} ; [ DW_TAG_lexical_block ] +!36 = metadata !{i32 524545, metadata !10, metadata !"i", metadata !1, i32 16, metadata !5} ; [ DW_TAG_arg_variable ] +!37 = metadata !{i32 16, i32 12, metadata !10, null} +!38 = metadata !{i32 16, i32 17, metadata !39, null} +!39 = metadata !{i32 524299, metadata !10, i32 16, i32 15, metadata !1, i32 5} ; [ DW_TAG_lexical_block ] +!40 = metadata !{i32 524545, metadata !11, metadata !"i", metadata !1, i32 17, metadata !41} ; [ DW_TAG_arg_variable ] +!41 = metadata !{i32 524307, metadata !1, metadata !"XYZ", metadata !1, i32 2, i64 160, i64 32, i64 0, i32 0, null, metadata !42, i32 0, null} ; [ DW_TAG_structure_type ] +!42 = metadata !{metadata !43, metadata !44, metadata !45, metadata !46, metadata !47} +!43 = metadata !{i32 524301, metadata !1, metadata !"x", metadata !1, i32 3, i64 32, i64 32, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] +!44 = metadata !{i32 524301, metadata !1, metadata !"y", metadata !1, i32 4, i64 32, i64 32, i64 32, i32 0, metadata !5} ; [ DW_TAG_member ] +!45 = metadata !{i32 524301, metadata !1, metadata !"z", metadata !1, i32 5, i64 32, i64 32, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] +!46 = metadata !{i32 524301, metadata !1, metadata !"a", metadata !1, i32 6, i64 32, i64 32, i64 96, i32 0, metadata !5} ; [ DW_TAG_member ] +!47 = metadata !{i32 524301, metadata !1, metadata !"b", metadata !1, i32 7, i64 32, i64 32, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] +!48 = metadata !{i32 17, i32 19, metadata !11, null} +!49 = metadata !{i32 17, i32 24, metadata !50, null} +!50 = metadata !{i32 524299, metadata !11, i32 17, i32 22, metadata !1, i32 6} ; [ DW_TAG_lexical_block ] +!51 = metadata !{i32 524545, metadata !12, metadata !"i", metadata !1, i32 18, metadata !41} ; [ DW_TAG_arg_variable ] +!52 = metadata !{i32 18, i32 19, metadata !12, null} +!53 = metadata !{i32 18, i32 24, metadata !54, null} +!54 = metadata !{i32 524299, metadata !12, i32 18, i32 22, metadata !1, i32 7} ; [ DW_TAG_lexical_block ] +!55 = metadata !{i32 524545, metadata !13, metadata !"i", metadata !1, i32 19, metadata !41} ; [ DW_TAG_arg_variable ] +!56 = metadata !{i32 19, i32 19, metadata !13, null} +!57 = metadata !{i32 19, i32 24, metadata !58, null} +!58 = metadata !{i32 524299, metadata !13, i32 19, i32 22, metadata !1, i32 8} ; [ DW_TAG_lexical_block ] +!59 = metadata !{i32 524545, metadata !14, metadata !"i", metadata !1, i32 20, metadata !41} ; [ DW_TAG_arg_variable ] +!60 = metadata !{i32 20, i32 20, metadata !14, null} +!61 = metadata !{i32 20, i32 25, metadata !62, null} +!62 = metadata !{i32 524299, metadata !14, i32 20, i32 23, metadata !1, i32 9} ; [ DW_TAG_lexical_block ] +!63 = metadata !{i32 24, i32 3, metadata !64, null} +!64 = metadata !{i32 524299, metadata !15, i32 23, i32 12, metadata !1, i32 10} ; [ DW_TAG_lexical_block ] +!65 = metadata !{i32 25, i32 3, metadata !64, null} +!66 = metadata !{i32 26, i32 3, metadata !64, null} +!67 = metadata !{i32 27, i32 3, metadata !64, null} +!68 = metadata !{i32 28, i32 3, metadata !64, null} +!69 = metadata !{i32 29, i32 3, metadata !64, null} +!70 = metadata !{i32 524544, metadata !64, metadata !"abc", metadata !1, i32 30, metadata !41} ; [ DW_TAG_auto_variable ] +!71 = metadata !{i32 30, i32 14, metadata !64, null} +!72 = metadata !{i32 30, i32 17, metadata !64, null} +!73 = metadata !{i32 31, i32 3, metadata !64, null} +!74 = metadata !{i32 32, i32 3, metadata !64, null} +!75 = metadata !{i32 33, i32 3, metadata !64, null} +!76 = metadata !{i32 34, i32 3, metadata !64, null} +!77 = metadata !{i32 36, i32 3, metadata !64, null} From dpatel at apple.com Tue Sep 7 12:03:44 2010 From: dpatel at apple.com (Devang Patel) Date: Tue, 07 Sep 2010 17:03:44 -0000 Subject: [llvm-commits] [llvm] r113210 - /llvm/trunk/test/CodeGen/X86/dbg-declare3.ll Message-ID: <20100907170344.89F762A6C12C@llvm.org> Author: dpatel Date: Tue Sep 7 12:03:44 2010 New Revision: 113210 URL: http://llvm.org/viewvc/llvm-project?rev=113210&view=rev Log: Add a test case to check handling of dbg-declare during hybrid mode where we begin using fast-isel but switch back to DAG building at some point. Added: llvm/trunk/test/CodeGen/X86/dbg-declare3.ll Added: llvm/trunk/test/CodeGen/X86/dbg-declare3.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-declare3.ll?rev=113210&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/dbg-declare3.ll (added) +++ llvm/trunk/test/CodeGen/X86/dbg-declare3.ll Tue Sep 7 12:03:44 2010 @@ -0,0 +1,266 @@ +; This test case checks handling of llvm.dbg.declare intrinsic during hybrid mode where we begin +; using fast-isel but switch back to DAG building at some point. +; RUN: llc --disable-fp-elim -O0 %s -o %t.s +; RUN: %compile_c %t.s -o %t.o +; RUN: %link %t.o -o %t.exe +; RUN: echo {break f1\n break f4\n break f5\n run \n p i\n c \n p i\n c \n p i\n} > %t.in +; RUN: gdb -q -batch -n -x %t.in %t.exe > %t.out +; RUN: grep "1 = 42" %t.out +; RUN: grep "2 = 45" %t.out +; RUN: grep "3 = 46" %t.out + +target triple = "x86_64-apple-darwin" +%struct.XYZ = type { i32, i32, i32, i32, i32 } +%0 = type { i64, i32 } +define %0 @foobar() { + ret i64 6, i32 7 +} + +; Check handling of llvm.dbg.declare for an argument referred through alloca, where +; alloca dominates llvm.dbg.declare +define i32 @f1(i32 %i) nounwind ssp { +entry: + %i.addr = alloca i32, align 4 + store i32 %i, i32* %i.addr, align 4 + %call = call %0 @foobar() + call void @llvm.dbg.declare(metadata !{i32* %i.addr}, metadata !16), !dbg !17 + %call2 = call %0 @foobar() + %tmp = load i32* %i.addr, align 4, !dbg !18 + ret i32 %tmp, !dbg !18 +} + +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + +; Check handling of llvm.dbg.declare for an argument referred through alloca, where +; llvm.dbg.declare dominates alloca. +define i32 @f2(i32 %i) nounwind ssp { +entry: + %call = call %0 @foobar() + call void @llvm.dbg.declare(metadata !{i32* %i.addr}, metadata !20), !dbg !21 + %call2 = call %0 @foobar() + %i.addr = alloca i32, align 4 + store i32 %i, i32* %i.addr, align 4 + %tmp = load i32* %i.addr, align 4, !dbg !22 + ret i32 %tmp, !dbg !22 +} + +; Check handling of an argument referred directly by llvm.dbg.declare where at least +; one argument use dominates llvm.dbg.declare. +define i32 @f3(i32 %i) nounwind ssp { +entry: + %i.addr = alloca i32, align 4 + store i32 %i, i32* %i.addr, align 4 + %call = call %0 @foobar() + call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !24), !dbg !2 + %call2 = call %0 @foobar() + %tmp = load i32* %i.addr, align 4, !dbg !26 + ret i32 %tmp, !dbg !26 +} + +; Check handling of an argument referred directly by llvm.dbg.declare where +; llvm.dbg.declare dominates all uses of argument. +define i32 @f4(i32 %i) nounwind ssp { +entry: + %call = call %0 @foobar() + call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !28), !dbg !29 + %call2 = call %0 @foobar() + ret i32 %i, !dbg !30 +} + +; Check handling of an argument referred directly by llvm.dbg.declare where +; llvm.dbg.declare dominates all uses of argument in separate basic block. +define i32 @f5(i32 %i) nounwind ssp { +entry: + %call = call %0 @foobar() + call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !32), !dbg !33 + %call2 = call %0 @foobar() + br label %bbr +bbr: + ret i32 %i, !dbg !34 +} + +; Check handling of an argument referred directly by llvm.dbg.declare where +; argument is not used. +define i32 @f6(i32 %i) nounwind ssp { +entry: + %call = call %0 @foobar() + call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !36), !dbg !37 + %call2 = call %0 @foobar() + ret i32 1, !dbg !38 +} + +; Check handling of an byval argument referred directly by llvm.dbg.declare where +; argument is not used. +define i32 @f7(%struct.XYZ* byval %i) nounwind ssp { +entry: + %call = call %0 @foobar() + call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !40), !dbg !48 + %call2 = call %0 @foobar() + ret i32 1, !dbg !49 +} + +; Check handling of an byval argument referred directly by llvm.dbg.declare where +; argument use dominates llvm.dbg.declare. +define i32 @f8(%struct.XYZ* byval %i) nounwind ssp { +entry: + %tmp = getelementptr inbounds %struct.XYZ* %i, i32 0, i32 1, !dbg !53 + %tmp1 = load i32* %tmp, align 4, !dbg !53 + %call = call %0 @foobar() + call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !51), !dbg !52 + %call2 = call %0 @foobar() + ret i32 %tmp1, !dbg !53 +} + +; Check handling of an byval argument referred directly by llvm.dbg.declare where +; llvm.dbg.declare dominates all uses of argument. +define i32 @f9(%struct.XYZ* byval %i) nounwind ssp { +entry: + %call = call %0 @foobar() + call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !55), !dbg !56 + %call2 = call %0 @foobar() + %tmp = getelementptr inbounds %struct.XYZ* %i, i32 0, i32 2, !dbg !57 + %tmp1 = load i32* %tmp, align 4, !dbg !57 + ret i32 %tmp1, !dbg !57 +} + +; Check handling of an byval argument referred directly by llvm.dbg.declare where +; llvm.dbg.declare dominates all uses of argument in separate basic block. +define i32 @f10(%struct.XYZ* byval %i) nounwind ssp { +entry: + %call = call %0 @foobar() + call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !59), !dbg !60 + %call2 = call %0 @foobar() + br label %bbr +bbr: + %tmp = getelementptr inbounds %struct.XYZ* %i, i32 0, i32 3, !dbg !61 + %tmp1 = load i32* %tmp, align 4, !dbg !61 + ret i32 %tmp1, !dbg !61 +} + +define i32 @main() nounwind ssp { +entry: + %retval = alloca i32, align 4 + %abc = alloca %struct.XYZ, align 4 + %agg.tmp = alloca %struct.XYZ, align 4 + %agg.tmp13 = alloca %struct.XYZ, align 4 + %agg.tmp17 = alloca %struct.XYZ, align 4 + %agg.tmp21 = alloca %struct.XYZ, align 4 + store i32 0, i32* %retval + %call = call i32 @f1(i32 42), !dbg !63 + %call1 = call i32 @f2(i32 43), !dbg !65 + %call2 = call i32 @f3(i32 44), !dbg !66 + %call3 = call i32 @f4(i32 45), !dbg !67 + %call4 = call i32 @f5(i32 46), !dbg !68 + %call5 = call i32 @f6(i32 47), !dbg !69 + call void @llvm.dbg.declare(metadata !{%struct.XYZ* %abc}, metadata !70), !dbg !71 + %tmp = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 0, !dbg !72 + store i32 51, i32* %tmp, align 4, !dbg !72 + %tmp6 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 1, !dbg !72 + store i32 52, i32* %tmp6, align 4, !dbg !72 + %tmp7 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 2, !dbg !72 + store i32 53, i32* %tmp7, align 4, !dbg !72 + %tmp8 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 3, !dbg !72 + store i32 54, i32* %tmp8, align 4, !dbg !72 + %tmp9 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 4, !dbg !72 + store i32 55, i32* %tmp9, align 4, !dbg !72 + %tmp10 = bitcast %struct.XYZ* %agg.tmp to i8*, !dbg !73 + %tmp11 = bitcast %struct.XYZ* %abc to i8*, !dbg !73 + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp10, i8* %tmp11, i64 20, i32 4, i1 false), !dbg !73 + %call12 = call i32 @f7(%struct.XYZ* byval %agg.tmp), !dbg !73 + %tmp14 = bitcast %struct.XYZ* %agg.tmp13 to i8*, !dbg !74 + %tmp15 = bitcast %struct.XYZ* %abc to i8*, !dbg !74 + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp14, i8* %tmp15, i64 20, i32 4, i1 false), !dbg !74 + %call16 = call i32 @f8(%struct.XYZ* byval %agg.tmp13), !dbg !74 + %tmp18 = bitcast %struct.XYZ* %agg.tmp17 to i8*, !dbg !75 + %tmp19 = bitcast %struct.XYZ* %abc to i8*, !dbg !75 + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp18, i8* %tmp19, i64 20, i32 4, i1 false), !dbg !75 + %call20 = call i32 @f9(%struct.XYZ* byval %agg.tmp17), !dbg !75 + %tmp22 = bitcast %struct.XYZ* %agg.tmp21 to i8*, !dbg !76 + %tmp23 = bitcast %struct.XYZ* %abc to i8*, !dbg !76 + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp22, i8* %tmp23, i64 20, i32 4, i1 false), !dbg !76 + %call24 = call i32 @f10(%struct.XYZ* byval %agg.tmp21), !dbg !76 + ret i32 0, !dbg !77 +} + +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind + +!llvm.dbg.sp = !{!0, !6, !7, !8, !9, !10, !11, !12, !13, !14, !15} + +!0 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f1", metadata !"f1", metadata !"f1", metadata !1, i32 11, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f1} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 524329, metadata !"/Users/manav/dbg_info_bugs/fastisel_arg.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 524305, i32 0, i32 12, metadata !"/Users/manav/dbg_info_bugs/fastisel_arg.c", metadata !"/private/tmp", metadata !"clang version 2.8 (trunk 112967)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{metadata !5} +!5 = metadata !{i32 524324, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f2", metadata !"f2", metadata !"f2", metadata !1, i32 12, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f2} ; [ DW_TAG_subprogram ] +!7 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f3", metadata !"f3", metadata !"f3", metadata !1, i32 13, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f3} ; [ DW_TAG_subprogram ] +!8 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f4", metadata !"f4", metadata !"f4", metadata !1, i32 14, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f4} ; [ DW_TAG_subprogram ] +!9 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f5", metadata !"f5", metadata !"f5", metadata !1, i32 15, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f5} ; [ DW_TAG_subprogram ] +!10 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f6", metadata !"f6", metadata !"f6", metadata !1, i32 16, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f6} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f7", metadata !"f7", metadata !"f7", metadata !1, i32 17, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f7} ; [ DW_TAG_subprogram ] +!12 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f8", metadata !"f8", metadata !"f8", metadata !1, i32 18, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f8} ; [ DW_TAG_subprogram ] +!13 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f9", metadata !"f9", metadata !"f9", metadata !1, i32 19, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f9} ; [ DW_TAG_subprogram ] +!14 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f10", metadata !"f10", metadata !"f10", metadata !1, i32 20, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f10} ; [ DW_TAG_subprogram ] +!15 = metadata !{i32 524334, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"main", metadata !1, i32 23, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @main} ; [ DW_TAG_subprogram ] +!16 = metadata !{i32 524545, metadata !0, metadata !"i", metadata !1, i32 11, metadata !5} ; [ DW_TAG_arg_variable ] +!17 = metadata !{i32 11, i32 12, metadata !0, null} +!18 = metadata !{i32 11, i32 17, metadata !19, null} +!19 = metadata !{i32 524299, metadata !0, i32 11, i32 15, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] +!20 = metadata !{i32 524545, metadata !6, metadata !"i", metadata !1, i32 12, metadata !5} ; [ DW_TAG_arg_variable ] +!21 = metadata !{i32 12, i32 12, metadata !6, null} +!22 = metadata !{i32 12, i32 17, metadata !23, null} +!23 = metadata !{i32 524299, metadata !6, i32 12, i32 15, metadata !1, i32 1} ; [ DW_TAG_lexical_block ] +!24 = metadata !{i32 524545, metadata !7, metadata !"i", metadata !1, i32 13, metadata !5} ; [ DW_TAG_arg_variable ] +!25 = metadata !{i32 13, i32 12, metadata !7, null} +!26 = metadata !{i32 13, i32 17, metadata !27, null} +!27 = metadata !{i32 524299, metadata !7, i32 13, i32 15, metadata !1, i32 2} ; [ DW_TAG_lexical_block ] +!28 = metadata !{i32 524545, metadata !8, metadata !"i", metadata !1, i32 14, metadata !5} ; [ DW_TAG_arg_variable ] +!29 = metadata !{i32 14, i32 12, metadata !8, null} +!30 = metadata !{i32 14, i32 17, metadata !31, null} +!31 = metadata !{i32 524299, metadata !8, i32 14, i32 15, metadata !1, i32 3} ; [ DW_TAG_lexical_block ] +!32 = metadata !{i32 524545, metadata !9, metadata !"i", metadata !1, i32 15, metadata !5} ; [ DW_TAG_arg_variable ] +!33 = metadata !{i32 15, i32 12, metadata !9, null} +!34 = metadata !{i32 15, i32 17, metadata !35, null} +!35 = metadata !{i32 524299, metadata !9, i32 15, i32 15, metadata !1, i32 4} ; [ DW_TAG_lexical_block ] +!36 = metadata !{i32 524545, metadata !10, metadata !"i", metadata !1, i32 16, metadata !5} ; [ DW_TAG_arg_variable ] +!37 = metadata !{i32 16, i32 12, metadata !10, null} +!38 = metadata !{i32 16, i32 17, metadata !39, null} +!39 = metadata !{i32 524299, metadata !10, i32 16, i32 15, metadata !1, i32 5} ; [ DW_TAG_lexical_block ] +!40 = metadata !{i32 524545, metadata !11, metadata !"i", metadata !1, i32 17, metadata !41} ; [ DW_TAG_arg_variable ] +!41 = metadata !{i32 524307, metadata !1, metadata !"XYZ", metadata !1, i32 2, i64 160, i64 32, i64 0, i32 0, null, metadata !42, i32 0, null} ; [ DW_TAG_structure_type ] +!42 = metadata !{metadata !43, metadata !44, metadata !45, metadata !46, metadata !47} +!43 = metadata !{i32 524301, metadata !1, metadata !"x", metadata !1, i32 3, i64 32, i64 32, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] +!44 = metadata !{i32 524301, metadata !1, metadata !"y", metadata !1, i32 4, i64 32, i64 32, i64 32, i32 0, metadata !5} ; [ DW_TAG_member ] +!45 = metadata !{i32 524301, metadata !1, metadata !"z", metadata !1, i32 5, i64 32, i64 32, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] +!46 = metadata !{i32 524301, metadata !1, metadata !"a", metadata !1, i32 6, i64 32, i64 32, i64 96, i32 0, metadata !5} ; [ DW_TAG_member ] +!47 = metadata !{i32 524301, metadata !1, metadata !"b", metadata !1, i32 7, i64 32, i64 32, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] +!48 = metadata !{i32 17, i32 19, metadata !11, null} +!49 = metadata !{i32 17, i32 24, metadata !50, null} +!50 = metadata !{i32 524299, metadata !11, i32 17, i32 22, metadata !1, i32 6} ; [ DW_TAG_lexical_block ] +!51 = metadata !{i32 524545, metadata !12, metadata !"i", metadata !1, i32 18, metadata !41} ; [ DW_TAG_arg_variable ] +!52 = metadata !{i32 18, i32 19, metadata !12, null} +!53 = metadata !{i32 18, i32 24, metadata !54, null} +!54 = metadata !{i32 524299, metadata !12, i32 18, i32 22, metadata !1, i32 7} ; [ DW_TAG_lexical_block ] +!55 = metadata !{i32 524545, metadata !13, metadata !"i", metadata !1, i32 19, metadata !41} ; [ DW_TAG_arg_variable ] +!56 = metadata !{i32 19, i32 19, metadata !13, null} +!57 = metadata !{i32 19, i32 24, metadata !58, null} +!58 = metadata !{i32 524299, metadata !13, i32 19, i32 22, metadata !1, i32 8} ; [ DW_TAG_lexical_block ] +!59 = metadata !{i32 524545, metadata !14, metadata !"i", metadata !1, i32 20, metadata !41} ; [ DW_TAG_arg_variable ] +!60 = metadata !{i32 20, i32 20, metadata !14, null} +!61 = metadata !{i32 20, i32 25, metadata !62, null} +!62 = metadata !{i32 524299, metadata !14, i32 20, i32 23, metadata !1, i32 9} ; [ DW_TAG_lexical_block ] +!63 = metadata !{i32 24, i32 3, metadata !64, null} +!64 = metadata !{i32 524299, metadata !15, i32 23, i32 12, metadata !1, i32 10} ; [ DW_TAG_lexical_block ] +!65 = metadata !{i32 25, i32 3, metadata !64, null} +!66 = metadata !{i32 26, i32 3, metadata !64, null} +!67 = metadata !{i32 27, i32 3, metadata !64, null} +!68 = metadata !{i32 28, i32 3, metadata !64, null} +!69 = metadata !{i32 29, i32 3, metadata !64, null} +!70 = metadata !{i32 524544, metadata !64, metadata !"abc", metadata !1, i32 30, metadata !41} ; [ DW_TAG_auto_variable ] +!71 = metadata !{i32 30, i32 14, metadata !64, null} +!72 = metadata !{i32 30, i32 17, metadata !64, null} +!73 = metadata !{i32 31, i32 3, metadata !64, null} +!74 = metadata !{i32 32, i32 3, metadata !64, null} +!75 = metadata !{i32 33, i32 3, metadata !64, null} +!76 = metadata !{i32 34, i32 3, metadata !64, null} +!77 = metadata !{i32 36, i32 3, metadata !64, null} From dpatel at apple.com Tue Sep 7 12:08:57 2010 From: dpatel at apple.com (Devang Patel) Date: Tue, 07 Sep 2010 17:08:57 -0000 Subject: [llvm-commits] [llvm] r113213 - in /llvm/trunk/test/CodeGen/X86: dbg-declare.ll dbg-declare2.ll dbg-declare3.ll Message-ID: <20100907170857.9CCC42A6C12C@llvm.org> Author: dpatel Date: Tue Sep 7 12:08:57 2010 New Revision: 113213 URL: http://llvm.org/viewvc/llvm-project?rev=113213&view=rev Log: Remove last three tests. I need to make them independent of my setup. Removed: llvm/trunk/test/CodeGen/X86/dbg-declare.ll llvm/trunk/test/CodeGen/X86/dbg-declare2.ll llvm/trunk/test/CodeGen/X86/dbg-declare3.ll Removed: llvm/trunk/test/CodeGen/X86/dbg-declare.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-declare.ll?rev=113212&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/dbg-declare.ll (original) +++ llvm/trunk/test/CodeGen/X86/dbg-declare.ll (removed) @@ -1,243 +0,0 @@ -; This test case checks handling of llvm.dbg.declare intrinsic during fast-isel. -; RUN: llc --disable-fp-elim -O0 %s -o %t.s -; RUN: %compile_c %t.s -o %t.o -; RUN: %link %t.o -o %t.exe -; RUN: echo {break f1\n break f2 \n break f3 \n break f5 \n break f9 \n run \n p i \n c \n p i\n c \n p i\n c \n p i\n c \n p i.x} > %t.in -; RUN: gdb -q -batch -n -x %t.in %t.exe > %t.out -; RUN: grep "1 = 42" %t.out -; RUN: grep "2 = 43" %t.out -; RUN: grep "3 = 44" %t.out -; RUN: grep "4 = 46" %t.out -; RUN: grep "5 = 51" %t.out - -target triple = "x86_64-apple-darwin" -%struct.XYZ = type { i32, i32, i32, i32, i32 } - -; Check handling of llvm.dbg.declare for an argument referred through alloca, where -; alloca dominates llvm.dbg.declare -define i32 @f1(i32 %i) nounwind ssp { -entry: - %i.addr = alloca i32, align 4 - store i32 %i, i32* %i.addr, align 4 - call void @llvm.dbg.declare(metadata !{i32* %i.addr}, metadata !16), !dbg !17 - %tmp = load i32* %i.addr, align 4, !dbg !18 - ret i32 %tmp, !dbg !18 -} - -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone - -; Check handling of llvm.dbg.declare for an argument referred through alloca, where -; llvm.dbg.declare dominates alloca. -define i32 @f2(i32 %i) nounwind ssp { -entry: - call void @llvm.dbg.declare(metadata !{i32* %i.addr}, metadata !20), !dbg !21 - %i.addr = alloca i32, align 4 - store i32 %i, i32* %i.addr, align 4 - %tmp = load i32* %i.addr, align 4, !dbg !22 - ret i32 %tmp, !dbg !22 -} - -; Check handling of an argument referred directly by llvm.dbg.declare where at least -; one argument use dominates llvm.dbg.declare. -define i32 @f3(i32 %i) nounwind ssp { -entry: - %i.addr = alloca i32, align 4 - store i32 %i, i32* %i.addr, align 4 - call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !24), !dbg !25 - %tmp = load i32* %i.addr, align 4, !dbg !26 - ret i32 %tmp, !dbg !26 -} - -; Check handling of an argument referred directly by llvm.dbg.declare where -; llvm.dbg.declare dominates all uses of argument. -define i32 @f4(i32 %i) nounwind ssp { -entry: - call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !28), !dbg !29 - ret i32 %i, !dbg !30 -} - -; Check handling of an argument referred directly by llvm.dbg.declare where -; llvm.dbg.declare dominates all uses of argument in separate basic block. -define i32 @f5(i32 %i) nounwind ssp { -entry: - call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !32), !dbg !33 - br label %bbr -bbr: - ret i32 %i, !dbg !34 -} - -; Check handling of an argument referred directly by llvm.dbg.declare where -; argument is not used. -define i32 @f6(i32 %i) nounwind ssp { -entry: - call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !36), !dbg !37 - ret i32 1, !dbg !38 -} - -; Check handling of an byval argument referred directly by llvm.dbg.declare where -; argument is not used. -define i32 @f7(%struct.XYZ* byval %i) nounwind ssp { -entry: - call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !40), !dbg !48 - ret i32 1, !dbg !49 -} - -; Check handling of an byval argument referred directly by llvm.dbg.declare where -; argument use dominates llvm.dbg.declare. -define i32 @f8(%struct.XYZ* byval %i) nounwind ssp { -entry: - %tmp = getelementptr inbounds %struct.XYZ* %i, i32 0, i32 1, !dbg !53 - %tmp1 = load i32* %tmp, align 4, !dbg !53 - call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !51), !dbg !52 - ret i32 %tmp1, !dbg !53 -} - -; Check handling of an byval argument referred directly by llvm.dbg.declare where -; llvm.dbg.declare dominates all uses of argument. -define i32 @f9(%struct.XYZ* byval %i) nounwind ssp { -entry: - call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !55), !dbg !56 - %tmp = getelementptr inbounds %struct.XYZ* %i, i32 0, i32 2, !dbg !57 - %tmp1 = load i32* %tmp, align 4, !dbg !57 - ret i32 %tmp1, !dbg !57 -} - -; Check handling of an byval argument referred directly by llvm.dbg.declare where -; llvm.dbg.declare dominates all uses of argument in separate basic block. -define i32 @f10(%struct.XYZ* byval %i) nounwind ssp { -entry: - call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !59), !dbg !60 - br label %bbr -bbr: - %tmp = getelementptr inbounds %struct.XYZ* %i, i32 0, i32 3, !dbg !61 - %tmp1 = load i32* %tmp, align 4, !dbg !61 - ret i32 %tmp1, !dbg !61 -} - -define i32 @main() nounwind ssp { -entry: - %retval = alloca i32, align 4 - %abc = alloca %struct.XYZ, align 4 - %agg.tmp = alloca %struct.XYZ, align 4 - %agg.tmp13 = alloca %struct.XYZ, align 4 - %agg.tmp17 = alloca %struct.XYZ, align 4 - %agg.tmp21 = alloca %struct.XYZ, align 4 - store i32 0, i32* %retval - %call = call i32 @f1(i32 42), !dbg !63 - %call1 = call i32 @f2(i32 43), !dbg !65 - %call2 = call i32 @f3(i32 44), !dbg !66 - %call3 = call i32 @f4(i32 45), !dbg !67 - %call4 = call i32 @f5(i32 46), !dbg !68 - %call5 = call i32 @f6(i32 47), !dbg !69 - call void @llvm.dbg.declare(metadata !{%struct.XYZ* %abc}, metadata !70), !dbg !71 - %tmp = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 0, !dbg !72 - store i32 51, i32* %tmp, align 4, !dbg !72 - %tmp6 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 1, !dbg !72 - store i32 52, i32* %tmp6, align 4, !dbg !72 - %tmp7 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 2, !dbg !72 - store i32 53, i32* %tmp7, align 4, !dbg !72 - %tmp8 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 3, !dbg !72 - store i32 54, i32* %tmp8, align 4, !dbg !72 - %tmp9 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 4, !dbg !72 - store i32 55, i32* %tmp9, align 4, !dbg !72 - %tmp10 = bitcast %struct.XYZ* %agg.tmp to i8*, !dbg !73 - %tmp11 = bitcast %struct.XYZ* %abc to i8*, !dbg !73 - call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp10, i8* %tmp11, i64 20, i32 4, i1 false), !dbg !73 - %call12 = call i32 @f7(%struct.XYZ* byval %agg.tmp), !dbg !73 - %tmp14 = bitcast %struct.XYZ* %agg.tmp13 to i8*, !dbg !74 - %tmp15 = bitcast %struct.XYZ* %abc to i8*, !dbg !74 - call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp14, i8* %tmp15, i64 20, i32 4, i1 false), !dbg !74 - %call16 = call i32 @f8(%struct.XYZ* byval %agg.tmp13), !dbg !74 - %tmp18 = bitcast %struct.XYZ* %agg.tmp17 to i8*, !dbg !75 - %tmp19 = bitcast %struct.XYZ* %abc to i8*, !dbg !75 - call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp18, i8* %tmp19, i64 20, i32 4, i1 false), !dbg !75 - %call20 = call i32 @f9(%struct.XYZ* byval %agg.tmp17), !dbg !75 - %tmp22 = bitcast %struct.XYZ* %agg.tmp21 to i8*, !dbg !76 - %tmp23 = bitcast %struct.XYZ* %abc to i8*, !dbg !76 - call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp22, i8* %tmp23, i64 20, i32 4, i1 false), !dbg !76 - %call24 = call i32 @f10(%struct.XYZ* byval %agg.tmp21), !dbg !76 - ret i32 0, !dbg !77 -} - -declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind - -!llvm.dbg.sp = !{!0, !6, !7, !8, !9, !10, !11, !12, !13, !14, !15} - -!0 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f1", metadata !"f1", metadata !"f1", metadata !1, i32 11, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f1} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 524329, metadata !"/Users/manav/dbg_info_bugs/fastisel_arg.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 524305, i32 0, i32 12, metadata !"/Users/manav/dbg_info_bugs/fastisel_arg.c", metadata !"/private/tmp", metadata !"clang version 2.8 (trunk 112967)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!3 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] -!4 = metadata !{metadata !5} -!5 = metadata !{i32 524324, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f2", metadata !"f2", metadata !"f2", metadata !1, i32 12, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f2} ; [ DW_TAG_subprogram ] -!7 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f3", metadata !"f3", metadata !"f3", metadata !1, i32 13, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f3} ; [ DW_TAG_subprogram ] -!8 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f4", metadata !"f4", metadata !"f4", metadata !1, i32 14, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f4} ; [ DW_TAG_subprogram ] -!9 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f5", metadata !"f5", metadata !"f5", metadata !1, i32 15, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f5} ; [ DW_TAG_subprogram ] -!10 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f6", metadata !"f6", metadata !"f6", metadata !1, i32 16, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f6} ; [ DW_TAG_subprogram ] -!11 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f7", metadata !"f7", metadata !"f7", metadata !1, i32 17, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f7} ; [ DW_TAG_subprogram ] -!12 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f8", metadata !"f8", metadata !"f8", metadata !1, i32 18, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f8} ; [ DW_TAG_subprogram ] -!13 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f9", metadata !"f9", metadata !"f9", metadata !1, i32 19, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f9} ; [ DW_TAG_subprogram ] -!14 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f10", metadata !"f10", metadata !"f10", metadata !1, i32 20, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f10} ; [ DW_TAG_subprogram ] -!15 = metadata !{i32 524334, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"main", metadata !1, i32 23, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @main} ; [ DW_TAG_subprogram ] -!16 = metadata !{i32 524545, metadata !0, metadata !"i", metadata !1, i32 11, metadata !5} ; [ DW_TAG_arg_variable ] -!17 = metadata !{i32 11, i32 12, metadata !0, null} -!18 = metadata !{i32 11, i32 17, metadata !19, null} -!19 = metadata !{i32 524299, metadata !0, i32 11, i32 15, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] -!20 = metadata !{i32 524545, metadata !6, metadata !"i", metadata !1, i32 12, metadata !5} ; [ DW_TAG_arg_variable ] -!21 = metadata !{i32 12, i32 12, metadata !6, null} -!22 = metadata !{i32 12, i32 17, metadata !23, null} -!23 = metadata !{i32 524299, metadata !6, i32 12, i32 15, metadata !1, i32 1} ; [ DW_TAG_lexical_block ] -!24 = metadata !{i32 524545, metadata !7, metadata !"i", metadata !1, i32 13, metadata !5} ; [ DW_TAG_arg_variable ] -!25 = metadata !{i32 13, i32 12, metadata !7, null} -!26 = metadata !{i32 13, i32 17, metadata !27, null} -!27 = metadata !{i32 524299, metadata !7, i32 13, i32 15, metadata !1, i32 2} ; [ DW_TAG_lexical_block ] -!28 = metadata !{i32 524545, metadata !8, metadata !"i", metadata !1, i32 14, metadata !5} ; [ DW_TAG_arg_variable ] -!29 = metadata !{i32 14, i32 12, metadata !8, null} -!30 = metadata !{i32 14, i32 17, metadata !31, null} -!31 = metadata !{i32 524299, metadata !8, i32 14, i32 15, metadata !1, i32 3} ; [ DW_TAG_lexical_block ] -!32 = metadata !{i32 524545, metadata !9, metadata !"i", metadata !1, i32 15, metadata !5} ; [ DW_TAG_arg_variable ] -!33 = metadata !{i32 15, i32 12, metadata !9, null} -!34 = metadata !{i32 15, i32 17, metadata !35, null} -!35 = metadata !{i32 524299, metadata !9, i32 15, i32 15, metadata !1, i32 4} ; [ DW_TAG_lexical_block ] -!36 = metadata !{i32 524545, metadata !10, metadata !"i", metadata !1, i32 16, metadata !5} ; [ DW_TAG_arg_variable ] -!37 = metadata !{i32 16, i32 12, metadata !10, null} -!38 = metadata !{i32 16, i32 17, metadata !39, null} -!39 = metadata !{i32 524299, metadata !10, i32 16, i32 15, metadata !1, i32 5} ; [ DW_TAG_lexical_block ] -!40 = metadata !{i32 524545, metadata !11, metadata !"i", metadata !1, i32 17, metadata !41} ; [ DW_TAG_arg_variable ] -!41 = metadata !{i32 524307, metadata !1, metadata !"XYZ", metadata !1, i32 2, i64 160, i64 32, i64 0, i32 0, null, metadata !42, i32 0, null} ; [ DW_TAG_structure_type ] -!42 = metadata !{metadata !43, metadata !44, metadata !45, metadata !46, metadata !47} -!43 = metadata !{i32 524301, metadata !1, metadata !"x", metadata !1, i32 3, i64 32, i64 32, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] -!44 = metadata !{i32 524301, metadata !1, metadata !"y", metadata !1, i32 4, i64 32, i64 32, i64 32, i32 0, metadata !5} ; [ DW_TAG_member ] -!45 = metadata !{i32 524301, metadata !1, metadata !"z", metadata !1, i32 5, i64 32, i64 32, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] -!46 = metadata !{i32 524301, metadata !1, metadata !"a", metadata !1, i32 6, i64 32, i64 32, i64 96, i32 0, metadata !5} ; [ DW_TAG_member ] -!47 = metadata !{i32 524301, metadata !1, metadata !"b", metadata !1, i32 7, i64 32, i64 32, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] -!48 = metadata !{i32 17, i32 19, metadata !11, null} -!49 = metadata !{i32 17, i32 24, metadata !50, null} -!50 = metadata !{i32 524299, metadata !11, i32 17, i32 22, metadata !1, i32 6} ; [ DW_TAG_lexical_block ] -!51 = metadata !{i32 524545, metadata !12, metadata !"i", metadata !1, i32 18, metadata !41} ; [ DW_TAG_arg_variable ] -!52 = metadata !{i32 18, i32 19, metadata !12, null} -!53 = metadata !{i32 18, i32 24, metadata !54, null} -!54 = metadata !{i32 524299, metadata !12, i32 18, i32 22, metadata !1, i32 7} ; [ DW_TAG_lexical_block ] -!55 = metadata !{i32 524545, metadata !13, metadata !"i", metadata !1, i32 19, metadata !41} ; [ DW_TAG_arg_variable ] -!56 = metadata !{i32 19, i32 19, metadata !13, null} -!57 = metadata !{i32 19, i32 24, metadata !58, null} -!58 = metadata !{i32 524299, metadata !13, i32 19, i32 22, metadata !1, i32 8} ; [ DW_TAG_lexical_block ] -!59 = metadata !{i32 524545, metadata !14, metadata !"i", metadata !1, i32 20, metadata !41} ; [ DW_TAG_arg_variable ] -!60 = metadata !{i32 20, i32 20, metadata !14, null} -!61 = metadata !{i32 20, i32 25, metadata !62, null} -!62 = metadata !{i32 524299, metadata !14, i32 20, i32 23, metadata !1, i32 9} ; [ DW_TAG_lexical_block ] -!63 = metadata !{i32 24, i32 3, metadata !64, null} -!64 = metadata !{i32 524299, metadata !15, i32 23, i32 12, metadata !1, i32 10} ; [ DW_TAG_lexical_block ] -!65 = metadata !{i32 25, i32 3, metadata !64, null} -!66 = metadata !{i32 26, i32 3, metadata !64, null} -!67 = metadata !{i32 27, i32 3, metadata !64, null} -!68 = metadata !{i32 28, i32 3, metadata !64, null} -!69 = metadata !{i32 29, i32 3, metadata !64, null} -!70 = metadata !{i32 524544, metadata !64, metadata !"abc", metadata !1, i32 30, metadata !41} ; [ DW_TAG_auto_variable ] -!71 = metadata !{i32 30, i32 14, metadata !64, null} -!72 = metadata !{i32 30, i32 17, metadata !64, null} -!73 = metadata !{i32 31, i32 3, metadata !64, null} -!74 = metadata !{i32 32, i32 3, metadata !64, null} -!75 = metadata !{i32 33, i32 3, metadata !64, null} -!76 = metadata !{i32 34, i32 3, metadata !64, null} -!77 = metadata !{i32 36, i32 3, metadata !64, null} Removed: llvm/trunk/test/CodeGen/X86/dbg-declare2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-declare2.ll?rev=113212&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/dbg-declare2.ll (original) +++ llvm/trunk/test/CodeGen/X86/dbg-declare2.ll (removed) @@ -1,244 +0,0 @@ -; This test case checks handling of llvm.dbg.declare intrinsic during isel. -; RUN: llc --disable-fp-elim -O0 -fast-isel=false %s -o %t.s -; RUN: %compile_c %t.s -o %t.o -; RUN: %link %t.o -o %t.exe -; RUN: echo {break f1\n break f2 \n break f7 \n break f8 \n break f9 \n break f10 \n run \n p i\n c \n p i\n c \n p i.x\n c \n p i.x\n c \n p i.x \n c \n p i.x \n} > %t.in -; RUN: gdb -q -batch -n -x %t.in %t.exe > %t.out -; RUN: grep "1 = 42" %t.out -; RUN: grep "2 = 43" %t.out -; RUN: grep "3 = 51" %t.out -; RUN: grep "4 = 51" %t.out -; RUN: grep "5 = 51" %t.out -; RUN: grep "6 = 51" %t.out - -target triple = "x86_64-apple-darwin" -%struct.XYZ = type { i32, i32, i32, i32, i32 } - -; Check handling of llvm.dbg.declare for an argument referred through alloca, where -; alloca dominates llvm.dbg.declare -define i32 @f1(i32 %i) nounwind ssp { -entry: - %i.addr = alloca i32, align 4 - store i32 %i, i32* %i.addr, align 4 - call void @llvm.dbg.declare(metadata !{i32* %i.addr}, metadata !16), !dbg !17 - %tmp = load i32* %i.addr, align 4, !dbg !18 - ret i32 %tmp, !dbg !18 -} - -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone - -; Check handling of llvm.dbg.declare for an argument referred through alloca, where -; llvm.dbg.declare dominates alloca. -define i32 @f2(i32 %i) nounwind ssp { -entry: - call void @llvm.dbg.declare(metadata !{i32* %i.addr}, metadata !20), !dbg !21 - %i.addr = alloca i32, align 4 - store i32 %i, i32* %i.addr, align 4 - %tmp = load i32* %i.addr, align 4, !dbg !22 - ret i32 %tmp, !dbg !22 -} - -; Check handling of an argument referred directly by llvm.dbg.declare where at least -; one argument use dominates llvm.dbg.declare. -define i32 @f3(i32 %i) nounwind ssp { -entry: - %i.addr = alloca i32, align 4 - store i32 %i, i32* %i.addr, align 4 - call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !24), !dbg !25 - %tmp = load i32* %i.addr, align 4, !dbg !26 - ret i32 %tmp, !dbg !26 -} - -; Check handling of an argument referred directly by llvm.dbg.declare where -; llvm.dbg.declare dominates all uses of argument. -define i32 @f4(i32 %i) nounwind ssp { -entry: - call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !28), !dbg !29 - ret i32 %i, !dbg !30 -} - -; Check handling of an argument referred directly by llvm.dbg.declare where -; llvm.dbg.declare dominates all uses of argument in separate basic block. -define i32 @f5(i32 %i) nounwind ssp { -entry: - call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !32), !dbg !33 - br label %bbr -bbr: - ret i32 %i, !dbg !34 -} - -; Check handling of an argument referred directly by llvm.dbg.declare where -; argument is not used. -define i32 @f6(i32 %i) nounwind ssp { -entry: - call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !36), !dbg !37 - ret i32 1, !dbg !38 -} - -; Check handling of an byval argument referred directly by llvm.dbg.declare where -; argument is not used. -define i32 @f7(%struct.XYZ* byval %i) nounwind ssp { -entry: - call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !40), !dbg !48 - ret i32 1, !dbg !49 -} - -; Check handling of an byval argument referred directly by llvm.dbg.declare where -; argument use dominates llvm.dbg.declare. -define i32 @f8(%struct.XYZ* byval %i) nounwind ssp { -entry: - %tmp = getelementptr inbounds %struct.XYZ* %i, i32 0, i32 1, !dbg !53 - %tmp1 = load i32* %tmp, align 4, !dbg !53 - call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !51), !dbg !52 - ret i32 %tmp1, !dbg !53 -} - -; Check handling of an byval argument referred directly by llvm.dbg.declare where -; llvm.dbg.declare dominates all uses of argument. -define i32 @f9(%struct.XYZ* byval %i) nounwind ssp { -entry: - call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !55), !dbg !56 - %tmp = getelementptr inbounds %struct.XYZ* %i, i32 0, i32 2, !dbg !57 - %tmp1 = load i32* %tmp, align 4, !dbg !57 - ret i32 %tmp1, !dbg !57 -} - -; Check handling of an byval argument referred directly by llvm.dbg.declare where -; llvm.dbg.declare dominates all uses of argument in separate basic block. -define i32 @f10(%struct.XYZ* byval %i) nounwind ssp { -entry: - call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !59), !dbg !60 - br label %bbr -bbr: - %tmp = getelementptr inbounds %struct.XYZ* %i, i32 0, i32 3, !dbg !61 - %tmp1 = load i32* %tmp, align 4, !dbg !61 - ret i32 %tmp1, !dbg !61 -} - -define i32 @main() nounwind ssp { -entry: - %retval = alloca i32, align 4 - %abc = alloca %struct.XYZ, align 4 - %agg.tmp = alloca %struct.XYZ, align 4 - %agg.tmp13 = alloca %struct.XYZ, align 4 - %agg.tmp17 = alloca %struct.XYZ, align 4 - %agg.tmp21 = alloca %struct.XYZ, align 4 - store i32 0, i32* %retval - %call = call i32 @f1(i32 42), !dbg !63 - %call1 = call i32 @f2(i32 43), !dbg !65 - %call2 = call i32 @f3(i32 44), !dbg !66 - %call3 = call i32 @f4(i32 45), !dbg !67 - %call4 = call i32 @f5(i32 46), !dbg !68 - %call5 = call i32 @f6(i32 47), !dbg !69 - call void @llvm.dbg.declare(metadata !{%struct.XYZ* %abc}, metadata !70), !dbg !71 - %tmp = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 0, !dbg !72 - store i32 51, i32* %tmp, align 4, !dbg !72 - %tmp6 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 1, !dbg !72 - store i32 52, i32* %tmp6, align 4, !dbg !72 - %tmp7 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 2, !dbg !72 - store i32 53, i32* %tmp7, align 4, !dbg !72 - %tmp8 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 3, !dbg !72 - store i32 54, i32* %tmp8, align 4, !dbg !72 - %tmp9 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 4, !dbg !72 - store i32 55, i32* %tmp9, align 4, !dbg !72 - %tmp10 = bitcast %struct.XYZ* %agg.tmp to i8*, !dbg !73 - %tmp11 = bitcast %struct.XYZ* %abc to i8*, !dbg !73 - call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp10, i8* %tmp11, i64 20, i32 4, i1 false), !dbg !73 - %call12 = call i32 @f7(%struct.XYZ* byval %agg.tmp), !dbg !73 - %tmp14 = bitcast %struct.XYZ* %agg.tmp13 to i8*, !dbg !74 - %tmp15 = bitcast %struct.XYZ* %abc to i8*, !dbg !74 - call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp14, i8* %tmp15, i64 20, i32 4, i1 false), !dbg !74 - %call16 = call i32 @f8(%struct.XYZ* byval %agg.tmp13), !dbg !74 - %tmp18 = bitcast %struct.XYZ* %agg.tmp17 to i8*, !dbg !75 - %tmp19 = bitcast %struct.XYZ* %abc to i8*, !dbg !75 - call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp18, i8* %tmp19, i64 20, i32 4, i1 false), !dbg !75 - %call20 = call i32 @f9(%struct.XYZ* byval %agg.tmp17), !dbg !75 - %tmp22 = bitcast %struct.XYZ* %agg.tmp21 to i8*, !dbg !76 - %tmp23 = bitcast %struct.XYZ* %abc to i8*, !dbg !76 - call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp22, i8* %tmp23, i64 20, i32 4, i1 false), !dbg !76 - %call24 = call i32 @f10(%struct.XYZ* byval %agg.tmp21), !dbg !76 - ret i32 0, !dbg !77 -} - -declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind - -!llvm.dbg.sp = !{!0, !6, !7, !8, !9, !10, !11, !12, !13, !14, !15} - -!0 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f1", metadata !"f1", metadata !"f1", metadata !1, i32 11, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f1} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 524329, metadata !"/Users/manav/dbg_info_bugs/fastisel_arg.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 524305, i32 0, i32 12, metadata !"/Users/manav/dbg_info_bugs/fastisel_arg.c", metadata !"/private/tmp", metadata !"clang version 2.8 (trunk 112967)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!3 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] -!4 = metadata !{metadata !5} -!5 = metadata !{i32 524324, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f2", metadata !"f2", metadata !"f2", metadata !1, i32 12, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f2} ; [ DW_TAG_subprogram ] -!7 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f3", metadata !"f3", metadata !"f3", metadata !1, i32 13, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f3} ; [ DW_TAG_subprogram ] -!8 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f4", metadata !"f4", metadata !"f4", metadata !1, i32 14, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f4} ; [ DW_TAG_subprogram ] -!9 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f5", metadata !"f5", metadata !"f5", metadata !1, i32 15, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f5} ; [ DW_TAG_subprogram ] -!10 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f6", metadata !"f6", metadata !"f6", metadata !1, i32 16, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f6} ; [ DW_TAG_subprogram ] -!11 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f7", metadata !"f7", metadata !"f7", metadata !1, i32 17, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f7} ; [ DW_TAG_subprogram ] -!12 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f8", metadata !"f8", metadata !"f8", metadata !1, i32 18, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f8} ; [ DW_TAG_subprogram ] -!13 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f9", metadata !"f9", metadata !"f9", metadata !1, i32 19, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f9} ; [ DW_TAG_subprogram ] -!14 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f10", metadata !"f10", metadata !"f10", metadata !1, i32 20, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f10} ; [ DW_TAG_subprogram ] -!15 = metadata !{i32 524334, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"main", metadata !1, i32 23, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @main} ; [ DW_TAG_subprogram ] -!16 = metadata !{i32 524545, metadata !0, metadata !"i", metadata !1, i32 11, metadata !5} ; [ DW_TAG_arg_variable ] -!17 = metadata !{i32 11, i32 12, metadata !0, null} -!18 = metadata !{i32 11, i32 17, metadata !19, null} -!19 = metadata !{i32 524299, metadata !0, i32 11, i32 15, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] -!20 = metadata !{i32 524545, metadata !6, metadata !"i", metadata !1, i32 12, metadata !5} ; [ DW_TAG_arg_variable ] -!21 = metadata !{i32 12, i32 12, metadata !6, null} -!22 = metadata !{i32 12, i32 17, metadata !23, null} -!23 = metadata !{i32 524299, metadata !6, i32 12, i32 15, metadata !1, i32 1} ; [ DW_TAG_lexical_block ] -!24 = metadata !{i32 524545, metadata !7, metadata !"i", metadata !1, i32 13, metadata !5} ; [ DW_TAG_arg_variable ] -!25 = metadata !{i32 13, i32 12, metadata !7, null} -!26 = metadata !{i32 13, i32 17, metadata !27, null} -!27 = metadata !{i32 524299, metadata !7, i32 13, i32 15, metadata !1, i32 2} ; [ DW_TAG_lexical_block ] -!28 = metadata !{i32 524545, metadata !8, metadata !"i", metadata !1, i32 14, metadata !5} ; [ DW_TAG_arg_variable ] -!29 = metadata !{i32 14, i32 12, metadata !8, null} -!30 = metadata !{i32 14, i32 17, metadata !31, null} -!31 = metadata !{i32 524299, metadata !8, i32 14, i32 15, metadata !1, i32 3} ; [ DW_TAG_lexical_block ] -!32 = metadata !{i32 524545, metadata !9, metadata !"i", metadata !1, i32 15, metadata !5} ; [ DW_TAG_arg_variable ] -!33 = metadata !{i32 15, i32 12, metadata !9, null} -!34 = metadata !{i32 15, i32 17, metadata !35, null} -!35 = metadata !{i32 524299, metadata !9, i32 15, i32 15, metadata !1, i32 4} ; [ DW_TAG_lexical_block ] -!36 = metadata !{i32 524545, metadata !10, metadata !"i", metadata !1, i32 16, metadata !5} ; [ DW_TAG_arg_variable ] -!37 = metadata !{i32 16, i32 12, metadata !10, null} -!38 = metadata !{i32 16, i32 17, metadata !39, null} -!39 = metadata !{i32 524299, metadata !10, i32 16, i32 15, metadata !1, i32 5} ; [ DW_TAG_lexical_block ] -!40 = metadata !{i32 524545, metadata !11, metadata !"i", metadata !1, i32 17, metadata !41} ; [ DW_TAG_arg_variable ] -!41 = metadata !{i32 524307, metadata !1, metadata !"XYZ", metadata !1, i32 2, i64 160, i64 32, i64 0, i32 0, null, metadata !42, i32 0, null} ; [ DW_TAG_structure_type ] -!42 = metadata !{metadata !43, metadata !44, metadata !45, metadata !46, metadata !47} -!43 = metadata !{i32 524301, metadata !1, metadata !"x", metadata !1, i32 3, i64 32, i64 32, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] -!44 = metadata !{i32 524301, metadata !1, metadata !"y", metadata !1, i32 4, i64 32, i64 32, i64 32, i32 0, metadata !5} ; [ DW_TAG_member ] -!45 = metadata !{i32 524301, metadata !1, metadata !"z", metadata !1, i32 5, i64 32, i64 32, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] -!46 = metadata !{i32 524301, metadata !1, metadata !"a", metadata !1, i32 6, i64 32, i64 32, i64 96, i32 0, metadata !5} ; [ DW_TAG_member ] -!47 = metadata !{i32 524301, metadata !1, metadata !"b", metadata !1, i32 7, i64 32, i64 32, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] -!48 = metadata !{i32 17, i32 19, metadata !11, null} -!49 = metadata !{i32 17, i32 24, metadata !50, null} -!50 = metadata !{i32 524299, metadata !11, i32 17, i32 22, metadata !1, i32 6} ; [ DW_TAG_lexical_block ] -!51 = metadata !{i32 524545, metadata !12, metadata !"i", metadata !1, i32 18, metadata !41} ; [ DW_TAG_arg_variable ] -!52 = metadata !{i32 18, i32 19, metadata !12, null} -!53 = metadata !{i32 18, i32 24, metadata !54, null} -!54 = metadata !{i32 524299, metadata !12, i32 18, i32 22, metadata !1, i32 7} ; [ DW_TAG_lexical_block ] -!55 = metadata !{i32 524545, metadata !13, metadata !"i", metadata !1, i32 19, metadata !41} ; [ DW_TAG_arg_variable ] -!56 = metadata !{i32 19, i32 19, metadata !13, null} -!57 = metadata !{i32 19, i32 24, metadata !58, null} -!58 = metadata !{i32 524299, metadata !13, i32 19, i32 22, metadata !1, i32 8} ; [ DW_TAG_lexical_block ] -!59 = metadata !{i32 524545, metadata !14, metadata !"i", metadata !1, i32 20, metadata !41} ; [ DW_TAG_arg_variable ] -!60 = metadata !{i32 20, i32 20, metadata !14, null} -!61 = metadata !{i32 20, i32 25, metadata !62, null} -!62 = metadata !{i32 524299, metadata !14, i32 20, i32 23, metadata !1, i32 9} ; [ DW_TAG_lexical_block ] -!63 = metadata !{i32 24, i32 3, metadata !64, null} -!64 = metadata !{i32 524299, metadata !15, i32 23, i32 12, metadata !1, i32 10} ; [ DW_TAG_lexical_block ] -!65 = metadata !{i32 25, i32 3, metadata !64, null} -!66 = metadata !{i32 26, i32 3, metadata !64, null} -!67 = metadata !{i32 27, i32 3, metadata !64, null} -!68 = metadata !{i32 28, i32 3, metadata !64, null} -!69 = metadata !{i32 29, i32 3, metadata !64, null} -!70 = metadata !{i32 524544, metadata !64, metadata !"abc", metadata !1, i32 30, metadata !41} ; [ DW_TAG_auto_variable ] -!71 = metadata !{i32 30, i32 14, metadata !64, null} -!72 = metadata !{i32 30, i32 17, metadata !64, null} -!73 = metadata !{i32 31, i32 3, metadata !64, null} -!74 = metadata !{i32 32, i32 3, metadata !64, null} -!75 = metadata !{i32 33, i32 3, metadata !64, null} -!76 = metadata !{i32 34, i32 3, metadata !64, null} -!77 = metadata !{i32 36, i32 3, metadata !64, null} Removed: llvm/trunk/test/CodeGen/X86/dbg-declare3.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-declare3.ll?rev=113212&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/dbg-declare3.ll (original) +++ llvm/trunk/test/CodeGen/X86/dbg-declare3.ll (removed) @@ -1,266 +0,0 @@ -; This test case checks handling of llvm.dbg.declare intrinsic during hybrid mode where we begin -; using fast-isel but switch back to DAG building at some point. -; RUN: llc --disable-fp-elim -O0 %s -o %t.s -; RUN: %compile_c %t.s -o %t.o -; RUN: %link %t.o -o %t.exe -; RUN: echo {break f1\n break f4\n break f5\n run \n p i\n c \n p i\n c \n p i\n} > %t.in -; RUN: gdb -q -batch -n -x %t.in %t.exe > %t.out -; RUN: grep "1 = 42" %t.out -; RUN: grep "2 = 45" %t.out -; RUN: grep "3 = 46" %t.out - -target triple = "x86_64-apple-darwin" -%struct.XYZ = type { i32, i32, i32, i32, i32 } -%0 = type { i64, i32 } -define %0 @foobar() { - ret i64 6, i32 7 -} - -; Check handling of llvm.dbg.declare for an argument referred through alloca, where -; alloca dominates llvm.dbg.declare -define i32 @f1(i32 %i) nounwind ssp { -entry: - %i.addr = alloca i32, align 4 - store i32 %i, i32* %i.addr, align 4 - %call = call %0 @foobar() - call void @llvm.dbg.declare(metadata !{i32* %i.addr}, metadata !16), !dbg !17 - %call2 = call %0 @foobar() - %tmp = load i32* %i.addr, align 4, !dbg !18 - ret i32 %tmp, !dbg !18 -} - -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone - -; Check handling of llvm.dbg.declare for an argument referred through alloca, where -; llvm.dbg.declare dominates alloca. -define i32 @f2(i32 %i) nounwind ssp { -entry: - %call = call %0 @foobar() - call void @llvm.dbg.declare(metadata !{i32* %i.addr}, metadata !20), !dbg !21 - %call2 = call %0 @foobar() - %i.addr = alloca i32, align 4 - store i32 %i, i32* %i.addr, align 4 - %tmp = load i32* %i.addr, align 4, !dbg !22 - ret i32 %tmp, !dbg !22 -} - -; Check handling of an argument referred directly by llvm.dbg.declare where at least -; one argument use dominates llvm.dbg.declare. -define i32 @f3(i32 %i) nounwind ssp { -entry: - %i.addr = alloca i32, align 4 - store i32 %i, i32* %i.addr, align 4 - %call = call %0 @foobar() - call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !24), !dbg !2 - %call2 = call %0 @foobar() - %tmp = load i32* %i.addr, align 4, !dbg !26 - ret i32 %tmp, !dbg !26 -} - -; Check handling of an argument referred directly by llvm.dbg.declare where -; llvm.dbg.declare dominates all uses of argument. -define i32 @f4(i32 %i) nounwind ssp { -entry: - %call = call %0 @foobar() - call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !28), !dbg !29 - %call2 = call %0 @foobar() - ret i32 %i, !dbg !30 -} - -; Check handling of an argument referred directly by llvm.dbg.declare where -; llvm.dbg.declare dominates all uses of argument in separate basic block. -define i32 @f5(i32 %i) nounwind ssp { -entry: - %call = call %0 @foobar() - call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !32), !dbg !33 - %call2 = call %0 @foobar() - br label %bbr -bbr: - ret i32 %i, !dbg !34 -} - -; Check handling of an argument referred directly by llvm.dbg.declare where -; argument is not used. -define i32 @f6(i32 %i) nounwind ssp { -entry: - %call = call %0 @foobar() - call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !36), !dbg !37 - %call2 = call %0 @foobar() - ret i32 1, !dbg !38 -} - -; Check handling of an byval argument referred directly by llvm.dbg.declare where -; argument is not used. -define i32 @f7(%struct.XYZ* byval %i) nounwind ssp { -entry: - %call = call %0 @foobar() - call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !40), !dbg !48 - %call2 = call %0 @foobar() - ret i32 1, !dbg !49 -} - -; Check handling of an byval argument referred directly by llvm.dbg.declare where -; argument use dominates llvm.dbg.declare. -define i32 @f8(%struct.XYZ* byval %i) nounwind ssp { -entry: - %tmp = getelementptr inbounds %struct.XYZ* %i, i32 0, i32 1, !dbg !53 - %tmp1 = load i32* %tmp, align 4, !dbg !53 - %call = call %0 @foobar() - call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !51), !dbg !52 - %call2 = call %0 @foobar() - ret i32 %tmp1, !dbg !53 -} - -; Check handling of an byval argument referred directly by llvm.dbg.declare where -; llvm.dbg.declare dominates all uses of argument. -define i32 @f9(%struct.XYZ* byval %i) nounwind ssp { -entry: - %call = call %0 @foobar() - call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !55), !dbg !56 - %call2 = call %0 @foobar() - %tmp = getelementptr inbounds %struct.XYZ* %i, i32 0, i32 2, !dbg !57 - %tmp1 = load i32* %tmp, align 4, !dbg !57 - ret i32 %tmp1, !dbg !57 -} - -; Check handling of an byval argument referred directly by llvm.dbg.declare where -; llvm.dbg.declare dominates all uses of argument in separate basic block. -define i32 @f10(%struct.XYZ* byval %i) nounwind ssp { -entry: - %call = call %0 @foobar() - call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !59), !dbg !60 - %call2 = call %0 @foobar() - br label %bbr -bbr: - %tmp = getelementptr inbounds %struct.XYZ* %i, i32 0, i32 3, !dbg !61 - %tmp1 = load i32* %tmp, align 4, !dbg !61 - ret i32 %tmp1, !dbg !61 -} - -define i32 @main() nounwind ssp { -entry: - %retval = alloca i32, align 4 - %abc = alloca %struct.XYZ, align 4 - %agg.tmp = alloca %struct.XYZ, align 4 - %agg.tmp13 = alloca %struct.XYZ, align 4 - %agg.tmp17 = alloca %struct.XYZ, align 4 - %agg.tmp21 = alloca %struct.XYZ, align 4 - store i32 0, i32* %retval - %call = call i32 @f1(i32 42), !dbg !63 - %call1 = call i32 @f2(i32 43), !dbg !65 - %call2 = call i32 @f3(i32 44), !dbg !66 - %call3 = call i32 @f4(i32 45), !dbg !67 - %call4 = call i32 @f5(i32 46), !dbg !68 - %call5 = call i32 @f6(i32 47), !dbg !69 - call void @llvm.dbg.declare(metadata !{%struct.XYZ* %abc}, metadata !70), !dbg !71 - %tmp = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 0, !dbg !72 - store i32 51, i32* %tmp, align 4, !dbg !72 - %tmp6 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 1, !dbg !72 - store i32 52, i32* %tmp6, align 4, !dbg !72 - %tmp7 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 2, !dbg !72 - store i32 53, i32* %tmp7, align 4, !dbg !72 - %tmp8 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 3, !dbg !72 - store i32 54, i32* %tmp8, align 4, !dbg !72 - %tmp9 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 4, !dbg !72 - store i32 55, i32* %tmp9, align 4, !dbg !72 - %tmp10 = bitcast %struct.XYZ* %agg.tmp to i8*, !dbg !73 - %tmp11 = bitcast %struct.XYZ* %abc to i8*, !dbg !73 - call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp10, i8* %tmp11, i64 20, i32 4, i1 false), !dbg !73 - %call12 = call i32 @f7(%struct.XYZ* byval %agg.tmp), !dbg !73 - %tmp14 = bitcast %struct.XYZ* %agg.tmp13 to i8*, !dbg !74 - %tmp15 = bitcast %struct.XYZ* %abc to i8*, !dbg !74 - call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp14, i8* %tmp15, i64 20, i32 4, i1 false), !dbg !74 - %call16 = call i32 @f8(%struct.XYZ* byval %agg.tmp13), !dbg !74 - %tmp18 = bitcast %struct.XYZ* %agg.tmp17 to i8*, !dbg !75 - %tmp19 = bitcast %struct.XYZ* %abc to i8*, !dbg !75 - call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp18, i8* %tmp19, i64 20, i32 4, i1 false), !dbg !75 - %call20 = call i32 @f9(%struct.XYZ* byval %agg.tmp17), !dbg !75 - %tmp22 = bitcast %struct.XYZ* %agg.tmp21 to i8*, !dbg !76 - %tmp23 = bitcast %struct.XYZ* %abc to i8*, !dbg !76 - call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp22, i8* %tmp23, i64 20, i32 4, i1 false), !dbg !76 - %call24 = call i32 @f10(%struct.XYZ* byval %agg.tmp21), !dbg !76 - ret i32 0, !dbg !77 -} - -declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind - -!llvm.dbg.sp = !{!0, !6, !7, !8, !9, !10, !11, !12, !13, !14, !15} - -!0 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f1", metadata !"f1", metadata !"f1", metadata !1, i32 11, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f1} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 524329, metadata !"/Users/manav/dbg_info_bugs/fastisel_arg.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 524305, i32 0, i32 12, metadata !"/Users/manav/dbg_info_bugs/fastisel_arg.c", metadata !"/private/tmp", metadata !"clang version 2.8 (trunk 112967)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!3 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] -!4 = metadata !{metadata !5} -!5 = metadata !{i32 524324, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f2", metadata !"f2", metadata !"f2", metadata !1, i32 12, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f2} ; [ DW_TAG_subprogram ] -!7 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f3", metadata !"f3", metadata !"f3", metadata !1, i32 13, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f3} ; [ DW_TAG_subprogram ] -!8 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f4", metadata !"f4", metadata !"f4", metadata !1, i32 14, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f4} ; [ DW_TAG_subprogram ] -!9 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f5", metadata !"f5", metadata !"f5", metadata !1, i32 15, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f5} ; [ DW_TAG_subprogram ] -!10 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f6", metadata !"f6", metadata !"f6", metadata !1, i32 16, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f6} ; [ DW_TAG_subprogram ] -!11 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f7", metadata !"f7", metadata !"f7", metadata !1, i32 17, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f7} ; [ DW_TAG_subprogram ] -!12 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f8", metadata !"f8", metadata !"f8", metadata !1, i32 18, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f8} ; [ DW_TAG_subprogram ] -!13 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f9", metadata !"f9", metadata !"f9", metadata !1, i32 19, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f9} ; [ DW_TAG_subprogram ] -!14 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f10", metadata !"f10", metadata !"f10", metadata !1, i32 20, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f10} ; [ DW_TAG_subprogram ] -!15 = metadata !{i32 524334, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"main", metadata !1, i32 23, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @main} ; [ DW_TAG_subprogram ] -!16 = metadata !{i32 524545, metadata !0, metadata !"i", metadata !1, i32 11, metadata !5} ; [ DW_TAG_arg_variable ] -!17 = metadata !{i32 11, i32 12, metadata !0, null} -!18 = metadata !{i32 11, i32 17, metadata !19, null} -!19 = metadata !{i32 524299, metadata !0, i32 11, i32 15, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] -!20 = metadata !{i32 524545, metadata !6, metadata !"i", metadata !1, i32 12, metadata !5} ; [ DW_TAG_arg_variable ] -!21 = metadata !{i32 12, i32 12, metadata !6, null} -!22 = metadata !{i32 12, i32 17, metadata !23, null} -!23 = metadata !{i32 524299, metadata !6, i32 12, i32 15, metadata !1, i32 1} ; [ DW_TAG_lexical_block ] -!24 = metadata !{i32 524545, metadata !7, metadata !"i", metadata !1, i32 13, metadata !5} ; [ DW_TAG_arg_variable ] -!25 = metadata !{i32 13, i32 12, metadata !7, null} -!26 = metadata !{i32 13, i32 17, metadata !27, null} -!27 = metadata !{i32 524299, metadata !7, i32 13, i32 15, metadata !1, i32 2} ; [ DW_TAG_lexical_block ] -!28 = metadata !{i32 524545, metadata !8, metadata !"i", metadata !1, i32 14, metadata !5} ; [ DW_TAG_arg_variable ] -!29 = metadata !{i32 14, i32 12, metadata !8, null} -!30 = metadata !{i32 14, i32 17, metadata !31, null} -!31 = metadata !{i32 524299, metadata !8, i32 14, i32 15, metadata !1, i32 3} ; [ DW_TAG_lexical_block ] -!32 = metadata !{i32 524545, metadata !9, metadata !"i", metadata !1, i32 15, metadata !5} ; [ DW_TAG_arg_variable ] -!33 = metadata !{i32 15, i32 12, metadata !9, null} -!34 = metadata !{i32 15, i32 17, metadata !35, null} -!35 = metadata !{i32 524299, metadata !9, i32 15, i32 15, metadata !1, i32 4} ; [ DW_TAG_lexical_block ] -!36 = metadata !{i32 524545, metadata !10, metadata !"i", metadata !1, i32 16, metadata !5} ; [ DW_TAG_arg_variable ] -!37 = metadata !{i32 16, i32 12, metadata !10, null} -!38 = metadata !{i32 16, i32 17, metadata !39, null} -!39 = metadata !{i32 524299, metadata !10, i32 16, i32 15, metadata !1, i32 5} ; [ DW_TAG_lexical_block ] -!40 = metadata !{i32 524545, metadata !11, metadata !"i", metadata !1, i32 17, metadata !41} ; [ DW_TAG_arg_variable ] -!41 = metadata !{i32 524307, metadata !1, metadata !"XYZ", metadata !1, i32 2, i64 160, i64 32, i64 0, i32 0, null, metadata !42, i32 0, null} ; [ DW_TAG_structure_type ] -!42 = metadata !{metadata !43, metadata !44, metadata !45, metadata !46, metadata !47} -!43 = metadata !{i32 524301, metadata !1, metadata !"x", metadata !1, i32 3, i64 32, i64 32, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] -!44 = metadata !{i32 524301, metadata !1, metadata !"y", metadata !1, i32 4, i64 32, i64 32, i64 32, i32 0, metadata !5} ; [ DW_TAG_member ] -!45 = metadata !{i32 524301, metadata !1, metadata !"z", metadata !1, i32 5, i64 32, i64 32, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] -!46 = metadata !{i32 524301, metadata !1, metadata !"a", metadata !1, i32 6, i64 32, i64 32, i64 96, i32 0, metadata !5} ; [ DW_TAG_member ] -!47 = metadata !{i32 524301, metadata !1, metadata !"b", metadata !1, i32 7, i64 32, i64 32, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] -!48 = metadata !{i32 17, i32 19, metadata !11, null} -!49 = metadata !{i32 17, i32 24, metadata !50, null} -!50 = metadata !{i32 524299, metadata !11, i32 17, i32 22, metadata !1, i32 6} ; [ DW_TAG_lexical_block ] -!51 = metadata !{i32 524545, metadata !12, metadata !"i", metadata !1, i32 18, metadata !41} ; [ DW_TAG_arg_variable ] -!52 = metadata !{i32 18, i32 19, metadata !12, null} -!53 = metadata !{i32 18, i32 24, metadata !54, null} -!54 = metadata !{i32 524299, metadata !12, i32 18, i32 22, metadata !1, i32 7} ; [ DW_TAG_lexical_block ] -!55 = metadata !{i32 524545, metadata !13, metadata !"i", metadata !1, i32 19, metadata !41} ; [ DW_TAG_arg_variable ] -!56 = metadata !{i32 19, i32 19, metadata !13, null} -!57 = metadata !{i32 19, i32 24, metadata !58, null} -!58 = metadata !{i32 524299, metadata !13, i32 19, i32 22, metadata !1, i32 8} ; [ DW_TAG_lexical_block ] -!59 = metadata !{i32 524545, metadata !14, metadata !"i", metadata !1, i32 20, metadata !41} ; [ DW_TAG_arg_variable ] -!60 = metadata !{i32 20, i32 20, metadata !14, null} -!61 = metadata !{i32 20, i32 25, metadata !62, null} -!62 = metadata !{i32 524299, metadata !14, i32 20, i32 23, metadata !1, i32 9} ; [ DW_TAG_lexical_block ] -!63 = metadata !{i32 24, i32 3, metadata !64, null} -!64 = metadata !{i32 524299, metadata !15, i32 23, i32 12, metadata !1, i32 10} ; [ DW_TAG_lexical_block ] -!65 = metadata !{i32 25, i32 3, metadata !64, null} -!66 = metadata !{i32 26, i32 3, metadata !64, null} -!67 = metadata !{i32 27, i32 3, metadata !64, null} -!68 = metadata !{i32 28, i32 3, metadata !64, null} -!69 = metadata !{i32 29, i32 3, metadata !64, null} -!70 = metadata !{i32 524544, metadata !64, metadata !"abc", metadata !1, i32 30, metadata !41} ; [ DW_TAG_auto_variable ] -!71 = metadata !{i32 30, i32 14, metadata !64, null} -!72 = metadata !{i32 30, i32 17, metadata !64, null} -!73 = metadata !{i32 31, i32 3, metadata !64, null} -!74 = metadata !{i32 32, i32 3, metadata !64, null} -!75 = metadata !{i32 33, i32 3, metadata !64, null} -!76 = metadata !{i32 34, i32 3, metadata !64, null} -!77 = metadata !{i32 36, i32 3, metadata !64, null} From criswell at uiuc.edu Tue Sep 7 12:16:48 2010 From: criswell at uiuc.edu (John Criswell) Date: Tue, 07 Sep 2010 17:16:48 -0000 Subject: [llvm-commits] [poolalloc] r113218 - /poolalloc/trunk/lib/DSA/EquivClassGraphs.cpp Message-ID: <20100907171648.3878E2A6C12C@llvm.org> Author: criswell Date: Tue Sep 7 12:16:48 2010 New Revision: 113218 URL: http://llvm.org/viewvc/llvm-project?rev=113218&view=rev Log: Removed unnecessary white space. No functionality changes. Modified: poolalloc/trunk/lib/DSA/EquivClassGraphs.cpp Modified: poolalloc/trunk/lib/DSA/EquivClassGraphs.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/EquivClassGraphs.cpp?rev=113218&r1=113217&r2=113218&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/EquivClassGraphs.cpp (original) +++ poolalloc/trunk/lib/DSA/EquivClassGraphs.cpp Tue Sep 7 12:16:48 2010 @@ -167,7 +167,7 @@ // the functions in this equivalence class. // setDSGraph(*F, BaseGraph); - } + } } } From bruno.cardoso at gmail.com Tue Sep 7 12:38:56 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 07 Sep 2010 17:38:56 -0000 Subject: [llvm-commits] [llvm] r113224 - in /llvm/trunk/lib/Target/X86: X86InstrFragmentsSIMD.td X86InstrSSE.td Message-ID: <20100907173856.24DAA2A6C12C@llvm.org> Author: bruno Date: Tue Sep 7 12:38:55 2010 New Revision: 113224 URL: http://llvm.org/viewvc/llvm-project?rev=113224&view=rev Log: Remove unused target specific node Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=113224&r1=113223&r2=113224&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Tue Sep 7 12:38:55 2010 @@ -134,18 +134,12 @@ def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisInt<3>]>; -def SDTShuff2OpLdI : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisPtrTy<1>, - SDTCisInt<2>]>; - def X86PAlign : SDNode<"X86ISD::PALIGN", SDTShuff3OpI>; def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>; def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>; def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>; -def X86PShufhwLd : SDNode<"X86ISD::PSHUFHW_LD", SDTShuff2OpLdI>; -def X86PShuflwLd : SDNode<"X86ISD::PSHUFLW_LD", SDTShuff2OpLdI>; - def X86Shufpd : SDNode<"X86ISD::SHUFPD", SDTShuff3OpI>; def X86Shufps : SDNode<"X86ISD::SHUFPS", SDTShuff3OpI>; Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=113224&r1=113223&r2=113224&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Sep 7 12:38:55 2010 @@ -5878,16 +5878,12 @@ (MOVSLDUPrm addr:$src)>; // Shuffle with PSHUFHW -def : Pat<(v8i16 (X86PShufhwLd addr:$src, (i8 imm:$imm))), - (PSHUFHWmi addr:$src, imm:$imm)>; def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))), (PSHUFHWri VR128:$src, imm:$imm)>; def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)), (i8 imm:$imm))), (PSHUFHWmi addr:$src, imm:$imm)>; // Shuffle with PSHUFLW -def : Pat<(v8i16 (X86PShuflwLd addr:$src, (i8 imm:$imm))), - (PSHUFLWmi addr:$src, imm:$imm)>; def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))), (PSHUFLWri VR128:$src, imm:$imm)>; def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)), (i8 imm:$imm))), From dpatel at apple.com Tue Sep 7 13:01:49 2010 From: dpatel at apple.com (Devang Patel) Date: Tue, 07 Sep 2010 18:01:49 -0000 Subject: [llvm-commits] [llvm] r113232 - in /llvm/trunk/test/CodeGen/X86: dbg-declare-fastisel.ll dbg-declare-hybrid.ll dbg-declare-isel.ll Message-ID: <20100907180149.A0A872A6C12C@llvm.org> Author: dpatel Date: Tue Sep 7 13:01:49 2010 New Revision: 113232 URL: http://llvm.org/viewvc/llvm-project?rev=113232&view=rev Log: Reintroduce dbg-declare tests. Added: llvm/trunk/test/CodeGen/X86/dbg-declare-fastisel.ll llvm/trunk/test/CodeGen/X86/dbg-declare-hybrid.ll llvm/trunk/test/CodeGen/X86/dbg-declare-isel.ll Added: llvm/trunk/test/CodeGen/X86/dbg-declare-fastisel.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-declare-fastisel.ll?rev=113232&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/dbg-declare-fastisel.ll (added) +++ llvm/trunk/test/CodeGen/X86/dbg-declare-fastisel.ll Tue Sep 7 13:01:49 2010 @@ -0,0 +1,244 @@ +; This test case checks handling of llvm.dbg.declare intrinsic during fast-isel. +; RUN: llc -mtriple=x86_64-apple-darwin --disable-fp-elim -O0 %s -o %t.s +; RUN: %compile_c -m64 %t.s -o %t.o +; RUN: %link %t.o -o %t.exe +; RUN: echo {break f1\n break f2 \n break f3 \n break f5 \n break f9 \n run \n p i \n c \n p i\n c \n p i\n c \n p i\n c \n p i.x} > %t.in +; RUN: gdb -q -batch -n -x %t.in %t.exe >& %t.out +; RUN: grep "1 = 42" %t.out +; RUN: grep "2 = 43" %t.out +; RUN: grep "3 = 44" %t.out +; RUN: grep "4 = 46" %t.out +; RUN: grep "5 = 51" %t.out + +; XTARGET: darwin +target triple = "x86_64-apple-darwin" +%struct.XYZ = type { i32, i32, i32, i32, i32 } + +; Check handling of llvm.dbg.declare for an argument referred through alloca, where +; alloca dominates llvm.dbg.declare +define i32 @f1(i32 %i) nounwind ssp { +entry: + %i.addr = alloca i32, align 4 + store i32 %i, i32* %i.addr, align 4 + call void @llvm.dbg.declare(metadata !{i32* %i.addr}, metadata !16), !dbg !17 + %tmp = load i32* %i.addr, align 4, !dbg !18 + ret i32 %tmp, !dbg !18 +} + +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + +; Check handling of llvm.dbg.declare for an argument referred through alloca, where +; llvm.dbg.declare dominates alloca. +define i32 @f2(i32 %i) nounwind ssp { +entry: + call void @llvm.dbg.declare(metadata !{i32* %i.addr}, metadata !20), !dbg !21 + %i.addr = alloca i32, align 4 + store i32 %i, i32* %i.addr, align 4 + %tmp = load i32* %i.addr, align 4, !dbg !22 + ret i32 %tmp, !dbg !22 +} + +; Check handling of an argument referred directly by llvm.dbg.declare where at least +; one argument use dominates llvm.dbg.declare. +define i32 @f3(i32 %i) nounwind ssp { +entry: + %i.addr = alloca i32, align 4 + store i32 %i, i32* %i.addr, align 4 + call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !24), !dbg !25 + %tmp = load i32* %i.addr, align 4, !dbg !26 + ret i32 %tmp, !dbg !26 +} + +; Check handling of an argument referred directly by llvm.dbg.declare where +; llvm.dbg.declare dominates all uses of argument. +define i32 @f4(i32 %i) nounwind ssp { +entry: + call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !28), !dbg !29 + ret i32 %i, !dbg !30 +} + +; Check handling of an argument referred directly by llvm.dbg.declare where +; llvm.dbg.declare dominates all uses of argument in separate basic block. +define i32 @f5(i32 %i) nounwind ssp { +entry: + call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !32), !dbg !33 + br label %bbr +bbr: + ret i32 %i, !dbg !34 +} + +; Check handling of an argument referred directly by llvm.dbg.declare where +; argument is not used. +define i32 @f6(i32 %i) nounwind ssp { +entry: + call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !36), !dbg !37 + ret i32 1, !dbg !38 +} + +; Check handling of an byval argument referred directly by llvm.dbg.declare where +; argument is not used. +define i32 @f7(%struct.XYZ* byval %i) nounwind ssp { +entry: + call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !40), !dbg !48 + ret i32 1, !dbg !49 +} + +; Check handling of an byval argument referred directly by llvm.dbg.declare where +; argument use dominates llvm.dbg.declare. +define i32 @f8(%struct.XYZ* byval %i) nounwind ssp { +entry: + %tmp = getelementptr inbounds %struct.XYZ* %i, i32 0, i32 1, !dbg !53 + %tmp1 = load i32* %tmp, align 4, !dbg !53 + call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !51), !dbg !52 + ret i32 %tmp1, !dbg !53 +} + +; Check handling of an byval argument referred directly by llvm.dbg.declare where +; llvm.dbg.declare dominates all uses of argument. +define i32 @f9(%struct.XYZ* byval %i) nounwind ssp { +entry: + call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !55), !dbg !56 + %tmp = getelementptr inbounds %struct.XYZ* %i, i32 0, i32 2, !dbg !57 + %tmp1 = load i32* %tmp, align 4, !dbg !57 + ret i32 %tmp1, !dbg !57 +} + +; Check handling of an byval argument referred directly by llvm.dbg.declare where +; llvm.dbg.declare dominates all uses of argument in separate basic block. +define i32 @f10(%struct.XYZ* byval %i) nounwind ssp { +entry: + call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !59), !dbg !60 + br label %bbr +bbr: + %tmp = getelementptr inbounds %struct.XYZ* %i, i32 0, i32 3, !dbg !61 + %tmp1 = load i32* %tmp, align 4, !dbg !61 + ret i32 %tmp1, !dbg !61 +} + +define i32 @main() nounwind ssp { +entry: + %retval = alloca i32, align 4 + %abc = alloca %struct.XYZ, align 4 + %agg.tmp = alloca %struct.XYZ, align 4 + %agg.tmp13 = alloca %struct.XYZ, align 4 + %agg.tmp17 = alloca %struct.XYZ, align 4 + %agg.tmp21 = alloca %struct.XYZ, align 4 + store i32 0, i32* %retval + %call = call i32 @f1(i32 42), !dbg !63 + %call1 = call i32 @f2(i32 43), !dbg !65 + %call2 = call i32 @f3(i32 44), !dbg !66 + %call3 = call i32 @f4(i32 45), !dbg !67 + %call4 = call i32 @f5(i32 46), !dbg !68 + %call5 = call i32 @f6(i32 47), !dbg !69 + call void @llvm.dbg.declare(metadata !{%struct.XYZ* %abc}, metadata !70), !dbg !71 + %tmp = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 0, !dbg !72 + store i32 51, i32* %tmp, align 4, !dbg !72 + %tmp6 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 1, !dbg !72 + store i32 52, i32* %tmp6, align 4, !dbg !72 + %tmp7 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 2, !dbg !72 + store i32 53, i32* %tmp7, align 4, !dbg !72 + %tmp8 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 3, !dbg !72 + store i32 54, i32* %tmp8, align 4, !dbg !72 + %tmp9 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 4, !dbg !72 + store i32 55, i32* %tmp9, align 4, !dbg !72 + %tmp10 = bitcast %struct.XYZ* %agg.tmp to i8*, !dbg !73 + %tmp11 = bitcast %struct.XYZ* %abc to i8*, !dbg !73 + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp10, i8* %tmp11, i64 20, i32 4, i1 false), !dbg !73 + %call12 = call i32 @f7(%struct.XYZ* byval %agg.tmp), !dbg !73 + %tmp14 = bitcast %struct.XYZ* %agg.tmp13 to i8*, !dbg !74 + %tmp15 = bitcast %struct.XYZ* %abc to i8*, !dbg !74 + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp14, i8* %tmp15, i64 20, i32 4, i1 false), !dbg !74 + %call16 = call i32 @f8(%struct.XYZ* byval %agg.tmp13), !dbg !74 + %tmp18 = bitcast %struct.XYZ* %agg.tmp17 to i8*, !dbg !75 + %tmp19 = bitcast %struct.XYZ* %abc to i8*, !dbg !75 + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp18, i8* %tmp19, i64 20, i32 4, i1 false), !dbg !75 + %call20 = call i32 @f9(%struct.XYZ* byval %agg.tmp17), !dbg !75 + %tmp22 = bitcast %struct.XYZ* %agg.tmp21 to i8*, !dbg !76 + %tmp23 = bitcast %struct.XYZ* %abc to i8*, !dbg !76 + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp22, i8* %tmp23, i64 20, i32 4, i1 false), !dbg !76 + %call24 = call i32 @f10(%struct.XYZ* byval %agg.tmp21), !dbg !76 + ret i32 0, !dbg !77 +} + +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind + +!llvm.dbg.sp = !{!0, !6, !7, !8, !9, !10, !11, !12, !13, !14, !15} + +!0 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f1", metadata !"f1", metadata !"f1", metadata !1, i32 11, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f1} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 524329, metadata !"arg.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 524305, i32 0, i32 12, metadata !"arg.c", metadata !"/private/tmp", metadata !"clang version 2.8 (trunk 112967)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{metadata !5} +!5 = metadata !{i32 524324, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f2", metadata !"f2", metadata !"f2", metadata !1, i32 12, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f2} ; [ DW_TAG_subprogram ] +!7 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f3", metadata !"f3", metadata !"f3", metadata !1, i32 13, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f3} ; [ DW_TAG_subprogram ] +!8 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f4", metadata !"f4", metadata !"f4", metadata !1, i32 14, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f4} ; [ DW_TAG_subprogram ] +!9 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f5", metadata !"f5", metadata !"f5", metadata !1, i32 15, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f5} ; [ DW_TAG_subprogram ] +!10 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f6", metadata !"f6", metadata !"f6", metadata !1, i32 16, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f6} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f7", metadata !"f7", metadata !"f7", metadata !1, i32 17, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f7} ; [ DW_TAG_subprogram ] +!12 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f8", metadata !"f8", metadata !"f8", metadata !1, i32 18, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f8} ; [ DW_TAG_subprogram ] +!13 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f9", metadata !"f9", metadata !"f9", metadata !1, i32 19, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f9} ; [ DW_TAG_subprogram ] +!14 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f10", metadata !"f10", metadata !"f10", metadata !1, i32 20, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f10} ; [ DW_TAG_subprogram ] +!15 = metadata !{i32 524334, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"main", metadata !1, i32 23, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @main} ; [ DW_TAG_subprogram ] +!16 = metadata !{i32 524545, metadata !0, metadata !"i", metadata !1, i32 11, metadata !5} ; [ DW_TAG_arg_variable ] +!17 = metadata !{i32 11, i32 12, metadata !0, null} +!18 = metadata !{i32 11, i32 17, metadata !19, null} +!19 = metadata !{i32 524299, metadata !0, i32 11, i32 15, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] +!20 = metadata !{i32 524545, metadata !6, metadata !"i", metadata !1, i32 12, metadata !5} ; [ DW_TAG_arg_variable ] +!21 = metadata !{i32 12, i32 12, metadata !6, null} +!22 = metadata !{i32 12, i32 17, metadata !23, null} +!23 = metadata !{i32 524299, metadata !6, i32 12, i32 15, metadata !1, i32 1} ; [ DW_TAG_lexical_block ] +!24 = metadata !{i32 524545, metadata !7, metadata !"i", metadata !1, i32 13, metadata !5} ; [ DW_TAG_arg_variable ] +!25 = metadata !{i32 13, i32 12, metadata !7, null} +!26 = metadata !{i32 13, i32 17, metadata !27, null} +!27 = metadata !{i32 524299, metadata !7, i32 13, i32 15, metadata !1, i32 2} ; [ DW_TAG_lexical_block ] +!28 = metadata !{i32 524545, metadata !8, metadata !"i", metadata !1, i32 14, metadata !5} ; [ DW_TAG_arg_variable ] +!29 = metadata !{i32 14, i32 12, metadata !8, null} +!30 = metadata !{i32 14, i32 17, metadata !31, null} +!31 = metadata !{i32 524299, metadata !8, i32 14, i32 15, metadata !1, i32 3} ; [ DW_TAG_lexical_block ] +!32 = metadata !{i32 524545, metadata !9, metadata !"i", metadata !1, i32 15, metadata !5} ; [ DW_TAG_arg_variable ] +!33 = metadata !{i32 15, i32 12, metadata !9, null} +!34 = metadata !{i32 15, i32 17, metadata !35, null} +!35 = metadata !{i32 524299, metadata !9, i32 15, i32 15, metadata !1, i32 4} ; [ DW_TAG_lexical_block ] +!36 = metadata !{i32 524545, metadata !10, metadata !"i", metadata !1, i32 16, metadata !5} ; [ DW_TAG_arg_variable ] +!37 = metadata !{i32 16, i32 12, metadata !10, null} +!38 = metadata !{i32 16, i32 17, metadata !39, null} +!39 = metadata !{i32 524299, metadata !10, i32 16, i32 15, metadata !1, i32 5} ; [ DW_TAG_lexical_block ] +!40 = metadata !{i32 524545, metadata !11, metadata !"i", metadata !1, i32 17, metadata !41} ; [ DW_TAG_arg_variable ] +!41 = metadata !{i32 524307, metadata !1, metadata !"XYZ", metadata !1, i32 2, i64 160, i64 32, i64 0, i32 0, null, metadata !42, i32 0, null} ; [ DW_TAG_structure_type ] +!42 = metadata !{metadata !43, metadata !44, metadata !45, metadata !46, metadata !47} +!43 = metadata !{i32 524301, metadata !1, metadata !"x", metadata !1, i32 3, i64 32, i64 32, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] +!44 = metadata !{i32 524301, metadata !1, metadata !"y", metadata !1, i32 4, i64 32, i64 32, i64 32, i32 0, metadata !5} ; [ DW_TAG_member ] +!45 = metadata !{i32 524301, metadata !1, metadata !"z", metadata !1, i32 5, i64 32, i64 32, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] +!46 = metadata !{i32 524301, metadata !1, metadata !"a", metadata !1, i32 6, i64 32, i64 32, i64 96, i32 0, metadata !5} ; [ DW_TAG_member ] +!47 = metadata !{i32 524301, metadata !1, metadata !"b", metadata !1, i32 7, i64 32, i64 32, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] +!48 = metadata !{i32 17, i32 19, metadata !11, null} +!49 = metadata !{i32 17, i32 24, metadata !50, null} +!50 = metadata !{i32 524299, metadata !11, i32 17, i32 22, metadata !1, i32 6} ; [ DW_TAG_lexical_block ] +!51 = metadata !{i32 524545, metadata !12, metadata !"i", metadata !1, i32 18, metadata !41} ; [ DW_TAG_arg_variable ] +!52 = metadata !{i32 18, i32 19, metadata !12, null} +!53 = metadata !{i32 18, i32 24, metadata !54, null} +!54 = metadata !{i32 524299, metadata !12, i32 18, i32 22, metadata !1, i32 7} ; [ DW_TAG_lexical_block ] +!55 = metadata !{i32 524545, metadata !13, metadata !"i", metadata !1, i32 19, metadata !41} ; [ DW_TAG_arg_variable ] +!56 = metadata !{i32 19, i32 19, metadata !13, null} +!57 = metadata !{i32 19, i32 24, metadata !58, null} +!58 = metadata !{i32 524299, metadata !13, i32 19, i32 22, metadata !1, i32 8} ; [ DW_TAG_lexical_block ] +!59 = metadata !{i32 524545, metadata !14, metadata !"i", metadata !1, i32 20, metadata !41} ; [ DW_TAG_arg_variable ] +!60 = metadata !{i32 20, i32 20, metadata !14, null} +!61 = metadata !{i32 20, i32 25, metadata !62, null} +!62 = metadata !{i32 524299, metadata !14, i32 20, i32 23, metadata !1, i32 9} ; [ DW_TAG_lexical_block ] +!63 = metadata !{i32 24, i32 3, metadata !64, null} +!64 = metadata !{i32 524299, metadata !15, i32 23, i32 12, metadata !1, i32 10} ; [ DW_TAG_lexical_block ] +!65 = metadata !{i32 25, i32 3, metadata !64, null} +!66 = metadata !{i32 26, i32 3, metadata !64, null} +!67 = metadata !{i32 27, i32 3, metadata !64, null} +!68 = metadata !{i32 28, i32 3, metadata !64, null} +!69 = metadata !{i32 29, i32 3, metadata !64, null} +!70 = metadata !{i32 524544, metadata !64, metadata !"abc", metadata !1, i32 30, metadata !41} ; [ DW_TAG_auto_variable ] +!71 = metadata !{i32 30, i32 14, metadata !64, null} +!72 = metadata !{i32 30, i32 17, metadata !64, null} +!73 = metadata !{i32 31, i32 3, metadata !64, null} +!74 = metadata !{i32 32, i32 3, metadata !64, null} +!75 = metadata !{i32 33, i32 3, metadata !64, null} +!76 = metadata !{i32 34, i32 3, metadata !64, null} +!77 = metadata !{i32 36, i32 3, metadata !64, null} Added: llvm/trunk/test/CodeGen/X86/dbg-declare-hybrid.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-declare-hybrid.ll?rev=113232&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/dbg-declare-hybrid.ll (added) +++ llvm/trunk/test/CodeGen/X86/dbg-declare-hybrid.ll Tue Sep 7 13:01:49 2010 @@ -0,0 +1,267 @@ +; This test case checks handling of llvm.dbg.declare intrinsic during hybrid mode where we begin +; using fast-isel but switch back to DAG building at some point. +; RUN: llc -mtriple=x86_64-apple-darwin --disable-fp-elim -O0 %s -o %t.s +; RUN: %compile_c -m64 %t.s -o %t.o +; RUN: %link %t.o -o %t.exe +; RUN: echo {break f1\n break f4\n break f5\n run \n p i\n c \n p i\n c \n p i\n} > %t.in +; RUN: gdb -q -batch -n -x %t.in %t.exe >& %t.out +; RUN: grep "1 = 42" %t.out +; RUN: grep "2 = 45" %t.out +; RUN: grep "3 = 46" %t.out + +; XTARGET: darwin +target triple = "x86_64-apple-darwin" +%struct.XYZ = type { i32, i32, i32, i32, i32 } +%0 = type { i64, i32 } +define %0 @foobar() { + ret i64 6, i32 7 +} + +; Check handling of llvm.dbg.declare for an argument referred through alloca, where +; alloca dominates llvm.dbg.declare +define i32 @f1(i32 %i) nounwind ssp { +entry: + %i.addr = alloca i32, align 4 + store i32 %i, i32* %i.addr, align 4 + %call = call %0 @foobar() + call void @llvm.dbg.declare(metadata !{i32* %i.addr}, metadata !16), !dbg !17 + %call2 = call %0 @foobar() + %tmp = load i32* %i.addr, align 4, !dbg !18 + ret i32 %tmp, !dbg !18 +} + +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + +; Check handling of llvm.dbg.declare for an argument referred through alloca, where +; llvm.dbg.declare dominates alloca. +define i32 @f2(i32 %i) nounwind ssp { +entry: + %call = call %0 @foobar() + call void @llvm.dbg.declare(metadata !{i32* %i.addr}, metadata !20), !dbg !21 + %call2 = call %0 @foobar() + %i.addr = alloca i32, align 4 + store i32 %i, i32* %i.addr, align 4 + %tmp = load i32* %i.addr, align 4, !dbg !22 + ret i32 %tmp, !dbg !22 +} + +; Check handling of an argument referred directly by llvm.dbg.declare where at least +; one argument use dominates llvm.dbg.declare. +define i32 @f3(i32 %i) nounwind ssp { +entry: + %i.addr = alloca i32, align 4 + store i32 %i, i32* %i.addr, align 4 + %call = call %0 @foobar() + call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !24), !dbg !2 + %call2 = call %0 @foobar() + %tmp = load i32* %i.addr, align 4, !dbg !26 + ret i32 %tmp, !dbg !26 +} + +; Check handling of an argument referred directly by llvm.dbg.declare where +; llvm.dbg.declare dominates all uses of argument. +define i32 @f4(i32 %i) nounwind ssp { +entry: + %call = call %0 @foobar() + call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !28), !dbg !29 + %call2 = call %0 @foobar() + ret i32 %i, !dbg !30 +} + +; Check handling of an argument referred directly by llvm.dbg.declare where +; llvm.dbg.declare dominates all uses of argument in separate basic block. +define i32 @f5(i32 %i) nounwind ssp { +entry: + %call = call %0 @foobar() + call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !32), !dbg !33 + %call2 = call %0 @foobar() + br label %bbr +bbr: + ret i32 %i, !dbg !34 +} + +; Check handling of an argument referred directly by llvm.dbg.declare where +; argument is not used. +define i32 @f6(i32 %i) nounwind ssp { +entry: + %call = call %0 @foobar() + call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !36), !dbg !37 + %call2 = call %0 @foobar() + ret i32 1, !dbg !38 +} + +; Check handling of an byval argument referred directly by llvm.dbg.declare where +; argument is not used. +define i32 @f7(%struct.XYZ* byval %i) nounwind ssp { +entry: + %call = call %0 @foobar() + call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !40), !dbg !48 + %call2 = call %0 @foobar() + ret i32 1, !dbg !49 +} + +; Check handling of an byval argument referred directly by llvm.dbg.declare where +; argument use dominates llvm.dbg.declare. +define i32 @f8(%struct.XYZ* byval %i) nounwind ssp { +entry: + %tmp = getelementptr inbounds %struct.XYZ* %i, i32 0, i32 1, !dbg !53 + %tmp1 = load i32* %tmp, align 4, !dbg !53 + %call = call %0 @foobar() + call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !51), !dbg !52 + %call2 = call %0 @foobar() + ret i32 %tmp1, !dbg !53 +} + +; Check handling of an byval argument referred directly by llvm.dbg.declare where +; llvm.dbg.declare dominates all uses of argument. +define i32 @f9(%struct.XYZ* byval %i) nounwind ssp { +entry: + %call = call %0 @foobar() + call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !55), !dbg !56 + %call2 = call %0 @foobar() + %tmp = getelementptr inbounds %struct.XYZ* %i, i32 0, i32 2, !dbg !57 + %tmp1 = load i32* %tmp, align 4, !dbg !57 + ret i32 %tmp1, !dbg !57 +} + +; Check handling of an byval argument referred directly by llvm.dbg.declare where +; llvm.dbg.declare dominates all uses of argument in separate basic block. +define i32 @f10(%struct.XYZ* byval %i) nounwind ssp { +entry: + %call = call %0 @foobar() + call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !59), !dbg !60 + %call2 = call %0 @foobar() + br label %bbr +bbr: + %tmp = getelementptr inbounds %struct.XYZ* %i, i32 0, i32 3, !dbg !61 + %tmp1 = load i32* %tmp, align 4, !dbg !61 + ret i32 %tmp1, !dbg !61 +} + +define i32 @main() nounwind ssp { +entry: + %retval = alloca i32, align 4 + %abc = alloca %struct.XYZ, align 4 + %agg.tmp = alloca %struct.XYZ, align 4 + %agg.tmp13 = alloca %struct.XYZ, align 4 + %agg.tmp17 = alloca %struct.XYZ, align 4 + %agg.tmp21 = alloca %struct.XYZ, align 4 + store i32 0, i32* %retval + %call = call i32 @f1(i32 42), !dbg !63 + %call1 = call i32 @f2(i32 43), !dbg !65 + %call2 = call i32 @f3(i32 44), !dbg !66 + %call3 = call i32 @f4(i32 45), !dbg !67 + %call4 = call i32 @f5(i32 46), !dbg !68 + %call5 = call i32 @f6(i32 47), !dbg !69 + call void @llvm.dbg.declare(metadata !{%struct.XYZ* %abc}, metadata !70), !dbg !71 + %tmp = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 0, !dbg !72 + store i32 51, i32* %tmp, align 4, !dbg !72 + %tmp6 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 1, !dbg !72 + store i32 52, i32* %tmp6, align 4, !dbg !72 + %tmp7 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 2, !dbg !72 + store i32 53, i32* %tmp7, align 4, !dbg !72 + %tmp8 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 3, !dbg !72 + store i32 54, i32* %tmp8, align 4, !dbg !72 + %tmp9 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 4, !dbg !72 + store i32 55, i32* %tmp9, align 4, !dbg !72 + %tmp10 = bitcast %struct.XYZ* %agg.tmp to i8*, !dbg !73 + %tmp11 = bitcast %struct.XYZ* %abc to i8*, !dbg !73 + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp10, i8* %tmp11, i64 20, i32 4, i1 false), !dbg !73 + %call12 = call i32 @f7(%struct.XYZ* byval %agg.tmp), !dbg !73 + %tmp14 = bitcast %struct.XYZ* %agg.tmp13 to i8*, !dbg !74 + %tmp15 = bitcast %struct.XYZ* %abc to i8*, !dbg !74 + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp14, i8* %tmp15, i64 20, i32 4, i1 false), !dbg !74 + %call16 = call i32 @f8(%struct.XYZ* byval %agg.tmp13), !dbg !74 + %tmp18 = bitcast %struct.XYZ* %agg.tmp17 to i8*, !dbg !75 + %tmp19 = bitcast %struct.XYZ* %abc to i8*, !dbg !75 + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp18, i8* %tmp19, i64 20, i32 4, i1 false), !dbg !75 + %call20 = call i32 @f9(%struct.XYZ* byval %agg.tmp17), !dbg !75 + %tmp22 = bitcast %struct.XYZ* %agg.tmp21 to i8*, !dbg !76 + %tmp23 = bitcast %struct.XYZ* %abc to i8*, !dbg !76 + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp22, i8* %tmp23, i64 20, i32 4, i1 false), !dbg !76 + %call24 = call i32 @f10(%struct.XYZ* byval %agg.tmp21), !dbg !76 + ret i32 0, !dbg !77 +} + +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind + +!llvm.dbg.sp = !{!0, !6, !7, !8, !9, !10, !11, !12, !13, !14, !15} + +!0 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f1", metadata !"f1", metadata !"f1", metadata !1, i32 11, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f1} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 524329, metadata !"arg.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 524305, i32 0, i32 12, metadata !"arg.c", metadata !"/private/tmp", metadata !"clang version 2.8 (trunk 112967)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{metadata !5} +!5 = metadata !{i32 524324, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f2", metadata !"f2", metadata !"f2", metadata !1, i32 12, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f2} ; [ DW_TAG_subprogram ] +!7 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f3", metadata !"f3", metadata !"f3", metadata !1, i32 13, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f3} ; [ DW_TAG_subprogram ] +!8 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f4", metadata !"f4", metadata !"f4", metadata !1, i32 14, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f4} ; [ DW_TAG_subprogram ] +!9 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f5", metadata !"f5", metadata !"f5", metadata !1, i32 15, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f5} ; [ DW_TAG_subprogram ] +!10 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f6", metadata !"f6", metadata !"f6", metadata !1, i32 16, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f6} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f7", metadata !"f7", metadata !"f7", metadata !1, i32 17, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f7} ; [ DW_TAG_subprogram ] +!12 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f8", metadata !"f8", metadata !"f8", metadata !1, i32 18, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f8} ; [ DW_TAG_subprogram ] +!13 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f9", metadata !"f9", metadata !"f9", metadata !1, i32 19, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f9} ; [ DW_TAG_subprogram ] +!14 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f10", metadata !"f10", metadata !"f10", metadata !1, i32 20, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f10} ; [ DW_TAG_subprogram ] +!15 = metadata !{i32 524334, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"main", metadata !1, i32 23, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @main} ; [ DW_TAG_subprogram ] +!16 = metadata !{i32 524545, metadata !0, metadata !"i", metadata !1, i32 11, metadata !5} ; [ DW_TAG_arg_variable ] +!17 = metadata !{i32 11, i32 12, metadata !0, null} +!18 = metadata !{i32 11, i32 17, metadata !19, null} +!19 = metadata !{i32 524299, metadata !0, i32 11, i32 15, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] +!20 = metadata !{i32 524545, metadata !6, metadata !"i", metadata !1, i32 12, metadata !5} ; [ DW_TAG_arg_variable ] +!21 = metadata !{i32 12, i32 12, metadata !6, null} +!22 = metadata !{i32 12, i32 17, metadata !23, null} +!23 = metadata !{i32 524299, metadata !6, i32 12, i32 15, metadata !1, i32 1} ; [ DW_TAG_lexical_block ] +!24 = metadata !{i32 524545, metadata !7, metadata !"i", metadata !1, i32 13, metadata !5} ; [ DW_TAG_arg_variable ] +!25 = metadata !{i32 13, i32 12, metadata !7, null} +!26 = metadata !{i32 13, i32 17, metadata !27, null} +!27 = metadata !{i32 524299, metadata !7, i32 13, i32 15, metadata !1, i32 2} ; [ DW_TAG_lexical_block ] +!28 = metadata !{i32 524545, metadata !8, metadata !"i", metadata !1, i32 14, metadata !5} ; [ DW_TAG_arg_variable ] +!29 = metadata !{i32 14, i32 12, metadata !8, null} +!30 = metadata !{i32 14, i32 17, metadata !31, null} +!31 = metadata !{i32 524299, metadata !8, i32 14, i32 15, metadata !1, i32 3} ; [ DW_TAG_lexical_block ] +!32 = metadata !{i32 524545, metadata !9, metadata !"i", metadata !1, i32 15, metadata !5} ; [ DW_TAG_arg_variable ] +!33 = metadata !{i32 15, i32 12, metadata !9, null} +!34 = metadata !{i32 15, i32 17, metadata !35, null} +!35 = metadata !{i32 524299, metadata !9, i32 15, i32 15, metadata !1, i32 4} ; [ DW_TAG_lexical_block ] +!36 = metadata !{i32 524545, metadata !10, metadata !"i", metadata !1, i32 16, metadata !5} ; [ DW_TAG_arg_variable ] +!37 = metadata !{i32 16, i32 12, metadata !10, null} +!38 = metadata !{i32 16, i32 17, metadata !39, null} +!39 = metadata !{i32 524299, metadata !10, i32 16, i32 15, metadata !1, i32 5} ; [ DW_TAG_lexical_block ] +!40 = metadata !{i32 524545, metadata !11, metadata !"i", metadata !1, i32 17, metadata !41} ; [ DW_TAG_arg_variable ] +!41 = metadata !{i32 524307, metadata !1, metadata !"XYZ", metadata !1, i32 2, i64 160, i64 32, i64 0, i32 0, null, metadata !42, i32 0, null} ; [ DW_TAG_structure_type ] +!42 = metadata !{metadata !43, metadata !44, metadata !45, metadata !46, metadata !47} +!43 = metadata !{i32 524301, metadata !1, metadata !"x", metadata !1, i32 3, i64 32, i64 32, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] +!44 = metadata !{i32 524301, metadata !1, metadata !"y", metadata !1, i32 4, i64 32, i64 32, i64 32, i32 0, metadata !5} ; [ DW_TAG_member ] +!45 = metadata !{i32 524301, metadata !1, metadata !"z", metadata !1, i32 5, i64 32, i64 32, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] +!46 = metadata !{i32 524301, metadata !1, metadata !"a", metadata !1, i32 6, i64 32, i64 32, i64 96, i32 0, metadata !5} ; [ DW_TAG_member ] +!47 = metadata !{i32 524301, metadata !1, metadata !"b", metadata !1, i32 7, i64 32, i64 32, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] +!48 = metadata !{i32 17, i32 19, metadata !11, null} +!49 = metadata !{i32 17, i32 24, metadata !50, null} +!50 = metadata !{i32 524299, metadata !11, i32 17, i32 22, metadata !1, i32 6} ; [ DW_TAG_lexical_block ] +!51 = metadata !{i32 524545, metadata !12, metadata !"i", metadata !1, i32 18, metadata !41} ; [ DW_TAG_arg_variable ] +!52 = metadata !{i32 18, i32 19, metadata !12, null} +!53 = metadata !{i32 18, i32 24, metadata !54, null} +!54 = metadata !{i32 524299, metadata !12, i32 18, i32 22, metadata !1, i32 7} ; [ DW_TAG_lexical_block ] +!55 = metadata !{i32 524545, metadata !13, metadata !"i", metadata !1, i32 19, metadata !41} ; [ DW_TAG_arg_variable ] +!56 = metadata !{i32 19, i32 19, metadata !13, null} +!57 = metadata !{i32 19, i32 24, metadata !58, null} +!58 = metadata !{i32 524299, metadata !13, i32 19, i32 22, metadata !1, i32 8} ; [ DW_TAG_lexical_block ] +!59 = metadata !{i32 524545, metadata !14, metadata !"i", metadata !1, i32 20, metadata !41} ; [ DW_TAG_arg_variable ] +!60 = metadata !{i32 20, i32 20, metadata !14, null} +!61 = metadata !{i32 20, i32 25, metadata !62, null} +!62 = metadata !{i32 524299, metadata !14, i32 20, i32 23, metadata !1, i32 9} ; [ DW_TAG_lexical_block ] +!63 = metadata !{i32 24, i32 3, metadata !64, null} +!64 = metadata !{i32 524299, metadata !15, i32 23, i32 12, metadata !1, i32 10} ; [ DW_TAG_lexical_block ] +!65 = metadata !{i32 25, i32 3, metadata !64, null} +!66 = metadata !{i32 26, i32 3, metadata !64, null} +!67 = metadata !{i32 27, i32 3, metadata !64, null} +!68 = metadata !{i32 28, i32 3, metadata !64, null} +!69 = metadata !{i32 29, i32 3, metadata !64, null} +!70 = metadata !{i32 524544, metadata !64, metadata !"abc", metadata !1, i32 30, metadata !41} ; [ DW_TAG_auto_variable ] +!71 = metadata !{i32 30, i32 14, metadata !64, null} +!72 = metadata !{i32 30, i32 17, metadata !64, null} +!73 = metadata !{i32 31, i32 3, metadata !64, null} +!74 = metadata !{i32 32, i32 3, metadata !64, null} +!75 = metadata !{i32 33, i32 3, metadata !64, null} +!76 = metadata !{i32 34, i32 3, metadata !64, null} +!77 = metadata !{i32 36, i32 3, metadata !64, null} Added: llvm/trunk/test/CodeGen/X86/dbg-declare-isel.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-declare-isel.ll?rev=113232&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/dbg-declare-isel.ll (added) +++ llvm/trunk/test/CodeGen/X86/dbg-declare-isel.ll Tue Sep 7 13:01:49 2010 @@ -0,0 +1,245 @@ +; This test case checks handling of llvm.dbg.declare intrinsic during isel. +; RUN: llc -mtriple=x86_64-apple-darwin --disable-fp-elim -O0 -fast-isel=false %s -o %t.s +; RUN: %compile_c -m64 %t.s -o %t.o +; RUN: %link %t.o -o %t.exe +; RUN: echo {break f1\n break f2 \n break f7 \n break f8 \n break f9 \n break f10 \n run \n p i\n c \n p i\n c \n p i.x\n c \n p i.x\n c \n p i.x \n c \n p i.x \n} > %t.in +; RUN: gdb -q -batch -n -x %t.in %t.exe >& %t.out +; RUN: grep "1 = 42" %t.out +; RUN: grep "2 = 43" %t.out +; RUN: grep "3 = 51" %t.out +; RUN: grep "4 = 51" %t.out +; RUN: grep "5 = 51" %t.out +; RUN: grep "6 = 51" %t.out + +; XTARGET: darwin +target triple = "x86_64-apple-darwin" +%struct.XYZ = type { i32, i32, i32, i32, i32 } + +; Check handling of llvm.dbg.declare for an argument referred through alloca, where +; alloca dominates llvm.dbg.declare +define i32 @f1(i32 %i) nounwind ssp { +entry: + %i.addr = alloca i32, align 4 + store i32 %i, i32* %i.addr, align 4 + call void @llvm.dbg.declare(metadata !{i32* %i.addr}, metadata !16), !dbg !17 + %tmp = load i32* %i.addr, align 4, !dbg !18 + ret i32 %tmp, !dbg !18 +} + +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + +; Check handling of llvm.dbg.declare for an argument referred through alloca, where +; llvm.dbg.declare dominates alloca. +define i32 @f2(i32 %i) nounwind ssp { +entry: + call void @llvm.dbg.declare(metadata !{i32* %i.addr}, metadata !20), !dbg !21 + %i.addr = alloca i32, align 4 + store i32 %i, i32* %i.addr, align 4 + %tmp = load i32* %i.addr, align 4, !dbg !22 + ret i32 %tmp, !dbg !22 +} + +; Check handling of an argument referred directly by llvm.dbg.declare where at least +; one argument use dominates llvm.dbg.declare. +define i32 @f3(i32 %i) nounwind ssp { +entry: + %i.addr = alloca i32, align 4 + store i32 %i, i32* %i.addr, align 4 + call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !24), !dbg !25 + %tmp = load i32* %i.addr, align 4, !dbg !26 + ret i32 %tmp, !dbg !26 +} + +; Check handling of an argument referred directly by llvm.dbg.declare where +; llvm.dbg.declare dominates all uses of argument. +define i32 @f4(i32 %i) nounwind ssp { +entry: + call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !28), !dbg !29 + ret i32 %i, !dbg !30 +} + +; Check handling of an argument referred directly by llvm.dbg.declare where +; llvm.dbg.declare dominates all uses of argument in separate basic block. +define i32 @f5(i32 %i) nounwind ssp { +entry: + call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !32), !dbg !33 + br label %bbr +bbr: + ret i32 %i, !dbg !34 +} + +; Check handling of an argument referred directly by llvm.dbg.declare where +; argument is not used. +define i32 @f6(i32 %i) nounwind ssp { +entry: + call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !36), !dbg !37 + ret i32 1, !dbg !38 +} + +; Check handling of an byval argument referred directly by llvm.dbg.declare where +; argument is not used. +define i32 @f7(%struct.XYZ* byval %i) nounwind ssp { +entry: + call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !40), !dbg !48 + ret i32 1, !dbg !49 +} + +; Check handling of an byval argument referred directly by llvm.dbg.declare where +; argument use dominates llvm.dbg.declare. +define i32 @f8(%struct.XYZ* byval %i) nounwind ssp { +entry: + %tmp = getelementptr inbounds %struct.XYZ* %i, i32 0, i32 1, !dbg !53 + %tmp1 = load i32* %tmp, align 4, !dbg !53 + call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !51), !dbg !52 + ret i32 %tmp1, !dbg !53 +} + +; Check handling of an byval argument referred directly by llvm.dbg.declare where +; llvm.dbg.declare dominates all uses of argument. +define i32 @f9(%struct.XYZ* byval %i) nounwind ssp { +entry: + call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !55), !dbg !56 + %tmp = getelementptr inbounds %struct.XYZ* %i, i32 0, i32 2, !dbg !57 + %tmp1 = load i32* %tmp, align 4, !dbg !57 + ret i32 %tmp1, !dbg !57 +} + +; Check handling of an byval argument referred directly by llvm.dbg.declare where +; llvm.dbg.declare dominates all uses of argument in separate basic block. +define i32 @f10(%struct.XYZ* byval %i) nounwind ssp { +entry: + call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !59), !dbg !60 + br label %bbr +bbr: + %tmp = getelementptr inbounds %struct.XYZ* %i, i32 0, i32 3, !dbg !61 + %tmp1 = load i32* %tmp, align 4, !dbg !61 + ret i32 %tmp1, !dbg !61 +} + +define i32 @main() nounwind ssp { +entry: + %retval = alloca i32, align 4 + %abc = alloca %struct.XYZ, align 4 + %agg.tmp = alloca %struct.XYZ, align 4 + %agg.tmp13 = alloca %struct.XYZ, align 4 + %agg.tmp17 = alloca %struct.XYZ, align 4 + %agg.tmp21 = alloca %struct.XYZ, align 4 + store i32 0, i32* %retval + %call = call i32 @f1(i32 42), !dbg !63 + %call1 = call i32 @f2(i32 43), !dbg !65 + %call2 = call i32 @f3(i32 44), !dbg !66 + %call3 = call i32 @f4(i32 45), !dbg !67 + %call4 = call i32 @f5(i32 46), !dbg !68 + %call5 = call i32 @f6(i32 47), !dbg !69 + call void @llvm.dbg.declare(metadata !{%struct.XYZ* %abc}, metadata !70), !dbg !71 + %tmp = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 0, !dbg !72 + store i32 51, i32* %tmp, align 4, !dbg !72 + %tmp6 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 1, !dbg !72 + store i32 52, i32* %tmp6, align 4, !dbg !72 + %tmp7 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 2, !dbg !72 + store i32 53, i32* %tmp7, align 4, !dbg !72 + %tmp8 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 3, !dbg !72 + store i32 54, i32* %tmp8, align 4, !dbg !72 + %tmp9 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 4, !dbg !72 + store i32 55, i32* %tmp9, align 4, !dbg !72 + %tmp10 = bitcast %struct.XYZ* %agg.tmp to i8*, !dbg !73 + %tmp11 = bitcast %struct.XYZ* %abc to i8*, !dbg !73 + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp10, i8* %tmp11, i64 20, i32 4, i1 false), !dbg !73 + %call12 = call i32 @f7(%struct.XYZ* byval %agg.tmp), !dbg !73 + %tmp14 = bitcast %struct.XYZ* %agg.tmp13 to i8*, !dbg !74 + %tmp15 = bitcast %struct.XYZ* %abc to i8*, !dbg !74 + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp14, i8* %tmp15, i64 20, i32 4, i1 false), !dbg !74 + %call16 = call i32 @f8(%struct.XYZ* byval %agg.tmp13), !dbg !74 + %tmp18 = bitcast %struct.XYZ* %agg.tmp17 to i8*, !dbg !75 + %tmp19 = bitcast %struct.XYZ* %abc to i8*, !dbg !75 + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp18, i8* %tmp19, i64 20, i32 4, i1 false), !dbg !75 + %call20 = call i32 @f9(%struct.XYZ* byval %agg.tmp17), !dbg !75 + %tmp22 = bitcast %struct.XYZ* %agg.tmp21 to i8*, !dbg !76 + %tmp23 = bitcast %struct.XYZ* %abc to i8*, !dbg !76 + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp22, i8* %tmp23, i64 20, i32 4, i1 false), !dbg !76 + %call24 = call i32 @f10(%struct.XYZ* byval %agg.tmp21), !dbg !76 + ret i32 0, !dbg !77 +} + +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind + +!llvm.dbg.sp = !{!0, !6, !7, !8, !9, !10, !11, !12, !13, !14, !15} + +!0 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f1", metadata !"f1", metadata !"f1", metadata !1, i32 11, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f1} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 524329, metadata !"arg.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 524305, i32 0, i32 12, metadata !"arg.c", metadata !"/private/tmp", metadata !"clang version 2.8 (trunk 112967)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{metadata !5} +!5 = metadata !{i32 524324, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f2", metadata !"f2", metadata !"f2", metadata !1, i32 12, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f2} ; [ DW_TAG_subprogram ] +!7 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f3", metadata !"f3", metadata !"f3", metadata !1, i32 13, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f3} ; [ DW_TAG_subprogram ] +!8 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f4", metadata !"f4", metadata !"f4", metadata !1, i32 14, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f4} ; [ DW_TAG_subprogram ] +!9 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f5", metadata !"f5", metadata !"f5", metadata !1, i32 15, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f5} ; [ DW_TAG_subprogram ] +!10 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f6", metadata !"f6", metadata !"f6", metadata !1, i32 16, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f6} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f7", metadata !"f7", metadata !"f7", metadata !1, i32 17, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f7} ; [ DW_TAG_subprogram ] +!12 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f8", metadata !"f8", metadata !"f8", metadata !1, i32 18, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f8} ; [ DW_TAG_subprogram ] +!13 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f9", metadata !"f9", metadata !"f9", metadata !1, i32 19, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f9} ; [ DW_TAG_subprogram ] +!14 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f10", metadata !"f10", metadata !"f10", metadata !1, i32 20, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f10} ; [ DW_TAG_subprogram ] +!15 = metadata !{i32 524334, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"main", metadata !1, i32 23, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @main} ; [ DW_TAG_subprogram ] +!16 = metadata !{i32 524545, metadata !0, metadata !"i", metadata !1, i32 11, metadata !5} ; [ DW_TAG_arg_variable ] +!17 = metadata !{i32 11, i32 12, metadata !0, null} +!18 = metadata !{i32 11, i32 17, metadata !19, null} +!19 = metadata !{i32 524299, metadata !0, i32 11, i32 15, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] +!20 = metadata !{i32 524545, metadata !6, metadata !"i", metadata !1, i32 12, metadata !5} ; [ DW_TAG_arg_variable ] +!21 = metadata !{i32 12, i32 12, metadata !6, null} +!22 = metadata !{i32 12, i32 17, metadata !23, null} +!23 = metadata !{i32 524299, metadata !6, i32 12, i32 15, metadata !1, i32 1} ; [ DW_TAG_lexical_block ] +!24 = metadata !{i32 524545, metadata !7, metadata !"i", metadata !1, i32 13, metadata !5} ; [ DW_TAG_arg_variable ] +!25 = metadata !{i32 13, i32 12, metadata !7, null} +!26 = metadata !{i32 13, i32 17, metadata !27, null} +!27 = metadata !{i32 524299, metadata !7, i32 13, i32 15, metadata !1, i32 2} ; [ DW_TAG_lexical_block ] +!28 = metadata !{i32 524545, metadata !8, metadata !"i", metadata !1, i32 14, metadata !5} ; [ DW_TAG_arg_variable ] +!29 = metadata !{i32 14, i32 12, metadata !8, null} +!30 = metadata !{i32 14, i32 17, metadata !31, null} +!31 = metadata !{i32 524299, metadata !8, i32 14, i32 15, metadata !1, i32 3} ; [ DW_TAG_lexical_block ] +!32 = metadata !{i32 524545, metadata !9, metadata !"i", metadata !1, i32 15, metadata !5} ; [ DW_TAG_arg_variable ] +!33 = metadata !{i32 15, i32 12, metadata !9, null} +!34 = metadata !{i32 15, i32 17, metadata !35, null} +!35 = metadata !{i32 524299, metadata !9, i32 15, i32 15, metadata !1, i32 4} ; [ DW_TAG_lexical_block ] +!36 = metadata !{i32 524545, metadata !10, metadata !"i", metadata !1, i32 16, metadata !5} ; [ DW_TAG_arg_variable ] +!37 = metadata !{i32 16, i32 12, metadata !10, null} +!38 = metadata !{i32 16, i32 17, metadata !39, null} +!39 = metadata !{i32 524299, metadata !10, i32 16, i32 15, metadata !1, i32 5} ; [ DW_TAG_lexical_block ] +!40 = metadata !{i32 524545, metadata !11, metadata !"i", metadata !1, i32 17, metadata !41} ; [ DW_TAG_arg_variable ] +!41 = metadata !{i32 524307, metadata !1, metadata !"XYZ", metadata !1, i32 2, i64 160, i64 32, i64 0, i32 0, null, metadata !42, i32 0, null} ; [ DW_TAG_structure_type ] +!42 = metadata !{metadata !43, metadata !44, metadata !45, metadata !46, metadata !47} +!43 = metadata !{i32 524301, metadata !1, metadata !"x", metadata !1, i32 3, i64 32, i64 32, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] +!44 = metadata !{i32 524301, metadata !1, metadata !"y", metadata !1, i32 4, i64 32, i64 32, i64 32, i32 0, metadata !5} ; [ DW_TAG_member ] +!45 = metadata !{i32 524301, metadata !1, metadata !"z", metadata !1, i32 5, i64 32, i64 32, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] +!46 = metadata !{i32 524301, metadata !1, metadata !"a", metadata !1, i32 6, i64 32, i64 32, i64 96, i32 0, metadata !5} ; [ DW_TAG_member ] +!47 = metadata !{i32 524301, metadata !1, metadata !"b", metadata !1, i32 7, i64 32, i64 32, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] +!48 = metadata !{i32 17, i32 19, metadata !11, null} +!49 = metadata !{i32 17, i32 24, metadata !50, null} +!50 = metadata !{i32 524299, metadata !11, i32 17, i32 22, metadata !1, i32 6} ; [ DW_TAG_lexical_block ] +!51 = metadata !{i32 524545, metadata !12, metadata !"i", metadata !1, i32 18, metadata !41} ; [ DW_TAG_arg_variable ] +!52 = metadata !{i32 18, i32 19, metadata !12, null} +!53 = metadata !{i32 18, i32 24, metadata !54, null} +!54 = metadata !{i32 524299, metadata !12, i32 18, i32 22, metadata !1, i32 7} ; [ DW_TAG_lexical_block ] +!55 = metadata !{i32 524545, metadata !13, metadata !"i", metadata !1, i32 19, metadata !41} ; [ DW_TAG_arg_variable ] +!56 = metadata !{i32 19, i32 19, metadata !13, null} +!57 = metadata !{i32 19, i32 24, metadata !58, null} +!58 = metadata !{i32 524299, metadata !13, i32 19, i32 22, metadata !1, i32 8} ; [ DW_TAG_lexical_block ] +!59 = metadata !{i32 524545, metadata !14, metadata !"i", metadata !1, i32 20, metadata !41} ; [ DW_TAG_arg_variable ] +!60 = metadata !{i32 20, i32 20, metadata !14, null} +!61 = metadata !{i32 20, i32 25, metadata !62, null} +!62 = metadata !{i32 524299, metadata !14, i32 20, i32 23, metadata !1, i32 9} ; [ DW_TAG_lexical_block ] +!63 = metadata !{i32 24, i32 3, metadata !64, null} +!64 = metadata !{i32 524299, metadata !15, i32 23, i32 12, metadata !1, i32 10} ; [ DW_TAG_lexical_block ] +!65 = metadata !{i32 25, i32 3, metadata !64, null} +!66 = metadata !{i32 26, i32 3, metadata !64, null} +!67 = metadata !{i32 27, i32 3, metadata !64, null} +!68 = metadata !{i32 28, i32 3, metadata !64, null} +!69 = metadata !{i32 29, i32 3, metadata !64, null} +!70 = metadata !{i32 524544, metadata !64, metadata !"abc", metadata !1, i32 30, metadata !41} ; [ DW_TAG_auto_variable ] +!71 = metadata !{i32 30, i32 14, metadata !64, null} +!72 = metadata !{i32 30, i32 17, metadata !64, null} +!73 = metadata !{i32 31, i32 3, metadata !64, null} +!74 = metadata !{i32 32, i32 3, metadata !64, null} +!75 = metadata !{i32 33, i32 3, metadata !64, null} +!76 = metadata !{i32 34, i32 3, metadata !64, null} +!77 = metadata !{i32 36, i32 3, metadata !64, null} From jan_sjodin at yahoo.com Tue Sep 7 13:10:17 2010 From: jan_sjodin at yahoo.com (Jan Sjodin) Date: Tue, 7 Sep 2010 11:10:17 -0700 (PDT) Subject: [llvm-commits] InitializeNativeAsmPrinter implementation In-Reply-To: <8888711F-1CCE-4D57-8B1D-95D9F9DADDA7@apple.com> References: <318832.28864.qm@web55601.mail.re4.yahoo.com> <8888711F-1CCE-4D57-8B1D-95D9F9DADDA7@apple.com> Message-ID: <192297.66340.qm@web55601.mail.re4.yahoo.com> This patch was applied (with modifications) in r109996, is this what is causing the problem? Thanks, Jan ----- Original Message ---- > From: Chris Lattner > To: Jan Sjodin > Cc: llvm-commits at cs.uiuc.edu; Olivier Meurant > Sent: Mon, September 6, 2010 6:09:25 AM > Subject: Re: [llvm-commits] InitializeNativeAsmPrinter implementation > > > On Jul 22, 2010, at 8:50 AM, Jan Sjodin wrote: > > > This patch is to prepare for MCJIT. I had to normalized the names for > > the initializers to have "Target" in the name to be able to use the > > LLVM_NATIVE_ARCH in the macros. > > Hi Jan, > > This patch applies but doesn't build correctly: > > In file included from EDDisassembler.cpp:37: > /Volumes/Data/Users/sabre/llvm/include/llvm/Target/TargetSelect.h:123:5: error: > > ? ? ? use of undeclared identifier 'LLVMInitializeX86AsmPrinter'; did you mean > ? ? ? 'LLVMInitializeX86TargetAsmPrinter'? > ? ? LLVM_NATIVE_ASMPRINTER(); > ? ? ^~~~~~~~~~~~~~~~~~~~~~ > > > Can you update it for mainline? > > -Chris From dalej at apple.com Tue Sep 7 13:10:56 2010 From: dalej at apple.com (Dale Johannesen) Date: Tue, 07 Sep 2010 18:10:56 -0000 Subject: [llvm-commits] [llvm] r113233 - in /llvm/trunk: include/llvm/IntrinsicsX86.td lib/Target/X86/X86InstrMMX.td lib/Target/X86/X86InstrSSE.td utils/TableGen/X86RecognizableInstr.cpp Message-ID: <20100907181056.B37B72A6C12C@llvm.org> Author: johannes Date: Tue Sep 7 13:10:56 2010 New Revision: 113233 URL: http://llvm.org/viewvc/llvm-project?rev=113233&view=rev Log: Add patterns for MMX that use the new intrinsics. Enable palignr intrinsic. These may need adjustment for a new VT in due course. Modified: llvm/trunk/include/llvm/IntrinsicsX86.td llvm/trunk/lib/Target/X86/X86InstrMMX.td llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp Modified: llvm/trunk/include/llvm/IntrinsicsX86.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsX86.td?rev=113233&r1=113232&r2=113233&view=diff ============================================================================== --- llvm/trunk/include/llvm/IntrinsicsX86.td (original) +++ llvm/trunk/include/llvm/IntrinsicsX86.td Tue Sep 7 13:10:56 2010 @@ -1570,9 +1570,9 @@ def int_x86_mmx_movnt_dq : GCCBuiltin<"__builtin_ia32_movntq">, Intrinsic<[], [llvm_ptr_ty, llvm_v1i64_ty], []>; -// def int_x86_mmx_palignr_b : GCCBuiltin<"__builtin_ia32_palignr">, -// Intrinsic<[llvm_v1i64_ty], [llvm_1i64_ty, -// llvm_v1i64_ty, llvm_i8_ty], [IntrNoMem]>; + def int_x86_mmx_palignr_b : GCCBuiltin<"__builtin_ia32_palignr">, + Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty, + llvm_v1i64_ty, llvm_i8_ty], [IntrNoMem]>; def int_x86_mmx_pextr_w : Intrinsic<[llvm_i32_ty], [llvm_v1i64_ty, llvm_i32_ty], Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrMMX.td?rev=113233&r1=113232&r2=113233&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrMMX.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrMMX.td Tue Sep 7 13:10:56 2010 @@ -18,7 +18,7 @@ //===----------------------------------------------------------------------===// let Constraints = "$src1 = $dst" in { - // MMXI_binop_rm - Simple MMX binary operator. + // MMXI_binop_rm - Simple MMX binary operator based on llvm operator. multiclass MMXI_binop_rm opc, string OpcodeStr, SDNode OpNode, ValueType OpVT, bit Commutable = 0> { def rr : MMXI; } + // MMXI_binop_rm_int - Simple MMX binary operator based on intrinsic. multiclass MMXI_binop_rm_int opc, string OpcodeStr, Intrinsic IntId, bit Commutable = 0> { def rr : MMXI; } + // MMXI_binop_rm_int2 - Simple MMX binary operator based on intrinsic, with a + // different name for the generated instructions than MMXI_binop_rm uses. + // Thus int2 and rm can coexist for different implementations of the same + // instruction, while int and rm cannot. This is temporary during transition + // to intrinsic-only implementation. When it is removed, remove the FIXME + // from X86RecognizableInstr.cpp. + multiclass MMXI_binop_rm_int2 opc, string OpcodeStr, Intrinsic IntId, + bit Commutable = 0> { + def irr : MMXI { + let isCommutable = Commutable; + } + def irm : MMXI; + } + // MMXI_binop_rm_v1i64 - Simple MMX binary operator whose type is v1i64. // // FIXME: we could eliminate this and use MMXI_binop_rm instead if tblgen knew @@ -188,11 +210,14 @@ // Arithmetic Instructions // -- Addition -defm MMX_PADDB : MMXI_binop_rm<0xFC, "paddb", add, v8i8, 1>; -defm MMX_PADDW : MMXI_binop_rm<0xFD, "paddw", add, v4i16, 1>; -defm MMX_PADDD : MMXI_binop_rm<0xFE, "paddd", add, v2i32, 1>; -defm MMX_PADDQ : MMXI_binop_rm<0xD4, "paddq", add, v1i64, 1>; - +defm MMX_PADDB : MMXI_binop_rm<0xFC, "paddb", add, v8i8, 1>, + MMXI_binop_rm_int2<0xFC, "paddb", int_x86_mmx_padd_b, 1>; +defm MMX_PADDW : MMXI_binop_rm<0xFD, "paddw", add, v4i16, 1>, + MMXI_binop_rm_int2<0xFD, "paddw", int_x86_mmx_padd_w, 1>; +defm MMX_PADDD : MMXI_binop_rm<0xFE, "paddd", add, v2i32, 1>, + MMXI_binop_rm_int2<0xFE, "paddd", int_x86_mmx_padd_d, 1>; +defm MMX_PADDQ : MMXI_binop_rm<0xD4, "paddq", add, v1i64, 1>, + MMXI_binop_rm_int2<0xD4, "paddq", int_x86_mmx_padd_q, 1>; defm MMX_PADDSB : MMXI_binop_rm_int<0xEC, "paddsb" , int_x86_mmx_padds_b, 1>; defm MMX_PADDSW : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w, 1>; @@ -200,10 +225,14 @@ defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w, 1>; // -- Subtraction -defm MMX_PSUBB : MMXI_binop_rm<0xF8, "psubb", sub, v8i8>; -defm MMX_PSUBW : MMXI_binop_rm<0xF9, "psubw", sub, v4i16>; -defm MMX_PSUBD : MMXI_binop_rm<0xFA, "psubd", sub, v2i32>; -defm MMX_PSUBQ : MMXI_binop_rm<0xFB, "psubq", sub, v1i64>; +defm MMX_PSUBB : MMXI_binop_rm<0xF8, "psubb", sub, v8i8>, + MMXI_binop_rm_int2<0xF8, "psubb", int_x86_mmx_psub_b>; +defm MMX_PSUBW : MMXI_binop_rm<0xF9, "psubw", sub, v4i16>, + MMXI_binop_rm_int2<0xF9, "psubw", int_x86_mmx_psub_w>; +defm MMX_PSUBD : MMXI_binop_rm<0xFA, "psubd", sub, v2i32>, + MMXI_binop_rm_int2<0xFA, "psubd", int_x86_mmx_psub_d>; +defm MMX_PSUBQ : MMXI_binop_rm<0xFB, "psubq", sub, v1i64>, + MMXI_binop_rm_int2<0xFB, "psubq", int_x86_mmx_psub_q>; defm MMX_PSUBSB : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b>; defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w>; @@ -212,7 +241,8 @@ defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w>; // -- Multiplication -defm MMX_PMULLW : MMXI_binop_rm<0xD5, "pmullw", mul, v4i16, 1>; +defm MMX_PMULLW : MMXI_binop_rm<0xD5, "pmullw", mul, v4i16, 1>, + MMXI_binop_rm_int2<0xD5, "pmullw", int_x86_mmx_pmull_w, 1>; defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw", int_x86_mmx_pmulh_w, 1>; defm MMX_PMULHUW : MMXI_binop_rm_int<0xE4, "pmulhuw", int_x86_mmx_pmulhu_w, 1>; @@ -233,9 +263,13 @@ defm MMX_PSADBW : MMXI_binop_rm_int<0xF6, "psadbw", int_x86_mmx_psad_bw, 1>; // Logical Instructions -defm MMX_PAND : MMXI_binop_rm_v1i64<0xDB, "pand", and, 1>; -defm MMX_POR : MMXI_binop_rm_v1i64<0xEB, "por" , or, 1>; -defm MMX_PXOR : MMXI_binop_rm_v1i64<0xEF, "pxor", xor, 1>; +defm MMX_PAND : MMXI_binop_rm_v1i64<0xDB, "pand", and, 1>, + MMXI_binop_rm_int2<0xDB, "pand", int_x86_mmx_pand, 1>; +defm MMX_POR : MMXI_binop_rm_v1i64<0xEB, "por" , or, 1>, + MMXI_binop_rm_int2<0xEB, "por" , int_x86_mmx_por, 1>; +defm MMX_PXOR : MMXI_binop_rm_v1i64<0xEF, "pxor", xor, 1>, + MMXI_binop_rm_int2<0xEF, "pxor", int_x86_mmx_pxor, 1>; +defm MMX_PANDN : MMXI_binop_rm_int2<0xDF, "pandn", int_x86_mmx_pandn, 1>; let Constraints = "$src1 = $dst" in { def MMX_PANDNrr : MMXI<0xDF, MRMSrcReg, @@ -363,6 +397,18 @@ (v2i32 (mmx_unpckl VR64:$src1, (bc_v2i32 (load_mmx addr:$src2)))))]>; } +defm MMX_PUNPCKHBW : MMXI_binop_rm_int2<0x68, "punpckhbw", + int_x86_mmx_punpckhbw>; +defm MMX_PUNPCKHWD : MMXI_binop_rm_int2<0x69, "punpckhwd", + int_x86_mmx_punpckhwd>; +defm MMX_PUNPCKHDQ : MMXI_binop_rm_int2<0x6A, "punpckhdq", + int_x86_mmx_punpckhdq>; +defm MMX_PUNPCKLBW : MMXI_binop_rm_int2<0x60, "punpcklbw", + int_x86_mmx_punpcklbw>; +defm MMX_PUNPCKLWD : MMXI_binop_rm_int2<0x61, "punpcklwd", + int_x86_mmx_punpcklwd>; +defm MMX_PUNPCKLDQ : MMXI_binop_rm_int2<0x62, "punpckldq", + int_x86_mmx_punpckldq>; // -- Pack Instructions defm MMX_PACKSSWB : MMXI_binop_rm_int<0x63, "packsswb", int_x86_mmx_packsswb>; Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=113233&r1=113232&r2=113233&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Sep 7 13:10:56 2010 @@ -3718,13 +3718,22 @@ // SSSE3 - Packed Align Instruction Patterns //===---------------------------------------------------------------------===// -multiclass ssse3_palign_mm { +multiclass ssse3_palign_mm { def R64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2, i8imm:$src3), !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>; def R64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2, i8imm:$src3), !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>; + def R64irr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst), + (ins VR64:$src1, VR64:$src2, i8imm:$src3), + !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), + [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2, (i8 imm:$src3)))]>; + def R64irm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst), + (ins VR64:$src1, i64mem:$src2, i8imm:$src3), + !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), + [(set VR64:$dst, (IntId VR64:$src1, + (bitconvert (load_mmx addr:$src2)), (i8 imm:$src3)))]>; } multiclass ssse3_palign { @@ -3748,7 +3757,7 @@ defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V; let Constraints = "$src1 = $dst" in defm PALIGN : ssse3_palign<"palignr">, - ssse3_palign_mm<"palignr">; + ssse3_palign_mm<"palignr", int_x86_mmx_palignr_b>; let AddedComplexity = 5 in { Modified: llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp?rev=113233&r1=113232&r2=113233&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp (original) +++ llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp Tue Sep 7 13:10:56 2010 @@ -311,7 +311,7 @@ return FILTER_STRONG; // Special cases. - + if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI") return FILTER_WEAK; if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI") @@ -368,6 +368,12 @@ (Name.find("to") != Name.npos))) return FILTER_WEAK; + // Filter out the intrinsic form of instructions that also have an llvm + // operator form. FIXME this is temporary. + if (Name.find("irm") != Name.npos || + Name.find("irr") != Name.npos) + return FILTER_WEAK; + return FILTER_NORMAL; } From nicholas at mxc.ca Tue Sep 7 13:14:24 2010 From: nicholas at mxc.ca (Nick Lewycky) Date: Tue, 07 Sep 2010 18:14:24 -0000 Subject: [llvm-commits] [llvm] r113235 - in /llvm/trunk: autoconf/ include/llvm/ADT/ lib/Support/ lib/Target/PTX/ lib/Target/PTX/AsmPrinter/ lib/Target/PTX/TargetInfo/ Message-ID: <20100907181424.715962A6C12C@llvm.org> Author: nicholas Date: Tue Sep 7 13:14:24 2010 New Revision: 113235 URL: http://llvm.org/viewvc/llvm-project?rev=113235&view=rev Log: Create PTX backend. Patch by Che-Liang Chiou! Added: llvm/trunk/lib/Target/PTX/ llvm/trunk/lib/Target/PTX/AsmPrinter/ llvm/trunk/lib/Target/PTX/AsmPrinter/CMakeLists.txt llvm/trunk/lib/Target/PTX/AsmPrinter/Makefile llvm/trunk/lib/Target/PTX/AsmPrinter/PTXAsmPrinter.cpp llvm/trunk/lib/Target/PTX/CMakeLists.txt llvm/trunk/lib/Target/PTX/Makefile llvm/trunk/lib/Target/PTX/PTX.h llvm/trunk/lib/Target/PTX/PTX.td llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp llvm/trunk/lib/Target/PTX/PTXTargetMachine.h llvm/trunk/lib/Target/PTX/TargetInfo/ llvm/trunk/lib/Target/PTX/TargetInfo/CMakeLists.txt llvm/trunk/lib/Target/PTX/TargetInfo/Makefile llvm/trunk/lib/Target/PTX/TargetInfo/PTXTargetInfo.cpp Modified: llvm/trunk/autoconf/configure.ac llvm/trunk/include/llvm/ADT/Triple.h llvm/trunk/lib/Support/Triple.cpp Modified: llvm/trunk/autoconf/configure.ac URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=113235&r1=113234&r2=113235&view=diff ============================================================================== --- llvm/trunk/autoconf/configure.ac (original) +++ llvm/trunk/autoconf/configure.ac Tue Sep 7 13:14:24 2010 @@ -332,6 +332,7 @@ s390x-*) llvm_cv_target_arch="SystemZ" ;; bfin-*) llvm_cv_target_arch="Blackfin" ;; mblaze-*) llvm_cv_target_arch="MBlaze" ;; + ptx-*) llvm_cv_target_arch="PTX" ;; *) llvm_cv_target_arch="Unknown" ;; esac]) @@ -469,6 +470,7 @@ SystemZ) AC_SUBST(TARGET_HAS_JIT,0) ;; Blackfin) AC_SUBST(TARGET_HAS_JIT,0) ;; MBlaze) AC_SUBST(TARGET_HAS_JIT,0) ;; + PTX) AC_SUBST(TARGET_HAS_JIT,0) ;; *) AC_SUBST(TARGET_HAS_JIT,0) ;; esac fi @@ -543,13 +545,13 @@ AC_ARG_ENABLE([targets],AS_HELP_STRING([--enable-targets], [Build specific host targets: all or target1,target2,... Valid targets are: host, x86, x86_64, sparc, powerpc, alpha, arm, mips, spu, pic16, - xcore, msp430, systemz, blackfin, cbe, and cpp (default=all)]),, + xcore, msp430, systemz, blackfin, ptx, cbe, and cpp (default=all)]),, enableval=all) if test "$enableval" = host-only ; then enableval=host fi case "$enableval" in - all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha ARM Mips CellSPU PIC16 XCore MSP430 SystemZ Blackfin CBackend CppBackend MBlaze" ;; + all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha ARM Mips CellSPU PIC16 XCore MSP430 SystemZ Blackfin CBackend CppBackend MBlaze PTX" ;; *)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do case "$a_target" in x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;; @@ -568,6 +570,7 @@ cbe) TARGETS_TO_BUILD="CBackend $TARGETS_TO_BUILD" ;; cpp) TARGETS_TO_BUILD="CppBackend $TARGETS_TO_BUILD" ;; mblaze) TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;; + ptx) TARGETS_TO_BUILD="PTX $TARGETS_TO_BUILD" ;; host) case "$llvm_cv_target_arch" in x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;; x86_64) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;; @@ -583,6 +586,7 @@ MSP430) TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;; s390x) TARGETS_TO_BUILD="SystemZ $TARGETS_TO_BUILD" ;; Blackfin) TARGETS_TO_BUILD="Blackfin $TARGETS_TO_BUILD" ;; + PTX) TARGETS_TO_BUILD="PTX $TARGETS_TO_BUILD" ;; *) AC_MSG_ERROR([Can not set target to build]) ;; esac ;; *) AC_MSG_ERROR([Unrecognized target $a_target]) ;; Modified: llvm/trunk/include/llvm/ADT/Triple.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/Triple.h?rev=113235&r1=113234&r2=113235&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/Triple.h (original) +++ llvm/trunk/include/llvm/ADT/Triple.h Tue Sep 7 13:14:24 2010 @@ -65,6 +65,7 @@ x86_64, // X86-64: amd64, x86_64 xcore, // XCore: xcore mblaze, // MBlaze: mblaze + ptx, // PTX: ptx InvalidArch }; Modified: llvm/trunk/lib/Support/Triple.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Triple.cpp?rev=113235&r1=113234&r2=113235&view=diff ============================================================================== --- llvm/trunk/lib/Support/Triple.cpp (original) +++ llvm/trunk/lib/Support/Triple.cpp Tue Sep 7 13:14:24 2010 @@ -41,6 +41,7 @@ case x86_64: return "x86_64"; case xcore: return "xcore"; case mblaze: return "mblaze"; + case ptx: return "ptx"; } return ""; @@ -70,7 +71,10 @@ case x86: case x86_64: return "x86"; + case xcore: return "xcore"; + + case ptx: return "ptx"; } } @@ -149,6 +153,8 @@ return x86_64; if (Name == "xcore") return xcore; + if (Name == "ptx") + return ptx; return UnknownArch; } @@ -187,6 +193,9 @@ Str == "armv6" || Str == "armv7") return Triple::arm; + if (Str == "ptx") + return Triple::ptx; + return Triple::UnknownArch; } @@ -216,6 +225,8 @@ return "armv6"; if (Str == "armv7" || Str == "thumbv7") return "armv7"; + if (Str == "ptx") + return "ptx"; return NULL; } @@ -266,6 +277,8 @@ return tce; else if (ArchName == "xcore") return xcore; + else if (ArchName == "ptx") + return ptx; else return UnknownArch; } Added: llvm/trunk/lib/Target/PTX/AsmPrinter/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/AsmPrinter/CMakeLists.txt?rev=113235&view=auto ============================================================================== --- llvm/trunk/lib/Target/PTX/AsmPrinter/CMakeLists.txt (added) +++ llvm/trunk/lib/Target/PTX/AsmPrinter/CMakeLists.txt Tue Sep 7 13:14:24 2010 @@ -0,0 +1,6 @@ +include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. ${CMAKE_CURRENT_SOURCE_DIR}/.. ) + +add_llvm_library(LLVMPTXAsmPrinter + PTXAsmPrinter.cpp + ) +add_dependencies(LLVMPTXAsmPrinter PTXCodeGenTable_gen) Added: llvm/trunk/lib/Target/PTX/AsmPrinter/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/AsmPrinter/Makefile?rev=113235&view=auto ============================================================================== --- llvm/trunk/lib/Target/PTX/AsmPrinter/Makefile (added) +++ llvm/trunk/lib/Target/PTX/AsmPrinter/Makefile Tue Sep 7 13:14:24 2010 @@ -0,0 +1,15 @@ +##===- lib/Target/PTX/AsmPrinter/Makefile ------------------*- Makefile -*-===## +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open Source +# License. See LICENSE.TXT for details. +# +##===----------------------------------------------------------------------===## +LEVEL = ../../../.. +LIBRARYNAME = LLVMPTXAsmPrinter + +# Hack: we need to include 'main' PTX target directory to grab private headers +CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/.. + +include $(LEVEL)/Makefile.common Added: llvm/trunk/lib/Target/PTX/AsmPrinter/PTXAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/AsmPrinter/PTXAsmPrinter.cpp?rev=113235&view=auto ============================================================================== --- llvm/trunk/lib/Target/PTX/AsmPrinter/PTXAsmPrinter.cpp (added) +++ llvm/trunk/lib/Target/PTX/AsmPrinter/PTXAsmPrinter.cpp Tue Sep 7 13:14:24 2010 @@ -0,0 +1,35 @@ +//===-- PTXAsmPrinter.cpp - PTX LLVM assembly writer ----------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains a printer that converts from our internal representation +// of machine-dependent LLVM code to PTX assembly language. +// +//===----------------------------------------------------------------------===// + +#include "PTX.h" +#include "PTXTargetMachine.h" +#include "llvm/CodeGen/AsmPrinter.h" +#include "llvm/Target/TargetRegistry.h" + +using namespace llvm; + +namespace { + class PTXAsmPrinter : public AsmPrinter { + public: + explicit PTXAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) : + AsmPrinter(TM, Streamer) {} + const char *getPassName() const { return "PTX Assembly Printer"; } + }; +} // namespace + +// Force static initialization. +extern "C" void LLVMInitializePTXAsmPrinter() +{ + RegisterAsmPrinter X(ThePTXTarget); +} Added: llvm/trunk/lib/Target/PTX/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/CMakeLists.txt?rev=113235&view=auto ============================================================================== --- llvm/trunk/lib/Target/PTX/CMakeLists.txt (added) +++ llvm/trunk/lib/Target/PTX/CMakeLists.txt Tue Sep 7 13:14:24 2010 @@ -0,0 +1,6 @@ +set(LLVM_TARGET_DEFINITIONS PTX.td) + +add_llvm_target(PTXCodeGen + ) + +target_link_libraries (LLVMPTXCodeGen LLVMSelectionDAG) Added: llvm/trunk/lib/Target/PTX/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/Makefile?rev=113235&view=auto ============================================================================== --- llvm/trunk/lib/Target/PTX/Makefile (added) +++ llvm/trunk/lib/Target/PTX/Makefile Tue Sep 7 13:14:24 2010 @@ -0,0 +1,19 @@ +##===- lib/Target/PTX/Makefile -----------------------------*- Makefile -*-===## +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open Source +# License. See LICENSE.TXT for details. +# +##===----------------------------------------------------------------------===## + +LEVEL = ../../.. +LIBRARYNAME = LLVMPTXCodeGen +TARGET = PTX + +# Make sure that tblgen is run, first thing. +BUILT_SOURCES = + +DIRS = AsmPrinter TargetInfo + +include $(LEVEL)/Makefile.common Added: llvm/trunk/lib/Target/PTX/PTX.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTX.h?rev=113235&view=auto ============================================================================== --- llvm/trunk/lib/Target/PTX/PTX.h (added) +++ llvm/trunk/lib/Target/PTX/PTX.h Tue Sep 7 13:14:24 2010 @@ -0,0 +1,24 @@ +//===-- PTX.h - Top-level interface for PTX representation ------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the entry points for global functions defined in the LLVM +// PTX back-end. +// +//===----------------------------------------------------------------------===// + +#ifndef PTX_H +#define PTX_H + +#include "llvm/Target/TargetMachine.h" + +namespace llvm { + extern Target ThePTXTarget; +} // namespace llvm; + +#endif // PTX_H Added: llvm/trunk/lib/Target/PTX/PTX.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTX.td?rev=113235&view=auto ============================================================================== --- llvm/trunk/lib/Target/PTX/PTX.td (added) +++ llvm/trunk/lib/Target/PTX/PTX.td Tue Sep 7 13:14:24 2010 @@ -0,0 +1,10 @@ +//===- PTX.td - Describe the PTX Target Machine ---------------*- tblgen -*-==// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// This is the top level entry point for the PTX target. +//===----------------------------------------------------------------------===// Added: llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp?rev=113235&view=auto ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp (added) +++ llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp Tue Sep 7 13:14:24 2010 @@ -0,0 +1,31 @@ +//===-- PTXTargetMachine.cpp - Define TargetMachine for PTX ---------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// Top-level implementation for the PTX target. +// +//===----------------------------------------------------------------------===// + +#include "PTX.h" +#include "PTXTargetMachine.h" +#include "llvm/Target/TargetRegistry.h" + +using namespace llvm; + +extern "C" void LLVMInitializePTXTarget() +{ + // Register the target + RegisterTargetMachine X(ThePTXTarget); +} + +PTXTargetMachine::PTXTargetMachine(const Target &T, + const std::string &TT, + const std::string &FS) : + LLVMTargetMachine(T, TT) +{ +} Added: llvm/trunk/lib/Target/PTX/PTXTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXTargetMachine.h?rev=113235&view=auto ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXTargetMachine.h (added) +++ llvm/trunk/lib/Target/PTX/PTXTargetMachine.h Tue Sep 7 13:14:24 2010 @@ -0,0 +1,27 @@ +//===-- PTXTargetMachine.h - Define TargetMachine for PTX -------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file declares the PTX specific subclass of TargetMachine. +// +//===----------------------------------------------------------------------===// + +#ifndef PTX_TARGET_MACHINE_H +#define PTX_TARGET_MACHINE_H + +#include "llvm/Target/TargetMachine.h" + +namespace llvm { + class PTXTargetMachine : public LLVMTargetMachine { + public: + PTXTargetMachine(const Target &T, const std::string &TT, + const std::string &FS); + }; // class PTXTargetMachine +} // namespace llvm + +#endif // PTX_TARGET_MACHINE_H Added: llvm/trunk/lib/Target/PTX/TargetInfo/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/TargetInfo/CMakeLists.txt?rev=113235&view=auto ============================================================================== --- llvm/trunk/lib/Target/PTX/TargetInfo/CMakeLists.txt (added) +++ llvm/trunk/lib/Target/PTX/TargetInfo/CMakeLists.txt Tue Sep 7 13:14:24 2010 @@ -0,0 +1,7 @@ +include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. ${CMAKE_CURRENT_SOURCE_DIR}/.. ) + +add_llvm_library(LLVMPTXInfo + PTXTargetInfo.cpp + ) + +add_dependencies(LLVMPTXInfo PTXCodeGenTable_gen) Added: llvm/trunk/lib/Target/PTX/TargetInfo/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/TargetInfo/Makefile?rev=113235&view=auto ============================================================================== --- llvm/trunk/lib/Target/PTX/TargetInfo/Makefile (added) +++ llvm/trunk/lib/Target/PTX/TargetInfo/Makefile Tue Sep 7 13:14:24 2010 @@ -0,0 +1,15 @@ +##===- lib/Target/PTX/TargetInfo/Makefile ------------------*- Makefile -*-===## +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open Source +# License. See LICENSE.TXT for details. +# +##===----------------------------------------------------------------------===## +LEVEL = ../../../.. +LIBRARYNAME = LLVMPTXInfo + +# Hack: we need to include 'main' target directory to grab private headers +CPPFLAGS = -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/.. + +include $(LEVEL)/Makefile.common Added: llvm/trunk/lib/Target/PTX/TargetInfo/PTXTargetInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/TargetInfo/PTXTargetInfo.cpp?rev=113235&view=auto ============================================================================== --- llvm/trunk/lib/Target/PTX/TargetInfo/PTXTargetInfo.cpp (added) +++ llvm/trunk/lib/Target/PTX/TargetInfo/PTXTargetInfo.cpp Tue Sep 7 13:14:24 2010 @@ -0,0 +1,22 @@ +//===-- PTXTargetInfo.cpp - PTX Target Implementation ---------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "PTX.h" +#include "llvm/Module.h" +#include "llvm/Target/TargetRegistry.h" + +using namespace llvm; + +Target llvm::ThePTXTarget; + +extern "C" void LLVMInitializePTXTargetInfo() +{ + // see llvm/ADT/Triple.h + RegisterTarget X(ThePTXTarget, "ptx", "PTX"); +} From nicholas at mxc.ca Tue Sep 7 13:14:42 2010 From: nicholas at mxc.ca (Nick Lewycky) Date: Tue, 07 Sep 2010 18:14:42 -0000 Subject: [llvm-commits] [llvm] r113236 - /llvm/trunk/configure Message-ID: <20100907181443.115C72A6C12C@llvm.org> Author: nicholas Date: Tue Sep 7 13:14:42 2010 New Revision: 113236 URL: http://llvm.org/viewvc/llvm-project?rev=113236&view=rev Log: Update configure for change to autoconf/configure.ac to add PTX backend. Modified: llvm/trunk/configure Modified: llvm/trunk/configure URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/configure?rev=113236&r1=113235&r2=113236&view=diff ============================================================================== --- llvm/trunk/configure (original) +++ llvm/trunk/configure Tue Sep 7 13:14:42 2010 @@ -1414,8 +1414,8 @@ --enable-targets Build specific host targets: all or target1,target2,... Valid targets are: host, x86, x86_64, sparc, powerpc, alpha, arm, mips, spu, - pic16, xcore, msp430, systemz, blackfin, cbe, and - cpp (default=all) + pic16, xcore, msp430, systemz, blackfin, ptx, cbe, + and cpp (default=all) --enable-cbe-printf-a Enable C Backend output with hex floating point via %a (default is YES) --enable-bindings Build specific language bindings: @@ -2361,6 +2361,7 @@ s390x-*) llvm_cv_target_arch="SystemZ" ;; bfin-*) llvm_cv_target_arch="Blackfin" ;; mblaze-*) llvm_cv_target_arch="MBlaze" ;; + ptx-*) llvm_cv_target_arch="PTX" ;; *) llvm_cv_target_arch="Unknown" ;; esac fi @@ -4828,6 +4829,8 @@ ;; MBlaze) TARGET_HAS_JIT=0 ;; + PTX) TARGET_HAS_JIT=0 + ;; *) TARGET_HAS_JIT=0 ;; esac @@ -4955,7 +4958,7 @@ enableval=host fi case "$enableval" in - all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha ARM Mips CellSPU PIC16 XCore MSP430 SystemZ Blackfin CBackend CppBackend MBlaze" ;; + all) TARGETS_TO_BUILD="X86 Sparc PowerPC Alpha ARM Mips CellSPU PIC16 XCore MSP430 SystemZ Blackfin CBackend CppBackend MBlaze PTX" ;; *)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do case "$a_target" in x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;; @@ -4974,6 +4977,7 @@ cbe) TARGETS_TO_BUILD="CBackend $TARGETS_TO_BUILD" ;; cpp) TARGETS_TO_BUILD="CppBackend $TARGETS_TO_BUILD" ;; mblaze) TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;; + ptx) TARGETS_TO_BUILD="PTX $TARGETS_TO_BUILD" ;; host) case "$llvm_cv_target_arch" in x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;; x86_64) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;; @@ -4989,6 +4993,7 @@ MSP430) TARGETS_TO_BUILD="MSP430 $TARGETS_TO_BUILD" ;; s390x) TARGETS_TO_BUILD="SystemZ $TARGETS_TO_BUILD" ;; Blackfin) TARGETS_TO_BUILD="Blackfin $TARGETS_TO_BUILD" ;; + PTX) TARGETS_TO_BUILD="PTX $TARGETS_TO_BUILD" ;; *) { { echo "$as_me:$LINENO: error: Can not set target to build" >&5 echo "$as_me: error: Can not set target to build" >&2;} { (exit 1); exit 1; }; } ;; @@ -11389,7 +11394,7 @@ lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext < Author: dpatel Date: Tue Sep 7 13:17:56 2010 New Revision: 113237 URL: http://llvm.org/viewvc/llvm-project?rev=113237&view=rev Log: Fix command line used to link these test cases. Modified: llvm/trunk/test/CodeGen/X86/dbg-declare-fastisel.ll llvm/trunk/test/CodeGen/X86/dbg-declare-hybrid.ll llvm/trunk/test/CodeGen/X86/dbg-declare-isel.ll Modified: llvm/trunk/test/CodeGen/X86/dbg-declare-fastisel.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-declare-fastisel.ll?rev=113237&r1=113236&r2=113237&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/dbg-declare-fastisel.ll (original) +++ llvm/trunk/test/CodeGen/X86/dbg-declare-fastisel.ll Tue Sep 7 13:17:56 2010 @@ -1,7 +1,7 @@ ; This test case checks handling of llvm.dbg.declare intrinsic during fast-isel. ; RUN: llc -mtriple=x86_64-apple-darwin --disable-fp-elim -O0 %s -o %t.s ; RUN: %compile_c -m64 %t.s -o %t.o -; RUN: %link %t.o -o %t.exe +; RUN: %link -m64 %t.o -o %t.exe ; RUN: echo {break f1\n break f2 \n break f3 \n break f5 \n break f9 \n run \n p i \n c \n p i\n c \n p i\n c \n p i\n c \n p i.x} > %t.in ; RUN: gdb -q -batch -n -x %t.in %t.exe >& %t.out ; RUN: grep "1 = 42" %t.out Modified: llvm/trunk/test/CodeGen/X86/dbg-declare-hybrid.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-declare-hybrid.ll?rev=113237&r1=113236&r2=113237&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/dbg-declare-hybrid.ll (original) +++ llvm/trunk/test/CodeGen/X86/dbg-declare-hybrid.ll Tue Sep 7 13:17:56 2010 @@ -2,7 +2,7 @@ ; using fast-isel but switch back to DAG building at some point. ; RUN: llc -mtriple=x86_64-apple-darwin --disable-fp-elim -O0 %s -o %t.s ; RUN: %compile_c -m64 %t.s -o %t.o -; RUN: %link %t.o -o %t.exe +; RUN: %link -m64 %t.o -o %t.exe ; RUN: echo {break f1\n break f4\n break f5\n run \n p i\n c \n p i\n c \n p i\n} > %t.in ; RUN: gdb -q -batch -n -x %t.in %t.exe >& %t.out ; RUN: grep "1 = 42" %t.out Modified: llvm/trunk/test/CodeGen/X86/dbg-declare-isel.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-declare-isel.ll?rev=113237&r1=113236&r2=113237&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/dbg-declare-isel.ll (original) +++ llvm/trunk/test/CodeGen/X86/dbg-declare-isel.ll Tue Sep 7 13:17:56 2010 @@ -1,7 +1,7 @@ ; This test case checks handling of llvm.dbg.declare intrinsic during isel. ; RUN: llc -mtriple=x86_64-apple-darwin --disable-fp-elim -O0 -fast-isel=false %s -o %t.s ; RUN: %compile_c -m64 %t.s -o %t.o -; RUN: %link %t.o -o %t.exe +; RUN: %link -m64 %t.o -o %t.exe ; RUN: echo {break f1\n break f2 \n break f7 \n break f8 \n break f9 \n break f10 \n run \n p i\n c \n p i\n c \n p i.x\n c \n p i.x\n c \n p i.x \n c \n p i.x \n} > %t.in ; RUN: gdb -q -batch -n -x %t.in %t.exe >& %t.out ; RUN: grep "1 = 42" %t.out From echristo at apple.com Tue Sep 7 13:22:07 2010 From: echristo at apple.com (Eric Christopher) Date: Tue, 7 Sep 2010 11:22:07 -0700 Subject: [llvm-commits] [PATCH] GNU ld win32 should not accept version script In-Reply-To: References: Message-ID: <98FC6E4A-5219-45BE-8787-C72372B505D7@apple.com> On Sep 6, 2010, at 7:03 AM, NAKAMURA Takumi wrote: > So this part I somewhat understand: +if test "$dynamic_linker" != "Win32 ld.exe" ; then + dnl Determine whether the linker supports the --version-script option. + AC_LINK_VERSION_SCRIPT +fi Though it'd probably be better to do a test similar to AC_PROG_GNU_LD to instead check for WIN32_LD. That said, what's with the moving of AC_LIBTOOL_DLOPEN AND AC_LIB_LTDL? -eric From bruno.cardoso at gmail.com Tue Sep 7 13:24:00 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 07 Sep 2010 18:24:00 -0000 Subject: [llvm-commits] [llvm] r113239 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20100907182400.AC1CC2A6C12C@llvm.org> Author: bruno Date: Tue Sep 7 13:24:00 2010 New Revision: 113239 URL: http://llvm.org/viewvc/llvm-project?rev=113239&view=rev Log: Minor change. Since the checks are equivalent, use isMMX Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=113239&r1=113238&r2=113239&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Sep 7 13:24:00 2010 @@ -5475,7 +5475,7 @@ // Only a few shuffle masks are handled for 64-bit vectors (MMX), and // 64-bit vectors which made to this point can't be handled, they are // expanded. - if (VT.getSizeInBits() == 64) + if (isMMX) return SDValue(); if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) && From gohman at apple.com Tue Sep 7 13:26:49 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 07 Sep 2010 18:26:49 -0000 Subject: [llvm-commits] [llvm] r113240 - /llvm/trunk/lib/System/Unix/Path.inc Message-ID: <20100907182650.030862A6C12C@llvm.org> Author: djg Date: Tue Sep 7 13:26:49 2010 New Revision: 113240 URL: http://llvm.org/viewvc/llvm-project?rev=113240&view=rev Log: Issue a #error if the host doesn't have an implementation for GetMainExecutable yet. Modified: llvm/trunk/lib/System/Unix/Path.inc Modified: llvm/trunk/lib/System/Unix/Path.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Unix/Path.inc?rev=113240&r1=113239&r2=113240&view=diff ============================================================================== --- llvm/trunk/lib/System/Unix/Path.inc (original) +++ llvm/trunk/lib/System/Unix/Path.inc Tue Sep 7 13:26:49 2010 @@ -372,6 +372,8 @@ char link_path[MAXPATHLEN]; if (realpath(DLInfo.dli_fname, link_path)) return Path(std::string(link_path)); +#else +#error GetMainExecutable is not implemented on this host yet. #endif return Path(); } From bruno.cardoso at gmail.com Tue Sep 7 13:29:03 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 07 Sep 2010 18:29:03 -0000 Subject: [llvm-commits] [llvm] r113242 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20100907182903.5CDDB2A6C12C@llvm.org> Author: bruno Date: Tue Sep 7 13:29:03 2010 New Revision: 113242 URL: http://llvm.org/viewvc/llvm-project?rev=113242&view=rev Log: Remove now useless check, because the code can be matched below, no need to leave it for isel Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=113242&r1=113241&r2=113242&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Sep 7 13:29:03 2010 @@ -5273,7 +5273,7 @@ // Promote splats to v4f32. if (SVOp->isSplat()) { - if (isMMX || NumElems < 4) + if (isMMX) return Op; return PromoteSplat(SVOp, DAG); } From bruno.cardoso at gmail.com Tue Sep 7 13:41:45 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 07 Sep 2010 18:41:45 -0000 Subject: [llvm-commits] [llvm] r113247 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20100907184146.13E0F2A6C12C@llvm.org> Author: bruno Date: Tue Sep 7 13:41:45 2010 New Revision: 113247 URL: http://llvm.org/viewvc/llvm-project?rev=113247&view=rev Log: decouple MMX check from regular splat checks. Some refactoring is coming, and MMX should be left alone to be easily removed after moving to intrinsics Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=113247&r1=113246&r2=113247&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Sep 7 13:41:45 2010 @@ -5271,12 +5271,16 @@ if (isZeroShuffle(SVOp)) return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); + // FIXME: this is somehow handled during isel by MMX pattern fragments. Remove + // the check or come up with another solution when all MMX move to intrinsics, + // but don't allow this to be considered legal, we don't want vector_shuffle + // operations to be matched during isel anymore. + if (isMMX && SVOp->isSplat()) + return Op; + // Promote splats to v4f32. - if (SVOp->isSplat()) { - if (isMMX) - return Op; + if (SVOp->isSplat()) return PromoteSplat(SVOp, DAG); - } // If the shuffle can be profitably rewritten as a narrower shuffle, then // do it! From stuart at apple.com Tue Sep 7 13:43:09 2010 From: stuart at apple.com (Stuart Hastings) Date: Tue, 07 Sep 2010 18:43:09 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r113248 - /llvm-gcc-4.2/trunk/gcc/c-typeck.c Message-ID: <20100907184309.E2E4F2A6C12C@llvm.org> Author: stuart Date: Tue Sep 7 13:43:09 2010 New Revision: 113248 URL: http://llvm.org/viewvc/llvm-project?rev=113248&view=rev Log: Diagnose illegal store into a const. Radar 8361341. Modified: llvm-gcc-4.2/trunk/gcc/c-typeck.c Modified: llvm-gcc-4.2/trunk/gcc/c-typeck.c URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/c-typeck.c?rev=113248&r1=113247&r2=113248&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/c-typeck.c (original) +++ llvm-gcc-4.2/trunk/gcc/c-typeck.c Tue Sep 7 13:43:09 2010 @@ -2132,7 +2132,10 @@ * and it provides it with more information for optimization. */ { - tree ty = TREE_TYPE(TREE_TYPE(ar)); + /* LLVM LOCAL begin 8361341 */ + tree orig_ty = TREE_TYPE(TREE_TYPE(ar)); + tree ty = orig_ty; + /* LLVM LOCAL end 8361341 */ if (TREE_CODE(ty) == RECORD_TYPE || TREE_CODE(ty) == UNION_TYPE || TREE_CODE(ty) == QUAL_UNION_TYPE) ty = TYPE_MAIN_VARIANT (ty); @@ -2149,8 +2152,10 @@ /* Mirror logic from build_indirect_ref to set TREE_THIS_VOLATILE and * other flags. */ - TREE_READONLY (ar) = TYPE_READONLY (TREE_TYPE (ar)); - TREE_THIS_VOLATILE(ar) = TYPE_VOLATILE(TREE_TYPE (ar)); + /* LLVM LOCAL begin 8361341 */ + TREE_READONLY (ar) = TYPE_READONLY (orig_ty); + TREE_THIS_VOLATILE(ar) = TYPE_VOLATILE(orig_ty); + /* LLVM LOCAL end 8361341 */ TREE_SIDE_EFFECTS (ar) = TREE_THIS_VOLATILE (ar) || TREE_SIDE_EFFECTS (array) || TREE_SIDE_EFFECTS (index); From stuart at apple.com Tue Sep 7 13:43:57 2010 From: stuart at apple.com (Stuart Hastings) Date: Tue, 07 Sep 2010 18:43:57 -0000 Subject: [llvm-commits] [llvm] r113249 - /llvm/trunk/test/FrontendC/2007-10-01-BuildArrayRef.c Message-ID: <20100907184357.E5DD62A6C12C@llvm.org> Author: stuart Date: Tue Sep 7 13:43:57 2010 New Revision: 113249 URL: http://llvm.org/viewvc/llvm-project?rev=113249&view=rev Log: Test case for r113248. Raar 8361341. Modified: llvm/trunk/test/FrontendC/2007-10-01-BuildArrayRef.c Modified: llvm/trunk/test/FrontendC/2007-10-01-BuildArrayRef.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/2007-10-01-BuildArrayRef.c?rev=113249&r1=113248&r2=113249&view=diff ============================================================================== --- llvm/trunk/test/FrontendC/2007-10-01-BuildArrayRef.c (original) +++ llvm/trunk/test/FrontendC/2007-10-01-BuildArrayRef.c Tue Sep 7 13:43:57 2010 @@ -1,8 +1,20 @@ -// RUN: not %llvmgcc -S %s -o /dev/null |& grep "error: assignment of read-only location" +// RUN: not %llvmgcc_only -c %s -o /dev/null |& FileCheck %s // PR 1603 -int func() +void func() { const int *arr; - arr[0] = 1; + arr[0] = 1; // CXHECK: error: assignment of read-only location } +struct foo { + int bar; +}; +struct foo sfoo = { 0 }; + +int func2() +{ + const struct foo *fp; + fp = &sfoo; + fp[0].bar = 1; // CHECK: error: assignment of read-only member 'bar' + return sfoo.bar; +} From gohman at apple.com Tue Sep 7 13:47:59 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 7 Sep 2010 11:47:59 -0700 Subject: [llvm-commits] [llvm] r112976 - /llvm/trunk/Makefile.rules In-Reply-To: References: <20100903172933.45D6E2A6C12C@llvm.org> Message-ID: On Sep 4, 2010, at 6:57 PM, NAKAMURA Takumi wrote: > Dan, > > A bad news, it broke mingw's enable_shared. > > HAVE_LINK_VERSION_SCRIPT is set on mingw by autoconf, > regadless of functionality of it. > > Also RPATH, RDYNAMIC are set. > > They are accepted but ignored by GNU ld win32. That's surprising, and sounds like a bug. > > To reorder "if (HAVE_LINK_VERSION_SCRIPT) clause and if (cyginw || > mingw) clause", > it would be resolved. This sounds fine to me, provided it's accompanied by a comment. Or, you could change the autoconf code to avoid setting HAVE_LINK_VERSION_SCRIPT if the linker doesn't *really* support it. Dan From isanbard at gmail.com Tue Sep 7 13:49:14 2010 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 07 Sep 2010 18:49:14 -0000 Subject: [llvm-commits] [llvm] r113250 - /llvm/trunk/utils/TableGen/CodeGenTarget.cpp Message-ID: <20100907184914.AEF272A6C12C@llvm.org> Author: void Date: Tue Sep 7 13:49:14 2010 New Revision: 113250 URL: http://llvm.org/viewvc/llvm-project?rev=113250&view=rev Log: Fix whitespace, because I'm OCD. Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=113250&r1=113249&r2=113250&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Tue Sep 7 13:49:14 2010 @@ -48,46 +48,46 @@ std::string llvm::getEnumName(MVT::SimpleValueType T) { switch (T) { - case MVT::Other: return "MVT::Other"; - case MVT::i1: return "MVT::i1"; - case MVT::i8: return "MVT::i8"; - case MVT::i16: return "MVT::i16"; - case MVT::i32: return "MVT::i32"; - case MVT::i64: return "MVT::i64"; - case MVT::i128: return "MVT::i128"; - case MVT::iAny: return "MVT::iAny"; - case MVT::fAny: return "MVT::fAny"; - case MVT::vAny: return "MVT::vAny"; - case MVT::f32: return "MVT::f32"; - case MVT::f64: return "MVT::f64"; - case MVT::f80: return "MVT::f80"; - case MVT::f128: return "MVT::f128"; + case MVT::Other: return "MVT::Other"; + case MVT::i1: return "MVT::i1"; + case MVT::i8: return "MVT::i8"; + case MVT::i16: return "MVT::i16"; + case MVT::i32: return "MVT::i32"; + case MVT::i64: return "MVT::i64"; + case MVT::i128: return "MVT::i128"; + case MVT::iAny: return "MVT::iAny"; + case MVT::fAny: return "MVT::fAny"; + case MVT::vAny: return "MVT::vAny"; + case MVT::f32: return "MVT::f32"; + case MVT::f64: return "MVT::f64"; + case MVT::f80: return "MVT::f80"; + case MVT::f128: return "MVT::f128"; case MVT::ppcf128: return "MVT::ppcf128"; - case MVT::Flag: return "MVT::Flag"; - case MVT::isVoid:return "MVT::isVoid"; - case MVT::v2i8: return "MVT::v2i8"; - case MVT::v4i8: return "MVT::v4i8"; - case MVT::v8i8: return "MVT::v8i8"; - case MVT::v16i8: return "MVT::v16i8"; - case MVT::v32i8: return "MVT::v32i8"; - case MVT::v2i16: return "MVT::v2i16"; - case MVT::v4i16: return "MVT::v4i16"; - case MVT::v8i16: return "MVT::v8i16"; - case MVT::v16i16: return "MVT::v16i16"; - case MVT::v2i32: return "MVT::v2i32"; - case MVT::v4i32: return "MVT::v4i32"; - case MVT::v8i32: return "MVT::v8i32"; - case MVT::v1i64: return "MVT::v1i64"; - case MVT::v2i64: return "MVT::v2i64"; - case MVT::v4i64: return "MVT::v4i64"; - case MVT::v8i64: return "MVT::v8i64"; - case MVT::v2f32: return "MVT::v2f32"; - case MVT::v4f32: return "MVT::v4f32"; - case MVT::v8f32: return "MVT::v8f32"; - case MVT::v2f64: return "MVT::v2f64"; - case MVT::v4f64: return "MVT::v4f64"; + case MVT::Flag: return "MVT::Flag"; + case MVT::isVoid: return "MVT::isVoid"; + case MVT::v2i8: return "MVT::v2i8"; + case MVT::v4i8: return "MVT::v4i8"; + case MVT::v8i8: return "MVT::v8i8"; + case MVT::v16i8: return "MVT::v16i8"; + case MVT::v32i8: return "MVT::v32i8"; + case MVT::v2i16: return "MVT::v2i16"; + case MVT::v4i16: return "MVT::v4i16"; + case MVT::v8i16: return "MVT::v8i16"; + case MVT::v16i16: return "MVT::v16i16"; + case MVT::v2i32: return "MVT::v2i32"; + case MVT::v4i32: return "MVT::v4i32"; + case MVT::v8i32: return "MVT::v8i32"; + case MVT::v1i64: return "MVT::v1i64"; + case MVT::v2i64: return "MVT::v2i64"; + case MVT::v4i64: return "MVT::v4i64"; + case MVT::v8i64: return "MVT::v8i64"; + case MVT::v2f32: return "MVT::v2f32"; + case MVT::v4f32: return "MVT::v4f32"; + case MVT::v8f32: return "MVT::v8f32"; + case MVT::v2f64: return "MVT::v2f64"; + case MVT::v4f64: return "MVT::v4f64"; case MVT::Metadata: return "MVT::Metadata"; - case MVT::iPTR: return "MVT::iPTR"; + case MVT::iPTR: return "MVT::iPTR"; case MVT::iPTRAny: return "MVT::iPTRAny"; default: assert(0 && "ILLEGAL VALUE TYPE!"); return ""; } From resistor at mac.com Tue Sep 7 14:16:26 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 07 Sep 2010 19:16:26 -0000 Subject: [llvm-commits] [llvm] r113252 - in /llvm/trunk: include/llvm/PassRegistry.h include/llvm/PassSupport.h lib/Analysis/LazyValueInfo.cpp lib/VMCore/PassRegistry.cpp Message-ID: <20100907191626.31FD82A6C12C@llvm.org> Author: resistor Date: Tue Sep 7 14:16:25 2010 New Revision: 113252 URL: http://llvm.org/viewvc/llvm-project?rev=113252&view=rev Log: Clean up some of the PassRegistry implementation, and pImpl-ize it to reduce #include clutter and exposing internal details. Modified: llvm/trunk/include/llvm/PassRegistry.h llvm/trunk/include/llvm/PassSupport.h llvm/trunk/lib/Analysis/LazyValueInfo.cpp llvm/trunk/lib/VMCore/PassRegistry.cpp Modified: llvm/trunk/include/llvm/PassRegistry.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/PassRegistry.h?rev=113252&r1=113251&r2=113252&view=diff ============================================================================== --- llvm/trunk/include/llvm/PassRegistry.h (original) +++ llvm/trunk/include/llvm/PassRegistry.h Tue Sep 7 14:16:25 2010 @@ -8,9 +8,9 @@ //===----------------------------------------------------------------------===// // // This file defines PassRegistry, a class that is used in the initialization -// and registration of passes. At initialization, passes are registered with -// the PassRegistry, which is later provided to the PassManager for dependency -// resolution and similar tasks. +// and registration of passes. At application startup, passes are registered +// with the PassRegistry, which is later provided to the PassManager for +// dependency resolution and similar tasks. // //===----------------------------------------------------------------------===// @@ -19,35 +19,22 @@ #include "llvm/ADT/StringMap.h" #include "llvm/System/DataTypes.h" -#include "llvm/System/Mutex.h" -#include -#include -#include namespace llvm { class PassInfo; struct PassRegistrationListener; +/// PassRegistry - This class manages the registration and intitialization of +/// the pass subsystem as application startup, and assists the PassManager +/// in resolving pass dependencies. +/// NOTE: PassRegistry is NOT thread-safe. If you want to use LLVM on multiple +/// threads simultaneously, you will need to use a separate PassRegistry on +/// each thread. class PassRegistry { - /// Guards the contents of this class. - mutable sys::SmartMutex Lock; - - /// PassInfoMap - Keep track of the PassInfo object for each registered pass. - typedef std::map MapType; - MapType PassInfoMap; - - typedef StringMap StringMapType; - StringMapType PassInfoStringMap; - - /// AnalysisGroupInfo - Keep track of information for each analysis group. - struct AnalysisGroupInfo { - std::set Implementations; - }; - std::map AnalysisGroupInfoMap; - - std::vector Listeners; - + mutable void *pImpl; + void *getImpl() const; + public: static PassRegistry *getPassRegistry(); Modified: llvm/trunk/include/llvm/PassSupport.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/PassSupport.h?rev=113252&r1=113251&r2=113252&view=diff ============================================================================== --- llvm/trunk/include/llvm/PassSupport.h (original) +++ llvm/trunk/include/llvm/PassSupport.h Tue Sep 7 14:16:25 2010 @@ -23,6 +23,7 @@ #include "Pass.h" #include "llvm/PassRegistry.h" +#include namespace llvm { Modified: llvm/trunk/lib/Analysis/LazyValueInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/LazyValueInfo.cpp?rev=113252&r1=113251&r2=113252&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/LazyValueInfo.cpp (original) +++ llvm/trunk/lib/Analysis/LazyValueInfo.cpp Tue Sep 7 14:16:25 2010 @@ -26,6 +26,8 @@ #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/DenseSet.h" #include "llvm/ADT/STLExtras.h" +#include +#include using namespace llvm; char LazyValueInfo::ID = 0; Modified: llvm/trunk/lib/VMCore/PassRegistry.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/PassRegistry.cpp?rev=113252&r1=113251&r2=113252&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/PassRegistry.cpp (original) +++ llvm/trunk/lib/VMCore/PassRegistry.cpp Tue Sep 7 14:16:25 2010 @@ -16,6 +16,9 @@ #include "llvm/PassSupport.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/ManagedStatic.h" +#include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/SmallPtrSet.h" +#include using namespace llvm; @@ -60,16 +63,48 @@ } +//===----------------------------------------------------------------------===// +// PassRegistryImpl +// + +struct PassRegistryImpl { + /// PassInfoMap - Keep track of the PassInfo object for each registered pass. + typedef DenseMap MapType; + MapType PassInfoMap; + + typedef StringMap StringMapType; + StringMapType PassInfoStringMap; + + /// AnalysisGroupInfo - Keep track of information for each analysis group. + struct AnalysisGroupInfo { + SmallPtrSet Implementations; + }; + DenseMap AnalysisGroupInfoMap; + + std::vector Listeners; +}; + +void *PassRegistry::getImpl() const { + if (!pImpl) + pImpl = new PassRegistryImpl(); + return pImpl; +} + +//===----------------------------------------------------------------------===// +// Accessors +// + const PassInfo *PassRegistry::getPassInfo(const void *TI) const { - sys::SmartScopedLock Guard(Lock); - MapType::const_iterator I = PassInfoMap.find(TI); - return I != PassInfoMap.end() ? I->second : 0; + PassRegistryImpl *Impl = static_cast(getImpl()); + PassRegistryImpl::MapType::const_iterator I = Impl->PassInfoMap.find(TI); + return I != Impl->PassInfoMap.end() ? I->second : 0; } const PassInfo *PassRegistry::getPassInfo(StringRef Arg) const { - sys::SmartScopedLock Guard(Lock); - StringMapType::const_iterator I = PassInfoStringMap.find(Arg); - return I != PassInfoStringMap.end() ? I->second : 0; + PassRegistryImpl *Impl = static_cast(getImpl()); + PassRegistryImpl::StringMapType::const_iterator + I = Impl->PassInfoStringMap.find(Arg); + return I != Impl->PassInfoStringMap.end() ? I->second : 0; } //===----------------------------------------------------------------------===// @@ -77,32 +112,33 @@ // void PassRegistry::registerPass(const PassInfo &PI) { - sys::SmartScopedLock Guard(Lock); + PassRegistryImpl *Impl = static_cast(getImpl()); bool Inserted = - PassInfoMap.insert(std::make_pair(PI.getTypeInfo(),&PI)).second; + Impl->PassInfoMap.insert(std::make_pair(PI.getTypeInfo(),&PI)).second; assert(Inserted && "Pass registered multiple times!"); Inserted=Inserted; - PassInfoStringMap[PI.getPassArgument()] = &PI; + Impl->PassInfoStringMap[PI.getPassArgument()] = &PI; // Notify any listeners. for (std::vector::iterator - I = Listeners.begin(), E = Listeners.end(); I != E; ++I) + I = Impl->Listeners.begin(), E = Impl->Listeners.end(); I != E; ++I) (*I)->passRegistered(&PI); } void PassRegistry::unregisterPass(const PassInfo &PI) { - sys::SmartScopedLock Guard(Lock); - MapType::iterator I = PassInfoMap.find(PI.getTypeInfo()); - assert(I != PassInfoMap.end() && "Pass registered but not in map!"); + PassRegistryImpl *Impl = static_cast(getImpl()); + PassRegistryImpl::MapType::iterator I = + Impl->PassInfoMap.find(PI.getTypeInfo()); + assert(I != Impl->PassInfoMap.end() && "Pass registered but not in map!"); // Remove pass from the map. - PassInfoMap.erase(I); - PassInfoStringMap.erase(PI.getPassArgument()); + Impl->PassInfoMap.erase(I); + Impl->PassInfoStringMap.erase(PI.getPassArgument()); } void PassRegistry::enumerateWith(PassRegistrationListener *L) { - sys::SmartScopedLock Guard(Lock); - for (MapType::const_iterator I = PassInfoMap.begin(), - E = PassInfoMap.end(); I != E; ++I) + PassRegistryImpl *Impl = static_cast(getImpl()); + for (PassRegistryImpl::MapType::const_iterator I = Impl->PassInfoMap.begin(), + E = Impl->PassInfoMap.end(); I != E; ++I) L->passEnumerate(I->second); } @@ -130,8 +166,9 @@ // the interface. ImplementationInfo->addInterfaceImplemented(InterfaceInfo); - sys::SmartScopedLock Guard(Lock); - AnalysisGroupInfo &AGI = AnalysisGroupInfoMap[InterfaceInfo]; + PassRegistryImpl *Impl = static_cast(getImpl()); + PassRegistryImpl::AnalysisGroupInfo &AGI = + Impl->AnalysisGroupInfoMap[InterfaceInfo]; assert(AGI.Implementations.count(ImplementationInfo) == 0 && "Cannot add a pass to the same analysis group more than once!"); AGI.Implementations.insert(ImplementationInfo); @@ -146,14 +183,15 @@ } void PassRegistry::addRegistrationListener(PassRegistrationListener *L) { - sys::SmartScopedLock Guard(Lock); - Listeners.push_back(L); + PassRegistryImpl *Impl = static_cast(getImpl()); + Impl->Listeners.push_back(L); } void PassRegistry::removeRegistrationListener(PassRegistrationListener *L) { - sys::SmartScopedLock Guard(Lock); + PassRegistryImpl *Impl = static_cast(getImpl()); std::vector::iterator I = - std::find(Listeners.begin(), Listeners.end(), L); - assert(I != Listeners.end() && "PassRegistrationListener not registered!"); - Listeners.erase(I); + std::find(Impl->Listeners.begin(), Impl->Listeners.end(), L); + assert(I != Impl->Listeners.end() && + "PassRegistrationListener not registered!"); + Impl->Listeners.erase(I); } From clattner at apple.com Tue Sep 7 14:46:30 2010 From: clattner at apple.com (Chris Lattner) Date: Tue, 7 Sep 2010 12:46:30 -0700 Subject: [llvm-commits] InitializeNativeAsmPrinter implementation In-Reply-To: <192297.66340.qm@web55601.mail.re4.yahoo.com> References: <318832.28864.qm@web55601.mail.re4.yahoo.com> <8888711F-1CCE-4D57-8B1D-95D9F9DADDA7@apple.com> <192297.66340.qm@web55601.mail.re4.yahoo.com> Message-ID: Ok, I missed that, no worries. Thanks! On Sep 7, 2010, at 11:10 AM, Jan Sjodin wrote: > This patch was applied (with modifications) in r109996, is this what is causing > the problem? > > Thanks, > Jan > > > ----- Original Message ---- >> From: Chris Lattner >> To: Jan Sjodin >> Cc: llvm-commits at cs.uiuc.edu; Olivier Meurant >> Sent: Mon, September 6, 2010 6:09:25 AM >> Subject: Re: [llvm-commits] InitializeNativeAsmPrinter implementation >> >> >> On Jul 22, 2010, at 8:50 AM, Jan Sjodin wrote: >> >>> This patch is to prepare for MCJIT. I had to normalized the names for >>> the initializers to have "Target" in the name to be able to use the >>> LLVM_NATIVE_ARCH in the macros. >> >> Hi Jan, >> >> This patch applies but doesn't build correctly: >> >> In file included from EDDisassembler.cpp:37: >> /Volumes/Data/Users/sabre/llvm/include/llvm/Target/TargetSelect.h:123:5: error: >> >> use of undeclared identifier 'LLVMInitializeX86AsmPrinter'; did you mean >> 'LLVMInitializeX86TargetAsmPrinter'? >> LLVM_NATIVE_ASMPRINTER(); >> ^~~~~~~~~~~~~~~~~~~~~~ >> >> >> Can you update it for mainline? >> >> -Chris From clattner at apple.com Tue Sep 7 14:47:47 2010 From: clattner at apple.com (Chris Lattner) Date: Tue, 7 Sep 2010 12:47:47 -0700 Subject: [llvm-commits] [llvm] r113237 - in /llvm/trunk/test/CodeGen/X86: dbg-declare-fastisel.ll dbg-declare-hybrid.ll dbg-declare-isel.ll In-Reply-To: <20100907181756.C78E12A6C12C@llvm.org> References: <20100907181756.C78E12A6C12C@llvm.org> Message-ID: On Sep 7, 2010, at 11:17 AM, Devang Patel wrote: > Author: dpatel > Date: Tue Sep 7 13:17:56 2010 > New Revision: 113237 > > URL: http://llvm.org/viewvc/llvm-project?rev=113237&view=rev > Log: > Fix command line used to link these test cases. Are these tests going to work on non-native hosts (e.g. a mips linux box)? These seem like something that should be in a different test suite. -Chris > > Modified: > llvm/trunk/test/CodeGen/X86/dbg-declare-fastisel.ll > llvm/trunk/test/CodeGen/X86/dbg-declare-hybrid.ll > llvm/trunk/test/CodeGen/X86/dbg-declare-isel.ll > > Modified: llvm/trunk/test/CodeGen/X86/dbg-declare-fastisel.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-declare-fastisel.ll?rev=113237&r1=113236&r2=113237&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/dbg-declare-fastisel.ll (original) > +++ llvm/trunk/test/CodeGen/X86/dbg-declare-fastisel.ll Tue Sep 7 13:17:56 2010 > @@ -1,7 +1,7 @@ > ; This test case checks handling of llvm.dbg.declare intrinsic during fast-isel. > ; RUN: llc -mtriple=x86_64-apple-darwin --disable-fp-elim -O0 %s -o %t.s > ; RUN: %compile_c -m64 %t.s -o %t.o > -; RUN: %link %t.o -o %t.exe > +; RUN: %link -m64 %t.o -o %t.exe > ; RUN: echo {break f1\n break f2 \n break f3 \n break f5 \n break f9 \n run \n p i \n c \n p i\n c \n p i\n c \n p i\n c \n p i.x} > %t.in > ; RUN: gdb -q -batch -n -x %t.in %t.exe >& %t.out > ; RUN: grep "1 = 42" %t.out > > Modified: llvm/trunk/test/CodeGen/X86/dbg-declare-hybrid.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-declare-hybrid.ll?rev=113237&r1=113236&r2=113237&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/dbg-declare-hybrid.ll (original) > +++ llvm/trunk/test/CodeGen/X86/dbg-declare-hybrid.ll Tue Sep 7 13:17:56 2010 > @@ -2,7 +2,7 @@ > ; using fast-isel but switch back to DAG building at some point. > ; RUN: llc -mtriple=x86_64-apple-darwin --disable-fp-elim -O0 %s -o %t.s > ; RUN: %compile_c -m64 %t.s -o %t.o > -; RUN: %link %t.o -o %t.exe > +; RUN: %link -m64 %t.o -o %t.exe > ; RUN: echo {break f1\n break f4\n break f5\n run \n p i\n c \n p i\n c \n p i\n} > %t.in > ; RUN: gdb -q -batch -n -x %t.in %t.exe >& %t.out > ; RUN: grep "1 = 42" %t.out > > Modified: llvm/trunk/test/CodeGen/X86/dbg-declare-isel.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-declare-isel.ll?rev=113237&r1=113236&r2=113237&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/dbg-declare-isel.ll (original) > +++ llvm/trunk/test/CodeGen/X86/dbg-declare-isel.ll Tue Sep 7 13:17:56 2010 > @@ -1,7 +1,7 @@ > ; This test case checks handling of llvm.dbg.declare intrinsic during isel. > ; RUN: llc -mtriple=x86_64-apple-darwin --disable-fp-elim -O0 -fast-isel=false %s -o %t.s > ; RUN: %compile_c -m64 %t.s -o %t.o > -; RUN: %link %t.o -o %t.exe > +; RUN: %link -m64 %t.o -o %t.exe > ; RUN: echo {break f1\n break f2 \n break f7 \n break f8 \n break f9 \n break f10 \n run \n p i\n c \n p i\n c \n p i.x\n c \n p i.x\n c \n p i.x \n c \n p i.x \n} > %t.in > ; RUN: gdb -q -batch -n -x %t.in %t.exe >& %t.out > ; RUN: grep "1 = 42" %t.out > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From resistor at mac.com Tue Sep 7 14:49:45 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 07 Sep 2010 12:49:45 -0700 Subject: [llvm-commits] [llvm] r108932 - in /llvm/trunk: include/llvm/PassRegistry.h lib/VMCore/Pass.cpp lib/VMCore/PassRegistry.cpp In-Reply-To: <9F11D537-80DA-4F24-B064-B3051462C7D0@apple.com> References: <20100720212224.6252B2A6C12C@llvm.org> <9F11D537-80DA-4F24-B064-B3051462C7D0@apple.com> Message-ID: On Sep 5, 2010, at 3:43 PM, Chris Lattner wrote: >> +namespace { > > Please only use namespaces for classes. For globals and functions, just use 'static' like the coding standards say: > http://llvm.org/docs/CodingStandards.html#micro_anonns 'static' is not legal in this instance, since we need to pass the address of cleanupPassRegistry() to the ManagedCleanup object. --Owen From clattner at apple.com Tue Sep 7 14:50:23 2010 From: clattner at apple.com (Chris Lattner) Date: Tue, 7 Sep 2010 12:50:23 -0700 Subject: [llvm-commits] [llvm] r108932 - in /llvm/trunk: include/llvm/PassRegistry.h lib/VMCore/Pass.cpp lib/VMCore/PassRegistry.cpp In-Reply-To: References: <20100720212224.6252B2A6C12C@llvm.org> <9F11D537-80DA-4F24-B064-B3051462C7D0@apple.com> Message-ID: <3EC08EBD-5A7E-4FD4-BA11-7937AC441440@apple.com> On Sep 7, 2010, at 12:49 PM, Owen Anderson wrote: > > On Sep 5, 2010, at 3:43 PM, Chris Lattner wrote: >>> +namespace { >> >> Please only use namespaces for classes. For globals and functions, just use 'static' like the coding standards say: >> http://llvm.org/docs/CodingStandards.html#micro_anonns > > 'static' is not legal in this instance, since we need to pass the address of cleanupPassRegistry() to the ManagedCleanup object. What does that have to do with it? -Chris From sabre at nondot.org Tue Sep 7 14:50:53 2010 From: sabre at nondot.org (Chris Lattner) Date: Tue, 07 Sep 2010 19:50:53 -0000 Subject: [llvm-commits] [llvm] r113255 - /llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.h Message-ID: <20100907195053.DF6BF2A6C12D@llvm.org> Author: lattner Date: Tue Sep 7 14:50:53 2010 New Revision: 113255 URL: http://llvm.org/viewvc/llvm-project?rev=113255&view=rev Log: hopefully fix a problem building on cygwin-1.5 Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.h Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.h?rev=113255&r1=113254&r2=113255&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.h (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.h Tue Sep 7 14:50:53 2010 @@ -126,8 +126,8 @@ } /// Utility function for setting [From, To] bits to Val for a uint32_t. -static inline void setSlice(uint32_t &Bits, unsigned From, unsigned To, - uint32_t Val) { +static inline void setSlice(unsigned &Bits, unsigned From, unsigned To, + unsigned Val) { assert(From < 32 && To < 32 && From >= To); uint32_t Mask = ((1 << (From - To + 1)) - 1); Bits &= ~(Mask << To); From sabre at nondot.org Tue Sep 7 14:57:06 2010 From: sabre at nondot.org (Chris Lattner) Date: Tue, 07 Sep 2010 19:57:06 -0000 Subject: [llvm-commits] [llvm] r113257 - in /llvm/trunk/test/Transforms/InstCombine: 2010-07-19-sqrt.ll sqrt.ll Message-ID: <20100907195706.A439C2A6C12D@llvm.org> Author: lattner Date: Tue Sep 7 14:57:06 2010 New Revision: 113257 URL: http://llvm.org/viewvc/llvm-project?rev=113257&view=rev Log: rename test. Added: llvm/trunk/test/Transforms/InstCombine/sqrt.ll - copied unchanged from r113252, llvm/trunk/test/Transforms/InstCombine/2010-07-19-sqrt.ll Removed: llvm/trunk/test/Transforms/InstCombine/2010-07-19-sqrt.ll Removed: llvm/trunk/test/Transforms/InstCombine/2010-07-19-sqrt.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/2010-07-19-sqrt.ll?rev=113256&view=auto ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/2010-07-19-sqrt.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/2010-07-19-sqrt.ll (removed) @@ -1,16 +0,0 @@ -; RUN: opt -S -instcombine %s | FileCheck %s - -define float @foo(float %x) nounwind readnone ssp { -entry: -; CHECK-NOT: fpext -; CHECK-NOT: sqrt( -; CHECK: sqrtf( -; CHECK-NOT: fptrunc - %conv = fpext float %x to double ; [#uses=1] - %call = tail call double @sqrt(double %conv) nounwind ; [#uses=1] - %conv1 = fptrunc double %call to float ; [#uses=1] -; CHECK: ret float - ret float %conv1 -} - -declare double @sqrt(double) readnone From evan.cheng at apple.com Tue Sep 7 15:01:10 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 07 Sep 2010 20:01:10 -0000 Subject: [llvm-commits] [llvm] r113259 - /llvm/trunk/lib/Target/X86/X86InstrInfo.td Message-ID: <20100907200110.4816E2A6C12C@llvm.org> Author: evancheng Date: Tue Sep 7 15:01:10 2010 New Revision: 113259 URL: http://llvm.org/viewvc/llvm-project?rev=113259&view=rev Log: Remove a dead comment. Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=113259&r1=113258&r2=113259&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Tue Sep 7 15:01:10 2010 @@ -599,7 +599,6 @@ } def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3", [(int_x86_int (i8 3))]>; -// FIXME: need to make sure that "int $3" matches int3 def INT : Ii8<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap", [(int_x86_int imm:$trap)]>; def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", []>, OpSize; From clattner at apple.com Tue Sep 7 14:51:55 2010 From: clattner at apple.com (Chris Lattner) Date: Tue, 7 Sep 2010 12:51:55 -0700 Subject: [llvm-commits] [PATCH] Target/ARM build failure on Cygwin-1.5 In-Reply-To: References: Message-ID: <1B3650AC-0C27-42EF-B68B-77D6484BCD23@apple.com> On Sep 6, 2010, at 5:52 PM, NAKAMURA Takumi wrote: > Hi, Chris, > > I got erros below; > > lib/Target/ARM/Disassembler/ARMDisassembler.cpp: In member function > `void llvm::Session::UpdateIT()': > lib/Target/ARM/Disassembler/ARMDisassembler.cpp:559: error: invalid > initialization of reference of type 'uint32_t&' from expression of > type 'unsigned int' > lib/Target/ARM/Disassembler/ARMDisassemblerCore.h:130: error: in > passing argument 1 of `void llvm::setSlice(uint32_t&, unsigned int, > unsigned int, uint32_t)' > > $ gcc --version > gcc (GCC) 3.4.4 (cygming special, gdc 0.12, using dmd 0.125) > > I thought it would not be good idea to fix setSlice(). Does r113255 fix the problem? -Chris From sabre at nondot.org Tue Sep 7 15:01:38 2010 From: sabre at nondot.org (Chris Lattner) Date: Tue, 07 Sep 2010 20:01:38 -0000 Subject: [llvm-commits] [llvm] r113260 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineCasts.cpp test/Transforms/InstCombine/sqrt.ll Message-ID: <20100907200138.A4FB32A6C12C@llvm.org> Author: lattner Date: Tue Sep 7 15:01:38 2010 New Revision: 113260 URL: http://llvm.org/viewvc/llvm-project?rev=113260&view=rev Log: Fix a serious performance regression introduced by r108687 on linux: turning (fptrunc (sqrt (fpext x))) -> (sqrtf x) is great, but we have to delete the original sqrt as well. Not doing so causes us to do two sqrt's when building with -fmath-errno (the default on linux). Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp llvm/trunk/test/Transforms/InstCombine/sqrt.ll Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp?rev=113260&r1=113259&r2=113260&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp Tue Sep 7 15:01:38 2010 @@ -1139,7 +1139,7 @@ Arg->getOperand(0)->getType()->isFloatTy()) { Function *Callee = Call->getCalledFunction(); Module *M = CI.getParent()->getParent()->getParent(); - Constant* SqrtfFunc = M->getOrInsertFunction("sqrtf", + Constant *SqrtfFunc = M->getOrInsertFunction("sqrtf", Callee->getAttributes(), Builder->getFloatTy(), Builder->getFloatTy(), @@ -1147,6 +1147,11 @@ CallInst *ret = CallInst::Create(SqrtfFunc, Arg->getOperand(0), "sqrtfcall"); ret->setAttributes(Callee->getAttributes()); + + + // Remove the old Call. With -fmath-errno, it won't get marked readnone. + Call->replaceAllUsesWith(UndefValue::get(Call->getType())); + EraseInstFromFunction(*Call); return ret; } } Modified: llvm/trunk/test/Transforms/InstCombine/sqrt.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/sqrt.ll?rev=113260&r1=113259&r2=113260&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/sqrt.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/sqrt.ll Tue Sep 7 15:01:38 2010 @@ -1,16 +1,32 @@ ; RUN: opt -S -instcombine %s | FileCheck %s -define float @foo(float %x) nounwind readnone ssp { +define float @test1(float %x) nounwind readnone ssp { entry: +; CHECK: @test1 ; CHECK-NOT: fpext ; CHECK-NOT: sqrt( ; CHECK: sqrtf( ; CHECK-NOT: fptrunc %conv = fpext float %x to double ; [#uses=1] - %call = tail call double @sqrt(double %conv) nounwind ; [#uses=1] + %call = tail call double @sqrt(double %conv) readnone nounwind ; [#uses=1] %conv1 = fptrunc double %call to float ; [#uses=1] ; CHECK: ret float ret float %conv1 } -declare double @sqrt(double) readnone +declare double @sqrt(double) + +; PR8096 +define float @test2(float %x) nounwind readnone ssp { +entry: +; CHECK: @test2 +; CHECK-NOT: fpext +; CHECK-NOT: sqrt( +; CHECK: sqrtf( +; CHECK-NOT: fptrunc + %conv = fpext float %x to double ; [#uses=1] + %call = tail call double @sqrt(double %conv) nounwind ; [#uses=1] + %conv1 = fptrunc double %call to float ; [#uses=1] +; CHECK: ret float + ret float %conv1 +} From nlewycky at google.com Tue Sep 7 15:03:57 2010 From: nlewycky at google.com (Nick Lewycky) Date: Tue, 7 Sep 2010 13:03:57 -0700 Subject: [llvm-commits] [patch][Target/PTX] Create PTX backend In-Reply-To: References: <3169B6A7-65A6-4742-AA1F-E28618D1F764@apple.com> Message-ID: Hi Che-Liang, I've committed this in r113235. Thanks for the patch! Nick On 6 September 2010 02:28, Che-Liang Chiou wrote: > Hi David, > > I regenerate against latest revision 113149. > Would you review and apply it if possible? > Thank you very much. > > Regards, > Che-Liang > > On Mon, Sep 6, 2010 at 5:22 AM, Chris Lattner wrote: > > On Aug 27, 2010, at 12:01 AM, Che-Liang Chiou wrote: > > > >> SVN revision: r112257 > >> > >> re-generate patch against svn head. > > > > This conflicts in the autoconf stuff, but otherwise looks good to me. > Please regenerate and ask someone to apply for you, thanks! > > > > -Chris > > > >> > >> On Wed, Aug 11, 2010 at 11:10 AM, Che-Liang Chiou > wrote: > >>> SVN revision: 110776 > >>> > >>> This patch is a part of upstream work of a PTX backend using LLVM code > >>> generator. > >>> > >>> Change list summary: > >>> - Add an empty backend that is merely compilable > >>> - Add PTX entry to autoconf/configure.ac and include/llvm/ADT/Triple.h > >>> > >>> Outcome: > >>> $ ./configure --enable-targets=ptx > >>> $ make > >>> $ llc -version | grep ptx > >>> ptx - PTX > >>> > >>> Misc: > >>> - Diff of auto-generated files are put in a separated patch > >>> - The autotool version on my machine is newer than > >>> autoconf/AutoGegen.sh requires, so the diff of auto-gen'd files might > >>> be differ with that on your machine > >>> > >>> Cheers, > >>> Che-Liang > >>> > >> > _______________________________________________ > >> llvm-commits mailing list > >> llvm-commits at cs.uiuc.edu > >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100907/bdbef513/attachment.html From resistor at mac.com Tue Sep 7 15:04:26 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 07 Sep 2010 20:04:26 -0000 Subject: [llvm-commits] [llvm] r113262 - /llvm/trunk/include/llvm/PassRegistry.h Message-ID: <20100907200426.4E9822A6C12D@llvm.org> Author: resistor Date: Tue Sep 7 15:04:26 2010 New Revision: 113262 URL: http://llvm.org/viewvc/llvm-project?rev=113262&view=rev Log: Add doxygen comments for PassRegistry. Modified: llvm/trunk/include/llvm/PassRegistry.h Modified: llvm/trunk/include/llvm/PassRegistry.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/PassRegistry.h?rev=113262&r1=113261&r2=113262&view=diff ============================================================================== --- llvm/trunk/include/llvm/PassRegistry.h (original) +++ llvm/trunk/include/llvm/PassRegistry.h Tue Sep 7 15:04:26 2010 @@ -36,20 +36,43 @@ void *getImpl() const; public: + /// getPassRegistry - Access the global registry object, which is + /// automatically initialized at application launch and destroyed by + /// llvm_shutdown. static PassRegistry *getPassRegistry(); + /// getPassInfo - Look up a pass' corresponding PassInfo, indexed by the pass' + /// type identifier (&MyPass::ID). const PassInfo *getPassInfo(const void *TI) const; + + /// getPassInfo - Look up a pass' corresponding PassInfo, indexed by the pass' + /// argument string. const PassInfo *getPassInfo(StringRef Arg) const; + /// registerPass - Register a pass (by means of its PassInfo) with the + /// registry. Required in order to use the pass with a PassManager. void registerPass(const PassInfo &PI); + + /// registerPass - Unregister a pass (by means of its PassInfo) with the + /// registry. void unregisterPass(const PassInfo &PI); - /// Analysis Group Mechanisms. + /// registerAnalysisGroup - Register an analysis group (or a pass implementing + // an analysis group) with the registry. Like registerPass, this is required + // in order for a PassManager to be able to use this group/pass. void registerAnalysisGroup(const void *InterfaceID, const void *PassID, PassInfo& Registeree, bool isDefault); + /// enumerateWith - Enumerate the registered passes, calling the provided + /// PassRegistrationListener's passEnumerate() callback on each of them. void enumerateWith(PassRegistrationListener *L); + + /// addRegistrationListener - Register the given PassRegistrationListener + /// to receive passRegistered() callbacks whenever a new pass is registered. void addRegistrationListener(PassRegistrationListener *L); + + /// removeRegistrationListener - Unregister a PassRegistrationListener so that + /// it no longer receives passRegistered() callbacks. void removeRegistrationListener(PassRegistrationListener *L); }; From isanbard at gmail.com Tue Sep 7 15:03:56 2010 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 07 Sep 2010 20:03:56 -0000 Subject: [llvm-commits] [llvm] r113261 - in /llvm/trunk: include/llvm/CodeGen/ValueTypes.h include/llvm/CodeGen/ValueTypes.td include/llvm/Intrinsics.td lib/Target/X86/X86ISelLowering.cpp lib/VMCore/ValueTypes.cpp utils/TableGen/CodeGenTarget.cpp Message-ID: <20100907200357.1CB442A6C12C@llvm.org> Author: void Date: Tue Sep 7 15:03:56 2010 New Revision: 113261 URL: http://llvm.org/viewvc/llvm-project?rev=113261&view=rev Log: Add an MVT::x86mmx type. It will take the place of all current MMX vector types. Modified: llvm/trunk/include/llvm/CodeGen/ValueTypes.h llvm/trunk/include/llvm/CodeGen/ValueTypes.td llvm/trunk/include/llvm/Intrinsics.td llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/VMCore/ValueTypes.cpp llvm/trunk/utils/TableGen/CodeGenTarget.cpp Modified: llvm/trunk/include/llvm/CodeGen/ValueTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ValueTypes.h?rev=113261&r1=113260&r2=113261&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/ValueTypes.h (original) +++ llvm/trunk/include/llvm/CodeGen/ValueTypes.h Tue Sep 7 15:03:56 2010 @@ -50,17 +50,17 @@ v2i8 = 12, // 2 x i8 v4i8 = 13, // 4 x i8 - v8i8 = 14, // 8 x i8 + v8i8 = 14, // 8 x i8 - MMX type v16i8 = 15, // 16 x i8 v32i8 = 16, // 32 x i8 v2i16 = 17, // 2 x i16 - v4i16 = 18, // 4 x i16 + v4i16 = 18, // 4 x i16 - MMX type v8i16 = 19, // 8 x i16 v16i16 = 20, // 16 x i16 - v2i32 = 21, // 2 x i32 + v2i32 = 21, // 2 x i32 - MMX type v4i32 = 22, // 4 x i32 v8i32 = 23, // 8 x i32 - v1i64 = 24, // 1 x i64 + v1i64 = 24, // 1 x i64 - MMX type v2i64 = 25, // 2 x i64 v4i64 = 26, // 4 x i64 v8i64 = 27, // 8 x i64 @@ -74,11 +74,13 @@ FIRST_VECTOR_VALUETYPE = v2i8, LAST_VECTOR_VALUETYPE = v4f64, - Flag = 33, // This glues nodes together during pre-RA sched + x86mmx = 33, // This is an X86 MMX value - isVoid = 34, // This has no value + Flag = 34, // This glues nodes together during pre-RA sched - LAST_VALUETYPE = 35, // This always remains at the end of the list. + isVoid = 35, // This has no value + + LAST_VALUETYPE = 36, // This always remains at the end of the list. // This is the current maximum for LAST_VALUETYPE. // EVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit vectors @@ -247,6 +249,7 @@ case i32 : case v4i8: case v2i16: return 32; + case x86mmx: case f64 : case i64 : case v8i8: Modified: llvm/trunk/include/llvm/CodeGen/ValueTypes.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ValueTypes.td?rev=113261&r1=113260&r2=113261&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/ValueTypes.td (original) +++ llvm/trunk/include/llvm/CodeGen/ValueTypes.td Tue Sep 7 15:03:56 2010 @@ -49,14 +49,15 @@ def v4i64 : ValueType<256, 26>; // 4 x f64 vector value def v8i64 : ValueType<512, 27>; // 4 x f64 vector value -def v2f32 : ValueType<64, 28>; // 2 x f32 vector value +def v2f32 : ValueType<64 , 28>; // 2 x f32 vector value def v4f32 : ValueType<128, 29>; // 4 x f32 vector value def v8f32 : ValueType<256, 30>; // 8 x f32 vector value def v2f64 : ValueType<128, 31>; // 2 x f64 vector value def v4f64 : ValueType<256, 32>; // 4 x f64 vector value -def FlagVT : ValueType<0 , 33>; // Pre-RA sched glue -def isVoid : ValueType<0 , 34>; // Produces no value +def x86mmx : ValueType<0 , 33>; // X86 MMX value +def FlagVT : ValueType<0 , 34>; // Pre-RA sched glue +def isVoid : ValueType<0 , 35>; // Produces no value def MetadataVT: ValueType<0, 250>; // Metadata Modified: llvm/trunk/include/llvm/Intrinsics.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Intrinsics.td?rev=113261&r1=113260&r2=113261&view=diff ============================================================================== --- llvm/trunk/include/llvm/Intrinsics.td (original) +++ llvm/trunk/include/llvm/Intrinsics.td Tue Sep 7 15:03:56 2010 @@ -109,6 +109,8 @@ def llvm_descriptor_ty : LLVMPointerType; // { }* def llvm_metadata_ty : LLVMType; // !{...} +def llvm_x86mmx_ty : LLVMType; + def llvm_v2i8_ty : LLVMType; // 2 x i8 def llvm_v4i8_ty : LLVMType; // 4 x i8 def llvm_v8i8_ty : LLVMType; // 8 x i8 Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=113261&r1=113260&r2=113261&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Sep 7 15:03:56 2010 @@ -614,6 +614,9 @@ // FIXME: In order to prevent SSE instructions being expanded to MMX ones // with -msoft-float, disable use of MMX as well. if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) { + addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass, false); + + // FIXME: Remove the rest of this stuff. addRegisterClass(MVT::v8i8, X86::VR64RegisterClass, false); addRegisterClass(MVT::v4i16, X86::VR64RegisterClass, false); addRegisterClass(MVT::v2i32, X86::VR64RegisterClass, false); Modified: llvm/trunk/lib/VMCore/ValueTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/ValueTypes.cpp?rev=113261&r1=113260&r2=113261&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/ValueTypes.cpp (original) +++ llvm/trunk/lib/VMCore/ValueTypes.cpp Tue Sep 7 15:03:56 2010 @@ -110,6 +110,7 @@ case MVT::isVoid: return "isVoid"; case MVT::Other: return "ch"; case MVT::Flag: return "flag"; + case MVT::x86mmx: return "x86mmx"; case MVT::v2i8: return "v2i8"; case MVT::v4i8: return "v4i8"; case MVT::v8i8: return "v8i8"; Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=113261&r1=113260&r2=113261&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Tue Sep 7 15:03:56 2010 @@ -63,6 +63,7 @@ case MVT::f80: return "MVT::f80"; case MVT::f128: return "MVT::f128"; case MVT::ppcf128: return "MVT::ppcf128"; + case MVT::x86mmx: return "MVT::x86mmx"; case MVT::Flag: return "MVT::Flag"; case MVT::isVoid: return "MVT::isVoid"; case MVT::v2i8: return "MVT::v2i8"; From clattner at apple.com Tue Sep 7 15:08:44 2010 From: clattner at apple.com (Chris Lattner) Date: Tue, 7 Sep 2010 13:08:44 -0700 Subject: [llvm-commits] [llvm] r113261 - in /llvm/trunk: include/llvm/CodeGen/ValueTypes.h include/llvm/CodeGen/ValueTypes.td include/llvm/Intrinsics.td lib/Target/X86/X86ISelLowering.cpp lib/VMCore/ValueTypes.cpp utils/TableGen/CodeGenTarget.cpp In-Reply-To: <20100907200357.1CB442A6C12C@llvm.org> References: <20100907200357.1CB442A6C12C@llvm.org> Message-ID: <2F24CED4-96A5-4F58-B7B5-68A382A74A43@apple.com> On Sep 7, 2010, at 1:03 PM, Bill Wendling wrote: > Author: void > Date: Tue Sep 7 15:03:56 2010 > New Revision: 113261 > > URL: http://llvm.org/viewvc/llvm-project?rev=113261&view=rev > Log: > Add an MVT::x86mmx type. It will take the place of all current MMX vector types. Hi Bill, why did you mark stuff in ValueTypes.h with "- MMX type"? The whole idea is that those won't map onto MMX anymore. -Chris From resistor at mac.com Tue Sep 7 15:13:48 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 07 Sep 2010 20:13:48 -0000 Subject: [llvm-commits] [llvm] r113264 - /llvm/trunk/include/llvm/PassRegistry.h Message-ID: <20100907201348.71AAC2A6C12C@llvm.org> Author: resistor Date: Tue Sep 7 15:13:48 2010 New Revision: 113264 URL: http://llvm.org/viewvc/llvm-project?rev=113264&view=rev Log: Properly initialize the pImpl member of PassRegistry to zero. Modified: llvm/trunk/include/llvm/PassRegistry.h Modified: llvm/trunk/include/llvm/PassRegistry.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/PassRegistry.h?rev=113264&r1=113263&r2=113264&view=diff ============================================================================== --- llvm/trunk/include/llvm/PassRegistry.h (original) +++ llvm/trunk/include/llvm/PassRegistry.h Tue Sep 7 15:13:48 2010 @@ -36,6 +36,8 @@ void *getImpl() const; public: + PassRegistry() : pImpl(0) { } + /// getPassRegistry - Access the global registry object, which is /// automatically initialized at application launch and destroyed by /// llvm_shutdown. From isanbard at gmail.com Tue Sep 7 15:16:24 2010 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 7 Sep 2010 13:16:24 -0700 Subject: [llvm-commits] [llvm] r113261 - in /llvm/trunk: include/llvm/CodeGen/ValueTypes.h include/llvm/CodeGen/ValueTypes.td include/llvm/Intrinsics.td lib/Target/X86/X86ISelLowering.cpp lib/VMCore/ValueTypes.cpp utils/TableGen/CodeGenTarget.cpp In-Reply-To: <2F24CED4-96A5-4F58-B7B5-68A382A74A43@apple.com> References: <20100907200357.1CB442A6C12C@llvm.org> <2F24CED4-96A5-4F58-B7B5-68A382A74A43@apple.com> Message-ID: <5409681F-BC43-46A2-A89B-E169F54BE618@gmail.com> On Sep 7, 2010, at 1:08 PM, Chris Lattner wrote: > > On Sep 7, 2010, at 1:03 PM, Bill Wendling wrote: > >> Author: void >> Date: Tue Sep 7 15:03:56 2010 >> New Revision: 113261 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=113261&view=rev >> Log: >> Add an MVT::x86mmx type. It will take the place of all current MMX vector types. > > Hi Bill, why did you mark stuff in ValueTypes.h with "- MMX type"? The whole idea is that those won't map onto MMX anymore. > Right. I was thinking that those would go away? Or at least shouldn't be used when not doing MMX? -bw From bruno.cardoso at gmail.com Tue Sep 7 15:20:27 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 07 Sep 2010 20:20:27 -0000 Subject: [llvm-commits] [llvm] r113267 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20100907202027.E912D2A6C12C@llvm.org> Author: bruno Date: Tue Sep 7 15:20:27 2010 New Revision: 113267 URL: http://llvm.org/viewvc/llvm-project?rev=113267&view=rev Log: Move code around to prepare for moving some of the logic together to another function Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=113267&r1=113266&r2=113267&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Sep 7 15:20:27 2010 @@ -5271,9 +5271,6 @@ MachineFunction &MF = DAG.getMachineFunction(); bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize); - if (isZeroShuffle(SVOp)) - return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); - // FIXME: this is somehow handled during isel by MMX pattern fragments. Remove // the check or come up with another solution when all MMX move to intrinsics, // but don't allow this to be considered legal, we don't want vector_shuffle @@ -5281,6 +5278,9 @@ if (isMMX && SVOp->isSplat()) return Op; + if (isZeroShuffle(SVOp)) + return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); + // Promote splats to v4f32. if (SVOp->isSplat()) return PromoteSplat(SVOp, DAG); From eli.friedman at gmail.com Tue Sep 7 15:25:31 2010 From: eli.friedman at gmail.com (Eli Friedman) Date: Tue, 7 Sep 2010 13:25:31 -0700 Subject: [llvm-commits] [llvm] r113261 - in /llvm/trunk: include/llvm/CodeGen/ValueTypes.h include/llvm/CodeGen/ValueTypes.td include/llvm/Intrinsics.td lib/Target/X86/X86ISelLowering.cpp lib/VMCore/ValueTypes.cpp utils/TableGen/CodeGenTarget.cpp In-Reply-To: <5409681F-BC43-46A2-A89B-E169F54BE618@gmail.com> References: <20100907200357.1CB442A6C12C@llvm.org> <2F24CED4-96A5-4F58-B7B5-68A382A74A43@apple.com> <5409681F-BC43-46A2-A89B-E169F54BE618@gmail.com> Message-ID: On Tue, Sep 7, 2010 at 1:16 PM, Bill Wendling wrote: > On Sep 7, 2010, at 1:08 PM, Chris Lattner wrote: > >> >> On Sep 7, 2010, at 1:03 PM, Bill Wendling wrote: >> >>> Author: void >>> Date: Tue Sep ?7 15:03:56 2010 >>> New Revision: 113261 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=113261&view=rev >>> Log: >>> Add an MVT::x86mmx type. It will take the place of all current MMX vector types. >> >> Hi Bill, why did you mark stuff in ValueTypes.h with "- MMX type"? ?The whole idea is that those won't map onto MMX anymore. >> > Right. I was thinking that those would go away? Or at least shouldn't be used when not doing MMX? They can't go away; at least NEON uses them. -Eli From rdivacky at freebsd.org Tue Sep 7 15:31:43 2010 From: rdivacky at freebsd.org (Roman Divacky) Date: Tue, 7 Sep 2010 22:31:43 +0200 Subject: [llvm-commits] [PATCH] ELF file alignments In-Reply-To: References: Message-ID: <20100907203143.GA51910@freebsd.org> On Mon, Sep 06, 2010 at 05:48:06PM +0800, Krister Wombell wrote: > The ELF spec says: > > All data structures that the object file format defines follow the > > "natural'' size and alignment guidelines for the relevant class. If > > necessary, data structures contain explicit padding to ensure 4-byte > > alignment for 4-byte objects, to force structure sizes to a multiple of 4, > > and so on. Data also have suitable alignment from the beginning of the file. > > Thus, for example, a structure containing an Elf32_Addr member will be > > aligned on a 4-byte boundary within the file. > > > > 1. ELFObjectWriter doesn't write the following objects with correct file > alignment: symtab, relocation sections, section headers. It probably goes > unnoticed because most CPUs support unaligned memory accesses and get to the > data without a problem plus linkers tend to fix things up too. CPUs without > unaligned accesses don't fare as well. > > 2. gas goes a step further than the rules above and ensures that even in > relocatable output that a section's file offset is also a multiple of the > section alignment. This behaviour falls out of the patch as well. hi, great patch! I wonder - are you interested in working on the MC-ELF some more? thank you, roman From gohman at apple.com Tue Sep 7 15:37:48 2010 From: gohman at apple.com (Dan Gohman) Date: Tue, 07 Sep 2010 20:37:48 -0000 Subject: [llvm-commits] [llvm] r113275 - /llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Message-ID: <20100907203748.0A2AF2A6C12C@llvm.org> Author: djg Date: Tue Sep 7 15:37:47 2010 New Revision: 113275 URL: http://llvm.org/viewvc/llvm-project?rev=113275&view=rev Log: Tidy up the getModRefInfo declarations. Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/AliasAnalysis.h?rev=113275&r1=113274&r2=113275&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/AliasAnalysis.h (original) +++ llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Tue Sep 7 15:37:47 2010 @@ -222,44 +222,60 @@ /// getModRefInfo - Return information about whether or not an instruction may /// read or write memory specified by the pointer operand. An instruction /// that doesn't read or write memory may be trivially LICM'd for example. + ModRefResult getModRefInfo(const Instruction *I, + const Value *P, unsigned Size) { + switch (I->getOpcode()) { + case Instruction::VAArg: return getModRefInfo((const VAArgInst*)I, P,Size); + case Instruction::Load: return getModRefInfo((const LoadInst*)I, P, Size); + case Instruction::Store: return getModRefInfo((const StoreInst*)I, P,Size); + case Instruction::Call: return getModRefInfo((const CallInst*)I, P, Size); + case Instruction::Invoke: return getModRefInfo((const InvokeInst*)I,P,Size); + default: return NoModRef; + } + } /// getModRefInfo (for call sites) - Return whether information about whether /// a particular call site modifies or reads the memory specified by the /// pointer. - /// virtual ModRefResult getModRefInfo(ImmutableCallSite CS, const Value *P, unsigned Size); - /// getModRefInfo - Return information about whether two call sites may refer - /// to the same set of memory locations. See - /// http://llvm.org/docs/AliasAnalysis.html#ModRefInfo - /// for details. - virtual ModRefResult getModRefInfo(ImmutableCallSite CS1, - ImmutableCallSite CS2); - -public: - /// Convenience functions... - ModRefResult getModRefInfo(const LoadInst *L, const Value *P, unsigned Size); - ModRefResult getModRefInfo(const StoreInst *S, const Value *P, unsigned Size); - ModRefResult getModRefInfo(const VAArgInst* I, const Value* P, unsigned Size); + /// getModRefInfo (for calls) - Return whether information about whether + /// a particular call modifies or reads the memory specified by the + /// pointer. ModRefResult getModRefInfo(const CallInst *C, const Value *P, unsigned Size) { return getModRefInfo(ImmutableCallSite(C), P, Size); } + + /// getModRefInfo (for invokes) - Return whether information about whether + /// a particular invoke modifies or reads the memory specified by the + /// pointer. ModRefResult getModRefInfo(const InvokeInst *I, const Value *P, unsigned Size) { return getModRefInfo(ImmutableCallSite(I), P, Size); } - ModRefResult getModRefInfo(const Instruction *I, - const Value *P, unsigned Size) { - switch (I->getOpcode()) { - case Instruction::VAArg: return getModRefInfo((const VAArgInst*)I, P,Size); - case Instruction::Load: return getModRefInfo((const LoadInst*)I, P, Size); - case Instruction::Store: return getModRefInfo((const StoreInst*)I, P,Size); - case Instruction::Call: return getModRefInfo((const CallInst*)I, P, Size); - case Instruction::Invoke: return getModRefInfo((const InvokeInst*)I,P,Size); - default: return NoModRef; - } - } + + /// getModRefInfo (for loads) - Return whether information about whether + /// a particular load modifies or reads the memory specified by the + /// pointer. + ModRefResult getModRefInfo(const LoadInst *L, const Value *P, unsigned Size); + + /// getModRefInfo (for stores) - Return whether information about whether + /// a particular store modifies or reads the memory specified by the + /// pointer. + ModRefResult getModRefInfo(const StoreInst *S, const Value *P, unsigned Size); + + /// getModRefInfo (for va_args) - Return whether information about whether + /// a particular va_arg modifies or reads the memory specified by the + /// pointer. + ModRefResult getModRefInfo(const VAArgInst* I, const Value* P, unsigned Size); + + /// getModRefInfo - Return information about whether two call sites may refer + /// to the same set of memory locations. See + /// http://llvm.org/docs/AliasAnalysis.html#ModRefInfo + /// for details. + virtual ModRefResult getModRefInfo(ImmutableCallSite CS1, + ImmutableCallSite CS2); //===--------------------------------------------------------------------===// /// Higher level methods for querying mod/ref information. From stuart at apple.com Tue Sep 7 15:39:07 2010 From: stuart at apple.com (Stuart Hastings) Date: Tue, 07 Sep 2010 20:39:07 -0000 Subject: [llvm-commits] [llvm] r113281 - /llvm/trunk/test/FrontendC/2007-10-01-BuildArrayRef.c Message-ID: <20100907203907.8709C2A6C12C@llvm.org> Author: stuart Date: Tue Sep 7 15:39:07 2010 New Revision: 113281 URL: http://llvm.org/viewvc/llvm-project?rev=113281&view=rev Log: Typo. Thanks to BillW for pointing it out! Modified: llvm/trunk/test/FrontendC/2007-10-01-BuildArrayRef.c Modified: llvm/trunk/test/FrontendC/2007-10-01-BuildArrayRef.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/2007-10-01-BuildArrayRef.c?rev=113281&r1=113280&r2=113281&view=diff ============================================================================== --- llvm/trunk/test/FrontendC/2007-10-01-BuildArrayRef.c (original) +++ llvm/trunk/test/FrontendC/2007-10-01-BuildArrayRef.c Tue Sep 7 15:39:07 2010 @@ -3,7 +3,7 @@ void func() { const int *arr; - arr[0] = 1; // CXHECK: error: assignment of read-only location + arr[0] = 1; // CHECK: error: assignment of read-only location } struct foo { From resistor at mac.com Tue Sep 7 15:48:10 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 07 Sep 2010 20:48:10 -0000 Subject: [llvm-commits] [llvm] r113283 - in /llvm/trunk: include/llvm/PassRegistry.h lib/VMCore/PassRegistry.cpp Message-ID: <20100907204810.A30542A6C12C@llvm.org> Author: resistor Date: Tue Sep 7 15:48:10 2010 New Revision: 113283 URL: http://llvm.org/viewvc/llvm-project?rev=113283&view=rev Log: Fix PR7972, in which the PassRegistry was being leaked. As part of this, switch to using a ManagedStatic for the global PassRegistry instead of a ManagedCleanup, and fix a destruction ordering bug this exposed. Modified: llvm/trunk/include/llvm/PassRegistry.h llvm/trunk/lib/VMCore/PassRegistry.cpp Modified: llvm/trunk/include/llvm/PassRegistry.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/PassRegistry.h?rev=113283&r1=113282&r2=113283&view=diff ============================================================================== --- llvm/trunk/include/llvm/PassRegistry.h (original) +++ llvm/trunk/include/llvm/PassRegistry.h Tue Sep 7 15:48:10 2010 @@ -37,6 +37,7 @@ public: PassRegistry() : pImpl(0) { } + ~PassRegistry(); /// getPassRegistry - Access the global registry object, which is /// automatically initialized at application launch and destroyed by Modified: llvm/trunk/lib/VMCore/PassRegistry.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/PassRegistry.cpp?rev=113283&r1=113282&r2=113283&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/PassRegistry.cpp (original) +++ llvm/trunk/lib/VMCore/PassRegistry.cpp Tue Sep 7 15:48:10 2010 @@ -22,45 +22,14 @@ using namespace llvm; -static PassRegistry *PassRegistryObj = 0; -PassRegistry *PassRegistry::getPassRegistry() { - // Use double-checked locking to safely initialize the registrar when - // we're running in multithreaded mode. - PassRegistry* tmp = PassRegistryObj; - if (llvm_is_multithreaded()) { - sys::MemoryFence(); - if (!tmp) { - llvm_acquire_global_lock(); - tmp = PassRegistryObj; - if (!tmp) { - tmp = new PassRegistry(); - sys::MemoryFence(); - PassRegistryObj = tmp; - } - llvm_release_global_lock(); - } - } else if (!tmp) { - PassRegistryObj = new PassRegistry(); - } - - return PassRegistryObj; -} - -namespace { - -// FIXME: We use ManagedCleanup to erase the pass registrar on shutdown. +// FIXME: We use ManagedStatic to erase the pass registrar on shutdown. // Unfortunately, passes are registered with static ctors, and having // llvm_shutdown clear this map prevents successful ressurection after // llvm_shutdown is run. Ideally we should find a solution so that we don't // leak the map, AND can still resurrect after shutdown. -void cleanupPassRegistry(void*) { - if (PassRegistryObj) { - delete PassRegistryObj; - PassRegistryObj = 0; - } -} -ManagedCleanup<&cleanupPassRegistry> registryCleanup ATTRIBUTE_USED; - +static ManagedStatic PassRegistryObj; +PassRegistry *PassRegistry::getPassRegistry() { + return &*PassRegistryObj; } //===----------------------------------------------------------------------===// @@ -94,6 +63,12 @@ // Accessors // +PassRegistry::~PassRegistry() { + PassRegistryImpl *Impl = static_cast(pImpl); + if (Impl) delete Impl; + pImpl = 0; +} + const PassInfo *PassRegistry::getPassInfo(const void *TI) const { PassRegistryImpl *Impl = static_cast(getImpl()); PassRegistryImpl::MapType::const_iterator I = Impl->PassInfoMap.find(TI); @@ -188,6 +163,12 @@ } void PassRegistry::removeRegistrationListener(PassRegistrationListener *L) { + // NOTE: This is necessary, because removeRegistrationListener() can be called + // as part of the llvm_shutdown sequence. Since we have no control over the + // order of that sequence, we need to gracefully handle the case where the + // PassRegistry is destructed before the object that triggers this call. + if (!pImpl) return; + PassRegistryImpl *Impl = static_cast(getImpl()); std::vector::iterator I = std::find(Impl->Listeners.begin(), Impl->Listeners.end(), L); From resistor at mac.com Tue Sep 7 15:53:39 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 07 Sep 2010 20:53:39 -0000 Subject: [llvm-commits] [llvm] r113284 - /llvm/trunk/include/llvm/Support/ManagedStatic.h Message-ID: <20100907205339.A5E812A6C12C@llvm.org> Author: resistor Date: Tue Sep 7 15:53:39 2010 New Revision: 113284 URL: http://llvm.org/viewvc/llvm-project?rev=113284&view=rev Log: Remove dead code. ManagedCleanup is unused, and contained a serious bug in that the provided cleanup function is never actually called. Modified: llvm/trunk/include/llvm/Support/ManagedStatic.h Modified: llvm/trunk/include/llvm/Support/ManagedStatic.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ManagedStatic.h?rev=113284&r1=113283&r2=113284&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/ManagedStatic.h (original) +++ llvm/trunk/include/llvm/Support/ManagedStatic.h Tue Sep 7 15:53:39 2010 @@ -91,12 +91,6 @@ } }; -template -class ManagedCleanup : public ManagedStaticBase { -public: - void Register() { RegisterManagedStatic(0, CleanupFn); } -}; - /// llvm_shutdown - Deallocate and destroy all ManagedStatic variables. void llvm_shutdown(); From dpatel at apple.com Tue Sep 7 15:59:09 2010 From: dpatel at apple.com (Devang Patel) Date: Tue, 07 Sep 2010 20:59:09 -0000 Subject: [llvm-commits] [llvm] r113285 - in /llvm/trunk/test/CodeGen/X86: dbg-declare-fastisel.ll dbg-declare-hybrid.ll dbg-declare-isel.ll Message-ID: <20100907205909.50A2A2A6C12C@llvm.org> Author: dpatel Date: Tue Sep 7 15:59:09 2010 New Revision: 113285 URL: http://llvm.org/viewvc/llvm-project?rev=113285&view=rev Log: There is no need to force target if the test is going to run on other x86 platforms. Modified: llvm/trunk/test/CodeGen/X86/dbg-declare-fastisel.ll llvm/trunk/test/CodeGen/X86/dbg-declare-hybrid.ll llvm/trunk/test/CodeGen/X86/dbg-declare-isel.ll Modified: llvm/trunk/test/CodeGen/X86/dbg-declare-fastisel.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-declare-fastisel.ll?rev=113285&r1=113284&r2=113285&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/dbg-declare-fastisel.ll (original) +++ llvm/trunk/test/CodeGen/X86/dbg-declare-fastisel.ll Tue Sep 7 15:59:09 2010 @@ -1,5 +1,5 @@ ; This test case checks handling of llvm.dbg.declare intrinsic during fast-isel. -; RUN: llc -mtriple=x86_64-apple-darwin --disable-fp-elim -O0 %s -o %t.s +; RUN: llc --disable-fp-elim -O0 %s -o %t.s ; RUN: %compile_c -m64 %t.s -o %t.o ; RUN: %link -m64 %t.o -o %t.exe ; RUN: echo {break f1\n break f2 \n break f3 \n break f5 \n break f9 \n run \n p i \n c \n p i\n c \n p i\n c \n p i\n c \n p i.x} > %t.in @@ -10,8 +10,6 @@ ; RUN: grep "4 = 46" %t.out ; RUN: grep "5 = 51" %t.out -; XTARGET: darwin -target triple = "x86_64-apple-darwin" %struct.XYZ = type { i32, i32, i32, i32, i32 } ; Check handling of llvm.dbg.declare for an argument referred through alloca, where Modified: llvm/trunk/test/CodeGen/X86/dbg-declare-hybrid.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-declare-hybrid.ll?rev=113285&r1=113284&r2=113285&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/dbg-declare-hybrid.ll (original) +++ llvm/trunk/test/CodeGen/X86/dbg-declare-hybrid.ll Tue Sep 7 15:59:09 2010 @@ -1,6 +1,6 @@ ; This test case checks handling of llvm.dbg.declare intrinsic during hybrid mode where we begin ; using fast-isel but switch back to DAG building at some point. -; RUN: llc -mtriple=x86_64-apple-darwin --disable-fp-elim -O0 %s -o %t.s +; RUN: llc --disable-fp-elim -O0 %s -o %t.s ; RUN: %compile_c -m64 %t.s -o %t.o ; RUN: %link -m64 %t.o -o %t.exe ; RUN: echo {break f1\n break f4\n break f5\n run \n p i\n c \n p i\n c \n p i\n} > %t.in @@ -9,8 +9,6 @@ ; RUN: grep "2 = 45" %t.out ; RUN: grep "3 = 46" %t.out -; XTARGET: darwin -target triple = "x86_64-apple-darwin" %struct.XYZ = type { i32, i32, i32, i32, i32 } %0 = type { i64, i32 } define %0 @foobar() { Modified: llvm/trunk/test/CodeGen/X86/dbg-declare-isel.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-declare-isel.ll?rev=113285&r1=113284&r2=113285&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/dbg-declare-isel.ll (original) +++ llvm/trunk/test/CodeGen/X86/dbg-declare-isel.ll Tue Sep 7 15:59:09 2010 @@ -1,5 +1,5 @@ ; This test case checks handling of llvm.dbg.declare intrinsic during isel. -; RUN: llc -mtriple=x86_64-apple-darwin --disable-fp-elim -O0 -fast-isel=false %s -o %t.s +; RUN: llc --disable-fp-elim -O0 -fast-isel=false %s -o %t.s ; RUN: %compile_c -m64 %t.s -o %t.o ; RUN: %link -m64 %t.o -o %t.exe ; RUN: echo {break f1\n break f2 \n break f7 \n break f8 \n break f9 \n break f10 \n run \n p i\n c \n p i\n c \n p i.x\n c \n p i.x\n c \n p i.x \n c \n p i.x \n} > %t.in @@ -11,8 +11,6 @@ ; RUN: grep "5 = 51" %t.out ; RUN: grep "6 = 51" %t.out -; XTARGET: darwin -target triple = "x86_64-apple-darwin" %struct.XYZ = type { i32, i32, i32, i32, i32 } ; Check handling of llvm.dbg.declare for an argument referred through alloca, where From dpatel at apple.com Tue Sep 7 16:03:09 2010 From: dpatel at apple.com (Devang Patel) Date: Tue, 7 Sep 2010 14:03:09 -0700 Subject: [llvm-commits] [llvm] r113237 - in /llvm/trunk/test/CodeGen/X86: dbg-declare-fastisel.ll dbg-declare-hybrid.ll dbg-declare-isel.ll In-Reply-To: References: <20100907181756.C78E12A6C12C@llvm.org> Message-ID: <1F2CFAE9-CF30-490A-AF78-67B696F6C6C5@apple.com> On Sep 7, 2010, at 12:47 PM, Chris Lattner wrote: > > On Sep 7, 2010, at 11:17 AM, Devang Patel wrote: > >> Author: dpatel >> Date: Tue Sep 7 13:17:56 2010 >> New Revision: 113237 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=113237&view=rev >> Log: >> Fix command line used to link these test cases. > > Are these tests going to work on non-native hosts (e.g. a mips linux box)? These seem like something that should be in a different test suite. This test should in a suite that is required to be run before every codegen check-in. I update these tests so that they are not forcing a target. This should work on all x86 platforms unless there is a platform specific bug. - Devang > > -Chris > >> >> Modified: >> llvm/trunk/test/CodeGen/X86/dbg-declare-fastisel.ll >> llvm/trunk/test/CodeGen/X86/dbg-declare-hybrid.ll >> llvm/trunk/test/CodeGen/X86/dbg-declare-isel.ll >> >> Modified: llvm/trunk/test/CodeGen/X86/dbg-declare-fastisel.ll >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-declare-fastisel.ll?rev=113237&r1=113236&r2=113237&view=diff >> ============================================================================== >> --- llvm/trunk/test/CodeGen/X86/dbg-declare-fastisel.ll (original) >> +++ llvm/trunk/test/CodeGen/X86/dbg-declare-fastisel.ll Tue Sep 7 13:17:56 2010 >> @@ -1,7 +1,7 @@ >> ; This test case checks handling of llvm.dbg.declare intrinsic during fast-isel. >> ; RUN: llc -mtriple=x86_64-apple-darwin --disable-fp-elim -O0 %s -o %t.s >> ; RUN: %compile_c -m64 %t.s -o %t.o >> -; RUN: %link %t.o -o %t.exe >> +; RUN: %link -m64 %t.o -o %t.exe >> ; RUN: echo {break f1\n break f2 \n break f3 \n break f5 \n break f9 \n run \n p i \n c \n p i\n c \n p i\n c \n p i\n c \n p i.x} > %t.in >> ; RUN: gdb -q -batch -n -x %t.in %t.exe >& %t.out >> ; RUN: grep "1 = 42" %t.out >> >> Modified: llvm/trunk/test/CodeGen/X86/dbg-declare-hybrid.ll >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-declare-hybrid.ll?rev=113237&r1=113236&r2=113237&view=diff >> ============================================================================== >> --- llvm/trunk/test/CodeGen/X86/dbg-declare-hybrid.ll (original) >> +++ llvm/trunk/test/CodeGen/X86/dbg-declare-hybrid.ll Tue Sep 7 13:17:56 2010 >> @@ -2,7 +2,7 @@ >> ; using fast-isel but switch back to DAG building at some point. >> ; RUN: llc -mtriple=x86_64-apple-darwin --disable-fp-elim -O0 %s -o %t.s >> ; RUN: %compile_c -m64 %t.s -o %t.o >> -; RUN: %link %t.o -o %t.exe >> +; RUN: %link -m64 %t.o -o %t.exe >> ; RUN: echo {break f1\n break f4\n break f5\n run \n p i\n c \n p i\n c \n p i\n} > %t.in >> ; RUN: gdb -q -batch -n -x %t.in %t.exe >& %t.out >> ; RUN: grep "1 = 42" %t.out >> >> Modified: llvm/trunk/test/CodeGen/X86/dbg-declare-isel.ll >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-declare-isel.ll?rev=113237&r1=113236&r2=113237&view=diff >> ============================================================================== >> --- llvm/trunk/test/CodeGen/X86/dbg-declare-isel.ll (original) >> +++ llvm/trunk/test/CodeGen/X86/dbg-declare-isel.ll Tue Sep 7 13:17:56 2010 >> @@ -1,7 +1,7 @@ >> ; This test case checks handling of llvm.dbg.declare intrinsic during isel. >> ; RUN: llc -mtriple=x86_64-apple-darwin --disable-fp-elim -O0 -fast-isel=false %s -o %t.s >> ; RUN: %compile_c -m64 %t.s -o %t.o >> -; RUN: %link %t.o -o %t.exe >> +; RUN: %link -m64 %t.o -o %t.exe >> ; RUN: echo {break f1\n break f2 \n break f7 \n break f8 \n break f9 \n break f10 \n run \n p i\n c \n p i\n c \n p i.x\n c \n p i.x\n c \n p i.x \n c \n p i.x \n} > %t.in >> ; RUN: gdb -q -batch -n -x %t.in %t.exe >& %t.out >> ; RUN: grep "1 = 42" %t.out >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From bruno.cardoso at gmail.com Tue Sep 7 16:03:14 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 07 Sep 2010 21:03:14 -0000 Subject: [llvm-commits] [llvm] r113286 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20100907210314.AE9D52A6C12C@llvm.org> Author: bruno Date: Tue Sep 7 16:03:14 2010 New Revision: 113286 URL: http://llvm.org/viewvc/llvm-project?rev=113286&view=rev Log: Factor out some x86 vector shuffle rewriting and add comments about the direction the shuffle lowering is heading to Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=113286&r1=113285&r2=113286&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Sep 7 16:03:14 2010 @@ -4898,8 +4898,7 @@ /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15> static SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, - SelectionDAG &DAG, - const TargetLowering &TLI, DebugLoc dl) { + SelectionDAG &DAG, DebugLoc dl) { EVT VT = SVOp->getValueType(0); SDValue V1 = SVOp->getOperand(0); SDValue V2 = SVOp->getOperand(1); @@ -5252,31 +5251,14 @@ return 0; } -SDValue -X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { +static +SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG, + const X86Subtarget *Subtarget) { ShuffleVectorSDNode *SVOp = cast(Op); - SDValue V1 = Op.getOperand(0); - SDValue V2 = Op.getOperand(1); EVT VT = Op.getValueType(); DebugLoc dl = Op.getDebugLoc(); - unsigned NumElems = VT.getVectorNumElements(); - bool isMMX = VT.getSizeInBits() == 64; - bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; - bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; - bool V1IsSplat = false; - bool V2IsSplat = false; - bool HasSSE2 = Subtarget->hasSSE2() || Subtarget->hasAVX(); - bool HasSSE3 = Subtarget->hasSSE3() || Subtarget->hasAVX(); - bool HasSSSE3 = Subtarget->hasSSSE3() || Subtarget->hasAVX(); - MachineFunction &MF = DAG.getMachineFunction(); - bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize); - - // FIXME: this is somehow handled during isel by MMX pattern fragments. Remove - // the check or come up with another solution when all MMX move to intrinsics, - // but don't allow this to be considered legal, we don't want vector_shuffle - // operations to be matched during isel anymore. - if (isMMX && SVOp->isSplat()) - return Op; + SDValue V1 = Op.getOperand(0); + SDValue V2 = Op.getOperand(1); if (isZeroShuffle(SVOp)) return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); @@ -5288,27 +5270,75 @@ // If the shuffle can be profitably rewritten as a narrower shuffle, then // do it! if (VT == MVT::v8i16 || VT == MVT::v16i8) { - SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl); + SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); if (NewOp.getNode()) - return DAG.getNode(ISD::BIT_CONVERT, dl, VT, - LowerVECTOR_SHUFFLE(NewOp, DAG)); + return DAG.getNode(ISD::BIT_CONVERT, dl, VT, NewOp); } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { // FIXME: Figure out a cleaner way to do this. // Try to make use of movq to zero out the top part. if (ISD::isBuildVectorAllZeros(V2.getNode())) { - SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl); + SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); if (NewOp.getNode()) { if (isCommutedMOVL(cast(NewOp), true, false)) return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0), DAG, Subtarget, dl); } } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { - SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl); + SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); if (NewOp.getNode() && X86::isMOVLMask(cast(NewOp))) return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1), DAG, Subtarget, dl); } } + return SDValue(); +} + +SDValue +X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { + ShuffleVectorSDNode *SVOp = cast(Op); + SDValue V1 = Op.getOperand(0); + SDValue V2 = Op.getOperand(1); + EVT VT = Op.getValueType(); + DebugLoc dl = Op.getDebugLoc(); + unsigned NumElems = VT.getVectorNumElements(); + bool isMMX = VT.getSizeInBits() == 64; + bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; + bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; + bool V1IsSplat = false; + bool V2IsSplat = false; + bool HasSSE2 = Subtarget->hasSSE2() || Subtarget->hasAVX(); + bool HasSSE3 = Subtarget->hasSSE3() || Subtarget->hasAVX(); + bool HasSSSE3 = Subtarget->hasSSSE3() || Subtarget->hasAVX(); + MachineFunction &MF = DAG.getMachineFunction(); + bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize); + + // FIXME: this is somehow handled during isel by MMX pattern fragments. Remove + // the check or come up with another solution when all MMX move to intrinsics, + // but don't allow this to be considered legal, we don't want vector_shuffle + // operations to be matched during isel anymore. + if (isMMX && SVOp->isSplat()) + return Op; + + // Vector shuffle lowering takes 3 steps: + // + // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable + // narrowing and commutation of operands should be handled. + // 2) Matching of shuffles with known shuffle masks to x86 target specific + // shuffle nodes. + // 3) Rewriting of unmatched masks into new generic shuffle operations, + // so the shuffle can be broken into other shuffles and the legalizer can + // try the lowering again. + // + // The general ideia is that no vector_shuffle operation should be left to + // be matched during isel, all of them must be converted to a target specific + // node here. + + // Normalize the input vectors. Here splats, zeroed vectors, profitable + // narrowing and commutation of operands should be handled. The actual code + // doesn't include all of those, work in progress... + SDValue NewOp = NormalizeVectorShuffle(Op, DAG, Subtarget); + if (NewOp.getNode()) + return NewOp; // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and // unpckh_undef). Only use pshufd if speed is more important than size. From isanbard at gmail.com Tue Sep 7 16:07:59 2010 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 07 Sep 2010 21:07:59 -0000 Subject: [llvm-commits] [llvm] r113287 - /llvm/trunk/include/llvm/CodeGen/ValueTypes.h Message-ID: <20100907210759.7B6D52A6C12C@llvm.org> Author: void Date: Tue Sep 7 16:07:59 2010 New Revision: 113287 URL: http://llvm.org/viewvc/llvm-project?rev=113287&view=rev Log: Remove untrue comments. Modified: llvm/trunk/include/llvm/CodeGen/ValueTypes.h Modified: llvm/trunk/include/llvm/CodeGen/ValueTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ValueTypes.h?rev=113287&r1=113286&r2=113287&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/ValueTypes.h (original) +++ llvm/trunk/include/llvm/CodeGen/ValueTypes.h Tue Sep 7 16:07:59 2010 @@ -50,17 +50,17 @@ v2i8 = 12, // 2 x i8 v4i8 = 13, // 4 x i8 - v8i8 = 14, // 8 x i8 - MMX type + v8i8 = 14, // 8 x i8 v16i8 = 15, // 16 x i8 v32i8 = 16, // 32 x i8 v2i16 = 17, // 2 x i16 - v4i16 = 18, // 4 x i16 - MMX type + v4i16 = 18, // 4 x i16 v8i16 = 19, // 8 x i16 v16i16 = 20, // 16 x i16 - v2i32 = 21, // 2 x i32 - MMX type + v2i32 = 21, // 2 x i32 v4i32 = 22, // 4 x i32 v8i32 = 23, // 8 x i32 - v1i64 = 24, // 1 x i64 - MMX type + v1i64 = 24, // 1 x i64 v2i64 = 25, // 2 x i64 v4i64 = 26, // 4 x i64 v8i64 = 27, // 8 x i64 From clattner at apple.com Tue Sep 7 16:09:06 2010 From: clattner at apple.com (Chris Lattner) Date: Tue, 7 Sep 2010 14:09:06 -0700 Subject: [llvm-commits] [llvm] r113285 - in /llvm/trunk/test/CodeGen/X86: dbg-declare-fastisel.ll dbg-declare-hybrid.ll dbg-declare-isel.ll In-Reply-To: <20100907205909.50A2A2A6C12C@llvm.org> References: <20100907205909.50A2A2A6C12C@llvm.org> Message-ID: On Sep 7, 2010, at 1:59 PM, Devang Patel wrote: > Author: dpatel > Date: Tue Sep 7 15:59:09 2010 > New Revision: 113285 > > URL: http://llvm.org/viewvc/llvm-project?rev=113285&view=rev > Log: > There is no need to force target if the test is going to run on other x86 platforms. Devang, "-m64" is not a portable option to pass to the compiler. -Chris > > Modified: > llvm/trunk/test/CodeGen/X86/dbg-declare-fastisel.ll > llvm/trunk/test/CodeGen/X86/dbg-declare-hybrid.ll > llvm/trunk/test/CodeGen/X86/dbg-declare-isel.ll > > Modified: llvm/trunk/test/CodeGen/X86/dbg-declare-fastisel.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-declare-fastisel.ll?rev=113285&r1=113284&r2=113285&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/dbg-declare-fastisel.ll (original) > +++ llvm/trunk/test/CodeGen/X86/dbg-declare-fastisel.ll Tue Sep 7 15:59:09 2010 > @@ -1,5 +1,5 @@ > ; This test case checks handling of llvm.dbg.declare intrinsic during fast-isel. > -; RUN: llc -mtriple=x86_64-apple-darwin --disable-fp-elim -O0 %s -o %t.s > +; RUN: llc --disable-fp-elim -O0 %s -o %t.s > ; RUN: %compile_c -m64 %t.s -o %t.o > ; RUN: %link -m64 %t.o -o %t.exe > ; RUN: echo {break f1\n break f2 \n break f3 \n break f5 \n break f9 \n run \n p i \n c \n p i\n c \n p i\n c \n p i\n c \n p i.x} > %t.in > @@ -10,8 +10,6 @@ > ; RUN: grep "4 = 46" %t.out > ; RUN: grep "5 = 51" %t.out > > -; XTARGET: darwin > -target triple = "x86_64-apple-darwin" > %struct.XYZ = type { i32, i32, i32, i32, i32 } > > ; Check handling of llvm.dbg.declare for an argument referred through alloca, where > > Modified: llvm/trunk/test/CodeGen/X86/dbg-declare-hybrid.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-declare-hybrid.ll?rev=113285&r1=113284&r2=113285&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/dbg-declare-hybrid.ll (original) > +++ llvm/trunk/test/CodeGen/X86/dbg-declare-hybrid.ll Tue Sep 7 15:59:09 2010 > @@ -1,6 +1,6 @@ > ; This test case checks handling of llvm.dbg.declare intrinsic during hybrid mode where we begin > ; using fast-isel but switch back to DAG building at some point. > -; RUN: llc -mtriple=x86_64-apple-darwin --disable-fp-elim -O0 %s -o %t.s > +; RUN: llc --disable-fp-elim -O0 %s -o %t.s > ; RUN: %compile_c -m64 %t.s -o %t.o > ; RUN: %link -m64 %t.o -o %t.exe > ; RUN: echo {break f1\n break f4\n break f5\n run \n p i\n c \n p i\n c \n p i\n} > %t.in > @@ -9,8 +9,6 @@ > ; RUN: grep "2 = 45" %t.out > ; RUN: grep "3 = 46" %t.out > > -; XTARGET: darwin > -target triple = "x86_64-apple-darwin" > %struct.XYZ = type { i32, i32, i32, i32, i32 } > %0 = type { i64, i32 } > define %0 @foobar() { > > Modified: llvm/trunk/test/CodeGen/X86/dbg-declare-isel.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-declare-isel.ll?rev=113285&r1=113284&r2=113285&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/dbg-declare-isel.ll (original) > +++ llvm/trunk/test/CodeGen/X86/dbg-declare-isel.ll Tue Sep 7 15:59:09 2010 > @@ -1,5 +1,5 @@ > ; This test case checks handling of llvm.dbg.declare intrinsic during isel. > -; RUN: llc -mtriple=x86_64-apple-darwin --disable-fp-elim -O0 -fast-isel=false %s -o %t.s > +; RUN: llc --disable-fp-elim -O0 -fast-isel=false %s -o %t.s > ; RUN: %compile_c -m64 %t.s -o %t.o > ; RUN: %link -m64 %t.o -o %t.exe > ; RUN: echo {break f1\n break f2 \n break f7 \n break f8 \n break f9 \n break f10 \n run \n p i\n c \n p i\n c \n p i.x\n c \n p i.x\n c \n p i.x \n c \n p i.x \n} > %t.in > @@ -11,8 +11,6 @@ > ; RUN: grep "5 = 51" %t.out > ; RUN: grep "6 = 51" %t.out > > -; XTARGET: darwin > -target triple = "x86_64-apple-darwin" > %struct.XYZ = type { i32, i32, i32, i32, i32 } > > ; Check handling of llvm.dbg.declare for an argument referred through alloca, where > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From clattner at apple.com Tue Sep 7 16:10:26 2010 From: clattner at apple.com (Chris Lattner) Date: Tue, 7 Sep 2010 14:10:26 -0700 Subject: [llvm-commits] [llvm] r113237 - in /llvm/trunk/test/CodeGen/X86: dbg-declare-fastisel.ll dbg-declare-hybrid.ll dbg-declare-isel.ll In-Reply-To: <1F2CFAE9-CF30-490A-AF78-67B696F6C6C5@apple.com> References: <20100907181756.C78E12A6C12C@llvm.org> <1F2CFAE9-CF30-490A-AF78-67B696F6C6C5@apple.com> Message-ID: <7AD3A7F5-730A-4AE3-A4C7-27C229941EC5@apple.com> On Sep 7, 2010, at 2:03 PM, Devang Patel wrote: > > On Sep 7, 2010, at 12:47 PM, Chris Lattner wrote: > >> >> On Sep 7, 2010, at 11:17 AM, Devang Patel wrote: >> >>> Author: dpatel >>> Date: Tue Sep 7 13:17:56 2010 >>> New Revision: 113237 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=113237&view=rev >>> Log: >>> Fix command line used to link these test cases. >> >> Are these tests going to work on non-native hosts (e.g. a mips linux box)? These seem like something that should be in a different test suite. > > This test should in a suite that is required to be run before every codegen check-in. > > I update these tests so that they are not forcing a target. This should work on all x86 platforms unless there is a platform specific bug. lib/CodeGen/X86 needs to run on any host. You are forcing the programs to build with the X86 code generator, then run. THis won't work unless the host is x86. -Chris From dalej at apple.com Tue Sep 7 16:10:58 2010 From: dalej at apple.com (Dale Johannesen) Date: Tue, 7 Sep 2010 14:10:58 -0700 Subject: [llvm-commits] [llvm] r113261 - in /llvm/trunk: include/llvm/CodeGen/ValueTypes.h include/llvm/CodeGen/ValueTypes.td include/llvm/Intrinsics.td lib/Target/X86/X86ISelLowering.cpp lib/VMCore/ValueTypes.cpp utils/TableGen/CodeGenTarget.cpp In-Reply-To: <5409681F-BC43-46A2-A89B-E169F54BE618@gmail.com> References: <20100907200357.1CB442A6C12C@llvm.org> <2F24CED4-96A5-4F58-B7B5-68A382A74A43@apple.com> <5409681F-BC43-46A2-A89B-E169F54BE618@gmail.com> Message-ID: <7E070AEA-F31A-4415-8835-08FC6EF5337C@apple.com> On Sep 7, 2010, at 1:16 PM, Bill Wendling wrote: > On Sep 7, 2010, at 1:08 PM, Chris Lattner wrote: > On Sep 7, 2010, at 1:03 PM, Bill Wendling wrote: >> >>> Author: void >>> Date: Tue Sep 7 15:03:56 2010 >>> New Revision: 113261 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=113261&view=rev >>> Log: >>> Add an MVT::x86mmx type. It will take the place of all current MMX >>> vector types. >> >> Hi Bill, why did you mark stuff in ValueTypes.h with "- MMX type"? >> The whole idea is that those won't map onto MMX anymore. >> > Right. I was thinking that those would go away? Or at least > shouldn't be used when not doing MMX? My understanding is this is what's supposed to happen: FEs use the vector types as they currently exist, but generate intrinsics for all MMX operations. Optimizers can optimize vector types, but they won't know about the intrinsics, and therefore won't alter or create MMX operations. In the X86 BE, the existing MMX-sized MVT types are made illegal. Anything in the X86 BE currently using them is changed to use the new ones you just added. SelectionDAGBuilder (i.e. X86ISelLowering) lowers the intrinsics to use the new types instead of the existing ones. Anything using an MMX-sized vector type that's not an MMX intrinisic is lowered using the standard lowering for illegal types. From isanbard at gmail.com Tue Sep 7 16:16:53 2010 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 7 Sep 2010 14:16:53 -0700 Subject: [llvm-commits] [llvm] r113261 - in /llvm/trunk: include/llvm/CodeGen/ValueTypes.h include/llvm/CodeGen/ValueTypes.td include/llvm/Intrinsics.td lib/Target/X86/X86ISelLowering.cpp lib/VMCore/ValueTypes.cpp utils/TableGen/CodeGenTarget.cpp In-Reply-To: <7E070AEA-F31A-4415-8835-08FC6EF5337C@apple.com> References: <20100907200357.1CB442A6C12C@llvm.org> <2F24CED4-96A5-4F58-B7B5-68A382A74A43@apple.com> <5409681F-BC43-46A2-A89B-E169F54BE618@gmail.com> <7E070AEA-F31A-4415-8835-08FC6EF5337C@apple.com> Message-ID: On Sep 7, 2010, at 2:10 PM, Dale Johannesen wrote: > On Sep 7, 2010, at 1:16 PM, Bill Wendling wrote: >> On Sep 7, 2010, at 1:08 PM, Chris Lattner wrote: >> On Sep 7, 2010, at 1:03 PM, Bill Wendling wrote: >>> >>>> Author: void >>>> Date: Tue Sep 7 15:03:56 2010 >>>> New Revision: 113261 >>>> >>>> URL: http://llvm.org/viewvc/llvm-project?rev=113261&view=rev >>>> Log: >>>> Add an MVT::x86mmx type. It will take the place of all current MMX >>>> vector types. >>> >>> Hi Bill, why did you mark stuff in ValueTypes.h with "- MMX type"? >>> The whole idea is that those won't map onto MMX anymore. >>> >> Right. I was thinking that those would go away? Or at least >> shouldn't be used when not doing MMX? > > My understanding is this is what's supposed to happen: > FEs use the vector types as they currently exist, but generate > intrinsics for all MMX operations. > Optimizers can optimize vector types, but they won't know about the > intrinsics, and therefore won't alter or create MMX operations. > In the X86 BE, the existing MMX-sized MVT types are made illegal. > Anything in the X86 BE currently using them is changed to use the new > ones you just added. > SelectionDAGBuilder (i.e. X86ISelLowering) lowers the intrinsics to > use the new types instead of the existing ones. > Anything using an MMX-sized vector type that's not an MMX intrinisic > is lowered using the standard lowering for illegal types. > That was my understanding too, but I confused the "X86 BE" with "all BEs". :-) I removed the comments. -bw From grosbach at apple.com Tue Sep 7 16:30:26 2010 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 07 Sep 2010 21:30:26 -0000 Subject: [llvm-commits] [llvm] r113289 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Message-ID: <20100907213026.1890A2A6C12C@llvm.org> Author: grosbach Date: Tue Sep 7 16:30:25 2010 New Revision: 113289 URL: http://llvm.org/viewvc/llvm-project?rev=113289&view=rev Log: grammar tweak Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=113289&r1=113288&r2=113289&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Tue Sep 7 16:30:25 2010 @@ -535,7 +535,7 @@ // Load / store multiple Instructions. // -// These requires base address to be written back or one of the loaded regs. +// These require base address to be written back or one of the loaded regs. let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in { def tLDM : T1I<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts, variable_ops), From dpatel at apple.com Tue Sep 7 16:52:35 2010 From: dpatel at apple.com (Devang Patel) Date: Tue, 7 Sep 2010 14:52:35 -0700 Subject: [llvm-commits] [llvm] r113237 - in /llvm/trunk/test/CodeGen/X86: dbg-declare-fastisel.ll dbg-declare-hybrid.ll dbg-declare-isel.ll In-Reply-To: <7AD3A7F5-730A-4AE3-A4C7-27C229941EC5@apple.com> References: <20100907181756.C78E12A6C12C@llvm.org> <1F2CFAE9-CF30-490A-AF78-67B696F6C6C5@apple.com> <7AD3A7F5-730A-4AE3-A4C7-27C229941EC5@apple.com> Message-ID: On Sep 7, 2010, at 2:10 PM, Chris Lattner wrote: > > On Sep 7, 2010, at 2:03 PM, Devang Patel wrote: > >> >> On Sep 7, 2010, at 12:47 PM, Chris Lattner wrote: >> >>> >>> On Sep 7, 2010, at 11:17 AM, Devang Patel wrote: >>> >>>> Author: dpatel >>>> Date: Tue Sep 7 13:17:56 2010 >>>> New Revision: 113237 >>>> >>>> URL: http://llvm.org/viewvc/llvm-project?rev=113237&view=rev >>>> Log: >>>> Fix command line used to link these test cases. >>> >>> Are these tests going to work on non-native hosts (e.g. a mips linux box)? These seem like something that should be in a different test suite. >> >> This test should in a suite that is required to be run before every codegen check-in. >> >> I update these tests so that they are not forcing a target. This should work on all x86 platforms unless there is a platform specific bug. > > lib/CodeGen/X86 needs to run on any host. You are forcing the programs to build with the X86 code generator, then run. THis won't work unless the host is x86. Is there any way to skip the test in this case ? What else do you suggest ? - Devang From clattner at apple.com Tue Sep 7 16:55:41 2010 From: clattner at apple.com (Chris Lattner) Date: Tue, 7 Sep 2010 14:55:41 -0700 Subject: [llvm-commits] [llvm] r113237 - in /llvm/trunk/test/CodeGen/X86: dbg-declare-fastisel.ll dbg-declare-hybrid.ll dbg-declare-isel.ll In-Reply-To: References: <20100907181756.C78E12A6C12C@llvm.org> <1F2CFAE9-CF30-490A-AF78-67B696F6C6C5@apple.com> <7AD3A7F5-730A-4AE3-A4C7-27C229941EC5@apple.com> Message-ID: On Sep 7, 2010, at 2:52 PM, Devang Patel wrote: >>>>> URL: http://llvm.org/viewvc/llvm-project?rev=113237&view=rev >>>>> Log: >>>>> Fix command line used to link these test cases. >>>> >>>> Are these tests going to work on non-native hosts (e.g. a mips linux box)? These seem like something that should be in a different test suite. >>> >>> This test should in a suite that is required to be run before every codegen check-in. >>> >>> I update these tests so that they are not forcing a target. This should work on all x86 platforms unless there is a platform specific bug. >> >> lib/CodeGen/X86 needs to run on any host. You are forcing the programs to build with the X86 code generator, then run. THis won't work unless the host is x86. > > Is there any way to skip the test in this case ? What else do you suggest ? There is some XHOST thing I think, but it's better to have a dedicated place for this. It's not like these are the only debug info tests we should have. Why not put them in the gdb testsuite or something that already has a harness? -Chris From dpatel at apple.com Tue Sep 7 17:04:06 2010 From: dpatel at apple.com (Devang Patel) Date: Tue, 7 Sep 2010 15:04:06 -0700 Subject: [llvm-commits] [llvm] r113237 - in /llvm/trunk/test/CodeGen/X86: dbg-declare-fastisel.ll dbg-declare-hybrid.ll dbg-declare-isel.ll In-Reply-To: References: <20100907181756.C78E12A6C12C@llvm.org> <1F2CFAE9-CF30-490A-AF78-67B696F6C6C5@apple.com> <7AD3A7F5-730A-4AE3-A4C7-27C229941EC5@apple.com> Message-ID: On Sep 7, 2010, at 2:55 PM, Chris Lattner wrote: >>>> This test should in a suite that is required to be run before every codegen check-in. >>>> >>>> I update these tests so that they are not forcing a target. This should work on all x86 platforms unless there is a platform specific bug. >>> >>> lib/CodeGen/X86 needs to run on any host. You are forcing the programs to build with the X86 code generator, then run. THis won't work unless the host is x86. >> >> Is there any way to skip the test in this case ? What else do you suggest ? > > There is some XHOST thing I think, but it's better to have a dedicated place for this. It's not like these are the only debug info tests we should have. Why not put them in the gdb testsuite or something that already has a harness? Dependence on anything that is not required to be tested before a check-in is not scaling well. Unfortunately, code gen changes not related to debug info work accidentally breaks debug info which may go unnoticed for a while. For immediate relief I'll revert these tests soon. - Devang From dpatel at apple.com Tue Sep 7 17:03:45 2010 From: dpatel at apple.com (Devang Patel) Date: Tue, 07 Sep 2010 22:03:45 -0000 Subject: [llvm-commits] [llvm] r113293 - in /llvm/trunk/test/CodeGen/X86: dbg-declare-fastisel.ll dbg-declare-hybrid.ll dbg-declare-isel.ll Message-ID: <20100907220345.23AE92A6C12C@llvm.org> Author: dpatel Date: Tue Sep 7 17:03:44 2010 New Revision: 113293 URL: http://llvm.org/viewvc/llvm-project?rev=113293&view=rev Log: remove these tests for now. Removed: llvm/trunk/test/CodeGen/X86/dbg-declare-fastisel.ll llvm/trunk/test/CodeGen/X86/dbg-declare-hybrid.ll llvm/trunk/test/CodeGen/X86/dbg-declare-isel.ll Removed: llvm/trunk/test/CodeGen/X86/dbg-declare-fastisel.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-declare-fastisel.ll?rev=113292&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/dbg-declare-fastisel.ll (original) +++ llvm/trunk/test/CodeGen/X86/dbg-declare-fastisel.ll (removed) @@ -1,242 +0,0 @@ -; This test case checks handling of llvm.dbg.declare intrinsic during fast-isel. -; RUN: llc --disable-fp-elim -O0 %s -o %t.s -; RUN: %compile_c -m64 %t.s -o %t.o -; RUN: %link -m64 %t.o -o %t.exe -; RUN: echo {break f1\n break f2 \n break f3 \n break f5 \n break f9 \n run \n p i \n c \n p i\n c \n p i\n c \n p i\n c \n p i.x} > %t.in -; RUN: gdb -q -batch -n -x %t.in %t.exe >& %t.out -; RUN: grep "1 = 42" %t.out -; RUN: grep "2 = 43" %t.out -; RUN: grep "3 = 44" %t.out -; RUN: grep "4 = 46" %t.out -; RUN: grep "5 = 51" %t.out - -%struct.XYZ = type { i32, i32, i32, i32, i32 } - -; Check handling of llvm.dbg.declare for an argument referred through alloca, where -; alloca dominates llvm.dbg.declare -define i32 @f1(i32 %i) nounwind ssp { -entry: - %i.addr = alloca i32, align 4 - store i32 %i, i32* %i.addr, align 4 - call void @llvm.dbg.declare(metadata !{i32* %i.addr}, metadata !16), !dbg !17 - %tmp = load i32* %i.addr, align 4, !dbg !18 - ret i32 %tmp, !dbg !18 -} - -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone - -; Check handling of llvm.dbg.declare for an argument referred through alloca, where -; llvm.dbg.declare dominates alloca. -define i32 @f2(i32 %i) nounwind ssp { -entry: - call void @llvm.dbg.declare(metadata !{i32* %i.addr}, metadata !20), !dbg !21 - %i.addr = alloca i32, align 4 - store i32 %i, i32* %i.addr, align 4 - %tmp = load i32* %i.addr, align 4, !dbg !22 - ret i32 %tmp, !dbg !22 -} - -; Check handling of an argument referred directly by llvm.dbg.declare where at least -; one argument use dominates llvm.dbg.declare. -define i32 @f3(i32 %i) nounwind ssp { -entry: - %i.addr = alloca i32, align 4 - store i32 %i, i32* %i.addr, align 4 - call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !24), !dbg !25 - %tmp = load i32* %i.addr, align 4, !dbg !26 - ret i32 %tmp, !dbg !26 -} - -; Check handling of an argument referred directly by llvm.dbg.declare where -; llvm.dbg.declare dominates all uses of argument. -define i32 @f4(i32 %i) nounwind ssp { -entry: - call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !28), !dbg !29 - ret i32 %i, !dbg !30 -} - -; Check handling of an argument referred directly by llvm.dbg.declare where -; llvm.dbg.declare dominates all uses of argument in separate basic block. -define i32 @f5(i32 %i) nounwind ssp { -entry: - call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !32), !dbg !33 - br label %bbr -bbr: - ret i32 %i, !dbg !34 -} - -; Check handling of an argument referred directly by llvm.dbg.declare where -; argument is not used. -define i32 @f6(i32 %i) nounwind ssp { -entry: - call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !36), !dbg !37 - ret i32 1, !dbg !38 -} - -; Check handling of an byval argument referred directly by llvm.dbg.declare where -; argument is not used. -define i32 @f7(%struct.XYZ* byval %i) nounwind ssp { -entry: - call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !40), !dbg !48 - ret i32 1, !dbg !49 -} - -; Check handling of an byval argument referred directly by llvm.dbg.declare where -; argument use dominates llvm.dbg.declare. -define i32 @f8(%struct.XYZ* byval %i) nounwind ssp { -entry: - %tmp = getelementptr inbounds %struct.XYZ* %i, i32 0, i32 1, !dbg !53 - %tmp1 = load i32* %tmp, align 4, !dbg !53 - call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !51), !dbg !52 - ret i32 %tmp1, !dbg !53 -} - -; Check handling of an byval argument referred directly by llvm.dbg.declare where -; llvm.dbg.declare dominates all uses of argument. -define i32 @f9(%struct.XYZ* byval %i) nounwind ssp { -entry: - call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !55), !dbg !56 - %tmp = getelementptr inbounds %struct.XYZ* %i, i32 0, i32 2, !dbg !57 - %tmp1 = load i32* %tmp, align 4, !dbg !57 - ret i32 %tmp1, !dbg !57 -} - -; Check handling of an byval argument referred directly by llvm.dbg.declare where -; llvm.dbg.declare dominates all uses of argument in separate basic block. -define i32 @f10(%struct.XYZ* byval %i) nounwind ssp { -entry: - call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !59), !dbg !60 - br label %bbr -bbr: - %tmp = getelementptr inbounds %struct.XYZ* %i, i32 0, i32 3, !dbg !61 - %tmp1 = load i32* %tmp, align 4, !dbg !61 - ret i32 %tmp1, !dbg !61 -} - -define i32 @main() nounwind ssp { -entry: - %retval = alloca i32, align 4 - %abc = alloca %struct.XYZ, align 4 - %agg.tmp = alloca %struct.XYZ, align 4 - %agg.tmp13 = alloca %struct.XYZ, align 4 - %agg.tmp17 = alloca %struct.XYZ, align 4 - %agg.tmp21 = alloca %struct.XYZ, align 4 - store i32 0, i32* %retval - %call = call i32 @f1(i32 42), !dbg !63 - %call1 = call i32 @f2(i32 43), !dbg !65 - %call2 = call i32 @f3(i32 44), !dbg !66 - %call3 = call i32 @f4(i32 45), !dbg !67 - %call4 = call i32 @f5(i32 46), !dbg !68 - %call5 = call i32 @f6(i32 47), !dbg !69 - call void @llvm.dbg.declare(metadata !{%struct.XYZ* %abc}, metadata !70), !dbg !71 - %tmp = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 0, !dbg !72 - store i32 51, i32* %tmp, align 4, !dbg !72 - %tmp6 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 1, !dbg !72 - store i32 52, i32* %tmp6, align 4, !dbg !72 - %tmp7 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 2, !dbg !72 - store i32 53, i32* %tmp7, align 4, !dbg !72 - %tmp8 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 3, !dbg !72 - store i32 54, i32* %tmp8, align 4, !dbg !72 - %tmp9 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 4, !dbg !72 - store i32 55, i32* %tmp9, align 4, !dbg !72 - %tmp10 = bitcast %struct.XYZ* %agg.tmp to i8*, !dbg !73 - %tmp11 = bitcast %struct.XYZ* %abc to i8*, !dbg !73 - call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp10, i8* %tmp11, i64 20, i32 4, i1 false), !dbg !73 - %call12 = call i32 @f7(%struct.XYZ* byval %agg.tmp), !dbg !73 - %tmp14 = bitcast %struct.XYZ* %agg.tmp13 to i8*, !dbg !74 - %tmp15 = bitcast %struct.XYZ* %abc to i8*, !dbg !74 - call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp14, i8* %tmp15, i64 20, i32 4, i1 false), !dbg !74 - %call16 = call i32 @f8(%struct.XYZ* byval %agg.tmp13), !dbg !74 - %tmp18 = bitcast %struct.XYZ* %agg.tmp17 to i8*, !dbg !75 - %tmp19 = bitcast %struct.XYZ* %abc to i8*, !dbg !75 - call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp18, i8* %tmp19, i64 20, i32 4, i1 false), !dbg !75 - %call20 = call i32 @f9(%struct.XYZ* byval %agg.tmp17), !dbg !75 - %tmp22 = bitcast %struct.XYZ* %agg.tmp21 to i8*, !dbg !76 - %tmp23 = bitcast %struct.XYZ* %abc to i8*, !dbg !76 - call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp22, i8* %tmp23, i64 20, i32 4, i1 false), !dbg !76 - %call24 = call i32 @f10(%struct.XYZ* byval %agg.tmp21), !dbg !76 - ret i32 0, !dbg !77 -} - -declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind - -!llvm.dbg.sp = !{!0, !6, !7, !8, !9, !10, !11, !12, !13, !14, !15} - -!0 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f1", metadata !"f1", metadata !"f1", metadata !1, i32 11, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f1} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 524329, metadata !"arg.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 524305, i32 0, i32 12, metadata !"arg.c", metadata !"/private/tmp", metadata !"clang version 2.8 (trunk 112967)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!3 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] -!4 = metadata !{metadata !5} -!5 = metadata !{i32 524324, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f2", metadata !"f2", metadata !"f2", metadata !1, i32 12, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f2} ; [ DW_TAG_subprogram ] -!7 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f3", metadata !"f3", metadata !"f3", metadata !1, i32 13, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f3} ; [ DW_TAG_subprogram ] -!8 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f4", metadata !"f4", metadata !"f4", metadata !1, i32 14, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f4} ; [ DW_TAG_subprogram ] -!9 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f5", metadata !"f5", metadata !"f5", metadata !1, i32 15, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f5} ; [ DW_TAG_subprogram ] -!10 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f6", metadata !"f6", metadata !"f6", metadata !1, i32 16, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f6} ; [ DW_TAG_subprogram ] -!11 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f7", metadata !"f7", metadata !"f7", metadata !1, i32 17, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f7} ; [ DW_TAG_subprogram ] -!12 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f8", metadata !"f8", metadata !"f8", metadata !1, i32 18, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f8} ; [ DW_TAG_subprogram ] -!13 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f9", metadata !"f9", metadata !"f9", metadata !1, i32 19, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f9} ; [ DW_TAG_subprogram ] -!14 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f10", metadata !"f10", metadata !"f10", metadata !1, i32 20, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f10} ; [ DW_TAG_subprogram ] -!15 = metadata !{i32 524334, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"main", metadata !1, i32 23, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @main} ; [ DW_TAG_subprogram ] -!16 = metadata !{i32 524545, metadata !0, metadata !"i", metadata !1, i32 11, metadata !5} ; [ DW_TAG_arg_variable ] -!17 = metadata !{i32 11, i32 12, metadata !0, null} -!18 = metadata !{i32 11, i32 17, metadata !19, null} -!19 = metadata !{i32 524299, metadata !0, i32 11, i32 15, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] -!20 = metadata !{i32 524545, metadata !6, metadata !"i", metadata !1, i32 12, metadata !5} ; [ DW_TAG_arg_variable ] -!21 = metadata !{i32 12, i32 12, metadata !6, null} -!22 = metadata !{i32 12, i32 17, metadata !23, null} -!23 = metadata !{i32 524299, metadata !6, i32 12, i32 15, metadata !1, i32 1} ; [ DW_TAG_lexical_block ] -!24 = metadata !{i32 524545, metadata !7, metadata !"i", metadata !1, i32 13, metadata !5} ; [ DW_TAG_arg_variable ] -!25 = metadata !{i32 13, i32 12, metadata !7, null} -!26 = metadata !{i32 13, i32 17, metadata !27, null} -!27 = metadata !{i32 524299, metadata !7, i32 13, i32 15, metadata !1, i32 2} ; [ DW_TAG_lexical_block ] -!28 = metadata !{i32 524545, metadata !8, metadata !"i", metadata !1, i32 14, metadata !5} ; [ DW_TAG_arg_variable ] -!29 = metadata !{i32 14, i32 12, metadata !8, null} -!30 = metadata !{i32 14, i32 17, metadata !31, null} -!31 = metadata !{i32 524299, metadata !8, i32 14, i32 15, metadata !1, i32 3} ; [ DW_TAG_lexical_block ] -!32 = metadata !{i32 524545, metadata !9, metadata !"i", metadata !1, i32 15, metadata !5} ; [ DW_TAG_arg_variable ] -!33 = metadata !{i32 15, i32 12, metadata !9, null} -!34 = metadata !{i32 15, i32 17, metadata !35, null} -!35 = metadata !{i32 524299, metadata !9, i32 15, i32 15, metadata !1, i32 4} ; [ DW_TAG_lexical_block ] -!36 = metadata !{i32 524545, metadata !10, metadata !"i", metadata !1, i32 16, metadata !5} ; [ DW_TAG_arg_variable ] -!37 = metadata !{i32 16, i32 12, metadata !10, null} -!38 = metadata !{i32 16, i32 17, metadata !39, null} -!39 = metadata !{i32 524299, metadata !10, i32 16, i32 15, metadata !1, i32 5} ; [ DW_TAG_lexical_block ] -!40 = metadata !{i32 524545, metadata !11, metadata !"i", metadata !1, i32 17, metadata !41} ; [ DW_TAG_arg_variable ] -!41 = metadata !{i32 524307, metadata !1, metadata !"XYZ", metadata !1, i32 2, i64 160, i64 32, i64 0, i32 0, null, metadata !42, i32 0, null} ; [ DW_TAG_structure_type ] -!42 = metadata !{metadata !43, metadata !44, metadata !45, metadata !46, metadata !47} -!43 = metadata !{i32 524301, metadata !1, metadata !"x", metadata !1, i32 3, i64 32, i64 32, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] -!44 = metadata !{i32 524301, metadata !1, metadata !"y", metadata !1, i32 4, i64 32, i64 32, i64 32, i32 0, metadata !5} ; [ DW_TAG_member ] -!45 = metadata !{i32 524301, metadata !1, metadata !"z", metadata !1, i32 5, i64 32, i64 32, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] -!46 = metadata !{i32 524301, metadata !1, metadata !"a", metadata !1, i32 6, i64 32, i64 32, i64 96, i32 0, metadata !5} ; [ DW_TAG_member ] -!47 = metadata !{i32 524301, metadata !1, metadata !"b", metadata !1, i32 7, i64 32, i64 32, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] -!48 = metadata !{i32 17, i32 19, metadata !11, null} -!49 = metadata !{i32 17, i32 24, metadata !50, null} -!50 = metadata !{i32 524299, metadata !11, i32 17, i32 22, metadata !1, i32 6} ; [ DW_TAG_lexical_block ] -!51 = metadata !{i32 524545, metadata !12, metadata !"i", metadata !1, i32 18, metadata !41} ; [ DW_TAG_arg_variable ] -!52 = metadata !{i32 18, i32 19, metadata !12, null} -!53 = metadata !{i32 18, i32 24, metadata !54, null} -!54 = metadata !{i32 524299, metadata !12, i32 18, i32 22, metadata !1, i32 7} ; [ DW_TAG_lexical_block ] -!55 = metadata !{i32 524545, metadata !13, metadata !"i", metadata !1, i32 19, metadata !41} ; [ DW_TAG_arg_variable ] -!56 = metadata !{i32 19, i32 19, metadata !13, null} -!57 = metadata !{i32 19, i32 24, metadata !58, null} -!58 = metadata !{i32 524299, metadata !13, i32 19, i32 22, metadata !1, i32 8} ; [ DW_TAG_lexical_block ] -!59 = metadata !{i32 524545, metadata !14, metadata !"i", metadata !1, i32 20, metadata !41} ; [ DW_TAG_arg_variable ] -!60 = metadata !{i32 20, i32 20, metadata !14, null} -!61 = metadata !{i32 20, i32 25, metadata !62, null} -!62 = metadata !{i32 524299, metadata !14, i32 20, i32 23, metadata !1, i32 9} ; [ DW_TAG_lexical_block ] -!63 = metadata !{i32 24, i32 3, metadata !64, null} -!64 = metadata !{i32 524299, metadata !15, i32 23, i32 12, metadata !1, i32 10} ; [ DW_TAG_lexical_block ] -!65 = metadata !{i32 25, i32 3, metadata !64, null} -!66 = metadata !{i32 26, i32 3, metadata !64, null} -!67 = metadata !{i32 27, i32 3, metadata !64, null} -!68 = metadata !{i32 28, i32 3, metadata !64, null} -!69 = metadata !{i32 29, i32 3, metadata !64, null} -!70 = metadata !{i32 524544, metadata !64, metadata !"abc", metadata !1, i32 30, metadata !41} ; [ DW_TAG_auto_variable ] -!71 = metadata !{i32 30, i32 14, metadata !64, null} -!72 = metadata !{i32 30, i32 17, metadata !64, null} -!73 = metadata !{i32 31, i32 3, metadata !64, null} -!74 = metadata !{i32 32, i32 3, metadata !64, null} -!75 = metadata !{i32 33, i32 3, metadata !64, null} -!76 = metadata !{i32 34, i32 3, metadata !64, null} -!77 = metadata !{i32 36, i32 3, metadata !64, null} Removed: llvm/trunk/test/CodeGen/X86/dbg-declare-hybrid.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-declare-hybrid.ll?rev=113292&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/dbg-declare-hybrid.ll (original) +++ llvm/trunk/test/CodeGen/X86/dbg-declare-hybrid.ll (removed) @@ -1,265 +0,0 @@ -; This test case checks handling of llvm.dbg.declare intrinsic during hybrid mode where we begin -; using fast-isel but switch back to DAG building at some point. -; RUN: llc --disable-fp-elim -O0 %s -o %t.s -; RUN: %compile_c -m64 %t.s -o %t.o -; RUN: %link -m64 %t.o -o %t.exe -; RUN: echo {break f1\n break f4\n break f5\n run \n p i\n c \n p i\n c \n p i\n} > %t.in -; RUN: gdb -q -batch -n -x %t.in %t.exe >& %t.out -; RUN: grep "1 = 42" %t.out -; RUN: grep "2 = 45" %t.out -; RUN: grep "3 = 46" %t.out - -%struct.XYZ = type { i32, i32, i32, i32, i32 } -%0 = type { i64, i32 } -define %0 @foobar() { - ret i64 6, i32 7 -} - -; Check handling of llvm.dbg.declare for an argument referred through alloca, where -; alloca dominates llvm.dbg.declare -define i32 @f1(i32 %i) nounwind ssp { -entry: - %i.addr = alloca i32, align 4 - store i32 %i, i32* %i.addr, align 4 - %call = call %0 @foobar() - call void @llvm.dbg.declare(metadata !{i32* %i.addr}, metadata !16), !dbg !17 - %call2 = call %0 @foobar() - %tmp = load i32* %i.addr, align 4, !dbg !18 - ret i32 %tmp, !dbg !18 -} - -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone - -; Check handling of llvm.dbg.declare for an argument referred through alloca, where -; llvm.dbg.declare dominates alloca. -define i32 @f2(i32 %i) nounwind ssp { -entry: - %call = call %0 @foobar() - call void @llvm.dbg.declare(metadata !{i32* %i.addr}, metadata !20), !dbg !21 - %call2 = call %0 @foobar() - %i.addr = alloca i32, align 4 - store i32 %i, i32* %i.addr, align 4 - %tmp = load i32* %i.addr, align 4, !dbg !22 - ret i32 %tmp, !dbg !22 -} - -; Check handling of an argument referred directly by llvm.dbg.declare where at least -; one argument use dominates llvm.dbg.declare. -define i32 @f3(i32 %i) nounwind ssp { -entry: - %i.addr = alloca i32, align 4 - store i32 %i, i32* %i.addr, align 4 - %call = call %0 @foobar() - call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !24), !dbg !2 - %call2 = call %0 @foobar() - %tmp = load i32* %i.addr, align 4, !dbg !26 - ret i32 %tmp, !dbg !26 -} - -; Check handling of an argument referred directly by llvm.dbg.declare where -; llvm.dbg.declare dominates all uses of argument. -define i32 @f4(i32 %i) nounwind ssp { -entry: - %call = call %0 @foobar() - call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !28), !dbg !29 - %call2 = call %0 @foobar() - ret i32 %i, !dbg !30 -} - -; Check handling of an argument referred directly by llvm.dbg.declare where -; llvm.dbg.declare dominates all uses of argument in separate basic block. -define i32 @f5(i32 %i) nounwind ssp { -entry: - %call = call %0 @foobar() - call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !32), !dbg !33 - %call2 = call %0 @foobar() - br label %bbr -bbr: - ret i32 %i, !dbg !34 -} - -; Check handling of an argument referred directly by llvm.dbg.declare where -; argument is not used. -define i32 @f6(i32 %i) nounwind ssp { -entry: - %call = call %0 @foobar() - call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !36), !dbg !37 - %call2 = call %0 @foobar() - ret i32 1, !dbg !38 -} - -; Check handling of an byval argument referred directly by llvm.dbg.declare where -; argument is not used. -define i32 @f7(%struct.XYZ* byval %i) nounwind ssp { -entry: - %call = call %0 @foobar() - call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !40), !dbg !48 - %call2 = call %0 @foobar() - ret i32 1, !dbg !49 -} - -; Check handling of an byval argument referred directly by llvm.dbg.declare where -; argument use dominates llvm.dbg.declare. -define i32 @f8(%struct.XYZ* byval %i) nounwind ssp { -entry: - %tmp = getelementptr inbounds %struct.XYZ* %i, i32 0, i32 1, !dbg !53 - %tmp1 = load i32* %tmp, align 4, !dbg !53 - %call = call %0 @foobar() - call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !51), !dbg !52 - %call2 = call %0 @foobar() - ret i32 %tmp1, !dbg !53 -} - -; Check handling of an byval argument referred directly by llvm.dbg.declare where -; llvm.dbg.declare dominates all uses of argument. -define i32 @f9(%struct.XYZ* byval %i) nounwind ssp { -entry: - %call = call %0 @foobar() - call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !55), !dbg !56 - %call2 = call %0 @foobar() - %tmp = getelementptr inbounds %struct.XYZ* %i, i32 0, i32 2, !dbg !57 - %tmp1 = load i32* %tmp, align 4, !dbg !57 - ret i32 %tmp1, !dbg !57 -} - -; Check handling of an byval argument referred directly by llvm.dbg.declare where -; llvm.dbg.declare dominates all uses of argument in separate basic block. -define i32 @f10(%struct.XYZ* byval %i) nounwind ssp { -entry: - %call = call %0 @foobar() - call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !59), !dbg !60 - %call2 = call %0 @foobar() - br label %bbr -bbr: - %tmp = getelementptr inbounds %struct.XYZ* %i, i32 0, i32 3, !dbg !61 - %tmp1 = load i32* %tmp, align 4, !dbg !61 - ret i32 %tmp1, !dbg !61 -} - -define i32 @main() nounwind ssp { -entry: - %retval = alloca i32, align 4 - %abc = alloca %struct.XYZ, align 4 - %agg.tmp = alloca %struct.XYZ, align 4 - %agg.tmp13 = alloca %struct.XYZ, align 4 - %agg.tmp17 = alloca %struct.XYZ, align 4 - %agg.tmp21 = alloca %struct.XYZ, align 4 - store i32 0, i32* %retval - %call = call i32 @f1(i32 42), !dbg !63 - %call1 = call i32 @f2(i32 43), !dbg !65 - %call2 = call i32 @f3(i32 44), !dbg !66 - %call3 = call i32 @f4(i32 45), !dbg !67 - %call4 = call i32 @f5(i32 46), !dbg !68 - %call5 = call i32 @f6(i32 47), !dbg !69 - call void @llvm.dbg.declare(metadata !{%struct.XYZ* %abc}, metadata !70), !dbg !71 - %tmp = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 0, !dbg !72 - store i32 51, i32* %tmp, align 4, !dbg !72 - %tmp6 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 1, !dbg !72 - store i32 52, i32* %tmp6, align 4, !dbg !72 - %tmp7 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 2, !dbg !72 - store i32 53, i32* %tmp7, align 4, !dbg !72 - %tmp8 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 3, !dbg !72 - store i32 54, i32* %tmp8, align 4, !dbg !72 - %tmp9 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 4, !dbg !72 - store i32 55, i32* %tmp9, align 4, !dbg !72 - %tmp10 = bitcast %struct.XYZ* %agg.tmp to i8*, !dbg !73 - %tmp11 = bitcast %struct.XYZ* %abc to i8*, !dbg !73 - call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp10, i8* %tmp11, i64 20, i32 4, i1 false), !dbg !73 - %call12 = call i32 @f7(%struct.XYZ* byval %agg.tmp), !dbg !73 - %tmp14 = bitcast %struct.XYZ* %agg.tmp13 to i8*, !dbg !74 - %tmp15 = bitcast %struct.XYZ* %abc to i8*, !dbg !74 - call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp14, i8* %tmp15, i64 20, i32 4, i1 false), !dbg !74 - %call16 = call i32 @f8(%struct.XYZ* byval %agg.tmp13), !dbg !74 - %tmp18 = bitcast %struct.XYZ* %agg.tmp17 to i8*, !dbg !75 - %tmp19 = bitcast %struct.XYZ* %abc to i8*, !dbg !75 - call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp18, i8* %tmp19, i64 20, i32 4, i1 false), !dbg !75 - %call20 = call i32 @f9(%struct.XYZ* byval %agg.tmp17), !dbg !75 - %tmp22 = bitcast %struct.XYZ* %agg.tmp21 to i8*, !dbg !76 - %tmp23 = bitcast %struct.XYZ* %abc to i8*, !dbg !76 - call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp22, i8* %tmp23, i64 20, i32 4, i1 false), !dbg !76 - %call24 = call i32 @f10(%struct.XYZ* byval %agg.tmp21), !dbg !76 - ret i32 0, !dbg !77 -} - -declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind - -!llvm.dbg.sp = !{!0, !6, !7, !8, !9, !10, !11, !12, !13, !14, !15} - -!0 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f1", metadata !"f1", metadata !"f1", metadata !1, i32 11, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f1} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 524329, metadata !"arg.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 524305, i32 0, i32 12, metadata !"arg.c", metadata !"/private/tmp", metadata !"clang version 2.8 (trunk 112967)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!3 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] -!4 = metadata !{metadata !5} -!5 = metadata !{i32 524324, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f2", metadata !"f2", metadata !"f2", metadata !1, i32 12, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f2} ; [ DW_TAG_subprogram ] -!7 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f3", metadata !"f3", metadata !"f3", metadata !1, i32 13, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f3} ; [ DW_TAG_subprogram ] -!8 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f4", metadata !"f4", metadata !"f4", metadata !1, i32 14, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f4} ; [ DW_TAG_subprogram ] -!9 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f5", metadata !"f5", metadata !"f5", metadata !1, i32 15, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f5} ; [ DW_TAG_subprogram ] -!10 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f6", metadata !"f6", metadata !"f6", metadata !1, i32 16, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f6} ; [ DW_TAG_subprogram ] -!11 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f7", metadata !"f7", metadata !"f7", metadata !1, i32 17, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f7} ; [ DW_TAG_subprogram ] -!12 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f8", metadata !"f8", metadata !"f8", metadata !1, i32 18, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f8} ; [ DW_TAG_subprogram ] -!13 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f9", metadata !"f9", metadata !"f9", metadata !1, i32 19, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f9} ; [ DW_TAG_subprogram ] -!14 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f10", metadata !"f10", metadata !"f10", metadata !1, i32 20, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f10} ; [ DW_TAG_subprogram ] -!15 = metadata !{i32 524334, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"main", metadata !1, i32 23, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @main} ; [ DW_TAG_subprogram ] -!16 = metadata !{i32 524545, metadata !0, metadata !"i", metadata !1, i32 11, metadata !5} ; [ DW_TAG_arg_variable ] -!17 = metadata !{i32 11, i32 12, metadata !0, null} -!18 = metadata !{i32 11, i32 17, metadata !19, null} -!19 = metadata !{i32 524299, metadata !0, i32 11, i32 15, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] -!20 = metadata !{i32 524545, metadata !6, metadata !"i", metadata !1, i32 12, metadata !5} ; [ DW_TAG_arg_variable ] -!21 = metadata !{i32 12, i32 12, metadata !6, null} -!22 = metadata !{i32 12, i32 17, metadata !23, null} -!23 = metadata !{i32 524299, metadata !6, i32 12, i32 15, metadata !1, i32 1} ; [ DW_TAG_lexical_block ] -!24 = metadata !{i32 524545, metadata !7, metadata !"i", metadata !1, i32 13, metadata !5} ; [ DW_TAG_arg_variable ] -!25 = metadata !{i32 13, i32 12, metadata !7, null} -!26 = metadata !{i32 13, i32 17, metadata !27, null} -!27 = metadata !{i32 524299, metadata !7, i32 13, i32 15, metadata !1, i32 2} ; [ DW_TAG_lexical_block ] -!28 = metadata !{i32 524545, metadata !8, metadata !"i", metadata !1, i32 14, metadata !5} ; [ DW_TAG_arg_variable ] -!29 = metadata !{i32 14, i32 12, metadata !8, null} -!30 = metadata !{i32 14, i32 17, metadata !31, null} -!31 = metadata !{i32 524299, metadata !8, i32 14, i32 15, metadata !1, i32 3} ; [ DW_TAG_lexical_block ] -!32 = metadata !{i32 524545, metadata !9, metadata !"i", metadata !1, i32 15, metadata !5} ; [ DW_TAG_arg_variable ] -!33 = metadata !{i32 15, i32 12, metadata !9, null} -!34 = metadata !{i32 15, i32 17, metadata !35, null} -!35 = metadata !{i32 524299, metadata !9, i32 15, i32 15, metadata !1, i32 4} ; [ DW_TAG_lexical_block ] -!36 = metadata !{i32 524545, metadata !10, metadata !"i", metadata !1, i32 16, metadata !5} ; [ DW_TAG_arg_variable ] -!37 = metadata !{i32 16, i32 12, metadata !10, null} -!38 = metadata !{i32 16, i32 17, metadata !39, null} -!39 = metadata !{i32 524299, metadata !10, i32 16, i32 15, metadata !1, i32 5} ; [ DW_TAG_lexical_block ] -!40 = metadata !{i32 524545, metadata !11, metadata !"i", metadata !1, i32 17, metadata !41} ; [ DW_TAG_arg_variable ] -!41 = metadata !{i32 524307, metadata !1, metadata !"XYZ", metadata !1, i32 2, i64 160, i64 32, i64 0, i32 0, null, metadata !42, i32 0, null} ; [ DW_TAG_structure_type ] -!42 = metadata !{metadata !43, metadata !44, metadata !45, metadata !46, metadata !47} -!43 = metadata !{i32 524301, metadata !1, metadata !"x", metadata !1, i32 3, i64 32, i64 32, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] -!44 = metadata !{i32 524301, metadata !1, metadata !"y", metadata !1, i32 4, i64 32, i64 32, i64 32, i32 0, metadata !5} ; [ DW_TAG_member ] -!45 = metadata !{i32 524301, metadata !1, metadata !"z", metadata !1, i32 5, i64 32, i64 32, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] -!46 = metadata !{i32 524301, metadata !1, metadata !"a", metadata !1, i32 6, i64 32, i64 32, i64 96, i32 0, metadata !5} ; [ DW_TAG_member ] -!47 = metadata !{i32 524301, metadata !1, metadata !"b", metadata !1, i32 7, i64 32, i64 32, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] -!48 = metadata !{i32 17, i32 19, metadata !11, null} -!49 = metadata !{i32 17, i32 24, metadata !50, null} -!50 = metadata !{i32 524299, metadata !11, i32 17, i32 22, metadata !1, i32 6} ; [ DW_TAG_lexical_block ] -!51 = metadata !{i32 524545, metadata !12, metadata !"i", metadata !1, i32 18, metadata !41} ; [ DW_TAG_arg_variable ] -!52 = metadata !{i32 18, i32 19, metadata !12, null} -!53 = metadata !{i32 18, i32 24, metadata !54, null} -!54 = metadata !{i32 524299, metadata !12, i32 18, i32 22, metadata !1, i32 7} ; [ DW_TAG_lexical_block ] -!55 = metadata !{i32 524545, metadata !13, metadata !"i", metadata !1, i32 19, metadata !41} ; [ DW_TAG_arg_variable ] -!56 = metadata !{i32 19, i32 19, metadata !13, null} -!57 = metadata !{i32 19, i32 24, metadata !58, null} -!58 = metadata !{i32 524299, metadata !13, i32 19, i32 22, metadata !1, i32 8} ; [ DW_TAG_lexical_block ] -!59 = metadata !{i32 524545, metadata !14, metadata !"i", metadata !1, i32 20, metadata !41} ; [ DW_TAG_arg_variable ] -!60 = metadata !{i32 20, i32 20, metadata !14, null} -!61 = metadata !{i32 20, i32 25, metadata !62, null} -!62 = metadata !{i32 524299, metadata !14, i32 20, i32 23, metadata !1, i32 9} ; [ DW_TAG_lexical_block ] -!63 = metadata !{i32 24, i32 3, metadata !64, null} -!64 = metadata !{i32 524299, metadata !15, i32 23, i32 12, metadata !1, i32 10} ; [ DW_TAG_lexical_block ] -!65 = metadata !{i32 25, i32 3, metadata !64, null} -!66 = metadata !{i32 26, i32 3, metadata !64, null} -!67 = metadata !{i32 27, i32 3, metadata !64, null} -!68 = metadata !{i32 28, i32 3, metadata !64, null} -!69 = metadata !{i32 29, i32 3, metadata !64, null} -!70 = metadata !{i32 524544, metadata !64, metadata !"abc", metadata !1, i32 30, metadata !41} ; [ DW_TAG_auto_variable ] -!71 = metadata !{i32 30, i32 14, metadata !64, null} -!72 = metadata !{i32 30, i32 17, metadata !64, null} -!73 = metadata !{i32 31, i32 3, metadata !64, null} -!74 = metadata !{i32 32, i32 3, metadata !64, null} -!75 = metadata !{i32 33, i32 3, metadata !64, null} -!76 = metadata !{i32 34, i32 3, metadata !64, null} -!77 = metadata !{i32 36, i32 3, metadata !64, null} Removed: llvm/trunk/test/CodeGen/X86/dbg-declare-isel.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-declare-isel.ll?rev=113292&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/dbg-declare-isel.ll (original) +++ llvm/trunk/test/CodeGen/X86/dbg-declare-isel.ll (removed) @@ -1,243 +0,0 @@ -; This test case checks handling of llvm.dbg.declare intrinsic during isel. -; RUN: llc --disable-fp-elim -O0 -fast-isel=false %s -o %t.s -; RUN: %compile_c -m64 %t.s -o %t.o -; RUN: %link -m64 %t.o -o %t.exe -; RUN: echo {break f1\n break f2 \n break f7 \n break f8 \n break f9 \n break f10 \n run \n p i\n c \n p i\n c \n p i.x\n c \n p i.x\n c \n p i.x \n c \n p i.x \n} > %t.in -; RUN: gdb -q -batch -n -x %t.in %t.exe >& %t.out -; RUN: grep "1 = 42" %t.out -; RUN: grep "2 = 43" %t.out -; RUN: grep "3 = 51" %t.out -; RUN: grep "4 = 51" %t.out -; RUN: grep "5 = 51" %t.out -; RUN: grep "6 = 51" %t.out - -%struct.XYZ = type { i32, i32, i32, i32, i32 } - -; Check handling of llvm.dbg.declare for an argument referred through alloca, where -; alloca dominates llvm.dbg.declare -define i32 @f1(i32 %i) nounwind ssp { -entry: - %i.addr = alloca i32, align 4 - store i32 %i, i32* %i.addr, align 4 - call void @llvm.dbg.declare(metadata !{i32* %i.addr}, metadata !16), !dbg !17 - %tmp = load i32* %i.addr, align 4, !dbg !18 - ret i32 %tmp, !dbg !18 -} - -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone - -; Check handling of llvm.dbg.declare for an argument referred through alloca, where -; llvm.dbg.declare dominates alloca. -define i32 @f2(i32 %i) nounwind ssp { -entry: - call void @llvm.dbg.declare(metadata !{i32* %i.addr}, metadata !20), !dbg !21 - %i.addr = alloca i32, align 4 - store i32 %i, i32* %i.addr, align 4 - %tmp = load i32* %i.addr, align 4, !dbg !22 - ret i32 %tmp, !dbg !22 -} - -; Check handling of an argument referred directly by llvm.dbg.declare where at least -; one argument use dominates llvm.dbg.declare. -define i32 @f3(i32 %i) nounwind ssp { -entry: - %i.addr = alloca i32, align 4 - store i32 %i, i32* %i.addr, align 4 - call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !24), !dbg !25 - %tmp = load i32* %i.addr, align 4, !dbg !26 - ret i32 %tmp, !dbg !26 -} - -; Check handling of an argument referred directly by llvm.dbg.declare where -; llvm.dbg.declare dominates all uses of argument. -define i32 @f4(i32 %i) nounwind ssp { -entry: - call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !28), !dbg !29 - ret i32 %i, !dbg !30 -} - -; Check handling of an argument referred directly by llvm.dbg.declare where -; llvm.dbg.declare dominates all uses of argument in separate basic block. -define i32 @f5(i32 %i) nounwind ssp { -entry: - call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !32), !dbg !33 - br label %bbr -bbr: - ret i32 %i, !dbg !34 -} - -; Check handling of an argument referred directly by llvm.dbg.declare where -; argument is not used. -define i32 @f6(i32 %i) nounwind ssp { -entry: - call void @llvm.dbg.declare(metadata !{i32 %i}, metadata !36), !dbg !37 - ret i32 1, !dbg !38 -} - -; Check handling of an byval argument referred directly by llvm.dbg.declare where -; argument is not used. -define i32 @f7(%struct.XYZ* byval %i) nounwind ssp { -entry: - call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !40), !dbg !48 - ret i32 1, !dbg !49 -} - -; Check handling of an byval argument referred directly by llvm.dbg.declare where -; argument use dominates llvm.dbg.declare. -define i32 @f8(%struct.XYZ* byval %i) nounwind ssp { -entry: - %tmp = getelementptr inbounds %struct.XYZ* %i, i32 0, i32 1, !dbg !53 - %tmp1 = load i32* %tmp, align 4, !dbg !53 - call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !51), !dbg !52 - ret i32 %tmp1, !dbg !53 -} - -; Check handling of an byval argument referred directly by llvm.dbg.declare where -; llvm.dbg.declare dominates all uses of argument. -define i32 @f9(%struct.XYZ* byval %i) nounwind ssp { -entry: - call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !55), !dbg !56 - %tmp = getelementptr inbounds %struct.XYZ* %i, i32 0, i32 2, !dbg !57 - %tmp1 = load i32* %tmp, align 4, !dbg !57 - ret i32 %tmp1, !dbg !57 -} - -; Check handling of an byval argument referred directly by llvm.dbg.declare where -; llvm.dbg.declare dominates all uses of argument in separate basic block. -define i32 @f10(%struct.XYZ* byval %i) nounwind ssp { -entry: - call void @llvm.dbg.declare(metadata !{%struct.XYZ* %i}, metadata !59), !dbg !60 - br label %bbr -bbr: - %tmp = getelementptr inbounds %struct.XYZ* %i, i32 0, i32 3, !dbg !61 - %tmp1 = load i32* %tmp, align 4, !dbg !61 - ret i32 %tmp1, !dbg !61 -} - -define i32 @main() nounwind ssp { -entry: - %retval = alloca i32, align 4 - %abc = alloca %struct.XYZ, align 4 - %agg.tmp = alloca %struct.XYZ, align 4 - %agg.tmp13 = alloca %struct.XYZ, align 4 - %agg.tmp17 = alloca %struct.XYZ, align 4 - %agg.tmp21 = alloca %struct.XYZ, align 4 - store i32 0, i32* %retval - %call = call i32 @f1(i32 42), !dbg !63 - %call1 = call i32 @f2(i32 43), !dbg !65 - %call2 = call i32 @f3(i32 44), !dbg !66 - %call3 = call i32 @f4(i32 45), !dbg !67 - %call4 = call i32 @f5(i32 46), !dbg !68 - %call5 = call i32 @f6(i32 47), !dbg !69 - call void @llvm.dbg.declare(metadata !{%struct.XYZ* %abc}, metadata !70), !dbg !71 - %tmp = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 0, !dbg !72 - store i32 51, i32* %tmp, align 4, !dbg !72 - %tmp6 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 1, !dbg !72 - store i32 52, i32* %tmp6, align 4, !dbg !72 - %tmp7 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 2, !dbg !72 - store i32 53, i32* %tmp7, align 4, !dbg !72 - %tmp8 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 3, !dbg !72 - store i32 54, i32* %tmp8, align 4, !dbg !72 - %tmp9 = getelementptr inbounds %struct.XYZ* %abc, i32 0, i32 4, !dbg !72 - store i32 55, i32* %tmp9, align 4, !dbg !72 - %tmp10 = bitcast %struct.XYZ* %agg.tmp to i8*, !dbg !73 - %tmp11 = bitcast %struct.XYZ* %abc to i8*, !dbg !73 - call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp10, i8* %tmp11, i64 20, i32 4, i1 false), !dbg !73 - %call12 = call i32 @f7(%struct.XYZ* byval %agg.tmp), !dbg !73 - %tmp14 = bitcast %struct.XYZ* %agg.tmp13 to i8*, !dbg !74 - %tmp15 = bitcast %struct.XYZ* %abc to i8*, !dbg !74 - call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp14, i8* %tmp15, i64 20, i32 4, i1 false), !dbg !74 - %call16 = call i32 @f8(%struct.XYZ* byval %agg.tmp13), !dbg !74 - %tmp18 = bitcast %struct.XYZ* %agg.tmp17 to i8*, !dbg !75 - %tmp19 = bitcast %struct.XYZ* %abc to i8*, !dbg !75 - call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp18, i8* %tmp19, i64 20, i32 4, i1 false), !dbg !75 - %call20 = call i32 @f9(%struct.XYZ* byval %agg.tmp17), !dbg !75 - %tmp22 = bitcast %struct.XYZ* %agg.tmp21 to i8*, !dbg !76 - %tmp23 = bitcast %struct.XYZ* %abc to i8*, !dbg !76 - call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp22, i8* %tmp23, i64 20, i32 4, i1 false), !dbg !76 - %call24 = call i32 @f10(%struct.XYZ* byval %agg.tmp21), !dbg !76 - ret i32 0, !dbg !77 -} - -declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind - -!llvm.dbg.sp = !{!0, !6, !7, !8, !9, !10, !11, !12, !13, !14, !15} - -!0 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f1", metadata !"f1", metadata !"f1", metadata !1, i32 11, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f1} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 524329, metadata !"arg.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 524305, i32 0, i32 12, metadata !"arg.c", metadata !"/private/tmp", metadata !"clang version 2.8 (trunk 112967)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!3 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] -!4 = metadata !{metadata !5} -!5 = metadata !{i32 524324, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f2", metadata !"f2", metadata !"f2", metadata !1, i32 12, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f2} ; [ DW_TAG_subprogram ] -!7 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f3", metadata !"f3", metadata !"f3", metadata !1, i32 13, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f3} ; [ DW_TAG_subprogram ] -!8 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f4", metadata !"f4", metadata !"f4", metadata !1, i32 14, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f4} ; [ DW_TAG_subprogram ] -!9 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f5", metadata !"f5", metadata !"f5", metadata !1, i32 15, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f5} ; [ DW_TAG_subprogram ] -!10 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f6", metadata !"f6", metadata !"f6", metadata !1, i32 16, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f6} ; [ DW_TAG_subprogram ] -!11 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f7", metadata !"f7", metadata !"f7", metadata !1, i32 17, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f7} ; [ DW_TAG_subprogram ] -!12 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f8", metadata !"f8", metadata !"f8", metadata !1, i32 18, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f8} ; [ DW_TAG_subprogram ] -!13 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f9", metadata !"f9", metadata !"f9", metadata !1, i32 19, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f9} ; [ DW_TAG_subprogram ] -!14 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f10", metadata !"f10", metadata !"f10", metadata !1, i32 20, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (%struct.XYZ*)* @f10} ; [ DW_TAG_subprogram ] -!15 = metadata !{i32 524334, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"main", metadata !1, i32 23, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @main} ; [ DW_TAG_subprogram ] -!16 = metadata !{i32 524545, metadata !0, metadata !"i", metadata !1, i32 11, metadata !5} ; [ DW_TAG_arg_variable ] -!17 = metadata !{i32 11, i32 12, metadata !0, null} -!18 = metadata !{i32 11, i32 17, metadata !19, null} -!19 = metadata !{i32 524299, metadata !0, i32 11, i32 15, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] -!20 = metadata !{i32 524545, metadata !6, metadata !"i", metadata !1, i32 12, metadata !5} ; [ DW_TAG_arg_variable ] -!21 = metadata !{i32 12, i32 12, metadata !6, null} -!22 = metadata !{i32 12, i32 17, metadata !23, null} -!23 = metadata !{i32 524299, metadata !6, i32 12, i32 15, metadata !1, i32 1} ; [ DW_TAG_lexical_block ] -!24 = metadata !{i32 524545, metadata !7, metadata !"i", metadata !1, i32 13, metadata !5} ; [ DW_TAG_arg_variable ] -!25 = metadata !{i32 13, i32 12, metadata !7, null} -!26 = metadata !{i32 13, i32 17, metadata !27, null} -!27 = metadata !{i32 524299, metadata !7, i32 13, i32 15, metadata !1, i32 2} ; [ DW_TAG_lexical_block ] -!28 = metadata !{i32 524545, metadata !8, metadata !"i", metadata !1, i32 14, metadata !5} ; [ DW_TAG_arg_variable ] -!29 = metadata !{i32 14, i32 12, metadata !8, null} -!30 = metadata !{i32 14, i32 17, metadata !31, null} -!31 = metadata !{i32 524299, metadata !8, i32 14, i32 15, metadata !1, i32 3} ; [ DW_TAG_lexical_block ] -!32 = metadata !{i32 524545, metadata !9, metadata !"i", metadata !1, i32 15, metadata !5} ; [ DW_TAG_arg_variable ] -!33 = metadata !{i32 15, i32 12, metadata !9, null} -!34 = metadata !{i32 15, i32 17, metadata !35, null} -!35 = metadata !{i32 524299, metadata !9, i32 15, i32 15, metadata !1, i32 4} ; [ DW_TAG_lexical_block ] -!36 = metadata !{i32 524545, metadata !10, metadata !"i", metadata !1, i32 16, metadata !5} ; [ DW_TAG_arg_variable ] -!37 = metadata !{i32 16, i32 12, metadata !10, null} -!38 = metadata !{i32 16, i32 17, metadata !39, null} -!39 = metadata !{i32 524299, metadata !10, i32 16, i32 15, metadata !1, i32 5} ; [ DW_TAG_lexical_block ] -!40 = metadata !{i32 524545, metadata !11, metadata !"i", metadata !1, i32 17, metadata !41} ; [ DW_TAG_arg_variable ] -!41 = metadata !{i32 524307, metadata !1, metadata !"XYZ", metadata !1, i32 2, i64 160, i64 32, i64 0, i32 0, null, metadata !42, i32 0, null} ; [ DW_TAG_structure_type ] -!42 = metadata !{metadata !43, metadata !44, metadata !45, metadata !46, metadata !47} -!43 = metadata !{i32 524301, metadata !1, metadata !"x", metadata !1, i32 3, i64 32, i64 32, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] -!44 = metadata !{i32 524301, metadata !1, metadata !"y", metadata !1, i32 4, i64 32, i64 32, i64 32, i32 0, metadata !5} ; [ DW_TAG_member ] -!45 = metadata !{i32 524301, metadata !1, metadata !"z", metadata !1, i32 5, i64 32, i64 32, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] -!46 = metadata !{i32 524301, metadata !1, metadata !"a", metadata !1, i32 6, i64 32, i64 32, i64 96, i32 0, metadata !5} ; [ DW_TAG_member ] -!47 = metadata !{i32 524301, metadata !1, metadata !"b", metadata !1, i32 7, i64 32, i64 32, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] -!48 = metadata !{i32 17, i32 19, metadata !11, null} -!49 = metadata !{i32 17, i32 24, metadata !50, null} -!50 = metadata !{i32 524299, metadata !11, i32 17, i32 22, metadata !1, i32 6} ; [ DW_TAG_lexical_block ] -!51 = metadata !{i32 524545, metadata !12, metadata !"i", metadata !1, i32 18, metadata !41} ; [ DW_TAG_arg_variable ] -!52 = metadata !{i32 18, i32 19, metadata !12, null} -!53 = metadata !{i32 18, i32 24, metadata !54, null} -!54 = metadata !{i32 524299, metadata !12, i32 18, i32 22, metadata !1, i32 7} ; [ DW_TAG_lexical_block ] -!55 = metadata !{i32 524545, metadata !13, metadata !"i", metadata !1, i32 19, metadata !41} ; [ DW_TAG_arg_variable ] -!56 = metadata !{i32 19, i32 19, metadata !13, null} -!57 = metadata !{i32 19, i32 24, metadata !58, null} -!58 = metadata !{i32 524299, metadata !13, i32 19, i32 22, metadata !1, i32 8} ; [ DW_TAG_lexical_block ] -!59 = metadata !{i32 524545, metadata !14, metadata !"i", metadata !1, i32 20, metadata !41} ; [ DW_TAG_arg_variable ] -!60 = metadata !{i32 20, i32 20, metadata !14, null} -!61 = metadata !{i32 20, i32 25, metadata !62, null} -!62 = metadata !{i32 524299, metadata !14, i32 20, i32 23, metadata !1, i32 9} ; [ DW_TAG_lexical_block ] -!63 = metadata !{i32 24, i32 3, metadata !64, null} -!64 = metadata !{i32 524299, metadata !15, i32 23, i32 12, metadata !1, i32 10} ; [ DW_TAG_lexical_block ] -!65 = metadata !{i32 25, i32 3, metadata !64, null} -!66 = metadata !{i32 26, i32 3, metadata !64, null} -!67 = metadata !{i32 27, i32 3, metadata !64, null} -!68 = metadata !{i32 28, i32 3, metadata !64, null} -!69 = metadata !{i32 29, i32 3, metadata !64, null} -!70 = metadata !{i32 524544, metadata !64, metadata !"abc", metadata !1, i32 30, metadata !41} ; [ DW_TAG_auto_variable ] -!71 = metadata !{i32 30, i32 14, metadata !64, null} -!72 = metadata !{i32 30, i32 17, metadata !64, null} -!73 = metadata !{i32 31, i32 3, metadata !64, null} -!74 = metadata !{i32 32, i32 3, metadata !64, null} -!75 = metadata !{i32 33, i32 3, metadata !64, null} -!76 = metadata !{i32 34, i32 3, metadata !64, null} -!77 = metadata !{i32 36, i32 3, metadata !64, null} From clattner at apple.com Tue Sep 7 17:17:13 2010 From: clattner at apple.com (Chris Lattner) Date: Tue, 7 Sep 2010 15:17:13 -0700 Subject: [llvm-commits] [llvm] r113237 - in /llvm/trunk/test/CodeGen/X86: dbg-declare-fastisel.ll dbg-declare-hybrid.ll dbg-declare-isel.ll In-Reply-To: References: <20100907181756.C78E12A6C12C@llvm.org> <1F2CFAE9-CF30-490A-AF78-67B696F6C6C5@apple.com> <7AD3A7F5-730A-4AE3-A4C7-27C229941EC5@apple.com> Message-ID: On Sep 7, 2010, at 3:04 PM, Devang Patel wrote: >>>> lib/CodeGen/X86 needs to run on any host. You are forcing the programs to build with the X86 code generator, then run. THis won't work unless the host is x86. >>> >>> Is there any way to skip the test in this case ? What else do you suggest ? >> >> There is some XHOST thing I think, but it's better to have a dedicated place for this. It's not like these are the only debug info tests we should have. Why not put them in the gdb testsuite or something that already has a harness? > > Dependence on anything that is not required to be tested before a check-in is not scaling well. Unfortunately, code gen changes not related to debug info work accidentally breaks debug info which may go unnoticed for a while. In an ideal world, we'd get generic infrastructure for doing debug info tests that works similar to the gdb testsuite but is more robust. In a less ideal world, this should just go in the existing gdb buildbot. -Chris From grosbach at apple.com Tue Sep 7 17:30:53 2010 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 07 Sep 2010 22:30:53 -0000 Subject: [llvm-commits] [llvm] r113297 - /llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp Message-ID: <20100907223053.73BD82A6C12C@llvm.org> Author: grosbach Date: Tue Sep 7 17:30:53 2010 New Revision: 113297 URL: http://llvm.org/viewvc/llvm-project?rev=113297&view=rev Log: To shrink a t2LDM instruction to the 16-bit wide tLDM instruction, the base register must be one of the destination registers for the load. Otherwise, the tLDM instruction will write-back to the base register, which isn't what's desired (otherwise, we'd have a t2LDM_UPD instead). rdar://8394087 Modified: llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp Modified: llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp?rev=113297&r1=113296&r2=113297&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp (original) +++ llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp Tue Sep 7 17:30:53 2010 @@ -315,6 +315,18 @@ ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(1).getImm()); if (!isARMLowRegister(BaseReg) || Mode != ARM_AM::ia) return false; + // For the non-writeback version (this one), the base register must be + // one of the registers being loaded. + bool isOK = false; + for (unsigned i = 4; i < MI->getNumOperands(); ++i) { + if (MI->getOperand(i).getReg() == BaseReg) { + isOK = true; + break; + } + } + if (!isOK) + return false; + OpNum = 0; isLdStMul = true; break; From stoklund at 2pi.dk Tue Sep 7 17:38:45 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 07 Sep 2010 22:38:45 -0000 Subject: [llvm-commits] [llvm] r113299 - /llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp Message-ID: <20100907223845.57D882A6C12C@llvm.org> Author: stoklund Date: Tue Sep 7 17:38:45 2010 New Revision: 113299 URL: http://llvm.org/viewvc/llvm-project?rev=113299&view=rev Log: Don't add operands during register rewriting. LiveIntervals already adds operands for super-registers when a subreg def defines the whole register. Thus, it is not necessary to do it again when rewriting. In fact, the super-register imp-defs caused miscompilations because the late scheduler couldn't see that the super-register was read. We still add super-reg operands when rewriting virtuals to physicals. Modified: llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp Modified: llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp?rev=113299&r1=113298&r2=113299&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp (original) +++ llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp Tue Sep 7 17:38:45 2010 @@ -67,23 +67,16 @@ /// Note that operands may be added, so the MO reference is no longer valid. static void substitutePhysReg(MachineOperand &MO, unsigned Reg, const TargetRegisterInfo &TRI) { - if (unsigned SubIdx = MO.getSubReg()) { - // Insert the physical subreg and reset the subreg field. - MO.setReg(TRI.getSubReg(Reg, SubIdx)); - MO.setSubReg(0); - - // Any def, dead, and kill flags apply to the full virtual register, so they - // also apply to the full physical register. Add imp-def/dead and imp-kill - // as needed. + if (MO.getSubReg()) { + MO.substPhysReg(Reg, TRI); + + // Any kill flags apply to the full virtual register, so they also apply to + // the full physical register. + // We assume that partial defs have already been decorated with a super-reg + // operand by LiveIntervals. MachineInstr &MI = *MO.getParent(); - if (MO.isDef()) - if (MO.isDead()) - MI.addRegisterDead(Reg, &TRI, /*AddIfNotFound=*/ true); - else - MI.addRegisterDefined(Reg, &TRI); - else if (!MO.isUndef() && - (MO.isKill() || - MI.isRegTiedToDefOperand(&MO-&MI.getOperand(0)))) + if (MO.isUse() && !MO.isUndef() && + (MO.isKill() || MI.isRegTiedToDefOperand(&MO-&MI.getOperand(0)))) MI.addRegisterKilled(Reg, &TRI, /*AddIfNotFound=*/ true); } else { MO.setReg(Reg); From rjmccall at apple.com Tue Sep 7 18:10:21 2010 From: rjmccall at apple.com (John McCall) Date: Tue, 07 Sep 2010 23:10:21 -0000 Subject: [llvm-commits] [llvm] r113303 - in /llvm/trunk/docs/CommandGuide: index.html llvm-diff.pod Message-ID: <20100907231021.A3B9E2A6C12C@llvm.org> Author: rjmccall Date: Tue Sep 7 18:10:21 2010 New Revision: 113303 URL: http://llvm.org/viewvc/llvm-project?rev=113303&view=rev Log: Add documentation for llvm-diff. Added: llvm/trunk/docs/CommandGuide/llvm-diff.pod Modified: llvm/trunk/docs/CommandGuide/index.html Modified: llvm/trunk/docs/CommandGuide/index.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CommandGuide/index.html?rev=113303&r1=113302&r2=113303&view=diff ============================================================================== --- llvm/trunk/docs/CommandGuide/index.html (original) +++ llvm/trunk/docs/CommandGuide/index.html Tue Sep 7 18:10:21 2010 @@ -72,6 +72,9 @@
  • llvmc - a generic customizable compiler driver
  • +
  • llvm-diff - + structurally compare two modules
  • + Added: llvm/trunk/docs/CommandGuide/llvm-diff.pod URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CommandGuide/llvm-diff.pod?rev=113303&view=auto ============================================================================== --- llvm/trunk/docs/CommandGuide/llvm-diff.pod (added) +++ llvm/trunk/docs/CommandGuide/llvm-diff.pod Tue Sep 7 18:10:21 2010 @@ -0,0 +1,53 @@ +=pod + +=head1 NAME + +llvm-diff - LLVM structural 'diff' + +=head1 SYNOPSIS + +B [I] I I [I] + +=head1 DESCRIPTION + +B compares the structure of two LLVM modules, primarily +focusing on differences in function definitions. Insignificant +differences, such as changes in the ordering of globals or in the +names of local values, are ignored. + +An input module will be interpreted as an assembly file if its name +ends in '.ll'; otherwise it will be read in as a bitcode file. + +If a list of global names is given, just the values with those names +are compared; otherwise, all global values are compared, and +diagnostics are produced for globals which only appear in one module +or the other. + +B compares two functions by comparing their basic blocks, +beginning with the entry blocks. If the terminators seem to match, +then the corresponding successors are compared; otherwise they are +ignored. This algorithm is very sensitive to changes in control flow, +which tend to stop any downstream changes from being detected. + +B is intended as a debugging tool for writers of LLVM +passes and frontends. It does not have a stable output format. + +=head1 EXIT STATUS + +If B finds no differences between the modules, it will exit +with 0 and produce no output. Otherwise it will exit with a non-zero +value. + +=head1 BUGS + +Many important differences, like changes in linkage or function +attributes, are not diagnosed. + +Changes in memory behavior (for example, coalescing loads) can cause +massive detected differences in blocks. + +=head1 AUTHORS + +Maintained by the LLVM Team (L). + +=cut From resistor at mac.com Tue Sep 7 18:15:30 2010 From: resistor at mac.com (Owen Anderson) Date: Tue, 07 Sep 2010 23:15:30 -0000 Subject: [llvm-commits] [llvm] r113306 - /llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp Message-ID: <20100907231530.DF7422A6C12C@llvm.org> Author: resistor Date: Tue Sep 7 18:15:30 2010 New Revision: 113306 URL: http://llvm.org/viewvc/llvm-project?rev=113306&view=rev Log: Add a separate unrolling threshold when the current function is being optimized for size. The threshold value of 50 is arbitrary, and I chose it simply by analogy to the inlining thresholds, where the baseline unrolling threshold is slightly smaller than the baseline inlining threshold. This could undoubtedly use some tuning. Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp?rev=113306&r1=113305&r2=113306&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp Tue Sep 7 18:15:30 2010 @@ -49,6 +49,12 @@ /// that the loop unroll should be performed regardless of how much /// code expansion would result. static const unsigned NoThreshold = UINT_MAX; + + // Threshold to use when optsize is specified (and there is no + // explicit -unroll-threshold). + static const unsigned OptSizeUnrollThreshold = 50; + + unsigned CurrentThreshold; bool runOnLoop(Loop *L, LPPassManager &LPM); @@ -88,12 +94,22 @@ } bool LoopUnroll::runOnLoop(Loop *L, LPPassManager &LPM) { + LoopInfo *LI = &getAnalysis(); BasicBlock *Header = L->getHeader(); DEBUG(dbgs() << "Loop Unroll: F[" << Header->getParent()->getName() << "] Loop %" << Header->getName() << "\n"); (void)Header; + + // Determine the current unrolling threshold. While this is normally set + // from UnrollThreshold, it is overridden to a smaller value if the current + // function is marked as optimize-for-size, and the unroll threshold was + // not user specified. + CurrentThreshold = UnrollThreshold; + if (Header->getParent()->hasFnAttr(Attribute::OptimizeForSize) && + UnrollThreshold.getNumOccurrences() == 0) + CurrentThreshold = OptSizeUnrollThreshold; // Find trip count unsigned TripCount = L->getSmallConstantTripCount(); @@ -111,7 +127,7 @@ } // Enforce the threshold. - if (UnrollThreshold != NoThreshold) { + if (CurrentThreshold != NoThreshold) { unsigned NumCalls; unsigned LoopSize = ApproximateLoopSize(L, NumCalls); DEBUG(dbgs() << " Loop Size = " << LoopSize << "\n"); @@ -120,16 +136,16 @@ return false; } uint64_t Size = (uint64_t)LoopSize*Count; - if (TripCount != 1 && Size > UnrollThreshold) { + if (TripCount != 1 && Size > CurrentThreshold) { DEBUG(dbgs() << " Too large to fully unroll with count: " << Count - << " because size: " << Size << ">" << UnrollThreshold << "\n"); + << " because size: " << Size << ">" << CurrentThreshold << "\n"); if (!UnrollAllowPartial) { DEBUG(dbgs() << " will not try to unroll partially because " << "-unroll-allow-partial not given\n"); return false; } // Reduce unroll count to be modulo of TripCount for partial unrolling - Count = UnrollThreshold / LoopSize; + Count = CurrentThreshold / LoopSize; while (Count != 0 && TripCount%Count != 0) { Count--; } From stoklund at 2pi.dk Tue Sep 7 18:28:26 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 07 Sep 2010 23:28:26 -0000 Subject: [llvm-commits] [test-suite] r113308 - in /test-suite/trunk/External/SPEC/CINT2000: 164.gzip/164.gzip.reference_output.small 164.gzip/Makefile 256.bzip2/256.bzip2.reference_output.small 256.bzip2/Makefile Message-ID: <20100907232826.A71192A6C12C@llvm.org> Author: stoklund Date: Tue Sep 7 18:28:26 2010 New Revision: 113308 URL: http://llvm.org/viewvc/llvm-project?rev=113308&view=rev Log: The RUN_TYPE make variable is not available until after including Makefile.spec2000. Modified: test-suite/trunk/External/SPEC/CINT2000/164.gzip/164.gzip.reference_output.small test-suite/trunk/External/SPEC/CINT2000/164.gzip/Makefile test-suite/trunk/External/SPEC/CINT2000/256.bzip2/256.bzip2.reference_output.small test-suite/trunk/External/SPEC/CINT2000/256.bzip2/Makefile Modified: test-suite/trunk/External/SPEC/CINT2000/164.gzip/164.gzip.reference_output.small URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/External/SPEC/CINT2000/164.gzip/164.gzip.reference_output.small?rev=113308&r1=113307&r2=113308&view=diff ============================================================================== --- test-suite/trunk/External/SPEC/CINT2000/164.gzip/164.gzip.reference_output.small (original) +++ test-suite/trunk/External/SPEC/CINT2000/164.gzip/164.gzip.reference_output.small Tue Sep 7 18:28:26 2010 @@ -0,0 +1,32 @@ +spec_init +Loading Input Data +Duplicating 1038922 bytes +Duplicating 19308 bytes +Input data 2097152 bytes in length +Compressing Input Data, level 1 +Compressed data 2078079 bytes in length +Uncompressing Data +Uncompressed data 2097152 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 3 +Compressed data 2077889 bytes in length +Uncompressing Data +Uncompressed data 2097152 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 5 +Compressed data 2076940 bytes in length +Uncompressing Data +Uncompressed data 2097152 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 7 +Compressed data 2076922 bytes in length +Uncompressing Data +Uncompressed data 2097152 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 2076922 bytes in length +Uncompressing Data +Uncompressed data 2097152 bytes in length +Uncompressed data compared correctly +Tested 2MB buffer: OK! +exit 0 Modified: test-suite/trunk/External/SPEC/CINT2000/164.gzip/Makefile URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/External/SPEC/CINT2000/164.gzip/Makefile?rev=113308&r1=113307&r2=113308&view=diff ============================================================================== --- test-suite/trunk/External/SPEC/CINT2000/164.gzip/Makefile (original) +++ test-suite/trunk/External/SPEC/CINT2000/164.gzip/Makefile Tue Sep 7 18:28:26 2010 @@ -1,8 +1,8 @@ LEVEL = ../../../.. RUN_OPTIONS = `cat $(REF_IN_DIR)control` +include ../../Makefile.spec2000 ifeq ($(RUN_TYPE),test) STDOUT_FILENAME := input.compressed.out else STDOUT_FILENAME := input.combined.out endif -include ../../Makefile.spec2000 Modified: test-suite/trunk/External/SPEC/CINT2000/256.bzip2/256.bzip2.reference_output.small URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/External/SPEC/CINT2000/256.bzip2/256.bzip2.reference_output.small?rev=113308&r1=113307&r2=113308&view=diff ============================================================================== --- test-suite/trunk/External/SPEC/CINT2000/256.bzip2/256.bzip2.reference_output.small (original) +++ test-suite/trunk/External/SPEC/CINT2000/256.bzip2/256.bzip2.reference_output.small Tue Sep 7 18:28:26 2010 @@ -0,0 +1,15 @@ +spec_init +Loading Input Data +Input data 2097152 bytes in length +Compressing Input Data, level 7 +Compressed data 2107853 bytes in length +Uncompressing Data +Uncompressed data 2097152 bytes in length +Uncompressed data compared correctly +Compressing Input Data, level 9 +Compressed data 2106855 bytes in length +Uncompressing Data +Uncompressed data 2097152 bytes in length +Uncompressed data compared correctly +Tested 2MB buffer: OK! +exit 0 Modified: test-suite/trunk/External/SPEC/CINT2000/256.bzip2/Makefile URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/External/SPEC/CINT2000/256.bzip2/Makefile?rev=113308&r1=113307&r2=113308&view=diff ============================================================================== --- test-suite/trunk/External/SPEC/CINT2000/256.bzip2/Makefile (original) +++ test-suite/trunk/External/SPEC/CINT2000/256.bzip2/Makefile Tue Sep 7 18:28:26 2010 @@ -1,10 +1,8 @@ LEVEL = ../../../.. - RUN_OPTIONS = `cat $(REF_IN_DIR)control` +include ../../Makefile.spec2000 ifeq ($(RUN_TYPE),test) STDOUT_FILENAME := input.random.out else STDOUT_FILENAME := input.compressed.out endif - -include ../../Makefile.spec2000 From echristo at apple.com Tue Sep 7 18:48:20 2010 From: echristo at apple.com (Eric Christopher) Date: Tue, 7 Sep 2010 16:48:20 -0700 Subject: [llvm-commits] [PATCH] GNU ld win32 should not accept version script In-Reply-To: <98FC6E4A-5219-45BE-8787-C72372B505D7@apple.com> References: <98FC6E4A-5219-45BE-8787-C72372B505D7@apple.com> Message-ID: <5F7E8A9D-43D6-41FF-8B88-47FDD5003659@apple.com> On Sep 7, 2010, at 11:22 AM, Eric Christopher wrote: > > On Sep 6, 2010, at 7:03 AM, NAKAMURA Takumi wrote: > >> > > So this part I somewhat understand: > > +if test "$dynamic_linker" != "Win32 ld.exe" ; then > + dnl Determine whether the linker supports the --version-script option. > + AC_LINK_VERSION_SCRIPT > +fi > > Though it'd probably be better to do a test similar to AC_PROG_GNU_LD to instead check for WIN32_LD. > > That said, what's with the moving of AC_LIBTOOL_DLOPEN AND AC_LIB_LTDL? OK, I'm still curious about this part. However for the rest it looks like a bit of a redesign of AC_LINK_VERSION_SCRIPT is really necessary, though the hack of moving the win32 bits above the gnu ld bits should work. What you want to really know is if and how to use a version file to successfully export symbols. The best bet there is to rewrite AC_LINK_VERSION_SCRIPT to do that sort of thing. Basically you'll probably want a pile of macros and some host checking to figure out what you should do, e.g.: case {$target} in *-*-darwin*) AC_DEFINE(DARWIN_EXPORT_TYPE, 1, [Define this if we should use darwin export types]) ;; *-*-windows* | *-*-mingw* | *-*-cygwin*) AC_DEFINE(WINDOWS_EXPORT_TYPE, 1, [Define this if we should use windows .def style export types]) .... etc. You'll need to include some of the existing checking for --version-script as well. -eric From stoklund at 2pi.dk Tue Sep 7 19:11:22 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 08 Sep 2010 00:11:22 -0000 Subject: [llvm-commits] [test-suite] r113318 - in /test-suite/trunk/External/SPEC/CINT95/099.go: 099.go.reference_output.small Makefile Message-ID: <20100908001122.843A92A6C12C@llvm.org> Author: stoklund Date: Tue Sep 7 19:11:22 2010 New Revision: 113318 URL: http://llvm.org/viewvc/llvm-project?rev=113318&view=rev Log: Fix 099.go for SMALL_PROBLEM_SIZE. This was another case of RUN_TYPE being used uninitialized. Modified: test-suite/trunk/External/SPEC/CINT95/099.go/099.go.reference_output.small test-suite/trunk/External/SPEC/CINT95/099.go/Makefile Modified: test-suite/trunk/External/SPEC/CINT95/099.go/099.go.reference_output.small URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/External/SPEC/CINT95/099.go/099.go.reference_output.small?rev=113318&r1=113317&r2=113318&view=diff ============================================================================== --- test-suite/trunk/External/SPEC/CINT95/099.go/099.go.reference_output.small (original) +++ test-suite/trunk/External/SPEC/CINT95/099.go/099.go.reference_output.small Tue Sep 7 19:11:22 2010 @@ -0,0 +1,298 @@ + 1 B D17 + 2 W C4 + 3 B R16 + 4 W Q4 + 5 B C15 + 6 W P16 + 7 B E4 + 8 W R15 + 9 B S15 + 10 W Q15 + 11 B R14 + 12 W S16 + 13 B S17 + 14 W S14 + 15 B T16 + 16 W R13 + 17 B Q17 + 18 W D6 + 19 B C3 + 20 W B3 + 21 B D3 + 22 W Q14 + 23 B B2 + 24 W B4 + 25 B O3 + 26 W Q6 + 27 B R8 + 28 W R10 + 29 B N17 + 30 W Q3 + 31 B L3 + 32 W H3 + 33 B G3 + 34 W H4 + 35 B H2 + 36 W J2 + 37 B G2 + 38 W A2 + 39 B C2 + 40 W P17 + 41 B K17 + 42 W Q18 + 43 B R18 + 44 W O18 + 45 B R9 + 46 W Q10 + 47 B S6 + 48 W Q8 + 49 B S10 + 50 W Q9 + 51 B S11 + 52 W S4 + 53 B K4 + 54 W K3 + 55 B K2 + 56 W R7 + 57 B L4 + 58 W P2 + 59 B J3 + 60 W J4 + 61 B J5 + 62 W H5 + 63 B H6 + 64 W K5 + 65 B G5 + 66 W J6 + 67 B G4 + 68 W H7 + 69 B J5 + 70 W M18 + 71 B N15 + 72 W G7 + 73 B L15 + 74 W E6 + 75 B C10 + 76 W C8 + 77 B C13 + 78 W K7 + 79 B K14 + 80 W L17 + 81 B K18 + 82 W M14 + 83 B M15 + 84 W N14 + 85 B G17 + 86 W S7 + 87 B B9 + 88 W B8 + 89 B A4 + 90 W A9 + 91 B E10 + 92 W C17 + 93 B E8 + 94 W D18 + 95 B D16 + 96 W E18 + 97 B F17 + 98 W B10 + 99 B B11 +100 W C9 +101 B D11 +102 W B16 +103 B B15 +104 W A11 +105 B A16 +106 W D9 +107 B B12 +108 W B18 +109 B L5 +110 W A17 +111 B K12 +112 W A15 +113 B F18 +114 W F19 +115 B M12 +116 W L13 +117 B B14 +118 W E17 +119 B E16 +120 W A13 +121 B B13 +122 W F8 +123 B E9 +124 W F7 +125 B E7 +126 W G6 +127 B D7 +128 W C7 +129 B F5 +130 W F10 +131 B F11 +132 W E12 +133 B G10 +134 W F12 +135 B L12 +136 W F15 +137 B K13 +138 W H15 +139 B J11 +140 W F9 +141 B E11 +142 W H5 +143 B G13 +144 W O15 +145 B H4 +146 W J4 +147 B J8 +148 W F6 +149 B O12 +150 W R19 +151 B S19 +152 W L14 +153 B P13 +154 W P14 +155 B N18 +156 W N19 +157 B M17 +158 W L18 +159 B P19 +160 W P18 +161 B K16 +162 W O10 +163 B O13 +164 W O14 +165 B E14 +166 W M10 +167 B D4 +168 W C5 +169 B O2 +170 W M6 +171 B L6 +172 W L7 +173 B M7 +174 W L9 +175 B M8 +176 W N6 +177 B O16 +178 W Q16 +179 B Q19 +180 W O8 +181 B K8 +182 W L8 +183 B Q13 +184 W R17 +185 B R12 +186 W S16 +187 B M19 +188 W O19 +189 B R16 +190 W S12 +191 B T12 +192 W S16 +193 B T18 +194 W T15 +195 B S8 +196 W S13 +197 B R11 +198 W Q11 +199 B Q12 +200 W N13 +201 B N12 +202 W G9 +203 B H10 +204 W N4 +205 B M3 +206 W D10 +207 B G19 +208 W K9 +209 B T7 +210 W H9 +211 B G12 +212 W J5 +213 B R5 +214 W Q5 +215 B R4 +216 W R3 +217 B S5 +218 W T9 +219 B R6 +220 W T5 +221 B Q7 +222 W P7 +223 B S3 +224 W S2 +225 B T4 +226 W N9 +227 B J9 +228 W N3 +229 B N2 +230 W O4 +231 B L16 +232 W L19 +233 B K19 +234 W M19 +235 B K10 +236 W T17 +237 B P11 +238 W S18 +239 B T2 +240 W S1 +241 B S17 +242 W T16 +243 B T3 +244 W T1 +245 B S4 +246 W R2 +247 B C11 +248 W R7 +249 B S7 +250 W E19 +251 B M5 +252 W Q7 +253 B P1 +254 W Q1 +255 B N5 +256 W O5 +257 B O1 +258 W P3 +259 B M2 +260 W T13 +261 B T11 +262 W P10 +263 B M11 +264 W O11 +265 B P12 +266 W O17 +267 B N16 +268 W L10 +269 B N11 +270 W L11 +271 B H8 +272 W K11 +273 B J10 +274 W D5 +275 B C16 +276 W M13 +277 B N10 +278 W D8 +279 B J7 +280 W K6 +281 B G8 +282 W E5 +283 B M4 +284 W pass +285 B B1 +286 W pass +287 B A1 +288 W A3 +289 B H19 +290 W pass +291 B A14 +292 W A16 +293 B A12 +294 W A10 +295 B pass +296 W pass +Game over +exit 0 Modified: test-suite/trunk/External/SPEC/CINT95/099.go/Makefile URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/External/SPEC/CINT95/099.go/Makefile?rev=113318&r1=113317&r2=113318&view=diff ============================================================================== --- test-suite/trunk/External/SPEC/CINT95/099.go/Makefile (original) +++ test-suite/trunk/External/SPEC/CINT95/099.go/Makefile Tue Sep 7 19:11:22 2010 @@ -1,8 +1,10 @@ LEVEL = ../../../.. BM=099.go +include ../../Makefile.spec95 + ifeq ($(RUN_TYPE),test) -STDIN_FILENAME = /dev/null +STDIN_FILENAME = null.in STDOUT_FILENAME = null.out RUN_OPTIONS = 40 19 else @@ -10,7 +12,6 @@ STDOUT_FILENAME = 2stone9.out RUN_OPTIONS = 50 9 endif -include ../../Makefile.spec95 ifeq ($(ARCH),Alpha) From stoklund at 2pi.dk Tue Sep 7 19:20:50 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 08 Sep 2010 00:20:50 -0000 Subject: [llvm-commits] [test-suite] r113320 - in /test-suite/trunk/External/SPEC/CINT95/132.ijpeg: 132.ijpeg.reference_output.small Makefile Message-ID: <20100908002050.213AF2A6C12C@llvm.org> Author: stoklund Date: Tue Sep 7 19:20:49 2010 New Revision: 113320 URL: http://llvm.org/viewvc/llvm-project?rev=113320&view=rev Log: Fix 132.ijpeg for SMALL_PROBLEM_SIZE=1 Modified: test-suite/trunk/External/SPEC/CINT95/132.ijpeg/132.ijpeg.reference_output.small test-suite/trunk/External/SPEC/CINT95/132.ijpeg/Makefile Modified: test-suite/trunk/External/SPEC/CINT95/132.ijpeg/132.ijpeg.reference_output.small URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/External/SPEC/CINT95/132.ijpeg/132.ijpeg.reference_output.small?rev=113320&r1=113319&r2=113320&view=diff ============================================================================== --- test-suite/trunk/External/SPEC/CINT95/132.ijpeg/132.ijpeg.reference_output.small (original) +++ test-suite/trunk/External/SPEC/CINT95/132.ijpeg/132.ijpeg.reference_output.small Tue Sep 7 19:20:49 2010 @@ -0,0 +1,2433 @@ + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 4270 +compression parameters: + quality : 90 + optimize_coding : 0 + smoothing_factor: 90 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3264 +L2 norm = 63908 +checksum: 145 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 3870 +compression parameters: + quality : 90 + optimize_coding : 1 + smoothing_factor: 90 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3264 +L2 norm = 63908 +checksum: 145 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 4488 +compression parameters: + quality : 90 + optimize_coding : 0 + smoothing_factor: 80 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3114 +L2 norm = 56426 +checksum: 255 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 4091 +compression parameters: + quality : 90 + optimize_coding : 1 + smoothing_factor: 80 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3114 +L2 norm = 56426 +checksum: 255 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 4776 +compression parameters: + quality : 90 + optimize_coding : 0 + smoothing_factor: 70 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 2972 +L2 norm = 49220 +checksum: 81 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 4373 +compression parameters: + quality : 90 + optimize_coding : 1 + smoothing_factor: 70 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 2972 +L2 norm = 49220 +checksum: 81 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 5029 +compression parameters: + quality : 90 + optimize_coding : 0 + smoothing_factor: 60 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 2620 +L2 norm = 38708 +checksum: 215 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 4630 +compression parameters: + quality : 90 + optimize_coding : 1 + smoothing_factor: 60 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 2620 +L2 norm = 38708 +checksum: 215 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 5274 +compression parameters: + quality : 90 + optimize_coding : 0 + smoothing_factor: 50 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 2481 +L2 norm = 33107 +checksum: 128 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 4877 +compression parameters: + quality : 90 + optimize_coding : 1 + smoothing_factor: 50 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 2481 +L2 norm = 33107 +checksum: 128 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 5477 +compression parameters: + quality : 90 + optimize_coding : 0 + smoothing_factor: 40 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 2242 +L2 norm = 26984 +checksum: 49 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 5094 +compression parameters: + quality : 90 + optimize_coding : 1 + smoothing_factor: 40 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 2242 +L2 norm = 26984 +checksum: 49 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 5671 +compression parameters: + quality : 90 + optimize_coding : 0 + smoothing_factor: 30 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 2028 +L2 norm = 21154 +checksum: 113 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 5291 +compression parameters: + quality : 90 + optimize_coding : 1 + smoothing_factor: 30 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 2028 +L2 norm = 21154 +checksum: 113 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 5868 +compression parameters: + quality : 90 + optimize_coding : 0 + smoothing_factor: 20 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 2047 +L2 norm = 20829 +checksum: 212 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 5491 +compression parameters: + quality : 90 + optimize_coding : 1 + smoothing_factor: 20 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 2047 +L2 norm = 20829 +checksum: 212 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 3191 +compression parameters: + quality : 80 + optimize_coding : 0 + smoothing_factor: 90 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3359 +L2 norm = 68665 +checksum: 188 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2861 +compression parameters: + quality : 80 + optimize_coding : 1 + smoothing_factor: 90 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3359 +L2 norm = 68665 +checksum: 188 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 3292 +compression parameters: + quality : 80 + optimize_coding : 0 + smoothing_factor: 80 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3301 +L2 norm = 65939 +checksum: 235 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2960 +compression parameters: + quality : 80 + optimize_coding : 1 + smoothing_factor: 80 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3301 +L2 norm = 65939 +checksum: 235 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 3426 +compression parameters: + quality : 80 + optimize_coding : 0 + smoothing_factor: 70 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3296 +L2 norm = 62152 +checksum: 233 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 3100 +compression parameters: + quality : 80 + optimize_coding : 1 + smoothing_factor: 70 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3296 +L2 norm = 62152 +checksum: 233 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 3552 +compression parameters: + quality : 80 + optimize_coding : 0 + smoothing_factor: 60 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3039 +L2 norm = 53591 +checksum: 182 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 3230 +compression parameters: + quality : 80 + optimize_coding : 1 + smoothing_factor: 60 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3039 +L2 norm = 53591 +checksum: 182 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 3712 +compression parameters: + quality : 80 + optimize_coding : 0 + smoothing_factor: 50 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3016 +L2 norm = 48588 +checksum: 227 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 3380 +compression parameters: + quality : 80 + optimize_coding : 1 + smoothing_factor: 50 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3016 +L2 norm = 48588 +checksum: 227 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 3871 +compression parameters: + quality : 80 + optimize_coding : 0 + smoothing_factor: 40 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 2768 +L2 norm = 40380 +checksum: 53 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 3536 +compression parameters: + quality : 80 + optimize_coding : 1 + smoothing_factor: 40 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 2768 +L2 norm = 40380 +checksum: 53 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 4014 +compression parameters: + quality : 80 + optimize_coding : 0 + smoothing_factor: 30 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 2659 +L2 norm = 39379 +checksum: 92 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 3681 +compression parameters: + quality : 80 + optimize_coding : 1 + smoothing_factor: 30 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 2659 +L2 norm = 39379 +checksum: 92 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 4170 +compression parameters: + quality : 80 + optimize_coding : 0 + smoothing_factor: 20 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 2560 +L2 norm = 35430 +checksum: 131 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 3831 +compression parameters: + quality : 80 + optimize_coding : 1 + smoothing_factor: 20 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 2560 +L2 norm = 35430 +checksum: 131 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2695 +compression parameters: + quality : 70 + optimize_coding : 0 + smoothing_factor: 90 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3549 +L2 norm = 75015 +checksum: 223 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2368 +compression parameters: + quality : 70 + optimize_coding : 1 + smoothing_factor: 90 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3549 +L2 norm = 75015 +checksum: 223 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2756 +compression parameters: + quality : 70 + optimize_coding : 0 + smoothing_factor: 80 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3460 +L2 norm = 72294 +checksum: 107 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2432 +compression parameters: + quality : 70 + optimize_coding : 1 + smoothing_factor: 80 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3460 +L2 norm = 72294 +checksum: 107 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2853 +compression parameters: + quality : 70 + optimize_coding : 0 + smoothing_factor: 70 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3411 +L2 norm = 67365 +checksum: 229 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2537 +compression parameters: + quality : 70 + optimize_coding : 1 + smoothing_factor: 70 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3411 +L2 norm = 67365 +checksum: 229 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2938 +compression parameters: + quality : 70 + optimize_coding : 0 + smoothing_factor: 60 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3168 +L2 norm = 59704 +checksum: 233 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2621 +compression parameters: + quality : 70 + optimize_coding : 1 + smoothing_factor: 60 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3168 +L2 norm = 59704 +checksum: 233 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 3040 +compression parameters: + quality : 70 + optimize_coding : 0 + smoothing_factor: 50 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3205 +L2 norm = 57935 +checksum: 66 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2719 +compression parameters: + quality : 70 + optimize_coding : 1 + smoothing_factor: 50 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3205 +L2 norm = 57935 +checksum: 66 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 3152 +compression parameters: + quality : 70 + optimize_coding : 0 + smoothing_factor: 40 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3065 +L2 norm = 53647 +checksum: 166 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2833 +compression parameters: + quality : 70 + optimize_coding : 1 + smoothing_factor: 40 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3065 +L2 norm = 53647 +checksum: 166 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 3267 +compression parameters: + quality : 70 + optimize_coding : 0 + smoothing_factor: 30 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 2833 +L2 norm = 42671 +checksum: 22 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2947 +compression parameters: + quality : 70 + optimize_coding : 1 + smoothing_factor: 30 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 2833 +L2 norm = 42671 +checksum: 22 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 3398 +compression parameters: + quality : 70 + optimize_coding : 0 + smoothing_factor: 20 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 2787 +L2 norm = 41499 +checksum: 192 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 3080 +compression parameters: + quality : 70 + optimize_coding : 1 + smoothing_factor: 20 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 2787 +L2 norm = 41499 +checksum: 192 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2420 +compression parameters: + quality : 60 + optimize_coding : 0 + smoothing_factor: 90 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3678 +L2 norm = 79836 +checksum: 228 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2099 +compression parameters: + quality : 60 + optimize_coding : 1 + smoothing_factor: 90 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3678 +L2 norm = 79836 +checksum: 228 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2467 +compression parameters: + quality : 60 + optimize_coding : 0 + smoothing_factor: 80 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3580 +L2 norm = 74366 +checksum: 197 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2140 +compression parameters: + quality : 60 + optimize_coding : 1 + smoothing_factor: 80 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3580 +L2 norm = 74366 +checksum: 197 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2512 +compression parameters: + quality : 60 + optimize_coding : 0 + smoothing_factor: 70 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3526 +L2 norm = 72698 +checksum: 196 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2188 +compression parameters: + quality : 60 + optimize_coding : 1 + smoothing_factor: 70 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3526 +L2 norm = 72698 +checksum: 196 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2575 +compression parameters: + quality : 60 + optimize_coding : 0 + smoothing_factor: 60 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3449 +L2 norm = 65671 +checksum: 98 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2248 +compression parameters: + quality : 60 + optimize_coding : 1 + smoothing_factor: 60 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3449 +L2 norm = 65671 +checksum: 98 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2658 +compression parameters: + quality : 60 + optimize_coding : 0 + smoothing_factor: 50 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3360 +L2 norm = 62590 +checksum: 159 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2330 +compression parameters: + quality : 60 + optimize_coding : 1 + smoothing_factor: 50 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3360 +L2 norm = 62590 +checksum: 159 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2744 +compression parameters: + quality : 60 + optimize_coding : 0 + smoothing_factor: 40 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3248 +L2 norm = 58232 +checksum: 153 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2421 +compression parameters: + quality : 60 + optimize_coding : 1 + smoothing_factor: 40 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3248 +L2 norm = 58232 +checksum: 153 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2826 +compression parameters: + quality : 60 + optimize_coding : 0 + smoothing_factor: 30 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3226 +L2 norm = 55278 +checksum: 203 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2501 +compression parameters: + quality : 60 + optimize_coding : 1 + smoothing_factor: 30 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3226 +L2 norm = 55278 +checksum: 203 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2899 +compression parameters: + quality : 60 + optimize_coding : 0 + smoothing_factor: 20 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3019 +L2 norm = 47309 +checksum: 18 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2571 +compression parameters: + quality : 60 + optimize_coding : 1 + smoothing_factor: 20 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3019 +L2 norm = 47309 +checksum: 18 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2218 +compression parameters: + quality : 50 + optimize_coding : 0 + smoothing_factor: 90 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3833 +L2 norm = 80909 +checksum: 3 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 1894 +compression parameters: + quality : 50 + optimize_coding : 1 + smoothing_factor: 90 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3833 +L2 norm = 80909 +checksum: 3 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2257 +compression parameters: + quality : 50 + optimize_coding : 0 + smoothing_factor: 80 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3833 +L2 norm = 82641 +checksum: 200 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 1932 +compression parameters: + quality : 50 + optimize_coding : 1 + smoothing_factor: 80 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3833 +L2 norm = 82641 +checksum: 200 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2305 +compression parameters: + quality : 50 + optimize_coding : 0 + smoothing_factor: 70 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3687 +L2 norm = 79453 +checksum: 34 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 1983 +compression parameters: + quality : 50 + optimize_coding : 1 + smoothing_factor: 70 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3687 +L2 norm = 79453 +checksum: 34 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2350 +compression parameters: + quality : 50 + optimize_coding : 0 + smoothing_factor: 60 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3625 +L2 norm = 75569 +checksum: 129 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2024 +compression parameters: + quality : 50 + optimize_coding : 1 + smoothing_factor: 60 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3625 +L2 norm = 75569 +checksum: 129 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2410 +compression parameters: + quality : 50 + optimize_coding : 0 + smoothing_factor: 50 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3592 +L2 norm = 73880 +checksum: 123 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2088 +compression parameters: + quality : 50 + optimize_coding : 1 + smoothing_factor: 50 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3592 +L2 norm = 73880 +checksum: 123 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2462 +compression parameters: + quality : 50 + optimize_coding : 0 + smoothing_factor: 40 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3425 +L2 norm = 65851 +checksum: 54 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2134 +compression parameters: + quality : 50 + optimize_coding : 1 + smoothing_factor: 40 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3425 +L2 norm = 65851 +checksum: 54 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2534 +compression parameters: + quality : 50 + optimize_coding : 0 + smoothing_factor: 30 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3348 +L2 norm = 64306 +checksum: 9 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2207 +compression parameters: + quality : 50 + optimize_coding : 1 + smoothing_factor: 30 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3348 +L2 norm = 64306 +checksum: 9 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2611 +compression parameters: + quality : 50 + optimize_coding : 0 + smoothing_factor: 20 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3523 +L2 norm = 65227 +checksum: 186 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2279 +compression parameters: + quality : 50 + optimize_coding : 1 + smoothing_factor: 20 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3523 +L2 norm = 65227 +checksum: 186 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2004 +compression parameters: + quality : 40 + optimize_coding : 0 + smoothing_factor: 90 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3795 +L2 norm = 79447 +checksum: 210 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 1668 +compression parameters: + quality : 40 + optimize_coding : 1 + smoothing_factor: 90 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3795 +L2 norm = 79447 +checksum: 210 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2050 +compression parameters: + quality : 40 + optimize_coding : 0 + smoothing_factor: 80 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3752 +L2 norm = 78334 +checksum: 64 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 1719 +compression parameters: + quality : 40 + optimize_coding : 1 + smoothing_factor: 80 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3752 +L2 norm = 78334 +checksum: 64 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2088 +compression parameters: + quality : 40 + optimize_coding : 0 + smoothing_factor: 70 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3832 +L2 norm = 82332 +checksum: 200 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 1759 +compression parameters: + quality : 40 + optimize_coding : 1 + smoothing_factor: 70 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3832 +L2 norm = 82332 +checksum: 200 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2135 +compression parameters: + quality : 40 + optimize_coding : 0 + smoothing_factor: 60 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3842 +L2 norm = 81520 +checksum: 51 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 1806 +compression parameters: + quality : 40 + optimize_coding : 1 + smoothing_factor: 60 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3842 +L2 norm = 81520 +checksum: 51 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2172 +compression parameters: + quality : 40 + optimize_coding : 0 + smoothing_factor: 50 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3839 +L2 norm = 84057 +checksum: 148 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 1841 +compression parameters: + quality : 40 + optimize_coding : 1 + smoothing_factor: 50 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3839 +L2 norm = 84057 +checksum: 148 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2223 +compression parameters: + quality : 40 + optimize_coding : 0 + smoothing_factor: 40 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3721 +L2 norm = 76145 +checksum: 76 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 1894 +compression parameters: + quality : 40 + optimize_coding : 1 + smoothing_factor: 40 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3721 +L2 norm = 76145 +checksum: 76 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2274 +compression parameters: + quality : 40 + optimize_coding : 0 + smoothing_factor: 30 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3567 +L2 norm = 69559 +checksum: 48 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 1945 +compression parameters: + quality : 40 + optimize_coding : 1 + smoothing_factor: 30 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3567 +L2 norm = 69559 +checksum: 48 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2317 +compression parameters: + quality : 40 + optimize_coding : 0 + smoothing_factor: 20 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3543 +L2 norm = 68199 +checksum: 64 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 1986 +compression parameters: + quality : 40 + optimize_coding : 1 + smoothing_factor: 20 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3543 +L2 norm = 68199 +checksum: 64 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 1793 +compression parameters: + quality : 30 + optimize_coding : 0 + smoothing_factor: 90 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3865 +L2 norm = 78833 +checksum: 207 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 1443 +compression parameters: + quality : 30 + optimize_coding : 1 + smoothing_factor: 90 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3865 +L2 norm = 78833 +checksum: 207 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 1822 +compression parameters: + quality : 30 + optimize_coding : 0 + smoothing_factor: 80 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3865 +L2 norm = 79881 +checksum: 225 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 1473 +compression parameters: + quality : 30 + optimize_coding : 1 + smoothing_factor: 80 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3865 +L2 norm = 79881 +checksum: 225 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 1857 +compression parameters: + quality : 30 + optimize_coding : 0 + smoothing_factor: 70 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3673 +L2 norm = 72801 +checksum: 211 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 1503 +compression parameters: + quality : 30 + optimize_coding : 1 + smoothing_factor: 70 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3673 +L2 norm = 72801 +checksum: 211 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 1891 +compression parameters: + quality : 30 + optimize_coding : 0 + smoothing_factor: 60 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3736 +L2 norm = 74762 +checksum: 140 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 1541 +compression parameters: + quality : 30 + optimize_coding : 1 + smoothing_factor: 60 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3736 +L2 norm = 74762 +checksum: 140 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 1924 +compression parameters: + quality : 30 + optimize_coding : 0 + smoothing_factor: 50 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3746 +L2 norm = 75098 +checksum: 8 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 1573 +compression parameters: + quality : 30 + optimize_coding : 1 + smoothing_factor: 50 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3746 +L2 norm = 75098 +checksum: 8 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 1962 +compression parameters: + quality : 30 + optimize_coding : 0 + smoothing_factor: 40 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3842 +L2 norm = 79826 +checksum: 27 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 1609 +compression parameters: + quality : 30 + optimize_coding : 1 + smoothing_factor: 40 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3842 +L2 norm = 79826 +checksum: 27 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2002 +compression parameters: + quality : 30 + optimize_coding : 0 + smoothing_factor: 30 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3997 +L2 norm = 86115 +checksum: 30 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 1648 +compression parameters: + quality : 30 + optimize_coding : 1 + smoothing_factor: 30 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3997 +L2 norm = 86115 +checksum: 30 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 2044 +compression parameters: + quality : 30 + optimize_coding : 0 + smoothing_factor: 20 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3955 +L2 norm = 86119 +checksum: 228 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 1689 +compression parameters: + quality : 30 + optimize_coding : 1 + smoothing_factor: 20 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 3955 +L2 norm = 86119 +checksum: 228 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 1541 +compression parameters: + quality : 20 + optimize_coding : 0 + smoothing_factor: 90 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 4536 +L2 norm = 106044 +checksum: 62 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 1175 +compression parameters: + quality : 20 + optimize_coding : 1 + smoothing_factor: 90 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 4536 +L2 norm = 106044 +checksum: 62 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 1559 +compression parameters: + quality : 20 + optimize_coding : 0 + smoothing_factor: 80 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 4365 +L2 norm = 97835 +checksum: 167 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 1188 +compression parameters: + quality : 20 + optimize_coding : 1 + smoothing_factor: 80 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 4365 +L2 norm = 97835 +checksum: 167 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 1573 +compression parameters: + quality : 20 + optimize_coding : 0 + smoothing_factor: 70 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 4231 +L2 norm = 91467 +checksum: 167 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 1201 +compression parameters: + quality : 20 + optimize_coding : 1 + smoothing_factor: 70 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 4231 +L2 norm = 91467 +checksum: 167 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 1596 +compression parameters: + quality : 20 + optimize_coding : 0 + smoothing_factor: 60 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 4261 +L2 norm = 90325 +checksum: 27 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 1223 +compression parameters: + quality : 20 + optimize_coding : 1 + smoothing_factor: 60 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 4261 +L2 norm = 90325 +checksum: 27 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 1626 +compression parameters: + quality : 20 + optimize_coding : 0 + smoothing_factor: 50 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 4321 +L2 norm = 94645 +checksum: 111 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 1256 +compression parameters: + quality : 20 + optimize_coding : 1 + smoothing_factor: 50 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 4321 +L2 norm = 94645 +checksum: 111 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 1650 +compression parameters: + quality : 20 + optimize_coding : 0 + smoothing_factor: 40 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 4221 +L2 norm = 90715 +checksum: 154 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 1278 +compression parameters: + quality : 20 + optimize_coding : 1 + smoothing_factor: 40 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 4221 +L2 norm = 90715 +checksum: 154 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 1677 +compression parameters: + quality : 20 + optimize_coding : 0 + smoothing_factor: 30 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 4221 +L2 norm = 90031 +checksum: 64 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 1306 +compression parameters: + quality : 20 + optimize_coding : 1 + smoothing_factor: 30 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 4221 +L2 norm = 90031 +checksum: 64 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 1706 +compression parameters: + quality : 20 + optimize_coding : 0 + smoothing_factor: 20 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 4193 +L2 norm = 90679 +checksum: 247 + +image filename: "specmun.ppm" +compression statistics: + uncompressed data size: 33024 + compressed data size: 1336 +compression parameters: + quality : 20 + optimize_coding : 1 + smoothing_factor: 20 + subimage : ul(0,0) lr(1,1) +decompression parameters: + quantize_colors : 0 + do_fancy_upsampling : 0 + desired_number_of_colors: 0 + two_pass_quantize : 0 + dither_mode : 0 +L1 norm = 4193 +L2 norm = 90679 +checksum: 247 +exit 0 Modified: test-suite/trunk/External/SPEC/CINT95/132.ijpeg/Makefile URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/External/SPEC/CINT95/132.ijpeg/Makefile?rev=113320&r1=113319&r2=113320&view=diff ============================================================================== --- test-suite/trunk/External/SPEC/CINT95/132.ijpeg/Makefile (original) +++ test-suite/trunk/External/SPEC/CINT95/132.ijpeg/Makefile Tue Sep 7 19:20:49 2010 @@ -1,4 +1,7 @@ LEVEL = ../../../.. +Source=libpbm1.c libpbm2.c libpbm3.c libpbm4.c libpbm5.c libpgm1.c libpgm2.c libppm1.c libppm2.c libppm3.c libppm4.c libppm5.c spec_image.c spec_jmemdst.c spec_jmemsrc.c spec_main.c rdppm.c wrppm.c rdgif.c wrgif.c rdtarga.c wrtarga.c rdbmp.c wrbmp.c jcapi.c jcparam.c jdatadst.c jcmaster.c jcmarker.c jcmainct.c jcprepct.c jccoefct.c jccolor.c jcsample.c jchuff.c jcdctmgr.c jfdctfst.c jfdctflt.c jfdctint.c jdapi.c jdatasrc.c jdmaster.c jdmarker.c jdmainct.c jdcoefct.c jdpostct.c jddctmgr.c jidctfst.c jidctflt.c jidctint.c jidctred.c jdhuff.c jdsample.c jdcolor.c jquant1.c jquant2.c jdmerge.c jcomapi.c jutils.c jerror.c jmemmgr.c jmemnobs.c +include ../../Makefile.spec95 + ifeq ($(RUN_TYPE),test) FILENAME := specmun else @@ -11,5 +14,3 @@ # This #define is the perfectly logical way to get 132.ijpeg to #include errno.h CPPFLAGS += -D__VMS -Source=libpbm1.c libpbm2.c libpbm3.c libpbm4.c libpbm5.c libpgm1.c libpgm2.c libppm1.c libppm2.c libppm3.c libppm4.c libppm5.c spec_image.c spec_jmemdst.c spec_jmemsrc.c spec_main.c rdppm.c wrppm.c rdgif.c wrgif.c rdtarga.c wrtarga.c rdbmp.c wrbmp.c jcapi.c jcparam.c jdatadst.c jcmaster.c jcmarker.c jcmainct.c jcprepct.c jccoefct.c jccolor.c jcsample.c jchuff.c jcdctmgr.c jfdctfst.c jfdctflt.c jfdctint.c jdapi.c jdatasrc.c jdmaster.c jdmarker.c jdmainct.c jdcoefct.c jdpostct.c jddctmgr.c jidctfst.c jidctflt.c jidctint.c jidctred.c jdhuff.c jdsample.c jdcolor.c jquant1.c jquant2.c jdmerge.c jcomapi.c jutils.c jerror.c jmemmgr.c jmemnobs.c -include ../../Makefile.spec95 From grosbach at apple.com Tue Sep 7 19:25:51 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 08 Sep 2010 00:25:51 -0000 Subject: [llvm-commits] [llvm] r113322 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrNEON.td ARMInstrVFP.td Message-ID: <20100908002551.1C1A42A6C12C@llvm.org> Author: grosbach Date: Tue Sep 7 19:25:50 2010 New Revision: 113322 URL: http://llvm.org/viewvc/llvm-project?rev=113322&view=rev Log: VFP/NEON load/store multiple instructions are addrmode4, not 5. Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=113322&r1=113321&r2=113322&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Tue Sep 7 19:25:50 2010 @@ -1332,9 +1332,9 @@ } // Load / store multiple -class AXDI5 pattern> - : VFPXI { // TODO: Mark the instructions with the appropriate subtarget info. let Inst{27-25} = 0b110; @@ -1344,9 +1344,9 @@ let D = VFPNeonDomain; } -class AXSI5 pattern> - : VFPXI { // TODO: Mark the instructions with the appropriate subtarget info. let Inst{27-25} = 0b110; Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=113322&r1=113321&r2=113322&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Sep 7 19:25:50 2010 @@ -133,7 +133,7 @@ // This is equivalent to VLDMD except that it has a Q register operand // instead of a pair of D registers. def VLDMQ - : AXDI5<(outs QPR:$dst), (ins addrmode4:$addr, pred:$p), + : AXDI4<(outs QPR:$dst), (ins addrmode4:$addr, pred:$p), IndexModeNone, IIC_fpLoadm, "vldm${addr:submode}${p}\t$addr, ${dst:dregpair}", "", [(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]>; @@ -151,7 +151,7 @@ // This is equivalent to VSTMD except that it has a Q register operand // instead of a pair of D registers. def VSTMQ - : AXDI5<(outs), (ins QPR:$src, addrmode4:$addr, pred:$p), + : AXDI4<(outs), (ins QPR:$src, addrmode4:$addr, pred:$p), IndexModeNone, IIC_fpStorem, "vstm${addr:submode}${p}\t$addr, ${src:dregpair}", "", [(store (v2f64 QPR:$src), addrmode4:$addr)]>; Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=113322&r1=113321&r2=113322&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Tue Sep 7 19:25:50 2010 @@ -77,19 +77,19 @@ // let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in { -def VLDMD : AXDI5<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts, +def VLDMD : AXDI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts, variable_ops), IndexModeNone, IIC_fpLoadm, "vldm${addr:submode}${p}\t$addr, $dsts", "", []> { let Inst{20} = 1; } -def VLDMS : AXSI5<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts, +def VLDMS : AXSI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts, variable_ops), IndexModeNone, IIC_fpLoadm, "vldm${addr:submode}${p}\t$addr, $dsts", "", []> { let Inst{20} = 1; } -def VLDMD_UPD : AXDI5<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, +def VLDMD_UPD : AXDI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, reglist:$dsts, variable_ops), IndexModeUpd, IIC_fpLoadm, "vldm${addr:submode}${p}\t$addr!, $dsts", @@ -97,7 +97,7 @@ let Inst{20} = 1; } -def VLDMS_UPD : AXSI5<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, +def VLDMS_UPD : AXSI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, reglist:$dsts, variable_ops), IndexModeUpd, IIC_fpLoadm, "vldm${addr:submode}${p}\t$addr!, $dsts", @@ -107,19 +107,19 @@ } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in { -def VSTMD : AXDI5<(outs), (ins addrmode4:$addr, pred:$p, reglist:$srcs, +def VSTMD : AXDI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$srcs, variable_ops), IndexModeNone, IIC_fpStorem, "vstm${addr:submode}${p}\t$addr, $srcs", "", []> { let Inst{20} = 0; } -def VSTMS : AXSI5<(outs), (ins addrmode4:$addr, pred:$p, reglist:$srcs, +def VSTMS : AXSI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$srcs, variable_ops), IndexModeNone, IIC_fpStorem, "vstm${addr:submode}${p}\t$addr, $srcs", "", []> { let Inst{20} = 0; } -def VSTMD_UPD : AXDI5<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, +def VSTMD_UPD : AXDI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, reglist:$srcs, variable_ops), IndexModeUpd, IIC_fpStorem, "vstm${addr:submode}${p}\t$addr!, $srcs", @@ -127,7 +127,7 @@ let Inst{20} = 0; } -def VSTMS_UPD : AXSI5<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, +def VSTMS_UPD : AXSI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, reglist:$srcs, variable_ops), IndexModeUpd, IIC_fpStorem, "vstm${addr:submode}${p}\t$addr!, $srcs", From grosbach at apple.com Tue Sep 7 19:26:59 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 08 Sep 2010 00:26:59 -0000 Subject: [llvm-commits] [llvm] r113323 - /llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Message-ID: <20100908002659.5AA412A6C12C@llvm.org> Author: grosbach Date: Tue Sep 7 19:26:59 2010 New Revision: 113323 URL: http://llvm.org/viewvc/llvm-project?rev=113323&view=rev Log: correct spill code to properly determine if dynamic stack realignment is present in the function and thus whether aligned load/store instructions can be used. Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=113323&r1=113322&r2=113323&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Sep 7 19:26:59 2010 @@ -748,7 +748,7 @@ case ARM::QPR_VFP2RegClassID: case ARM::QPR_8RegClassID: // FIXME: Neon instructions should support predicates - if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { + if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) { AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q)) .addFrameIndex(FI).addImm(16) .addReg(SrcReg, getKillRegState(isKill)) @@ -846,7 +846,7 @@ case ARM::QPRRegClassID: case ARM::QPR_VFP2RegClassID: case ARM::QPR_8RegClassID: - if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { + if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) { AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q), DestReg) .addFrameIndex(FI).addImm(16) .addMemOperand(MMO)); From gohman at apple.com Tue Sep 7 20:32:20 2010 From: gohman at apple.com (Dan Gohman) Date: Wed, 08 Sep 2010 01:32:20 -0000 Subject: [llvm-commits] [llvm] r113329 - in /llvm/trunk: include/llvm/Analysis/AliasAnalysis.h lib/Analysis/AliasAnalysis.cpp lib/Analysis/BasicAliasAnalysis.cpp Message-ID: <20100908013220.8342E2A6C12C@llvm.org> Author: djg Date: Tue Sep 7 20:32:20 2010 New Revision: 113329 URL: http://llvm.org/viewvc/llvm-project?rev=113329&view=rev Log: Add a new experimental generalized dependence query interface to AliasAnalysis, and some code for implementing the new query on top of existing implementations by making standard alias and getModRefInfo queries. Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h llvm/trunk/lib/Analysis/AliasAnalysis.cpp llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/AliasAnalysis.h?rev=113329&r1=113328&r2=113329&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/AliasAnalysis.h (original) +++ llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Tue Sep 7 20:32:20 2010 @@ -278,6 +278,81 @@ ImmutableCallSite CS2); //===--------------------------------------------------------------------===// + /// Dependence queries. + /// + + /// DependenceResult - These are the return values for getDependence queries. + /// They are defined in terms of "memory", but they are also used to model + /// other side effects, such as I/O and volatility. + enum DependenceResult { + /// ReadThenRead - The instructions are ReadThenReadSome and the second + /// instruction reads from exactly the same memory read from by the first. + ReadThenRead, + + /// ReadThenReadSome - The instructions are Independent, both are read-only, + /// and the second instruction reads from a subset of the memory read from + /// by the first. + ReadThenReadSome, + + /// Independent - Neither instruction reads from or writes to memory written + /// to by the other. All enum values lower than this one are special cases + /// of Indepenent. + Independent, + + /// WriteThenRead - The instructions are WriteThenReadSome and the second + /// instruction reads from exactly the same memory written by the first. + WriteThenRead, + + /// WriteThenReadSome - The first instruction is write-only, the second + /// instruction is read-only, and the second only reads from memory + /// written to by the first. + WriteThenReadSome, + + /// ReadThenWrite - The instructions are ReadThenWriteSome and the second + /// instruction writes to exactly the same memory read from by the first. + ReadThenWrite, + + /// WriteThenWrite - The instructions are WriteThenWriteSome, and the + /// second instruction writes to exactly the same memory written to by + /// the first. + WriteThenWrite, + + /// WriteSomeThenWrite - Both instructions are write-only, and the second + /// instruction writes to a superset of the memory written to by the first. + WriteSomeThenWrite, + + /// Unknown - The relationship between the instructions cannot be + /// determined or does not fit into any of the cases defined here. + Unknown + }; + + /// DependenceQueryFlags - Flags for refining dependence queries. + enum DependenceQueryFlags { + Default = 0, + IgnoreLoads = 1, + IgnoreStores = 2 + }; + + /// getDependence - Determine the dependence relationship between the + /// instructions. This does not include "register" dependencies; it just + /// considers memory references and other side effects. + /// WARNING: This is an experimental interface. + DependenceResult getDependence(const Instruction *First, + const Instruction *Second) { + return getDependence(First, Default, Second, Default); + } + + /// getDependence - Determine the dependence relationship between the + /// instructions. This does not include "register" dependencies; it just + /// considers memory references and other side effects. This overload + /// accepts additional flags to refine the query. + /// WARNING: This is an experimental interface. + virtual DependenceResult getDependence(const Instruction *First, + DependenceQueryFlags FirstFlags, + const Instruction *Second, + DependenceQueryFlags SecondFlags); + + //===--------------------------------------------------------------------===// /// Higher level methods for querying mod/ref information. /// @@ -322,6 +397,15 @@ copyValue(Old, New); deleteValue(Old); } + +protected: + /// getDependenceViaModRefInfo - Helper function for implementing getDependence + /// in implementations which already have getModRefInfo implementations. + DependenceResult getDependenceViaModRefInfo(const Instruction *First, + DependenceQueryFlags FirstFlags, + const Instruction *Second, + DependenceQueryFlags SecondFlags); + }; /// isNoAliasCall - Return true if this pointer is returned by a noalias Modified: llvm/trunk/lib/Analysis/AliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasAnalysis.cpp?rev=113329&r1=113328&r2=113329&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/AliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/AliasAnalysis.cpp Tue Sep 7 20:32:20 2010 @@ -188,6 +188,14 @@ return AA->getModRefBehavior(F); } +AliasAnalysis::DependenceResult +AliasAnalysis::getDependence(const Instruction *First, + DependenceQueryFlags FirstFlags, + const Instruction *Second, + DependenceQueryFlags SecondFlags) { + assert(AA && "AA didn't call InitializeAliasAnalyais in its run method!"); + return AA->getDependence(First, FirstFlags, Second, SecondFlags); +} //===----------------------------------------------------------------------===// // AliasAnalysis non-virtual helper method implementation @@ -245,6 +253,190 @@ return ModRef; } +AliasAnalysis::DependenceResult +AliasAnalysis::getDependenceViaModRefInfo(const Instruction *First, + DependenceQueryFlags FirstFlags, + const Instruction *Second, + DependenceQueryFlags SecondFlags) { + if (const LoadInst *L = dyn_cast(First)) { + // Be over-conservative with volatile for now. + if (L->isVolatile()) + return Unknown; + + // Forward this query to getModRefInfo. + switch (getModRefInfo(Second, + L->getPointerOperand(), + getTypeStoreSize(L->getType()))) { + case NoModRef: + // Second doesn't reference First's memory, so they're independent. + return Independent; + + case Ref: + // Second only reads from the memory read from by First. If it + // also writes to any other memory, be conservative. + if (Second->mayWriteToMemory()) + return Unknown; + + // If it's loading the same size from the same address, we can + // give a more precise result. + if (const LoadInst *SecondL = dyn_cast(Second)) { + unsigned LSize = getTypeStoreSize(L->getType()); + unsigned SecondLSize = getTypeStoreSize(SecondL->getType()); + if (alias(L->getPointerOperand(), LSize, + SecondL->getPointerOperand(), SecondLSize) == + MustAlias) { + // If the loads are the same size, it's ReadThenRead. + if (LSize == SecondLSize) + return ReadThenRead; + + // If the second load is smaller, it's only ReadThenReadSome. + if (LSize > SecondLSize) + return ReadThenReadSome; + } + } + + // Otherwise it's just two loads. + return Independent; + + case Mod: + // Second only writes to the memory read from by First. If it + // also reads from any other memory, be conservative. + if (Second->mayReadFromMemory()) + return Unknown; + + // If it's storing the same size to the same address, we can + // give a more precise result. + if (const StoreInst *SecondS = dyn_cast(Second)) { + unsigned LSize = getTypeStoreSize(L->getType()); + unsigned SecondSSize = getTypeStoreSize(SecondS->getType()); + if (alias(L->getPointerOperand(), LSize, + SecondS->getPointerOperand(), SecondSSize) == + MustAlias) { + // If the load and the store are the same size, it's ReadThenWrite. + if (LSize == SecondSSize) + return ReadThenWrite; + } + } + + // Otherwise we don't know if it could be writing to other memory. + return Unknown; + + case ModRef: + // Second reads and writes to the memory read from by First. + // We don't have a way to express that. + return Unknown; + } + + } else if (const StoreInst *S = dyn_cast(First)) { + // Be over-conservative with volatile for now. + if (S->isVolatile()) + return Unknown; + + // Forward this query to getModRefInfo. + switch (getModRefInfo(Second, + S->getPointerOperand(), + getTypeStoreSize(S->getValueOperand()->getType()))) { + case NoModRef: + // Second doesn't reference First's memory, so they're independent. + return Independent; + + case Ref: + // Second only reads from the memory written to by First. If it + // also writes to any other memory, be conservative. + if (Second->mayWriteToMemory()) + return Unknown; + + // If it's loading the same size from the same address, we can + // give a more precise result. + if (const LoadInst *SecondL = dyn_cast(Second)) { + unsigned SSize = getTypeStoreSize(S->getValueOperand()->getType()); + unsigned SecondLSize = getTypeStoreSize(SecondL->getType()); + if (alias(S->getPointerOperand(), SSize, + SecondL->getPointerOperand(), SecondLSize) == + MustAlias) { + // If the store and the load are the same size, it's WriteThenRead. + if (SSize == SecondLSize) + return WriteThenRead; + + // If the load is smaller, it's only WriteThenReadSome. + if (SSize > SecondLSize) + return WriteThenReadSome; + } + } + + // Otherwise we don't know if it could be reading from other memory. + return Unknown; + + case Mod: + // Second only writes to the memory written to by First. If it + // also reads from any other memory, be conservative. + if (Second->mayReadFromMemory()) + return Unknown; + + // If it's storing the same size to the same address, we can + // give a more precise result. + if (const StoreInst *SecondS = dyn_cast(Second)) { + unsigned SSize = getTypeStoreSize(S->getValueOperand()->getType()); + unsigned SecondSSize = getTypeStoreSize(SecondS->getType()); + if (alias(S->getPointerOperand(), SSize, + SecondS->getPointerOperand(), SecondSSize) == + MustAlias) { + // If the stores are the same size, it's WriteThenWrite. + if (SSize == SecondSSize) + return WriteThenWrite; + + // If the second store is larger, it's only WriteSomeThenWrite. + if (SSize < SecondSSize) + return WriteSomeThenWrite; + } + } + + // Otherwise we don't know if it could be writing to other memory. + return Unknown; + + case ModRef: + // Second reads and writes to the memory written to by First. + // We don't have a way to express that. + return Unknown; + } + + } else if (const VAArgInst *V = dyn_cast(First)) { + // Forward this query to getModRefInfo. + if (getModRefInfo(Second, V->getOperand(0), UnknownSize) == NoModRef) + // Second doesn't reference First's memory, so they're independent. + return Independent; + + } else if (ImmutableCallSite FirstCS = cast(First)) { + // If both instructions are calls/invokes we can use the two-callsite + // form of getModRefInfo. + if (ImmutableCallSite SecondCS = cast(Second)) + // getModRefInfo's arguments are backwards from intuition. + switch (getModRefInfo(SecondCS, FirstCS)) { + case NoModRef: + // Second doesn't reference First's memory, so they're independent. + return Independent; + + case Ref: + // If they're both read-only, there's no dependence. + if (FirstCS.onlyReadsMemory() && SecondCS.onlyReadsMemory()) + return Independent; + + // Otherwise it's not obvious what we can do here. + return Unknown; + + case Mod: + // It's not obvious what we can do here. + return Unknown; + + case ModRef: + // I know, right? + return Unknown; + } + } + + // For anything else, be conservative. + return Unknown; +} AliasAnalysis::ModRefBehavior AliasAnalysis::getIntrinsicModRefBehavior(unsigned iid) { Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=113329&r1=113328&r2=113329&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Tue Sep 7 20:32:20 2010 @@ -171,6 +171,13 @@ return ModRef; } + virtual DependenceResult getDependence(const Instruction *First, + DependenceQueryFlags FirstFlags, + const Instruction *Second, + DependenceQueryFlags SecondFlags) { + return Unknown; + } + virtual void deleteValue(Value *V) {} virtual void copyValue(Value *From, Value *To) {} @@ -523,6 +530,11 @@ /// For use when the call site is not known. virtual ModRefBehavior getModRefBehavior(const Function *F); + virtual DependenceResult getDependence(const Instruction *First, + DependenceQueryFlags FirstFlags, + const Instruction *Second, + DependenceQueryFlags SecondFlags); + /// getAdjustedAnalysisPointer - This method is used when a pass implements /// an analysis interface through multiple inheritance. If needed, it /// should override this to adjust the this pointer as needed for the @@ -734,6 +746,14 @@ return AliasAnalysis::getModRefInfo(CS, P, Size); } +AliasAnalysis::DependenceResult +BasicAliasAnalysis::getDependence(const Instruction *First, + DependenceQueryFlags FirstFlags, + const Instruction *Second, + DependenceQueryFlags SecondFlags) { + // We don't have anything special to say yet. + return getDependenceViaModRefInfo(First, FirstFlags, Second, SecondFlags); +} /// aliasGEP - Provide a bunch of ad-hoc rules to disambiguate a GEP instruction /// against another pointer. We know that V1 is a GEP, but we don't know From grosbach at apple.com Tue Sep 7 20:47:49 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 08 Sep 2010 01:47:49 -0000 Subject: [llvm-commits] [llvm] r113331 - /llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Message-ID: <20100908014749.A549A2A6C12C@llvm.org> Author: grosbach Date: Tue Sep 7 20:47:49 2010 New Revision: 113331 URL: http://llvm.org/viewvc/llvm-project?rev=113331&view=rev Log: disable temporarily while sorting out a few test failures in Thumb2-O0 tests. Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=113331&r1=113330&r2=113331&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Tue Sep 7 20:47:49 2010 @@ -51,7 +51,7 @@ using namespace llvm; static cl::opt -EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true), +EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(false), cl::desc("Enable use of a base pointer for complex stack frames")); unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum, From grosbach at apple.com Tue Sep 7 20:49:09 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 08 Sep 2010 01:49:09 -0000 Subject: [llvm-commits] [llvm] r113332 - /llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Message-ID: <20100908014909.AEC042A6C12C@llvm.org> Author: grosbach Date: Tue Sep 7 20:49:09 2010 New Revision: 113332 URL: http://llvm.org/viewvc/llvm-project?rev=113332&view=rev Log: woops. need to update a test along with this. Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=113332&r1=113331&r2=113332&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Tue Sep 7 20:49:09 2010 @@ -51,7 +51,7 @@ using namespace llvm; static cl::opt -EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(false), +EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true), cl::desc("Enable use of a base pointer for complex stack frames")); unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum, From grosbach at apple.com Tue Sep 7 21:00:34 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 08 Sep 2010 02:00:34 -0000 Subject: [llvm-commits] [llvm] r113333 - in /llvm/trunk: lib/Target/ARM/ARMBaseRegisterInfo.cpp test/CodeGen/Thumb/dyn-stackalloc.ll Message-ID: <20100908020035.038C92A6C12C@llvm.org> Author: grosbach Date: Tue Sep 7 21:00:34 2010 New Revision: 113333 URL: http://llvm.org/viewvc/llvm-project?rev=113333&view=rev Log: disable for the moment while tracking down a few Thumb2-O0 failure that look related. (attempt deux, complete w/ test update this time) Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp llvm/trunk/test/CodeGen/Thumb/dyn-stackalloc.ll Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=113333&r1=113332&r2=113333&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Tue Sep 7 21:00:34 2010 @@ -51,7 +51,7 @@ using namespace llvm; static cl::opt -EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true), +EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(false), cl::desc("Enable use of a base pointer for complex stack frames")); unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum, Modified: llvm/trunk/test/CodeGen/Thumb/dyn-stackalloc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/dyn-stackalloc.ll?rev=113333&r1=113332&r2=113333&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/dyn-stackalloc.ll (original) +++ llvm/trunk/test/CodeGen/Thumb/dyn-stackalloc.ll Tue Sep 7 21:00:34 2010 @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=thumb | not grep {ldr sp} ; RUN: llc < %s -mtriple=thumb-apple-darwin | \ ; RUN: not grep {sub.*r7} -; RUN: llc < %s -march=thumb | grep {mov.*r6, sp} +; RUN: llc < %s -march=thumb | grep 4294967280 %struct.state = type { i32, %struct.info*, float**, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64, i64, i64, i64, i64, i64, i8* } %struct.info = type { i32, i32, i32, i32, i32, i32, i32, i8* } From criswell at uiuc.edu Tue Sep 7 22:50:29 2010 From: criswell at uiuc.edu (John Criswell) Date: Wed, 08 Sep 2010 03:50:29 -0000 Subject: [llvm-commits] [poolalloc] r113336 - in /poolalloc/trunk: include/poolalloc/PoolAllocate.h lib/PoolAllocate/PoolAllocate.cpp Message-ID: <20100908035029.EB0522A6C12C@llvm.org> Author: criswell Date: Tue Sep 7 22:50:29 2010 New Revision: 113336 URL: http://llvm.org/viewvc/llvm-project?rev=113336&view=rev Log: Initial refactoring to properly handle indirect function calls to targets with differing signatures. Moved the code that finds function pool arguments into the FindPoolArgs() method. Modified the code to ask DSA which DSNodes need to have their pools passed in and have a function find those DSNodes reachable from those DSNodes. No functionality changes. Modified: poolalloc/trunk/include/poolalloc/PoolAllocate.h poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp Modified: poolalloc/trunk/include/poolalloc/PoolAllocate.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/poolalloc/PoolAllocate.h?rev=113336&r1=113335&r2=113336&view=diff ============================================================================== --- poolalloc/trunk/include/poolalloc/PoolAllocate.h (original) +++ poolalloc/trunk/include/poolalloc/PoolAllocate.h Tue Sep 7 22:50:29 2010 @@ -443,10 +443,15 @@ /// are global pools. bool SetupGlobalPools(Module &M); + /// FindPoolArgs - Make a pass over the module and find the arguments of each + /// function that need to have their pools passed in. This will build a + /// FunctionInfo for each function. + void FindPoolArgs (Module & M); + /// FindFunctionPoolArgs - In the first pass over the program, we decide which /// arguments will have to be added for each function, build the FunctionInfo /// map and recording this info in the ArgNodes set. - void FindFunctionPoolArgs(Function &F); + void FindFunctionPoolArgs (Function &F); /// MakeFunctionClone - If the specified function needs to be modified for /// pool allocation support, make a clone of it, adding additional arguments Modified: poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp?rev=113336&r1=113335&r2=113336&view=diff ============================================================================== --- poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp (original) +++ poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp Tue Sep 7 22:50:29 2010 @@ -133,11 +133,11 @@ if (SetupGlobalPools(M)) return true; - // Loop over the functions in the original program finding the pool desc. - // arguments necessary for each function that is indirectly callable. - for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I) - if (!I->isDeclaration() && Graphs->hasDSGraph(*I)) - FindFunctionPoolArgs(*I); + // + // Find the DSNodes for each function that will require pool descriptor + // arguments to be passed into the function. + // + FindPoolArgs (M); // Map that maps an original function to its clone std::map FuncMap; @@ -523,7 +523,7 @@ // MarkedNodes - A set of DSNodes whose associated pools should be // passed into the function when it is called. // -static void +static inline void MarkNodesWhichMustBePassedIn (DenseSet &MarkedNodes, Function &F, DSGraph* G, bool PassAllArguments) { @@ -619,11 +619,92 @@ } } +// +// Function: MarkNodesWhichMustBePassedIn() +// +// Description: +// Given a function and its DSGraph, determine which values will need to have +// their pools passed in from the caller. +// +// Inputs: +// RootNodes - The root DSNodes for which pools may need to be passed +// in. These include the DSNodes of any arguments, the +// DSNode of the return value, and the VarArgs DSNode. +// G - The DSGraph of the function F. +// PassAllArguments - Flags whether all arguments should have their pool +// handles passed into the function. +// +// Outputs: +// MarkedNodes - A set of DSNodes whose associated pools should be +// passed into the function when it is called. +// +static inline void +MarkNodesWhichMustBePassedIn (DenseSet &MarkedNodes, + const std::vector & RootNodes, + DSGraph* G, + bool PassAllArguments) { + // + // Loop through all of the root DSNodes. Insert them and any DSNode + // reachable from them into the set of DSNodes for which a pool descriptor + // must be passed. + // + for (unsigned index = 0; index < RootNodes.size(); ++index) { + if (DSNode * N = RootNodes[index].getNode()) { + MarkedNodes.insert (N); + N->markReachableNodes(MarkedNodes); + } + } + + // + // Determine which DSNodes are reachable from globals. If a node is + // reachable from a global, we will create a global pool for it, so no + // argument passage is required. + // + DenseSet NodesFromGlobals; + GetNodesReachableFromGlobals (G, NodesFromGlobals); + + // + // Remove any nodes reachable from a global. These nodes will be put into + // global pools, which do not require arguments to be passed in. Also, erase + // any marked node that is not a heap node. Since no allocations or frees + // will be done with it, it needs no argument. + // + // FIXME: + // 1) PassAllArguments seems to be ignored here. Why is that? + // 2) Should the heap node check be part of the PassAllArguments check? + // 3) SAFECode probably needs to pass the pool even if it's not a heap node. + // We should probably just do what the heuristic tells us to do. + // + for (DenseSet::iterator I = MarkedNodes.begin(), + E = MarkedNodes.end(); I != E; ) { + const DSNode *N = *I; ++I; + if ((!(1 || N->isHeapNode()) && !PassAllArguments) || NodesFromGlobals.count(N)) + MarkedNodes.erase(N); + } + + return; +} + + +// +// Method: FindPoolArgs() +// +// Description: +// Loop over the functions in the original program finding the pool descriptor +// arguments necessary for each function. +// +void +PoolAllocate::FindPoolArgs (Module & M) { + for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I) + if (!I->isDeclaration() && Graphs->hasDSGraph(*I)) + FindFunctionPoolArgs(*I); +} /// FindFunctionPoolArgs - In the first pass over the program, we decide which /// arguments will have to be added for each function, build the FunctionInfo /// map and recording this info in the ArgNodes set. -void PoolAllocate::FindFunctionPoolArgs(Function &F) { +void +PoolAllocate::FindFunctionPoolArgs (Function & F) { DSGraph* G = Graphs->getDSGraph(F); // Create a new entry for F. @@ -631,33 +712,60 @@ FunctionInfo.insert(std::make_pair(&F, FuncInfo(F))).first->second; DenseSet &MarkedNodes = FI.MarkedNodes; + // + // If there is no memory activity in this function, then nothing is required. + // if (G->node_begin() == G->node_end()) - return; // No memory activity, nothing is required + return; + + // + // Find all of the DSNodes which could require a pool to be passed into the + // function. + // + std::vector Args; + G->getFunctionArgumentsForCall (&F, Args); // Find DataStructure nodes which are allocated in pools non-local to the // current function. This set will contain all of the DSNodes which require // pools to be passed in from outside of the function. - MarkNodesWhichMustBePassedIn(MarkedNodes, F, G, PassAllArguments); + MarkNodesWhichMustBePassedIn(MarkedNodes, Args, G, PassAllArguments); - //FI.ArgNodes.insert(FI.ArgNodes.end(), MarkedNodes.begin(), MarkedNodes.end()); - //Work around DenseSet not having iterator traits + // + // DenseSet does not have iterator traits, so we cannot use an insert() + // method that takes iterators. Instead, we must use a loop to insert each + // element into ArgNodes one at a time. + // for (DenseSet::iterator ii = MarkedNodes.begin(), ee = MarkedNodes.end(); ii != ee; ++ii) FI.ArgNodes.insert(FI.ArgNodes.end(), *ii); } -// MakeFunctionClone - If the specified function needs to be modified for pool -// allocation support, make a clone of it, adding additional arguments as -// necessary, and return it. If not, just return null. // -Function *PoolAllocate::MakeFunctionClone(Function &F) { +// Method: MakeFunctionClone() +// +// Description: +// If the specified function needs to be modified for pool allocation support, +// make a clone of it, adding additional arguments as necessary, and return +// it. +// +// Return value: +// NULL - The function did not need to be cloned. +// Otherwise, a pointer to the clone of the function is returned. +// +Function * +PoolAllocate::MakeFunctionClone (Function & F) { + // + // If the DSGraph for this function has no DSNodes, then we don't need to + // make a clone. + // DSGraph* G = Graphs->getDSGraph(F); if (G->node_begin() == G->node_end()) return 0; - - FuncInfo &FI = *getFuncInfo(F); - // No need to clone if no pools need to be passed in! + // + // There is no need to clone a function if no pools need to be passed in! + // + FuncInfo &FI = *getFuncInfo(F); if (FI.ArgNodes.empty()) return 0; From grosbach at apple.com Tue Sep 7 22:51:44 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 08 Sep 2010 03:51:44 -0000 Subject: [llvm-commits] [llvm] r113337 - /llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Message-ID: <20100908035144.644962A6C12C@llvm.org> Author: grosbach Date: Tue Sep 7 22:51:44 2010 New Revision: 113337 URL: http://llvm.org/viewvc/llvm-project?rev=113337&view=rev Log: remove obsolete comment Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=113337&r1=113336&r2=113337&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Sep 7 22:51:44 2010 @@ -747,7 +747,6 @@ case ARM::QPRRegClassID: case ARM::QPR_VFP2RegClassID: case ARM::QPR_8RegClassID: - // FIXME: Neon instructions should support predicates if (Align >= 16 && getRegisterInfo().needsStackRealignment(MF)) { AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q)) .addFrameIndex(FI).addImm(16) From grosbach at apple.com Tue Sep 7 22:54:02 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 08 Sep 2010 03:54:02 -0000 Subject: [llvm-commits] [llvm] r113338 - /llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Message-ID: <20100908035402.9F8BD2A6C12C@llvm.org> Author: grosbach Date: Tue Sep 7 22:54:02 2010 New Revision: 113338 URL: http://llvm.org/viewvc/llvm-project?rev=113338&view=rev Log: remove trailing whitespace Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=113338&r1=113337&r2=113338&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Sep 7 22:54:02 2010 @@ -57,7 +57,7 @@ cl::desc("Generate tail calls (TEMPORARY OPTION)."), cl::init(false)); -// This option should go away when Machine LICM is smart enough to hoist a +// This option should go away when Machine LICM is smart enough to hoist a // reg-to-reg VDUP. static cl::opt EnableARMVDUPsplat("arm-vdup-splat", cl::Hidden, @@ -640,7 +640,7 @@ case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP"; case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN"; - + case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER"; case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC"; @@ -1490,7 +1490,7 @@ // LR. This means if we need to reload LR, it takes an extra instructions, // which outweighs the value of the tail call; but here we don't know yet // whether LR is going to be used. Probably the right approach is to - // generate the tail call here and turn it back into CALL/RET in + // generate the tail call here and turn it back into CALL/RET in // emitEpilogue if LR is used. if (Subtarget->isThumb1Only()) return false; @@ -1583,7 +1583,7 @@ if (!VA.isRegLoc()) return false; if (!ArgLocs[++i].isRegLoc()) - return false; + return false; if (RegVT == MVT::v2f64) { if (!ArgLocs[++i].isRegLoc()) return false; @@ -2054,7 +2054,7 @@ RC = ARM::GPRRegisterClass; // Transform the arguments stored in physical registers into virtual ones. - unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); + unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); SDValue ArgValue2; @@ -2825,7 +2825,7 @@ return DAG.getMergeValues(Ops, 2, dl); } -SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op, +SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const { // The rounding mode is in bits 23:22 of the FPSCR. // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0 @@ -2835,11 +2835,11 @@ SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32, DAG.getConstant(Intrinsic::arm_get_fpscr, MVT::i32)); - SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR, + SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR, DAG.getConstant(1U << 22, MVT::i32)); SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds, DAG.getConstant(22, MVT::i32)); - return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE, + return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE, DAG.getConstant(3, MVT::i32)); } @@ -3376,7 +3376,7 @@ // If this is a case we can't handle, return null and let the default // expansion code take care of it. -static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, +static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) { BuildVectorSDNode *BVN = cast(Op.getNode()); DebugLoc dl = Op.getDebugLoc(); @@ -3448,11 +3448,11 @@ if (VT.getVectorElementType().isFloatingPoint()) { SmallVector Ops; for (unsigned i = 0; i < NumElts; ++i) - Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, + Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op.getOperand(i))); SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &Ops[0], NumElts); - return DAG.getNode(ISD::BIT_CONVERT, dl, VT, + return DAG.getNode(ISD::BIT_CONVERT, dl, VT, LowerBUILD_VECTOR(Val, DAG, ST)); } SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl); @@ -5143,7 +5143,7 @@ if (!Subtarget->isThumb()) return ARM_AM::getSOImmVal(Imm) != -1; if (Subtarget->isThumb2()) - return ARM_AM::getT2SOImmVal(Imm) != -1; + return ARM_AM::getT2SOImmVal(Imm) != -1; return Imm >= 0 && Imm <= 255; } From aggarwa4 at illinois.edu Tue Sep 7 23:05:33 2010 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Wed, 08 Sep 2010 04:05:33 -0000 Subject: [llvm-commits] [poolalloc] r113339 - in /poolalloc/trunk/lib/DSA: DSGraph.cpp DSTest.cpp Local.cpp Message-ID: <20100908040533.DA73A2A6C12C@llvm.org> Author: aggarwa4 Date: Tue Sep 7 23:05:33 2010 New Revision: 113339 URL: http://llvm.org/viewvc/llvm-project?rev=113339&view=rev Log: Removed redundant code, and fixed some code Modified: poolalloc/trunk/lib/DSA/DSGraph.cpp poolalloc/trunk/lib/DSA/DSTest.cpp poolalloc/trunk/lib/DSA/Local.cpp Modified: poolalloc/trunk/lib/DSA/DSGraph.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DSGraph.cpp?rev=113339&r1=113338&r2=113339&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/DSGraph.cpp (original) +++ poolalloc/trunk/lib/DSA/DSGraph.cpp Tue Sep 7 23:05:33 2010 @@ -549,6 +549,11 @@ //of a better way. For now, this assumption is known limitation. const FunctionType *CalleeFuncType = DSCallSite::FunctionTypeOfCallSite(CS); int NumFixedArgs = CalleeFuncType->getNumParams(); + + // Sanity check--this really, really shouldn't happen + if (!CalleeFuncType->isVarArg()) + assert(CS.arg_size() == static_cast(NumFixedArgs) && + "Too many arguments/incorrect function signature!"); std::vector Args; Args.reserve(CS.arg_end()-CS.arg_begin()); Modified: poolalloc/trunk/lib/DSA/DSTest.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DSTest.cpp?rev=113339&r1=113338&r2=113339&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/DSTest.cpp (original) +++ poolalloc/trunk/lib/DSA/DSTest.cpp Tue Sep 7 23:05:33 2010 @@ -279,14 +279,14 @@ if (N->type_begin() != N->type_end()) for (DSNode::TyMapTy::const_iterator ii = N->type_begin(), ee = N->type_end(); ii != ee; ++ii) { - if (!firstType) O << " "; + if (!firstType) O << "::"; firstType = false; O << ii->first << ":"; if (ii->second) { bool first = true; for (svset::const_iterator ni = ii->second->begin(), ne = ii->second->end(); ni != ne; ++ni) { - if (!first) O << ","; + if (!first) O << "|"; WriteTypeSymbolic(O, *ni, M); first = false; } Modified: poolalloc/trunk/lib/DSA/Local.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/Local.cpp?rev=113339&r1=113338&r2=113339&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/Local.cpp (original) +++ poolalloc/trunk/lib/DSA/Local.cpp Tue Sep 7 23:05:33 2010 @@ -447,8 +447,7 @@ Dest.getNode()->setModifiedMarker(); // Ensure a type-record exists... - Dest.getNode()->mergeTypeInfo(StoredTy, 0); //FIXME: calculate offset - Dest.getNode()->foldNodeCompletely(); + Dest.getNode()->mergeTypeInfo(StoredTy, I.getInsertedValueOperandIndex()); // Avoid adding edges from null, or processing non-"pointer" stores if (isa(StoredTy)) @@ -462,8 +461,7 @@ Ptr.getNode()->setReadMarker(); // Ensure a typerecord exists... - // FIXME: calculate offset - Ptr.getNode()->mergeTypeInfo(I.getType(), 0); + Ptr.getNode()->mergeTypeInfo(I.getType(), I.getAggregateOperandIndex()); if (isa(I.getType())) setDestTo(I, getLink(Ptr)); @@ -924,31 +922,17 @@ DSNodeHandle VarArgNH; // Calculate the arguments vector... - if (!CalleeFuncType->isVarArg()) { - // Add all pointer arguments - for (CallSite::arg_iterator I = CS.arg_begin(), E = CS.arg_end(); - I != E; ++I) { - if (isa((*I)->getType())) - Args.push_back(getValueDest(*I)); - if (I - CS.arg_begin() >= NumFixedArgs) { - errs() << "WARNING: Call contains too many arguments:\n"; - CS.getInstruction()->dump(); - assert(0 && "Failing for now"); - } - } - } else { // Add all fixed pointer arguments, then merge the rest together - for (CallSite::arg_iterator I = CS.arg_begin(), E = CS.arg_end(); - I != E; ++I) - if (isa((*I)->getType())) { - DSNodeHandle ArgNode = getValueDest(*I); - if (I - CS.arg_begin() < NumFixedArgs) { - Args.push_back(ArgNode); - } else { - VarArgNH.mergeWith(ArgNode); - } + for (CallSite::arg_iterator I = CS.arg_begin(), E = CS.arg_end(); + I != E; ++I) + if (isa((*I)->getType())) { + DSNodeHandle ArgNode = getValueDest(*I); + if (I - CS.arg_begin() < NumFixedArgs) { + Args.push_back(ArgNode); + } else { + VarArgNH.mergeWith(ArgNode); } - } + } // Add a new function call entry... if (CalleeNode) { From aggarwa4 at illinois.edu Tue Sep 7 23:08:25 2010 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Wed, 08 Sep 2010 04:08:25 -0000 Subject: [llvm-commits] [poolalloc] r113340 - in /poolalloc/trunk/test/dsa/var_arg: basic_32.ll basic_64.ll Message-ID: <20100908040825.3D0A42A6C12C@llvm.org> Author: aggarwa4 Date: Tue Sep 7 23:08:25 2010 New Revision: 113340 URL: http://llvm.org/viewvc/llvm-project?rev=113340&view=rev Log: Fixed syntax for type testing Modified: poolalloc/trunk/test/dsa/var_arg/basic_32.ll poolalloc/trunk/test/dsa/var_arg/basic_64.ll Modified: poolalloc/trunk/test/dsa/var_arg/basic_32.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/var_arg/basic_32.ll?rev=113340&r1=113339&r2=113340&view=diff ============================================================================== --- poolalloc/trunk/test/dsa/var_arg/basic_32.ll (original) +++ poolalloc/trunk/test/dsa/var_arg/basic_32.ll Tue Sep 7 23:08:25 2010 @@ -12,9 +12,9 @@ ; Don't propagate the VAStart flag to children... ;RUN: dsaopt %s -dsa-local -analyze -verify-flags "get:ap:0-V" ; On 32-bit, VAStart node should point to an array of the arguments -;RUN: dsaopt %s -dsa-local -analyze -check-type "get:ap:0,FoldedVOIDArray" +;RUN: dsaopt %s -dsa-local -analyze -check-type=get:ap:0,FoldedVOIDArray ; And the argument node should be of the proper type (in this case an i32) -;RUN: dsaopt %s -dsa-local -analyze -check-type "get:ap:0:0,0:i32" +;RUN: dsaopt %s -dsa-local -analyze -check-type=get:ap:0:0,0:i32 ; The argument should be ref'd, but not mod'd ;RUN: dsaopt %s -dsa-local -analyze --verify-flags "get:ap:0:0+R-M" Modified: poolalloc/trunk/test/dsa/var_arg/basic_64.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/var_arg/basic_64.ll?rev=113340&r1=113339&r2=113340&view=diff ============================================================================== --- poolalloc/trunk/test/dsa/var_arg/basic_64.ll (original) +++ poolalloc/trunk/test/dsa/var_arg/basic_64.ll Tue Sep 7 23:08:25 2010 @@ -13,13 +13,13 @@ ;RUN: dsaopt %s -dsa-local -analyze -verify-flags "get:ap:8-V" ;RUN: dsaopt %s -dsa-local -analyze -verify-flags "get:ap:16-V" ; On 64-bit, VAStart node should be a struct pointing to an array of the arguments -;RUN: dsaopt %s -dsa-local -analyze -check-type "get:ap:8,FoldedVOIDArray" +;RUN: dsaopt %s -dsa-local -analyze -check-type=get:ap:8,FoldedVOIDArray ; Both offsets 8 and 16 point to the array as a simplification. ; Verify that these are indeed the same node. ;RUN: dsaopt %s -dsa-local -analyze -check-same-node \ ;RUN: "get:ap:8,get:ap:16" ; And the argument node should be of the proper type (in this case an i32) -;RUN: dsaopt %s -dsa-local -analyze -check-type "get:ap:8:0,0:i32" +;RUN: dsaopt %s -dsa-local -analyze -check-type=get:ap:8:0,0:i32 ; The argument should be ref'd, but not mod'd ;RUN: dsaopt %s -dsa-local -analyze --verify-flags "get:ap:8:0+R-M" From aggarwa4 at illinois.edu Tue Sep 7 23:09:15 2010 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Wed, 08 Sep 2010 04:09:15 -0000 Subject: [llvm-commits] [poolalloc] r113341 - /poolalloc/trunk/test/dsa/local/union.ll Message-ID: <20100908040915.A6AAE2A6C12C@llvm.org> Author: aggarwa4 Date: Tue Sep 7 23:09:15 2010 New Revision: 113341 URL: http://llvm.org/viewvc/llvm-project?rev=113341&view=rev Log: more tests Added: poolalloc/trunk/test/dsa/local/union.ll Added: poolalloc/trunk/test/dsa/local/union.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/local/union.ll?rev=113341&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/local/union.ll (added) +++ poolalloc/trunk/test/dsa/local/union.ll Tue Sep 7 23:09:15 2010 @@ -0,0 +1,59 @@ +; ModuleID = 'union.bc' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" + +;RUN: dsaopt %s -dsa-local -analyze -check-same-node=func:tmp:0,func:c:0,func:s1:0 +;RUN: dsaopt %s -dsa-local -analyze -check-same-node=func:s1:8,func:x:8 + +%struct.StructType = type { float, i32* } +%union.UnionType = type { %struct.StructType, [96 x i32] } + +define void @func() nounwind { +entry: + %tmp = alloca i32* ; [#uses=2] + %s1 = alloca %union.UnionType ; <%union.UnionType*> [#uses=5] + %c = alloca i32* ; [#uses=1] + %d = alloca i32 ; [#uses=1] + %arr = alloca i32 ; [#uses=1] + %x = alloca %struct.StructType ; <%struct.StructType*> [#uses=3] + %y = alloca float ; [#uses=1] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + %0 = call noalias i8* @malloc(i64 4) nounwind ; [#uses=1] + %1 = bitcast i8* %0 to i32* ; [#uses=1] + store i32* %1, i32** %tmp, align 8 + %2 = getelementptr inbounds %union.UnionType* %s1, i32 0, i32 0 ; <%struct.StructType*> [#uses=1] + %3 = bitcast %struct.StructType* %2 to i32** ; [#uses=1] + %4 = load i32** %tmp, align 8 ; [#uses=1] + store i32* %4, i32** %3, align 8 + %5 = getelementptr inbounds %union.UnionType* %s1, i32 0, i32 0 ; <%struct.StructType*> [#uses=1] + %6 = bitcast %struct.StructType* %5 to i32** ; [#uses=1] + %7 = load i32** %6, align 8 ; [#uses=1] + store i32* %7, i32** %c, align 8 + %8 = getelementptr inbounds %union.UnionType* %s1, i32 0, i32 0 ; <%struct.StructType*> [#uses=1] + %9 = bitcast %struct.StructType* %8 to i32* ; [#uses=1] + %10 = load i32* %9, align 8 ; [#uses=1] + store i32 %10, i32* %d, align 4 + %11 = getelementptr inbounds %union.UnionType* %s1, i32 0, i32 0 ; <%struct.StructType*> [#uses=1] + %12 = bitcast %struct.StructType* %11 to [100 x i32]* ; <[100 x i32]*> [#uses=1] + %13 = getelementptr inbounds [100 x i32]* %12, i64 0, i64 0 ; [#uses=1] + %14 = load i32* %13, align 4 ; [#uses=1] + store i32 %14, i32* %arr, align 4 + %15 = getelementptr inbounds %union.UnionType* %s1, i32 0, i32 0 ; <%struct.StructType*> [#uses=2] + %16 = getelementptr inbounds %struct.StructType* %x, i32 0, i32 0 ; [#uses=1] + %17 = getelementptr inbounds %struct.StructType* %15, i32 0, i32 0 ; [#uses=1] + %18 = load float* %17, align 8 ; [#uses=1] + store float %18, float* %16, align 8 + %19 = getelementptr inbounds %struct.StructType* %x, i32 0, i32 1 ; [#uses=1] + %20 = getelementptr inbounds %struct.StructType* %15, i32 0, i32 1 ; [#uses=1] + %21 = load i32** %20, align 8 ; [#uses=1] + store i32* %21, i32** %19, align 8 + %22 = getelementptr inbounds %struct.StructType* %x, i32 0, i32 0 ; [#uses=1] + %23 = load float* %22, align 8 ; [#uses=1] + store float %23, float* %y, align 4 + br label %return + +return: ; preds = %entry + ret void +} + +declare noalias i8* @malloc(i64) nounwind From aggarwa4 at illinois.edu Tue Sep 7 23:09:46 2010 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Wed, 08 Sep 2010 04:09:46 -0000 Subject: [llvm-commits] [poolalloc] r113342 - in /poolalloc/trunk/test/dsa/types: ./ union.c union.ll union1.c union1.ll union2.c union2.ll union3.c union3.ll union4.c union4.ll union_arrays.c union_arrays.ll Message-ID: <20100908040946.4BE672A6C12C@llvm.org> Author: aggarwa4 Date: Tue Sep 7 23:09:46 2010 New Revision: 113342 URL: http://llvm.org/viewvc/llvm-project?rev=113342&view=rev Log: test for types Added: poolalloc/trunk/test/dsa/types/ poolalloc/trunk/test/dsa/types/union.c poolalloc/trunk/test/dsa/types/union.ll poolalloc/trunk/test/dsa/types/union1.c poolalloc/trunk/test/dsa/types/union1.ll poolalloc/trunk/test/dsa/types/union2.c poolalloc/trunk/test/dsa/types/union2.ll poolalloc/trunk/test/dsa/types/union3.c poolalloc/trunk/test/dsa/types/union3.ll poolalloc/trunk/test/dsa/types/union4.c poolalloc/trunk/test/dsa/types/union4.ll poolalloc/trunk/test/dsa/types/union_arrays.c poolalloc/trunk/test/dsa/types/union_arrays.ll Added: poolalloc/trunk/test/dsa/types/union.c URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/types/union.c?rev=113342&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/types/union.c (added) +++ poolalloc/trunk/test/dsa/types/union.c Tue Sep 7 23:09:46 2010 @@ -0,0 +1,35 @@ + +//--Make sure we can run DSA on it! +//RUN: llvm-gcc %s -c --emit-llvm -o - | \ +//RUN: dsaopt -dsa-bu -dsa-td -disable-output + + +#include +struct StructType { + + float a; + int *b; +}; +union UnionType { + + int a; + int *b; + int c[100]; + struct StructType obj; + +}; + +void func() { + + int *tmp = (int*) malloc(sizeof(int)); + union UnionType s1; + + s1.b = tmp; + + int *c = s1.b; + int d = s1.a; + int arr = s1.c[0]; + struct StructType x = s1.obj; + float y = x.a; +} + Added: poolalloc/trunk/test/dsa/types/union.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/types/union.ll?rev=113342&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/types/union.ll (added) +++ poolalloc/trunk/test/dsa/types/union.ll Tue Sep 7 23:09:46 2010 @@ -0,0 +1,61 @@ +; ModuleID = 'union.bc' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" + +;RUN: dsaopt %s -dsa-local -analyze -check-same-node=func:tmp:0,func:c:0,func:s1:0 +;RUN: dsaopt %s -dsa-local -analyze -check-same-node=func:s1:8,func:x:8 +;RUN: dsaopt %s -dsa-local -analyze -check-type=func:s1,0:float|i32|i32*::8:i32* +;RUN: dsaopt %s -dsa-local -analyze -check-type=func:x,0:float::8:i32* + +%struct.StructType = type { float, i32* } +%union.UnionType = type { %struct.StructType, [96 x i32] } + +define void @func() nounwind { +entry: + %tmp = alloca i32* ; [#uses=2] + %s1 = alloca %union.UnionType ; <%union.UnionType*> [#uses=5] + %c = alloca i32* ; [#uses=1] + %d = alloca i32 ; [#uses=1] + %arr = alloca i32 ; [#uses=1] + %x = alloca %struct.StructType ; <%struct.StructType*> [#uses=3] + %y = alloca float ; [#uses=1] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + %0 = call noalias i8* @malloc(i64 4) nounwind ; [#uses=1] + %1 = bitcast i8* %0 to i32* ; [#uses=1] + store i32* %1, i32** %tmp, align 8 + %2 = getelementptr inbounds %union.UnionType* %s1, i32 0, i32 0 ; <%struct.StructType*> [#uses=1] + %3 = bitcast %struct.StructType* %2 to i32** ; [#uses=1] + %4 = load i32** %tmp, align 8 ; [#uses=1] + store i32* %4, i32** %3, align 8 + %5 = getelementptr inbounds %union.UnionType* %s1, i32 0, i32 0 ; <%struct.StructType*> [#uses=1] + %6 = bitcast %struct.StructType* %5 to i32** ; [#uses=1] + %7 = load i32** %6, align 8 ; [#uses=1] + store i32* %7, i32** %c, align 8 + %8 = getelementptr inbounds %union.UnionType* %s1, i32 0, i32 0 ; <%struct.StructType*> [#uses=1] + %9 = bitcast %struct.StructType* %8 to i32* ; [#uses=1] + %10 = load i32* %9, align 8 ; [#uses=1] + store i32 %10, i32* %d, align 4 + %11 = getelementptr inbounds %union.UnionType* %s1, i32 0, i32 0 ; <%struct.StructType*> [#uses=1] + %12 = bitcast %struct.StructType* %11 to [100 x i32]* ; <[100 x i32]*> [#uses=1] + %13 = getelementptr inbounds [100 x i32]* %12, i64 0, i64 0 ; [#uses=1] + %14 = load i32* %13, align 4 ; [#uses=1] + store i32 %14, i32* %arr, align 4 + %15 = getelementptr inbounds %union.UnionType* %s1, i32 0, i32 0 ; <%struct.StructType*> [#uses=2] + %16 = getelementptr inbounds %struct.StructType* %x, i32 0, i32 0 ; [#uses=1] + %17 = getelementptr inbounds %struct.StructType* %15, i32 0, i32 0 ; [#uses=1] + %18 = load float* %17, align 8 ; [#uses=1] + store float %18, float* %16, align 8 + %19 = getelementptr inbounds %struct.StructType* %x, i32 0, i32 1 ; [#uses=1] + %20 = getelementptr inbounds %struct.StructType* %15, i32 0, i32 1 ; [#uses=1] + %21 = load i32** %20, align 8 ; [#uses=1] + store i32* %21, i32** %19, align 8 + %22 = getelementptr inbounds %struct.StructType* %x, i32 0, i32 0 ; [#uses=1] + %23 = load float* %22, align 8 ; [#uses=1] + store float %23, float* %y, align 4 + br label %return + +return: ; preds = %entry + ret void +} + +declare noalias i8* @malloc(i64) nounwind Added: poolalloc/trunk/test/dsa/types/union1.c URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/types/union1.c?rev=113342&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/types/union1.c (added) +++ poolalloc/trunk/test/dsa/types/union1.c Tue Sep 7 23:09:46 2010 @@ -0,0 +1,41 @@ + +//--Make sure we can run DSA on it! +//RUN: llvm-gcc %s -c --emit-llvm -o - | \ +//RUN: dsaopt -dsa-bu -dsa-td -disable-output + + +#include +struct NestedStructType { + + float a1; + int *b1; +}; +struct StructType { + + float a2; + int *b2; + struct NestedStructType ns2; +}; +union UnionType { + + int a; + int *b; + int c[100]; + struct StructType obj; + +}; + +void func() { + + int *tmp = (int*) malloc(sizeof(int)); + union UnionType s1; + + s1.b = tmp; + + int *c = s1.b; + int d = s1.a; + int arr = s1.c[0]; + struct StructType x = s1.obj; + float y = x.a2; +} + Added: poolalloc/trunk/test/dsa/types/union1.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/types/union1.ll?rev=113342&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/types/union1.ll (added) +++ poolalloc/trunk/test/dsa/types/union1.ll Tue Sep 7 23:09:46 2010 @@ -0,0 +1,67 @@ +; ModuleID = 'union1.bc' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" + +%struct.NestedStructType = type { float, i32* } +%struct.StructType = type { float, i32*, %struct.NestedStructType } +%union.UnionType = type { %struct.StructType, [92 x i32] } + +define void @func() nounwind { +entry: + %tmp = alloca i32* ; [#uses=2] + %s1 = alloca %union.UnionType ; <%union.UnionType*> [#uses=5] + %c = alloca i32* ; [#uses=1] + %d = alloca i32 ; [#uses=1] + %arr = alloca i32 ; [#uses=1] + %x = alloca %struct.StructType ; <%struct.StructType*> [#uses=4] + %y = alloca float ; [#uses=1] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + %0 = call noalias i8* @malloc(i64 4) nounwind ; [#uses=1] + %1 = bitcast i8* %0 to i32* ; [#uses=1] + store i32* %1, i32** %tmp, align 8 + %2 = getelementptr inbounds %union.UnionType* %s1, i32 0, i32 0 ; <%struct.StructType*> [#uses=1] + %3 = bitcast %struct.StructType* %2 to i32** ; [#uses=1] + %4 = load i32** %tmp, align 8 ; [#uses=1] + store i32* %4, i32** %3, align 8 + %5 = getelementptr inbounds %union.UnionType* %s1, i32 0, i32 0 ; <%struct.StructType*> [#uses=1] + %6 = bitcast %struct.StructType* %5 to i32** ; [#uses=1] + %7 = load i32** %6, align 8 ; [#uses=1] + store i32* %7, i32** %c, align 8 + %8 = getelementptr inbounds %union.UnionType* %s1, i32 0, i32 0 ; <%struct.StructType*> [#uses=1] + %9 = bitcast %struct.StructType* %8 to i32* ; [#uses=1] + %10 = load i32* %9, align 8 ; [#uses=1] + store i32 %10, i32* %d, align 4 + %11 = getelementptr inbounds %union.UnionType* %s1, i32 0, i32 0 ; <%struct.StructType*> [#uses=1] + %12 = bitcast %struct.StructType* %11 to [100 x i32]* ; <[100 x i32]*> [#uses=1] + %13 = getelementptr inbounds [100 x i32]* %12, i64 0, i64 0 ; [#uses=1] + %14 = load i32* %13, align 4 ; [#uses=1] + store i32 %14, i32* %arr, align 4 + %15 = getelementptr inbounds %union.UnionType* %s1, i32 0, i32 0 ; <%struct.StructType*> [#uses=3] + %16 = getelementptr inbounds %struct.StructType* %x, i32 0, i32 0 ; [#uses=1] + %17 = getelementptr inbounds %struct.StructType* %15, i32 0, i32 0 ; [#uses=1] + %18 = load float* %17, align 8 ; [#uses=1] + store float %18, float* %16, align 8 + %19 = getelementptr inbounds %struct.StructType* %x, i32 0, i32 1 ; [#uses=1] + %20 = getelementptr inbounds %struct.StructType* %15, i32 0, i32 1 ; [#uses=1] + %21 = load i32** %20, align 8 ; [#uses=1] + store i32* %21, i32** %19, align 8 + %22 = getelementptr inbounds %struct.StructType* %x, i32 0, i32 2 ; <%struct.NestedStructType*> [#uses=2] + %23 = getelementptr inbounds %struct.StructType* %15, i32 0, i32 2 ; <%struct.NestedStructType*> [#uses=2] + %24 = getelementptr inbounds %struct.NestedStructType* %22, i32 0, i32 0 ; [#uses=1] + %25 = getelementptr inbounds %struct.NestedStructType* %23, i32 0, i32 0 ; [#uses=1] + %26 = load float* %25, align 8 ; [#uses=1] + store float %26, float* %24, align 8 + %27 = getelementptr inbounds %struct.NestedStructType* %22, i32 0, i32 1 ; [#uses=1] + %28 = getelementptr inbounds %struct.NestedStructType* %23, i32 0, i32 1 ; [#uses=1] + %29 = load i32** %28, align 8 ; [#uses=1] + store i32* %29, i32** %27, align 8 + %30 = getelementptr inbounds %struct.StructType* %x, i32 0, i32 0 ; [#uses=1] + %31 = load float* %30, align 8 ; [#uses=1] + store float %31, float* %y, align 4 + br label %return + +return: ; preds = %entry + ret void +} + +declare noalias i8* @malloc(i64) nounwind Added: poolalloc/trunk/test/dsa/types/union2.c URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/types/union2.c?rev=113342&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/types/union2.c (added) +++ poolalloc/trunk/test/dsa/types/union2.c Tue Sep 7 23:09:46 2010 @@ -0,0 +1,39 @@ + +//--Make sure we can run DSA on it! +//RUN: llvm-gcc %s -c --emit-llvm -o - | \ +//RUN: dsaopt -dsa-bu -dsa-td -disable-output + + +#include +struct StructType1 { + + int a1; + int b1; + int c1; +}; +struct StructType2 { + + int a2; + short b2; + int c2; +}; + +union UnionType { + struct StructType1 s1; + struct StructType2 s2; +}; + +void func() { + + union UnionType obj; + + obj.s1.a1 = 2l; + obj.s1.b1 = 33; + obj.s1.c1 = 22; + + struct StructType2 s = obj.s2; + + int t = obj.s2.c2; + int t1 = obj.s1.c1; +} + Added: poolalloc/trunk/test/dsa/types/union2.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/types/union2.ll?rev=113342&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/types/union2.ll (added) +++ poolalloc/trunk/test/dsa/types/union2.ll Tue Sep 7 23:09:46 2010 @@ -0,0 +1,52 @@ +; ModuleID = 'union2.bc' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" + +%struct.StructType1 = type { i32, i32, i32 } +%struct.StructType2 = type { i32, i16, i32 } +%union.UnionType = type { %struct.StructType1 } + +define void @func() nounwind { +entry: + %obj = alloca %union.UnionType ; <%union.UnionType*> [#uses=6] + %s = alloca %struct.StructType2 ; <%struct.StructType2*> [#uses=3] + %t = alloca i32 ; [#uses=1] + %t1 = alloca i32 ; [#uses=1] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + %0 = getelementptr inbounds %union.UnionType* %obj, i32 0, i32 0 ; <%struct.StructType1*> [#uses=1] + %1 = getelementptr inbounds %struct.StructType1* %0, i32 0, i32 0 ; [#uses=1] + store i32 2, i32* %1, align 4 + %2 = getelementptr inbounds %union.UnionType* %obj, i32 0, i32 0 ; <%struct.StructType1*> [#uses=1] + %3 = getelementptr inbounds %struct.StructType1* %2, i32 0, i32 1 ; [#uses=1] + store i32 33, i32* %3, align 4 + %4 = getelementptr inbounds %union.UnionType* %obj, i32 0, i32 0 ; <%struct.StructType1*> [#uses=1] + %5 = getelementptr inbounds %struct.StructType1* %4, i32 0, i32 2 ; [#uses=1] + store i32 22, i32* %5, align 4 + %6 = getelementptr inbounds %union.UnionType* %obj, i32 0, i32 0 ; <%struct.StructType1*> [#uses=1] + %7 = bitcast %struct.StructType1* %6 to %struct.StructType2* ; <%struct.StructType2*> [#uses=3] + %8 = getelementptr inbounds %struct.StructType2* %s, i32 0, i32 0 ; [#uses=1] + %9 = getelementptr inbounds %struct.StructType2* %7, i32 0, i32 0 ; [#uses=1] + %10 = load i32* %9, align 4 ; [#uses=1] + store i32 %10, i32* %8, align 4 + %11 = getelementptr inbounds %struct.StructType2* %s, i32 0, i32 1 ; [#uses=1] + %12 = getelementptr inbounds %struct.StructType2* %7, i32 0, i32 1 ; [#uses=1] + %13 = load i16* %12, align 4 ; [#uses=1] + store i16 %13, i16* %11, align 4 + %14 = getelementptr inbounds %struct.StructType2* %s, i32 0, i32 2 ; [#uses=1] + %15 = getelementptr inbounds %struct.StructType2* %7, i32 0, i32 2 ; [#uses=1] + %16 = load i32* %15, align 4 ; [#uses=1] + store i32 %16, i32* %14, align 4 + %17 = getelementptr inbounds %union.UnionType* %obj, i32 0, i32 0 ; <%struct.StructType1*> [#uses=1] + %18 = bitcast %struct.StructType1* %17 to %struct.StructType2* ; <%struct.StructType2*> [#uses=1] + %19 = getelementptr inbounds %struct.StructType2* %18, i32 0, i32 2 ; [#uses=1] + %20 = load i32* %19, align 4 ; [#uses=1] + store i32 %20, i32* %t, align 4 + %21 = getelementptr inbounds %union.UnionType* %obj, i32 0, i32 0 ; <%struct.StructType1*> [#uses=1] + %22 = getelementptr inbounds %struct.StructType1* %21, i32 0, i32 2 ; [#uses=1] + %23 = load i32* %22, align 4 ; [#uses=1] + store i32 %23, i32* %t1, align 4 + br label %return + +return: ; preds = %entry + ret void +} Added: poolalloc/trunk/test/dsa/types/union3.c URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/types/union3.c?rev=113342&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/types/union3.c (added) +++ poolalloc/trunk/test/dsa/types/union3.c Tue Sep 7 23:09:46 2010 @@ -0,0 +1,37 @@ + +//--Make sure we can run DSA on it! +//RUN: llvm-gcc %s -c --emit-llvm -o - | \ +//RUN: dsaopt -dsa-bu -dsa-td -disable-output + + +#include +struct StructType1 { + + int a1; + int b1; + int c1; +}; +struct StructType2 { + + int a2; + short b2; + short c3; + int c2; +}; + +union UnionType { + struct StructType1 s1; + struct StructType2 s2; +}; + +void func() { + + union UnionType obj; + + obj.s1.a1 = 2l; + obj.s1.b1 = 33; + obj.s1.c1 = 22; + + struct StructType2 s = obj.s2; +} + Added: poolalloc/trunk/test/dsa/types/union3.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/types/union3.ll?rev=113342&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/types/union3.ll (added) +++ poolalloc/trunk/test/dsa/types/union3.ll Tue Sep 7 23:09:46 2010 @@ -0,0 +1,45 @@ +; ModuleID = 'union3.bc' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" + +%struct.StructType1 = type { i32, i32, i32 } +%struct.StructType2 = type { i32, i16, i16, i32 } +%union.UnionType = type { %struct.StructType1 } + +define void @func() nounwind { +entry: + %obj = alloca %union.UnionType ; <%union.UnionType*> [#uses=4] + %s = alloca %struct.StructType2 ; <%struct.StructType2*> [#uses=4] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + %0 = getelementptr inbounds %union.UnionType* %obj, i32 0, i32 0 ; <%struct.StructType1*> [#uses=1] + %1 = getelementptr inbounds %struct.StructType1* %0, i32 0, i32 0 ; [#uses=1] + store i32 2, i32* %1, align 4 + %2 = getelementptr inbounds %union.UnionType* %obj, i32 0, i32 0 ; <%struct.StructType1*> [#uses=1] + %3 = getelementptr inbounds %struct.StructType1* %2, i32 0, i32 1 ; [#uses=1] + store i32 33, i32* %3, align 4 + %4 = getelementptr inbounds %union.UnionType* %obj, i32 0, i32 0 ; <%struct.StructType1*> [#uses=1] + %5 = getelementptr inbounds %struct.StructType1* %4, i32 0, i32 2 ; [#uses=1] + store i32 22, i32* %5, align 4 + %6 = getelementptr inbounds %union.UnionType* %obj, i32 0, i32 0 ; <%struct.StructType1*> [#uses=1] + %7 = bitcast %struct.StructType1* %6 to %struct.StructType2* ; <%struct.StructType2*> [#uses=4] + %8 = getelementptr inbounds %struct.StructType2* %s, i32 0, i32 0 ; [#uses=1] + %9 = getelementptr inbounds %struct.StructType2* %7, i32 0, i32 0 ; [#uses=1] + %10 = load i32* %9, align 4 ; [#uses=1] + store i32 %10, i32* %8, align 4 + %11 = getelementptr inbounds %struct.StructType2* %s, i32 0, i32 1 ; [#uses=1] + %12 = getelementptr inbounds %struct.StructType2* %7, i32 0, i32 1 ; [#uses=1] + %13 = load i16* %12, align 4 ; [#uses=1] + store i16 %13, i16* %11, align 4 + %14 = getelementptr inbounds %struct.StructType2* %s, i32 0, i32 2 ; [#uses=1] + %15 = getelementptr inbounds %struct.StructType2* %7, i32 0, i32 2 ; [#uses=1] + %16 = load i16* %15, align 2 ; [#uses=1] + store i16 %16, i16* %14, align 2 + %17 = getelementptr inbounds %struct.StructType2* %s, i32 0, i32 3 ; [#uses=1] + %18 = getelementptr inbounds %struct.StructType2* %7, i32 0, i32 3 ; [#uses=1] + %19 = load i32* %18, align 4 ; [#uses=1] + store i32 %19, i32* %17, align 4 + br label %return + +return: ; preds = %entry + ret void +} Added: poolalloc/trunk/test/dsa/types/union4.c URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/types/union4.c?rev=113342&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/types/union4.c (added) +++ poolalloc/trunk/test/dsa/types/union4.c Tue Sep 7 23:09:46 2010 @@ -0,0 +1,38 @@ + +//--Make sure we can run DSA on it! +//RUN: llvm-gcc %s -c --emit-llvm -o - | \ +//RUN: dsaopt -dsa-bu -dsa-td -disable-output + + +#include +struct StructType1 { + + int a1; + int b1; + int c1; +}; +struct StructType2 { + + int a2; + short b2; + short c3; + int c2; +}; + +union UnionType { + struct StructType1 s1; + struct StructType2 s2; +}; + +void func() { + + union UnionType obj; + + obj.s1.a1 = 2l; + obj.s1.b1 = 33; + obj.s1.c1 = 22; + + short x = obj.s2.b2; + short y = obj.s2.c3; +} + Added: poolalloc/trunk/test/dsa/types/union4.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/types/union4.ll?rev=113342&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/types/union4.ll (added) +++ poolalloc/trunk/test/dsa/types/union4.ll Tue Sep 7 23:09:46 2010 @@ -0,0 +1,38 @@ +; ModuleID = 'union4.bc' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" + +%struct.StructType1 = type { i32, i32, i32 } +%struct.StructType2 = type { i32, i16, i16, i32 } +%union.UnionType = type { %struct.StructType1 } + +define void @func() nounwind { +entry: + %obj = alloca %union.UnionType ; <%union.UnionType*> [#uses=5] + %x = alloca i16 ; [#uses=1] + %y = alloca i16 ; [#uses=1] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + %0 = getelementptr inbounds %union.UnionType* %obj, i32 0, i32 0 ; <%struct.StructType1*> [#uses=1] + %1 = getelementptr inbounds %struct.StructType1* %0, i32 0, i32 0 ; [#uses=1] + store i32 2, i32* %1, align 4 + %2 = getelementptr inbounds %union.UnionType* %obj, i32 0, i32 0 ; <%struct.StructType1*> [#uses=1] + %3 = getelementptr inbounds %struct.StructType1* %2, i32 0, i32 1 ; [#uses=1] + store i32 33, i32* %3, align 4 + %4 = getelementptr inbounds %union.UnionType* %obj, i32 0, i32 0 ; <%struct.StructType1*> [#uses=1] + %5 = getelementptr inbounds %struct.StructType1* %4, i32 0, i32 2 ; [#uses=1] + store i32 22, i32* %5, align 4 + %6 = getelementptr inbounds %union.UnionType* %obj, i32 0, i32 0 ; <%struct.StructType1*> [#uses=1] + %7 = bitcast %struct.StructType1* %6 to %struct.StructType2* ; <%struct.StructType2*> [#uses=1] + %8 = getelementptr inbounds %struct.StructType2* %7, i32 0, i32 1 ; [#uses=1] + %9 = load i16* %8, align 4 ; [#uses=1] + store i16 %9, i16* %x, align 2 + %10 = getelementptr inbounds %union.UnionType* %obj, i32 0, i32 0 ; <%struct.StructType1*> [#uses=1] + %11 = bitcast %struct.StructType1* %10 to %struct.StructType2* ; <%struct.StructType2*> [#uses=1] + %12 = getelementptr inbounds %struct.StructType2* %11, i32 0, i32 2 ; [#uses=1] + %13 = load i16* %12, align 2 ; [#uses=1] + store i16 %13, i16* %y, align 2 + br label %return + +return: ; preds = %entry + ret void +} Added: poolalloc/trunk/test/dsa/types/union_arrays.c URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/types/union_arrays.c?rev=113342&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/types/union_arrays.c (added) +++ poolalloc/trunk/test/dsa/types/union_arrays.c Tue Sep 7 23:09:46 2010 @@ -0,0 +1,39 @@ + +//--Make sure we can run DSA on it! +//RUN: llvm-gcc %s -c --emit-llvm -o - | \ +//RUN: dsaopt -dsa-bu -dsa-td -disable-output + + +#include +struct StructType1 { + int a1[10]; + short b1[10]; + int c1[10]; +}; +struct StructType2 { + int a2[10]; + int b2[10]; + int c2[10]; +}; +union UnionType { + struct StructType1 s1; + struct StructType2 s2; +}; + +void func() { + + union UnionType obj; + union UnionType obj_copy; + int i; + for(i=0;i<10;i++) { + obj.s1.a1[i] = i + 10; + obj.s1.b1[i] = i + 32; + obj.s1.c1[i] = i + 64; + } + for(i=0;i<10;i++) { + obj_copy.s2.a2[i] = obj.s1.a1[i]; + obj_copy.s2.b2[i] = obj.s1.b1[i]; + obj_copy.s2.c2[i] = obj.s1.c1[i]; + } +} + Added: poolalloc/trunk/test/dsa/types/union_arrays.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/types/union_arrays.ll?rev=113342&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/types/union_arrays.ll (added) +++ poolalloc/trunk/test/dsa/types/union_arrays.ll Tue Sep 7 23:09:46 2010 @@ -0,0 +1,117 @@ +; ModuleID = 'union_arrays.bc' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" + +%struct.StructType1 = type { [10 x i32], [10 x i16], [10 x i32] } +%struct.StructType2 = type { [10 x i32], [10 x i32], [10 x i32] } +%union.UnionType = type { %struct.StructType2 } + +define void @func() nounwind { +entry: + %obj = alloca %union.UnionType ; <%union.UnionType*> [#uses=6] + %obj_copy = alloca %union.UnionType ; <%union.UnionType*> [#uses=3] + %i = alloca i32 ; [#uses=20] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store i32 0, i32* %i, align 4 + br label %bb1 + +bb: ; preds = %bb1 + %0 = load i32* %i, align 4 ; [#uses=1] + %1 = load i32* %i, align 4 ; [#uses=1] + %2 = add nsw i32 %1, 10 ; [#uses=1] + %3 = getelementptr inbounds %union.UnionType* %obj, i32 0, i32 0 ; <%struct.StructType2*> [#uses=1] + %4 = bitcast %struct.StructType2* %3 to %struct.StructType1* ; <%struct.StructType1*> [#uses=1] + %5 = getelementptr inbounds %struct.StructType1* %4, i32 0, i32 0 ; <[10 x i32]*> [#uses=1] + %6 = sext i32 %0 to i64 ; [#uses=1] + %7 = getelementptr inbounds [10 x i32]* %5, i64 0, i64 %6 ; [#uses=1] + store i32 %2, i32* %7, align 4 + %8 = load i32* %i, align 4 ; [#uses=1] + %9 = load i32* %i, align 4 ; [#uses=1] + %10 = trunc i32 %9 to i16 ; [#uses=1] + %11 = add i16 %10, 32 ; [#uses=1] + %12 = getelementptr inbounds %union.UnionType* %obj, i32 0, i32 0 ; <%struct.StructType2*> [#uses=1] + %13 = bitcast %struct.StructType2* %12 to %struct.StructType1* ; <%struct.StructType1*> [#uses=1] + %14 = getelementptr inbounds %struct.StructType1* %13, i32 0, i32 1 ; <[10 x i16]*> [#uses=1] + %15 = sext i32 %8 to i64 ; [#uses=1] + %16 = getelementptr inbounds [10 x i16]* %14, i64 0, i64 %15 ; [#uses=1] + store i16 %11, i16* %16, align 2 + %17 = load i32* %i, align 4 ; [#uses=1] + %18 = load i32* %i, align 4 ; [#uses=1] + %19 = add nsw i32 %18, 64 ; [#uses=1] + %20 = getelementptr inbounds %union.UnionType* %obj, i32 0, i32 0 ; <%struct.StructType2*> [#uses=1] + %21 = bitcast %struct.StructType2* %20 to %struct.StructType1* ; <%struct.StructType1*> [#uses=1] + %22 = getelementptr inbounds %struct.StructType1* %21, i32 0, i32 2 ; <[10 x i32]*> [#uses=1] + %23 = sext i32 %17 to i64 ; [#uses=1] + %24 = getelementptr inbounds [10 x i32]* %22, i64 0, i64 %23 ; [#uses=1] + store i32 %19, i32* %24, align 4 + %25 = load i32* %i, align 4 ; [#uses=1] + %26 = add nsw i32 %25, 1 ; [#uses=1] + store i32 %26, i32* %i, align 4 + br label %bb1 + +bb1: ; preds = %bb, %entry + %27 = load i32* %i, align 4 ; [#uses=1] + %28 = icmp sle i32 %27, 9 ; [#uses=1] + br i1 %28, label %bb, label %bb2 + +bb2: ; preds = %bb1 + store i32 0, i32* %i, align 4 + br label %bb4 + +bb3: ; preds = %bb4 + %29 = load i32* %i, align 4 ; [#uses=1] + %30 = load i32* %i, align 4 ; [#uses=1] + %31 = getelementptr inbounds %union.UnionType* %obj, i32 0, i32 0 ; <%struct.StructType2*> [#uses=1] + %32 = bitcast %struct.StructType2* %31 to %struct.StructType1* ; <%struct.StructType1*> [#uses=1] + %33 = getelementptr inbounds %struct.StructType1* %32, i32 0, i32 0 ; <[10 x i32]*> [#uses=1] + %34 = sext i32 %30 to i64 ; [#uses=1] + %35 = getelementptr inbounds [10 x i32]* %33, i64 0, i64 %34 ; [#uses=1] + %36 = load i32* %35, align 4 ; [#uses=1] + %37 = getelementptr inbounds %union.UnionType* %obj_copy, i32 0, i32 0 ; <%struct.StructType2*> [#uses=1] + %38 = getelementptr inbounds %struct.StructType2* %37, i32 0, i32 0 ; <[10 x i32]*> [#uses=1] + %39 = sext i32 %29 to i64 ; [#uses=1] + %40 = getelementptr inbounds [10 x i32]* %38, i64 0, i64 %39 ; [#uses=1] + store i32 %36, i32* %40, align 4 + %41 = load i32* %i, align 4 ; [#uses=1] + %42 = load i32* %i, align 4 ; [#uses=1] + %43 = getelementptr inbounds %union.UnionType* %obj, i32 0, i32 0 ; <%struct.StructType2*> [#uses=1] + %44 = bitcast %struct.StructType2* %43 to %struct.StructType1* ; <%struct.StructType1*> [#uses=1] + %45 = getelementptr inbounds %struct.StructType1* %44, i32 0, i32 1 ; <[10 x i16]*> [#uses=1] + %46 = sext i32 %42 to i64 ; [#uses=1] + %47 = getelementptr inbounds [10 x i16]* %45, i64 0, i64 %46 ; [#uses=1] + %48 = load i16* %47, align 2 ; [#uses=1] + %49 = sext i16 %48 to i32 ; [#uses=1] + %50 = getelementptr inbounds %union.UnionType* %obj_copy, i32 0, i32 0 ; <%struct.StructType2*> [#uses=1] + %51 = getelementptr inbounds %struct.StructType2* %50, i32 0, i32 1 ; <[10 x i32]*> [#uses=1] + %52 = sext i32 %41 to i64 ; [#uses=1] + %53 = getelementptr inbounds [10 x i32]* %51, i64 0, i64 %52 ; [#uses=1] + store i32 %49, i32* %53, align 4 + %54 = load i32* %i, align 4 ; [#uses=1] + %55 = load i32* %i, align 4 ; [#uses=1] + %56 = getelementptr inbounds %union.UnionType* %obj, i32 0, i32 0 ; <%struct.StructType2*> [#uses=1] + %57 = bitcast %struct.StructType2* %56 to %struct.StructType1* ; <%struct.StructType1*> [#uses=1] + %58 = getelementptr inbounds %struct.StructType1* %57, i32 0, i32 2 ; <[10 x i32]*> [#uses=1] + %59 = sext i32 %55 to i64 ; [#uses=1] + %60 = getelementptr inbounds [10 x i32]* %58, i64 0, i64 %59 ; [#uses=1] + %61 = load i32* %60, align 4 ; [#uses=1] + %62 = getelementptr inbounds %union.UnionType* %obj_copy, i32 0, i32 0 ; <%struct.StructType2*> [#uses=1] + %63 = getelementptr inbounds %struct.StructType2* %62, i32 0, i32 2 ; <[10 x i32]*> [#uses=1] + %64 = sext i32 %54 to i64 ; [#uses=1] + %65 = getelementptr inbounds [10 x i32]* %63, i64 0, i64 %64 ; [#uses=1] + store i32 %61, i32* %65, align 4 + %66 = load i32* %i, align 4 ; [#uses=1] + %67 = add nsw i32 %66, 1 ; [#uses=1] + store i32 %67, i32* %i, align 4 + br label %bb4 + +bb4: ; preds = %bb3, %bb2 + %68 = load i32* %i, align 4 ; [#uses=1] + %69 = icmp sle i32 %68, 9 ; [#uses=1] + br i1 %69, label %bb3, label %bb5 + +bb5: ; preds = %bb4 + br label %return + +return: ; preds = %bb5 + ret void +} From geek4civic at gmail.com Tue Sep 7 23:11:25 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Wed, 8 Sep 2010 13:11:25 +0900 Subject: [llvm-commits] [PATCH] Target/ARM build failure on Cygwin-1.5 In-Reply-To: <1B3650AC-0C27-42EF-B68B-77D6484BCD23@apple.com> References: <1B3650AC-0C27-42EF-B68B-77D6484BCD23@apple.com> Message-ID: Good afternoon, Chris. 2010/9/8 Chris Lattner : > Does r113255 fix the problem? No. It needs additional patches. Attached. Thank you, ...Takumi -------------- next part -------------- diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 14acf80..e220289 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -298,7 +298,7 @@ static unsigned T2Morph2LoadLiteral(unsigned Opcode) { /// decodeInstruction(insn) is invoked on the original insn. /// /// Otherwise, decodeThumbInstruction is called with the original insn. -static unsigned decodeThumbSideEffect(bool IsThumb2, uint32_t &insn) { +static unsigned decodeThumbSideEffect(bool IsThumb2, unsigned &insn) { if (IsThumb2) { uint16_t op1 = slice(insn, 28, 27); uint16_t op2 = slice(insn, 26, 20); @@ -436,7 +436,7 @@ bool ThumbDisassembler::getInstruction(MCInst &MI, // passed to decodeThumbInstruction(). For 16-bit Thumb instruction, the top // halfword of insn is 0x00 0x00; otherwise, the first halfword is moved to // the top half followed by the second halfword. - uint32_t insn = 0; + unsigned insn = 0; // Possible second halfword. uint16_t insn1 = 0; From clattner at apple.com Tue Sep 7 23:33:33 2010 From: clattner at apple.com (Chris Lattner) Date: Tue, 7 Sep 2010 21:33:33 -0700 Subject: [llvm-commits] [PATCH] Target/ARM build failure on Cygwin-1.5 In-Reply-To: References: <1B3650AC-0C27-42EF-B68B-77D6484BCD23@apple.com> Message-ID: Looks great to me, please apply. Should one or both of these be applied to the LLVM 2.8 branch? If so, please email the svn rev #'s to Bill Wendling. Thanks again, -Chris On Sep 7, 2010, at 9:11 PM, NAKAMURA Takumi wrote: > Good afternoon, Chris. > > 2010/9/8 Chris Lattner : >> Does r113255 fix the problem? > > No. It needs additional patches. Attached. > > Thank you, ...Takumi > From sabre at nondot.org Tue Sep 7 23:30:51 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 08 Sep 2010 04:30:51 -0000 Subject: [llvm-commits] [llvm] r113343 - in /llvm/trunk: lib/Target/X86/AsmParser/X86AsmParser.cpp lib/Target/X86/X86InstrInfo.td test/MC/AsmParser/X86/x86_32-new-encoder.s test/MC/AsmParser/X86/x86_64-new-encoder.s test/MC/MachO/jcc.s Message-ID: <20100908043051.76D572A6C12C@llvm.org> Author: lattner Date: Tue Sep 7 23:30:51 2010 New Revision: 113343 URL: http://llvm.org/viewvc/llvm-project?rev=113343&view=rev Log: fix the encoding of the "jump on *cx" family of instructions, rdar://8061602 Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.td llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s llvm/trunk/test/MC/MachO/jcc.s Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=113343&r1=113342&r2=113343&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Tue Sep 7 23:30:51 2010 @@ -615,15 +615,6 @@ bool X86ATTAsmParser:: ParseInstruction(StringRef Name, SMLoc NameLoc, SmallVectorImpl &Operands) { - - // The "Jump if rCX Zero" form jcxz is not allowed in 64-bit mode and - // the form jrcxz is not allowed in 32-bit mode. - if (Is64Bit) { - // FIXME: We can do jcxz/jecxz, we just don't have the encoding right yet. - if (Name == "jcxz" || Name == "jecxz") - return Error(NameLoc, Name + " cannot be encoded in 64-bit mode"); - } - // FIXME: Hack to recognize "sal..." and "rep..." for now. We need a way to // represent alternative syntaxes in the .td file, without requiring // instruction duplication. @@ -646,11 +637,6 @@ .Case("jz", "je") .Case("jnz", "jne") .Case("jc", "jb") - // FIXME: in 32-bit mode jcxz requires an AdSize prefix. In 64-bit mode - // jecxz requires an AdSize prefix but jecxz does not have a prefix in - // 32-bit mode. - .Case("jecxz", "jcxz") - .Case("jrcxz", Is64Bit ? "jcxz" : "jrcxz") .Case("jna", "jbe") .Case("jnae", "jb") .Case("jnb", "jae") Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=113343&r1=113342&r2=113343&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Tue Sep 7 23:30:51 2010 @@ -664,10 +664,28 @@ defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>; defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>; -// FIXME: What about the CX/RCX versions of this instruction? -let Uses = [ECX], isBranch = 1, isTerminator = 1 in - def JCXZ8 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst), - "jcxz\t$dst", []>; +// jcx/jecx/jrcx instructions. +let isAsmParserOnly = 1, isBranch = 1, isTerminator = 1 in { + // These are the 32-bit versions of this instruction for the asmparser. In + // 32-bit mode, the address size prefix is jcxz and the unprefixed version is + // jecxz. + let Uses = [CX] in + def JCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst), + "jcxz\t$dst", []>, AdSize, Requires<[In32BitMode]>; + let Uses = [ECX] in + def JECXZ_32 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst), + "jecxz\t$dst", []>, Requires<[In32BitMode]>; + + // J*CXZ instruction: 64-bit versions of this instruction for the asmparser. + // In 64-bit mode, the address size prefix is jecxz and the unprefixed version + // is jrcxz. + let Uses = [ECX] in + def JECXZ_64 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst), + "jecxz\t$dst", []>, AdSize, Requires<[In64BitMode]>; + let Uses = [RCX] in + def JRCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst), + "jrcxz\t$dst", []>, Requires<[In64BitMode]>; +} // Indirect branches Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s?rev=113343&r1=113342&r2=113343&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s Tue Sep 7 23:30:51 2010 @@ -423,3 +423,14 @@ // CHECK: lcalll $2, $4660 // CHECK: encoding: [0x9a,0x34,0x12,0x00,0x00,0x02,0x00] lcalll $0x2, $0x1234 + + +// rdar://8061602 +L1: + jcxz L1 +// CHECK: jcxz L1 +// CHECK: encoding: [0x67,0xe3,A] + jecxz L1 +// CHECK: jecxz L1 +// CHECK: encoding: [0xe3,A] + Modified: llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s?rev=113343&r1=113342&r2=113343&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s Tue Sep 7 23:30:51 2010 @@ -157,3 +157,14 @@ // CHECK: btq $61, -216(%rbp) // CHECK: encoding: [0x48,0x0f,0xba,0xa5,0x28,0xff,0xff,0xff,0x3d] btq $61, -216(%rbp) + + +// rdar://8061602 +L1: + jecxz L1 +// CHECK: jecxz L1 +// CHECK: encoding: [0x67,0xe3,A] + jrcxz L1 +// CHECK: jrcxz L1 +// CHECK: encoding: [0xe3,A] + Modified: llvm/trunk/test/MC/MachO/jcc.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/jcc.s?rev=113343&r1=113342&r2=113343&view=diff ============================================================================== --- llvm/trunk/test/MC/MachO/jcc.s (original) +++ llvm/trunk/test/MC/MachO/jcc.s Tue Sep 7 23:30:51 2010 @@ -10,7 +10,7 @@ 1: nop jc 1f 1: nop - jcxz 1f + jecxz 1f 1: nop jecxz 1f 1: nop From geek4civic at gmail.com Tue Sep 7 23:48:17 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Wed, 08 Sep 2010 04:48:17 -0000 Subject: [llvm-commits] [llvm] r113345 - /llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Message-ID: <20100908044817.599062A6C12C@llvm.org> Author: chapuni Date: Tue Sep 7 23:48:17 2010 New Revision: 113345 URL: http://llvm.org/viewvc/llvm-project?rev=113345&view=rev Log: ARM/Disassembler: Fix definitions incompatible(unsigned and uint32_t) to Cygwin-1.5, following up to r113255. Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=113345&r1=113344&r2=113345&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Tue Sep 7 23:48:17 2010 @@ -298,7 +298,7 @@ /// decodeInstruction(insn) is invoked on the original insn. /// /// Otherwise, decodeThumbInstruction is called with the original insn. -static unsigned decodeThumbSideEffect(bool IsThumb2, uint32_t &insn) { +static unsigned decodeThumbSideEffect(bool IsThumb2, unsigned &insn) { if (IsThumb2) { uint16_t op1 = slice(insn, 28, 27); uint16_t op2 = slice(insn, 26, 20); @@ -436,7 +436,7 @@ // passed to decodeThumbInstruction(). For 16-bit Thumb instruction, the top // halfword of insn is 0x00 0x00; otherwise, the first halfword is moved to // the top half followed by the second halfword. - uint32_t insn = 0; + unsigned insn = 0; // Possible second halfword. uint16_t insn1 = 0; From sabre at nondot.org Tue Sep 7 23:53:27 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 08 Sep 2010 04:53:27 -0000 Subject: [llvm-commits] [llvm] r113346 - in /llvm/trunk: lib/Target/X86/AsmParser/X86AsmParser.cpp test/MC/AsmParser/X86/x86_64-new-encoder.s Message-ID: <20100908045327.DC8F02A6C12C@llvm.org> Author: lattner Date: Tue Sep 7 23:53:27 2010 New Revision: 113346 URL: http://llvm.org/viewvc/llvm-project?rev=113346&view=rev Log: gas accepts xchg , as a synonym for xchg , . Add this to the mc assembler, fixing PR8061 Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=113346&r1=113345&r2=113346&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Tue Sep 7 23:53:27 2010 @@ -753,6 +753,7 @@ PatchedName = "vpclmulqdq"; } } + Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc)); if (ExtraImmOp) @@ -827,6 +828,16 @@ delete Operands[0]; Operands[0] = X86Operand::CreateToken("sldtw", NameLoc); } + + // The assembler accepts "xchgX , " and "xchgX , " as + // synonyms. Our tables only have the ", " form, so if we see the + // other operand order, swap them. + if (Name == "xchgb" || Name == "xchgw" || Name == "xchgl" || Name == "xchgq") + if (Operands.size() == 3 && + static_cast(Operands[1])->isMem() && + static_cast(Operands[2])->isReg()) { + std::swap(Operands[1], Operands[2]); + } return false; } Modified: llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s?rev=113346&r1=113345&r2=113346&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s Tue Sep 7 23:53:27 2010 @@ -168,3 +168,8 @@ // CHECK: jrcxz L1 // CHECK: encoding: [0xe3,A] +// PR8061 +xchgl 368(%rax),%ecx +// CHECK: xchgl %ecx, 368(%rax) +xchgl %ecx, 368(%rax) +// CHECK: xchgl %ecx, 368(%rax) From geek4civic at gmail.com Tue Sep 7 23:58:09 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Wed, 8 Sep 2010 13:58:09 +0900 Subject: [llvm-commits] [PATCH] Target/ARM build failure on Cygwin-1.5 In-Reply-To: References: <1B3650AC-0C27-42EF-B68B-77D6484BCD23@apple.com> Message-ID: Chris, Applied in r113345! 2010/9/8 Chris Lattner : > Looks great to me, please apply. ?Should one or both of these be applied to the LLVM 2.8 branch? ?If so, please email the svn rev #'s to Bill Wendling. ?Thanks again, I have not prepared the branch, excuse me. Bill, Would you please pick up my r113345(and Chris' r113255) to the branch? ...Takumi From sabre at nondot.org Wed Sep 8 00:10:46 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 08 Sep 2010 05:10:46 -0000 Subject: [llvm-commits] [llvm] r113347 - in /llvm/trunk/lib: MC/MCParser/AsmParser.cpp Target/ARM/AsmParser/ARMAsmParser.cpp Target/X86/AsmParser/X86AsmParser.cpp Message-ID: <20100908051046.E22872A6C12C@llvm.org> Author: lattner Date: Wed Sep 8 00:10:46 2010 New Revision: 113347 URL: http://llvm.org/viewvc/llvm-project?rev=113347&view=rev Log: change the MC "ParseInstruction" interface to make it the implementation's job to check for and lex the EndOfStatement marker. Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=113347&r1=113346&r2=113347&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Wed Sep 8 00:10:46 2010 @@ -917,8 +917,6 @@ SmallVector ParsedOperands; bool HadError = getTargetParser().ParseInstruction(Opcode.str(), IDLoc, ParsedOperands); - if (!HadError && Lexer.isNot(AsmToken::EndOfStatement)) - HadError = TokError("unexpected token in argument list"); // Dump the parsed representation, if requested. if (getShowParsedOperands()) { @@ -945,11 +943,6 @@ HadError = true; } - // If there was no error, consume the end-of-statement token. Otherwise this - // will be done by our caller. - if (!HadError) - Lex(); - // Free any parsed operands. for (unsigned i = 0, e = ParsedOperands.size(); i != e; ++i) delete ParsedOperands[i]; Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=113347&r1=113346&r2=113347&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Sep 8 00:10:46 2010 @@ -737,6 +737,11 @@ Operands.push_back(Op.take()); } } + + if (getLexer().isNot(AsmToken::EndOfStatement)) + return TokError("unexpected token in argument list"); + Parser.Lex(); // Consume the EndOfStatement + return false; } Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=113347&r1=113346&r2=113347&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Wed Sep 8 00:10:46 2010 @@ -786,6 +786,10 @@ return true; } } + + if (getLexer().isNot(AsmToken::EndOfStatement)) + return TokError("unexpected token in argument list"); + Parser.Lex(); // Consume the EndOfStatement // FIXME: Hack to handle recognizing s{hr,ar,hl}? $1. if ((Name.startswith("shr") || Name.startswith("sar") || From sabre at nondot.org Wed Sep 8 00:17:37 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 08 Sep 2010 05:17:37 -0000 Subject: [llvm-commits] [llvm] r113348 - in /llvm/trunk: lib/Target/X86/AsmParser/X86AsmParser.cpp test/MC/AsmParser/X86/x86_64-new-encoder.s Message-ID: <20100908051737.CCFA02A6C12D@llvm.org> Author: lattner Date: Wed Sep 8 00:17:37 2010 New Revision: 113348 URL: http://llvm.org/viewvc/llvm-project?rev=113348&view=rev Log: add support for instruction prefixes on the same line as the instruction, implementing rdar://8033482 and PR7254. Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=113348&r1=113347&r2=113348&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Wed Sep 8 00:17:37 2010 @@ -758,10 +758,19 @@ if (ExtraImmOp) Operands.push_back(X86Operand::CreateImm(ExtraImmOp, NameLoc, NameLoc)); - - // This does the actual operand parsing. - if (getLexer().isNot(AsmToken::EndOfStatement)) { + + // Determine whether this is an instruction prefix. + bool isPrefix = + PatchedName == "lock" || PatchedName == "rep" || + PatchedName == "repne"; + + + // This does the actual operand parsing. Don't parse any more if we have a + // prefix juxtaposed with an operation like "lock incl 4(%rax)", because we + // just want to parse the "lock" as the first instruction and the "incl" as + // the next one. + if (getLexer().isNot(AsmToken::EndOfStatement) && !isPrefix) { // Parse '*' modifier. if (getLexer().is(AsmToken::Star)) { @@ -785,11 +794,13 @@ else return true; } + + if (getLexer().isNot(AsmToken::EndOfStatement)) + return TokError("unexpected token in argument list"); } - if (getLexer().isNot(AsmToken::EndOfStatement)) - return TokError("unexpected token in argument list"); - Parser.Lex(); // Consume the EndOfStatement + if (getLexer().is(AsmToken::EndOfStatement)) + Parser.Lex(); // Consume the EndOfStatement // FIXME: Hack to handle recognizing s{hr,ar,hl}? $1. if ((Name.startswith("shr") || Name.startswith("sar") || Modified: llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s?rev=113348&r1=113347&r2=113348&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s Wed Sep 8 00:17:37 2010 @@ -173,3 +173,15 @@ // CHECK: xchgl %ecx, 368(%rax) xchgl %ecx, 368(%rax) // CHECK: xchgl %ecx, 368(%rax) + +// PR7254 +lock incl 1(%rsp) +// CHECK: lock +// CHECK: incl 1(%rsp) + +// rdar://8033482 +rep movsl +// CHECK: rep +// CHECK: encoding: [0xf3] +// CHECK: movsl +// CHECK: encoding: [0xa5] From nicholas at mxc.ca Wed Sep 8 00:22:33 2010 From: nicholas at mxc.ca (Nick Lewycky) Date: Tue, 07 Sep 2010 22:22:33 -0700 Subject: [llvm-commits] [llvm] r113329 - in /llvm/trunk: include/llvm/Analysis/AliasAnalysis.h lib/Analysis/AliasAnalysis.cpp lib/Analysis/BasicAliasAnalysis.cpp In-Reply-To: <20100908013220.8342E2A6C12C@llvm.org> References: <20100908013220.8342E2A6C12C@llvm.org> Message-ID: <4C871D99.6040900@mxc.ca> Dan Gohman wrote: > Author: djg > Date: Tue Sep 7 20:32:20 2010 > New Revision: 113329 > > URL: http://llvm.org/viewvc/llvm-project?rev=113329&view=rev > Log: > Add a new experimental generalized dependence query interface to > AliasAnalysis, and some code for implementing the new query on top of > existing implementations by making standard alias and getModRefInfo > queries. Hi Dan, Are you sure you don't just want MemoryDependenceAnalysis? Your DependenceResult enum is much larger than memdep's MemDepResult, but in reality passes use I->mayWriteToMemory and the like to determine the extra info your pass puts in the result enum. Nick > > Modified: > llvm/trunk/include/llvm/Analysis/AliasAnalysis.h > llvm/trunk/lib/Analysis/AliasAnalysis.cpp > llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp > > Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/AliasAnalysis.h?rev=113329&r1=113328&r2=113329&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/Analysis/AliasAnalysis.h (original) > +++ llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Tue Sep 7 20:32:20 2010 > @@ -278,6 +278,81 @@ > ImmutableCallSite CS2); > > //===--------------------------------------------------------------------===// > + /// Dependence queries. > + /// > + > + /// DependenceResult - These are the return values for getDependence queries. > + /// They are defined in terms of "memory", but they are also used to model > + /// other side effects, such as I/O and volatility. > + enum DependenceResult { > + /// ReadThenRead - The instructions are ReadThenReadSome and the second > + /// instruction reads from exactly the same memory read from by the first. > + ReadThenRead, > + > + /// ReadThenReadSome - The instructions are Independent, both are read-only, > + /// and the second instruction reads from a subset of the memory read from > + /// by the first. > + ReadThenReadSome, > + > + /// Independent - Neither instruction reads from or writes to memory written > + /// to by the other. All enum values lower than this one are special cases > + /// of Indepenent. > + Independent, > + > + /// WriteThenRead - The instructions are WriteThenReadSome and the second > + /// instruction reads from exactly the same memory written by the first. > + WriteThenRead, > + > + /// WriteThenReadSome - The first instruction is write-only, the second > + /// instruction is read-only, and the second only reads from memory > + /// written to by the first. > + WriteThenReadSome, > + > + /// ReadThenWrite - The instructions are ReadThenWriteSome and the second > + /// instruction writes to exactly the same memory read from by the first. > + ReadThenWrite, > + > + /// WriteThenWrite - The instructions are WriteThenWriteSome, and the > + /// second instruction writes to exactly the same memory written to by > + /// the first. > + WriteThenWrite, > + > + /// WriteSomeThenWrite - Both instructions are write-only, and the second > + /// instruction writes to a superset of the memory written to by the first. > + WriteSomeThenWrite, > + > + /// Unknown - The relationship between the instructions cannot be > + /// determined or does not fit into any of the cases defined here. > + Unknown > + }; > + > + /// DependenceQueryFlags - Flags for refining dependence queries. > + enum DependenceQueryFlags { > + Default = 0, > + IgnoreLoads = 1, > + IgnoreStores = 2 > + }; > + > + /// getDependence - Determine the dependence relationship between the > + /// instructions. This does not include "register" dependencies; it just > + /// considers memory references and other side effects. > + /// WARNING: This is an experimental interface. > + DependenceResult getDependence(const Instruction *First, > + const Instruction *Second) { > + return getDependence(First, Default, Second, Default); > + } > + > + /// getDependence - Determine the dependence relationship between the > + /// instructions. This does not include "register" dependencies; it just > + /// considers memory references and other side effects. This overload > + /// accepts additional flags to refine the query. > + /// WARNING: This is an experimental interface. > + virtual DependenceResult getDependence(const Instruction *First, > + DependenceQueryFlags FirstFlags, > + const Instruction *Second, > + DependenceQueryFlags SecondFlags); > + > + //===--------------------------------------------------------------------===// > /// Higher level methods for querying mod/ref information. > /// > > @@ -322,6 +397,15 @@ > copyValue(Old, New); > deleteValue(Old); > } > + > +protected: > + /// getDependenceViaModRefInfo - Helper function for implementing getDependence > + /// in implementations which already have getModRefInfo implementations. > + DependenceResult getDependenceViaModRefInfo(const Instruction *First, > + DependenceQueryFlags FirstFlags, > + const Instruction *Second, > + DependenceQueryFlags SecondFlags); > + > }; > > /// isNoAliasCall - Return true if this pointer is returned by a noalias > > Modified: llvm/trunk/lib/Analysis/AliasAnalysis.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasAnalysis.cpp?rev=113329&r1=113328&r2=113329&view=diff > ============================================================================== > --- llvm/trunk/lib/Analysis/AliasAnalysis.cpp (original) > +++ llvm/trunk/lib/Analysis/AliasAnalysis.cpp Tue Sep 7 20:32:20 2010 > @@ -188,6 +188,14 @@ > return AA->getModRefBehavior(F); > } > > +AliasAnalysis::DependenceResult > +AliasAnalysis::getDependence(const Instruction *First, > + DependenceQueryFlags FirstFlags, > + const Instruction *Second, > + DependenceQueryFlags SecondFlags) { > + assert(AA&& "AA didn't call InitializeAliasAnalyais in its run method!"); > + return AA->getDependence(First, FirstFlags, Second, SecondFlags); > +} > > //===----------------------------------------------------------------------===// > // AliasAnalysis non-virtual helper method implementation > @@ -245,6 +253,190 @@ > return ModRef; > } > > +AliasAnalysis::DependenceResult > +AliasAnalysis::getDependenceViaModRefInfo(const Instruction *First, > + DependenceQueryFlags FirstFlags, > + const Instruction *Second, > + DependenceQueryFlags SecondFlags) { > + if (const LoadInst *L = dyn_cast(First)) { > + // Be over-conservative with volatile for now. > + if (L->isVolatile()) > + return Unknown; > + > + // Forward this query to getModRefInfo. > + switch (getModRefInfo(Second, > + L->getPointerOperand(), > + getTypeStoreSize(L->getType()))) { > + case NoModRef: > + // Second doesn't reference First's memory, so they're independent. > + return Independent; > + > + case Ref: > + // Second only reads from the memory read from by First. If it > + // also writes to any other memory, be conservative. > + if (Second->mayWriteToMemory()) > + return Unknown; > + > + // If it's loading the same size from the same address, we can > + // give a more precise result. > + if (const LoadInst *SecondL = dyn_cast(Second)) { > + unsigned LSize = getTypeStoreSize(L->getType()); > + unsigned SecondLSize = getTypeStoreSize(SecondL->getType()); > + if (alias(L->getPointerOperand(), LSize, > + SecondL->getPointerOperand(), SecondLSize) == > + MustAlias) { > + // If the loads are the same size, it's ReadThenRead. > + if (LSize == SecondLSize) > + return ReadThenRead; > + > + // If the second load is smaller, it's only ReadThenReadSome. > + if (LSize> SecondLSize) > + return ReadThenReadSome; > + } > + } > + > + // Otherwise it's just two loads. > + return Independent; > + > + case Mod: > + // Second only writes to the memory read from by First. If it > + // also reads from any other memory, be conservative. > + if (Second->mayReadFromMemory()) > + return Unknown; > + > + // If it's storing the same size to the same address, we can > + // give a more precise result. > + if (const StoreInst *SecondS = dyn_cast(Second)) { > + unsigned LSize = getTypeStoreSize(L->getType()); > + unsigned SecondSSize = getTypeStoreSize(SecondS->getType()); > + if (alias(L->getPointerOperand(), LSize, > + SecondS->getPointerOperand(), SecondSSize) == > + MustAlias) { > + // If the load and the store are the same size, it's ReadThenWrite. > + if (LSize == SecondSSize) > + return ReadThenWrite; > + } > + } > + > + // Otherwise we don't know if it could be writing to other memory. > + return Unknown; > + > + case ModRef: > + // Second reads and writes to the memory read from by First. > + // We don't have a way to express that. > + return Unknown; > + } > + > + } else if (const StoreInst *S = dyn_cast(First)) { > + // Be over-conservative with volatile for now. > + if (S->isVolatile()) > + return Unknown; > + > + // Forward this query to getModRefInfo. > + switch (getModRefInfo(Second, > + S->getPointerOperand(), > + getTypeStoreSize(S->getValueOperand()->getType()))) { > + case NoModRef: > + // Second doesn't reference First's memory, so they're independent. > + return Independent; > + > + case Ref: > + // Second only reads from the memory written to by First. If it > + // also writes to any other memory, be conservative. > + if (Second->mayWriteToMemory()) > + return Unknown; > + > + // If it's loading the same size from the same address, we can > + // give a more precise result. > + if (const LoadInst *SecondL = dyn_cast(Second)) { > + unsigned SSize = getTypeStoreSize(S->getValueOperand()->getType()); > + unsigned SecondLSize = getTypeStoreSize(SecondL->getType()); > + if (alias(S->getPointerOperand(), SSize, > + SecondL->getPointerOperand(), SecondLSize) == > + MustAlias) { > + // If the store and the load are the same size, it's WriteThenRead. > + if (SSize == SecondLSize) > + return WriteThenRead; > + > + // If the load is smaller, it's only WriteThenReadSome. > + if (SSize> SecondLSize) > + return WriteThenReadSome; > + } > + } > + > + // Otherwise we don't know if it could be reading from other memory. > + return Unknown; > + > + case Mod: > + // Second only writes to the memory written to by First. If it > + // also reads from any other memory, be conservative. > + if (Second->mayReadFromMemory()) > + return Unknown; > + > + // If it's storing the same size to the same address, we can > + // give a more precise result. > + if (const StoreInst *SecondS = dyn_cast(Second)) { > + unsigned SSize = getTypeStoreSize(S->getValueOperand()->getType()); > + unsigned SecondSSize = getTypeStoreSize(SecondS->getType()); > + if (alias(S->getPointerOperand(), SSize, > + SecondS->getPointerOperand(), SecondSSize) == > + MustAlias) { > + // If the stores are the same size, it's WriteThenWrite. > + if (SSize == SecondSSize) > + return WriteThenWrite; > + > + // If the second store is larger, it's only WriteSomeThenWrite. > + if (SSize< SecondSSize) > + return WriteSomeThenWrite; > + } > + } > + > + // Otherwise we don't know if it could be writing to other memory. > + return Unknown; > + > + case ModRef: > + // Second reads and writes to the memory written to by First. > + // We don't have a way to express that. > + return Unknown; > + } > + > + } else if (const VAArgInst *V = dyn_cast(First)) { > + // Forward this query to getModRefInfo. > + if (getModRefInfo(Second, V->getOperand(0), UnknownSize) == NoModRef) > + // Second doesn't reference First's memory, so they're independent. > + return Independent; > + > + } else if (ImmutableCallSite FirstCS = cast(First)) { > + // If both instructions are calls/invokes we can use the two-callsite > + // form of getModRefInfo. > + if (ImmutableCallSite SecondCS = cast(Second)) > + // getModRefInfo's arguments are backwards from intuition. > + switch (getModRefInfo(SecondCS, FirstCS)) { > + case NoModRef: > + // Second doesn't reference First's memory, so they're independent. > + return Independent; > + > + case Ref: > + // If they're both read-only, there's no dependence. > + if (FirstCS.onlyReadsMemory()&& SecondCS.onlyReadsMemory()) > + return Independent; > + > + // Otherwise it's not obvious what we can do here. > + return Unknown; > + > + case Mod: > + // It's not obvious what we can do here. > + return Unknown; > + > + case ModRef: > + // I know, right? > + return Unknown; > + } > + } > + > + // For anything else, be conservative. > + return Unknown; > +} > > AliasAnalysis::ModRefBehavior > AliasAnalysis::getIntrinsicModRefBehavior(unsigned iid) { > > Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=113329&r1=113328&r2=113329&view=diff > ============================================================================== > --- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original) > +++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Tue Sep 7 20:32:20 2010 > @@ -171,6 +171,13 @@ > return ModRef; > } > > + virtual DependenceResult getDependence(const Instruction *First, > + DependenceQueryFlags FirstFlags, > + const Instruction *Second, > + DependenceQueryFlags SecondFlags) { > + return Unknown; > + } > + > virtual void deleteValue(Value *V) {} > virtual void copyValue(Value *From, Value *To) {} > > @@ -523,6 +530,11 @@ > /// For use when the call site is not known. > virtual ModRefBehavior getModRefBehavior(const Function *F); > > + virtual DependenceResult getDependence(const Instruction *First, > + DependenceQueryFlags FirstFlags, > + const Instruction *Second, > + DependenceQueryFlags SecondFlags); > + > /// getAdjustedAnalysisPointer - This method is used when a pass implements > /// an analysis interface through multiple inheritance. If needed, it > /// should override this to adjust the this pointer as needed for the > @@ -734,6 +746,14 @@ > return AliasAnalysis::getModRefInfo(CS, P, Size); > } > > +AliasAnalysis::DependenceResult > +BasicAliasAnalysis::getDependence(const Instruction *First, > + DependenceQueryFlags FirstFlags, > + const Instruction *Second, > + DependenceQueryFlags SecondFlags) { > + // We don't have anything special to say yet. > + return getDependenceViaModRefInfo(First, FirstFlags, Second, SecondFlags); > +} > > /// aliasGEP - Provide a bunch of ad-hoc rules to disambiguate a GEP instruction > /// against another pointer. We know that V1 is a GEP, but we don't know > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From sabre at nondot.org Wed Sep 8 00:38:31 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 08 Sep 2010 05:38:31 -0000 Subject: [llvm-commits] [llvm] r113349 - in /llvm/trunk: lib/Target/X86/AsmParser/X86AsmParser.cpp lib/Target/X86/X86Instr64bit.td lib/Target/X86/X86InstrInfo.td test/MC/AsmParser/X86/x86_32-new-encoder.s test/MC/AsmParser/X86/x86_64-new-encoder.s Message-ID: <20100908053832.1B1602A6C12C@llvm.org> Author: lattner Date: Wed Sep 8 00:38:31 2010 New Revision: 113349 URL: http://llvm.org/viewvc/llvm-project?rev=113349&view=rev Log: implement the iret suite of instructions properly, fixing rdar://8403974 Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/lib/Target/X86/X86Instr64bit.td llvm/trunk/lib/Target/X86/X86InstrInfo.td llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=113349&r1=113348&r2=113349&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Wed Sep 8 00:38:31 2010 @@ -627,6 +627,7 @@ .Case("repe", "rep") .Case("repz", "rep") .Case("repnz", "repne") + .Case("iret", "iretl") .Case("push", Is64Bit ? "pushq" : "pushl") .Case("pushf", Is64Bit ? "pushfq" : "pushfl") .Case("popf", Is64Bit ? "popfq" : "popfl") Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=113349&r1=113348&r2=113349&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original) +++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Wed Sep 8 00:38:31 2010 @@ -117,7 +117,8 @@ } // Interrupt Instructions -def IRET64 : RI<0xcf, RawFrm, (outs), (ins), "iret{q}", []>; +def IRET64 : RI<0xcf, RawFrm, (outs), (ins), "iretq", []>, + Requires<[In64BitMode]>; //===----------------------------------------------------------------------===// // Call Instructions... Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=113349&r1=113348&r2=113349&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Wed Sep 8 00:38:31 2010 @@ -601,8 +601,8 @@ [(int_x86_int (i8 3))]>; def INT : Ii8<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap", [(int_x86_int imm:$trap)]>; -def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", []>, OpSize; -def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l}", []>; +def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iretw", []>, OpSize; +def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l|d}", []>; // PIC base construction. This expands to code that looks like this: // call $next_inst Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s?rev=113349&r1=113348&r2=113349&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s Wed Sep 8 00:38:31 2010 @@ -434,3 +434,13 @@ // CHECK: jecxz L1 // CHECK: encoding: [0xe3,A] +// rdar://8403974 +iret +// CHECK: iretl +// CHECK: encoding: [0xcf] +iretw +// CHECK: iretw +// CHECK: encoding: [0x66,0xcf] +iretl +// CHECK: iretl +// CHECK: encoding: [0xcf] Modified: llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s?rev=113349&r1=113348&r2=113349&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s Wed Sep 8 00:38:31 2010 @@ -185,3 +185,20 @@ // CHECK: encoding: [0xf3] // CHECK: movsl // CHECK: encoding: [0xa5] + + +// rdar://8403974 +iret +// CHECK: iretl +// CHECK: encoding: [0xcf] +iretw +// CHECK: iretw +// CHECK: encoding: [0x66,0xcf] +iretl +// CHECK: iretl +// CHECK: encoding: [0xcf] +iretq +// CHECK: iretq +// CHECK: encoding: [0x48,0xcf] + + From sabre at nondot.org Wed Sep 8 00:45:35 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 08 Sep 2010 05:45:35 -0000 Subject: [llvm-commits] [llvm] r113350 - in /llvm/trunk: lib/Target/X86/AsmParser/X86AsmParser.cpp lib/Target/X86/X86Instr64bit.td lib/Target/X86/X86InstrInfo.td test/MC/AsmParser/X86/x86_32-new-encoder.s test/MC/AsmParser/X86/x86_64-new-encoder.s Message-ID: <20100908054535.3980C2A6C12C@llvm.org> Author: lattner Date: Wed Sep 8 00:45:34 2010 New Revision: 113350 URL: http://llvm.org/viewvc/llvm-project?rev=113350&view=rev Log: implement proper support for sysret{,l,q}, rdar://8403907 Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/lib/Target/X86/X86Instr64bit.td llvm/trunk/lib/Target/X86/X86InstrInfo.td llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=113350&r1=113349&r2=113350&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Wed Sep 8 00:45:34 2010 @@ -628,6 +628,7 @@ .Case("repz", "rep") .Case("repnz", "repne") .Case("iret", "iretl") + .Case("sysret", "sysretl") .Case("push", Is64Bit ? "pushq" : "pushl") .Case("pushf", Is64Bit ? "pushfq" : "pushfl") .Case("popf", Is64Bit ? "popfq" : "popfl") Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=113350&r1=113349&r2=113350&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original) +++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Wed Sep 8 00:45:34 2010 @@ -120,6 +120,10 @@ def IRET64 : RI<0xcf, RawFrm, (outs), (ins), "iretq", []>, Requires<[In64BitMode]>; +def SYSRETQ : RI<0x07, RawFrm, + (outs), (ins), "sysretq", []>, TB, Requires<[In64BitMode]>; + + //===----------------------------------------------------------------------===// // Call Instructions... // Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=113350&r1=113349&r2=113350&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Wed Sep 8 00:45:34 2010 @@ -971,8 +971,8 @@ def SYSCALL : I<0x05, RawFrm, (outs), (ins), "syscall", []>, TB; -def SYSRET : I<0x07, RawFrm, - (outs), (ins), "sysret", []>, TB; +def SYSRETL : I<0x07, RawFrm, + (outs), (ins), "sysretl", []>, TB; def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", []>, TB; def SYSEXIT : I<0x35, RawFrm, Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s?rev=113350&r1=113349&r2=113350&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s Wed Sep 8 00:45:34 2010 @@ -444,3 +444,11 @@ iretl // CHECK: iretl // CHECK: encoding: [0xcf] + +// rdar://8403907 +sysret +// CHECK: sysretl +// CHECK: encoding: [0x0f,0x07] +sysretl +// CHECK: sysretl +// CHECK: encoding: [0x0f,0x07] Modified: llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s?rev=113350&r1=113349&r2=113350&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s Wed Sep 8 00:45:34 2010 @@ -201,4 +201,13 @@ // CHECK: iretq // CHECK: encoding: [0x48,0xcf] - +// rdar://8403907 +sysret +// CHECK: sysretl +// CHECK: encoding: [0x0f,0x07] +sysretl +// CHECK: sysretl +// CHECK: encoding: [0x0f,0x07] +sysretq +// CHECK: sysretq +// CHECK: encoding: [0x48,0x0f,0x07] From criswell at uiuc.edu Wed Sep 8 00:50:10 2010 From: criswell at uiuc.edu (John Criswell) Date: Wed, 08 Sep 2010 05:50:10 -0000 Subject: [llvm-commits] [poolalloc] r113351 - in /poolalloc/trunk: include/poolalloc/PoolAllocate.h lib/PoolAllocate/PoolAllocate.cpp lib/PoolAllocate/TransformFunctionBody.cpp Message-ID: <20100908055010.EDEED2A6C12C@llvm.org> Author: criswell Date: Wed Sep 8 00:50:10 2010 New Revision: 113351 URL: http://llvm.org/viewvc/llvm-project?rev=113351&view=rev Log: This commit fixes 254.gap on Mac OS X and should fix PR#8103. First, when finding which arguments need pools, process an entire equivalence class at a time. This ensures that every function in an equivalence class has the same DSNodes listed in MarkedNodes and ArgNodes in its FuncInfo, which helps to transform the functions in the equivalence class uniformly. Second, when transforming a call site, examine the target with the maximum number of arguments. This originaly helped prevent eliding a pool argument because a particular target didn't need it. I'm not convinced that this change in TransformFunctionBody.cpp is needed (or correct), but it's not breaking anything at the moment, so it goes in. Modified: poolalloc/trunk/include/poolalloc/PoolAllocate.h poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp Modified: poolalloc/trunk/include/poolalloc/PoolAllocate.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/poolalloc/PoolAllocate.h?rev=113351&r1=113350&r2=113351&view=diff ============================================================================== --- poolalloc/trunk/include/poolalloc/PoolAllocate.h (original) +++ poolalloc/trunk/include/poolalloc/PoolAllocate.h Wed Sep 8 00:50:10 2010 @@ -451,7 +451,7 @@ /// FindFunctionPoolArgs - In the first pass over the program, we decide which /// arguments will have to be added for each function, build the FunctionInfo /// map and recording this info in the ArgNodes set. - void FindFunctionPoolArgs (Function &F); + void FindFunctionPoolArgs (const std::vector & Funcs); /// MakeFunctionClone - If the specified function needs to be modified for /// pool allocation support, make a clone of it, adding additional arguments Modified: poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp?rev=113351&r1=113350&r2=113351&view=diff ============================================================================== --- poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp (original) +++ poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp Wed Sep 8 00:50:10 2010 @@ -620,7 +620,7 @@ } // -// Function: MarkNodesWhichMustBePassedIn() +// Function: RemoveGlobalNodes() // // Description: // Given a function and its DSGraph, determine which values will need to have @@ -695,50 +695,164 @@ // void PoolAllocate::FindPoolArgs (Module & M) { - for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I) - if (!I->isDeclaration() && Graphs->hasDSGraph(*I)) - FindFunctionPoolArgs(*I); + // + // Scan through each equivalence class. The Equivalence Class Bottom-Up + // pass guarantees that each function that is the target of an indirect + // function call will have the same DSGraph and will have identical DSNodes + // for corresponding arguments. Therefore, we want to process all the + // functions in the same equivalence class once to avoid doing extra work. + // + EquivalenceClasses & GlobalECs = Graphs->getGlobalECs(); + EquivalenceClasses::iterator EQSI = GlobalECs.begin(); + EquivalenceClasses::iterator EQSE = GlobalECs.end(); + for (;EQSI != EQSE; ++EQSI) { + // + // If this element is not a leader, then skip it. + // + if (!EQSI->isLeader()) continue; + + // + // Iterate through all members of this equivalence class, looking for + // functions. Record all of those functions which need to be processed. + // + std::vector Functions; + EquivalenceClasses::member_iterator MI; + for (MI=GlobalECs.member_begin(EQSI); MI != GlobalECs.member_end(); ++MI) { + if (const Function* F = dyn_cast(*MI)) { + // + // If the function has no body, then it has no DSGraph. + // + // FIXME: I don't believe this is correct; the stdlib pass can assign + // DSGraphs to C standard library functions. + // + if (!(F->isDeclaration())) + Functions.push_back (F); + } + } + + // + // Find the pool arguments for all of the functions in the equivalence + // class and construct the FuncInfo structure for each one. + // + FindFunctionPoolArgs (Functions); + } + + // + // Make sure every function has a FuncInfo structure. + // + for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I) { + if (!I->isDeclaration() && Graphs->hasDSGraph(*I)) { + if (FunctionInfo.find (I) == FunctionInfo.end()) { + FunctionInfo.insert(std::make_pair(I, FuncInfo(*I))); + } + } + } + + return; } /// FindFunctionPoolArgs - In the first pass over the program, we decide which /// arguments will have to be added for each function, build the FunctionInfo /// map and recording this info in the ArgNodes set. void -PoolAllocate::FindFunctionPoolArgs (Function & F) { - DSGraph* G = Graphs->getDSGraph(F); +PoolAllocate::FindFunctionPoolArgs (const std::vector & Functions) { + // + // If there are no functions to process, then do nothing. + // + if (Functions.size() == 0) + return; - // Create a new entry for F. - FuncInfo &FI = - FunctionInfo.insert(std::make_pair(&F, FuncInfo(F))).first->second; - DenseSet &MarkedNodes = FI.MarkedNodes; + // + // Find all of the DSNodes which could possibly require a pool to be passed + // in. Collect these DSNodes into one big container. + // + std::vector RootNodes; + for (unsigned index = 0; index < Functions.size(); ++index) { + // + // Get the DSGraph of the function. + // + const Function * F = Functions[index]; + DSGraph* G = Graphs->getDSGraph (*F); + + // + // Get all of the DSNodes which could possibly require a pool to be + // passed into the function. + // + G->getFunctionArgumentsForCall (F, RootNodes); + } // - // If there is no memory activity in this function, then nothing is required. + // If there is no memory activity in any of these functions, then nothing is + // required. // - if (G->node_begin() == G->node_end()) + if (RootNodes.size() == 0) return; // - // Find all of the DSNodes which could require a pool to be passed into the - // function. + // Now find all nodes which are reachable from these DSNodes. // - std::vector Args; - G->getFunctionArgumentsForCall (&F, Args); + DenseSet MarkedNodes; + for (unsigned index = 0; index < RootNodes.size(); ++index) { + if (DSNode * N = RootNodes[index].getNode()) { + MarkedNodes.insert (N); + N->markReachableNodes(MarkedNodes); + } + } - // Find DataStructure nodes which are allocated in pools non-local to the - // current function. This set will contain all of the DSNodes which require - // pools to be passed in from outside of the function. - MarkNodesWhichMustBePassedIn(MarkedNodes, Args, G, PassAllArguments); + // + // Determine which DSNodes are reachable from globals. If a node is + // reachable from a global, we will create a global pool for it, so no + // argument passage is required. + // + DenseSet NodesFromGlobals; + for (unsigned index = 0; index < Functions.size(); ++index) { + // + // Get the DSGraph of the function. + // + const Function * F = Functions[index]; + DSGraph* G = Graphs->getDSGraph(*F); + GetNodesReachableFromGlobals (G, NodesFromGlobals); + } + // + // Remove any nodes reachable from a global. These nodes will be put into + // global pools, which do not require arguments to be passed in. Also, erase + // any marked node that is not a heap node. Since no allocations or frees + // will be done with it, it needs no argument. + // + // FIXME: + // 1) PassAllArguments seems to be ignored here. Why is that? + // 2) Should the heap node check be part of the PassAllArguments check? + // 3) SAFECode probably needs to pass the pool even if it's not a heap node. + // We should probably just do what the heuristic tells us to do. + // + for (DenseSet::iterator I = MarkedNodes.begin(), + E = MarkedNodes.end(); I != E; ) { + const DSNode *N = *I; ++I; + if ((!(1 || N->isHeapNode()) && !PassAllArguments) || + NodesFromGlobals.count(N)) + MarkedNodes.erase(N); + } // - // DenseSet does not have iterator traits, so we cannot use an insert() - // method that takes iterators. Instead, we must use a loop to insert each - // element into ArgNodes one at a time. + // Create new FuncInfo entries for all of the functions. Each one will have + // the same set of DSNodes passed in. // - for (DenseSet::iterator ii = MarkedNodes.begin(), - ee = MarkedNodes.end(); ii != ee; ++ii) - FI.ArgNodes.insert(FI.ArgNodes.end(), *ii); + for (unsigned index = 0; index < Functions.size(); ++index) { + Function * F = (Function *) Functions[index]; + FuncInfo & FI = + FunctionInfo.insert(std::make_pair(F, FuncInfo(*F))).first->second; + // + // DenseSet does not have iterator traits, so we cannot use an insert() + // method that takes iterators. Instead, we must use a loop to insert each + // element into MarkedNodes and ArgNodes one at a time. + // + for (DenseSet::iterator ii = MarkedNodes.begin(), + ee = MarkedNodes.end(); ii != ee; ++ii) { + FI.MarkedNodes.insert(*ii); + FI.ArgNodes.insert(FI.ArgNodes.end(), *ii); + } + } } // Modified: poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp?rev=113351&r1=113350&r2=113351&view=diff ============================================================================== --- poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp (original) +++ poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp Wed Sep 8 00:50:10 2010 @@ -855,10 +855,30 @@ // sure to use the original call site from the original function; the // points-to analysis has no information on the clones we've created. // + // Also, look for the target that has the greatest number of arguments that + // have associated DSNodes. This ensures that we pass the maximum number + // of pools possible and prevents us from eliding a pool because we're + // examining a target that doesn't need it. + // const DSCallGraph & callGraph = Graphs.getCallGraph(); + unsigned maxArgsWithNodes = 0; DSCallGraph::callee_iterator I = callGraph.callee_begin(OrigInst); - if (I != callGraph.callee_end(OrigInst)) - CF = *I; + for (; I != callGraph.callee_end(OrigInst); ++I) { + // + // Get the information for this function. Since this is coming from DSA, + // it should be an original function. + // + FuncInfo *CFI = PAInfo.getFuncInfo(**I); + + // + // If this target takes more DSNodes than the last one we found, then + // make *this* target our canonical target. + // + if (CFI->ArgNodes.size() > maxArgsWithNodes) { + maxArgsWithNodes = CFI->ArgNodes.size(); + CF = *I; + } + } // // If we didn't find the callee in the constructed call graph, try From sabre at nondot.org Wed Sep 8 00:51:13 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 08 Sep 2010 05:51:13 -0000 Subject: [llvm-commits] [llvm] r113352 - in /llvm/trunk: lib/Target/X86/AsmParser/X86AsmParser.cpp test/MC/AsmParser/X86/x86_32-new-encoder.s Message-ID: <20100908055113.0CC672A6C12C@llvm.org> Author: lattner Date: Wed Sep 8 00:51:12 2010 New Revision: 113352 URL: http://llvm.org/viewvc/llvm-project?rev=113352&view=rev Log: add support for the commuted form of the test instruction, rdar://8018260. Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=113352&r1=113351&r2=113352&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Wed Sep 8 00:51:12 2010 @@ -856,6 +856,16 @@ std::swap(Operands[1], Operands[2]); } + // The assembler accepts "testX , " and "testX , " as + // synonyms. Our tables only have the ", " form, so if we see the + // other operand order, swap them. + if (Name == "testb" || Name == "testw" || Name == "testl" || Name == "testq") + if (Operands.size() == 3 && + static_cast(Operands[1])->isReg() && + static_cast(Operands[2])->isMem()) { + std::swap(Operands[1], Operands[2]); + } + return false; } Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s?rev=113352&r1=113351&r2=113352&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s Wed Sep 8 00:51:12 2010 @@ -452,3 +452,10 @@ sysretl // CHECK: sysretl // CHECK: encoding: [0x0f,0x07] + +// rdar://8018260 +testl %ecx, -24(%ebp) +// CHECK: testl -24(%ebp), %ecx +testl -24(%ebp), %ecx +// CHECK: testl -24(%ebp), %ecx + From evan.cheng at apple.com Wed Sep 8 01:02:44 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 07 Sep 2010 23:02:44 -0700 Subject: [llvm-commits] [llvm] r112664 - in /llvm/trunk: lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td test/CodeGen/ARM/mvncc.ll test/CodeGen/Thumb2/thumb2-mvncc.ll In-Reply-To: <20100831224122.6BA6E2A6C12E@llvm.org> References: <20100831224122.6BA6E2A6C12E@llvm.org> Message-ID: <8C81CB0A-63B8-4893-A3EE-F319C0012D52@apple.com> Hi Bill, Thanks for doing this but I have some questions. On Aug 31, 2010, at 3:41 PM, Bill Wendling wrote: > Author: void > Date: Tue Aug 31 17:41:22 2010 > New Revision: 112664 > > URL: http://llvm.org/viewvc/llvm-project?rev=112664&view=rev > Log: > We have a chance for an optimization. Consider this code: > > int x(int t) { > if (t & 256) > return -26; > return 0; > } > > We generate this: > > tst.w r0, #256 > mvn r0, #25 > it eq > moveq r0, #0 > > while gcc generates this: > > ands r0, r0, #256 > it ne > mvnne r0, #25 > bx lr Is it possible to generate the "and" and comparison at isel time and let the peephole pass get rid of the compare later? I'd prefer to avoid having these instructions like ARM::ANDS. Evan > > Scandalous really! > > During ISel time, we can look for this particular pattern. One where we have a > "MOVCC" that uses the flag off of a CMPZ that itself is comparing an AND > instruction to 0. Something like this (greatly simplified): > > %r0 = ISD::AND ... > ARMISD::CMPZ %r0, 0 @ sets [CPSR] > %r0 = ARMISD::MOVCC 0, -26 @ reads [CPSR] > > All we have to do is convert the "ISD::AND" into an "ARM::ANDS" that sets [CPSR] > when it's zero. The zero value will all ready be in the %r0 register and we only > need to change it if the AND wasn't zero. Easy! > > Added: > llvm/trunk/test/CodeGen/ARM/mvncc.ll > llvm/trunk/test/CodeGen/Thumb2/thumb2-mvncc.ll > Modified: > llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp > llvm/trunk/lib/Target/ARM/ARMInstrInfo.td > llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td > > Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=112664&r1=112663&r2=112664&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Tue Aug 31 17:41:22 2010 > @@ -180,6 +180,9 @@ > SDNode *SelectARMCMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, > ARMCC::CondCodes CCVal, SDValue CCR, > SDValue InFlag); > + SDNode *OptimizeCMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, > + ARMCC::CondCodes CCVal, SDValue CCR, > + SDValue InFlag, bool IsThumb2); > > SDNode *SelectConcatVector(SDNode *N); > > @@ -1641,6 +1644,92 @@ > return 0; > } > > +/// OptimizeCMOVSoImmOp - It's possible to save an instruction or two be > +/// recognizing that the TST and AND instructions perform the same function > +/// (they "and" the two values). See inside for more details. > +SDNode *ARMDAGToDAGISel:: > +OptimizeCMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, > + ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag, > + bool IsThumb2) { > + // Convert: > + // > + // tst.w r0, #256 > + // mvn r0, #25 > + // it eq > + // moveq r0, #0 > + // > + // into: > + // > + // ands.w r0, r0, #256 > + // it ne > + // mvnne.w r0, #25 > + // > + if (InFlag.getOpcode() != ARMISD::CMPZ || > + InFlag.getOperand(0).getOpcode() != ISD::AND) > + return 0; > + > + // The true value needs to be zero, as that's the result of the AND > + // instruction. > + ConstantSDNode *True = dyn_cast(TrueVal); > + if (!True || True->getZExtValue() != 0) > + return 0; > + > + // Bail if the false value isn't an immediate. > + ConstantSDNode *False = dyn_cast(FalseVal); > + if (!False) > + return 0; > + > + bool UseMVN = false; > + if ((IsThumb2 && !Pred_t2_so_imm(FalseVal.getNode())) || > + (!IsThumb2 && !Pred_so_imm(FalseVal.getNode()))) { > + // The false value isn't a proper immediate. Check to see if we can use the > + // bitwise NOT version. > + if ((IsThumb2 && ARM_AM::getT2SOImmVal(~False->getZExtValue()) != -1) || > + (!IsThumb2 && ARM_AM::getSOImmVal(~False->getZExtValue()) != -1)) { > + UseMVN = true; > + FalseVal = CurDAG->getTargetConstant(~False->getZExtValue(), MVT::i32); > + } else { > + return 0; > + } > + } else { > + FalseVal = CurDAG->getTargetConstant(False->getZExtValue(), MVT::i32); > + } > + > + // A comparison against zero corresponds with the flag AND sets if the result > + // is zero. > + ConstantSDNode *CmpVal = dyn_cast(InFlag.getOperand(1)); > + if (!CmpVal || CmpVal->getZExtValue() != 0) > + return 0; > + > + ARMCC::CondCodes NegCC = ARMCC::getOppositeCondition(CCVal); > + SDValue OrigAnd = InFlag.getOperand(0); > + SDValue NewAnd = > + CurDAG->getNode(ARMISD::AND, N->getDebugLoc(), > + CurDAG->getVTList(OrigAnd.getValueType(), MVT::Flag), > + OrigAnd->getOperand(0), OrigAnd->getOperand(1)); > + > + unsigned Opcode = !UseMVN ? > + (IsThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi) : > + (IsThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi); > + > + SDValue Ops[] = { > + NewAnd.getValue(0), > + FalseVal, > + CurDAG->getTargetConstant(NegCC, MVT::i32), > + CCR, NewAnd.getValue(1) > + }; > + SDNode *ResNode = CurDAG->SelectNodeTo(N, Opcode, MVT::i32, Ops, 5); > + > + // Manually run "Select" on the newly created "ARMISD::AND" node to make > + // sure that it's converted properly. > + SDNode *AndNode = Select(NewAnd.getNode()); > + if (AndNode && NewAnd.getNode() != AndNode && > + NewAnd.getNode()->getOpcode() != ISD::DELETED_NODE) > + ReplaceUses(NewAnd.getNode(), AndNode); > + > + return ResNode; > +} > + > SDNode *ARMDAGToDAGISel:: > SelectT2CMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal, > ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) { > @@ -1649,6 +1738,10 @@ > return 0; > > if (Pred_t2_so_imm(TrueVal.getNode())) { > + SDNode *ResNode = OptimizeCMOVSoImmOp(N, FalseVal, TrueVal, CCVal, CCR, > + InFlag, true); > + if (ResNode) return ResNode; > + > SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32); > SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32); > SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag }; > @@ -1666,6 +1759,10 @@ > return 0; > > if (Pred_so_imm(TrueVal.getNode())) { > + SDNode *ResNode = OptimizeCMOVSoImmOp(N, FalseVal, TrueVal, CCVal, CCR, > + InFlag, false); > + if (ResNode) return ResNode; > + > SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32); > SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32); > SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag }; > > Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=112664&r1=112663&r2=112664&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) > +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Aug 31 17:41:22 2010 > @@ -2419,6 +2419,14 @@ > RegConstraint<"$false = $dst">, UnaryDP { > let Inst{25} = 1; > } > + > +def MVNCCi : AI1<0b1111, (outs GPR:$dst), > + (ins GPR:$false, so_imm:$true), DPFrm, IIC_iCMOVi, > + "mvn", "\t$dst, $true", > + [/*(set GPR:$dst, (ARMcmov GPR:$false,so_imm_not:$true,imm:$cc,CCR:$ccr))*/]>, > + RegConstraint<"$false = $dst">, UnaryDP { > + let Inst{25} = 0; > +} > } // neverHasSideEffects > > //===----------------------------------------------------------------------===// > > Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=112664&r1=112663&r2=112664&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) > +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Aug 31 17:41:22 2010 > @@ -2195,6 +2195,18 @@ > let Inst{15} = 0; > } > > +def t2MVNCCi : T2I<(outs rGPR:$dst), (ins rGPR:$false, t2_so_imm:$true), > + IIC_iCMOVi, "mvn", ".w\t$dst, $true", > +[/*(set rGPR:$dst,(ARMcmov rGPR:$false,t2_so_imm_not:$true,imm:$cc,CCR:$ccr))*/]>, > + RegConstraint<"$false = $dst"> { > + let Inst{31-27} = 0b11110; > + let Inst{25} = 0; > + let Inst{24-21} = 0b0011; > + let Inst{20} = 0; // The S bit. > + let Inst{19-16} = 0b1111; // Rn > + let Inst{15} = 0; > +} > + > class T2I_movcc_sh opcod, dag oops, dag iops, InstrItinClass itin, > string opc, string asm, list pattern> > : T2I { > > Added: llvm/trunk/test/CodeGen/ARM/mvncc.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/mvncc.ll?rev=112664&view=auto > ============================================================================== > --- llvm/trunk/test/CodeGen/ARM/mvncc.ll (added) > +++ llvm/trunk/test/CodeGen/ARM/mvncc.ll Tue Aug 31 17:41:22 2010 > @@ -0,0 +1,12 @@ > +; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s > + > +define i32 @f1(i32 %t) nounwind { > +; CHECK: f1 > +; CHECK-NOT: tst > +; CHECK: and > +; CHECK: mvnne > + %and = and i32 %t, 256 > + %tobool = icmp eq i32 %and, 0 > + %retval.0 = select i1 %tobool, i32 0, i32 -26 > + ret i32 %retval.0 > +} > > Added: llvm/trunk/test/CodeGen/Thumb2/thumb2-mvncc.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-mvncc.ll?rev=112664&view=auto > ============================================================================== > --- llvm/trunk/test/CodeGen/Thumb2/thumb2-mvncc.ll (added) > +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-mvncc.ll Tue Aug 31 17:41:22 2010 > @@ -0,0 +1,13 @@ > +; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s > + > +define i32 @f1(i32 %t) nounwind { > +; CHECK: f1 > +; CHECK-NOT: tst > +; CHECK: ands > +; CHECK: it ne > +; CHECK: mvnne > + %and = and i32 %t, 256 > + %tobool = icmp eq i32 %and, 0 > + %retval.0 = select i1 %tobool, i32 0, i32 -26 > + ret i32 %retval.0 > +} > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From isanbard at gmail.com Wed Sep 8 05:10:28 2010 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 8 Sep 2010 03:10:28 -0700 Subject: [llvm-commits] [PATCH] Target/ARM build failure on Cygwin-1.5 In-Reply-To: References: <1B3650AC-0C27-42EF-B68B-77D6484BCD23@apple.com> Message-ID: Applied here: $ svn merge -c 113255 https://llvm.org/svn/llvm-project/llvm/trunk --- Merging r113255 into '.': U lib/Target/ARM/Disassembler/ARMDisassemblerCore.h $ svn merge -c 113345 https://llvm.org/svn/llvm-project/llvm/trunk --- Merging r113345 into '.': U lib/Target/ARM/Disassembler/ARMDisassembler.cpp Sending lib/Target/ARM/Disassembler/ARMDisassembler.cpp Sending lib/Target/ARM/Disassembler/ARMDisassemblerCore.h Transmitting file data .. Committed revision 113353. -bw On Sep 7, 2010, at 9:58 PM, NAKAMURA Takumi wrote: > Chris, Applied in r113345! > > 2010/9/8 Chris Lattner : >> Looks great to me, please apply. Should one or both of these be applied to the LLVM 2.8 branch? If so, please email the svn rev #'s to Bill Wendling. Thanks again, > > I have not prepared the branch, excuse me. > > Bill, Would you please pick up my r113345(and Chris' r113255) to the branch? > > ...Takumi From isanbard at gmail.com Wed Sep 8 05:20:30 2010 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 8 Sep 2010 03:20:30 -0700 Subject: [llvm-commits] [llvm] r112664 - in /llvm/trunk: lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td test/CodeGen/ARM/mvncc.ll test/CodeGen/Thumb2/thumb2-mvncc.ll In-Reply-To: <8C81CB0A-63B8-4893-A3EE-F319C0012D52@apple.com> References: <20100831224122.6BA6E2A6C12E@llvm.org> <8C81CB0A-63B8-4893-A3EE-F319C0012D52@apple.com> Message-ID: <23950B4D-6DDC-4B88-94F9-55ACCE0C4218@gmail.com> On Sep 7, 2010, at 11:02 PM, Evan Cheng wrote: > Hi Bill, > > Thanks for doing this but I have some questions. > > On Aug 31, 2010, at 3:41 PM, Bill Wendling wrote: > >> Author: void >> Date: Tue Aug 31 17:41:22 2010 >> New Revision: 112664 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=112664&view=rev >> Log: >> We have a chance for an optimization. Consider this code: >> >> int x(int t) { >> if (t & 256) >> return -26; >> return 0; >> } >> >> We generate this: >> >> tst.w r0, #256 >> mvn r0, #25 >> it eq >> moveq r0, #0 >> >> while gcc generates this: >> >> ands r0, r0, #256 >> it ne >> mvnne r0, #25 >> bx lr > > Is it possible to generate the "and" and comparison at isel time and let the peephole pass get rid of the compare later? I'd prefer to avoid having these instructions like ARM::ANDS. > It's possible. I preferred the isel time change, because it wasn't a hybrid approach. I will try it out though. :-) -bw From kalle.raiskila at nokia.com Wed Sep 8 06:53:38 2010 From: kalle.raiskila at nokia.com (Kalle Raiskila) Date: Wed, 08 Sep 2010 11:53:38 -0000 Subject: [llvm-commits] [llvm] r113355 - in /llvm/trunk: lib/Target/CellSPU/SPUISelLowering.cpp test/CodeGen/CellSPU/shuffles.ll Message-ID: <20100908115338.49D882A6C12C@llvm.org> Author: kraiskil Date: Wed Sep 8 06:53:38 2010 New Revision: 113355 URL: http://llvm.org/viewvc/llvm-project?rev=113355&view=rev Log: Fix CellSPU vector shuffles, again. Some cases of lowering to rotate were miscompiled. Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp llvm/trunk/test/CodeGen/CellSPU/shuffles.ll Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=113355&r1=113354&r2=113355&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Wed Sep 8 06:53:38 2010 @@ -1735,9 +1735,9 @@ unsigned CurrElt = 0; unsigned MaxElts = VecVT.getVectorNumElements(); unsigned PrevElt = 0; - unsigned V0Elt = 0; bool monotonic = true; bool rotate = true; + int rotamt; EVT maskVT; // which of the c?d instructions to use if (EltVT == MVT::i8) { @@ -1781,14 +1781,13 @@ if (PrevElt > 0 && SrcElt < MaxElts) { if ((PrevElt == SrcElt - 1) || (PrevElt == MaxElts - 1 && SrcElt == 0)) { + rotamt = SrcElt-i; PrevElt = SrcElt; - if (SrcElt == 0) - V0Elt = i; } else { rotate = false; } - } else if (i == 0) { - // First time through, need to keep track of previous element + } else if (i == 0 || (PrevElt==0 && SrcElt==1)) { + // First time or after a "wrap around" PrevElt = SrcElt; } else { // This isn't a rotation, takes elements from vector 2 @@ -1813,8 +1812,9 @@ return DAG.getNode(SPUISD::SHUFB, dl, V1.getValueType(), V2, V1, ShufMaskOp); } else if (rotate) { - int rotamt = (MaxElts - V0Elt) * EltVT.getSizeInBits()/8; - + if (rotamt < 0) + rotamt +=MaxElts; + rotamt *= EltVT.getSizeInBits()/8; return DAG.getNode(SPUISD::ROTBYTES_LEFT, dl, V1.getValueType(), V1, DAG.getConstant(rotamt, MVT::i16)); } else { Modified: llvm/trunk/test/CodeGen/CellSPU/shuffles.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/shuffles.ll?rev=113355&r1=113354&r2=113355&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/CellSPU/shuffles.ll (original) +++ llvm/trunk/test/CodeGen/CellSPU/shuffles.ll Wed Sep 8 06:53:38 2010 @@ -39,3 +39,29 @@ ret <4 x float> %rv } +define <2 x i32> @test_v2i32(<4 x i32>%vec) +{ +;CHECK: rotqbyi $3, $3, 4 +;CHECK: bi $lr + %rv = shufflevector <4 x i32> %vec, <4 x i32> undef, <2 x i32> + ret <2 x i32> %rv +} + +define <4 x i32> @test_v4i32_rot8(<4 x i32>%vec) +{ +;CHECK: rotqbyi $3, $3, 8 +;CHECK: bi $lr + %rv = shufflevector <4 x i32> %vec, <4 x i32> undef, + <4 x i32> + ret <4 x i32> %rv +} + +define <4 x i32> @test_v4i32_rot4(<4 x i32>%vec) +{ +;CHECK: rotqbyi $3, $3, 4 +;CHECK: bi $lr + %rv = shufflevector <4 x i32> %vec, <4 x i32> undef, + <4 x i32> + ret <4 x i32> %rv +} + From baldrick at free.fr Wed Sep 8 09:06:36 2010 From: baldrick at free.fr (Duncan Sands) Date: Wed, 08 Sep 2010 14:06:36 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r113357 - in /llvm-gcc-4.2/trunk/gcc: llvm-convert.cpp llvm-internal.h Message-ID: <20100908140636.D32EF2A6C12C@llvm.org> Author: baldrick Date: Wed Sep 8 09:06:36 2010 New Revision: 113357 URL: http://llvm.org/viewvc/llvm-project?rev=113357&view=rev Log: The _Unwind_Resume_or_Rethrow fixup code in DwarfEHPrepare needs llvm.eh.catch.all.value in order to do its job, but llvm-gcc was only outputting it if the original code had a catch-all in it. The result was that code that uses cleanups and catches some exceptions (but not all) did not always work correctly. So just always output llvm.eh.catch.all.value when doing exception handling, fixing several failures in the Ada ACATS test suite. Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp llvm-gcc-4.2/trunk/gcc/llvm-internal.h Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=113357&r1=113356&r2=113357&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Wed Sep 8 09:06:36 2010 @@ -188,6 +188,7 @@ GreatestAlignment = TheTarget->getFrameInfo()->getStackAlignment(); SeenVLA = NULL; + CatchAll = 0; ExceptionValue = 0; ExceptionSelectorValue = 0; FuncEHException = 0; @@ -2151,6 +2152,23 @@ Intrinsic::eh_selector); FuncEHGetTypeID = Intrinsic::getDeclaration(TheModule, Intrinsic::eh_typeid_for); + + CatchAll = TheModule->getGlobalVariable("llvm.eh.catch.all.value"); + if (!CatchAll && lang_eh_catch_all) { + Constant *Init = 0; + tree catch_all_type = lang_eh_catch_all(); + if (catch_all_type == NULL_TREE) + // Use a C++ style null catch-all object. + Init = Constant::getNullValue(Type::getInt8PtrTy(Context)); + else + // This language has a type that catches all others. + Init = cast(Emit(catch_all_type, 0)); + + CatchAll = new GlobalVariable(*TheModule, Init->getType(), true, + GlobalVariable::LinkOnceAnyLinkage, + Init, "llvm.eh.catch.all.value"); + CatchAll->setSection("llvm.metadata"); + } } /// getPostPad - Return the post landing pad for the given exception handling @@ -2204,7 +2222,6 @@ bool HasCleanup = false; bool HasCatchAll = false; - static GlobalVariable *CatchAll = 0; for (std::vector::iterator I = Handlers.begin(), E = Handlers.end(); I != E; ++I) { @@ -2231,17 +2248,8 @@ tree TypeList = get_eh_type_list(region); if (!TypeList) { - // Catch-all - push a null pointer. - if (!CatchAll) { - Constant *Init = - Constant::getNullValue(Type::getInt8PtrTy(Context)); - - CatchAll = new GlobalVariable(*TheModule, Init->getType(), true, - GlobalVariable::LinkOnceAnyLinkage, - Init, "llvm.eh.catch.all.value"); - CatchAll->setSection("llvm.metadata"); - } - + // Catch-all - push the catch-all object. + assert(CatchAll && "Language did not define lang_eh_catch_all?"); Args.push_back(CatchAll); HasCatchAll = true; } else { @@ -2268,23 +2276,7 @@ // Some exceptions from this region may not be caught by any handler. // Since invokes are required to branch to the unwind label no matter // what exception is being unwound, append a catch-all. - - if (!CatchAll) { - Constant *Init = 0; - tree catch_all_type = lang_eh_catch_all(); - if (catch_all_type == NULL_TREE) - // Use a C++ style null catch-all object. - Init = Constant::getNullValue(Type::getInt8PtrTy(Context)); - else - // This language has a type that catches all others. - Init = cast(Emit(catch_all_type, 0)); - - CatchAll = new GlobalVariable(*TheModule, Init->getType(), true, - GlobalVariable::LinkOnceAnyLinkage, - Init, "llvm.eh.catch.all.value"); - CatchAll->setSection("llvm.metadata"); - } - + assert(CatchAll && "Language did not define lang_eh_catch_all?"); Args.push_back(CatchAll); } } Modified: llvm-gcc-4.2/trunk/gcc/llvm-internal.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-internal.h?rev=113357&r1=113356&r2=113357&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-internal.h (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-internal.h Wed Sep 8 09:06:36 2010 @@ -320,6 +320,9 @@ /// PostPads - The post landing pad for a given EH region. IndexedMap PostPads; + /// CatchAll - Language specific catch-all object. + GlobalVariable *CatchAll; + /// ExceptionValue - Is the local to receive the current exception. Value *ExceptionValue; From rdivacky at freebsd.org Wed Sep 8 09:29:45 2010 From: rdivacky at freebsd.org (Roman Divacky) Date: Wed, 08 Sep 2010 14:29:45 -0000 Subject: [llvm-commits] [llvm] r113358 - /llvm/trunk/lib/MC/ELFObjectWriter.cpp Message-ID: <20100908142945.B838B2A6C12C@llvm.org> Author: rdivacky Date: Wed Sep 8 09:29:45 2010 New Revision: 113358 URL: http://llvm.org/viewvc/llvm-project?rev=113358&view=rev Log: Unresolved weak symbols have value equal zero. Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=113358&r1=113357&r2=113358&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Wed Sep 8 09:29:45 2010 @@ -364,7 +364,7 @@ if (Data.isCommon() && Data.isExternal()) Value = Data.getCommonAlignment(); - if (!Data.isCommon()) + if (!Data.isCommon() && !(Data.getFlags() & ELF_STB_Weak)) if (MCFragment *FF = Data.getFragment()) Value = Layout.getSymbolAddress(&Data) - Layout.getSectionAddress(FF->getParent()); From grosser at fim.uni-passau.de Wed Sep 8 10:02:51 2010 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Wed, 08 Sep 2010 15:02:51 -0000 Subject: [llvm-commits] [llvm] r113360 - /llvm/trunk/tools/opt/opt.cpp Message-ID: <20100908150251.C0BC62A6C12D@llvm.org> Author: grosser Date: Wed Sep 8 10:02:51 2010 New Revision: 113360 URL: http://llvm.org/viewvc/llvm-project?rev=113360&view=rev Log: Execute all Pass Printers even if -quiet is set. Follow the same logic in the LoopPass, ModulePass and CallGraphSCCPass printers, as it was already used in the BasicBlockPass and FunctionPass printers. This is more consistent. The other option would have been to completely disable dumping the analysis information. However, as this information is the only information printed if the -analysis flag is set, calling opt would not do anything at all. Modified: llvm/trunk/tools/opt/opt.cpp Modified: llvm/trunk/tools/opt/opt.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/opt/opt.cpp?rev=113360&r1=113359&r2=113360&view=diff ============================================================================== --- llvm/trunk/tools/opt/opt.cpp (original) +++ llvm/trunk/tools/opt/opt.cpp Wed Sep 8 10:02:51 2010 @@ -148,17 +148,16 @@ } virtual bool runOnSCC(CallGraphSCC &SCC) { - if (!Quiet) { + if (!Quiet) Out << "Printing analysis '" << PassToPrint->getPassName() << "':\n"; - for (CallGraphSCC::iterator I = SCC.begin(), E = SCC.end(); I != E; ++I) { - Function *F = (*I)->getFunction(); - if (F) - getAnalysisID(PassToPrint->getTypeInfo()).print(Out, - F->getParent()); - } - } // Get and print pass... + for (CallGraphSCC::iterator I = SCC.begin(), E = SCC.end(); I != E; ++I) { + Function *F = (*I)->getFunction(); + if (F) + getAnalysisID(PassToPrint->getTypeInfo()).print(Out, + F->getParent()); + } return false; } @@ -185,12 +184,11 @@ } virtual bool runOnModule(Module &M) { - if (!Quiet) { + if (!Quiet) Out << "Printing analysis '" << PassToPrint->getPassName() << "':\n"; - getAnalysisID(PassToPrint->getTypeInfo()).print(Out, &M); - } // Get and print pass... + getAnalysisID(PassToPrint->getTypeInfo()).print(Out, &M); return false; } @@ -216,10 +214,10 @@ } virtual bool runOnFunction(Function &F) { - if (!Quiet) { + if (!Quiet) Out << "Printing analysis '" << PassToPrint->getPassName() << "' for function '" << F.getName() << "':\n"; - } + // Get and print pass... getAnalysisID(PassToPrint->getTypeInfo()).print(Out, F.getParent()); @@ -250,12 +248,12 @@ virtual bool runOnLoop(Loop *L, LPPassManager &LPM) { - if (!Quiet) { + if (!Quiet) Out << "Printing analysis '" << PassToPrint->getPassName() << "':\n"; - getAnalysisID(PassToPrint->getTypeInfo()).print(Out, - L->getHeader()->getParent()->getParent()); - } + // Get and print pass... + getAnalysisID(PassToPrint->getTypeInfo()).print(Out, + L->getHeader()->getParent()->getParent()); return false; } @@ -282,10 +280,9 @@ } virtual bool runOnBasicBlock(BasicBlock &BB) { - if (!Quiet) { + if (!Quiet) Out << "Printing Analysis info for BasicBlock '" << BB.getName() << "': Pass " << PassToPrint->getPassName() << ":\n"; - } // Get and print pass... getAnalysisID(PassToPrint->getTypeInfo()).print(Out, From grosser at fim.uni-passau.de Wed Sep 8 10:02:47 2010 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Wed, 08 Sep 2010 15:02:47 -0000 Subject: [llvm-commits] [llvm] r113359 - /llvm/trunk/tools/opt/opt.cpp Message-ID: <20100908150247.4FB082A6C12C@llvm.org> Author: grosser Date: Wed Sep 8 10:02:47 2010 New Revision: 113359 URL: http://llvm.org/viewvc/llvm-project?rev=113359&view=rev Log: Include original pass name in the PassPrinter's name. Modified: llvm/trunk/tools/opt/opt.cpp Modified: llvm/trunk/tools/opt/opt.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/opt/opt.cpp?rev=113359&r1=113358&r2=113359&view=diff ============================================================================== --- llvm/trunk/tools/opt/opt.cpp (original) +++ llvm/trunk/tools/opt/opt.cpp Wed Sep 8 10:02:47 2010 @@ -139,8 +139,13 @@ static char ID; const PassInfo *PassToPrint; raw_ostream &Out; + std::string PassName; + CallGraphSCCPassPrinter(const PassInfo *PI, raw_ostream &out) : - CallGraphSCCPass(ID), PassToPrint(PI), Out(out) {} + CallGraphSCCPass(ID), PassToPrint(PI), Out(out) { + std::string PassToPrintName = PassToPrint->getPassName(); + PassName = "CallGraphSCCPass Printer: " + PassToPrintName; + } virtual bool runOnSCC(CallGraphSCC &SCC) { if (!Quiet) { @@ -157,7 +162,7 @@ return false; } - virtual const char *getPassName() const { return "'Pass' Printer"; } + virtual const char *getPassName() const { return PassName.c_str(); } virtual void getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequiredID(PassToPrint->getTypeInfo()); @@ -171,8 +176,13 @@ static char ID; const PassInfo *PassToPrint; raw_ostream &Out; + std::string PassName; + ModulePassPrinter(const PassInfo *PI, raw_ostream &out) - : ModulePass(ID), PassToPrint(PI), Out(out) {} + : ModulePass(ID), PassToPrint(PI), Out(out) { + std::string PassToPrintName = PassToPrint->getPassName(); + PassName = "ModulePass Printer: " + PassToPrintName; + } virtual bool runOnModule(Module &M) { if (!Quiet) { @@ -184,7 +194,7 @@ return false; } - virtual const char *getPassName() const { return "'Pass' Printer"; } + virtual const char *getPassName() const { return PassName.c_str(); } virtual void getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequiredID(PassToPrint->getTypeInfo()); @@ -197,8 +207,13 @@ const PassInfo *PassToPrint; raw_ostream &Out; static char ID; + std::string PassName; + FunctionPassPrinter(const PassInfo *PI, raw_ostream &out) - : FunctionPass(ID), PassToPrint(PI), Out(out) {} + : FunctionPass(ID), PassToPrint(PI), Out(out) { + std::string PassToPrintName = PassToPrint->getPassName(); + PassName = "FunctionPass Printer: " + PassToPrintName; + } virtual bool runOnFunction(Function &F) { if (!Quiet) { @@ -211,7 +226,7 @@ return false; } - virtual const char *getPassName() const { return "FunctionPass Printer"; } + virtual const char *getPassName() const { return PassName.c_str(); } virtual void getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequiredID(PassToPrint->getTypeInfo()); @@ -225,8 +240,14 @@ static char ID; const PassInfo *PassToPrint; raw_ostream &Out; + std::string PassName; + LoopPassPrinter(const PassInfo *PI, raw_ostream &out) : - LoopPass(ID), PassToPrint(PI), Out(out) {} + LoopPass(ID), PassToPrint(PI), Out(out) { + std::string PassToPrintName = PassToPrint->getPassName(); + PassName = "LoopPass Printer: " + PassToPrintName; + } + virtual bool runOnLoop(Loop *L, LPPassManager &LPM) { if (!Quiet) { @@ -238,7 +259,7 @@ return false; } - virtual const char *getPassName() const { return "'Pass' Printer"; } + virtual const char *getPassName() const { return PassName.c_str(); } virtual void getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequiredID(PassToPrint->getTypeInfo()); @@ -252,8 +273,13 @@ const PassInfo *PassToPrint; raw_ostream &Out; static char ID; + std::string PassName; + BasicBlockPassPrinter(const PassInfo *PI, raw_ostream &out) - : BasicBlockPass(ID), PassToPrint(PI), Out(out) {} + : BasicBlockPass(ID), PassToPrint(PI), Out(out) { + std::string PassToPrintName = PassToPrint->getPassName(); + PassName = "BasicBlockPass Printer: " + PassToPrintName; + } virtual bool runOnBasicBlock(BasicBlock &BB) { if (!Quiet) { @@ -267,7 +293,7 @@ return false; } - virtual const char *getPassName() const { return "BasicBlockPass Printer"; } + virtual const char *getPassName() const { return PassName.c_str(); } virtual void getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequiredID(PassToPrint->getTypeInfo()); From baldrick at free.fr Wed Sep 8 10:04:57 2010 From: baldrick at free.fr (Duncan Sands) Date: Wed, 08 Sep 2010 15:04:57 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r113361 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Message-ID: <20100908150457.668B12A6C12C@llvm.org> Author: baldrick Date: Wed Sep 8 10:04:57 2010 New Revision: 113361 URL: http://llvm.org/viewvc/llvm-project?rev=113361&view=rev Log: Forgot this somehow in previous patch: if llvm.eh.catch.all.value is not used anywhere then the optimizers will delete it, however it may still be needed by the URoR fixup code in DwarfEHPrepare. Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=113361&r1=113360&r2=113361&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Wed Sep 8 10:04:57 2010 @@ -2168,6 +2168,7 @@ GlobalVariable::LinkOnceAnyLinkage, Init, "llvm.eh.catch.all.value"); CatchAll->setSection("llvm.metadata"); + AttributeUsedGlobals.insert(CatchAll); } } From baldrick at free.fr Wed Sep 8 10:59:52 2010 From: baldrick at free.fr (Duncan Sands) Date: Wed, 08 Sep 2010 15:59:52 -0000 Subject: [llvm-commits] [test-suite] r113362 - /test-suite/trunk/SingleSource/Regression/C++/EH/inlined_cleanup.cpp Message-ID: <20100908155952.EDBC52A6C12C@llvm.org> Author: baldrick Date: Wed Sep 8 10:59:52 2010 New Revision: 113362 URL: http://llvm.org/viewvc/llvm-project?rev=113362&view=rev Log: Testcase for llvm-gcc commits 113357 and 113361. With those commits the output for llvm-gcc+opt+llc matches the native gcc output. Added: test-suite/trunk/SingleSource/Regression/C++/EH/inlined_cleanup.cpp Added: test-suite/trunk/SingleSource/Regression/C++/EH/inlined_cleanup.cpp URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/Regression/C%2B%2B/EH/inlined_cleanup.cpp?rev=113362&view=auto ============================================================================== --- test-suite/trunk/SingleSource/Regression/C++/EH/inlined_cleanup.cpp (added) +++ test-suite/trunk/SingleSource/Regression/C++/EH/inlined_cleanup.cpp Wed Sep 8 10:59:52 2010 @@ -0,0 +1,22 @@ +#include + +class Cleanup { +public: + ~Cleanup() { + printf("In cleanup!\n"); + } +}; + +static void foo() { + Cleanup C; + throw 3; +} + +int main(void) { + try { + foo(); + } catch (int i) { + printf("Caught %d!\n", i); + } + return 0; +} From grosbach at apple.com Wed Sep 8 12:05:45 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 08 Sep 2010 17:05:45 -0000 Subject: [llvm-commits] [llvm] r113365 - /llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Message-ID: <20100908170546.042F72A6C12C@llvm.org> Author: grosbach Date: Wed Sep 8 12:05:45 2010 New Revision: 113365 URL: http://llvm.org/viewvc/llvm-project?rev=113365&view=rev Log: Add missing assert Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=113365&r1=113364&r2=113365&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Wed Sep 8 12:05:45 2010 @@ -1057,8 +1057,11 @@ if (isFixed) { FrameReg = getFrameRegister(MF); Offset = FPOffset; - } else if (MFI->hasVarSizedObjects()) + } else if (MFI->hasVarSizedObjects()) { + assert(hasBasePointer(MF) && + "VLAs and dynamic stack alignment, but missing base pointer!"); FrameReg = BasePtr; + } return Offset; } From grosbach at apple.com Wed Sep 8 12:22:12 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 08 Sep 2010 17:22:12 -0000 Subject: [llvm-commits] [llvm] r113366 - /llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Message-ID: <20100908172212.F024A2A6C12C@llvm.org> Author: grosbach Date: Wed Sep 8 12:22:12 2010 New Revision: 113366 URL: http://llvm.org/viewvc/llvm-project?rev=113366&view=rev Log: Be more careful about when to do dynamic stack realignment. Since we have an option to disable base pointer usage, pay attention to it when deciding if we can realign (if no base pointer and VLAs, we can't). Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=113366&r1=113365&r2=113366&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Wed Sep 8 12:22:12 2010 @@ -667,8 +667,14 @@ } bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const { + const MachineFrameInfo *MFI = MF.getFrameInfo(); const ARMFunctionInfo *AFI = MF.getInfo(); - return (RealignStack && !AFI->isThumb1OnlyFunction()); + // We can't realign the stack if: + // 1. Dynamic stack realignment is explicitly disabled, + // 2. This is a Thumb1 function (it's not useful, so we don't bother), or + // 3. There are VLAs in the function and the base pointer is disabled. + return (RealignStack && !AFI->isThumb1OnlyFunction() && + (!MFI->hasVarSizedObjects() || EnableBasePointer)); } bool ARMBaseRegisterInfo:: @@ -1890,7 +1896,8 @@ AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); AFI->setDPRCalleeSavedAreaSize(DPRCSSize); - // If we need dynamic stack realignment, do it here. + // If we need dynamic stack realignment, do it here. Be paranoid and make + // sure if we also have VLAs, we have a base pointer for frame access. if (needsStackRealignment(MF)) { unsigned MaxAlign = MFI->getMaxAlignment(); assert (!AFI->isThumb1OnlyFunction()); From bruno.cardoso at gmail.com Wed Sep 8 12:43:25 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Wed, 08 Sep 2010 17:43:25 -0000 Subject: [llvm-commits] [llvm] r113369 - in /llvm/trunk/lib/Target/X86: X86ISelLowering.cpp X86InstrSSE.td Message-ID: <20100908174326.25B482A6C12C@llvm.org> Author: bruno Date: Wed Sep 8 12:43:25 2010 New Revision: 113369 URL: http://llvm.org/viewvc/llvm-project?rev=113369&view=rev Log: x86 vector shuffle lowering now relies only on target specific nodes to emit shuffles and don't do isel mask matching anymore. - Add the selection of the remaining shuffle opcode (movddup) - Introduce two new functions to "recognize" where we may get potential folds and add several comments to them explaining why they are not yet in the desidered shape. - Add more patterns to fallback the case where we select a specific shuffle opcode as if it could fold a load, but it can't, so remap to a valid instruction. - Add a couple of FIXMEs to address in the following days once there's a good solution to the current folding problem. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=113369&r1=113368&r2=113369&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Sep 8 12:43:25 2010 @@ -2604,6 +2604,7 @@ case X86ISD::MOVLPD: case X86ISD::MOVSHDUP: case X86ISD::MOVSLDUP: + case X86ISD::MOVDDUP: case X86ISD::MOVSS: case X86ISD::MOVSD: case X86ISD::UNPCKLPS: @@ -2629,6 +2630,7 @@ default: llvm_unreachable("Unknown x86 shuffle node"); case X86ISD::MOVSHDUP: case X86ISD::MOVSLDUP: + case X86ISD::MOVDDUP: return DAG.getNode(Opc, dl, VT, V1); } @@ -3645,9 +3647,6 @@ /// PromoteSplat - Promote a splat of v4i32, v8i16 or v16i8 to v4f32. static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) { - if (SV->getValueType(0).getVectorNumElements() <= 4) - return SDValue(SV, 0); - EVT PVT = MVT::v4f32; EVT VT = SV->getValueType(0); DebugLoc dl = SV->getDebugLoc(); @@ -5138,6 +5137,98 @@ return false; } +// FIXME: the version above should always be used. Since there's +// a bug where several vector shuffles can't be folded because the +// DAG is not updated during lowering and a node claims to have two +// uses while it only has one, use this version, and let isel match +// another instruction if the load really happens to have more than +// one use. Remove this version after this bug get fixed. +static bool RelaxedMayFoldVectorLoad(SDValue V) { + if (V.hasOneUse() && V.getOpcode() == ISD::BIT_CONVERT) + V = V.getOperand(0); + if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) + V = V.getOperand(0); + if (ISD::isNormalLoad(V.getNode())) + return true; + return false; +} + +/// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by +/// a vector extract, and if both can be later optimized into a single load. +/// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked +/// here because otherwise a target specific shuffle node is going to be +/// emitted for this shuffle, and the optimization not done. +/// FIXME: This is probably not the best approach, but fix the problem +/// until the right path is decided. +static +bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG, + const TargetLowering &TLI) { + EVT VT = V.getValueType(); + ShuffleVectorSDNode *SVOp = dyn_cast(V); + + // Be sure that the vector shuffle is present in a pattern like this: + // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr) + if (!V.hasOneUse()) + return false; + + SDNode *N = *V.getNode()->use_begin(); + if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT) + return false; + + SDValue EltNo = N->getOperand(1); + if (!isa(EltNo)) + return false; + + // If the bit convert changed the number of elements, it is unsafe + // to examine the mask. + bool HasShuffleIntoBitcast = false; + if (V.getOpcode() == ISD::BIT_CONVERT) { + EVT SrcVT = V.getOperand(0).getValueType(); + if (SrcVT.getVectorNumElements() != VT.getVectorNumElements()) + return false; + V = V.getOperand(0); + HasShuffleIntoBitcast = true; + } + + // Select the input vector, guarding against out of range extract vector. + unsigned NumElems = VT.getVectorNumElements(); + unsigned Elt = cast(EltNo)->getZExtValue(); + int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt); + V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1); + + // Skip one more bit_convert if necessary + if (V.getOpcode() == ISD::BIT_CONVERT) + V = V.getOperand(0); + + if (ISD::isNormalLoad(V.getNode())) { + // Is the original load suitable? + LoadSDNode *LN0 = cast(V); + + // FIXME: avoid the multi-use bug that is preventing lots of + // of foldings to be detected, this is still wrong of course, but + // give the temporary desired behavior, and if it happens that + // the load has real more uses, during isel it will not fold, and + // will generate poor code. + if (!LN0 || LN0->isVolatile()) // || !LN0->hasOneUse() + return false; + + if (!HasShuffleIntoBitcast) + return true; + + // If there's a bitcast before the shuffle, check if the load type and + // alignment is valid. + unsigned Align = LN0->getAlignment(); + unsigned NewAlign = + TLI.getTargetData()->getABITypeAlignment( + VT.getTypeForEVT(*DAG.getContext())); + + if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT)) + return false; + } + + return true; +} + static SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) { @@ -5253,6 +5344,7 @@ static SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG, + const TargetLowering &TLI, const X86Subtarget *Subtarget) { ShuffleVectorSDNode *SVOp = cast(Op); EVT VT = Op.getValueType(); @@ -5263,9 +5355,23 @@ if (isZeroShuffle(SVOp)) return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl); - // Promote splats to v4f32. - if (SVOp->isSplat()) + // Handle splat operations + if (SVOp->isSplat()) { + // Special case, this is the only place now where it's + // allowed to return a vector_shuffle operation without + // using a target specific node, because *hopefully* it + // will be optimized away by the dag combiner. + if (VT.getVectorNumElements() <= 4 && + CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI)) + return Op; + + // Handle splats by matching through known masks + if (VT.getVectorNumElements() <= 4) + return SDValue(); + + // Canonize all of the remaining to v4f32. return PromoteSplat(SVOp, DAG); + } // If the shuffle can be profitably rewritten as a narrower shuffle, then // do it! @@ -5336,7 +5442,7 @@ // Normalize the input vectors. Here splats, zeroed vectors, profitable // narrowing and commutation of operands should be handled. The actual code // doesn't include all of those, work in progress... - SDValue NewOp = NormalizeVectorShuffle(Op, DAG, Subtarget); + SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget); if (NewOp.getNode()) return NewOp; @@ -5349,6 +5455,18 @@ if (VT != MVT::v2i64 && VT != MVT::v2f64) return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG); + if (X86::isMOVDDUPMask(SVOp) && HasSSE3 && V2IsUndef && + RelaxedMayFoldVectorLoad(V1) && !isMMX) + return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG); + + if (!isMMX && X86::isMOVHLPS_v_undef_Mask(SVOp)) + return getMOVHighToLow(Op, dl, DAG); + + // Use to match splats + if (HasSSE2 && X86::isUNPCKHMask(SVOp) && V2IsUndef && + (VT == MVT::v2f64 || VT == MVT::v2i64)) + return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG); + if (X86::isPSHUFDMask(SVOp)) { // The actual implementation will match the mask in the if above and then // during isel it can match several different instructions, not only pshufd Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=113369&r1=113368&r2=113369&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Sep 8 12:43:25 2010 @@ -5820,6 +5820,14 @@ (MOVLHPSrr VR128:$src1, VR128:$src2)>; def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)), (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>; +// FIXME: Instead of X86Movddup, there should be a X86Movlhps here, the problem +// is during lowering, where it's not possible to recognize the load fold cause +// it has two uses through a bitcast. One use disappears at isel time and the +// fold opportunity reappears. +def : Pat<(v2i64 (X86Movddup VR128:$src)), + (MOVLHPSrr VR128:$src, VR128:$src)>; +def : Pat<(v4f32 (X86Movddup VR128:$src)), + (MOVLHPSrr VR128:$src, VR128:$src)>; // Shuffle with MOVLHPD def : Pat<(v2f64 (X86Movlhpd VR128:$src1, From evan.cheng at apple.com Wed Sep 8 13:01:08 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 8 Sep 2010 11:01:08 -0700 Subject: [llvm-commits] [llvm] r112664 - in /llvm/trunk: lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td test/CodeGen/ARM/mvncc.ll test/CodeGen/Thumb2/thumb2-mvncc.ll In-Reply-To: <23950B4D-6DDC-4B88-94F9-55ACCE0C4218@gmail.com> References: <20100831224122.6BA6E2A6C12E@llvm.org> <8C81CB0A-63B8-4893-A3EE-F319C0012D52@apple.com> <23950B4D-6DDC-4B88-94F9-55ACCE0C4218@gmail.com> Message-ID: <4B718D16-ADCF-4C23-B908-6C32A1E6D3A2@apple.com> On Sep 8, 2010, at 3:20 AM, Bill Wendling wrote: > On Sep 7, 2010, at 11:02 PM, Evan Cheng wrote: > >> Hi Bill, >> >> Thanks for doing this but I have some questions. >> >> On Aug 31, 2010, at 3:41 PM, Bill Wendling wrote: >> >>> Author: void >>> Date: Tue Aug 31 17:41:22 2010 >>> New Revision: 112664 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=112664&view=rev >>> Log: >>> We have a chance for an optimization. Consider this code: >>> >>> int x(int t) { >>> if (t & 256) >>> return -26; >>> return 0; >>> } >>> >>> We generate this: >>> >>> tst.w r0, #256 >>> mvn r0, #25 >>> it eq >>> moveq r0, #0 >>> >>> while gcc generates this: >>> >>> ands r0, r0, #256 >>> it ne >>> mvnne r0, #25 >>> bx lr >> >> Is it possible to generate the "and" and comparison at isel time and let the peephole pass get rid of the compare later? I'd prefer to avoid having these instructions like ARM::ANDS. >> > It's possible. I preferred the isel time change, because it wasn't a hybrid approach. I will try it out though. :-) Thanks. IMO, one of the big advantage of the machine instruction peephole pass is it avoid having these instruction variants. Evan > > -bw > From resistor at mac.com Wed Sep 8 13:03:32 2010 From: resistor at mac.com (Owen Anderson) Date: Wed, 08 Sep 2010 18:03:32 -0000 Subject: [llvm-commits] [llvm] r113374 - in /llvm/trunk: include/llvm/LLVMContext.h lib/VMCore/LLVMContext.cpp lib/VMCore/LLVMContextImpl.cpp lib/VMCore/LLVMContextImpl.h lib/VMCore/Module.cpp Message-ID: <20100908180332.EB7FB2A6C12C@llvm.org> Author: resistor Date: Wed Sep 8 13:03:32 2010 New Revision: 113374 URL: http://llvm.org/viewvc/llvm-project?rev=113374&view=rev Log: Clarify the ownership model of LLVMContext and Module. Namely, contexts own modules are instantiated in them. If the context is deleted, all of its owned modules are also deleted. Modified: llvm/trunk/include/llvm/LLVMContext.h llvm/trunk/lib/VMCore/LLVMContext.cpp llvm/trunk/lib/VMCore/LLVMContextImpl.cpp llvm/trunk/lib/VMCore/LLVMContextImpl.h llvm/trunk/lib/VMCore/Module.cpp Modified: llvm/trunk/include/llvm/LLVMContext.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/LLVMContext.h?rev=113374&r1=113373&r2=113374&view=diff ============================================================================== --- llvm/trunk/include/llvm/LLVMContext.h (original) +++ llvm/trunk/include/llvm/LLVMContext.h Wed Sep 8 13:03:32 2010 @@ -20,6 +20,7 @@ class LLVMContextImpl; class StringRef; class Instruction; +class Module; template class SmallVectorImpl; /// This is an important class for using LLVM in a threaded context. It @@ -37,6 +38,13 @@ LLVMContext(); ~LLVMContext(); + /// addModule - Register a module as being instantiated in this context. If + /// the context is deleted, the module will be deleted as well. + void addModule(Module*); + + /// removeModule - Unregister a module from this context. + void removeModule(Module*); + // Pinned metadata names, which always have the same value. This is a // compile-time performance optimization, not a correctness optimization. enum { Modified: llvm/trunk/lib/VMCore/LLVMContext.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/LLVMContext.cpp?rev=113374&r1=113373&r2=113374&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/LLVMContext.cpp (original) +++ llvm/trunk/lib/VMCore/LLVMContext.cpp Wed Sep 8 13:03:32 2010 @@ -34,6 +34,14 @@ } LLVMContext::~LLVMContext() { delete pImpl; } +void LLVMContext::addModule(Module *M) { + pImpl->OwnedModules.insert(M); +} + +void LLVMContext::removeModule(Module *M) { + pImpl->OwnedModules.erase(M); +} + //===----------------------------------------------------------------------===// // Recoverable Backend Errors //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/VMCore/LLVMContextImpl.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/LLVMContextImpl.cpp?rev=113374&r1=113373&r2=113374&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/LLVMContextImpl.cpp (original) +++ llvm/trunk/lib/VMCore/LLVMContextImpl.cpp Wed Sep 8 13:03:32 2010 @@ -12,6 +12,7 @@ //===----------------------------------------------------------------------===// #include "LLVMContextImpl.h" +#include "llvm/Module.h" #include using namespace llvm; @@ -51,6 +52,15 @@ } LLVMContextImpl::~LLVMContextImpl() { + // NOTE: We need to delete the contents of OwnedModules, but we have to + // duplicate it into a temporary vector, because the destructor of Module + // will try to remove itself from OwnedModules set. This would cause + // iterator invalidation if we iterated on the set directly. + std::vector Modules(OwnedModules.begin(), OwnedModules.end()); + for (std::vector::iterator I = Modules.begin(), E = Modules.end(); + I != E; ++I) + delete *I; + std::for_each(ExprConstants.map_begin(), ExprConstants.map_end(), DropReferences()); std::for_each(ArrayConstants.map_begin(), ArrayConstants.map_end(), Modified: llvm/trunk/lib/VMCore/LLVMContextImpl.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/LLVMContextImpl.h?rev=113374&r1=113373&r2=113374&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/LLVMContextImpl.h (original) +++ llvm/trunk/lib/VMCore/LLVMContextImpl.h Wed Sep 8 13:03:32 2010 @@ -115,6 +115,10 @@ class LLVMContextImpl { public: + /// OwnedModules - The set of modules instantiated in this context, and which + /// will be automatically deleted if this context is deleted. + SmallPtrSet OwnedModules; + void *InlineAsmDiagHandler, *InlineAsmDiagContext; typedef DenseMap(); + Context.addModule(this); } Module::~Module() { + Context.removeModule(this); dropAllReferences(); GlobalList.clear(); FunctionList.clear(); From clattner at apple.com Wed Sep 8 13:07:27 2010 From: clattner at apple.com (Chris Lattner) Date: Wed, 8 Sep 2010 11:07:27 -0700 Subject: [llvm-commits] [llvm] r113374 - in /llvm/trunk: include/llvm/LLVMContext.h lib/VMCore/LLVMContext.cpp lib/VMCore/LLVMContextImpl.cpp lib/VMCore/LLVMContextImpl.h lib/VMCore/Module.cpp In-Reply-To: <20100908180332.EB7FB2A6C12C@llvm.org> References: <20100908180332.EB7FB2A6C12C@llvm.org> Message-ID: On Sep 8, 2010, at 11:03 AM, Owen Anderson wrote: > Author: resistor > Date: Wed Sep 8 13:03:32 2010 > New Revision: 113374 > > URL: http://llvm.org/viewvc/llvm-project?rev=113374&view=rev > Log: > Clarify the ownership model of LLVMContext and Module. Namely, contexts own > modules are instantiated in them. If the context is deleted, all of its owned > modules are also deleted. Nice! Please make add/removeModule private members of LLVMContext (friend'ing Module) so that other clients of LLVMContext don't worry about them. Alternatively, maybe it is better to put add/removeModule on LLVMContextImpl since Module can see it, then it would be really clearly an implementation detail. Thanks Owen, -Chris From rdivacky at freebsd.org Wed Sep 8 13:08:40 2010 From: rdivacky at freebsd.org (Roman Divacky) Date: Wed, 08 Sep 2010 18:08:40 -0000 Subject: [llvm-commits] [llvm] r113375 - in /llvm/trunk/lib/MC: ELFObjectWriter.cpp MCELFStreamer.cpp Message-ID: <20100908180840.4363A2A6C12C@llvm.org> Author: rdivacky Date: Wed Sep 8 13:08:40 2010 New Revision: 113375 URL: http://llvm.org/viewvc/llvm-project?rev=113375&view=rev Log: ELF_STB_Local is 0 so setting and checking it must be done specially Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp llvm/trunk/lib/MC/MCELFStreamer.cpp Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=113375&r1=113374&r2=113375&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Wed Sep 8 13:08:40 2010 @@ -439,7 +439,7 @@ assert((Data.getFlags() & ELF_STB_Global) && "External symbol requires STB_GLOBAL flag"); WriteSymbol(F, MSD, Layout); - if (Data.getFlags() & ELF_STB_Local) + if ((Data.getFlags() & (0xf << ELF_STB_Shift)) == ELF_STB_Local) LastLocalSymbolIndex++; } @@ -448,7 +448,7 @@ MCSymbolData &Data = *MSD.SymbolData; Data.setFlags(Data.getFlags() | ELF_STB_Global); WriteSymbol(F, MSD, Layout); - if (Data.getFlags() & ELF_STB_Local) + if ((Data.getFlags() & (0xf << ELF_STB_Shift)) == ELF_STB_Local) LastLocalSymbolIndex++; } } Modified: llvm/trunk/lib/MC/MCELFStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCELFStreamer.cpp?rev=113375&r1=113374&r2=113375&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCELFStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCELFStreamer.cpp Wed Sep 8 13:08:40 2010 @@ -196,7 +196,9 @@ break; case MCSA_Local: - SD.setFlags(SD.getFlags() | ELF_STB_Local); + // ELF_STB_Local is 0, so zero the ELF_STB area + // SD.getFlags() | ELF_STB_Local is a NOP + SD.setFlags(SD.getFlags() & ~(0xf << ELF_STB_Shift)); break; case MCSA_ELF_TypeFunction: From bruno.cardoso at gmail.com Wed Sep 8 13:12:31 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Wed, 08 Sep 2010 18:12:31 -0000 Subject: [llvm-commits] [llvm] r113378 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20100908181231.73AE02A6C12C@llvm.org> Author: bruno Date: Wed Sep 8 13:12:31 2010 New Revision: 113378 URL: http://llvm.org/viewvc/llvm-project?rev=113378&view=rev Log: Minor change. Fix comments and remove unused and redundant code Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=113378&r1=113377&r2=113378&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Sep 8 13:12:31 2010 @@ -4891,10 +4891,10 @@ } /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide -/// ones, or rewriting v4i32 / v2i32 as 2 wide ones if possible. This can be +/// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be /// done when every pair / quad of shuffle mask elements point to elements in /// the right sequence. e.g. -/// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15> +/// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15> static SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, DebugLoc dl) { @@ -4903,8 +4903,7 @@ SDValue V2 = SVOp->getOperand(1); unsigned NumElems = VT.getVectorNumElements(); unsigned NewWidth = (NumElems == 4) ? 2 : 4; - EVT MaskVT = (NewWidth == 4) ? MVT::v4i16 : MVT::v2i32; - EVT NewVT = MaskVT; + EVT NewVT; switch (VT.getSimpleVT().SimpleTy) { default: assert(false && "Unexpected!"); case MVT::v4f32: NewVT = MVT::v2f64; break; @@ -4913,12 +4912,6 @@ case MVT::v16i8: NewVT = MVT::v4i32; break; } - if (NewWidth == 2) { - if (VT.isInteger()) - NewVT = MVT::v2i64; - else - NewVT = MVT::v2f64; - } int Scale = NumElems / NewWidth; SmallVector MaskVec; for (unsigned i = 0; i < NumElems; i += Scale) { From gohman at apple.com Wed Sep 8 13:14:29 2010 From: gohman at apple.com (Dan Gohman) Date: Wed, 8 Sep 2010 11:14:29 -0700 Subject: [llvm-commits] [llvm] r113329 - in /llvm/trunk: include/llvm/Analysis/AliasAnalysis.h lib/Analysis/AliasAnalysis.cpp lib/Analysis/BasicAliasAnalysis.cpp In-Reply-To: <4C871D99.6040900@mxc.ca> References: <20100908013220.8342E2A6C12C@llvm.org> <4C871D99.6040900@mxc.ca> Message-ID: On Sep 7, 2010, at 10:22 PM, Nick Lewycky wrote: > Dan Gohman wrote: >> Author: djg >> Date: Tue Sep 7 20:32:20 2010 >> New Revision: 113329 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=113329&view=rev >> Log: >> Add a new experimental generalized dependence query interface to >> AliasAnalysis, and some code for implementing the new query on top of >> existing implementations by making standard alias and getModRefInfo >> queries. > > Hi Dan, > > Are you sure you don't just want MemoryDependenceAnalysis? Your DependenceResult enum is much larger than memdep's MemDepResult, but in reality passes use I->mayWriteToMemory and the like to determine the extra info your pass puts in the result enum. I'm thinking about porting MemoryDependenceAnalysis to use this new interface, or something like it, instead of getModRefInfo. This would give AliasAnslysis implementations, in particular TBAA, the ability to look at both dereference instructions (to examine their metadata) at the same time. Dan From resistor at mac.com Wed Sep 8 13:22:11 2010 From: resistor at mac.com (Owen Anderson) Date: Wed, 08 Sep 2010 18:22:11 -0000 Subject: [llvm-commits] [llvm] r113380 - /llvm/trunk/include/llvm/LLVMContext.h Message-ID: <20100908182211.4737B2A6C12C@llvm.org> Author: resistor Date: Wed Sep 8 13:22:11 2010 New Revision: 113380 URL: http://llvm.org/viewvc/llvm-project?rev=113380&view=rev Log: Make module ownership methods on LLVMContext private, and make Module a friend so that it can access them. These are not intended to be externally accessible APIs. Modified: llvm/trunk/include/llvm/LLVMContext.h Modified: llvm/trunk/include/llvm/LLVMContext.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/LLVMContext.h?rev=113380&r1=113379&r2=113380&view=diff ============================================================================== --- llvm/trunk/include/llvm/LLVMContext.h (original) +++ llvm/trunk/include/llvm/LLVMContext.h Wed Sep 8 13:22:11 2010 @@ -33,11 +33,6 @@ LLVMContext(LLVMContext&); void operator=(LLVMContext&); -public: - LLVMContextImpl *const pImpl; - LLVMContext(); - ~LLVMContext(); - /// addModule - Register a module as being instantiated in this context. If /// the context is deleted, the module will be deleted as well. void addModule(Module*); @@ -45,6 +40,14 @@ /// removeModule - Unregister a module from this context. void removeModule(Module*); + // Module needs access to the add/removeModule methods. + friend class Module; + +public: + LLVMContextImpl *const pImpl; + LLVMContext(); + ~LLVMContext(); + // Pinned metadata names, which always have the same value. This is a // compile-time performance optimization, not a correctness optimization. enum { From isanbard at gmail.com Wed Sep 8 13:30:06 2010 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 08 Sep 2010 18:30:06 -0000 Subject: [llvm-commits] [llvm] r113381 - /llvm/trunk/utils/release/ Message-ID: <20100908183006.488B82A6C12C@llvm.org> Author: void Date: Wed Sep 8 13:30:06 2010 New Revision: 113381 URL: http://llvm.org/viewvc/llvm-project?rev=113381&view=rev Log: Add a directory for release management scripts. Added: llvm/trunk/utils/release/ From isanbard at gmail.com Wed Sep 8 13:32:31 2010 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 08 Sep 2010 18:32:31 -0000 Subject: [llvm-commits] [llvm] r113382 - /llvm/trunk/utils/release/test-release.sh Message-ID: <20100908183231.3DD8B2A6C12C@llvm.org> Author: void Date: Wed Sep 8 13:32:31 2010 New Revision: 113382 URL: http://llvm.org/viewvc/llvm-project?rev=113382&view=rev Log: A script that tests a certain release candidate in several modes. It does a 2-phase build of llvm and llvm-gcc, similar to what the buildbots do, and runs the regression testsuite. Things to do: - Work out some bugs with llvm-gcc flags. - Not all platforms support ObjC. - Run the test-suite. Added: llvm/trunk/utils/release/test-release.sh Added: llvm/trunk/utils/release/test-release.sh URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/release/test-release.sh?rev=113382&view=auto ============================================================================== --- llvm/trunk/utils/release/test-release.sh (added) +++ llvm/trunk/utils/release/test-release.sh Wed Sep 8 13:32:31 2010 @@ -0,0 +1,391 @@ +#!/bin/bash +#===-- test-release.sh - Test the LLVM release candidates ------------------===# +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open Source +# License. +# +#===------------------------------------------------------------------------===# +# +# Download, build, and test the release candidate for an LLVM release. +# +#===------------------------------------------------------------------------===# + +set -e + +Release="" +Release_no_dot="" +RC="" +do_checkout="yes" +do_ada="no" +do_fortran="yes" +do_64bit="yes" +BuildDir="`pwd`" + +# Figure out how many make processes to run. +NumJobs=`sysctl -n hw.activecpu 2> /dev/null || true` +if [ -z "$NumJobs" ]; then + NumJobs=`sysctl -n hw.ncpu 2> /dev/null || true` +fi +if [ -z "$NumJobs" ]; then + NumJobs=`grep -c processor /proc/cpuinfo 2> /dev/null || true` +fi + +function usage() { + echo "usage: `basename $0` -release X.Y -rc NUM [OPTIONS]" + echo "" + echo " -release X.Y The release number to test." + echo " -rc NUM The pre-release candidate number." + echo " -j NUM Number of compile jobs to run. [default: 3]" + echo " -build-dir DIR Directory to perform testing in. [default: pwd]" + echo " -no-checkout Don't checkout the sources from SVN." + echo " -no-64bit Don't test the 64-bit version. [default: yes]" + echo " -ada Build Ada. [default: no]" + echo " -disable-fortran Disable Fortran build. [default: build]" +} + +while [ $# -gt 0 ]; do + case $1 in + -release | --release ) + shift + Release="$1" + Release_no_dot="`echo $1 | sed -e 's,\.,,'`" + ;; + -rc | --rc | -RC | --RC ) + shift + RC=$1 + ;; + -j* ) + NumJobs="`echo $1 | sed -e 's,-j\([0-9]*\),\1,g'`" + if [ -z "$NumJobs" ]; then + shift + NumJobs="$1" + fi + ;; + -build-dir | --build-dir | -builddir | --builddir ) + shift + BuildDir="$1" + ;; + -no-checkout | --no-checkout ) + do_checkout="no" + ;; + -no-64bit | --no-64bit ) + do_64bit="no" + ;; + -ada | --ada ) + do_ada="yes" + ;; + -disable-fortran | --disable-fortran ) + echo "WARNING: Do you *really* need to disable Fortran?" + sleep 5 + do_fortran="no" + ;; + -help | --help | -h | --h | -\? ) + usage + exit 0 + ;; + * ) + echo "unknown option: $1" + usage + exit 1 + ;; + esac + shift +done + +# Check required arguments. +if [ -z "$Release" ]; then + echo "No release number specified!" + exit 1 +fi +if [ -z "$RC" ]; then + echo "No release candidate number specified!" + exit 1 +fi + +if [ -z "$NumJobs" ]; then + NumJobs=3 +fi + +# Location of sources. +llvmCore_srcdir=$BuildDir/llvmCore-$Release-rc$RC.src +llvmgcc42_srcdir=$BuildDir/llvmgcc42-$Release-rc$RC.src + +# Location of log files. +LogDirName="$Release-rc$RC.logs" +LogDir=$BuildDir/$LogDirName +mkdir -p $LogDir + +# SVN URLs for the sources. +Base_url="http://llvm.org/svn/llvm-project" +llvmCore_RC_url="$Base_url/llvm/tags/RELEASE_$Release_no_dot/rc$RC" +llvmgcc42_RC_url="$Base_url/llvm-gcc-4.2/tags/RELEASE_$Release_no_dot/rc$RC" +clang_RC_url="$Base_url/cfe/tags/RELEASE_$Release_no_dot/rc$RC" +test_suite_RC_url="$Base_url/test-suite/tags/RELEASE_$Release_no_dot/rc$RC" + +# Make sure that the URLs are valid. +function check_valid_urls() { + echo "# Validating SVN URLs" + if ! svn ls $llvmCore_RC_url > /dev/null 2>&1 ; then + echo "llvm $Release release candidate $RC doesn't exist!" + exit 1 + fi + if ! svn ls $llvmgcc42_RC_url > /dev/null 2>&1 ; then + echo "llvm-gcc-4.2 $Release release candidate $RC doesn't exist!" + exit 1 + fi + if ! svn ls $clang_RC_url > /dev/null 2>&1 ; then + echo "clang $Release release candidate $RC doesn't exist!" + exit 1 + fi + if ! svn ls $test_suite_RC_url > /dev/null 2>&1 ; then + echo "test-suite $Release release candidate $RC doesn't exist!" + exit 1 + fi +} + +# Export sources to the the build directory. +function export_sources() { + check_valid_urls + + echo "# Exporting llvm $Release-RC$RC sources" + svn export -q $llvmCore_RC_url $llvmCore_srcdir + echo "# Exporting llvm-gcc-4.2 $Release-rc$RC sources" + svn export -q $llvmgcc42_RC_url $llvmgcc42_srcdir + echo "# Exporting clang $Release-rc$RC sources" + svn export -q $clang_RC_url $llvmCore_srcdir/tools/clang + echo "# Exporting llvm test suite $Release-rc$RC sources" + svn export -q $test_suite_RC_url $llvmCore_srcdir/projects/llvm-test +} + +function configure_llvmCore() { + Phase="$1" + Flavor="$2" + ObjDir="$3" + InstallDir="$4" + llvmgccDir="$5" + + case $Flavor in + Release | Release-64 ) + Optimized="yes" + Assertions="yes" + ;; + Release-Asserts ) + Optimized="yes" + Assertions="no" + ;; + Debug ) + Optimized="no" + Assertions="yes" + ;; + * ) + echo "# Invalid flavor $Flavor!" + echo "" + return + ;; + esac + + cd $ObjDir + echo "# Configuring llvm $Release-rc$RC $Flavor" + echo "# $llvmCore_srcdir/configure --prefix=$llvmCore_installdir \ + --enable-optimized=$Optimized \ + --enable-assertions=$Assertions \ + --with-llvmgccdir=$llvmgccDir" + $llvmCore_srcdir/configure --prefix=$InstallDir \ + --enable-optimized=$Optimized \ + --enable-assertions=$Assertions \ + --with-llvmgccdir=$llvmgccDir \ + > $LogDir/llvm.configure.$Release-rc$RC-Phase$Phase-$Flavor.log 2>&1 + cd - +} + +function build_llvmCore() { + Phase="$1" + Flavor="$2" + ObjDir="$3" + ExtraOpts="" + + CompilerFlags="" + if [ "$Phase" = "2" ]; then + CompilerFlags="CC=$llvmgccDir/bin/llvm-gcc CXX=$llvmgccDir/bin/llvm-g++" + fi + if [ "$Flavor" = "Release-64" ]; then + ExtraOpts="EXTRA_OPTIONS=-m64" + fi + + cd $ObjDir + echo "# Compiling llvm $Release-rc$RC $Flavor" + echo "# make -j $NumJobs VERBOSE=1 $ExtraOpts" + make -j $NumJobs VERBOSE=1 $ExtraOpts $CompilerFlags \ + > $LogDir/llvm.make.$Release-rc$RC-Phase$Phase-$Flavor.log 2>&1 + + echo "# Installing llvm $Release-rc$RC $Flavor" + echo "# make install" + make install \ + > $LogDir/llvm.install.$Release-rc$RC-Phase$Phase-$Flavor.log 2>&1 + cd - +} + +function test_llvmCore() { + Phase="$1" + Flavor="$2" + ObjDir="$3" + + cd $ObjDir + make check \ + > $LogDir/llvm.check.$Release-rc$RC-Phase$Phase-$Flavor.log 2>&1 + make -C tools/clang test \ + > $LogDir/clang.check.$Release-rc$RC-Phase$Phase-$Flavor.log 2>&1 + make unittests \ + > $LogDir/llvm.unittests.$Release-rc$RC-Phase$Phase-$Flavor.log 2>&1 + cd - +} + +function configure_llvm_gcc() { + Phase="$1" + Flavor="$2" + ObjDir="$3" + InstallDir="$4" + llvmObjDir="$5" + + languages="c,c++,objc,obj-c++" + if [ "$do_fortran" = "yes" ]; then + languages="$languages,fortran" + fi + if [ "$do_ada" = "yes" ]; then + languages="$languages,ada" + fi + + cd $ObjDir + echo "# Configuring llvm-gcc $Release-rc$RC $Flavor" + echo "# $llvmgcc42_srcdir/configure --prefix=$InstallDir \ + --program-prefix=llvm- --enable-llvm=$llvmObjDir \ + --enable-languages=$languages \ + --with-gxx-include-dir=/usr/include/c++/4.2.1" + $llvmgcc42_srcdir/configure --prefix=$InstallDir \ + --program-prefix=llvm- --enable-llvm=$llvmObjDir \ + --enable-languages=$languages \ + --with-gxx-include-dir=/usr/include/c++/4.2.1 \ + > $LogDir/llvm-gcc.configure.$Release-rc$RC-Phase$Phase-$Flavor.log 2>&1 + cd - +} + +function build_llvm_gcc() { + Phase="$1" + Flavor="$2" + ObjDir="$3" + llvmgccDir="$4" + + CompilerFlags="" + if [ "$Phase" = "2" ]; then + CompilerFlags="CC=$llvmgccDir/bin/llvm-gcc CXX=$llvmgccDir/bin/llvm-g++" + fi + + cd $ObjDir + echo "# Compiling llvm-gcc $Release-rc$RC $Flavor" + echo "# make -j $NumJobs bootstrap LLVM_VERSION_INFO=$Release" + make -j $NumJobs bootstrap LLVM_VERSION_INFO=$Release $CompilerFlags \ + > $LogDir/llvm-gcc.make.$Release-rc$RC-Phase$Phase-$Flavor.log 2>&1 + + echo "# Installing llvm-gcc $Release-rc$RC $Flavor" + echo "# make install" + make install \ + > $LogDir/llvm-gcc.install.$Release-rc$RC-Phase$Phase-$Flavor.log 2>&1 + cd - +} + +if [ "$do_checkout" = "yes" ]; then + export_sources +fi + +( +Flavors="Debug Release Release-Asserts" +if [ "$do_64bit" = "yes" ]; then + Flavors="$Flavors Release-64" +fi + +for Flavor in $Flavors ; do + echo "" + echo "" + echo "********************************************************************************" + echo " Release: $Release-rc$RC" + echo " Build: $Flavor" + echo " System Info: " + echo " `uname -a`" + echo "********************************************************************************" + echo "" + + llvmCore_phase1_objdir=$BuildDir/Phase1/$Flavor/llvmCore-$Release-rc$RC.obj + llvmCore_phase1_installdir=$BuildDir/Phase1/$Flavor/llvmCore-$Release-rc$RC.install + + llvmCore_phase2_objdir=$BuildDir/Phase2/$Flavor/llvmCore-$Release-rc$RC.obj + llvmCore_phase2_installdir=$BuildDir/Phase2/$Flavor/llvmCore-$Release-rc$RC.install + + rm -rf $llvmCore_phase1_objdir + rm -rf $llvmCore_phase1_installdir + rm -rf $llvmCore_phase2_objdir + rm -rf $llvmCore_phase2_installdir + + mkdir -p $llvmCore_phase1_objdir + mkdir -p $llvmCore_phase1_installdir + mkdir -p $llvmCore_phase2_objdir + mkdir -p $llvmCore_phase2_installdir + + llvmgcc42_phase1_objdir=$BuildDir/Phase1/$Flavor/llvmgcc42-$Release-rc$RC.obj + llvmgcc42_phase1_installdir=$BuildDir/Phase1/$Flavor/llvmgcc42-$Release-rc$RC.install + + llvmgcc42_phase2_objdir=$BuildDir/Phase2/$Flavor/llvmgcc42-$Release-rc$RC.obj + llvmgcc42_phase2_installdir=$BuildDir/Phase2/$Flavor/llvmgcc42-$Release-rc$RC.install + + rm -rf $llvmgcc42_phase1_objdir + rm -rf $llvmgcc42_phase1_installdir + rm -rf $llvmgcc42_phase2_objdir + rm -rf $llvmgcc42_phase2_installdir + + mkdir -p $llvmgcc42_phase1_objdir + mkdir -p $llvmgcc42_phase1_installdir + mkdir -p $llvmgcc42_phase2_objdir + mkdir -p $llvmgcc42_phase2_installdir + + ############################################################################ + # Phase 1: Build llvmCore and llvmgcc42 + echo "# Phase 1: Building llvmCore" + configure_llvmCore 1 $Flavor \ + $llvmCore_phase1_objdir $llvmCore_phase1_installdir \ + $llvmgcc42_phase1_installdir + build_llvmCore 1 $Flavor \ + $llvmCore_phase1_objdir + + echo "# Phase 1: Building llvmgcc42" + configure_llvm_gcc 1 $Flavor \ + $llvmgcc42_phase1_objdir $llvmgcc42_phase1_installdir \ + $llvmCore_phase1_objdir + build_llvm_gcc 1 $Flavor \ + $llvmgcc42_phase1_objdir $llvmgcc42_phase1_installdir + + ############################################################################ + # Phase 2: Build llvmCore with newly built llvmgcc42 from phase 1. + echo "# Phase 2: Building llvmCore" + configure_llvmCore 2 $Flavor \ + $llvmCore_phase2_objdir $llvmCore_phase2_installdir \ + $llvmgcc42_phase1_installdir + build_llvmCore 2 $Flavor \ + $llvmCore_phase2_objdir + + echo "# Phase 2: Building llvmgcc42" + configure_llvm_gcc 2 $Flavor \ + $llvmgcc42_phase2_objdir $llvmgcc42_phase2_installdir \ + $llvmCore_phase2_objdir + build_llvm_gcc 2 $Flavor \ + $llvmgcc42_phase2_objdir $llvmgcc42_phase1_installdir + + echo "# Testing - built with llvmgcc42" + test_llvmCore 2 $Flavor $llvmCore_phase2_objdir +done +) 2>&1 | tee $LogDir/testing.$Release-rc$RC.log + +# Woo hoo! +echo "### Testing Finished ###" +echo "### Logs: $LogDir" +exit 0 From geek4civic at gmail.com Wed Sep 8 13:38:07 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Thu, 9 Sep 2010 03:38:07 +0900 Subject: [llvm-commits] [PATCH] test/ shlibdir-aware In-Reply-To: References: Message-ID: > TODO: > I don't have CMake environments yet. I made an additional patch for cmake. Tested with cmake-2.8.2 on ppc-fedora12. Doesn't cmake build unittests? sleepy...Takumi -------------- next part -------------- diff --git a/test/CMakeLists.txt b/test/CMakeLists.txt index ad9a243..a6c8b1e 100644 --- a/test/CMakeLists.txt +++ b/test/CMakeLists.txt @@ -7,6 +7,8 @@ set(TARGETS_TO_BUILD ${TARGETS_BUILT}) set(LLVM_LIBS_DIR "${LLVM_BINARY_DIR}/lib/${CMAKE_CFG_INTDIR}") set(SHLIBEXT "${LTDL_SHLIB_EXT}") +set(SHLIBDIR "${LLVM_BINARY_DIR}/lib/${CMAKE_CFG_INTDIR}") + if(BUILD_SHARED_LIBS) set(LLVM_SHARED_LIBS_ENABLED "1") else() @@ -61,6 +63,7 @@ if(PYTHONINTERP_FOUND) -e "s#\@LLVMGCCDIR\@##" -e "s#\@LLVM_BUILD_MODE\@#${CMAKE_CFG_INTDIR}#" -e "s#\@ENABLE_SHARED\@#${LLVM_SHARED_LIBS_ENABLED}#" + -e "s#\@SHLIBDIR\@#${SHLIBDIR}#" -e "s#\@SHLIBPATH_VAR\@#${SHLIBPATH_VAR}#" ${CMAKE_CURRENT_SOURCE_DIR}/Unit/lit.site.cfg.in > ${CMAKE_CURRENT_BINARY_DIR}/Unit/lit.site.cfg diff --git a/test/site.exp.in b/test/site.exp.in index c760c2c..1c8f122 100644 --- a/test/site.exp.in +++ b/test/site.exp.in @@ -5,6 +5,7 @@ set TARGETS_TO_BUILD "@TARGETS_TO_BUILD@" set llvmgcc_langs "@LLVMGCC_LANGS@" set llvmtoolsdir "@LLVM_TOOLS_DIR@" set llvmlibsdir "@LLVM_LIBS_DIR@" +set llvmshlibdir "@SHLIBDIR@" set llvm_bindings "@LLVM_BINDINGS@" set srcroot "@LLVM_SOURCE_DIR@" set objroot "@LLVM_BINARY_DIR@" From evan.cheng at apple.com Wed Sep 8 13:40:46 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 8 Sep 2010 11:40:46 -0700 Subject: [llvm-commits] [llvm] r113056 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp In-Reply-To: References: <20100904023607.4F2512A6C12C@llvm.org> <07D973DD-C3FE-409A-97B1-968516F75AFF@apple.com> Message-ID: On Sep 4, 2010, at 2:45 AM, Bruno Cardoso Lopes wrote: > On Sat, Sep 4, 2010 at 12:44 AM, Eric Christopher wrote: >> >> On Sep 3, 2010, at 7:36 PM, Bruno Cardoso Lopes wrote: >> >>> bool HasSSE2 = Subtarget->hasSSE2() || Subtarget->hasAVX(); >>> bool HasSSE3 = Subtarget->hasSSE3() || Subtarget->hasAVX(); >>> + bool HasSSSE3 = Subtarget->hasSSSE3() || Subtarget->hasAVX(); >> >> I understand it's probably just a side effect, but >> >> "HasSSE2" = "HasSSE2 or this other thing" >> >> reads somewhat oddly :) > > Yep, we need to incorporate somehow the AVX with SSE levels, but in > a way that we can select the disjoint set of them - selecting only > AVX stuff when AVX is turned on (since AVX contains a version of all > 128-bit SSE instructions). We try to emulate that right now during isel > by defining: > > def HasSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">; > > There's a FIXME there explaining why! > Anyway, better approaches are always welcome! :) How about renaming HasSSE3 to CanUseSSE3, etc.? Evan > > -- > Bruno Cardoso Lopes > http://www.brunocardoso.cc > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From resistor at mac.com Wed Sep 8 13:41:08 2010 From: resistor at mac.com (Owen Anderson) Date: Wed, 08 Sep 2010 18:41:08 -0000 Subject: [llvm-commits] [llvm] r113385 - /llvm/trunk/include/llvm/LLVMContext.h Message-ID: <20100908184108.1F9E72A6C12C@llvm.org> Author: resistor Date: Wed Sep 8 13:41:07 2010 New Revision: 113385 URL: http://llvm.org/viewvc/llvm-project?rev=113385&view=rev Log: Move private member functions to the end of the class declaration. Modified: llvm/trunk/include/llvm/LLVMContext.h Modified: llvm/trunk/include/llvm/LLVMContext.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/LLVMContext.h?rev=113385&r1=113384&r2=113385&view=diff ============================================================================== --- llvm/trunk/include/llvm/LLVMContext.h (original) +++ llvm/trunk/include/llvm/LLVMContext.h Wed Sep 8 13:41:07 2010 @@ -29,20 +29,6 @@ /// LLVMContext itself provides no locking guarantees, so you should be careful /// to have one context per thread. class LLVMContext { - // DO NOT IMPLEMENT - LLVMContext(LLVMContext&); - void operator=(LLVMContext&); - - /// addModule - Register a module as being instantiated in this context. If - /// the context is deleted, the module will be deleted as well. - void addModule(Module*); - - /// removeModule - Unregister a module from this context. - void removeModule(Module*); - - // Module needs access to the add/removeModule methods. - friend class Module; - public: LLVMContextImpl *const pImpl; LLVMContext(); @@ -88,6 +74,21 @@ void emitError(unsigned LocCookie, StringRef ErrorStr); void emitError(const Instruction *I, StringRef ErrorStr); void emitError(StringRef ErrorStr); + +private: + // DO NOT IMPLEMENT + LLVMContext(LLVMContext&); + void operator=(LLVMContext&); + + /// addModule - Register a module as being instantiated in this context. If + /// the context is deleted, the module will be deleted as well. + void addModule(Module*); + + /// removeModule - Unregister a module from this context. + void removeModule(Module*); + + // Module needs access to the add/removeModule methods. + friend class Module; }; /// getGlobalContext - Returns a global context. This is for LLVM clients that From stoklund at 2pi.dk Wed Sep 8 13:50:24 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 08 Sep 2010 18:50:24 -0000 Subject: [llvm-commits] [llvm] r113386 - in /llvm/trunk: include/llvm/CodeGen/LiveInterval.h lib/CodeGen/LiveInterval.cpp Message-ID: <20100908185024.6CE962A6C12C@llvm.org> Author: stoklund Date: Wed Sep 8 13:50:24 2010 New Revision: 113386 URL: http://llvm.org/viewvc/llvm-project?rev=113386&view=rev Log: Remove dead code. Modified: llvm/trunk/include/llvm/CodeGen/LiveInterval.h llvm/trunk/lib/CodeGen/LiveInterval.cpp Modified: llvm/trunk/include/llvm/CodeGen/LiveInterval.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveInterval.h?rev=113386&r1=113385&r2=113386&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/LiveInterval.h (original) +++ llvm/trunk/include/llvm/CodeGen/LiveInterval.h Wed Sep 8 13:50:24 2010 @@ -447,10 +447,6 @@ /// index (register interval) or defined VNInfo *findDefinedVNInfoForRegInt(SlotIndex Idx) const; - /// findDefinedVNInfo - Find the VNInfo that's defined by the specified - /// register (stack inteval only). - VNInfo *findDefinedVNInfoForStackInt(unsigned Reg) const; - /// overlaps - Return true if the intersection of the two live intervals is /// not empty. Modified: llvm/trunk/lib/CodeGen/LiveInterval.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveInterval.cpp?rev=113386&r1=113385&r2=113386&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveInterval.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveInterval.cpp Wed Sep 8 13:50:24 2010 @@ -443,17 +443,6 @@ return 0; } -/// findDefinedVNInfo - Find the VNInfo defined by the specified -/// register (stack inteval). -VNInfo *LiveInterval::findDefinedVNInfoForStackInt(unsigned reg) const { - for (LiveInterval::const_vni_iterator i = vni_begin(), e = vni_end(); - i != e; ++i) { - if ((*i)->getReg() == reg) - return *i; - } - return 0; -} - /// join - Join two live intervals (this, and other) together. This applies /// mappings to the value numbers in the LHS/RHS intervals as specified. If /// the intervals are not joinable, this aborts. From echristo at apple.com Wed Sep 8 13:56:34 2010 From: echristo at apple.com (Eric Christopher) Date: Wed, 08 Sep 2010 18:56:34 -0000 Subject: [llvm-commits] [llvm] r113387 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20100908185634.DEE672A6C12C@llvm.org> Author: echristo Date: Wed Sep 8 13:56:34 2010 New Revision: 113387 URL: http://llvm.org/viewvc/llvm-project?rev=113387&view=rev Log: Rewrite TargetMaterializeConstant. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=113387&r1=113386&r2=113387&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Wed Sep 8 13:56:34 2010 @@ -328,11 +328,12 @@ // Only handle simple types. if (!VT.isSimple()) return 0; + + // Handle double width floating point? + if (VT.getSimpleVT().SimpleTy == MVT::f64) return 0; - // TODO: This should be safe for fp because they're just bits from the - // Constant. - // TODO: Theoretically we could materialize fp constants with instructions - // from VFP3. + // TODO: Theoretically we could materialize fp constants directly with + // instructions from VFP3. // MachineConstantPool wants an explicit alignment. unsigned Align = TD.getPrefTypeAlignment(C->getType()); @@ -342,8 +343,7 @@ } unsigned Idx = MCP.getConstantPoolIndex(C, Align); - unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); - // Different addressing modes between ARM/Thumb2 for constant pool loads. + unsigned DestReg = createResultReg(TLI.getRegClassFor(MVT::i32)); if (isThumb) AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::t2LDRpci)) @@ -351,8 +351,19 @@ else AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp)) - .addReg(DestReg).addConstantPoolIndex(Idx) + .addReg(DestReg).addConstantPoolIndex(Idx) .addReg(0).addImm(0)); + + // If we have a floating point constant we expect it in a floating point + // register. + // TODO: Make this use ARMBaseInstrInfo::copyPhysReg. + if (C->getType()->isFloatTy()) { + unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); + AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, + TII.get(ARM::VMOVRS), MoveReg) + .addReg(DestReg)); + return MoveReg; + } return DestReg; } From dalej at apple.com Wed Sep 8 14:15:38 2010 From: dalej at apple.com (Dale Johannesen) Date: Wed, 08 Sep 2010 19:15:38 -0000 Subject: [llvm-commits] [llvm] r113388 - /llvm/trunk/lib/Target/X86/X86InstrMMX.td Message-ID: <20100908191538.627712A6C12C@llvm.org> Author: johannes Date: Wed Sep 8 14:15:38 2010 New Revision: 113388 URL: http://llvm.org/viewvc/llvm-project?rev=113388&view=rev Log: Add intrinsic forms of mmx<->sse conversions. Notes: Omission of memory form of PI2PD is intentional; this does not use an MMX register and does not put the chip into MMX mode (PI2PS, oddly enough, does). Operands of PI2PS follow the gcc builtin, not Intel. Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrMMX.td?rev=113388&r1=113387&r2=113388&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrMMX.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrMMX.td Wed Sep 8 14:15:38 2010 @@ -471,6 +471,57 @@ "cvttps2pi\t{$src, $dst|$dst, $src}", []>; } // end neverHasSideEffects +// Intrinsic versions. +def MMX_CVTPD2PIirr : MMX2I<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src), + "cvtpd2pi\t{$src, $dst|$dst, $src}", + [(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>; +def MMX_CVTPD2PIirm : MMX2I<0x2D, MRMSrcMem, (outs VR64:$dst), + (ins f128mem:$src), + "cvtpd2pi\t{$src, $dst|$dst, $src}", + [(set VR64:$dst, + (int_x86_sse_cvtpd2pi + (bitconvert (loadv2i64 addr:$src))))]>; +def MMX_CVTPI2PDirr : MMX2I<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src), + "cvtpi2pd\t{$src, $dst|$dst, $src}", + [(set VR128:$dst, (int_x86_sse_cvtpi2pd VR64:$src))]>; +let Constraints = "$src1 = $dst" in { +def MMX_CVTPI2PSirr : MMXI<0x2A, MRMSrcReg, (outs VR128:$dst), + (ins VR128:$src1, VR64:$src2), + "cvtpi2ps\t{$src2, $dst|$dst, $src2}", + [(set VR128:$dst, + (int_x86_sse_cvtpi2ps VR128:$src1, VR64:$src2))]>; +def MMX_CVTPI2PSirm : MMXI<0x2A, MRMSrcMem, (outs VR128:$dst), + (ins VR128:$src1, i64mem:$src2), + "cvtpi2ps\t{$src2, $dst|$dst, $src2}", + [(set VR128:$dst, + (int_x86_sse_cvtpi2ps VR128:$src1, + (bitconvert (load_mmx addr:$src2))))]>; +} +def MMX_CVTPS2PIirr : MMXI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src), + "cvtps2pi\t{$src, $dst|$dst, $src}", + [(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>; +def MMX_CVTPS2PIirm : MMXI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src), + "cvtps2pi\t{$src, $dst|$dst, $src}", + [(set VR64:$dst, + (int_x86_sse_cvtps2pi + (bitconvert (load_mmx addr:$src))))]>; +def MMX_CVTTPD2PIirr: MMX2I<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src), + "cvttpd2pi\t{$src, $dst|$dst, $src}", + [(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>; +def MMX_CVTTPD2PIirm: MMX2I<0x2C, MRMSrcMem, (outs VR64:$dst), + (ins f128mem:$src), + "cvttpd2pi\t{$src, $dst|$dst, $src}", + [(set VR64:$dst, + (int_x86_sse_cvtpd2pi + (bitconvert (loadv2i64 addr:$src))))]>; +def MMX_CVTTPS2PIirr: MMXI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src), + "cvttps2pi\t{$src, $dst|$dst, $src}", + [(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>; +def MMX_CVTTPS2PIirm: MMXI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src), + "cvttps2pi\t{$src, $dst|$dst, $src}", + [(set VR64:$dst, + (int_x86_sse_cvtpd2pi + (bitconvert (load_mmx addr:$src))))]>; // Extract / Insert def MMX_X86pinsrw : SDNode<"X86ISD::MMX_PINSRW", From steinke-dirk at web.de Wed Sep 8 14:19:54 2010 From: steinke-dirk at web.de (Dirk Steinke) Date: Wed, 08 Sep 2010 21:19:54 +0200 Subject: [llvm-commits] [PATCH] InstCombine: Generalized patch for (icmp eq (A&B), C) & (icmp eq (A&D), E), again Message-ID: <4C87E1DA.7090200@web.de> Hi, a couple weeks ago I provided (basically) the same patch to InstCombine. According to Owen: > Dirk, > > Your updated testcase (bit-checks.ll) doesn't pass for me after > applying your patch. > > --Owen Meanwhile I've setup a Linux box (VM) for LLVM, applied the patch, ran 'make' and 'make check', and there were only expected failures. So it wasn't my fault, and I'm all happy. :-) Please review again and apply. The attached version handles more testcases, has a bug fixed (which was detected by one of the new tests), has an early out if the icmp's do not compare the same integer type, and does no longer (unvoluntarily) handle integer vectors. (Integer vectors might work, but I didn't think this through yet.) Bye Dirk -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: foldmaskedicmp3.diff Url: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100908/ae62ab51/attachment.pl From daniel at zuster.org Wed Sep 8 14:21:08 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 08 Sep 2010 19:21:08 -0000 Subject: [llvm-commits] [test-suite] r113389 - in /test-suite/trunk/SingleSource/UnitTests/Vector/NEON: ./ Makefile simple.c Message-ID: <20100908192108.8E9E42A6C12C@llvm.org> Author: ddunbar Date: Wed Sep 8 14:21:08 2010 New Revision: 113389 URL: http://llvm.org/viewvc/llvm-project?rev=113389&view=rev Log: Sketch a simple NEON test. Not wired into build yet, because we don't have a way to detect neonability, yet. Added: test-suite/trunk/SingleSource/UnitTests/Vector/NEON/ test-suite/trunk/SingleSource/UnitTests/Vector/NEON/Makefile test-suite/trunk/SingleSource/UnitTests/Vector/NEON/simple.c Added: test-suite/trunk/SingleSource/UnitTests/Vector/NEON/Makefile URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/Vector/NEON/Makefile?rev=113389&view=auto ============================================================================== --- test-suite/trunk/SingleSource/UnitTests/Vector/NEON/Makefile (added) +++ test-suite/trunk/SingleSource/UnitTests/Vector/NEON/Makefile Wed Sep 8 14:21:08 2010 @@ -0,0 +1,8 @@ +# SingleSource/UnitTests/Vector/NEON/Makefile + +DIRS = +LEVEL = ../../../.. + +include $(LEVEL)/SingleSource/Makefile.singlesrc + +CFLAGS += -std=c99 Added: test-suite/trunk/SingleSource/UnitTests/Vector/NEON/simple.c URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/Vector/NEON/simple.c?rev=113389&view=auto ============================================================================== --- test-suite/trunk/SingleSource/UnitTests/Vector/NEON/simple.c (added) +++ test-suite/trunk/SingleSource/UnitTests/Vector/NEON/simple.c Wed Sep 8 14:21:08 2010 @@ -0,0 +1,166 @@ +#include +#include + +typedef int8x16_t v16i8; +typedef int16x8_t v8i16; +typedef int32x4_t v4i32; + +typedef int8x16x2_t v16i8x2; +typedef int16x8x2_t v8i16x2; +typedef int32x4x2_t v4i32x2; + +v16i8 init_v16i8(int8_t a0, int8_t a1, int8_t a2, int8_t a3, + int8_t a4, int8_t a5, int8_t a6, int8_t a7, + int8_t a8, int8_t a9, int8_t a10, int8_t a11, + int8_t a12, int8_t a13, int8_t a14, int8_t a15) { + int8_t d[16]; + + d[0] = a0; d[1] = a1; d[2] = a2; d[3] = a3; + d[4] = a4; d[5] = a5; d[6] = a6; d[7] = a7; + d[8] = a8; d[9] = a9; d[10] = a10; d[11] = a11; + d[12] = a12; d[13] = a13; d[14] = a14; d[15] = a15; + + return vld1q_s8(d); +} + +v8i16 init_v8i16(int16_t a0, int16_t a1, int16_t a2, int16_t a3, + int16_t a4, int16_t a5, int16_t a6, int16_t a7) { + int16_t d[8]; + + d[0] = a0; d[1] = a1; d[2] = a2; d[3] = a3; + d[4] = a4; d[5] = a5; d[6] = a6; d[7] = a7; + + return vld1q_s16(d); +} + +v4i32 init_v4i32(int32_t a0, int32_t a1, int32_t a2, int32_t a3) { + int32_t d[8]; + + d[0] = a0; d[1] = a1; d[2] = a2; d[3] = a3; + + return vld1q_s32(d); +} + +void print_v16i8(v16i8 a) { + int8_t d[16]; + vst1q_s8(d, a); + printf("(%d, %d, %d, %d, %d, %d, %d, %d, " + "%d, %d, %d, %d, %d, %d, %d, %d)", + d[0], d[1], d[2], d[3], d[4], d[5], d[6], d[7], + d[8], d[9], d[10], d[11], d[12], d[13], d[14], d[15]); +} +void print_v8i16(v8i16 a) { + int16_t d[8]; + vst1q_s16(d, a); + printf("(%d, %d, %d, %d, %d, %d, %d, %d)", + d[0], d[1], d[2], d[3], d[4], d[5], d[6], d[7]); +} +void print_v4i32(v4i32 a) { + int32_t d[4]; + vst1q_s32(d, a); + printf("(%d, %d, %d, %d)", d[0], d[1], d[2], d[3]); +} + +void test_basic() { + printf("%s\n", __FUNCTION__); + + v16i8 a0_0 = vmovq_n_s8(1); + v16i8 a0_1 = init_v16i8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); + v16i8 a0_2 = vaddq_s8(a0_0, a0_1); + printf("a0_0: "); + print_v16i8(a0_0); + printf("\n"); + printf("a0_1: "); + print_v16i8(a0_1); + printf("\n"); + printf("a0_2: "); + print_v16i8(a0_2); + printf("\n"); + + v8i16 a1_0 = vmovq_n_s16(1); + v8i16 a1_1 = init_v8i16(0, 1, 2, 3, 4, 5, 6, 7); + v8i16 a1_2 = vaddq_s16(a1_0, a1_1); + printf("a1_0: "); + print_v8i16(a1_0); + printf("\n"); + printf("a1_1: "); + print_v8i16(a1_1); + printf("\n"); + printf("a1_2: "); + print_v8i16(a1_2); + printf("\n"); + + v4i32 a2_0 = vmovq_n_s32(1); + v4i32 a2_1 = init_v4i32(0, 1, 2, 3); + v4i32 a2_2 = vaddq_s32(a2_0, a2_1); + printf("a2_0: "); + print_v4i32(a2_0); + printf("\n"); + printf("a2_1: "); + print_v4i32(a2_1); + printf("\n"); + printf("a2_2: "); + print_v4i32(a2_2); + printf("\n"); +} + +void test_zip() { + printf("%s\n", __FUNCTION__); + + v16i8 a0_0 = init_v16i8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); + v16i8 a0_1 = init_v16i8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); + v16i8x2 a0_2 = vzipq_s8(a0_0, a0_1); + v16i8x2 a0_3 = vuzpq_s8(a0_2.val[0], a0_2.val[1]); + printf("a0_2.val[0]: "); + print_v16i8(a0_2.val[0]); + printf("\n"); + printf("a0_2.val[1]: "); + print_v16i8(a0_2.val[1]); + printf("\n"); + printf("a0_3.val[0]: "); + print_v16i8(a0_3.val[0]); + printf("\n"); + printf("a0_3.val[1]: "); + print_v16i8(a0_3.val[1]); + printf("\n"); + + v8i16 a1_0 = init_v8i16(0, 1, 2, 3, 4, 5, 6, 7); + v8i16 a1_1 = init_v8i16(7, 6, 5, 4, 3, 2, 1, 0); + v8i16x2 a1_2 = vzipq_s16(a1_0, a1_1); + v8i16x2 a1_3 = vuzpq_s16(a1_2.val[0], a1_2.val[1]); + printf("a1_2.val[0]: "); + print_v8i16(a1_2.val[0]); + printf("\n"); + printf("a1_2.val[1]: "); + print_v8i16(a1_2.val[1]); + printf("\n"); + printf("a1_3.val[0]: "); + print_v8i16(a1_3.val[0]); + printf("\n"); + printf("a1_3.val[1]: "); + print_v8i16(a1_3.val[1]); + printf("\n"); + + v4i32 a2_0 = init_v4i32(0, 1, 2, 3); + v4i32 a2_1 = init_v4i32(3, 2, 1, 0); + v4i32x2 a2_2 = vzipq_s32(a2_0, a2_1); + v4i32x2 a2_3 = vuzpq_s32(a2_2.val[0], a2_2.val[1]); + printf("a2_2.val[0]: "); + print_v4i32(a2_2.val[0]); + printf("\n"); + printf("a2_2.val[1]: "); + print_v4i32(a2_2.val[1]); + printf("\n"); + printf("a2_3.val[0]: "); + print_v4i32(a2_3.val[0]); + printf("\n"); + printf("a2_3.val[1]: "); + print_v4i32(a2_3.val[1]); + printf("\n"); +} + +int main() { + test_basic(); + test_zip(); + return 0; +} From daniel at zuster.org Wed Sep 8 14:21:27 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Wed, 08 Sep 2010 19:21:27 -0000 Subject: [llvm-commits] [test-suite] r113390 - /test-suite/trunk/SingleSource/Regression/C++/EH/inlined_cleanup.reference_output Message-ID: <20100908192127.146712A6C12C@llvm.org> Author: ddunbar Date: Wed Sep 8 14:21:26 2010 New Revision: 113390 URL: http://llvm.org/viewvc/llvm-project?rev=113390&view=rev Log: Add a reference output. Added: test-suite/trunk/SingleSource/Regression/C++/EH/inlined_cleanup.reference_output Added: test-suite/trunk/SingleSource/Regression/C++/EH/inlined_cleanup.reference_output URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/Regression/C%2B%2B/EH/inlined_cleanup.reference_output?rev=113390&view=auto ============================================================================== --- test-suite/trunk/SingleSource/Regression/C++/EH/inlined_cleanup.reference_output (added) +++ test-suite/trunk/SingleSource/Regression/C++/EH/inlined_cleanup.reference_output Wed Sep 8 14:21:26 2010 @@ -0,0 +1,3 @@ +In cleanup! +Caught 3! +exit 0 From grosbach at apple.com Wed Sep 8 14:28:00 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 8 Sep 2010 12:28:00 -0700 Subject: [llvm-commits] [test-suite] r113389 - in /test-suite/trunk/SingleSource/UnitTests/Vector/NEON: ./ Makefile simple.c In-Reply-To: <20100908192108.8E9E42A6C12C@llvm.org> References: <20100908192108.8E9E42A6C12C@llvm.org> Message-ID: <1B7484FA-4A2F-4E3A-8024-6620F5771B1A@apple.com> On Sep 8, 2010, at 12:21 PM, Daniel Dunbar wrote: > Author: ddunbar > Date: Wed Sep 8 14:21:08 2010 > New Revision: 113389 > > URL: http://llvm.org/viewvc/llvm-project?rev=113389&view=rev > Log: > Sketch a simple NEON test. Not wired into build yet, because we don't have a way to detect neonability, yet. > Detect it when? At compile time, we (should) have a pre-defined macro, __ARM_NEON__, which is defined to '1' when NEON is available, and is undefined otherwise. > Added: > test-suite/trunk/SingleSource/UnitTests/Vector/NEON/ > test-suite/trunk/SingleSource/UnitTests/Vector/NEON/Makefile > test-suite/trunk/SingleSource/UnitTests/Vector/NEON/simple.c > > Added: test-suite/trunk/SingleSource/UnitTests/Vector/NEON/Makefile > URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/Vector/NEON/Makefile?rev=113389&view=auto > ============================================================================== > --- test-suite/trunk/SingleSource/UnitTests/Vector/NEON/Makefile (added) > +++ test-suite/trunk/SingleSource/UnitTests/Vector/NEON/Makefile Wed Sep 8 14:21:08 2010 > @@ -0,0 +1,8 @@ > +# SingleSource/UnitTests/Vector/NEON/Makefile > + > +DIRS = > +LEVEL = ../../../.. > + > +include $(LEVEL)/SingleSource/Makefile.singlesrc > + > +CFLAGS += -std=c99 > > Added: test-suite/trunk/SingleSource/UnitTests/Vector/NEON/simple.c > URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/Vector/NEON/simple.c?rev=113389&view=auto > ============================================================================== > --- test-suite/trunk/SingleSource/UnitTests/Vector/NEON/simple.c (added) > +++ test-suite/trunk/SingleSource/UnitTests/Vector/NEON/simple.c Wed Sep 8 14:21:08 2010 > @@ -0,0 +1,166 @@ > +#include > +#include > + > +typedef int8x16_t v16i8; > +typedef int16x8_t v8i16; > +typedef int32x4_t v4i32; > + > +typedef int8x16x2_t v16i8x2; > +typedef int16x8x2_t v8i16x2; > +typedef int32x4x2_t v4i32x2; > + > +v16i8 init_v16i8(int8_t a0, int8_t a1, int8_t a2, int8_t a3, > + int8_t a4, int8_t a5, int8_t a6, int8_t a7, > + int8_t a8, int8_t a9, int8_t a10, int8_t a11, > + int8_t a12, int8_t a13, int8_t a14, int8_t a15) { > + int8_t d[16]; > + > + d[0] = a0; d[1] = a1; d[2] = a2; d[3] = a3; > + d[4] = a4; d[5] = a5; d[6] = a6; d[7] = a7; > + d[8] = a8; d[9] = a9; d[10] = a10; d[11] = a11; > + d[12] = a12; d[13] = a13; d[14] = a14; d[15] = a15; > + > + return vld1q_s8(d); > +} > + > +v8i16 init_v8i16(int16_t a0, int16_t a1, int16_t a2, int16_t a3, > + int16_t a4, int16_t a5, int16_t a6, int16_t a7) { > + int16_t d[8]; > + > + d[0] = a0; d[1] = a1; d[2] = a2; d[3] = a3; > + d[4] = a4; d[5] = a5; d[6] = a6; d[7] = a7; > + > + return vld1q_s16(d); > +} > + > +v4i32 init_v4i32(int32_t a0, int32_t a1, int32_t a2, int32_t a3) { > + int32_t d[8]; > + > + d[0] = a0; d[1] = a1; d[2] = a2; d[3] = a3; > + > + return vld1q_s32(d); > +} > + > +void print_v16i8(v16i8 a) { > + int8_t d[16]; > + vst1q_s8(d, a); > + printf("(%d, %d, %d, %d, %d, %d, %d, %d, " > + "%d, %d, %d, %d, %d, %d, %d, %d)", > + d[0], d[1], d[2], d[3], d[4], d[5], d[6], d[7], > + d[8], d[9], d[10], d[11], d[12], d[13], d[14], d[15]); > +} > +void print_v8i16(v8i16 a) { > + int16_t d[8]; > + vst1q_s16(d, a); > + printf("(%d, %d, %d, %d, %d, %d, %d, %d)", > + d[0], d[1], d[2], d[3], d[4], d[5], d[6], d[7]); > +} > +void print_v4i32(v4i32 a) { > + int32_t d[4]; > + vst1q_s32(d, a); > + printf("(%d, %d, %d, %d)", d[0], d[1], d[2], d[3]); > +} > + > +void test_basic() { > + printf("%s\n", __FUNCTION__); > + > + v16i8 a0_0 = vmovq_n_s8(1); > + v16i8 a0_1 = init_v16i8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); > + v16i8 a0_2 = vaddq_s8(a0_0, a0_1); > + printf("a0_0: "); > + print_v16i8(a0_0); > + printf("\n"); > + printf("a0_1: "); > + print_v16i8(a0_1); > + printf("\n"); > + printf("a0_2: "); > + print_v16i8(a0_2); > + printf("\n"); > + > + v8i16 a1_0 = vmovq_n_s16(1); > + v8i16 a1_1 = init_v8i16(0, 1, 2, 3, 4, 5, 6, 7); > + v8i16 a1_2 = vaddq_s16(a1_0, a1_1); > + printf("a1_0: "); > + print_v8i16(a1_0); > + printf("\n"); > + printf("a1_1: "); > + print_v8i16(a1_1); > + printf("\n"); > + printf("a1_2: "); > + print_v8i16(a1_2); > + printf("\n"); > + > + v4i32 a2_0 = vmovq_n_s32(1); > + v4i32 a2_1 = init_v4i32(0, 1, 2, 3); > + v4i32 a2_2 = vaddq_s32(a2_0, a2_1); > + printf("a2_0: "); > + print_v4i32(a2_0); > + printf("\n"); > + printf("a2_1: "); > + print_v4i32(a2_1); > + printf("\n"); > + printf("a2_2: "); > + print_v4i32(a2_2); > + printf("\n"); > +} > + > +void test_zip() { > + printf("%s\n", __FUNCTION__); > + > + v16i8 a0_0 = init_v16i8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); > + v16i8 a0_1 = init_v16i8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); > + v16i8x2 a0_2 = vzipq_s8(a0_0, a0_1); > + v16i8x2 a0_3 = vuzpq_s8(a0_2.val[0], a0_2.val[1]); > + printf("a0_2.val[0]: "); > + print_v16i8(a0_2.val[0]); > + printf("\n"); > + printf("a0_2.val[1]: "); > + print_v16i8(a0_2.val[1]); > + printf("\n"); > + printf("a0_3.val[0]: "); > + print_v16i8(a0_3.val[0]); > + printf("\n"); > + printf("a0_3.val[1]: "); > + print_v16i8(a0_3.val[1]); > + printf("\n"); > + > + v8i16 a1_0 = init_v8i16(0, 1, 2, 3, 4, 5, 6, 7); > + v8i16 a1_1 = init_v8i16(7, 6, 5, 4, 3, 2, 1, 0); > + v8i16x2 a1_2 = vzipq_s16(a1_0, a1_1); > + v8i16x2 a1_3 = vuzpq_s16(a1_2.val[0], a1_2.val[1]); > + printf("a1_2.val[0]: "); > + print_v8i16(a1_2.val[0]); > + printf("\n"); > + printf("a1_2.val[1]: "); > + print_v8i16(a1_2.val[1]); > + printf("\n"); > + printf("a1_3.val[0]: "); > + print_v8i16(a1_3.val[0]); > + printf("\n"); > + printf("a1_3.val[1]: "); > + print_v8i16(a1_3.val[1]); > + printf("\n"); > + > + v4i32 a2_0 = init_v4i32(0, 1, 2, 3); > + v4i32 a2_1 = init_v4i32(3, 2, 1, 0); > + v4i32x2 a2_2 = vzipq_s32(a2_0, a2_1); > + v4i32x2 a2_3 = vuzpq_s32(a2_2.val[0], a2_2.val[1]); > + printf("a2_2.val[0]: "); > + print_v4i32(a2_2.val[0]); > + printf("\n"); > + printf("a2_2.val[1]: "); > + print_v4i32(a2_2.val[1]); > + printf("\n"); > + printf("a2_3.val[0]: "); > + print_v4i32(a2_3.val[0]); > + printf("\n"); > + printf("a2_3.val[1]: "); > + print_v4i32(a2_3.val[1]); > + printf("\n"); > +} > + > +int main() { > + test_basic(); > + test_zip(); > + return 0; > +} > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From echristo at apple.com Wed Sep 8 14:32:34 2010 From: echristo at apple.com (Eric Christopher) Date: Wed, 08 Sep 2010 19:32:34 -0000 Subject: [llvm-commits] [llvm] r113392 - /llvm/trunk/test/CodeGen/ARM/fast-isel.ll Message-ID: <20100908193234.D5B912A6C12C@llvm.org> Author: echristo Date: Wed Sep 8 14:32:34 2010 New Revision: 113392 URL: http://llvm.org/viewvc/llvm-project?rev=113392&view=rev Log: Remove ssp from this test. Modified: llvm/trunk/test/CodeGen/ARM/fast-isel.ll Modified: llvm/trunk/test/CodeGen/ARM/fast-isel.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel.ll?rev=113392&r1=113391&r2=113392&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fast-isel.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fast-isel.ll Wed Sep 8 14:32:34 2010 @@ -3,7 +3,7 @@ ; Very basic fast-isel functionality. -define i32 @add(i32 %a, i32 %b) nounwind ssp { +define i32 @add(i32 %a, i32 %b) nounwind { entry: %a.addr = alloca i32, align 4 %b.addr = alloca i32, align 4 From grosbach at apple.com Wed Sep 8 14:55:28 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 08 Sep 2010 19:55:28 -0000 Subject: [llvm-commits] [llvm] r113394 - /llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Message-ID: <20100908195528.7BC7A2A6C12D@llvm.org> Author: grosbach Date: Wed Sep 8 14:55:28 2010 New Revision: 113394 URL: http://llvm.org/viewvc/llvm-project?rev=113394&view=rev Log: Fix errant fall-throughs causing the base pointer to be used when the frame pointer was intended. rdar://8401980 Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=113394&r1=113393&r2=113394&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Wed Sep 8 14:55:28 2010 @@ -1077,7 +1077,7 @@ // there are VLAs (and thus the SP isn't reliable as a base). if (isFixed || (MFI->hasVarSizedObjects() && !hasBasePointer(MF))) { FrameReg = getFrameRegister(MF); - Offset = FPOffset; + return FPOffset; } else if (MFI->hasVarSizedObjects()) { assert(hasBasePointer(MF) && "missing base pointer!"); // Use the base register since we have it. @@ -1087,12 +1087,12 @@ // out of range references. if (FPOffset >= -255 && FPOffset < 0) { FrameReg = getFrameRegister(MF); - Offset = FPOffset; + return FPOffset; } } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) { // Otherwise, use SP or FP, whichever is closer to the stack slot. FrameReg = getFrameRegister(MF); - Offset = FPOffset; + return FPOffset; } } // Use the base pointer if we have one. From baldrick at free.fr Wed Sep 8 14:50:25 2010 From: baldrick at free.fr (Duncan Sands) Date: Wed, 08 Sep 2010 19:50:25 -0000 Subject: [llvm-commits] [llvm] r113393 - /llvm/trunk/utils/release/test-release.sh Message-ID: <20100908195025.4E4BC2A6C12C@llvm.org> Author: baldrick Date: Wed Sep 8 14:50:25 2010 New Revision: 113393 URL: http://llvm.org/viewvc/llvm-project?rev=113393&view=rev Log: Move the number of cpus logic to somewhere more logical. Modified: llvm/trunk/utils/release/test-release.sh Modified: llvm/trunk/utils/release/test-release.sh URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/release/test-release.sh?rev=113393&r1=113392&r2=113393&view=diff ============================================================================== --- llvm/trunk/utils/release/test-release.sh (original) +++ llvm/trunk/utils/release/test-release.sh Wed Sep 8 14:50:25 2010 @@ -23,15 +23,6 @@ do_64bit="yes" BuildDir="`pwd`" -# Figure out how many make processes to run. -NumJobs=`sysctl -n hw.activecpu 2> /dev/null || true` -if [ -z "$NumJobs" ]; then - NumJobs=`sysctl -n hw.ncpu 2> /dev/null || true` -fi -if [ -z "$NumJobs" ]; then - NumJobs=`grep -c processor /proc/cpuinfo 2> /dev/null || true` -fi - function usage() { echo "usage: `basename $0` -release X.Y -rc NUM [OPTIONS]" echo "" @@ -104,6 +95,16 @@ exit 1 fi +# Figure out how many make processes to run. +if [ -z "$NumJobs" ]; then + NumJobs=`sysctl -n hw.activecpu 2> /dev/null || true` +fi +if [ -z "$NumJobs" ]; then + NumJobs=`sysctl -n hw.ncpu 2> /dev/null || true` +fi +if [ -z "$NumJobs" ]; then + NumJobs=`grep -c processor /proc/cpuinfo 2> /dev/null || true` +fi if [ -z "$NumJobs" ]; then NumJobs=3 fi From baldrick at free.fr Wed Sep 8 14:58:15 2010 From: baldrick at free.fr (Duncan Sands) Date: Wed, 08 Sep 2010 19:58:15 -0000 Subject: [llvm-commits] [llvm] r113395 - /llvm/trunk/utils/release/test-release.sh Message-ID: <20100908195815.805152A6C12C@llvm.org> Author: baldrick Date: Wed Sep 8 14:58:15 2010 New Revision: 113395 URL: http://llvm.org/viewvc/llvm-project?rev=113395&view=rev Log: Correct variable name. Modified: llvm/trunk/utils/release/test-release.sh Modified: llvm/trunk/utils/release/test-release.sh URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/release/test-release.sh?rev=113395&r1=113394&r2=113395&view=diff ============================================================================== --- llvm/trunk/utils/release/test-release.sh (original) +++ llvm/trunk/utils/release/test-release.sh Wed Sep 8 14:58:15 2010 @@ -189,7 +189,7 @@ cd $ObjDir echo "# Configuring llvm $Release-rc$RC $Flavor" - echo "# $llvmCore_srcdir/configure --prefix=$llvmCore_installdir \ + echo "# $llvmCore_srcdir/configure --prefix=$InstallDir \ --enable-optimized=$Optimized \ --enable-assertions=$Assertions \ --with-llvmgccdir=$llvmgccDir" From dpatel at apple.com Wed Sep 8 15:06:41 2010 From: dpatel at apple.com (Devang Patel) Date: Wed, 8 Sep 2010 13:06:41 -0700 Subject: [llvm-commits] [llvm] r113329 - in /llvm/trunk: include/llvm/Analysis/AliasAnalysis.h lib/Analysis/AliasAnalysis.cpp lib/Analysis/BasicAliasAnalysis.cpp In-Reply-To: <20100908013220.8342E2A6C12C@llvm.org> References: <20100908013220.8342E2A6C12C@llvm.org> Message-ID: On Sep 7, 2010, at 6:32 PM, Dan Gohman wrote: > + /// ReadThenWrite - The instructions are ReadThenWriteSome and the second > + /// instruction writes to exactly the same memory read from by the first. > + ReadThenWrite, > + ReadThenWriteSome is missing. > + /// WriteThenWrite - The instructions are WriteThenWriteSome, and the > + /// second instruction writes to exactly the same memory written to by > + /// the first. > + WriteThenWrite, > + > + /// WriteSomeThenWrite - Both instructions are write-only, and the second > + /// instruction writes to a superset of the memory written to by the first. > + WriteSomeThenWrite, I am curious, why did not you use WriteThenWriteSome alternative ? - Devang From isanbard at gmail.com Wed Sep 8 15:09:14 2010 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 08 Sep 2010 20:09:14 -0000 Subject: [llvm-commits] [llvm] r113398 - /llvm/trunk/utils/release/test-release.sh Message-ID: <20100908200914.51DF62A6C12C@llvm.org> Author: void Date: Wed Sep 8 15:09:14 2010 New Revision: 113398 URL: http://llvm.org/viewvc/llvm-project?rev=113398&view=rev Log: Add an option to not test ObjC for those platforms which don't support it. Modified: llvm/trunk/utils/release/test-release.sh Modified: llvm/trunk/utils/release/test-release.sh URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/release/test-release.sh?rev=113398&r1=113397&r2=113398&view=diff ============================================================================== --- llvm/trunk/utils/release/test-release.sh (original) +++ llvm/trunk/utils/release/test-release.sh Wed Sep 8 15:09:14 2010 @@ -19,6 +19,7 @@ RC="" do_checkout="yes" do_ada="no" +do_objc="yes" do_fortran="yes" do_64bit="yes" BuildDir="`pwd`" @@ -33,6 +34,7 @@ echo " -no-checkout Don't checkout the sources from SVN." echo " -no-64bit Don't test the 64-bit version. [default: yes]" echo " -ada Build Ada. [default: no]" + echo " -disable-objc Disable ObjC build. [default: build]" echo " -disable-fortran Disable Fortran build. [default: build]" } @@ -67,6 +69,9 @@ -ada | --ada ) do_ada="yes" ;; + -disable-objc | --disable-objc ) + do_objc="no" + ;; -disable-fortran | --disable-fortran ) echo "WARNING: Do you *really* need to disable Fortran?" sleep 5 @@ -250,7 +255,10 @@ InstallDir="$4" llvmObjDir="$5" - languages="c,c++,objc,obj-c++" + languages="c,c++" + if [ "$do_objc" = "yes" ]; then + languages="$languages,objc,obj-c++" + fi if [ "$do_fortran" = "yes" ]; then languages="$languages,fortran" fi From grosbach at apple.com Wed Sep 8 15:12:02 2010 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 08 Sep 2010 20:12:02 -0000 Subject: [llvm-commits] [llvm] r113399 - in /llvm/trunk: lib/Target/ARM/ARMBaseRegisterInfo.cpp test/CodeGen/Thumb/dyn-stackalloc.ll Message-ID: <20100908201202.B5CAA2A6C12C@llvm.org> Author: grosbach Date: Wed Sep 8 15:12:02 2010 New Revision: 113399 URL: http://llvm.org/viewvc/llvm-project?rev=113399&view=rev Log: Re-enable usage of the ARM base pointer. r113394 fixed the known failures. Re-running some nightly testers w/ it enabled to verify. Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp llvm/trunk/test/CodeGen/Thumb/dyn-stackalloc.ll Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=113399&r1=113398&r2=113399&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Wed Sep 8 15:12:02 2010 @@ -51,7 +51,7 @@ using namespace llvm; static cl::opt -EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(false), +EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true), cl::desc("Enable use of a base pointer for complex stack frames")); unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum, Modified: llvm/trunk/test/CodeGen/Thumb/dyn-stackalloc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/dyn-stackalloc.ll?rev=113399&r1=113398&r2=113399&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb/dyn-stackalloc.ll (original) +++ llvm/trunk/test/CodeGen/Thumb/dyn-stackalloc.ll Wed Sep 8 15:12:02 2010 @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=thumb | not grep {ldr sp} ; RUN: llc < %s -mtriple=thumb-apple-darwin | \ ; RUN: not grep {sub.*r7} -; RUN: llc < %s -march=thumb | grep 4294967280 +; RUN: llc < %s -march=thumb | grep {mov.*r6, sp} %struct.state = type { i32, %struct.info*, float**, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64, i64, i64, i64, i64, i64, i8* } %struct.info = type { i32, i32, i32, i32, i32, i32, i32, i8* } From isanbard at gmail.com Wed Sep 8 15:21:11 2010 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 08 Sep 2010 20:21:11 -0000 Subject: [llvm-commits] [llvm] r113401 - /llvm/trunk/utils/release/test-release.sh Message-ID: <20100908202111.BAD3A2A6C12C@llvm.org> Author: void Date: Wed Sep 8 15:21:11 2010 New Revision: 113401 URL: http://llvm.org/viewvc/llvm-project?rev=113401&view=rev Log: Remove --with-gxx-include-dir option because it's causing problems on non-Darwin platforms. Modified: llvm/trunk/utils/release/test-release.sh Modified: llvm/trunk/utils/release/test-release.sh URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/release/test-release.sh?rev=113401&r1=113400&r2=113401&view=diff ============================================================================== --- llvm/trunk/utils/release/test-release.sh (original) +++ llvm/trunk/utils/release/test-release.sh Wed Sep 8 15:21:11 2010 @@ -270,12 +270,10 @@ echo "# Configuring llvm-gcc $Release-rc$RC $Flavor" echo "# $llvmgcc42_srcdir/configure --prefix=$InstallDir \ --program-prefix=llvm- --enable-llvm=$llvmObjDir \ - --enable-languages=$languages \ - --with-gxx-include-dir=/usr/include/c++/4.2.1" + --enable-languages=$languages" $llvmgcc42_srcdir/configure --prefix=$InstallDir \ --program-prefix=llvm- --enable-llvm=$llvmObjDir \ --enable-languages=$languages \ - --with-gxx-include-dir=/usr/include/c++/4.2.1 \ > $LogDir/llvm-gcc.configure.$Release-rc$RC-Phase$Phase-$Flavor.log 2>&1 cd - } From resistor at mac.com Wed Sep 8 15:48:43 2010 From: resistor at mac.com (Owen Anderson) Date: Wed, 08 Sep 2010 13:48:43 -0700 Subject: [llvm-commits] [llvm] r113306 - /llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp In-Reply-To: <20100907231530.DF7422A6C12C@llvm.org> References: <20100907231530.DF7422A6C12C@llvm.org> Message-ID: <944B1EDF-344F-4F64-B683-BCF41291634A@mac.com> On Sep 7, 2010, at 4:15 PM, Owen Anderson wrote: > Author: resistor > Date: Tue Sep 7 18:15:30 2010 > New Revision: 113306 > > URL: http://llvm.org/viewvc/llvm-project?rev=113306&view=rev > Log: > Add a separate unrolling threshold when the current function is being optimized for size. > The threshold value of 50 is arbitrary, and I chose it simply by analogy to the inlining thresholds, where > the baseline unrolling threshold is slightly smaller than the baseline inlining threshold. This could > undoubtedly use some tuning. Actually, after researching this, it looks like 50 is a pretty decent threshold choice, as evidenced by the attached data from SPEC2000/2006: -------------- next part -------------- A non-text attachment was scrubbed... Name: CodeSize.png Type: image/png Size: 27210 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100908/6bd4b459/attachment.png -------------- next part -------------- --Owen From bigcheesegs at gmail.com Wed Sep 8 15:49:40 2010 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Wed, 08 Sep 2010 20:49:40 -0000 Subject: [llvm-commits] [llvm] r113405 - /llvm/trunk/cmake/modules/VersionFromVCS.cmake Message-ID: <20100908204940.455822A6C12C@llvm.org> Author: mspencer Date: Wed Sep 8 15:49:40 2010 New Revision: 113405 URL: http://llvm.org/viewvc/llvm-project?rev=113405&view=rev Log: CMake: Use the svn revision information from git-svn if available. Modified: llvm/trunk/cmake/modules/VersionFromVCS.cmake Modified: llvm/trunk/cmake/modules/VersionFromVCS.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/VersionFromVCS.cmake?rev=113405&r1=113404&r2=113405&view=diff ============================================================================== --- llvm/trunk/cmake/modules/VersionFromVCS.cmake (original) +++ llvm/trunk/cmake/modules/VersionFromVCS.cmake Wed Sep 8 15:49:40 2010 @@ -10,7 +10,7 @@ if( Subversion_FOUND ) subversion_wc_info( ${CMAKE_CURRENT_SOURCE_DIR} Project ) if( Project_WC_REVISION ) - set(result "${result}-r${Project_WC_REVISION}") + set(result "${result}-r${Project_WC_REVISION}") endif() endif() elseif( EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/.git ) @@ -19,13 +19,23 @@ find_program(git_executable NAMES git git.exe git.cmd) if( git_executable ) execute_process(COMMAND ${git_executable} show-ref HEAD - WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} - TIMEOUT 5 - RESULT_VARIABLE git_result - OUTPUT_VARIABLE git_output) + WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} + TIMEOUT 5 + RESULT_VARIABLE git_result + OUTPUT_VARIABLE git_output) if( git_result EQUAL 0 ) - string(SUBSTRING ${git_output} 0 7 git_ref_id) - set(result "${result}-${git_ref_id}") + string(SUBSTRING ${git_output} 0 7 git_ref_id) + set(result "${result}-${git_ref_id}") + else() + execute_process(COMMAND ${git_executable} svn log --limit=1 --oneline + WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} + TIMEOUT 5 + RESULT_VARIABLE git_result + OUTPUT_VARIABLE git_output) + if( git_result EQUAL 0 ) + string(REGEX MATCH r[0-9]+ git_svn_rev ${git_output}) + set(result "${result}-svn-${git_svn_rev}") + endif() endif() endif() endif() From dalej at apple.com Wed Sep 8 15:54:01 2010 From: dalej at apple.com (Dale Johannesen) Date: Wed, 08 Sep 2010 20:54:01 -0000 Subject: [llvm-commits] [llvm] r113406 - /llvm/trunk/lib/Target/X86/X86InstrMMX.td Message-ID: <20100908205401.24A4C2A6C12C@llvm.org> Author: johannes Date: Wed Sep 8 15:54:00 2010 New Revision: 113406 URL: http://llvm.org/viewvc/llvm-project?rev=113406&view=rev Log: Slight cleanup, use only one form of MMXI_binop_rm_int. Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrMMX.td?rev=113406&r1=113405&r2=113406&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrMMX.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrMMX.td Wed Sep 8 15:54:00 2010 @@ -35,29 +35,13 @@ (load_mmx addr:$src2)))))]>; } - // MMXI_binop_rm_int - Simple MMX binary operator based on intrinsic. - multiclass MMXI_binop_rm_int opc, string OpcodeStr, Intrinsic IntId, - bit Commutable = 0> { - def rr : MMXI { - let isCommutable = Commutable; - } - def rm : MMXI; - } - - // MMXI_binop_rm_int2 - Simple MMX binary operator based on intrinsic, with a + // MMXI_binop_rm_int - Simple MMX binary operator based on intrinsic, with a // different name for the generated instructions than MMXI_binop_rm uses. - // Thus int2 and rm can coexist for different implementations of the same - // instruction, while int and rm cannot. This is temporary during transition - // to intrinsic-only implementation. When it is removed, remove the FIXME - // from X86RecognizableInstr.cpp. - multiclass MMXI_binop_rm_int2 opc, string OpcodeStr, Intrinsic IntId, + // Thus int and rm can coexist for different implementations of the same + // instruction. This is temporary during transition to intrinsic-only + // implementation; eventually the non-intrinsic forms will go away. When + // When this is cleaned up, remove the FIXME from X86RecognizableInstr.cpp. + multiclass MMXI_binop_rm_int opc, string OpcodeStr, Intrinsic IntId, bit Commutable = 0> { def irr : MMXI, - MMXI_binop_rm_int2<0xFC, "paddb", int_x86_mmx_padd_b, 1>; + MMXI_binop_rm_int<0xFC, "paddb", int_x86_mmx_padd_b, 1>; defm MMX_PADDW : MMXI_binop_rm<0xFD, "paddw", add, v4i16, 1>, - MMXI_binop_rm_int2<0xFD, "paddw", int_x86_mmx_padd_w, 1>; + MMXI_binop_rm_int<0xFD, "paddw", int_x86_mmx_padd_w, 1>; defm MMX_PADDD : MMXI_binop_rm<0xFE, "paddd", add, v2i32, 1>, - MMXI_binop_rm_int2<0xFE, "paddd", int_x86_mmx_padd_d, 1>; + MMXI_binop_rm_int<0xFE, "paddd", int_x86_mmx_padd_d, 1>; defm MMX_PADDQ : MMXI_binop_rm<0xD4, "paddq", add, v1i64, 1>, - MMXI_binop_rm_int2<0xD4, "paddq", int_x86_mmx_padd_q, 1>; + MMXI_binop_rm_int<0xD4, "paddq", int_x86_mmx_padd_q, 1>; defm MMX_PADDSB : MMXI_binop_rm_int<0xEC, "paddsb" , int_x86_mmx_padds_b, 1>; defm MMX_PADDSW : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w, 1>; @@ -226,13 +210,13 @@ // -- Subtraction defm MMX_PSUBB : MMXI_binop_rm<0xF8, "psubb", sub, v8i8>, - MMXI_binop_rm_int2<0xF8, "psubb", int_x86_mmx_psub_b>; + MMXI_binop_rm_int<0xF8, "psubb", int_x86_mmx_psub_b>; defm MMX_PSUBW : MMXI_binop_rm<0xF9, "psubw", sub, v4i16>, - MMXI_binop_rm_int2<0xF9, "psubw", int_x86_mmx_psub_w>; + MMXI_binop_rm_int<0xF9, "psubw", int_x86_mmx_psub_w>; defm MMX_PSUBD : MMXI_binop_rm<0xFA, "psubd", sub, v2i32>, - MMXI_binop_rm_int2<0xFA, "psubd", int_x86_mmx_psub_d>; + MMXI_binop_rm_int<0xFA, "psubd", int_x86_mmx_psub_d>; defm MMX_PSUBQ : MMXI_binop_rm<0xFB, "psubq", sub, v1i64>, - MMXI_binop_rm_int2<0xFB, "psubq", int_x86_mmx_psub_q>; + MMXI_binop_rm_int<0xFB, "psubq", int_x86_mmx_psub_q>; defm MMX_PSUBSB : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b>; defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w>; @@ -242,7 +226,7 @@ // -- Multiplication defm MMX_PMULLW : MMXI_binop_rm<0xD5, "pmullw", mul, v4i16, 1>, - MMXI_binop_rm_int2<0xD5, "pmullw", int_x86_mmx_pmull_w, 1>; + MMXI_binop_rm_int<0xD5, "pmullw", int_x86_mmx_pmull_w, 1>; defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw", int_x86_mmx_pmulh_w, 1>; defm MMX_PMULHUW : MMXI_binop_rm_int<0xE4, "pmulhuw", int_x86_mmx_pmulhu_w, 1>; @@ -264,12 +248,12 @@ // Logical Instructions defm MMX_PAND : MMXI_binop_rm_v1i64<0xDB, "pand", and, 1>, - MMXI_binop_rm_int2<0xDB, "pand", int_x86_mmx_pand, 1>; + MMXI_binop_rm_int<0xDB, "pand", int_x86_mmx_pand, 1>; defm MMX_POR : MMXI_binop_rm_v1i64<0xEB, "por" , or, 1>, - MMXI_binop_rm_int2<0xEB, "por" , int_x86_mmx_por, 1>; + MMXI_binop_rm_int<0xEB, "por" , int_x86_mmx_por, 1>; defm MMX_PXOR : MMXI_binop_rm_v1i64<0xEF, "pxor", xor, 1>, - MMXI_binop_rm_int2<0xEF, "pxor", int_x86_mmx_pxor, 1>; -defm MMX_PANDN : MMXI_binop_rm_int2<0xDF, "pandn", int_x86_mmx_pandn, 1>; + MMXI_binop_rm_int<0xEF, "pxor", int_x86_mmx_pxor, 1>; +defm MMX_PANDN : MMXI_binop_rm_int<0xDF, "pandn", int_x86_mmx_pandn, 1>; let Constraints = "$src1 = $dst" in { def MMX_PANDNrr : MMXI<0xDF, MRMSrcReg, @@ -397,17 +381,17 @@ (v2i32 (mmx_unpckl VR64:$src1, (bc_v2i32 (load_mmx addr:$src2)))))]>; } -defm MMX_PUNPCKHBW : MMXI_binop_rm_int2<0x68, "punpckhbw", +defm MMX_PUNPCKHBW : MMXI_binop_rm_int<0x68, "punpckhbw", int_x86_mmx_punpckhbw>; -defm MMX_PUNPCKHWD : MMXI_binop_rm_int2<0x69, "punpckhwd", +defm MMX_PUNPCKHWD : MMXI_binop_rm_int<0x69, "punpckhwd", int_x86_mmx_punpckhwd>; -defm MMX_PUNPCKHDQ : MMXI_binop_rm_int2<0x6A, "punpckhdq", +defm MMX_PUNPCKHDQ : MMXI_binop_rm_int<0x6A, "punpckhdq", int_x86_mmx_punpckhdq>; -defm MMX_PUNPCKLBW : MMXI_binop_rm_int2<0x60, "punpcklbw", +defm MMX_PUNPCKLBW : MMXI_binop_rm_int<0x60, "punpcklbw", int_x86_mmx_punpcklbw>; -defm MMX_PUNPCKLWD : MMXI_binop_rm_int2<0x61, "punpcklwd", +defm MMX_PUNPCKLWD : MMXI_binop_rm_int<0x61, "punpcklwd", int_x86_mmx_punpcklwd>; -defm MMX_PUNPCKLDQ : MMXI_binop_rm_int2<0x62, "punpckldq", +defm MMX_PUNPCKLDQ : MMXI_binop_rm_int<0x62, "punpckldq", int_x86_mmx_punpckldq>; // -- Pack Instructions @@ -723,30 +707,30 @@ // Patterns for vector comparisons def : Pat<(v8i8 (X86pcmpeqb VR64:$src1, VR64:$src2)), - (MMX_PCMPEQBrr VR64:$src1, VR64:$src2)>; + (MMX_PCMPEQBirr VR64:$src1, VR64:$src2)>; def : Pat<(v8i8 (X86pcmpeqb VR64:$src1, (bitconvert (load_mmx addr:$src2)))), - (MMX_PCMPEQBrm VR64:$src1, addr:$src2)>; + (MMX_PCMPEQBirm VR64:$src1, addr:$src2)>; def : Pat<(v4i16 (X86pcmpeqw VR64:$src1, VR64:$src2)), - (MMX_PCMPEQWrr VR64:$src1, VR64:$src2)>; + (MMX_PCMPEQWirr VR64:$src1, VR64:$src2)>; def : Pat<(v4i16 (X86pcmpeqw VR64:$src1, (bitconvert (load_mmx addr:$src2)))), - (MMX_PCMPEQWrm VR64:$src1, addr:$src2)>; + (MMX_PCMPEQWirm VR64:$src1, addr:$src2)>; def : Pat<(v2i32 (X86pcmpeqd VR64:$src1, VR64:$src2)), - (MMX_PCMPEQDrr VR64:$src1, VR64:$src2)>; + (MMX_PCMPEQDirr VR64:$src1, VR64:$src2)>; def : Pat<(v2i32 (X86pcmpeqd VR64:$src1, (bitconvert (load_mmx addr:$src2)))), - (MMX_PCMPEQDrm VR64:$src1, addr:$src2)>; + (MMX_PCMPEQDirm VR64:$src1, addr:$src2)>; def : Pat<(v8i8 (X86pcmpgtb VR64:$src1, VR64:$src2)), - (MMX_PCMPGTBrr VR64:$src1, VR64:$src2)>; + (MMX_PCMPGTBirr VR64:$src1, VR64:$src2)>; def : Pat<(v8i8 (X86pcmpgtb VR64:$src1, (bitconvert (load_mmx addr:$src2)))), - (MMX_PCMPGTBrm VR64:$src1, addr:$src2)>; + (MMX_PCMPGTBirm VR64:$src1, addr:$src2)>; def : Pat<(v4i16 (X86pcmpgtw VR64:$src1, VR64:$src2)), - (MMX_PCMPGTWrr VR64:$src1, VR64:$src2)>; + (MMX_PCMPGTWirr VR64:$src1, VR64:$src2)>; def : Pat<(v4i16 (X86pcmpgtw VR64:$src1, (bitconvert (load_mmx addr:$src2)))), - (MMX_PCMPGTWrm VR64:$src1, addr:$src2)>; + (MMX_PCMPGTWirm VR64:$src1, addr:$src2)>; def : Pat<(v2i32 (X86pcmpgtd VR64:$src1, VR64:$src2)), - (MMX_PCMPGTDrr VR64:$src1, VR64:$src2)>; + (MMX_PCMPGTDirr VR64:$src1, VR64:$src2)>; def : Pat<(v2i32 (X86pcmpgtd VR64:$src1, (bitconvert (load_mmx addr:$src2)))), - (MMX_PCMPGTDrm VR64:$src1, addr:$src2)>; + (MMX_PCMPGTDirm VR64:$src1, addr:$src2)>; // CMOV* - Used to implement the SELECT DAG operation. Expanded after // instruction selection into a branch sequence. From dalej at apple.com Wed Sep 8 16:09:49 2010 From: dalej at apple.com (Dale Johannesen) Date: Wed, 08 Sep 2010 21:09:49 -0000 Subject: [llvm-commits] [llvm] r113409 - /llvm/trunk/lib/Target/X86/X86MCInstLower.cpp Message-ID: <20100908210949.1BFA52A6C12C@llvm.org> Author: johannes Date: Wed Sep 8 16:09:48 2010 New Revision: 113409 URL: http://llvm.org/viewvc/llvm-project?rev=113409&view=rev Log: Check in forgotten file. Should fix build. Modified: llvm/trunk/lib/Target/X86/X86MCInstLower.cpp Modified: llvm/trunk/lib/Target/X86/X86MCInstLower.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MCInstLower.cpp?rev=113409&r1=113408&r2=113409&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86MCInstLower.cpp (original) +++ llvm/trunk/lib/Target/X86/X86MCInstLower.cpp Wed Sep 8 16:09:48 2010 @@ -379,7 +379,7 @@ case X86::MOV32r0: LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); break; case X86::MMX_V_SET0: LowerUnaryToTwoAddr(OutMI, X86::MMX_PXORrr); break; case X86::MMX_V_SETALLONES: - LowerUnaryToTwoAddr(OutMI, X86::MMX_PCMPEQDrr); break; + LowerUnaryToTwoAddr(OutMI, X86::MMX_PCMPEQDirr); break; case X86::FsFLD0SS: LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break; case X86::FsFLD0SD: LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break; case X86::V_SET0PS: LowerUnaryToTwoAddr(OutMI, X86::XORPSrr); break; From echristo at apple.com Wed Sep 8 16:12:20 2010 From: echristo at apple.com (Eric Christopher) Date: Wed, 8 Sep 2010 14:12:20 -0700 Subject: [llvm-commits] [llvm] r113409 - /llvm/trunk/lib/Target/X86/X86MCInstLower.cpp In-Reply-To: <20100908210949.1BFA52A6C12C@llvm.org> References: <20100908210949.1BFA52A6C12C@llvm.org> Message-ID: <3AAE3805-8068-4C75-8A52-3538B81CD902@apple.com> On Sep 8, 2010, at 2:09 PM, Dale Johannesen wrote: > Author: johannes > Date: Wed Sep 8 16:09:48 2010 > New Revision: 113409 > > URL: http://llvm.org/viewvc/llvm-project?rev=113409&view=rev > Log: > Check in forgotten file. Should fix build. Thanks Dale! -eric From isanbard at gmail.com Wed Sep 8 16:15:16 2010 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 08 Sep 2010 21:15:16 -0000 Subject: [llvm-commits] [test-suite] r113410 - in /test-suite/branches/release_28: autoconf/configure.ac configure Message-ID: <20100908211516.605792A6C12C@llvm.org> Author: void Date: Wed Sep 8 16:15:16 2010 New Revision: 113410 URL: http://llvm.org/viewvc/llvm-project?rev=113410&view=rev Log: Change version from 2.8svn to 2.8rc. Modified: test-suite/branches/release_28/autoconf/configure.ac test-suite/branches/release_28/configure Modified: test-suite/branches/release_28/autoconf/configure.ac URL: http://llvm.org/viewvc/llvm-project/test-suite/branches/release_28/autoconf/configure.ac?rev=113410&r1=113409&r2=113410&view=diff ============================================================================== --- test-suite/branches/release_28/autoconf/configure.ac (original) +++ test-suite/branches/release_28/autoconf/configure.ac Wed Sep 8 16:15:16 2010 @@ -1,5 +1,5 @@ dnl Initialize autoconf -AC_INIT([[LLVM-TEST]],[[2.8svn]],[llvmbugs at cs.uiuc.edu]) +AC_INIT([[LLVM-TEST]],[[2.8rc]],[llvmbugs at cs.uiuc.edu]) dnl Place all of the extra autoconf files into the config subdirectory AC_CONFIG_AUX_DIR([autoconf]) Modified: test-suite/branches/release_28/configure URL: http://llvm.org/viewvc/llvm-project/test-suite/branches/release_28/configure?rev=113410&r1=113409&r2=113410&view=diff ============================================================================== --- test-suite/branches/release_28/configure (original) +++ test-suite/branches/release_28/configure Wed Sep 8 16:15:16 2010 @@ -1,6 +1,6 @@ #! /bin/sh # Guess values for system-dependent variables and create Makefiles. -# Generated by GNU Autoconf 2.60 for LLVM-TEST 2.8svn. +# Generated by GNU Autoconf 2.60 for LLVM-TEST 2.8rc. # # Report bugs to . # @@ -713,8 +713,8 @@ # Identity of this package. PACKAGE_NAME='LLVM-TEST' PACKAGE_TARNAME='-llvm-test-' -PACKAGE_VERSION='2.8svn' -PACKAGE_STRING='LLVM-TEST 2.8svn' +PACKAGE_VERSION='2.8rc' +PACKAGE_STRING='LLVM-TEST 2.8rc' PACKAGE_BUGREPORT='llvmbugs at cs.uiuc.edu' ac_unique_file="SingleSource/Benchmarks/Makefile" @@ -1382,7 +1382,7 @@ # Omit some internal or obsolete options to make the list less imposing. # This message is too long to be a string in the A/UX 3.1 sh. cat <<_ACEOF -\`configure' configures LLVM-TEST 2.8svn to adapt to many kinds of systems. +\`configure' configures LLVM-TEST 2.8rc to adapt to many kinds of systems. Usage: $0 [OPTION]... [VAR=VALUE]... @@ -1447,7 +1447,7 @@ if test -n "$ac_init_help"; then case $ac_init_help in - short | recursive ) echo "Configuration of LLVM-TEST 2.8svn:";; + short | recursive ) echo "Configuration of LLVM-TEST 2.8rc:";; esac cat <<\_ACEOF @@ -1564,7 +1564,7 @@ test -n "$ac_init_help" && exit $ac_status if $ac_init_version; then cat <<\_ACEOF -LLVM-TEST configure 2.8svn +LLVM-TEST configure 2.8rc generated by GNU Autoconf 2.60 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, @@ -1578,7 +1578,7 @@ This file contains any messages produced by compilers while running configure, to aid debugging if configure makes a mistake. -It was created by LLVM-TEST $as_me 2.8svn, which was +It was created by LLVM-TEST $as_me 2.8rc, which was generated by GNU Autoconf 2.60. Invocation command line was $ $0 $@ @@ -20888,7 +20888,7 @@ # report actual input values of CONFIG_FILES etc. instead of their # values after options handling. ac_log=" -This file was extended by LLVM-TEST $as_me 2.8svn, which was +This file was extended by LLVM-TEST $as_me 2.8rc, which was generated by GNU Autoconf 2.60. Invocation command line was CONFIG_FILES = $CONFIG_FILES @@ -20935,7 +20935,7 @@ _ACEOF cat >>$CONFIG_STATUS <<_ACEOF ac_cs_version="\\ -LLVM-TEST config.status 2.8svn +LLVM-TEST config.status 2.8rc configured by $0, generated by GNU Autoconf 2.60, with options \\"`echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`\\" From stoklund at 2pi.dk Wed Sep 8 16:21:29 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 08 Sep 2010 21:21:29 -0000 Subject: [llvm-commits] [llvm] r113411 - /llvm/trunk/include/llvm/CodeGen/LiveInterval.h Message-ID: <20100908212129.1998C2A6C12C@llvm.org> Author: stoklund Date: Wed Sep 8 16:21:28 2010 New Revision: 113411 URL: http://llvm.org/viewvc/llvm-project?rev=113411&view=rev Log: Remove dead code and data. Modified: llvm/trunk/include/llvm/CodeGen/LiveInterval.h Modified: llvm/trunk/include/llvm/CodeGen/LiveInterval.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveInterval.h?rev=113411&r1=113410&r2=113411&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/LiveInterval.h (original) +++ llvm/trunk/include/llvm/CodeGen/LiveInterval.h Wed Sep 8 16:21:28 2010 @@ -61,10 +61,7 @@ }; unsigned char flags; - union { - MachineInstr *copy; - unsigned reg; - } cr; + MachineInstr *copy; public: typedef BumpPtrAllocator Allocator; @@ -79,17 +76,17 @@ /// d is presumed to point to the actual defining instr. If it doesn't /// setIsDefAccurate(false) should be called after construction. VNInfo(unsigned i, SlotIndex d, MachineInstr *c) - : flags(IS_DEF_ACCURATE), id(i), def(d) { cr.copy = c; } + : flags(IS_DEF_ACCURATE), id(i), def(d) { copy = c; } /// VNInfo construtor, copies values from orig, except for the value number. VNInfo(unsigned i, const VNInfo &orig) - : flags(orig.flags), cr(orig.cr), id(i), def(orig.def) + : flags(orig.flags), copy(orig.copy), id(i), def(orig.def) { } /// Copy from the parameter into this VNInfo. void copyFrom(VNInfo &src) { flags = src.flags; - cr = src.cr; + copy = src.copy; def = src.def; } @@ -100,20 +97,11 @@ /// For a register interval, if this VN was definied by a copy instr /// getCopy() returns a pointer to it, otherwise returns 0. /// For a stack interval the behaviour of this method is undefined. - MachineInstr* getCopy() const { return cr.copy; } + MachineInstr* getCopy() const { return copy; } /// For a register interval, set the copy member. /// This method should not be called on stack intervals as it may lead to /// undefined behavior. - void setCopy(MachineInstr *c) { cr.copy = c; } - - /// For a stack interval, returns the reg which this stack interval was - /// defined from. - /// For a register interval the behaviour of this method is undefined. - unsigned getReg() const { return cr.reg; } - /// For a stack interval, set the defining register. - /// This method should not be called on register intervals as it may lead - /// to undefined behaviour. - void setReg(unsigned reg) { cr.reg = reg; } + void setCopy(MachineInstr *c) { copy = c; } /// Returns true if one or more kills are PHI nodes. bool hasPHIKill() const { return flags & HAS_PHI_KILL; } From echristo at apple.com Wed Sep 8 16:49:50 2010 From: echristo at apple.com (Eric Christopher) Date: Wed, 08 Sep 2010 21:49:50 -0000 Subject: [llvm-commits] [llvm] r113417 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20100908214950.41DFB2A6C12C@llvm.org> Author: echristo Date: Wed Sep 8 16:49:50 2010 New Revision: 113417 URL: http://llvm.org/viewvc/llvm-project?rev=113417&view=rev Log: Make the loads/stores match the type we really want to store. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=113417&r1=113416&r2=113417&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Wed Sep 8 16:49:50 2010 @@ -120,8 +120,8 @@ bool isLoadTypeLegal(const Type *Ty, EVT &VT); bool ARMEmitLoad(EVT VT, unsigned &ResultReg, unsigned Reg, int Offset); bool ARMEmitStore(EVT VT, unsigned SrcReg, unsigned Reg, int Offset); - bool ARMLoadAlloca(const Instruction *I); - bool ARMStoreAlloca(const Instruction *I, unsigned SrcReg); + bool ARMLoadAlloca(const Instruction *I, EVT VT); + bool ARMStoreAlloca(const Instruction *I, unsigned SrcReg, EVT VT); bool ARMComputeRegOffset(const Value *Obj, unsigned &Reg, int &Offset); bool ARMMaterializeConstant(const ConstantInt *Val, unsigned &Reg); @@ -461,7 +461,7 @@ return true; } -bool ARMFastISel::ARMLoadAlloca(const Instruction *I) { +bool ARMFastISel::ARMLoadAlloca(const Instruction *I, EVT VT) { Value *Op0 = I->getOperand(0); // Verify it's an alloca. @@ -470,7 +470,7 @@ FuncInfo.StaticAllocaMap.find(AI); if (SI != FuncInfo.StaticAllocaMap.end()) { - TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy()); + TargetRegisterClass* RC = TLI.getRegClassFor(VT); unsigned ResultReg = createResultReg(RC); TII.loadRegFromStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt, ResultReg, SI->second, RC, @@ -521,7 +521,7 @@ return true; } -bool ARMFastISel::ARMStoreAlloca(const Instruction *I, unsigned SrcReg) { +bool ARMFastISel::ARMStoreAlloca(const Instruction *I, unsigned SrcReg, EVT VT){ Value *Op1 = I->getOperand(1); // Verify it's an alloca. @@ -530,7 +530,7 @@ FuncInfo.StaticAllocaMap.find(AI); if (SI != FuncInfo.StaticAllocaMap.end()) { - TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy()); + TargetRegisterClass* RC = TLI.getRegClassFor(VT); assert(SrcReg != 0 && "Nothing to store!"); TII.storeRegToStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt, SrcReg, true /*isKill*/, SI->second, RC, @@ -588,7 +588,7 @@ // If we're an alloca we know we have a frame index and can emit the store // quickly. - if (ARMStoreAlloca(I, SrcReg)) + if (ARMStoreAlloca(I, SrcReg, VT)) return true; // Our register and offset with innocuous defaults. @@ -606,16 +606,16 @@ } bool ARMFastISel::ARMSelectLoad(const Instruction *I) { - // If we're an alloca we know we have a frame index and can emit the load - // directly in short order. - if (ARMLoadAlloca(I)) - return true; - // Verify we have a legal type before going any further. EVT VT; if (!isLoadTypeLegal(I->getType(), VT)) return false; + // If we're an alloca we know we have a frame index and can emit the load + // directly in short order. + if (ARMLoadAlloca(I, VT)) + return true; + // Our register and offset with innocuous defaults. unsigned Reg = 0; int Offset = 0; From dalej at apple.com Wed Sep 8 17:08:41 2010 From: dalej at apple.com (Dale Johannesen) Date: Wed, 08 Sep 2010 22:08:41 -0000 Subject: [llvm-commits] [llvm] r113420 - /llvm/trunk/lib/Target/X86/X86InstrMMX.td Message-ID: <20100908220841.2D5052A6C12C@llvm.org> Author: johannes Date: Wed Sep 8 17:08:40 2010 New Revision: 113420 URL: http://llvm.org/viewvc/llvm-project?rev=113420&view=rev Log: Add intrinsic-based patterns for MMX PINSRW and PEXTRW. Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrMMX.td?rev=113420&r1=113419&r2=113420&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrMMX.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrMMX.td Wed Sep 8 17:08:40 2010 @@ -518,6 +518,11 @@ "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}", [(set GR32:$dst, (X86pextrw (v4i16 VR64:$src1), (iPTR imm:$src2)))]>; +def MMX_PEXTRWirri: MMXIi8<0xC5, MRMSrcReg, + (outs GR32:$dst), (ins VR64:$src1, i32i8imm:$src2), + "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}", + [(set GR32:$dst, (int_x86_mmx_pextr_w VR64:$src1, + (iPTR imm:$src2)))]>; let Constraints = "$src1 = $dst" in { def MMX_PINSRWrri : MMXIi8<0xC4, MRMSrcReg, (outs VR64:$dst), @@ -533,6 +538,20 @@ (v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1), (i32 (anyext (loadi16 addr:$src2))), (iPTR imm:$src3))))]>; + def MMX_PINSRWirri : MMXIi8<0xC4, MRMSrcReg, + (outs VR64:$dst), + (ins VR64:$src1, GR32:$src2, i32i8imm:$src3), + "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1, + GR32:$src2, (iPTR imm:$src3)))]>; + + def MMX_PINSRWirmi : MMXIi8<0xC4, MRMSrcMem, + (outs VR64:$dst), + (ins VR64:$src1, i16mem:$src2, i32i8imm:$src3), + "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}", + [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1, + (i32 (anyext (loadi16 addr:$src2))), + (iPTR imm:$src3)))]>; } // MMX to XMM for vector types From sabre at nondot.org Wed Sep 8 17:13:08 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 08 Sep 2010 22:13:08 -0000 Subject: [llvm-commits] [llvm] r113422 - in /llvm/trunk: lib/Target/X86/AsmParser/X86AsmParser.cpp lib/Target/X86/X86InstrInfo.td test/MC/AsmParser/X86/x86_32-new-encoder.s test/MC/AsmParser/X86/x86_64-new-encoder.s utils/TableGen/EDEmitter.cpp Message-ID: <20100908221309.19FE82A6C12C@llvm.org> Author: lattner Date: Wed Sep 8 17:13:08 2010 New Revision: 113422 URL: http://llvm.org/viewvc/llvm-project?rev=113422&view=rev Log: fix bugs in push/pop segment support, rdar://8407242 Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.td llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s llvm/trunk/utils/TableGen/EDEmitter.cpp Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=113422&r1=113421&r2=113422&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Wed Sep 8 17:13:08 2010 @@ -630,6 +630,7 @@ .Case("iret", "iretl") .Case("sysret", "sysretl") .Case("push", Is64Bit ? "pushq" : "pushl") + .Case("pop", Is64Bit ? "popq" : "popl") .Case("pushf", Is64Bit ? "pushfq" : "pushfl") .Case("popf", Is64Bit ? "popfq" : "popfl") .Case("retl", Is64Bit ? "retl" : "ret") Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=113422&r1=113421&r2=113422&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Wed Sep 8 17:13:08 2010 @@ -4274,23 +4274,53 @@ def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src), "ltr{w}\t{$src}", []>, TB; +def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins), + "push{w}\t%cs", []>, Requires<[In32BitMode]>, OpSize; +def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins), + "push{l}\t%cs", []>, Requires<[In32BitMode]>; +def PUSHSS16 : I<0x16, RawFrm, (outs), (ins), + "push{w}\t%ss", []>, Requires<[In32BitMode]>, OpSize; +def PUSHSS32 : I<0x16, RawFrm, (outs), (ins), + "push{l}\t%ss", []>, Requires<[In32BitMode]>; +def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins), + "push{w}\t%ds", []>, Requires<[In32BitMode]>, OpSize; +def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins), + "push{l}\t%ds", []>, Requires<[In32BitMode]>; +def PUSHES16 : I<0x06, RawFrm, (outs), (ins), + "push{w}\t%es", []>, Requires<[In32BitMode]>, OpSize; +def PUSHES32 : I<0x06, RawFrm, (outs), (ins), + "push{l}\t%es", []>, Requires<[In32BitMode]>; + def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins), "push{w}\t%fs", []>, OpSize, TB; def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins), - "push{l}\t%fs", []>, TB; + "push{l}\t%fs", []>, TB, Requires<[In32BitMode]>; def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins), "push{w}\t%gs", []>, OpSize, TB; def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins), - "push{l}\t%gs", []>, TB; + "push{l}\t%gs", []>, TB, Requires<[In32BitMode]>; +// No "pop cs" instruction. +def POPSS16 : I<0x17, RawFrm, (outs), (ins), + "pop{w}\t%ss", []>, OpSize, Requires<[In32BitMode]>; +def POPSS32 : I<0x17, RawFrm, (outs), (ins), + "pop{l}\t%ss", []> , Requires<[In32BitMode]>; +def POPDS16 : I<0x1F, RawFrm, (outs), (ins), + "pop{w}\t%ds", []>, OpSize, Requires<[In32BitMode]>; +def POPDS32 : I<0x1F, RawFrm, (outs), (ins), + "pop{l}\t%ds", []> , Requires<[In32BitMode]>; +def POPES16 : I<0x07, RawFrm, (outs), (ins), + "pop{w}\t%es", []>, OpSize, Requires<[In32BitMode]>; +def POPES32 : I<0x07, RawFrm, (outs), (ins), + "pop{l}\t%es", []> , Requires<[In32BitMode]>; def POPFS16 : I<0xa1, RawFrm, (outs), (ins), "pop{w}\t%fs", []>, OpSize, TB; def POPFS32 : I<0xa1, RawFrm, (outs), (ins), - "pop{l}\t%fs", []>, TB; + "pop{l}\t%fs", []>, TB , Requires<[In32BitMode]>; def POPGS16 : I<0xa9, RawFrm, (outs), (ins), "pop{w}\t%gs", []>, OpSize, TB; def POPGS32 : I<0xa9, RawFrm, (outs), (ins), - "pop{l}\t%gs", []>, TB; + "pop{l}\t%gs", []>, TB , Requires<[In32BitMode]>; def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src), "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize; Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s?rev=113422&r1=113421&r2=113422&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s Wed Sep 8 17:13:08 2010 @@ -459,3 +459,52 @@ testl -24(%ebp), %ecx // CHECK: testl -24(%ebp), %ecx + +// rdar://8407242 +push %cs +// CHECK: pushl %cs +// CHECK: encoding: [0x0e] +push %ds +// CHECK: pushl %ds +// CHECK: encoding: [0x1e] +push %ss +// CHECK: pushl %ss +// CHECK: encoding: [0x16] +push %es +// CHECK: pushl %es +// CHECK: encoding: [0x06] +push %fs +// CHECK: pushl %fs +// CHECK: encoding: [0x0f,0xa0] +push %gs +// CHECK: pushl %gs +// CHECK: encoding: [0x0f,0xa8] + +pushw %cs +// CHECK: pushw %cs +// CHECK: encoding: [0x66,0x0e] +pushw %ds +// CHECK: pushw %ds +// CHECK: encoding: [0x66,0x1e] +pushw %ss +// CHECK: pushw %ss +// CHECK: encoding: [0x66,0x16] +pushw %es +// CHECK: pushw %es +// CHECK: encoding: [0x66,0x06] +pushw %fs +// CHECK: pushw %fs +// CHECK: encoding: [0x66,0x0f,0xa0] +pushw %gs +// CHECK: pushw %gs +// CHECK: encoding: [0x66,0x0f,0xa8] + +pop %ss +// CHECK: popl %ss +// CHECK: encoding: [0x17] +pop %ds +// CHECK: popl %ds +// CHECK: encoding: [0x1f] +pop %es +// CHECK: popl %es +// CHECK: encoding: [0x07] Modified: llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s?rev=113422&r1=113421&r2=113422&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s Wed Sep 8 17:13:08 2010 @@ -211,3 +211,36 @@ sysretq // CHECK: sysretq // CHECK: encoding: [0x48,0x0f,0x07] + +// rdar://8407242 +push %fs +// CHECK: pushq %fs +// CHECK: encoding: [0x0f,0xa0] +push %gs +// CHECK: pushq %gs +// CHECK: encoding: [0x0f,0xa8] + +pushw %fs +// CHECK: pushw %fs +// CHECK: encoding: [0x66,0x0f,0xa0] +pushw %gs +// CHECK: pushw %gs +// CHECK: encoding: [0x66,0x0f,0xa8] + + +pop %fs +// CHECK: popq %fs +// CHECK: encoding: [0x0f,0xa1] +pop %gs +// CHECK: popq %gs +// CHECK: encoding: [0x0f,0xa9] + +popw %fs +// CHECK: popw %fs +// CHECK: encoding: [0x66,0x0f,0xa1] +popw %gs +// CHECK: popw %gs +// CHECK: encoding: [0x66,0x0f,0xa9] + + + Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=113422&r1=113421&r2=113422&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/EDEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/EDEmitter.cpp Wed Sep 8 17:13:08 2010 @@ -461,8 +461,12 @@ } if (name.find("PUSH") != name.npos) { - if (name.find("FS") != name.npos || - name.find("GS") != name.npos) { + if (name.find("CS") != name.npos || + name.find("DS") != name.npos || + name.find("ES") != name.npos || + name.find("FS") != name.npos || + name.find("GS") != name.npos || + name.find("SS") != name.npos) { instType.set("kInstructionTypePush"); // TODO add support for fixed operands } else if (name.find("F") != name.npos) { @@ -481,8 +485,12 @@ if (name.find("POP") != name.npos) { if (name.find("POPCNT") != name.npos) { // ignore (not a real pop) - } else if (name.find("FS") != name.npos || - name.find("GS") != name.npos) { + } else if (name.find("CS") != name.npos || + name.find("DS") != name.npos || + name.find("ES") != name.npos || + name.find("FS") != name.npos || + name.find("GS") != name.npos || + name.find("SS") != name.npos) { instType.set("kInstructionTypePop"); // TODO add support for fixed operands } else if (name.find("F") != name.npos) { From resistor at mac.com Wed Sep 8 17:16:18 2010 From: resistor at mac.com (Owen Anderson) Date: Wed, 08 Sep 2010 22:16:18 -0000 Subject: [llvm-commits] [llvm] r113423 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineAndOrXor.cpp test/Transforms/InstCombine/bit-checks.ll Message-ID: <20100908221618.1EF3A2A6C12C@llvm.org> Author: resistor Date: Wed Sep 8 17:16:17 2010 New Revision: 113423 URL: http://llvm.org/viewvc/llvm-project?rev=113423&view=rev Log: Generalize instcombine's support for combining multiple bit checks into a single test. Patch by Dirk Steinke! Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp llvm/trunk/test/Transforms/InstCombine/bit-checks.ll Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp?rev=113423&r1=113422&r2=113423&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp Wed Sep 8 17:16:17 2010 @@ -434,6 +434,270 @@ return Builder->CreateAdd(LHSI->getOperand(0), RHS, "fold"); } +/// enum for classifying (icmp eq (A & B), C) and (icmp ne (A & B), C) +/// One of A and B is considered the mask, the other the value. This is +/// described as the "AMask" or "BMask" part of the enum. If the enum +/// contains only "Mask", then both A and B can be considered masks. +/// If A is the mask, then it was proven, that (A & C) == C. This +/// is trivial if C == A, or C == 0. If both A and C are constants, this +/// proof is also easy. +/// For the following explanations we assume that A is the mask. +/// The part "AllOnes" declares, that the comparison is true only +/// if (A & B) == A, or all bits of A are set in B. +/// Example: (icmp eq (A & 3), 3) -> FoldMskICmp_AMask_AllOnes +/// The part "AllZeroes" declares, that the comparison is true only +/// if (A & B) == 0, or all bits of A are cleared in B. +/// Example: (icmp eq (A & 3), 0) -> FoldMskICmp_Mask_AllZeroes +/// The part "Mixed" declares, that (A & B) == C and C might or might not +/// contain any number of one bits and zero bits. +/// Example: (icmp eq (A & 3), 1) -> FoldMskICmp_AMask_Mixed +/// The Part "Not" means, that in above descriptions "==" should be replaced +/// by "!=". +/// Example: (icmp ne (A & 3), 3) -> FoldMskICmp_AMask_NotAllOnes +/// If the mask A contains a single bit, then the following is equivalent: +/// (icmp eq (A & B), A) equals (icmp ne (A & B), 0) +/// (icmp ne (A & B), A) equals (icmp eq (A & B), 0) +enum MaskedICmpType { + FoldMskICmp_AMask_AllOnes = 1, + FoldMskICmp_AMask_NotAllOnes = 2, + FoldMskICmp_BMask_AllOnes = 4, + FoldMskICmp_BMask_NotAllOnes = 8, + FoldMskICmp_Mask_AllZeroes = 16, + FoldMskICmp_Mask_NotAllZeroes = 32, + FoldMskICmp_AMask_Mixed = 64, + FoldMskICmp_AMask_NotMixed = 128, + FoldMskICmp_BMask_Mixed = 256, + FoldMskICmp_BMask_NotMixed = 512 +}; + +/// return the set of pattern classes (from MaskedICmpType) +/// that (icmp SCC (A & B), C) satisfies +static unsigned getTypeOfMaskedICmp(Value* A, Value* B, Value* C, + ICmpInst::Predicate SCC) +{ + ConstantInt *ACst = dyn_cast(A); + ConstantInt *BCst = dyn_cast(B); + ConstantInt *CCst = dyn_cast(C); + bool icmp_eq = (SCC == ICmpInst::ICMP_EQ); + bool icmp_abit = (ACst != 0 && !ACst->isZero() && + ACst->getValue().isPowerOf2()); + bool icmp_bbit = (BCst != 0 && !BCst->isZero() && + BCst->getValue().isPowerOf2()); + unsigned result = 0; + if (CCst != 0 && CCst->isZero()) { + // if C is zero, then both A and B qualify as mask + result |= (icmp_eq ? (FoldMskICmp_Mask_AllZeroes | + FoldMskICmp_Mask_AllZeroes | + FoldMskICmp_AMask_Mixed | + FoldMskICmp_BMask_Mixed) + : (FoldMskICmp_Mask_NotAllZeroes | + FoldMskICmp_Mask_NotAllZeroes | + FoldMskICmp_AMask_NotMixed | + FoldMskICmp_BMask_NotMixed)); + if (icmp_abit) + result |= (icmp_eq ? (FoldMskICmp_AMask_NotAllOnes | + FoldMskICmp_AMask_NotMixed) + : (FoldMskICmp_AMask_AllOnes | + FoldMskICmp_AMask_Mixed)); + if (icmp_bbit) + result |= (icmp_eq ? (FoldMskICmp_BMask_NotAllOnes | + FoldMskICmp_BMask_NotMixed) + : (FoldMskICmp_BMask_AllOnes | + FoldMskICmp_BMask_Mixed)); + return result; + } + if (A == C) { + result |= (icmp_eq ? (FoldMskICmp_AMask_AllOnes | + FoldMskICmp_AMask_Mixed) + : (FoldMskICmp_AMask_NotAllOnes | + FoldMskICmp_AMask_NotMixed)); + if (icmp_abit) + result |= (icmp_eq ? (FoldMskICmp_Mask_NotAllZeroes | + FoldMskICmp_AMask_NotMixed) + : (FoldMskICmp_Mask_AllZeroes | + FoldMskICmp_AMask_Mixed)); + } + else if (ACst != 0 && CCst != 0 && + ConstantExpr::getAnd(ACst, CCst) == CCst) { + result |= (icmp_eq ? FoldMskICmp_AMask_Mixed + : FoldMskICmp_AMask_NotMixed); + } + if (B == C) + { + result |= (icmp_eq ? (FoldMskICmp_BMask_AllOnes | + FoldMskICmp_BMask_Mixed) + : (FoldMskICmp_BMask_NotAllOnes | + FoldMskICmp_BMask_NotMixed)); + if (icmp_bbit) + result |= (icmp_eq ? (FoldMskICmp_Mask_NotAllZeroes | + FoldMskICmp_BMask_NotMixed) + : (FoldMskICmp_Mask_AllZeroes | + FoldMskICmp_BMask_Mixed)); + } + else if (BCst != 0 && CCst != 0 && + ConstantExpr::getAnd(BCst, CCst) == CCst) { + result |= (icmp_eq ? FoldMskICmp_BMask_Mixed + : FoldMskICmp_BMask_NotMixed); + } + return result; +} + +/// foldLogOpOfMaskedICmpsHelper: +/// handle (icmp(A & B) ==/!= C) &/| (icmp(A & D) ==/!= E) +/// return the set of pattern classes (from MaskedICmpType) +/// that both LHS and RHS satisfy +static unsigned foldLogOpOfMaskedICmpsHelper(Value*& A, + Value*& B, Value*& C, + Value*& D, Value*& E, + ICmpInst *LHS, ICmpInst *RHS) { + ICmpInst::Predicate LHSCC = LHS->getPredicate(), RHSCC = RHS->getPredicate(); + if (LHSCC != ICmpInst::ICMP_EQ && LHSCC != ICmpInst::ICMP_NE) return 0; + if (RHSCC != ICmpInst::ICMP_EQ && RHSCC != ICmpInst::ICMP_NE) return 0; + if (LHS->getOperand(0)->getType() != RHS->getOperand(0)->getType()) return 0; + // vectors are not (yet?) supported + if (LHS->getOperand(0)->getType()->isVectorTy()) return 0; + + // Here comes the tricky part: + // LHS might be of the form L11 & L12 == X, X == L21 & L22, + // and L11 & L12 == L21 & L22. The same goes for RHS. + // Now we must find those components L** and R**, that are equal, so + // that we can extract the parameters A, B, C, D, and E for the canonical + // above. + Value *L1 = LHS->getOperand(0); + Value *L2 = LHS->getOperand(1); + Value *L11,*L12,*L21,*L22; + if (match(L1, m_And(m_Value(L11), m_Value(L12)))) { + if (!match(L2, m_And(m_Value(L21), m_Value(L22)))) + L21 = L22 = 0; + } + else { + if (!match(L2, m_And(m_Value(L11), m_Value(L12)))) + return 0; + std::swap(L1, L2); + L21 = L22 = 0; + } + + Value *R1 = RHS->getOperand(0); + Value *R2 = RHS->getOperand(1); + Value *R11,*R12; + bool ok = false; + if (match(R1, m_And(m_Value(R11), m_Value(R12)))) { + if (R11 != 0 && (R11 == L11 || R11 == L12 || R11 == L21 || R11 == L22)) { + A = R11; D = R12; E = R2; ok = true; + } + else + if (R12 != 0 && (R12 == L11 || R12 == L12 || R12 == L21 || R12 == L22)) { + A = R12; D = R11; E = R2; ok = true; + } + } + if (!ok && match(R2, m_And(m_Value(R11), m_Value(R12)))) { + if (R11 != 0 && (R11 == L11 || R11 == L12 || R11 == L21 || R11 == L22)) { + A = R11; D = R12; E = R1; ok = true; + } + else + if (R12 != 0 && (R12 == L11 || R12 == L12 || R12 == L21 || R12 == L22)) { + A = R12; D = R11; E = R1; ok = true; + } + else + return 0; + } + if (!ok) + return 0; + + if (L11 == A) { + B = L12; C = L2; + } + else if (L12 == A) { + B = L11; C = L2; + } + else if (L21 == A) { + B = L22; C = L1; + } + else if (L22 == A) { + B = L21; C = L1; + } + + unsigned left_type = getTypeOfMaskedICmp(A, B, C, LHSCC); + unsigned right_type = getTypeOfMaskedICmp(A, D, E, RHSCC); + return left_type & right_type; +} +/// foldLogOpOfMaskedICmps: +/// try to fold (icmp(A & B) ==/!= C) &/| (icmp(A & D) ==/!= E) +/// into a single (icmp(A & X) ==/!= Y) +static Value* foldLogOpOfMaskedICmps(ICmpInst *LHS, ICmpInst *RHS, + ICmpInst::Predicate NEWCC, + llvm::InstCombiner::BuilderTy* Builder) { + Value *A = 0, *B = 0, *C = 0, *D = 0, *E = 0; + unsigned mask = foldLogOpOfMaskedICmpsHelper(A, B, C, D, E, LHS, RHS); + if (mask == 0) return 0; + + if (NEWCC == ICmpInst::ICMP_NE) + mask >>= 1; // treat "Not"-states as normal states + + if (mask & FoldMskICmp_Mask_AllZeroes) { + // (icmp eq (A & B), 0) & (icmp eq (A & D), 0) + // -> (icmp eq (A & (B|D)), 0) + Value* newOr = Builder->CreateOr(B, D); + Value* newAnd = Builder->CreateAnd(A, newOr); + // we can't use C as zero, because we might actually handle + // (icmp ne (A & B), B) & (icmp ne (A & D), D) + // with B and D, having a single bit set + Value* zero = Constant::getNullValue(A->getType()); + return Builder->CreateICmp(NEWCC, newAnd, zero); + } + else if (mask & FoldMskICmp_BMask_AllOnes) { + // (icmp eq (A & B), B) & (icmp eq (A & D), D) + // -> (icmp eq (A & (B|D)), (B|D)) + Value* newOr = Builder->CreateOr(B, D); + Value* newAnd = Builder->CreateAnd(A, newOr); + return Builder->CreateICmp(NEWCC, newAnd, newOr); + } + else if (mask & FoldMskICmp_AMask_AllOnes) { + // (icmp eq (A & B), A) & (icmp eq (A & D), A) + // -> (icmp eq (A & (B&D)), A) + Value* newAnd1 = Builder->CreateAnd(B, D); + Value* newAnd = Builder->CreateAnd(A, newAnd1); + return Builder->CreateICmp(NEWCC, newAnd, A); + } + else if (mask & FoldMskICmp_BMask_Mixed) { + // (icmp eq (A & B), C) & (icmp eq (A & D), E) + // We already know that B & C == C && D & E == E. + // If we can prove that (B & D) & (C ^ E) == 0, that is, the bits of + // C and E, which are shared by both the mask B and the mask D, don't + // contradict, then we can transform to + // -> (icmp eq (A & (B|D)), (C|E)) + // Currently, we only handle the case of B, C, D, and E being constant. + ConstantInt *BCst = dyn_cast(B); + if (BCst == 0) return 0; + ConstantInt *DCst = dyn_cast(D); + if (DCst == 0) return 0; + // we can't simply use C and E, because we might actually handle + // (icmp ne (A & B), B) & (icmp eq (A & D), D) + // with B and D, having a single bit set + + ConstantInt *CCst = dyn_cast(C); + if (CCst == 0) return 0; + if (LHS->getPredicate() != NEWCC) + CCst = dyn_cast( ConstantExpr::getXor(BCst, CCst) ); + ConstantInt *ECst = dyn_cast(E); + if (ECst == 0) return 0; + if (RHS->getPredicate() != NEWCC) + ECst = dyn_cast( ConstantExpr::getXor(DCst, ECst) ); + ConstantInt* MCst = dyn_cast( + ConstantExpr::getAnd(ConstantExpr::getAnd(BCst, DCst), + ConstantExpr::getXor(CCst, ECst)) ); + // if there is a conflict we should actually return a false for the + // whole construct + if (!MCst->isZero()) + return 0; + Value* newOr1 = Builder->CreateOr(B, D); + Value* newOr2 = ConstantExpr::getOr(CCst, ECst); + Value* newAnd = Builder->CreateAnd(A, newOr1); + return Builder->CreateICmp(NEWCC, newAnd, newOr2); + } + return 0; +} + /// FoldAndOfICmps - Fold (icmp)&(icmp) if possible. Value *InstCombiner::FoldAndOfICmps(ICmpInst *LHS, ICmpInst *RHS) { ICmpInst::Predicate LHSCC = LHS->getPredicate(), RHSCC = RHS->getPredicate(); @@ -451,6 +715,13 @@ return getICmpValue(isSigned, Code, Op0, Op1, Builder); } } + + { + // handle (roughly): + // (icmp eq (A & B), C) & (icmp eq (A & D), E) + Value* fold = foldLogOpOfMaskedICmps(LHS, RHS, ICmpInst::ICMP_EQ, Builder); + if (fold) return fold; + } // This only handles icmp of constants: (icmp1 A, C1) & (icmp2 B, C2). Value *Val = LHS->getOperand(0), *Val2 = RHS->getOperand(0); @@ -472,22 +743,6 @@ Value *NewOr = Builder->CreateOr(Val, Val2); return Builder->CreateICmp(LHSCC, NewOr, LHSCst); } - - // (icmp ne (A & C1), 0) & (icmp ne (A & C2), 0) --> - // (icmp eq (A & (C1|C2)), (C1|C2)) where C1 and C2 are non-zero POT - if (LHSCC == ICmpInst::ICMP_NE && LHSCst->isZero()) { - Value *Op1 = 0, *Op2 = 0; - ConstantInt *CI1 = 0, *CI2 = 0; - if (match(LHS->getOperand(0), m_And(m_Value(Op1), m_ConstantInt(CI1))) && - match(RHS->getOperand(0), m_And(m_Value(Op2), m_ConstantInt(CI2)))) { - if (Op1 == Op2 && !CI1->isZero() && !CI2->isZero() && - CI1->getValue().isPowerOf2() && CI2->getValue().isPowerOf2()) { - Constant *ConstOr = ConstantExpr::getOr(CI1, CI2); - Value *NewAnd = Builder->CreateAnd(Op1, ConstOr); - return Builder->CreateICmp(ICmpInst::ICMP_EQ, NewAnd, ConstOr); - } - } - } } // From here on, we only handle: @@ -1161,6 +1416,13 @@ } } + { + // handle (roughly): + // (icmp ne (A & B), C) | (icmp ne (A & D), E) + Value* fold = foldLogOpOfMaskedICmps(LHS, RHS, ICmpInst::ICMP_NE, Builder); + if (fold) return fold; + } + // This only handles icmp of constants: (icmp1 A, C1) | (icmp2 B, C2). Value *Val = LHS->getOperand(0), *Val2 = RHS->getOperand(0); ConstantInt *LHSCst = dyn_cast(LHS->getOperand(1)); @@ -1173,22 +1435,6 @@ Value *NewOr = Builder->CreateOr(Val, Val2); return Builder->CreateICmp(LHSCC, NewOr, LHSCst); } - - // (icmp eq (A & C1), 0) | (icmp eq (A & C2), 0) --> - // (icmp ne (A & (C1|C2)), (C1|C2)) where C1 and C2 are non-zero POT - if (LHSCC == ICmpInst::ICMP_EQ && LHSCst->isZero()) { - Value *Op1 = 0, *Op2 = 0; - ConstantInt *CI1 = 0, *CI2 = 0; - if (match(LHS->getOperand(0), m_And(m_Value(Op1), m_ConstantInt(CI1))) && - match(RHS->getOperand(0), m_And(m_Value(Op2), m_ConstantInt(CI2)))) { - if (Op1 == Op2 && !CI1->isZero() && !CI2->isZero() && - CI1->getValue().isPowerOf2() && CI2->getValue().isPowerOf2()) { - Constant *ConstOr = ConstantExpr::getOr(CI1, CI2); - Value *NewAnd = Builder->CreateAnd(Op1, ConstOr); - return Builder->CreateICmp(ICmpInst::ICMP_NE, NewAnd, ConstOr); - } - } - } } // From here on, we only handle: Modified: llvm/trunk/test/Transforms/InstCombine/bit-checks.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/bit-checks.ll?rev=113423&r1=113422&r2=113423&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/bit-checks.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/bit-checks.ll Wed Sep 8 17:16:17 2010 @@ -23,4 +23,350 @@ %or.cond = or i1 %tobool, %tobool3 ; [#uses=1] %storemerge = select i1 %or.cond, i32 0, i32 1 ; [#uses=1] ret i32 %storemerge -} \ No newline at end of file +} + +; tests to check combining (icmp eq (A & B), C) & (icmp eq (A & D), E) +; tests to check if (icmp eq (A & B), 0) is treated like (icmp eq (A & B), B) +; if B is a single bit constant + +; (icmp eq (A & B), 0) & (icmp eq (A & D), 0) -> (icmp eq (A & (B|D)), 0) +define i32 @main3(i32 %argc, i8** nocapture %argv) nounwind readnone ssp { +entry: + %and = and i32 %argc, 7 ; [#uses=1] + %tobool = icmp eq i32 %and, 0 ; [#uses=1] + %and2 = and i32 %argc, 48 ; [#uses=1] + %tobool3 = icmp eq i32 %and2, 0 ; [#uses=1] + %and.cond = and i1 %tobool, %tobool3 ; [#uses=1] + %storemerge = select i1 %and.cond, i32 0, i32 1 ; [#uses=1] + ret i32 %storemerge +} + +define i32 @main3b(i32 %argc, i8** nocapture %argv) nounwind readnone ssp { +entry: + %and = and i32 %argc, 7 ; [#uses=1] + %tobool = icmp eq i32 %and, 0 ; [#uses=1] + %and2 = and i32 %argc, 16 ; [#uses=1] + %tobool3 = icmp ne i32 %and2, 16 ; [#uses=1] + %and.cond = and i1 %tobool, %tobool3 ; [#uses=1] + %storemerge = select i1 %and.cond, i32 0, i32 1 ; [#uses=1] + ret i32 %storemerge +} + +define i32 @main3e_like(i32 %argc, i32 %argc2, i32 %argc3, i8** nocapture %argv) + nounwind readnone ssp { +entry: + %and = and i32 %argc, %argc2 ; [#uses=1] + %tobool = icmp eq i32 %and, 0 ; [#uses=1] + %and2 = and i32 %argc, %argc3 ; [#uses=1] + %tobool3 = icmp eq i32 %and2, 0 ; [#uses=1] + %and.cond = and i1 %tobool, %tobool3 ; [#uses=1] + %storemerge = select i1 %and.cond, i32 0, i32 1 ; [#uses=1] + ret i32 %storemerge +} + +; (icmp ne (A & B), 0) | (icmp ne (A & D), 0) -> (icmp ne (A & (B|D)), 0) +define i32 @main3c(i32 %argc, i8** nocapture %argv) nounwind readnone ssp { +entry: + %and = and i32 %argc, 7 ; [#uses=1] + %tobool = icmp ne i32 %and, 0 ; [#uses=1] + %and2 = and i32 %argc, 48 ; [#uses=1] + %tobool3 = icmp ne i32 %and2, 0 ; [#uses=1] + %or.cond = or i1 %tobool, %tobool3 ; [#uses=1] + %storemerge = select i1 %or.cond, i32 0, i32 1 ; [#uses=1] + ret i32 %storemerge +} + +define i32 @main3d(i32 %argc, i8** nocapture %argv) nounwind readnone ssp { +entry: + %and = and i32 %argc, 7 ; [#uses=1] + %tobool = icmp ne i32 %and, 0 ; [#uses=1] + %and2 = and i32 %argc, 16 ; [#uses=1] + %tobool3 = icmp eq i32 %and2, 16 ; [#uses=1] + %or.cond = or i1 %tobool, %tobool3 ; [#uses=1] + %storemerge = select i1 %or.cond, i32 0, i32 1 ; [#uses=1] + ret i32 %storemerge +} + +define i32 @main3f_like(i32 %argc, i32 %argc2, i32 %argc3, i8** nocapture %argv) + nounwind readnone ssp { +entry: + %and = and i32 %argc, %argc2 ; [#uses=1] + %tobool = icmp ne i32 %and, 0 ; [#uses=1] + %and2 = and i32 %argc, %argc3 ; [#uses=1] + %tobool3 = icmp ne i32 %and2, 0 ; [#uses=1] + %or.cond = or i1 %tobool, %tobool3 ; [#uses=1] + %storemerge = select i1 %or.cond, i32 0, i32 1 ; [#uses=1] + ret i32 %storemerge +} + +; (icmp eq (A & B), B) & (icmp eq (A & D), D) -> (icmp eq (A & (B|D)), (B|D)) +define i32 @main4(i32 %argc, i8** nocapture %argv) nounwind readnone ssp { +entry: + %and = and i32 %argc, 7 ; [#uses=1] + %tobool = icmp eq i32 %and, 7 ; [#uses=1] + %and2 = and i32 %argc, 48 ; [#uses=1] + %tobool3 = icmp eq i32 %and2, 48 ; [#uses=1] + %and.cond = and i1 %tobool, %tobool3 ; [#uses=1] + %storemerge = select i1 %and.cond, i32 0, i32 1 ; [#uses=1] + ret i32 %storemerge +} + +define i32 @main4b(i32 %argc, i8** nocapture %argv) nounwind readnone ssp { +entry: + %and = and i32 %argc, 7 ; [#uses=1] + %tobool = icmp eq i32 %and, 7 ; [#uses=1] + %and2 = and i32 %argc, 16 ; [#uses=1] + %tobool3 = icmp ne i32 %and2, 0 ; [#uses=1] + %and.cond = and i1 %tobool, %tobool3 ; [#uses=1] + %storemerge = select i1 %and.cond, i32 0, i32 1 ; [#uses=1] + ret i32 %storemerge +} + +define i32 @main4e_like(i32 %argc, i32 %argc2, i32 %argc3, i8** nocapture %argv) + nounwind readnone ssp { +entry: + %and = and i32 %argc, %argc2 ; [#uses=1] + %tobool = icmp eq i32 %and, %argc2 ; [#uses=1] + %and2 = and i32 %argc, %argc3 ; [#uses=1] + %tobool3 = icmp eq i32 %and2, %argc3 ; [#uses=1] + %and.cond = and i1 %tobool, %tobool3 ; [#uses=1] + %storemerge = select i1 %and.cond, i32 0, i32 1 ; [#uses=1] + ret i32 %storemerge +} + +; (icmp ne (A & B), B) | (icmp ne (A & D), D) -> (icmp ne (A & (B|D)), (B|D)) +define i32 @main4c(i32 %argc, i8** nocapture %argv) nounwind readnone ssp { +entry: + %and = and i32 %argc, 7 ; [#uses=1] + %tobool = icmp ne i32 %and, 7 ; [#uses=1] + %and2 = and i32 %argc, 48 ; [#uses=1] + %tobool3 = icmp ne i32 %and2, 48 ; [#uses=1] + %or.cond = or i1 %tobool, %tobool3 ; [#uses=1] + %storemerge = select i1 %or.cond, i32 0, i32 1 ; [#uses=1] + ret i32 %storemerge +} + +define i32 @main4d(i32 %argc, i8** nocapture %argv) nounwind readnone ssp { +entry: + %and = and i32 %argc, 7 ; [#uses=1] + %tobool = icmp ne i32 %and, 7 ; [#uses=1] + %and2 = and i32 %argc, 16 ; [#uses=1] + %tobool3 = icmp eq i32 %and2, 0 ; [#uses=1] + %or.cond = or i1 %tobool, %tobool3 ; [#uses=1] + %storemerge = select i1 %or.cond, i32 0, i32 1 ; [#uses=1] + ret i32 %storemerge +} + +define i32 @main4f_like(i32 %argc, i32 %argc2, i32 %argc3, i8** nocapture %argv) + nounwind readnone ssp { +entry: + %and = and i32 %argc, %argc2 ; [#uses=1] + %tobool = icmp ne i32 %and, %argc2 ; [#uses=1] + %and2 = and i32 %argc, %argc3 ; [#uses=1] + %tobool3 = icmp ne i32 %and2, %argc3 ; [#uses=1] + %or.cond = or i1 %tobool, %tobool3 ; [#uses=1] + %storemerge = select i1 %or.cond, i32 0, i32 1 ; [#uses=1] + ret i32 %storemerge +} + +; (icmp eq (A & B), A) & (icmp eq (A & D), A) -> (icmp eq (A & (B&D)), A) +define i32 @main5_like(i32 %argc, i32 %argc2, i8** nocapture %argv) + nounwind readnone ssp { +entry: + %and = and i32 %argc, 7 ; [#uses=1] + %tobool = icmp eq i32 %and, 7 ; [#uses=1] + %and2 = and i32 %argc2, 7 ; [#uses=1] + %tobool3 = icmp eq i32 %and2, 7 ; [#uses=1] + %and.cond = and i1 %tobool, %tobool3 ; [#uses=1] + %storemerge = select i1 %and.cond, i32 0, i32 1 ; [#uses=1] + ret i32 %storemerge +} + +define i32 @main5e_like(i32 %argc, i32 %argc2, i32 %argc3, i8** nocapture %argv) + nounwind readnone ssp { +entry: + %and = and i32 %argc, %argc2 ; [#uses=1] + %tobool = icmp eq i32 %and, %argc ; [#uses=1] + %and2 = and i32 %argc, %argc3 ; [#uses=1] + %tobool3 = icmp eq i32 %and2, %argc ; [#uses=1] + %and.cond = and i1 %tobool, %tobool3 ; [#uses=1] + %storemerge = select i1 %and.cond, i32 0, i32 1 ; [#uses=1] + ret i32 %storemerge +} + +; (icmp ne (A & B), A) | (icmp ne (A & D), A) -> (icmp ne (A & (B&D)), A) +define i32 @main5c_like(i32 %argc, i32 %argc2, i8** nocapture %argv) + nounwind readnone ssp { +entry: + %and = and i32 %argc, 7 ; [#uses=1] + %tobool = icmp ne i32 %and, 7 ; [#uses=1] + %and2 = and i32 %argc2, 7 ; [#uses=1] + %tobool3 = icmp ne i32 %and2, 7 ; [#uses=1] + %or.cond = or i1 %tobool, %tobool3 ; [#uses=1] + %storemerge = select i1 %or.cond, i32 0, i32 1 ; [#uses=1] + ret i32 %storemerge +} + +define i32 @main5f_like(i32 %argc, i32 %argc2, i32 %argc3, i8** nocapture %argv) + nounwind readnone ssp { +entry: + %and = and i32 %argc, %argc2 ; [#uses=1] + %tobool = icmp ne i32 %and, %argc ; [#uses=1] + %and2 = and i32 %argc, %argc3 ; [#uses=1] + %tobool3 = icmp ne i32 %and2, %argc ; [#uses=1] + %or.cond = or i1 %tobool, %tobool3 ; [#uses=1] + %storemerge = select i1 %or.cond, i32 0, i32 1 ; [#uses=1] + ret i32 %storemerge +} + +; (icmp eq (A & B), C) & (icmp eq (A & D), E) -> (icmp eq (A & (B|D)), (C|E)) +; if B, C, D, E are constant, and it's possible +define i32 @main6(i32 %argc, i8** nocapture %argv) nounwind readnone ssp { +entry: + %and = and i32 %argc, 7 ; [#uses=1] + %tobool = icmp eq i32 %and, 3 ; [#uses=1] + %and2 = and i32 %argc, 48 ; [#uses=1] + %tobool3 = icmp eq i32 %and2, 16 ; [#uses=1] + %and.cond = and i1 %tobool, %tobool3 ; [#uses=1] + %storemerge = select i1 %and.cond, i32 0, i32 1 ; [#uses=1] + ret i32 %storemerge +} + +define i32 @main6b(i32 %argc, i8** nocapture %argv) nounwind readnone ssp { +entry: + %and = and i32 %argc, 7 ; [#uses=1] + %tobool = icmp eq i32 %and, 3 ; [#uses=1] + %and2 = and i32 %argc, 16 ; [#uses=1] + %tobool3 = icmp ne i32 %and2, 0 ; [#uses=1] + %and.cond = and i1 %tobool, %tobool3 ; [#uses=1] + %storemerge = select i1 %and.cond, i32 0, i32 1 ; [#uses=1] + ret i32 %storemerge +} + +; (icmp ne (A & B), C) | (icmp ne (A & D), E) -> (icmp ne (A & (B|D)), (C|E)) +; if B, C, D, E are constant, and it's possible +define i32 @main6c(i32 %argc, i8** nocapture %argv) nounwind readnone ssp { +entry: + %and = and i32 %argc, 7 ; [#uses=1] + %tobool = icmp ne i32 %and, 3 ; [#uses=1] + %and2 = and i32 %argc, 48 ; [#uses=1] + %tobool3 = icmp ne i32 %and2, 16 ; [#uses=1] + %or.cond = or i1 %tobool, %tobool3 ; [#uses=1] + %storemerge = select i1 %or.cond, i32 0, i32 1 ; [#uses=1] + ret i32 %storemerge +} + +define i32 @main6d(i32 %argc, i8** nocapture %argv) nounwind readnone ssp { +entry: + %and = and i32 %argc, 7 ; [#uses=1] + %tobool = icmp ne i32 %and, 3 ; [#uses=1] + %and2 = and i32 %argc, 16 ; [#uses=1] + %tobool3 = icmp eq i32 %and2, 0 ; [#uses=1] + %or.cond = or i1 %tobool, %tobool3 ; [#uses=1] + %storemerge = select i1 %or.cond, i32 0, i32 1 ; [#uses=1] + ret i32 %storemerge +} + +; test parameter permutations +; (B & A) == B & (D & A) == D +define i32 @main7a(i32 %argc, i32 %argc2, i32 %argc3, i8** nocapture %argv) + nounwind readnone ssp { +entry: + %and1 = and i32 %argc2, %argc ; [#uses=1] + %tobool = icmp eq i32 %and1, %argc2 ; [#uses=1] + %and2 = and i32 %argc3, %argc ; [#uses=1] + %tobool3 = icmp eq i32 %and2, %argc3 ; [#uses=1] + %and.cond = and i1 %tobool, %tobool3 ; [#uses=1] + %storemerge = select i1 %and.cond, i32 0, i32 1 ; [#uses=1] + ret i32 %storemerge +} + +; B == (A & B) & D == (A & D) +define i32 @main7b(i32 %argc, i32 %argc2, i32 %argc3, i8** nocapture %argv) + nounwind readnone ssp { +entry: + %and1 = and i32 %argc, %argc2 ; [#uses=1] + %tobool = icmp eq i32 %argc2, %and1 ; [#uses=1] + %and2 = and i32 %argc, %argc3 ; [#uses=1] + %tobool3 = icmp eq i32 %argc3, %and2 ; [#uses=1] + %and.cond = and i1 %tobool, %tobool3 ; [#uses=1] + %storemerge = select i1 %and.cond, i32 0, i32 1 ; [#uses=1] + ret i32 %storemerge +} + +; B == (B & A) & D == (D & A) +define i32 @main7c(i32 %argc, i32 %argc2, i32 %argc3, i8** nocapture %argv) + nounwind readnone ssp { +entry: + %and1 = and i32 %argc2, %argc ; [#uses=1] + %tobool = icmp eq i32 %argc2, %and1 ; [#uses=1] + %and2 = and i32 %argc3, %argc ; [#uses=1] + %tobool3 = icmp eq i32 %argc3, %and2 ; [#uses=1] + %and.cond = and i1 %tobool, %tobool3 ; [#uses=1] + %storemerge = select i1 %and.cond, i32 0, i32 1 ; [#uses=1] + ret i32 %storemerge +} + +; (A & (B & C)) == (B & C) & (A & (D & E)) == (D & E) +define i32 @main7d(i32 %argc, i32 %argc2, i32 %argc3, + i32 %argc4, i32 %argc5, i8** nocapture %argv) + nounwind readnone ssp { +entry: + %bc = and i32 %argc2, %argc4 ; [#uses=1] + %de = and i32 %argc3, %argc5 ; [#uses=1] + %and1 = and i32 %argc, %bc ; [#uses=1] + %tobool = icmp eq i32 %and1, %bc ; [#uses=1] + %and2 = and i32 %argc, %de ; [#uses=1] + %tobool3 = icmp eq i32 %and2, %de ; [#uses=1] + %and.cond = and i1 %tobool, %tobool3 ; [#uses=1] + %storemerge = select i1 %and.cond, i32 0, i32 1 ; [#uses=1] + ret i32 %storemerge +} + +; ((B & C) & A) == (B & C) & ((D & E) & A) == (D & E) +define i32 @main7e(i32 %argc, i32 %argc2, i32 %argc3, + i32 %argc4, i32 %argc5, i8** nocapture %argv) + nounwind readnone ssp { +entry: + %bc = and i32 %argc2, %argc4 ; [#uses=1] + %de = and i32 %argc3, %argc5 ; [#uses=1] + %and1 = and i32 %bc, %argc ; [#uses=1] + %tobool = icmp eq i32 %and1, %bc ; [#uses=1] + %and2 = and i32 %de, %argc ; [#uses=1] + %tobool3 = icmp eq i32 %and2, %de ; [#uses=1] + %and.cond = and i1 %tobool, %tobool3 ; [#uses=1] + %storemerge = select i1 %and.cond, i32 0, i32 1 ; [#uses=1] + ret i32 %storemerge +} + +; (B & C) == (A & (B & C)) & (D & E) == (A & (D & E)) +define i32 @main7f(i32 %argc, i32 %argc2, i32 %argc3, + i32 %argc4, i32 %argc5, i8** nocapture %argv) + nounwind readnone ssp { +entry: + %bc = and i32 %argc2, %argc4 ; [#uses=1] + %de = and i32 %argc3, %argc5 ; [#uses=1] + %and1 = and i32 %argc, %bc ; [#uses=1] + %tobool = icmp eq i32 %bc, %and1 ; [#uses=1] + %and2 = and i32 %argc, %de ; [#uses=1] + %tobool3 = icmp eq i32 %de, %and2 ; [#uses=1] + %and.cond = and i1 %tobool, %tobool3 ; [#uses=1] + %storemerge = select i1 %and.cond, i32 0, i32 1 ; [#uses=1] + ret i32 %storemerge +} + +; (B & C) == ((B & C) & A) & (D & E) == ((D & E) & A) +define i32 @main7g(i32 %argc, i32 %argc2, i32 %argc3, + i32 %argc4, i32 %argc5, i8** nocapture %argv) + nounwind readnone ssp { +entry: + %bc = and i32 %argc2, %argc4 ; [#uses=1] + %de = and i32 %argc3, %argc5 ; [#uses=1] + %and1 = and i32 %bc, %argc ; [#uses=1] + %tobool = icmp eq i32 %bc, %and1 ; [#uses=1] + %and2 = and i32 %de, %argc ; [#uses=1] + %tobool3 = icmp eq i32 %de, %and2 ; [#uses=1] + %and.cond = and i1 %tobool, %tobool3 ; [#uses=1] + %storemerge = select i1 %and.cond, i32 0, i32 1 ; [#uses=1] + ret i32 %storemerge +} From resistor at mac.com Wed Sep 8 17:17:50 2010 From: resistor at mac.com (Owen Anderson) Date: Wed, 08 Sep 2010 15:17:50 -0700 Subject: [llvm-commits] [PATCH] InstCombine: Generalized patch for (icmp eq (A&B), C) & (icmp eq (A&D), E), again In-Reply-To: <4C87E1DA.7090200@web.de> References: <4C87E1DA.7090200@web.de> Message-ID: <9D7224D3-853C-46D1-9977-C617A630DED8@mac.com> On Sep 8, 2010, at 12:19 PM, Dirk Steinke wrote: > Meanwhile I've setup a Linux box (VM) for LLVM, applied the patch, > ran 'make' and 'make check', and there were only expected failures. > So it wasn't my fault, and I'm all happy. :-) > Please review again and apply. This improved version passes testing for me, so I've applied it in r113423. Thanks! --Owen From sabre at nondot.org Wed Sep 8 17:22:10 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 08 Sep 2010 22:22:10 -0000 Subject: [llvm-commits] [llvm] r113426 - /llvm/trunk/lib/Target/X86/X86Instr64bit.td Message-ID: <20100908222210.478E72A6C12C@llvm.org> Author: lattner Date: Wed Sep 8 17:22:10 2010 New Revision: 113426 URL: http://llvm.org/viewvc/llvm-project?rev=113426&view=rev Log: fix wonky formatting. Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=113426&r1=113425&r2=113426&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original) +++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Wed Sep 8 17:22:10 2010 @@ -1631,7 +1631,7 @@ "lock\n\t" "or{q}\t{$zero, (%rsp)|(%rsp), $zero}", [(X86MemBarrierNoSSE GR64:$zero)]>, - Requires<[In64BitMode]>, LOCK; + Requires<[In64BitMode]>, LOCK; let Defs = [RAX, EFLAGS], Uses = [RAX] in { def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap), From sabre at nondot.org Wed Sep 8 17:27:05 2010 From: sabre at nondot.org (Chris Lattner) Date: Wed, 08 Sep 2010 22:27:05 -0000 Subject: [llvm-commits] [llvm] r113427 - in /llvm/trunk: lib/Target/X86/AsmParser/X86AsmParser.cpp test/MC/AsmParser/X86/x86_64-new-encoder.s Message-ID: <20100908222705.3B7422A6C12C@llvm.org> Author: lattner Date: Wed Sep 8 17:27:05 2010 New Revision: 113427 URL: http://llvm.org/viewvc/llvm-project?rev=113427&view=rev Log: fix rdar://8407548, I missed the commuted form of xchg/test without a suffix. Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=113427&r1=113426&r2=113427&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Wed Sep 8 17:27:05 2010 @@ -850,7 +850,8 @@ // The assembler accepts "xchgX , " and "xchgX , " as // synonyms. Our tables only have the ", " form, so if we see the // other operand order, swap them. - if (Name == "xchgb" || Name == "xchgw" || Name == "xchgl" || Name == "xchgq") + if (Name == "xchgb" || Name == "xchgw" || Name == "xchgl" || Name == "xchgq"|| + Name == "xchg") if (Operands.size() == 3 && static_cast(Operands[1])->isMem() && static_cast(Operands[2])->isReg()) { @@ -860,7 +861,8 @@ // The assembler accepts "testX , " and "testX , " as // synonyms. Our tables only have the ", " form, so if we see the // other operand order, swap them. - if (Name == "testb" || Name == "testw" || Name == "testl" || Name == "testq") + if (Name == "testb" || Name == "testw" || Name == "testl" || Name == "testq"|| + Name == "test") if (Operands.size() == 3 && static_cast(Operands[1])->isReg() && static_cast(Operands[2])->isMem()) { Modified: llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s?rev=113427&r1=113426&r2=113427&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_64-new-encoder.s Wed Sep 8 17:27:05 2010 @@ -174,6 +174,12 @@ xchgl %ecx, 368(%rax) // CHECK: xchgl %ecx, 368(%rax) +// rdar://8407548 +xchg 0xdeadbeef(%rbx,%rcx,8),%bl +// CHECK: xchgb %bl, 3735928559(%rbx,%rcx,8) + + + // PR7254 lock incl 1(%rsp) // CHECK: lock From echristo at apple.com Wed Sep 8 17:35:23 2010 From: echristo at apple.com (Eric Christopher) Date: Wed, 8 Sep 2010 15:35:23 -0700 Subject: [llvm-commits] [llvm] r113426 - /llvm/trunk/lib/Target/X86/X86Instr64bit.td In-Reply-To: <20100908222210.478E72A6C12C@llvm.org> References: <20100908222210.478E72A6C12C@llvm.org> Message-ID: <5ECA6765-5637-4F33-A017-05F3064EAA9F@apple.com> On Sep 8, 2010, at 3:22 PM, Chris Lattner wrote: > Author: lattner > Date: Wed Sep 8 17:22:10 2010 > New Revision: 113426 > > URL: http://llvm.org/viewvc/llvm-project?rev=113426&view=rev > Log: > fix wonky formatting. > > Modified: > llvm/trunk/lib/Target/X86/X86Instr64bit.td > > Modified: llvm/trunk/lib/Target/X86/X86Instr64bit.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr64bit.td?rev=113426&r1=113425&r2=113426&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/X86Instr64bit.td (original) > +++ llvm/trunk/lib/Target/X86/X86Instr64bit.td Wed Sep 8 17:22:10 2010 > @@ -1631,7 +1631,7 @@ > "lock\n\t" > "or{q}\t{$zero, (%rsp)|(%rsp), $zero}", > [(X86MemBarrierNoSSE GR64:$zero)]>, > - Requires<[In64BitMode]>, LOCK; > + Requires<[In64BitMode]>, LOCK; Weird, my editor must have lost its mind. Thanks! -eric From clattner at apple.com Wed Sep 8 17:45:49 2010 From: clattner at apple.com (Chris Lattner) Date: Wed, 8 Sep 2010 15:45:49 -0700 Subject: [llvm-commits] [llvm] r113306 - /llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp In-Reply-To: <944B1EDF-344F-4F64-B683-BCF41291634A@mac.com> References: <20100907231530.DF7422A6C12C@llvm.org> <944B1EDF-344F-4F64-B683-BCF41291634A@mac.com> Message-ID: <6B138CBE-6C94-4570-9116-FD0EF736E7B2@apple.com> On Sep 8, 2010, at 1:48 PM, Owen Anderson wrote: > > On Sep 7, 2010, at 4:15 PM, Owen Anderson wrote: > >> Author: resistor >> Date: Tue Sep 7 18:15:30 2010 >> New Revision: 113306 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=113306&view=rev >> Log: >> Add a separate unrolling threshold when the current function is being optimized for size. >> The threshold value of 50 is arbitrary, and I chose it simply by analogy to the inlining thresholds, where >> the baseline unrolling threshold is slightly smaller than the baseline inlining threshold. This could >> undoubtedly use some tuning. > > Actually, after researching this, it looks like 50 is a pretty decent threshold choice, as evidenced by the attached data from SPEC2000/2006: Sounds great, thanks Owen! -Chris From evan.cheng at apple.com Wed Sep 8 17:57:09 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 08 Sep 2010 22:57:09 -0000 Subject: [llvm-commits] [llvm] r113435 - in /llvm/trunk/lib/Target/ARM: ARMInstrInfo.td ARMInstrThumb2.td ARMSchedule.td ARMScheduleA8.td ARMScheduleA9.td Message-ID: <20100908225709.336272A6C12C@llvm.org> Author: evancheng Date: Wed Sep 8 17:57:08 2010 New Revision: 113435 URL: http://llvm.org/viewvc/llvm-project?rev=113435&view=rev Log: Fix LDM_RET schedule itinery. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/lib/Target/ARM/ARMSchedule.td llvm/trunk/lib/Target/ARM/ARMScheduleA8.td llvm/trunk/lib/Target/ARM/ARMScheduleA9.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=113435&r1=113434&r2=113435&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Sep 8 17:57:08 2010 @@ -940,7 +940,7 @@ hasExtraDefRegAllocReq = 1 in def LDM_RET : AXI4ld<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, reglist:$dsts, variable_ops), - IndexModeUpd, LdStMulFrm, IIC_Br, + IndexModeUpd, LdStMulFrm, IIC_iLoadmBr, "ldm${addr:submode}${p}\t$addr!, $dsts", "$addr.addr = $wb", []>; Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=113435&r1=113434&r2=113435&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Sep 8 17:57:08 2010 @@ -2454,7 +2454,8 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, hasExtraDefRegAllocReq = 1 in def t2LDM_RET : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, - reglist:$dsts, variable_ops), IIC_Br, + reglist:$dsts, variable_ops), + IIC_iLoadmBr, "ldm${addr:submode}${p}${addr:wide}\t$addr!, $dsts", "$addr.addr = $wb", []> { let Inst{31-27} = 0b11101; Modified: llvm/trunk/lib/Target/ARM/ARMSchedule.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSchedule.td?rev=113435&r1=113434&r2=113435&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSchedule.td (original) +++ llvm/trunk/lib/Target/ARM/ARMSchedule.td Wed Sep 8 17:57:08 2010 @@ -43,6 +43,7 @@ def IIC_iLoadru : InstrItinClass; def IIC_iLoadsiu : InstrItinClass; def IIC_iLoadm : InstrItinClass; +def IIC_iLoadmBr : InstrItinClass; def IIC_iStorei : InstrItinClass; def IIC_iStorer : InstrItinClass; def IIC_iStoresi : InstrItinClass; Modified: llvm/trunk/lib/Target/ARM/ARMScheduleA8.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA8.td?rev=113435&r1=113434&r2=113435&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMScheduleA8.td (original) +++ llvm/trunk/lib/Target/ARM/ARMScheduleA8.td Wed Sep 8 17:57:08 2010 @@ -122,6 +122,15 @@ InstrStage<1, [A8_Pipe0, A8_Pipe1]>, InstrStage<1, [A8_LdSt0]>]>, + // + // Load multiple plus branch + InstrItinData, + InstrStage<2, [A8_Pipe0], 0>, + InstrStage<2, [A8_Pipe1]>, + InstrStage<1, [A8_Pipe0, A8_Pipe1]>, + InstrStage<1, [A8_LdSt0]>, + InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>, + // Integer store pipeline // // use A8_Issue to enforce the 1 load/store per cycle limit Modified: llvm/trunk/lib/Target/ARM/ARMScheduleA9.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA9.td?rev=113435&r1=113434&r2=113435&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMScheduleA9.td (original) +++ llvm/trunk/lib/Target/ARM/ARMScheduleA9.td Wed Sep 8 17:57:08 2010 @@ -107,6 +107,12 @@ InstrItinData, InstrStage<1, [A9_LSPipe]>]>, + // + // Load multiple plus branch + InstrItinData, + InstrStage<1, [A9_LSPipe]>, + InstrStage<1, [A9_Pipe0, A9_Pipe1]>]>, + // Integer store pipeline /// // Immediate offset From echristo at apple.com Wed Sep 8 17:58:35 2010 From: echristo at apple.com (Eric Christopher) Date: Wed, 08 Sep 2010 22:58:35 -0000 Subject: [llvm-commits] [llvm] r113436 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20100908225835.7F7892A6C12C@llvm.org> Author: echristo Date: Wed Sep 8 17:58:35 2010 New Revision: 113436 URL: http://llvm.org/viewvc/llvm-project?rev=113436&view=rev Log: Delete dead code. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=113436&r1=113435&r2=113436&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Wed Sep 8 17:58:35 2010 @@ -123,7 +123,6 @@ bool ARMLoadAlloca(const Instruction *I, EVT VT); bool ARMStoreAlloca(const Instruction *I, unsigned SrcReg, EVT VT); bool ARMComputeRegOffset(const Value *Obj, unsigned &Reg, int &Offset); - bool ARMMaterializeConstant(const ConstantInt *Val, unsigned &Reg); bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR); const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB); From resistor at mac.com Wed Sep 8 18:10:07 2010 From: resistor at mac.com (Owen Anderson) Date: Wed, 08 Sep 2010 23:10:07 -0000 Subject: [llvm-commits] [llvm] r113439 - in /llvm/trunk: lib/Transforms/Scalar/LoopUnrollPass.cpp test/Transforms/LoopUnroll/call.ll Message-ID: <20100908231007.6F2552A6C12C@llvm.org> Author: resistor Date: Wed Sep 8 18:10:07 2010 New Revision: 113439 URL: http://llvm.org/viewvc/llvm-project?rev=113439&view=rev Log: Relax the "don't unroll loops containing calls" rule. Instead, when a loop contains a call, lower the unrolling threshold to the optimize-for-size threshold. Basically, for loops containing calls, unrolling can still be profitable as long as the loop is REALLY small. Added: llvm/trunk/test/Transforms/LoopUnroll/call.ll Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp?rev=113439&r1=113438&r2=113439&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp Wed Sep 8 18:10:07 2010 @@ -132,8 +132,10 @@ unsigned LoopSize = ApproximateLoopSize(L, NumCalls); DEBUG(dbgs() << " Loop Size = " << LoopSize << "\n"); if (NumCalls != 0) { - DEBUG(dbgs() << " Not unrolling loop with function calls.\n"); - return false; + // Even for a loop that contains calls, it can still be profitable to + // unroll if the loop is really, REALLY small. + DEBUG(dbgs() <<" Using lower threshold for loop with function calls.\n"); + CurrentThreshold = OptSizeUnrollThreshold; } uint64_t Size = (uint64_t)LoopSize*Count; if (TripCount != 1 && Size > CurrentThreshold) { Added: llvm/trunk/test/Transforms/LoopUnroll/call.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopUnroll/call.ll?rev=113439&view=auto ============================================================================== --- llvm/trunk/test/Transforms/LoopUnroll/call.ll (added) +++ llvm/trunk/test/Transforms/LoopUnroll/call.ll Wed Sep 8 18:10:07 2010 @@ -0,0 +1,51 @@ +; RUN: opt < %s -S -loop-unroll | FileCheck %s + + at id = internal global i32 0 + at val = internal global [4 x i32] zeroinitializer, align 16 + +; CHECK: @test +define i32 @test(i32 %k) nounwind ssp { +; CHECK-NOT: call i32 @test(i32 %t.06) +; CHECK: call i32 @test(i32 0) +; CHECK-NOT: call i32 @test(i32 %t.06) +; CHECK: call i32 @test(i32 1) +; CHECK-NOT: call i32 @test(i32 %t.06) +; CHECK: call i32 @test(i32 2) +; CHECK-NOT: call i32 @test(i32 %t.06) +; CHECK: call i32 @test(i32 3) +; CHECK-NOT: call i32 @test(i32 %t.06) + +bb.nph: + %0 = load i32* @id, align 4 + %1 = add nsw i32 %0, 1 + store i32 %1, i32* @id, align 4 + %2 = sext i32 %k to i64 + %3 = getelementptr inbounds [4 x i32]* @val, i64 0, i64 %2 + store i32 %1, i32* %3, align 4 + br label %bb + +bb: ; preds = %bb2, %bb.nph + %indvar = phi i64 [ 0, %bb.nph ], [ %indvar.next, %bb2 ] + %scevgep = getelementptr [4 x i32]* @val, i64 0, i64 %indvar + %4 = load i32* %scevgep, align 4 + %5 = icmp eq i32 %4, 0 + br i1 %5, label %bb1, label %bb2 + +bb1: ; preds = %bb + %t.06 = trunc i64 %indvar to i32 + %6 = tail call i32 @test(i32 %t.06) nounwind + br label %bb2 + +bb2: ; preds = %bb1, %bb + %indvar.next = add i64 %indvar, 1 + %exitcond = icmp eq i64 %indvar.next, 4 + br i1 %exitcond, label %bb4, label %bb + +bb4: ; preds = %bb2 + %.pre = load i32* @id, align 4 + %7 = add nsw i32 %.pre, -1 + store i32 %7, i32* @id, align 4 + store i32 0, i32* %3, align 4 + ret i32 undef +; CHECK: } +} From echristo at apple.com Wed Sep 8 18:13:46 2010 From: echristo at apple.com (Eric Christopher) Date: Wed, 08 Sep 2010 23:13:46 -0000 Subject: [llvm-commits] [llvm] r113440 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20100908231346.1A2522A6C12C@llvm.org> Author: echristo Date: Wed Sep 8 18:13:45 2010 New Revision: 113440 URL: http://llvm.org/viewvc/llvm-project?rev=113440&view=rev Log: Very basic compare support. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=113440&r1=113439&r2=113440&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Wed Sep 8 18:13:45 2010 @@ -113,6 +113,7 @@ virtual bool ARMSelectLoad(const Instruction *I); virtual bool ARMSelectStore(const Instruction *I); virtual bool ARMSelectBranch(const Instruction *I); + virtual bool ARMSelectCmp(const Instruction *I); // Utility routines. private: @@ -650,6 +651,50 @@ return true; } +bool ARMFastISel::ARMSelectCmp(const Instruction *I) { + const CmpInst *CI = cast(I); + + EVT VT; + const Type *Ty = CI->getOperand(0)->getType(); + if (!isTypeLegal(Ty, VT)) + return false; + + bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy()); + if (isFloat && !Subtarget->hasVFP2()) + return false; + + unsigned CmpOpc; + switch (VT.getSimpleVT().SimpleTy) { + default: return false; + // TODO: Verify compares. + case MVT::f32: + CmpOpc = ARM::VCMPES; + break; + case MVT::f64: + CmpOpc = ARM::VCMPED; + break; + case MVT::i32: + CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr; + break; + } + + unsigned Arg1 = getRegForValue(CI->getOperand(0)); + if (Arg1 == 0) return false; + + unsigned Arg2 = getRegForValue(CI->getOperand(1)); + if (Arg2 == 0) return false; + + AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc)) + .addReg(Arg1).addReg(Arg2)); + + // For floating point we need to move the result to a register we can + // actually do something with. + if (isFloat) + AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, + TII.get(ARM::FMSTAT))); + return true; +} + // TODO: SoftFP support. bool ARMFastISel::TargetSelectInstruction(const Instruction *I) { // No Thumb-1 for now. @@ -662,6 +707,9 @@ return ARMSelectStore(I); case Instruction::Br: return ARMSelectBranch(I); + case Instruction::ICmp: + case Instruction::FCmp: + return ARMSelectCmp(I); default: break; } return false; From clattner at apple.com Wed Sep 8 18:19:34 2010 From: clattner at apple.com (Chris Lattner) Date: Wed, 8 Sep 2010 16:19:34 -0700 Subject: [llvm-commits] [llvm] r113439 - in /llvm/trunk: lib/Transforms/Scalar/LoopUnrollPass.cpp test/Transforms/LoopUnroll/call.ll In-Reply-To: <20100908231007.6F2552A6C12C@llvm.org> References: <20100908231007.6F2552A6C12C@llvm.org> Message-ID: On Sep 8, 2010, at 4:10 PM, Owen Anderson wrote: > Author: resistor > Date: Wed Sep 8 18:10:07 2010 > New Revision: 113439 > > URL: http://llvm.org/viewvc/llvm-project?rev=113439&view=rev > Log: > Relax the "don't unroll loops containing calls" rule. Instead, when a loop contains a call, lower the > unrolling threshold to the optimize-for-size threshold. Basically, for loops containing calls, unrolling > can still be profitable as long as the loop is REALLY small. This doesn't seem like the right approach: loop unroll should use the same code size estimator as the inliner. It just treats calls as having a large code size. As long as the estimator says that the loop body (minus any expected shrinkage) is under the threshold, whether it has a call or not shouldn't matter. -Chris From bob.wilson at apple.com Wed Sep 8 18:39:54 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Wed, 08 Sep 2010 23:39:54 -0000 Subject: [llvm-commits] [llvm] r113442 - /llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Message-ID: <20100908233954.434492A6C12C@llvm.org> Author: bwilson Date: Wed Sep 8 18:39:54 2010 New Revision: 113442 URL: http://llvm.org/viewvc/llvm-project?rev=113442&view=rev Log: Clean up a comment. Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=113442&r1=113441&r2=113442&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Wed Sep 8 18:39:54 2010 @@ -7,10 +7,10 @@ // //===----------------------------------------------------------------------===// // -// This file contains a pass that expand pseudo instructions into target +// This file contains a pass that expands pseudo instructions into target // instructions to allow proper scheduling, if-conversion, and other late // optimizations. This pass should be run after register allocation but before -// post- regalloc scheduling pass. +// the post-regalloc scheduling pass. // //===----------------------------------------------------------------------===// From stoklund at 2pi.dk Wed Sep 8 18:54:00 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 08 Sep 2010 23:54:00 -0000 Subject: [llvm-commits] [llvm] r113445 - /llvm/trunk/include/llvm/CodeGen/LiveInterval.h Message-ID: <20100908235401.01D422A6C12C@llvm.org> Author: stoklund Date: Wed Sep 8 18:54:00 2010 New Revision: 113445 URL: http://llvm.org/viewvc/llvm-project?rev=113445&view=rev Log: Rearrange for better alignment and less padding Modified: llvm/trunk/include/llvm/CodeGen/LiveInterval.h Modified: llvm/trunk/include/llvm/CodeGen/LiveInterval.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveInterval.h?rev=113445&r1=113444&r2=113445&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/LiveInterval.h (original) +++ llvm/trunk/include/llvm/CodeGen/LiveInterval.h Wed Sep 8 18:54:00 2010 @@ -60,8 +60,8 @@ IS_DEF_ACCURATE = 1 << 4 }; - unsigned char flags; MachineInstr *copy; + unsigned char flags; public: typedef BumpPtrAllocator Allocator; @@ -76,11 +76,12 @@ /// d is presumed to point to the actual defining instr. If it doesn't /// setIsDefAccurate(false) should be called after construction. VNInfo(unsigned i, SlotIndex d, MachineInstr *c) - : flags(IS_DEF_ACCURATE), id(i), def(d) { copy = c; } + : copy(c), flags(IS_DEF_ACCURATE), id(i), def(d) + { } /// VNInfo construtor, copies values from orig, except for the value number. VNInfo(unsigned i, const VNInfo &orig) - : flags(orig.flags), copy(orig.copy), id(i), def(orig.def) + : copy(orig.copy), flags(orig.flags), id(i), def(orig.def) { } /// Copy from the parameter into this VNInfo. From bob.wilson at apple.com Wed Sep 8 19:15:32 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Thu, 09 Sep 2010 00:15:32 -0000 Subject: [llvm-commits] [llvm] r113452 - /llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Message-ID: <20100909001532.DEA912A6C12C@llvm.org> Author: bwilson Date: Wed Sep 8 19:15:32 2010 New Revision: 113452 URL: http://llvm.org/viewvc/llvm-project?rev=113452&view=rev Log: Simplify copying over operands from pseudo NEON load/store instructions. For VLD3/VLD4 with double-spaced registers, add the implicit use of the super register for both the instruction loading the even registers and the instruction loading the odd registers. Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=113452&r1=113451&r2=113452&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Wed Sep 8 19:15:32 2010 @@ -67,10 +67,9 @@ const MachineOperand &MO = OldMI.getOperand(i); assert(MO.isReg() && MO.getReg()); if (MO.isUse()) - UseMI.addReg(MO.getReg(), getKillRegState(MO.isKill())); + UseMI.addOperand(MO); else - DefMI.addReg(MO.getReg(), - getDefRegState(true) | getDeadRegState(MO.isDead())); + DefMI.addOperand(MO); } } @@ -112,26 +111,21 @@ if (NumRegs > 3) MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); - if (hasWriteBack) { - bool WBIsDead = MI.getOperand(OpIdx).isDead(); - unsigned WBReg = MI.getOperand(OpIdx++).getReg(); - MIB.addReg(WBReg, RegState::Define | getDeadRegState(WBIsDead)); - } + if (hasWriteBack) + MIB.addOperand(MI.getOperand(OpIdx++)); + // Copy the addrmode6 operands. - bool AddrIsKill = MI.getOperand(OpIdx).isKill(); - MIB.addReg(MI.getOperand(OpIdx++).getReg(), getKillRegState(AddrIsKill)); - MIB.addImm(MI.getOperand(OpIdx++).getImm()); - if (hasWriteBack) { - // Copy the am6offset operand. - bool OffsetIsKill = MI.getOperand(OpIdx).isKill(); - MIB.addReg(MI.getOperand(OpIdx++).getReg(), getKillRegState(OffsetIsKill)); - } + MIB.addOperand(MI.getOperand(OpIdx++)); + MIB.addOperand(MI.getOperand(OpIdx++)); + // Copy the am6offset operand. + if (hasWriteBack) + MIB.addOperand(MI.getOperand(OpIdx++)); MIB = AddDefaultPred(MIB); TransferImpOps(MI, MIB, MIB); // For an instruction writing the odd subregs, add an implicit use of the // super-register because the even subregs were loaded separately. - if (RegSpc == OddDblSpc) + if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc) MIB.addReg(DstReg, RegState::Implicit); // Add an implicit def for the super-register. MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); @@ -148,20 +142,15 @@ MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)); unsigned OpIdx = 0; - if (hasWriteBack) { - bool DstIsDead = MI.getOperand(OpIdx).isDead(); - unsigned DstReg = MI.getOperand(OpIdx++).getReg(); - MIB.addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)); - } + if (hasWriteBack) + MIB.addOperand(MI.getOperand(OpIdx++)); + // Copy the addrmode6 operands. - bool AddrIsKill = MI.getOperand(OpIdx).isKill(); - MIB.addReg(MI.getOperand(OpIdx++).getReg(), getKillRegState(AddrIsKill)); - MIB.addImm(MI.getOperand(OpIdx++).getImm()); - if (hasWriteBack) { - // Copy the am6offset operand. - bool OffsetIsKill = MI.getOperand(OpIdx).isKill(); - MIB.addReg(MI.getOperand(OpIdx++).getReg(), getKillRegState(OffsetIsKill)); - } + MIB.addOperand(MI.getOperand(OpIdx++)); + MIB.addOperand(MI.getOperand(OpIdx++)); + // Copy the am6offset operand. + if (hasWriteBack) + MIB.addOperand(MI.getOperand(OpIdx++)); bool SrcIsKill = MI.getOperand(OpIdx).isKill(); unsigned SrcReg = MI.getOperand(OpIdx).getReg(); From echristo at apple.com Wed Sep 8 19:19:41 2010 From: echristo at apple.com (Eric Christopher) Date: Thu, 09 Sep 2010 00:19:41 -0000 Subject: [llvm-commits] [llvm] r113453 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20100909001941.509CA2A6C12C@llvm.org> Author: echristo Date: Wed Sep 8 19:19:41 2010 New Revision: 113453 URL: http://llvm.org/viewvc/llvm-project?rev=113453&view=rev Log: Rewrite TargetMaterializeConstant splitting it out into two functions for integer and fp constants. Implement todo to use vfp3 instructions to materialize easy constants if we can. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=113453&r1=113452&r2=113453&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Wed Sep 8 19:19:41 2010 @@ -124,6 +124,8 @@ bool ARMLoadAlloca(const Instruction *I, EVT VT); bool ARMStoreAlloca(const Instruction *I, unsigned SrcReg, EVT VT); bool ARMComputeRegOffset(const Value *Obj, unsigned &Reg, int &Offset); + unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT); + unsigned ARMMaterializeInt(const Constant *C); bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR); const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB); @@ -323,18 +325,40 @@ return ResultReg; } -unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) { - EVT VT = TLI.getValueType(C->getType(), true); - - // Only handle simple types. - if (!VT.isSimple()) return 0; - - // Handle double width floating point? - if (VT.getSimpleVT().SimpleTy == MVT::f64) return 0; +// For double width floating point we need to materialize two constants +// (the high and the low) into integer registers then use a move to get +// the combined constant into an FP reg. +unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) { + const APFloat Val = CFP->getValueAPF(); + bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64; + + // This checks to see if we can use VFP3 instructions to materialize + // a constant, otherwise we have to go through the constant pool. + if (TLI.isFPImmLegal(Val, VT)) { + unsigned Opc = is64bit ? ARM::FCONSTD : ARM::FCONSTS; + unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); + AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), + DestReg) + .addFPImm(CFP)); + return DestReg; + } + + // No 64-bit at the moment. + if (is64bit) return 0; - // TODO: Theoretically we could materialize fp constants directly with - // instructions from VFP3. + // Load this from the constant pool. + unsigned DestReg = ARMMaterializeInt(cast(CFP)); + + // If we have a floating point constant we expect it in a floating point + // register. + unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); + AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, + TII.get(ARM::VMOVRS), MoveReg) + .addReg(DestReg)); + return MoveReg; +} +unsigned ARMFastISel::ARMMaterializeInt(const Constant *C) { // MachineConstantPool wants an explicit alignment. unsigned Align = TD.getPrefTypeAlignment(C->getType()); if (Align == 0) { @@ -353,21 +377,21 @@ TII.get(ARM::LDRcp)) .addReg(DestReg).addConstantPoolIndex(Idx) .addReg(0).addImm(0)); - - // If we have a floating point constant we expect it in a floating point - // register. - // TODO: Make this use ARMBaseInstrInfo::copyPhysReg. - if (C->getType()->isFloatTy()) { - unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); - AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, - TII.get(ARM::VMOVRS), MoveReg) - .addReg(DestReg)); - return MoveReg; - } return DestReg; } +unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) { + EVT VT = TLI.getValueType(C->getType(), true); + + // Only handle simple types. + if (!VT.isSimple()) return 0; + + if (const ConstantFP *CFP = dyn_cast(C)) + return ARMMaterializeFP(CFP, VT); + return ARMMaterializeInt(C); +} + bool ARMFastISel::isTypeLegal(const Type *Ty, EVT &VT) { VT = TLI.getValueType(Ty, true); From echristo at apple.com Wed Sep 8 19:26:49 2010 From: echristo at apple.com (Eric Christopher) Date: Thu, 09 Sep 2010 00:26:49 -0000 Subject: [llvm-commits] [llvm] r113455 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20100909002649.1BBC92A6C12C@llvm.org> Author: echristo Date: Wed Sep 8 19:26:48 2010 New Revision: 113455 URL: http://llvm.org/viewvc/llvm-project?rev=113455&view=rev Log: Handle float->double extension. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=113455&r1=113454&r2=113455&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Wed Sep 8 19:26:48 2010 @@ -114,6 +114,7 @@ virtual bool ARMSelectStore(const Instruction *I); virtual bool ARMSelectBranch(const Instruction *I); virtual bool ARMSelectCmp(const Instruction *I); + virtual bool ARMSelectFPExt(const Instruction *I); // Utility routines. private: @@ -719,6 +720,26 @@ return true; } +bool ARMFastISel::ARMSelectFPExt(const Instruction *I) { + // Make sure we have VFP and that we're extending float to double. + if (!Subtarget->hasVFP2()) return false; + + Value *V = I->getOperand(0); + if (!I->getType()->isDoubleTy() || + !V->getType()->isFloatTy()) return false; + + unsigned Op = getRegForValue(V); + if (Op == 0) return false; + + unsigned Result = createResultReg(ARM::DPRRegisterClass); + + AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, + TII.get(ARM::VCVTDS), Result) + .addReg(Op)); + UpdateValueMap(I, Result); + return true; +} + // TODO: SoftFP support. bool ARMFastISel::TargetSelectInstruction(const Instruction *I) { // No Thumb-1 for now. @@ -734,6 +755,8 @@ case Instruction::ICmp: case Instruction::FCmp: return ARMSelectCmp(I); + case Instruction::FPExt: + return ARMSelectFPExt(I); default: break; } return false; From bigcheesegs at gmail.com Wed Sep 8 19:39:07 2010 From: bigcheesegs at gmail.com (Michael Spencer) Date: Wed, 8 Sep 2010 20:39:07 -0400 Subject: [llvm-commits] [PATCH][CMake] Removing LLVMLibDeps.cmake and exporting libraries for CMake clients. Message-ID: While implementing the object file library I ran into some weird linking issues. It turned out that you have to manually specify extra library dependencies in LLVMLibDeps.cmake, along with what you already specify in the CMakeLists.txt file for the component. The attached patches remove this requirement, and add real CMake package export capabilities. A CMake user wishing to use LLVM can now use something similar to this: cmake_minimum_required(VERSION 2.8) find_package(LLVM REQUIRED) add_definitions(${LLVM_CXXFLAGS}) add_executable(llvm-external-test llvm-external-test.cpp) target_link_libraries(llvm-external-test ${LLVM_SYSTEM_LIBS} ${LLVM_JIT_LIBS} ${LLVM_NATIVECODEGEN_LIBS}) llvm+clang compile with these changes on both Linux and MSVS. Currently both patches must be applied at the same time. I can refactor them into a 3 step process if needed. Does this break anything for anyone? - Michael Spencer -------------- next part -------------- A non-text attachment was scrubbed... Name: remove-LLVMLibDeps.cmake.patch Type: application/octet-stream Size: 46934 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100908/5e129cfc/attachment.obj -------------- next part -------------- A non-text attachment was scrubbed... Name: cmake-update-to-match.patch Type: application/octet-stream Size: 9825 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100908/5e129cfc/attachment-0001.obj From bob.wilson at apple.com Wed Sep 8 19:40:17 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Wed, 8 Sep 2010 17:40:17 -0700 Subject: [llvm-commits] [llvm] r112983 - in /llvm/trunk/lib/Target/ARM: ARMExpandPseudoInsts.cpp ARMISelDAGToDAG.cpp ARMInstrNEON.td NEONPreAllocPass.cpp In-Reply-To: References: <20100903181602.C949B2A6C12C@llvm.org> Message-ID: On Sep 3, 2010, at 3:38 PM, Jakob Stoklund Olesen wrote: > > On Sep 3, 2010, at 11:16 AM, Bob Wilson wrote: > >> Author: bwilson >> Date: Fri Sep 3 13:16:02 2010 >> New Revision: 112983 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=112983&view=rev >> Log: >> Finish converting the rest of the NEON VLD instructions to use pseudo- >> instructions prior to regalloc. Since it's getting a little close to >> the 2.8 branch deadline, I'll have to leave the rest of the instructions >> handled by the NEONPreAllocPass for now, but I didn't want to leave half >> of the VLD instructions converted and the other half not. >> >> Modified: >> llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp >> llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp >> llvm/trunk/lib/Target/ARM/ARMInstrNEON.td >> llvm/trunk/lib/Target/ARM/NEONPreAllocPass.cpp >> >> Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=112983&r1=112982&r2=112983&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original) >> +++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Fri Sep 3 13:16:02 2010 >> @@ -105,16 +105,17 @@ >> D2 = TRI->getSubReg(DstReg, ARM::dsub_5); >> D3 = TRI->getSubReg(DstReg, ARM::dsub_7); >> } >> - MIB.addReg(D0).addReg(D1); >> + MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)) >> + .addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); >> if (NumRegs > 2) >> - MIB.addReg(D2); >> + MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); >> if (NumRegs > 3) >> - MIB.addReg(D3); >> + MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); > > Thanks! > >> - MIB.addReg(WBReg, getDefRegState(true) | getDeadRegState(WBIsDead)); >> + MIB.addReg(WBReg, RegState::Define | getDeadRegState(WBIsDead)); > > Right. I think using the enums directly is fine. The functions were added as helpers when your bit is variable like here. > > Not in this patch, but related: > > // Copy the addrmode6 operands. > bool AddrIsKill = MI.getOperand(OpIdx).isKill(); > MIB.addReg(MI.getOperand(OpIdx++).getReg(), getKillRegState(AddrIsKill)); > MIB.addImm(MI.getOperand(OpIdx++).getImm()); > > Is easier like this: > > MIB.addOperand(MI.getOperand(OpIdx++)); > MIB.addOperand(MI.getOperand(OpIdx++)); OK, thanks for suggesting that. I've changed all of those. > > >> } >> // Copy the addrmode6 operands. >> bool AddrIsKill = MI.getOperand(OpIdx).isKill(); >> @@ -128,9 +129,12 @@ >> >> MIB = AddDefaultPred(MIB); >> TransferImpOps(MI, MIB, MIB); >> - // Add an implicit def for the super-reg. >> - MIB.addReg(DstReg, (getDefRegState(true) | getDeadRegState(DstIsDead) | >> - getImplRegState(true))); >> + // For an instruction writing the odd subregs, add an implicit use of the >> + // super-register because the even subregs were loaded separately. >> + if (RegSpc == OddDblSpc) >> + MIB.addReg(DstReg, RegState::Implicit); > > This part is weird. Is OddDblSpc guaranteed to have DstReg live in? In that case, would there already be a DstReg operand on MI that gets transferred by TransferImpOps()? > > The end result should be: > > %D0, %D2, ... = VLD ..., %QQQQ0 > %D1, %D3, ... = VLD ..., %QQQQ0, %QQQQ0 > The double-spaced VLD3/VLD4 instructions will have an explicit source operand for the super register. (It is tied to the destination operand, so it will always be the same register at this point.) The operand is basically being transferred from an explicit operand on the pseudo instruction to an implicit operand on the real instruction. Because of that, we shouldn't have to worry about conflicts with arbitrary implicit operands. As we discussed Friday, I also added the imp-use for both of the "even" and "odd" VLDs. > >> + // Add an implicit def for the super-register. >> + MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); > > This is correct, but since TransferImpOps() has added arbitrary imp-ops to your new instruction, it would be better to call addRegisterDefined() / addRegisterDead(). That handles existing operands, and it will even flip the bit on subregs if you pass in a TRI. > > You could argue that we are missing a MachineInstr::addRegisterUsed() function to complete the quartet. > > /jakob > > > > > From bob.wilson at apple.com Wed Sep 8 19:38:33 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Thu, 09 Sep 2010 00:38:33 -0000 Subject: [llvm-commits] [llvm] r113456 - /llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Message-ID: <20100909003833.0C2BB2A6C12C@llvm.org> Author: bwilson Date: Wed Sep 8 19:38:32 2010 New Revision: 113456 URL: http://llvm.org/viewvc/llvm-project?rev=113456&view=rev Log: For double-spaced VLD3/VLD4 instructions, copy the explicit super-register use operand from the pseudo instruction to the new instruction as an implicit use. This will preserve any other flags (e.g., kill) on the operand. Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=113456&r1=113455&r2=113456&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Wed Sep 8 19:38:32 2010 @@ -122,13 +122,17 @@ MIB.addOperand(MI.getOperand(OpIdx++)); MIB = AddDefaultPred(MIB); - TransferImpOps(MI, MIB, MIB); - // For an instruction writing the odd subregs, add an implicit use of the - // super-register because the even subregs were loaded separately. - if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc) - MIB.addReg(DstReg, RegState::Implicit); + // For an instruction writing double-spaced subregs, the pseudo instruction + // has an extra operand that is a use of the super-register. Copy that over + // to the new instruction as an implicit operand. + if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc) { + MachineOperand MO = MI.getOperand(OpIdx); + MO.setImplicit(true); + MIB.addOperand(MO); + } // Add an implicit def for the super-register. MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); + TransferImpOps(MI, MIB, MIB); MI.eraseFromParent(); } From echristo at apple.com Wed Sep 8 19:53:57 2010 From: echristo at apple.com (Eric Christopher) Date: Thu, 09 Sep 2010 00:53:57 -0000 Subject: [llvm-commits] [llvm] r113459 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20100909005357.AC9562A6C12C@llvm.org> Author: echristo Date: Wed Sep 8 19:53:57 2010 New Revision: 113459 URL: http://llvm.org/viewvc/llvm-project?rev=113459&view=rev Log: Basic 32-bit FP operations. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=113459&r1=113458&r2=113459&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Wed Sep 8 19:53:57 2010 @@ -115,6 +115,7 @@ virtual bool ARMSelectBranch(const Instruction *I); virtual bool ARMSelectCmp(const Instruction *I); virtual bool ARMSelectFPExt(const Instruction *I); + virtual bool ARMSelectBinaryOp(const Instruction *I, unsigned ISDOpcode); // Utility routines. private: @@ -740,6 +741,44 @@ return true; } +bool ARMFastISel::ARMSelectBinaryOp(const Instruction *I, unsigned ISDOpcode) { + // We can get here in the case when we want to use NEON for our fp + // operations, but can't figure out how to. Just use the vfp instructions + // if we have them. + // FIXME: It'd be nice to use NEON instructions. + if (!Subtarget->hasVFP2()) return false; + + EVT VT = TLI.getValueType(I->getType(), true); + + // In this case make extra sure we have a 32-bit floating point add. + if (VT != MVT::f32) return false; + + unsigned Op1 = getRegForValue(I->getOperand(0)); + if (Op1 == 0) return false; + + unsigned Op2 = getRegForValue(I->getOperand(1)); + if (Op2 == 0) return false; + + unsigned Opc; + switch (ISDOpcode) { + default: return false; + case ISD::FADD: + Opc = ARM::VADDS; + break; + case ISD::FSUB: + Opc = ARM::VSUBS; + break; + case ISD::FMUL: + Opc = ARM::VMULS; + break; + } + unsigned ResultReg = createResultReg(ARM::SPRRegisterClass); + AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, + TII.get(Opc), ResultReg) + .addReg(Op1).addReg(Op2)); + return true; +} + // TODO: SoftFP support. bool ARMFastISel::TargetSelectInstruction(const Instruction *I) { // No Thumb-1 for now. @@ -757,6 +796,12 @@ return ARMSelectCmp(I); case Instruction::FPExt: return ARMSelectFPExt(I); + case Instruction::FAdd: + return ARMSelectBinaryOp(I, ISD::FADD); + case Instruction::FSub: + return ARMSelectBinaryOp(I, ISD::FSUB); + case Instruction::FMul: + return ARMSelectBinaryOp(I, ISD::FMUL); default: break; } return false; From echristo at apple.com Wed Sep 8 20:02:03 2010 From: echristo at apple.com (Eric Christopher) Date: Thu, 09 Sep 2010 01:02:03 -0000 Subject: [llvm-commits] [llvm] r113461 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20100909010203.6AF102A6C12E@llvm.org> Author: echristo Date: Wed Sep 8 20:02:03 2010 New Revision: 113461 URL: http://llvm.org/viewvc/llvm-project?rev=113461&view=rev Log: Handle 64-bit floating point binops as well. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=113461&r1=113460&r2=113461&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Wed Sep 8 20:02:03 2010 @@ -742,16 +742,16 @@ } bool ARMFastISel::ARMSelectBinaryOp(const Instruction *I, unsigned ISDOpcode) { + EVT VT = TLI.getValueType(I->getType(), true); + // We can get here in the case when we want to use NEON for our fp // operations, but can't figure out how to. Just use the vfp instructions // if we have them. // FIXME: It'd be nice to use NEON instructions. - if (!Subtarget->hasVFP2()) return false; - - EVT VT = TLI.getValueType(I->getType(), true); - - // In this case make extra sure we have a 32-bit floating point add. - if (VT != MVT::f32) return false; + const Type *Ty = I->getType(); + bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy()); + if (isFloat && !Subtarget->hasVFP2()) + return false; unsigned Op1 = getRegForValue(I->getOperand(0)); if (Op1 == 0) return false; @@ -760,19 +760,21 @@ if (Op2 == 0) return false; unsigned Opc; + bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64 || + VT.getSimpleVT().SimpleTy == MVT::i64; switch (ISDOpcode) { default: return false; case ISD::FADD: - Opc = ARM::VADDS; + Opc = is64bit ? ARM::VADDD : ARM::VADDS; break; case ISD::FSUB: - Opc = ARM::VSUBS; + Opc = is64bit ? ARM::VSUBD : ARM::VSUBS; break; case ISD::FMUL: - Opc = ARM::VMULS; + Opc = is64bit ? ARM::VMULD : ARM::VMULS; break; } - unsigned ResultReg = createResultReg(ARM::SPRRegisterClass); + unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg) .addReg(Op1).addReg(Op2)); From dalej at apple.com Wed Sep 8 20:02:39 2010 From: dalej at apple.com (Dale Johannesen) Date: Thu, 09 Sep 2010 01:02:39 -0000 Subject: [llvm-commits] [llvm] r113462 - in /llvm/trunk/lib/Target/X86: X86InstrMMX.td X86InstrSSE.td Message-ID: <20100909010239.8680C2A6C12E@llvm.org> Author: johannes Date: Wed Sep 8 20:02:39 2010 New Revision: 113462 URL: http://llvm.org/viewvc/llvm-project?rev=113462&view=rev Log: Move most MMX instructions (defined as anything that uses MMX, even if it also uses other things) from InstrSSE into InstrMMX. No (intended) functional change. Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrMMX.td?rev=113462&r1=113461&r2=113462&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrMMX.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrMMX.td Wed Sep 8 20:02:39 2010 @@ -11,6 +11,9 @@ // and properties of the instructions which are needed for code generation, // machine code emission, and analysis. // +// All instructions that use MMX should be in this file, even if they also use +// SSE. +// //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// @@ -95,6 +98,56 @@ } } +/// Unary MMX instructions requiring SSSE3. +multiclass SS3I_unop_rm_int_mm opc, string OpcodeStr, + PatFrag mem_frag64, Intrinsic IntId64> { + def rr64 : SS38I; + + def rm64 : SS38I; +} + +/// Binary MMX instructions requiring SSSE3. +let ImmT = NoImm, Constraints = "$src1 = $dst" in { +multiclass SS3I_binop_rm_int_mm opc, string OpcodeStr, + PatFrag mem_frag64, Intrinsic IntId64> { + let isCommutable = 0 in + def rr64 : SS38I; + def rm64 : SS38I; +} +} + +/// PALIGN MMX instructions (require SSSE3). +multiclass ssse3_palign_mm { + def R64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst), + (ins VR64:$src1, VR64:$src2, i8imm:$src3), + !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>; + def R64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst), + (ins VR64:$src1, i64mem:$src2, i8imm:$src3), + !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>; + def R64irr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst), + (ins VR64:$src1, VR64:$src2, i8imm:$src3), + !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), + [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2, (i8 imm:$src3)))]>; + def R64irm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst), + (ins VR64:$src1, i64mem:$src2, i8imm:$src3), + !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), + [(set VR64:$dst, (IntId VR64:$src1, + (bitconvert (load_mmx addr:$src2)), (i8 imm:$src3)))]>; +} + //===----------------------------------------------------------------------===// // MMX EMMS & FEMMS Instructions //===----------------------------------------------------------------------===// @@ -192,7 +245,12 @@ (scalar_to_vector (loadi32 addr:$src))))))]>; // Arithmetic Instructions - +defm MMX_PABSB : SS3I_unop_rm_int_mm<0x1C, "pabsb", memopv8i8, + int_x86_ssse3_pabs_b>; +defm MMX_PABSW : SS3I_unop_rm_int_mm<0x1D, "pabsw", memopv4i16, + int_x86_ssse3_pabs_w>; +defm MMX_PABSD : SS3I_unop_rm_int_mm<0x1E, "pabsd", memopv2i32, + int_x86_ssse3_pabs_d>; // -- Addition defm MMX_PADDB : MMXI_binop_rm<0xFC, "paddb", add, v8i8, 1>, MMXI_binop_rm_int<0xFC, "paddb", int_x86_mmx_padd_b, 1>; @@ -208,6 +266,14 @@ defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b, 1>; defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w, 1>; +defm MMX_PHADDW : SS3I_binop_rm_int_mm<0x01, "phaddw", memopv4i16, + int_x86_ssse3_phadd_w>; +defm MMX_PHADD : SS3I_binop_rm_int_mm<0x02, "phaddd", memopv2i32, + int_x86_ssse3_phadd_d>; +defm MMX_PHADDSW : SS3I_binop_rm_int_mm<0x03, "phaddsw", memopv4i16, + int_x86_ssse3_phadd_sw>; + + // -- Subtraction defm MMX_PSUBB : MMXI_binop_rm<0xF8, "psubb", sub, v8i8>, MMXI_binop_rm_int<0xF8, "psubb", int_x86_mmx_psub_b>; @@ -224,6 +290,13 @@ defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b>; defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w>; +defm MMX_PHSUBW : SS3I_binop_rm_int_mm<0x05, "phsubw", memopv4i16, + int_x86_ssse3_phsub_w>; +defm MMX_PHSUBD : SS3I_binop_rm_int_mm<0x06, "phsubd", memopv2i32, + int_x86_ssse3_phsub_d>; +defm MMX_PHSUBSW : SS3I_binop_rm_int_mm<0x07, "phsubsw", memopv4i16, + int_x86_ssse3_phsub_sw>; + // -- Multiplication defm MMX_PMULLW : MMXI_binop_rm<0xD5, "pmullw", mul, v4i16, 1>, MMXI_binop_rm_int<0xD5, "pmullw", int_x86_mmx_pmull_w, 1>; @@ -231,10 +304,15 @@ defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw", int_x86_mmx_pmulh_w, 1>; defm MMX_PMULHUW : MMXI_binop_rm_int<0xE4, "pmulhuw", int_x86_mmx_pmulhu_w, 1>; defm MMX_PMULUDQ : MMXI_binop_rm_int<0xF4, "pmuludq", int_x86_mmx_pmulu_dq, 1>; +let isCommutable = 1 in +defm MMX_PMULHRSW : SS3I_binop_rm_int_mm<0x0B, "pmulhrsw", memopv4i16, + int_x86_ssse3_pmul_hr_sw>; // -- Miscellanea defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd, 1>; +defm MMX_PMADDUBSW : SS3I_binop_rm_int_mm<0x04, "pmaddubsw", memopv8i8, + int_x86_ssse3_pmadd_ub_sw>; defm MMX_PAVGB : MMXI_binop_rm_int<0xE0, "pavgb", int_x86_mmx_pavg_b, 1>; defm MMX_PAVGW : MMXI_binop_rm_int<0xE3, "pavgw", int_x86_mmx_pavg_w, 1>; @@ -246,6 +324,35 @@ defm MMX_PSADBW : MMXI_binop_rm_int<0xF6, "psadbw", int_x86_mmx_psad_bw, 1>; +defm MMX_PSIGNB : SS3I_binop_rm_int_mm<0x08, "psignb", memopv8i8, + int_x86_ssse3_psign_b>; +defm MMX_PSIGNW : SS3I_binop_rm_int_mm<0x09, "psignw", memopv4i16, + int_x86_ssse3_psign_w>; +defm MMX_PSIGND : SS3I_binop_rm_int_mm<0x0A, "psignd", memopv2i32, + int_x86_ssse3_psign_d>; +let Constraints = "$src1 = $dst" in + defm MMX_PALIGN : ssse3_palign_mm<"palignr", int_x86_mmx_palignr_b>; + +let AddedComplexity = 5 in { + +def : Pat<(v1i64 (palign:$src3 VR64:$src1, VR64:$src2)), + (MMX_PALIGNR64rr VR64:$src2, VR64:$src1, + (SHUFFLE_get_palign_imm VR64:$src3))>, + Requires<[HasSSSE3]>; +def : Pat<(v2i32 (palign:$src3 VR64:$src1, VR64:$src2)), + (MMX_PALIGNR64rr VR64:$src2, VR64:$src1, + (SHUFFLE_get_palign_imm VR64:$src3))>, + Requires<[HasSSSE3]>; +def : Pat<(v4i16 (palign:$src3 VR64:$src1, VR64:$src2)), + (MMX_PALIGNR64rr VR64:$src2, VR64:$src1, + (SHUFFLE_get_palign_imm VR64:$src3))>, + Requires<[HasSSSE3]>; +def : Pat<(v8i8 (palign:$src3 VR64:$src1, VR64:$src2)), + (MMX_PALIGNR64rr VR64:$src2, VR64:$src1, + (SHUFFLE_get_palign_imm VR64:$src3))>, + Requires<[HasSSSE3]>; +} + // Logical Instructions defm MMX_PAND : MMXI_binop_rm_v1i64<0xDB, "pand", and, 1>, MMXI_binop_rm_int<0xDB, "pand", int_x86_mmx_pand, 1>; @@ -412,6 +519,18 @@ (mmx_pshufw:$src2 (bc_v4i16 (load_mmx addr:$src1)), (undef)))]>; +defm MMX_PSHUFB : SS3I_binop_rm_int_mm<0x00, "pshufb", memopv8i8, + int_x86_ssse3_pshuf_b>; +// Shuffle with PALIGN +def : Pat<(v1i64 (X86PAlign VR64:$src1, VR64:$src2, (i8 imm:$imm))), + (MMX_PALIGNR64rr VR64:$src2, VR64:$src1, imm:$imm)>; +def : Pat<(v2i32 (X86PAlign VR64:$src1, VR64:$src2, (i8 imm:$imm))), + (MMX_PALIGNR64rr VR64:$src2, VR64:$src1, imm:$imm)>; +def : Pat<(v4i16 (X86PAlign VR64:$src1, VR64:$src2, (i8 imm:$imm))), + (MMX_PALIGNR64rr VR64:$src2, VR64:$src1, imm:$imm)>; +def : Pat<(v8i8 (X86PAlign VR64:$src1, VR64:$src2, (i8 imm:$imm))), + (MMX_PALIGNR64rr VR64:$src2, VR64:$src1, imm:$imm)>; + // -- Conversion Instructions let neverHasSideEffects = 1 in { def MMX_CVTPD2PIrr : MMX2I<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src), Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=113462&r1=113461&r2=113462&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Sep 8 20:02:39 2010 @@ -3532,18 +3532,6 @@ // SSSE3 - Packed Absolute Instructions //===---------------------------------------------------------------------===// -/// SS3I_unop_rm_int_mm - Simple SSSE3 unary whose type can be v*{i8,i16,i32}. -multiclass SS3I_unop_rm_int_mm opc, string OpcodeStr, - PatFrag mem_frag64, Intrinsic IntId64> { - def rr64 : SS38I; - - def rm64 : SS38I; -} /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}. multiclass SS3I_unop_rm_int opc, string OpcodeStr, @@ -3572,19 +3560,11 @@ } defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", memopv16i8, - int_x86_ssse3_pabs_b_128>, - SS3I_unop_rm_int_mm<0x1C, "pabsb", memopv8i8, - int_x86_ssse3_pabs_b>; - + int_x86_ssse3_pabs_b_128>; defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", memopv8i16, - int_x86_ssse3_pabs_w_128>, - SS3I_unop_rm_int_mm<0x1D, "pabsw", memopv4i16, - int_x86_ssse3_pabs_w>; - + int_x86_ssse3_pabs_w_128>; defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", memopv4i32, - int_x86_ssse3_pabs_d_128>, - SS3I_unop_rm_int_mm<0x1E, "pabsd", memopv2i32, - int_x86_ssse3_pabs_d>; + int_x86_ssse3_pabs_d_128>; //===---------------------------------------------------------------------===// // SSSE3 - Packed Binary Operator Instructions @@ -3611,20 +3591,6 @@ (IntId128 VR128:$src1, (bitconvert (memopv16i8 addr:$src2))))]>, OpSize; } -multiclass SS3I_binop_rm_int_mm opc, string OpcodeStr, - PatFrag mem_frag64, Intrinsic IntId64> { - let isCommutable = 1 in - def rr64 : SS38I; - def rm64 : SS38I; -} let isAsmParserOnly = 1, Predicates = [HasAVX] in { let isCommutable = 0 in { @@ -3659,54 +3625,30 @@ let ImmT = NoImm, Constraints = "$src1 = $dst" in { let isCommutable = 0 in { defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw", memopv8i16, - int_x86_ssse3_phadd_w_128>, - SS3I_binop_rm_int_mm<0x01, "phaddw", memopv4i16, - int_x86_ssse3_phadd_w>; + int_x86_ssse3_phadd_w_128>; defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd", memopv4i32, - int_x86_ssse3_phadd_d_128>, - SS3I_binop_rm_int_mm<0x02, "phaddd", memopv2i32, - int_x86_ssse3_phadd_d>; + int_x86_ssse3_phadd_d_128>; defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", memopv8i16, - int_x86_ssse3_phadd_sw_128>, - SS3I_binop_rm_int_mm<0x03, "phaddsw", memopv4i16, - int_x86_ssse3_phadd_sw>; + int_x86_ssse3_phadd_sw_128>; defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw", memopv8i16, - int_x86_ssse3_phsub_w_128>, - SS3I_binop_rm_int_mm<0x05, "phsubw", memopv4i16, - int_x86_ssse3_phsub_w>; + int_x86_ssse3_phsub_w_128>; defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd", memopv4i32, - int_x86_ssse3_phsub_d_128>, - SS3I_binop_rm_int_mm<0x06, "phsubd", memopv2i32, - int_x86_ssse3_phsub_d>; + int_x86_ssse3_phsub_d_128>; defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", memopv8i16, - int_x86_ssse3_phsub_sw_128>, - SS3I_binop_rm_int_mm<0x07, "phsubsw", memopv4i16, - int_x86_ssse3_phsub_sw>; + int_x86_ssse3_phsub_sw_128>; defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv16i8, - int_x86_ssse3_pmadd_ub_sw_128>, - SS3I_binop_rm_int_mm<0x04, "pmaddubsw", memopv8i8, - int_x86_ssse3_pmadd_ub_sw>; + int_x86_ssse3_pmadd_ub_sw_128>; defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", memopv8i8, - int_x86_ssse3_pshuf_b_128>, - SS3I_binop_rm_int_mm<0x00, "pshufb", memopv8i8, - int_x86_ssse3_pshuf_b>; + int_x86_ssse3_pshuf_b_128>; defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", memopv16i8, - int_x86_ssse3_psign_b_128>, - SS3I_binop_rm_int_mm<0x08, "psignb", memopv8i8, - int_x86_ssse3_psign_b>; + int_x86_ssse3_psign_b_128>; defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", memopv8i16, - int_x86_ssse3_psign_w_128>, - SS3I_binop_rm_int_mm<0x09, "psignw", memopv4i16, - int_x86_ssse3_psign_w>; + int_x86_ssse3_psign_w_128>; defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", memopv4i32, - int_x86_ssse3_psign_d_128>, - SS3I_binop_rm_int_mm<0x0A, "psignd", memopv2i32, - int_x86_ssse3_psign_d>; + int_x86_ssse3_psign_d_128>; } defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv8i16, - int_x86_ssse3_pmul_hr_sw_128>, - SS3I_binop_rm_int_mm<0x0B, "pmulhrsw", memopv4i16, - int_x86_ssse3_pmul_hr_sw>; + int_x86_ssse3_pmul_hr_sw_128>; } def : Pat<(X86pshufb VR128:$src, VR128:$mask), @@ -3718,24 +3660,6 @@ // SSSE3 - Packed Align Instruction Patterns //===---------------------------------------------------------------------===// -multiclass ssse3_palign_mm { - def R64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst), - (ins VR64:$src1, VR64:$src2, i8imm:$src3), - !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>; - def R64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst), - (ins VR64:$src1, i64mem:$src2, i8imm:$src3), - !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>; - def R64irr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst), - (ins VR64:$src1, VR64:$src2, i8imm:$src3), - !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), - [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2, (i8 imm:$src3)))]>; - def R64irm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst), - (ins VR64:$src1, i64mem:$src2, i8imm:$src3), - !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), - [(set VR64:$dst, (IntId VR64:$src1, - (bitconvert (load_mmx addr:$src2)), (i8 imm:$src3)))]>; -} - multiclass ssse3_palign { def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3), @@ -3756,28 +3680,9 @@ let isAsmParserOnly = 1, Predicates = [HasAVX] in defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V; let Constraints = "$src1 = $dst" in - defm PALIGN : ssse3_palign<"palignr">, - ssse3_palign_mm<"palignr", int_x86_mmx_palignr_b>; + defm PALIGN : ssse3_palign<"palignr">; let AddedComplexity = 5 in { - -def : Pat<(v1i64 (palign:$src3 VR64:$src1, VR64:$src2)), - (PALIGNR64rr VR64:$src2, VR64:$src1, - (SHUFFLE_get_palign_imm VR64:$src3))>, - Requires<[HasSSSE3]>; -def : Pat<(v2i32 (palign:$src3 VR64:$src1, VR64:$src2)), - (PALIGNR64rr VR64:$src2, VR64:$src1, - (SHUFFLE_get_palign_imm VR64:$src3))>, - Requires<[HasSSSE3]>; -def : Pat<(v4i16 (palign:$src3 VR64:$src1, VR64:$src2)), - (PALIGNR64rr VR64:$src2, VR64:$src1, - (SHUFFLE_get_palign_imm VR64:$src3))>, - Requires<[HasSSSE3]>; -def : Pat<(v8i8 (palign:$src3 VR64:$src1, VR64:$src2)), - (PALIGNR64rr VR64:$src2, VR64:$src1, - (SHUFFLE_get_palign_imm VR64:$src3))>, - Requires<[HasSSSE3]>; - def : Pat<(v4i32 (palign:$src3 VR128:$src1, VR128:$src2)), (PALIGNR128rr VR128:$src2, VR128:$src1, (SHUFFLE_get_palign_imm VR128:$src3))>, @@ -5907,15 +5812,6 @@ (PSHUFLWmi addr:$src, imm:$imm)>; // Shuffle with PALIGN -def : Pat<(v1i64 (X86PAlign VR64:$src1, VR64:$src2, (i8 imm:$imm))), - (PALIGNR64rr VR64:$src2, VR64:$src1, imm:$imm)>; -def : Pat<(v2i32 (X86PAlign VR64:$src1, VR64:$src2, (i8 imm:$imm))), - (PALIGNR64rr VR64:$src2, VR64:$src1, imm:$imm)>; -def : Pat<(v4i16 (X86PAlign VR64:$src1, VR64:$src2, (i8 imm:$imm))), - (PALIGNR64rr VR64:$src2, VR64:$src1, imm:$imm)>; -def : Pat<(v8i8 (X86PAlign VR64:$src1, VR64:$src2, (i8 imm:$imm))), - (PALIGNR64rr VR64:$src2, VR64:$src1, imm:$imm)>; - def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))), (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>; def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))), From echristo at apple.com Wed Sep 8 20:06:51 2010 From: echristo at apple.com (Eric Christopher) Date: Thu, 09 Sep 2010 01:06:51 -0000 Subject: [llvm-commits] [llvm] r113463 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20100909010651.3495F2A6C12E@llvm.org> Author: echristo Date: Wed Sep 8 20:06:51 2010 New Revision: 113463 URL: http://llvm.org/viewvc/llvm-project?rev=113463&view=rev Log: Nuke whitespace and fix some indenting. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=113463&r1=113462&r2=113463&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Wed Sep 8 20:06:51 2010 @@ -63,7 +63,7 @@ bool isThumb; public: - explicit ARMFastISel(FunctionLoweringInfo &funcInfo) + explicit ARMFastISel(FunctionLoweringInfo &funcInfo) : FastISel(funcInfo), TM(funcInfo.MF->getTarget()), TII(*TM.getInstrInfo()), @@ -102,13 +102,13 @@ virtual unsigned FastEmitInst_extractsubreg(MVT RetVT, unsigned Op0, bool Op0IsKill, uint32_t Idx); - + // Backend specific FastISel code. virtual bool TargetSelectInstruction(const Instruction *I); virtual unsigned TargetMaterializeConstant(const Constant *C); #include "ARMGenFastISel.inc" - + // Instruction selection routines. virtual bool ARMSelectLoad(const Instruction *I); virtual bool ARMSelectStore(const Instruction *I); @@ -128,7 +128,7 @@ bool ARMComputeRegOffset(const Value *Obj, unsigned &Reg, int &Offset); unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT); unsigned ARMMaterializeInt(const Constant *C); - + bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR); const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB); }; @@ -164,7 +164,7 @@ // Do we use a predicate? if (TII.isPredicable(MI)) AddDefaultPred(MIB); - + // Do we optionally set a predicate? Preds is size > 0 iff the predicate // defines CPSR. All other OptionalDefines in ARM are the CCR register. bool CPSR = false; @@ -301,7 +301,7 @@ uint64_t Imm) { unsigned ResultReg = createResultReg(RC); const TargetInstrDesc &II = TII.get(MachineInstOpcode); - + if (II.getNumDefs() >= 1) AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) .addImm(Imm)); @@ -333,7 +333,7 @@ unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) { const APFloat Val = CFP->getValueAPF(); bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64; - + // This checks to see if we can use VFP3 instructions to materialize // a constant, otherwise we have to go through the constant pool. if (TLI.isFPImmLegal(Val, VT)) { @@ -344,10 +344,10 @@ .addFPImm(CFP)); return DestReg; } - + // No 64-bit at the moment. if (is64bit) return 0; - + // Load this from the constant pool. unsigned DestReg = ARMMaterializeInt(cast(CFP)); @@ -379,7 +379,7 @@ TII.get(ARM::LDRcp)) .addReg(DestReg).addConstantPoolIndex(Idx) .addReg(0).addImm(0)); - + return DestReg; } @@ -396,10 +396,10 @@ bool ARMFastISel::isTypeLegal(const Type *Ty, EVT &VT) { VT = TLI.getValueType(Ty, true); - + // Only handle simple types. if (VT == MVT::Other || !VT.isSimple()) return false; - + // Handle all legal types, i.e. a register that will directly hold this // value. return TLI.isTypeLegal(VT); @@ -407,12 +407,12 @@ bool ARMFastISel::isLoadTypeLegal(const Type *Ty, EVT &VT) { if (isTypeLegal(Ty, VT)) return true; - + // If this is a type than can be sign or zero-extended to a basic operation // go ahead and accept it now. if (VT == MVT::i8 || VT == MVT::i16) return true; - + return false; } @@ -441,9 +441,9 @@ // Fast instruction selection doesn't support the special // address spaces. return false; - + switch (Opcode) { - default: + default: //errs() << "Failing Opcode is: " << *Op1 << "\n"; break; case Instruction::Alloca: { @@ -451,13 +451,13 @@ return false; } } - + if (const GlobalValue *GV = dyn_cast(Obj)) { //errs() << "Failing GV is: " << GV << "\n"; (void)GV; return false; } - + // Try to get this in a register if nothing else has worked. Reg = getRegForValue(Obj); if (Reg == 0) return false; @@ -483,7 +483,7 @@ static_cast(TII)); } } - + return true; } @@ -510,12 +510,12 @@ bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, unsigned Reg, int Offset) { - + assert(VT.isSimple() && "Non-simple types are invalid here!"); unsigned Opc; - + switch (VT.getSimpleVT().SimpleTy) { - default: + default: assert(false && "Trying to emit for an unhandled type!"); return false; case MVT::i16: @@ -530,9 +530,9 @@ Opc = isThumb ? ARM::tLDR : ARM::LDR; break; } - + ResultReg = createResultReg(TLI.getRegClassFor(VT)); - + // TODO: Fix the Addressing modes so that these can share some code. // Since this is a Thumb1 load this will work in Thumb1 or 2 mode. if (isThumb) @@ -543,7 +543,7 @@ AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg) .addReg(Reg).addReg(0).addImm(Offset)); - + return true; } @@ -585,7 +585,7 @@ StrOpc = ARM::VSTRD; break; } - + if (isThumb) AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(StrOpc), SrcReg) @@ -594,7 +594,7 @@ AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(StrOpc), SrcReg) .addReg(DstReg).addReg(0).addImm(Offset)); - + return true; } @@ -611,24 +611,24 @@ SrcReg = getRegForValue(Op0); if (SrcReg == 0) return false; - + // If we're an alloca we know we have a frame index and can emit the store // quickly. if (ARMStoreAlloca(I, SrcReg, VT)) return true; - + // Our register and offset with innocuous defaults. unsigned Reg = 0; int Offset = 0; - + // See if we can handle this as Reg + Offset if (!ARMComputeRegOffset(I->getOperand(1), Reg, Offset)) return false; - + if (!ARMEmitStore(VT, SrcReg, Reg, Offset /* 0 */)) return false; - + return false; - + } bool ARMFastISel::ARMSelectLoad(const Instruction *I) { @@ -636,23 +636,23 @@ EVT VT; if (!isLoadTypeLegal(I->getType(), VT)) return false; - + // If we're an alloca we know we have a frame index and can emit the load // directly in short order. if (ARMLoadAlloca(I, VT)) return true; - + // Our register and offset with innocuous defaults. unsigned Reg = 0; int Offset = 0; - + // See if we can handle this as Reg + Offset if (!ARMComputeRegOffset(I->getOperand(0), Reg, Offset)) return false; - + unsigned ResultReg; if (!ARMEmitLoad(VT, ResultReg, Reg, Offset /* 0 */)) return false; - + UpdateValueMap(I, ResultReg); return true; } @@ -661,11 +661,11 @@ const BranchInst *BI = cast(I); MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)]; MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)]; - + // Simple branch support. unsigned CondReg = getRegForValue(BI->getCondition()); if (CondReg == 0) return false; - + unsigned CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr; unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc; AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc)) @@ -679,16 +679,16 @@ bool ARMFastISel::ARMSelectCmp(const Instruction *I) { const CmpInst *CI = cast(I); - + EVT VT; const Type *Ty = CI->getOperand(0)->getType(); if (!isTypeLegal(Ty, VT)) return false; - + bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy()); if (isFloat && !Subtarget->hasVFP2()) return false; - + unsigned CmpOpc; switch (VT.getSimpleVT().SimpleTy) { default: return false; @@ -706,13 +706,13 @@ unsigned Arg1 = getRegForValue(CI->getOperand(0)); if (Arg1 == 0) return false; - + unsigned Arg2 = getRegForValue(CI->getOperand(1)); if (Arg2 == 0) return false; - + AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc)) .addReg(Arg1).addReg(Arg2)); - + // For floating point we need to move the result to a register we can // actually do something with. if (isFloat) @@ -724,17 +724,17 @@ bool ARMFastISel::ARMSelectFPExt(const Instruction *I) { // Make sure we have VFP and that we're extending float to double. if (!Subtarget->hasVFP2()) return false; - + Value *V = I->getOperand(0); if (!I->getType()->isDoubleTy() || !V->getType()->isFloatTy()) return false; - + unsigned Op = getRegForValue(V); if (Op == 0) return false; - + unsigned Result = createResultReg(ARM::DPRRegisterClass); - AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, + AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::VCVTDS), Result) .addReg(Op)); UpdateValueMap(I, Result); @@ -743,7 +743,7 @@ bool ARMFastISel::ARMSelectBinaryOp(const Instruction *I, unsigned ISDOpcode) { EVT VT = TLI.getValueType(I->getType(), true); - + // We can get here in the case when we want to use NEON for our fp // operations, but can't figure out how to. Just use the vfp instructions // if we have them. @@ -752,13 +752,13 @@ bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy()); if (isFloat && !Subtarget->hasVFP2()) return false; - + unsigned Op1 = getRegForValue(I->getOperand(0)); if (Op1 == 0) return false; - + unsigned Op2 = getRegForValue(I->getOperand(1)); if (Op2 == 0) return false; - + unsigned Opc; bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64 || VT.getSimpleVT().SimpleTy == MVT::i64; @@ -785,7 +785,7 @@ bool ARMFastISel::TargetSelectInstruction(const Instruction *I) { // No Thumb-1 for now. if (isThumb && !AFI->isThumb2Function()) return false; - + switch (I->getOpcode()) { case Instruction::Load: return ARMSelectLoad(I); @@ -795,15 +795,15 @@ return ARMSelectBranch(I); case Instruction::ICmp: case Instruction::FCmp: - return ARMSelectCmp(I); + return ARMSelectCmp(I); case Instruction::FPExt: - return ARMSelectFPExt(I); + return ARMSelectFPExt(I); case Instruction::FAdd: - return ARMSelectBinaryOp(I, ISD::FADD); + return ARMSelectBinaryOp(I, ISD::FADD); case Instruction::FSub: - return ARMSelectBinaryOp(I, ISD::FSUB); + return ARMSelectBinaryOp(I, ISD::FSUB); case Instruction::FMul: - return ARMSelectBinaryOp(I, ISD::FMUL); + return ARMSelectBinaryOp(I, ISD::FMUL); default: break; } return false; From ofv at wanadoo.es Wed Sep 8 21:34:34 2010 From: ofv at wanadoo.es (=?utf-8?Q?=C3=93scar_Fuentes?=) Date: Thu, 09 Sep 2010 04:34:34 +0200 Subject: [llvm-commits] [PATCH][CMake] Removing LLVMLibDeps.cmake and exporting libraries for CMake clients. References: Message-ID: <87vd6fejb9.fsf@telefonica.net> [llvm-dev ml elided] Michael Spencer writes: > While implementing the object file library I ran into some weird > linking issues. It turned out that you have to manually specify extra > library dependencies in LLVMLibDeps.cmake, along with what you already > specify in the CMakeLists.txt file for the component. Uh? What those extra library dependencies are and why they do require modifications to LLVMLibDeps.cmake? Please provide an example. > The attached patches remove this requirement, Your patch switches from automatic to manually maintained library dependencies. On the case of LLVM, that increases the workload of the maintainer and it is the CMake equivalent of spaghetti code. Only a strong benefit would justify that. > and add real CMake > package export capabilities. A CMake user wishing to use LLVM can now > use something similar to this: > > cmake_minimum_required(VERSION 2.8) > > find_package(LLVM REQUIRED) > add_definitions(${LLVM_CXXFLAGS}) > add_executable(llvm-external-test llvm-external-test.cpp) > target_link_libraries(llvm-external-test ${LLVM_SYSTEM_LIBS} > ${LLVM_JIT_LIBS} ${LLVM_NATIVECODEGEN_LIBS}) How is that better than http://www.llvm.org/docs/CMake.html#embedding ? Think that it is usual practice to have and use multiple LLVM builds with different configurations on the same system. > llvm+clang compile with these changes on both Linux and MSVS. > Currently both patches must be applied at the same time. I can > refactor them into a 3 step process if needed. > > Does this break anything for anyone? If that is accepted (and for now I see no reason for accepting it) extensive testing on all major platforms (Linux, OS/X, Windows/mingw/MSVC++) is required before throwing away the current method, wich has its limitations, but we know them. [snip] From stoklund at 2pi.dk Wed Sep 8 22:42:24 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 8 Sep 2010 20:42:24 -0700 Subject: [llvm-commits] [llvm] r112983 - in /llvm/trunk/lib/Target/ARM: ARMExpandPseudoInsts.cpp ARMISelDAGToDAG.cpp ARMInstrNEON.td NEONPreAllocPass.cpp In-Reply-To: References: <20100903181602.C949B2A6C12C@llvm.org> Message-ID: <6CC42D25-6F2C-427D-9583-7759DDE98268@2pi.dk> On Sep 8, 2010, at 5:40 PM, Bob Wilson wrote: >> This part is weird. Is OddDblSpc guaranteed to have DstReg live in? In that case, would there already be a DstReg operand on MI that gets transferred by TransferImpOps()? >> >> The end result should be: >> >> %D0, %D2, ... = VLD ..., %QQQQ0 >> %D1, %D3, ... = VLD ..., %QQQQ0, %QQQQ0 >> > > The double-spaced VLD3/VLD4 instructions will have an explicit source operand for the super register. (It is tied to the destination operand, so it will always be the same register at this point.) The operand is basically being transferred from an explicit operand on the pseudo instruction to an implicit operand on the real instruction. Because of that, we shouldn't have to worry about conflicts with arbitrary implicit operands. > > As we discussed Friday, I also added the imp-use for both of the "even" and "odd" VLDs. Thanks, it looks good to me. The first load will get a %QQQQ0 operand which is pretty much a noop, but I think it is more robust this way. /jakob -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100908/793f6dd1/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: smime.p7s Type: application/pkcs7-signature Size: 1929 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100908/793f6dd1/attachment.bin From bigcheesegs at gmail.com Wed Sep 8 22:53:01 2010 From: bigcheesegs at gmail.com (Michael Spencer) Date: Wed, 8 Sep 2010 23:53:01 -0400 Subject: [llvm-commits] [PATCH][CMake] Removing LLVMLibDeps.cmake and exporting libraries for CMake clients. In-Reply-To: <87vd6fejb9.fsf@telefonica.net> References: <87vd6fejb9.fsf@telefonica.net> Message-ID: On Wed, Sep 8, 2010 at 10:34 PM, ?scar Fuentes wrote: > [llvm-dev ml elided] > > Michael Spencer > writes: > >> While implementing the object file library I ran into some weird >> linking issues. It turned out that you have to manually specify extra >> library dependencies in LLVMLibDeps.cmake, along with what you already >> specify in the CMakeLists.txt file for the component. > > Uh? What those extra library dependencies are and why they do require > modifications to LLVMLibDeps.cmake? Please provide an example. When I added LLVMObject, I had to go and add the following to LLVMLibDeps.cmake: set(MSVC_LIB_DEPS_LLVMObject LLVMSupport LLVMSystem) Apparently this file can be automatically generated, but only on non Windows platforms with all targets enabled, neither of which I do. >> The attached patches remove this requirement, > > Your patch switches from automatic to manually maintained library > dependencies. On the case of LLVM, that increases the workload of the > maintainer and it is the CMake equivalent of spaghetti code. Only a > strong benefit would justify that. Currently we have a mess of both. Some targets use target_link_libraries, and others use LLVM_LINK_COMPONENTS. We already have to manually maintain LLVMLibDeps.cmake. In fact just recently someone forgot to commit that file when they made other changes. My proposal is hardly spaghetti code. It's the same thing as #include. Should compilers just look at all of the header files and pick which ones to include automatically? With target_link_libraries, you only have to specify which libraries the target _directly_ needs to link to. Any other libraries will be pulled in because CMake knows about the dependencies. >> and add real CMake >> package export capabilities. A CMake user wishing to use LLVM can now >> use something similar to this: >> >> cmake_minimum_required(VERSION 2.8) >> >> find_package(LLVM REQUIRED) >> add_definitions(${LLVM_CXXFLAGS}) >> add_executable(llvm-external-test llvm-external-test.cpp) >> target_link_libraries(llvm-external-test ${LLVM_SYSTEM_LIBS} >> ${LLVM_JIT_LIBS} ${LLVM_NATIVECODEGEN_LIBS}) > > How is that better than > > http://www.llvm.org/docs/CMake.html#embedding Because it is the standard CMake way of doing things. It allows trivial selection between multiple versions. It is also simpler in the case of finding non-installed builds without worrying about in/out of source builds. It is not sensitive to location changes. > ? Think that it is usual practice to have and use multiple LLVM builds > with different configurations on the same system. find_package easily supports this. In fact, if you have both a Release and Debug build of LLVM installed, it will automatically choose the correct build based on your own current build type. >> llvm+clang compile with these changes on both Linux and MSVS. >> Currently both patches must be applied at the same time. I can >> refactor them into a 3 step process if needed. >> >> Does this break anything for anyone? > > If that is accepted (and for now I see no reason for accepting it) > extensive testing on all major platforms (Linux, OS/X, > Windows/mingw/MSVC++) is required before throwing away the current > method, wich has its limitations, but we know them. I agree it needs to be well tested. Currently the only platform that it has yet to be tested on is OS/X. - Michael Spencer From aggarwa4 at illinois.edu Wed Sep 8 23:01:02 2010 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Thu, 09 Sep 2010 04:01:02 -0000 Subject: [llvm-commits] [poolalloc] r113470 - /poolalloc/trunk/test/dsa/td/fptr.ll Message-ID: <20100909040102.7B2962A6C12E@llvm.org> Author: aggarwa4 Date: Wed Sep 8 23:01:02 2010 New Revision: 113470 URL: http://llvm.org/viewvc/llvm-project?rev=113470&view=rev Log: More test Added: poolalloc/trunk/test/dsa/td/fptr.ll Added: poolalloc/trunk/test/dsa/td/fptr.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/td/fptr.ll?rev=113470&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/td/fptr.ll (added) +++ poolalloc/trunk/test/dsa/td/fptr.ll Wed Sep 8 23:01:02 2010 @@ -0,0 +1,156 @@ + +;RUN: dsaopt %s -dsa-eq -analyze + +; ModuleID = 'multi_level.o' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" + +define i32* @foo1(i32* %a) nounwind { +entry: + %a_addr = alloca i32* ; [#uses=2] + %retval = alloca i32* ; [#uses=2] + %0 = alloca i32* ; [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store i32* %a, i32** %a_addr + %1 = load i32** %a_addr, align 8 ; [#uses=1] + store i32* %1, i32** %0, align 8 + %2 = load i32** %0, align 8 ; [#uses=1] + store i32* %2, i32** %retval, align 8 + br label %return + +return: ; preds = %entry + %retval1 = load i32** %retval ; [#uses=1] + ret i32* %retval1 +} + +define i32* @foo2(i32* %a) nounwind { +entry: + %a_addr = alloca i32* ; [#uses=2] + %retval = alloca i32* ; [#uses=2] + %0 = alloca i32* ; [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store i32* %a, i32** %a_addr + %1 = load i32** %a_addr, align 8 ; [#uses=1] + store i32* %1, i32** %0, align 8 + %2 = load i32** %0, align 8 ; [#uses=1] + store i32* %2, i32** %retval, align 8 + br label %return + +return: ; preds = %entry + %retval1 = load i32** %retval ; [#uses=1] + ret i32* %retval1 +} + +define i32* @foo3(i32* %a) nounwind { +entry: + %a_addr = alloca i32* ; [#uses=2] + %retval = alloca i32* ; [#uses=2] + %0 = alloca i32* ; [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store i32* %a, i32** %a_addr + %1 = load i32** %a_addr, align 8 ; [#uses=1] + store i32* %1, i32** %0, align 8 + %2 = load i32** %0, align 8 ; [#uses=1] + store i32* %2, i32** %retval, align 8 + br label %return + +return: ; preds = %entry + %retval1 = load i32** %retval ; [#uses=1] + ret i32* %retval1 +} + +define i32* @foo4(i32* %a) nounwind { +entry: + %a_addr = alloca i32* ; [#uses=2] + %retval = alloca i32* ; [#uses=2] + %0 = alloca i32* ; [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store i32* %a, i32** %a_addr + %1 = load i32** %a_addr, align 8 ; [#uses=1] + store i32* %1, i32** %0, align 8 + %2 = load i32** %0, align 8 ; [#uses=1] + store i32* %2, i32** %retval, align 8 + br label %return + +return: ; preds = %entry + %retval1 = load i32** %retval ; [#uses=1] + ret i32* %retval1 +} + +define i32* @bar1(i32* (i32*)* %fp, i32* %b) nounwind { +entry: + %fp_addr = alloca i32* (i32*)* ; [#uses=2] + %b_addr = alloca i32* ; [#uses=2] + %retval = alloca i32* ; [#uses=2] + %0 = alloca i32* ; [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store i32* (i32*)* %fp, i32* (i32*)** %fp_addr + store i32* %b, i32** %b_addr + %1 = load i32* (i32*)** %fp_addr, align 8 ; [#uses=1] + %2 = load i32** %b_addr, align 8 ; [#uses=1] + %3 = call i32* %1(i32* %2) nounwind ; [#uses=1] + store i32* %3, i32** %0, align 8 + %4 = load i32** %0, align 8 ; [#uses=1] + store i32* %4, i32** %retval, align 8 + br label %return + +return: ; preds = %entry + %retval1 = load i32** %retval ; [#uses=1] + ret i32* %retval1 +} + +define i32* @zar1(i32* (i32*)* %fp1, i32* (i32*)* %fp2, i32* %c) nounwind { +entry: + %fp1_addr = alloca i32* (i32*)* ; [#uses=2] + %fp2_addr = alloca i32* (i32*)* ; [#uses=2] + %c_addr = alloca i32* ; [#uses=4] + %retval = alloca i32* ; [#uses=2] + %0 = alloca i32* ; [#uses=3] + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + store i32* (i32*)* %fp1, i32* (i32*)** %fp1_addr + store i32* (i32*)* %fp2, i32* (i32*)** %fp2_addr + store i32* %c, i32** %c_addr + %1 = load i32** %c_addr, align 8 ; [#uses=1] + %2 = load i32* %1, align 4 ; [#uses=1] + %3 = icmp sgt i32 %2, 10 ; [#uses=1] + br i1 %3, label %bb, label %bb1 + +bb: ; preds = %entry + %4 = load i32* (i32*)** %fp1_addr, align 8 ; [#uses=1] + %5 = load i32** %c_addr, align 8 ; [#uses=1] + %6 = call i32* @bar1(i32* (i32*)* %4, i32* %5) nounwind ; [#uses=1] + store i32* %6, i32** %0, align 8 + br label %bb2 + +bb1: ; preds = %entry + %7 = load i32* (i32*)** %fp2_addr, align 8 ; [#uses=1] + %8 = load i32** %c_addr, align 8 ; [#uses=1] + %9 = call i32* @bar1(i32* (i32*)* %7, i32* %8) nounwind ; [#uses=1] + store i32* %9, i32** %0, align 8 + br label %bb2 + +bb2: ; preds = %bb1, %bb + %10 = load i32** %0, align 8 ; [#uses=1] + store i32* %10, i32** %retval, align 8 + br label %return + +return: ; preds = %bb2 + %retval3 = load i32** %retval ; [#uses=1] + ret i32* %retval3 +} + +define void @main() nounwind { +entry: + %0 = call noalias i8* @malloc(i64 4) nounwind ; [#uses=1] + %1 = bitcast i8* %0 to i32* ; [#uses=1] + %2 = call i32* @zar1(i32* (i32*)* @foo1, i32* (i32*)* @foo2, i32* %1) nounwind ; [#uses=0] + %3 = call noalias i8* @malloc(i64 4) nounwind ; [#uses=1] + %4 = bitcast i8* %3 to i32* ; [#uses=1] + %5 = call i32* @zar1(i32* (i32*)* @foo3, i32* (i32*)* @foo4, i32* %4) nounwind ; [#uses=0] + br label %return + +return: ; preds = %entry + ret void +} + +declare noalias i8* @malloc(i64) nounwind From aggarwa4 at illinois.edu Wed Sep 8 23:01:29 2010 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Thu, 09 Sep 2010 04:01:29 -0000 Subject: [llvm-commits] [poolalloc] r113471 - /poolalloc/trunk/lib/DSA/Local.cpp Message-ID: <20100909040129.8D9B92A6C12E@llvm.org> Author: aggarwa4 Date: Wed Sep 8 23:01:29 2010 New Revision: 113471 URL: http://llvm.org/viewvc/llvm-project?rev=113471&view=rev Log: Comment Change. No functionality changed Modified: poolalloc/trunk/lib/DSA/Local.cpp Modified: poolalloc/trunk/lib/DSA/Local.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/Local.cpp?rev=113471&r1=113470&r2=113471&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/Local.cpp (original) +++ poolalloc/trunk/lib/DSA/Local.cpp Wed Sep 8 23:01:29 2010 @@ -904,9 +904,12 @@ } //NOTE: This code is identical to 'DSGraph::getDSCallSiteForCallSite', - //the reason it's duplicated apparently is so we can increment the - //stats 'NumIndirectCall' and 'NumDirectCall'. - //FIXME: refactor so we don't have this duplication + //the reason it's duplicated is so because this calls getValueDest, + //instead of getNodeForValue. Possibly because a DS node may not exist + //at this time, in which case getNodeForValue, creates the node, unlike + // getNodeForValue. + + //FIXME: refactor so we don't have this duplication. //Get the FunctionType for the called function const FunctionType *CalleeFuncType = DSCallSite::FunctionTypeOfCallSite(CS); From bigcheesegs at gmail.com Wed Sep 8 22:53:01 2010 From: bigcheesegs at gmail.com (Michael Spencer) Date: Wed, 8 Sep 2010 23:53:01 -0400 Subject: [llvm-commits] [PATCH][CMake] Removing LLVMLibDeps.cmake and exporting libraries for CMake clients. In-Reply-To: <87vd6fejb9.fsf@telefonica.net> References: <87vd6fejb9.fsf@telefonica.net> Message-ID: On Wed, Sep 8, 2010 at 10:34 PM, ?scar Fuentes wrote: > [llvm-dev ml elided] > > Michael Spencer > writes: > >> While implementing the object file library I ran into some weird >> linking issues. It turned out that you have to manually specify extra >> library dependencies in LLVMLibDeps.cmake, along with what you already >> specify in the CMakeLists.txt file for the component. > > Uh? What those extra library dependencies are and why they do require > modifications to LLVMLibDeps.cmake? Please provide an example. When I added LLVMObject, I had to go and add the following to LLVMLibDeps.cmake: set(MSVC_LIB_DEPS_LLVMObject LLVMSupport LLVMSystem) Apparently this file can be automatically generated, but only on non Windows platforms with all targets enabled, neither of which I do. >> The attached patches remove this requirement, > > Your patch switches from automatic to manually maintained library > dependencies. On the case of LLVM, that increases the workload of the > maintainer and it is the CMake equivalent of spaghetti code. Only a > strong benefit would justify that. Currently we have a mess of both. Some targets use target_link_libraries, and others use LLVM_LINK_COMPONENTS. We already have to manually maintain LLVMLibDeps.cmake. In fact just recently someone forgot to commit that file when they made other changes. My proposal is hardly spaghetti code. It's the same thing as #include. Should compilers just look at all of the header files and pick which ones to include automatically? With target_link_libraries, you only have to specify which libraries the target _directly_ needs to link to. Any other libraries will be pulled in because CMake knows about the dependencies. >> and add real CMake >> package export capabilities. A CMake user wishing to use LLVM can now >> use something similar to this: >> >> cmake_minimum_required(VERSION 2.8) >> >> find_package(LLVM REQUIRED) >> add_definitions(${LLVM_CXXFLAGS}) >> add_executable(llvm-external-test llvm-external-test.cpp) >> target_link_libraries(llvm-external-test ${LLVM_SYSTEM_LIBS} >> ${LLVM_JIT_LIBS} ${LLVM_NATIVECODEGEN_LIBS}) > > How is that better than > > http://www.llvm.org/docs/CMake.html#embedding Because it is the standard CMake way of doing things. It allows trivial selection between multiple versions. It is also simpler in the case of finding non-installed builds without worrying about in/out of source builds. It is not sensitive to location changes. > ? Think that it is usual practice to have and use multiple LLVM builds > with different configurations on the same system. find_package easily supports this. In fact, if you have both a Release and Debug build of LLVM installed, it will automatically choose the correct build based on your own current build type. >> llvm+clang compile with these changes on both Linux and MSVS. >> Currently both patches must be applied at the same time. I can >> refactor them into a 3 step process if needed. >> >> Does this break anything for anyone? > > If that is accepted (and for now I see no reason for accepting it) > extensive testing on all major platforms (Linux, OS/X, > Windows/mingw/MSVC++) is required before throwing away the current > method, wich has its limitations, but we know them. I agree it needs to be well tested. Currently the only platform that it has yet to be tested on is OS/X. - Michael Spencer From ofv at wanadoo.es Wed Sep 8 23:47:35 2010 From: ofv at wanadoo.es (=?utf-8?Q?=C3=93scar?= Fuentes) Date: Thu, 09 Sep 2010 06:47:35 +0200 Subject: [llvm-commits] [PATCH][CMake] Removing LLVMLibDeps.cmake and exporting libraries for CMake clients. In-Reply-To: (Michael Spencer's message of "Wed, 8 Sep 2010 23:53:01 -0400") References: <87vd6fejb9.fsf@telefonica.net> Message-ID: <87fwxjed5k.fsf@telefonica.net> Michael Spencer writes: >> Uh? What those extra library dependencies are and why they do require >> modifications to LLVMLibDeps.cmake? Please provide an example. > > When I added LLVMObject, I had to go and add the following to LLVMLibDeps.cmake: > > set(MSVC_LIB_DEPS_LLVMObject LLVMSupport LLVMSystem) > > Apparently this file can be automatically generated, but only on non > Windows platforms with all targets enabled, neither of which I do. Well, so you had to add a line to a file. It doesn't seem a big issue. (And last time I tried it is possible to regenerate LLVMLibDeps.cmake with MinGW/MSYS on Windows) Anyways putting target_link_libraries(object support system) on libs/Obect/CMakeLists.txt would do too until some *nix guy regenerates the dependencies, unless there are other LLVM libraries that depend on LLVMObject. >> Your patch switches from automatic to manually maintained library >> dependencies. On the case of LLVM, that increases the workload of the >> maintainer and it is the CMake equivalent of spaghetti code. Only a >> strong benefit would justify that. > > Currently we have a mess of both. Some targets use > target_link_libraries, No targets should use target_link_libraries for dependencies on LLVM libraries, except perhaps some utilities like tblgen. > and others use LLVM_LINK_COMPONENTS. We already > have to manually maintain LLVMLibDeps.cmake. In fact just recently > someone forgot to commit that file when they made other changes. It is very different to have to commit a file than to wade through several files updating dependency lists. Take a look at the svn history of LLVMLibDeps.cmake and you can get an idea of the amount of work. And that only shows the changes caused by committed changes on the libraries. > My proposal is hardly spaghetti code. It's the same thing as #include. > Should compilers just look at all of the header files and pick which > ones to include automatically? Certainly, it would be a nice feaure :-) The current system is not doing exactly that, though. You pass a list of top-level component names and LLVMConfig.cmake figures out the list of required LLVM libraries. > With target_link_libraries, you only have to specify which libraries > the target _directly_ needs to link to. Any other libraries will be > pulled in because CMake knows about the dependencies. Right, but then you need to maintain dependencies on the 76 CMakeLists.txt files under lib/. Figuring out on which library the missing reference resides is not a straightforward task, contrary to just re-running the build. >> How is that better than >> >> http://www.llvm.org/docs/CMake.html#embedding > > Because it is the standard CMake way of doing things. It allows > trivial selection between multiple versions. It is also simpler in the > case of finding non-installed builds without worrying about in/out of > source builds. It is not sensitive to location changes. I'm not familiar with EXPORT, so maybe you are right here. A different issue is the compatibility of EXPORT with the current dependency system. >> ? Think that it is usual practice to have and use multiple LLVM builds >> with different configurations on the same system. > > find_package easily supports this. In fact, if you have both a Release > and Debug build of LLVM installed, it will automatically choose the > correct build based on your own current build type. How? If I have d:/libs/llvm/vcr, d:/libs/llvm/vcd, d:/libs/llvm/mr, d:/libs/llvm/md, etc (for (r)elease and (d)ebug builds on (m)ing and (v)visual (c)++) how it knows which to pick? And if I add to that another variant: (s)table, (t)esting and (t)ip builds? I see no way of sorting out that conundrum except for explicitly passing the path to the install or build I want to use. And then find_package is useless. > I agree it needs to be well tested. Currently the only platform that > it has yet to be tested on is OS/X. Just to be clear: by "testing" I don't mean to run the default build to see if it completes. It consists on trying combinations of at least the most popular variables and options, which includes BUILD_SHARED_LIBS (where supported) CMAKE_BUILD_TYPE, etc and the LLVM-specific variables listed on http://www.llvm.org/docs/CMake.html Yes, I know it is a lot of time. Being there, done that. From bob.wilson at apple.com Thu Sep 9 00:40:26 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Thu, 09 Sep 2010 05:40:26 -0000 Subject: [llvm-commits] [llvm] r113473 - in /llvm/trunk: lib/Target/ARM/ARMInstrNEON.td test/CodeGen/Thumb2/machine-licm-vdup.ll Message-ID: <20100909054026.E1E1A2A6C12C@llvm.org> Author: bwilson Date: Thu Sep 9 00:40:26 2010 New Revision: 113473 URL: http://llvm.org/viewvc/llvm-project?rev=113473&view=rev Log: Fix NEON VLD pseudo instruction itineraries that were incorrectly copied from the VST pseudos. The VLD/VST scheduling still needs work (see pr6722), but at least we shouldn't confuse the loads with the stores. Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td llvm/trunk/test/CodeGen/Thumb2/machine-licm-vdup.ll Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=113473&r1=113472&r2=113473&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Thu Sep 9 00:40:26 2010 @@ -170,20 +170,20 @@ // Classes for VLD* pseudo-instructions with multi-register operands. // These are expanded to real instructions after register allocation. class VLDQPseudo - : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), IIC_VST, "">; + : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), IIC_VLD2, "">; class VLDQWBPseudo : PseudoNLdSt<(outs QPR:$dst, GPR:$wb), - (ins addrmode6:$addr, am6offset:$offset), IIC_VST, + (ins addrmode6:$addr, am6offset:$offset), IIC_VLD2, "$addr.addr = $wb">; class VLDQQPseudo - : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), IIC_VST, "">; + : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), IIC_VLD4, "">; class VLDQQWBPseudo : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb), - (ins addrmode6:$addr, am6offset:$offset), IIC_VST, + (ins addrmode6:$addr, am6offset:$offset), IIC_VLD4, "$addr.addr = $wb">; class VLDQQQQWBPseudo : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb), - (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), IIC_VST, + (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), IIC_VLD4, "$addr.addr = $wb, $src = $dst">; // VLD1 : Vector Load (multiple single elements) Modified: llvm/trunk/test/CodeGen/Thumb2/machine-licm-vdup.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/machine-licm-vdup.ll?rev=113473&r1=113472&r2=113473&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/machine-licm-vdup.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/machine-licm-vdup.ll Thu Sep 9 00:40:26 2010 @@ -12,7 +12,7 @@ bb1: ; CHECK-NEXT: %bb1 -; CHECK: vdup.32 q1, r3 +; CHECK: vdup.32 q{{.*}}, r3 %indvar = phi i32 [ %indvar.next, %bb1 ], [ 0, %entry ] %tmp1 = shl i32 %indvar, 2 %gep1 = getelementptr i8* %ptr1, i32 %tmp1 From espindola at google.com Thu Sep 9 01:01:57 2010 From: espindola at google.com (Rafael Espindola) Date: Thu, 9 Sep 2010 02:01:57 -0400 Subject: [llvm-commits] [llvm-gcc][arm][patch] Lower function signatures a bit more Message-ID: With the recent improvements Chris did to the optimization of shifts I thought that an old patch I wrote for PR6059 might have gained some extra usefulness. The patch lowers the function signatures a bit more so that it is explicit in the IL that the arguments are being split into 32 bit chunks. For example, the C code ------------------------------------------------- struct foo {double a; int b;}; void f(int, struct foo); void g(int a, double b, int c) { struct foo x = {b, c}; f(a, x); } ------------------------------------------------- Is currently lowered to -------------------------------- define void @g(i32 %a, double %b, i32 %c) nounwind optsize { entry: %tmp11 = bitcast double %b to i64 %tmp5 = zext i32 %c to i64 tail call void @f(i32 %a, i64 %tmp11, i64 %tmp5) nounwind ret void } declare void @f(i32, i64, i64) ------------------------------ And with the patch it is lowered to -------------------------------------------------------------------------------- define void @g(i32 %a.0, i32, i32 %b.0, i32 %b.1, i32 %c.0) nounwind optsize { entry: tail call void @f(i32 %a.0, i32 undef, i32 %b.0, i32 %b.1, i32 %c.0, i32 0) nounwind ret void } declare void @f(i32, i32, i32, i32, i32, i32) ----------------------------------------------------------------------------------- I tested with Debian's gcc 4.3.2 compatibility test suite: make ALT_CC_UNDER_TEST=/home/espindola/llvm-gcc-inst/bin/llvm-gcc check-gcc RUNTESTFLAGS="compat.exp" I understand if there is not a lot of interest in optimizing llvm-gcc. I will just try to remember to to check what clang does when I get the time to work with it. Cheers, -- Rafael ?vila de Esp?ndola -------------- next part -------------- A non-text attachment was scrubbed... Name: pr6059.patch Type: text/x-patch Size: 9809 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100909/b23031d8/attachment.bin From deeppatel1987 at gmail.com Thu Sep 9 01:28:05 2010 From: deeppatel1987 at gmail.com (Sandeep Patel) Date: Thu, 9 Sep 2010 06:28:05 +0000 Subject: [llvm-commits] [llvm-gcc][arm][patch] Lower function signatures a bit more In-Reply-To: References: Message-ID: If there are no regressions with hard float, LGTM with perhaps some comments explaining why you're using the TRY_PASS hook and what types you expect it to apply to. deep On Thu, Sep 9, 2010 at 6:01 AM, Rafael Espindola wrote: > With the recent improvements Chris did to the optimization of shifts I > thought that an old patch I wrote for PR6059 might have gained some > extra usefulness. The patch lowers the function signatures a bit more > so that it is explicit in the IL that the arguments are being split > into 32 bit chunks. For example, the C code > > ------------------------------------------------- > struct foo {double a; int b;}; > void f(int, struct foo); > void g(int a, double b, int c) { > ?struct foo x = {b, c}; > ?f(a, x); > } > ------------------------------------------------- > > Is currently lowered to > > -------------------------------- > > define void @g(i32 %a, double %b, i32 %c) nounwind optsize { > entry: > ?%tmp11 = bitcast double %b to i64 > ?%tmp5 = zext i32 %c to i64 > ?tail call void @f(i32 %a, i64 %tmp11, i64 %tmp5) nounwind > ?ret void > } > > declare void @f(i32, i64, i64) > > ------------------------------ > > And with the patch it is lowered to > > -------------------------------------------------------------------------------- > define void @g(i32 %a.0, i32, i32 %b.0, i32 %b.1, i32 %c.0) nounwind optsize { > entry: > ?tail call void @f(i32 %a.0, i32 undef, i32 %b.0, i32 %b.1, i32 %c.0, > i32 0) nounwind > ?ret void > } > declare void @f(i32, i32, i32, i32, i32, i32) > ----------------------------------------------------------------------------------- > > I tested with Debian's gcc 4.3.2 compatibility test suite: > > make ALT_CC_UNDER_TEST=/home/espindola/llvm-gcc-inst/bin/llvm-gcc > check-gcc RUNTESTFLAGS="compat.exp" > > I understand if there is not a lot of interest in optimizing llvm-gcc. > I will just try to remember to to check what clang does when I get the > time to work with it. > > Cheers, > -- > Rafael ?vila de Esp?ndola > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > From kalle.raiskila at nokia.com Thu Sep 9 02:30:15 2010 From: kalle.raiskila at nokia.com (Kalle Raiskila) Date: Thu, 09 Sep 2010 07:30:15 -0000 Subject: [llvm-commits] [llvm] r113478 - /llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Message-ID: <20100909073015.6E6922A6C12D@llvm.org> Author: kraiskil Date: Thu Sep 9 02:30:15 2010 New Revision: 113478 URL: http://llvm.org/viewvc/llvm-project?rev=113478&view=rev Log: Silence compiler warning. Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=113478&r1=113477&r2=113478&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Thu Sep 9 02:30:15 2010 @@ -1737,7 +1737,7 @@ unsigned PrevElt = 0; bool monotonic = true; bool rotate = true; - int rotamt; + int rotamt=0; EVT maskVT; // which of the c?d instructions to use if (EltVT == MVT::i8) { From baldrick at free.fr Thu Sep 9 04:37:55 2010 From: baldrick at free.fr (Duncan Sands) Date: Thu, 09 Sep 2010 09:37:55 -0000 Subject: [llvm-commits] [llvm] r113479 - /llvm/trunk/utils/release/test-release.sh Message-ID: <20100909093755.1C7602A6C12C@llvm.org> Author: baldrick Date: Thu Sep 9 04:37:54 2010 New Revision: 113479 URL: http://llvm.org/viewvc/llvm-project?rev=113479&view=rev Log: This script is executable. Modified: llvm/trunk/utils/release/test-release.sh (props changed) Propchange: llvm/trunk/utils/release/test-release.sh ------------------------------------------------------------------------------ svn:executable = * From baldrick at free.fr Thu Sep 9 07:43:44 2010 From: baldrick at free.fr (Duncan Sands) Date: Thu, 09 Sep 2010 12:43:44 -0000 Subject: [llvm-commits] [llvm] r113483 - in /llvm/trunk/test/FrontendC: 2010-05-18-asmsched.c asm-reg-var-local.c Message-ID: <20100909124344.85FF82A6C12C@llvm.org> Author: baldrick Date: Thu Sep 9 07:43:44 2010 New Revision: 113483 URL: http://llvm.org/viewvc/llvm-project?rev=113483&view=rev Log: On i386, llvm-gcc cannot be assumed to support -m64. Since these tests pass here (i686-linux and x86-64-linux) without -m64, simply remove the -m64. Modified: llvm/trunk/test/FrontendC/2010-05-18-asmsched.c llvm/trunk/test/FrontendC/asm-reg-var-local.c Modified: llvm/trunk/test/FrontendC/2010-05-18-asmsched.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/2010-05-18-asmsched.c?rev=113483&r1=113482&r2=113483&view=diff ============================================================================== --- llvm/trunk/test/FrontendC/2010-05-18-asmsched.c (original) +++ llvm/trunk/test/FrontendC/2010-05-18-asmsched.c Thu Sep 9 07:43:44 2010 @@ -1,4 +1,4 @@ -// RUN: %llvmgcc %s -c -O3 -m64 -emit-llvm -o - | llc -march=x86-64 -mtriple=x86_64-apple-darwin | FileCheck %s +// RUN: %llvmgcc %s -c -O3 -emit-llvm -o - | llc -march=x86-64 -mtriple=x86_64-apple-darwin | FileCheck %s // r9 used to be clobbered before its value was moved to r10. 7993104. void foo(int x, int y) { @@ -14,4 +14,4 @@ lr9 = x; lr10 = foo; asm volatile("bar" : "=r"(lr9) : "r"(lr9), "r"(lr10)); -} \ No newline at end of file +} Modified: llvm/trunk/test/FrontendC/asm-reg-var-local.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/asm-reg-var-local.c?rev=113483&r1=113482&r2=113483&view=diff ============================================================================== --- llvm/trunk/test/FrontendC/asm-reg-var-local.c (original) +++ llvm/trunk/test/FrontendC/asm-reg-var-local.c Thu Sep 9 07:43:44 2010 @@ -1,4 +1,4 @@ -// RUN: %llvmgcc %s -m64 -S -o - | FileCheck %s +// RUN: %llvmgcc %s -S -o - | FileCheck %s // Exercise various use cases for local asm "register variables". // XFAIL: * // XTARGET: x86_64,i686,i386 From baldrick at free.fr Thu Sep 9 07:48:04 2010 From: baldrick at free.fr (Duncan Sands) Date: Thu, 09 Sep 2010 12:48:04 -0000 Subject: [llvm-commits] [llvm] r113484 - /llvm/trunk/test/FrontendC/cstring-align.c Message-ID: <20100909124804.652E42A6C12C@llvm.org> Author: baldrick Date: Thu Sep 9 07:48:04 2010 New Revision: 113484 URL: http://llvm.org/viewvc/llvm-project?rev=113484&view=rev Log: Another test that uses -m64. Here too it looks like it can be removed. Not that the XTARGET wasn't doing anything since it does nothing without an accompanying XFAIL. Modified: llvm/trunk/test/FrontendC/cstring-align.c Modified: llvm/trunk/test/FrontendC/cstring-align.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/cstring-align.c?rev=113484&r1=113483&r2=113484&view=diff ============================================================================== --- llvm/trunk/test/FrontendC/cstring-align.c (original) +++ llvm/trunk/test/FrontendC/cstring-align.c Thu Sep 9 07:48:04 2010 @@ -1,6 +1,4 @@ -// RUN: %llvmgcc %s -c -Os -m32 -emit-llvm -o - | llc -march=x86 -mtriple=i386-apple-darwin10 | FileCheck %s -check-prefix=DARWIN32 -// RUN: %llvmgcc %s -c -Os -m64 -emit-llvm -o - | llc -march=x86-64 -mtriple=x86_64-apple-darwin10 | FileCheck %s -check-prefix=DARWIN64 -// XTARGET: darwin +// RUN: %llvmgcc %s -c -Os -emit-llvm -o - | llc -march=x86 -mtriple=i386-apple-darwin10 | FileCheck %s extern void func(const char *, const char *); @@ -8,10 +6,6 @@ func("%s: the function name", __func__); } -// DARWIN64: .align 4 -// DARWIN64: ___func__. -// DARWIN64: .asciz "long_function_name" - -// DARWIN32: .align 4 -// DARWIN32: ___func__. -// DARWIN32: .asciz "long_function_name" +// CHECK: .align 4 +// CHECK: ___func__. +// CHECK: .asciz "long_function_name" From baldrick at free.fr Thu Sep 9 07:57:29 2010 From: baldrick at free.fr (Duncan Sands) Date: Thu, 09 Sep 2010 12:57:29 -0000 Subject: [llvm-commits] [llvm] r113485 - /llvm/trunk/test/FrontendC/2010-07-14-overconservative-align.c Message-ID: <20100909125729.B395E2A6C12C@llvm.org> Author: baldrick Date: Thu Sep 9 07:57:29 2010 New Revision: 113485 URL: http://llvm.org/viewvc/llvm-project?rev=113485&view=rev Log: Get rid of the last use of -m64 in FrontendC. This solution of checking for either 4 or 8 is not very satisfactory, but it would catch the original problem (an alignment of 1). Modified: llvm/trunk/test/FrontendC/2010-07-14-overconservative-align.c Modified: llvm/trunk/test/FrontendC/2010-07-14-overconservative-align.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/2010-07-14-overconservative-align.c?rev=113485&r1=113484&r2=113485&view=diff ============================================================================== --- llvm/trunk/test/FrontendC/2010-07-14-overconservative-align.c (original) +++ llvm/trunk/test/FrontendC/2010-07-14-overconservative-align.c Thu Sep 9 07:57:29 2010 @@ -1,4 +1,4 @@ -// RUN: %llvmgcc %s -emit-llvm -m64 -S -o - | FileCheck %s +// RUN: %llvmgcc %s -emit-llvm -S -o - | FileCheck %s // PR 5995 struct s { int word; @@ -9,6 +9,6 @@ void func (struct s *s) { -// CHECK: load %struct.s** %s_addr, align 8 +// CHECK: load %struct.s** %s_addr, align {{[48]}} s->word = 0; } From geek4civic at gmail.com Thu Sep 9 08:30:48 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Thu, 09 Sep 2010 13:30:48 -0000 Subject: [llvm-commits] [llvm] r113486 - /llvm/trunk/lib/System/Host.cpp Message-ID: <20100909133048.BAB3D2A6C12C@llvm.org> Author: chapuni Date: Thu Sep 9 08:30:48 2010 New Revision: 113486 URL: http://llvm.org/viewvc/llvm-project?rev=113486&view=rev Log: lib/System/Host.cpp: 7bit-ize. Eliminate "TM" and "(R)" in comments. Modified: llvm/trunk/lib/System/Host.cpp Modified: llvm/trunk/lib/System/Host.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/System/Host.cpp?rev=113486&r1=113485&r2=113486&view=diff ============================================================================== --- llvm/trunk/lib/System/Host.cpp (original) +++ llvm/trunk/lib/System/Host.cpp Thu Sep 9 08:30:48 2010 @@ -129,21 +129,21 @@ return "i386"; case 4: switch (Model) { - case 0: // Intel486TM DX processors - case 1: // Intel486TM DX processors + case 0: // Intel486 DX processors + case 1: // Intel486 DX processors case 2: // Intel486 SX processors - case 3: // Intel487TM processors, IntelDX2 OverDrive?? processors, - // IntelDX2TM processors + case 3: // Intel487 processors, IntelDX2 OverDrive processors, + // IntelDX2 processors case 4: // Intel486 SL processor - case 5: // IntelSX2TM processors + case 5: // IntelSX2 processors case 7: // Write-Back Enhanced IntelDX2 processors - case 8: // IntelDX4 OverDrive processors, IntelDX4TM processors + case 8: // IntelDX4 OverDrive processors, IntelDX4 processors default: return "i486"; } case 5: switch (Model) { case 1: // Pentium OverDrive processor for Pentium processor (60, 66), - // Pentium?? processors (60, 66) + // Pentium processors (60, 66) case 2: // Pentium OverDrive processor for Pentium processor (75, 90, // 100, 120, 133), Pentium processors (75, 90, 100, 120, 133, // 150, 166, 200) @@ -151,9 +151,9 @@ // systems return "pentium"; - case 4: // Pentium OverDrive processor with MMXTM technology for Pentium + case 4: // Pentium OverDrive processor with MMX technology for Pentium // processor (75, 90, 100, 120, 133), Pentium processor with - // MMXTM technology (166, 200) + // MMX technology (166, 200) return "pentium-mmx"; default: return "pentium"; @@ -166,7 +166,7 @@ case 3: // Intel Pentium II OverDrive processor, Pentium II processor, // model 03 case 5: // Pentium II processor, model 05, Pentium II Xeon processor, - // model 05, and Intel?? Celeron?? processor, model 05 + // model 05, and Intel Celeron processor, model 05 case 6: // Celeron processor, model 06 return "pentium2"; @@ -183,13 +183,13 @@ // 0Dh. All processors are manufactured using the 90 nm process. return "pentium-m"; - case 14: // Intel CoreTM Duo processor, Intel CoreTM Solo processor, model + case 14: // Intel Core Duo processor, Intel Core Solo processor, model // 0Eh. All processors are manufactured using the 65 nm process. return "yonah"; - case 15: // Intel CoreTM2 Duo processor, Intel CoreTM2 Duo mobile - // processor, Intel CoreTM2 Quad processor, Intel CoreTM2 Quad - // mobile processor, Intel CoreTM2 Extreme processor, Intel + case 15: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile + // processor, Intel Core 2 Quad processor, Intel Core 2 Quad + // mobile processor, Intel Core 2 Extreme processor, Intel // Pentium Dual-Core processor, Intel Xeon processor, model // 0Fh. All processors are manufactured using the 65 nm process. case 22: // Intel Celeron processor model 16h. All processors are @@ -200,7 +200,7 @@ // Integrated Processor with Intel QuickAssist Technology return "i686"; // FIXME: ??? - case 23: // Intel CoreTM2 Extreme processor, Intel Xeon processor, model + case 23: // Intel Core 2 Extreme processor, Intel Xeon processor, model // 17h. All processors are manufactured using the 45 nm process. // // 45nm: Penryn , Wolfdale, Yorkfield (XE) @@ -225,7 +225,7 @@ case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon // processor MP, and Intel Celeron processor. All processors are // model 01h and manufactured using the 0.18 micron process. - case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor ??? M, + case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M, // Intel Xeon processor, Intel Xeon processor MP, Intel Celeron // processor, and Mobile Intel Celeron processor. All processors // are model 02h and manufactured using the 0.13 micron process. From benny.kra at googlemail.com Thu Sep 9 10:00:41 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Thu, 09 Sep 2010 15:00:41 -0000 Subject: [llvm-commits] [llvm] r113488 - in /llvm/trunk/test: MC/ELF/basic-elf.ll Scripts/elf-dump Scripts/elf-dump.bat Message-ID: <20100909150041.683122A6C12C@llvm.org> Author: d0k Date: Thu Sep 9 10:00:41 2010 New Revision: 113488 URL: http://llvm.org/viewvc/llvm-project?rev=113488&view=rev Log: Add an elf-dumper utility. - Output format and some of the code stolen from macho-dump. - Somewhat incomplete and probably buggy. - Comes with a very basic test. Added: llvm/trunk/test/MC/ELF/basic-elf.ll llvm/trunk/test/Scripts/elf-dump (with props) llvm/trunk/test/Scripts/elf-dump.bat Added: llvm/trunk/test/MC/ELF/basic-elf.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/basic-elf.ll?rev=113488&view=auto ============================================================================== --- llvm/trunk/test/MC/ELF/basic-elf.ll (added) +++ llvm/trunk/test/MC/ELF/basic-elf.ll Thu Sep 9 10:00:41 2010 @@ -0,0 +1,110 @@ +; RUN: llc -filetype=obj -mtriple i686-pc-linux-gnu %s -o - | elf-dump | FileCheck -check-prefix=32 %s +; RUN: llc -filetype=obj -mtriple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck -check-prefix=64 %s + + at .str1 = private constant [6 x i8] c"Hello\00" + at .str2 = private constant [7 x i8] c"World!\00" + +define i32 @main() nounwind { + %1 = call i32 @puts(i8* getelementptr inbounds ([6 x i8]* @.str1, i32 0, i32 0)) + %2 = call i32 @puts(i8* getelementptr inbounds ([7 x i8]* @.str2, i32 0, i32 0)) + ret i32 0 +} + +declare i32 @puts(i8* nocapture) nounwind + +; 32: ('e_indent[EI_CLASS]', 1) +; 32: ('e_indent[EI_DATA]', 1) +; 32: ('e_indent[EI_VERSION]', 1) +; 32: ('_sections', [ +; 32: # Section 0 +; 32: (('sh_name', 0) # '' + +; 32: # '.text' +; 32: # '.rel.text' + +; 32: ('_relocations', [ +; 32: # Relocation 0 +; 32: (('r_offset', 6) +; 32: ('r_type', 1) +; 32: ), +; 32: # Relocation 1 +; 32: (('r_offset', 11) +; 32: ('r_type', 2) +; 32: ), +; 32: # Relocation 2 +; 32: (('r_offset', 18) +; 32: ('r_type', 1) +; 32: ), +; 32: # Relocation 3 +; 32: (('r_offset', 23) +; 32: ('r_type', 2) +; 32: ), +; 32: ]) + +; 32: ('st_bind', 0) +; 32: ('st_type', 3) + +; 32: ('st_bind', 0) +; 32: ('st_type', 3) + +; 32: ('st_bind', 0) +; 32: ('st_type', 3) + +; 32: # 'main' +; 32: ('st_bind', 1) +; 32-NEXT: ('st_type', 2) + +; 32: # 'puts' +; 32: ('st_bind', 1) +; 32-NEXT: ('st_type', 0) + + +; 64: ('e_indent[EI_CLASS]', 2) +; 64: ('e_indent[EI_DATA]', 1) +; 64: ('e_indent[EI_VERSION]', 1) +; 64: ('_sections', [ +; 64: # Section 0 +; 64: (('sh_name', 0) # '' + +; 64: # '.text' +; 64: # '.rela.text' + +; 64: ('_relocations', [ +; 64: # Relocation 0 +; 64: (('r_offset', 5) +; 64: ('r_type', 11) +; 64: ('r_addend', 0) +; 64: ), +; 64: # Relocation 1 +; 64: (('r_offset', 10) +; 64: ('r_type', 2) +; 64: ('r_addend', -4) +; 64: ), +; 64: # Relocation 2 +; 64: (('r_offset', 15) +; 64: ('r_type', 11) +; 64: ('r_addend', 6) +; 64: ), +; 64: # Relocation 3 +; 64: (('r_offset', 20) +; 64: ('r_type', 2) +; 64: ('r_addend', -4) +; 64: ), +; 64: ]) + +; 64: ('st_bind', 0) +; 64: ('st_type', 3) + +; 64: ('st_bind', 0) +; 64: ('st_type', 3) + +; 64: ('st_bind', 0) +; 64: ('st_type', 3) + +; 64: # 'main' +; 64-NEXT: ('st_bind', 1) +; 64-NEXT: ('st_type', 2) + +; 64: # 'puts' +; 64-NEXT: ('st_bind', 1) +; 64-NEXT: ('st_type', 0) Added: llvm/trunk/test/Scripts/elf-dump URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Scripts/elf-dump?rev=113488&view=auto ============================================================================== --- llvm/trunk/test/Scripts/elf-dump (added) +++ llvm/trunk/test/Scripts/elf-dump Thu Sep 9 10:00:41 2010 @@ -0,0 +1,225 @@ +#!/usr/bin/env python + +import struct +import sys +import StringIO + +class Reader: + def __init__(self, path): + if path == "-": + # Snarf all the data so we can seek. + self.file = StringIO.StringIO(sys.stdin.read()) + else: + self.file = open(path, "rb") + self.isLSB = None + self.is64Bit = None + + def seek(self, pos): + self.file.seek(pos) + + def read(self, N): + data = self.file.read(N) + if len(data) != N: + raise ValueError, "Out of data!" + return data + + def read8(self): + return ord(self.read(1)) + + def read16(self): + return struct.unpack('><'[self.isLSB] + 'H', self.read(2))[0] + + def read32(self): + return struct.unpack('><'[self.isLSB] + 'I', self.read(4))[0] + + def read32S(self): + return struct.unpack('><'[self.isLSB] + 'i', self.read(4))[0] + + def read64(self): + return struct.unpack('><'[self.isLSB] + 'Q', self.read(8))[0] + + def read64S(self): + return struct.unpack('><'[self.isLSB] + 'q', self.read(8))[0] + + def readWord(self): + if self.is64Bit: + return self.read64() + else: + return self.read32() + + def readWordS(self): + if self.is64Bit: + return self.read64S() + else: + return self.read32S() + +class StringTable: + def __init__(self, strings): + self.string_table = strings + + def __getitem__(self, index): + end = self.string_table.index('\x00', index) + return self.string_table[index:end] + +class Section: + def __init__(self, f): + self.sh_name = f.read32() + self.sh_type = f.read32() + self.sh_flags = f.readWord() + self.sh_addr = f.readWord() + self.sh_offset = f.readWord() + self.sh_size = f.readWord() + self.sh_link = f.read32() + self.sh_info = f.read32() + self.sh_addralign = f.readWord() + self.sh_entsize = f.readWord() + + def dump(self, shstrtab, f, strtab, dumpdata): + print " (('sh_name', %d) # %r" % (self.sh_name, shstrtab[self.sh_name]) + print " ('sh_type', %d)" % self.sh_type + print " ('sh_flags', %d)" % self.sh_flags + print " ('sh_addr', %d)" % self.sh_addr + print " ('sh_offset', %d)" % self.sh_offset + print " ('sh_size', %d)" % self.sh_size + print " ('sh_link', %d)" % self.sh_link + print " ('sh_info', %d)" % self.sh_info + print " ('sh_addralign', %d)" % self.sh_addralign + print " ('sh_entsize', %d)" % self.sh_entsize + if self.sh_type == 2: # SHT_SYMTAB + print " ('_symbols', [" + dumpSymtab(f, self, strtab) + print " ])" + elif self.sh_type == 4 or self.sh_type == 9: # SHT_RELA / SHT_REL + print " ('_relocations', [" + dumpRel(f, self, self.sh_type == 4) + print " ])" + elif dumpdata: + f.seek(self.sh_offset) + print " ('_section_data', %r)" % f.read(self.sh_size) + print " )," + +def dumpSymtab(f, section, strtab): + entries = section.sh_size // section.sh_entsize + + for index in range(entries): + f.seek(section.sh_offset + index * section.sh_entsize) + print " # Symbol %d" % index + name = f.read32() + print " (('st_name', %d) # %r" % (name, strtab[name]) + if not f.is64Bit: + print " ('st_value', %d)" % f.read32() + print " ('st_size', %d)" % f.read32() + st_info = f.read8() + print " ('st_bind', %d)" % (st_info >> 4) + print " ('st_type', %d)" % (st_info & 0xf) + print " ('st_other', %d)" % f.read8() + print " ('st_shndx', %d)" % f.read16() + if f.is64Bit: + print " ('st_value', %d)" % f.read64() + print " ('st_size', %d)" % f.read64() + print " )," + +def dumpRel(f, section, dumprela = False): + entries = section.sh_size // section.sh_entsize + + for index in range(entries): + f.seek(section.sh_offset + index * section.sh_entsize) + print " # Relocation %d" % index + print " (('r_offset', %d)" % f.readWord() + r_info = f.readWord() + if f.is64Bit: + print " ('r_sym', %d)" % (r_info >> 32) + print " ('r_type', %d)" % (r_info & 0xffffffff) + else: + print " ('r_sym', %d)" % (r_info >> 8) + print " ('r_type', %d)" % (r_info & 0xff) + if dumprela: + print " ('r_addend', %d)" % f.readWordS() + print " )," + +def dumpELF(path, opts): + f = Reader(path) + + magic = f.read(4) + assert magic == '\x7FELF' + + fileclass = f.read8() + if fileclass == 1: # ELFCLASS32 + f.is64Bit = False + elif fileclass == 2: # ELFCLASS64 + f.is64Bit = True + else: + raise ValueError, "Unknown file class %d" % fileclass + print "('e_indent[EI_CLASS]', %d)" % fileclass + + byteordering = f.read8() + if byteordering == 1: # ELFDATA2LSB + f.isLSB = True + elif byteordering == 2: # ELFDATA2MSB + f.isLSB = False + else: + raise ValueError, "Unknown byte ordering %d" % byteordering + print "('e_indent[EI_DATA]', %d)" % byteordering + + print "('e_indent[EI_VERSION]', %d)" % f.read8() + print "('e_indent[EI_OSABI]', %d)" % f.read8() + print "('e_indent[EI_ABIVERSION]', %d)" % f.read8() + + f.seek(16) # Seek to end of e_ident. + + print "('e_type', %d)" % f.read16() + print "('e_machine', %d)" % f.read16() + print "('e_version', %d)" % f.read32() + print "('e_entry', %d)" % f.readWord() + print "('e_phoff', %d)" % f.readWord() + e_shoff = f.readWord() + print "('e_shoff', %d)" % e_shoff + print "('e_flags', %d)" % f.read32() + print "('e_ehsize', %d)" % f.read16() + print "('e_phentsize', %d)" % f.read16() + print "('e_phnum', %d)" % f.read16() + e_shentsize = f.read16() + print "('e_shentsize', %d)" % e_shentsize + e_shnum = f.read16() + print "('e_shnum', %d)" % e_shnum + e_shstrndx = f.read16() + print "('e_shstrndx', %d)" % e_shstrndx + + # Read all section headers + sections = [] + for index in range(e_shnum): + f.seek(e_shoff + index * e_shentsize) + s = Section(f) + sections.append(s) + + # Read .shstrtab so we can resolve section names + f.seek(sections[e_shstrndx].sh_offset) + shstrtab = StringTable(f.read(sections[e_shstrndx].sh_size)) + + # Get the symbol string table + strtab = None + for section in sections: + if shstrtab[section.sh_name] == ".strtab": + f.seek(section.sh_offset) + strtab = StringTable(f.read(section.sh_size)) + break + + print "('_sections', [" + for index in range(e_shnum): + print " # Section %d" % index + sections[index].dump(shstrtab, f, strtab, opts.dumpSectionData) + print "])" + +if __name__ == "__main__": + from optparse import OptionParser, OptionGroup + parser = OptionParser("usage: %prog [options] {files}") + parser.add_option("", "--dump-section-data", dest="dumpSectionData", + help="Dump the contents of sections", + action="store_true", default=False) + (opts, args) = parser.parse_args() + + if not args: + args.append('-') + + for arg in args: + dumpELF(arg, opts) Propchange: llvm/trunk/test/Scripts/elf-dump ------------------------------------------------------------------------------ svn:executable = * Added: llvm/trunk/test/Scripts/elf-dump.bat URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Scripts/elf-dump.bat?rev=113488&view=auto ============================================================================== --- llvm/trunk/test/Scripts/elf-dump.bat (added) +++ llvm/trunk/test/Scripts/elf-dump.bat Thu Sep 9 10:00:41 2010 @@ -0,0 +1,7 @@ + at echo off + + at rem We need to set -u to treat stdin as binary. Python 3 has support for doing + at rem this in code, but I haven't found a way to do this in 2.6 yet. + +%PYTHON_EXECUTABLE% -u %LLVM_SRC_ROOT%\test\Scripts\elf-dump %1 %2 %3 %4 %5 %6 %7 %8 %9 + From espindola at google.com Thu Sep 9 10:19:26 2010 From: espindola at google.com (Rafael Espindola) Date: Thu, 9 Sep 2010 11:19:26 -0400 Subject: [llvm-commits] [llvm-gcc][arm][patch] Lower function signatures a bit more In-Reply-To: References: Message-ID: On 9 September 2010 02:28, Sandeep Patel wrote: > If there are no regressions with hard float, LGTM with perhaps some > comments explaining why you're using the TRY_PASS hook and what types > you expect it to apply to. I will add comments, but I don't have any system that uses hard float. Is it possible to test this with some simulator? > deep Cheers, -- Rafael ?vila de Esp?ndola From gohman at apple.com Thu Sep 9 10:49:27 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 9 Sep 2010 08:49:27 -0700 Subject: [llvm-commits] [llvm] r113329 - in /llvm/trunk: include/llvm/Analysis/AliasAnalysis.h lib/Analysis/AliasAnalysis.cpp lib/Analysis/BasicAliasAnalysis.cpp In-Reply-To: References: <20100908013220.8342E2A6C12C@llvm.org> Message-ID: On Sep 8, 2010, at 1:06 PM, Devang Patel wrote: > > On Sep 7, 2010, at 6:32 PM, Dan Gohman wrote: > >> + /// ReadThenWrite - The instructions are ReadThenWriteSome and the second >> + /// instruction writes to exactly the same memory read from by the first. >> + ReadThenWrite, >> + > > ReadThenWriteSome is missing. We can add it if there's a need for it. That said, ReadThenWrite isn't especially urgent either, though it does communicates type safety (as it's sometimes called at this level). >> + /// WriteThenWrite - The instructions are WriteThenWriteSome, and the >> + /// second instruction writes to exactly the same memory written to by >> + /// the first. >> + WriteThenWrite, >> + >> + /// WriteSomeThenWrite - Both instructions are write-only, and the second >> + /// instruction writes to a superset of the memory written to by the first. >> + WriteSomeThenWrite, > > I am curious, why did not you use WriteThenWriteSome alternative ? These are for DSE. A WriteThenWriteSome would mean that only part of the first store is potentially dead, which is a lot trickier to handle. It could be added if someone were interested in that kind of thing. Dan From daniel at zuster.org Thu Sep 9 10:49:32 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 09 Sep 2010 15:49:32 -0000 Subject: [llvm-commits] [llvm] r113490 - /llvm/trunk/projects/Makefile Message-ID: <20100909154932.7F4432A6C12C@llvm.org> Author: ddunbar Date: Thu Sep 9 10:49:32 2010 New Revision: 113490 URL: http://llvm.org/viewvc/llvm-project?rev=113490&view=rev Log: projects: Don't try to build libcxx if one happens to have it checked out into llvm/projects. Modified: llvm/trunk/projects/Makefile Modified: llvm/trunk/projects/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/projects/Makefile?rev=113490&r1=113489&r2=113490&view=diff ============================================================================== --- llvm/trunk/projects/Makefile (original) +++ llvm/trunk/projects/Makefile Thu Sep 9 10:49:32 2010 @@ -14,9 +14,12 @@ # Before 2008.06.24 it lived in llvm-test, so exclude that as well for now. DIRS:= $(filter-out llvm-test test-suite,$(patsubst $(PROJ_SRC_DIR)/%/Makefile,%,$(wildcard $(PROJ_SRC_DIR)/*/Makefile))) -# Don't build compiler-rt either, it isn't designed to be built directly. +# Don't build compiler-rt, it isn't designed to be built directly. DIRS := $(filter-out compiler-rt,$(DIRS)) +# Don't build libcxx, it isn't designed to be built directly. +DIRS := $(filter-out libcxx,$(DIRS)) + # Sparc cannot link shared libraries (libtool problem?) ifeq ($(ARCH), Sparc) DIRS := $(filter-out sample, $(DIRS)) From daniel at zuster.org Thu Sep 9 10:50:19 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 09 Sep 2010 15:50:19 -0000 Subject: [llvm-commits] [llvm] r113491 - in /llvm/trunk/test: Bindings/Ocaml/analysis.ml Bindings/Ocaml/bitreader.ml Bindings/Ocaml/bitwriter.ml Bindings/Ocaml/executionengine.ml Bindings/Ocaml/scalar_opts.ml Bindings/Ocaml/target.ml Bindings/Ocaml/vmcore.ml TableGen/FieldAccess.td TableGen/ListManip.td Message-ID: <20100909155019.A27D02A6C12C@llvm.org> Author: ddunbar Date: Thu Sep 9 10:50:19 2010 New Revision: 113491 URL: http://llvm.org/viewvc/llvm-project?rev=113491&view=rev Log: tests: XFAIL a handful of tests on the vg_leak builder, so we can get back to green. Modified: llvm/trunk/test/Bindings/Ocaml/analysis.ml llvm/trunk/test/Bindings/Ocaml/bitreader.ml llvm/trunk/test/Bindings/Ocaml/bitwriter.ml llvm/trunk/test/Bindings/Ocaml/executionengine.ml llvm/trunk/test/Bindings/Ocaml/scalar_opts.ml llvm/trunk/test/Bindings/Ocaml/target.ml llvm/trunk/test/Bindings/Ocaml/vmcore.ml llvm/trunk/test/TableGen/FieldAccess.td llvm/trunk/test/TableGen/ListManip.td Modified: llvm/trunk/test/Bindings/Ocaml/analysis.ml URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bindings/Ocaml/analysis.ml?rev=113491&r1=113490&r2=113491&view=diff ============================================================================== --- llvm/trunk/test/Bindings/Ocaml/analysis.ml (original) +++ llvm/trunk/test/Bindings/Ocaml/analysis.ml Thu Sep 9 10:50:19 2010 @@ -1,5 +1,6 @@ (* RUN: %ocamlopt -warn-error A llvm.cmxa llvm_analysis.cmxa %s -o %t * RUN: %t + * XFAIL: vg_leak *) open Llvm Modified: llvm/trunk/test/Bindings/Ocaml/bitreader.ml URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bindings/Ocaml/bitreader.ml?rev=113491&r1=113490&r2=113491&view=diff ============================================================================== --- llvm/trunk/test/Bindings/Ocaml/bitreader.ml (original) +++ llvm/trunk/test/Bindings/Ocaml/bitreader.ml Thu Sep 9 10:50:19 2010 @@ -1,6 +1,7 @@ (* RUN: %ocamlopt -warn-error A llvm.cmxa llvm_bitreader.cmxa llvm_bitwriter.cmxa %s -o %t * RUN: %t %t.bc * RUN: llvm-dis < %t.bc | grep caml_int_ty + * XFAIL: vg_leak *) (* Note that this takes a moment to link, so it's best to keep the number of Modified: llvm/trunk/test/Bindings/Ocaml/bitwriter.ml URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bindings/Ocaml/bitwriter.ml?rev=113491&r1=113490&r2=113491&view=diff ============================================================================== --- llvm/trunk/test/Bindings/Ocaml/bitwriter.ml (original) +++ llvm/trunk/test/Bindings/Ocaml/bitwriter.ml Thu Sep 9 10:50:19 2010 @@ -1,6 +1,7 @@ (* RUN: %ocamlopt -warn-error A unix.cmxa llvm.cmxa llvm_bitwriter.cmxa %s -o %t * RUN: %t %t.bc * RUN: llvm-dis < %t.bc | grep caml_int_ty + * XFAIL: vg_leak *) (* Note that this takes a moment to link, so it's best to keep the number of Modified: llvm/trunk/test/Bindings/Ocaml/executionengine.ml URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bindings/Ocaml/executionengine.ml?rev=113491&r1=113490&r2=113491&view=diff ============================================================================== --- llvm/trunk/test/Bindings/Ocaml/executionengine.ml (original) +++ llvm/trunk/test/Bindings/Ocaml/executionengine.ml Thu Sep 9 10:50:19 2010 @@ -1,5 +1,6 @@ (* RUN: %ocamlopt -warn-error A llvm.cmxa llvm_target.cmxa llvm_executionengine.cmxa %s -o %t * RUN: %t + * XFAIL: vg_leak *) open Llvm Modified: llvm/trunk/test/Bindings/Ocaml/scalar_opts.ml URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bindings/Ocaml/scalar_opts.ml?rev=113491&r1=113490&r2=113491&view=diff ============================================================================== --- llvm/trunk/test/Bindings/Ocaml/scalar_opts.ml (original) +++ llvm/trunk/test/Bindings/Ocaml/scalar_opts.ml Thu Sep 9 10:50:19 2010 @@ -1,5 +1,6 @@ (* RUN: %ocamlopt -warn-error A llvm.cmxa llvm_scalar_opts.cmxa llvm_target.cmxa %s -o %t * RUN: %t %t.bc + * XFAIL: vg_leak *) (* Note: It takes several seconds for ocamlopt to link an executable with Modified: llvm/trunk/test/Bindings/Ocaml/target.ml URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bindings/Ocaml/target.ml?rev=113491&r1=113490&r2=113491&view=diff ============================================================================== --- llvm/trunk/test/Bindings/Ocaml/target.ml (original) +++ llvm/trunk/test/Bindings/Ocaml/target.ml Thu Sep 9 10:50:19 2010 @@ -1,5 +1,6 @@ (* RUN: %ocamlopt -warn-error A llvm.cmxa llvm_target.cmxa %s -o %t * RUN: %t %t.bc + * XFAIL: vg_leak *) (* Note: It takes several seconds for ocamlopt to link an executable with Modified: llvm/trunk/test/Bindings/Ocaml/vmcore.ml URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bindings/Ocaml/vmcore.ml?rev=113491&r1=113490&r2=113491&view=diff ============================================================================== --- llvm/trunk/test/Bindings/Ocaml/vmcore.ml (original) +++ llvm/trunk/test/Bindings/Ocaml/vmcore.ml Thu Sep 9 10:50:19 2010 @@ -1,6 +1,7 @@ (* RUN: %ocamlopt -warn-error A llvm.cmxa llvm_analysis.cmxa llvm_bitwriter.cmxa %s -o %t * RUN: %t %t.bc * RUN: llvm-dis < %t.bc > %t.ll + * XFAIL: vg_leak *) (* Note: It takes several seconds for ocamlopt to link an executable with Modified: llvm/trunk/test/TableGen/FieldAccess.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/TableGen/FieldAccess.td?rev=113491&r1=113490&r2=113491&view=diff ============================================================================== --- llvm/trunk/test/TableGen/FieldAccess.td (original) +++ llvm/trunk/test/TableGen/FieldAccess.td Thu Sep 9 10:50:19 2010 @@ -1,4 +1,6 @@ // RUN: tblgen %s +// XFAIL: vg_leak + class Bla { string blu = t; Modified: llvm/trunk/test/TableGen/ListManip.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/TableGen/ListManip.td?rev=113491&r1=113490&r2=113491&view=diff ============================================================================== --- llvm/trunk/test/TableGen/ListManip.td (original) +++ llvm/trunk/test/TableGen/ListManip.td Thu Sep 9 10:50:19 2010 @@ -1,4 +1,6 @@ // RUN: tblgen %s +// XFAIL: vg_leak + class Bli { string t = _t; From dpatel at apple.com Thu Sep 9 10:59:43 2010 From: dpatel at apple.com (Devang Patel) Date: Thu, 9 Sep 2010 08:59:43 -0700 Subject: [llvm-commits] [llvm] r113329 - in /llvm/trunk: include/llvm/Analysis/AliasAnalysis.h lib/Analysis/AliasAnalysis.cpp lib/Analysis/BasicAliasAnalysis.cpp In-Reply-To: References: <20100908013220.8342E2A6C12C@llvm.org> Message-ID: On Sep 9, 2010, at 8:49 AM, Dan Gohman wrote: > > On Sep 8, 2010, at 1:06 PM, Devang Patel wrote: > >> >> On Sep 7, 2010, at 6:32 PM, Dan Gohman wrote: >> >>> + /// ReadThenWrite - The instructions are ReadThenWriteSome and the second >>> + /// instruction writes to exactly the same memory read from by the first. >>> + ReadThenWrite, >>> + >> >> ReadThenWriteSome is missing. > > We can add it if there's a need for it. OK, in that case comment should not mention it now. - Devang From daniel at zuster.org Thu Sep 9 11:23:33 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 09 Sep 2010 16:23:33 -0000 Subject: [llvm-commits] [llvm] r113494 - /llvm/trunk/lib/MC/MCAssembler.cpp Message-ID: <20100909162333.B4E7F2A6C12C@llvm.org> Author: ddunbar Date: Thu Sep 9 11:23:33 2010 New Revision: 113494 URL: http://llvm.org/viewvc/llvm-project?rev=113494&view=rev Log: MC: Give a (lame) hard error if a .org directive would create an unreasonably large object file (> 1GB). Modified: llvm/trunk/lib/MC/MCAssembler.cpp Modified: llvm/trunk/lib/MC/MCAssembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAssembler.cpp?rev=113494&r1=113493&r2=113494&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAssembler.cpp (original) +++ llvm/trunk/lib/MC/MCAssembler.cpp Thu Sep 9 11:23:33 2010 @@ -447,7 +447,7 @@ // FIXME: We need a way to communicate this error. int64_t Offset = TargetLocation - FragmentOffset; - if (Offset < 0) + if (Offset < 0 || Offset >= 0x40000000) report_fatal_error("invalid .org offset '" + Twine(TargetLocation) + "' (at offset '" + Twine(FragmentOffset) + "'"); From daniel at zuster.org Thu Sep 9 11:53:37 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 09 Sep 2010 16:53:37 -0000 Subject: [llvm-commits] [test-suite] r113497 - /test-suite/trunk/External/SPEC/CINT2006/464.h264ref/Makefile Message-ID: <20100909165337.CF6F62A6C12C@llvm.org> Author: ddunbar Date: Thu Sep 9 11:53:37 2010 New Revision: 113497 URL: http://llvm.org/viewvc/llvm-project?rev=113497&view=rev Log: RUNTIMELIMIT needs to be set before including Makefile.spec2006. Modified: test-suite/trunk/External/SPEC/CINT2006/464.h264ref/Makefile Modified: test-suite/trunk/External/SPEC/CINT2006/464.h264ref/Makefile URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/External/SPEC/CINT2006/464.h264ref/Makefile?rev=113497&r1=113496&r2=113497&view=diff ============================================================================== --- test-suite/trunk/External/SPEC/CINT2006/464.h264ref/Makefile (original) +++ test-suite/trunk/External/SPEC/CINT2006/464.h264ref/Makefile Thu Sep 9 11:53:37 2010 @@ -6,11 +6,11 @@ LEVEL = ../../../.. -include ../../Makefile.spec2006 - # This test can take more than the default 500s timeout at -O0. RUNTIMELIMIT:=750 +include ../../Makefile.spec2006 + ifeq ($(RUN_TYPE),test) RUN_OPTIONS := -d foreman_test_encoder_baseline.cfg STDOUT_FILENAME := foreman_test_baseline_encodelog.out From resistor at mac.com Thu Sep 9 11:56:42 2010 From: resistor at mac.com (Owen Anderson) Date: Thu, 09 Sep 2010 16:56:42 -0000 Subject: [llvm-commits] [llvm] r113499 - in /llvm/trunk: include/llvm/Analysis/CodeMetrics.h include/llvm/Analysis/InlineCost.h lib/Analysis/InlineCost.cpp Message-ID: <20100909165642.5753C2A6C12C@llvm.org> Author: resistor Date: Thu Sep 9 11:56:42 2010 New Revision: 113499 URL: http://llvm.org/viewvc/llvm-project?rev=113499&view=rev Log: Refactor code-size reduction estimation methods out of InlineCostAnalyzer and into CodeMetrics. They don't use any InlineCostAnalyzer state, and are useful for other clients who don't necessarily want to use all of InlineCostAnalyzer's logic, some of which is fairly inlining-specific. No intended functionality change. Modified: llvm/trunk/include/llvm/Analysis/CodeMetrics.h llvm/trunk/include/llvm/Analysis/InlineCost.h llvm/trunk/lib/Analysis/InlineCost.cpp Modified: llvm/trunk/include/llvm/Analysis/CodeMetrics.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/CodeMetrics.h?rev=113499&r1=113498&r2=113499&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/CodeMetrics.h (original) +++ llvm/trunk/include/llvm/Analysis/CodeMetrics.h Thu Sep 9 11:56:42 2010 @@ -66,6 +66,17 @@ /// analyzeFunction - Add information about the specified function /// to the current structure. void analyzeFunction(Function *F); + + /// CountCodeReductionForConstant - Figure out an approximation for how + /// many instructions will be constant folded if the specified value is + /// constant. + unsigned CountCodeReductionForConstant(Value *V); + + /// CountCodeReductionForAlloca - Figure out an approximation of how much + /// smaller the function will be if it is inlined into a context where an + /// argument becomes an alloca. + /// + unsigned CountCodeReductionForAlloca(Value *V); }; } Modified: llvm/trunk/include/llvm/Analysis/InlineCost.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/InlineCost.h?rev=113499&r1=113498&r2=113499&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/InlineCost.h (original) +++ llvm/trunk/include/llvm/Analysis/InlineCost.h Thu Sep 9 11:56:42 2010 @@ -110,16 +110,7 @@ /// entry here. std::vector ArgumentWeights; - /// CountCodeReductionForConstant - Figure out an approximation for how - /// many instructions will be constant folded if the specified value is - /// constant. - unsigned CountCodeReductionForConstant(Value *V); - - /// CountCodeReductionForAlloca - Figure out an approximation of how much - /// smaller the function will be if it is inlined into a context where an - /// argument becomes an alloca. - /// - unsigned CountCodeReductionForAlloca(Value *V); + /// analyzeFunction - Add information about the specified function /// to the current structure. Modified: llvm/trunk/lib/Analysis/InlineCost.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InlineCost.cpp?rev=113499&r1=113498&r2=113499&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/InlineCost.cpp (original) +++ llvm/trunk/lib/Analysis/InlineCost.cpp Thu Sep 9 11:56:42 2010 @@ -18,96 +18,6 @@ #include "llvm/ADT/SmallPtrSet.h" using namespace llvm; -// CountCodeReductionForConstant - Figure out an approximation for how many -// instructions will be constant folded if the specified value is constant. -// -unsigned InlineCostAnalyzer::FunctionInfo:: -CountCodeReductionForConstant(Value *V) { - unsigned Reduction = 0; - for (Value::use_iterator UI = V->use_begin(), E = V->use_end(); UI != E;++UI){ - User *U = *UI; - if (isa(U) || isa(U)) { - // We will be able to eliminate all but one of the successors. - const TerminatorInst &TI = cast(*U); - const unsigned NumSucc = TI.getNumSuccessors(); - unsigned Instrs = 0; - for (unsigned I = 0; I != NumSucc; ++I) - Instrs += Metrics.NumBBInsts[TI.getSuccessor(I)]; - // We don't know which blocks will be eliminated, so use the average size. - Reduction += InlineConstants::InstrCost*Instrs*(NumSucc-1)/NumSucc; - } else if (CallInst *CI = dyn_cast(U)) { - // Turning an indirect call into a direct call is a BIG win - if (CI->getCalledValue() == V) - Reduction += InlineConstants::IndirectCallBonus; - } else if (InvokeInst *II = dyn_cast(U)) { - // Turning an indirect call into a direct call is a BIG win - if (II->getCalledValue() == V) - Reduction += InlineConstants::IndirectCallBonus; - } else { - // Figure out if this instruction will be removed due to simple constant - // propagation. - Instruction &Inst = cast(*U); - - // We can't constant propagate instructions which have effects or - // read memory. - // - // FIXME: It would be nice to capture the fact that a load from a - // pointer-to-constant-global is actually a *really* good thing to zap. - // Unfortunately, we don't know the pointer that may get propagated here, - // so we can't make this decision. - if (Inst.mayReadFromMemory() || Inst.mayHaveSideEffects() || - isa(Inst)) - continue; - - bool AllOperandsConstant = true; - for (unsigned i = 0, e = Inst.getNumOperands(); i != e; ++i) - if (!isa(Inst.getOperand(i)) && Inst.getOperand(i) != V) { - AllOperandsConstant = false; - break; - } - - if (AllOperandsConstant) { - // We will get to remove this instruction... - Reduction += InlineConstants::InstrCost; - - // And any other instructions that use it which become constants - // themselves. - Reduction += CountCodeReductionForConstant(&Inst); - } - } - } - return Reduction; -} - -// CountCodeReductionForAlloca - Figure out an approximation of how much smaller -// the function will be if it is inlined into a context where an argument -// becomes an alloca. -// -unsigned InlineCostAnalyzer::FunctionInfo:: - CountCodeReductionForAlloca(Value *V) { - if (!V->getType()->isPointerTy()) return 0; // Not a pointer - unsigned Reduction = 0; - for (Value::use_iterator UI = V->use_begin(), E = V->use_end(); UI != E;++UI){ - Instruction *I = cast(*UI); - if (isa(I) || isa(I)) - Reduction += InlineConstants::InstrCost; - else if (GetElementPtrInst *GEP = dyn_cast(I)) { - // If the GEP has variable indices, we won't be able to do much with it. - if (GEP->hasAllConstantIndices()) - Reduction += CountCodeReductionForAlloca(GEP); - } else if (BitCastInst *BCI = dyn_cast(I)) { - // Track pointer through bitcasts. - Reduction += CountCodeReductionForAlloca(BCI); - } else { - // If there is some other strange instruction, we're not going to be able - // to do much if we inline this. - return 0; - } - } - - return Reduction; -} - /// callIsSmall - If a call is likely to lower to a single target instruction, /// or is otherwise deemed small return true. /// TODO: Perhaps calls like memcpy, strcpy, etc? @@ -226,6 +136,94 @@ NumBBInsts[BB] = NumInsts - NumInstsBeforeThisBB; } +// CountCodeReductionForConstant - Figure out an approximation for how many +// instructions will be constant folded if the specified value is constant. +// +unsigned CodeMetrics::CountCodeReductionForConstant(Value *V) { + unsigned Reduction = 0; + for (Value::use_iterator UI = V->use_begin(), E = V->use_end(); UI != E;++UI){ + User *U = *UI; + if (isa(U) || isa(U)) { + // We will be able to eliminate all but one of the successors. + const TerminatorInst &TI = cast(*U); + const unsigned NumSucc = TI.getNumSuccessors(); + unsigned Instrs = 0; + for (unsigned I = 0; I != NumSucc; ++I) + Instrs += NumBBInsts[TI.getSuccessor(I)]; + // We don't know which blocks will be eliminated, so use the average size. + Reduction += InlineConstants::InstrCost*Instrs*(NumSucc-1)/NumSucc; + } else if (CallInst *CI = dyn_cast(U)) { + // Turning an indirect call into a direct call is a BIG win + if (CI->getCalledValue() == V) + Reduction += InlineConstants::IndirectCallBonus; + } else if (InvokeInst *II = dyn_cast(U)) { + // Turning an indirect call into a direct call is a BIG win + if (II->getCalledValue() == V) + Reduction += InlineConstants::IndirectCallBonus; + } else { + // Figure out if this instruction will be removed due to simple constant + // propagation. + Instruction &Inst = cast(*U); + + // We can't constant propagate instructions which have effects or + // read memory. + // + // FIXME: It would be nice to capture the fact that a load from a + // pointer-to-constant-global is actually a *really* good thing to zap. + // Unfortunately, we don't know the pointer that may get propagated here, + // so we can't make this decision. + if (Inst.mayReadFromMemory() || Inst.mayHaveSideEffects() || + isa(Inst)) + continue; + + bool AllOperandsConstant = true; + for (unsigned i = 0, e = Inst.getNumOperands(); i != e; ++i) + if (!isa(Inst.getOperand(i)) && Inst.getOperand(i) != V) { + AllOperandsConstant = false; + break; + } + + if (AllOperandsConstant) { + // We will get to remove this instruction... + Reduction += InlineConstants::InstrCost; + + // And any other instructions that use it which become constants + // themselves. + Reduction += CountCodeReductionForConstant(&Inst); + } + } + } + return Reduction; +} + +// CountCodeReductionForAlloca - Figure out an approximation of how much smaller +// the function will be if it is inlined into a context where an argument +// becomes an alloca. +// +unsigned CodeMetrics::CountCodeReductionForAlloca(Value *V) { + if (!V->getType()->isPointerTy()) return 0; // Not a pointer + unsigned Reduction = 0; + for (Value::use_iterator UI = V->use_begin(), E = V->use_end(); UI != E;++UI){ + Instruction *I = cast(*UI); + if (isa(I) || isa(I)) + Reduction += InlineConstants::InstrCost; + else if (GetElementPtrInst *GEP = dyn_cast(I)) { + // If the GEP has variable indices, we won't be able to do much with it. + if (GEP->hasAllConstantIndices()) + Reduction += CountCodeReductionForAlloca(GEP); + } else if (BitCastInst *BCI = dyn_cast(I)) { + // Track pointer through bitcasts. + Reduction += CountCodeReductionForAlloca(BCI); + } else { + // If there is some other strange instruction, we're not going to be able + // to do much if we inline this. + return 0; + } + } + + return Reduction; +} + /// analyzeFunction - Fill in the current structure with information gleaned /// from the specified function. void CodeMetrics::analyzeFunction(Function *F) { @@ -254,8 +252,8 @@ // code can be eliminated if one of the arguments is a constant. ArgumentWeights.reserve(F->arg_size()); for (Function::arg_iterator I = F->arg_begin(), E = F->arg_end(); I != E; ++I) - ArgumentWeights.push_back(ArgInfo(CountCodeReductionForConstant(I), - CountCodeReductionForAlloca(I))); + ArgumentWeights.push_back(ArgInfo(Metrics.CountCodeReductionForConstant(I), + Metrics.CountCodeReductionForAlloca(I))); } /// NeverInline - returns true if the function should never be inlined into From clattner at apple.com Thu Sep 9 11:59:28 2010 From: clattner at apple.com (Chris Lattner) Date: Thu, 9 Sep 2010 09:59:28 -0700 Subject: [llvm-commits] [llvm-gcc][arm][patch] Lower function signatures a bit more In-Reply-To: References: Message-ID: <386B2A85-DD45-4217-BE7A-FAE01B59A23B@apple.com> On Sep 8, 2010, at 11:01 PM, Rafael Espindola wrote: > With the recent improvements Chris did to the optimization of shifts I > thought that an old patch I wrote for PR6059 might have gained some > extra usefulness. The patch lowers the function signatures a bit more > so that it is explicit in the IL that the arguments are being split > into 32 bit chunks. For example, the C code I haven't reviewed the patch, but in principle this sounds like a great idea! What IR does: double foo(double X, double Y) { return X+Y; } get lowered into, and what ARM code ends up generated? -Chris > > ------------------------------------------------- > struct foo {double a; int b;}; > void f(int, struct foo); > void g(int a, double b, int c) { > struct foo x = {b, c}; > f(a, x); > } > ------------------------------------------------- > > Is currently lowered to > > -------------------------------- > > define void @g(i32 %a, double %b, i32 %c) nounwind optsize { > entry: > %tmp11 = bitcast double %b to i64 > %tmp5 = zext i32 %c to i64 > tail call void @f(i32 %a, i64 %tmp11, i64 %tmp5) nounwind > ret void > } > > declare void @f(i32, i64, i64) > > ------------------------------ > > And with the patch it is lowered to > > -------------------------------------------------------------------------------- > define void @g(i32 %a.0, i32, i32 %b.0, i32 %b.1, i32 %c.0) nounwind optsize { > entry: > tail call void @f(i32 %a.0, i32 undef, i32 %b.0, i32 %b.1, i32 %c.0, > i32 0) nounwind > ret void > } > declare void @f(i32, i32, i32, i32, i32, i32) > ----------------------------------------------------------------------------------- > > I tested with Debian's gcc 4.3.2 compatibility test suite: > > make ALT_CC_UNDER_TEST=/home/espindola/llvm-gcc-inst/bin/llvm-gcc > check-gcc RUNTESTFLAGS="compat.exp" > > I understand if there is not a lot of interest in optimizing llvm-gcc. > I will just try to remember to to check what clang does when I get the > time to work with it. > > Cheers, > -- > Rafael ?vila de Esp?ndola > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dalej at apple.com Thu Sep 9 12:13:07 2010 From: dalej at apple.com (Dale Johannesen) Date: Thu, 09 Sep 2010 17:13:07 -0000 Subject: [llvm-commits] [llvm] r113501 - in /llvm/trunk/lib/Target/X86: X86InstrMMX.td X86InstrSSE.td Message-ID: <20100909171307.790482A6C12C@llvm.org> Author: johannes Date: Thu Sep 9 12:13:07 2010 New Revision: 113501 URL: http://llvm.org/viewvc/llvm-project?rev=113501&view=rev Log: Move remaining MMX instructions from SSE to MMX. Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrMMX.td?rev=113501&r1=113500&r2=113501&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrMMX.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrMMX.td Thu Sep 9 12:13:07 2010 @@ -148,6 +148,25 @@ (bitconvert (load_mmx addr:$src2)), (i8 imm:$src3)))]>; } +multiclass sse12_cvt_pint opc, RegisterClass SrcRC, RegisterClass DstRC, + Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag, + string asm, Domain d> { + def irr : PI; + def irm : PI; +} + +multiclass sse12_cvt_pint_3addr opc, RegisterClass SrcRC, + RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop, + PatFrag ld_frag, string asm, Domain d> { + def irr : PI; + def irm : PI; +} + //===----------------------------------------------------------------------===// // MMX EMMS & FEMMS Instructions //===----------------------------------------------------------------------===// @@ -533,13 +552,6 @@ // -- Conversion Instructions let neverHasSideEffects = 1 in { -def MMX_CVTPD2PIrr : MMX2I<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src), - "cvtpd2pi\t{$src, $dst|$dst, $src}", []>; -let mayLoad = 1 in -def MMX_CVTPD2PIrm : MMX2I<0x2D, MRMSrcMem, (outs VR64:$dst), - (ins f128mem:$src), - "cvtpd2pi\t{$src, $dst|$dst, $src}", []>; - def MMX_CVTPI2PDrr : MMX2I<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src), "cvtpi2pd\t{$src, $dst|$dst, $src}", []>; let mayLoad = 1 in @@ -554,12 +566,6 @@ (ins i64mem:$src), "cvtpi2ps\t{$src, $dst|$dst, $src}", []>; -def MMX_CVTPS2PIrr : MMXI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src), - "cvtps2pi\t{$src, $dst|$dst, $src}", []>; -let mayLoad = 1 in -def MMX_CVTPS2PIrm : MMXI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src), - "cvtps2pi\t{$src, $dst|$dst, $src}", []>; - def MMX_CVTTPD2PIrr : MMX2I<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src), "cvttpd2pi\t{$src, $dst|$dst, $src}", []>; let mayLoad = 1 in @@ -574,57 +580,33 @@ "cvttps2pi\t{$src, $dst|$dst, $src}", []>; } // end neverHasSideEffects -// Intrinsic versions. -def MMX_CVTPD2PIirr : MMX2I<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src), - "cvtpd2pi\t{$src, $dst|$dst, $src}", - [(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>; -def MMX_CVTPD2PIirm : MMX2I<0x2D, MRMSrcMem, (outs VR64:$dst), - (ins f128mem:$src), - "cvtpd2pi\t{$src, $dst|$dst, $src}", - [(set VR64:$dst, - (int_x86_sse_cvtpd2pi - (bitconvert (loadv2i64 addr:$src))))]>; -def MMX_CVTPI2PDirr : MMX2I<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src), - "cvtpi2pd\t{$src, $dst|$dst, $src}", - [(set VR128:$dst, (int_x86_sse_cvtpi2pd VR64:$src))]>; +// Intrinsic forms. +defm MMX_CVTPS2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtps2pi, + f64mem, load, "cvtps2pi\t{$src, $dst|$dst, $src}", + SSEPackedSingle>, TB; +defm MMX_CVTPD2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtpd2pi, + f128mem, memop, "cvtpd2pi\t{$src, $dst|$dst, $src}", + SSEPackedDouble>, TB, OpSize; +defm MMX_CVTTPS2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttps2pi, + f64mem, load, "cvttps2pi\t{$src, $dst|$dst, $src}", + SSEPackedSingle>, TB; +defm MMX_CVTTPD2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttpd2pi, + f128mem, memop, "cvttpd2pi\t{$src, $dst|$dst, $src}", + SSEPackedDouble>, TB, OpSize; +defm MMX_CVTPI2PD : sse12_cvt_pint<0x2A, VR64, VR128, int_x86_sse_cvtpi2pd, + i64mem, load, "cvtpi2pd\t{$src, $dst|$dst, $src}", + SSEPackedDouble>, TB, OpSize; let Constraints = "$src1 = $dst" in { -def MMX_CVTPI2PSirr : MMXI<0x2A, MRMSrcReg, (outs VR128:$dst), - (ins VR128:$src1, VR64:$src2), - "cvtpi2ps\t{$src2, $dst|$dst, $src2}", - [(set VR128:$dst, - (int_x86_sse_cvtpi2ps VR128:$src1, VR64:$src2))]>; -def MMX_CVTPI2PSirm : MMXI<0x2A, MRMSrcMem, (outs VR128:$dst), - (ins VR128:$src1, i64mem:$src2), - "cvtpi2ps\t{$src2, $dst|$dst, $src2}", - [(set VR128:$dst, - (int_x86_sse_cvtpi2ps VR128:$src1, - (bitconvert (load_mmx addr:$src2))))]>; -} -def MMX_CVTPS2PIirr : MMXI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src), - "cvtps2pi\t{$src, $dst|$dst, $src}", - [(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>; -def MMX_CVTPS2PIirm : MMXI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src), - "cvtps2pi\t{$src, $dst|$dst, $src}", - [(set VR64:$dst, - (int_x86_sse_cvtps2pi - (bitconvert (load_mmx addr:$src))))]>; -def MMX_CVTTPD2PIirr: MMX2I<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src), - "cvttpd2pi\t{$src, $dst|$dst, $src}", - [(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>; -def MMX_CVTTPD2PIirm: MMX2I<0x2C, MRMSrcMem, (outs VR64:$dst), - (ins f128mem:$src), - "cvttpd2pi\t{$src, $dst|$dst, $src}", - [(set VR64:$dst, - (int_x86_sse_cvtpd2pi - (bitconvert (loadv2i64 addr:$src))))]>; -def MMX_CVTTPS2PIirr: MMXI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src), - "cvttps2pi\t{$src, $dst|$dst, $src}", - [(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>; -def MMX_CVTTPS2PIirm: MMXI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src), - "cvttps2pi\t{$src, $dst|$dst, $src}", - [(set VR64:$dst, - (int_x86_sse_cvtpd2pi - (bitconvert (load_mmx addr:$src))))]>; + defm MMX_CVTPI2PS : sse12_cvt_pint_3addr<0x2A, VR64, VR128, + int_x86_sse_cvtpi2ps, + i64mem, load, "cvtpi2ps\t{$src2, $dst|$dst, $src2}", + SSEPackedSingle>, TB; +} +// MMX->MMX vector casts. +def : Pat<(v2f64 (sint_to_fp (v2i32 VR64:$src))), + (MMX_CVTPI2PDrr VR64:$src)>, Requires<[HasSSE2]>; +def : Pat<(v2i32 (fp_to_sint (v2f64 VR128:$src))), + (MMX_CVTTPD2PIrr VR128:$src)>, Requires<[HasSSE2]>; // Extract / Insert def MMX_X86pinsrw : SDNode<"X86ISD::MMX_PINSRW", Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=113501&r1=113500&r2=113501&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Sep 9 12:13:07 2010 @@ -598,14 +598,6 @@ // Conversion Instructions Intrinsics - Match intrinsics which expect MM // and/or XMM operand(s). -multiclass sse12_cvt_pint opc, RegisterClass SrcRC, RegisterClass DstRC, - Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag, - string asm, Domain d> { - def rr : PI; - def rm : PI; -} multiclass sse12_cvt_sint opc, RegisterClass SrcRC, RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag, @@ -618,16 +610,6 @@ [(set DstRC:$dst, (Int (ld_frag addr:$src)))]>; } -multiclass sse12_cvt_pint_3addr opc, RegisterClass SrcRC, - RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop, - PatFrag ld_frag, string asm, Domain d> { - def rr : PI; - def rm : PI; -} - multiclass sse12_cvt_sint_3addr opc, RegisterClass SrcRC, RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag, string asm, bit Is2Addr = 1> { @@ -705,29 +687,6 @@ "cvtsi2sd">, XD, REX_W; } -// Instructions below don't have an AVX form. -defm Int_CVTPS2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtps2pi, - f64mem, load, "cvtps2pi\t{$src, $dst|$dst, $src}", - SSEPackedSingle>, TB; -defm Int_CVTPD2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtpd2pi, - f128mem, memop, "cvtpd2pi\t{$src, $dst|$dst, $src}", - SSEPackedDouble>, TB, OpSize; -defm Int_CVTTPS2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttps2pi, - f64mem, load, "cvttps2pi\t{$src, $dst|$dst, $src}", - SSEPackedSingle>, TB; -defm Int_CVTTPD2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttpd2pi, - f128mem, memop, "cvttpd2pi\t{$src, $dst|$dst, $src}", - SSEPackedDouble>, TB, OpSize; -defm Int_CVTPI2PD : sse12_cvt_pint<0x2A, VR64, VR128, int_x86_sse_cvtpi2pd, - i64mem, load, "cvtpi2pd\t{$src, $dst|$dst, $src}", - SSEPackedDouble>, TB, OpSize; -let Constraints = "$src1 = $dst" in { - defm Int_CVTPI2PS : sse12_cvt_pint_3addr<0x2A, VR64, VR128, - int_x86_sse_cvtpi2ps, - i64mem, load, "cvtpi2ps\t{$src2, $dst|$dst, $src2}", - SSEPackedSingle>, TB; -} - /// SSE 1 Only // Aliases for intrinsics @@ -3957,10 +3916,6 @@ (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>; def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))), (Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>; -def : Pat<(v2f64 (sint_to_fp (v2i32 VR64:$src))), - (Int_CVTPI2PDrr VR64:$src)>, Requires<[HasSSE2]>; -def : Pat<(v2i32 (fp_to_sint (v2f64 VR128:$src))), - (Int_CVTTPD2PIrr VR128:$src)>, Requires<[HasSSE2]>; // Use movaps / movups for SSE integer load / store (one byte shorter). let Predicates = [HasSSE1] in { From aggarwa4 at illinois.edu Thu Sep 9 12:15:11 2010 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Thu, 09 Sep 2010 17:15:11 -0000 Subject: [llvm-commits] [poolalloc] r113502 - /poolalloc/trunk/lib/DSA/CompleteBottomUp.cpp Message-ID: <20100909171511.4DDDF2A6C12C@llvm.org> Author: aggarwa4 Date: Thu Sep 9 12:15:11 2010 New Revision: 113502 URL: http://llvm.org/viewvc/llvm-project?rev=113502&view=rev Log: Fixed declaration bug Modified: poolalloc/trunk/lib/DSA/CompleteBottomUp.cpp Modified: poolalloc/trunk/lib/DSA/CompleteBottomUp.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/CompleteBottomUp.cpp?rev=113502&r1=113501&r2=113502&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/CompleteBottomUp.cpp (original) +++ poolalloc/trunk/lib/DSA/CompleteBottomUp.cpp Thu Sep 9 12:15:11 2010 @@ -172,7 +172,7 @@ ++csi; continue; } - DSNodeHandle SrcNH = SM.find(*sccii)->second; + SrcNH = SM.find(*sccii)->second; ++sccii; for(;sccii != sccee; ++sccii) { DSGraph::ScalarMapTy::const_iterator I = SM.find(*sccii); From daniel at zuster.org Thu Sep 9 12:38:11 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 09 Sep 2010 17:38:11 -0000 Subject: [llvm-commits] [llvm] r113503 - /llvm/trunk/Makefile.rules Message-ID: <20100909173811.32FF32A6C12C@llvm.org> Author: ddunbar Date: Thu Sep 9 12:38:11 2010 New Revision: 113503 URL: http://llvm.org/viewvc/llvm-project?rev=113503&view=rev Log: build: Allow subdir Makefiles to provide an alternate location for the SRCDIR Makefile, which can be used to allow building out of tree sources. Modified: llvm/trunk/Makefile.rules Modified: llvm/trunk/Makefile.rules URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=113503&r1=113502&r2=113503&view=diff ============================================================================== --- llvm/trunk/Makefile.rules (original) +++ llvm/trunk/Makefile.rules Thu Sep 9 12:38:11 2010 @@ -161,9 +161,13 @@ # If the Makefile in the source tree has been updated, copy it over into the # build tree. But, only do this if the source and object makefiles differ #------------------------------------------------------------------------ +ifndef PROJ_MAKEFILE +PROJ_MAKEFILE := $(PROJ_SRC_DIR)/Makefile +endif + ifneq ($(PROJ_OBJ_DIR),$(PROJ_SRC_DIR)) -Makefile: $(PROJ_SRC_DIR)/Makefile $(ExtraMakefiles) +Makefile: $(PROJ_MAKEFILE) $(ExtraMakefiles) $(Echo) "Updating Makefile" $(Verb) $(MKDIR) $(@D) $(Verb) $(CP) -f $< $@ @@ -171,7 +175,7 @@ # Copy the Makefile.* files unless we're in the root directory which avoids # the copying of Makefile.config.in or other things that should be explicitly # taken care of. -$(PROJ_OBJ_DIR)/Makefile% : $(PROJ_SRC_DIR)/Makefile% +$(PROJ_OBJ_DIR)/Makefile% : $(PROJ_MAKEFILE)% @case '$?' in \ *Makefile.rules) ;; \ *.in) ;; \ @@ -1436,27 +1440,27 @@ DEPEND_MOVEFILE = then $(MV) -f "$(ObjDir)/$*.d.tmp" "$(ObjDir)/$*.d"; \ else $(RM) "$(ObjDir)/$*.d.tmp"; exit 1; fi -$(ObjDir)/%.o: %.cpp $(ObjDir)/.dir $(BUILT_SOURCES) $(PROJ_SRC_DIR)/Makefile +$(ObjDir)/%.o: %.cpp $(ObjDir)/.dir $(BUILT_SOURCES) $(PROJ_MAKEFILE) $(Echo) "Compiling $*.cpp for $(BuildMode) build" $(PIC_FLAG) $(Verb) if $(Compile.CXX) $(DEPEND_OPTIONS) $< -o $(ObjDir)/$*.o ; \ $(DEPEND_MOVEFILE) -$(ObjDir)/%.o: %.mm $(ObjDir)/.dir $(BUILT_SOURCES) $(PROJ_SRC_DIR)/Makefile +$(ObjDir)/%.o: %.mm $(ObjDir)/.dir $(BUILT_SOURCES) $(PROJ_MAKEFILE) $(Echo) "Compiling $*.mm for $(BuildMode) build" $(PIC_FLAG) $(Verb) if $(Compile.CXX) $(DEPEND_OPTIONS) $< -o $(ObjDir)/$*.o ; \ $(DEPEND_MOVEFILE) -$(ObjDir)/%.o: %.cc $(ObjDir)/.dir $(BUILT_SOURCES) $(PROJ_SRC_DIR)/Makefile +$(ObjDir)/%.o: %.cc $(ObjDir)/.dir $(BUILT_SOURCES) $(PROJ_MAKEFILE) $(Echo) "Compiling $*.cc for $(BuildMode) build" $(PIC_FLAG) $(Verb) if $(Compile.CXX) $(DEPEND_OPTIONS) $< -o $(ObjDir)/$*.o ; \ $(DEPEND_MOVEFILE) -$(ObjDir)/%.o: %.c $(ObjDir)/.dir $(BUILT_SOURCES) $(PROJ_SRC_DIR)/Makefile +$(ObjDir)/%.o: %.c $(ObjDir)/.dir $(BUILT_SOURCES) $(PROJ_MAKEFILE) $(Echo) "Compiling $*.c for $(BuildMode) build" $(PIC_FLAG) $(Verb) if $(Compile.C) $(DEPEND_OPTIONS) $< -o $(ObjDir)/$*.o ; \ $(DEPEND_MOVEFILE) -$(ObjDir)/%.o: %.m $(ObjDir)/.dir $(BUILT_SOURCES) $(PROJ_SRC_DIR)/Makefile +$(ObjDir)/%.o: %.m $(ObjDir)/.dir $(BUILT_SOURCES) $(PROJ_MAKEFILE) $(Echo) "Compiling $*.m for $(BuildMode) build" $(PIC_FLAG) $(Verb) if $(Compile.C) $(DEPEND_OPTIONS) $< -o $(ObjDir)/$*.o ; \ $(DEPEND_MOVEFILE) From wdietz2 at illinois.edu Thu Sep 9 12:45:59 2010 From: wdietz2 at illinois.edu (Will Dietz) Date: Thu, 09 Sep 2010 17:45:59 -0000 Subject: [llvm-commits] [poolalloc] r113507 - /poolalloc/trunk/lib/DSA/Local.cpp Message-ID: <20100909174559.CBFDF2A6C12C@llvm.org> Author: wdietz2 Date: Thu Sep 9 12:45:59 2010 New Revision: 113507 URL: http://llvm.org/viewvc/llvm-project?rev=113507&view=rev Log: Reworded comment. No functionality changes. Modified: poolalloc/trunk/lib/DSA/Local.cpp Modified: poolalloc/trunk/lib/DSA/Local.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/Local.cpp?rev=113507&r1=113506&r2=113507&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/Local.cpp (original) +++ poolalloc/trunk/lib/DSA/Local.cpp Thu Sep 9 12:45:59 2010 @@ -903,13 +903,13 @@ } } - //NOTE: This code is identical to 'DSGraph::getDSCallSiteForCallSite', - //the reason it's duplicated is so because this calls getValueDest, - //instead of getNodeForValue. Possibly because a DS node may not exist - //at this time, in which case getNodeForValue, creates the node, unlike - // getNodeForValue. + // NOTE: This code is identical to 'DSGraph::getDSCallSiteForCallSite', + // the reason it's duplicated is because this calls getValueDest instead + // of getNodeForValue to get the DSNodes for the arguments. Since we're in + // local it's possible that we need to create a DSNode for the argument, as + // opposed to getNodeForValue which simply retrieves the existing node. - //FIXME: refactor so we don't have this duplication. + // FIXME: refactor so we don't have this duplication. //Get the FunctionType for the called function const FunctionType *CalleeFuncType = DSCallSite::FunctionTypeOfCallSite(CS); From rdivacky at freebsd.org Thu Sep 9 12:57:50 2010 From: rdivacky at freebsd.org (Roman Divacky) Date: Thu, 09 Sep 2010 17:57:50 -0000 Subject: [llvm-commits] [llvm] r113508 - in /llvm/trunk: include/llvm/MC/ELFObjectWriter.h lib/MC/ELFObjectWriter.cpp lib/Target/X86/X86AsmBackend.cpp Message-ID: <20100909175750.3D3B52A6C12C@llvm.org> Author: rdivacky Date: Thu Sep 9 12:57:50 2010 New Revision: 113508 URL: http://llvm.org/viewvc/llvm-project?rev=113508&view=rev Log: Make ELF OS ABI dependent on the OS from target triple. Modified: llvm/trunk/include/llvm/MC/ELFObjectWriter.h llvm/trunk/lib/MC/ELFObjectWriter.cpp llvm/trunk/lib/Target/X86/X86AsmBackend.cpp Modified: llvm/trunk/include/llvm/MC/ELFObjectWriter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/ELFObjectWriter.h?rev=113508&r1=113507&r2=113508&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/ELFObjectWriter.h (original) +++ llvm/trunk/include/llvm/MC/ELFObjectWriter.h Thu Sep 9 12:57:50 2010 @@ -10,6 +10,7 @@ #ifndef LLVM_MC_ELFOBJECTWRITER_H #define LLVM_MC_ELFOBJECTWRITER_H +#include "llvm/ADT/Triple.h" #include "llvm/MC/MCObjectWriter.h" #include "llvm/Support/raw_ostream.h" #include @@ -25,8 +26,8 @@ void *Impl; public: - ELFObjectWriter(raw_ostream &OS, bool Is64Bit, bool IsLittleEndian = true, - bool HasRelocationAddend = true); + ELFObjectWriter(raw_ostream &OS, bool Is64Bit, Triple::OSType OSType, + bool IsLittleEndian = true, bool HasRelocationAddend = true); virtual ~ELFObjectWriter(); Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=113508&r1=113507&r2=113508&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Thu Sep 9 12:57:50 2010 @@ -107,6 +107,8 @@ bool HasRelocationAddend; + Triple::OSType OSType; + // This holds the symbol table index of the last local symbol. unsigned LastLocalSymbolIndex; // This holds the .strtab section index. @@ -116,9 +118,10 @@ public: ELFObjectWriterImpl(ELFObjectWriter *_Writer, bool _Is64Bit, - bool _HasRelAddend) + bool _HasRelAddend, Triple::OSType _OSType) : Writer(_Writer), OS(Writer->getStream()), - Is64Bit(_Is64Bit), HasRelocationAddend(_HasRelAddend) { + Is64Bit(_Is64Bit), HasRelocationAddend(_HasRelAddend), + OSType(_OSType) { } void Write8(uint8_t Value) { Writer->Write8(Value); } @@ -270,7 +273,12 @@ Write8(Writer->isLittleEndian() ? ELF::ELFDATA2LSB : ELF::ELFDATA2MSB); Write8(ELF::EV_CURRENT); // e_ident[EI_VERSION] - Write8(ELF::ELFOSABI_LINUX); // e_ident[EI_OSABI] + // e_ident[EI_OSABI] + switch (OSType) { + case Triple::FreeBSD: Write8(ELF::ELFOSABI_FREEBSD); break; + case Triple::Linux: Write8(ELF::ELFOSABI_LINUX); break; + default: Write8(ELF::ELFOSABI_NONE); break; + } Write8(0); // e_ident[EI_ABIVERSION] WriteZeros(ELF::EI_NIDENT - ELF::EI_PAD); @@ -955,11 +963,12 @@ ELFObjectWriter::ELFObjectWriter(raw_ostream &OS, bool Is64Bit, + Triple::OSType OSType, bool IsLittleEndian, bool HasRelocationAddend) : MCObjectWriter(OS, IsLittleEndian) { - Impl = new ELFObjectWriterImpl(this, Is64Bit, HasRelocationAddend); + Impl = new ELFObjectWriterImpl(this, Is64Bit, HasRelocationAddend, OSType); } ELFObjectWriter::~ELFObjectWriter() { Modified: llvm/trunk/lib/Target/X86/X86AsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86AsmBackend.cpp?rev=113508&r1=113507&r2=113508&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86AsmBackend.cpp (original) +++ llvm/trunk/lib/Target/X86/X86AsmBackend.cpp Thu Sep 9 12:57:50 2010 @@ -186,25 +186,27 @@ namespace { class ELFX86AsmBackend : public X86AsmBackend { public: - ELFX86AsmBackend(const Target &T) - : X86AsmBackend(T) { + Triple::OSType OSType; + ELFX86AsmBackend(const Target &T, Triple::OSType _OSType) + : X86AsmBackend(T), OSType(_OSType) { HasAbsolutizedSet = true; HasScatteredSymbols = true; } bool isVirtualSection(const MCSection &Section) const { const MCSectionELF &SE = static_cast(Section); - return SE.getType() == MCSectionELF::SHT_NOBITS;; + return SE.getType() == MCSectionELF::SHT_NOBITS; } }; class ELFX86_32AsmBackend : public ELFX86AsmBackend { public: - ELFX86_32AsmBackend(const Target &T) - : ELFX86AsmBackend(T) {} + ELFX86_32AsmBackend(const Target &T, Triple::OSType OSType) + : ELFX86AsmBackend(T, OSType) {} MCObjectWriter *createObjectWriter(raw_ostream &OS) const { return new ELFObjectWriter(OS, /*Is64Bit=*/false, + OSType, /*IsLittleEndian=*/true, /*HasRelocationAddend=*/false); } @@ -212,11 +214,12 @@ class ELFX86_64AsmBackend : public ELFX86AsmBackend { public: - ELFX86_64AsmBackend(const Target &T) - : ELFX86AsmBackend(T) {} + ELFX86_64AsmBackend(const Target &T, Triple::OSType OSType) + : ELFX86AsmBackend(T, OSType) {} MCObjectWriter *createObjectWriter(raw_ostream &OS) const { return new ELFObjectWriter(OS, /*Is64Bit=*/true, + OSType, /*IsLittleEndian=*/true, /*HasRelocationAddend=*/true); } @@ -324,7 +327,7 @@ case Triple::Win32: return new WindowsX86AsmBackend(T, false); default: - return new ELFX86_32AsmBackend(T); + return new ELFX86_32AsmBackend(T, Triple(TT).getOS()); } } @@ -338,6 +341,6 @@ case Triple::Win32: return new WindowsX86AsmBackend(T, true); default: - return new ELFX86_64AsmBackend(T); + return new ELFX86_64AsmBackend(T, Triple(TT).getOS()); } } From benny.kra at googlemail.com Thu Sep 9 13:01:29 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Thu, 09 Sep 2010 18:01:29 -0000 Subject: [llvm-commits] [llvm] r113509 - /llvm/trunk/lib/MC/ELFObjectWriter.cpp Message-ID: <20100909180129.8BDCB2A6C12C@llvm.org> Author: d0k Date: Thu Sep 9 13:01:29 2010 New Revision: 113509 URL: http://llvm.org/viewvc/llvm-project?rev=113509&view=rev Log: MCELF: Write relocation fragments in the right endian. - This code is gross, but does the job for now. Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=113509&r1=113508&r2=113509&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Thu Sep 9 13:01:29 2010 @@ -745,12 +745,33 @@ for (unsigned i = 0, e = Relocs.size(); i != e; ++i) { ELFRelocationEntry entry = Relocs[e - i - 1]; - unsigned WordSize = Is64Bit ? 8 : 4; - F->getContents() += StringRef((const char *)&entry.r_offset, WordSize); - F->getContents() += StringRef((const char *)&entry.r_info, WordSize); + if (Is64Bit) { + char buf[8]; - if (HasRelocationAddend) - F->getContents() += StringRef((const char *)&entry.r_addend, WordSize); + String64(buf, entry.r_offset); + F->getContents() += StringRef(buf, 8); + + String64(buf, entry.r_info); + F->getContents() += StringRef(buf, 8); + + if (HasRelocationAddend) { + String64(buf, entry.r_addend); + F->getContents() += StringRef(buf, 8); + } + } else { + char buf[4]; + + String32(buf, entry.r_offset); + F->getContents() += StringRef(buf, 4); + + String32(buf, entry.r_info); + F->getContents() += StringRef(buf, 4); + + if (HasRelocationAddend) { + String32(buf, entry.r_addend); + F->getContents() += StringRef(buf, 4); + } + } } } From gohman at apple.com Thu Sep 9 13:04:22 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 09 Sep 2010 18:04:22 -0000 Subject: [llvm-commits] [llvm] r113511 - /llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Message-ID: <20100909180422.BF2982A6C12D@llvm.org> Author: djg Date: Thu Sep 9 13:04:22 2010 New Revision: 113511 URL: http://llvm.org/viewvc/llvm-project?rev=113511&view=rev Log: Fix this comment. Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/AliasAnalysis.h?rev=113511&r1=113510&r2=113511&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/AliasAnalysis.h (original) +++ llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Thu Sep 9 13:04:22 2010 @@ -308,8 +308,9 @@ /// written to by the first. WriteThenReadSome, - /// ReadThenWrite - The instructions are ReadThenWriteSome and the second - /// instruction writes to exactly the same memory read from by the first. + /// ReadThenWrite - The first instruction is read-only, the second + /// instruction is write-only, and the second wrotes to exactly the + /// same memory read from by the first. ReadThenWrite, /// WriteThenWrite - The instructions are WriteThenWriteSome, and the From gohman at apple.com Thu Sep 9 13:05:46 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 9 Sep 2010 11:05:46 -0700 Subject: [llvm-commits] [llvm] r113329 - in /llvm/trunk: include/llvm/Analysis/AliasAnalysis.h lib/Analysis/AliasAnalysis.cpp lib/Analysis/BasicAliasAnalysis.cpp In-Reply-To: References: <20100908013220.8342E2A6C12C@llvm.org> Message-ID: <3C355ADA-1B59-42A3-AF0C-E6259CAD2DEA@apple.com> On Sep 9, 2010, at 8:59 AM, Devang Patel wrote: > > On Sep 9, 2010, at 8:49 AM, Dan Gohman wrote: > >> >> On Sep 8, 2010, at 1:06 PM, Devang Patel wrote: >> >>> >>> On Sep 7, 2010, at 6:32 PM, Dan Gohman wrote: >>> >>>> + /// ReadThenWrite - The instructions are ReadThenWriteSome and the second >>>> + /// instruction writes to exactly the same memory read from by the first. >>>> + ReadThenWrite, >>>> + >>> >>> ReadThenWriteSome is missing. >> >> We can add it if there's a need for it. > > OK, in that case comment should not mention it now. Thanks, fixed. Dan From evan.cheng at apple.com Thu Sep 9 13:18:55 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 09 Sep 2010 18:18:55 -0000 Subject: [llvm-commits] [llvm] r113513 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h include/llvm/Target/TargetInstrItineraries.h include/llvm/Target/TargetSchedule.td lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h lib/Target/ARM/ARMInstrThumb.td lib/Target/ARM/ARMSchedule.td lib/Target/ARM/ARMScheduleV6.td lib/Target/TargetInstrInfo.cpp utils/TableGen/SubtargetEmitter.cpp utils/TableGen/SubtargetEmitter.h Message-ID: <20100909181855.B33C62A6C12C@llvm.org> Author: evancheng Date: Thu Sep 9 13:18:55 2010 New Revision: 113513 URL: http://llvm.org/viewvc/llvm-project?rev=113513&view=rev Log: For each instruction itinerary class, specify the number of micro-ops each instruction in the class would be decoded to. Or zero if the number of uOPs must be determined dynamically. This will be used to determine the cost-effectiveness of predicating a micro-coded instruction. Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h llvm/trunk/include/llvm/Target/TargetInstrItineraries.h llvm/trunk/include/llvm/Target/TargetSchedule.td llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h llvm/trunk/lib/Target/ARM/ARMInstrThumb.td llvm/trunk/lib/Target/ARM/ARMSchedule.td llvm/trunk/lib/Target/ARM/ARMScheduleV6.td llvm/trunk/lib/Target/TargetInstrInfo.cpp llvm/trunk/utils/TableGen/SubtargetEmitter.cpp llvm/trunk/utils/TableGen/SubtargetEmitter.h Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=113513&r1=113512&r2=113513&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Thu Sep 9 13:18:55 2010 @@ -591,6 +591,11 @@ MachineInstr *CmpInstr) const { return false; } + + /// getNumMicroOps - Return the number of u-operations the given machine + /// instruction will be decoded to on the target cpu. + virtual unsigned getNumMicroOps(const MachineInstr *MI, + const InstrItineraryData &ItinData) const; }; /// TargetInstrInfoImpl - This is the default implementation of Modified: llvm/trunk/include/llvm/Target/TargetInstrItineraries.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrItineraries.h?rev=113513&r1=113512&r2=113513&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetInstrItineraries.h (original) +++ llvm/trunk/include/llvm/Target/TargetInstrItineraries.h Thu Sep 9 13:18:55 2010 @@ -95,6 +95,7 @@ /// operands are read and written. /// struct InstrItinerary { + unsigned NumMicroOps; ///< # of micro-ops, 0 means it's variable unsigned FirstStage; ///< Index of first stage in itinerary unsigned LastStage; ///< Index of last + 1 stage in itinerary unsigned FirstOperandCycle; ///< Index of first operand rd/wr Modified: llvm/trunk/include/llvm/Target/TargetSchedule.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSchedule.td?rev=113513&r1=113512&r2=113513&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetSchedule.td (original) +++ llvm/trunk/include/llvm/Target/TargetSchedule.td Thu Sep 9 13:18:55 2010 @@ -66,7 +66,14 @@ // across all chip sets. Thus a new chip set can be added without modifying // instruction information. // -class InstrItinClass; +// NumMicroOps represents the number of micro-operations that each instruction +// in the class are decoded to. If the number is zero, then it means the +// instruction can decode into variable number of micro-ops and it must be +// determined dynamically. +// +class InstrItinClass { + int NumMicroOps = ops; +} def NoItinerary : InstrItinClass; //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=113513&r1=113512&r2=113513&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Thu Sep 9 13:18:55 2010 @@ -1412,3 +1412,66 @@ return false; } + +unsigned +ARMBaseInstrInfo::getNumMicroOps(const MachineInstr *MI, + const InstrItineraryData &ItinData) const { + if (ItinData.isEmpty()) + return 1; + + const TargetInstrDesc &Desc = MI->getDesc(); + unsigned Class = Desc.getSchedClass(); + unsigned UOps = ItinData.Itineratries[Class].NumMicroOps; + if (UOps) + return UOps; + + unsigned Opc = MI->getOpcode(); + switch (Opc) { + default: + llvm_unreachable("Unexpected multi-uops instruction!"); + break; + case ARM::VSTMQ: + return 2; + + // The number of uOps for load / store multiple are determined by the number + // registers. + // On Cortex-A8, each odd / even pair of register loads / stores + // (e.g. r5 + r6) can be completed on the same cycle. The minimum is + // 2. For VFP / NEON load / store multiple, the formula is + // (#reg / 2) + (#reg % 2) + 1. + // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). + case ARM::VLDMD: + case ARM::VLDMS: + case ARM::VLDMD_UPD: + case ARM::VLDMS_UPD: + case ARM::VSTMD: + case ARM::VSTMS: + case ARM::VSTMD_UPD: + case ARM::VSTMS_UPD: { + unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands(); + return (NumRegs / 2) + (NumRegs % 2) + 1; + } + case ARM::LDM_RET: + case ARM::LDM: + case ARM::LDM_UPD: + case ARM::STM: + case ARM::STM_UPD: + case ARM::tLDM: + case ARM::tLDM_UPD: + case ARM::tSTM_UPD: + case ARM::tPOP_RET: + case ARM::tPOP: + case ARM::tPUSH: + case ARM::t2LDM_RET: + case ARM::t2LDM: + case ARM::t2LDM_UPD: + case ARM::t2STM: + case ARM::t2STM_UPD: { + // FIXME: Distinquish between Cortex-A8 / Cortex-A9 and other processor + // families. + unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands(); + UOps = (NumRegs / 2) + (NumRegs % 2); + return (UOps > 2) ? UOps : 2; + } + } +} Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h?rev=113513&r1=113512&r2=113513&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Thu Sep 9 13:18:55 2010 @@ -348,6 +348,9 @@ /// that we can remove a "comparison with zero". virtual bool ConvertToSetZeroFlag(MachineInstr *Instr, MachineInstr *CmpInstr) const; + + virtual unsigned getNumMicroOps(const MachineInstr *MI, + const InstrItineraryData &ItinData) const; }; static inline Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=113513&r1=113512&r2=113513&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Thu Sep 9 13:18:55 2010 @@ -282,7 +282,8 @@ // FIXME: remove when we have a way to marking a MI with these properties. let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, hasExtraDefRegAllocReq = 1 in -def tPOP_RET : T1I<(outs), (ins pred:$p, reglist:$dsts, variable_ops), IIC_Br, +def tPOP_RET : T1I<(outs), (ins pred:$p, reglist:$dsts, variable_ops), + IIC_iLoadmBr, "pop${p}\t$dsts", []>, T1Misc<{1,1,0,?,?,?,?}>; @@ -560,12 +561,12 @@ T1Encoding<{1,1,0,0,0,?}>; // A6.2 & A8.6.189 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in -def tPOP : T1I<(outs), (ins pred:$p, reglist:$dsts, variable_ops), IIC_Br, +def tPOP : T1I<(outs), (ins pred:$p, reglist:$dsts, variable_ops), IIC_iLoadmBr, "pop${p}\t$dsts", []>, T1Misc<{1,1,0,?,?,?,?}>; let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in -def tPUSH : T1I<(outs), (ins pred:$p, reglist:$srcs, variable_ops), IIC_Br, +def tPUSH : T1I<(outs), (ins pred:$p, reglist:$srcs, variable_ops), IIC_iStorem, "push${p}\t$srcs", []>, T1Misc<{0,1,0,?,?,?,?}>; Modified: llvm/trunk/lib/Target/ARM/ARMSchedule.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSchedule.td?rev=113513&r1=113512&r2=113513&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSchedule.td (original) +++ llvm/trunk/lib/Target/ARM/ARMSchedule.td Thu Sep 9 13:18:55 2010 @@ -42,15 +42,15 @@ def IIC_iLoadiu : InstrItinClass; def IIC_iLoadru : InstrItinClass; def IIC_iLoadsiu : InstrItinClass; -def IIC_iLoadm : InstrItinClass; -def IIC_iLoadmBr : InstrItinClass; +def IIC_iLoadm : InstrItinClass<0>; // micro-coded +def IIC_iLoadmBr : InstrItinClass<0>; // micro-coded def IIC_iStorei : InstrItinClass; def IIC_iStorer : InstrItinClass; def IIC_iStoresi : InstrItinClass; def IIC_iStoreiu : InstrItinClass; def IIC_iStoreru : InstrItinClass; def IIC_iStoresiu : InstrItinClass; -def IIC_iStorem : InstrItinClass; +def IIC_iStorem : InstrItinClass<0>; // micro-coded def IIC_Br : InstrItinClass; def IIC_fpSTAT : InstrItinClass; def IIC_fpUNA32 : InstrItinClass; @@ -81,10 +81,10 @@ def IIC_fpSQRT64 : InstrItinClass; def IIC_fpLoad32 : InstrItinClass; def IIC_fpLoad64 : InstrItinClass; -def IIC_fpLoadm : InstrItinClass; +def IIC_fpLoadm : InstrItinClass<0>; // micro-coded def IIC_fpStore32 : InstrItinClass; def IIC_fpStore64 : InstrItinClass; -def IIC_fpStorem : InstrItinClass; +def IIC_fpStorem : InstrItinClass<0>; // micro-coded def IIC_VLD1 : InstrItinClass; def IIC_VLD2 : InstrItinClass; def IIC_VLD3 : InstrItinClass; Modified: llvm/trunk/lib/Target/ARM/ARMScheduleV6.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleV6.td?rev=113513&r1=113512&r2=113513&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMScheduleV6.td (original) +++ llvm/trunk/lib/Target/ARM/ARMScheduleV6.td Thu Sep 9 13:18:55 2010 @@ -86,6 +86,11 @@ // Load multiple InstrItinData]>, + // + // Load multiple plus branch + InstrItinData, + InstrStage<1, [V6_Pipe]>]>, + // Integer store pipeline // // Immediate offset Modified: llvm/trunk/lib/Target/TargetInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetInstrInfo.cpp?rev=113513&r1=113512&r2=113513&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/TargetInstrInfo.cpp Thu Sep 9 13:18:55 2010 @@ -13,6 +13,7 @@ #include "llvm/Target/TargetInstrInfo.h" #include "llvm/MC/MCAsmInfo.h" +#include "llvm/Target/TargetInstrItineraries.h" #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Support/ErrorHandling.h" using namespace llvm; @@ -47,6 +48,22 @@ TargetInstrInfo::~TargetInstrInfo() { } +unsigned +TargetInstrInfo::getNumMicroOps(const MachineInstr *MI, + const InstrItineraryData &ItinData) const { + if (ItinData.isEmpty()) + return 1; + + unsigned Class = MI->getDesc().getSchedClass(); + unsigned UOps = ItinData.Itineratries[Class].NumMicroOps; + if (UOps) + return UOps; + + // The # of u-ops is dynamically determined. The specific target should + // override this function to return the right number. + return 1; +} + /// insertNoop - Insert a noop into the instruction stream at the specified /// point. void TargetInstrInfo::insertNoop(MachineBasicBlock &MBB, Modified: llvm/trunk/utils/TableGen/SubtargetEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/SubtargetEmitter.cpp?rev=113513&r1=113512&r2=113513&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/SubtargetEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/SubtargetEmitter.cpp Thu Sep 9 13:18:55 2010 @@ -172,13 +172,10 @@ // CollectAllItinClasses - Gathers and enumerates all the itinerary classes. // Returns itinerary class count. // -unsigned SubtargetEmitter::CollectAllItinClasses(raw_ostream &OS, - std::map &ItinClassesMap) { - // Gather and sort all itinerary classes - std::vector ItinClassList = - Records.getAllDerivedDefinitions("InstrItinClass"); - std::sort(ItinClassList.begin(), ItinClassList.end(), LessRecord()); - +unsigned SubtargetEmitter:: +CollectAllItinClasses(raw_ostream &OS, + std::map &ItinClassesMap, + std::vector &ItinClassList) { // For each itinerary class unsigned N = ItinClassList.size(); for (unsigned i = 0; i < N; i++) { @@ -271,7 +268,8 @@ // void SubtargetEmitter::EmitStageAndOperandCycleData(raw_ostream &OS, unsigned NItinClasses, - std::map &ItinClassesMap, + std::map &ItinClassesMap, + std::vector &ItinClassList, std::vector > &ProcList) { // Gather processor iteraries std::vector ProcItinList = @@ -374,14 +372,16 @@ } } - // Set up itinerary as location and location + stage count - InstrItinerary Intinerary = { FindStage, FindStage + NStages, - FindOperandCycle, FindOperandCycle + NOperandCycles}; - // Locate where to inject into processor itinerary table const std::string &Name = ItinData->getValueAsDef("TheClass")->getName(); unsigned Find = ItinClassesMap[Name]; + // Set up itinerary as location and location + stage count + unsigned NumUOps = ItinClassList[Find]->getValueAsInt("NumMicroOps"); + InstrItinerary Intinerary = { NumUOps, FindStage, FindStage + NStages, + FindOperandCycle, + FindOperandCycle + NOperandCycles}; + // Inject - empty slots will be 0, 0 ItinList[Find] = Intinerary; } @@ -443,9 +443,11 @@ // Emit in the form of // { firstStage, lastStage, firstCycle, lastCycle } // index if (Intinerary.FirstStage == 0) { - OS << " { 0, 0, 0, 0 }"; + OS << " { 1, 0, 0, 0, 0 }"; } else { - OS << " { " << Intinerary.FirstStage << ", " << + OS << " { " << + Intinerary.NumMicroOps << ", " << + Intinerary.FirstStage << ", " << Intinerary.LastStage << ", " << Intinerary.FirstOperandCycle << ", " << Intinerary.LastOperandCycle << " }"; @@ -455,7 +457,7 @@ } // End processor itinerary table - OS << " { ~0U, ~0U, ~0U, ~0U } // end marker\n"; + OS << " { 1, ~0U, ~0U, ~0U, ~0U } // end marker\n"; OS << "};\n"; } } @@ -511,16 +513,22 @@ // void SubtargetEmitter::EmitData(raw_ostream &OS) { std::map ItinClassesMap; - std::vector > ProcList; + // Gather and sort all itinerary classes + std::vector ItinClassList = + Records.getAllDerivedDefinitions("InstrItinClass"); + std::sort(ItinClassList.begin(), ItinClassList.end(), LessRecord()); // Enumerate all the itinerary classes - unsigned NItinClasses = CollectAllItinClasses(OS, ItinClassesMap); + unsigned NItinClasses = CollectAllItinClasses(OS, ItinClassesMap, + ItinClassList); // Make sure the rest is worth the effort HasItineraries = NItinClasses != 1; // Ignore NoItinerary. if (HasItineraries) { + std::vector > ProcList; // Emit the stage data - EmitStageAndOperandCycleData(OS, NItinClasses, ItinClassesMap, ProcList); + EmitStageAndOperandCycleData(OS, NItinClasses, ItinClassesMap, + ItinClassList, ProcList); // Emit the processor itinerary data EmitProcessorData(OS, ProcList); // Emit the processor lookup data Modified: llvm/trunk/utils/TableGen/SubtargetEmitter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/SubtargetEmitter.h?rev=113513&r1=113512&r2=113513&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/SubtargetEmitter.h (original) +++ llvm/trunk/utils/TableGen/SubtargetEmitter.h Thu Sep 9 13:18:55 2010 @@ -33,7 +33,8 @@ void FeatureKeyValues(raw_ostream &OS); void CPUKeyValues(raw_ostream &OS); unsigned CollectAllItinClasses(raw_ostream &OS, - std::map &ItinClassesMap); + std::map &ItinClassesMap, + std::vector &ItinClassList); void FormItineraryStageString(const std::string &Names, Record *ItinData, std::string &ItinString, unsigned &NStages); @@ -41,6 +42,7 @@ unsigned &NOperandCycles); void EmitStageAndOperandCycleData(raw_ostream &OS, unsigned NItinClasses, std::map &ItinClassesMap, + std::vector &ItinClassList, std::vector > &ProcList); void EmitProcessorData(raw_ostream &OS, std::vector > &ProcList); From gohman at apple.com Thu Sep 9 13:32:40 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 09 Sep 2010 18:32:40 -0000 Subject: [llvm-commits] [llvm] r113520 - /llvm/trunk/include/llvm/Instructions.h Message-ID: <20100909183240.9D7812A6C12C@llvm.org> Author: djg Date: Thu Sep 9 13:32:40 2010 New Revision: 113520 URL: http://llvm.org/viewvc/llvm-project?rev=113520&view=rev Log: Add a getPointerOperand() helper function to VAArgInst, for consistency with LoadInst and StoreInst. Modified: llvm/trunk/include/llvm/Instructions.h Modified: llvm/trunk/include/llvm/Instructions.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=113520&r1=113519&r2=113520&view=diff ============================================================================== --- llvm/trunk/include/llvm/Instructions.h (original) +++ llvm/trunk/include/llvm/Instructions.h Thu Sep 9 13:32:40 2010 @@ -1207,6 +1207,10 @@ setName(NameStr); } + Value *getPointerOperand() { return getOperand(0); } + const Value *getPointerOperand() const { return getOperand(0); } + static unsigned getPointerOperandIndex() { return 0U; } + // Methods for support type inquiry through isa, cast, and dyn_cast: static inline bool classof(const VAArgInst *) { return true; } static inline bool classof(const Instruction *I) { From gohman at apple.com Thu Sep 9 13:37:31 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 09 Sep 2010 18:37:31 -0000 Subject: [llvm-commits] [llvm] r113521 - in /llvm/trunk: include/llvm/Analysis/AliasAnalysis.h lib/Analysis/AliasAnalysis.cpp lib/Analysis/BasicAliasAnalysis.cpp Message-ID: <20100909183731.D54BB2A6C12C@llvm.org> Author: djg Date: Thu Sep 9 13:37:31 2010 New Revision: 113521 URL: http://llvm.org/viewvc/llvm-project?rev=113521&view=rev Log: Extend the getDependence query with support for PHI translation. Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h llvm/trunk/lib/Analysis/AliasAnalysis.cpp llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/AliasAnalysis.h?rev=113521&r1=113520&r2=113521&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/AliasAnalysis.h (original) +++ llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Thu Sep 9 13:37:31 2010 @@ -340,17 +340,20 @@ /// WARNING: This is an experimental interface. DependenceResult getDependence(const Instruction *First, const Instruction *Second) { - return getDependence(First, Default, Second, Default); + return getDependence(First, 0, Default, Second, 0, Default); } /// getDependence - Determine the dependence relationship between the /// instructions. This does not include "register" dependencies; it just /// considers memory references and other side effects. This overload - /// accepts additional flags to refine the query. + /// has additional parameters to allow phi-translated addresses to be + /// specified, and additional flags to refine the query. /// WARNING: This is an experimental interface. virtual DependenceResult getDependence(const Instruction *First, + const Value *FirstPHITranslatedAddr, DependenceQueryFlags FirstFlags, const Instruction *Second, + const Value *SecondPHITranslatedAddr, DependenceQueryFlags SecondFlags); //===--------------------------------------------------------------------===// @@ -403,8 +406,10 @@ /// getDependenceViaModRefInfo - Helper function for implementing getDependence /// in implementations which already have getModRefInfo implementations. DependenceResult getDependenceViaModRefInfo(const Instruction *First, + const Value *FirstPHITranslatedAddr, DependenceQueryFlags FirstFlags, const Instruction *Second, + const Value *SecondPHITranslatedAddr, DependenceQueryFlags SecondFlags); }; Modified: llvm/trunk/lib/Analysis/AliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/AliasAnalysis.cpp?rev=113521&r1=113520&r2=113521&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/AliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/AliasAnalysis.cpp Thu Sep 9 13:37:31 2010 @@ -190,11 +190,14 @@ AliasAnalysis::DependenceResult AliasAnalysis::getDependence(const Instruction *First, + const Value *FirstPHITranslatedAddr, DependenceQueryFlags FirstFlags, const Instruction *Second, + const Value *SecondPHITranslatedAddr, DependenceQueryFlags SecondFlags) { assert(AA && "AA didn't call InitializeAliasAnalyais in its run method!"); - return AA->getDependence(First, FirstFlags, Second, SecondFlags); + return AA->getDependence(First, FirstPHITranslatedAddr, FirstFlags, + Second, SecondPHITranslatedAddr, SecondFlags); } //===----------------------------------------------------------------------===// @@ -255,17 +258,23 @@ AliasAnalysis::DependenceResult AliasAnalysis::getDependenceViaModRefInfo(const Instruction *First, + const Value *FirstPHITranslatedAddr, DependenceQueryFlags FirstFlags, const Instruction *Second, + const Value *SecondPHITranslatedAddr, DependenceQueryFlags SecondFlags) { if (const LoadInst *L = dyn_cast(First)) { // Be over-conservative with volatile for now. if (L->isVolatile()) return Unknown; + // If we don't have a phi-translated address, use the actual one. + if (!FirstPHITranslatedAddr) + FirstPHITranslatedAddr = L->getPointerOperand(); + // Forward this query to getModRefInfo. switch (getModRefInfo(Second, - L->getPointerOperand(), + FirstPHITranslatedAddr, getTypeStoreSize(L->getType()))) { case NoModRef: // Second doesn't reference First's memory, so they're independent. @@ -280,10 +289,14 @@ // If it's loading the same size from the same address, we can // give a more precise result. if (const LoadInst *SecondL = dyn_cast(Second)) { + // If we don't have a phi-translated address, use the actual one. + if (!SecondPHITranslatedAddr) + SecondPHITranslatedAddr = SecondL->getPointerOperand(); + unsigned LSize = getTypeStoreSize(L->getType()); unsigned SecondLSize = getTypeStoreSize(SecondL->getType()); - if (alias(L->getPointerOperand(), LSize, - SecondL->getPointerOperand(), SecondLSize) == + if (alias(FirstPHITranslatedAddr, LSize, + SecondPHITranslatedAddr, SecondLSize) == MustAlias) { // If the loads are the same size, it's ReadThenRead. if (LSize == SecondLSize) @@ -307,10 +320,14 @@ // If it's storing the same size to the same address, we can // give a more precise result. if (const StoreInst *SecondS = dyn_cast(Second)) { + // If we don't have a phi-translated address, use the actual one. + if (!SecondPHITranslatedAddr) + SecondPHITranslatedAddr = SecondS->getPointerOperand(); + unsigned LSize = getTypeStoreSize(L->getType()); unsigned SecondSSize = getTypeStoreSize(SecondS->getType()); - if (alias(L->getPointerOperand(), LSize, - SecondS->getPointerOperand(), SecondSSize) == + if (alias(FirstPHITranslatedAddr, LSize, + SecondPHITranslatedAddr, SecondSSize) == MustAlias) { // If the load and the store are the same size, it's ReadThenWrite. if (LSize == SecondSSize) @@ -332,9 +349,13 @@ if (S->isVolatile()) return Unknown; + // If we don't have a phi-translated address, use the actual one. + if (!FirstPHITranslatedAddr) + FirstPHITranslatedAddr = S->getPointerOperand(); + // Forward this query to getModRefInfo. switch (getModRefInfo(Second, - S->getPointerOperand(), + FirstPHITranslatedAddr, getTypeStoreSize(S->getValueOperand()->getType()))) { case NoModRef: // Second doesn't reference First's memory, so they're independent. @@ -349,10 +370,14 @@ // If it's loading the same size from the same address, we can // give a more precise result. if (const LoadInst *SecondL = dyn_cast(Second)) { + // If we don't have a phi-translated address, use the actual one. + if (!SecondPHITranslatedAddr) + SecondPHITranslatedAddr = SecondL->getPointerOperand(); + unsigned SSize = getTypeStoreSize(S->getValueOperand()->getType()); unsigned SecondLSize = getTypeStoreSize(SecondL->getType()); - if (alias(S->getPointerOperand(), SSize, - SecondL->getPointerOperand(), SecondLSize) == + if (alias(FirstPHITranslatedAddr, SSize, + SecondPHITranslatedAddr, SecondLSize) == MustAlias) { // If the store and the load are the same size, it's WriteThenRead. if (SSize == SecondLSize) @@ -376,10 +401,14 @@ // If it's storing the same size to the same address, we can // give a more precise result. if (const StoreInst *SecondS = dyn_cast(Second)) { + // If we don't have a phi-translated address, use the actual one. + if (!SecondPHITranslatedAddr) + SecondPHITranslatedAddr = SecondS->getPointerOperand(); + unsigned SSize = getTypeStoreSize(S->getValueOperand()->getType()); unsigned SecondSSize = getTypeStoreSize(SecondS->getType()); - if (alias(S->getPointerOperand(), SSize, - SecondS->getPointerOperand(), SecondSSize) == + if (alias(FirstPHITranslatedAddr, SSize, + SecondPHITranslatedAddr, SecondSSize) == MustAlias) { // If the stores are the same size, it's WriteThenWrite. if (SSize == SecondSSize) @@ -401,12 +430,20 @@ } } else if (const VAArgInst *V = dyn_cast(First)) { + // If we don't have a phi-translated address, use the actual one. + if (!FirstPHITranslatedAddr) + FirstPHITranslatedAddr = V->getPointerOperand(); + // Forward this query to getModRefInfo. - if (getModRefInfo(Second, V->getOperand(0), UnknownSize) == NoModRef) + if (getModRefInfo(Second, FirstPHITranslatedAddr, UnknownSize) == NoModRef) // Second doesn't reference First's memory, so they're independent. return Independent; } else if (ImmutableCallSite FirstCS = cast(First)) { + assert(!FirstPHITranslatedAddr && + !SecondPHITranslatedAddr && + "PHI translation with calls not supported yet!"); + // If both instructions are calls/invokes we can use the two-callsite // form of getModRefInfo. if (ImmutableCallSite SecondCS = cast(Second)) Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=113521&r1=113520&r2=113521&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Thu Sep 9 13:37:31 2010 @@ -172,8 +172,10 @@ } virtual DependenceResult getDependence(const Instruction *First, + const Value *FirstPHITranslatedAddr, DependenceQueryFlags FirstFlags, const Instruction *Second, + const Value *SecondPHITranslatedAddr, DependenceQueryFlags SecondFlags) { return Unknown; } @@ -531,8 +533,10 @@ virtual ModRefBehavior getModRefBehavior(const Function *F); virtual DependenceResult getDependence(const Instruction *First, + const Value *FirstPHITranslatedAddr, DependenceQueryFlags FirstFlags, const Instruction *Second, + const Value *SecondPHITranslatedAddr, DependenceQueryFlags SecondFlags); /// getAdjustedAnalysisPointer - This method is used when a pass implements @@ -748,11 +752,14 @@ AliasAnalysis::DependenceResult BasicAliasAnalysis::getDependence(const Instruction *First, + const Value *FirstPHITranslatedAddr, DependenceQueryFlags FirstFlags, const Instruction *Second, + const Value *SecondPHITranslatedAddr, DependenceQueryFlags SecondFlags) { // We don't have anything special to say yet. - return getDependenceViaModRefInfo(First, FirstFlags, Second, SecondFlags); + return getDependenceViaModRefInfo(First, FirstPHITranslatedAddr, FirstFlags, + Second, SecondPHITranslatedAddr, SecondFlags); } /// aliasGEP - Provide a bunch of ad-hoc rules to disambiguate a GEP instruction From bruno.cardoso at gmail.com Thu Sep 9 13:48:34 2010 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Thu, 09 Sep 2010 18:48:34 -0000 Subject: [llvm-commits] [llvm] r113522 - in /llvm/trunk: lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/vec_shuffle-37.ll Message-ID: <20100909184835.16EBC2A6C12C@llvm.org> Author: bruno Date: Thu Sep 9 13:48:34 2010 New Revision: 113522 URL: http://llvm.org/viewvc/llvm-project?rev=113522&view=rev Log: Add one more pattern to fallback movddup Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/test/CodeGen/X86/vec_shuffle-37.ll Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=113522&r1=113521&r2=113522&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Sep 9 13:48:34 2010 @@ -5688,6 +5688,8 @@ (MOVLHPSrr VR128:$src, VR128:$src)>; def : Pat<(v4f32 (X86Movddup VR128:$src)), (MOVLHPSrr VR128:$src, VR128:$src)>; +def : Pat<(v2f64 (X86Movddup VR128:$src)), + (UNPCKLPDrr VR128:$src, VR128:$src)>; // Shuffle with MOVLHPD def : Pat<(v2f64 (X86Movlhpd VR128:$src1, Modified: llvm/trunk/test/CodeGen/X86/vec_shuffle-37.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_shuffle-37.ll?rev=113522&r1=113521&r2=113522&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/vec_shuffle-37.ll (original) +++ llvm/trunk/test/CodeGen/X86/vec_shuffle-37.ll Thu Sep 9 13:48:34 2010 @@ -1,4 +1,5 @@ ; RUN: llc < %s -march=x86-64 | FileCheck %s +; RUN: llc -O0 < %s -march=x86 -mcpu=core2 | FileCheck %s --check-prefix=CHECK_O0 define <4 x i32> @t00(<4 x i32>* %a0) nounwind ssp { entry: @@ -12,3 +13,12 @@ ret <4 x i32> %2 } +define void @t01(double* %a0) nounwind ssp { +entry: +; CHECK_O0: movsd (%eax), %xmm0 +; CHECK_O0: unpcklpd %xmm0, %xmm0 + %tmp93 = load double* %a0, align 8 + %vecinit94 = insertelement <2 x double> undef, double %tmp93, i32 1 + store <2 x double> %vecinit94, <2 x double>* undef + ret void +} From echristo at apple.com Thu Sep 9 13:54:59 2010 From: echristo at apple.com (Eric Christopher) Date: Thu, 09 Sep 2010 18:54:59 -0000 Subject: [llvm-commits] [llvm] r113523 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20100909185459.3C1A62A6C12C@llvm.org> Author: echristo Date: Thu Sep 9 13:54:59 2010 New Revision: 113523 URL: http://llvm.org/viewvc/llvm-project?rev=113523&view=rev Log: Basic FP->Int, Int->FP conversions. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=113523&r1=113522&r2=113523&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Thu Sep 9 13:54:59 2010 @@ -116,6 +116,8 @@ virtual bool ARMSelectCmp(const Instruction *I); virtual bool ARMSelectFPExt(const Instruction *I); virtual bool ARMSelectBinaryOp(const Instruction *I, unsigned ISDOpcode); + virtual bool ARMSelectSIToFP(const Instruction *I); + virtual bool ARMSelectFPToSI(const Instruction *I); // Utility routines. private: @@ -741,6 +743,55 @@ return true; } +bool ARMFastISel::ARMSelectSIToFP(const Instruction *I) { + // Make sure we have VFP. + if (!Subtarget->hasVFP2()) return false; + + EVT VT; + const Type *Ty = I->getType(); + if (!isTypeLegal(Ty, VT)) + return false; + + unsigned Op = getRegForValue(I->getOperand(0)); + if (Op == 0) return false; + + unsigned Opc; + if (Ty->isFloatTy()) Opc = ARM::VSITOS; + else if (Ty->isDoubleTy()) Opc = ARM::VSITOD; + else return 0; + + unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); + AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), + ResultReg) + .addReg(Op)); + return true; +} + +bool ARMFastISel::ARMSelectFPToSI(const Instruction *I) { + // Make sure we have VFP. + if (!Subtarget->hasVFP2()) return false; + + EVT VT; + const Type *RetTy = I->getType(); + if (!isTypeLegal(RetTy, VT)) + return false; + + unsigned Op = getRegForValue(I->getOperand(0)); + if (Op == 0) return false; + + unsigned Opc; + const Type *OpTy = I->getOperand(0)->getType(); + if (OpTy->isFloatTy()) Opc = ARM::VTOSIZS; + else if (OpTy->isDoubleTy()) Opc = ARM::VTOSIZD; + else return 0; + + unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); + AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), + ResultReg) + .addReg(Op)); + return true; +} + bool ARMFastISel::ARMSelectBinaryOp(const Instruction *I, unsigned ISDOpcode) { EVT VT = TLI.getValueType(I->getType(), true); @@ -798,6 +849,10 @@ return ARMSelectCmp(I); case Instruction::FPExt: return ARMSelectFPExt(I); + case Instruction::SIToFP: + return ARMSelectSIToFP(I); + case Instruction::FPToSI: + return ARMSelectFPToSI(I); case Instruction::FAdd: return ARMSelectBinaryOp(I, ISD::FADD); case Instruction::FSub: From dgregor at apple.com Thu Sep 9 14:02:14 2010 From: dgregor at apple.com (Douglas Gregor) Date: Thu, 9 Sep 2010 12:02:14 -0700 Subject: [llvm-commits] [LLVMdev] [PATCH][CMake] Removing LLVMLibDeps.cmake and exporting libraries for CMake clients. In-Reply-To: References: Message-ID: <0731F7C5-7F24-4FCE-BDB4-F8199FD74C4C@apple.com> On Sep 8, 2010, at 5:39 PM, Michael Spencer wrote: > While implementing the object file library I ran into some weird > linking issues. It turned out that you have to manually specify extra > library dependencies in LLVMLibDeps.cmake, along with what you already > specify in the CMakeLists.txt file for the component. > > The attached patches remove this requirement, and add real CMake > package export capabilities. A CMake user wishing to use LLVM can now > use something similar to this: > > cmake_minimum_required(VERSION 2.8) > > find_package(LLVM REQUIRED) > add_definitions(${LLVM_CXXFLAGS}) > add_executable(llvm-external-test llvm-external-test.cpp) > target_link_libraries(llvm-external-test ${LLVM_SYSTEM_LIBS} > ${LLVM_JIT_LIBS} ${LLVM_NATIVECODEGEN_LIBS}) > > llvm+clang compile with these changes on both Linux and MSVS. > Currently both patches must be applied at the same time. I can > refactor them into a 3 step process if needed. > > Does this break anything for anyone? I think this is great, and I'd like to see it go in, but I can't test it at the moment because, unfortunately, we collided: I just updated a bunch of CMake dependencies in Clang, so your patch doesn't apply. Can you regenerate and post again? - Doug From resistor at mac.com Thu Sep 9 14:07:31 2010 From: resistor at mac.com (Owen Anderson) Date: Thu, 09 Sep 2010 19:07:31 -0000 Subject: [llvm-commits] [llvm] r113525 - /llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp Message-ID: <20100909190731.BABE82A6C12C@llvm.org> Author: resistor Date: Thu Sep 9 14:07:31 2010 New Revision: 113525 URL: http://llvm.org/viewvc/llvm-project?rev=113525&view=rev Log: Use code-size reduction metrics to estimate the amount of savings we'll get when we unroll a loop. Next step is to recalculate the threshold values given this new heuristic. Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp?rev=113525&r1=113524&r2=113525&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp Thu Sep 9 14:07:31 2010 @@ -90,7 +90,30 @@ I != E; ++I) Metrics.analyzeBasicBlock(*I); NumCalls = Metrics.NumCalls; - return Metrics.NumInsts; + + unsigned LoopSize = Metrics.NumInsts; + + // If we can identify the induction variable, we know that it will become + // constant when we unroll the loop, so factor that into our loop size + // estimate. + // FIXME: We have to divide by InlineConstants::InstrCost because the + // measure returned by CountCodeReductionForConstant is not an instruction + // count, but rather a weight as defined by InlineConstants. It would + // probably be a good idea to standardize on a single weighting scheme by + // pushing more of the logic for weighting into CodeMetrics. + if (PHINode *IndVar = L->getCanonicalInductionVariable()) { + unsigned SizeDecrease = Metrics.CountCodeReductionForConstant(IndVar); + // NOTE: Because SizeDecrease is a fuzzy estimate, we don't want to allow + // it to totally negate the cost of unrolling a loop. + SizeDecrease = SizeDecrease > LoopSize / 2 ? LoopSize : SizeDecrease; + } + + // Don't allow an estimate of size zero. This would allows unrolling of loops + // with huge iteration counts, which is a compile time problem even if it's + // not a problem for code quality. + if (LoopSize == 0) LoopSize = 1; + + return LoopSize; } bool LoopUnroll::runOnLoop(Loop *L, LPPassManager &LPM) { From resistor at mac.com Thu Sep 9 14:08:59 2010 From: resistor at mac.com (Owen Anderson) Date: Thu, 09 Sep 2010 19:08:59 -0000 Subject: [llvm-commits] [llvm] r113526 - /llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp Message-ID: <20100909190859.B3CEE2A6C12C@llvm.org> Author: resistor Date: Thu Sep 9 14:08:59 2010 New Revision: 113526 URL: http://llvm.org/viewvc/llvm-project?rev=113526&view=rev Log: Fix typo in code to cap the loop code size reduction calculation. Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp?rev=113526&r1=113525&r2=113526&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp Thu Sep 9 14:08:59 2010 @@ -27,7 +27,7 @@ using namespace llvm; static cl::opt -UnrollThreshold("unroll-threshold", cl::init(200), cl::Hidden, +UnrollThreshold("unroll-threshold", cl::init(0), cl::Hidden, cl::desc("The cut-off point for automatic loop unrolling")); static cl::opt @@ -105,7 +105,7 @@ unsigned SizeDecrease = Metrics.CountCodeReductionForConstant(IndVar); // NOTE: Because SizeDecrease is a fuzzy estimate, we don't want to allow // it to totally negate the cost of unrolling a loop. - SizeDecrease = SizeDecrease > LoopSize / 2 ? LoopSize : SizeDecrease; + SizeDecrease = SizeDecrease > LoopSize / 2 ? LoopSize / 2 : SizeDecrease; } // Don't allow an estimate of size zero. This would allows unrolling of loops From resistor at mac.com Thu Sep 9 14:11:57 2010 From: resistor at mac.com (Owen Anderson) Date: Thu, 09 Sep 2010 19:11:57 -0000 Subject: [llvm-commits] [llvm] r113527 - /llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp Message-ID: <20100909191157.522D52A6C12C@llvm.org> Author: resistor Date: Thu Sep 9 14:11:57 2010 New Revision: 113527 URL: http://llvm.org/viewvc/llvm-project?rev=113527&view=rev Log: r113526 introduced an unintended change to the loop unrolling threshold. Revert it. Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp?rev=113527&r1=113526&r2=113527&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp Thu Sep 9 14:11:57 2010 @@ -27,7 +27,7 @@ using namespace llvm; static cl::opt -UnrollThreshold("unroll-threshold", cl::init(0), cl::Hidden, +UnrollThreshold("unroll-threshold", cl::init(200), cl::Hidden, cl::desc("The cut-off point for automatic loop unrolling")); static cl::opt From ofv at wanadoo.es Thu Sep 9 14:33:40 2010 From: ofv at wanadoo.es (=?utf-8?Q?=C3=93scar_Fuentes?=) Date: Thu, 09 Sep 2010 21:33:40 +0200 Subject: [llvm-commits] [LLVMdev] [PATCH][CMake] Removing LLVMLibDeps.cmake and exporting libraries for CMake clients. References: <0731F7C5-7F24-4FCE-BDB4-F8199FD74C4C@apple.com> Message-ID: <87bp86emp7.fsf@telefonica.net> Douglas Gregor writes: > I think this is great, and I'd like to see it go in, Do you think it is great to manually maintain library dependencies on 70+ CMakeLists.txt files? [snip] From resistor at mac.com Thu Sep 9 15:02:23 2010 From: resistor at mac.com (Owen Anderson) Date: Thu, 09 Sep 2010 20:02:23 -0000 Subject: [llvm-commits] [llvm] r113528 - in /llvm/trunk: lib/Transforms/Scalar/LoopUnrollPass.cpp test/Transforms/LoopUnroll/call.ll Message-ID: <20100909200223.85E822A6C12C@llvm.org> Author: resistor Date: Thu Sep 9 15:02:23 2010 New Revision: 113528 URL: http://llvm.org/viewvc/llvm-project?rev=113528&view=rev Log: Revert r113439, which relaxed the requirement that loops containing calls cannot be unrolled. After some discussion, there seems to be a better way to achieve the same effect. Removed: llvm/trunk/test/Transforms/LoopUnroll/call.ll Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp?rev=113528&r1=113527&r2=113528&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp Thu Sep 9 15:02:23 2010 @@ -155,10 +155,8 @@ unsigned LoopSize = ApproximateLoopSize(L, NumCalls); DEBUG(dbgs() << " Loop Size = " << LoopSize << "\n"); if (NumCalls != 0) { - // Even for a loop that contains calls, it can still be profitable to - // unroll if the loop is really, REALLY small. - DEBUG(dbgs() <<" Using lower threshold for loop with function calls.\n"); - CurrentThreshold = OptSizeUnrollThreshold; + DEBUG(dbgs() << " Not unrolling loop with function calls.\n"); + return false; } uint64_t Size = (uint64_t)LoopSize*Count; if (TripCount != 1 && Size > CurrentThreshold) { Removed: llvm/trunk/test/Transforms/LoopUnroll/call.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopUnroll/call.ll?rev=113527&view=auto ============================================================================== --- llvm/trunk/test/Transforms/LoopUnroll/call.ll (original) +++ llvm/trunk/test/Transforms/LoopUnroll/call.ll (removed) @@ -1,51 +0,0 @@ -; RUN: opt < %s -S -loop-unroll | FileCheck %s - - at id = internal global i32 0 - at val = internal global [4 x i32] zeroinitializer, align 16 - -; CHECK: @test -define i32 @test(i32 %k) nounwind ssp { -; CHECK-NOT: call i32 @test(i32 %t.06) -; CHECK: call i32 @test(i32 0) -; CHECK-NOT: call i32 @test(i32 %t.06) -; CHECK: call i32 @test(i32 1) -; CHECK-NOT: call i32 @test(i32 %t.06) -; CHECK: call i32 @test(i32 2) -; CHECK-NOT: call i32 @test(i32 %t.06) -; CHECK: call i32 @test(i32 3) -; CHECK-NOT: call i32 @test(i32 %t.06) - -bb.nph: - %0 = load i32* @id, align 4 - %1 = add nsw i32 %0, 1 - store i32 %1, i32* @id, align 4 - %2 = sext i32 %k to i64 - %3 = getelementptr inbounds [4 x i32]* @val, i64 0, i64 %2 - store i32 %1, i32* %3, align 4 - br label %bb - -bb: ; preds = %bb2, %bb.nph - %indvar = phi i64 [ 0, %bb.nph ], [ %indvar.next, %bb2 ] - %scevgep = getelementptr [4 x i32]* @val, i64 0, i64 %indvar - %4 = load i32* %scevgep, align 4 - %5 = icmp eq i32 %4, 0 - br i1 %5, label %bb1, label %bb2 - -bb1: ; preds = %bb - %t.06 = trunc i64 %indvar to i32 - %6 = tail call i32 @test(i32 %t.06) nounwind - br label %bb2 - -bb2: ; preds = %bb1, %bb - %indvar.next = add i64 %indvar, 1 - %exitcond = icmp eq i64 %indvar.next, 4 - br i1 %exitcond, label %bb4, label %bb - -bb4: ; preds = %bb2 - %.pre = load i32* @id, align 4 - %7 = add nsw i32 %.pre, -1 - store i32 %7, i32* @id, align 4 - store i32 0, i32* %3, align 4 - ret i32 undef -; CHECK: } -} From espindola at google.com Thu Sep 9 15:18:11 2010 From: espindola at google.com (Rafael Espindola) Date: Thu, 9 Sep 2010 16:18:11 -0400 Subject: [llvm-commits] [patch][mc] Add support for .uleb Message-ID: My first ELF MC patch :-) Cheers, -- Rafael ?vila de Esp?ndola -------------- next part -------------- A non-text attachment was scrubbed... Name: uleb128.patch Type: text/x-patch Size: 2552 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100909/05eb790d/attachment.bin From echristo at apple.com Thu Sep 9 15:26:31 2010 From: echristo at apple.com (Eric Christopher) Date: Thu, 09 Sep 2010 20:26:31 -0000 Subject: [llvm-commits] [llvm] r113533 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20100909202631.5EF312A6C12C@llvm.org> Author: echristo Date: Thu Sep 9 15:26:31 2010 New Revision: 113533 URL: http://llvm.org/viewvc/llvm-project?rev=113533&view=rev Log: Add FPTrunc, fix some bugs where I forgot to update the value map. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=113533&r1=113532&r2=113533&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Thu Sep 9 15:26:31 2010 @@ -115,6 +115,7 @@ virtual bool ARMSelectBranch(const Instruction *I); virtual bool ARMSelectCmp(const Instruction *I); virtual bool ARMSelectFPExt(const Instruction *I); + virtual bool ARMSelectFPTrunc(const Instruction *I); virtual bool ARMSelectBinaryOp(const Instruction *I, unsigned ISDOpcode); virtual bool ARMSelectSIToFP(const Instruction *I); virtual bool ARMSelectFPToSI(const Instruction *I); @@ -545,7 +546,6 @@ AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg) .addReg(Reg).addReg(0).addImm(Offset)); - return true; } @@ -630,7 +630,6 @@ if (!ARMEmitStore(VT, SrcReg, Reg, Offset /* 0 */)) return false; return false; - } bool ARMFastISel::ARMSelectLoad(const Instruction *I) { @@ -720,6 +719,8 @@ if (isFloat) AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::FMSTAT))); + + // TODO: How to update the value map when there's no result reg? return true; } @@ -737,6 +738,26 @@ unsigned Result = createResultReg(ARM::DPRRegisterClass); AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, + TII.get(ARM::VCVTSD), Result) + .addReg(Op)); + UpdateValueMap(I, Result); + return true; +} + +bool ARMFastISel::ARMSelectFPTrunc(const Instruction *I) { + // Make sure we have VFP and that we're truncating double to float. + if (!Subtarget->hasVFP2()) return false; + + Value *V = I->getOperand(0); + if (!I->getType()->isFloatTy() || + !V->getType()->isDoubleTy()) return false; + + unsigned Op = getRegForValue(V); + if (Op == 0) return false; + + unsigned Result = createResultReg(ARM::SPRRegisterClass); + + AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::VCVTDS), Result) .addReg(Op)); UpdateValueMap(I, Result); @@ -764,6 +785,7 @@ AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg) .addReg(Op)); + UpdateValueMap(I, ResultReg); return true; } @@ -789,6 +811,7 @@ AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg) .addReg(Op)); + UpdateValueMap(I, ResultReg); return true; } @@ -829,6 +852,7 @@ AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg) .addReg(Op1).addReg(Op2)); + UpdateValueMap(I, ResultReg); return true; } @@ -849,6 +873,8 @@ return ARMSelectCmp(I); case Instruction::FPExt: return ARMSelectFPExt(I); + case Instruction::FPTrunc: + return ARMSelectFPTrunc(I); case Instruction::SIToFP: return ARMSelectSIToFP(I); case Instruction::FPToSI: From resistor at mac.com Thu Sep 9 15:32:23 2010 From: resistor at mac.com (Owen Anderson) Date: Thu, 09 Sep 2010 20:32:23 -0000 Subject: [llvm-commits] [llvm] r113535 - in /llvm/trunk: include/llvm/Analysis/CodeMetrics.h lib/Analysis/InlineCost.cpp lib/Transforms/Scalar/LoopUnrollPass.cpp Message-ID: <20100909203223.E16D52A6C12C@llvm.org> Author: resistor Date: Thu Sep 9 15:32:23 2010 New Revision: 113535 URL: http://llvm.org/viewvc/llvm-project?rev=113535&view=rev Log: What the loop unroller cares about, rather than just not unrolling loops with calls, is not unrolling loops that contain calls that would be better off getting inlined. This mostly comes up when an interleaved devirtualization pass has devirtualized a call which the inliner will inline on a future pass. Thus, rather than blocking all loops containing calls, add a metric for "inline candidate calls" and block loops containing those instead. Modified: llvm/trunk/include/llvm/Analysis/CodeMetrics.h llvm/trunk/lib/Analysis/InlineCost.cpp llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp Modified: llvm/trunk/include/llvm/Analysis/CodeMetrics.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/CodeMetrics.h?rev=113535&r1=113534&r2=113535&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/CodeMetrics.h (original) +++ llvm/trunk/include/llvm/Analysis/CodeMetrics.h Thu Sep 9 15:32:23 2010 @@ -45,6 +45,11 @@ /// NumCalls - Keep track of the number of calls to 'big' functions. unsigned NumCalls; + + /// NumInlineCandidates - Keep track of the number of calls to internal + /// functions with only a single caller. These are likely targets for + /// future inlining, likely exposed by interleaved devirtualization. + unsigned NumInlineCandidates; /// NumVectorInsts - Keep track of how many instructions produce vector /// values. The inliner is being more aggressive with inlining vector @@ -56,7 +61,8 @@ CodeMetrics() : callsSetJmp(false), isRecursive(false), containsIndirectBr(false), usesDynamicAlloca(false), - NumInsts(0), NumBlocks(0), NumCalls(0), NumVectorInsts(0), + NumInsts(0), NumBlocks(0), NumCalls(0), + NumInlineCandidates(0), NumVectorInsts(0), NumRets(0) {} /// analyzeBasicBlock - Add information about the specified basic block Modified: llvm/trunk/lib/Analysis/InlineCost.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InlineCost.cpp?rev=113535&r1=113534&r2=113535&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/InlineCost.cpp (original) +++ llvm/trunk/lib/Analysis/InlineCost.cpp Thu Sep 9 15:32:23 2010 @@ -70,6 +70,12 @@ // variables as volatile if they are live across a setjmp call, and they // probably won't do this in callers. if (const Function *F = CS.getCalledFunction()) { + // If a function is both internal and has a single use, then it is + // extremely likely to get inlined in the future (it was probably + // exposed by an interleaved devirtualization pass). + if (F->hasInternalLinkage() && F->hasOneUse()) + ++NumInlineCandidates; + if (F->isDeclaration() && (F->getName() == "setjmp" || F->getName() == "_setjmp")) callsSetJmp = true; Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp?rev=113535&r1=113534&r2=113535&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp Thu Sep 9 15:32:23 2010 @@ -89,7 +89,7 @@ for (Loop::block_iterator I = L->block_begin(), E = L->block_end(); I != E; ++I) Metrics.analyzeBasicBlock(*I); - NumCalls = Metrics.NumCalls; + NumCalls = Metrics.NumInlineCandidates; unsigned LoopSize = Metrics.NumInsts; @@ -151,11 +151,11 @@ // Enforce the threshold. if (CurrentThreshold != NoThreshold) { - unsigned NumCalls; - unsigned LoopSize = ApproximateLoopSize(L, NumCalls); + unsigned NumInlineCandidates; + unsigned LoopSize = ApproximateLoopSize(L, NumInlineCandidates); DEBUG(dbgs() << " Loop Size = " << LoopSize << "\n"); - if (NumCalls != 0) { - DEBUG(dbgs() << " Not unrolling loop with function calls.\n"); + if (NumInlineCandidates != 0) { + DEBUG(dbgs() << " Not unrolling loop with inlinable calls.\n"); return false; } uint64_t Size = (uint64_t)LoopSize*Count; From echristo at apple.com Thu Sep 9 15:36:19 2010 From: echristo at apple.com (Eric Christopher) Date: Thu, 09 Sep 2010 20:36:19 -0000 Subject: [llvm-commits] [llvm] r113536 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20100909203619.543022A6C12C@llvm.org> Author: echristo Date: Thu Sep 9 15:36:19 2010 New Revision: 113536 URL: http://llvm.org/viewvc/llvm-project?rev=113536&view=rev Log: "Strike that, reverse it." -- Mr. Wonka. Truncate when truncating, extend when extending. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=113536&r1=113535&r2=113536&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Thu Sep 9 15:36:19 2010 @@ -738,7 +738,7 @@ unsigned Result = createResultReg(ARM::DPRRegisterClass); AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, - TII.get(ARM::VCVTSD), Result) + TII.get(ARM::VCVTDS), Result) .addReg(Op)); UpdateValueMap(I, Result); return true; @@ -758,7 +758,7 @@ unsigned Result = createResultReg(ARM::SPRRegisterClass); AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, - TII.get(ARM::VCVTDS), Result) + TII.get(ARM::VCVTSD), Result) .addReg(Op)); UpdateValueMap(I, Result); return true; From echristo at apple.com Thu Sep 9 15:49:25 2010 From: echristo at apple.com (Eric Christopher) Date: Thu, 09 Sep 2010 20:49:25 -0000 Subject: [llvm-commits] [llvm] r113537 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20100909204925.63A552A6C12C@llvm.org> Author: echristo Date: Thu Sep 9 15:49:25 2010 New Revision: 113537 URL: http://llvm.org/viewvc/llvm-project?rev=113537&view=rev Log: New "move to fp reg" routine. Use it. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=113537&r1=113536&r2=113537&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Thu Sep 9 15:49:25 2010 @@ -131,6 +131,7 @@ bool ARMComputeRegOffset(const Value *Obj, unsigned &Reg, int &Offset); unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT); unsigned ARMMaterializeInt(const Constant *C); + unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg); bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR); const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB); @@ -330,6 +331,16 @@ return ResultReg; } +unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) { + // If we have a floating point constant we expect it in a floating point + // register. + unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); + AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, + TII.get(ARM::VMOVRS), MoveReg) + .addReg(SrcReg)); + return MoveReg; +} + // For double width floating point we need to materialize two constants // (the high and the low) into integer registers then use a move to get // the combined constant into an FP reg. @@ -356,11 +367,7 @@ // If we have a floating point constant we expect it in a floating point // register. - unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); - AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, - TII.get(ARM::VMOVRS), MoveReg) - .addReg(DestReg)); - return MoveReg; + return ARMMoveToFPReg(VT, DestReg); } unsigned ARMFastISel::ARMMaterializeInt(const Constant *C) { From clattner at apple.com Thu Sep 9 15:51:27 2010 From: clattner at apple.com (Chris Lattner) Date: Thu, 9 Sep 2010 13:51:27 -0700 Subject: [llvm-commits] [patch][mc] Add support for .uleb In-Reply-To: References: Message-ID: <9279A406-42FB-4AA3-A60C-B0A31078DDBE@apple.com> On Sep 9, 2010, at 1:18 PM, Rafael Espindola wrote: > My first ELF MC patch :-) Awesome! One major comment: please add this to generic code. The darwin assembler also supports this directive, we just never got around to implementing it. We should also add a "emit uleb/sleb" value in MCStreamer, because these directives don't require an immediate, it can be a symbolic value (like a label difference). -Chris From gohman at apple.com Thu Sep 9 15:53:58 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 09 Sep 2010 20:53:58 -0000 Subject: [llvm-commits] [llvm] r113538 - /llvm/trunk/lib/VMCore/AsmWriter.cpp Message-ID: <20100909205358.D04A12A6C12C@llvm.org> Author: djg Date: Thu Sep 9 15:53:58 2010 New Revision: 113538 URL: http://llvm.org/viewvc/llvm-project?rev=113538&view=rev Log: Print invalid metadata references as , for consistency with regular value references. Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=113538&r1=113537&r2=113538&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/AsmWriter.cpp (original) +++ llvm/trunk/lib/VMCore/AsmWriter.cpp Thu Sep 9 15:53:58 2010 @@ -1165,7 +1165,11 @@ else Machine = new SlotTracker(Context); } - Out << '!' << Machine->getMetadataSlot(N); + int Slot = Machine->getMetadataSlot(N); + if (Slot == -1) + Out << ""; + else + Out << '!' << Slot; return; } @@ -1395,7 +1399,11 @@ Out << "!" << NMD->getName() << " = !{"; for (unsigned i = 0, e = NMD->getNumOperands(); i != e; ++i) { if (i) Out << ", "; - Out << '!' << Machine.getMetadataSlot(NMD->getOperand(i)); + int Slot = Machine.getMetadataSlot(NMD->getOperand(i)); + if (Slot == -1) + Out << ""; + else + Out << '!' << Slot; } Out << "}\n"; } From gohman at apple.com Thu Sep 9 15:54:24 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 09 Sep 2010 20:54:24 -0000 Subject: [llvm-commits] [llvm] r113539 - /llvm/trunk/lib/VMCore/AsmWriter.cpp Message-ID: <20100909205424.509FC2A6C12C@llvm.org> Author: djg Date: Thu Sep 9 15:54:24 2010 New Revision: 113539 URL: http://llvm.org/viewvc/llvm-project?rev=113539&view=rev Log: MDNodes are not Constants. Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=113539&r1=113538&r2=113539&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/AsmWriter.cpp (original) +++ llvm/trunk/lib/VMCore/AsmWriter.cpp Thu Sep 9 15:54:24 2010 @@ -1057,11 +1057,6 @@ return; } - if (const MDNode *Node = dyn_cast(CV)) { - Out << "!" << Machine->getMetadataSlot(Node); - return; - } - if (const ConstantExpr *CE = dyn_cast(CV)) { Out << CE->getOpcodeName(); WriteOptimizationInfo(Out, CE); From espindola at google.com Thu Sep 9 16:34:52 2010 From: espindola at google.com (Rafael Espindola) Date: Thu, 9 Sep 2010 17:34:52 -0400 Subject: [llvm-commits] [llvm-gcc][arm][patch] Lower function signatures a bit more In-Reply-To: <386B2A85-DD45-4217-BE7A-FAE01B59A23B@apple.com> References: <386B2A85-DD45-4217-BE7A-FAE01B59A23B@apple.com> Message-ID: > I haven't reviewed the patch, but in principle this sounds like a great idea! > > What IR does: > ?double foo(double X, double Y) { return X+Y; } > > get lowered into, and what ARM code ends up generated? With the patch the generated IL is ---------------------------------------------------------------------- define double @foo(i32 %X.0, i32 %X.1, i32 %Y.0, i32 %Y.1) nounwind readnone optsize { entry: %tmp17 = zext i32 %X.0 to i64 %tmp12 = zext i32 %X.1 to i64 %tmp13 = shl i64 %tmp12, 32 %ins15 = or i64 %tmp13, %tmp17 %tmp6 = zext i32 %Y.0 to i64 %tmp3 = zext i32 %Y.1 to i64 %tmp4 = shl i64 %tmp3, 32 %ins = or i64 %tmp4, %tmp6 %tmp10 = bitcast i64 %ins15 to double %tmp2 = bitcast i64 %ins to double %0 = fadd double %tmp10, %tmp2 ret double %0 } --------------------------------------------------------------------- and the asm is ---------------------------------------------------------------- foo: vmov d0, r2, r3 vmov d1, r0, r1 vadd.f64 d0, d1, d0 vmov r0, r1, d0 bx lr ---------------------------------------------------------------- or with -mfloat-abi=soft ------------------------------------------------------------- foo: stmdb sp!, {r11, lr} bl __adddf3 ldmia sp!, {r11, pc} ------------------------------------------------------------- Currently we get a more compact but less explicit IL: ---------------------------------------- define double @foo(double %X, double %Y) nounwind readnone optsize { entry: %0 = fadd double %X, %Y ret double %0 } ---------------------------------------- And exactly the same assembly. > -Chris Cheers, -- Rafael ?vila de Esp?ndola From echristo at apple.com Thu Sep 9 16:44:45 2010 From: echristo at apple.com (Eric Christopher) Date: Thu, 09 Sep 2010 21:44:45 -0000 Subject: [llvm-commits] [llvm] r113546 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20100909214445.CABB62A6C12C@llvm.org> Author: echristo Date: Thu Sep 9 16:44:45 2010 New Revision: 113546 URL: http://llvm.org/viewvc/llvm-project?rev=113546&view=rev Log: SIToFP and FPToSI conversions work only on fp-reg to fp-reg. Move some data around and implement a couple of move routines to do this. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=113546&r1=113545&r2=113546&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Thu Sep 9 16:44:45 2010 @@ -132,6 +132,7 @@ unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT); unsigned ARMMaterializeInt(const Constant *C); unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg); + unsigned ARMMoveToIntReg(EVT VT, unsigned SrcReg); bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR); const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB); @@ -332,11 +333,25 @@ } unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) { + // Don't worry about 64-bit now. + if (VT.getSimpleVT().SimpleTy == MVT::f64) return 0; + + unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); + AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, + TII.get(ARM::VMOVRS), MoveReg) + .addReg(SrcReg)); + return MoveReg; +} + +unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) { + // Don't worry about 64-bit now. + if (VT.getSimpleVT().SimpleTy == MVT::i64) return 0; + // If we have a floating point constant we expect it in a floating point // register. unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, - TII.get(ARM::VMOVRS), MoveReg) + TII.get(ARM::VMOVSR), MoveReg) .addReg(SrcReg)); return MoveReg; } @@ -775,23 +790,27 @@ // Make sure we have VFP. if (!Subtarget->hasVFP2()) return false; - EVT VT; + EVT DstVT; const Type *Ty = I->getType(); - if (!isTypeLegal(Ty, VT)) + if (!isTypeLegal(Ty, DstVT)) return false; unsigned Op = getRegForValue(I->getOperand(0)); if (Op == 0) return false; + // The conversion routine works on fp-reg to fp-reg. + unsigned FP = ARMMoveToFPReg(DstVT, Op); + if (FP == 0) return false; + unsigned Opc; if (Ty->isFloatTy()) Opc = ARM::VSITOS; else if (Ty->isDoubleTy()) Opc = ARM::VSITOD; else return 0; - unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); + unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT)); AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg) - .addReg(Op)); + .addReg(FP)); UpdateValueMap(I, ResultReg); return true; } @@ -813,12 +832,19 @@ if (OpTy->isFloatTy()) Opc = ARM::VTOSIZS; else if (OpTy->isDoubleTy()) Opc = ARM::VTOSIZD; else return 0; + EVT OpVT = TLI.getValueType(OpTy, true); - unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); + unsigned ResultReg = createResultReg(TLI.getRegClassFor(OpVT)); AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg) .addReg(Op)); - UpdateValueMap(I, ResultReg); + + // This result needs to be in an integer register, but the conversion only + // takes place in fp-regs. + unsigned IntReg = ARMMoveToIntReg(VT, ResultReg); + if (IntReg == 0) return false; + + UpdateValueMap(I, IntReg); return true; } From clattner at apple.com Thu Sep 9 16:53:00 2010 From: clattner at apple.com (Chris Lattner) Date: Thu, 9 Sep 2010 14:53:00 -0700 Subject: [llvm-commits] [llvm-gcc][arm][patch] Lower function signatures a bit more In-Reply-To: References: <386B2A85-DD45-4217-BE7A-FAE01B59A23B@apple.com> Message-ID: On Sep 9, 2010, at 2:34 PM, Rafael Espindola wrote: >> I haven't reviewed the patch, but in principle this sounds like a great idea! >> >> What IR does: >> double foo(double X, double Y) { return X+Y; } >> >> get lowered into, and what ARM code ends up generated? > > With the patch the generated IL is Great, I was worried that the "long" IR wouldn't be pattern matched back into good machine code. I think this is a great idea, doing it in clang would really be appreciated! -Chris > > ---------------------------------------------------------------------- > define double @foo(i32 %X.0, i32 %X.1, i32 %Y.0, i32 %Y.1) nounwind > readnone optsize { > entry: > %tmp17 = zext i32 %X.0 to i64 > %tmp12 = zext i32 %X.1 to i64 > %tmp13 = shl i64 %tmp12, 32 > %ins15 = or i64 %tmp13, %tmp17 > %tmp6 = zext i32 %Y.0 to i64 > %tmp3 = zext i32 %Y.1 to i64 > %tmp4 = shl i64 %tmp3, 32 > %ins = or i64 %tmp4, %tmp6 > %tmp10 = bitcast i64 %ins15 to double > %tmp2 = bitcast i64 %ins to double > %0 = fadd double %tmp10, %tmp2 > ret double %0 > } > --------------------------------------------------------------------- > > and the asm is > > ---------------------------------------------------------------- > foo: > vmov d0, r2, r3 > vmov d1, r0, r1 > vadd.f64 d0, d1, d0 > vmov r0, r1, d0 > bx lr > ---------------------------------------------------------------- > > or with -mfloat-abi=soft > > ------------------------------------------------------------- > foo: > stmdb sp!, {r11, lr} > bl __adddf3 > ldmia sp!, {r11, pc} > ------------------------------------------------------------- > > Currently we get a more compact but less explicit IL: > ---------------------------------------- > define double @foo(double %X, double %Y) nounwind readnone optsize { > entry: > %0 = fadd double %X, %Y > ret double %0 > } > ---------------------------------------- > > And exactly the same assembly. > >> -Chris > > > Cheers, > -- > Rafael ?vila de Esp?ndola From stoklund at 2pi.dk Thu Sep 9 17:02:13 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 09 Sep 2010 22:02:13 -0000 Subject: [llvm-commits] [llvm] r113550 - /llvm/trunk/test/Other/close-stderr.ll Message-ID: <20100909220213.CE8432A6C12C@llvm.org> Author: stoklund Date: Thu Sep 9 17:02:13 2010 New Revision: 113550 URL: http://llvm.org/viewvc/llvm-project?rev=113550&view=rev Log: XFAIL test under valgrind. It is not really our problem if sh is leaking. Modified: llvm/trunk/test/Other/close-stderr.ll Modified: llvm/trunk/test/Other/close-stderr.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Other/close-stderr.ll?rev=113550&r1=113549&r2=113550&view=diff ============================================================================== --- llvm/trunk/test/Other/close-stderr.ll (original) +++ llvm/trunk/test/Other/close-stderr.ll Thu Sep 9 17:02:13 2010 @@ -4,6 +4,7 @@ ; RUN: " | FileCheck %s ; CHECK: {{^1$}} ; CHECK: {{^0$}} +; XFAIL: vg_leak ; Test that the error handling when writing to stderr fails exits the ; program cleanly rather than aborting. From wendling at apple.com Thu Sep 9 17:23:43 2010 From: wendling at apple.com (Bill Wendling) Date: Thu, 9 Sep 2010 15:23:43 -0700 Subject: [llvm-commits] [llvm] r113550 - /llvm/trunk/test/Other/close-stderr.ll In-Reply-To: <20100909220213.CE8432A6C12C@llvm.org> References: <20100909220213.CE8432A6C12C@llvm.org> Message-ID: <42A4E88A-7EC0-434A-B370-5DC239F3ECD7@apple.com> On Sep 9, 2010, at 3:02 PM, Jakob Stoklund Olesen wrote: > Author: stoklund > Date: Thu Sep 9 17:02:13 2010 > New Revision: 113550 > > URL: http://llvm.org/viewvc/llvm-project?rev=113550&view=rev > Log: > XFAIL test under valgrind. It is not really our problem if sh is leaking. > Is there a way to have valgrind ignore sh leaks? -bw From stoklund at 2pi.dk Thu Sep 9 17:37:35 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 9 Sep 2010 15:37:35 -0700 Subject: [llvm-commits] [llvm] r113550 - /llvm/trunk/test/Other/close-stderr.ll In-Reply-To: <42A4E88A-7EC0-434A-B370-5DC239F3ECD7@apple.com> References: <20100909220213.CE8432A6C12C@llvm.org> <42A4E88A-7EC0-434A-B370-5DC239F3ECD7@apple.com> Message-ID: <308FE3E1-8327-4A8A-874E-374A40D73F89@2pi.dk> On Sep 9, 2010, at 3:23 PM, Bill Wendling wrote: > On Sep 9, 2010, at 3:02 PM, Jakob Stoklund Olesen wrote: > >> Author: stoklund >> Date: Thu Sep 9 17:02:13 2010 >> New Revision: 113550 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=113550&view=rev >> Log: >> XFAIL test under valgrind. It is not really our problem if sh is leaking. >> > Is there a way to have valgrind ignore sh leaks? I don't know, but I don't think so. We already have a bunch of these for tablegen and llvmc leaks. It would make sense to give the vg_leak bot a whitelist of executables to check. Tests that run a different executable should simply be skipped. /jakob From daniel at zuster.org Thu Sep 9 17:42:56 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 09 Sep 2010 22:42:56 -0000 Subject: [llvm-commits] [llvm] r113551 - in /llvm/trunk: lib/MC/MCParser/AsmParser.cpp test/MC/AsmParser/directive_abort.s Message-ID: <20100909224256.951702A6C12C@llvm.org> Author: ddunbar Date: Thu Sep 9 17:42:56 2010 New Revision: 113551 URL: http://llvm.org/viewvc/llvm-project?rev=113551&view=rev Log: llvm-mc: Make sure we exit != 0 if any errors are encountered. Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp llvm/trunk/test/MC/AsmParser/directive_abort.s Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=113551&r1=113550&r2=113551&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Thu Sep 9 17:42:56 2010 @@ -102,6 +102,9 @@ /// Boolean tracking whether macro substitution is enabled. unsigned MacrosEnabled : 1; + /// Flag tracking whether any errors have been encountered. + unsigned HadError : 1; + public: AsmParser(const Target &T, SourceMgr &SM, MCContext &Ctx, MCStreamer &Out, const MCAsmInfo &MAI); @@ -304,6 +307,7 @@ } bool AsmParser::Error(SMLoc L, const Twine &Msg) { + HadError = true; PrintMessage(L, Msg.str(), "error"); PrintMacroInstantiations(); return true; @@ -361,17 +365,17 @@ // Prime the lexer. Lex(); - - bool HadError = false; - + + HadError = false; AsmCond StartingCondState = TheCondState; // While we have input, parse each statement. while (Lexer.isNot(AsmToken::Eof)) { if (!ParseStatement()) continue; - // We had an error, remember it and recover by skipping to the next line. - HadError = true; + // We had an error, validate that one was emitted and recover by skipping to + // the next line. + assert(HadError && "Parse statement returned an error, but none emitted!"); EatToEndOfStatement(); } @@ -383,10 +387,8 @@ const std::vector &MCDwarfFiles = getContext().getMCDwarfFiles(); for (unsigned i = 1; i < MCDwarfFiles.size(); i++) { - if (!MCDwarfFiles[i]){ + if (!MCDwarfFiles[i]) TokError("unassigned file number: " + Twine(i) + " for .file directives"); - HadError = true; - } } // Finalize the output stream if there are no errors and if the client wants Modified: llvm/trunk/test/MC/AsmParser/directive_abort.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/directive_abort.s?rev=113551&r1=113550&r2=113551&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/directive_abort.s (original) +++ llvm/trunk/test/MC/AsmParser/directive_abort.s Thu Sep 9 17:42:56 2010 @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple i386-unknown-unknown %s 2> %t +# RUN: not llvm-mc -triple i386-unknown-unknown %s 2> %t # RUN: FileCheck -input-file %t %s # CHECK: error: .abort 'please stop assembing' From daniel at zuster.org Thu Sep 9 17:42:59 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 09 Sep 2010 22:42:59 -0000 Subject: [llvm-commits] [llvm] r113552 - in /llvm/trunk: lib/MC/MCParser/AsmParser.cpp test/MC/AsmParser/dash-n.s Message-ID: <20100909224300.02CBB2A6C12D@llvm.org> Author: ddunbar Date: Thu Sep 9 17:42:59 2010 New Revision: 113552 URL: http://llvm.org/viewvc/llvm-project?rev=113552&view=rev Log: llvm-mc: Don't crash when using -n and we see a directive before the initial section. - This is annoying, because we have to scatter this check everywhere that could emit real data, but I see no better solution. Added: llvm/trunk/test/MC/AsmParser/dash-n.s Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=113552&r1=113551&r2=113552&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Thu Sep 9 17:42:59 2010 @@ -140,6 +140,8 @@ /// } private: + void CheckForValidSection(); + bool ParseStatement(); bool HandleMacroEntry(StringRef Name, SMLoc NameLoc, const Macro *M); @@ -399,6 +401,16 @@ return HadError; } +void AsmParser::CheckForValidSection() { + if (!getStreamer().getCurrentSection()) { + TokError("expected section directive before assembly directive"); + Out.SwitchSection(Ctx.getMachOSection( + "__TEXT", "__text", + MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS, + 0, SectionKind::getText())); + } +} + /// EatToEndOfStatement - Throw away the rest of the line for testing purposes. void AsmParser::EatToEndOfStatement() { while (Lexer.isNot(AsmToken::EndOfStatement) && @@ -759,6 +771,8 @@ // See what kind of statement we have. switch (Lexer.getKind()) { case AsmToken::Colon: { + CheckForValidSection(); + // identifier ':' -> Label. Lex(); @@ -911,6 +925,8 @@ return false; } + CheckForValidSection(); + // Canonicalize the opcode to lower case. SmallString<128> Opcode; for (unsigned i = 0, e = IDVal.size(); i != e; ++i) @@ -1238,6 +1254,8 @@ /// ::= ( .ascii | .asciz ) [ "string" ( , "string" )* ] bool AsmParser::ParseDirectiveAscii(bool ZeroTerminated) { if (getLexer().isNot(AsmToken::EndOfStatement)) { + CheckForValidSection(); + for (;;) { if (getLexer().isNot(AsmToken::String)) return TokError("expected string in '.ascii' or '.asciz' directive"); @@ -1269,6 +1287,8 @@ /// ::= (.byte | .short | ... ) [ expression (, expression)* ] bool AsmParser::ParseDirectiveValue(unsigned Size) { if (getLexer().isNot(AsmToken::EndOfStatement)) { + CheckForValidSection(); + for (;;) { const MCExpr *Value; SMLoc ATTRIBUTE_UNUSED StartLoc = getLexer().getLoc(); @@ -1298,6 +1318,8 @@ /// ParseDirectiveSpace /// ::= .space expression [ , expression ] bool AsmParser::ParseDirectiveSpace() { + CheckForValidSection(); + int64_t NumBytes; if (ParseAbsoluteExpression(NumBytes)) return true; @@ -1329,6 +1351,8 @@ /// ParseDirectiveFill /// ::= .fill expression , expression , expression bool AsmParser::ParseDirectiveFill() { + CheckForValidSection(); + int64_t NumValues; if (ParseAbsoluteExpression(NumValues)) return true; @@ -1366,6 +1390,8 @@ /// ParseDirectiveOrg /// ::= .org expression [ , expression ] bool AsmParser::ParseDirectiveOrg() { + CheckForValidSection(); + const MCExpr *Offset; if (ParseExpression(Offset)) return true; @@ -1396,6 +1422,8 @@ /// ParseDirectiveAlign /// ::= {.align, ...} expression [ , expression [ , expression ]] bool AsmParser::ParseDirectiveAlign(bool IsPow2, unsigned ValueSize) { + CheckForValidSection(); + SMLoc AlignmentLoc = getLexer().getLoc(); int64_t Alignment; if (ParseAbsoluteExpression(Alignment)) @@ -1560,6 +1588,8 @@ /// ParseDirectiveComm /// ::= ( .comm | .lcomm ) identifier , size_expression [ , align_expression ] bool AsmParser::ParseDirectiveComm(bool IsLocal) { + CheckForValidSection(); + SMLoc IDLoc = getLexer().getLoc(); StringRef Name; if (ParseIdentifier(Name)) Added: llvm/trunk/test/MC/AsmParser/dash-n.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/dash-n.s?rev=113552&view=auto ============================================================================== --- llvm/trunk/test/MC/AsmParser/dash-n.s (added) +++ llvm/trunk/test/MC/AsmParser/dash-n.s Thu Sep 9 17:42:59 2010 @@ -0,0 +1,7 @@ +// RUN: not llvm-mc -n -triple i386-unknown-unknown %s 2> %t +// RUN: FileCheck < %t %s + +.globl a +// CHECK: error: expected section directive before assembly directive +.long 0 + From bigcheesegs at gmail.com Thu Sep 9 18:01:41 2010 From: bigcheesegs at gmail.com (Michael Spencer) Date: Thu, 9 Sep 2010 19:01:41 -0400 Subject: [llvm-commits] [LLVMdev] [PATCH][CMake] Removing LLVMLibDeps.cmake and exporting libraries for CMake clients. In-Reply-To: <0731F7C5-7F24-4FCE-BDB4-F8199FD74C4C@apple.com> References: <0731F7C5-7F24-4FCE-BDB4-F8199FD74C4C@apple.com> Message-ID: On Thu, Sep 9, 2010 at 3:02 PM, Douglas Gregor wrote: > > On Sep 8, 2010, at 5:39 PM, Michael Spencer wrote: > >> While implementing the object file library I ran into some weird >> linking issues. It turned out that you have to manually specify extra >> library dependencies in LLVMLibDeps.cmake, along with what you already >> specify in the CMakeLists.txt file for the component. >> >> The attached patches remove this requirement, and add real CMake >> package export capabilities. A CMake user wishing to use LLVM can now >> use something similar to this: >> >> cmake_minimum_required(VERSION 2.8) >> >> find_package(LLVM REQUIRED) >> add_definitions(${LLVM_CXXFLAGS}) >> add_executable(llvm-external-test llvm-external-test.cpp) >> target_link_libraries(llvm-external-test ${LLVM_SYSTEM_LIBS} >> ${LLVM_JIT_LIBS} ${LLVM_NATIVECODEGEN_LIBS}) >> >> llvm+clang compile with these changes on both Linux and MSVS. >> Currently both patches must be applied at the same time. I can >> refactor them into a 3 step process if needed. >> >> Does this break anything for anyone? > > I think this is great, and I'd like to see it go in, but I can't test it at the moment because, unfortunately, we collided: I just updated a bunch of CMake dependencies in Clang, so your patch doesn't apply. Can you regenerate and post again? > > ? ? ? ?- Doug Attached is the clang patch against r113524. - Michael Spencer -------------- next part -------------- A non-text attachment was scrubbed... Name: clang-cmake-upate-to-match.patch Type: application/octet-stream Size: 18074 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100909/859c475d/attachment.obj From gohman at apple.com Thu Sep 9 18:12:39 2010 From: gohman at apple.com (Dan Gohman) Date: Thu, 09 Sep 2010 23:12:39 -0000 Subject: [llvm-commits] [llvm] r113557 - in /llvm/trunk: include/llvm/Bitcode/LLVMBitCodes.h lib/Bitcode/Reader/BitcodeReader.cpp lib/Bitcode/Writer/BitcodeWriter.cpp tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp Message-ID: <20100909231239.593462A6C12C@llvm.org> Author: djg Date: Thu Sep 9 18:12:39 2010 New Revision: 113557 URL: http://llvm.org/viewvc/llvm-project?rev=113557&view=rev Log: Discard metadata produced by LLVM 2.7. The value enumeration it used is different from what the code now uses in a two ways: NamedMDNodes were considered Values and included in the numbering, and the function-local metadata counter wasn't reset between functions. The later problem breaks lazy deserialization, so instead of trying to emulate the old numbering, just drop the old metadata. The only in-tree use case is debug info with LTO, where the QOI loss is considered acceptable. Modified: llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp Modified: llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h?rev=113557&r1=113556&r2=113557&view=diff ============================================================================== --- llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h (original) +++ llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h Thu Sep 9 18:12:39 2010 @@ -110,12 +110,20 @@ enum MetadataCodes { METADATA_STRING = 1, // MDSTRING: [values] - METADATA_NODE = 2, // MDNODE: [n x (type num, value num)] - METADATA_FN_NODE = 3, // FN_MDNODE: [n x (type num, value num)] + // FIXME: Remove NODE in favor of NODE2 in LLVM 3.0 + METADATA_NODE = 2, // NODE with potentially invalid metadata + // FIXME: Remove FN_NODE in favor of FN_NODE2 in LLVM 3.0 + METADATA_FN_NODE = 3, // FN_NODE with potentially invalid metadata METADATA_NAME = 4, // STRING: [values] - METADATA_NAMED_NODE = 5, // NAMEDMDNODE: [n x mdnodes] + // FIXME: Remove NAMED_NODE in favor of NAMED_NODE2 in LLVM 3.0 + METADATA_NAMED_NODE = 5, // NAMED_NODE with potentially invalid metadata METADATA_KIND = 6, // [n x [id, name]] - METADATA_ATTACHMENT = 7 // [m x [value, [n x [id, mdnode]]] + // FIXME: Remove ATTACHMENT in favor of ATTACHMENT2 in LLVM 3.0 + METADATA_ATTACHMENT = 7, // ATTACHMENT with potentially invalid metadata + METADATA_NODE2 = 8, // NODE2: [n x (type num, value num)] + METADATA_FN_NODE2 = 9, // FN_NODE2: [n x (type num, value num)] + METADATA_NAMED_NODE2 = 10, // NAMED_NODE2: [n x mdnodes] + METADATA_ATTACHMENT2 = 11 // [m x [value, [n x [id, mdnode]]] }; // The constants block (CONSTANTS_BLOCK_ID) describes emission for each // constant and maintains an implicit current type value. @@ -223,7 +231,8 @@ FUNC_CODE_INST_LOAD = 20, // LOAD: [opty, op, align, vol] // FIXME: Remove STORE in favor of STORE2 in LLVM 3.0 FUNC_CODE_INST_STORE = 21, // STORE: [valty,val,ptr, align, vol] - FUNC_CODE_INST_CALL = 22, // CALL: [attr, fnty, fnid, args...] + // FIXME: Remove CALL in favor of CALL2 in LLVM 3.0 + FUNC_CODE_INST_CALL = 22, // CALL with potentially invalid metadata FUNC_CODE_INST_VAARG = 23, // VAARG: [valistty, valist, instty] // This store code encodes the pointer type, rather than the value type // this is so information only available in the pointer type (e.g. address @@ -241,8 +250,13 @@ FUNC_CODE_INST_INBOUNDS_GEP= 30, // INBOUNDS_GEP: [n x operands] FUNC_CODE_INST_INDIRECTBR = 31, // INDIRECTBR: [opty, op0, op1, ...] - FUNC_CODE_DEBUG_LOC = 32, // DEBUG_LOC: [Line,Col,ScopeVal, IAVal] - FUNC_CODE_DEBUG_LOC_AGAIN = 33 // DEBUG_LOC_AGAIN + // FIXME: Remove DEBUG_LOC in favor of DEBUG_LOC2 in LLVM 3.0 + FUNC_CODE_DEBUG_LOC = 32, // DEBUG_LOC with potentially invalid metadata + FUNC_CODE_DEBUG_LOC_AGAIN = 33, // DEBUG_LOC_AGAIN + + FUNC_CODE_INST_CALL2 = 34, // CALL2: [attr, fnty, fnid, args...] + + FUNC_CODE_DEBUG_LOC2 = 35 // DEBUG_LOC2: [Line,Col,ScopeVal, IAVal] }; } // End bitc namespace } // End llvm namespace Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp?rev=113557&r1=113556&r2=113557&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp (original) +++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp Thu Sep 9 18:12:39 2010 @@ -786,8 +786,12 @@ Record.clear(); Code = Stream.ReadCode(); - // METADATA_NAME is always followed by METADATA_NAMED_NODE. - if (Stream.ReadRecord(Code, Record) != bitc::METADATA_NAMED_NODE) + // METADATA_NAME is always followed by METADATA_NAMED_NODE2. + unsigned NextBitCode = Stream.ReadRecord(Code, Record); + // FIXME: LLVM 3.0: Remove this. + if (NextBitCode == bitc::METADATA_NAMED_NODE) + break; + if (NextBitCode != bitc::METADATA_NAMED_NODE2) assert ( 0 && "Inavlid Named Metadata record"); // Read named metadata elements. @@ -802,11 +806,19 @@ break; } case bitc::METADATA_FN_NODE: + // FIXME: Legacy support for the old fn_node, where function-local + // metadata operands were bogus. Remove in LLVM 3.0. + break; + case bitc::METADATA_NODE: + // FIXME: Legacy support for the old node, where function-local + // metadata operands were bogus. Remove in LLVM 3.0. + break; + case bitc::METADATA_FN_NODE2: IsFunctionLocal = true; // fall-through - case bitc::METADATA_NODE: { + case bitc::METADATA_NODE2: { if (Record.size() % 2 == 1) - return Error("Invalid METADATA_NODE record"); + return Error("Invalid METADATA_NODE2 record"); unsigned Size = Record.size(); SmallVector Elts; @@ -1593,7 +1605,10 @@ switch (Stream.ReadRecord(Code, Record)) { default: // Default behavior: ignore. break; - case bitc::METADATA_ATTACHMENT: { + case bitc::METADATA_ATTACHMENT: + // LLVM 3.0: Remove this. + break; + case bitc::METADATA_ATTACHMENT2: { unsigned RecordLength = Record.size(); if (Record.empty() || (RecordLength - 1) % 2 == 1) return Error ("Invalid METADATA_ATTACHMENT reader!"); @@ -1706,7 +1721,11 @@ I = 0; continue; - case bitc::FUNC_CODE_DEBUG_LOC: { // DEBUG_LOC: [line, col, scope, ia] + case bitc::FUNC_CODE_DEBUG_LOC: + // FIXME: Ignore. Remove this in LLVM 3.0. + continue; + + case bitc::FUNC_CODE_DEBUG_LOC2: { // DEBUG_LOC: [line, col, scope, ia] I = 0; // Get the last instruction emitted. if (CurBB && !CurBB->empty()) I = &CurBB->back(); @@ -2221,7 +2240,12 @@ InstructionList.push_back(I); break; } - case bitc::FUNC_CODE_INST_CALL: { + case bitc::FUNC_CODE_INST_CALL: + case bitc::FUNC_CODE_INST_CALL2: { + // FIXME: Legacy support for the old call instruction, where function-local + // metadata operands were bogus. Remove in LLVM 3.0. + bool DropMetadata = BitCode == bitc::FUNC_CODE_INST_CALL; + // CALL: [paramattrs, cc, fnty, fnid, arg0, arg1...] if (Record.size() < 3) return Error("Invalid CALL record"); @@ -2245,7 +2269,13 @@ for (unsigned i = 0, e = FTy->getNumParams(); i != e; ++i, ++OpNum) { if (FTy->getParamType(i)->getTypeID()==Type::LabelTyID) Args.push_back(getBasicBlock(Record[OpNum])); - else + else if (DropMetadata && + FTy->getParamType(i)->getTypeID()==Type::MetadataTyID) { + // LLVM 2.7 compatibility: drop metadata arguments to null. + Value *Ops = 0; + Args.push_back(MDNode::get(Context, &Ops, 1)); + continue; + } else Args.push_back(getFnValueByID(Record[OpNum], FTy->getParamType(i))); if (Args.back() == 0) return Error("Invalid CALL record"); } Modified: llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp?rev=113557&r1=113556&r2=113557&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp (original) +++ llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp Thu Sep 9 18:12:39 2010 @@ -485,8 +485,8 @@ Record.push_back(0); } } - unsigned MDCode = N->isFunctionLocal() ? bitc::METADATA_FN_NODE : - bitc::METADATA_NODE; + unsigned MDCode = N->isFunctionLocal() ? bitc::METADATA_FN_NODE2 : + bitc::METADATA_NODE2; Stream.EmitRecord(MDCode, Record, 0); Record.clear(); } @@ -549,7 +549,7 @@ // Write named metadata operands. for (unsigned i = 0, e = NMD->getNumOperands(); i != e; ++i) Record.push_back(VE.getValueID(NMD->getOperand(i))); - Stream.EmitRecord(bitc::METADATA_NAMED_NODE, Record, 0); + Stream.EmitRecord(bitc::METADATA_NAMED_NODE2, Record, 0); Record.clear(); } @@ -585,7 +585,7 @@ SmallVector Record; // Write metadata attachments - // METADATA_ATTACHMENT - [m x [value, [n x [id, mdnode]]] + // METADATA_ATTACHMENT2 - [m x [value, [n x [id, mdnode]]] SmallVector, 4> MDs; for (Function::const_iterator BB = F.begin(), E = F.end(); BB != E; ++BB) @@ -603,7 +603,7 @@ Record.push_back(MDs[i].first); Record.push_back(VE.getValueID(MDs[i].second)); } - Stream.EmitRecord(bitc::METADATA_ATTACHMENT, Record, 0); + Stream.EmitRecord(bitc::METADATA_ATTACHMENT2, Record, 0); Record.clear(); } @@ -1111,7 +1111,7 @@ const PointerType *PTy = cast(CI.getCalledValue()->getType()); const FunctionType *FTy = cast(PTy->getElementType()); - Code = bitc::FUNC_CODE_INST_CALL; + Code = bitc::FUNC_CODE_INST_CALL2; Vals.push_back(VE.getAttributeID(CI.getAttributes())); Vals.push_back((CI.getCallingConv() << 1) | unsigned(CI.isTailCall())); @@ -1255,7 +1255,7 @@ Vals.push_back(DL.getCol()); Vals.push_back(Scope ? VE.getValueID(Scope)+1 : 0); Vals.push_back(IA ? VE.getValueID(IA)+1 : 0); - Stream.EmitRecord(bitc::FUNC_CODE_DEBUG_LOC, Vals); + Stream.EmitRecord(bitc::FUNC_CODE_DEBUG_LOC2, Vals); Vals.clear(); LastDL = DL; Modified: llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp?rev=113557&r1=113556&r2=113557&view=diff ============================================================================== --- llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp (original) +++ llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp Thu Sep 9 18:12:39 2010 @@ -236,6 +236,8 @@ case bitc::FUNC_CODE_INST_VSELECT: return "INST_VSELECT"; case bitc::FUNC_CODE_DEBUG_LOC: return "DEBUG_LOC"; case bitc::FUNC_CODE_DEBUG_LOC_AGAIN: return "DEBUG_LOC_AGAIN"; + case bitc::FUNC_CODE_INST_CALL2: return "INST_CALL2"; + case bitc::FUNC_CODE_DEBUG_LOC2: return "DEBUG_LOC2"; } case bitc::TYPE_SYMTAB_BLOCK_ID: switch (CodeID) { @@ -263,6 +265,10 @@ case bitc::METADATA_NAMED_NODE: return "METADATA_NAMED_NODE"; case bitc::METADATA_KIND: return "METADATA_KIND"; case bitc::METADATA_ATTACHMENT: return "METADATA_ATTACHMENT"; + case bitc::METADATA_NODE2: return "METADATA_NODE2"; + case bitc::METADATA_FN_NODE2: return "METADATA_FN_NODE2"; + case bitc::METADATA_NAMED_NODE2: return "METADATA_NAMED_NODE2"; + case bitc::METADATA_ATTACHMENT2: return "METADATA_ATTACHMENT2"; } } } From wdietz2 at illinois.edu Thu Sep 9 18:14:22 2010 From: wdietz2 at illinois.edu (Will Dietz) Date: Thu, 09 Sep 2010 23:14:22 -0000 Subject: [llvm-commits] [poolalloc] r113558 - /poolalloc/trunk/test/TEST.poolalloc.Makefile Message-ID: <20100909231422.CDF6E2A6C12C@llvm.org> Author: wdietz2 Date: Thu Sep 9 18:14:22 2010 New Revision: 113558 URL: http://llvm.org/viewvc/llvm-project?rev=113558&view=rev Log: Make running the poolalloc tests safe on non-mac platforms (by running tool via RunToolSafely) Modified: poolalloc/trunk/test/TEST.poolalloc.Makefile Modified: poolalloc/trunk/test/TEST.poolalloc.Makefile URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/TEST.poolalloc.Makefile?rev=113558&r1=113557&r2=113558&view=diff ============================================================================== --- poolalloc/trunk/test/TEST.poolalloc.Makefile (original) +++ poolalloc/trunk/test/TEST.poolalloc.Makefile Thu Sep 9 18:14:22 2010 @@ -40,7 +40,7 @@ #PA_RT_O := $(PROJECT_DIR)/lib/$(CONFIGURATION)/poolalloc_fl_rt.o # Command to run opt with the pool allocator pass loaded -OPT_PA := $(WATCHDOG) $(LOPT) -load $(DSA_SO) -load $(PA_SO) +OPT_PA := $(RUNTOOLSAFELY) $(WATCHDOG) $(LOPT) -load $(DSA_SO) -load $(PA_SO) # OPT_PA_STATS - Run opt with the -stats and -time-passes options, capturing the # output to a file. From wdietz2 at illinois.edu Thu Sep 9 18:15:52 2010 From: wdietz2 at illinois.edu (Will Dietz) Date: Thu, 09 Sep 2010 23:15:52 -0000 Subject: [llvm-commits] [poolalloc] r113559 - /poolalloc/trunk/lib/DSA/CompleteBottomUp.cpp Message-ID: <20100909231552.957122A6C12C@llvm.org> Author: wdietz2 Date: Thu Sep 9 18:15:52 2010 New Revision: 113559 URL: http://llvm.org/viewvc/llvm-project?rev=113559&view=rev Log: Simplify CBU code greatly, fix bug due to not using the NH by reference. Modified: poolalloc/trunk/lib/DSA/CompleteBottomUp.cpp Modified: poolalloc/trunk/lib/DSA/CompleteBottomUp.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/CompleteBottomUp.cpp?rev=113559&r1=113558&r2=113559&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/CompleteBottomUp.cpp (original) +++ poolalloc/trunk/lib/DSA/CompleteBottomUp.cpp Thu Sep 9 18:15:52 2010 @@ -123,6 +123,7 @@ } #endif + // // Note: The code above and below is dealing with the fact that the targets // of *direct* function calls do not show up in the Scalar Map of the @@ -160,30 +161,9 @@ // bur are not the targets of an indirect function call site, they will not // be merged by CBU. - DSNodeHandle SrcNH; - while(csi != cse) { - const Function *F = *csi; - DSCallGraph::scc_iterator sccii = callgraph.scc_begin(F), - sccee = callgraph.scc_end(F); - while(sccii != sccee && SM.find(*sccii) == SM.end()) { - ++sccii; - } - if(sccii == sccee) { - ++csi; - continue; - } - SrcNH = SM.find(*sccii)->second; - ++sccii; - for(;sccii != sccee; ++sccii) { - DSGraph::ScalarMapTy::const_iterator I = SM.find(*sccii); - if (I != SM.end()) { - SrcNH.mergeWith(I->second); - } - } - ++csi; - break; - } - + // This NH starts off empty, but ends up merging them all together + DSNodeHandle calleesNH; + while(csi != cse) { const Function *F = *csi; DSCallGraph::scc_iterator sccii = callgraph.scc_begin(F), @@ -191,7 +171,7 @@ for(;sccii != sccee; ++sccii) { DSGraph::ScalarMapTy::const_iterator I = SM.find(*sccii); if (I != SM.end()) { - SrcNH.mergeWith(I->second); + calleesNH.mergeWith(I->second); } } ++csi; From echristo at apple.com Thu Sep 9 18:50:01 2010 From: echristo at apple.com (Eric Christopher) Date: Thu, 09 Sep 2010 23:50:01 -0000 Subject: [llvm-commits] [llvm] r113561 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20100909235001.153102A6C12C@llvm.org> Author: echristo Date: Thu Sep 9 18:50:00 2010 New Revision: 113561 URL: http://llvm.org/viewvc/llvm-project?rev=113561&view=rev Log: 64-bit fp loads can come straight out of the constant pool, not as bad as I'd thought. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=113561&r1=113560&r2=113561&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Thu Sep 9 18:50:00 2010 @@ -373,16 +373,24 @@ .addFPImm(CFP)); return DestReg; } - - // No 64-bit at the moment. - if (is64bit) return 0; - - // Load this from the constant pool. - unsigned DestReg = ARMMaterializeInt(cast(CFP)); - - // If we have a floating point constant we expect it in a floating point - // register. - return ARMMoveToFPReg(VT, DestReg); + + // Require VFP2 for this. + if (!Subtarget->hasVFP2()) return false; + + // MachineConstantPool wants an explicit alignment. + unsigned Align = TD.getPrefTypeAlignment(CFP->getType()); + if (Align == 0) { + // TODO: Figure out if this is correct. + Align = TD.getTypeAllocSize(CFP->getType()); + } + unsigned Idx = MCP.getConstantPoolIndex(cast(CFP), Align); + unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); + unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS; + + AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc)) + .addReg(DestReg).addConstantPoolIndex(Idx) + .addReg(0)); + return DestReg; } unsigned ARMFastISel::ARMMaterializeInt(const Constant *C) { From stoklund at 2pi.dk Thu Sep 9 19:08:10 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 9 Sep 2010 17:08:10 -0700 Subject: [llvm-commits] [llvm] r113405 - /llvm/trunk/cmake/modules/VersionFromVCS.cmake In-Reply-To: <20100908204940.455822A6C12C@llvm.org> References: <20100908204940.455822A6C12C@llvm.org> Message-ID: <9C99DC0B-219E-4D81-9088-01C5A91C85A6@2pi.dk> On Sep 8, 2010, at 1:49 PM, Michael J. Spencer wrote: > Author: mspencer > Date: Wed Sep 8 15:49:40 2010 > New Revision: 113405 > > URL: http://llvm.org/viewvc/llvm-project?rev=113405&view=rev > Log: > CMake: Use the svn revision information from git-svn if available. The clang-i686-xp-msvc9 tester has not been green since this change. It is looking like a possible culprit. This build failed because of a trivial compile error: http://google1.osuosl.org:8011/builders/clang-i686-xp-msvc9/builds/9005 The next build had the compile error fixed, but the tester didn't recover: http://google1.osuosl.org:8011/builders/clang-i686-xp-msvc9/builds/9006 Could you take a look, please? > > Modified: > llvm/trunk/cmake/modules/VersionFromVCS.cmake > > Modified: llvm/trunk/cmake/modules/VersionFromVCS.cmake > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/VersionFromVCS.cmake?rev=113405&r1=113404&r2=113405&view=diff > ============================================================================== > --- llvm/trunk/cmake/modules/VersionFromVCS.cmake (original) > +++ llvm/trunk/cmake/modules/VersionFromVCS.cmake Wed Sep 8 15:49:40 2010 > @@ -10,7 +10,7 @@ > if( Subversion_FOUND ) > subversion_wc_info( ${CMAKE_CURRENT_SOURCE_DIR} Project ) > if( Project_WC_REVISION ) > - set(result "${result}-r${Project_WC_REVISION}") > + set(result "${result}-r${Project_WC_REVISION}") > endif() > endif() > elseif( EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/.git ) > @@ -19,13 +19,23 @@ > find_program(git_executable NAMES git git.exe git.cmd) > if( git_executable ) > execute_process(COMMAND ${git_executable} show-ref HEAD > - WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} > - TIMEOUT 5 > - RESULT_VARIABLE git_result > - OUTPUT_VARIABLE git_output) > + WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} > + TIMEOUT 5 > + RESULT_VARIABLE git_result > + OUTPUT_VARIABLE git_output) > if( git_result EQUAL 0 ) > - string(SUBSTRING ${git_output} 0 7 git_ref_id) > - set(result "${result}-${git_ref_id}") > + string(SUBSTRING ${git_output} 0 7 git_ref_id) > + set(result "${result}-${git_ref_id}") > + else() > + execute_process(COMMAND ${git_executable} svn log --limit=1 --oneline > + WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} > + TIMEOUT 5 > + RESULT_VARIABLE git_result > + OUTPUT_VARIABLE git_output) > + if( git_result EQUAL 0 ) > + string(REGEX MATCH r[0-9]+ git_svn_rev ${git_output}) > + set(result "${result}-svn-${git_svn_rev}") > + endif() > endif() > endif() > endif() > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From echristo at apple.com Thu Sep 9 19:34:35 2010 From: echristo at apple.com (Eric Christopher) Date: Fri, 10 Sep 2010 00:34:35 -0000 Subject: [llvm-commits] [llvm] r113565 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20100910003435.433B22A6C12C@llvm.org> Author: echristo Date: Thu Sep 9 19:34:35 2010 New Revision: 113565 URL: http://llvm.org/viewvc/llvm-project?rev=113565&view=rev Log: Update comments, reorganize some code, rename variables to be more clear. No functional change. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=113565&r1=113564&r2=113565&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Thu Sep 9 19:34:35 2010 @@ -332,8 +332,9 @@ return ResultReg; } +// TODO: Don't worry about 64-bit now, but when this is fixed remove the +// checks from the various callers. unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) { - // Don't worry about 64-bit now. if (VT.getSimpleVT().SimpleTy == MVT::f64) return 0; unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); @@ -344,11 +345,8 @@ } unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) { - // Don't worry about 64-bit now. if (VT.getSimpleVT().SimpleTy == MVT::i64) return 0; - // If we have a floating point constant we expect it in a floating point - // register. unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::VMOVSR), MoveReg) @@ -374,7 +372,7 @@ return DestReg; } - // Require VFP2 for this. + // Require VFP2 for loading fp constants. if (!Subtarget->hasVFP2()) return false; // MachineConstantPool wants an explicit alignment. @@ -387,12 +385,14 @@ unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS; + // The extra reg is for addrmode5. AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc)) .addReg(DestReg).addConstantPoolIndex(Idx) .addReg(0)); return DestReg; } +// TODO: Verify 64-bit. unsigned ARMFastISel::ARMMaterializeInt(const Constant *C) { // MachineConstantPool wants an explicit alignment. unsigned Align = TD.getPrefTypeAlignment(C->getType()); @@ -401,13 +401,14 @@ Align = TD.getTypeAllocSize(C->getType()); } unsigned Idx = MCP.getConstantPoolIndex(C, Align); - unsigned DestReg = createResultReg(TLI.getRegClassFor(MVT::i32)); + if (isThumb) AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::t2LDRpci)) .addReg(DestReg).addConstantPoolIndex(Idx)); else + // The extra reg and immediate are for addrmode2. AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp)) .addReg(DestReg).addConstantPoolIndex(Idx) @@ -461,7 +462,6 @@ // virtual registers. if (FuncInfo.MBBMap[I->getParent()] != FuncInfo.MBB) return false; - Opcode = I->getOpcode(); U = I; } else if (const ConstantExpr *C = dyn_cast(Obj)) { @@ -477,7 +477,6 @@ switch (Opcode) { default: - //errs() << "Failing Opcode is: " << *Op1 << "\n"; break; case Instruction::Alloca: { assert(false && "Alloca should have been handled earlier!"); @@ -485,8 +484,8 @@ } } + // FIXME: Handle global variables. if (const GlobalValue *GV = dyn_cast(Obj)) { - //errs() << "Failing GV is: " << GV << "\n"; (void)GV; return false; } @@ -516,7 +515,6 @@ static_cast(TII)); } } - return true; } @@ -579,6 +577,32 @@ return true; } +bool ARMFastISel::ARMSelectLoad(const Instruction *I) { + // Verify we have a legal type before going any further. + EVT VT; + if (!isLoadTypeLegal(I->getType(), VT)) + return false; + + // If we're an alloca we know we have a frame index and can emit the load + // directly in short order. + if (ARMLoadAlloca(I, VT)) + return true; + + // Our register and offset with innocuous defaults. + unsigned Reg = 0; + int Offset = 0; + + // See if we can handle this as Reg + Offset + if (!ARMComputeRegOffset(I->getOperand(0), Reg, Offset)) + return false; + + unsigned ResultReg; + if (!ARMEmitLoad(VT, ResultReg, Reg, Offset /* 0 */)) return false; + + UpdateValueMap(I, ResultReg); + return true; +} + bool ARMFastISel::ARMStoreAlloca(const Instruction *I, unsigned SrcReg, EVT VT){ Value *Op1 = I->getOperand(1); @@ -662,32 +686,6 @@ return false; } -bool ARMFastISel::ARMSelectLoad(const Instruction *I) { - // Verify we have a legal type before going any further. - EVT VT; - if (!isLoadTypeLegal(I->getType(), VT)) - return false; - - // If we're an alloca we know we have a frame index and can emit the load - // directly in short order. - if (ARMLoadAlloca(I, VT)) - return true; - - // Our register and offset with innocuous defaults. - unsigned Reg = 0; - int Offset = 0; - - // See if we can handle this as Reg + Offset - if (!ARMComputeRegOffset(I->getOperand(0), Reg, Offset)) - return false; - - unsigned ResultReg; - if (!ARMEmitLoad(VT, ResultReg, Reg, Offset /* 0 */)) return false; - - UpdateValueMap(I, ResultReg); - return true; -} - bool ARMFastISel::ARMSelectBranch(const Instruction *I) { const BranchInst *BI = cast(I); MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)]; @@ -744,8 +742,8 @@ AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc)) .addReg(Arg1).addReg(Arg2)); - // For floating point we need to move the result to a register we can - // actually do something with. + // For floating point we need to move the result to a comparison register + // that we can then use for branches. if (isFloat) AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::FMSTAT))); @@ -766,7 +764,6 @@ if (Op == 0) return false; unsigned Result = createResultReg(ARM::DPRRegisterClass); - AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::VCVTDS), Result) .addReg(Op)); @@ -786,7 +783,6 @@ if (Op == 0) return false; unsigned Result = createResultReg(ARM::SPRRegisterClass); - AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::VCVTSD), Result) .addReg(Op)); @@ -806,7 +802,8 @@ unsigned Op = getRegForValue(I->getOperand(0)); if (Op == 0) return false; - // The conversion routine works on fp-reg to fp-reg. + // The conversion routine works on fp-reg to fp-reg and the operand above + // was an integer, move it to the fp registers if possible. unsigned FP = ARMMoveToFPReg(DstVT, Op); if (FP == 0) return false; @@ -827,7 +824,7 @@ // Make sure we have VFP. if (!Subtarget->hasVFP2()) return false; - EVT VT; + EVT DstVT; const Type *RetTy = I->getType(); if (!isTypeLegal(RetTy, VT)) return false; @@ -849,7 +846,7 @@ // This result needs to be in an integer register, but the conversion only // takes place in fp-regs. - unsigned IntReg = ARMMoveToIntReg(VT, ResultReg); + unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg); if (IntReg == 0) return false; UpdateValueMap(I, IntReg); From echristo at apple.com Thu Sep 9 19:35:09 2010 From: echristo at apple.com (Eric Christopher) Date: Fri, 10 Sep 2010 00:35:09 -0000 Subject: [llvm-commits] [llvm] r113566 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20100910003509.2FDF92A6C12C@llvm.org> Author: echristo Date: Thu Sep 9 19:35:09 2010 New Revision: 113566 URL: http://llvm.org/viewvc/llvm-project?rev=113566&view=rev Log: Fix build error. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=113566&r1=113565&r2=113566&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Thu Sep 9 19:35:09 2010 @@ -826,7 +826,7 @@ EVT DstVT; const Type *RetTy = I->getType(); - if (!isTypeLegal(RetTy, VT)) + if (!isTypeLegal(RetTy, DstVT)) return false; unsigned Op = getRegForValue(I->getOperand(0)); From aggarwa4 at illinois.edu Thu Sep 9 19:39:41 2010 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Fri, 10 Sep 2010 00:39:41 -0000 Subject: [llvm-commits] [poolalloc] r113567 - /poolalloc/trunk/lib/DSA/CompleteBottomUp.cpp Message-ID: <20100910003941.D42182A6C12C@llvm.org> Author: aggarwa4 Date: Thu Sep 9 19:39:41 2010 New Revision: 113567 URL: http://llvm.org/viewvc/llvm-project?rev=113567&view=rev Log: Making sure that DSInfo is initialized with a list of all the functions in the module at the beginning of CBU. Modified: poolalloc/trunk/lib/DSA/CompleteBottomUp.cpp Modified: poolalloc/trunk/lib/DSA/CompleteBottomUp.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/CompleteBottomUp.cpp?rev=113567&r1=113566&r2=113567&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/CompleteBottomUp.cpp (original) +++ poolalloc/trunk/lib/DSA/CompleteBottomUp.cpp Thu Sep 9 19:39:41 2010 @@ -43,6 +43,17 @@ CompleteBUDataStructures::runOnModule (Module &M) { init(&getAnalysis(), false, true, false, true); + + // + // Make sure we have a DSGraph for all declared functions in the Module. + // formGlobalECs assumes that DSInfo is populated with a list of + // DSgraphs for all the functions. + + for (Module::iterator F = M.begin(); F != M.end(); ++F) { + if (!(F->isDeclaration())) + getOrCreateGraph(F); + } + buildIndirectFunctionSets(); formGlobalECs(); From espindola at google.com Thu Sep 9 20:06:52 2010 From: espindola at google.com (Rafael Espindola) Date: Thu, 9 Sep 2010 21:06:52 -0400 Subject: [llvm-commits] [patch][mc] Add support for .uleb In-Reply-To: <9279A406-42FB-4AA3-A60C-B0A31078DDBE@apple.com> References: <9279A406-42FB-4AA3-A60C-B0A31078DDBE@apple.com> Message-ID: > Awesome! ?One major comment: please add this to generic code. ?The darwin assembler also supports this directive, we just never got around to implementing it. Moved. It is still supporting only absolute expressions. I left HasLEB128 unchanged in X86MCAsmInfoDarwin because I don't know if it needs full support or just absolute expressions are sufficient. > We should also add a "emit uleb/sleb" value in MCStreamer, because these directives don't require an immediate, it can be a symbolic value (like a label difference). This looks bigger than the current patch. Is it OK to add support for absolute expressions first and come back after more of the low hanging ELF bits are done? > -Chris Cheers, -- Rafael ?vila de Esp?ndola -------------- next part -------------- A non-text attachment was scrubbed... Name: leb128.patch Type: text/x-patch Size: 7546 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100909/8f39dcc1/attachment.bin From espindola at google.com Thu Sep 9 20:15:37 2010 From: espindola at google.com (Rafael Espindola) Date: Thu, 9 Sep 2010 21:15:37 -0400 Subject: [llvm-commits] [llvm-gcc][arm][patch] Lower function signatures a bit more In-Reply-To: References: <386B2A85-DD45-4217-BE7A-FAE01B59A23B@apple.com> Message-ID: > Great, I was worried that the "long" IR wouldn't be pattern matched back into good machine code. ?I think this is a great idea, doing it in clang would really be appreciated! Sure. Will give it a try when we start using clang. Maybe a bit earlier :-) So, how do I test this for hard float? If I understand the config macros correctly, the check if (TARGET_HARD_FLOAT_ABI) return false; should keep the results unchanged for hard float. > -Chris Cheers, -- Rafael ?vila de Esp?ndola From evan.cheng at apple.com Thu Sep 9 20:29:17 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 10 Sep 2010 01:29:17 -0000 Subject: [llvm-commits] [llvm] r113570 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ lib/Target/ARM/ lib/Target/CellSPU/ lib/Target/PowerPC/ test/CodeGen/ARM/ test/CodeGen/Thumb2/ Message-ID: <20100910012917.6A2C42A6C12C@llvm.org> Author: evancheng Date: Thu Sep 9 20:29:16 2010 New Revision: 113570 URL: http://llvm.org/viewvc/llvm-project?rev=113570&view=rev Log: Teach if-converter to be more careful with predicating instructions that would take multiple cycles to decode. For the current if-converter clients (actually only ARM), the instructions that are predicated on false are not nops. They would still take machine cycles to decode. Micro-coded instructions such as LDM / STM can potentially take multiple cycles to decode. If-converter should take treat them as non-micro-coded simple instructions. Added: llvm/trunk/test/CodeGen/ARM/ifcvt10.ll Modified: llvm/trunk/include/llvm/CodeGen/PostRAHazardRecognizer.h llvm/trunk/include/llvm/Target/TargetInstrInfo.h llvm/trunk/include/llvm/Target/TargetInstrItineraries.h llvm/trunk/include/llvm/Target/TargetMachine.h llvm/trunk/lib/CodeGen/IfConversion.cpp llvm/trunk/lib/CodeGen/PostRAHazardRecognizer.cpp llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.h llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp llvm/trunk/lib/Target/ARM/ARM.td llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.h llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp llvm/trunk/lib/Target/ARM/ARMSubtarget.h llvm/trunk/lib/Target/ARM/ARMTargetMachine.h llvm/trunk/lib/Target/ARM/Thumb2HazardRecognizer.h llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.h llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h llvm/trunk/lib/Target/TargetInstrInfo.cpp llvm/trunk/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll Modified: llvm/trunk/include/llvm/CodeGen/PostRAHazardRecognizer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/PostRAHazardRecognizer.h?rev=113570&r1=113569&r2=113570&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/PostRAHazardRecognizer.h (original) +++ llvm/trunk/include/llvm/CodeGen/PostRAHazardRecognizer.h Thu Sep 9 20:29:16 2010 @@ -75,13 +75,13 @@ }; // Itinerary data for the target. - const InstrItineraryData &ItinData; + const InstrItineraryData *ItinData; ScoreBoard ReservedScoreboard; ScoreBoard RequiredScoreboard; public: - PostRAHazardRecognizer(const InstrItineraryData &ItinData); + PostRAHazardRecognizer(const InstrItineraryData *ItinData); virtual HazardType getHazardType(SUnit *SU); virtual void Reset(); Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=113570&r1=113569&r2=113570&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Thu Sep 9 20:29:16 2010 @@ -575,7 +575,7 @@ /// to use for this target when scheduling the machine instructions after /// register allocation. virtual ScheduleHazardRecognizer* - CreateTargetPostRAHazardRecognizer(const InstrItineraryData&) const = 0; + CreateTargetPostRAHazardRecognizer(const InstrItineraryData*) const = 0; /// AnalyzeCompare - For a comparison instruction, return the source register /// in SrcReg and the value it compares against in CmpValue. Return true if @@ -595,7 +595,7 @@ /// getNumMicroOps - Return the number of u-operations the given machine /// instruction will be decoded to on the target cpu. virtual unsigned getNumMicroOps(const MachineInstr *MI, - const InstrItineraryData &ItinData) const; + const InstrItineraryData *ItinData) const; }; /// TargetInstrInfoImpl - This is the default implementation of @@ -631,7 +631,7 @@ const MachineFunction &MF) const; virtual ScheduleHazardRecognizer * - CreateTargetPostRAHazardRecognizer(const InstrItineraryData&) const; + CreateTargetPostRAHazardRecognizer(const InstrItineraryData*) const; }; } // End llvm namespace Modified: llvm/trunk/include/llvm/Target/TargetInstrItineraries.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrItineraries.h?rev=113570&r1=113569&r2=113570&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetInstrItineraries.h (original) +++ llvm/trunk/include/llvm/Target/TargetInstrItineraries.h Thu Sep 9 20:29:16 2010 @@ -181,6 +181,14 @@ return (int)OperandCycles[FirstIdx + OperandIdx]; } + + /// isMicroCoded - Return true if the instructions in the given class decode + /// to more than one micro-ops. + bool isMicroCoded(unsigned ItinClassIndx) const { + if (isEmpty()) + return false; + return Itineratries[ItinClassIndx].NumMicroOps != 1; + } }; Modified: llvm/trunk/include/llvm/Target/TargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=113570&r1=113569&r2=113570&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetMachine.h (original) +++ llvm/trunk/include/llvm/Target/TargetMachine.h Thu Sep 9 20:29:16 2010 @@ -152,8 +152,8 @@ /// getInstrItineraryData - Returns instruction itinerary data for the target /// or specific subtarget. /// - virtual const InstrItineraryData getInstrItineraryData() const { - return InstrItineraryData(); + virtual const InstrItineraryData *getInstrItineraryData() const { + return 0; } /// getELFWriterInfo - If this target supports an ELF writer, return Modified: llvm/trunk/lib/CodeGen/IfConversion.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/IfConversion.cpp?rev=113570&r1=113569&r2=113570&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/IfConversion.cpp (original) +++ llvm/trunk/lib/CodeGen/IfConversion.cpp Thu Sep 9 20:29:16 2010 @@ -18,6 +18,7 @@ #include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/Target/TargetInstrInfo.h" +#include "llvm/Target/TargetInstrItineraries.h" #include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetRegisterInfo.h" @@ -150,6 +151,7 @@ const TargetLowering *TLI; const TargetInstrInfo *TII; const TargetRegisterInfo *TRI; + const InstrItineraryData *InstrItins; bool MadeChange; int FnNum; public: @@ -238,6 +240,7 @@ TLI = MF.getTarget().getTargetLowering(); TII = MF.getTarget().getInstrInfo(); TRI = MF.getTarget().getRegisterInfo(); + InstrItins = MF.getTarget().getInstrItineraryData(); if (!TII) return false; // Tail merge tend to expose more if-conversion opportunities. @@ -641,9 +644,10 @@ bool isCondBr = BBI.IsBrAnalyzable && TID.isConditionalBranch(); if (!isCondBr) { - if (!isPredicated) - BBI.NonPredSize++; - else if (!AlreadyPredicated) { + if (!isPredicated) { + unsigned NumOps = TII->getNumMicroOps(&*I, InstrItins); + BBI.NonPredSize += NumOps; + } else if (!AlreadyPredicated) { // FIXME: This instruction is already predicated before the // if-conversion pass. It's probably something like a conditional move. // Mark this block unpredicable for now. @@ -1364,7 +1368,8 @@ MachineInstr *MI = MF.CloneMachineInstr(I); ToBBI.BB->insert(ToBBI.BB->end(), MI); - ToBBI.NonPredSize++; + unsigned NumOps = TII->getNumMicroOps(MI, InstrItins); + ToBBI.NonPredSize += NumOps; if (!TII->isPredicated(I) && !MI->isDebugValue()) { if (!TII->PredicateInstruction(MI, Cond)) { Modified: llvm/trunk/lib/CodeGen/PostRAHazardRecognizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PostRAHazardRecognizer.cpp?rev=113570&r1=113569&r2=113570&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PostRAHazardRecognizer.cpp (original) +++ llvm/trunk/lib/CodeGen/PostRAHazardRecognizer.cpp Thu Sep 9 20:29:16 2010 @@ -23,19 +23,19 @@ using namespace llvm; PostRAHazardRecognizer:: -PostRAHazardRecognizer(const InstrItineraryData &LItinData) : +PostRAHazardRecognizer(const InstrItineraryData *LItinData) : ScheduleHazardRecognizer(), ItinData(LItinData) { // Determine the maximum depth of any itinerary. This determines the // depth of the scoreboard. We always make the scoreboard at least 1 // cycle deep to avoid dealing with the boundary condition. unsigned ScoreboardDepth = 1; - if (!ItinData.isEmpty()) { + if (ItinData && !ItinData->isEmpty()) { for (unsigned idx = 0; ; ++idx) { - if (ItinData.isEndMarker(idx)) + if (ItinData->isEndMarker(idx)) break; - const InstrStage *IS = ItinData.beginStage(idx); - const InstrStage *E = ItinData.endStage(idx); + const InstrStage *IS = ItinData->beginStage(idx); + const InstrStage *E = ItinData->endStage(idx); unsigned ItinDepth = 0; for (; IS != E; ++IS) ItinDepth += IS->getCycles(); @@ -74,7 +74,7 @@ ScheduleHazardRecognizer::HazardType PostRAHazardRecognizer::getHazardType(SUnit *SU) { - if (ItinData.isEmpty()) + if (!ItinData || ItinData->isEmpty()) return NoHazard; unsigned cycle = 0; @@ -82,8 +82,8 @@ // Use the itinerary for the underlying instruction to check for // free FU's in the scoreboard at the appropriate future cycles. unsigned idx = SU->getInstr()->getDesc().getSchedClass(); - for (const InstrStage *IS = ItinData.beginStage(idx), - *E = ItinData.endStage(idx); IS != E; ++IS) { + for (const InstrStage *IS = ItinData->beginStage(idx), + *E = ItinData->endStage(idx); IS != E; ++IS) { // We must find one of the stage's units free for every cycle the // stage is occupied. FIXME it would be more accurate to find the // same unit free in all the cycles. @@ -121,7 +121,7 @@ } void PostRAHazardRecognizer::EmitInstruction(SUnit *SU) { - if (ItinData.isEmpty()) + if (!ItinData || ItinData->isEmpty()) return; unsigned cycle = 0; @@ -129,8 +129,8 @@ // Use the itinerary for the underlying instruction to reserve FU's // in the scoreboard at the appropriate future cycles. unsigned idx = SU->getInstr()->getDesc().getSchedClass(); - for (const InstrStage *IS = ItinData.beginStage(idx), - *E = ItinData.endStage(idx); IS != E; ++IS) { + for (const InstrStage *IS = ItinData->beginStage(idx), + *E = ItinData->endStage(idx); IS != E; ++IS) { // We must reserve one of the stage's units for every cycle the // stage is occupied. FIXME it would be more accurate to reserve // the same unit free in all the cycles. Modified: llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp?rev=113570&r1=113569&r2=113570&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp (original) +++ llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp Thu Sep 9 20:29:16 2010 @@ -213,7 +213,7 @@ const MachineLoopInfo &MLI = getAnalysis(); const MachineDominatorTree &MDT = getAnalysis(); const TargetMachine &TM = Fn.getTarget(); - const InstrItineraryData &InstrItins = TM.getInstrItineraryData(); + const InstrItineraryData *InstrItins = TM.getInstrItineraryData(); ScheduleHazardRecognizer *HR = TM.getInstrInfo()->CreateTargetPostRAHazardRecognizer(InstrItins); AntiDepBreaker *ADB = Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=113570&r1=113569&r2=113570&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp (original) +++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Thu Sep 9 20:29:16 2010 @@ -32,9 +32,9 @@ ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf, const MachineLoopInfo &mli, const MachineDominatorTree &mdt) - : ScheduleDAG(mf), MLI(mli), MDT(mdt), Defs(TRI->getNumRegs()), - Uses(TRI->getNumRegs()), LoopRegs(MLI, MDT) { - MFI = mf.getFrameInfo(); + : ScheduleDAG(mf), MLI(mli), MDT(mdt), MFI(mf.getFrameInfo()), + InstrItins(mf.getTarget().getInstrItineraryData()), + Defs(TRI->getNumRegs()), Uses(TRI->getNumRegs()), LoopRegs(MLI, MDT) { DbgValueVec.clear(); } @@ -498,23 +498,22 @@ } void ScheduleDAGInstrs::ComputeLatency(SUnit *SU) { - const InstrItineraryData &InstrItins = TM.getInstrItineraryData(); - // Compute the latency for the node. - SU->Latency = - InstrItins.getStageLatency(SU->getInstr()->getDesc().getSchedClass()); + if (!InstrItins || InstrItins->isEmpty()) { + SU->Latency = 1; - // Simplistic target-independent heuristic: assume that loads take - // extra time. - if (InstrItins.isEmpty()) + // Simplistic target-independent heuristic: assume that loads take + // extra time. if (SU->getInstr()->getDesc().mayLoad()) SU->Latency += 2; + } else + SU->Latency = + InstrItins->getStageLatency(SU->getInstr()->getDesc().getSchedClass()); } void ScheduleDAGInstrs::ComputeOperandLatency(SUnit *Def, SUnit *Use, SDep& dep) const { - const InstrItineraryData &InstrItins = TM.getInstrItineraryData(); - if (InstrItins.isEmpty()) + if (!InstrItins || InstrItins->isEmpty()) return; // For a data dependency with a known register... @@ -528,8 +527,8 @@ MachineInstr *DefMI = Def->getInstr(); int DefIdx = DefMI->findRegisterDefOperandIdx(Reg); if (DefIdx != -1) { - int DefCycle = InstrItins.getOperandCycle(DefMI->getDesc().getSchedClass(), - DefIdx); + int DefCycle = InstrItins->getOperandCycle(DefMI->getDesc().getSchedClass(), + DefIdx); if (DefCycle >= 0) { MachineInstr *UseMI = Use->getInstr(); const unsigned UseClass = UseMI->getDesc().getSchedClass(); @@ -544,7 +543,7 @@ if (MOReg != Reg) continue; - int UseCycle = InstrItins.getOperandCycle(UseClass, i); + int UseCycle = InstrItins->getOperandCycle(UseClass, i); if (UseCycle >= 0) Latency = std::max(Latency, DefCycle - UseCycle + 1); } Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.h?rev=113570&r1=113569&r2=113570&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.h (original) +++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.h Thu Sep 9 20:29:16 2010 @@ -101,6 +101,7 @@ const MachineLoopInfo &MLI; const MachineDominatorTree &MDT; const MachineFrameInfo *MFI; + const InstrItineraryData *InstrItins; /// Defs, Uses - Remember where defs and uses of each physical register /// are as we iterate upward through the instructions. This is allocated Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp?rev=113570&r1=113569&r2=113570&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp Thu Sep 9 20:29:16 2010 @@ -34,8 +34,8 @@ STATISTIC(LoadsClustered, "Number of loads clustered together"); ScheduleDAGSDNodes::ScheduleDAGSDNodes(MachineFunction &mf) - : ScheduleDAG(mf) { -} + : ScheduleDAG(mf), + InstrItins(mf.getTarget().getInstrItineraryData()) {} /// Run - perform scheduling. /// @@ -429,8 +429,7 @@ return; } - const InstrItineraryData &InstrItins = TM.getInstrItineraryData(); - if (InstrItins.isEmpty()) { + if (!InstrItins || InstrItins->isEmpty()) { SU->Latency = 1; return; } @@ -440,7 +439,7 @@ SU->Latency = 0; for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode()) if (N->isMachineOpcode()) { - SU->Latency += InstrItins. + SU->Latency += InstrItins-> getStageLatency(TII->get(N->getMachineOpcode()).getSchedClass()); } } @@ -451,8 +450,7 @@ if (ForceUnitLatencies()) return; - const InstrItineraryData &InstrItins = TM.getInstrItineraryData(); - if (InstrItins.isEmpty()) + if (!InstrItins || InstrItins->isEmpty()) return; if (dep.getKind() != SDep::Data) @@ -463,13 +461,13 @@ const TargetInstrDesc &II = TII->get(Def->getMachineOpcode()); if (DefIdx >= II.getNumDefs()) return; - int DefCycle = InstrItins.getOperandCycle(II.getSchedClass(), DefIdx); + int DefCycle = InstrItins->getOperandCycle(II.getSchedClass(), DefIdx); if (DefCycle < 0) return; int UseCycle = 1; if (Use->isMachineOpcode()) { const unsigned UseClass = TII->get(Use->getMachineOpcode()).getSchedClass(); - UseCycle = InstrItins.getOperandCycle(UseClass, OpIdx); + UseCycle = InstrItins->getOperandCycle(UseClass, OpIdx); } if (UseCycle >= 0) { int Latency = DefCycle - UseCycle + 1; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h?rev=113570&r1=113569&r2=113570&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h Thu Sep 9 20:29:16 2010 @@ -36,6 +36,7 @@ class ScheduleDAGSDNodes : public ScheduleDAG { public: SelectionDAG *DAG; // DAG of the current basic block + const InstrItineraryData *InstrItins; explicit ScheduleDAGSDNodes(MachineFunction &mf); Modified: llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp?rev=113570&r1=113569&r2=113570&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp (original) +++ llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp Thu Sep 9 20:29:16 2010 @@ -416,6 +416,6 @@ // Default implementation of CreateTargetPostRAHazardRecognizer. ScheduleHazardRecognizer *TargetInstrInfoImpl:: -CreateTargetPostRAHazardRecognizer(const InstrItineraryData &II) const { +CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II) const { return (ScheduleHazardRecognizer *)new PostRAHazardRecognizer(II); } Modified: llvm/trunk/lib/Target/ARM/ARM.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=113570&r1=113569&r2=113570&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARM.td (original) +++ llvm/trunk/lib/Target/ARM/ARM.td Thu Sep 9 20:29:16 2010 @@ -91,6 +91,15 @@ include "ARMSchedule.td" +// ARM processor families. +def ProcOthers : SubtargetFeature<"others", "ARMProcFamily", "Others", + "One of the other ARM processor families">; +def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8", + "Cortex-A8 ARM processors", + [FeatureSlowFPBrcc, FeatureNEONForFP]>; +def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9", + "Cortex-A9 ARM processors">; + class ProcNoItin Features> : Processor; @@ -150,10 +159,10 @@ // V7 Processors. def : Processor<"cortex-a8", CortexA8Itineraries, - [ArchV7A, FeatureHasSlowVMLx, - FeatureSlowFPBrcc, FeatureNEONForFP, FeatureT2XtPk]>; + [ArchV7A, ProcA8, + FeatureHasSlowVMLx, FeatureT2XtPk]>; def : Processor<"cortex-a9", CortexA9Itineraries, - [ArchV7A, FeatureT2XtPk]>; + [ArchV7A, ProcA9, FeatureT2XtPk]>; // V7M Processors. def : ProcNoItin<"cortex-m3", [ArchV7M]>; Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=113570&r1=113569&r2=113570&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Thu Sep 9 20:29:16 2010 @@ -1415,13 +1415,13 @@ unsigned ARMBaseInstrInfo::getNumMicroOps(const MachineInstr *MI, - const InstrItineraryData &ItinData) const { - if (ItinData.isEmpty()) + const InstrItineraryData *ItinData) const { + if (!ItinData || ItinData->isEmpty()) return 1; const TargetInstrDesc &Desc = MI->getDesc(); unsigned Class = Desc.getSchedClass(); - unsigned UOps = ItinData.Itineratries[Class].NumMicroOps; + unsigned UOps = ItinData->Itineratries[Class].NumMicroOps; if (UOps) return UOps; @@ -1430,16 +1430,19 @@ default: llvm_unreachable("Unexpected multi-uops instruction!"); break; + case ARM::VLDMQ: case ARM::VSTMQ: return 2; // The number of uOps for load / store multiple are determined by the number // registers. - // On Cortex-A8, each odd / even pair of register loads / stores - // (e.g. r5 + r6) can be completed on the same cycle. The minimum is - // 2. For VFP / NEON load / store multiple, the formula is + // On Cortex-A8, each pair of register loads / stores can be scheduled on the + // same cycle. The scheduling for the first load / store must be done + // separately by assuming the the address is not 64-bit aligned. + // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address + // is not 64-bit aligned, then AGU would take an extra cycle. + // For VFP / NEON load / store multiple, the formula is // (#reg / 2) + (#reg % 2) + 1. - // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). case ARM::VLDMD: case ARM::VLDMS: case ARM::VLDMD_UPD: @@ -1467,11 +1470,24 @@ case ARM::t2LDM_UPD: case ARM::t2STM: case ARM::t2STM_UPD: { - // FIXME: Distinquish between Cortex-A8 / Cortex-A9 and other processor - // families. - unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands(); - UOps = (NumRegs / 2) + (NumRegs % 2); - return (UOps > 2) ? UOps : 2; + unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1; + if (Subtarget.isCortexA8()) { + // 4 registers would be issued: 1, 2, 1. + // 5 registers would be issued: 1, 2, 2. + return 1 + (NumRegs / 2); + } else if (Subtarget.isCortexA9()) { + UOps = (NumRegs / 2); + // If there are odd number of registers or if it's not 64-bit aligned, + // then it takes an extra AGU (Address Generation Unit) cycle. + if ((NumRegs % 2) || + !MI->hasOneMemOperand() || + (*MI->memoperands_begin())->getAlignment() < 8) + ++UOps; + return UOps; + } else { + // Assume the worst. + return NumRegs; + } } } } Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h?rev=113570&r1=113569&r2=113570&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Thu Sep 9 20:29:16 2010 @@ -350,7 +350,7 @@ MachineInstr *CmpInstr) const; virtual unsigned getNumMicroOps(const MachineInstr *MI, - const InstrItineraryData &ItinData) const; + const InstrItineraryData *ItinData) const; }; static inline Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=113570&r1=113569&r2=113570&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Sep 9 20:29:16 2010 @@ -177,6 +177,7 @@ : TargetLowering(TM, createTLOF(TM)) { Subtarget = &TM.getSubtarget(); RegInfo = TM.getRegisterInfo(); + Itins = TM.getInstrItineraryData(); if (Subtarget->isTargetDarwin()) { // Uses VFP for Thumb libfuncs if available. @@ -749,8 +750,7 @@ if (TID.mayLoad()) return Sched::Latency; - const InstrItineraryData &Itins = getTargetMachine().getInstrItineraryData(); - if (!Itins.isEmpty() && Itins.getStageLatency(TID.getSchedClass()) > 2) + if (!Itins->isEmpty() && Itins->getStageLatency(TID.getSchedClass()) > 2) return Sched::Latency; return Sched::RegPressure; } Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=113570&r1=113569&r2=113570&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Thu Sep 9 20:29:16 2010 @@ -301,6 +301,8 @@ const TargetRegisterInfo *RegInfo; + const InstrItineraryData *Itins; + /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created. /// unsigned ARMPCLabelIndex; Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=113570&r1=113569&r2=113570&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Thu Sep 9 20:29:16 2010 @@ -30,6 +30,7 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &FS, bool isT) : ARMArchVersion(V4) + , ARMProcFamily(Others) , ARMFPUType(None) , UseNEONForSinglePrecisionFP(false) , SlowVMLx(false) @@ -50,7 +51,7 @@ , CPUString("generic") , TargetType(isELF) // Default to ELF unless otherwise specified. , TargetABI(ARM_ABI_APCS) { - // default to soft float ABI + // Default to soft float ABI if (FloatABIType == FloatABI::Default) FloatABIType = FloatABI::Soft; Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=113570&r1=113569&r2=113570&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original) +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Thu Sep 9 20:29:16 2010 @@ -29,6 +29,10 @@ V4, V4T, V5T, V5TE, V6, V6M, V6T2, V7A, V7M }; + enum ARMProcFamilyEnum { + Others, CortexA8, CortexA9 + }; + enum ARMFPEnum { None, VFPv2, VFPv3, NEON }; @@ -42,6 +46,9 @@ /// V6, V6T2, V7A, V7M. ARMArchEnum ARMArchVersion; + /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others. + ARMProcFamilyEnum ARMProcFamily; + /// ARMFPUType - Floating Point Unit type. ARMFPEnum ARMFPUType; @@ -143,6 +150,9 @@ bool hasV6T2Ops() const { return ARMArchVersion >= V6T2; } bool hasV7Ops() const { return ARMArchVersion >= V7A; } + bool isCortexA8() const { return ARMProcFamily == CortexA8; } + bool isCortexA9() const { return ARMProcFamily == CortexA9; } + bool hasARMOps() const { return !NoARM; } bool hasVFP2() const { return ARMFPUType >= VFPv2; } Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.h?rev=113570&r1=113569&r2=113570&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.h (original) +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.h Thu Sep 9 20:29:16 2010 @@ -45,8 +45,8 @@ virtual const ARMFrameInfo *getFrameInfo() const { return &FrameInfo; } virtual ARMJITInfo *getJITInfo() { return &JITInfo; } virtual const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; } - virtual const InstrItineraryData getInstrItineraryData() const { - return InstrItins; + virtual const InstrItineraryData *getInstrItineraryData() const { + return &InstrItins; } // Pass Pipeline Configuration Modified: llvm/trunk/lib/Target/ARM/Thumb2HazardRecognizer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2HazardRecognizer.h?rev=113570&r1=113569&r2=113570&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb2HazardRecognizer.h (original) +++ llvm/trunk/lib/Target/ARM/Thumb2HazardRecognizer.h Thu Sep 9 20:29:16 2010 @@ -26,7 +26,7 @@ MachineInstr *ITBlockMIs[4]; public: - Thumb2HazardRecognizer(const InstrItineraryData &ItinData) : + Thumb2HazardRecognizer(const InstrItineraryData *ItinData) : PostRAHazardRecognizer(ItinData) {} virtual HazardType getHazardType(SUnit *SU); Modified: llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp?rev=113570&r1=113569&r2=113570&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp Thu Sep 9 20:29:16 2010 @@ -194,7 +194,7 @@ } ScheduleHazardRecognizer *Thumb2InstrInfo:: -CreateTargetPostRAHazardRecognizer(const InstrItineraryData &II) const { +CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II) const { return (ScheduleHazardRecognizer *)new Thumb2HazardRecognizer(II); } Modified: llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.h?rev=113570&r1=113569&r2=113570&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.h (original) +++ llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.h Thu Sep 9 20:29:16 2010 @@ -72,7 +72,7 @@ const Thumb2RegisterInfo &getRegisterInfo() const { return RI; } ScheduleHazardRecognizer * - CreateTargetPostRAHazardRecognizer(const InstrItineraryData &II) const; + CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II) const; }; /// getITInstrPredicate - Valid only in Thumb2 mode. This function is identical Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h?rev=113570&r1=113569&r2=113570&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h (original) +++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h Thu Sep 9 20:29:16 2010 @@ -75,8 +75,8 @@ return &DataLayout; } - virtual const InstrItineraryData getInstrItineraryData() const { - return InstrItins; + virtual const InstrItineraryData *getInstrItineraryData() const { + return &InstrItins; } // Pass Pipeline Configuration Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h?rev=113570&r1=113569&r2=113570&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h (original) +++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h Thu Sep 9 20:29:16 2010 @@ -58,8 +58,8 @@ virtual const TargetData *getTargetData() const { return &DataLayout; } virtual const PPCSubtarget *getSubtargetImpl() const { return &Subtarget; } - virtual const InstrItineraryData getInstrItineraryData() const { - return InstrItins; + virtual const InstrItineraryData *getInstrItineraryData() const { + return &InstrItins; } // Pass Pipeline Configuration Modified: llvm/trunk/lib/Target/TargetInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetInstrInfo.cpp?rev=113570&r1=113569&r2=113570&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/TargetInstrInfo.cpp Thu Sep 9 20:29:16 2010 @@ -50,12 +50,12 @@ unsigned TargetInstrInfo::getNumMicroOps(const MachineInstr *MI, - const InstrItineraryData &ItinData) const { - if (ItinData.isEmpty()) + const InstrItineraryData *ItinData) const { + if (!ItinData || ItinData->isEmpty()) return 1; unsigned Class = MI->getDesc().getSchedClass(); - unsigned UOps = ItinData.Itineratries[Class].NumMicroOps; + unsigned UOps = ItinData->Itineratries[Class].NumMicroOps; if (UOps) return UOps; Added: llvm/trunk/test/CodeGen/ARM/ifcvt10.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ifcvt10.ll?rev=113570&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/ifcvt10.ll (added) +++ llvm/trunk/test/CodeGen/ARM/ifcvt10.ll Thu Sep 9 20:29:16 2010 @@ -0,0 +1,30 @@ +; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s +; rdar://8402126 +; Make sure if-converter is not predicating vldmia and ldmia. These are +; micro-coded and would have long issue latency even if predicated on +; false predicate. + +%0 = type { float, float, float, float } +%pln = type { %vec, float } +%vec = type { [4 x float] } + +define arm_aapcs_vfpcc float @aaa(%vec* nocapture %ustart, %vec* nocapture %udir, %vec* nocapture %vstart, %vec* nocapture %vdir, %vec* %upoint, %vec* %vpoint) { +; CHECK: aaa: +; CHECK: vldr.32 +; CHECK-NOT: vldrne +; CHECK-NOT: vldmiane +; CHECK-NOT: ldmiane +; CHECK: vldmia sp! +; CHECK: ldmia sp! +entry: + br i1 undef, label %bb81, label %bb48 + +bb48: ; preds = %entry + %0 = call arm_aapcs_vfpcc %0 @bbb(%pln* undef, %vec* %vstart, %vec* undef) nounwind ; <%0> [#uses=0] + ret float 0.000000e+00 + +bb81: ; preds = %entry + ret float 0.000000e+00 +} + +declare arm_aapcs_vfpcc %0 @bbb(%pln* nocapture, %vec* nocapture, %vec* nocapture) nounwind Modified: llvm/trunk/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll?rev=113570&r1=113569&r2=113570&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll Thu Sep 9 20:29:16 2010 @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -O3 -relocation-model=pic -mcpu=cortex-a8 | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -O3 -relocation-model=pic | FileCheck %s ; rdar://8115404 ; Tail merging must not split an IT block. From deeppatel1987 at gmail.com Thu Sep 9 21:33:15 2010 From: deeppatel1987 at gmail.com (Sandeep Patel) Date: Fri, 10 Sep 2010 02:33:15 +0000 Subject: [llvm-commits] [llvm-gcc][arm][patch] Lower function signatures a bit more In-Reply-To: References: <386B2A85-DD45-4217-BE7A-FAE01B59A23B@apple.com> Message-ID: On Fri, Sep 10, 2010 at 1:15 AM, Rafael Espindola wrote: >> Great, I was worried that the "long" IR wouldn't be pattern matched back into good machine code. ?I think this is a great idea, doing it in clang would really be appreciated! > > Sure. Will give it a try when we start using clang. Maybe a bit earlier :-) > > So, how do I test this for hard float? If I understand the config > macros correctly, the check > > ?if (TARGET_HARD_FLOAT_ABI) > ? return false; > > should keep the results unchanged for hard float. FSF GCC (DragonEgg) has an__attribute__((pcs("aapcs-vfp"))) that could give you a hard float function without TARGET_HARD_FLOAT_ABI being set. I haven't yet added this attribute to llvm-gcc or clang yet until there's a clear need. Sorry, but I don't have a hard float system to offer for testing at this time. I did the ABI work partly using a Beagleboard and booting it directly into each program with a customized newlib. GCC also has test cases for various parts of the ABI that can be compiled and manually inspected, which is what I did for many cases. They're in gcc/testsuite/gcc.target/arm/aapcs and they're far from complete. deep From espindola at google.com Thu Sep 9 22:23:56 2010 From: espindola at google.com (Rafael Espindola) Date: Thu, 9 Sep 2010 23:23:56 -0400 Subject: [llvm-commits] [llvm-gcc][arm][patch] Lower function signatures a bit more In-Reply-To: References: <386B2A85-DD45-4217-BE7A-FAE01B59A23B@apple.com> Message-ID: > FSF GCC (DragonEgg) has an__attribute__((pcs("aapcs-vfp"))) that could > give you a hard float function without TARGET_HARD_FLOAT_ABI being > set. I haven't yet added this attribute to llvm-gcc or clang yet until > there's a clear need. I don't see that being used in any part of llvm-arm.cpp, for example, bool llvm_arm_should_pass_or_return_aggregate_in_regs(tree TreeType, CallingConv::ID &CC) { // Homogeneous aggregates are an AAPCS-VFP feature. if ((CC != CallingConv::ARM_AAPCS_VFP) || !(TARGET_AAPCS_BASED && TARGET_VFP && TARGET_HARD_FLOAT_ABI)) return false; So checking TARGET_HARD_FLOAT_ABI is probably consistent with what the rest of the file does right now. I don't see gcc/testsuite/gcc.target/arm/aapcs in llvm-gcc, only in vanilla gcc... > deep > Cheers, -- Rafael ?vila de Esp?ndola From clattner at apple.com Fri Sep 10 00:03:16 2010 From: clattner at apple.com (Chris Lattner) Date: Thu, 9 Sep 2010 22:03:16 -0700 Subject: [llvm-commits] [llvm] r113557 - in /llvm/trunk: include/llvm/Bitcode/LLVMBitCodes.h lib/Bitcode/Reader/BitcodeReader.cpp lib/Bitcode/Writer/BitcodeWriter.cpp tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp In-Reply-To: <20100909231239.593462A6C12C@llvm.org> References: <20100909231239.593462A6C12C@llvm.org> Message-ID: <9CEA1823-AE4D-47EA-94A3-DCE60F5EC868@apple.com> On Sep 9, 2010, at 4:12 PM, Dan Gohman wrote: > Author: djg > Date: Thu Sep 9 18:12:39 2010 > New Revision: 113557 > > URL: http://llvm.org/viewvc/llvm-project?rev=113557&view=rev > Log: > Discard metadata produced by LLVM 2.7. The value enumeration it used > is different from what the code now uses in a two ways: NamedMDNodes > were considered Values and included in the numbering, and the > function-local metadata counter wasn't reset between functions. > > The later problem breaks lazy deserialization, so instead of trying > to emulate the old numbering, just drop the old metadata. The only > in-tree use case is debug info with LTO, where the QOI loss is > considered acceptable. Hi Dan, Is it possible to only do this for function local metadata, or is there no way to detect it? -Chris > > Modified: > llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h > llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp > llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp > llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp > > Modified: llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h?rev=113557&r1=113556&r2=113557&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h (original) > +++ llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h Thu Sep 9 18:12:39 2010 > @@ -110,12 +110,20 @@ > > enum MetadataCodes { > METADATA_STRING = 1, // MDSTRING: [values] > - METADATA_NODE = 2, // MDNODE: [n x (type num, value num)] > - METADATA_FN_NODE = 3, // FN_MDNODE: [n x (type num, value num)] > + // FIXME: Remove NODE in favor of NODE2 in LLVM 3.0 > + METADATA_NODE = 2, // NODE with potentially invalid metadata > + // FIXME: Remove FN_NODE in favor of FN_NODE2 in LLVM 3.0 > + METADATA_FN_NODE = 3, // FN_NODE with potentially invalid metadata > METADATA_NAME = 4, // STRING: [values] > - METADATA_NAMED_NODE = 5, // NAMEDMDNODE: [n x mdnodes] > + // FIXME: Remove NAMED_NODE in favor of NAMED_NODE2 in LLVM 3.0 > + METADATA_NAMED_NODE = 5, // NAMED_NODE with potentially invalid metadata > METADATA_KIND = 6, // [n x [id, name]] > - METADATA_ATTACHMENT = 7 // [m x [value, [n x [id, mdnode]]] > + // FIXME: Remove ATTACHMENT in favor of ATTACHMENT2 in LLVM 3.0 > + METADATA_ATTACHMENT = 7, // ATTACHMENT with potentially invalid metadata > + METADATA_NODE2 = 8, // NODE2: [n x (type num, value num)] > + METADATA_FN_NODE2 = 9, // FN_NODE2: [n x (type num, value num)] > + METADATA_NAMED_NODE2 = 10, // NAMED_NODE2: [n x mdnodes] > + METADATA_ATTACHMENT2 = 11 // [m x [value, [n x [id, mdnode]]] > }; > // The constants block (CONSTANTS_BLOCK_ID) describes emission for each > // constant and maintains an implicit current type value. > @@ -223,7 +231,8 @@ > FUNC_CODE_INST_LOAD = 20, // LOAD: [opty, op, align, vol] > // FIXME: Remove STORE in favor of STORE2 in LLVM 3.0 > FUNC_CODE_INST_STORE = 21, // STORE: [valty,val,ptr, align, vol] > - FUNC_CODE_INST_CALL = 22, // CALL: [attr, fnty, fnid, args...] > + // FIXME: Remove CALL in favor of CALL2 in LLVM 3.0 > + FUNC_CODE_INST_CALL = 22, // CALL with potentially invalid metadata > FUNC_CODE_INST_VAARG = 23, // VAARG: [valistty, valist, instty] > // This store code encodes the pointer type, rather than the value type > // this is so information only available in the pointer type (e.g. address > @@ -241,8 +250,13 @@ > FUNC_CODE_INST_INBOUNDS_GEP= 30, // INBOUNDS_GEP: [n x operands] > FUNC_CODE_INST_INDIRECTBR = 31, // INDIRECTBR: [opty, op0, op1, ...] > > - FUNC_CODE_DEBUG_LOC = 32, // DEBUG_LOC: [Line,Col,ScopeVal, IAVal] > - FUNC_CODE_DEBUG_LOC_AGAIN = 33 // DEBUG_LOC_AGAIN > + // FIXME: Remove DEBUG_LOC in favor of DEBUG_LOC2 in LLVM 3.0 > + FUNC_CODE_DEBUG_LOC = 32, // DEBUG_LOC with potentially invalid metadata > + FUNC_CODE_DEBUG_LOC_AGAIN = 33, // DEBUG_LOC_AGAIN > + > + FUNC_CODE_INST_CALL2 = 34, // CALL2: [attr, fnty, fnid, args...] > + > + FUNC_CODE_DEBUG_LOC2 = 35 // DEBUG_LOC2: [Line,Col,ScopeVal, IAVal] > }; > } // End bitc namespace > } // End llvm namespace > > Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp?rev=113557&r1=113556&r2=113557&view=diff > ============================================================================== > --- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp (original) > +++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp Thu Sep 9 18:12:39 2010 > @@ -786,8 +786,12 @@ > Record.clear(); > Code = Stream.ReadCode(); > > - // METADATA_NAME is always followed by METADATA_NAMED_NODE. > - if (Stream.ReadRecord(Code, Record) != bitc::METADATA_NAMED_NODE) > + // METADATA_NAME is always followed by METADATA_NAMED_NODE2. > + unsigned NextBitCode = Stream.ReadRecord(Code, Record); > + // FIXME: LLVM 3.0: Remove this. > + if (NextBitCode == bitc::METADATA_NAMED_NODE) > + break; > + if (NextBitCode != bitc::METADATA_NAMED_NODE2) > assert ( 0 && "Inavlid Named Metadata record"); > > // Read named metadata elements. > @@ -802,11 +806,19 @@ > break; > } > case bitc::METADATA_FN_NODE: > + // FIXME: Legacy support for the old fn_node, where function-local > + // metadata operands were bogus. Remove in LLVM 3.0. > + break; > + case bitc::METADATA_NODE: > + // FIXME: Legacy support for the old node, where function-local > + // metadata operands were bogus. Remove in LLVM 3.0. > + break; > + case bitc::METADATA_FN_NODE2: > IsFunctionLocal = true; > // fall-through > - case bitc::METADATA_NODE: { > + case bitc::METADATA_NODE2: { > if (Record.size() % 2 == 1) > - return Error("Invalid METADATA_NODE record"); > + return Error("Invalid METADATA_NODE2 record"); > > unsigned Size = Record.size(); > SmallVector Elts; > @@ -1593,7 +1605,10 @@ > switch (Stream.ReadRecord(Code, Record)) { > default: // Default behavior: ignore. > break; > - case bitc::METADATA_ATTACHMENT: { > + case bitc::METADATA_ATTACHMENT: > + // LLVM 3.0: Remove this. > + break; > + case bitc::METADATA_ATTACHMENT2: { > unsigned RecordLength = Record.size(); > if (Record.empty() || (RecordLength - 1) % 2 == 1) > return Error ("Invalid METADATA_ATTACHMENT reader!"); > @@ -1706,7 +1721,11 @@ > I = 0; > continue; > > - case bitc::FUNC_CODE_DEBUG_LOC: { // DEBUG_LOC: [line, col, scope, ia] > + case bitc::FUNC_CODE_DEBUG_LOC: > + // FIXME: Ignore. Remove this in LLVM 3.0. > + continue; > + > + case bitc::FUNC_CODE_DEBUG_LOC2: { // DEBUG_LOC: [line, col, scope, ia] > I = 0; // Get the last instruction emitted. > if (CurBB && !CurBB->empty()) > I = &CurBB->back(); > @@ -2221,7 +2240,12 @@ > InstructionList.push_back(I); > break; > } > - case bitc::FUNC_CODE_INST_CALL: { > + case bitc::FUNC_CODE_INST_CALL: > + case bitc::FUNC_CODE_INST_CALL2: { > + // FIXME: Legacy support for the old call instruction, where function-local > + // metadata operands were bogus. Remove in LLVM 3.0. > + bool DropMetadata = BitCode == bitc::FUNC_CODE_INST_CALL; > + > // CALL: [paramattrs, cc, fnty, fnid, arg0, arg1...] > if (Record.size() < 3) > return Error("Invalid CALL record"); > @@ -2245,7 +2269,13 @@ > for (unsigned i = 0, e = FTy->getNumParams(); i != e; ++i, ++OpNum) { > if (FTy->getParamType(i)->getTypeID()==Type::LabelTyID) > Args.push_back(getBasicBlock(Record[OpNum])); > - else > + else if (DropMetadata && > + FTy->getParamType(i)->getTypeID()==Type::MetadataTyID) { > + // LLVM 2.7 compatibility: drop metadata arguments to null. > + Value *Ops = 0; > + Args.push_back(MDNode::get(Context, &Ops, 1)); > + continue; > + } else > Args.push_back(getFnValueByID(Record[OpNum], FTy->getParamType(i))); > if (Args.back() == 0) return Error("Invalid CALL record"); > } > > Modified: llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp?rev=113557&r1=113556&r2=113557&view=diff > ============================================================================== > --- llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp (original) > +++ llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp Thu Sep 9 18:12:39 2010 > @@ -485,8 +485,8 @@ > Record.push_back(0); > } > } > - unsigned MDCode = N->isFunctionLocal() ? bitc::METADATA_FN_NODE : > - bitc::METADATA_NODE; > + unsigned MDCode = N->isFunctionLocal() ? bitc::METADATA_FN_NODE2 : > + bitc::METADATA_NODE2; > Stream.EmitRecord(MDCode, Record, 0); > Record.clear(); > } > @@ -549,7 +549,7 @@ > // Write named metadata operands. > for (unsigned i = 0, e = NMD->getNumOperands(); i != e; ++i) > Record.push_back(VE.getValueID(NMD->getOperand(i))); > - Stream.EmitRecord(bitc::METADATA_NAMED_NODE, Record, 0); > + Stream.EmitRecord(bitc::METADATA_NAMED_NODE2, Record, 0); > Record.clear(); > } > > @@ -585,7 +585,7 @@ > SmallVector Record; > > // Write metadata attachments > - // METADATA_ATTACHMENT - [m x [value, [n x [id, mdnode]]] > + // METADATA_ATTACHMENT2 - [m x [value, [n x [id, mdnode]]] > SmallVector, 4> MDs; > > for (Function::const_iterator BB = F.begin(), E = F.end(); BB != E; ++BB) > @@ -603,7 +603,7 @@ > Record.push_back(MDs[i].first); > Record.push_back(VE.getValueID(MDs[i].second)); > } > - Stream.EmitRecord(bitc::METADATA_ATTACHMENT, Record, 0); > + Stream.EmitRecord(bitc::METADATA_ATTACHMENT2, Record, 0); > Record.clear(); > } > > @@ -1111,7 +1111,7 @@ > const PointerType *PTy = cast(CI.getCalledValue()->getType()); > const FunctionType *FTy = cast(PTy->getElementType()); > > - Code = bitc::FUNC_CODE_INST_CALL; > + Code = bitc::FUNC_CODE_INST_CALL2; > > Vals.push_back(VE.getAttributeID(CI.getAttributes())); > Vals.push_back((CI.getCallingConv() << 1) | unsigned(CI.isTailCall())); > @@ -1255,7 +1255,7 @@ > Vals.push_back(DL.getCol()); > Vals.push_back(Scope ? VE.getValueID(Scope)+1 : 0); > Vals.push_back(IA ? VE.getValueID(IA)+1 : 0); > - Stream.EmitRecord(bitc::FUNC_CODE_DEBUG_LOC, Vals); > + Stream.EmitRecord(bitc::FUNC_CODE_DEBUG_LOC2, Vals); > Vals.clear(); > > LastDL = DL; > > Modified: llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp?rev=113557&r1=113556&r2=113557&view=diff > ============================================================================== > --- llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp (original) > +++ llvm/trunk/tools/llvm-bcanalyzer/llvm-bcanalyzer.cpp Thu Sep 9 18:12:39 2010 > @@ -236,6 +236,8 @@ > case bitc::FUNC_CODE_INST_VSELECT: return "INST_VSELECT"; > case bitc::FUNC_CODE_DEBUG_LOC: return "DEBUG_LOC"; > case bitc::FUNC_CODE_DEBUG_LOC_AGAIN: return "DEBUG_LOC_AGAIN"; > + case bitc::FUNC_CODE_INST_CALL2: return "INST_CALL2"; > + case bitc::FUNC_CODE_DEBUG_LOC2: return "DEBUG_LOC2"; > } > case bitc::TYPE_SYMTAB_BLOCK_ID: > switch (CodeID) { > @@ -263,6 +265,10 @@ > case bitc::METADATA_NAMED_NODE: return "METADATA_NAMED_NODE"; > case bitc::METADATA_KIND: return "METADATA_KIND"; > case bitc::METADATA_ATTACHMENT: return "METADATA_ATTACHMENT"; > + case bitc::METADATA_NODE2: return "METADATA_NODE2"; > + case bitc::METADATA_FN_NODE2: return "METADATA_FN_NODE2"; > + case bitc::METADATA_NAMED_NODE2: return "METADATA_NAMED_NODE2"; > + case bitc::METADATA_ATTACHMENT2: return "METADATA_ATTACHMENT2"; > } > } > } > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From bob.wilson at apple.com Fri Sep 10 00:15:04 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Fri, 10 Sep 2010 05:15:04 -0000 Subject: [llvm-commits] [llvm] r113576 - in /llvm/trunk: lib/Target/ARM/ARMLoadStoreOptimizer.cpp test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll Message-ID: <20100910051504.9175F2A6C12C@llvm.org> Author: bwilson Date: Fri Sep 10 00:15:04 2010 New Revision: 113576 URL: http://llvm.org/viewvc/llvm-project?rev=113576&view=rev Log: Fix merging base-updates for VLDM/VSTM: Before I switched these instructions to use AddrMode4, there was a count of the registers stored in one of the operands. I changed that to just count the operands but forgot to adjust for the size of D registers. This was noticed by Evan as a performance problem but it is a potential correctness bug as well, since it is possible that this could merge a base update with a non-matching immediate. Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp llvm/trunk/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=113576&r1=113575&r2=113576&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Fri Sep 10 00:15:04 2010 @@ -458,9 +458,10 @@ case ARM::t2STM: case ARM::VLDMS: case ARM::VSTMS: + return (MI->getNumOperands() - 4) * 4; case ARM::VLDMD: case ARM::VSTMD: - return (MI->getNumOperands() - 4) * 4; + return (MI->getNumOperands() - 4) * 8; } } Modified: llvm/trunk/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll?rev=113576&r1=113575&r2=113576&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll (original) +++ llvm/trunk/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll Fri Sep 10 00:15:04 2010 @@ -1,11 +1,15 @@ -; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 +; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 | FileCheck %s @quant_coef = external global [6 x [4 x [4 x i32]]] ; <[6 x [4 x [4 x i32]]]*> [#uses=1] @dequant_coef = external global [6 x [4 x [4 x i32]]] ; <[6 x [4 x [4 x i32]]]*> [#uses=1] @A = external global [4 x [4 x i32]] ; <[4 x [4 x i32]]*> [#uses=1] +; CHECK: dct_luma_sp: define fastcc i32 @dct_luma_sp(i32 %block_x, i32 %block_y, i32* %coeff_cost) { entry: +; Make sure to use base-updating stores for saving callee-saved registers. +; CHECK-NOT: sub sp +; CHECK: vstmdb sp! %predicted_block = alloca [4 x [4 x i32]], align 4 ; <[4 x [4 x i32]]*> [#uses=1] br label %cond_next489 From stoklund at 2pi.dk Fri Sep 10 00:50:18 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 9 Sep 2010 22:50:18 -0700 Subject: [llvm-commits] [llvm] r113570 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ lib/Target/ARM/ lib/Target/CellSPU/ lib/Target/PowerPC/ test/CodeGen/ARM/ test/CodeGen/Thumb2/ In-Reply-To: <20100910012917.6A2C42A6C12C@llvm.org> References: <20100910012917.6A2C42A6C12C@llvm.org> Message-ID: <25D74F97-E815-4801-97B4-6B886ECF1911@2pi.dk> Hi Evan, The test you added is failing on all the non-darwin testers. Please take a look. /jakob On Sep 9, 2010, at 6:29 PM, Evan Cheng wrote: > llvm/trunk/test/CodeGen/ARM/ifcvt10.ll From evan.cheng at apple.com Fri Sep 10 00:54:24 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 09 Sep 2010 22:54:24 -0700 Subject: [llvm-commits] [llvm] r113570 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ lib/Target/ARM/ lib/Target/CellSPU/ lib/Target/PowerPC/ test/CodeGen/ARM/ test/CodeGen/Thumb2/ In-Reply-To: <25D74F97-E815-4801-97B4-6B886ECF1911@2pi.dk> References: <20100910012917.6A2C42A6C12C@llvm.org> <25D74F97-E815-4801-97B4-6B886ECF1911@2pi.dk> Message-ID: <1C003828-B85A-4691-9B22-F4E76BCE5477@apple.com> Sorry I can't do anything about it now. Can you add a triplet to the test line? That should fix it. Thanks, Evan On Sep 9, 2010, at 10:50 PM, Jakob Stoklund Olesen wrote: > Hi Evan, > > The test you added is failing on all the non-darwin testers. Please take a look. > > /jakob > > On Sep 9, 2010, at 6:29 PM, Evan Cheng wrote: > >> llvm/trunk/test/CodeGen/ARM/ifcvt10.ll From deeppatel1987 at gmail.com Fri Sep 10 01:02:55 2010 From: deeppatel1987 at gmail.com (Sandeep Patel) Date: Fri, 10 Sep 2010 06:02:55 +0000 Subject: [llvm-commits] [llvm-gcc][arm][patch] Lower function signatures a bit more In-Reply-To: References: <386B2A85-DD45-4217-BE7A-FAE01B59A23B@apple.com> Message-ID: On Fri, Sep 10, 2010 at 3:23 AM, Rafael Espindola wrote: >> FSF GCC (DragonEgg) has an__attribute__((pcs("aapcs-vfp"))) that could >> give you a hard float function without TARGET_HARD_FLOAT_ABI being >> set. I haven't yet added this attribute to llvm-gcc or clang yet until >> there's a clear need. > > I don't see that being used in any part of llvm-arm.cpp, for example, > > bool llvm_arm_should_pass_or_return_aggregate_in_regs(tree TreeType, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?CallingConv::ID &CC) { > ?// Homogeneous aggregates are an AAPCS-VFP feature. > ?if ((CC != CallingConv::ARM_AAPCS_VFP) || > ? ? ?!(TARGET_AAPCS_BASED && TARGET_VFP && TARGET_HARD_FLOAT_ABI)) > ? ?return false; > > So checking ?TARGET_HARD_FLOAT_ABI is probably consistent with what > the rest of the file does right now. Correct, as I said, I haven't ported this feature over, but you should be aware of it. > I don't see gcc/testsuite/gcc.target/arm/aapcs in llvm-gcc, only in > vanilla gcc... Correct. But if you want to test hard float, that's the only publicly available test suite. I asked ARM and they have nothing to offer here to help. deep From evan.cheng at apple.com Fri Sep 10 01:20:01 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 10 Sep 2010 06:20:01 -0000 Subject: [llvm-commits] [llvm] r113577 - /llvm/trunk/test/CodeGen/ARM/ifcvt10.ll Message-ID: <20100910062001.45CF92A6C12C@llvm.org> Author: evancheng Date: Fri Sep 10 01:20:01 2010 New Revision: 113577 URL: http://llvm.org/viewvc/llvm-project?rev=113577&view=rev Log: Fix test so it passes on non-Darwin hosts. Modified: llvm/trunk/test/CodeGen/ARM/ifcvt10.ll Modified: llvm/trunk/test/CodeGen/ARM/ifcvt10.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ifcvt10.ll?rev=113577&r1=113576&r2=113577&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/ifcvt10.ll (original) +++ llvm/trunk/test/CodeGen/ARM/ifcvt10.ll Fri Sep 10 01:20:01 2010 @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s +; RUN: llc < %s -mtriple=arm-apple-darwin -mcpu=cortex-a8 | FileCheck %s ; rdar://8402126 ; Make sure if-converter is not predicating vldmia and ldmia. These are ; micro-coded and would have long issue latency even if predicated on From evan.cheng at apple.com Fri Sep 10 01:21:28 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 09 Sep 2010 23:21:28 -0700 Subject: [llvm-commits] [llvm] r113570 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ lib/Target/ARM/ lib/Target/CellSPU/ lib/Target/PowerPC/ test/CodeGen/ARM/ test/CodeGen/Thumb2/ In-Reply-To: <25D74F97-E815-4801-97B4-6B886ECF1911@2pi.dk> References: <20100910012917.6A2C42A6C12C@llvm.org> <25D74F97-E815-4801-97B4-6B886ECF1911@2pi.dk> Message-ID: <10A6A1EC-67DB-4847-9BA9-13563762ACF2@apple.com> Hopefully fixed now. Evan On Sep 9, 2010, at 10:50 PM, Jakob Stoklund Olesen wrote: > Hi Evan, > > The test you added is failing on all the non-darwin testers. Please take a look. > > /jakob > > On Sep 9, 2010, at 6:29 PM, Evan Cheng wrote: > >> llvm/trunk/test/CodeGen/ARM/ifcvt10.ll From geek4civic at gmail.com Fri Sep 10 01:26:58 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Fri, 10 Sep 2010 06:26:58 -0000 Subject: [llvm-commits] [llvm] r113578 - /llvm/trunk/tools/gold/Makefile Message-ID: <20100910062658.1A1012A6C12C@llvm.org> Author: chapuni Date: Fri Sep 10 01:26:57 2010 New Revision: 113578 URL: http://llvm.org/viewvc/llvm-project?rev=113578&view=rev Log: Don't build redundant libLLVMgold.a. Building archive would be executed due to definition of BUILD_ARCHIVE, even if BUILD_ARCHIVE = "0". Modified: llvm/trunk/tools/gold/Makefile Modified: llvm/trunk/tools/gold/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/gold/Makefile?rev=113578&r1=113577&r2=113578&view=diff ============================================================================== --- llvm/trunk/tools/gold/Makefile (original) +++ llvm/trunk/tools/gold/Makefile Fri Sep 10 01:26:57 2010 @@ -19,7 +19,6 @@ LINK_LIBS_IN_SHARED=1 SHARED_LIBRARY = 1 -BUILD_ARCHIVE = 0 LOADABLE_MODULE = 1 LINK_COMPONENTS := support system From geek4civic at gmail.com Fri Sep 10 01:27:02 2010 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Fri, 10 Sep 2010 06:27:02 -0000 Subject: [llvm-commits] [llvm] r113579 - /llvm/trunk/Makefile.rules Message-ID: <20100910062702.DC5652A6C12D@llvm.org> Author: chapuni Date: Fri Sep 10 01:27:02 2010 New Revision: 113579 URL: http://llvm.org/viewvc/llvm-project?rev=113579&view=rev Log: Makefile.rules: LOADABLE_MODULE/Win32: "all" components may be linked only when ENABLE_SHARED=1. Loadable module for Win32 requires all symbols resolved for linking. Modified: llvm/trunk/Makefile.rules Modified: llvm/trunk/Makefile.rules URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=113579&r1=113578&r2=113579&view=diff ============================================================================== --- llvm/trunk/Makefile.rules (original) +++ llvm/trunk/Makefile.rules Fri Sep 10 01:27:02 2010 @@ -894,10 +894,13 @@ LLVMLibsPaths := $(addprefix $(LLVMLibDir)/,$(LLVMUsedLibs)) endif -# Win32.DLL may refer to other components. -ifeq ($(HOST_OS), $(filter $(HOST_OS), Cygwin MingW)) +# Loadable module for Win32 requires all symbols resolved for linking. +# Then all symbols in LLVM.dll will be available. +ifeq ($(ENABLE_SHARED),1) ifdef LOADABLE_MODULE - LINK_COMPONENTS := all + ifneq (,$(filter $(HOST_OS),Cygwin MingW)) + LINK_COMPONENTS += all + endif endif endif From echristo at apple.com Fri Sep 10 01:38:46 2010 From: echristo at apple.com (Eric Christopher) Date: Thu, 9 Sep 2010 23:38:46 -0700 Subject: [llvm-commits] [llvm] r113576 - in /llvm/trunk: lib/Target/ARM/ARMLoadStoreOptimizer.cpp test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll In-Reply-To: <20100910051504.9175F2A6C12C@llvm.org> References: <20100910051504.9175F2A6C12C@llvm.org> Message-ID: <864CDCA7-5AE0-42D3-8E88-FB45FA4515A3@apple.com> On Sep 9, 2010, at 10:15 PM, Bob Wilson wrote: > to use AddrMode4, there was a count of the registers stored in one of the > operands. I changed that to just count the operands but forgot to adjust for > the size of D registers. This was noticed by Evan as a performance problem > but it is a potential correctness bug as well, since it is possible that this > could merge a base update with a non-matching immediate. > > Modified: > llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp > llvm/trunk/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll > > Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=113576&r1=113575&r2=113576&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Fri Sep 10 00:15:04 2010 > @@ -458,9 +458,10 @@ > case ARM::t2STM: > case ARM::VLDMS: > case ARM::VSTMS: > + return (MI->getNumOperands() - 4) * 4; > case ARM::VLDMD: > case ARM::VSTMD: > - return (MI->getNumOperands() - 4) * 4; > + return (MI->getNumOperands() - 4) * 8; Perhaps less magic numbers? -eric From evan.cheng at apple.com Fri Sep 10 01:49:55 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 9 Sep 2010 23:49:55 -0700 Subject: [llvm-commits] [llvm] r112741 - /llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp In-Reply-To: <20100901210427.9497B2A6C12C@llvm.org> References: <20100901210427.9497B2A6C12C@llvm.org> Message-ID: To me it seems like tri_->getAllocatableSet(fn), allocation_order_begin, allocation_order_end should not include reserved registers. After all, their names implied as such. Wouldn't every register allocator needs to do the same check? Evan On Sep 1, 2010, at 2:04 PM, Jim Grosbach wrote: > Author: grosbach > Date: Wed Sep 1 16:04:27 2010 > New Revision: 112741 > > URL: http://llvm.org/viewvc/llvm-project?rev=112741&view=rev > Log: > The register allocator shouldn't consider allocating reserved registers. > r112728 did this for fast regalloc. > > Modified: > llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp > > Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp?rev=112741&r1=112740&r2=112741&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp (original) > +++ llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Wed Sep 1 16:04:27 2010 > @@ -125,6 +125,7 @@ > const TargetRegisterInfo* tri_; > const TargetInstrInfo* tii_; > BitVector allocatableRegs_; > + BitVector reservedRegs_; > LiveIntervals* li_; > LiveStacks* ls_; > MachineLoopInfo *loopInfo; > @@ -464,6 +465,7 @@ > tri_ = tm_->getRegisterInfo(); > tii_ = tm_->getInstrInfo(); > allocatableRegs_ = tri_->getAllocatableSet(fn); > + reservedRegs_ = tri_->getReservedRegs(fn); > li_ = &getAnalysis(); > ls_ = &getAnalysis(); > loopInfo = &getAnalysis(); > @@ -949,8 +951,14 @@ > const TargetRegisterClass *RC = mri_->getRegClass(cur->reg); > if (cur->empty()) { > unsigned physReg = vrm_->getRegAllocPref(cur->reg); > - if (!physReg) > - physReg = *RC->allocation_order_begin(*mf_); > + if (!physReg) { > + TargetRegisterClass::iterator aoe = RC->allocation_order_end(*mf_); > + TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_); > + while (reservedRegs_.test(*i) && i != aoe) > + ++i; > + assert(i != aoe && "All registers reserved?!"); > + physReg = *i; > + } > DEBUG(dbgs() << tri_->getName(physReg) << '\n'); > // Note the register is not really in use. > vrm_->assignVirt2Phys(cur->reg, physReg); > @@ -1133,8 +1141,9 @@ > e = RC->allocation_order_end(*mf_); i != e; ++i) { > unsigned reg = *i; > float regWeight = SpillWeights[reg]; > - // Skip recently allocated registers. > - if (minWeight > regWeight && !isRecentlyUsed(reg)) > + // Skip recently allocated registers and reserved registers. > + if (minWeight > regWeight && !isRecentlyUsed(reg) && > + !reservedRegs_.test(reg)) > Found = true; > RegsWeights.push_back(std::make_pair(reg, regWeight)); > } > @@ -1144,6 +1153,8 @@ > for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_), > e = RC->allocation_order_end(*mf_); i != e; ++i) { > unsigned reg = *i; > + if (reservedRegs_.test(reg)) > + continue; > // No need to worry about if the alias register size < regsize of RC. > // We are going to spill all registers that alias it anyway. > for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as) > @@ -1157,7 +1168,15 @@ > minWeight = RegsWeights[0].second; > if (minWeight == HUGE_VALF) { > // All registers must have inf weight. Just grab one! > - minReg = BestPhysReg ? BestPhysReg : *RC->allocation_order_begin(*mf_); > + if (BestPhysReg == 0) { > + TargetRegisterClass::iterator aoe = RC->allocation_order_end(*mf_); > + TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_); > + while (reservedRegs_.test(*i) && i != aoe) > + ++i; > + assert(i != aoe && "All registers reserved?!"); > + minReg = *i; > + } else > + minReg = BestPhysReg; > if (cur->weight == HUGE_VALF || > li_->getApproximateInstructionCount(*cur) == 0) { > // Spill a physical register around defs and uses. > @@ -1414,6 +1433,9 @@ > // Ignore "downgraded" registers. > if (SkipDGRegs && DowngradedRegs.count(Reg)) > continue; > + // Skip reserved registers. > + if (reservedRegs_.test(Reg)) > + continue; > // Skip recently allocated registers. > if (isRegAvail(Reg) && !isRecentlyUsed(Reg)) { > FreeReg = Reg; > @@ -1442,6 +1464,9 @@ > // Ignore "downgraded" registers. > if (SkipDGRegs && DowngradedRegs.count(Reg)) > continue; > + // Skip reserved registers. > + if (reservedRegs_.test(Reg)) > + continue; > if (isRegAvail(Reg) && Reg < inactiveCounts.size() && > FreeRegInactiveCount < inactiveCounts[Reg] && !isRecentlyUsed(Reg)) { > FreeReg = Reg; > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Fri Sep 10 01:53:03 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 9 Sep 2010 23:53:03 -0700 Subject: [llvm-commits] [llvm] r112742 - /llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp In-Reply-To: <20100901212303.CDE9E2A6C12C@llvm.org> References: <20100901212303.CDE9E2A6C12C@llvm.org> Message-ID: Hmm. I really am not seeing the advantage of doing the check in every register allocator (as opposed to have allocation_order_* excluding non-allocatable registers). Now all the out-of-tree register allocators will need have the same code. I missed a lot of patches during the last few weeks. What's the motivation for this change? Evan On Sep 1, 2010, at 2:23 PM, Jim Grosbach wrote: > Author: grosbach > Date: Wed Sep 1 16:23:03 2010 > New Revision: 112742 > > URL: http://llvm.org/viewvc/llvm-project?rev=112742&view=rev > Log: > The register allocator shouldn't consider allocating reserved registers. PBQP version. > > Modified: > llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp > > Modified: llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp?rev=112742&r1=112741&r2=112742&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp (original) > +++ llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp Wed Sep 1 16:23:03 2010 > @@ -587,6 +587,8 @@ > // Resize allowedSets container appropriately. > allowedSets.resize(vregIntervalsToAlloc.size()); > > + BitVector ReservedRegs = tri->getReservedRegs(*mf); > + > // Iterate over virtual register intervals to compute allowed sets... > for (unsigned node = 0; node < node2LI.size(); ++node) { > > @@ -595,8 +597,12 @@ > const TargetRegisterClass *liRC = mri->getRegClass(li->reg); > > // Start by assuming all allocable registers in the class are allowed... > - RegVector liAllowed(liRC->allocation_order_begin(*mf), > - liRC->allocation_order_end(*mf)); > + RegVector liAllowed; > + TargetRegisterClass::iterator aob = liRC->allocation_order_begin(*mf); > + TargetRegisterClass::iterator aoe = liRC->allocation_order_end(*mf); > + for (TargetRegisterClass::iterator it = aob; it != aoe; ++it) > + if (!ReservedRegs.test(*it)) > + liAllowed.push_back(*it); > > // Eliminate the physical registers which overlap with this range, along > // with all their aliases. > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Fri Sep 10 01:56:59 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 9 Sep 2010 23:56:59 -0700 Subject: [llvm-commits] [llvm] r112567 - /llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp In-Reply-To: <20100831012750.25FCE2A6C12D@llvm.org> References: <20100831012750.25FCE2A6C12D@llvm.org> Message-ID: On Aug 30, 2010, at 6:27 PM, Jakob Stoklund Olesen wrote: > Author: stoklund > Date: Mon Aug 30 20:27:49 2010 > New Revision: 112567 > > URL: http://llvm.org/viewvc/llvm-project?rev=112567&view=rev > Log: > Add experimental -disable-physical-join command line option. > > Eventually, we want to disable physreg coalescing completely, and let the > register allocator do its job using hints. > > This option makes it possible to measure the impact of disabling physreg > coalescing. But that will make the coalescer simpler! It will no longer be appropriately named. Evan > > Modified: > llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp > > Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=112567&r1=112566&r2=112567&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original) > +++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Mon Aug 30 20:27:49 2010 > @@ -59,6 +59,11 @@ > cl::desc("Avoid coalescing cross register class copies"), > cl::init(false), cl::Hidden); > > +static cl::opt > +DisablePhysicalJoin("disable-physical-join", > + cl::desc("Avoid coalescing physical register copies"), > + cl::init(false), cl::Hidden); > + > INITIALIZE_AG_PASS(SimpleRegisterCoalescing, RegisterCoalescer, > "simple-register-coalescing", "Simple Register Coalescing", > false, false, true); > @@ -1036,6 +1041,11 @@ > return false; // Not coalescable. > } > > + if (DisablePhysicalJoin && CP.isPhys()) { > + DEBUG(dbgs() << "\tPhysical joins disabled.\n"); > + return false; > + } > + > DEBUG(dbgs() << "\tConsidering merging %reg" << CP.getSrcReg()); > > // Enforce policies. > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Fri Sep 10 02:03:26 2010 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 10 Sep 2010 00:03:26 -0700 Subject: [llvm-commits] [llvm] r113576 - in /llvm/trunk: lib/Target/ARM/ARMLoadStoreOptimizer.cpp test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll In-Reply-To: <864CDCA7-5AE0-42D3-8E88-FB45FA4515A3@apple.com> References: <20100910051504.9175F2A6C12C@llvm.org> <864CDCA7-5AE0-42D3-8E88-FB45FA4515A3@apple.com> Message-ID: <58BEDCB8-9F59-4D70-B642-B14BF3BD9B18@apple.com> On Sep 9, 2010, at 11:38 PM, Eric Christopher wrote: > > On Sep 9, 2010, at 10:15 PM, Bob Wilson wrote: > >> to use AddrMode4, there was a count of the registers stored in one of the >> operands. I changed that to just count the operands but forgot to adjust for >> the size of D registers. This was noticed by Evan as a performance problem >> but it is a potential correctness bug as well, since it is possible that this >> could merge a base update with a non-matching immediate. >> >> Modified: >> llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp >> llvm/trunk/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll >> >> Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=113576&r1=113575&r2=113576&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original) >> +++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Fri Sep 10 00:15:04 2010 >> @@ -458,9 +458,10 @@ >> case ARM::t2STM: >> case ARM::VLDMS: >> case ARM::VSTMS: >> + return (MI->getNumOperands() - 4) * 4; >> case ARM::VLDMD: >> case ARM::VSTMD: >> - return (MI->getNumOperands() - 4) * 4; >> + return (MI->getNumOperands() - 4) * 8; > > Perhaps less magic numbers? Right. It probably should replace 4 with MI->getDesc().getNumOperands()-1. Evan > > -eric > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From isanbard at gmail.com Fri Sep 10 05:31:11 2010 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 10 Sep 2010 10:31:11 -0000 Subject: [llvm-commits] [llvm] r113584 - /llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Message-ID: <20100910103111.354B32A6C12C@llvm.org> Author: void Date: Fri Sep 10 05:31:11 2010 New Revision: 113584 URL: http://llvm.org/viewvc/llvm-project?rev=113584&view=rev Log: Reword since this may not be a bug but intended behavior. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=113584&r1=113583&r2=113584&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Fri Sep 10 05:31:11 2010 @@ -2310,8 +2310,8 @@ defm CMP : AI1_cmp_irs<0b1010, "cmp", BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>; -// FIXME: There seems to be a (potential) hardware bug with the CMN instruction -// and comparison with 0. These two pieces of code should give identical +// FIXME: We have to be careful when using the CMN instruction and comparison +// with 0. One would expect these two pieces of code should give identical // results: // // rsbs r1, r1, 0 @@ -2336,20 +2336,16 @@ // never a "carry" when this AddWithCarry is performed (because the "carry bit" // parameter to AddWithCarry is defined as 0). // -// The AddWithCarry in the CMP case seems to be relying upon the identity: -// -// ~x + 1 = -x -// -// However when x is 0 and unsigned, this doesn't hold: +// When x is 0 and unsigned: // // x = 0 // ~x = 0xFFFF FFFF // ~x + 1 = 0x1 0000 0000 // (-x = 0) != (0x1 0000 0000 = ~x + 1) // -// Therefore, we should disable *all* versions of CMN, especially when comparing -// against zero, until we can limit when the CMN instruction is used (when we -// know that the RHS is not 0) or when we have a hardware fix for this. +// Therefore, we should disable CMN when comparing against zero, until we can +// limit when the CMN instruction is used (when we know that the RHS is not 0 or +// when it's a comparison which doesn't look at the 'carry' flag). // // (See the ARM docs for the "AddWithCarry" pseudo-code.) // From isanbard at gmail.com Fri Sep 10 05:34:22 2010 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 10 Sep 2010 10:34:22 -0000 Subject: [llvm-commits] [llvm] r113585 - /llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Message-ID: <20100910103422.5342C2A6C12C@llvm.org> Author: void Date: Fri Sep 10 05:34:22 2010 New Revision: 113585 URL: http://llvm.org/viewvc/llvm-project?rev=113585&view=rev Log: Mark the sse_load_f32 and sse_load_f64 load patterns as having memoperands so that the memoperands are properly set after DAG building and general mucking about. Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=113585&r1=113584&r2=113585&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Fri Sep 10 05:34:22 2010 @@ -181,9 +181,9 @@ // the top elements. These are used for the SSE 'ss' and 'sd' instruction // forms. def sse_load_f32 : ComplexPattern; + [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; def sse_load_f64 : ComplexPattern; + [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; def ssmem : Operand { let PrintMethod = "printf32mem"; From espindola at google.com Fri Sep 10 09:33:07 2010 From: espindola at google.com (Rafael Espindola) Date: Fri, 10 Sep 2010 10:33:07 -0400 Subject: [llvm-commits] [llvm-gcc][arm][patch] Lower function signatures a bit more In-Reply-To: References: <386B2A85-DD45-4217-BE7A-FAE01B59A23B@apple.com> Message-ID: >> So checking ?TARGET_HARD_FLOAT_ABI is probably consistent with what >> the rest of the file does right now. > > Correct, as I said, I haven't ported this feature over, but you should > be aware of it. So, your first message was "If there are no regressions with hard float, LGTM". Can I assume a LGTM then with some extra comments? :-) > deep > Cheers, -- Rafael ?vila de Esp?ndola From stoklund at 2pi.dk Fri Sep 10 09:57:30 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Fri, 10 Sep 2010 07:57:30 -0700 Subject: [llvm-commits] [llvm] r113570 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ lib/Target/ARM/ lib/Target/CellSPU/ lib/Target/PowerPC/ test/CodeGen/ARM/ test/CodeGen/Thumb2/ In-Reply-To: <10A6A1EC-67DB-4847-9BA9-13563762ACF2@apple.com> References: <20100910012917.6A2C42A6C12C@llvm.org> <25D74F97-E815-4801-97B4-6B886ECF1911@2pi.dk> <10A6A1EC-67DB-4847-9BA9-13563762ACF2@apple.com> Message-ID: <29ECD9B3-CDD7-44E7-82A9-DA9ACE8D0B7D@2pi.dk> On Sep 9, 2010, at 11:21 PM, Evan Cheng wrote: > Hopefully fixed now. It is, thanks! > > Evan > > On Sep 9, 2010, at 10:50 PM, Jakob Stoklund Olesen wrote: > >> Hi Evan, >> >> The test you added is failing on all the non-darwin testers. Please take a look. >> >> /jakob >> >> On Sep 9, 2010, at 6:29 PM, Evan Cheng wrote: >> >>> llvm/trunk/test/CodeGen/ARM/ifcvt10.ll -------------- next part -------------- A non-text attachment was scrubbed... Name: smime.p7s Type: application/pkcs7-signature Size: 1929 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100910/a96dda3a/attachment.bin From stoklund at 2pi.dk Fri Sep 10 10:03:22 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Fri, 10 Sep 2010 08:03:22 -0700 Subject: [llvm-commits] [llvm] r112567 - /llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp In-Reply-To: References: <20100831012750.25FCE2A6C12D@llvm.org> Message-ID: On Sep 9, 2010, at 11:56 PM, Evan Cheng wrote: > > On Aug 30, 2010, at 6:27 PM, Jakob Stoklund Olesen wrote: > >> Author: stoklund >> Date: Mon Aug 30 20:27:49 2010 >> New Revision: 112567 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=112567&view=rev >> Log: >> Add experimental -disable-physical-join command line option. >> >> Eventually, we want to disable physreg coalescing completely, and let the >> register allocator do its job using hints. >> >> This option makes it possible to measure the impact of disabling physreg >> coalescing. > > But that will make the coalescer simpler! It will no longer be appropriately named. I am sure we can think of something else to stick in there, so we won't have to rename it TrivialCoalescing. The code in http://llvm.org/pr8112 is interesting re physreg coalescing. When you compile it with -disable-physical-join, the coalescer removes all virtual copies, and the allocator removes all but one physreg copy. To get rid of the last copy, an xor should have been commuted during coalescing. But since the coalescer did a perfect job of the virtual copies, that is hard to spot. -------------- next part -------------- A non-text attachment was scrubbed... Name: smime.p7s Type: application/pkcs7-signature Size: 1929 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100910/c82b1ff3/attachment.bin From grosbach at apple.com Fri Sep 10 10:37:28 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 10 Sep 2010 08:37:28 -0700 Subject: [llvm-commits] [llvm] r112742 - /llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp In-Reply-To: References: <20100901212303.CDE9E2A6C12C@llvm.org> Message-ID: <28D460DB-3A6B-428B-A8D9-FCC244B3CE5F@apple.com> Hi Evan, Jakob and I talked about this prior to this set of changes beforehand to make sure we were on the same page regarding overall direction and philosophy for how the allocators should handle allocation orders. The idea of these patches is to better encapsulate functionality, simplify the implementation and improve robustness. These patches are a beginning step. I have some additional thoughts on how to further improve these interfaces, and I know Jakob does too. 1. Conceptually, a register allocator should not allocate a reserved register. To do so is, by definition, incorrect. The less the allocators have to rely on the targets enforcing things like that, the more robust they are. In this case, a reserved register being in the allocation order is simply ignored when allocating. 2. Previously, targets had to maintain the information for reserved registers in multiple places. At minimum, in the isReservedReg() function and in any allocation orders for register classes containing those registers. With these changes, that's reduced to just the isReservedReg() function. The allocators automatically do the rest. 3. This allows targets to define their register classes more simply, without having to deal with all the conditional logic for when certain registers are reserved. Any conditionally reserved registers (based on qualities of the function being compiled) would require quite a bit of logic and code duplication in the begin/end iterators. That's no longer nearly so much the case. The ARM register class simplifications that followed are an example of this. -Jim The set of reserved registers isn't fixed, and having to update the allocation order iterators On Sep 9, 2010, at 11:53 PM, Evan Cheng wrote: > Hmm. I really am not seeing the advantage of doing the check in every register allocator (as opposed to have allocation_order_* excluding non-allocatable registers). Now all the out-of-tree register allocators will need have the same code. I missed a lot of patches during the last few weeks. What's the motivation for this change? > > Evan > > On Sep 1, 2010, at 2:23 PM, Jim Grosbach wrote: > >> Author: grosbach >> Date: Wed Sep 1 16:23:03 2010 >> New Revision: 112742 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=112742&view=rev >> Log: >> The register allocator shouldn't consider allocating reserved registers. PBQP version. >> >> Modified: >> llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp >> >> Modified: llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp?rev=112742&r1=112741&r2=112742&view=diff >> ============================================================================== >> --- llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp (original) >> +++ llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp Wed Sep 1 16:23:03 2010 >> @@ -587,6 +587,8 @@ >> // Resize allowedSets container appropriately. >> allowedSets.resize(vregIntervalsToAlloc.size()); >> >> + BitVector ReservedRegs = tri->getReservedRegs(*mf); >> + >> // Iterate over virtual register intervals to compute allowed sets... >> for (unsigned node = 0; node < node2LI.size(); ++node) { >> >> @@ -595,8 +597,12 @@ >> const TargetRegisterClass *liRC = mri->getRegClass(li->reg); >> >> // Start by assuming all allocable registers in the class are allowed... >> - RegVector liAllowed(liRC->allocation_order_begin(*mf), >> - liRC->allocation_order_end(*mf)); >> + RegVector liAllowed; >> + TargetRegisterClass::iterator aob = liRC->allocation_order_begin(*mf); >> + TargetRegisterClass::iterator aoe = liRC->allocation_order_end(*mf); >> + for (TargetRegisterClass::iterator it = aob; it != aoe; ++it) >> + if (!ReservedRegs.test(*it)) >> + liAllowed.push_back(*it); >> >> // Eliminate the physical registers which overlap with this range, along >> // with all their aliases. >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From stoklund at 2pi.dk Fri Sep 10 10:45:04 2010 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Fri, 10 Sep 2010 08:45:04 -0700 Subject: [llvm-commits] [llvm] r112741 - /llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp In-Reply-To: References: <20100901210427.9497B2A6C12C@llvm.org> Message-ID: On Sep 9, 2010, at 11:49 PM, Evan Cheng wrote: > To me it seems like tri_->getAllocatableSet(fn), allocation_order_begin, allocation_order_end should not include reserved registers. After all, their names implied as such. I agree in principle, and tri_->getAllocatableSet(fn) has since been fixed to filter out the reserved regs. Only the iterators may include reserved regs. > Wouldn't every register allocator needs to do the same check? Yes. We are missing a comment in TargetRegisterInfo.h to that effect. I agree that it isn't pretty, but it is an improvement over the old system. The allocation_order_* methods in the RegisterInfo.td files were getting too complicated and error prone. The system worked well for the occasional reserved frame pointer on x86, but the number of registers that can be reserved on ARM make the combinatorics untenable. Ultimately, I would like to see tablegen getting more involved in this. Tablegen should know which registers may be reserved and the corresponding predicates. Then it can generate allocation_order_* methods based on that. > > Evan > > On Sep 1, 2010, at 2:04 PM, Jim Grosbach wrote: > >> Author: grosbach >> Date: Wed Sep 1 16:04:27 2010 >> New Revision: 112741 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=112741&view=rev >> Log: >> The register allocator shouldn't consider allocating reserved registers. >> r112728 did this for fast regalloc. >> >> Modified: >> llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp >> >> Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp?rev=112741&r1=112740&r2=112741&view=diff >> ============================================================================== >> --- llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp (original) >> +++ llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Wed Sep 1 16:04:27 2010 >> @@ -125,6 +125,7 @@ >> const TargetRegisterInfo* tri_; >> const TargetInstrInfo* tii_; >> BitVector allocatableRegs_; >> + BitVector reservedRegs_; >> LiveIntervals* li_; >> LiveStacks* ls_; >> MachineLoopInfo *loopInfo; >> @@ -464,6 +465,7 @@ >> tri_ = tm_->getRegisterInfo(); >> tii_ = tm_->getInstrInfo(); >> allocatableRegs_ = tri_->getAllocatableSet(fn); >> + reservedRegs_ = tri_->getReservedRegs(fn); >> li_ = &getAnalysis(); >> ls_ = &getAnalysis(); >> loopInfo = &getAnalysis(); >> @@ -949,8 +951,14 @@ >> const TargetRegisterClass *RC = mri_->getRegClass(cur->reg); >> if (cur->empty()) { >> unsigned physReg = vrm_->getRegAllocPref(cur->reg); >> - if (!physReg) >> - physReg = *RC->allocation_order_begin(*mf_); >> + if (!physReg) { >> + TargetRegisterClass::iterator aoe = RC->allocation_order_end(*mf_); >> + TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_); >> + while (reservedRegs_.test(*i) && i != aoe) >> + ++i; >> + assert(i != aoe && "All registers reserved?!"); >> + physReg = *i; >> + } >> DEBUG(dbgs() << tri_->getName(physReg) << '\n'); >> // Note the register is not really in use. >> vrm_->assignVirt2Phys(cur->reg, physReg); >> @@ -1133,8 +1141,9 @@ >> e = RC->allocation_order_end(*mf_); i != e; ++i) { >> unsigned reg = *i; >> float regWeight = SpillWeights[reg]; >> - // Skip recently allocated registers. >> - if (minWeight > regWeight && !isRecentlyUsed(reg)) >> + // Skip recently allocated registers and reserved registers. >> + if (minWeight > regWeight && !isRecentlyUsed(reg) && >> + !reservedRegs_.test(reg)) >> Found = true; >> RegsWeights.push_back(std::make_pair(reg, regWeight)); >> } >> @@ -1144,6 +1153,8 @@ >> for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_), >> e = RC->allocation_order_end(*mf_); i != e; ++i) { >> unsigned reg = *i; >> + if (reservedRegs_.test(reg)) >> + continue; >> // No need to worry about if the alias register size < regsize of RC. >> // We are going to spill all registers that alias it anyway. >> for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as) >> @@ -1157,7 +1168,15 @@ >> minWeight = RegsWeights[0].second; >> if (minWeight == HUGE_VALF) { >> // All registers must have inf weight. Just grab one! >> - minReg = BestPhysReg ? BestPhysReg : *RC->allocation_order_begin(*mf_); >> + if (BestPhysReg == 0) { >> + TargetRegisterClass::iterator aoe = RC->allocation_order_end(*mf_); >> + TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_); >> + while (reservedRegs_.test(*i) && i != aoe) >> + ++i; >> + assert(i != aoe && "All registers reserved?!"); >> + minReg = *i; >> + } else >> + minReg = BestPhysReg; >> if (cur->weight == HUGE_VALF || >> li_->getApproximateInstructionCount(*cur) == 0) { >> // Spill a physical register around defs and uses. >> @@ -1414,6 +1433,9 @@ >> // Ignore "downgraded" registers. >> if (SkipDGRegs && DowngradedRegs.count(Reg)) >> continue; >> + // Skip reserved registers. >> + if (reservedRegs_.test(Reg)) >> + continue; >> // Skip recently allocated registers. >> if (isRegAvail(Reg) && !isRecentlyUsed(Reg)) { >> FreeReg = Reg; >> @@ -1442,6 +1464,9 @@ >> // Ignore "downgraded" registers. >> if (SkipDGRegs && DowngradedRegs.count(Reg)) >> continue; >> + // Skip reserved registers. >> + if (reservedRegs_.test(Reg)) >> + continue; >> if (isRegAvail(Reg) && Reg < inactiveCounts.size() && >> FreeRegInactiveCount < inactiveCounts[Reg] && !isRecentlyUsed(Reg)) { >> FreeReg = Reg; >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -------------- next part -------------- A non-text attachment was scrubbed... Name: smime.p7s Type: application/pkcs7-signature Size: 1929 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100910/8d89824e/attachment.bin From criswell at uiuc.edu Fri Sep 10 10:44:29 2010 From: criswell at uiuc.edu (John Criswell) Date: Fri, 10 Sep 2010 15:44:29 -0000 Subject: [llvm-commits] [poolalloc] r113587 - in /poolalloc/trunk/utils: ./ NightlyCronTab NightlyTest.sh Message-ID: <20100910154429.234602A6C12C@llvm.org> Author: criswell Date: Fri Sep 10 10:44:28 2010 New Revision: 113587 URL: http://llvm.org/viewvc/llvm-project?rev=113587&view=rev Log: Adding a utility directory for miscellaneous stuff. In particular, we now have a simple testing script and a simple crontab for said script for nightly tests. Added: poolalloc/trunk/utils/ poolalloc/trunk/utils/NightlyCronTab poolalloc/trunk/utils/NightlyTest.sh (with props) Added: poolalloc/trunk/utils/NightlyCronTab URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/utils/NightlyCronTab?rev=113587&view=auto ============================================================================== --- poolalloc/trunk/utils/NightlyCronTab (added) +++ poolalloc/trunk/utils/NightlyCronTab Fri Sep 10 10:44:28 2010 @@ -0,0 +1,10 @@ +# +# Send mail to no one +# +MAILTO="" + +# +# Taken from the Linux man page and modified. +# +0 3 * * * $HOME/cronjobs/llvm27/projects/poolalloc/utils/NightlyTest.sh + Added: poolalloc/trunk/utils/NightlyTest.sh URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/utils/NightlyTest.sh?rev=113587&view=auto ============================================================================== --- poolalloc/trunk/utils/NightlyTest.sh (added) +++ poolalloc/trunk/utils/NightlyTest.sh Fri Sep 10 10:44:28 2010 @@ -0,0 +1,62 @@ +#!/bin/sh + +# Location of the LLVM source and object trees +LLVMDIR=$HOME/cronjobs/llvm27 + +# Location of test suite object tree +TESTSUITE=$LLVMDIR/projects/test-suite + +# Location of file containing log of the test build and run +LOGFILE=$LLVMDIR/projects/poolalloc/test/results + +# List of directories to clean before test +TESTDIRS="MultiSource/Benchmarks/Olden External/SPEC/CINT2000" + +# +# Switch to the LLVM source tree. +# +cd $LLVMDIR + +# +# Make sure LLVM is up-to-date. +# +echo "Updating LLVM" +svn up +echo "Building LLVM" +make -s -j3 tools-only + +# +# Update and build Automatic Pool Allocation +# +cd $LLVMDIR/projects/poolalloc +echo "Updating Poolalloc" +svn up +echo "Building Poolalloc" +make -s -j3 + +# +# Clean out the old test files. +# +echo "Cleaning out old test files..." +for dir in $TESTDIRS +do + cd $TESTSUITE/$dir + make clean +done + +# +# Run the automatic pool allocation tests. +# +echo "Testing Poolalloc..." +cd $LLVMDIR/projects/poolalloc/test +mv $LOGFILE $LOGFILE.old +make NO_STABLE_NUMBERS=1 -j3 progtest 2>&1 > $LOGFILE + +# +# Print out the results. +# +for dir in $TESTDIRS +do + cat $TESTSUITE/$dir/report.poolalloc.txt +done + Propchange: poolalloc/trunk/utils/NightlyTest.sh ------------------------------------------------------------------------------ svn:executable = * From grosbach at apple.com Fri Sep 10 10:37:28 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 10 Sep 2010 08:37:28 -0700 Subject: [llvm-commits] [llvm] r112742 - /llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp In-Reply-To: References: <20100901212303.CDE9E2A6C12C@llvm.org> Message-ID: <28D460DB-3A6B-428B-A8D9-FCC244B3CE5F@apple.com> Hi Evan, Jakob and I talked about this prior to this set of changes beforehand to make sure we were on the same page regarding overall direction and philosophy for how the allocators should handle allocation orders. The idea of these patches is to better encapsulate functionality, simplify the implementation and improve robustness. These patches are a beginning step. I have some additional thoughts on how to further improve these interfaces, and I know Jakob does too. 1. Conceptually, a register allocator should not allocate a reserved register. To do so is, by definition, incorrect. The less the allocators have to rely on the targets enforcing things like that, the more robust they are. In this case, a reserved register being in the allocation order is simply ignored when allocating. 2. Previously, targets had to maintain the information for reserved registers in multiple places. At minimum, in the isReservedReg() function and in any allocation orders for register classes containing those registers. With these changes, that's reduced to just the isReservedReg() function. The allocators automatically do the rest. 3. This allows targets to define their register classes more simply, without having to deal with all the conditional logic for when certain registers are reserved. Any conditionally reserved registers (based on qualities of the function being compiled) would require quite a bit of logic and code duplication in the begin/end iterators. That's no longer nearly so much the case. The ARM register class simplifications that followed are an example of this. -Jim The set of reserved registers isn't fixed, and having to update the allocation order iterators On Sep 9, 2010, at 11:53 PM, Evan Cheng wrote: > Hmm. I really am not seeing the advantage of doing the check in every register allocator (as opposed to have allocation_order_* excluding non-allocatable registers). Now all the out-of-tree register allocators will need have the same code. I missed a lot of patches during the last few weeks. What's the motivation for this change? > > Evan > > On Sep 1, 2010, at 2:23 PM, Jim Grosbach wrote: > >> Author: grosbach >> Date: Wed Sep 1 16:23:03 2010 >> New Revision: 112742 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=112742&view=rev >> Log: >> The register allocator shouldn't consider allocating reserved registers. PBQP version. >> >> Modified: >> llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp >> >> Modified: llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp?rev=112742&r1=112741&r2=112742&view=diff >> ============================================================================== >> --- llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp (original) >> +++ llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp Wed Sep 1 16:23:03 2010 >> @@ -587,6 +587,8 @@ >> // Resize allowedSets container appropriately. >> allowedSets.resize(vregIntervalsToAlloc.size()); >> >> + BitVector ReservedRegs = tri->getReservedRegs(*mf); >> + >> // Iterate over virtual register intervals to compute allowed sets... >> for (unsigned node = 0; node < node2LI.size(); ++node) { >> >> @@ -595,8 +597,12 @@ >> const TargetRegisterClass *liRC = mri->getRegClass(li->reg); >> >> // Start by assuming all allocable registers in the class are allowed... >> - RegVector liAllowed(liRC->allocation_order_begin(*mf), >> - liRC->allocation_order_end(*mf)); >> + RegVector liAllowed; >> + TargetRegisterClass::iterator aob = liRC->allocation_order_begin(*mf); >> + TargetRegisterClass::iterator aoe = liRC->allocation_order_end(*mf); >> + for (TargetRegisterClass::iterator it = aob; it != aoe; ++it) >> + if (!ReservedRegs.test(*it)) >> + liAllowed.push_back(*it); >> >> // Eliminate the physical registers which overlap with this range, along >> // with all their aliases. >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From grosbach at apple.com Fri Sep 10 12:41:34 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 10 Sep 2010 10:41:34 -0700 Subject: [llvm-commits] [llvm] r112741 - /llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp In-Reply-To: References: <20100901210427.9497B2A6C12C@llvm.org> Message-ID: <5ADDB227-D5BD-4384-9842-4A062F3EEA86@apple.com> On Sep 10, 2010, at 8:45 AM, Jakob Stoklund Olesen wrote: > > On Sep 9, 2010, at 11:49 PM, Evan Cheng wrote: > >> To me it seems like tri_->getAllocatableSet(fn), allocation_order_begin, allocation_order_end should not include reserved registers. After all, their names implied as such. > > I agree in principle, and tri_->getAllocatableSet(fn) has since been fixed to filter out the reserved regs. > > Only the iterators may include reserved regs. Right. The idea is that getAllocatableSet() should become the canonical way of determining which registers are allocatable. Allocation orders are a lower level interface that say, in effect, "Of those registers that may be allocatable, what order should they be allocated in." That is, they include all registers that might be allocatable, and any entry is checked against the allocatable set before use. This allows things like the frame pointer being allocatable (or not) on a function by function basis without the allocation order iterators needing to change. > >> Wouldn't every register allocator needs to do the same check? > > Yes. We are missing a comment in TargetRegisterInfo.h to that effect. > Good point. I'll do something about that. > I agree that it isn't pretty, but it is an improvement over the old system. The allocation_order_* methods in the RegisterInfo.td files were getting too complicated and error prone. > > The system worked well for the occasional reserved frame pointer on x86, but the number of registers that can be reserved on ARM make the combinatorics untenable. > > Ultimately, I would like to see tablegen getting more involved in this. Tablegen should know which registers may be reserved and the corresponding predicates. Then it can generate allocation_order_* methods based on that Absolutely. There's a lot of room for improvement here. We should be able get to a solution that doesn't require targets to directly implement allocation order iterators at all, at least for typical use cases. They should be created automatically based on predicates expressed in the td files. This will be a huge improvement, as we'll be moving towards allowing back-ends to express intent for the register classes rather than having to specify details of implementation for the register allocator(s). For example, given the register classes, the calling convention(s), the isReservedReg() hook and the subtarget predicates, it should be entirely reasonable to auto-generate the necessary register allocation orders from the register classes without the target having to do anything else barring something really weird. We're not there yet, obviously, but we're getting there. -Jim > >> >> Evan >> >> On Sep 1, 2010, at 2:04 PM, Jim Grosbach wrote: >> >>> Author: grosbach >>> Date: Wed Sep 1 16:04:27 2010 >>> New Revision: 112741 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=112741&view=rev >>> Log: >>> The register allocator shouldn't consider allocating reserved registers. >>> r112728 did this for fast regalloc. >>> >>> Modified: >>> llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp >>> >>> Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp?rev=112741&r1=112740&r2=112741&view=diff >>> ============================================================================== >>> --- llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp (original) >>> +++ llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Wed Sep 1 16:04:27 2010 >>> @@ -125,6 +125,7 @@ >>> const TargetRegisterInfo* tri_; >>> const TargetInstrInfo* tii_; >>> BitVector allocatableRegs_; >>> + BitVector reservedRegs_; >>> LiveIntervals* li_; >>> LiveStacks* ls_; >>> MachineLoopInfo *loopInfo; >>> @@ -464,6 +465,7 @@ >>> tri_ = tm_->getRegisterInfo(); >>> tii_ = tm_->getInstrInfo(); >>> allocatableRegs_ = tri_->getAllocatableSet(fn); >>> + reservedRegs_ = tri_->getReservedRegs(fn); >>> li_ = &getAnalysis(); >>> ls_ = &getAnalysis(); >>> loopInfo = &getAnalysis(); >>> @@ -949,8 +951,14 @@ >>> const TargetRegisterClass *RC = mri_->getRegClass(cur->reg); >>> if (cur->empty()) { >>> unsigned physReg = vrm_->getRegAllocPref(cur->reg); >>> - if (!physReg) >>> - physReg = *RC->allocation_order_begin(*mf_); >>> + if (!physReg) { >>> + TargetRegisterClass::iterator aoe = RC->allocation_order_end(*mf_); >>> + TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_); >>> + while (reservedRegs_.test(*i) && i != aoe) >>> + ++i; >>> + assert(i != aoe && "All registers reserved?!"); >>> + physReg = *i; >>> + } >>> DEBUG(dbgs() << tri_->getName(physReg) << '\n'); >>> // Note the register is not really in use. >>> vrm_->assignVirt2Phys(cur->reg, physReg); >>> @@ -1133,8 +1141,9 @@ >>> e = RC->allocation_order_end(*mf_); i != e; ++i) { >>> unsigned reg = *i; >>> float regWeight = SpillWeights[reg]; >>> - // Skip recently allocated registers. >>> - if (minWeight > regWeight && !isRecentlyUsed(reg)) >>> + // Skip recently allocated registers and reserved registers. >>> + if (minWeight > regWeight && !isRecentlyUsed(reg) && >>> + !reservedRegs_.test(reg)) >>> Found = true; >>> RegsWeights.push_back(std::make_pair(reg, regWeight)); >>> } >>> @@ -1144,6 +1153,8 @@ >>> for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_), >>> e = RC->allocation_order_end(*mf_); i != e; ++i) { >>> unsigned reg = *i; >>> + if (reservedRegs_.test(reg)) >>> + continue; >>> // No need to worry about if the alias register size < regsize of RC. >>> // We are going to spill all registers that alias it anyway. >>> for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as) >>> @@ -1157,7 +1168,15 @@ >>> minWeight = RegsWeights[0].second; >>> if (minWeight == HUGE_VALF) { >>> // All registers must have inf weight. Just grab one! >>> - minReg = BestPhysReg ? BestPhysReg : *RC->allocation_order_begin(*mf_); >>> + if (BestPhysReg == 0) { >>> + TargetRegisterClass::iterator aoe = RC->allocation_order_end(*mf_); >>> + TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_); >>> + while (reservedRegs_.test(*i) && i != aoe) >>> + ++i; >>> + assert(i != aoe && "All registers reserved?!"); >>> + minReg = *i; >>> + } else >>> + minReg = BestPhysReg; >>> if (cur->weight == HUGE_VALF || >>> li_->getApproximateInstructionCount(*cur) == 0) { >>> // Spill a physical register around defs and uses. >>> @@ -1414,6 +1433,9 @@ >>> // Ignore "downgraded" registers. >>> if (SkipDGRegs && DowngradedRegs.count(Reg)) >>> continue; >>> + // Skip reserved registers. >>> + if (reservedRegs_.test(Reg)) >>> + continue; >>> // Skip recently allocated registers. >>> if (isRegAvail(Reg) && !isRecentlyUsed(Reg)) { >>> FreeReg = Reg; >>> @@ -1442,6 +1464,9 @@ >>> // Ignore "downgraded" registers. >>> if (SkipDGRegs && DowngradedRegs.count(Reg)) >>> continue; >>> + // Skip reserved registers. >>> + if (reservedRegs_.test(Reg)) >>> + continue; >>> if (isRegAvail(Reg) && Reg < inactiveCounts.size() && >>> FreeRegInactiveCount < inactiveCounts[Reg] && !isRecentlyUsed(Reg)) { >>> FreeReg = Reg; >>> >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From bob.wilson at apple.com Fri Sep 10 12:42:31 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Fri, 10 Sep 2010 10:42:31 -0700 Subject: [llvm-commits] [llvm] r113576 - in /llvm/trunk: lib/Target/ARM/ARMLoadStoreOptimizer.cpp test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll In-Reply-To: <58BEDCB8-9F59-4D70-B642-B14BF3BD9B18@apple.com> References: <20100910051504.9175F2A6C12C@llvm.org> <864CDCA7-5AE0-42D3-8E88-FB45FA4515A3@apple.com> <58BEDCB8-9F59-4D70-B642-B14BF3BD9B18@apple.com> Message-ID: On Sep 10, 2010, at 12:03 AM, Evan Cheng wrote: > > On Sep 9, 2010, at 11:38 PM, Eric Christopher wrote: > >> >> On Sep 9, 2010, at 10:15 PM, Bob Wilson wrote: >> >>> to use AddrMode4, there was a count of the registers stored in one of the >>> operands. I changed that to just count the operands but forgot to adjust for >>> the size of D registers. This was noticed by Evan as a performance problem >>> but it is a potential correctness bug as well, since it is possible that this >>> could merge a base update with a non-matching immediate. >>> >>> Modified: >>> llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp >>> llvm/trunk/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll >>> >>> Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=113576&r1=113575&r2=113576&view=diff >>> ============================================================================== >>> --- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original) >>> +++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Fri Sep 10 00:15:04 2010 >>> @@ -458,9 +458,10 @@ >>> case ARM::t2STM: >>> case ARM::VLDMS: >>> case ARM::VSTMS: >>> + return (MI->getNumOperands() - 4) * 4; >>> case ARM::VLDMD: >>> case ARM::VSTMD: >>> - return (MI->getNumOperands() - 4) * 4; >>> + return (MI->getNumOperands() - 4) * 8; >> >> Perhaps less magic numbers? > > Right. It probably should replace 4 with MI->getDesc().getNumOperands()-1. How would that work? They're variadic instructions. From grosbach at apple.com Fri Sep 10 12:51:35 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 10 Sep 2010 17:51:35 -0000 Subject: [llvm-commits] [llvm] r113593 - /llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Message-ID: <20100910175135.1EBE62A6C12C@llvm.org> Author: grosbach Date: Fri Sep 10 12:51:34 2010 New Revision: 113593 URL: http://llvm.org/viewvc/llvm-project?rev=113593&view=rev Log: add a comment explicitly calling out that allocation orders may include reserved regs and that register allocators need to explicitly check for them. Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=113593&r1=113592&r2=113593&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Fri Sep 10 12:51:34 2010 @@ -227,9 +227,12 @@ /// cheaper to allocate caller saved registers. /// /// These methods take a MachineFunction argument, which can be used to tune - /// the allocatable registers based on the characteristics of the function. - /// One simple example is that the frame pointer register can be used if - /// frame-pointer-elimination is performed. + /// the allocatable registers based on the characteristics of the function, + /// subtarget, or other criteria. + /// + /// Register allocators should account for the fact that an allocation + /// order iterator may return a reserved register and always check + /// if the register is allocatable (getAllocatableSet()) before using it. /// /// By default, these methods return all registers in the class. /// From dalej at apple.com Fri Sep 10 12:51:47 2010 From: dalej at apple.com (Dale Johannesen) Date: Fri, 10 Sep 2010 17:51:47 -0000 Subject: [llvm-commits] [llvm] r113594 - /llvm/trunk/include/llvm/CodeGen/ValueTypes.td Message-ID: <20100910175147.C99C92A6C12C@llvm.org> Author: johannes Date: Fri Sep 10 12:51:47 2010 New Revision: 113594 URL: http://llvm.org/viewvc/llvm-project?rev=113594&view=rev Log: x86mmx is 64 bits. Modified: llvm/trunk/include/llvm/CodeGen/ValueTypes.td Modified: llvm/trunk/include/llvm/CodeGen/ValueTypes.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ValueTypes.td?rev=113594&r1=113593&r2=113594&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/ValueTypes.td (original) +++ llvm/trunk/include/llvm/CodeGen/ValueTypes.td Fri Sep 10 12:51:47 2010 @@ -55,7 +55,7 @@ def v2f64 : ValueType<128, 31>; // 2 x f64 vector value def v4f64 : ValueType<256, 32>; // 4 x f64 vector value -def x86mmx : ValueType<0 , 33>; // X86 MMX value +def x86mmx : ValueType<64 , 33>; // X86 MMX value def FlagVT : ValueType<0 , 34>; // Pre-RA sched glue def isVoid : ValueType<0 , 35>; // Produces no value From resistor at mac.com Fri Sep 10 12:57:00 2010 From: resistor at mac.com (Owen Anderson) Date: Fri, 10 Sep 2010 17:57:00 -0000 Subject: [llvm-commits] [llvm] r113595 - /llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp Message-ID: <20100910175700.394A12A6C12C@llvm.org> Author: resistor Date: Fri Sep 10 12:57:00 2010 New Revision: 113595 URL: http://llvm.org/viewvc/llvm-project?rev=113595&view=rev Log: Lower the unrolling theshold to 150. Empirical tests indicate that this is a sweet spot in the performance per code size increase curve. Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp?rev=113595&r1=113594&r2=113595&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp Fri Sep 10 12:57:00 2010 @@ -27,7 +27,7 @@ using namespace llvm; static cl::opt -UnrollThreshold("unroll-threshold", cl::init(200), cl::Hidden, +UnrollThreshold("unroll-threshold", cl::init(150), cl::Hidden, cl::desc("The cut-off point for automatic loop unrolling")); static cl::opt From bob.wilson at apple.com Fri Sep 10 13:09:05 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Fri, 10 Sep 2010 11:09:05 -0700 Subject: [llvm-commits] [llvm] r113576 - in /llvm/trunk: lib/Target/ARM/ARMLoadStoreOptimizer.cpp test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll In-Reply-To: References: <20100910051504.9175F2A6C12C@llvm.org> <864CDCA7-5AE0-42D3-8E88-FB45FA4515A3@apple.com> <58BEDCB8-9F59-4D70-B642-B14BF3BD9B18@apple.com> Message-ID: <8B936328-4F11-46BA-945F-0D560E084A93@apple.com> On Sep 10, 2010, at 10:42 AM, Bob Wilson wrote: > > On Sep 10, 2010, at 12:03 AM, Evan Cheng wrote: >> >> Right. It probably should replace 4 with MI->getDesc().getNumOperands()-1. > > How would that work? They're variadic instructions. Oh. It suddenly hit me what you meant (which was exactly what you wrote). I'll go with that. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100910/12c319f4/attachment.html From bob.wilson at apple.com Fri Sep 10 13:25:35 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Fri, 10 Sep 2010 18:25:35 -0000 Subject: [llvm-commits] [llvm] r113597 - /llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Message-ID: <20100910182535.C42ED2A6C12C@llvm.org> Author: bwilson Date: Fri Sep 10 13:25:35 2010 New Revision: 113597 URL: http://llvm.org/viewvc/llvm-project?rev=113597&view=rev Log: Calculate the number of VLDM/VSTM registers by subtracting the number of fixed operands from the total number of operands (including the variadic ones). Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=113597&r1=113596&r2=113597&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Fri Sep 10 13:25:35 2010 @@ -458,10 +458,10 @@ case ARM::t2STM: case ARM::VLDMS: case ARM::VSTMS: - return (MI->getNumOperands() - 4) * 4; + return (MI->getNumOperands() - MI->getDesc().getNumOperands() + 1) * 4; case ARM::VLDMD: case ARM::VSTMD: - return (MI->getNumOperands() - 4) * 8; + return (MI->getNumOperands() - MI->getDesc().getNumOperands() + 1) * 8; } } From espindola at google.com Fri Sep 10 13:38:42 2010 From: espindola at google.com (Rafael Espindola) Date: Fri, 10 Sep 2010 14:38:42 -0400 Subject: [llvm-commits] [patch][MC] Change the way we dump section_data Message-ID: While working on the LEB128 patch I found the output of elf-dump and macho-dump for section_data hard to read. The problem is that "%r" works best for mostly ascii data. Since that is normally the case, we get things like "\xc88\xf4". Note that the second '8' is the ascii char '8'. With this patch we get "c838f4" with a space every 4 bytes. IMHO it makes the output a lot easier to decode. Cheers, -- Rafael ?vila de Esp?ndola -------------- next part -------------- A non-text attachment was scrubbed... Name: section_data.patch Type: text/x-patch Size: 23503 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100910/ea978f2e/attachment.bin From isanbard at gmail.com Fri Sep 10 13:51:56 2010 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 10 Sep 2010 18:51:56 -0000 Subject: [llvm-commits] [llvm] r113600 - in /llvm/trunk: include/llvm/AutoUpgrade.h lib/Bitcode/Reader/BitcodeReader.cpp lib/VMCore/AutoUpgrade.cpp test/Bitcode/AutoUpgradeGlobals.ll test/Bitcode/AutoUpgradeGlobals.ll.bc Message-ID: <20100910185156.3425E2A6C12C@llvm.org> Author: void Date: Fri Sep 10 13:51:56 2010 New Revision: 113600 URL: http://llvm.org/viewvc/llvm-project?rev=113600&view=rev Log: Auto-upgrade the magic ".llvm.eh.catch.all.value" global to "llvm.eh.catch.all.value". Only the name needs to be changed. Added: llvm/trunk/test/Bitcode/AutoUpgradeGlobals.ll llvm/trunk/test/Bitcode/AutoUpgradeGlobals.ll.bc (with props) Modified: llvm/trunk/include/llvm/AutoUpgrade.h llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp llvm/trunk/lib/VMCore/AutoUpgrade.cpp Modified: llvm/trunk/include/llvm/AutoUpgrade.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/AutoUpgrade.h?rev=113600&r1=113599&r2=113600&view=diff ============================================================================== --- llvm/trunk/include/llvm/AutoUpgrade.h (original) +++ llvm/trunk/include/llvm/AutoUpgrade.h Fri Sep 10 13:51:56 2010 @@ -16,6 +16,7 @@ namespace llvm { class Module; + class GlobalVariable; class Function; class CallInst; @@ -35,6 +36,10 @@ /// so that it can update all calls to the old function. void UpgradeCallsToIntrinsic(Function* F); + /// This checks for global variables which should be upgraded. It returns true + /// if it requires upgrading. + bool UpgradeGlobalVariable(GlobalVariable *GV); + /// This function checks debug info intrinsics. If an intrinsic is invalid /// then this function simply removes the intrinsic. void CheckDebugInfoIntrinsics(Module *M); Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp?rev=113600&r1=113599&r2=113600&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp (original) +++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp Fri Sep 10 13:51:56 2010 @@ -1288,6 +1288,12 @@ UpgradedIntrinsics.push_back(std::make_pair(FI, NewFn)); } + // Look for global variables which need to be renamed. + for (Module::global_iterator + GI = TheModule->global_begin(), GE = TheModule->global_end(); + GI != GE; ++GI) + UpgradeGlobalVariable(GI); + // Force deallocation of memory for these vectors to favor the client that // want lazy deserialization. std::vector >().swap(GlobalInits); Modified: llvm/trunk/lib/VMCore/AutoUpgrade.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AutoUpgrade.cpp?rev=113600&r1=113599&r2=113600&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/AutoUpgrade.cpp (original) +++ llvm/trunk/lib/VMCore/AutoUpgrade.cpp Fri Sep 10 13:51:56 2010 @@ -365,6 +365,20 @@ return Upgraded; } +bool llvm::UpgradeGlobalVariable(GlobalVariable *GV) { + const std::string &Name = GV->getName(); + + // We are only upgrading one symbol here. If we upgrade more, we will want to + // perform some sort of short-circuiting like in the + // "UpgradeIntrinsicFunction1" function. + if (Name == ".llvm.eh.catch.all.value") { + GV->setName("llvm.eh.catch.all.value"); + return true; + } + + return false; +} + /// ExtendNEONArgs - For NEON "long" and "wide" operations, where the results /// have vector elements twice as big as one or both source operands, do the /// sign- or zero-extension that used to be handled by intrinsics. The Added: llvm/trunk/test/Bitcode/AutoUpgradeGlobals.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bitcode/AutoUpgradeGlobals.ll?rev=113600&view=auto ============================================================================== --- llvm/trunk/test/Bitcode/AutoUpgradeGlobals.ll (added) +++ llvm/trunk/test/Bitcode/AutoUpgradeGlobals.ll Fri Sep 10 13:51:56 2010 @@ -0,0 +1,3 @@ +; This isn't really an assembly file. It just runs test on bitcode to ensure +; it is auto-upgraded. +; RUN: llvm-dis < %s.bc | not grep {i32 @\\.llvm\\.eh} Added: llvm/trunk/test/Bitcode/AutoUpgradeGlobals.ll.bc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bitcode/AutoUpgradeGlobals.ll.bc?rev=113600&view=auto ============================================================================== Binary file - no diff available. Propchange: llvm/trunk/test/Bitcode/AutoUpgradeGlobals.ll.bc ------------------------------------------------------------------------------ svn:mime-type = application/octet-stream From isanbard at gmail.com Fri Sep 10 14:06:58 2010 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 10 Sep 2010 19:06:58 -0000 Subject: [llvm-commits] [llvm] r113603 - /llvm/trunk/lib/VMCore/AutoUpgrade.cpp Message-ID: <20100910190658.89DFC2A6C12C@llvm.org> Author: void Date: Fri Sep 10 14:06:58 2010 New Revision: 113603 URL: http://llvm.org/viewvc/llvm-project?rev=113603&view=rev Log: Early exit with simple checks. Modified: llvm/trunk/lib/VMCore/AutoUpgrade.cpp Modified: llvm/trunk/lib/VMCore/AutoUpgrade.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AutoUpgrade.cpp?rev=113603&r1=113602&r2=113603&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/AutoUpgrade.cpp (original) +++ llvm/trunk/lib/VMCore/AutoUpgrade.cpp Fri Sep 10 14:06:58 2010 @@ -368,9 +368,12 @@ bool llvm::UpgradeGlobalVariable(GlobalVariable *GV) { const std::string &Name = GV->getName(); - // We are only upgrading one symbol here. If we upgrade more, we will want to - // perform some sort of short-circuiting like in the - // "UpgradeIntrinsicFunction1" function. + // Early exit with simple tests. + if (Name.length() != 24 || Name[0] != '.' || Name[1] != 'l' || + Name[3] != 'l' || Name[4] != 'v' || Name[5] != 'm' || Name[6] != '.') + return false; + + // We are only upgrading one symbol here. if (Name == ".llvm.eh.catch.all.value") { GV->setName("llvm.eh.catch.all.value"); return true; From isanbard at gmail.com Fri Sep 10 14:20:48 2010 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 10 Sep 2010 19:20:48 -0000 Subject: [llvm-commits] [llvm] r113605 - /llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Message-ID: <20100910192048.260302A6C12C@llvm.org> Author: void Date: Fri Sep 10 14:20:47 2010 New Revision: 113605 URL: http://llvm.org/viewvc/llvm-project?rev=113605&view=rev Log: r113585 was causing clang-i686-xp-msvc9 to fail in mysterious ways that I can't understand (the log file was no help). Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=113605&r1=113604&r2=113605&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Fri Sep 10 14:20:47 2010 @@ -181,9 +181,9 @@ // the top elements. These are used for the SSE 'ss' and 'sd' instruction // forms. def sse_load_f32 : ComplexPattern; + [SDNPHasChain, SDNPMayLoad]>; def sse_load_f64 : ComplexPattern; + [SDNPHasChain, SDNPMayLoad]>; def ssmem : Operand { let PrintMethod = "printf32mem"; From benny.kra at googlemail.com Fri Sep 10 14:52:35 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Fri, 10 Sep 2010 19:52:35 -0000 Subject: [llvm-commits] [llvm] r113608 - /llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp Message-ID: <20100910195235.779B42A6C12C@llvm.org> Author: d0k Date: Fri Sep 10 14:52:35 2010 New Revision: 113608 URL: http://llvm.org/viewvc/llvm-project?rev=113608&view=rev Log: This transform is also performed by InstructionSimplify, remove the duplicate. Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp?rev=113608&r1=113607&r2=113608&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp Fri Sep 10 14:52:35 2010 @@ -207,9 +207,6 @@ } break; case Instruction::Or: - if (Together == AndRHS) // (X | C) & C --> C - return ReplaceInstUsesWith(TheAnd, AndRHS); - if (Op->hasOneUse() && Together != OpRHS) { // (X | C1) & C2 --> (X | (C1&C2)) & C2 Value *Or = Builder->CreateOr(X, Together); From isanbard at gmail.com Fri Sep 10 15:20:28 2010 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 10 Sep 2010 20:20:28 -0000 Subject: [llvm-commits] [llvm] r113610 - /llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Message-ID: <20100910202028.D3C002A6C12C@llvm.org> Author: void Date: Fri Sep 10 15:20:28 2010 New Revision: 113610 URL: http://llvm.org/viewvc/llvm-project?rev=113610&view=rev Log: Reapply r113585. The msvc machine is mercurial. Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=113610&r1=113609&r2=113610&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Fri Sep 10 15:20:28 2010 @@ -181,9 +181,9 @@ // the top elements. These are used for the SSE 'ss' and 'sd' instruction // forms. def sse_load_f32 : ComplexPattern; + [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; def sse_load_f64 : ComplexPattern; + [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; def ssmem : Operand { let PrintMethod = "printf32mem"; From clattner at apple.com Fri Sep 10 15:27:27 2010 From: clattner at apple.com (Chris Lattner) Date: Fri, 10 Sep 2010 13:27:27 -0700 Subject: [llvm-commits] [llvm] r113603 - /llvm/trunk/lib/VMCore/AutoUpgrade.cpp In-Reply-To: <20100910190658.89DFC2A6C12C@llvm.org> References: <20100910190658.89DFC2A6C12C@llvm.org> Message-ID: On Sep 10, 2010, at 12:06 PM, Bill Wendling wrote: > Author: void > Date: Fri Sep 10 14:06:58 2010 > New Revision: 113603 > > URL: http://llvm.org/viewvc/llvm-project?rev=113603&view=rev > Log: > Early exit with simple checks. Hi Bill, please capture Name as a StringRef instead of std::string. The early exit isn't needed, stringref does it for you in == with a constant string. -Chris > > Modified: > llvm/trunk/lib/VMCore/AutoUpgrade.cpp > > Modified: llvm/trunk/lib/VMCore/AutoUpgrade.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AutoUpgrade.cpp?rev=113603&r1=113602&r2=113603&view=diff > ============================================================================== > --- llvm/trunk/lib/VMCore/AutoUpgrade.cpp (original) > +++ llvm/trunk/lib/VMCore/AutoUpgrade.cpp Fri Sep 10 14:06:58 2010 > @@ -368,9 +368,12 @@ > bool llvm::UpgradeGlobalVariable(GlobalVariable *GV) { > const std::string &Name = GV->getName(); > > - // We are only upgrading one symbol here. If we upgrade more, we will want to > - // perform some sort of short-circuiting like in the > - // "UpgradeIntrinsicFunction1" function. > + // Early exit with simple tests. > + if (Name.length() != 24 || Name[0] != '.' || Name[1] != 'l' || > + Name[3] != 'l' || Name[4] != 'v' || Name[5] != 'm' || Name[6] != '.') > + return false; > + > + // We are only upgrading one symbol here. > if (Name == ".llvm.eh.catch.all.value") { > GV->setName("llvm.eh.catch.all.value"); > return true; > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dpatel at apple.com Fri Sep 10 15:32:09 2010 From: dpatel at apple.com (Devang Patel) Date: Fri, 10 Sep 2010 20:32:09 -0000 Subject: [llvm-commits] [llvm] r113614 - in /llvm/trunk/lib/CodeGen: RegAllocFast.cpp SelectionDAG/FastISel.cpp Message-ID: <20100910203209.807452A6C12C@llvm.org> Author: dpatel Date: Fri Sep 10 15:32:09 2010 New Revision: 113614 URL: http://llvm.org/viewvc/llvm-project?rev=113614&view=rev Log: Add DEBUG message. Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=113614&r1=113613&r2=113614&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocFast.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp Fri Sep 10 15:32:09 2010 @@ -798,9 +798,11 @@ setPhysReg(MI, i, LRI->second.PhysReg); else { int SS = StackSlotForVirtReg[Reg]; - if (SS == -1) + if (SS == -1) { // We can't allocate a physreg for a DebugValue, sorry! + DEBUG(dbgs() << "Unable to allocate vreg used by DBG_VALUE"); MO.setReg(0); + } else { // Modify DBG_VALUE now that the value is in a spill slot. int64_t Offset = MI->getOperand(1).getImm(); @@ -817,9 +819,11 @@ MI = NewDV; ScanDbgValue = true; break; - } else + } else { // We can't allocate a physreg for a DebugValue; sorry! + DEBUG(dbgs() << "Unable to allocate vreg used by DBG_VALUE"); MO.setReg(0); + } } } } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=113614&r1=113613&r2=113614&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Fri Sep 10 15:32:09 2010 @@ -473,10 +473,18 @@ return true; const AllocaInst *AI = dyn_cast(Address); // Don't handle byval struct arguments or VLAs, for example. - if (!AI) + if (!AI) { // Building the map above is target independent. Generating DBG_VALUE // inline is target dependent; do this now. - (void)TargetSelectInstruction(cast(I)); + DenseMap::iterator It = + FuncInfo.ValueMap.find(Address); + if (0 && It != FuncInfo.ValueMap.end()) { + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, + TII.get(TargetOpcode::DBG_VALUE)) + .addReg(It->second, RegState::Debug).addImm(0).addMetadata(DI->getVariable()); + } else + (void)TargetSelectInstruction(cast(I)); + } return true; } case Intrinsic::dbg_value: { From isanbard at gmail.com Fri Sep 10 15:42:26 2010 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 10 Sep 2010 20:42:26 -0000 Subject: [llvm-commits] [llvm] r113615 - /llvm/trunk/lib/VMCore/AutoUpgrade.cpp Message-ID: <20100910204226.9AD272A6C12C@llvm.org> Author: void Date: Fri Sep 10 15:42:26 2010 New Revision: 113615 URL: http://llvm.org/viewvc/llvm-project?rev=113615&view=rev Log: Use StringRef which performs the "early exit" when compared against a constant string. Modified: llvm/trunk/lib/VMCore/AutoUpgrade.cpp Modified: llvm/trunk/lib/VMCore/AutoUpgrade.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AutoUpgrade.cpp?rev=113615&r1=113614&r2=113615&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/AutoUpgrade.cpp (original) +++ llvm/trunk/lib/VMCore/AutoUpgrade.cpp Fri Sep 10 15:42:26 2010 @@ -366,12 +366,7 @@ } bool llvm::UpgradeGlobalVariable(GlobalVariable *GV) { - const std::string &Name = GV->getName(); - - // Early exit with simple tests. - if (Name.length() != 24 || Name[0] != '.' || Name[1] != 'l' || - Name[3] != 'l' || Name[4] != 'v' || Name[5] != 'm' || Name[6] != '.') - return false; + StringRef Name(GV->getName()); // We are only upgrading one symbol here. if (Name == ".llvm.eh.catch.all.value") { From isanbard at gmail.com Fri Sep 10 15:43:45 2010 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 10 Sep 2010 13:43:45 -0700 Subject: [llvm-commits] [llvm] r113603 - /llvm/trunk/lib/VMCore/AutoUpgrade.cpp In-Reply-To: References: <20100910190658.89DFC2A6C12C@llvm.org> Message-ID: <80D0A9E0-6925-4DEA-9A7E-A7F84F1F98C4@gmail.com> On Sep 10, 2010, at 1:27 PM, Chris Lattner wrote: > On Sep 10, 2010, at 12:06 PM, Bill Wendling wrote: > >> Author: void >> Date: Fri Sep 10 14:06:58 2010 >> New Revision: 113603 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=113603&view=rev >> Log: >> Early exit with simple checks. > > Hi Bill, please capture Name as a StringRef instead of std::string. > > The early exit isn't needed, stringref does it for you in == with a constant string. > Oh nice. Done! -bw From dalej at apple.com Fri Sep 10 15:55:01 2010 From: dalej at apple.com (Dale Johannesen) Date: Fri, 10 Sep 2010 20:55:01 -0000 Subject: [llvm-commits] [llvm] r113618 - in /llvm/trunk: bindings/ocaml/llvm/ include/llvm-c/ include/llvm/ include/llvm/Bitcode/ include/llvm/Support/ lib/AsmParser/ lib/Bitcode/Reader/ lib/Bitcode/Writer/ lib/Target/ lib/Target/CBackend/ lib/Target/CppBackend/ lib/VMCore/ Message-ID: <20100910205501.8F6CC2A6C12C@llvm.org> Author: johannes Date: Fri Sep 10 15:55:01 2010 New Revision: 113618 URL: http://llvm.org/viewvc/llvm-project?rev=113618&view=rev Log: Add X86 MMX type to bitcode and Type. (The Ada bindings probably need it too, but all the obvious places to change say "do not edit this file".) Modified: llvm/trunk/bindings/ocaml/llvm/llvm_ocaml.c llvm/trunk/include/llvm-c/Core.h llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h llvm/trunk/include/llvm/Support/TypeBuilder.h llvm/trunk/include/llvm/Type.h llvm/trunk/lib/AsmParser/LLLexer.cpp llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp llvm/trunk/lib/Target/CBackend/CBackend.cpp llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp llvm/trunk/lib/Target/TargetData.cpp llvm/trunk/lib/VMCore/AsmWriter.cpp llvm/trunk/lib/VMCore/Core.cpp llvm/trunk/lib/VMCore/LLVMContextImpl.cpp llvm/trunk/lib/VMCore/LLVMContextImpl.h llvm/trunk/lib/VMCore/Type.cpp llvm/trunk/lib/VMCore/ValueTypes.cpp Modified: llvm/trunk/bindings/ocaml/llvm/llvm_ocaml.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/bindings/ocaml/llvm/llvm_ocaml.c?rev=113618&r1=113617&r2=113618&view=diff ============================================================================== --- llvm/trunk/bindings/ocaml/llvm/llvm_ocaml.c (original) +++ llvm/trunk/bindings/ocaml/llvm/llvm_ocaml.c Fri Sep 10 15:55:01 2010 @@ -264,6 +264,11 @@ return LLVMPPCFP128TypeInContext(Context); } +/* llcontext -> lltype */ +CAMLprim LLVMTypeRef llvm_x86mmx_type(LLVMContextRef Context) { + return LLVMX86MMXTypeInContext(Context); +} + /*--... Operations on function types .......................................--*/ /* lltype -> lltype array -> lltype */ Modified: llvm/trunk/include/llvm-c/Core.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm-c/Core.h?rev=113618&r1=113617&r2=113618&view=diff ============================================================================== --- llvm/trunk/include/llvm-c/Core.h (original) +++ llvm/trunk/include/llvm-c/Core.h Fri Sep 10 15:55:01 2010 @@ -204,7 +204,8 @@ LLVMPointerTypeKind, /**< Pointers */ LLVMOpaqueTypeKind, /**< Opaque: type with unknown structure */ LLVMVectorTypeKind, /**< SIMD 'packed' format, or other vector type */ - LLVMMetadataTypeKind /**< Metadata */ + LLVMMetadataTypeKind, /**< Metadata */ + LLVMX86_MMXTypeKind /**< X86 MMX */ } LLVMTypeKind; typedef enum { Modified: llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h?rev=113618&r1=113617&r2=113618&view=diff ============================================================================== --- llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h (original) +++ llvm/trunk/include/llvm/Bitcode/LLVMBitCodes.h Fri Sep 10 15:55:01 2010 @@ -94,7 +94,9 @@ TYPE_CODE_FP128 = 14, // LONG DOUBLE (112 bit mantissa) TYPE_CODE_PPC_FP128= 15, // PPC LONG DOUBLE (2 doubles) - TYPE_CODE_METADATA = 16 // METADATA + TYPE_CODE_METADATA = 16, // METADATA + + TYPE_CODE_X86_MMX = 17 // X86 MMX }; // The type symbol table only has one code (TST_ENTRY_CODE). Modified: llvm/trunk/include/llvm/Support/TypeBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/TypeBuilder.h?rev=113618&r1=113617&r2=113618&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/TypeBuilder.h (original) +++ llvm/trunk/include/llvm/Support/TypeBuilder.h Fri Sep 10 15:55:01 2010 @@ -88,6 +88,8 @@ class x86_fp80 {}; class fp128 {}; class ppc_fp128 {}; +// X86 MMX. +class x86_mmx {}; } // namespace types // LLVM doesn't have const or volatile types. @@ -219,6 +221,10 @@ public: static const Type *get(LLVMContext& C) { return Type::getPPC_FP128Ty(C); } }; +template class TypeBuilder { +public: + static const Type *get(LLVMContext& C) { return Type::getX86_MMXTy(C); } +}; template class TypeBuilder { public: Modified: llvm/trunk/include/llvm/Type.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Type.h?rev=113618&r1=113617&r2=113618&view=diff ============================================================================== --- llvm/trunk/include/llvm/Type.h (original) +++ llvm/trunk/include/llvm/Type.h Fri Sep 10 15:55:01 2010 @@ -76,19 +76,20 @@ PPC_FP128TyID, ///< 5: 128 bit floating point type (two 64-bits) LabelTyID, ///< 6: Labels MetadataTyID, ///< 7: Metadata + X86_MMXTyID, ///< 8: MMX vectors (64 bits) // Derived types... see DerivedTypes.h file... // Make sure FirstDerivedTyID stays up to date!!! - IntegerTyID, ///< 8: Arbitrary bit width integers - FunctionTyID, ///< 9: Functions - StructTyID, ///< 10: Structures - ArrayTyID, ///< 11: Arrays - PointerTyID, ///< 12: Pointers - OpaqueTyID, ///< 13: Opaque: type with unknown structure - VectorTyID, ///< 14: SIMD 'packed' format, or other vector type + IntegerTyID, ///< 9: Arbitrary bit width integers + FunctionTyID, ///< 10: Functions + StructTyID, ///< 11: Structures + ArrayTyID, ///< 12: Arrays + PointerTyID, ///< 13: Pointers + OpaqueTyID, ///< 14: Opaque: type with unknown structure + VectorTyID, ///< 15: SIMD 'packed' format, or other vector type NumTypeIDs, // Must remain as last defined ID - LastPrimitiveTyID = MetadataTyID, + LastPrimitiveTyID = X86_MMXTyID, FirstDerivedTyID = IntegerTyID }; @@ -212,6 +213,9 @@ bool isFloatingPointTy() const { return ID == FloatTyID || ID == DoubleTyID || ID == X86_FP80TyID || ID == FP128TyID || ID == PPC_FP128TyID; } + /// isPPC_FP128Ty - Return true if this is X86 MMX. + bool isX86_MMXTy() const { return ID == X86_MMXTyID; } + /// isFPOrFPVectorTy - Return true if this is a FP type or a vector of FP. /// bool isFPOrFPVectorTy() const; @@ -400,6 +404,7 @@ static const Type *getX86_FP80Ty(LLVMContext &C); static const Type *getFP128Ty(LLVMContext &C); static const Type *getPPC_FP128Ty(LLVMContext &C); + static const Type *getX86_MMXTy(LLVMContext &C); static const IntegerType *getIntNTy(LLVMContext &C, unsigned N); static const IntegerType *getInt1Ty(LLVMContext &C); static const IntegerType *getInt8Ty(LLVMContext &C); @@ -416,6 +421,7 @@ static const PointerType *getX86_FP80PtrTy(LLVMContext &C, unsigned AS = 0); static const PointerType *getFP128PtrTy(LLVMContext &C, unsigned AS = 0); static const PointerType *getPPC_FP128PtrTy(LLVMContext &C, unsigned AS = 0); + static const PointerType *getX86_MMXPtrTy(LLVMContext &C, unsigned AS = 0); static const PointerType *getIntNPtrTy(LLVMContext &C, unsigned N, unsigned AS = 0); static const PointerType *getInt1PtrTy(LLVMContext &C, unsigned AS = 0); Modified: llvm/trunk/lib/AsmParser/LLLexer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLLexer.cpp?rev=113618&r1=113617&r2=113618&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLLexer.cpp (original) +++ llvm/trunk/lib/AsmParser/LLLexer.cpp Fri Sep 10 15:55:01 2010 @@ -595,6 +595,7 @@ TYPEKEYWORD("ppc_fp128", Type::getPPC_FP128Ty(Context)); TYPEKEYWORD("label", Type::getLabelTy(Context)); TYPEKEYWORD("metadata", Type::getMetadataTy(Context)); + TYPEKEYWORD("x86_mmx", Type::getX86_MMXTy(Context)); #undef TYPEKEYWORD // Handle special forms for autoupgrading. Drop these in LLVM 3.0. This is Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp?rev=113618&r1=113617&r2=113618&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp (original) +++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp Fri Sep 10 15:55:01 2010 @@ -549,6 +549,9 @@ case bitc::TYPE_CODE_METADATA: // METADATA ResultTy = Type::getMetadataTy(Context); break; + case bitc::TYPE_CODE_X86_MMX: // X86_MMX + ResultTy = Type::getX86_MMXTy(Context); + break; case bitc::TYPE_CODE_INTEGER: // INTEGER: [width] if (Record.size() < 1) return Error("Invalid Integer type record"); Modified: llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp?rev=113618&r1=113617&r2=113618&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp (original) +++ llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp Fri Sep 10 15:55:01 2010 @@ -211,6 +211,7 @@ case Type::LabelTyID: Code = bitc::TYPE_CODE_LABEL; break; case Type::OpaqueTyID: Code = bitc::TYPE_CODE_OPAQUE; break; case Type::MetadataTyID: Code = bitc::TYPE_CODE_METADATA; break; + case Type::X86_MMXTyID: Code = bitc::TYPE_CODE_X86_MMX; break; case Type::IntegerTyID: // INTEGER: [width] Code = bitc::TYPE_CODE_INTEGER; Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=113618&r1=113617&r2=113618&view=diff ============================================================================== --- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original) +++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Fri Sep 10 15:55:01 2010 @@ -514,7 +514,11 @@ case Type::X86_FP80TyID: case Type::PPC_FP128TyID: case Type::FP128TyID: return Out << "long double " << NameSoFar; - + + case Type::X86_MMXTyID: + return printSimpleType(Out, Type::getInt32Ty(Ty->getContext()), isSigned, + " __attribute__((vector_size(64))) " + NameSoFar); + case Type::VectorTyID: { const VectorType *VTy = cast(Ty); return printSimpleType(Out, VTy->getElementType(), isSigned, Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp?rev=113618&r1=113617&r2=113618&view=diff ============================================================================== --- llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp (original) +++ llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Fri Sep 10 15:55:01 2010 @@ -358,6 +358,7 @@ case Type::FloatTyID: return "Type::getFloatTy(mod->getContext())"; case Type::DoubleTyID: return "Type::getDoubleTy(mod->getContext())"; case Type::LabelTyID: return "Type::getLabelTy(mod->getContext())"; + case Type::X86_MMXTyID: return "Type::getX86_MMXTy(mod->getContext())"; default: error("Invalid primitive type"); break; Modified: llvm/trunk/lib/Target/TargetData.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetData.cpp?rev=113618&r1=113617&r2=113618&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetData.cpp (original) +++ llvm/trunk/lib/Target/TargetData.cpp Fri Sep 10 15:55:01 2010 @@ -461,6 +461,7 @@ case Type::FloatTyID: return 32; case Type::DoubleTyID: + case Type::X86_MMXTyID: return 64; case Type::PPC_FP128TyID: case Type::FP128TyID: Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=113618&r1=113617&r2=113618&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/AsmWriter.cpp (original) +++ llvm/trunk/lib/VMCore/AsmWriter.cpp Fri Sep 10 15:55:01 2010 @@ -198,6 +198,7 @@ case Type::PPC_FP128TyID: OS << "ppc_fp128"; break; case Type::LabelTyID: OS << "label"; break; case Type::MetadataTyID: OS << "metadata"; break; + case Type::X86_MMXTyID: OS << "x86_mmx"; break; case Type::IntegerTyID: OS << 'i' << cast(Ty)->getBitWidth(); break; Modified: llvm/trunk/lib/VMCore/Core.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Core.cpp?rev=113618&r1=113617&r2=113618&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Core.cpp (original) +++ llvm/trunk/lib/VMCore/Core.cpp Fri Sep 10 15:55:01 2010 @@ -164,6 +164,8 @@ return LLVMOpaqueTypeKind; case Type::VectorTyID: return LLVMVectorTypeKind; + case Type::X86_MMXTyID: + return LLVMX86_MMXTypeKind; } } @@ -232,6 +234,9 @@ LLVMTypeRef LLVMPPCFP128TypeInContext(LLVMContextRef C) { return (LLVMTypeRef) Type::getPPC_FP128Ty(*unwrap(C)); } +LLVMTypeRef LLVMX86MMXTypeInContext(LLVMContextRef C) { + return (LLVMTypeRef) Type::getX86_MMXTy(*unwrap(C)); +} LLVMTypeRef LLVMFloatType(void) { return LLVMFloatTypeInContext(LLVMGetGlobalContext()); @@ -248,6 +253,9 @@ LLVMTypeRef LLVMPPCFP128Type(void) { return LLVMPPCFP128TypeInContext(LLVMGetGlobalContext()); } +LLVMTypeRef LLVMX86MMXType(void) { + return LLVMX86MMXTypeInContext(LLVMGetGlobalContext()); +} /*--.. Operations on function types ........................................--*/ Modified: llvm/trunk/lib/VMCore/LLVMContextImpl.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/LLVMContextImpl.cpp?rev=113618&r1=113617&r2=113618&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/LLVMContextImpl.cpp (original) +++ llvm/trunk/lib/VMCore/LLVMContextImpl.cpp Fri Sep 10 15:55:01 2010 @@ -26,6 +26,7 @@ X86_FP80Ty(C, Type::X86_FP80TyID), FP128Ty(C, Type::FP128TyID), PPC_FP128Ty(C, Type::PPC_FP128TyID), + X86_MMXTy(C, Type::X86_MMXTyID), Int1Ty(C, 1), Int8Ty(C, 8), Int16Ty(C, 16), Modified: llvm/trunk/lib/VMCore/LLVMContextImpl.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/LLVMContextImpl.h?rev=113618&r1=113617&r2=113618&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/LLVMContextImpl.h (original) +++ llvm/trunk/lib/VMCore/LLVMContextImpl.h Fri Sep 10 15:55:01 2010 @@ -174,6 +174,7 @@ const Type X86_FP80Ty; const Type FP128Ty; const Type PPC_FP128Ty; + const Type X86_MMXTy; const IntegerType Int1Ty; const IntegerType Int8Ty; const IntegerType Int16Ty; Modified: llvm/trunk/lib/VMCore/Type.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Type.cpp?rev=113618&r1=113617&r2=113618&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Type.cpp (original) +++ llvm/trunk/lib/VMCore/Type.cpp Fri Sep 10 15:55:01 2010 @@ -109,6 +109,7 @@ case PPC_FP128TyID : return getPPC_FP128Ty(C); case LabelTyID : return getLabelTy(C); case MetadataTyID : return getMetadataTy(C); + case X86_MMXTyID : return getX86_MMXTy(C); default: return 0; } @@ -192,6 +193,7 @@ case Type::X86_FP80TyID: return 80; case Type::FP128TyID: return 128; case Type::PPC_FP128TyID: return 128; + case Type::X86_MMXTyID: return 64; case Type::IntegerTyID: return cast(this)->getBitWidth(); case Type::VectorTyID: return cast(this)->getBitWidth(); default: return 0; @@ -354,6 +356,10 @@ return &C.pImpl->PPC_FP128Ty; } +const Type *Type::getX86_MMXTy(LLVMContext &C) { + return &C.pImpl->X86_MMXTy; +} + const IntegerType *Type::getIntNTy(LLVMContext &C, unsigned N) { return IntegerType::get(C, N); } @@ -398,6 +404,10 @@ return getPPC_FP128Ty(C)->getPointerTo(AS); } +const PointerType *Type::getX86_MMXPtrTy(LLVMContext &C, unsigned AS) { + return getX86_MMXTy(C)->getPointerTo(AS); +} + const PointerType *Type::getIntNPtrTy(LLVMContext &C, unsigned N, unsigned AS) { return getIntNTy(C, N)->getPointerTo(AS); } Modified: llvm/trunk/lib/VMCore/ValueTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/ValueTypes.cpp?rev=113618&r1=113617&r2=113618&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/ValueTypes.cpp (original) +++ llvm/trunk/lib/VMCore/ValueTypes.cpp Fri Sep 10 15:55:01 2010 @@ -156,6 +156,7 @@ case MVT::f80: return Type::getX86_FP80Ty(Context); case MVT::f128: return Type::getFP128Ty(Context); case MVT::ppcf128: return Type::getPPC_FP128Ty(Context); + case MVT::x86mmx: return Type::getX86_MMXTy(Context); case MVT::v2i8: return VectorType::get(Type::getInt8Ty(Context), 2); case MVT::v4i8: return VectorType::get(Type::getInt8Ty(Context), 4); case MVT::v8i8: return VectorType::get(Type::getInt8Ty(Context), 8); From bigcheesegs at gmail.com Fri Sep 10 16:14:25 2010 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Fri, 10 Sep 2010 21:14:25 -0000 Subject: [llvm-commits] [llvm] r113632 - in /llvm/trunk: ./ cmake/modules/ examples/BrainF/ examples/ExceptionDemo/ examples/Fibonacci/ examples/HowToUseJIT/ examples/Kaleidoscope/Chapter3/ examples/Kaleidoscope/Chapter4/ examples/Kaleidoscope/Chapter5/ examples/Kaleidoscope/Chapter6/ examples/Kaleidoscope/Chapter7/ examples/ModuleMaker/ examples/ParallelJIT/ lib/Analysis/ lib/Analysis/IPA/ lib/Archive/ lib/AsmParser/ lib/Bitcode/Reader/ lib/CodeGen/ lib/CodeGen/AsmPrinter/ lib/CodeGen/SelectionDAG/ lib/CompilerDriver/ lib/Exec... Message-ID: <20100910211425.C5FE82A6C12C@llvm.org> Author: mspencer Date: Fri Sep 10 16:14:25 2010 New Revision: 113632 URL: http://llvm.org/viewvc/llvm-project?rev=113632&view=rev Log: CMake: Get rid of LLVMLibDeps.cmake and export the libraries normally. Added: llvm/trunk/cmake/modules/LLVMConfig.cmake.in Removed: llvm/trunk/cmake/modules/LLVMConfig.cmake llvm/trunk/cmake/modules/LLVMLibDeps.cmake Modified: llvm/trunk/CMakeLists.txt llvm/trunk/cmake/modules/AddLLVM.cmake llvm/trunk/cmake/modules/CMakeLists.txt llvm/trunk/examples/BrainF/CMakeLists.txt llvm/trunk/examples/ExceptionDemo/CMakeLists.txt llvm/trunk/examples/Fibonacci/CMakeLists.txt llvm/trunk/examples/HowToUseJIT/CMakeLists.txt llvm/trunk/examples/Kaleidoscope/Chapter3/CMakeLists.txt llvm/trunk/examples/Kaleidoscope/Chapter4/CMakeLists.txt llvm/trunk/examples/Kaleidoscope/Chapter5/CMakeLists.txt llvm/trunk/examples/Kaleidoscope/Chapter6/CMakeLists.txt llvm/trunk/examples/Kaleidoscope/Chapter7/CMakeLists.txt llvm/trunk/examples/ModuleMaker/CMakeLists.txt llvm/trunk/examples/ParallelJIT/CMakeLists.txt llvm/trunk/lib/Analysis/CMakeLists.txt llvm/trunk/lib/Analysis/IPA/CMakeLists.txt llvm/trunk/lib/Archive/CMakeLists.txt llvm/trunk/lib/AsmParser/CMakeLists.txt llvm/trunk/lib/Bitcode/Reader/CMakeLists.txt llvm/trunk/lib/CodeGen/AsmPrinter/CMakeLists.txt llvm/trunk/lib/CodeGen/CMakeLists.txt llvm/trunk/lib/CodeGen/SelectionDAG/CMakeLists.txt llvm/trunk/lib/CompilerDriver/CMakeLists.txt llvm/trunk/lib/ExecutionEngine/CMakeLists.txt llvm/trunk/lib/ExecutionEngine/Interpreter/CMakeLists.txt llvm/trunk/lib/ExecutionEngine/JIT/CMakeLists.txt llvm/trunk/lib/Linker/CMakeLists.txt llvm/trunk/lib/MC/MCDisassembler/CMakeLists.txt llvm/trunk/lib/Target/ARM/AsmParser/CMakeLists.txt llvm/trunk/lib/Target/ARM/AsmPrinter/CMakeLists.txt llvm/trunk/lib/Target/ARM/CMakeLists.txt llvm/trunk/lib/Target/CMakeLists.txt llvm/trunk/lib/Target/X86/AsmParser/CMakeLists.txt llvm/trunk/lib/Target/X86/AsmPrinter/CMakeLists.txt llvm/trunk/lib/Target/X86/CMakeLists.txt llvm/trunk/lib/Target/X86/Disassembler/CMakeLists.txt llvm/trunk/lib/Transforms/IPO/CMakeLists.txt llvm/trunk/lib/Transforms/InstCombine/CMakeLists.txt llvm/trunk/lib/Transforms/Instrumentation/CMakeLists.txt llvm/trunk/lib/Transforms/Scalar/CMakeLists.txt llvm/trunk/lib/Transforms/Utils/CMakeLists.txt llvm/trunk/tools/CMakeLists.txt llvm/trunk/tools/bugpoint/CMakeLists.txt llvm/trunk/tools/llc/CMakeLists.txt llvm/trunk/tools/lli/CMakeLists.txt llvm/trunk/tools/llvm-ar/CMakeLists.txt llvm/trunk/tools/llvm-as/CMakeLists.txt llvm/trunk/tools/llvm-bcanalyzer/CMakeLists.txt llvm/trunk/tools/llvm-config/CMakeLists.txt llvm/trunk/tools/llvm-diff/CMakeLists.txt llvm/trunk/tools/llvm-dis/CMakeLists.txt llvm/trunk/tools/llvm-extract/CMakeLists.txt llvm/trunk/tools/llvm-ld/CMakeLists.txt llvm/trunk/tools/llvm-link/CMakeLists.txt llvm/trunk/tools/llvm-mc/CMakeLists.txt llvm/trunk/tools/llvm-nm/CMakeLists.txt llvm/trunk/tools/llvm-prof/CMakeLists.txt llvm/trunk/tools/llvm-ranlib/CMakeLists.txt llvm/trunk/tools/opt/CMakeLists.txt Modified: llvm/trunk/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/CMakeLists.txt (original) +++ llvm/trunk/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -263,6 +263,7 @@ # Everything else depends on Support and System: set(LLVM_COMMON_DEPENDS ${LLVM_COMMON_DEPENDS} ${LLVM_LIBS} ) +set(LLVM_COMMON_LIBS LLVMSupport LLVMSystem) set(LLVM_TABLEGEN "tblgen" CACHE STRING "Native TableGen executable. Saves building one when cross-compiling.") @@ -362,6 +363,11 @@ add_subdirectory(cmake/modules) +install(EXPORT LLVM + DESTINATION lib${LLVM_LIBDIR_SUFFIX}/cmake/llvm/ + FILE LLVMTargets.cmake + ) + install(DIRECTORY include/ DESTINATION include FILES_MATCHING Modified: llvm/trunk/cmake/modules/AddLLVM.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/AddLLVM.cmake?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/cmake/modules/AddLLVM.cmake (original) +++ llvm/trunk/cmake/modules/AddLLVM.cmake Fri Sep 10 16:14:25 2010 @@ -1,5 +1,21 @@ include(LLVMProcessSources) -include(LLVMConfig) + +function(get_system_libs return_var) + # Returns in `return_var' a list of system libraries used by LLVM. + if( NOT MSVC ) + if( MINGW ) + set(system_libs ${system_libs} imagehlp psapi) + elseif( CMAKE_HOST_UNIX ) + if( HAVE_LIBDL ) + set(system_libs ${system_libs} ${CMAKE_DL_LIBS}) + endif() + if( LLVM_ENABLE_THREADS AND HAVE_LIBPTHREAD ) + set(system_libs ${system_libs} pthread) + endif() + endif( MINGW ) + endif( NOT MSVC ) + set(${return_var} ${system_libs} PARENT_SCOPE) +endfunction(get_system_libs) macro(add_llvm_library name) llvm_process_sources( ALL_FILES ${ARGN} ) @@ -9,7 +25,11 @@ if( LLVM_COMMON_DEPENDS ) add_dependencies( ${name} ${LLVM_COMMON_DEPENDS} ) endif( LLVM_COMMON_DEPENDS ) + if (LLVM_COMMON_LIBS) + target_link_libraries(${name} ${LLVM_COMMON_LIBS}) + endif() install(TARGETS ${name} + EXPORT LLVM LIBRARY DESTINATION lib${LLVM_LIBDIR_SUFFIX} ARCHIVE DESTINATION lib${LLVM_LIBDIR_SUFFIX}) # The LLVM Target library shall be built before its sublibraries @@ -38,6 +58,7 @@ endif() install(TARGETS ${name} + EXPORT LLVM LIBRARY DESTINATION lib${LLVM_LIBDIR_SUFFIX} ARCHIVE DESTINATION lib${LLVM_LIBDIR_SUFFIX}) endif() @@ -57,9 +78,6 @@ target_link_libraries( ${name} ${lib} ) endforeach(lib) endif( LLVM_USED_LIBS ) - if( LLVM_LINK_COMPONENTS ) - llvm_config(${name} ${LLVM_LINK_COMPONENTS}) - endif( LLVM_LINK_COMPONENTS ) get_system_libs(llvm_system_libs) if( llvm_system_libs ) target_link_libraries(${name} ${llvm_system_libs}) @@ -67,6 +85,9 @@ if( LLVM_COMMON_DEPENDS ) add_dependencies( ${name} ${LLVM_COMMON_DEPENDS} ) endif( LLVM_COMMON_DEPENDS ) + if (LLVM_COMMON_LIBS) + target_link_libraries(${name} ${LLVM_COMMON_LIBS}) + endif() endmacro(add_llvm_executable name) @@ -107,3 +128,61 @@ endif (TABLEGEN_OUTPUT) set(CURRENT_LLVM_TARGET LLVM${target_name} PARENT_SCOPE) endmacro(add_llvm_target) + +macro(llvm_get_target_libraries return_var) + set( link_components ${ARGN} ) + foreach(c ${link_components}) + # add codegen, asmprinter, asmparser, disassembler + list(FIND LLVM_TARGETS_TO_BUILD ${c} idx) + if( NOT idx LESS 0 ) + list(FIND llvm_libs "LLVM${c}CodeGen" idx) + if( NOT idx LESS 0 ) + list(APPEND expanded_components "LLVM${c}CodeGen") + else() + list(FIND llvm_libs "LLVM${c}" idx) + if( NOT idx LESS 0 ) + list(APPEND expanded_components "LLVM${c}") + else() + message(FATAL_ERROR "Target ${c} is not in the set of libraries.") + endif() + endif() + list(FIND llvm_libs "LLVM${c}AsmPrinter" asmidx) + if( NOT asmidx LESS 0 ) + list(APPEND expanded_components "LLVM${c}AsmPrinter") + endif() + list(FIND llvm_libs "LLVM${c}AsmParser" asmidx) + if( NOT asmidx LESS 0 ) + list(APPEND expanded_components "LLVM${c}AsmParser") + endif() + list(FIND llvm_libs "LLVM${c}Info" asmidx) + if( NOT asmidx LESS 0 ) + list(APPEND expanded_components "LLVM${c}Info") + endif() + list(FIND llvm_libs "LLVM${c}Disassembler" asmidx) + if( NOT asmidx LESS 0 ) + list(APPEND expanded_components "LLVM${c}Disassembler") + endif() + elseif( c STREQUAL "native" ) + list(APPEND expanded_components "LLVM${LLVM_NATIVE_ARCH}CodeGen") + elseif( c STREQUAL "nativecodegen" ) + list(APPEND expanded_components "LLVM${LLVM_NATIVE_ARCH}CodeGen") + elseif( c STREQUAL "backend" ) + # same case as in `native'. + elseif( c STREQUAL "engine" OR c STREQUAL "jit") + # TODO: as we assume we are on X86, this is `jit'. + list(APPEND expanded_components "LLVMJIT") + elseif( c STREQUAL "interpreter" ) + list(APPEND expanded_components "LLVMInterpreter") + elseif( c STREQUAL "all" ) + list(APPEND expanded_components ${llvm_libs}) + else( NOT idx LESS 0 ) + list(APPEND expanded_components LLVM${c}) + endif( NOT idx LESS 0 ) + endforeach(c) + set(${return_var} ${expanded_components}) +endmacro(llvm_get_target_libraries) + +macro(add_llvm_link_components target_name) + llvm_get_target_libraries(target_libs ${ARGN}) + target_link_libraries(${target_name} ${target_libs}) +endmacro() Modified: llvm/trunk/cmake/modules/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/cmake/modules/CMakeLists.txt (original) +++ llvm/trunk/cmake/modules/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -1,12 +1,18 @@ -set(llvm_cmake_builddir "${LLVM_BINARY_DIR}/share/llvm/cmake") +set(LLVM_CFLAGS "${CMAKE_C_FLAGS_${uppercase_CMAKE_BUILD_TYPE}} ${LLVM_DEFINITIONS}") +set(LLVM_CXXFLAGS "${CMAKE_CXX_FLAGS_${uppercase_CMAKE_BUILD_TYPE}} ${LLVM_DEFINITIONS}") +set(LLVM_CPPFLAGS "${CMAKE_CPP_FLAGS_${uppercase_CMAKE_BUILD_TYPE}} ${LLVM_DEFINITIONS}") +llvm_get_target_libraries(LLVM_JIT_LIBS jit) +llvm_get_target_libraries(LLVM_INTERPRETER_LIBS interpreter) +llvm_get_target_libraries(LLVM_NATIVECODEGEN_LIBS nativecodegen) +get_system_libs(LLVM_SYSTEM_LIBS) configure_file( - LLVM.cmake - ${llvm_cmake_builddir}/LLVM.cmake - @ONLY) + LLVMConfig.cmake.in + ${LLVM_BINARY_DIR}/cmake/modules/LLVMConfig.cmake + @ONLY + ) install(FILES - ${llvm_cmake_builddir}/LLVM.cmake - LLVMConfig.cmake - LLVMLibDeps.cmake - DESTINATION share/llvm/cmake) + ${LLVM_BINARY_DIR}/cmake/modules/LLVMConfig.cmake + DESTINATION lib${LLVM_LIBDIR_SUFFIX}/cmake/llvm/ + ) Removed: llvm/trunk/cmake/modules/LLVMConfig.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/LLVMConfig.cmake?rev=113631&view=auto ============================================================================== --- llvm/trunk/cmake/modules/LLVMConfig.cmake (original) +++ llvm/trunk/cmake/modules/LLVMConfig.cmake (removed) @@ -1,165 +0,0 @@ -function(get_system_libs return_var) - # Returns in `return_var' a list of system libraries used by LLVM. - if( NOT MSVC ) - if( MINGW ) - set(system_libs ${system_libs} imagehlp psapi) - elseif( CMAKE_HOST_UNIX ) - if( HAVE_LIBDL ) - set(system_libs ${system_libs} ${CMAKE_DL_LIBS}) - endif() - if( LLVM_ENABLE_THREADS AND HAVE_LIBPTHREAD ) - set(system_libs ${system_libs} pthread) - endif() - endif( MINGW ) - endif( NOT MSVC ) - set(${return_var} ${system_libs} PARENT_SCOPE) -endfunction(get_system_libs) - - -function(is_llvm_target_library library return_var) - # Sets variable `return_var' to ON if `library' corresponds to a - # LLVM supported target. To OFF if it doesn't. - set(${return_var} OFF PARENT_SCOPE) - string(TOUPPER "${library}" capitalized_lib) - string(TOUPPER "${LLVM_ALL_TARGETS}" targets) - foreach(t ${targets}) - if( capitalized_lib STREQUAL "LLVM${t}" OR - capitalized_lib STREQUAL "LLVM${t}CODEGEN" OR - capitalized_lib STREQUAL "LLVM${t}ASMPARSER" OR - capitalized_lib STREQUAL "LLVM${t}ASMPRINTER" OR - capitalized_lib STREQUAL "LLVM${t}DISASSEMBLER" OR - capitalized_lib STREQUAL "LLVM${t}INFO" ) - set(${return_var} ON PARENT_SCOPE) - break() - endif() - endforeach() -endfunction(is_llvm_target_library) - - -macro(llvm_config executable) - explicit_llvm_config(${executable} ${ARGN}) -endmacro(llvm_config) - - -function(explicit_llvm_config executable) - set( link_components ${ARGN} ) - - explicit_map_components_to_libraries(LIBRARIES ${link_components}) - target_link_libraries(${executable} ${LIBRARIES}) -endfunction(explicit_llvm_config) - - -# This is a variant intended for the final user: -function(llvm_map_components_to_libraries OUT_VAR) - explicit_map_components_to_libraries(result ${ARGN}) - get_system_libs(sys_result) - set( ${OUT_VAR} ${result} ${sys_result} PARENT_SCOPE ) -endfunction(llvm_map_components_to_libraries) - - -function(explicit_map_components_to_libraries out_libs) - set( link_components ${ARGN} ) - foreach(c ${link_components}) - # add codegen, asmprinter, asmparser, disassembler - list(FIND LLVM_TARGETS_TO_BUILD ${c} idx) - if( NOT idx LESS 0 ) - list(FIND llvm_libs "LLVM${c}CodeGen" idx) - if( NOT idx LESS 0 ) - list(APPEND expanded_components "LLVM${c}CodeGen") - else() - list(FIND llvm_libs "LLVM${c}" idx) - if( NOT idx LESS 0 ) - list(APPEND expanded_components "LLVM${c}") - else() - message(FATAL_ERROR "Target ${c} is not in the set of libraries.") - endif() - endif() - list(FIND llvm_libs "LLVM${c}AsmPrinter" asmidx) - if( NOT asmidx LESS 0 ) - list(APPEND expanded_components "LLVM${c}AsmPrinter") - endif() - list(FIND llvm_libs "LLVM${c}AsmParser" asmidx) - if( NOT asmidx LESS 0 ) - list(APPEND expanded_components "LLVM${c}AsmParser") - endif() - list(FIND llvm_libs "LLVM${c}Info" asmidx) - if( NOT asmidx LESS 0 ) - list(APPEND expanded_components "LLVM${c}Info") - endif() - list(FIND llvm_libs "LLVM${c}Disassembler" asmidx) - if( NOT asmidx LESS 0 ) - list(APPEND expanded_components "LLVM${c}Disassembler") - endif() - elseif( c STREQUAL "native" ) - list(APPEND expanded_components "LLVM${LLVM_NATIVE_ARCH}CodeGen") - elseif( c STREQUAL "nativecodegen" ) - list(APPEND expanded_components "LLVM${LLVM_NATIVE_ARCH}CodeGen") - elseif( c STREQUAL "backend" ) - # same case as in `native'. - elseif( c STREQUAL "engine" ) - # TODO: as we assume we are on X86, this is `jit'. - list(APPEND expanded_components "LLVMJIT") - elseif( c STREQUAL "all" ) - list(APPEND expanded_components ${llvm_libs}) - else( NOT idx LESS 0 ) - list(APPEND expanded_components LLVM${c}) - endif( NOT idx LESS 0 ) - endforeach(c) - # We must match capitalization. - string(TOUPPER "${llvm_libs}" capitalized_libs) - list(REMOVE_DUPLICATES expanded_components) - list(LENGTH expanded_components lst_size) - set(result "") - while( 0 LESS ${lst_size} ) - list(GET expanded_components 0 c) - string(TOUPPER "${c}" capitalized) - list(FIND capitalized_libs ${capitalized} idx) - set(add_it ON) - if( idx LESS 0 ) - # The library is unkown. Maybe is an ommitted target? - is_llvm_target_library(${c} iltl_result) - if( NOT iltl_result ) - message(FATAL_ERROR "Library ${c} not found in list of llvm libraries.") - endif() - set(add_it OFF) - endif( idx LESS 0 ) - list(GET llvm_libs ${idx} canonical_lib) - list(REMOVE_ITEM result ${canonical_lib}) - foreach(c ${MSVC_LIB_DEPS_${canonical_lib}}) - list(REMOVE_ITEM expanded_components ${c}) - endforeach() - if( add_it ) - list(APPEND result ${canonical_lib}) - list(APPEND expanded_components ${MSVC_LIB_DEPS_${canonical_lib}}) - endif() - list(REMOVE_AT expanded_components 0) - list(LENGTH expanded_components lst_size) - endwhile( 0 LESS ${lst_size} ) - set(${out_libs} ${result} PARENT_SCOPE) -endfunction(explicit_map_components_to_libraries) - - -# The library dependency data is contained in the file -# LLVMLibDeps.cmake on this directory. It is automatically generated -# by tools/llvm-config/CMakeLists.txt when the build comprises all the -# targets and we are on a environment Posix enough to build the -# llvm-config script. This, in practice, just excludes MSVC. - -# When you remove or rename a library from the build, be sure to -# remove its file from lib/ as well, or the GenLibDeps.pl script will -# include it on its analysis! - -# The format generated by GenLibDeps.pl - -# libLLVMARMAsmPrinter.a: libLLVMMC.a libLLVMSupport.a - -# is translated to: - -# set(MSVC_LIB_DEPS_LLVMARMAsmPrinter LLVMMC LLVMSupport) - -# It is necessary to remove the `lib' prefix and the `.a' suffix. - -# This 'sed' script should do the trick: -# sed -e s'#\.a##g' -e 's#libLLVM#LLVM#g' -e 's#: # #' -e 's#\(.*\)#set(MSVC_LIB_DEPS_\1)#' ~/llvm/tools/llvm-config/LibDeps.txt - -include(LLVMLibDeps) Added: llvm/trunk/cmake/modules/LLVMConfig.cmake.in URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/LLVMConfig.cmake.in?rev=113632&view=auto ============================================================================== --- llvm/trunk/cmake/modules/LLVMConfig.cmake.in (added) +++ llvm/trunk/cmake/modules/LLVMConfig.cmake.in Fri Sep 10 16:14:25 2010 @@ -0,0 +1,11 @@ +get_filename_component(SELF_DIR "${CMAKE_CURRENT_LIST_FILE}" PATH) +include(${SELF_DIR}/LLVMTargets.cmake) +get_filename_component(LLVM_INCLUDE_DIRS "${SELF_DIR}/../../../include" ABSOLUTE) +set(LLVM_CPPFLAGS "@LLVM_CPPFLAGS@") +set(LLVM_CFLAGS "@LLVM_CFLAGS@") +set(LLVM_CXXFLAGS "@LLVM_CXXFLAGS@") +set(LLVM_SYSTEM_LIBS "@LLVM_SYSTEM_LIBS@") +set(LLVM_JIT_LIBS "@LLVM_JIT_LIBS@") +set(LLVM_INTERPRETER_LIBS "@LLVM_INTERPRETER_LIBS@") +set(LLVM_NATIVECODEGEN_LIBS "@LLVM_NATIVECODEGEN_LIBS@") +set(LLVM_BUILDMODE "@LLVM_BUILDMODE@") Removed: llvm/trunk/cmake/modules/LLVMLibDeps.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/LLVMLibDeps.cmake?rev=113631&view=auto ============================================================================== --- llvm/trunk/cmake/modules/LLVMLibDeps.cmake (original) +++ llvm/trunk/cmake/modules/LLVMLibDeps.cmake (removed) @@ -1,71 +0,0 @@ -set(MSVC_LIB_DEPS_LLVMARMAsmParser LLVMARMInfo LLVMMC LLVMMCParser LLVMSupport LLVMTarget) -set(MSVC_LIB_DEPS_LLVMARMAsmPrinter LLVMMC LLVMSupport) -set(MSVC_LIB_DEPS_LLVMARMCodeGen LLVMARMInfo LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget) -set(MSVC_LIB_DEPS_LLVMARMInfo LLVMSupport) -set(MSVC_LIB_DEPS_LLVMAlphaAsmPrinter LLVMAlphaInfo LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSupport LLVMTarget) -set(MSVC_LIB_DEPS_LLVMAlphaCodeGen LLVMAlphaInfo LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget) -set(MSVC_LIB_DEPS_LLVMAlphaInfo LLVMSupport) -set(MSVC_LIB_DEPS_LLVMAnalysis LLVMCore LLVMSupport LLVMSystem LLVMTarget) -set(MSVC_LIB_DEPS_LLVMArchive LLVMBitReader LLVMCore LLVMSupport LLVMSystem) -set(MSVC_LIB_DEPS_LLVMAsmParser LLVMCore LLVMSupport) -set(MSVC_LIB_DEPS_LLVMAsmPrinter LLVMAnalysis LLVMCodeGen LLVMCore LLVMMC LLVMMCParser LLVMSupport LLVMSystem LLVMTarget) -set(MSVC_LIB_DEPS_LLVMBitReader LLVMCore LLVMSupport) -set(MSVC_LIB_DEPS_LLVMBitWriter LLVMCore LLVMSupport) -set(MSVC_LIB_DEPS_LLVMBlackfinAsmPrinter LLVMAsmPrinter LLVMBlackfinInfo LLVMCodeGen LLVMCore LLVMMC LLVMSupport LLVMTarget) -set(MSVC_LIB_DEPS_LLVMBlackfinCodeGen LLVMBlackfinInfo LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget) -set(MSVC_LIB_DEPS_LLVMBlackfinInfo LLVMSupport) -set(MSVC_LIB_DEPS_LLVMCBackend LLVMAnalysis LLVMCBackendInfo LLVMCodeGen LLVMCore LLVMMC LLVMScalarOpts LLVMSupport LLVMSystem LLVMTarget LLVMTransformUtils LLVMipa) -set(MSVC_LIB_DEPS_LLVMCBackendInfo LLVMSupport) -set(MSVC_LIB_DEPS_LLVMCellSPUAsmPrinter LLVMAsmPrinter LLVMCellSPUInfo LLVMCodeGen LLVMCore LLVMMC LLVMSupport LLVMTarget) -set(MSVC_LIB_DEPS_LLVMCellSPUCodeGen LLVMCellSPUInfo LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget) -set(MSVC_LIB_DEPS_LLVMCellSPUInfo LLVMSupport) -set(MSVC_LIB_DEPS_LLVMCodeGen LLVMAnalysis LLVMCore LLVMMC LLVMScalarOpts LLVMSupport LLVMSystem LLVMTarget LLVMTransformUtils) -set(MSVC_LIB_DEPS_LLVMCore LLVMSupport LLVMSystem) -set(MSVC_LIB_DEPS_LLVMCppBackend LLVMCore LLVMCppBackendInfo LLVMSupport LLVMTarget) -set(MSVC_LIB_DEPS_LLVMCppBackendInfo LLVMSupport) -set(MSVC_LIB_DEPS_LLVMExecutionEngine LLVMCore LLVMSupport LLVMSystem LLVMTarget) -set(MSVC_LIB_DEPS_LLVMInstCombine LLVMAnalysis LLVMCore LLVMSupport LLVMSystem LLVMTarget LLVMTransformUtils) -set(MSVC_LIB_DEPS_LLVMInstrumentation LLVMAnalysis LLVMCore LLVMSupport LLVMSystem LLVMTransformUtils) -set(MSVC_LIB_DEPS_LLVMInterpreter LLVMCodeGen LLVMCore LLVMExecutionEngine LLVMSupport LLVMSystem LLVMTarget) -set(MSVC_LIB_DEPS_LLVMJIT LLVMCodeGen LLVMCore LLVMExecutionEngine LLVMMC LLVMSupport LLVMSystem LLVMTarget) -set(MSVC_LIB_DEPS_LLVMLinker LLVMArchive LLVMBitReader LLVMCore LLVMSupport LLVMSystem LLVMTransformUtils) -set(MSVC_LIB_DEPS_LLVMMBlazeAsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMBlazeCodeGen LLVMMBlazeInfo LLVMMC LLVMSupport LLVMTarget) -set(MSVC_LIB_DEPS_LLVMMBlazeCodeGen LLVMCodeGen LLVMCore LLVMMBlazeInfo LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget) -set(MSVC_LIB_DEPS_LLVMMBlazeInfo LLVMSupport) -set(MSVC_LIB_DEPS_LLVMMC LLVMSupport LLVMSystem) -set(MSVC_LIB_DEPS_LLVMMCDisassembler LLVMARMAsmParser LLVMARMCodeGen LLVMARMInfo LLVMAlphaAsmPrinter LLVMAlphaCodeGen LLVMAlphaInfo LLVMBlackfinAsmPrinter LLVMBlackfinCodeGen LLVMBlackfinInfo LLVMCBackend LLVMCBackendInfo LLVMCellSPUAsmPrinter LLVMCellSPUCodeGen LLVMCellSPUInfo LLVMCppBackend LLVMCppBackendInfo LLVMMBlazeAsmPrinter LLVMMBlazeCodeGen LLVMMBlazeInfo LLVMMC LLVMMCParser LLVMMSP430AsmPrinter LLVMMSP430CodeGen LLVMMSP430Info LLVMMipsAsmPrinter LLVMMipsCodeGen LLVMMipsInfo LLVMPIC16AsmPrinter LLVMPIC16CodeGen LLVMPIC16Info LLVMPowerPCAsmPrinter LLVMPowerPCCodeGen LLVMPowerPCInfo LLVMSparcAsmPrinter LLVMSparcCodeGen LLVMSparcInfo LLVMSupport LLVMSystem LLVMSystemZAsmPrinter LLVMSystemZCodeGen LLVMSystemZInfo LLVMX86AsmParser LLVMX86CodeGen LLVMX86Disassembler LLVMX86Info LLVMXCoreAsmPrinter LLVMXCoreCodeGen LLVMXCoreInfo) -set(MSVC_LIB_DEPS_LLVMMCParser LLVMMC LLVMSupport) -set(MSVC_LIB_DEPS_LLVMMSP430AsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMMSP430Info LLVMSupport LLVMTarget) -set(MSVC_LIB_DEPS_LLVMMSP430CodeGen LLVMCodeGen LLVMCore LLVMMC LLVMMSP430Info LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget) -set(MSVC_LIB_DEPS_LLVMMSP430Info LLVMSupport) -set(MSVC_LIB_DEPS_LLVMMipsAsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMMipsCodeGen LLVMMipsInfo LLVMSupport LLVMTarget) -set(MSVC_LIB_DEPS_LLVMMipsCodeGen LLVMCodeGen LLVMCore LLVMMC LLVMMipsInfo LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget) -set(MSVC_LIB_DEPS_LLVMMipsInfo LLVMSupport) -set(MSVC_LIB_DEPS_LLVMPIC16AsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMPIC16CodeGen LLVMPIC16Info LLVMSupport LLVMTarget) -set(MSVC_LIB_DEPS_LLVMPIC16CodeGen LLVMAnalysis LLVMCodeGen LLVMCore LLVMMC LLVMPIC16Info LLVMSelectionDAG LLVMSupport LLVMTarget) -set(MSVC_LIB_DEPS_LLVMPIC16Info LLVMSupport) -set(MSVC_LIB_DEPS_LLVMPowerPCAsmPrinter LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMPowerPCInfo LLVMSupport LLVMTarget) -set(MSVC_LIB_DEPS_LLVMPowerPCCodeGen LLVMCodeGen LLVMCore LLVMMC LLVMPowerPCInfo LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget) -set(MSVC_LIB_DEPS_LLVMPowerPCInfo LLVMSupport) -set(MSVC_LIB_DEPS_LLVMScalarOpts LLVMAnalysis LLVMCore LLVMInstCombine LLVMSupport LLVMSystem LLVMTarget LLVMTransformUtils) -set(MSVC_LIB_DEPS_LLVMSelectionDAG LLVMAnalysis LLVMCodeGen LLVMCore LLVMMC LLVMSupport LLVMSystem LLVMTarget) -set(MSVC_LIB_DEPS_LLVMSparcAsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSparcInfo LLVMSupport LLVMTarget) -set(MSVC_LIB_DEPS_LLVMSparcCodeGen LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSparcInfo LLVMSupport LLVMSystem LLVMTarget) -set(MSVC_LIB_DEPS_LLVMSparcInfo LLVMSupport) -set(MSVC_LIB_DEPS_LLVMSupport LLVMSystem) -set(MSVC_LIB_DEPS_LLVMSystem ) -set(MSVC_LIB_DEPS_LLVMSystemZAsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSupport LLVMSystemZInfo LLVMTarget) -set(MSVC_LIB_DEPS_LLVMSystemZCodeGen LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystemZInfo LLVMTarget) -set(MSVC_LIB_DEPS_LLVMSystemZInfo LLVMSupport) -set(MSVC_LIB_DEPS_LLVMTarget LLVMCore LLVMMC LLVMSupport) -set(MSVC_LIB_DEPS_LLVMTransformUtils LLVMAnalysis LLVMCore LLVMSupport LLVMSystem LLVMTarget LLVMipa) -set(MSVC_LIB_DEPS_LLVMX86AsmParser LLVMMC LLVMMCParser LLVMSupport LLVMTarget LLVMX86Info) -set(MSVC_LIB_DEPS_LLVMX86AsmPrinter LLVMMC LLVMSupport) -set(MSVC_LIB_DEPS_LLVMX86CodeGen LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMSystem LLVMTarget LLVMX86AsmPrinter LLVMX86Info) -set(MSVC_LIB_DEPS_LLVMX86Disassembler LLVMMC LLVMSupport LLVMX86Info) -set(MSVC_LIB_DEPS_LLVMX86Info LLVMSupport) -set(MSVC_LIB_DEPS_LLVMXCoreAsmPrinter LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSupport LLVMTarget LLVMXCoreInfo) -set(MSVC_LIB_DEPS_LLVMXCoreCodeGen LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget LLVMXCoreInfo) -set(MSVC_LIB_DEPS_LLVMXCoreInfo LLVMSupport) -set(MSVC_LIB_DEPS_LLVMipa LLVMAnalysis LLVMCore LLVMSupport LLVMSystem) -set(MSVC_LIB_DEPS_LLVMipo LLVMAnalysis LLVMCore LLVMScalarOpts LLVMSupport LLVMSystem LLVMTarget LLVMTransformUtils LLVMipa) Modified: llvm/trunk/examples/BrainF/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/BrainF/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/examples/BrainF/CMakeLists.txt (original) +++ llvm/trunk/examples/BrainF/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -1,6 +1,7 @@ -set(LLVM_LINK_COMPONENTS jit bitwriter nativecodegen interpreter) - add_llvm_example(BrainF BrainF.cpp BrainFDriver.cpp ) + +add_llvm_link_components(BrainF jit nativecodegen interpreter) +target_link_libraries(BrainF LLVMBitWriter) Modified: llvm/trunk/examples/ExceptionDemo/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/ExceptionDemo/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/examples/ExceptionDemo/CMakeLists.txt (original) +++ llvm/trunk/examples/ExceptionDemo/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -1,5 +1,5 @@ -set(LLVM_LINK_COMPONENTS jit nativecodegen) - add_llvm_example(ExceptionDemo ExceptionDemo.cpp ) + +add_llvm_link_components(ExceptionDemo jit nativecodegen) Modified: llvm/trunk/examples/Fibonacci/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/Fibonacci/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/examples/Fibonacci/CMakeLists.txt (original) +++ llvm/trunk/examples/Fibonacci/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -1,5 +1,5 @@ -set(LLVM_LINK_COMPONENTS jit interpreter nativecodegen) - add_llvm_example(Fibonacci fibonacci.cpp ) + +add_llvm_link_components(Fibonacci jit interpreter nativecodegen) Modified: llvm/trunk/examples/HowToUseJIT/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/HowToUseJIT/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/examples/HowToUseJIT/CMakeLists.txt (original) +++ llvm/trunk/examples/HowToUseJIT/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -1,5 +1,5 @@ -set(LLVM_LINK_COMPONENTS jit interpreter nativecodegen) - add_llvm_example(HowToUseJIT HowToUseJIT.cpp ) + +add_llvm_link_components(HowToUseJIT jit interpreter nativecodegen) Modified: llvm/trunk/examples/Kaleidoscope/Chapter3/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/Kaleidoscope/Chapter3/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/examples/Kaleidoscope/Chapter3/CMakeLists.txt (original) +++ llvm/trunk/examples/Kaleidoscope/Chapter3/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -1,5 +1,5 @@ -set(LLVM_LINK_COMPONENTS core) - add_llvm_example(Kaleidoscope-Ch3 toy.cpp ) + +target_link_libraries(Kaleidoscope-Ch3 LLVMCore) Modified: llvm/trunk/examples/Kaleidoscope/Chapter4/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/Kaleidoscope/Chapter4/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/examples/Kaleidoscope/Chapter4/CMakeLists.txt (original) +++ llvm/trunk/examples/Kaleidoscope/Chapter4/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -1,5 +1,6 @@ -set(LLVM_LINK_COMPONENTS core jit interpreter native) - add_llvm_example(Kaleidoscope-Ch4 toy.cpp ) + +add_llvm_link_components(Kaleidoscope-Ch4 jit interpreter native) +target_link_libraries(Kaleidoscope-Ch4 LLVMCore) Modified: llvm/trunk/examples/Kaleidoscope/Chapter5/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/Kaleidoscope/Chapter5/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/examples/Kaleidoscope/Chapter5/CMakeLists.txt (original) +++ llvm/trunk/examples/Kaleidoscope/Chapter5/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -1,5 +1,6 @@ -set(LLVM_LINK_COMPONENTS core jit interpreter native) - add_llvm_example(Kaleidoscope-Ch5 toy.cpp ) + +add_llvm_link_components(Kaleidoscope-Ch5 jit interpreter native) +target_link_libraries(Kaleidoscope-Ch5 LLVMCore) Modified: llvm/trunk/examples/Kaleidoscope/Chapter6/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/Kaleidoscope/Chapter6/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/examples/Kaleidoscope/Chapter6/CMakeLists.txt (original) +++ llvm/trunk/examples/Kaleidoscope/Chapter6/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -1,5 +1,6 @@ -set(LLVM_LINK_COMPONENTS core jit interpreter native) - add_llvm_example(Kaleidoscope-Ch6 toy.cpp ) + +add_llvm_link_components(Kaleidoscope-Ch6 jit interpreter native) +target_link_libraries(Kaleidoscope-Ch6 LLVMCore) Modified: llvm/trunk/examples/Kaleidoscope/Chapter7/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/Kaleidoscope/Chapter7/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/examples/Kaleidoscope/Chapter7/CMakeLists.txt (original) +++ llvm/trunk/examples/Kaleidoscope/Chapter7/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -1,5 +1,6 @@ -set(LLVM_LINK_COMPONENTS core jit interpreter native) - add_llvm_example(Kaleidoscope-Ch7 toy.cpp ) + +add_llvm_link_components(Kaleidoscope-Ch7 jit interpreter native) +target_link_libraries(Kaleidoscope-Ch7 LLVMCore) Modified: llvm/trunk/examples/ModuleMaker/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/ModuleMaker/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/examples/ModuleMaker/CMakeLists.txt (original) +++ llvm/trunk/examples/ModuleMaker/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -1,5 +1,5 @@ -set(LLVM_LINK_COMPONENTS bitwriter) - add_llvm_example(ModuleMaker ModuleMaker.cpp ) + +target_link_libraries(ModuleMaker LLVMBitWriter LLVMCore) Modified: llvm/trunk/examples/ParallelJIT/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/examples/ParallelJIT/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/examples/ParallelJIT/CMakeLists.txt (original) +++ llvm/trunk/examples/ParallelJIT/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -1,9 +1,9 @@ -set(LLVM_LINK_COMPONENTS jit interpreter nativecodegen) - add_llvm_example(ParallelJIT ParallelJIT.cpp ) +add_llvm_link_components(ParallelJIT jit interpreter nativecodegen) + if(HAVE_LIBPTHREAD) target_link_libraries(ParallelJIT pthread) endif(HAVE_LIBPTHREAD) Modified: llvm/trunk/lib/Analysis/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/CMakeLists.txt (original) +++ llvm/trunk/lib/Analysis/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -50,4 +50,4 @@ ValueTracking.cpp ) -target_link_libraries (LLVMAnalysis LLVMSupport) +target_link_libraries(LLVMAnalysis LLVMCore LLVMTarget) Modified: llvm/trunk/lib/Analysis/IPA/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/IPA/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/IPA/CMakeLists.txt (original) +++ llvm/trunk/lib/Analysis/IPA/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -4,3 +4,5 @@ FindUsedTypes.cpp GlobalsModRef.cpp ) + +target_link_libraries(LLVMipa LLVMAnalysis LLVMCore) Modified: llvm/trunk/lib/Archive/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Archive/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/lib/Archive/CMakeLists.txt (original) +++ llvm/trunk/lib/Archive/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -3,3 +3,5 @@ ArchiveReader.cpp ArchiveWriter.cpp ) + +target_link_libraries(LLVMArchive LLVMBitReader LLVMCore) Modified: llvm/trunk/lib/AsmParser/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/CMakeLists.txt (original) +++ llvm/trunk/lib/AsmParser/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -4,3 +4,5 @@ LLParser.cpp Parser.cpp ) + +target_link_libraries(LLVMAsmParser LLVMCore) Modified: llvm/trunk/lib/Bitcode/Reader/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Reader/CMakeLists.txt (original) +++ llvm/trunk/lib/Bitcode/Reader/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -2,3 +2,5 @@ BitReader.cpp BitcodeReader.cpp ) + +target_link_libraries(LLVMBitReader LLVMCore) Modified: llvm/trunk/lib/CodeGen/AsmPrinter/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/CMakeLists.txt (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -8,4 +8,11 @@ OcamlGCPrinter.cpp ) -target_link_libraries (LLVMAsmPrinter LLVMMCParser) +target_link_libraries (LLVMAsmPrinter + LLVMAnalysis + LLVMCodeGen + LLVMCore + LLVMMC + LLVMMCParser + LLVMTarget + ) Modified: llvm/trunk/lib/CodeGen/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CMakeLists.txt (original) +++ llvm/trunk/lib/CodeGen/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -83,4 +83,11 @@ VirtRegRewriter.cpp ) -target_link_libraries (LLVMCodeGen LLVMCore LLVMScalarOpts) +target_link_libraries (LLVMCodeGen + LLVMAnalysis + LLVMCore + LLVMMC + LLVMScalarOpts + LLVMTarget + LLVMTransformUtils + ) Modified: llvm/trunk/lib/CodeGen/SelectionDAG/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/CMakeLists.txt (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -22,4 +22,10 @@ TargetSelectionDAGInfo.cpp ) -target_link_libraries (LLVMSelectionDAG LLVMAnalysis LLVMAsmPrinter LLVMCodeGen) +target_link_libraries(LLVMSelectionDAG + LLVMAnalysis + LLVMCodeGen + LLVMCore + LLVMMC + LLVMTarget + ) Modified: llvm/trunk/lib/CompilerDriver/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CompilerDriver/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/lib/CompilerDriver/CMakeLists.txt (original) +++ llvm/trunk/lib/CompilerDriver/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -1,4 +1,3 @@ -set(LLVM_LINK_COMPONENTS support system) set(LLVM_REQUIRES_EH 1) add_llvm_tool(llvmc Modified: llvm/trunk/lib/ExecutionEngine/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/CMakeLists.txt (original) +++ llvm/trunk/lib/ExecutionEngine/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -2,3 +2,5 @@ ExecutionEngine.cpp ExecutionEngineBindings.cpp ) + +target_link_libraries(LLVMExecutionEngine LLVMCore LLVMTarget) Modified: llvm/trunk/lib/ExecutionEngine/Interpreter/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/Interpreter/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/Interpreter/CMakeLists.txt (original) +++ llvm/trunk/lib/ExecutionEngine/Interpreter/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -3,3 +3,10 @@ ExternalFunctions.cpp Interpreter.cpp ) + +target_link_libraries(LLVMInterpreter + LLVMCodeGen + LLVMCore + LLVMExecutionEngine + LLVMTarget + ) Modified: llvm/trunk/lib/ExecutionEngine/JIT/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/JIT/CMakeLists.txt (original) +++ llvm/trunk/lib/ExecutionEngine/JIT/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -11,3 +11,11 @@ OProfileJITEventListener.cpp TargetSelect.cpp ) + +target_link_libraries(LLVMJIT + LLVMCodeGen + LLVMCore + LLVMExecutionEngine + LLVMMC + LLVMTarget + ) Modified: llvm/trunk/lib/Linker/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Linker/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/lib/Linker/CMakeLists.txt (original) +++ llvm/trunk/lib/Linker/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -4,3 +4,10 @@ LinkModules.cpp Linker.cpp ) + +target_link_libraries(LLVMLinker + LLVMArchive + LLVMBitReader + LLVMCore + LLVMTransformUtils + ) Modified: llvm/trunk/lib/MC/MCDisassembler/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDisassembler/CMakeLists.txt (original) +++ llvm/trunk/lib/MC/MCDisassembler/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -1,7 +1,8 @@ - add_llvm_library(LLVMMCDisassembler EDDisassembler.cpp EDOperand.cpp EDInst.cpp EDToken.cpp ) + +add_llvm_link_components(LLVMMCDisassembler all) Modified: llvm/trunk/lib/Target/ARM/AsmParser/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -5,3 +5,9 @@ ARMAsmParser.cpp ) +target_link_libraries(LLVMARMAsmParser + LLVMARMInfo + LLVMMC + LLVMMCParser + LLVMTarget + ) Modified: llvm/trunk/lib/Target/ARM/AsmPrinter/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmPrinter/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmPrinter/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/ARM/AsmPrinter/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -3,4 +3,6 @@ add_llvm_library(LLVMARMAsmPrinter ARMInstPrinter.cpp ) + add_dependencies(LLVMARMAsmPrinter ARMCodeGenTable_gen) +target_link_libraries(LLVMARMAsmPrinter LLVMMC) Modified: llvm/trunk/lib/Target/ARM/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/ARM/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -47,4 +47,13 @@ Thumb2SizeReduction.cpp ) -target_link_libraries (LLVMARMCodeGen LLVMARMAsmPrinter LLVMSelectionDAG) +target_link_libraries (LLVMARMCodeGen + LLVMARMInfo + LLVMAnalysis + LLVMAsmPrinter + LLVMCodeGen + LLVMCore + LLVMMC + LLVMSelectionDAG + LLVMTarget + ) Modified: llvm/trunk/lib/Target/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/lib/Target/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -13,3 +13,5 @@ TargetRegisterInfo.cpp TargetSubtarget.cpp ) + +target_link_libraries(LLVMTarget LLVMCore LLVMMC) Modified: llvm/trunk/lib/Target/X86/AsmParser/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/X86/AsmParser/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -4,4 +4,11 @@ X86AsmLexer.cpp X86AsmParser.cpp ) + add_dependencies(LLVMX86AsmParser X86CodeGenTable_gen) +target_link_libraries(LLVMX86AsmParser + LLVMMC + LLVMMCParser + LLVMTarget + LLVMX86Info + ) Modified: llvm/trunk/lib/Target/X86/AsmPrinter/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmPrinter/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmPrinter/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/X86/AsmPrinter/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -5,4 +5,6 @@ X86IntelInstPrinter.cpp X86InstComments.cpp ) + add_dependencies(LLVMX86AsmPrinter X86CodeGenTable_gen) +target_link_libraries(LLVMX86AsmPrinter LLVMMC) Modified: llvm/trunk/lib/Target/X86/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/X86/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -29,7 +29,7 @@ X86InstrInfo.cpp X86JITInfo.cpp X86MCAsmInfo.cpp - X86MCCodeEmitter.cpp + X86MCCodeEmitter.cpp X86MCInstLower.cpp X86RegisterInfo.cpp X86SelectionDAGInfo.cpp @@ -49,4 +49,14 @@ endif() add_llvm_target(X86CodeGen ${sources}) - +target_link_libraries(LLVMX86CodeGen + LLVMAnalysis + LLVMAsmPrinter + LLVMCodeGen + LLVMCore + LLVMMC + LLVMSelectionDAG + LLVMTarget + LLVMX86AsmPrinter + LLVMX86Info + ) Modified: llvm/trunk/lib/Target/X86/Disassembler/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/Disassembler/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/X86/Disassembler/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -11,4 +11,6 @@ PROPERTY COMPILE_FLAGS "/Od" ) endif() + add_dependencies(LLVMX86Disassembler X86CodeGenTable_gen) +target_link_libraries(LLVMX86Disassembler LLVMMC LLVMX86Info) Modified: llvm/trunk/lib/Transforms/IPO/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/IPO/CMakeLists.txt (original) +++ llvm/trunk/lib/Transforms/IPO/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -24,4 +24,11 @@ StructRetPromotion.cpp ) -target_link_libraries (LLVMipo LLVMScalarOpts LLVMInstCombine) +target_link_libraries(LLVMipo + LLVMAnalysis + LLVMCore + LLVMScalarOpts + LLVMTarget + LLVMTransformUtils + LLVMipa + ) Modified: llvm/trunk/lib/Transforms/InstCombine/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/CMakeLists.txt (original) +++ llvm/trunk/lib/Transforms/InstCombine/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -9,9 +9,14 @@ InstCombineMulDivRem.cpp InstCombinePHI.cpp InstCombineSelect.cpp - InstCombineShifts.cpp + InstCombineShifts.cpp InstCombineSimplifyDemanded.cpp InstCombineVectorOps.cpp ) -target_link_libraries (LLVMInstCombine LLVMTransformUtils) +target_link_libraries(LLVMInstCombine + LLVMAnalysis + LLVMCore + LLVMTarget + LLVMTransformUtils + ) Modified: llvm/trunk/lib/Transforms/Instrumentation/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Instrumentation/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Instrumentation/CMakeLists.txt (original) +++ llvm/trunk/lib/Transforms/Instrumentation/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -3,3 +3,9 @@ OptimalEdgeProfiling.cpp ProfilingUtils.cpp ) + +target_link_libraries(LLVMInstrumentation + LLVMAnalysis + LLVMCore + LLVMTransformUtils + ) Modified: llvm/trunk/lib/Transforms/Scalar/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/CMakeLists.txt (original) +++ llvm/trunk/lib/Transforms/Scalar/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -32,4 +32,10 @@ TailRecursionElimination.cpp ) -target_link_libraries (LLVMScalarOpts LLVMTransformUtils) +target_link_libraries (LLVMScalarOpts + LLVMAnalysis + LLVMCore + LLVMInstCombine + LLVMTarget + LLVMTransformUtils + ) Modified: llvm/trunk/lib/Transforms/Utils/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/CMakeLists.txt (original) +++ llvm/trunk/lib/Transforms/Utils/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -25,4 +25,9 @@ ValueMapper.cpp ) -target_link_libraries (LLVMTransformUtils LLVMSupport) +target_link_libraries(LLVMTransformUtils + LLVMAnalysis + LLVMCore + LLVMTarget + LLVMipa + ) Modified: llvm/trunk/tools/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/tools/CMakeLists.txt (original) +++ llvm/trunk/tools/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -2,15 +2,6 @@ # large and three small executables. This is done to minimize memory load # in parallel builds. Please retain this ordering. -if( NOT WIN32 OR MSYS OR CYGWIN ) - # It is useful to build llvm-config before the other tools, so we - # have a fresh LibDeps.txt for regenerating the hard-coded library - # dependencies. llvm-config/CMakeLists.txt takes care of this but we - # must keep llvm-config as the first entry on the list of tools to - # be built. - add_subdirectory(llvm-config) -endif() - add_subdirectory(opt) add_subdirectory(llvm-as) add_subdirectory(llvm-dis) @@ -38,6 +29,4 @@ if( EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/clang/CMakeLists.txt ) add_subdirectory( ${CMAKE_CURRENT_SOURCE_DIR}/clang ) -endif( EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/clang/CMakeLists.txt ) - -set(LLVM_COMMON_DEPENDS ${LLVM_COMMON_DEPENDS} PARENT_SCOPE) +endif() Modified: llvm/trunk/tools/bugpoint/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/bugpoint/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/tools/bugpoint/CMakeLists.txt (original) +++ llvm/trunk/tools/bugpoint/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -1,6 +1,3 @@ -set(LLVM_LINK_COMPONENTS asmparser instrumentation scalaropts ipo - linker bitreader bitwriter) - add_llvm_tool(bugpoint BugDriver.cpp CrashDebugger.cpp @@ -12,3 +9,13 @@ ToolRunner.cpp bugpoint.cpp ) + +target_link_libraries(bugpoint + LLVMAsmParser + LLVMInstrumentation + LLVMScalarOpts + LLVMipo + LLVMLinker + LLVMBitReader + LLVMBitWriter + ) Modified: llvm/trunk/tools/llc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llc/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/tools/llc/CMakeLists.txt (original) +++ llvm/trunk/tools/llc/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -1,5 +1,6 @@ -set(LLVM_LINK_COMPONENTS ${LLVM_TARGETS_TO_BUILD} bitreader asmparser) - add_llvm_tool(llc llc.cpp ) + +add_llvm_link_components(llc all) +target_link_libraries(llc LLVMBitReader LLVMAsmParser) Modified: llvm/trunk/tools/lli/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lli/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/tools/lli/CMakeLists.txt (original) +++ llvm/trunk/tools/lli/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -1,5 +1,6 @@ -set(LLVM_LINK_COMPONENTS jit interpreter nativecodegen bitreader selectiondag) - add_llvm_tool(lli lli.cpp ) + +add_llvm_link_components(lli jit interpreter nativecodegen) +target_link_libraries(lli LLVMBitReader LLVMSelectionDAG) Modified: llvm/trunk/tools/llvm-ar/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-ar/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/tools/llvm-ar/CMakeLists.txt (original) +++ llvm/trunk/tools/llvm-ar/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -1,8 +1,9 @@ -set(LLVM_LINK_COMPONENTS archive) set(LLVM_REQUIRES_EH 1) add_llvm_tool(llvm-ar llvm-ar.cpp ) +target_link_libraries(llvm-ar LLVMArchive) + # TODO: Support check-local. Modified: llvm/trunk/tools/llvm-as/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-as/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/tools/llvm-as/CMakeLists.txt (original) +++ llvm/trunk/tools/llvm-as/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -1,6 +1,7 @@ -set(LLVM_LINK_COMPONENTS asmparser bitwriter) set(LLVM_REQUIRES_EH 1) add_llvm_tool(llvm-as llvm-as.cpp ) + +target_link_libraries(llvm-as LLVMAsmParser LLVMBitWriter) Modified: llvm/trunk/tools/llvm-bcanalyzer/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-bcanalyzer/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/tools/llvm-bcanalyzer/CMakeLists.txt (original) +++ llvm/trunk/tools/llvm-bcanalyzer/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -1,6 +1,7 @@ -set(LLVM_LINK_COMPONENTS bitreader) set(LLVM_REQUIRES_EH 1) add_llvm_tool(llvm-bcanalyzer llvm-bcanalyzer.cpp ) + +target_link_libraries(llvm-bcanalyzer LLVMBitReader) Modified: llvm/trunk/tools/llvm-config/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-config/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/tools/llvm-config/CMakeLists.txt (original) +++ llvm/trunk/tools/llvm-config/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -110,10 +110,6 @@ add_dependencies(llvm-config.target ${llvm_lib_targets}) -# Make sure that llvm-config builds before the llvm tools, so we have -# LibDeps.txt and can use it for updating the hard-coded library -# dependencies on cmake/modules/LLVMLibDeps.cmake when the tools' -# build fail due to outdated dependencies: set(LLVM_COMMON_DEPENDS ${LLVM_COMMON_DEPENDS} llvm-config.target) install(FILES ${LLVM_CONFIG} @@ -122,25 +118,4 @@ DESTINATION bin) -# Regeneration of library dependencies. - -# See the comments at the end of cmake/modules/LLVMConfig.cmake for -# notes and guidelines. - -set(LLVMLibDeps ${LLVM_MAIN_SRC_DIR}/cmake/modules/LLVMLibDeps.cmake) -set(LLVMLibDeps_TMP ${CMAKE_CURRENT_BINARY_DIR}/LLVMLibDeps.cmake.tmp) - -add_custom_command(OUTPUT ${LLVMLibDeps_TMP} - COMMAND sed -e s'@\\.a@@g' -e s'@\\.so@@g' -e 's at libLLVM@LLVM at g' -e 's@: @ @' -e 's@\\\(.*\\\)@set\(MSVC_LIB_DEPS_\\1\)@' ${FINAL_LIBDEPS} > ${LLVMLibDeps_TMP} - COMMAND ${CMAKE_COMMAND} -E copy_if_different ${LLVMLibDeps_TMP} ${LLVMLibDeps} - DEPENDS ${FINAL_LIBDEPS} - COMMENT "Updating cmake library dependencies file ${LLVMLibDeps}" - ) - -if( LLVM_TARGETS_TO_BUILD STREQUAL LLVM_ALL_TARGETS ) - add_custom_target(llvmlibdeps.target ALL DEPENDS ${LLVMLibDeps_TMP}) - add_dependencies(llvmlibdeps.target llvm-config.target) - set(LLVM_COMMON_DEPENDS ${LLVM_COMMON_DEPENDS} llvmlibdeps.target) -endif() - set(LLVM_COMMON_DEPENDS ${LLVM_COMMON_DEPENDS} PARENT_SCOPE) Modified: llvm/trunk/tools/llvm-diff/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-diff/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/tools/llvm-diff/CMakeLists.txt (original) +++ llvm/trunk/tools/llvm-diff/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -1,6 +1,6 @@ -set(LLVM_LINK_COMPONENTS support asmparser bitreader) - add_llvm_tool(llvm-diff llvm-diff.cpp DifferenceEngine.cpp ) + +target_link_libraries(llvm-diff LLVMAsmParser LLVMBitReader) Modified: llvm/trunk/tools/llvm-dis/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-dis/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/tools/llvm-dis/CMakeLists.txt (original) +++ llvm/trunk/tools/llvm-dis/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -1,6 +1,7 @@ -set(LLVM_LINK_COMPONENTS bitreader) set(LLVM_REQUIRES_EH 1) add_llvm_tool(llvm-dis llvm-dis.cpp ) + +target_link_libraries(llvm-dis LLVMCore LLVMBitReader) Modified: llvm/trunk/tools/llvm-extract/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-extract/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/tools/llvm-extract/CMakeLists.txt (original) +++ llvm/trunk/tools/llvm-extract/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -1,5 +1,10 @@ -set(LLVM_LINK_COMPONENTS asmparser ipo bitreader bitwriter) - add_llvm_tool(llvm-extract llvm-extract.cpp ) + +target_link_libraries(llvm-extract + LLVMAsmParser + LLVMipo + LLVMBitReader + LLVMBitWriter + ) Modified: llvm/trunk/tools/llvm-ld/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-ld/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/tools/llvm-ld/CMakeLists.txt (original) +++ llvm/trunk/tools/llvm-ld/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -1,6 +1,12 @@ -set(LLVM_LINK_COMPONENTS ipo scalaropts linker archive bitwriter) - add_llvm_tool(llvm-ld Optimize.cpp llvm-ld.cpp ) + +target_link_libraries(llvm-ld + LLVMipo + LLVMScalarOpts + LLVMLinker + LLVMArchive + LLVMBitWriter + ) Modified: llvm/trunk/tools/llvm-link/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-link/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/tools/llvm-link/CMakeLists.txt (original) +++ llvm/trunk/tools/llvm-link/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -1,5 +1,10 @@ -set(LLVM_LINK_COMPONENTS linker bitreader bitwriter asmparser) - add_llvm_tool(llvm-link llvm-link.cpp ) + +target_link_libraries(llvm-link + LLVMLinker + LLVMBitReader + LLVMBitWriter + LLVMAsmParser + ) Modified: llvm/trunk/tools/llvm-mc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/CMakeLists.txt (original) +++ llvm/trunk/tools/llvm-mc/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -1,6 +1,7 @@ -set(LLVM_LINK_COMPONENTS ${LLVM_TARGETS_TO_BUILD} support MC MCParser MCDisassembler) - add_llvm_tool(llvm-mc llvm-mc.cpp Disassembler.cpp ) + +add_llvm_link_components(llvm-mc all) +target_link_libraries(llvm-mc LLVMMC LLVMMCParser LLVMMCDisassembler) Modified: llvm/trunk/tools/llvm-nm/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-nm/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/tools/llvm-nm/CMakeLists.txt (original) +++ llvm/trunk/tools/llvm-nm/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -1,5 +1,5 @@ -set(LLVM_LINK_COMPONENTS archive bitreader) - add_llvm_tool(llvm-nm llvm-nm.cpp ) + +target_link_libraries(llvm-nm LLVMArchive LLVMBitReader) Modified: llvm/trunk/tools/llvm-prof/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-prof/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/tools/llvm-prof/CMakeLists.txt (original) +++ llvm/trunk/tools/llvm-prof/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -1,5 +1,5 @@ -set(LLVM_LINK_COMPONENTS bitreader analysis) - add_llvm_tool(llvm-prof llvm-prof.cpp ) + +target_link_libraries(llvm-prof LLVMBitReader LLVMAnalysis) Modified: llvm/trunk/tools/llvm-ranlib/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-ranlib/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/tools/llvm-ranlib/CMakeLists.txt (original) +++ llvm/trunk/tools/llvm-ranlib/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -1,6 +1,7 @@ -set(LLVM_LINK_COMPONENTS archive) set(LLVM_REQUIRES_EH 1) add_llvm_tool(llvm-ranlib llvm-ranlib.cpp ) + +target_link_libraries(llvm-ranlib LLVMArchive) Modified: llvm/trunk/tools/opt/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/opt/CMakeLists.txt?rev=113632&r1=113631&r2=113632&view=diff ============================================================================== --- llvm/trunk/tools/opt/CMakeLists.txt (original) +++ llvm/trunk/tools/opt/CMakeLists.txt Fri Sep 10 16:14:25 2010 @@ -1,8 +1,15 @@ -set(LLVM_LINK_COMPONENTS bitreader asmparser bitwriter instrumentation scalaropts ipo) - add_llvm_tool(opt AnalysisWrappers.cpp GraphPrinters.cpp PrintSCC.cpp opt.cpp ) + +target_link_libraries(opt + LLVMBitReader + LLVMAsmParser + LLVMBitWriter + LLVMInstrumentation + LLVMScalarOpts + LLVMipo + ) From isanbard at gmail.com Fri Sep 10 16:29:00 2010 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 10 Sep 2010 14:29:00 -0700 Subject: [llvm-commits] [llvm] r112664 - in /llvm/trunk: lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td test/CodeGen/ARM/mvncc.ll test/CodeGen/Thumb2/thumb2-mvncc.ll In-Reply-To: <4B718D16-ADCF-4C23-B908-6C32A1E6D3A2@apple.com> References: <20100831224122.6BA6E2A6C12E@llvm.org> <8C81CB0A-63B8-4893-A3EE-F319C0012D52@apple.com> <23950B4D-6DDC-4B88-94F9-55ACCE0C4218@gmail.com> <4B718D16-ADCF-4C23-B908-6C32A1E6D3A2@apple.com> Message-ID: On Sep 8, 2010, at 11:01 AM, Evan Cheng wrote: > On Sep 8, 2010, at 3:20 AM, Bill Wendling wrote: > >> On Sep 7, 2010, at 11:02 PM, Evan Cheng wrote: >> >>> Hi Bill, >>> >>> Thanks for doing this but I have some questions. >>> >>> On Aug 31, 2010, at 3:41 PM, Bill Wendling wrote: >>> >>>> Author: void >>>> Date: Tue Aug 31 17:41:22 2010 >>>> New Revision: 112664 >>>> >>>> URL: http://llvm.org/viewvc/llvm-project?rev=112664&view=rev >>>> Log: >>>> We have a chance for an optimization. Consider this code: >>>> >>>> int x(int t) { >>>> if (t & 256) >>>> return -26; >>>> return 0; >>>> } >>>> >>>> We generate this: >>>> >>>> tst.w r0, #256 >>>> mvn r0, #25 >>>> it eq >>>> moveq r0, #0 >>>> >>>> while gcc generates this: >>>> >>>> ands r0, r0, #256 >>>> it ne >>>> mvnne r0, #25 >>>> bx lr >>> >>> Is it possible to generate the "and" and comparison at isel time and let the peephole pass get rid of the compare later? I'd prefer to avoid having these instructions like ARM::ANDS. >>> >> It's possible. I preferred the isel time change, because it wasn't a hybrid approach. I will try it out though. :-) > > Thanks. IMO, one of the big advantage of the machine instruction peephole pass is it avoid having these instruction variants. > Now that I'm thinking about this, I could revisit an idea that I had at the beginning but rejected because it was a bit heavy-handed. Basically, perform this whole transformation in the peephole optimizer. (No need to convert it to AND, etc.) I rejected it because it was transforming much more than just one or two instructions. But now that I think of it, I might be able to do something good there. -bw From grosbach at apple.com Fri Sep 10 16:38:23 2010 From: grosbach at apple.com (Jim Grosbach) Date: Fri, 10 Sep 2010 21:38:23 -0000 Subject: [llvm-commits] [llvm] r113637 - /llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Message-ID: <20100910213823.13EB22A6C12C@llvm.org> Author: grosbach Date: Fri Sep 10 16:38:22 2010 New Revision: 113637 URL: http://llvm.org/viewvc/llvm-project?rev=113637&view=rev Log: Add a missing case to duplicateCPV() for LSDA constants. Add a FIXME. rdar://8302157 Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=113637&r1=113636&r2=113637&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Fri Sep 10 16:38:22 2010 @@ -922,6 +922,11 @@ unsigned PCLabelId = AFI->createConstPoolEntryUId(); ARMConstantPoolValue *NewCPV = 0; + // FIXME: The below assumes PIC relocation model and that the function + // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and + // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR + // instructions, so that's probably OK, but is PIC always correct when + // we get here? if (ACPV->isGlobalValue()) NewCPV = new ARMConstantPoolValue(ACPV->getGV(), PCLabelId, ARMCP::CPValue, 4); @@ -931,6 +936,9 @@ else if (ACPV->isBlockAddress()) NewCPV = new ARMConstantPoolValue(ACPV->getBlockAddress(), PCLabelId, ARMCP::CPBlockAddress, 4); + else if (ACPV->isLSDA()) + NewCPV = new ARMConstantPoolValue(MF.getFunction(), PCLabelId, + ARMCP::CPLSDA, 4); else llvm_unreachable("Unexpected ARM constantpool value type!!"); CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment()); From isanbard at gmail.com Fri Sep 10 16:55:43 2010 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 10 Sep 2010 21:55:43 -0000 Subject: [llvm-commits] [llvm] r113640 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/PeepholeOptimizer.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h Message-ID: <20100910215543.8C7282A6C12C@llvm.org> Author: void Date: Fri Sep 10 16:55:43 2010 New Revision: 113640 URL: http://llvm.org/viewvc/llvm-project?rev=113640&view=rev Log: Modify the comparison optimizations in the peephole optimizer to update the iterator when an optimization took place. This allows us to do more insane things with the code than just remove an instruction or two. Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=113640&r1=113639&r2=113640&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Fri Sep 10 16:55:43 2010 @@ -586,9 +586,11 @@ } /// ConvertToSetZeroFlag - Convert the instruction to set the zero flag so - /// that we can remove a "comparison with zero". - virtual bool ConvertToSetZeroFlag(MachineInstr *Instr, - MachineInstr *CmpInstr) const { + /// that we can remove a "comparison with zero". Update the iterator *only* + /// if a transformation took place. + virtual bool ConvertToSetZeroFlag(MachineInstr * /*Instr*/, + MachineInstr * /*CmpInstr*/, + MachineBasicBlock::iterator &) const { return false; } Modified: llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp?rev=113640&r1=113639&r2=113640&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp (original) +++ llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp Fri Sep 10 16:55:43 2010 @@ -76,7 +76,8 @@ } private: - bool OptimizeCmpInstr(MachineInstr *MI, MachineBasicBlock *MBB); + bool OptimizeCmpInstr(MachineInstr *MI, MachineBasicBlock *MBB, + MachineBasicBlock::iterator &MII); bool OptimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB, SmallPtrSet &LocalMIs); }; @@ -232,7 +233,8 @@ /// set) the same flag as the compare, then we can remove the comparison and use /// the flag from the previous instruction. bool PeepholeOptimizer::OptimizeCmpInstr(MachineInstr *MI, - MachineBasicBlock *MBB) { + MachineBasicBlock *MBB, + MachineBasicBlock::iterator &NextIter){ // If this instruction is a comparison against zero and isn't comparing a // physical register, we can try to optimize it. unsigned SrcReg; @@ -247,7 +249,7 @@ return false; // Attempt to convert the defining instruction to set the "zero" flag. - if (TII->ConvertToSetZeroFlag(&*DI, MI)) { + if (TII->ConvertToSetZeroFlag(&*DI, MI, NextIter)) { ++NumEliminated; return true; } @@ -269,12 +271,14 @@ LocalMIs.clear(); for (MachineBasicBlock::iterator - MII = I->begin(), ME = I->end(); MII != ME; ) { + MII = I->begin(), MIE = I->end(); MII != MIE; ) { MachineInstr *MI = &*MII; if (MI->getDesc().isCompare()) { - ++MII; // The iterator may become invalid if the compare is deleted. - Changed |= OptimizeCmpInstr(MI, MBB); + if (OptimizeCmpInstr(MI, MBB, MII)) + Changed = true; + else + ++MII; } else { Changed |= OptimizeExtInstr(MI, MBB, LocalMIs); ++MII; Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=113640&r1=113639&r2=113640&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Fri Sep 10 16:55:43 2010 @@ -1378,9 +1378,11 @@ } /// ConvertToSetZeroFlag - Convert the instruction to set the "zero" flag so -/// that we can remove a "comparison with zero". +/// that we can remove a "comparison with zero". Update the iterator *only* if a +/// transformation took place. bool ARMBaseInstrInfo:: -ConvertToSetZeroFlag(MachineInstr *MI, MachineInstr *CmpInstr) const { +ConvertToSetZeroFlag(MachineInstr *MI, MachineInstr *CmpInstr, + MachineBasicBlock::iterator &MII) const { // Conservatively refuse to convert an instruction which isn't in the same BB // as the comparison. if (MI->getParent() != CmpInstr->getParent()) @@ -1414,6 +1416,7 @@ MI->RemoveOperand(5); MachineInstrBuilder(MI) .addReg(ARM::CPSR, RegState::Define | RegState::Implicit); + MII = llvm::next(MachineBasicBlock::iterator(CmpInstr)); CmpInstr->eraseFromParent(); return true; } Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h?rev=113640&r1=113639&r2=113640&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Fri Sep 10 16:55:43 2010 @@ -347,7 +347,8 @@ /// ConvertToSetZeroFlag - Convert the instruction to set the zero flag so /// that we can remove a "comparison with zero". virtual bool ConvertToSetZeroFlag(MachineInstr *Instr, - MachineInstr *CmpInstr) const; + MachineInstr *CmpInstr, + MachineBasicBlock::iterator &MII) const; virtual unsigned getNumMicroOps(const MachineInstr *MI, const InstrItineraryData *ItinData) const; From dalej at apple.com Fri Sep 10 16:58:02 2010 From: dalej at apple.com (Dale Johannesen) Date: Fri, 10 Sep 2010 21:58:02 -0000 Subject: [llvm-commits] [llvm] r113643 - /llvm/trunk/include/llvm-c/Core.h Message-ID: <20100910215802.7DF3D2A6C12C@llvm.org> Author: johannes Date: Fri Sep 10 16:58:02 2010 New Revision: 113643 URL: http://llvm.org/viewvc/llvm-project?rev=113643&view=rev Log: Add missing X86 MMX declarations. Hopefully fixes buildbot? Modified: llvm/trunk/include/llvm-c/Core.h Modified: llvm/trunk/include/llvm-c/Core.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm-c/Core.h?rev=113643&r1=113642&r2=113643&view=diff ============================================================================== --- llvm/trunk/include/llvm-c/Core.h (original) +++ llvm/trunk/include/llvm-c/Core.h Fri Sep 10 16:58:02 2010 @@ -409,10 +409,12 @@ LLVMTypeRef LLVMVoidTypeInContext(LLVMContextRef C); LLVMTypeRef LLVMLabelTypeInContext(LLVMContextRef C); LLVMTypeRef LLVMOpaqueTypeInContext(LLVMContextRef C); +LLVMTypeRef LLVMX86MMXTypeInContext(LLVMContextRef C); LLVMTypeRef LLVMVoidType(void); LLVMTypeRef LLVMLabelType(void); LLVMTypeRef LLVMOpaqueType(void); +LLVMTypeRef LLVMX86MMXType(void); /* Operations on type handles */ LLVMTypeHandleRef LLVMCreateTypeHandle(LLVMTypeRef PotentiallyAbstractTy); From daniel at zuster.org Fri Sep 10 17:01:54 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Fri, 10 Sep 2010 22:01:54 -0000 Subject: [llvm-commits] [zorg] r113644 - /zorg/trunk/lnt/lnt/tests/nt.py Message-ID: <20100910220154.D5FBD2A6C12C@llvm.org> Author: ddunbar Date: Fri Sep 10 17:01:54 2010 New Revision: 113644 URL: http://llvm.org/viewvc/llvm-project?rev=113644&view=rev Log: LNT/nt: Allow capturing the run_order from llvm-gcc/clang for tags like '2207.5', by discarding the values after the point. I will rework this system one fine day. Modified: zorg/trunk/lnt/lnt/tests/nt.py Modified: zorg/trunk/lnt/lnt/tests/nt.py URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/lnt/lnt/tests/nt.py?rev=113644&r1=113643&r2=113644&view=diff ============================================================================== --- zorg/trunk/lnt/lnt/tests/nt.py (original) +++ zorg/trunk/lnt/lnt/tests/nt.py Fri Sep 10 17:01:54 2010 @@ -469,8 +469,8 @@ run_info.get('cc_src_tag') != '0' and run_info.get('cc_src_tag') != '00' and run_info.get('cc_src_tag') != '9999' and - run_info.get('cc_src_tag','').isdigit()): - run_info['run_order'] = run_info['cc_src_tag'] + run_info.get('cc_src_tag','').split('.',1)[0].isdigit()): + run_info['run_order'] = run_info['cc_src_tag'].split('.',1)[0] # Otherwise, infer from the llvm revision. elif run_info.get('llvm_revision','').isdigit(): From ggreif at gmail.com Fri Sep 10 17:25:59 2010 From: ggreif at gmail.com (Gabor Greif) Date: Fri, 10 Sep 2010 22:25:59 -0000 Subject: [llvm-commits] [llvm] r113647 - in /llvm/trunk: include/llvm/Analysis/Dominators.h include/llvm/CodeGen/MachineDominators.h lib/Transforms/Scalar/LoopIndexSplit.cpp lib/Transforms/Utils/BasicBlockUtils.cpp lib/Transforms/Utils/CodeExtractor.cpp Message-ID: <20100910222559.1C48A2A6C12C@llvm.org> Author: ggreif Date: Fri Sep 10 17:25:58 2010 New Revision: 113647 URL: http://llvm.org/viewvc/llvm-project?rev=113647&view=rev Log: typoes Modified: llvm/trunk/include/llvm/Analysis/Dominators.h llvm/trunk/include/llvm/CodeGen/MachineDominators.h llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp llvm/trunk/lib/Transforms/Utils/CodeExtractor.cpp Modified: llvm/trunk/include/llvm/Analysis/Dominators.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/Dominators.h?rev=113647&r1=113646&r2=113647&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/Dominators.h (original) +++ llvm/trunk/include/llvm/Analysis/Dominators.h Fri Sep 10 17:25:58 2010 @@ -509,7 +509,7 @@ } /// eraseNode - Removes a node from the dominator tree. Block must not - /// domiante any other blocks. Removes node from its immediate dominator's + /// dominate any other blocks. Removes node from its immediate dominator's /// children list. Deletes dominator node associated with basic block BB. void eraseNode(NodeT *BB) { DomTreeNodeBase *Node = getNode(BB); @@ -807,7 +807,7 @@ } /// eraseNode - Removes a node from the dominator tree. Block must not - /// domiante any other blocks. Removes node from its immediate dominator's + /// dominate any other blocks. Removes node from its immediate dominator's /// children list. Deletes dominator node associated with basic block BB. inline void eraseNode(BasicBlock *BB) { DT->eraseNode(BB); Modified: llvm/trunk/include/llvm/CodeGen/MachineDominators.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineDominators.h?rev=113647&r1=113646&r2=113647&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineDominators.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineDominators.h Fri Sep 10 17:25:58 2010 @@ -145,7 +145,7 @@ } /// eraseNode - Removes a node from the dominator tree. Block must not - /// domiante any other blocks. Removes node from its immediate dominator's + /// dominate any other blocks. Removes node from its immediate dominator's /// children list. Deletes dominator node associated with basic block BB. inline void eraseNode(MachineBasicBlock *BB) { DT->eraseNode(BB); Modified: llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp?rev=113647&r1=113646&r2=113647&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopIndexSplit.cpp Fri Sep 10 17:25:58 2010 @@ -617,8 +617,8 @@ if (Op1->use_empty()) Op1->eraseFromParent(); - // Update domiantor info. Now, ExitingBlock has only one predecessor, - // ExitingBBPred, and it is ExitingBlock's immediate domiantor. + // Update dominator info. Now, ExitingBlock has only one predecessor, + // ExitingBBPred, and it is ExitingBlock's immediate dominator. DT->changeImmediateDominator(ExitingBlock, ExitingBBPred); BasicBlock *ExitBlock = ExitingBlock->getTerminator()->getSuccessor(1); @@ -1040,7 +1040,7 @@ // [*] Update BLoop's header phi nodes. Remove incoming PHINode's from // original loop's preheader. Add incoming PHINode values from - // ALoop's exiting block. Update BLoop header's domiantor info. + // ALoop's exiting block. Update BLoop header's dominator info. // Collect inverse map of Header PHINodes. DenseMap InverseMap; Modified: llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp?rev=113647&r1=113646&r2=113647&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp Fri Sep 10 17:25:58 2010 @@ -327,7 +327,7 @@ L->addBasicBlockToLoop(New, LI->getBase()); if (DominatorTree *DT = P->getAnalysisIfAvailable()) { - // Old dominates New. New node domiantes all other nodes dominated by Old. + // Old dominates New. New node dominates all other nodes dominated by Old. DomTreeNode *OldNode = DT->getNode(Old); std::vector Children; for (DomTreeNode::iterator I = OldNode->begin(), E = OldNode->end(); Modified: llvm/trunk/lib/Transforms/Utils/CodeExtractor.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/CodeExtractor.cpp?rev=113647&r1=113646&r2=113647&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/CodeExtractor.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/CodeExtractor.cpp Fri Sep 10 17:25:58 2010 @@ -186,8 +186,8 @@ if (ReturnInst *RI = dyn_cast((*I)->getTerminator())) { BasicBlock *New = (*I)->splitBasicBlock(RI, (*I)->getName()+".ret"); if (DT) { - // Old dominates New. New node domiantes all other nodes dominated - //by Old. + // Old dominates New. New node dominates all other nodes dominated + // by Old. DomTreeNode *OldNode = DT->getNode(*I); SmallVector Children; for (DomTreeNode::iterator DI = OldNode->begin(), DE = OldNode->end(); From aggarwa4 at illinois.edu Fri Sep 10 17:28:42 2010 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Fri, 10 Sep 2010 22:28:42 -0000 Subject: [llvm-commits] [poolalloc] r113649 - /poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp Message-ID: <20100910222842.432092A6C12C@llvm.org> Author: aggarwa4 Date: Fri Sep 10 17:28:42 2010 New Revision: 113649 URL: http://llvm.org/viewvc/llvm-project?rev=113649&view=rev Log: The pool allocation algorithm was missing functions that were not part of any global EC. The function now goes over these functions, and checks if they need pools passed to them. Modified: poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp Modified: poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp?rev=113649&r1=113648&r2=113649&view=diff ============================================================================== --- poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp (original) +++ poolalloc/trunk/lib/PoolAllocate/PoolAllocate.cpp Fri Sep 10 17:28:42 2010 @@ -743,7 +743,9 @@ for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I) { if (!I->isDeclaration() && Graphs->hasDSGraph(*I)) { if (FunctionInfo.find (I) == FunctionInfo.end()) { - FunctionInfo.insert(std::make_pair(I, FuncInfo(*I))); + std::vector Functions; + Functions.push_back(I); + FindFunctionPoolArgs (Functions); } } } From benny.kra at googlemail.com Fri Sep 10 17:39:55 2010 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Fri, 10 Sep 2010 22:39:55 -0000 Subject: [llvm-commits] [llvm] r113651 - in /llvm/trunk: lib/Analysis/InstructionSimplify.cpp test/Transforms/InstCombine/and2.ll test/Transforms/InstCombine/or.ll Message-ID: <20100910223955.62B842A6C12C@llvm.org> Author: d0k Date: Fri Sep 10 17:39:55 2010 New Revision: 113651 URL: http://llvm.org/viewvc/llvm-project?rev=113651&view=rev Log: Teach InstructionSimplify to fold (A & B) & A -> A & B and (A | B) | A -> A | B. Reassociate does this but it doesn't catch all cases (e.g. if the operands are i1). Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp llvm/trunk/test/Transforms/InstCombine/and2.ll llvm/trunk/test/Transforms/InstCombine/or.ll Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InstructionSimplify.cpp?rev=113651&r1=113650&r2=113651&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/InstructionSimplify.cpp (original) +++ llvm/trunk/lib/Analysis/InstructionSimplify.cpp Fri Sep 10 17:39:55 2010 @@ -106,6 +106,16 @@ (A == Op0 || B == Op0)) return Op0; + // (A & B) & A -> A & B + if (match(Op0, m_And(m_Value(A), m_Value(B))) && + (A == Op1 || B == Op1)) + return Op0; + + // A & (A & B) -> A & B + if (match(Op1, m_And(m_Value(A), m_Value(B))) && + (A == Op0 || B == Op0)) + return Op1; + return 0; } @@ -165,6 +175,16 @@ (A == Op0 || B == Op0)) return Op0; + // (A | B) | A -> A | B + if (match(Op0, m_Or(m_Value(A), m_Value(B))) && + (A == Op1 || B == Op1)) + return Op0; + + // A | (A | B) -> A | B + if (match(Op1, m_Or(m_Value(A), m_Value(B))) && + (A == Op0 || B == Op0)) + return Op1; + return 0; } Modified: llvm/trunk/test/Transforms/InstCombine/and2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/and2.ll?rev=113651&r1=113650&r2=113651&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/and2.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/and2.ll Fri Sep 10 17:39:55 2010 @@ -8,3 +8,21 @@ ret i1 %bothcond ; CHECK: fcmp ord double %Y, %X } + +define i1 @test2(i1 %X, i1 %Y) { + %a = and i1 %X, %Y + %b = and i1 %a, %X + ret i1 %b +; CHECK: @test2 +; CHECK-NEXT: and i1 %X, %Y +; CHECK-NEXT: ret +} + +define i32 @test3(i32 %X, i32 %Y) { + %a = and i32 %X, %Y + %b = and i32 %Y, %a + ret i32 %b +; CHECK: @test3 +; CHECK-NEXT: and i32 %X, %Y +; CHECK-NEXT: ret +} Modified: llvm/trunk/test/Transforms/InstCombine/or.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/or.ll?rev=113651&r1=113650&r2=113651&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/or.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/or.ll Fri Sep 10 17:39:55 2010 @@ -350,3 +350,20 @@ ; CHECK: or <4 x i32> %and.i, %and.i129 } +define i1 @test33(i1 %X, i1 %Y) { + %a = or i1 %X, %Y + %b = or i1 %a, %X + ret i1 %b +; CHECK: @test33 +; CHECK-NEXT: or i1 %X, %Y +; CHECK-NEXT: ret +} + +define i32 @test34(i32 %X, i32 %Y) { + %a = or i32 %X, %Y + %b = or i32 %Y, %a + ret i32 %b +; CHECK: @test34 +; CHECK-NEXT: or i32 %X, %Y +; CHECK-NEXT: ret +} From echristo at apple.com Fri Sep 10 17:42:07 2010 From: echristo at apple.com (Eric Christopher) Date: Fri, 10 Sep 2010 22:42:07 -0000 Subject: [llvm-commits] [llvm] r113652 - in /llvm/trunk/lib/Target/ARM: ARMCallingConv.h ARMISelLowering.cpp Message-ID: <20100910224207.2F9802A6C12C@llvm.org> Author: echristo Date: Fri Sep 10 17:42:06 2010 New Revision: 113652 URL: http://llvm.org/viewvc/llvm-project?rev=113652&view=rev Log: Split out some of the calling convention bits so that they can be used for fast-isel. Added: llvm/trunk/lib/Target/ARM/ARMCallingConv.h Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Added: llvm/trunk/lib/Target/ARM/ARMCallingConv.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCallingConv.h?rev=113652&view=auto ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCallingConv.h (added) +++ llvm/trunk/lib/Target/ARM/ARMCallingConv.h Fri Sep 10 17:42:06 2010 @@ -0,0 +1,160 @@ +//===-- ARMCallingConv.h - ARM Custom Calling Convention Routines ---------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the custom routines for the ARM Calling Convention that +// aren't done by tablegen. +// +//===----------------------------------------------------------------------===// + +#ifndef ARMCALLINGCONV_H +#define ARMCALLINGCONV_H + +#include "llvm/CallingConv.h" +#include "llvm/CodeGen/CallingConvLower.h" +#include "llvm/Target/TargetInstrInfo.h" +#include "ARMBaseInstrInfo.h" +#include "ARMRegisterInfo.h" +#include "ARMSubtarget.h" +#include "ARM.h" + +namespace llvm { + +// APCS f64 is in register pairs, possibly split to stack +static bool f64AssignAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT, + CCValAssign::LocInfo &LocInfo, + CCState &State, bool CanFail) { + static const unsigned RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; + + // Try to get the first register. + if (unsigned Reg = State.AllocateReg(RegList, 4)) + State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); + else { + // For the 2nd half of a v2f64, do not fail. + if (CanFail) + return false; + + // Put the whole thing on the stack. + State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, + State.AllocateStack(8, 4), + LocVT, LocInfo)); + return true; + } + + // Try to get the second register. + if (unsigned Reg = State.AllocateReg(RegList, 4)) + State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); + else + State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, + State.AllocateStack(4, 4), + LocVT, LocInfo)); + return true; +} + +static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, + CCValAssign::LocInfo &LocInfo, + ISD::ArgFlagsTy &ArgFlags, + CCState &State) { + if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true)) + return false; + if (LocVT == MVT::v2f64 && + !f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false)) + return false; + return true; // we handled it +} + +// AAPCS f64 is in aligned register pairs +static bool f64AssignAAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT, + CCValAssign::LocInfo &LocInfo, + CCState &State, bool CanFail) { + static const unsigned HiRegList[] = { ARM::R0, ARM::R2 }; + static const unsigned LoRegList[] = { ARM::R1, ARM::R3 }; + static const unsigned ShadowRegList[] = { ARM::R0, ARM::R1 }; + + unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList, 2); + if (Reg == 0) { + // For the 2nd half of a v2f64, do not just fail. + if (CanFail) + return false; + + // Put the whole thing on the stack. + State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, + State.AllocateStack(8, 8), + LocVT, LocInfo)); + return true; + } + + unsigned i; + for (i = 0; i < 2; ++i) + if (HiRegList[i] == Reg) + break; + + unsigned T = State.AllocateReg(LoRegList[i]); + (void)T; + assert(T == LoRegList[i] && "Could not allocate register"); + + State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); + State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i], + LocVT, LocInfo)); + return true; +} + +static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, + CCValAssign::LocInfo &LocInfo, + ISD::ArgFlagsTy &ArgFlags, + CCState &State) { + if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true)) + return false; + if (LocVT == MVT::v2f64 && + !f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false)) + return false; + return true; // we handled it +} + +static bool f64RetAssign(unsigned &ValNo, EVT &ValVT, EVT &LocVT, + CCValAssign::LocInfo &LocInfo, CCState &State) { + static const unsigned HiRegList[] = { ARM::R0, ARM::R2 }; + static const unsigned LoRegList[] = { ARM::R1, ARM::R3 }; + + unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2); + if (Reg == 0) + return false; // we didn't handle it + + unsigned i; + for (i = 0; i < 2; ++i) + if (HiRegList[i] == Reg) + break; + + State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); + State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i], + LocVT, LocInfo)); + return true; +} + +static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, + CCValAssign::LocInfo &LocInfo, + ISD::ArgFlagsTy &ArgFlags, + CCState &State) { + if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State)) + return false; + if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State)) + return false; + return true; // we handled it +} + +static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, + CCValAssign::LocInfo &LocInfo, + ISD::ArgFlagsTy &ArgFlags, + CCState &State) { + return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, + State); +} + +} // End llvm namespace + +#endif \ No newline at end of file Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=113652&r1=113651&r2=113652&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri Sep 10 17:42:06 2010 @@ -15,6 +15,7 @@ #define DEBUG_TYPE "arm-isel" #include "ARM.h" #include "ARMAddressingModes.h" +#include "ARMCallingConv.h" #include "ARMConstantPoolValue.h" #include "ARMISelLowering.h" #include "ARMMachineFunctionInfo.h" @@ -79,23 +80,6 @@ cl::desc("Enable code placement pass for ARM"), cl::init(false)); -static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, - CCValAssign::LocInfo &LocInfo, - ISD::ArgFlagsTy &ArgFlags, - CCState &State); -static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, - CCValAssign::LocInfo &LocInfo, - ISD::ArgFlagsTy &ArgFlags, - CCState &State); -static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, - CCValAssign::LocInfo &LocInfo, - ISD::ArgFlagsTy &ArgFlags, - CCState &State); -static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, - CCValAssign::LocInfo &LocInfo, - ISD::ArgFlagsTy &ArgFlags, - CCState &State); - void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT) { if (VT != PromotedLdStVT) { @@ -829,136 +813,6 @@ #include "ARMGenCallingConv.inc" -// APCS f64 is in register pairs, possibly split to stack -static bool f64AssignAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT, - CCValAssign::LocInfo &LocInfo, - CCState &State, bool CanFail) { - static const unsigned RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; - - // Try to get the first register. - if (unsigned Reg = State.AllocateReg(RegList, 4)) - State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); - else { - // For the 2nd half of a v2f64, do not fail. - if (CanFail) - return false; - - // Put the whole thing on the stack. - State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, - State.AllocateStack(8, 4), - LocVT, LocInfo)); - return true; - } - - // Try to get the second register. - if (unsigned Reg = State.AllocateReg(RegList, 4)) - State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); - else - State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, - State.AllocateStack(4, 4), - LocVT, LocInfo)); - return true; -} - -static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, - CCValAssign::LocInfo &LocInfo, - ISD::ArgFlagsTy &ArgFlags, - CCState &State) { - if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true)) - return false; - if (LocVT == MVT::v2f64 && - !f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false)) - return false; - return true; // we handled it -} - -// AAPCS f64 is in aligned register pairs -static bool f64AssignAAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT, - CCValAssign::LocInfo &LocInfo, - CCState &State, bool CanFail) { - static const unsigned HiRegList[] = { ARM::R0, ARM::R2 }; - static const unsigned LoRegList[] = { ARM::R1, ARM::R3 }; - static const unsigned ShadowRegList[] = { ARM::R0, ARM::R1 }; - - unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList, 2); - if (Reg == 0) { - // For the 2nd half of a v2f64, do not just fail. - if (CanFail) - return false; - - // Put the whole thing on the stack. - State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, - State.AllocateStack(8, 8), - LocVT, LocInfo)); - return true; - } - - unsigned i; - for (i = 0; i < 2; ++i) - if (HiRegList[i] == Reg) - break; - - unsigned T = State.AllocateReg(LoRegList[i]); - (void)T; - assert(T == LoRegList[i] && "Could not allocate register"); - - State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); - State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i], - LocVT, LocInfo)); - return true; -} - -static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, - CCValAssign::LocInfo &LocInfo, - ISD::ArgFlagsTy &ArgFlags, - CCState &State) { - if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true)) - return false; - if (LocVT == MVT::v2f64 && - !f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false)) - return false; - return true; // we handled it -} - -static bool f64RetAssign(unsigned &ValNo, EVT &ValVT, EVT &LocVT, - CCValAssign::LocInfo &LocInfo, CCState &State) { - static const unsigned HiRegList[] = { ARM::R0, ARM::R2 }; - static const unsigned LoRegList[] = { ARM::R1, ARM::R3 }; - - unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2); - if (Reg == 0) - return false; // we didn't handle it - - unsigned i; - for (i = 0; i < 2; ++i) - if (HiRegList[i] == Reg) - break; - - State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); - State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i], - LocVT, LocInfo)); - return true; -} - -static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, - CCValAssign::LocInfo &LocInfo, - ISD::ArgFlagsTy &ArgFlags, - CCState &State) { - if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State)) - return false; - if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State)) - return false; - return true; // we handled it -} - -static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, - CCValAssign::LocInfo &LocInfo, - ISD::ArgFlagsTy &ArgFlags, - CCState &State) { - return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, - State); -} - /// CCAssignFnForNode - Selects the correct CCAssignFn for a the /// given CallingConvention value. CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC, From bob.wilson at apple.com Fri Sep 10 17:42:21 2010 From: bob.wilson at apple.com (Bob Wilson) Date: Fri, 10 Sep 2010 22:42:21 -0000 Subject: [llvm-commits] [llvm] r113653 - /llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp Message-ID: <20100910224221.B5B2A2A6C12C@llvm.org> Author: bwilson Date: Fri Sep 10 17:42:21 2010 New Revision: 113653 URL: http://llvm.org/viewvc/llvm-project?rev=113653&view=rev Log: Fix a comment typo. Modified: llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp Modified: llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp?rev=113653&r1=113652&r2=113653&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp (original) +++ llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp Fri Sep 10 17:42:21 2010 @@ -177,7 +177,7 @@ // that have special allocation requirements. Also assume all registers // used in a call must not be changed (ABI). // FIXME: The issue with predicated instruction is more complex. We are being - // conservatively here because the kill markers cannot be trusted after + // conservative here because the kill markers cannot be trusted after // if-conversion: // %R6 = LDR %SP, %reg0, 92, pred:14, pred:%reg0; mem:LD4[FixedStack14] // ... From echristo at apple.com Fri Sep 10 17:46:03 2010 From: echristo at apple.com (Eric Christopher) Date: Fri, 10 Sep 2010 22:46:03 -0000 Subject: [llvm-commits] [llvm] r113654 - /llvm/trunk/lib/Target/ARM/ARMCallingConv.h Message-ID: <20100910224603.321532A6C12C@llvm.org> Author: echristo Date: Fri Sep 10 17:46:03 2010 New Revision: 113654 URL: http://llvm.org/viewvc/llvm-project?rev=113654&view=rev Log: Newline at end of file. Modified: llvm/trunk/lib/Target/ARM/ARMCallingConv.h Modified: llvm/trunk/lib/Target/ARM/ARMCallingConv.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCallingConv.h?rev=113654&r1=113653&r2=113654&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCallingConv.h (original) +++ llvm/trunk/lib/Target/ARM/ARMCallingConv.h Fri Sep 10 17:46:03 2010 @@ -157,4 +157,4 @@ } // End llvm namespace -#endif \ No newline at end of file +#endif From echristo at apple.com Fri Sep 10 18:10:30 2010 From: echristo at apple.com (Eric Christopher) Date: Fri, 10 Sep 2010 23:10:30 -0000 Subject: [llvm-commits] [llvm] r113659 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20100910231030.48C1F2A6C12C@llvm.org> Author: echristo Date: Fri Sep 10 18:10:30 2010 New Revision: 113659 URL: http://llvm.org/viewvc/llvm-project?rev=113659&view=rev Log: For consistency. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=113659&r1=113658&r2=113659&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Fri Sep 10 18:10:30 2010 @@ -110,6 +110,7 @@ #include "ARMGenFastISel.inc" // Instruction selection routines. + private: virtual bool ARMSelectLoad(const Instruction *I); virtual bool ARMSelectStore(const Instruction *I); virtual bool ARMSelectBranch(const Instruction *I); From echristo at apple.com Fri Sep 10 18:18:12 2010 From: echristo at apple.com (Eric Christopher) Date: Fri, 10 Sep 2010 23:18:12 -0000 Subject: [llvm-commits] [llvm] r113662 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20100910231812.CB7492A6C12C@llvm.org> Author: echristo Date: Fri Sep 10 18:18:12 2010 New Revision: 113662 URL: http://llvm.org/viewvc/llvm-project?rev=113662&view=rev Log: Start sketching out ARM fast-isel calls. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=113662&r1=113661&r2=113662&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Fri Sep 10 18:18:12 2010 @@ -15,6 +15,7 @@ #include "ARM.h" #include "ARMBaseInstrInfo.h" +#include "ARMCallingConv.h" #include "ARMRegisterInfo.h" #include "ARMTargetMachine.h" #include "ARMSubtarget.h" @@ -135,13 +136,19 @@ unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg); unsigned ARMMoveToIntReg(EVT VT, unsigned SrcReg); + // Call handling routines. + private: + CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool Return); + + // OptionalDef handling routines. + private: bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR); const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB); }; } // end anonymous namespace -// #include "ARMGenCallingConv.inc" +#include "ARMGenCallingConv.inc" // DefinesOptionalPredicate - This is different from DefinesPredicate in that // we don't care about implicit defs here, just places we'll need to add a @@ -895,6 +902,35 @@ return true; } +// Call Handling Code + +// This is largely taken directly from CCAssignFnForNode - we don't support +// varargs in FastISel so that part has been removed. +// TODO: We may not support all of this. +CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC, bool Return) { + switch (CC) { + default: + llvm_unreachable("Unsupported calling convention"); + case CallingConv::C: + case CallingConv::Fast: + // Use target triple & subtarget features to do actual dispatch. + if (Subtarget->isAAPCS_ABI()) { + if (Subtarget->hasVFP2() && + FloatABIType == FloatABI::Hard) + return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP); + else + return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS); + } else + return (Return ? RetCC_ARM_APCS: CC_ARM_APCS); + case CallingConv::ARM_AAPCS_VFP: + return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP); + case CallingConv::ARM_AAPCS: + return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS); + case CallingConv::ARM_APCS: + return (Return ? RetCC_ARM_APCS: CC_ARM_APCS); + } +} + // TODO: SoftFP support. bool ARMFastISel::TargetSelectInstruction(const Instruction *I) { // No Thumb-1 for now. From isanbard at gmail.com Fri Sep 10 18:34:19 2010 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 10 Sep 2010 23:34:19 -0000 Subject: [llvm-commits] [llvm] r113665 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/PeepholeOptimizer.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h Message-ID: <20100910233419.E7DA82A6C12C@llvm.org> Author: void Date: Fri Sep 10 18:34:19 2010 New Revision: 113665 URL: http://llvm.org/viewvc/llvm-project?rev=113665&view=rev Log: Move some of the decision logic for converting an instruction into one that sets the 'zero' bit down into the back-end. There are other cases where this logic isn't sufficient, so they should be handled separately. Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=113665&r1=113664&r2=113665&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Fri Sep 10 18:34:19 2010 @@ -585,11 +585,10 @@ return false; } - /// ConvertToSetZeroFlag - Convert the instruction to set the zero flag so - /// that we can remove a "comparison with zero". Update the iterator *only* - /// if a transformation took place. - virtual bool ConvertToSetZeroFlag(MachineInstr * /*Instr*/, - MachineInstr * /*CmpInstr*/, + /// ConvertToSetZeroFlag - Convert the instruction supplying the argument to + /// the comparison into one that sets the zero bit in the flags + /// register. Update the iterator *only* if a transformation took place. + virtual bool ConvertToSetZeroFlag(MachineInstr * /*CmpInstr*/, MachineBasicBlock::iterator &) const { return false; } Modified: llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp?rev=113665&r1=113664&r2=113665&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp (original) +++ llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp Fri Sep 10 18:34:19 2010 @@ -240,16 +240,11 @@ unsigned SrcReg; int CmpValue; if (!TII->AnalyzeCompare(MI, SrcReg, CmpValue) || - TargetRegisterInfo::isPhysicalRegister(SrcReg) || CmpValue != 0) - return false; - - MachineRegisterInfo::def_iterator DI = MRI->def_begin(SrcReg); - if (llvm::next(DI) != MRI->def_end()) - // Only support one definition. + TargetRegisterInfo::isPhysicalRegister(SrcReg)) return false; // Attempt to convert the defining instruction to set the "zero" flag. - if (TII->ConvertToSetZeroFlag(&*DI, MI, NextIter)) { + if (TII->ConvertToSetZeroFlag(MI, NextIter)) { ++NumEliminated; return true; } Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=113665&r1=113664&r2=113665&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Fri Sep 10 18:34:19 2010 @@ -1377,12 +1377,25 @@ return false; } -/// ConvertToSetZeroFlag - Convert the instruction to set the "zero" flag so -/// that we can remove a "comparison with zero". Update the iterator *only* if a -/// transformation took place. +/// ConvertToSetZeroFlag - Convert the instruction supplying the argument to the +/// comparison into one that sets the zero bit in the flags register. Update the +/// iterator *only* if a transformation took place. bool ARMBaseInstrInfo:: -ConvertToSetZeroFlag(MachineInstr *MI, MachineInstr *CmpInstr, +ConvertToSetZeroFlag(MachineInstr *CmpInstr, MachineBasicBlock::iterator &MII) const { + unsigned SrcReg; + int CmpValue; + if (!AnalyzeCompare(CmpInstr, SrcReg, CmpValue) || CmpValue != 0) + return false; + + MachineRegisterInfo &MRI = CmpInstr->getParent()->getParent()->getRegInfo(); + MachineRegisterInfo::def_iterator DI = MRI.def_begin(SrcReg); + if (llvm::next(DI) != MRI.def_end()) + // Only support one definition. + return false; + + MachineInstr *MI = &*DI; + // Conservatively refuse to convert an instruction which isn't in the same BB // as the comparison. if (MI->getParent() != CmpInstr->getParent()) Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h?rev=113665&r1=113664&r2=113665&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Fri Sep 10 18:34:19 2010 @@ -346,8 +346,7 @@ /// ConvertToSetZeroFlag - Convert the instruction to set the zero flag so /// that we can remove a "comparison with zero". - virtual bool ConvertToSetZeroFlag(MachineInstr *Instr, - MachineInstr *CmpInstr, + virtual bool ConvertToSetZeroFlag(MachineInstr *CmpInstr, MachineBasicBlock::iterator &MII) const; virtual unsigned getNumMicroOps(const MachineInstr *MI, From isanbard at gmail.com Fri Sep 10 18:46:12 2010 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 10 Sep 2010 23:46:12 -0000 Subject: [llvm-commits] [llvm] r113666 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/PeepholeOptimizer.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h Message-ID: <20100910234612.480532A6C12C@llvm.org> Author: void Date: Fri Sep 10 18:46:12 2010 New Revision: 113666 URL: http://llvm.org/viewvc/llvm-project?rev=113666&view=rev Log: No need to recompute the SrcReg and CmpValue. Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=113666&r1=113665&r2=113666&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Fri Sep 10 18:46:12 2010 @@ -589,6 +589,7 @@ /// the comparison into one that sets the zero bit in the flags /// register. Update the iterator *only* if a transformation took place. virtual bool ConvertToSetZeroFlag(MachineInstr * /*CmpInstr*/, + unsigned /*SrcReg*/, int /*CmpValue*/, MachineBasicBlock::iterator &) const { return false; } Modified: llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp?rev=113666&r1=113665&r2=113666&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp (original) +++ llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp Fri Sep 10 18:46:12 2010 @@ -244,7 +244,7 @@ return false; // Attempt to convert the defining instruction to set the "zero" flag. - if (TII->ConvertToSetZeroFlag(MI, NextIter)) { + if (TII->ConvertToSetZeroFlag(MI, SrcReg, CmpValue, NextIter)) { ++NumEliminated; return true; } Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=113666&r1=113665&r2=113666&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Fri Sep 10 18:46:12 2010 @@ -1381,11 +1381,9 @@ /// comparison into one that sets the zero bit in the flags register. Update the /// iterator *only* if a transformation took place. bool ARMBaseInstrInfo:: -ConvertToSetZeroFlag(MachineInstr *CmpInstr, +ConvertToSetZeroFlag(MachineInstr *CmpInstr, unsigned SrcReg, int CmpValue, MachineBasicBlock::iterator &MII) const { - unsigned SrcReg; - int CmpValue; - if (!AnalyzeCompare(CmpInstr, SrcReg, CmpValue) || CmpValue != 0) + if (CmpValue != 0) return false; MachineRegisterInfo &MRI = CmpInstr->getParent()->getParent()->getRegInfo(); Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h?rev=113666&r1=113665&r2=113666&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Fri Sep 10 18:46:12 2010 @@ -346,7 +346,8 @@ /// ConvertToSetZeroFlag - Convert the instruction to set the zero flag so /// that we can remove a "comparison with zero". - virtual bool ConvertToSetZeroFlag(MachineInstr *CmpInstr, + virtual bool ConvertToSetZeroFlag(MachineInstr *CmpInstr, unsigned SrcReg, + int CmpValue, MachineBasicBlock::iterator &MII) const; virtual unsigned getNumMicroOps(const MachineInstr *MI, From isanbard at gmail.com Fri Sep 10 19:13:50 2010 From: isanbard at gmail.com (Bill Wendling) Date: Sat, 11 Sep 2010 00:13:50 -0000 Subject: [llvm-commits] [llvm] r113670 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/PeepholeOptimizer.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h Message-ID: <20100911001350.9B7AE2A6C12C@llvm.org> Author: void Date: Fri Sep 10 19:13:50 2010 New Revision: 113670 URL: http://llvm.org/viewvc/llvm-project?rev=113670&view=rev Log: Rename ConvertToSetZeroFlag to something more general. Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=113670&r1=113669&r2=113670&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Fri Sep 10 19:13:50 2010 @@ -585,10 +585,11 @@ return false; } - /// ConvertToSetZeroFlag - Convert the instruction supplying the argument to - /// the comparison into one that sets the zero bit in the flags - /// register. Update the iterator *only* if a transformation took place. - virtual bool ConvertToSetZeroFlag(MachineInstr * /*CmpInstr*/, + /// OptimizeCompareInstr - See if the comparison instruction can be converted + /// into something more efficient. E.g., on ARM most instructions can set the + /// flags register, obviating the need for a separate CMP. Update the iterator + /// *only* if a transformation took place. + virtual bool OptimizeCompareInstr(MachineInstr * /*CmpInstr*/, unsigned /*SrcReg*/, int /*CmpValue*/, MachineBasicBlock::iterator &) const { return false; Modified: llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp?rev=113670&r1=113669&r2=113670&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp (original) +++ llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp Fri Sep 10 19:13:50 2010 @@ -243,8 +243,8 @@ TargetRegisterInfo::isPhysicalRegister(SrcReg)) return false; - // Attempt to convert the defining instruction to set the "zero" flag. - if (TII->ConvertToSetZeroFlag(MI, SrcReg, CmpValue, NextIter)) { + // Attempt to optimize the comparison instruction. + if (TII->OptimizeCompareInstr(MI, SrcReg, CmpValue, NextIter)) { ++NumEliminated; return true; } Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=113670&r1=113669&r2=113670&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Fri Sep 10 19:13:50 2010 @@ -1377,11 +1377,11 @@ return false; } -/// ConvertToSetZeroFlag - Convert the instruction supplying the argument to the +/// OptimizeCompareInstr - Convert the instruction supplying the argument to the /// comparison into one that sets the zero bit in the flags register. Update the /// iterator *only* if a transformation took place. bool ARMBaseInstrInfo:: -ConvertToSetZeroFlag(MachineInstr *CmpInstr, unsigned SrcReg, int CmpValue, +OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpValue, MachineBasicBlock::iterator &MII) const { if (CmpValue != 0) return false; Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h?rev=113670&r1=113669&r2=113670&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Fri Sep 10 19:13:50 2010 @@ -344,9 +344,9 @@ virtual bool AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, int &CmpValue) const; - /// ConvertToSetZeroFlag - Convert the instruction to set the zero flag so + /// OptimizeCompareInstr - Convert the instruction to set the zero flag so /// that we can remove a "comparison with zero". - virtual bool ConvertToSetZeroFlag(MachineInstr *CmpInstr, unsigned SrcReg, + virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpValue, MachineBasicBlock::iterator &MII) const; From dalej at apple.com Fri Sep 10 19:16:46 2010 From: dalej at apple.com (Dale Johannesen) Date: Sat, 11 Sep 2010 00:16:46 -0000 Subject: [llvm-commits] [llvm] r113671 - /llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp Message-ID: <20100911001646.8CAF02A6C12C@llvm.org> Author: johannes Date: Fri Sep 10 19:16:46 2010 New Revision: 113671 URL: http://llvm.org/viewvc/llvm-project?rev=113671&view=rev Log: Add x86mmx to TableGen. Modified: llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp Modified: llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp?rev=113671&r1=113670&r2=113671&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/IntrinsicEmitter.cpp Fri Sep 10 19:16:46 2010 @@ -192,6 +192,8 @@ OS << "Type::getVoidTy(Context)"; } else if (VT == MVT::Metadata) { OS << "Type::getMetadataTy(Context)"; + } else if (VT == MVT::x86mmx) { + OS << "Type::getX86_MMXTy(Context)"; } else { assert(false && "Unsupported ValueType!"); } From bigcheesegs at gmail.com Fri Sep 10 21:13:39 2010 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Sat, 11 Sep 2010 02:13:39 -0000 Subject: [llvm-commits] [llvm] r113676 - in /llvm/trunk: CMakeLists.txt cmake/modules/AddLLVM.cmake Message-ID: <20100911021339.78C9D2A6C12C@llvm.org> Author: mspencer Date: Fri Sep 10 21:13:39 2010 New Revision: 113676 URL: http://llvm.org/viewvc/llvm-project?rev=113676&view=rev Log: CMake: Fix mingw32 build. Modified: llvm/trunk/CMakeLists.txt llvm/trunk/cmake/modules/AddLLVM.cmake Modified: llvm/trunk/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CMakeLists.txt?rev=113676&r1=113675&r2=113676&view=diff ============================================================================== --- llvm/trunk/CMakeLists.txt (original) +++ llvm/trunk/CMakeLists.txt Fri Sep 10 21:13:39 2010 @@ -258,6 +258,15 @@ include(AddLLVM) include(TableGen) +if( MINGW ) + get_system_libs(LLVM_SYSTEM_LIBS_LIST) + foreach(l ${LLVM_SYSTEM_LIBS_LIST}) + set(LLVM_SYSTEM_LIBS "${LLVM_SYSTEM_LIBS} -l${l}") + endforeach() + set(CMAKE_CXX_STANDARD_LIBRARIES "${CMAKE_CXX_STANDARD_LIBRARIES}${LLVM_SYSTEM_LIBS}") + set(CMAKE_C_STANDARD_LIBRARIES "${CMAKE_C_STANDARD_LIBRARIES}${LLVM_SYSTEM_LIBS}") +endif() + add_subdirectory(lib/Support) add_subdirectory(lib/System) Modified: llvm/trunk/cmake/modules/AddLLVM.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/AddLLVM.cmake?rev=113676&r1=113675&r2=113676&view=diff ============================================================================== --- llvm/trunk/cmake/modules/AddLLVM.cmake (original) +++ llvm/trunk/cmake/modules/AddLLVM.cmake Fri Sep 10 21:13:39 2010 @@ -78,16 +78,18 @@ target_link_libraries( ${name} ${lib} ) endforeach(lib) endif( LLVM_USED_LIBS ) - get_system_libs(llvm_system_libs) - if( llvm_system_libs ) - target_link_libraries(${name} ${llvm_system_libs}) - endif() if( LLVM_COMMON_DEPENDS ) add_dependencies( ${name} ${LLVM_COMMON_DEPENDS} ) endif( LLVM_COMMON_DEPENDS ) if (LLVM_COMMON_LIBS) target_link_libraries(${name} ${LLVM_COMMON_LIBS}) endif() + if( NOT MINGW ) + get_system_libs(llvm_system_libs) + if( llvm_system_libs ) + target_link_libraries(${name} ${llvm_system_libs}) + endif() + endif() endmacro(add_llvm_executable name) From daniel at zuster.org Fri Sep 10 22:26:02 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Fri, 10 Sep 2010 20:26:02 -0700 Subject: [llvm-commits] [llvm] r113595 - /llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp In-Reply-To: <20100910175700.394A12A6C12C@llvm.org> References: <20100910175700.394A12A6C12C@llvm.org> Message-ID: On Fri, Sep 10, 2010 at 10:57 AM, Owen Anderson wrote: > Author: resistor > Date: Fri Sep 10 12:57:00 2010 > New Revision: 113595 > > URL: http://llvm.org/viewvc/llvm-project?rev=113595&view=rev > Log: > Lower the unrolling theshold to 150. ?Empirical tests indicate that this is a sweet spot in the performance per > code size increase curve. Graphs? :) - Daniel > Modified: > ? ?llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp > > Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp?rev=113595&r1=113594&r2=113595&view=diff > ============================================================================== > --- llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp (original) > +++ llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp Fri Sep 10 12:57:00 2010 > @@ -27,7 +27,7 @@ > ?using namespace llvm; > > ?static cl::opt > -UnrollThreshold("unroll-threshold", cl::init(200), cl::Hidden, > +UnrollThreshold("unroll-threshold", cl::init(150), cl::Hidden, > ? cl::desc("The cut-off point for automatic loop unrolling")); > > ?static cl::opt > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From daniel at zuster.org Fri Sep 10 22:30:08 2010 From: daniel at zuster.org (Daniel Dunbar) Date: Fri, 10 Sep 2010 20:30:08 -0700 Subject: [llvm-commits] [patch][MC] Change the way we dump section_data In-Reply-To: References: Message-ID: Sure, LGTM. Ideally we would replace both of these with more sane dumping tools. FWIW, the original motivation behind macho-dump was because I wanted a pure representation of every byte in the object file, since we were shooting for bitwise equivalence with Darwin 'as'. Now that we have achieved that, it would definitely make sense to move to more readable output formats -- especially if we get a real llvm-objdump. Thanks, - Daniel On Fri, Sep 10, 2010 at 11:38 AM, Rafael Espindola wrote: > While working on the LEB128 patch I found the output of elf-dump and > macho-dump for section_data hard to read. The problem is that "%r" > works best for mostly ascii data. Since that is normally the case, we > get things like "\xc88\xf4". Note that the second '8' is the ascii > char '8'. With this patch we get "c838f4" with a space every 4 bytes. > IMHO it makes the output a lot easier to decode. > > Cheers, > -- > Rafael ?vila de Esp?ndola > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > From resistor at mac.com Sat Sep 11 00:48:06 2010 From: resistor at mac.com (Owen Anderson) Date: Sat, 11 Sep 2010 05:48:06 -0000 Subject: [llvm-commits] [llvm] r113679 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineAndOrXor.cpp test/Transforms/InstCombine/and-or-inversion.ll test/Transforms/InstCombine/cast.ll test/Transforms/InstCombine/or.ll test/Transforms/InstCombine/xor2.ll Message-ID: <20100911054807.0AD9B2A6C12C@llvm.org> Author: resistor Date: Sat Sep 11 00:48:06 2010 New Revision: 113679 URL: http://llvm.org/viewvc/llvm-project?rev=113679&view=rev Log: Invert and-of-or into or-of-and when doing so would allow us to clear bits of the and's mask. This can result in increased opportunities for store narrowing in code generation. Update a number of tests for this change. This fixes . Additionally, because this inverts the order of ors and ands, some patterns for optimizing or-of-and-of-or no longer fire in instances where they did originally. Add a simple transform which recaptures most of these opportunities: if we have an or-of-constant-or and have failed to fold away the inner or, commute the order of the two ors, to give the non-constant or a chance for simplification instead. Added: llvm/trunk/test/Transforms/InstCombine/and-or-inversion.ll Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp llvm/trunk/test/Transforms/InstCombine/cast.ll llvm/trunk/test/Transforms/InstCombine/or.ll llvm/trunk/test/Transforms/InstCombine/xor2.ll Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp?rev=113679&r1=113678&r2=113679&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp Sat Sep 11 00:48:06 2010 @@ -207,12 +207,26 @@ } break; case Instruction::Or: - if (Op->hasOneUse() && Together != OpRHS) { - // (X | C1) & C2 --> (X | (C1&C2)) & C2 - Value *Or = Builder->CreateOr(X, Together); - Or->takeName(Op); - return BinaryOperator::CreateAnd(Or, AndRHS); + if (Op->hasOneUse()){ + if (Together != OpRHS) { + // (X | C1) & C2 --> (X | (C1&C2)) & C2 + Value *Or = Builder->CreateOr(X, Together); + Or->takeName(Op); + return BinaryOperator::CreateAnd(Or, AndRHS); + } + + ConstantInt *TogetherCI = dyn_cast(Together); + if (TogetherCI && !TogetherCI->isZero()){ + // (X | C1) & C2 --> (X & (C2^(C1&C2))) | C1 + // NOTE: This reduces the number of bits set in the & mask, which + // can expose opportunities for store narrowing. + Together = ConstantExpr::getXor(AndRHS, Together); + Value *And = Builder->CreateAnd(X, Together); + And->takeName(Op); + return BinaryOperator::CreateOr(And, OpRHS); + } } + break; case Instruction::Add: if (Op->hasOneUse()) { @@ -1943,6 +1957,17 @@ } } + // Note: If we've gotten to the point of visiting the outer OR, then the + // inner one couldn't be simplified. If it was a constant, then it won't + // be simplified by a later pass either, so we try swapping the inner/outer + // ORs in the hopes that we'll be able to simplify it this way. + // (X|C) | V --> (X|V) | C + if (Op0->hasOneUse() && match(Op0, m_Or(m_Value(A), m_ConstantInt(C1)))) { + Value *Inner = Builder->CreateOr(Op0, Op1); + Inner->takeName(Op0); + return BinaryOperator::CreateOr(Inner, C1); + } + return Changed ? &I : 0; } Added: llvm/trunk/test/Transforms/InstCombine/and-or-inversion.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/and-or-inversion.ll?rev=113679&view=auto ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/and-or-inversion.ll (added) +++ llvm/trunk/test/Transforms/InstCombine/and-or-inversion.ll Sat Sep 11 00:48:06 2010 @@ -0,0 +1,13 @@ +; RUN: opt -S -instcombine < %s | FileCheck %s +; + +; CHECK: @func +define i32 @func(i32 %a) nounwind ssp align 2 { +entry: +; CHECK: and i32 %a, -256 + %0 = or i32 %a, 8 +; CHECK: or i32 %0, 8 + %1 = and i32 %0, -248 + ret i32 %1 +; CHECK: } +} Modified: llvm/trunk/test/Transforms/InstCombine/cast.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/cast.ll?rev=113679&r1=113678&r2=113679&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/cast.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/cast.ll Sat Sep 11 00:48:06 2010 @@ -437,8 +437,8 @@ ret i64 %E ; CHECK: @test47 ; CHECK-NEXT: %B = sext i8 %A to i64 -; CHECK-NEXT: %C = or i64 %B, 42 -; CHECK-NEXT: %E = and i64 %C, 4294967295 +; CHECK-NEXT: %C = and i64 %B, 4294967253 +; CHECK-NEXT: %E = or i64 %C, 42 ; CHECK-NEXT: ret i64 %E } @@ -508,8 +508,8 @@ ret i32 %E ; CHECK: @test52 ; CHECK-NEXT: %B = trunc i64 %A to i32 -; CHECK-NEXT: %C = or i32 %B, 32962 -; CHECK-NEXT: %D = and i32 %C, 40186 +; CHECK-NEXT: %C = and i32 %B, 7224 +; CHECK-NEXT: %D = or i32 %C, 32962 ; CHECK-NEXT: ret i32 %D } @@ -521,8 +521,8 @@ ret i64 %E ; CHECK: @test53 ; CHECK-NEXT: %B = zext i32 %A to i64 -; CHECK-NEXT: %C = or i64 %B, 32962 -; CHECK-NEXT: %D = and i64 %C, 40186 +; CHECK-NEXT: %C = and i64 %B, 7224 +; CHECK-NEXT: %D = or i64 %C, 32962 ; CHECK-NEXT: ret i64 %D } @@ -534,8 +534,8 @@ ret i32 %E ; CHECK: @test54 ; CHECK-NEXT: %B = trunc i64 %A to i32 -; CHECK-NEXT: %C = or i32 %B, -32574 -; CHECK-NEXT: %D = and i32 %C, -25350 +; CHECK-NEXT: %C = and i32 %B, 7224 +; CHECK-NEXT: %D = or i32 %C, -32574 ; CHECK-NEXT: ret i32 %D } @@ -547,8 +547,8 @@ ret i64 %E ; CHECK: @test55 ; CHECK-NEXT: %B = zext i32 %A to i64 -; CHECK-NEXT: %C = or i64 %B, -32574 -; CHECK-NEXT: %D = and i64 %C, -25350 +; CHECK-NEXT: %C = and i64 %B, 7224 +; CHECK-NEXT: %D = or i64 %C, -32574 ; CHECK-NEXT: ret i64 %D } @@ -584,8 +584,8 @@ ; CHECK: @test58 ; CHECK-NEXT: %C = lshr i64 %A, 8 -; CHECK-NEXT: %D = or i64 %C, 128 -; CHECK-NEXT: %E = and i64 %D, 16777215 +; CHECK-NEXT: %D = and i64 %C, 16777087 +; CHECK-NEXT: %E = or i64 %D, 128 ; CHECK-NEXT: ret i64 %E } Modified: llvm/trunk/test/Transforms/InstCombine/or.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/or.ll?rev=113679&r1=113678&r2=113679&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/or.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/or.ll Sat Sep 11 00:48:06 2010 @@ -316,8 +316,8 @@ %E = or i32 %D, %C ret i32 %E ; CHECK: @test30 -; CHECK: %B = or i32 %A, 32962 -; CHECK: %E = and i32 %B, -25350 +; CHECK: %D = and i32 %A, -58312 +; CHECK: %E = or i32 %D, 32962 ; CHECK: ret i32 %E } @@ -332,8 +332,8 @@ %F = or i64 %D, %E ret i64 %F ; CHECK: @test31 -; CHECK-NEXT: %bitfield = or i64 %A, 32962 -; CHECK-NEXT: %F = and i64 %bitfield, 4294941946 +; CHECK-NEXT: %E1 = and i64 %A, 4294908984 +; CHECK-NEXT: %F = or i64 %E1, 32962 ; CHECK-NEXT: ret i64 %F } @@ -367,3 +367,12 @@ ; CHECK-NEXT: or i32 %X, %Y ; CHECK-NEXT: ret } + +define i32 @test35(i32 %a, i32 %b) { + %1 = or i32 %a, 1135 + %2 = or i32 %1, %b + ret i32 %2 + ; CHECK: @test35 + ; CHECK-NEXT: or i32 %a, %b + ; CHECK-NEXT: or i32 %1, 1135 +} Modified: llvm/trunk/test/Transforms/InstCombine/xor2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/xor2.ll?rev=113679&r1=113678&r2=113679&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/xor2.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/xor2.ll Sat Sep 11 00:48:06 2010 @@ -34,7 +34,7 @@ define i32 @test3(i32 %tmp1) { ; CHECK: @test3 ; CHECK-NEXT: and i32 %tmp1, 32 -; CHECK-NEXT: or i32 %tmp, 8 +; CHECK-NEXT: or i32 %ovm, 8 ; CHECK-NEXT: ret i32 %ovm = or i32 %tmp1, 145 %ov31 = and i32 %ovm, 177 From ggreif at gmail.com Sat Sep 11 02:49:06 2010 From: ggreif at gmail.com (Gabor Greif) Date: Sat, 11 Sep 2010 00:49:06 -0700 (PDT) Subject: [llvm-commits] [llvm] r113670 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/PeepholeOptimizer.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h In-Reply-To: <20100911001350.9B7AE2A6C12C@llvm.org> References: <20100911001350.9B7AE2A6C12C@llvm.org> Message-ID: <2da5ae35-a8e5-4373-8732-c9073b95b598@q2g2000vbk.googlegroups.com> Bill, you might be interested in my dabbling attempts with http://llvm.org/bugs/show_bug.cgi?id=8125 The x86 peephole already manages to eliminate the test after the 'and', It would be interesting to see whether ARM does too. Btw., my commit is not really restricted to 'and', any operation that sets the zero flag will do. A.t.m. (before your changes) I got: LBB0_1: @ %tailrecurse @ =>This Inner Loop Header: Depth=1 ldr lr, [r2, #-4] and r4, lr, #3 tst lr, #3 beq LBB0_4 from the transformed IR: ######################################### gabor at google7:~/llvm-build$ Debug+Asserts/bin/llc -print- after=codegenprepare -mtriple=arm-apple-darwin < /home/gabor/llvm/test/ CodeGen/X86/switch-and.ll .syntax unified *** IR Dump After Optimize for code generation *** %struct.Foo = type { i8* } define %struct.Foo* @_ZN3Foo7collectEj(%struct.Foo* %this, i32 %acc) nounwind readonly align 2 { entry: %scevgep = getelementptr %struct.Foo* %this, i32 1 ; <%struct.Foo*> [#uses=1] br label %tailrecurse tailrecurse: ; preds = %sw.bb, %entry %lsr.iv4 = phi %struct.Foo* [ %scevgep5, %sw.bb ], [ %scevgep, %entry ] ; <%struct.Foo*> [#uses=3] %lsr.iv = phi i64 [ %lsr.iv.next, %sw.bb ], [ 1, %entry ] ; [#uses=2] %acc.tr = phi i32 [ %or, %sw.bb ], [ %acc, %entry ] ; [#uses=2] %lsr.iv46 = bitcast %struct.Foo* %lsr.iv4 to i8** ; [#uses=1] %scevgep7 = getelementptr i8** %lsr.iv46, i32 -1 ; [#uses=1] %tmp2 = load i8** %scevgep7, align 8 ; [#uses=1] %0 = ptrtoint i8* %tmp2 to i64 ; [#uses=1] %and = and i64 %0, 3 ; [#uses=1] %conv = trunc i64 %and to i32 ; [#uses=3] %tst = icmp eq i32 %conv, 0 ; [#uses=1] br i1 %tst, label %sw.bb, label %tailrecurse.switch tailrecurse.switch: ; preds = %tailrecurse switch i32 %conv, label %sw.epilog [ i32 1, label %sw.bb i32 3, label %sw.bb6 i32 2, label %sw.bb8 ] sw.bb: ; preds = %tailrecurse.switch, %tailrecurse %shl = shl i32 %acc.tr, 1 ; [#uses=1] %or = or i32 %conv, %shl ; [#uses=1] %lsr.iv.next = add i64 %lsr.iv, 1 ; [#uses=1] %scevgep5 = getelementptr %struct.Foo* %lsr.iv4, i32 1 ; < %struct.Foo*> [#uses=1] br label %tailrecurse sw.bb6: ; preds = %tailrecurse.switch ret %struct.Foo* %lsr.iv4 sw.bb8: ; preds = %tailrecurse.switch %tmp1 = zext i32 %acc.tr to i64 ; [#uses=1] %tmp3 = add i64 %tmp1, %lsr.iv ; [#uses=1] %add.ptr11 = getelementptr inbounds %struct.Foo* %this, i64 %tmp3 ; < %struct.Foo*> [#uses=1] ret %struct.Foo* %add.ptr11 sw.epilog: ; preds = %tailrecurse.switch ret %struct.Foo* undef } ######################################### Cheers, Gabor On 11 Sep., 02:13, Bill Wendling wrote: > Author: void > Date: Fri Sep 10 19:13:50 2010 > New Revision: 113670 > > URL:http://llvm.org/viewvc/llvm-project?rev=113670&view=rev > Log: > Rename ConvertToSetZeroFlag to something more general. > > Modified: > ? ? llvm/trunk/include/llvm/Target/TargetInstrInfo.h > ? ? llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp > ? ? llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp > ? ? llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h > > Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h > URL:http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Ta... > =========================================================================== === > --- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original) > +++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Fri Sep 10 19:13:50 2010 > @@ -585,10 +585,11 @@ > ? ? ?return false; > ? ?} > > - ?/// ConvertToSetZeroFlag - Convert the instruction supplying the argument to > - ?/// the comparison into one that sets the zero bit in the flags > - ?/// register. Update the iterator *only* if a transformation took place. > - ?virtual bool ConvertToSetZeroFlag(MachineInstr * /*CmpInstr*/, > + ?/// OptimizeCompareInstr - See if the comparison instruction can be converted > + ?/// into something more efficient. E.g., on ARM most instructions can set the > + ?/// flags register, obviating the need for a separate CMP. Update the iterator > + ?/// *only* if a transformation took place. > + ?virtual bool OptimizeCompareInstr(MachineInstr * /*CmpInstr*/, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned /*SrcReg*/, int /*CmpValue*/, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?MachineBasicBlock::iterator &) const { > ? ? ?return false; > > Modified: llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp > URL:http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PeepholeOp... > =========================================================================== === > --- llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp (original) > +++ llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp Fri Sep 10 19:13:50 2010 > @@ -243,8 +243,8 @@ > ? ? ? ?TargetRegisterInfo::isPhysicalRegister(SrcReg)) > ? ? ?return false; > > - ?// Attempt to convert the defining instruction to set the "zero" flag. > - ?if (TII->ConvertToSetZeroFlag(MI, SrcReg, CmpValue, NextIter)) { > + ?// Attempt to optimize the comparison instruction. > + ?if (TII->OptimizeCompareInstr(MI, SrcReg, CmpValue, NextIter)) { > ? ? ?++NumEliminated; > ? ? ?return true; > ? ?} > > Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp > URL:http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBase... > =========================================================================== === > --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Fri Sep 10 19:13:50 2010 > @@ -1377,11 +1377,11 @@ > ? ?return false; > ?} > > -/// ConvertToSetZeroFlag - Convert the instruction supplying the argument to the > +/// OptimizeCompareInstr - Convert the instruction supplying the argument to the > ?/// comparison into one that sets the zero bit in the flags register. Update the > ?/// iterator *only* if a transformation took place. > ?bool ARMBaseInstrInfo:: > -ConvertToSetZeroFlag(MachineInstr *CmpInstr, unsigned SrcReg, int CmpValue, > +OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpValue, > ? ? ? ? ? ? ? ? ? ? ? MachineBasicBlock::iterator &MII) const { > ? ?if (CmpValue != 0) > ? ? ?return false; > > Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h > URL:http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBase... > =========================================================================== === > --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h (original) > +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Fri Sep 10 19:13:50 2010 > @@ -344,9 +344,9 @@ > ? ?virtual bool AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?int &CmpValue) const; > > - ?/// ConvertToSetZeroFlag - Convert the instruction to set the zero flag so > + ?/// OptimizeCompareInstr - Convert the instruction to set the zero flag so > ? ?/// that we can remove a "comparison with zero". > - ?virtual bool ConvertToSetZeroFlag(MachineInstr *CmpInstr, unsigned SrcReg, > + ?virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?int CmpValue, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?MachineBasicBlock::iterator &MII) const; > > _______________________________________________ > llvm-commits mailing list > llvm-comm... at cs.uiuc.eduhttp://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From ggreif at gmail.com Sat Sep 11 03:21:41 2010 From: ggreif at gmail.com (Gabor Greif) Date: Sat, 11 Sep 2010 01:21:41 -0700 (PDT) Subject: [llvm-commits] [llvm] r113670 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/PeepholeOptimizer.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h In-Reply-To: <2da5ae35-a8e5-4373-8732-c9073b95b598@q2g2000vbk.googlegroups.com> References: <20100911001350.9B7AE2A6C12C@llvm.org> <2da5ae35-a8e5-4373-8732-c9073b95b598@q2g2000vbk.googlegroups.com> Message-ID: <388c60a6-2720-4c4d-a898-925af5c1401f@q26g2000vbn.googlegroups.com> Ugh, added the 64-bit version, that won't help you on ARM :-( Here is 32-bit: ############################# ; *** IR Dump After Optimize for code generation *** %struct.Foo = type { i8* } define %struct.Foo* @_ZN3Foo7collectEj(%struct.Foo* %this, i32 %acc) nounwind readonly align 2 { entry: %scevgep = getelementptr %struct.Foo* %this, i32 1 ; <%struct.Foo*> [#uses=1] br label %tailrecurse tailrecurse: ; preds = %sw.bb, %entry %lsr.iv2 = phi %struct.Foo* [ %scevgep3, %sw.bb ], [ %scevgep, %entry ] ; <%struct.Foo*> [#uses=3] %lsr.iv = phi i32 [ %lsr.iv.next, %sw.bb ], [ 1, %entry ] ; [#uses=2] %acc.tr = phi i32 [ %or, %sw.bb ], [ %acc, %entry ] ; [#uses=2] %lsr.iv24 = bitcast %struct.Foo* %lsr.iv2 to i8** ; [#uses=1] %scevgep5 = getelementptr i8** %lsr.iv24, i32 -1 ; [#uses=1] %tmp2 = load i8** %scevgep5 ; [#uses=1] %0 = ptrtoint i8* %tmp2 to i32 ; [#uses=1] %and = and i32 %0, 3 ; [#uses=3] %tst = icmp eq i32 %and, 0 ; [#uses=1] br i1 %tst, label %sw.bb, label %tailrecurse.switch tailrecurse.switch: ; preds = %tailrecurse switch i32 %and, label %sw.epilog [ i32 1, label %sw.bb i32 3, label %sw.bb6 i32 2, label %sw.bb8 ] sw.bb: ; preds = %tailrecurse.switch, %tailrecurse %shl = shl i32 %acc.tr, 1 ; [#uses=1] %or = or i32 %and, %shl ; [#uses=1] %lsr.iv.next = add i32 %lsr.iv, 1 ; [#uses=1] %scevgep3 = getelementptr %struct.Foo* %lsr.iv2, i32 1 ; < %struct.Foo*> [#uses=1] br label %tailrecurse sw.bb6: ; preds = %tailrecurse.switch ret %struct.Foo* %lsr.iv2 sw.bb8: ; preds = %tailrecurse.switch %tmp1 = add i32 %acc.tr, %lsr.iv ; [#uses=1] %add.ptr11 = getelementptr inbounds %struct.Foo* %this, i32 %tmp1 ; < %struct.Foo*> [#uses=1] ret %struct.Foo* %add.ptr11 sw.epilog: ; preds = %tailrecurse.switch ret %struct.Foo* undef } ############################# On 11 Sep., 09:49, Gabor Greif wrote: > Bill, > > you might be interested in my dabbling attempts > withhttp://llvm.org/bugs/show_bug.cgi?id=8125 > The x86 peephole already manages to eliminate > the test after the 'and', It would be interesting > to see whether ARM does too. > Btw., my commit is not really restricted to 'and', > any operation that sets the zero flag will do. > From ggreif at gmail.com Sat Sep 11 07:43:13 2010 From: ggreif at gmail.com (Gabor Greif) Date: Sat, 11 Sep 2010 05:43:13 -0700 (PDT) Subject: [llvm-commits] [llvm] r113670 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/PeepholeOptimizer.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h In-Reply-To: <20100911001350.9B7AE2A6C12C@llvm.org> References: <20100911001350.9B7AE2A6C12C@llvm.org> Message-ID: <39c53e0a-1bff-4c04-96d8-5f68bb0a7ed8@l17g2000vbf.googlegroups.com> Bill, I tried to extend your approach to TSTri (as an eliminable compare instr.) and ANDri (as an implicit compare) with this patch: gabor at google8:~/llvm-build$ svn diff /home/gabor/llvm/lib/Target/ARM/ ARMBaseInstrInfo.cpp Index: /home/gabor/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp =================================================================== --- /home/gabor/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp (revision 113683) +++ /home/gabor/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp (working copy) @@ -1372,6 +1372,10 @@ SrcReg = MI->getOperand(0).getReg(); CmpValue = MI->getOperand(1).getImm(); return true; + case ARM::TSTri: + SrcReg = MI->getOperand(0).getReg(); + CmpValue = 0; + return true; } return false; @@ -1421,6 +1425,7 @@ switch (MI->getOpcode()) { default: break; case ARM::ADDri: + case ARM::ANDri: case ARM::SUBri: case ARM::t2ADDri: case ARM::t2SUBri: gabor at google8:~/llvm-build$ BUT, it does not trigger on my example, because of something that appears to be a bug: %reg16388 = PHI %reg16396, , %reg16392, ; GPR: %reg16388,16396,16392 %reg16389 = PHI %reg16385, , %reg16391, ; GPR: %reg16389,16385,16391 %reg16397 = LDR %reg16387, %reg0, 4100, pred:14, pred: %reg0; mem:LD4[%scevgep1] GPR:%reg16397,16387 %reg16390 = ANDri %reg16397, 3, pred:14, pred:%reg0, opt: %reg0; GPR:%reg16390,16397 TSTri %reg16397, 3, pred:14, pred:%reg0, %CPSR; GPR: %reg16397 Bcc , pred:0, pred:%CPSR The TST seems to use the result of the LDR instead of that of the AND! Very fishy... The bitcode is ok: %tmp2 = load i8** %scevgep1 %0 = ptrtoint i8* %tmp2 to i32 %and = and i32 %0, 3 %tst = icmp eq i32 %and, 0 br i1 %tst, label %sw.bb, label %tailrecurse.switch What do you think? Okay to commit the above? Cheers, Gabor On 11 Sep., 02:13, Bill Wendling wrote: > Author: void > Date: Fri Sep 10 19:13:50 2010 > New Revision: 113670 From ofv at wanadoo.es Sat Sep 11 08:49:24 2010 From: ofv at wanadoo.es (=?utf-8?Q?=C3=93scar_Fuentes?=) Date: Sat, 11 Sep 2010 15:49:24 +0200 Subject: [llvm-commits] [llvm] r113632 - in /llvm/trunk: ./ cmake/modules/ examples/BrainF/ examples/ExceptionDemo/ examples/Fibonacci/ examples/HowToUseJIT/ examples/Kaleidoscope/Chapter3/ examples/Kaleidoscope/Chapter4/ examples/Kaleidoscope/Chapter5/ examples/Kaleidoscope/Chapter6/ examples/Kaleidoscope/Chapter7/ examples/ModuleMaker/ examples/ParallelJIT/ lib/Analysis/ lib/Analysis/IPA/ lib/Archive/ lib/AsmParser/ lib/Bitcode/Reader/ lib/CodeGen/ lib/CodeGen/AsmPrinter/ lib/CodeGen/SelectionDAG/ lib/CompilerDriver/ lib/Exec... References: <20100910211425.C5FE82A6C12C@llvm.org> Message-ID: <874odwe6fv.fsf@telefonica.net> "Michael J. Spencer" writes: > URL: http://llvm.org/viewvc/llvm-project?rev=113632&view=rev > Log: > CMake: Get rid of LLVMLibDeps.cmake and export the libraries normally. Who approved this change? [snip] From bigcheesegs at gmail.com Sat Sep 11 10:03:26 2010 From: bigcheesegs at gmail.com (Michael Spencer) Date: Sat, 11 Sep 2010 11:03:26 -0400 Subject: [llvm-commits] [llvm] r113632 - in /llvm/trunk: ./ cmake/modules/ examples/BrainF/ examples/ExceptionDemo/ examples/Fibonacci/ examples/HowToUseJIT/ examples/Kaleidoscope/Chapter3/ examples/Kaleidoscope/Chapter4/ examples/Kaleidoscope/Chapter5/ e Message-ID: On Sat, Sep 11, 2010 at 9:49 AM, ?scar Fuentes wrote: > "Michael J. Spencer" > writes: > >> URL: http://llvm.org/viewvc/llvm-project?rev=113632&view=rev >> Log: >> CMake: Get rid of LLVMLibDeps.cmake and export the libraries normally. > > Who approved this change? Douglas Gregor. - Michael Spencer From rafael.espindola at gmail.com Sat Sep 11 10:25:59 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Sat, 11 Sep 2010 15:25:59 -0000 Subject: [llvm-commits] [llvm] r113685 - in /llvm/trunk/test: MC/MachO/ Scripts/ Message-ID: <20100911152559.51B2A2A6C12C@llvm.org> Author: rafael Date: Sat Sep 11 10:25:58 2010 New Revision: 113685 URL: http://llvm.org/viewvc/llvm-project?rev=113685&view=rev Log: Change section_data dumping to print hex numbers instead of using python's %r. Added: llvm/trunk/test/Scripts/common_dump.py Modified: llvm/trunk/test/MC/MachO/absolutize.s llvm/trunk/test/MC/MachO/darwin-x86_64-reloc-offsets.s llvm/trunk/test/MC/MachO/darwin-x86_64-reloc.s llvm/trunk/test/MC/MachO/direction_labels.s llvm/trunk/test/MC/MachO/indirect-symbols.s llvm/trunk/test/MC/MachO/jcc.s llvm/trunk/test/MC/MachO/relax-jumps.s llvm/trunk/test/MC/MachO/reloc-pcrel-offset.s llvm/trunk/test/MC/MachO/reloc.s llvm/trunk/test/MC/MachO/string-table.s llvm/trunk/test/MC/MachO/tbss.s llvm/trunk/test/MC/MachO/tdata.s llvm/trunk/test/MC/MachO/thread_init_func.s llvm/trunk/test/MC/MachO/tls.s llvm/trunk/test/MC/MachO/tlv-reloc.s llvm/trunk/test/MC/MachO/tlv.s llvm/trunk/test/MC/MachO/x86_32-optimal_nop.s llvm/trunk/test/MC/MachO/zerofill-5.s llvm/trunk/test/Scripts/elf-dump llvm/trunk/test/Scripts/macho-dump Modified: llvm/trunk/test/MC/MachO/absolutize.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/absolutize.s?rev=113685&r1=113684&r2=113685&view=diff ============================================================================== --- llvm/trunk/test/MC/MachO/absolutize.s (original) +++ llvm/trunk/test/MC/MachO/absolutize.s Sat Sep 11 10:25:58 2010 @@ -103,7 +103,7 @@ // CHECK: (('word-0', 0xa1000000), // CHECK: ('word-1', 0x2)), // CHECK: ]) -// CHECK: ('_section_data', '1\xc01\xc01\xc01\xc0\xb8\xfe\xff\xff\xff\xb8\xfe\xff\xff\xff\xb8\x02\x00\x00\x00\xb8\x02\x00\x00\x00\xb8\x02\x00\x00\x00\xb8\x02\x00\x00\x00\xb8\xfe\xff\xff\xff') +// CHECK: ('_section_data', '31c031c0 31c031c0 b8feffff ffb8feff ffffb802 000000b8 02000000 b8020000 00b80200 0000b8fe ffffff') // CHECK: # Section 1 // CHECK: (('section_name', '__data\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') // CHECK: ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') @@ -140,7 +140,7 @@ // CHECK: (('word-0', 0xa1000000), // CHECK: ('word-1', 0x2f)), // CHECK: ]) -// CHECK: ('_section_data', "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\xfc\xff\xff\xff\xfc\xff\xff\xff\x04\x00\x00\x00\x04\x00\x00\x00\x04\x00\x00\x00\x04\x00\x00\x00'\x00\x00\x00") +// CHECK: ('_section_data', '00000000 00000000 00000000 00000000 fcffffff fcffffff 04000000 04000000 04000000 04000000 27000000') // CHECK: ]) // CHECK: ), // CHECK: # Load Command 1 Modified: llvm/trunk/test/MC/MachO/darwin-x86_64-reloc-offsets.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/darwin-x86_64-reloc-offsets.s?rev=113685&r1=113684&r2=113685&view=diff ============================================================================== --- llvm/trunk/test/MC/MachO/darwin-x86_64-reloc-offsets.s (original) +++ llvm/trunk/test/MC/MachO/darwin-x86_64-reloc-offsets.s Sat Sep 11 10:25:58 2010 @@ -277,7 +277,7 @@ // CHECK: (('word-0', 0x2), // CHECK: ('word-1', 0x6d000000)), // CHECK: ]) -// CHECK: ('_section_data', '\xc6\x05\xff\xff\xff\xff\x12\xc6\x05\x00\x00\x00\x00\x12\xc7\x05\xfc\xff\xff\xffxV4\x12\xc7\x05\xfd\xff\xff\xffxV4\x12\xc7\x05\xfe\xff\xff\xffxV4\x12\xc7\x05\xff\xff\xff\xffxV4\x12\xc7\x05\x00\x00\x00\x00xV4\x12\x88\x05\x00\x00\x00\x00\x88\x05\x01\x00\x00\x00\x89\x05\x00\x00\x00\x00\x89\x05\x01\x00\x00\x00\x89\x05\x02\x00\x00\x00\x89\x05\x03\x00\x00\x00\x89\x05\x04\x00\x00\x00\xc6\x05\xdd\x00\x00\x00\x12\xc6\x05\xd7\x00\x00\x00\x12\xc7\x05\xcc\x00\x00\x00xV4\x12\xc7\x05\xc3\x00\x00\x00xV4\x12\xc7\x05\xba\x00\x00\x00xV4\x12\xc7\x05\xb1\x00\x00\x00xV4\x12\xc7\x05\xa8\x00\x00\x00xV4\x12\x88\x05\x9e\x00\x00\x00\x88\x05\x99\x00\x00\x00\x89\x05\x92\x00\x00\x00\x89\x05\x8d\x00\x00\x00\x89\x05\x88\x00\x00\x00\x89\x05\x83\x00\x00\x00\x89\x05~\x00\x00\x00\xc6\x05\x03\x00\x00\x00\x12\xc6\x05\x04\x00\x00\x00\x12\xc7\x05\x00\x00\x00\x00xV4\x12\xc7\x05\x01\x00\x00\x00xV4\x12\xc7\x05\x02\x00\x00\x00xV4\x12\xc7\x05\x03\x00\x00\x00xV4\x12\xc7\x05\x04\x00\x00\x0 0xV4\x12\x88\x05\x04\x00\x00\x00\x88\x05\x05\x00\x00\x00\x89\x05\x04\x00\x00\x00\x89\x05\x05\x00\x00\x00\x89\x05\x06\x00\x00\x00\x89\x05\x07\x00\x00\x00\x89\x05\x08\x00\x00\x00') +// CHECK: ('_section_data', 'c605ffff ffff12c6 05000000 0012c705 fcffffff 78563412 c705fdff ffff7856 3412c705 feffffff 78563412 c705ffff ffff7856 3412c705 00000000 78563412 88050000 00008805 01000000 89050000 00008905 01000000 89050200 00008905 03000000 89050400 0000c605 dd000000 12c605d7 00000012 c705cc00 00007856 3412c705 c3000000 78563412 c705ba00 00007856 3412c705 b1000000 78563412 c705a800 00007856 34128805 9e000000 88059900 00008905 92000000 89058d00 00008905 88000000 89058300 00008905 7e000000 c6050300 000012c6 05040000 0012c705 00000000 78563412 c7050100 00007856 3412c705 02000000 78563412 c7050300 00007856 3412c705 04000000 78563412 88050400 00008805 05000000 89050400 00008905 05000000 89050600 00008905 07000000 89050800 0000') // CHECK: # Section 1 // CHECK: (('section_name', '__data\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') // CHECK: ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') @@ -294,7 +294,7 @@ // CHECK: ), // CHECK: ('_relocations', [ // CHECK: ]) -// CHECK: ('_section_data', '\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('_section_data', '00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000') // CHECK: ]) // CHECK: ), // CHECK: # Load Command 1 Modified: llvm/trunk/test/MC/MachO/darwin-x86_64-reloc.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/darwin-x86_64-reloc.s?rev=113685&r1=113684&r2=113685&view=diff ============================================================================== --- llvm/trunk/test/MC/MachO/darwin-x86_64-reloc.s (original) +++ llvm/trunk/test/MC/MachO/darwin-x86_64-reloc.s Sat Sep 11 10:25:58 2010 @@ -139,7 +139,7 @@ // CHECK: (('word-0', 0x4), // CHECK: ('word-1', 0x4d000008)), // CHECK: ]) -// CHECK: ('_section_data', '\x00\x00\x00\x00\x04\x00\x00\x00\x04\x00\x00\x00\x00\x00\x00\x00\x1f\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00/\x01\x00\x00\x00\x00\x00\x00') +// CHECK: ('_section_data', '00000000 04000000 04000000 00000000 1f010000 00000000 00000000 00000000 2f010000 00000000') // CHECK: # Section 1 // CHECK: (('section_name', '__text\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') // CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') @@ -252,7 +252,7 @@ // CHECK: (('word-0', 0x2), // CHECK: ('word-1', 0x2d000000)), // CHECK: ]) -// CHECK: ('_section_data', '\xc3\xe8\x00\x00\x00\x00\xe8\x04\x00\x00\x00H\x8b\x05\x00\x00\x00\x00\xff5\x00\x00\x00\x00\x8b\x05\x00\x00\x00\x00\x8b\x05\x04\x00\x00\x00\xc6\x05\xff\xff\xff\xff\x12\xc7\x05\xfc\xff\xff\xffxV4\x12\x00\x00\x00\x00\x00\x00\x00\x00\x04\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x04\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00H\x8d\x05,\x00\x00\x00H\x8d\x05\x14\x00\x00\x00\x83\x05\x13\x00\x00\x00\x06f\x81\x05\x12\x00\x00\x00\xf4\x01\x81\x05\x10\x00\x00\x00\xf4\x01\x00\x00\x90\x90\x90\x90\x90\x90\x90\x90\x90\x90\x90\x90,\x00\x00\x00\x00\x00\x00\x00\x14\x00\x00\x00\x00\x00\x00\x00\xe4\xff\xff\xff\xff\xff\xff\xff\xd4\xff\xff\xff\xff\xff\xff\xff,\x00\x00\x00\x00\x00\x00\x00\x83\xc0\x00\x03\x04%\x03\x00\x00\x00\x8b\x05\x1f\xff\xff\xff\x8b\x05,\x00\x00\x00\x8b\x05\x00\x00\x00\x00\x8b\x050\x00\x00\x00H\x83=\xff\xff\xff\xff\x00') +// CHECK: ('_section_data', 'c3e80000 0000e804 00000048 8b050000 0000ff35 00000000 8b050000 00008b05 04000000 c605ffff ffff12c7 05fcffff ff785634 12000000 00000000 00040000 00000000 00000000 00000000 00040000 00000000 00000000 00488d05 2c000000 488d0514 00000083 05130000 00066681 05120000 00f40181 05100000 00f40100 00909090 90909090 90909090 902c0000 00000000 00140000 00000000 00e4ffff ffffffff ffd4ffff ffffffff ff2c0000 00000000 0083c000 03042503 0000008b 051fffff ff8b052c 0000008b 05000000 008b0530 00000048 833dffff ffff00') // CHECK: # Section 2 // CHECK: (('section_name', '__debug_frame\x00\x00\x00') // CHECK: ('segment_name', '__DWARF\x00\x00\x00\x00\x00\x00\x00\x00\x00') @@ -275,7 +275,7 @@ // CHECK: (('word-0', 0x0), // CHECK: ('word-1', 0x6000002)), // CHECK: ]) -// CHECK: ('_section_data', '\xd5\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('_section_data', 'd5000000 00000000 00000000 00000000') // CHECK: # Section 3 // CHECK: (('section_name', '__literal8\x00\x00\x00\x00\x00\x00') // CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') @@ -292,7 +292,7 @@ // CHECK: ), // CHECK: ('_relocations', [ // CHECK: ]) -// CHECK: ('_section_data', '\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('_section_data', '00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000') // CHECK: ]) // CHECK: ), // CHECK: # Load Command 1 Modified: llvm/trunk/test/MC/MachO/direction_labels.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/direction_labels.s?rev=113685&r1=113684&r2=113685&view=diff ============================================================================== --- llvm/trunk/test/MC/MachO/direction_labels.s (original) +++ llvm/trunk/test/MC/MachO/direction_labels.s Sat Sep 11 10:25:58 2010 @@ -46,7 +46,7 @@ // CHECK: ), // CHECK: ('_relocations', [ // CHECK: ]) -// CHECK: ('_section_data', '\x90\xeb\xfd\x90u\x00\x90u\xfd\xeb\x00\x90\xc3') +// CHECK: ('_section_data', '90ebfd90 75009075 fdeb0090 c3') // CHECK: ]) // CHECK: ), // CHECK: # Load Command 1 Modified: llvm/trunk/test/MC/MachO/indirect-symbols.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/indirect-symbols.s?rev=113685&r1=113684&r2=113685&view=diff ============================================================================== --- llvm/trunk/test/MC/MachO/indirect-symbols.s (original) +++ llvm/trunk/test/MC/MachO/indirect-symbols.s Sat Sep 11 10:25:58 2010 @@ -71,7 +71,7 @@ // CHECK: ), // CHECK: ('_relocations', [ // CHECK: ]) -// CHECK: ('_section_data', '\xf4\xf4\xf4\xf4\xf4\xf4\xf4\xf4\xf4\xf4\xf4\xf4\xf4\xf4\xf4') +// CHECK: ('_section_data', 'f4f4f4f4 f4f4f4f4 f4f4f4f4 f4f4f4') // CHECK: # Section 2 // CHECK: (('section_name', '__pointers\x00\x00\x00\x00\x00\x00') // CHECK: ('segment_name', '__IMPORT\x00\x00\x00\x00\x00\x00\x00\x00') @@ -87,7 +87,7 @@ // CHECK: ), // CHECK: ('_relocations', [ // CHECK: ]) -// CHECK: ('_section_data', '\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('_section_data', '00000000 00000000 00000000') // CHECK: ]) // CHECK: ), // CHECK: # Load Command 1 Modified: llvm/trunk/test/MC/MachO/jcc.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/jcc.s?rev=113685&r1=113684&r2=113685&view=diff ============================================================================== --- llvm/trunk/test/MC/MachO/jcc.s (original) +++ llvm/trunk/test/MC/MachO/jcc.s Sat Sep 11 10:25:58 2010 @@ -100,7 +100,7 @@ // CHECK: ), // CHECK: ('_relocations', [ // CHECK: ]) -// CHECK: ('_section_data', 'w\x00\x90s\x00\x90r\x00\x90v\x00\x90r\x00\x90\xe3\x00\x90\xe3\x00\x90t\x00\x90\x7f\x00\x90}\x00\x90|\x00\x90~\x00\x90v\x00\x90r\x00\x90s\x00\x90w\x00\x90s\x00\x90u\x00\x90~\x00\x90|\x00\x90}\x00\x90\x7f\x00\x90q\x00\x90{\x00\x90y\x00\x90u\x00\x90p\x00\x90z\x00\x90z\x00\x90{\x00\x90x\x00\x90t\x00\x90') +// CHECK: ('_section_data', '77009073 00907200 90760090 720090e3 0090e300 90740090 7f00907d 00907c00 907e0090 76009072 00907300 90770090 73009075 00907e00 907c0090 7d00907f 00907100 907b0090 79009075 00907000 907a0090 7a00907b 00907800 90740090') // CHECK: ]) // CHECK: ), // CHECK: ]) Modified: llvm/trunk/test/MC/MachO/relax-jumps.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/relax-jumps.s?rev=113685&r1=113684&r2=113685&view=diff ============================================================================== --- llvm/trunk/test/MC/MachO/relax-jumps.s (original) +++ llvm/trunk/test/MC/MachO/relax-jumps.s Sat Sep 11 10:25:58 2010 @@ -10,9 +10,9 @@ // diff $f.{as,mc}.dump) // to examine the results in a more sensible fashion. -// CHECK: ('_section_data', '\x90 -// CHECK: \x0f\x842\xff\xff\xff\x0f\x82\xe6\x00\x00\x00\x0f\x87&\xff\xff\xff\x0f\x8f\xda\x00\x00\x00\x0f\x88\x1a\xff\xff\xff\x0f\x83\xce\x00\x00\x00\x0f\x89\x0e\xff\xff\xff\x90 -// CHECK: \x901\xc0') +// CHECK: ('_section_data', '90 +// CHECK: 0f8432ff ffff0f82 e6000000 0f8726ff ffff0f8f da000000 0f881aff ffff0f83 ce000000 0f890eff ffff90 +// CHECK: 9031c0') L1: .space 200, 0x90 Modified: llvm/trunk/test/MC/MachO/reloc-pcrel-offset.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/reloc-pcrel-offset.s?rev=113685&r1=113684&r2=113685&view=diff ============================================================================== --- llvm/trunk/test/MC/MachO/reloc-pcrel-offset.s (original) +++ llvm/trunk/test/MC/MachO/reloc-pcrel-offset.s Sat Sep 11 10:25:58 2010 @@ -4,7 +4,7 @@ // CHECK: (('word-0', 0x1), // CHECK: ('word-1', 0x5000002)), // CHECK-NEXT: ]) -// CHECK: ('_section_data', '\xe8\xfb\xff\xff\xff') +// CHECK: ('_section_data', 'e8fbffff ff') .data .long 0 Modified: llvm/trunk/test/MC/MachO/reloc.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/reloc.s?rev=113685&r1=113684&r2=113685&view=diff ============================================================================== --- llvm/trunk/test/MC/MachO/reloc.s (original) +++ llvm/trunk/test/MC/MachO/reloc.s Sat Sep 11 10:25:58 2010 @@ -90,7 +90,7 @@ // CHECK: (('word-0', 0x1), // CHECK: ('word-1', 0x5000003)), // CHECK: ]) -// CHECK: ('_section_data', '\xe9:\x00\x00\x00\xeb\xf9\xc3') +// CHECK: ('_section_data', 'e93a0000 00ebf9c3') // CHECK: # Section 1 // CHECK: (('section_name', '__data\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') // CHECK: ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') @@ -139,7 +139,7 @@ // CHECK: (('word-0', 0x0), // CHECK: ('word-1', 0xc000009)), // CHECK: ]) -// CHECK: ('_section_data', '\x00\x00\x00\x00\x04\x00\x00\x00\x10\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\xed\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x19\x00\x00\x00"\x00\x00\x00,\x00q\x00\x00\x00\x00\x04\x00\x00\x00') +// CHECK: ('_section_data', '00000000 04000000 10000000 00000000 00000000 ed000000 00000000 00000000 19000000 22000000 2c007100 00000004 000000') // CHECK: # Section 2 // CHECK: (('section_name', '__const\x00\x00\x00\x00\x00\x00\x00\x00\x00') // CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') @@ -167,7 +167,7 @@ // CHECK: (('word-0', 0xa1000000), // CHECK: ('word-1', 0x3b)), // CHECK: ]) -// CHECK: ('_section_data', '\xfe\xff\xff\xff?\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('_section_data', 'feffffff 3f000000 00000000') // CHECK: ]) // CHECK: ), // CHECK: # Load Command 1 Modified: llvm/trunk/test/MC/MachO/string-table.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/string-table.s?rev=113685&r1=113684&r2=113685&view=diff ============================================================================== --- llvm/trunk/test/MC/MachO/string-table.s (original) +++ llvm/trunk/test/MC/MachO/string-table.s Sat Sep 11 10:25:58 2010 @@ -43,7 +43,7 @@ // CHECK: (('word-0', 0x2), // CHECK: ('word-1', 0xc000001)), // CHECK: ]) -// CHECK: ('_section_data', '\xc7\x05\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('_section_data', 'c7050000 00000000 0000') // CHECK: ]) // CHECK: ), // CHECK: # Load Command 1 Modified: llvm/trunk/test/MC/MachO/tbss.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/tbss.s?rev=113685&r1=113684&r2=113685&view=diff ============================================================================== --- llvm/trunk/test/MC/MachO/tbss.s (original) +++ llvm/trunk/test/MC/MachO/tbss.s Sat Sep 11 10:25:58 2010 @@ -57,7 +57,7 @@ // CHECK: ), // CHECK: ('_relocations', [ // CHECK: ]) -// CHECK: ('_section_data', '\xcf\xfa\xed\xfe\x07\x00\x00\x01\x03\x00\x00\x00') +// CHECK: ('_section_data', 'cffaedfe 07000001 03000000') // CHECK: ]) // CHECK: ), // CHECK: # Load Command 1 Modified: llvm/trunk/test/MC/MachO/tdata.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/tdata.s?rev=113685&r1=113684&r2=113685&view=diff ============================================================================== --- llvm/trunk/test/MC/MachO/tdata.s (original) +++ llvm/trunk/test/MC/MachO/tdata.s Sat Sep 11 10:25:58 2010 @@ -57,7 +57,7 @@ // CHECK: ), // CHECK: ('_relocations', [ // CHECK: ]) -// CHECK: ('_section_data', '\x04\x00\x00\x00') +// CHECK: ('_section_data', '04000000') // CHECK: ]) // CHECK: ), // CHECK: # Load Command 1 Modified: llvm/trunk/test/MC/MachO/thread_init_func.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/thread_init_func.s?rev=113685&r1=113684&r2=113685&view=diff ============================================================================== --- llvm/trunk/test/MC/MachO/thread_init_func.s (original) +++ llvm/trunk/test/MC/MachO/thread_init_func.s Sat Sep 11 10:25:58 2010 @@ -57,7 +57,7 @@ // CHECK: ), // CHECK: ('_relocations', [ // CHECK: ]) -// CHECK: ('_section_data', '\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('_section_data', '00000000 00000000') // CHECK: ]) // CHECK: ), // CHECK: ]) Modified: llvm/trunk/test/MC/MachO/tls.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/tls.s?rev=113685&r1=113684&r2=113685&view=diff ============================================================================== --- llvm/trunk/test/MC/MachO/tls.s (original) +++ llvm/trunk/test/MC/MachO/tls.s Sat Sep 11 10:25:58 2010 @@ -99,7 +99,7 @@ // CHECK: ), // CHECK: ('_relocations', [ // CHECK: ]) -// CHECK: ('_section_data', '\x04\x00\x00\x00\x05\x00\x00\x00') +// CHECK: ('_section_data', '04000000 05000000') // CHECK: # Section 2 // CHECK: (('section_name', '__thread_vars\x00\x00\x00') // CHECK: ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') @@ -140,7 +140,7 @@ // CHECK: (('word-0', 0x0), // CHECK: ('word-1', 0xe000008)), // CHECK: ]) -// CHECK: ('_section_data', '\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('_section_data', '00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000') // CHECK: # Section 3 // CHECK: (('section_name', '__thread_bss\x00\x00\x00\x00') // CHECK: ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') @@ -157,7 +157,7 @@ // CHECK: ), // CHECK: ('_relocations', [ // CHECK: ]) -// CHECK: ('_section_data', '\xcf\xfa\xed\xfe\x07\x00\x00\x01') +// CHECK: ('_section_data', 'cffaedfe 07000001') // CHECK: ]) // CHECK: ), // CHECK: # Load Command 1 Modified: llvm/trunk/test/MC/MachO/tlv-reloc.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/tlv-reloc.s?rev=113685&r1=113684&r2=113685&view=diff ============================================================================== --- llvm/trunk/test/MC/MachO/tlv-reloc.s (original) +++ llvm/trunk/test/MC/MachO/tlv-reloc.s Sat Sep 11 10:25:58 2010 @@ -61,7 +61,7 @@ // CHECK: (('word-0', 0x3), // CHECK: ('word-1', 0x9d000001)), // CHECK: ]) -// CHECK: ('_section_data', 'H\x8b=\x00\x00\x00\x00\xff\x17\xc3') +// CHECK: ('_section_data', '488b3d00 000000ff 17c3') // CHECK: # Section 1 // CHECK: (('section_name', '__thread_data\x00\x00\x00') // CHECK: ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') @@ -78,7 +78,7 @@ // CHECK: ), // CHECK: ('_relocations', [ // CHECK: ]) -// CHECK: ('_section_data', '\x04\x00\x00\x00') +// CHECK: ('_section_data', '04000000') // CHECK: # Section 2 // CHECK: (('section_name', '__thread_vars\x00\x00\x00') // CHECK: ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') @@ -101,7 +101,7 @@ // CHECK: (('word-0', 0x0), // CHECK: ('word-1', 0xe000003)), // CHECK: ]) -// CHECK: ('_section_data', '\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('_section_data', '00000000 00000000 00000000 00000000 00000000 00000000') // CHECK: ]) // CHECK: ), // CHECK: # Load Command 1 Modified: llvm/trunk/test/MC/MachO/tlv.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/tlv.s?rev=113685&r1=113684&r2=113685&view=diff ============================================================================== --- llvm/trunk/test/MC/MachO/tlv.s (original) +++ llvm/trunk/test/MC/MachO/tlv.s Sat Sep 11 10:25:58 2010 @@ -61,7 +61,7 @@ // CHECK: ), // CHECK: ('_relocations', [ // CHECK: ]) -// CHECK: ('_section_data', '\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK: ('_section_data', '00000000 00000000 00000000 00000000 00000000 00000000') // CHECK: ]) // CHECK: ), // CHECK: # Load Command 1 Modified: llvm/trunk/test/MC/MachO/x86_32-optimal_nop.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/x86_32-optimal_nop.s?rev=113685&r1=113684&r2=113685&view=diff ============================================================================== --- llvm/trunk/test/MC/MachO/x86_32-optimal_nop.s (original) +++ llvm/trunk/test/MC/MachO/x86_32-optimal_nop.s Sat Sep 11 10:25:58 2010 @@ -192,7 +192,7 @@ // CHECK: ), // CHECK: ('_relocations', [ // CHECK: ]) -// CHECK: ('_section_data', '\xc3\x90\xc3\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\xc3\xc3f\x90\xc3\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\xc3\x0f\x1f\x00\xc3\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\xc3\xc3\xc3\xc3\x0f\x1f@\x00\xc3\x00\x00\x00\x00\x00\x00\x00\xc3\xc3\xc3\x0f\x1fD\x00\x00\xc3\x00\x00\x00\x00\x00\x00\x00\xc3\xc3f\x0f\x1fD\x00\x00\xc3\x00\x00\x00\x00\x00\x00\x00\xc3\x0f\x1f\x80\x00\x00\x00\x00\xc3\x00\x00\x00\x00\x00\x00\x00\xc3\xc3\xc3\xc3\xc3\xc3\xc3\xc3\xc3\x00\x00\x00\x00\x00\x00\x00\xc3\xc3\xc3\xc3\xc3\xc3\xc3f\x0f\x1f\x84\x00\x00\x00\x00\x00\xc3\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\xc3\xc3\xc3\xc3\xc3\xc3\xc3f\x0f\x1f\x84\x00\x00\x00\x00\x00\xc3\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\xc3\xc3\xc3\xc3\xc3\x0f\x1fD\x00\x00f\x0f\x1fD\x00\x00\xc3\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\xc3\xc3\xc3\xc3f\x0f\x1fD\x00\x00f\x0f\x1fD\x00\x00\xc3\x00\x00\x00\x00\x00\x00\x00\x00\x00 \x00\x00\x00\x00\x00\x00\xc3\xc3\xc3f\x0f\x1fD\x00\x00\x0f\x1f\x80\x00\x00\x00\x00\xc3\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\xc3\xc3\x0f\x1f\x80\x00\x00\x00\x00\x0f\x1f\x80\x00\x00\x00\x00\xc3\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\xc3\x0f\x1f\x80\x00\x00\x00\x00\x0f\x1f\x84\x00\x00\x00\x00\x00\xc3') +// CHECK: ('_section_data', 'c390c300 00000000 00000000 00000000 c3c36690 c3000000 00000000 00000000 c30f1f00 c3000000 00000000 00000000 c3c3c3c3 0f1f4000 c3000000 00000000 c3c3c30f 1f440000 c3000000 00000000 c3c3660f 1f440000 c3000000 00000000 c30f1f80 00000000 c3000000 00000000 c3c3c3c3 c3c3c3c3 c3000000 00000000 c3c3c3c3 c3c3c366 0f1f8400 00000000 c3000000 00000000 00000000 00000000 c3c3c3c3 c3c3c366 0f1f8400 00000000 c3000000 00000000 00000000 00000000 c3c3c3c3 c30f1f44 0000660f 1f440000 c3000000 00000000 00000000 00000000 c3c3c3c3 660f1f44 0000660f 1f440000 c3000000 00000000 00000000 00000000 c3c3c366 0f1f4400 000f1f80 00000000 c3000000 00000000 00000000 00000000 c3c30f1f 80000000 000f1f80 00000000 c3000000 00000000 00000000 00000000 c30f1f80 00000000 0f1f8400 00000000 c3') // CHECK: # Section 1 // CHECK: (('section_name', '__const\x00\x00\x00\x00\x00\x00\x00\x00\x00') // CHECK: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') @@ -208,7 +208,7 @@ // CHECK: ), // CHECK: ('_relocations', [ // CHECK: ]) -// CHECK: ('_section_data', '\x00\x90\x90\x90\x90\x90\x90\x90\x90\x90\x90\x90\x90\x90\x90\x90\x00\x00\x00\x00') +// CHECK: ('_section_data', '00909090 90909090 90909090 90909090 00000000') // CHECK: ]) // CHECK: ), // CHECK: # Load Command 1 Modified: llvm/trunk/test/MC/MachO/zerofill-5.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/zerofill-5.s?rev=113685&r1=113684&r2=113685&view=diff ============================================================================== --- llvm/trunk/test/MC/MachO/zerofill-5.s (original) +++ llvm/trunk/test/MC/MachO/zerofill-5.s Sat Sep 11 10:25:58 2010 @@ -43,7 +43,7 @@ // CHECK: ), // CHECK: ('_relocations', [ // CHECK: ]) -// CHECK: ('_section_data', '\x02\x00\x00\x00') +// CHECK: ('_section_data', '02000000') // CHECK: # Section 1 // CHECK: (('section_name', '__bss\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') // CHECK: ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') @@ -60,7 +60,7 @@ // CHECK: ), // CHECK: ('_relocations', [ // CHECK: ]) -// CHECK: ('_section_data', '\xcf\xfa\xed\xfe\x07\x00\x00\x01') +// CHECK: ('_section_data', 'cffaedfe 07000001') // CHECK: ]) // CHECK: ), // CHECK: # Load Command 1 Added: llvm/trunk/test/Scripts/common_dump.py URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Scripts/common_dump.py?rev=113685&view=auto ============================================================================== --- llvm/trunk/test/Scripts/common_dump.py (added) +++ llvm/trunk/test/Scripts/common_dump.py Sat Sep 11 10:25:58 2010 @@ -0,0 +1,13 @@ +def dataToHex(d): + """ Convert the raw data in 'd' to an hex string with a space every 4 bytes. + """ + bytes = [] + for i,c in enumerate(d): + byte = ord(c) + hex_byte = hex(byte)[2:] + if byte <= 0xf: + hex_byte = '0' + hex_byte + if i % 4 == 3: + hex_byte += ' ' + bytes.append(hex_byte) + return ''.join(bytes).strip() Modified: llvm/trunk/test/Scripts/elf-dump URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Scripts/elf-dump?rev=113685&r1=113684&r2=113685&view=diff ============================================================================== --- llvm/trunk/test/Scripts/elf-dump (original) +++ llvm/trunk/test/Scripts/elf-dump Sat Sep 11 10:25:58 2010 @@ -4,6 +4,8 @@ import sys import StringIO +import common_dump + class Reader: def __init__(self, path): if path == "-": @@ -95,7 +97,8 @@ print " ])" elif dumpdata: f.seek(self.sh_offset) - print " ('_section_data', %r)" % f.read(self.sh_size) + data = f.read(self.sh_size) + print " ('_section_data', %s)" % common_dump.dataToHex(data) print " )," def dumpSymtab(f, section, strtab): Modified: llvm/trunk/test/Scripts/macho-dump URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Scripts/macho-dump?rev=113685&r1=113684&r2=113685&view=diff ============================================================================== --- llvm/trunk/test/Scripts/macho-dump (original) +++ llvm/trunk/test/Scripts/macho-dump Sat Sep 11 10:25:58 2010 @@ -4,6 +4,8 @@ import sys import StringIO +import common_dump + class Reader: def __init__(self, path): if path == '-': @@ -267,7 +269,7 @@ if opts.dumpSectionData: f.seek(offset) - print " ('_section_data', %r)" % f.read(size) + print " ('_section_data', '%s')" % common_dump.dataToHex(f.read(size)) f.seek(prev_pos) From rafael.espindola at gmail.com Sat Sep 11 10:45:48 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Sat, 11 Sep 2010 15:45:48 -0000 Subject: [llvm-commits] [llvm] r113687 - /llvm/trunk/test/Scripts/elf-dump Message-ID: <20100911154548.E688F2A6C12C@llvm.org> Author: rafael Date: Sat Sep 11 10:45:48 2010 New Revision: 113687 URL: http://llvm.org/viewvc/llvm-project?rev=113687&view=rev Log: Add missing single quotes. Modified: llvm/trunk/test/Scripts/elf-dump Modified: llvm/trunk/test/Scripts/elf-dump URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Scripts/elf-dump?rev=113687&r1=113686&r2=113687&view=diff ============================================================================== --- llvm/trunk/test/Scripts/elf-dump (original) +++ llvm/trunk/test/Scripts/elf-dump Sat Sep 11 10:45:48 2010 @@ -98,7 +98,7 @@ elif dumpdata: f.seek(self.sh_offset) data = f.read(self.sh_size) - print " ('_section_data', %s)" % common_dump.dataToHex(data) + print " ('_section_data', '%s')" % common_dump.dataToHex(data) print " )," def dumpSymtab(f, section, strtab): From sabre at nondot.org Sat Sep 11 11:18:25 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 11 Sep 2010 16:18:25 -0000 Subject: [llvm-commits] [llvm] r113688 - in /llvm/trunk: include/llvm/MC/MCParser/MCAsmParser.h lib/MC/MCParser/AsmParser.cpp lib/Target/ARM/AsmParser/ARMAsmParser.cpp lib/Target/X86/AsmParser/X86AsmParser.cpp Message-ID: <20100911161825.34D302A6C12C@llvm.org> Author: lattner Date: Sat Sep 11 11:18:25 2010 New Revision: 113688 URL: http://llvm.org/viewvc/llvm-project?rev=113688&view=rev Log: fix the asmparser so that the target is responsible for skipping to the end of the line on a parser error, allowing skipping to happen for syntactic errors but not for semantic errors. Before we would miss emitting a diagnostic about the second line, because we skipped it due to the semantic error on the first line: foo %eax bar %al This fixes rdar://8414033 - llvm-mc ignores lines after an invalid instruction mnemonic errors Modified: llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h llvm/trunk/lib/MC/MCParser/AsmParser.cpp llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Modified: llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h?rev=113688&r1=113687&r2=113688&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h (original) +++ llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h Sat Sep 11 11:18:25 2010 @@ -99,6 +99,10 @@ /// will be either the EndOfStatement or EOF. virtual StringRef ParseStringToEndOfStatement() = 0; + /// EatToEndOfStatement - Skip to the end of the current statement, for error + /// recovery. + virtual void EatToEndOfStatement() = 0; + /// ParseExpression - Parse an arbitrary expression. /// /// @param Res - The value of the expression. The result is undefined Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=113688&r1=113687&r2=113688&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Sat Sep 11 11:18:25 2010 @@ -965,7 +965,9 @@ for (unsigned i = 0, e = ParsedOperands.size(); i != e; ++i) delete ParsedOperands[i]; - return HadError; + // Don't skip the rest of the line, the instruction parser is responsible for + // that. + return false; } MacroInstantiation::MacroInstantiation(const Macro *M, SMLoc IL, SMLoc EL, Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=113688&r1=113687&r2=113688&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Sat Sep 11 11:18:25 2010 @@ -726,22 +726,29 @@ if (getLexer().isNot(AsmToken::EndOfStatement)) { // Read the first operand. OwningPtr Op; - if (ParseOperand(Op)) return true; + if (ParseOperand(Op)) { + Parser.EatToEndOfStatement(); + return true; + } Operands.push_back(Op.take()); while (getLexer().is(AsmToken::Comma)) { Parser.Lex(); // Eat the comma. // Parse and remember the operand. - if (ParseOperand(Op)) return true; + if (ParseOperand(Op)) { + Parser.EatToEndOfStatement(); + return true; + } Operands.push_back(Op.take()); } } - if (getLexer().isNot(AsmToken::EndOfStatement)) + if (getLexer().isNot(AsmToken::EndOfStatement)) { + Parser.EatToEndOfStatement(); return TokError("unexpected token in argument list"); + } Parser.Lex(); // Consume the EndOfStatement - return false; } Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=113688&r1=113687&r2=113688&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Sat Sep 11 11:18:25 2010 @@ -785,8 +785,10 @@ // Read the first operand. if (X86Operand *Op = ParseOperand()) Operands.push_back(Op); - else + else { + Parser.EatToEndOfStatement(); return true; + } while (getLexer().is(AsmToken::Comma)) { Parser.Lex(); // Eat the comma. @@ -794,12 +796,16 @@ // Parse and remember the operand. if (X86Operand *Op = ParseOperand()) Operands.push_back(Op); - else + else { + Parser.EatToEndOfStatement(); return true; + } } - if (getLexer().isNot(AsmToken::EndOfStatement)) + if (getLexer().isNot(AsmToken::EndOfStatement)) { + Parser.EatToEndOfStatement(); return TokError("unexpected token in argument list"); + } } if (getLexer().is(AsmToken::EndOfStatement)) From sabre at nondot.org Sat Sep 11 11:32:13 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 11 Sep 2010 16:32:13 -0000 Subject: [llvm-commits] [llvm] r113689 - in /llvm/trunk: lib/Target/X86/AsmParser/X86AsmParser.cpp test/MC/AsmParser/X86/x86_instructions.s Message-ID: <20100911163213.147B42A6C12C@llvm.org> Author: lattner Date: Sat Sep 11 11:32:12 2010 New Revision: 113689 URL: http://llvm.org/viewvc/llvm-project?rev=113689&view=rev Log: implement rdar://8407928 - support for in/out with a missing "a" register. Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=113689&r1=113688&r2=113689&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Sat Sep 11 11:32:12 2010 @@ -811,7 +811,8 @@ if (getLexer().is(AsmToken::EndOfStatement)) Parser.Lex(); // Consume the EndOfStatement - // FIXME: Hack to handle recognizing s{hr,ar,hl}? $1. + // FIXME: Hack to handle recognize s{hr,ar,hl} , $1. Canonicalize to + // "shift ". if ((Name.startswith("shr") || Name.startswith("sar") || Name.startswith("shl")) && Operands.size() == 3) { @@ -823,6 +824,37 @@ } } + // FIXME: Hack to handle recognize "in[bwl] ". Canonicalize it to + // "inb , %al". + if ((Name == "inb" || Name == "inw" || Name == "inl") && + Operands.size() == 2) { + unsigned Reg; + if (Name[2] == 'b') + Reg = MatchRegisterName("al"); + else if (Name[2] == 'w') + Reg = MatchRegisterName("ax"); + else + Reg = MatchRegisterName("eax"); + SMLoc Loc = Operands.back()->getEndLoc(); + Operands.push_back(X86Operand::CreateReg(Reg, Loc, Loc)); + } + + // FIXME: Hack to handle recognize "out[bwl] ". Canonicalize it to + // "outb %al, ". + if ((Name == "outb" || Name == "outw" || Name == "outl") && + Operands.size() == 2) { + unsigned Reg; + if (Name[3] == 'b') + Reg = MatchRegisterName("al"); + else if (Name[3] == 'w') + Reg = MatchRegisterName("ax"); + else + Reg = MatchRegisterName("eax"); + SMLoc Loc = Operands.back()->getEndLoc(); + Operands.push_back(X86Operand::CreateReg(Reg, Loc, Loc)); + std::swap(Operands[1], Operands[2]); + } + // FIXME: Hack to handle "f{mul*,add*,sub*,div*} $op, st(0)" the same as // "f{mul*,add*,sub*,div*} $op" if ((Name.startswith("fmul") || Name.startswith("fadd") || Modified: llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s?rev=113689&r1=113688&r2=113689&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_instructions.s Sat Sep 11 11:32:12 2010 @@ -188,3 +188,15 @@ // CHECK: cmovneq %rbx, %rax cmovnzq %rbx, %rax + +// rdar://8407928 +// CHECK: inb $127, %al +// CHECK: inw %dx, %ax +// CHECK: outb %al, $127 +// CHECK: outw %ax, %dx +// CHECK: inl %dx, %eax +inb $0x7f +inw %dx +outb $0x7f +outw %dx +inl %dx From sabre at nondot.org Sat Sep 11 11:39:16 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 11 Sep 2010 16:39:16 -0000 Subject: [llvm-commits] [llvm] r113690 - in /llvm/trunk: lib/Target/X86/AsmParser/X86AsmParser.cpp test/MC/AsmParser/X86/x86_32-new-encoder.s Message-ID: <20100911163916.4869D2A6C12C@llvm.org> Author: lattner Date: Sat Sep 11 11:39:16 2010 New Revision: 113690 URL: http://llvm.org/viewvc/llvm-project?rev=113690&view=rev Log: add support for pushfd/popfd which are aliases for pushfl/popfl. This fixes rdar://8408129 - pushfd and popfd get invalid instruction mnemonic errors Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=113690&r1=113689&r2=113690&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Sat Sep 11 11:39:16 2010 @@ -633,6 +633,8 @@ .Case("pop", Is64Bit ? "popq" : "popl") .Case("pushf", Is64Bit ? "pushfq" : "pushfl") .Case("popf", Is64Bit ? "popfq" : "popfl") + .Case("pushfd", "pushfl") + .Case("popfd", "popfl") .Case("retl", Is64Bit ? "retl" : "ret") .Case("retq", Is64Bit ? "ret" : "retq") .Case("setz", "sete") Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s?rev=113690&r1=113689&r2=113690&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s Sat Sep 11 11:39:16 2010 @@ -508,3 +508,13 @@ pop %es // CHECK: popl %es // CHECK: encoding: [0x07] + +// rdar://8408129 +pushfd +// CHECK: pushfl +popfd +// CHECK: popfl +pushfl +// CHECK: pushfl +popfl +// CHECK: popfl From rafael.espindola at gmail.com Sat Sep 11 11:45:15 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Sat, 11 Sep 2010 16:45:15 -0000 Subject: [llvm-commits] [llvm] r113691 - in /llvm/trunk: lib/MC/MCParser/AsmParser.cpp lib/MC/MCParser/ELFAsmParser.cpp test/MC/ELF/dg.exp test/MC/ELF/sleb.s test/MC/ELF/uleb.s Message-ID: <20100911164516.0D3402A6C12C@llvm.org> Author: rafael Date: Sat Sep 11 11:45:15 2010 New Revision: 113691 URL: http://llvm.org/viewvc/llvm-project?rev=113691&view=rev Log: Add support for leb128 of absolute expressions. Added: llvm/trunk/test/MC/ELF/sleb.s llvm/trunk/test/MC/ELF/uleb.s Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp llvm/trunk/test/MC/ELF/dg.exp Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=113691&r1=113690&r2=113691&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Sat Sep 11 11:45:15 2010 @@ -238,6 +238,9 @@ AddDirectiveHandler<&GenericAsmParser::ParseDirectiveMacro>(".macro"); AddDirectiveHandler<&GenericAsmParser::ParseDirectiveEndMacro>(".endm"); AddDirectiveHandler<&GenericAsmParser::ParseDirectiveEndMacro>(".endmacro"); + + AddDirectiveHandler<&GenericAsmParser::ParseDirectiveLEB128>(".sleb128"); + AddDirectiveHandler<&GenericAsmParser::ParseDirectiveLEB128>(".uleb128"); } bool ParseDirectiveFile(StringRef, SMLoc DirectiveLoc); @@ -247,6 +250,10 @@ bool ParseDirectiveMacrosOnOff(StringRef, SMLoc DirectiveLoc); bool ParseDirectiveMacro(StringRef, SMLoc DirectiveLoc); bool ParseDirectiveEndMacro(StringRef, SMLoc DirectiveLoc); + + void ParseUleb128(uint64_t Value); + void ParseSleb128(int64_t Value); + bool ParseDirectiveLEB128(StringRef, SMLoc); }; } @@ -2049,6 +2056,48 @@ "no current macro definition"); } +void GenericAsmParser::ParseUleb128(uint64_t Value) { + const uint64_t Mask = (1 << 7) - 1; + do { + unsigned Byte = Value & Mask; + Value >>= 7; + if (Value) // Not the last one + Byte |= (1 << 7); + getStreamer().EmitIntValue(Byte, 1, DEFAULT_ADDRSPACE); + } while (Value); +} + +void GenericAsmParser::ParseSleb128(int64_t Value) { + const int64_t Mask = (1 << 7) - 1; + for(;;) { + unsigned Byte = Value & Mask; + Value >>= 7; + bool Done = ((Value == 0 && (Byte & 0x40) == 0) || + (Value == -1 && (Byte & 0x40) != 0)); + if (!Done) + Byte |= (1 << 7); + getStreamer().EmitIntValue(Byte, 1, DEFAULT_ADDRSPACE); + if (Done) + break; + } +} + +bool GenericAsmParser::ParseDirectiveLEB128(StringRef DirName, SMLoc) { + int64_t Value; + if (getParser().ParseAbsoluteExpression(Value)) + return true; + + if (getLexer().isNot(AsmToken::EndOfStatement)) + return TokError("unexpected token in directive"); + + if (DirName[1] == 's') + ParseSleb128(Value); + else + ParseUleb128(Value); + return false; +} + + /// \brief Create an MCAsmParser instance. MCAsmParser *llvm::createMCAsmParser(const Target &T, SourceMgr &SM, MCContext &C, MCStreamer &Out, Modified: llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp?rev=113691&r1=113690&r2=113691&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/ELFAsmParser.cpp Sat Sep 11 11:45:15 2010 @@ -48,8 +48,6 @@ AddDirectiveHandler<&ELFAsmParser::ParseSectionDirectiveEhFrame>(".eh_frame"); AddDirectiveHandler<&ELFAsmParser::ParseDirectiveSection>(".section"); AddDirectiveHandler<&ELFAsmParser::ParseDirectiveSize>(".size"); - AddDirectiveHandler<&ELFAsmParser::ParseDirectiveLEB128>(".sleb128"); - AddDirectiveHandler<&ELFAsmParser::ParseDirectiveLEB128>(".uleb128"); AddDirectiveHandler<&ELFAsmParser::ParseDirectivePrevious>(".previous"); } @@ -109,7 +107,6 @@ MCSectionELF::SHF_WRITE, SectionKind::getDataRel()); } - bool ParseDirectiveLEB128(StringRef, SMLoc); bool ParseDirectiveSection(StringRef, SMLoc); bool ParseDirectiveSize(StringRef, SMLoc); bool ParseDirectivePrevious(StringRef, SMLoc); @@ -254,26 +251,6 @@ return false; } -bool ELFAsmParser::ParseDirectiveLEB128(StringRef DirName, SMLoc) { - int64_t Value; - if (getParser().ParseAbsoluteExpression(Value)) - return true; - - if (getLexer().isNot(AsmToken::EndOfStatement)) - return TokError("unexpected token in directive"); - - // FIXME: Add proper MC support. - if (getContext().getAsmInfo().hasLEB128()) { - if (DirName[1] == 's') - getStreamer().EmitRawText("\t.sleb128\t" + Twine(Value)); - else - getStreamer().EmitRawText("\t.uleb128\t" + Twine(Value)); - return false; - } - // FIXME: This shouldn't be an error! - return TokError("LEB128 not supported yet"); -} - bool ELFAsmParser::ParseDirectivePrevious(StringRef DirName, SMLoc) { const MCSection *PreviousSection = getStreamer().getPreviousSection(); if (PreviousSection != NULL) Modified: llvm/trunk/test/MC/ELF/dg.exp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/dg.exp?rev=113691&r1=113690&r2=113691&view=diff ============================================================================== --- llvm/trunk/test/MC/ELF/dg.exp (original) +++ llvm/trunk/test/MC/ELF/dg.exp Sat Sep 11 11:45:15 2010 @@ -1,5 +1,5 @@ load_lib llvm.exp if { [llvm_supports_target X86] } { - RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll}]] + RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,s}]] } Added: llvm/trunk/test/MC/ELF/sleb.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/sleb.s?rev=113691&view=auto ============================================================================== --- llvm/trunk/test/MC/ELF/sleb.s (added) +++ llvm/trunk/test/MC/ELF/sleb.s Sat Sep 11 11:45:15 2010 @@ -0,0 +1,29 @@ +// RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu -n %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=ELF_32 %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -n %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=ELF_64 %s +// RUN: llvm-mc -filetype=obj -triple i386-apple-darwin9 %s -o - | macho-dump --dump-section-data | FileCheck -check-prefix=MACHO_32 %s +// RUN: llvm-mc -filetype=obj -triple x86_64-apple-darwin9 %s -o - | macho-dump --dump-section-data | FileCheck -check-prefix=MACHO_64 %s + + .text +foo: + .sleb128 0 + .sleb128 1 + .sleb128 -1 + .sleb128 63 + .sleb128 -64 + + .sleb128 64 + .sleb128 -65 + + .sleb128 8191 + .sleb128 -8192 + + .sleb128 8193 + +// ELF_32: ('sh_name', 1) # '.text' +// ELF_32: ('_section_data', '00017f3f 40c000bf 7fff3f80 4081c000') +// ELF_64: ('sh_name', 1) # '.text' +// ELF_64: ('_section_data', '00017f3f 40c000bf 7fff3f80 4081c000') +// MACHO_32: ('section_name', '__text\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// MACHO_32: ('_section_data', '00017f3f 40c000bf 7fff3f80 4081c000') +// MACHO_64: ('section_name', '__text\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// MACHO_64: ('_section_data', '00017f3f 40c000bf 7fff3f80 4081c000') Added: llvm/trunk/test/MC/ELF/uleb.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/uleb.s?rev=113691&view=auto ============================================================================== --- llvm/trunk/test/MC/ELF/uleb.s (added) +++ llvm/trunk/test/MC/ELF/uleb.s Sat Sep 11 11:45:15 2010 @@ -0,0 +1,22 @@ +// RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu -n %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=ELF_32 %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -n %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=ELF_64 %s +// RUN: llvm-mc -filetype=obj -triple i386-apple-darwin9 %s -o - | macho-dump --dump-section-data | FileCheck -check-prefix=MACHO_32 %s +// RUN: llvm-mc -filetype=obj -triple x86_64-apple-darwin9 %s -o - | macho-dump --dump-section-data | FileCheck -check-prefix=MACHO_64 %s + + .text +foo: + .uleb128 0 + .uleb128 1 + .uleb128 127 + .uleb128 128 + .uleb128 16383 + .uleb128 16384 + +// ELF_32: ('sh_name', 1) # '.text' +// ELF_32: ('_section_data', '00017f80 01ff7f80 8001') +// ELF_64: ('sh_name', 1) # '.text' +// ELF_64: ('_section_data', '00017f80 01ff7f80 8001') +// MACHO_32: ('section_name', '__text\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// MACHO_32: ('_section_data', '00017f80 01ff7f80 8001') +// MACHO_64: ('section_name', '__text\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// MACHO_64: ('_section_data', '00017f80 01ff7f80 8001') From sabre at nondot.org Sat Sep 11 12:06:05 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 11 Sep 2010 17:06:05 -0000 Subject: [llvm-commits] [llvm] r113692 - in /llvm/trunk: lib/Target/X86/AsmParser/X86AsmParser.cpp test/MC/AsmParser/X86/x86_32-new-encoder.s Message-ID: <20100911170605.9CE2F2A6C12C@llvm.org> Author: lattner Date: Sat Sep 11 12:06:05 2010 New Revision: 113692 URL: http://llvm.org/viewvc/llvm-project?rev=113692&view=rev Log: add support for all the setCC aliases. Part of rdar://8416805 Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=113692&r1=113691&r2=113692&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Sat Sep 11 12:06:05 2010 @@ -637,22 +637,20 @@ .Case("popfd", "popfl") .Case("retl", Is64Bit ? "retl" : "ret") .Case("retq", Is64Bit ? "ret" : "retq") - .Case("setz", "sete") - .Case("setnz", "setne") - .Case("jz", "je") - .Case("jnz", "jne") - .Case("jc", "jb") - .Case("jna", "jbe") - .Case("jnae", "jb") - .Case("jnb", "jae") - .Case("jnbe", "ja") - .Case("jnc", "jae") - .Case("jng", "jle") - .Case("jnge", "jl") - .Case("jnl", "jge") - .Case("jnle", "jg") - .Case("jpe", "jp") - .Case("jpo", "jnp") + .Case("setz", "sete") .Case("setnz", "setne") + .Case("setc", "setb") .Case("setna", "setbe") + .Case("setnae", "setb").Case("setnb", "setae") + .Case("setnbe", "seta").Case("setnc", "setae") + .Case("setng", "setle").Case("setnge", "setl") + .Case("setnl", "setge").Case("setnle", "setg") + .Case("setpe", "setp") .Case("setpo", "setnp") + .Case("jz", "je") .Case("jnz", "jne") + .Case("jc", "jb") .Case("jna", "jbe") + .Case("jnae", "jb").Case("jnb", "jae") + .Case("jnbe", "ja").Case("jnc", "jae") + .Case("jng", "jle").Case("jnge", "jl") + .Case("jnl", "jge").Case("jnle", "jg") + .Case("jpe", "jp") .Case("jpo", "jnp") // Condition code aliases for 16-bit, 32-bit, 64-bit and unspec operands. .Case("cmovcw", "cmovbw") .Case("cmovcl", "cmovbl") .Case("cmovcq", "cmovbq") .Case("cmovc", "cmovb") Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s?rev=113692&r1=113691&r2=113692&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s Sat Sep 11 12:06:05 2010 @@ -518,3 +518,18 @@ // CHECK: pushfl popfl // CHECK: popfl + + +// rdar://8416805 + setc %bl + setnae %bl + setnb %bl + setnc %bl + setna %bl + setnbe %bl + setpe %bl + setpo %bl + setnge %bl + setnl %bl + setng %bl + setnle %bl From sabre at nondot.org Sat Sep 11 12:08:22 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 11 Sep 2010 17:08:22 -0000 Subject: [llvm-commits] [llvm] r113693 - in /llvm/trunk: lib/Target/X86/AsmParser/X86AsmParser.cpp test/MC/AsmParser/X86/x86_32-new-encoder.s Message-ID: <20100911170822.4E9B82A6C12C@llvm.org> Author: lattner Date: Sat Sep 11 12:08:22 2010 New Revision: 113693 URL: http://llvm.org/viewvc/llvm-project?rev=113693&view=rev Log: add a missed cmov alias, part of rdar://8416805 Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=113693&r1=113692&r2=113693&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original) +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Sat Sep 11 12:08:22 2010 @@ -654,6 +654,8 @@ // Condition code aliases for 16-bit, 32-bit, 64-bit and unspec operands. .Case("cmovcw", "cmovbw") .Case("cmovcl", "cmovbl") .Case("cmovcq", "cmovbq") .Case("cmovc", "cmovb") + .Case("cmovnaew","cmovbw") .Case("cmovnael","cmovbl") + .Case("cmovnaeq","cmovbq") .Case("cmovnae", "cmovb") .Case("cmovnaw", "cmovbew").Case("cmovnal", "cmovbel") .Case("cmovnaq", "cmovbeq").Case("cmovna", "cmovbe") .Case("cmovnbw", "cmovaew").Case("cmovnbl", "cmovael") Modified: llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s?rev=113693&r1=113692&r2=113693&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s (original) +++ llvm/trunk/test/MC/AsmParser/X86/x86_32-new-encoder.s Sat Sep 11 12:08:22 2010 @@ -107,6 +107,10 @@ // CHECK: encoding: [0x0f,0x42,0xd0] cmovbl %eax,%edx +// CHECK: cmovbw %bx, %bx +cmovnae %bx,%bx + + // CHECK: cmovbel %eax, %edx // CHECK: encoding: [0x0f,0x46,0xd0] cmovbel %eax,%edx From pichet2000 at gmail.com Sat Sep 11 12:16:59 2010 From: pichet2000 at gmail.com (Francois Pichet) Date: Sat, 11 Sep 2010 13:16:59 -0400 Subject: [llvm-commits] [PATCH][MS][Review request] - Fix index lit tests failing on Windows Message-ID: This patch fixes all the index lit tests failing on Win32. lit index tests were failing on windows because GetPreamblePCHPath was returning a empty string. Returning a empty string because when python spawn c-index-test.exe neither "TMPDIR", "TEMP" or "TMP" are defined as environment variables. Then GetPreamblePCHPath returning "" created a complicated chain of events leading to a crash. Probably the code should be more robust. I am not sure if this can be defined as trivial change i can commit without review? -------------- next part -------------- A non-text attachment was scrubbed... Name: index_test_win32_fix.patch Type: application/octet-stream Size: 545 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20100911/e3e52167/attachment.obj From rafael.espindola at gmail.com Sat Sep 11 12:37:42 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Sat, 11 Sep 2010 17:37:42 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r113694 - in /llvm-gcc-4.2/trunk/gcc: config/arm/llvm-arm-target.h config/arm/llvm-arm.cpp llvm-abi-default.cpp llvm-abi.h llvm-convert.cpp llvm-types.cpp Message-ID: <20100911173742.2316C2A6C12C@llvm.org> Author: rafael Date: Sat Sep 11 12:37:41 2010 New Revision: 113694 URL: http://llvm.org/viewvc/llvm-project?rev=113694&view=rev Log: Lower ARM function signatures a bit more. I implemented only AAPCS since that is what I can test. With this patch we convert struct foo {double a; int b;}; void f(int, struct foo); void g(int a, double b, int c) { struct foo x = {b, c}; f(a, x); } into ------------------------------------------------------ define void @g(i32 %a.0, i32, i32 %b.0, i32 %b.1, i32 %c.0) nounwind optsize { entry: tail call void @f(i32 %a.0, i32 undef, i32 %b.0, i32 %b.1, i32 %c.0, i32 0) nounwind ret void } declare void @f(i32, i32, i32, i32, i32, i32) ---------------------------------------------------- instead of --------------------------------------------------- define void @g(i32 %a, double %b, i32 %c) nounwind optsize { entry: %tmp11 = bitcast double %b to i64 %tmp5 = zext i32 %c to i64 tail call void @f(i32 %a, i64 %tmp11, i64 %tmp5) nounwind ret void } declare void @f(i32, i64, i64) -------------------------------------------------- The IL for ------------------------------------------ double foo(double X, double Y) { return X+Y; } ----------------------------------------- now shows that the arguments being passed in the integer registres: ---------------------------------------------------------------------- define double @foo(i32 %X.0, i32 %X.1, i32 %Y.0, i32 %Y.1) nounwind readnone optsize { entry: %tmp17 = zext i32 %X.0 to i64 %tmp12 = zext i32 %X.1 to i64 %tmp13 = shl i64 %tmp12, 32 %ins15 = or i64 %tmp13, %tmp17 %tmp6 = zext i32 %Y.0 to i64 %tmp3 = zext i32 %Y.1 to i64 %tmp4 = shl i64 %tmp3, 32 %ins = or i64 %tmp4, %tmp6 %tmp10 = bitcast i64 %ins15 to double %tmp2 = bitcast i64 %ins to double %0 = fadd double %tmp10, %tmp2 ret double %0 } --------------------------------------------------------------------- And the produces assembly is the same as before: ---------------------------------------------------------------- foo: vmov d0, r2, r3 vmov d1, r0, r1 vadd.f64 d0, d1, d0 vmov r0, r1, d0 bx lr ---------------------------------------------------------------- Modified: llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm-target.h llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp llvm-gcc-4.2/trunk/gcc/llvm-abi.h llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Modified: llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm-target.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm-target.h?rev=113694&r1=113693&r2=113694&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm-target.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm-target.h Sat Sep 11 12:37:41 2010 @@ -55,6 +55,15 @@ #define LLVM_SHOULD_PASS_AGGREGATE_IN_MIXED_REGS(T, TY, CC, E) \ llvm_arm_should_pass_aggregate_in_mixed_regs((T), (TY), (CC), (E)) +struct DefaultABIClient; +extern bool +llvm_arm_try_pass_aggregate_custom(tree, std::vector&, + CallingConv::ID&, + struct DefaultABIClient*); + +#define LLVM_TRY_PASS_AGGREGATE_CUSTOM(T, E, CC, C) \ + llvm_arm_try_pass_aggregate_custom((T), (E), (CC), (C)) + extern bool llvm_arm_aggregate_partially_passed_in_regs(std::vector&, std::vector&, Modified: llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp?rev=113694&r1=113693&r2=113694&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp Sat Sep 11 12:37:41 2010 @@ -2557,6 +2557,91 @@ } } +static unsigned count_num_words(std::vector &ScalarElts) { + unsigned NumWords = 0; + for (unsigned i = 0, e = ScalarElts.size(); i != e; ++i) { + const Type *Ty = ScalarElts[i]; + if (Ty->isPointerTy()) { + NumWords++; + } else if (Ty->isIntegerTy()) { + const unsigned TypeSize = Ty->getPrimitiveSizeInBits(); + const unsigned NumWordsForType = (TypeSize + 31) / 32; + + NumWords += NumWordsForType; + } else { + assert (0 && "Unexpected type."); + } + } + return NumWords; +} + +// This function is used only on AAPCS. The difference from the generic +// handling of arguments is that arguments larger than 32 bits are split +// and padding arguments are added as necessary for alignment. This makes +// the IL a bit more explicit about how arguments are handled. +extern bool +llvm_arm_try_pass_aggregate_custom(tree type, + std::vector& ScalarElts, + CallingConv::ID& CC, + struct DefaultABIClient* C) { + if (CC != CallingConv::ARM_AAPCS && CC != CallingConv::C) + return false; + + if (CC == CallingConv::C && !TARGET_AAPCS_BASED) + return false; + + if (TARGET_HARD_FLOAT_ABI) + return false; + const Type *Ty = ConvertType(type); + if (Ty->isPointerTy()) + return false; + + const unsigned Size = TREE_INT_CST_LOW(TYPE_SIZE(type))/8; + const unsigned Alignment = TYPE_ALIGN(type)/8; + const unsigned NumWords = count_num_words(ScalarElts); + const bool AddPad = Alignment >= 8 && (NumWords % 2); + + // First, build a type that will be bitcast to the original one and + // from where elements will be extracted. + std::vector Elts; + const Type* Int32Ty = Type::getInt32Ty(getGlobalContext()); + const unsigned NumRegularArgs = Size / 4; + for (unsigned i = 0; i < NumRegularArgs; ++i) { + Elts.push_back(Int32Ty); + } + const unsigned RestSize = Size % 4; + const llvm::Type *RestType = NULL; + if (RestSize> 2) { + RestType = Type::getInt32Ty(getGlobalContext()); + } else if (RestSize > 1) { + RestType = Type::getInt16Ty(getGlobalContext()); + } else if (RestSize > 0) { + RestType = Type::getInt8Ty(getGlobalContext()); + } + if (RestType) + Elts.push_back(RestType); + const StructType *STy = StructType::get(getGlobalContext(), Elts, false); + + if (AddPad) { + ScalarElts.push_back(Int32Ty); + C->HandlePad(Int32Ty); + } + + for (unsigned i = 0; i < NumRegularArgs; ++i) { + C->EnterField(i, STy); + C->HandleScalarArgument(Int32Ty, 0); + ScalarElts.push_back(Int32Ty); + C->ExitField(); + } + if (RestType) { + C->EnterField(NumRegularArgs, STy); + C->HandleScalarArgument(RestType, 0, RestSize); + ScalarElts.push_back(RestType); + C->ExitField(); + } + return true; +} + // Target hook for llvm-abi.h. It returns true if an aggregate of the // specified type should be passed in a number of registers of mixed types. // It also returns a vector of types that correspond to the registers used Modified: llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp?rev=113694&r1=113693&r2=113694&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp Sat Sep 11 12:37:41 2010 @@ -8,7 +8,8 @@ /// return type. It potentially breaks down the argument and invokes methods /// on the client that indicate how its pieces should be handled. This /// handles things like returning structures via hidden parameters. -void DefaultABI::HandleReturnType(tree type, tree fn, bool isBuiltin) { +void DefaultABI::HandleReturnType(tree type, tree fn, bool isBuiltin, + std::vector &ScalarElts) { unsigned Offset = 0; const Type *Ty = ConvertType(type); if (Ty->isVectorTy()) { @@ -52,7 +53,9 @@ // FIXME: should return the hidden first argument for some targets // (e.g. ELF i386). - C.HandleAggregateShadowResult(Ty->getPointerTo(), false); + const PointerType *PTy = Ty->getPointerTo(); + C.HandleAggregateShadowResult(PTy, false); + ScalarElts.push_back(PTy); } } Modified: llvm-gcc-4.2/trunk/gcc/llvm-abi.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-abi.h?rev=113694&r1=113693&r2=113694&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-abi.h (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-abi.h Sat Sep 11 12:37:41 2010 @@ -396,7 +396,8 @@ /// return type. It potentially breaks down the argument and invokes methods /// on the client that indicate how its pieces should be handled. This /// handles things like returning structures via hidden parameters. - void HandleReturnType(tree type, tree fn, bool isBuiltin); + void HandleReturnType(tree type, tree fn, bool isBuiltin, + std::vector &ScalarElts); /// HandleArgument - This is invoked by the target-independent code for each /// argument type passed into the function. It potentially breaks down the Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=113694&r1=113693&r2=113694&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Sat Sep 11 12:37:41 2010 @@ -673,17 +673,19 @@ FunctionPrologArgumentConversion Client(FnDecl, AI, Builder, CallingConv); DefaultABI ABIConverter(Client); + // Scalar arguments processed so far. + std::vector ScalarArgs; + // Handle the DECL_RESULT. ABIConverter.HandleReturnType(TREE_TYPE(TREE_TYPE(FnDecl)), FnDecl, - DECL_BUILT_IN(FnDecl)); + DECL_BUILT_IN(FnDecl), + ScalarArgs); // Remember this for use by FinishFunctionBody. ReturnOffset = Client.Offset; // Prepend the static chain (if any) to the list of arguments. tree Args = static_chain ? static_chain : DECL_ARGUMENTS(FnDecl); - // Scalar arguments processed so far. - std::vector ScalarArgs; while (Args) { const char *Name = "unnamed_arg"; if (DECL_NAME(Args)) Name = IDENTIFIER_POINTER(DECL_NAME(Args)); @@ -3012,16 +3014,17 @@ DefaultABI ABIConverter(Client); // Handle the result, including struct returns. + std::vector ScalarArgs; ABIConverter.HandleReturnType(TREE_TYPE(exp), fndecl ? fndecl : exp, - fndecl ? DECL_BUILT_IN(fndecl) : false); + fndecl ? DECL_BUILT_IN(fndecl) : false, + ScalarArgs); // Pass the static chain, if any, as the first parameter. if (TREE_OPERAND(exp, 2)) CallOperands.push_back(Emit(TREE_OPERAND(exp, 2), 0)); // Loop over the arguments, expanding them and adding them to the op list. - std::vector ScalarArgs; for (tree arg = TREE_OPERAND(exp, 1); arg; arg = TREE_CHAIN(arg)) { tree type = TREE_TYPE(TREE_VALUE(arg)); const Type *ArgTy = ConvertType(type); Modified: llvm-gcc-4.2/trunk/gcc/llvm-types.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-types.cpp?rev=113694&r1=113693&r2=113694&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-types.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Sat Sep 11 12:37:41 2010 @@ -1082,8 +1082,10 @@ TARGET_ADJUST_LLVM_CC(CallingConv, type); #endif + std::vector ScalarArgs; // Builtins are always prototyped, so this isn't one. - ABIConverter.HandleReturnType(ReturnType, current_function_decl, false); + ABIConverter.HandleReturnType(ReturnType, current_function_decl, false, + ScalarArgs); SmallVector Attrs; @@ -1110,7 +1112,6 @@ Attrs.push_back(AttributeWithIndex::get(ArgTys.size(), Attribute::StructRet)); - std::vector ScalarArgs; if (static_chain) { // Pass the static chain as the first parameter. ABIConverter.HandleArgument(TREE_TYPE(static_chain), ScalarArgs); @@ -1152,8 +1153,10 @@ TARGET_ADJUST_LLVM_CC(CallingConv, type); #endif + std::vector ScalarArgs; ABIConverter.HandleReturnType(TREE_TYPE(type), current_function_decl, - decl ? DECL_BUILT_IN(decl) : false); + decl ? DECL_BUILT_IN(decl) : false, + ScalarArgs); // Compute attributes for return type (and function attributes). SmallVector Attrs; @@ -1218,7 +1221,6 @@ Attrs.push_back(AttributeWithIndex::get(ArgTypes.size(), Attribute::StructRet | Attribute::NoAlias)); - std::vector ScalarArgs; if (static_chain) { // Pass the static chain as the first parameter. ABIConverter.HandleArgument(TREE_TYPE(static_chain), ScalarArgs); From dgregor at apple.com Sat Sep 11 12:39:56 2010 From: dgregor at apple.com (Douglas Gregor) Date: Sat, 11 Sep 2010 10:39:56 -0700 Subject: [llvm-commits] [PATCH][MS][Review request] - Fix index lit tests failing on Windows In-Reply-To: References: Message-ID: <816DE3CF-45B8-495F-8E33-883F4EF61875@apple.com> On Sep 11, 2010, at 10:16 AM, Francois Pichet wrote: > This patch fixes all the index lit tests failing on Win32. > > lit index tests were failing on windows because GetPreamblePCHPath was > returning a empty string. > Returning a empty string because when python spawn c-index-test.exe > neither "TMPDIR", "TEMP" or "TMP" are defined as environment > variables. Thanks for tracking this down! It's a very weird error indeed. > Then GetPreamblePCHPath returning "" created a complicated chain of > events leading to a crash. Probably the code should be more robust. We should fix GetPreamblePCHPatch, so that it doesn't fail in this case, and also fix its caller, so that it can handle such a failure gracefully. I'll take a shot at it. However, I don't think you should commit this change to lit, because none of the tests should require it. - Doug From clattner at apple.com Sat Sep 11 12:53:37 2010 From: clattner at apple.com (Chris Lattner) Date: Sat, 11 Sep 2010 10:53:37 -0700 Subject: [llvm-commits] [llvm] r113618 - in /llvm/trunk: bindings/ocaml/llvm/ include/llvm-c/ include/llvm/ include/llvm/Bitcode/ include/llvm/Support/ lib/AsmParser/ lib/Bitcode/Reader/ lib/Bitcode/Writer/ lib/Target/ lib/Target/CBackend/ lib/Target/CppBackend/ lib/VMCore/ In-Reply-To: <20100910205501.8F6CC2A6C12C@llvm.org> References: <20100910205501.8F6CC2A6C12C@llvm.org> Message-ID: <6763036C-8F1C-4018-A152-948F5E9A34CA@apple.com> On Sep 10, 2010, at 1:55 PM, Dale Johannesen wrote: > Author: johannes > Date: Fri Sep 10 15:55:01 2010 > New Revision: 113618 > > URL: http://llvm.org/viewvc/llvm-project?rev=113618&view=rev > Log: > Add X86 MMX type to bitcode and Type. > (The Ada bindings probably need it too, but all the > obvious places to change say "do not edit this file".) > Looks good, thanks Dale. One minor nit, a comment pasto. > > + /// isPPC_FP128Ty - Return true if this is X86 MMX. > + bool isX86_MMXTy() const { return ID == X86_MMXTyID; } Please add a testcase to test/Assembler to ensure that these are round tripping through the .ll and .bc reader/parser. Thanks! -Chris From clattner at apple.com Sat Sep 11 13:38:49 2010 From: clattner at apple.com (Chris Lattner) Date: Sat, 11 Sep 2010 11:38:49 -0700 Subject: [llvm-commits] [llvm] r113252 - in /llvm/trunk: include/llvm/PassRegistry.h include/llvm/PassSupport.h lib/Analysis/LazyValueInfo.cpp lib/VMCore/PassRegistry.cpp In-Reply-To: <20100907191626.31FD82A6C12C@llvm.org> References: <20100907191626.31FD82A6C12C@llvm.org> Message-ID: On Sep 7, 2010, at 12:16 PM, Owen Anderson wrote: > Author: resistor > Date: Tue Sep 7 14:16:25 2010 > New Revision: 113252 > Clean up some of the PassRegistry implementation, and pImpl-ize it to reduce #include clutter > and exposing internal details. Very nice Owen, thanks. > +++ llvm/trunk/include/llvm/PassRegistry.h Tue Sep 7 14:16:25 2010 > @@ -19,35 +19,22 @@ > > #include "llvm/ADT/StringMap.h" > #include "llvm/System/DataTypes.h" These two #includes don't look needed. -Chris From ofv at wanadoo.es Sat Sep 11 14:35:04 2010 From: ofv at wanadoo.es (=?utf-8?Q?=C3=93scar?= Fuentes) Date: Sat, 11 Sep 2010 21:35:04 +0200 Subject: [llvm-commits] [llvm] r113632 - in /llvm/trunk: ./ cmake/modules/ examples/BrainF/ examples/ExceptionDemo/ examples/Fibonacci/ examples/HowToUseJIT/ examples/Kaleidoscope/Chapter3/ examples/Kaleidoscope/Chapter4/ examples/Kaleidoscope/Chapter5/ e In-Reply-To: (Michael Spencer's message of "Sat, 11 Sep 2010 11:03:26 -0400") References: Message-ID: <87y6b8cbvb.fsf@telefonica.net> Michael Spencer writes: >>> URL: http://llvm.org/viewvc/llvm-project?rev=113632&view=rev >>> Log: >>> CMake: Get rid of LLVMLibDeps.cmake and export the libraries normally. >> >> Who approved this change? > > Douglas Gregor. As you refused to discuss my concerns and committed the change against my opinion, I'll take this as an statement from Doug about him taking the responsibility of the CMake build and the irrelevance of my opinion as the original author and maintainer, so I'll refrain from further work on that area. That said, I'm very surprised to see this antisocial behavior on LLVM. From dgregor at apple.com Sat Sep 11 14:54:48 2010 From: dgregor at apple.com (Douglas Gregor) Date: Sat, 11 Sep 2010 12:54:48 -0700 Subject: [llvm-commits] [llvm] r113632 - in /llvm/trunk: ./ cmake/modules/ examples/BrainF/ examples/ExceptionDemo/ examples/Fibonacci/ examples/HowToUseJIT/ examples/Kaleidoscope/Chapter3/ examples/Kaleidoscope/Chapter4/ examples/Kaleidoscope/Chapter5/ e In-Reply-To: <87y6b8cbvb.fsf@telefonica.net> References: <87y6b8cbvb.fsf@telefonica.net> Message-ID: <247FC08B-C730-43B9-86B7-05721C952616@apple.com> On Sep 11, 2010, at 12:35 PM, ?scar Fuentes wrote: > Michael Spencer writes: > >>>> URL: http://llvm.org/viewvc/llvm-project?rev=113632&view=rev >>>> Log: >>>> CMake: Get rid of LLVMLibDeps.cmake and export the libraries normally. >>> >>> Who approved this change? >> >> Douglas Gregor. > > As you refused to discuss my concerns and committed the change against > my opinion, I'll take this as an statement from Doug about him taking > the responsibility of the CMake build and the irrelevance of my opinion > as the original author and maintainer, so I'll refrain from further work > on that area. > > That said, I'm very surprised to see this antisocial behavior on LLVM. I'm sorry, I completely missed your replies. Michael sent the patch to both llvmdev and llvm-commits, and I was watching llvmdev but not llvm-commits. So, when you "elided" llvmdev in your reply to Michael, I missed that and the subsequent discussion. Seeing no discussion, I approved the patch. My apologies for the misunderstanding! I'll reply to you over on llvm-commits about the technical details. If you think the changes should be reverted while we discuss them, we can do that. - Doug From dgregor at apple.com Sat Sep 11 15:21:44 2010 From: dgregor at apple.com (Douglas Gregor) Date: Sat, 11 Sep 2010 13:21:44 -0700 Subject: [llvm-commits] [PATCH][CMake] Removing LLVMLibDeps.cmake and exporting libraries for CMake clients. In-Reply-To: <87vd6fejb9.fsf@telefonica.net> References: <87vd6fejb9.fsf@telefonica.net> Message-ID: <470F86A9-0C61-47BF-B12B-1556310BFA55@apple.com> On Sep 8, 2010, at 7:34 PM, ?scar Fuentes wrote: > [llvm-dev ml elided] > > Michael Spencer > writes: > >> The attached patches remove this requirement, > > Your patch switches from automatic to manually maintained library > dependencies. On the case of LLVM, that increases the workload of the > maintainer and it is the CMake equivalent of spaghetti code. Only a > strong benefit would justify that. There are numerous benefits to explicitly-maintained library dependencies: - It's clear what those dependencies are, which leads to better understanding of the system as a whole - Changes in dependencies, which are fundamentally architectural changes, become obvious when they happen - Dependencies can make their way into other tools far more easily, e.g., component-based CPack installers (e.g., http://www.paraview.org/Wiki/CMake:Component_Install_With_CPack) - It's clean and easy-to-understand, unlike our implicit dependency-generation scripts (and mapping from those to CMake dependencies) - On the "make" side of the world, explicit dependencies could improve build performance by exposing more parallelism. CMake-generated make files build faster than the autotools-generated makefiles, partly for this reason >> and add real CMake >> package export capabilities. A CMake user wishing to use LLVM can now >> use something similar to this: >> >> cmake_minimum_required(VERSION 2.8) >> >> find_package(LLVM REQUIRED) >> add_definitions(${LLVM_CXXFLAGS}) >> add_executable(llvm-external-test llvm-external-test.cpp) >> target_link_libraries(llvm-external-test ${LLVM_SYSTEM_LIBS} >> ${LLVM_JIT_LIBS} ${LLVM_NATIVECODEGEN_LIBS}) > > How is that better than > > http://www.llvm.org/docs/CMake.html#embedding > > ? Think that it is usual practice to have and use multiple LLVM builds > with different configurations on the same system. For one, find_package is the standard CMake way of finding a package, so we should be providing that to CMake users. CMake's export is designed to make it easy to get find_package working well, with versioning, the ability to directly depend on the exported project's targets, etc. One huge benefit to doing exporting/find_package well is that it would make it easier to separate the LLVM core from, e.g., Clang, because LLVM could export its targets and Clang could just import them via find_package. The rest of Clang's CMakeLists.txt files shouldn't have to change. That could be a big win for IDE users, because it would make it easier to create a project for just Clang that depends on a built or installed LLVM. The same CMakeListst.txt (minus the find_package, of course) would also work in-tree for those who want one giant LLVM+Clang+whatever project. >> llvm+clang compile with these changes on both Linux and MSVS. >> Currently both patches must be applied at the same time. I can >> refactor them into a 3 step process if needed. >> >> Does this break anything for anyone? > > If that is accepted (and for now I see no reason for accepting it) > extensive testing on all major platforms (Linux, OS/X, > Windows/mingw/MSVC++) is required before throwing away the current > method, wich has its limitations, but we know them. Michael has addressed the problems that cropped up. Do we know of any other problems that need to be addressed? - Doug From espindola at google.com Sat Sep 11 15:28:45 2010 From: espindola at google.com (Rafael Espindola) Date: Sat, 11 Sep 2010 16:28:45 -0400 Subject: [llvm-commits] [PATCH][CMake] Removing LLVMLibDeps.cmake and exporting libraries for CMake clients. In-Reply-To: <470F86A9-0C61-47BF-B12B-1556310BFA55@apple.com> References: <87vd6fejb9.fsf@telefonica.net> <470F86A9-0C61-47BF-B12B-1556310BFA55@apple.com> Message-ID: > There are numerous benefits to explicitly-maintained library dependencies: > ? ? ? ?- It's clear what those dependencies are, which leads to better understanding of the system as a whole > > ? ? ? ?- Changes in dependencies, which are fundamentally architectural changes, become obvious when they happen > > ? ? ? ?- Dependencies can make their way into other tools far more easily, e.g., component-based CPack installers ?(e.g., http://www.paraview.org/Wiki/CMake:Component_Install_With_CPack) > > ? ? ? ?- It's clean and easy-to-understand, unlike our implicit dependency-generation scripts (and mapping from those to CMake dependencies) > > ? ? ? ?- On the "make" side of the world, explicit dependencies could improve build performance by exposing more parallelism. CMake-generated make files build faster than the autotools-generated makefiles, partly for this reason +1 Ideally we would have manually declared and automatically checked dependencies. Even better if both the auto* and the cmake build used the same list, but this is already an improvement. Cheers, -- Rafael ?vila de Esp?ndola From pichet2000 at gmail.com Sat Sep 11 15:38:38 2010 From: pichet2000 at gmail.com (Francois Pichet) Date: Sat, 11 Sep 2010 16:38:38 -0400 Subject: [llvm-commits] [PATCH][CMake] Removing LLVMLibDeps.cmake and exporting libraries for CMake clients. In-Reply-To: <470F86A9-0C61-47BF-B12B-1556310BFA55@apple.com> References: <87vd6fejb9.fsf@telefonica.net> <470F86A9-0C61-47BF-B12B-1556310BFA55@apple.com> Message-ID: Since we are discussing cmake, i'll put forward my only complain about the current cmake system. I generate my projects/solution using CMake -G "Visual Studio 9 2008" then when I open llvm.sln, I see these: brainF Kaleidoscope-Ch2 Kaleidoscope-Ch3 Kaleidoscope-Ch4 Kaleidoscope-Ch5 Kaleidoscope-Ch6 Kaleidoscope-Ch7 Fibonacci Nice examples but after you looked at them once they just add to build time. would it be possible to remove them from the main solution? On Sat, Sep 11, 2010 at 4:21 PM, Douglas Gregor wrote: > > On Sep 8, 2010, at 7:34 PM, ?scar Fuentes wrote: > >> [llvm-dev ml elided] From ofv at wanadoo.es Sat Sep 11 16:41:46 2010 From: ofv at wanadoo.es (=?utf-8?Q?=C3=93scar_Fuentes?=) Date: Sat, 11 Sep 2010 23:41:46 +0200 Subject: [llvm-commits] [PATCH][CMake] Removing LLVMLibDeps.cmake and exporting libraries for CMake clients. References: <87vd6fejb9.fsf@telefonica.net> <470F86A9-0C61-47BF-B12B-1556310BFA55@apple.com> Message-ID: <87tylwc605.fsf@telefonica.net> Francois Pichet writes: > Since we are discussing cmake, i'll put forward my only complain about > the current cmake system. > I generate my projects/solution using > CMake -G "Visual Studio 9 2008" > > then when I open llvm.sln, I see these: > brainF > Kaleidoscope-Ch2 > Kaleidoscope-Ch3 > Kaleidoscope-Ch4 > Kaleidoscope-Ch5 > Kaleidoscope-Ch6 > Kaleidoscope-Ch7 > Fibonacci > > Nice examples but after you looked at them once they just add to build > time. would it be possible to remove them from the main solution? Please see http://www.llvm.org/docs/CMake.html#llvmvars and specifically LLVM_BUILD_EXAMPLES. When that variable is OFF (the default since 10 months ago) build targets for the LLVM examples are created, but they are not part of the ALL target. Hence, they are not rebuilt unless you explitictly ask for it. From ofv at wanadoo.es Sat Sep 11 17:31:48 2010 From: ofv at wanadoo.es (=?utf-8?Q?=C3=93scar?= Fuentes) Date: Sun, 12 Sep 2010 00:31:48 +0200 Subject: [llvm-commits] [PATCH][CMake] Removing LLVMLibDeps.cmake and exporting libraries for CMake clients. In-Reply-To: <470F86A9-0C61-47BF-B12B-1556310BFA55@apple.com> (Douglas Gregor's message of "Sat, 11 Sep 2010 13:21:44 -0700") References: <87vd6fejb9.fsf@telefonica.net> <470F86A9-0C61-47BF-B12B-1556310BFA55@apple.com> Message-ID: <87occ3di97.fsf@telefonica.net> Hello Doug. Glad to see my confidence on the sociability of the LLVM developers restored ;-) Douglas Gregor writes: >> Your patch switches from automatic to manually maintained library >> dependencies. On the case of LLVM, that increases the workload of the >> maintainer and it is the CMake equivalent of spaghetti code. Only a >> strong benefit would justify that. > > There are numerous benefits to explicitly-maintained library dependencies: > - It's clear what those dependencies are, which leads to better > understanding of the system as a wholea The file cmake/modules/LLVMLibDeps.cmake concentrates all those dependencies, so if you want to get the whole picture of the library dependencies, you have a single point to look at, instead of dozens of files scattered all around the source tree. It is possible to make that file more redable, if you wish. > - Changes in dependencies, which are fundamentally architectural > changes, become obvious when they happen Again, looking at the history of LLVMLibDeps.cmake you can see all those changes at a glance. > - Dependencies can make their way into other tools far more > easily, e.g., component-based CPack installers (e.g., > http://www.paraview.org/Wiki/CMake:Component_Install_With_CPack) CPack works fine with the automatic library dependency system. Please note that the automatic system ends using target_link_libraries anyways, so putting it explicitly on the corresponding CMakeLists.txt makes no difference for tools that require its existente. > - It's clean and easy-to-understand, unlike our implicit > dependency-generation scripts (and mapping from those to CMake > dependencies) Agreed. > - On the "make" side of the world, explicit dependencies could > improve build performance by exposing more > parallelism. CMake-generated make files build faster than the > autotools-generated makefiles, partly for this reason Again, the just-committed system makes no difference here. > For one, find_package is the standard CMake way of finding a package, > so we should be providing that to CMake users. That sounds good, but we shall think on terms of the specific characteristics of LLVM. find_package works fine for libraries such as zlib, that is, components that you install on standard places because they are required by some other package and which are stable and remain unchanged until a bug is found or a new version is required. I don't think LLVM fits there. Either you have LLVM for working *on* it, or you are tracking its development. In any case LLVM is not just "a library," but THE library. And given how LLVM is developed you end working with it as if it were work-in-progress, i.e. everything but stable (in the sense of "frozen") not mentioning that you can easily end with several installs around and wanting to use uninstalled builds too. AFAIK find_package doesn't shine on those scenarios. For the average user, I don't think that find_package offers significant advantages over the method documented in http://www.llvm.org/docs/CMake.html#embedding That said, I *think* that the automatic library dependencies system is not an impediment for supporting find_package. > CMake's export is designed to make it easy to get find_package working > well, with versioning, the ability to directly depend on the exported > project's targets, etc. One huge benefit to doing > exporting/find_package well is that it would make it easier to > separate the LLVM core from, e.g., Clang, because LLVM could export > its targets and Clang could just import them via find_package. The > rest of Clang's CMakeLists.txt files shouldn't have to change. At some point on the past, I had a patch for doing that without the need of find_package. It removed the requirement of putting clang under the LLVM source tree. It wasn't committed because I wanted to improve some aesthetics and becuase I didn't perceived too much enthusiasm about that feature. [snip] > Michael has addressed the problems that cropped up. Do we know of any > other problems that need to be addressed? I haven't looked at the patch in detail, but my experience says that issues will appear. This is not my main concern, though. The issue here is that this patch goes against the main goal of the CMake build as I implemented it: simple maintenance. As configure&&make is the most used system by the developers, the CMake build will inevitably go out of sync with the actual state of the source. So easying the job of fixing it is paramount. On the case of a removed or added source file the fix is easy, something anyone can do without having a cmake build hence doable for those who use conf&&make. Not so for a change on a library dependency: figuring out what's happening *and* the optimal point for fixing the broken dependency is not so easy and may require quite a few tentative builds. Furthermore, unnecessary dependencis will accumulate either due to failures at reflecting the optimal dependencies (i.e. putting the dependency on libraries A and B when it should go to C) or due to dependencies which are no longer required. This goes against your goal of having an easy way of seeing the project structure. There are other more subtle cases of possible brokenness, such as removed libraries that are forgotten on the list of dependencies: the problem would only be visible if you do "make clean all". Overall, my opinion is that removing automatic library dependencies will create more broken builds and will increase the time required for fixing the breakage. It will be seen as a problem too if at some point someone proposes to switch to CMake and ditch configure&&make (just remember how much fuss was about explicitly adding and removing source files to the build.) I think that the best thing we can do for our users is to provide a reliable build, even if that requires renouncing to some nifty features. At least until CMake is adopted as the official LLVM build. From sabre at nondot.org Sat Sep 11 18:02:10 2010 From: sabre at nondot.org (Chris Lattner) Date: Sat, 11 Sep 2010 23:02:10 -0000 Subject: [llvm-commits] [llvm] r113707 - /llvm/trunk/docs/CodeGenerator.html Message-ID: <20100911230210.8175B2A6C12C@llvm.org> Author: lattner Date: Sat Sep 11 18:02:10 2010 New Revision: 113707 URL: http://llvm.org/viewvc/llvm-project?rev=113707&view=rev Log: add some documentation for the most important MC-level classes along with an overview of mc and the idea of the code emission phase. Modified: llvm/trunk/docs/CodeGenerator.html Modified: llvm/trunk/docs/CodeGenerator.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/CodeGenerator.html?rev=113707&r1=113706&r2=113707&view=diff ============================================================================== --- llvm/trunk/docs/CodeGenerator.html (original) +++ llvm/trunk/docs/CodeGenerator.html Sat Sep 11 18:02:10 2010 @@ -33,7 +33,7 @@
  • The TargetJITInfo class
  • -
  • Machine code description classes +
  • The "Machine" Code Generator classes
  • +
  • The "MC" Layer + +
  • Target-independent code generation algorithms
  • -
  • Code Emission -
  • +
  • Code Emission
  • +
  • Implementing a Native Assembler
  • +
  • Target-specific Implementation Notes
    • Tail call optimization
    • @@ -100,11 +107,7 @@
      -

      Written by Chris Lattner, - Bill Wendling, - Fernando Magno Quintao - Pereira and - Jim Laskey

      +

      Written by the LLVM Team.

      @@ -123,7 +126,7 @@ suite of reusable components for translating the LLVM internal representation to the machine code for a specified target—either in assembly form (suitable for a static compiler) or in binary machine code format (usable for - a JIT compiler). The LLVM target-independent code generator consists of five + a JIT compiler). The LLVM target-independent code generator consists of six main components:

        @@ -132,10 +135,17 @@ independently of how they will be used. These interfaces are defined in include/llvm/Target/. -
      1. Classes used to represent the machine code - being generated for a target. These classes are intended to be abstract +
      2. Classes used to represent the code being + generated for a target. These classes are intended to be abstract enough to represent the machine code for any target machine. These - classes are defined in include/llvm/CodeGen/.
      3. + classes are defined in include/llvm/CodeGen/. At this level, + concepts like "constant pool entries" and "jump tables" are explicitly + exposed. + +
      4. Classes and algorithms used to represent code as the object file level, + the MC Layer. These classes represent assembly level + constructs like labels, sections, and instructions. At this level, + concepts like "constant pool entries" and "jump tables" don't exist.
      5. Target-independent algorithms used to implement various phases of native code generation (register allocation, scheduling, @@ -732,6 +742,157 @@
      + + + + + +
      + +

      +The MC Layer is used to represent and process code at the raw machine code +level, devoid of "high level" information like "constant pools", "jump tables", +"global variables" or anything like that. At this level, LLVM handles things +like label names, machine instructions, and sections in the object file. The +code in this layer is used for a number of important purposes: the tail end of +the code generator uses it to write a .s or .o file, and it is also used by the +llvm-mc tool to implement standalone machine codeassemblers and disassemblers. +

      + +

      +This section describes some of the important classes. There are also a number +of important subsystems that interact at this layer, they are described later +in this manual. +

      + +
      + + + + + +
      + +

      +MCStreamer is best thought of as an assembler API. It is an abstract API which +is implemented in different ways (e.g. to output a .s file, output an +ELF .o file, etc) but whose API correspond directly to what you see in a .s +file. MCStreamer has one method per directive, such as EmitLabel, +EmitSymbolAttribute, SwitchSection, EmitValue (for .byte, .word), etc, which +directly correspond to assembly level directives. It also has an +EmitInstruction method, which is used to output an MCInst to the streamer. +

      + +

      +This API is most important for two clients: the llvm-mc stand-alone assembler is +effectively a parser that parses a line, then invokes a method on MCStreamer. In +the code generator, the Code Emission phase of the code +generator lowers higher level LLVM IR and Machine* constructs down to the MC +layer, emitting directives through MCStreamer.

      + +

      +On the implementation side of MCStreamer, there are two major implementations: +one for writing out a .s file (MCAsmStreamer), and one for writing out a .o +file (MCObjectStreamer). MCAsmStreamer is a straight-forward implementation +that prints out a directive for each method (e.g. EmitValue -> .byte), but +MCObjectStreamer implements a full assembler. +

      + +
      + + + + +
      + +

      +The MCContext class is the owner of a variety of uniqued data structures at the +MC layer, including symbols, sections, etc. As such, this is the class that you +interact with to create symbols and sections. This class can not be subclassed. +

      + +
      + + + + +
      + +

      +The MCSymbol class represents a symbol (aka label) in the assembly file. There +are two interesting kinds of symbols: assembler temporary symbols, and normal +symbols. Assembler temporary symbols are used and processed by the assembler +but are discarded when the object file is produced. The distinction is usually +represented by adding a prefix to the label, for example "L" labels are +assembler temporary labels in MachO. +

      + +

      MCSymbols are created by MCContext and uniqued there. This means that +MCSymbols can be compared for pointer equivalence to find out if they are the +same symbol. Note that pointer inequality does not guarantee the labels will +end up at different addresses though. It's perfectly legal to output something +like this to the .s file:

      + +

      +  foo:
      +  bar:
      +    .byte 4
      +
      + +

      In this case, both the foo and bar symbols will have the same address.

      + +
      + + + + +
      + +

      +The MCSection class represents an object-file specific section. It is subclassed +by object file specific implementations (e.g. MCSectionMachO, +MCSectionCOFF, MCSectionELF) and these are created and uniqued +by MCContext. The MCStreamer has a notion of the current section, which can be +changed with the SwitchToSection method (which corresponds to a ".section" +directive in a .s file). +

      + +
      + + + + +
      + +

      +The MCInst class is a target-independent representation of an instruction. It +is a simple class (much more so than MachineInstr) +that holds a target-specific opcode and a vector of MCOperands. MCOperand, in +turn, is a simple discriminated union of three cases: 1) a simple immediate, +2) a target register ID, 3) a symbolic expression (e.g. "Lfoo-Lbar+42") as an +MCExpr. +

      + +

      MCInst is the common currency used to represent machine instructions at the +MC layer. It is the type used by the instruction encoder, the instruction +printer, and the type generated by the assembly parser and disassembler. +

      + +
      + +

      To Be Written

      + -

      To Be Written

      - -
      - Generating Assembly Code + +
      + +

      The code emission step of code generation is responsible for lowering from +the code generator abstractions (like MachineFunction, MachineInstr, etc) down +to the abstractions used by the MC layer (MCInst, +MCStreamer, etc). This is +done with a combination of several different classes: the (misnamed) +target-independent AsmPrinter class, target-specific subclasses of AsmPrinter +(such as SparcAsmPrinter), and the TargetLoweringObjectFile class.

      + +

      Since the MC layer works at the level of abstraction of object files, it +doesn't have a notion of functions, global variables etc. Instead, it thinks +about labels, directives, and instructions. A key class used at this time is +the MCStreamer class. This is an abstract API that is implemented in different +ways (e.g. to output a .s file, output an ELF .o file, etc) that is effectively +an "assembler API". MCStreamer has one method per directive, such as EmitLabel, +EmitSymbolAttribute, SwitchSection, etc, which directly correspond to assembly +level directives. +

      + +

      If you are interested in implementing a code generator for a target, there +are three important things that you have to implement for your target:

      + +
        +
      1. First, you need a subclass of AsmPrinter for your target. This class +implements the general lowering process converting MachineFunction's into MC +label constructs. The AsmPrinter base class provides a number of useful methods +and routines, and also allows you to override the lowering process in some +important ways. You should get much of the lowering for free if you are +implementing an ELF, COFF, or MachO target, because the TargetLoweringObjectFile +class implements much of the common logic.
      2. + +
      3. Second, you need to implement an instruction printer for your target. The +instruction printer takes an MCInst and renders it to a +raw_ostream as text. Most of this is automatically generated from the .td file +(when you specify something like "add $dst, $src1, $src2" in the +instructions), but you need to implement routines to print operands.
      4. + +
      5. Third, you need to implement code that lowers a MachineInstr to an MCInst, usually implemented in +"<target>MCInstLower.cpp". This lowering process is often target +specific, and is responsible for turning jump table entries, constant pool +indices, global variable addresses, etc into MCLabels as appropriate. This +translation layer is also responsible for expanding pseudo ops used by the code +generator into the actual machine instructions they correspond to. The MCInsts +that are generated by this are fed into the instruction printer or the encoder. +
      6. + +
      + +

      Finally, at your choosing, you can also implement an subclass of +MCCodeEmitter which lowers MCInst's into machine code bytes and relocations. +This is important if you want to support direct .o file emission, or would like +to implement an assembler for your target.

      +
      -

      To Be Written

      - -
      - Generating Binary Machine Code + + + +
      -

      For the JIT or .o file writer

      + +

      TODO

      +
      From wendling at apple.com Sat Sep 11 19:04:03 2010 From: wendling at apple.com (Bill Wendling) Date: Sat, 11 Sep 2010 17:04:03 -0700 Subject: [llvm-commits] [llvm] r113670 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/PeepholeOptimizer.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h In-Reply-To: <39c53e0a-1bff-4c04-96d8-5f68bb0a7ed8@l17g2000vbf.googlegroups.com> References: <20100911001350.9B7AE2A6C12C@llvm.org> <39c53e0a-1bff-4c04-96d8-5f68bb0a7ed8@l17g2000vbf.googlegroups.com> Message-ID: <394A85E5-1552-42D1-A388-E3F734AD65B1@apple.com> On Sep 11, 2010, at 5:43 AM, Gabor Greif wrote: > Bill, > > I tried to extend your approach to TSTri (as an eliminable compare > instr.) and > ANDri (as an implicit compare) with this patch: > That's what I'm attempting to do right now. :-) I want to do a bit more than just replace the TST with an AND that sets CPSR, though that's the first step. I'm introducing a separate callback instruction to handle TST (i.e., comparisons against a non-zero value). > gabor at google8:~/llvm-build$ svn diff /home/gabor/llvm/lib/Target/ARM/ > ARMBaseInstrInfo.cpp > Index: /home/gabor/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp > =================================================================== > --- /home/gabor/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp > (revision 113683) > +++ /home/gabor/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp > (working copy) > @@ -1372,6 +1372,10 @@ > SrcReg = MI->getOperand(0).getReg(); > CmpValue = MI->getOperand(1).getImm(); > return true; > + case ARM::TSTri: > + SrcReg = MI->getOperand(0).getReg(); > + CmpValue = 0; I think the TST instruction can take a compare value other than 0. The CMP instructions take 0, right? > @@ -1421,6 +1425,7 @@ > switch (MI->getOpcode()) { > default: break; > case ARM::ADDri: > + case ARM::ANDri: > case ARM::SUBri: > case ARM::t2ADDri: > case ARM::t2SUBri: > gabor at google8:~/llvm-build$ > > > BUT, it does not trigger on my example, because of > something that appears to be a bug: > > %reg16388 = PHI %reg16396, , %reg16392, ; GPR: > %reg16388,16396,16392 > %reg16389 = PHI %reg16385, , %reg16391, ; GPR: > %reg16389,16385,16391 > %reg16397 = LDR %reg16387, %reg0, 4100, pred:14, pred: > %reg0; mem:LD4[%scevgep1] GPR:%reg16397,16387 > %reg16390 = ANDri %reg16397, 3, pred:14, pred:%reg0, opt: > %reg0; GPR:%reg16390,16397 > TSTri %reg16397, 3, pred:14, pred:%reg0, %CPSR; GPR: > %reg16397 > Bcc , pred:0, pred:%CPSR > > The TST seems to use the result of the LDR instead of that of the AND! > Very fishy... > If you want to use the result of AND instead of TST in the Bcc, you'll need to say that AND implicitly defines CSPR. In the above case, it looks like the AND is basically dead (at least in this code snippet). The TST performs an "and" of the 3 to the result of LDR, which is what the AND instruction does. The only difference here is that TST sets CPSR and the AND doesn't. > The bitcode is ok: > > %tmp2 = load i8** %scevgep1 > %0 = ptrtoint i8* %tmp2 to i32 > %and = and i32 %0, 3 > %tst = icmp eq i32 %and, 0 > br i1 %tst, label %sw.bb, label %tailrecurse.switch > > What do you think? Okay to commit the above? > Below is what I have in my tree right now. It's just the skeleton of how I'd like to handle this (it does nothing right now). I like it because of how it separates out different optimization potentialities for each type of instruction, but it may be overkill... -bw Index: include/llvm/Target/TargetInstrInfo.h =================================================================== --- include/llvm/Target/TargetInstrInfo.h (revision 113706) +++ include/llvm/Target/TargetInstrInfo.h (working copy) @@ -595,6 +595,15 @@ return false; } + /// OptimizeTestInstr - See if the test instruction can be converted into + /// something more efficient. Update the iterator *only* if a transformation + /// took place. + virtual bool OptimizeTestInstr(MachineInstr * /*CmpInstr*/, + unsigned /*SrcReg*/, int /*CmpValue*/, + MachineBasicBlock::iterator &MII) const { + return false; + } + /// getNumMicroOps - Return the number of u-operations the given machine /// instruction will be decoded to on the target cpu. virtual unsigned getNumMicroOps(const MachineInstr *MI, Index: lib/Target/ARM/ARMBaseInstrInfo.cpp =================================================================== --- lib/Target/ARM/ARMBaseInstrInfo.cpp (revision 113706) +++ lib/Target/ARM/ARMBaseInstrInfo.cpp (working copy) @@ -1377,6 +1377,18 @@ return false; } +/// OptimizeTestInstr - See if we can convert the TEST instruction into an +/// equivalent AND instruction, possibly saving an instruction or two if we can +/// make AND set the flags register. +bool ARMBaseInstrInfo:: +OptimizeTestInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpValue, + MachineBasicBlock::iterator &MII) const { + if (CmpValue == 0) + return false; + + return false; +} + /// OptimizeCompareInstr - Convert the instruction supplying the argument to the /// comparison into one that sets the zero bit in the flags register. Update the /// iterator *only* if a transformation took place. Index: lib/Target/ARM/ARMBaseInstrInfo.h =================================================================== --- lib/Target/ARM/ARMBaseInstrInfo.h (revision 113706) +++ lib/Target/ARM/ARMBaseInstrInfo.h (working copy) @@ -350,6 +350,13 @@ int CmpValue, MachineBasicBlock::iterator &MII) const; + /// OptimizeTestInstr - See if we can convert the TEST instruction into an + /// equivalent AND instruction, possibly saving an instruction or two if we + /// can make AND set the flags register. + virtual bool OptimizeTestInstr(MachineInstr *CmpInstr, unsigned SrcReg, + int CmpValue, + MachineBasicBlock::iterator &MII) const; + virtual unsigned getNumMicroOps(const MachineInstr *MI, const InstrItineraryData *ItinData) const; }; Index: lib/CodeGen/PeepholeOptimizer.cpp =================================================================== --- lib/CodeGen/PeepholeOptimizer.cpp (revision 113706) +++ lib/CodeGen/PeepholeOptimizer.cpp (working copy) @@ -249,6 +249,12 @@ return true; } + // Attempt to optimize the test instruction. + if (TII->OptimizeTestInstr(MI, SrcReg, CmpValue, NextIter)) { + ++NumEliminated; + return true; + } + return false; } From dgregor at apple.com Sat Sep 11 19:11:05 2010 From: dgregor at apple.com (Douglas Gregor) Date: Sat, 11 Sep 2010 17:11:05 -0700 Subject: [llvm-commits] [PATCH][CMake] Removing LLVMLibDeps.cmake and exporting libraries for CMake clients. In-Reply-To: <87occ3di97.fsf@telefonica.net> References: <87vd6fejb9.fsf@telefonica.net> <470F86A9-0C61-47BF-B12B-1556310BFA55@apple.com> <87occ3di97.fsf@telefonica.net> Message-ID: <2FED81DC-D4AD-47A6-9863-8ACB3C2B5586@apple.com> On Sep 11, 2010, at 3:31 PM, ?scar Fuentes wrote: > Hello Doug. Glad to see my confidence on the sociability of the LLVM > developers restored ;-) :) > Douglas Gregor writes: > >>> Your patch switches from automatic to manually maintained library >>> dependencies. On the case of LLVM, that increases the workload of the >>> maintainer and it is the CMake equivalent of spaghetti code. Only a >>> strong benefit would justify that. >> >> There are numerous benefits to explicitly-maintained library dependencies: >> - It's clear what those dependencies are, which leads to better >> understanding of the system as a wholea > > The file cmake/modules/LLVMLibDeps.cmake concentrates all those > dependencies, so if you want to get the whole picture of the library > dependencies, you have a single point to look at, instead of dozens of > files scattered all around the source tree. If you want the whole picture, it's slightly better to have one large list of dependencies. That said, text is a horrible format for such a task, and it's far more likely that someone wanted to look at the whole picture would actually want a picture, e.g., as generated by GraphViz. I do have a few issues with putting all of the dependencies in a single file: 1) People forget about it when they make changes. LLVM developers have gotten fairly good at updating CMakeLists.txt when they change the corresponding makefile (finally!), because they live alongside the Makefiles. This other file off in an apparently-unrelated subdirectory gets forgotten. 2) Most of the time, we want to reason about dependencies locally ("I added this feature, and now my library depends on..."), and a single file makes that harder. 3) It's unclear how a "single file" works for multiple projects. For example, LLVMLibDeps didn't have Clang's dependencies, because Clang is in a different repository. Should Clang have its own ClangLibDeps? Should they all be merged together? We actually had a mix of LLVMLibDeps dependencies and per-CMakeLists.txt dependencies. > It is possible to make that file more redable, if you wish. > >> - Changes in dependencies, which are fundamentally architectural >> changes, become obvious when they happen > > Again, looking at the history of LLVMLibDeps.cmake you can see all those > changes at a glance. Yes, agreed. >> - Dependencies can make their way into other tools far more >> easily, e.g., component-based CPack installers (e.g., >> http://www.paraview.org/Wiki/CMake:Component_Install_With_CPack) > > CPack works fine with the automatic library dependency system. Please > note that the automatic system ends using target_link_libraries anyways, > so putting it explicitly on the corresponding CMakeLists.txt makes no > difference for tools that require its existente. I'm specifically referring to dependencies in component-based installers, which are separate from those dependencies and can be at a higher level of granularity (e.g., dependencies between groups of libraries in the graphical installer). >> For one, find_package is the standard CMake way of finding a package, >> so we should be providing that to CMake users. > > That sounds good, but we shall think on terms of the specific > characteristics of LLVM. find_package works fine for libraries such as > zlib, that is, components that you install on standard places because > they are required by some other package and which are stable and remain > unchanged until a bug is found or a new version is required. > > I don't think LLVM fits there. Either you have LLVM for working *on* it, > or you are tracking its development. In any case LLVM is not just "a > library," but THE library. And given how LLVM is developed you end > working with it as if it were work-in-progress, i.e. everything but > stable (in the sense of "frozen") not mentioning that you can easily end > with several installs around and wanting to use uninstalled builds > too. AFAIK find_package doesn't shine on those scenarios. My understanding of CMake's export feature is that it helps with this, too; you can use CMake variables to push find_package toward, for example, a build tree of LLVM in your project that depends on LLVM. > For the average user, I don't think that find_package offers significant > advantages over the method documented in > > http://www.llvm.org/docs/CMake.html#embedding I think the advantage is familiarity; we'd fit better into the general CMake ecosystem if we follow their conventions. > That said, I *think* that the automatic library dependencies system is > not an impediment for supporting find_package. No, it should be separate. Indeed, these two pieces of the patch (dependencies changes and export changes) should have been separated. >> CMake's export is designed to make it easy to get find_package working >> well, with versioning, the ability to directly depend on the exported >> project's targets, etc. One huge benefit to doing >> exporting/find_package well is that it would make it easier to >> separate the LLVM core from, e.g., Clang, because LLVM could export >> its targets and Clang could just import them via find_package. The >> rest of Clang's CMakeLists.txt files shouldn't have to change. > > At some point on the past, I had a patch for doing that without the need > of find_package. It removed the requirement of putting clang under the > LLVM source tree. It wasn't committed because I wanted to improve some > aesthetics and becuase I didn't perceived too much enthusiasm about that > feature. You'll likely get more enthusiasm as Clang and LLVM get bigger and bigger. The Xcode project for Clang+LLVM is *huge*, and things will get much more interesting when we get a CMake'ified lldb (which depends on Clang+LLVM). We have a lot more subprojects than we had even a year ago, and they're not small. > The issue here is that this patch goes against the main goal of the > CMake build as I implemented it: simple maintenance. As configure&&make > is the most used system by the developers, the CMake build will > inevitably go out of sync with the actual state of the source. Recently, this hasn't been much of a problem. LLVM developers have gotten accustomed to updating CMakeLists.txt files, and we now have buildbots that use the CMake build system (on Windows), so I find myself having to fix CMakeLists.txt files far less often than even a few months ago. Plus, there are at least several Clang developers that use the CMake build system on a daily basis. When problems crop up, they get fixed fast. > So > easying the job of fixing it is paramount. On the case of a removed or > added source file the fix is easy, something anyone can do without > having a cmake build hence doable for those who use conf&&make. Not so > for a change on a library dependency: figuring out what's happening > *and* the optimal point for fixing the broken dependency is not so easy > and may require quite a few tentative builds. Furthermore, unnecessary > dependencis will accumulate either due to failures at reflecting the > optimal dependencies (i.e. putting the dependency on libraries A and B > when it should go to C) or due to dependencies which are no longer > required. This goes against your goal of having an easy way of seeing > the project structure. Mistakes can creep in anywhere, and when we find them, we'll fix them. Automatic checking (as Rafael mentioned) would certainly help, but a little common sense goes a long way toward keeping things consistent, and I believe that LLVM developers are careful enough that these issues won't turn into serious problems. > There are other more subtle cases of possible > brokenness, such as removed libraries that are forgotten on the list of > dependencies: the problem would only be visible if you do "make clean > all". The buildbots do a "make clean all" every hour or so; we'd catch such an error quickly. > Overall, my opinion is that removing automatic library dependencies will > create more broken builds and will increase the time required for fixing > the breakage. It will be seen as a problem too if at some point someone > proposes to switch to CMake and ditch configure&&make (just remember how > much fuss was about explicitly adding and removing source files to the > build.) I think that the best thing we can do for our users is to > provide a reliable build, even if that requires renouncing to some nifty > features. At least until CMake is adopted as the official LLVM build. Let's say that we adopt CMake as the official LLVM build system tomorrow. Would you still want implicit dependencies, or would you then favor explicit dependencies? - Doug From wendling at apple.com Sat Sep 11 19:22:45 2010 From: wendling at apple.com (Bill Wendling) Date: Sat, 11 Sep 2010 17:22:45 -0700 Subject: [llvm-commits] [llvm] r113670 - in /llvm/trunk: include/llvm/Target/TargetInstrInfo.h lib/CodeGen/PeepholeOptimizer.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h In-Reply-To: <2da5ae35-a8e5-4373-8732-c9073b95b598@q2g2000vbk.googlegroups.com> References: <20100911001350.9B7AE2A6C12C@llvm.org> <2da5ae35-a8e5-4373-8732-c9073b95b598@q2g2000vbk.googlegroups.com> Message-ID: <5292DDBE-195D-4E8E-8462-7650E7C3E649@apple.com> On Sep 11, 2010, at 12:49 AM, Gabor Greif wrote: > Bill, > > you might be interested in my dabbling attempts > with http://llvm.org/bugs/show_bug.cgi?id=8125 > The x86 peephole already manages to eliminate > the test after the 'and', It would be interesting > to see whether ARM does too. > Btw., my commit is not really restricted to 'and', > any operation that sets the zero flag will do. > > A.t.m. (before your changes) I got: > LBB0_1: @ %tailrecurse > @ =>This Inner Loop Header: > Depth=1 > ldr lr, [r2, #-4] > and r4, lr, #3 > tst lr, #3 > beq LBB0_4 > I saw your patch go through. As with your other code, I don't understand it fully. :) It's certainly an interesting optimization. But I think that we would still need the peephole optimizer for ARM (and PPC?). X86's instructions either always set the EFLAGS register or not. A lot of ARM instructions may set CSPR, but they don't have to. And it appears that that decision needs to wait until after instruction selection... -bw From ofv at wanadoo.es Sat Sep 11 19:29:29 2010 From: ofv at wanadoo.es (=?utf-8?Q?=C3=93scar_Fuentes?=) Date: Sun, 12 Sep 2010 02:29:29 +0200 Subject: [llvm-commits] [PATCH][CMake] Removing LLVMLibDeps.cmake and exporting libraries for CMake clients. References: <87vd6fejb9.fsf@telefonica.net> <470F86A9-0C61-47BF-B12B-1556310BFA55@apple.com> <87occ3di97.fsf@telefonica.net> Message-ID: <87k4mrdct2.fsf@telefonica.net> ?scar Fuentes writes: [snip] >> Michael has addressed the problems that cropped up. Do we know of any >> other problems that need to be addressed? > > I haven't looked at the patch in detail, but my experience says that > issues will appear. This is not my main concern, though. Just tried the build on Linux/AMD64, and it fails with this: Linking CXX executable ../../bin/llvm-mc ../../lib/libLLVMPIC16AsmPrinter.a(PIC16AsmPrinter.cpp.o): In function `llvm::PIC16AsmPrinter::doFinalization(llvm::Module&)': PIC16AsmPrinter.cpp:(.text+0x12a2): undefined reference to `llvm::PIC16DbgInfo::EndModule(llvm::Module&)' ../../lib/libLLVMPIC16AsmPrinter.a(PIC16AsmPrinter.cpp.o): In function `llvm::PIC16AsmPrinter::doInitialization(llvm::Module&)': PIC16AsmPrinter.cpp:(.text+0x1f86): undefined reference to `llvm::PIC16DbgInfo::BeginModule(llvm::Module&)' ../../lib/libLLVMPIC16AsmPrinter.a(PIC16AsmPrinter.cpp.o): In function `llvm::PIC16AsmPrinter::runOnMachineFunction(llvm::MachineFunction&)': PIC16AsmPrinter.cpp:(.text+0x3be4): undefined reference to `llvm::PIC16DbgInfo::BeginFunction(llvm::MachineFunction const&)' PIC16AsmPrinter.cpp:(.text+0x3f3e): undefined reference to `llvm::PIC16DbgInfo::ChangeDebugLoc(llvm::MachineFunction const&, llvm::DebugLoc const&, bool)' PIC16AsmPrinter.cpp:(.text+0x3fcf): undefined reference to `llvm::PIC16DbgInfo::EndFunction(llvm::MachineFunction const&)' collect2: ld returned 1 exit status make[2]: *** [bin/llvm-mc] Error 1 make[1]: *** [tools/llvm-mc/CMakeFiles/llvm-mc.dir/all] Error 2 make: *** [all] Error 2 As Michael reported that the build worked for him on Linux yesterday, it would be *very* interesting to analyze this failure. It can be illustrative. From ofv at wanadoo.es Sat Sep 11 21:27:15 2010 From: ofv at wanadoo.es (=?utf-8?Q?=C3=93scar?= Fuentes) Date: Sun, 12 Sep 2010 04:27:15 +0200 Subject: [llvm-commits] [PATCH][CMake] Removing LLVMLibDeps.cmake and exporting libraries for CMake clients. In-Reply-To: <2FED81DC-D4AD-47A6-9863-8ACB3C2B5586@apple.com> (Douglas Gregor's message of "Sat, 11 Sep 2010 17:11:05 -0700") References: <87vd6fejb9.fsf@telefonica.net> <470F86A9-0C61-47BF-B12B-1556310BFA55@apple.com> <87occ3di97.fsf@telefonica.net> <2FED81DC-D4AD-47A6-9863-8ACB3C2B5586@apple.com> Message-ID: <878w37d7cs.fsf@telefonica.net> Douglas Gregor writes: > If you want the whole picture, it's slightly better to have one large > list of dependencies. That said, text is a horrible format for such a > task, and it's far more likely that someone wanted to look at the > whole picture would actually want a picture, e.g., as generated by > GraphViz. Again, extracting GraphViz data or XML describing dependencies from CMake is unaffected by the automatic dependency system. > I do have a few issues with putting all of the dependencies in a single file: > > 1) People forget about it when they make changes. LLVM > developers have gotten fairly good at updating CMakeLists.txt > when they change the corresponding makefile (finally!), because > they live alongside the Makefiles. This other file off in an > apparently-unrelated subdirectory gets forgotten. > > 2) Most of the time, we want to reason about dependencies > locally ("I added this feature, and now my library depends > on..."), and a single file makes that harder. If explicitly keeping library dependencies are so good, why do you keep using the llvm-config script on the configure&&make build? Why llvm-config was introduced on the first place? > 3) It's unclear how a "single file" works for multiple > projects. For example, LLVMLibDeps didn't have Clang's > dependencies, because Clang is in a different repository. Should > Clang have its own ClangLibDeps? Should they all be merged > together? We actually had a mix of LLVMLibDeps dependencies and > per-CMakeLists.txt dependencies. Since I implemented the CMake build on Clang, I lost touch with it. Hence can't comment. But I don't see how the existence of LLVMLibDeps is an inconvenience for Clang. [snip] >> CPack works fine with the automatic library dependency system. Please >> note that the automatic system ends using target_link_libraries anyways, >> so putting it explicitly on the corresponding CMakeLists.txt makes no >> difference for tools that require its existente. > > I'm specifically referring to dependencies in component-based > installers, which are separate from those dependencies and can be at a > higher level of granularity (e.g., dependencies between groups of > libraries in the graphical installer). Again, this is independent of where you put target_link_libraries, on each CMakeLists.txt or on some .cmake script. > My understanding of CMake's export feature is that it helps with this, > too; you can use CMake variables to push find_package toward, for > example, a build tree of LLVM in your project that depends on LLVM. In any case, this shall be documented on docs/CMake.html, with examples for the case of multiple installs. I wouldn't never approve the change until it includes updates to the documentation. >> For the average user, I don't think that find_package offers significant >> advantages over the method documented in >> >> http://www.llvm.org/docs/CMake.html#embedding > > I think the advantage is familiarity; we'd fit better into the general > CMake ecosystem if we follow their conventions. I'm more concerned about fitting into the LLVM ecosystem :-) [snip] > Mistakes can creep in anywhere, and when we find them, we'll fix them. The point about the automatic system is that it avoids mistakes and makes fixes unnecessary. [snip] > Let's say that we adopt CMake as the official LLVM build system > tomorrow. Would you still want implicit dependencies, or would you > then favor explicit dependencies? I think that automatically updated library dependencies ("implicit" is not the right word, as they are very explicitly stated on LLVMLibDeps.cmake) saves work and are more accurate than manually mantained ones. If you want to stay on touch with the structure of the project, you look at LLVMLibDeps.cmake or ask CMake for a XML or GraphViz file that describes it. Doug, if you are so convinced about the virtues of manually maintained library dependencies for LLVM, go ahead, keep the change on the repo. After all, if I'm right about my concerns it doesn't mean complete disaster. But I'll like to be sure that you are not basing your decision on false premises and that you are aware of the social and workload implications. I know you are committed to a high quality CMake build and possibly can devote more energy than me to that cause. So I'm willing to silence my opposition and pass the responsibility of driving the evolution of the CMake build to you and others who have their own ideas and want to see them materialized. I hate to stop people from doing things and think that I can't always keep others from making mistakes. Not to mention that sometimes it is me who is mistaken ;-) From echristo at apple.com Sat Sep 11 22:26:36 2010 From: echristo at apple.com (Eric Christopher) Date: Sun, 12 Sep 2010 03:26:36 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r113710 - in /llvm-gcc-4.2/trunk/gcc: config/arm/llvm-arm-target.h config/arm/llvm-arm.cpp llvm-abi-default.cpp llvm-abi.h llvm-convert.cpp llvm-types.cpp Message-ID: <20100912032637.086E92A6C12C@llvm.org> Author: echristo Date: Sat Sep 11 22:26:36 2010 New Revision: 113710 URL: http://llvm.org/viewvc/llvm-project?rev=113710&view=rev Log: Revert 113694 in an attempt to fix the buildbots. Modified: llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm-target.h llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp llvm-gcc-4.2/trunk/gcc/llvm-abi.h llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Modified: llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm-target.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm-target.h?rev=113710&r1=113709&r2=113710&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm-target.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm-target.h Sat Sep 11 22:26:36 2010 @@ -55,15 +55,6 @@ #define LLVM_SHOULD_PASS_AGGREGATE_IN_MIXED_REGS(T, TY, CC, E) \ llvm_arm_should_pass_aggregate_in_mixed_regs((T), (TY), (CC), (E)) -struct DefaultABIClient; -extern bool -llvm_arm_try_pass_aggregate_custom(tree, std::vector&, - CallingConv::ID&, - struct DefaultABIClient*); - -#define LLVM_TRY_PASS_AGGREGATE_CUSTOM(T, E, CC, C) \ - llvm_arm_try_pass_aggregate_custom((T), (E), (CC), (C)) - extern bool llvm_arm_aggregate_partially_passed_in_regs(std::vector&, std::vector&, Modified: llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp?rev=113710&r1=113709&r2=113710&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp Sat Sep 11 22:26:36 2010 @@ -2557,91 +2557,6 @@ } } -static unsigned count_num_words(std::vector &ScalarElts) { - unsigned NumWords = 0; - for (unsigned i = 0, e = ScalarElts.size(); i != e; ++i) { - const Type *Ty = ScalarElts[i]; - if (Ty->isPointerTy()) { - NumWords++; - } else if (Ty->isIntegerTy()) { - const unsigned TypeSize = Ty->getPrimitiveSizeInBits(); - const unsigned NumWordsForType = (TypeSize + 31) / 32; - - NumWords += NumWordsForType; - } else { - assert (0 && "Unexpected type."); - } - } - return NumWords; -} - -// This function is used only on AAPCS. The difference from the generic -// handling of arguments is that arguments larger than 32 bits are split -// and padding arguments are added as necessary for alignment. This makes -// the IL a bit more explicit about how arguments are handled. -extern bool -llvm_arm_try_pass_aggregate_custom(tree type, - std::vector& ScalarElts, - CallingConv::ID& CC, - struct DefaultABIClient* C) { - if (CC != CallingConv::ARM_AAPCS && CC != CallingConv::C) - return false; - - if (CC == CallingConv::C && !TARGET_AAPCS_BASED) - return false; - - if (TARGET_HARD_FLOAT_ABI) - return false; - const Type *Ty = ConvertType(type); - if (Ty->isPointerTy()) - return false; - - const unsigned Size = TREE_INT_CST_LOW(TYPE_SIZE(type))/8; - const unsigned Alignment = TYPE_ALIGN(type)/8; - const unsigned NumWords = count_num_words(ScalarElts); - const bool AddPad = Alignment >= 8 && (NumWords % 2); - - // First, build a type that will be bitcast to the original one and - // from where elements will be extracted. - std::vector Elts; - const Type* Int32Ty = Type::getInt32Ty(getGlobalContext()); - const unsigned NumRegularArgs = Size / 4; - for (unsigned i = 0; i < NumRegularArgs; ++i) { - Elts.push_back(Int32Ty); - } - const unsigned RestSize = Size % 4; - const llvm::Type *RestType = NULL; - if (RestSize> 2) { - RestType = Type::getInt32Ty(getGlobalContext()); - } else if (RestSize > 1) { - RestType = Type::getInt16Ty(getGlobalContext()); - } else if (RestSize > 0) { - RestType = Type::getInt8Ty(getGlobalContext()); - } - if (RestType) - Elts.push_back(RestType); - const StructType *STy = StructType::get(getGlobalContext(), Elts, false); - - if (AddPad) { - ScalarElts.push_back(Int32Ty); - C->HandlePad(Int32Ty); - } - - for (unsigned i = 0; i < NumRegularArgs; ++i) { - C->EnterField(i, STy); - C->HandleScalarArgument(Int32Ty, 0); - ScalarElts.push_back(Int32Ty); - C->ExitField(); - } - if (RestType) { - C->EnterField(NumRegularArgs, STy); - C->HandleScalarArgument(RestType, 0, RestSize); - ScalarElts.push_back(RestType); - C->ExitField(); - } - return true; -} - // Target hook for llvm-abi.h. It returns true if an aggregate of the // specified type should be passed in a number of registers of mixed types. // It also returns a vector of types that correspond to the registers used Modified: llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp?rev=113710&r1=113709&r2=113710&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp Sat Sep 11 22:26:36 2010 @@ -8,8 +8,7 @@ /// return type. It potentially breaks down the argument and invokes methods /// on the client that indicate how its pieces should be handled. This /// handles things like returning structures via hidden parameters. -void DefaultABI::HandleReturnType(tree type, tree fn, bool isBuiltin, - std::vector &ScalarElts) { +void DefaultABI::HandleReturnType(tree type, tree fn, bool isBuiltin) { unsigned Offset = 0; const Type *Ty = ConvertType(type); if (Ty->isVectorTy()) { @@ -53,9 +52,7 @@ // FIXME: should return the hidden first argument for some targets // (e.g. ELF i386). - const PointerType *PTy = Ty->getPointerTo(); - C.HandleAggregateShadowResult(PTy, false); - ScalarElts.push_back(PTy); + C.HandleAggregateShadowResult(Ty->getPointerTo(), false); } } Modified: llvm-gcc-4.2/trunk/gcc/llvm-abi.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-abi.h?rev=113710&r1=113709&r2=113710&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-abi.h (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-abi.h Sat Sep 11 22:26:36 2010 @@ -396,8 +396,7 @@ /// return type. It potentially breaks down the argument and invokes methods /// on the client that indicate how its pieces should be handled. This /// handles things like returning structures via hidden parameters. - void HandleReturnType(tree type, tree fn, bool isBuiltin, - std::vector &ScalarElts); + void HandleReturnType(tree type, tree fn, bool isBuiltin); /// HandleArgument - This is invoked by the target-independent code for each /// argument type passed into the function. It potentially breaks down the Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=113710&r1=113709&r2=113710&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Sat Sep 11 22:26:36 2010 @@ -673,19 +673,17 @@ FunctionPrologArgumentConversion Client(FnDecl, AI, Builder, CallingConv); DefaultABI ABIConverter(Client); - // Scalar arguments processed so far. - std::vector ScalarArgs; - // Handle the DECL_RESULT. ABIConverter.HandleReturnType(TREE_TYPE(TREE_TYPE(FnDecl)), FnDecl, - DECL_BUILT_IN(FnDecl), - ScalarArgs); + DECL_BUILT_IN(FnDecl)); // Remember this for use by FinishFunctionBody. ReturnOffset = Client.Offset; // Prepend the static chain (if any) to the list of arguments. tree Args = static_chain ? static_chain : DECL_ARGUMENTS(FnDecl); + // Scalar arguments processed so far. + std::vector ScalarArgs; while (Args) { const char *Name = "unnamed_arg"; if (DECL_NAME(Args)) Name = IDENTIFIER_POINTER(DECL_NAME(Args)); @@ -3014,17 +3012,16 @@ DefaultABI ABIConverter(Client); // Handle the result, including struct returns. - std::vector ScalarArgs; ABIConverter.HandleReturnType(TREE_TYPE(exp), fndecl ? fndecl : exp, - fndecl ? DECL_BUILT_IN(fndecl) : false, - ScalarArgs); + fndecl ? DECL_BUILT_IN(fndecl) : false); // Pass the static chain, if any, as the first parameter. if (TREE_OPERAND(exp, 2)) CallOperands.push_back(Emit(TREE_OPERAND(exp, 2), 0)); // Loop over the arguments, expanding them and adding them to the op list. + std::vector ScalarArgs; for (tree arg = TREE_OPERAND(exp, 1); arg; arg = TREE_CHAIN(arg)) { tree type = TREE_TYPE(TREE_VALUE(arg)); const Type *ArgTy = ConvertType(type); Modified: llvm-gcc-4.2/trunk/gcc/llvm-types.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-types.cpp?rev=113710&r1=113709&r2=113710&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-types.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Sat Sep 11 22:26:36 2010 @@ -1082,10 +1082,8 @@ TARGET_ADJUST_LLVM_CC(CallingConv, type); #endif - std::vector ScalarArgs; // Builtins are always prototyped, so this isn't one. - ABIConverter.HandleReturnType(ReturnType, current_function_decl, false, - ScalarArgs); + ABIConverter.HandleReturnType(ReturnType, current_function_decl, false); SmallVector Attrs; @@ -1112,6 +1110,7 @@ Attrs.push_back(AttributeWithIndex::get(ArgTys.size(), Attribute::StructRet)); + std::vector ScalarArgs; if (static_chain) { // Pass the static chain as the first parameter. ABIConverter.HandleArgument(TREE_TYPE(static_chain), ScalarArgs); @@ -1153,10 +1152,8 @@ TARGET_ADJUST_LLVM_CC(CallingConv, type); #endif - std::vector ScalarArgs; ABIConverter.HandleReturnType(TREE_TYPE(type), current_function_decl, - decl ? DECL_BUILT_IN(decl) : false, - ScalarArgs); + decl ? DECL_BUILT_IN(decl) : false); // Compute attributes for return type (and function attributes). SmallVector Attrs; @@ -1221,6 +1218,7 @@ Attrs.push_back(AttributeWithIndex::get(ArgTypes.size(), Attribute::StructRet | Attribute::NoAlias)); + std::vector ScalarArgs; if (static_chain) { // Pass the static chain as the first parameter. ABIConverter.HandleArgument(TREE_TYPE(static_chain), ScalarArgs); From bigcheesegs at gmail.com Sat Sep 11 22:47:31 2010 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Sun, 12 Sep 2010 03:47:31 -0000 Subject: [llvm-commits] [llvm] r113712 - /llvm/trunk/lib/Target/PIC16/AsmPrinter/CMakeLists.txt Message-ID: <20100912034731.DF5E02A6C12C@llvm.org> Author: mspencer Date: Sat Sep 11 22:47:31 2010 New Revision: 113712 URL: http://llvm.org/viewvc/llvm-project?rev=113712&view=rev Log: CMake: Fix mingw32 build. Modified: llvm/trunk/lib/Target/PIC16/AsmPrinter/CMakeLists.txt Modified: llvm/trunk/lib/Target/PIC16/AsmPrinter/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/AsmPrinter/CMakeLists.txt?rev=113712&r1=113711&r2=113712&view=diff ============================================================================== --- llvm/trunk/lib/Target/PIC16/AsmPrinter/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/PIC16/AsmPrinter/CMakeLists.txt Sat Sep 11 22:47:31 2010 @@ -6,4 +6,9 @@ add_llvm_library(LLVMPIC16AsmPrinter PIC16AsmPrinter.cpp ) + +target_link_libraries(LLVMPIC16AsmPrinter + LLVMPIC16CodeGen + ) + add_dependencies(LLVMPIC16AsmPrinter PIC16CodeGenTable_gen) From echristo at apple.com Sun Sep 12 01:09:23 2010 From: echristo at apple.com (Eric Christopher) Date: Sun, 12 Sep 2010 06:09:23 -0000 Subject: [llvm-commits] [llvm] r113720 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineAndOrXor.cpp test/CodeGen/ARM/fast-isel.ll test/Transforms/InstCombine/and-or-inversion.ll test/Transforms/InstCombine/cast.ll test/Transforms/InstCombine/or.ll test/Transforms/InstCombine/xor2.ll Message-ID: <20100912060923.4A1722A6C12C@llvm.org> Author: echristo Date: Sun Sep 12 01:09:23 2010 New Revision: 113720 URL: http://llvm.org/viewvc/llvm-project?rev=113720&view=rev Log: Revert 113679, it was causing an infinite loop in a testcase that I've sent on to Owen. Removed: llvm/trunk/test/Transforms/InstCombine/and-or-inversion.ll Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp llvm/trunk/test/CodeGen/ARM/fast-isel.ll llvm/trunk/test/Transforms/InstCombine/cast.ll llvm/trunk/test/Transforms/InstCombine/or.ll llvm/trunk/test/Transforms/InstCombine/xor2.ll Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp?rev=113720&r1=113719&r2=113720&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp Sun Sep 12 01:09:23 2010 @@ -207,26 +207,12 @@ } break; case Instruction::Or: - if (Op->hasOneUse()){ - if (Together != OpRHS) { - // (X | C1) & C2 --> (X | (C1&C2)) & C2 - Value *Or = Builder->CreateOr(X, Together); - Or->takeName(Op); - return BinaryOperator::CreateAnd(Or, AndRHS); - } - - ConstantInt *TogetherCI = dyn_cast(Together); - if (TogetherCI && !TogetherCI->isZero()){ - // (X | C1) & C2 --> (X & (C2^(C1&C2))) | C1 - // NOTE: This reduces the number of bits set in the & mask, which - // can expose opportunities for store narrowing. - Together = ConstantExpr::getXor(AndRHS, Together); - Value *And = Builder->CreateAnd(X, Together); - And->takeName(Op); - return BinaryOperator::CreateOr(And, OpRHS); - } + if (Op->hasOneUse() && Together != OpRHS) { + // (X | C1) & C2 --> (X | (C1&C2)) & C2 + Value *Or = Builder->CreateOr(X, Together); + Or->takeName(Op); + return BinaryOperator::CreateAnd(Or, AndRHS); } - break; case Instruction::Add: if (Op->hasOneUse()) { @@ -1957,17 +1943,6 @@ } } - // Note: If we've gotten to the point of visiting the outer OR, then the - // inner one couldn't be simplified. If it was a constant, then it won't - // be simplified by a later pass either, so we try swapping the inner/outer - // ORs in the hopes that we'll be able to simplify it this way. - // (X|C) | V --> (X|V) | C - if (Op0->hasOneUse() && match(Op0, m_Or(m_Value(A), m_ConstantInt(C1)))) { - Value *Inner = Builder->CreateOr(Op0, Op1); - Inner->takeName(Op0); - return BinaryOperator::CreateOr(Inner, C1); - } - return Changed ? &I : 0; } Modified: llvm/trunk/test/CodeGen/ARM/fast-isel.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel.ll?rev=113720&r1=113719&r2=113720&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fast-isel.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fast-isel.ll Sun Sep 12 01:09:23 2010 @@ -15,6 +15,22 @@ ret i32 %add } +define float @fp_ops(float %a, float %b) nounwind { +entry: + %a.addr = alloca float, align 4 + %b.addr = alloca float, align 4 + store float %a, float* %a.addr + store float %b, float* %b.addr + %tmp = load float* %a.addr + %tmp1 = load float* %b.addr + %mul = fmul float %tmp, %tmp1 + %tmp2 = load float* %b.addr + %tmp3 = load float* %a.addr + %mul2 = fmul float %tmp2, %tmp3 + %add = fadd float %mul, %mul2 + ret float %mul +} + define i32* @foo(i32* %p, i32* %q, i32** %z) nounwind { entry: %r = load i32* %p Removed: llvm/trunk/test/Transforms/InstCombine/and-or-inversion.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/and-or-inversion.ll?rev=113719&view=auto ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/and-or-inversion.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/and-or-inversion.ll (removed) @@ -1,13 +0,0 @@ -; RUN: opt -S -instcombine < %s | FileCheck %s -; - -; CHECK: @func -define i32 @func(i32 %a) nounwind ssp align 2 { -entry: -; CHECK: and i32 %a, -256 - %0 = or i32 %a, 8 -; CHECK: or i32 %0, 8 - %1 = and i32 %0, -248 - ret i32 %1 -; CHECK: } -} Modified: llvm/trunk/test/Transforms/InstCombine/cast.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/cast.ll?rev=113720&r1=113719&r2=113720&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/cast.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/cast.ll Sun Sep 12 01:09:23 2010 @@ -437,8 +437,8 @@ ret i64 %E ; CHECK: @test47 ; CHECK-NEXT: %B = sext i8 %A to i64 -; CHECK-NEXT: %C = and i64 %B, 4294967253 -; CHECK-NEXT: %E = or i64 %C, 42 +; CHECK-NEXT: %C = or i64 %B, 42 +; CHECK-NEXT: %E = and i64 %C, 4294967295 ; CHECK-NEXT: ret i64 %E } @@ -508,8 +508,8 @@ ret i32 %E ; CHECK: @test52 ; CHECK-NEXT: %B = trunc i64 %A to i32 -; CHECK-NEXT: %C = and i32 %B, 7224 -; CHECK-NEXT: %D = or i32 %C, 32962 +; CHECK-NEXT: %C = or i32 %B, 32962 +; CHECK-NEXT: %D = and i32 %C, 40186 ; CHECK-NEXT: ret i32 %D } @@ -521,8 +521,8 @@ ret i64 %E ; CHECK: @test53 ; CHECK-NEXT: %B = zext i32 %A to i64 -; CHECK-NEXT: %C = and i64 %B, 7224 -; CHECK-NEXT: %D = or i64 %C, 32962 +; CHECK-NEXT: %C = or i64 %B, 32962 +; CHECK-NEXT: %D = and i64 %C, 40186 ; CHECK-NEXT: ret i64 %D } @@ -534,8 +534,8 @@ ret i32 %E ; CHECK: @test54 ; CHECK-NEXT: %B = trunc i64 %A to i32 -; CHECK-NEXT: %C = and i32 %B, 7224 -; CHECK-NEXT: %D = or i32 %C, -32574 +; CHECK-NEXT: %C = or i32 %B, -32574 +; CHECK-NEXT: %D = and i32 %C, -25350 ; CHECK-NEXT: ret i32 %D } @@ -547,8 +547,8 @@ ret i64 %E ; CHECK: @test55 ; CHECK-NEXT: %B = zext i32 %A to i64 -; CHECK-NEXT: %C = and i64 %B, 7224 -; CHECK-NEXT: %D = or i64 %C, -32574 +; CHECK-NEXT: %C = or i64 %B, -32574 +; CHECK-NEXT: %D = and i64 %C, -25350 ; CHECK-NEXT: ret i64 %D } @@ -584,8 +584,8 @@ ; CHECK: @test58 ; CHECK-NEXT: %C = lshr i64 %A, 8 -; CHECK-NEXT: %D = and i64 %C, 16777087 -; CHECK-NEXT: %E = or i64 %D, 128 +; CHECK-NEXT: %D = or i64 %C, 128 +; CHECK-NEXT: %E = and i64 %D, 16777215 ; CHECK-NEXT: ret i64 %E } Modified: llvm/trunk/test/Transforms/InstCombine/or.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/or.ll?rev=113720&r1=113719&r2=113720&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/or.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/or.ll Sun Sep 12 01:09:23 2010 @@ -316,8 +316,8 @@ %E = or i32 %D, %C ret i32 %E ; CHECK: @test30 -; CHECK: %D = and i32 %A, -58312 -; CHECK: %E = or i32 %D, 32962 +; CHECK: %B = or i32 %A, 32962 +; CHECK: %E = and i32 %B, -25350 ; CHECK: ret i32 %E } @@ -332,8 +332,8 @@ %F = or i64 %D, %E ret i64 %F ; CHECK: @test31 -; CHECK-NEXT: %E1 = and i64 %A, 4294908984 -; CHECK-NEXT: %F = or i64 %E1, 32962 +; CHECK-NEXT: %bitfield = or i64 %A, 32962 +; CHECK-NEXT: %F = and i64 %bitfield, 4294941946 ; CHECK-NEXT: ret i64 %F } @@ -367,12 +367,3 @@ ; CHECK-NEXT: or i32 %X, %Y ; CHECK-NEXT: ret } - -define i32 @test35(i32 %a, i32 %b) { - %1 = or i32 %a, 1135 - %2 = or i32 %1, %b - ret i32 %2 - ; CHECK: @test35 - ; CHECK-NEXT: or i32 %a, %b - ; CHECK-NEXT: or i32 %1, 1135 -} Modified: llvm/trunk/test/Transforms/InstCombine/xor2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/xor2.ll?rev=113720&r1=113719&r2=113720&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/xor2.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/xor2.ll Sun Sep 12 01:09:23 2010 @@ -34,7 +34,7 @@ define i32 @test3(i32 %tmp1) { ; CHECK: @test3 ; CHECK-NEXT: and i32 %tmp1, 32 -; CHECK-NEXT: or i32 %ovm, 8 +; CHECK-NEXT: or i32 %tmp, 8 ; CHECK-NEXT: ret i32 %ovm = or i32 %tmp1, 145 %ov31 = and i32 %ovm, 177 From espindola at google.com Sun Sep 12 02:23:54 2010 From: espindola at google.com (Rafael Espindola) Date: Sun, 12 Sep 2010 03:23:54 -0400 Subject: [llvm-commits] [llvm-gcc-4.2] r113710 - in /llvm-gcc-4.2/trunk/gcc: config/arm/llvm-arm-target.h config/arm/llvm-arm.cpp llvm-abi-default.cpp llvm-abi.h llvm-convert.cpp llvm-types.cpp In-Reply-To: <20100912032637.086E92A6C12C@llvm.org> References: <20100912032637.086E92A6C12C@llvm.org> Message-ID: Thanks. Do you have a testcase? For some reason I got no email from the bots... On 11 September 2010 23:26, Eric Christopher wrote: > Author: echristo > Date: Sat Sep 11 22:26:36 2010 > New Revision: 113710 > > URL: http://llvm.org/viewvc/llvm-project?rev=113710&view=rev > Log: > Revert 113694 in an attempt to fix the buildbots. > > Modified: > ? ?llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm-target.h > ? ?llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp > ? ?llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp > ? ?llvm-gcc-4.2/trunk/gcc/llvm-abi.h > ? ?llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp > ? ?llvm-gcc-4.2/trunk/gcc/llvm-types.cpp > > Modified: llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm-target.h > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm-target.h?rev=113710&r1=113709&r2=113710&view=diff > ============================================================================== > --- llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm-target.h (original) > +++ llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm-target.h Sat Sep 11 22:26:36 2010 > @@ -55,15 +55,6 @@ > ?#define LLVM_SHOULD_PASS_AGGREGATE_IN_MIXED_REGS(T, TY, CC, E) ? ?\ > ? ?llvm_arm_should_pass_aggregate_in_mixed_regs((T), (TY), (CC), (E)) > > -struct DefaultABIClient; > -extern bool > -llvm_arm_try_pass_aggregate_custom(tree, std::vector&, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?CallingConv::ID&, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?struct DefaultABIClient*); > - > -#define LLVM_TRY_PASS_AGGREGATE_CUSTOM(T, E, CC, C) ? ?\ > - ?llvm_arm_try_pass_aggregate_custom((T), (E), (CC), (C)) > - > ?extern > ?bool llvm_arm_aggregate_partially_passed_in_regs(std::vector&, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?std::vector&, > > Modified: llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp?rev=113710&r1=113709&r2=113710&view=diff > ============================================================================== > --- llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp (original) > +++ llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp Sat Sep 11 22:26:36 2010 > @@ -2557,91 +2557,6 @@ > ? } > ?} > > -static unsigned count_num_words(std::vector &ScalarElts) { > - ?unsigned NumWords = 0; > - ?for (unsigned i = 0, e = ScalarElts.size(); i != e; ++i) { > - ? ?const Type *Ty = ScalarElts[i]; > - ? ?if (Ty->isPointerTy()) { > - ? ? ?NumWords++; > - ? ?} else if (Ty->isIntegerTy()) { > - ? ? ?const unsigned TypeSize = Ty->getPrimitiveSizeInBits(); > - ? ? ?const unsigned NumWordsForType = (TypeSize + 31) / 32; > - > - ? ? ?NumWords += NumWordsForType; > - ? ?} else { > - ? ? ?assert (0 && "Unexpected type."); > - ? ?} > - ?} > - ?return NumWords; > -} > - > -// This function is used only on AAPCS. The difference from the generic > -// handling of arguments is that arguments larger than 32 bits are split > -// and padding arguments are added as necessary for alignment. This makes > -// the IL a bit more explicit about how arguments are handled. > -extern bool > -llvm_arm_try_pass_aggregate_custom(tree type, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? std::vector& ScalarElts, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?CallingConv::ID& CC, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?struct DefaultABIClient* C) { > - ?if (CC != CallingConv::ARM_AAPCS && CC != CallingConv::C) > - ? ?return false; > - > - ?if (CC == CallingConv::C && !TARGET_AAPCS_BASED) > - ? ?return false; > - > - ?if (TARGET_HARD_FLOAT_ABI) > - ? ?return false; > - ?const Type *Ty = ConvertType(type); > - ?if (Ty->isPointerTy()) > - ? ?return false; > - > - ?const unsigned Size = TREE_INT_CST_LOW(TYPE_SIZE(type))/8; > - ?const unsigned Alignment = TYPE_ALIGN(type)/8; > - ?const unsigned NumWords = count_num_words(ScalarElts); > - ?const bool AddPad = Alignment >= 8 && (NumWords % 2); > - > - ?// First, build a type that will be bitcast to the original one and > - ?// from where elements will be extracted. > - ?std::vector Elts; > - ?const Type* Int32Ty = Type::getInt32Ty(getGlobalContext()); > - ?const unsigned NumRegularArgs = Size / 4; > - ?for (unsigned i = 0; i < NumRegularArgs; ++i) { > - ? ?Elts.push_back(Int32Ty); > - ?} > - ?const unsigned RestSize = Size % 4; > - ?const llvm::Type *RestType = NULL; > - ?if (RestSize> 2) { > - ? ?RestType = Type::getInt32Ty(getGlobalContext()); > - ?} else if (RestSize > 1) { > - ? ?RestType = Type::getInt16Ty(getGlobalContext()); > - ?} else if (RestSize > 0) { > - ? ?RestType = Type::getInt8Ty(getGlobalContext()); > - ?} > - ?if (RestType) > - ? ?Elts.push_back(RestType); > - ?const StructType *STy = StructType::get(getGlobalContext(), Elts, false); > - > - ?if (AddPad) { > - ? ?ScalarElts.push_back(Int32Ty); > - ? ?C->HandlePad(Int32Ty); > - ?} > - > - ?for (unsigned i = 0; i < NumRegularArgs; ++i) { > - ? ?C->EnterField(i, STy); > - ? ?C->HandleScalarArgument(Int32Ty, 0); > - ? ?ScalarElts.push_back(Int32Ty); > - ? ?C->ExitField(); > - ?} > - ?if (RestType) { > - ? ?C->EnterField(NumRegularArgs, STy); > - ? ?C->HandleScalarArgument(RestType, 0, RestSize); > - ? ?ScalarElts.push_back(RestType); > - ? ?C->ExitField(); > - ?} > - ?return true; > -} > - > ?// Target hook for llvm-abi.h. It returns true if an aggregate of the > ?// specified type should be passed in a number of registers of mixed types. > ?// It also returns a vector of types that correspond to the registers used > > Modified: llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp?rev=113710&r1=113709&r2=113710&view=diff > ============================================================================== > --- llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp (original) > +++ llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp Sat Sep 11 22:26:36 2010 > @@ -8,8 +8,7 @@ > ?/// return type. It potentially breaks down the argument and invokes methods > ?/// on the client that indicate how its pieces should be handled. ?This > ?/// handles things like returning structures via hidden parameters. > -void DefaultABI::HandleReturnType(tree type, tree fn, bool isBuiltin, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?std::vector &ScalarElts) { > +void DefaultABI::HandleReturnType(tree type, tree fn, bool isBuiltin) { > ? unsigned Offset = 0; > ? const Type *Ty = ConvertType(type); > ? if (Ty->isVectorTy()) { > @@ -53,9 +52,7 @@ > > ? ? // FIXME: should return the hidden first argument for some targets > ? ? // (e.g. ELF i386). > - ? ?const PointerType *PTy = Ty->getPointerTo(); > - ? ?C.HandleAggregateShadowResult(PTy, false); > - ? ?ScalarElts.push_back(PTy); > + ? ?C.HandleAggregateShadowResult(Ty->getPointerTo(), false); > ? } > ?} > > > Modified: llvm-gcc-4.2/trunk/gcc/llvm-abi.h > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-abi.h?rev=113710&r1=113709&r2=113710&view=diff > ============================================================================== > --- llvm-gcc-4.2/trunk/gcc/llvm-abi.h (original) > +++ llvm-gcc-4.2/trunk/gcc/llvm-abi.h Sat Sep 11 22:26:36 2010 > @@ -396,8 +396,7 @@ > ? /// return type. It potentially breaks down the argument and invokes methods > ? /// on the client that indicate how its pieces should be handled. ?This > ? /// handles things like returning structures via hidden parameters. > - ?void HandleReturnType(tree type, tree fn, bool isBuiltin, > - ? ? ? ? ? ? ? ? ? ? ? ?std::vector &ScalarElts); > + ?void HandleReturnType(tree type, tree fn, bool isBuiltin); > > ? /// HandleArgument - This is invoked by the target-independent code for each > ? /// argument type passed into the function. ?It potentially breaks down the > > Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=113710&r1=113709&r2=113710&view=diff > ============================================================================== > --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) > +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Sat Sep 11 22:26:36 2010 > @@ -673,19 +673,17 @@ > ? FunctionPrologArgumentConversion Client(FnDecl, AI, Builder, CallingConv); > ? DefaultABI ABIConverter(Client); > > - ?// Scalar arguments processed so far. > - ?std::vector ScalarArgs; > - > ? // Handle the DECL_RESULT. > ? ABIConverter.HandleReturnType(TREE_TYPE(TREE_TYPE(FnDecl)), FnDecl, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DECL_BUILT_IN(FnDecl), > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?ScalarArgs); > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DECL_BUILT_IN(FnDecl)); > ? // Remember this for use by FinishFunctionBody. > ? ReturnOffset = Client.Offset; > > ? // Prepend the static chain (if any) to the list of arguments. > ? tree Args = static_chain ? static_chain : DECL_ARGUMENTS(FnDecl); > > + ?// Scalar arguments processed so far. > + ?std::vector ScalarArgs; > ? while (Args) { > ? ? const char *Name = "unnamed_arg"; > ? ? if (DECL_NAME(Args)) Name = IDENTIFIER_POINTER(DECL_NAME(Args)); > @@ -3014,17 +3012,16 @@ > ? DefaultABI ABIConverter(Client); > > ? // Handle the result, including struct returns. > - ?std::vector ScalarArgs; > ? ABIConverter.HandleReturnType(TREE_TYPE(exp), > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? fndecl ? fndecl : exp, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?fndecl ? DECL_BUILT_IN(fndecl) : false, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?ScalarArgs); > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?fndecl ? DECL_BUILT_IN(fndecl) : false); > > ? // Pass the static chain, if any, as the first parameter. > ? if (TREE_OPERAND(exp, 2)) > ? ? CallOperands.push_back(Emit(TREE_OPERAND(exp, 2), 0)); > > ? // Loop over the arguments, expanding them and adding them to the op list. > + ?std::vector ScalarArgs; > ? for (tree arg = TREE_OPERAND(exp, 1); arg; arg = TREE_CHAIN(arg)) { > ? ? tree type = TREE_TYPE(TREE_VALUE(arg)); > ? ? const Type *ArgTy = ConvertType(type); > > Modified: llvm-gcc-4.2/trunk/gcc/llvm-types.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-types.cpp?rev=113710&r1=113709&r2=113710&view=diff > ============================================================================== > --- llvm-gcc-4.2/trunk/gcc/llvm-types.cpp (original) > +++ llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Sat Sep 11 22:26:36 2010 > @@ -1082,10 +1082,8 @@ > ? TARGET_ADJUST_LLVM_CC(CallingConv, type); > ?#endif > > - ?std::vector ScalarArgs; > ? // Builtins are always prototyped, so this isn't one. > - ?ABIConverter.HandleReturnType(ReturnType, current_function_decl, false, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?ScalarArgs); > + ?ABIConverter.HandleReturnType(ReturnType, current_function_decl, false); > > ? SmallVector Attrs; > > @@ -1112,6 +1110,7 @@ > ? ? Attrs.push_back(AttributeWithIndex::get(ArgTys.size(), > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Attribute::StructRet)); > > + ?std::vector ScalarArgs; > ? if (static_chain) { > ? ? // Pass the static chain as the first parameter. > ? ? ABIConverter.HandleArgument(TREE_TYPE(static_chain), ScalarArgs); > @@ -1153,10 +1152,8 @@ > ? TARGET_ADJUST_LLVM_CC(CallingConv, type); > ?#endif > > - ?std::vector ScalarArgs; > ? ABIConverter.HandleReturnType(TREE_TYPE(type), current_function_decl, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?decl ? DECL_BUILT_IN(decl) : false, > - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?ScalarArgs); > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?decl ? DECL_BUILT_IN(decl) : false); > > ? // Compute attributes for return type (and function attributes). > ? SmallVector Attrs; > @@ -1221,6 +1218,7 @@ > ? ? Attrs.push_back(AttributeWithIndex::get(ArgTypes.size(), > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Attribute::StructRet | Attribute::NoAlias)); > > + ?std::vector ScalarArgs; > ? if (static_chain) { > ? ? // Pass the static chain as the first parameter. > ? ? ABIConverter.HandleArgument(TREE_TYPE(static_chain), ScalarArgs); > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -- Rafael ?vila de Esp?ndola From echristo at apple.com Sun Sep 12 02:25:45 2010 From: echristo at apple.com (Eric Christopher) Date: Sun, 12 Sep 2010 00:25:45 -0700 Subject: [llvm-commits] [llvm-gcc-4.2] r113710 - in /llvm-gcc-4.2/trunk/gcc: config/arm/llvm-arm-target.h config/arm/llvm-arm.cpp llvm-abi-default.cpp llvm-abi.h llvm-convert.cpp llvm-types.cpp In-Reply-To: References: <20100912032637.086E92A6C12C@llvm.org> Message-ID: <9F4852D2-A728-4171-83C3-E75229FE9D40@apple.com> On Sep 12, 2010, at 12:23 AM, Rafael Espindola wrote: > Thanks. Do you have a testcase? For some reason I got no email from the bots... I don't sorry, but the llvm-gcc darwin selfhost-rel bot was failing before I reverted it. Lots of crashes post-bootstrap. Can you bootstrap and then try using that compiler to compile llvm or run the testsuite on darwin? I think I saw it fail doing that. -eric From espindola at google.com Sun Sep 12 02:29:21 2010 From: espindola at google.com (Rafael Espindola) Date: Sun, 12 Sep 2010 03:29:21 -0400 Subject: [llvm-commits] [llvm-gcc-4.2] r113710 - in /llvm-gcc-4.2/trunk/gcc: config/arm/llvm-arm-target.h config/arm/llvm-arm.cpp llvm-abi-default.cpp llvm-abi.h llvm-convert.cpp llvm-types.cpp In-Reply-To: <9F4852D2-A728-4171-83C3-E75229FE9D40@apple.com> References: <20100912032637.086E92A6C12C@llvm.org> <9F4852D2-A728-4171-83C3-E75229FE9D40@apple.com> Message-ID: On 12 September 2010 03:25, Eric Christopher wrote: > > On Sep 12, 2010, at 12:23 AM, Rafael Espindola wrote: > >> Thanks. Do you have a testcase? For some reason I got no email from the bots... > > I don't sorry, but the llvm-gcc darwin selfhost-rel bot was failing before I reverted it. ?Lots of crashes post-bootstrap. > > Can you bootstrap and then try using that compiler to compile llvm or run the testsuite on darwin? ?I think I saw it fail doing that. On Darwin X86_64? I will give it a try. Probably missed some use of ScalarElts. Sorry about that. > -eric Cheers, -- Rafael ?vila de Esp?ndola From echristo at apple.com Sun Sep 12 02:37:47 2010 From: echristo at apple.com (Eric Christopher) Date: Sun, 12 Sep 2010 00:37:47 -0700 Subject: [llvm-commits] [llvm-gcc-4.2] r113710 - in /llvm-gcc-4.2/trunk/gcc: config/arm/llvm-arm-target.h config/arm/llvm-arm.cpp llvm-abi-default.cpp llvm-abi.h llvm-convert.cpp llvm-types.cpp In-Reply-To: References: <20100912032637.086E92A6C12C@llvm.org> <9F4852D2-A728-4171-83C3-E75229FE9D40@apple.com> Message-ID: <897DF0A4-0D7F-4B77-AE9E-24617C509C25@apple.com> On Sep 12, 2010, at 12:29 AM, Rafael Espindola wrote: > On 12 September 2010 03:25, Eric Christopher wrote: >> >> On Sep 12, 2010, at 12:23 AM, Rafael Espindola wrote: >> >>> Thanks. Do you have a testcase? For some reason I got no email from the bots... >> >> I don't sorry, but the llvm-gcc darwin selfhost-rel bot was failing before I reverted it. Lots of crashes post-bootstrap. >> >> Can you bootstrap and then try using that compiler to compile llvm or run the testsuite on darwin? I think I saw it fail doing that. > > On Darwin X86_64? I will give it a try. Probably missed some use of > ScalarElts. Sorry about that. No problem. It happens. I only noticed because another tester of mine died a horrible death trying to build stuff :) -eric From rafael.espindola at gmail.com Sun Sep 12 04:00:41 2010 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Sun, 12 Sep 2010 09:00:41 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r113726 - in /llvm-gcc-4.2/trunk/gcc: config/arm/llvm-arm-target.h config/arm/llvm-arm.cpp config/i386/llvm-i386-target.h config/i386/llvm-i386.cpp llvm-abi-default.cpp llvm-abi.h llvm-convert.cpp llvm-types.cpp Message-ID: <20100912090041.C93C12A6C12C@llvm.org> Author: rafael Date: Sun Sep 12 04:00:41 2010 New Revision: 113726 URL: http://llvm.org/viewvc/llvm-project?rev=113726&view=rev Log: Fixed version of 113694. The problem with the original one is that it would cause double accounting of sret parameters. Original message: Lower ARM function signatures a bit more. I implemented only AAPCS since that is what I can test. With this patch we convert struct foo {double a; int b;}; void f(int, struct foo); void g(int a, double b, int c) { struct foo x = {b, c}; f(a, x); } into ------------------------------------------------------ define void @g(i32 %a.0, i32, i32 %b.0, i32 %b.1, i32 %c.0) nounwind optsize { entry: tail call void @f(i32 %a.0, i32 undef, i32 %b.0, i32 %b.1, i32 %c.0, i32 0) nounwind ret void } declare void @f(i32, i32, i32, i32, i32, i32) ---------------------------------------------------- instead of --------------------------------------------------- define void @g(i32 %a, double %b, i32 %c) nounwind optsize { entry: %tmp11 = bitcast double %b to i64 %tmp5 = zext i32 %c to i64 tail call void @f(i32 %a, i64 %tmp11, i64 %tmp5) nounwind ret void } declare void @f(i32, i64, i64) -------------------------------------------------- The IL for ------------------------------------------ double foo(double X, double Y) { return X+Y; } ----------------------------------------- now shows that the arguments being passed in the integer registres: ---------------------------------------------------------------------- define double @foo(i32 %X.0, i32 %X.1, i32 %Y.0, i32 %Y.1) nounwind readnone optsize { entry: %tmp17 = zext i32 %X.0 to i64 %tmp12 = zext i32 %X.1 to i64 %tmp13 = shl i64 %tmp12, 32 %ins15 = or i64 %tmp13, %tmp17 %tmp6 = zext i32 %Y.0 to i64 %tmp3 = zext i32 %Y.1 to i64 %tmp4 = shl i64 %tmp3, 32 %ins = or i64 %tmp4, %tmp6 %tmp10 = bitcast i64 %ins15 to double %tmp2 = bitcast i64 %ins to double %0 = fadd double %tmp10, %tmp2 ret double %0 } --------------------------------------------------------------------- And the produces assembly is the same as before: ---------------------------------------------------------------- foo: vmov d0, r2, r3 vmov d1, r0, r1 vadd.f64 d0, d1, d0 vmov r0, r1, d0 bx lr ---------------------------------------------------------------- Modified: llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm-target.h llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp llvm-gcc-4.2/trunk/gcc/llvm-abi.h llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Modified: llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm-target.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm-target.h?rev=113726&r1=113725&r2=113726&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm-target.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm-target.h Sun Sep 12 04:00:41 2010 @@ -55,13 +55,22 @@ #define LLVM_SHOULD_PASS_AGGREGATE_IN_MIXED_REGS(T, TY, CC, E) \ llvm_arm_should_pass_aggregate_in_mixed_regs((T), (TY), (CC), (E)) +struct DefaultABIClient; +extern bool +llvm_arm_try_pass_aggregate_custom(tree, std::vector&, + CallingConv::ID&, + struct DefaultABIClient*); + +#define LLVM_TRY_PASS_AGGREGATE_CUSTOM(T, E, CC, C) \ + llvm_arm_try_pass_aggregate_custom((T), (E), (CC), (C)) + extern bool llvm_arm_aggregate_partially_passed_in_regs(std::vector&, std::vector&, - bool, CallingConv::ID&); + CallingConv::ID&); -#define LLVM_AGGREGATE_PARTIALLY_PASSED_IN_REGS(E, SE, ISR, CC) \ - llvm_arm_aggregate_partially_passed_in_regs((E), (SE), (ISR), (CC)) +#define LLVM_AGGREGATE_PARTIALLY_PASSED_IN_REGS(E, SE, CC) \ + llvm_arm_aggregate_partially_passed_in_regs((E), (SE), (CC)) extern const Type *llvm_arm_aggr_type_for_struct_return(tree type, CallingConv::ID &CC); Modified: llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp?rev=113726&r1=113725&r2=113726&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/config/arm/llvm-arm.cpp Sun Sep 12 04:00:41 2010 @@ -2557,6 +2557,91 @@ } } +static unsigned count_num_words(std::vector &ScalarElts) { + unsigned NumWords = 0; + for (unsigned i = 0, e = ScalarElts.size(); i != e; ++i) { + const Type *Ty = ScalarElts[i]; + if (Ty->isPointerTy()) { + NumWords++; + } else if (Ty->isIntegerTy()) { + const unsigned TypeSize = Ty->getPrimitiveSizeInBits(); + const unsigned NumWordsForType = (TypeSize + 31) / 32; + + NumWords += NumWordsForType; + } else { + assert (0 && "Unexpected type."); + } + } + return NumWords; +} + +// This function is used only on AAPCS. The difference from the generic +// handling of arguments is that arguments larger than 32 bits are split +// and padding arguments are added as necessary for alignment. This makes +// the IL a bit more explicit about how arguments are handled. +extern bool +llvm_arm_try_pass_aggregate_custom(tree type, + std::vector& ScalarElts, + CallingConv::ID& CC, + struct DefaultABIClient* C) { + if (CC != CallingConv::ARM_AAPCS && CC != CallingConv::C) + return false; + + if (CC == CallingConv::C && !TARGET_AAPCS_BASED) + return false; + + if (TARGET_HARD_FLOAT_ABI) + return false; + const Type *Ty = ConvertType(type); + if (Ty->isPointerTy()) + return false; + + const unsigned Size = TREE_INT_CST_LOW(TYPE_SIZE(type))/8; + const unsigned Alignment = TYPE_ALIGN(type)/8; + const unsigned NumWords = count_num_words(ScalarElts); + const bool AddPad = Alignment >= 8 && (NumWords % 2); + + // First, build a type that will be bitcast to the original one and + // from where elements will be extracted. + std::vector Elts; + const Type* Int32Ty = Type::getInt32Ty(getGlobalContext()); + const unsigned NumRegularArgs = Size / 4; + for (unsigned i = 0; i < NumRegularArgs; ++i) { + Elts.push_back(Int32Ty); + } + const unsigned RestSize = Size % 4; + const llvm::Type *RestType = NULL; + if (RestSize> 2) { + RestType = Type::getInt32Ty(getGlobalContext()); + } else if (RestSize > 1) { + RestType = Type::getInt16Ty(getGlobalContext()); + } else if (RestSize > 0) { + RestType = Type::getInt8Ty(getGlobalContext()); + } + if (RestType) + Elts.push_back(RestType); + const StructType *STy = StructType::get(getGlobalContext(), Elts, false); + + if (AddPad) { + ScalarElts.push_back(Int32Ty); + C->HandlePad(Int32Ty); + } + + for (unsigned i = 0; i < NumRegularArgs; ++i) { + C->EnterField(i, STy); + C->HandleScalarArgument(Int32Ty, 0); + ScalarElts.push_back(Int32Ty); + C->ExitField(); + } + if (RestType) { + C->EnterField(NumRegularArgs, STy); + C->HandleScalarArgument(RestType, 0, RestSize); + ScalarElts.push_back(RestType); + C->ExitField(); + } + return true; +} + // Target hook for llvm-abi.h. It returns true if an aggregate of the // specified type should be passed in a number of registers of mixed types. // It also returns a vector of types that correspond to the registers used @@ -2658,7 +2743,6 @@ bool llvm_arm_aggregate_partially_passed_in_regs(std::vector &Elts, std::vector &ScalarElts, - bool isShadowReturn, CallingConv::ID &CC) { // Homogeneous aggregates are an AAPCS-VFP feature. if ((CC != CallingConv::ARM_AAPCS_VFP) || Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h?rev=113726&r1=113725&r2=113726&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h Sun Sep 12 04:00:41 2010 @@ -219,12 +219,11 @@ extern bool llvm_x86_64_aggregate_partially_passed_in_regs(std::vector&, - std::vector&, - bool); + std::vector&); -#define LLVM_AGGREGATE_PARTIALLY_PASSED_IN_REGS(E, SE, ISR, CC) \ +#define LLVM_AGGREGATE_PARTIALLY_PASSED_IN_REGS(E, SE, CC) \ (TARGET_64BIT ? \ - llvm_x86_64_aggregate_partially_passed_in_regs((E), (SE), (ISR)) : \ + llvm_x86_64_aggregate_partially_passed_in_regs((E), (SE)) : \ false) #endif /* LLVM_ABI_H */ Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp?rev=113726&r1=113725&r2=113726&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386.cpp Sun Sep 12 04:00:41 2010 @@ -869,8 +869,7 @@ be passed in memory. */ bool llvm_x86_64_aggregate_partially_passed_in_regs(std::vector &Elts, - std::vector &ScalarElts, - bool isShadowReturn) { + std::vector &ScalarElts) { // Counting number of GPRs and XMMs used so far. According to AMD64 ABI // document: "If there are no registers available for any eightbyte of an // argument, the whole argument is passed on the stack." X86-64 uses 6 @@ -879,7 +878,7 @@ // both parts will be in memory. // FIXME: This is a temporary solution. To be removed when llvm has first // class aggregate values. - unsigned NumGPRs = isShadowReturn ? 1 : 0; + unsigned NumGPRs = 0; unsigned NumXMMs = 0; count_num_registers_uses(ScalarElts, NumGPRs, NumXMMs); Modified: llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp?rev=113726&r1=113725&r2=113726&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-abi-default.cpp Sun Sep 12 04:00:41 2010 @@ -8,7 +8,8 @@ /// return type. It potentially breaks down the argument and invokes methods /// on the client that indicate how its pieces should be handled. This /// handles things like returning structures via hidden parameters. -void DefaultABI::HandleReturnType(tree type, tree fn, bool isBuiltin) { +void DefaultABI::HandleReturnType(tree type, tree fn, bool isBuiltin, + std::vector &ScalarElts) { unsigned Offset = 0; const Type *Ty = ConvertType(type); if (Ty->isVectorTy()) { @@ -52,7 +53,9 @@ // FIXME: should return the hidden first argument for some targets // (e.g. ELF i386). - C.HandleAggregateShadowResult(Ty->getPointerTo(), false); + const PointerType *PTy = Ty->getPointerTo(); + C.HandleAggregateShadowResult(PTy, false); + ScalarElts.push_back(PTy); } } @@ -104,7 +107,6 @@ C.getCallingConv(), Elts)) { if (!LLVM_AGGREGATE_PARTIALLY_PASSED_IN_REGS(Elts, ScalarElts, - C.isShadowReturn(), C.getCallingConv())) PassInMixedRegisters(Ty, Elts, ScalarElts); else { Modified: llvm-gcc-4.2/trunk/gcc/llvm-abi.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-abi.h?rev=113726&r1=113725&r2=113726&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-abi.h (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-abi.h Sun Sep 12 04:00:41 2010 @@ -302,7 +302,7 @@ // the aggregate. Note, this routine should return false if none of the needed // registers are available. #ifndef LLVM_AGGREGATE_PARTIALLY_PASSED_IN_REGS -#define LLVM_AGGREGATE_PARTIALLY_PASSED_IN_REGS(E, SE, ISR, CC) \ +#define LLVM_AGGREGATE_PARTIALLY_PASSED_IN_REGS(E, SE, CC) \ false #endif @@ -396,7 +396,8 @@ /// return type. It potentially breaks down the argument and invokes methods /// on the client that indicate how its pieces should be handled. This /// handles things like returning structures via hidden parameters. - void HandleReturnType(tree type, tree fn, bool isBuiltin); + void HandleReturnType(tree type, tree fn, bool isBuiltin, + std::vector &ScalarElts); /// HandleArgument - This is invoked by the target-independent code for each /// argument type passed into the function. It potentially breaks down the Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=113726&r1=113725&r2=113726&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Sun Sep 12 04:00:41 2010 @@ -436,13 +436,13 @@ // passed in memory byval. static bool isPassedByVal(tree type, const Type *Ty, std::vector &ScalarArgs, - bool isShadowRet, CallingConv::ID &CC) { + CallingConv::ID &CC) { if (LLVM_SHOULD_PASS_AGGREGATE_USING_BYVAL_ATTR(type, Ty)) return true; std::vector Args; if (LLVM_SHOULD_PASS_AGGREGATE_IN_MIXED_REGS(type, Ty, CC, Args) && - LLVM_AGGREGATE_PARTIALLY_PASSED_IN_REGS(Args, ScalarArgs, isShadowRet, + LLVM_AGGREGATE_PARTIALLY_PASSED_IN_REGS(Args, ScalarArgs, CC)) // We want to pass the whole aggregate in registers but only some of the // registers are available. @@ -673,17 +673,19 @@ FunctionPrologArgumentConversion Client(FnDecl, AI, Builder, CallingConv); DefaultABI ABIConverter(Client); + // Scalar arguments processed so far. + std::vector ScalarArgs; + // Handle the DECL_RESULT. ABIConverter.HandleReturnType(TREE_TYPE(TREE_TYPE(FnDecl)), FnDecl, - DECL_BUILT_IN(FnDecl)); + DECL_BUILT_IN(FnDecl), + ScalarArgs); // Remember this for use by FinishFunctionBody. ReturnOffset = Client.Offset; // Prepend the static chain (if any) to the list of arguments. tree Args = static_chain ? static_chain : DECL_ARGUMENTS(FnDecl); - // Scalar arguments processed so far. - std::vector ScalarArgs; while (Args) { const char *Name = "unnamed_arg"; if (DECL_NAME(Args)) Name = IDENTIFIER_POINTER(DECL_NAME(Args)); @@ -696,7 +698,7 @@ !LLVM_BYVAL_ALIGNMENT_TOO_SMALL(TREE_TYPE(Args))) || (!ArgTy->isSingleValueType() && isPassedByVal(TREE_TYPE(Args), ArgTy, ScalarArgs, - Client.isShadowReturn(), CallingConv) && + CallingConv) && !LLVM_BYVAL_ALIGNMENT_TOO_SMALL(TREE_TYPE(Args)))) { // If the value is passed by 'invisible reference' or 'byval reference', // the l-value for the argument IS the argument itself. But for byval @@ -3012,16 +3014,17 @@ DefaultABI ABIConverter(Client); // Handle the result, including struct returns. + std::vector ScalarArgs; ABIConverter.HandleReturnType(TREE_TYPE(exp), fndecl ? fndecl : exp, - fndecl ? DECL_BUILT_IN(fndecl) : false); + fndecl ? DECL_BUILT_IN(fndecl) : false, + ScalarArgs); // Pass the static chain, if any, as the first parameter. if (TREE_OPERAND(exp, 2)) CallOperands.push_back(Emit(TREE_OPERAND(exp, 2), 0)); // Loop over the arguments, expanding them and adding them to the op list. - std::vector ScalarArgs; for (tree arg = TREE_OPERAND(exp, 1); arg; arg = TREE_CHAIN(arg)) { tree type = TREE_TYPE(TREE_VALUE(arg)); const Type *ArgTy = ConvertType(type); Modified: llvm-gcc-4.2/trunk/gcc/llvm-types.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-types.cpp?rev=113726&r1=113725&r2=113726&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-types.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Sun Sep 12 04:00:41 2010 @@ -1082,8 +1082,10 @@ TARGET_ADJUST_LLVM_CC(CallingConv, type); #endif + std::vector ScalarArgs; // Builtins are always prototyped, so this isn't one. - ABIConverter.HandleReturnType(ReturnType, current_function_decl, false); + ABIConverter.HandleReturnType(ReturnType, current_function_decl, false, + ScalarArgs); SmallVector Attrs; @@ -1110,7 +1112,6 @@ Attrs.push_back(AttributeWithIndex::get(ArgTys.size(), Attribute::StructRet)); - std::vector ScalarArgs; if (static_chain) { // Pass the static chain as the first parameter. ABIConverter.HandleArgument(TREE_TYPE(static_chain), ScalarArgs); @@ -1152,8 +1153,10 @@ TARGET_ADJUST_LLVM_CC(CallingConv, type); #endif + std::vector ScalarArgs; ABIConverter.HandleReturnType(TREE_TYPE(type), current_function_decl, - decl ? DECL_BUILT_IN(decl) : false); + decl ? DECL_BUILT_IN(decl) : false, + ScalarArgs); // Compute attributes for return type (and function attributes). SmallVector Attrs; @@ -1218,7 +1221,6 @@ Attrs.push_back(AttributeWithIndex::get(ArgTypes.size(), Attribute::StructRet | Attribute::NoAlias)); - std::vector ScalarArgs; if (static_chain) { // Pass the static chain as the first parameter. ABIConverter.HandleArgument(TREE_TYPE(static_chain), ScalarArgs); From bigcheesegs at gmail.com Sun Sep 12 13:32:57 2010 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Sun, 12 Sep 2010 18:32:57 -0000 Subject: [llvm-commits] [llvm] r113727 - in /llvm/trunk/lib/Target: MSP430/TargetInfo/CMakeLists.txt PIC16/TargetInfo/CMakeLists.txt XCore/TargetInfo/CMakeLists.txt Message-ID: <20100912183257.F06DE2A6C12C@llvm.org> Author: mspencer Date: Sun Sep 12 13:32:57 2010 New Revision: 113727 URL: http://llvm.org/viewvc/llvm-project?rev=113727&view=rev Log: CMake: Fix MSVS build. Although I don't know why this didn't break other build systems... This problem is unrelated to the recent dependency tracking change. It seems like noone noticed the problem because I don't think anyone compiles any target other than X86 on windows. Modified: llvm/trunk/lib/Target/MSP430/TargetInfo/CMakeLists.txt llvm/trunk/lib/Target/PIC16/TargetInfo/CMakeLists.txt llvm/trunk/lib/Target/XCore/TargetInfo/CMakeLists.txt Modified: llvm/trunk/lib/Target/MSP430/TargetInfo/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/TargetInfo/CMakeLists.txt?rev=113727&r1=113726&r2=113727&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/TargetInfo/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/MSP430/TargetInfo/CMakeLists.txt Sun Sep 12 13:32:57 2010 @@ -4,4 +4,4 @@ MSP430TargetInfo.cpp ) -add_dependencies(LLVMMSP430Info MSP430Table_gen) +add_dependencies(LLVMMSP430Info MSP430CodeGenTable_gen) Modified: llvm/trunk/lib/Target/PIC16/TargetInfo/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PIC16/TargetInfo/CMakeLists.txt?rev=113727&r1=113726&r2=113727&view=diff ============================================================================== --- llvm/trunk/lib/Target/PIC16/TargetInfo/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/PIC16/TargetInfo/CMakeLists.txt Sun Sep 12 13:32:57 2010 @@ -4,4 +4,4 @@ PIC16TargetInfo.cpp ) -add_dependencies(LLVMPIC16Info PIC16Table_gen) +add_dependencies(LLVMPIC16Info PIC16CodeGenTable_gen) Modified: llvm/trunk/lib/Target/XCore/TargetInfo/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/TargetInfo/CMakeLists.txt?rev=113727&r1=113726&r2=113727&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/TargetInfo/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/XCore/TargetInfo/CMakeLists.txt Sun Sep 12 13:32:57 2010 @@ -4,4 +4,4 @@ XCoreTargetInfo.cpp ) -add_dependencies(LLVMXCoreInfo XCoreTable_gen) +add_dependencies(LLVMXCoreInfo XCoreCodeGenTable_gen) From dalej at apple.com Sun Sep 12 17:36:13 2010 From: dalej at apple.com (Dale Johannesen) Date: Sun, 12 Sep 2010 22:36:13 -0000 Subject: [llvm-commits] [llvm] r113728 - /llvm/trunk/include/llvm/Type.h Message-ID: <20100912223613.584EB2A6C12C@llvm.org> Author: johannes Date: Sun Sep 12 17:36:13 2010 New Revision: 113728 URL: http://llvm.org/viewvc/llvm-project?rev=113728&view=rev Log: Fix comment typo. Modified: llvm/trunk/include/llvm/Type.h Modified: llvm/trunk/include/llvm/Type.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Type.h?rev=113728&r1=113727&r2=113728&view=diff ============================================================================== --- llvm/trunk/include/llvm/Type.h (original) +++ llvm/trunk/include/llvm/Type.h Sun Sep 12 17:36:13 2010 @@ -213,7 +213,7 @@ bool isFloatingPointTy() const { return ID == FloatTyID || ID == DoubleTyID || ID == X86_FP80TyID || ID == FP128TyID || ID == PPC_FP128TyID; } - /// isPPC_FP128Ty - Return true if this is X86 MMX. + /// isX86_MMXTy - Return true if this is X86 MMX. bool isX86_MMXTy() const { return ID == X86_MMXTyID; } /// isFPOrFPVectorTy - Return true if this is a FP type or a vector of FP.